1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "stringpool.h"
39 #include "stor-layout.h"
50 #include "hash-table.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
56 #include "sched-int.h"
57 #include "pointer-set.h"
59 #include "basic-block.h"
60 #include "tree-ssa-alias.h"
61 #include "internal-fn.h"
62 #include "gimple-fold.h"
64 #include "gimple-expr.h"
69 #include "diagnostic.h"
70 #include "target-globals.h"
72 #include "tree-pass.h"
77 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
78 #define UNSPEC_ADDRESS_P(X) \
79 (GET_CODE (X) == UNSPEC \
80 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
81 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
83 /* Extract the symbol or label from UNSPEC wrapper X. */
84 #define UNSPEC_ADDRESS(X) \
87 /* Extract the symbol type from UNSPEC wrapper X. */
88 #define UNSPEC_ADDRESS_TYPE(X) \
89 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
91 /* The maximum distance between the top of the stack frame and the
92 value $sp has when we save and restore registers.
94 The value for normal-mode code must be a SMALL_OPERAND and must
95 preserve the maximum stack alignment. We therefore use a value
96 of 0x7ff0 in this case.
98 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
99 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
101 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
102 up to 0x7f8 bytes and can usually save or restore all the registers
103 that we need to save or restore. (Note that we can only use these
104 instructions for o32, for which the stack alignment is 8 bytes.)
106 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
107 RESTORE are not available. We can then use unextended instructions
108 to save and restore registers, and to allocate and deallocate the top
109 part of the frame. */
110 #define MIPS_MAX_FIRST_STACK_STEP \
111 (!TARGET_COMPRESSION ? 0x7ff0 \
112 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
113 : TARGET_64BIT ? 0x100 : 0x400)
115 /* True if INSN is a mips.md pattern or asm statement. */
116 /* ??? This test exists through the compiler, perhaps it should be
118 #define USEFUL_INSN_P(INSN) \
119 (NONDEBUG_INSN_P (INSN) \
120 && GET_CODE (PATTERN (INSN)) != USE \
121 && GET_CODE (PATTERN (INSN)) != CLOBBER)
123 /* If INSN is a delayed branch sequence, return the first instruction
124 in the sequence, otherwise return INSN itself. */
125 #define SEQ_BEGIN(INSN) \
126 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
127 ? XVECEXP (PATTERN (INSN), 0, 0) \
130 /* Likewise for the last instruction in a delayed branch sequence. */
131 #define SEQ_END(INSN) \
132 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
133 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
136 /* Execute the following loop body with SUBINSN set to each instruction
137 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
138 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
139 for ((SUBINSN) = SEQ_BEGIN (INSN); \
140 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
141 (SUBINSN) = NEXT_INSN (SUBINSN))
143 /* True if bit BIT is set in VALUE. */
144 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
146 /* Return the opcode for a ptr_mode load of the form:
148 l[wd] DEST, OFFSET(BASE). */
149 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
150 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
155 /* Return the opcode to move register SRC into register DEST. */
156 #define MIPS_MOVE(DEST, SRC) \
157 ((TARGET_64BIT ? 0x2d : 0x21) \
161 /* Return the opcode for:
164 #define MIPS_LUI(DEST, VALUE) \
165 ((0xf << 26) | ((DEST) << 16) | (VALUE))
167 /* Return the opcode to jump to register DEST. */
168 #define MIPS_JR(DEST) \
169 (((DEST) << 21) | 0x8)
171 /* Return the opcode for:
173 bal . + (1 + OFFSET) * 4. */
174 #define MIPS_BAL(OFFSET) \
175 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
177 /* Return the usual opcode for a nop. */
180 /* Classifies an address.
183 A natural register + offset address. The register satisfies
184 mips_valid_base_register_p and the offset is a const_arith_operand.
187 A LO_SUM rtx. The first operand is a valid base register and
188 the second operand is a symbolic address.
191 A signed 16-bit constant address.
194 A constant symbolic address. */
195 enum mips_address_type
{
202 /* Macros to create an enumeration identifier for a function prototype. */
203 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
204 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
205 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
206 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
208 /* Classifies the prototype of a built-in function. */
209 enum mips_function_type
{
210 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
211 #include "config/mips/mips-ftypes.def"
212 #undef DEF_MIPS_FTYPE
216 /* Specifies how a built-in function should be converted into rtl. */
217 enum mips_builtin_type
{
218 /* The function corresponds directly to an .md pattern. The return
219 value is mapped to operand 0 and the arguments are mapped to
220 operands 1 and above. */
223 /* The function corresponds directly to an .md pattern. There is no return
224 value and the arguments are mapped to operands 0 and above. */
225 MIPS_BUILTIN_DIRECT_NO_TARGET
,
227 /* The function corresponds to a comparison instruction followed by
228 a mips_cond_move_tf_ps pattern. The first two arguments are the
229 values to compare and the second two arguments are the vector
230 operands for the movt.ps or movf.ps instruction (in assembly order). */
234 /* The function corresponds to a V2SF comparison instruction. Operand 0
235 of this instruction is the result of the comparison, which has mode
236 CCV2 or CCV4. The function arguments are mapped to operands 1 and
237 above. The function's return value is an SImode boolean that is
238 true under the following conditions:
240 MIPS_BUILTIN_CMP_ANY: one of the registers is true
241 MIPS_BUILTIN_CMP_ALL: all of the registers are true
242 MIPS_BUILTIN_CMP_LOWER: the first register is true
243 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
244 MIPS_BUILTIN_CMP_ANY
,
245 MIPS_BUILTIN_CMP_ALL
,
246 MIPS_BUILTIN_CMP_UPPER
,
247 MIPS_BUILTIN_CMP_LOWER
,
249 /* As above, but the instruction only sets a single $fcc register. */
250 MIPS_BUILTIN_CMP_SINGLE
,
252 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
253 MIPS_BUILTIN_BPOSGE32
256 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
257 #define MIPS_FP_CONDITIONS(MACRO) \
275 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
276 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
277 enum mips_fp_condition
{
278 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
280 #undef DECLARE_MIPS_COND
282 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
283 #define STRINGIFY(X) #X
284 static const char *const mips_fp_conditions
[] = {
285 MIPS_FP_CONDITIONS (STRINGIFY
)
289 /* A class used to control a comdat-style stub that we output in each
290 translation unit that needs it. */
291 class mips_one_only_stub
{
293 virtual ~mips_one_only_stub () {}
295 /* Return the name of the stub. */
296 virtual const char *get_name () = 0;
298 /* Output the body of the function to asm_out_file. */
299 virtual void output_body () = 0;
302 /* Tuning information that is automatically derived from other sources
303 (such as the scheduler). */
305 /* The architecture and tuning settings that this structure describes. */
309 /* True if this structure describes MIPS16 settings. */
312 /* True if the structure has been initialized. */
315 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
316 when optimizing for speed. */
317 bool fast_mult_zero_zero_p
;
320 /* Information about a function's frame layout. */
321 struct GTY(()) mips_frame_info
{
322 /* The size of the frame in bytes. */
323 HOST_WIDE_INT total_size
;
325 /* The number of bytes allocated to variables. */
326 HOST_WIDE_INT var_size
;
328 /* The number of bytes allocated to outgoing function arguments. */
329 HOST_WIDE_INT args_size
;
331 /* The number of bytes allocated to the .cprestore slot, or 0 if there
333 HOST_WIDE_INT cprestore_size
;
335 /* Bit X is set if the function saves or restores GPR X. */
338 /* Likewise FPR X. */
341 /* Likewise doubleword accumulator X ($acX). */
342 unsigned int acc_mask
;
344 /* The number of GPRs, FPRs, doubleword accumulators and COP0
348 unsigned int num_acc
;
349 unsigned int num_cop0_regs
;
351 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
352 save slots from the top of the frame, or zero if no such slots are
354 HOST_WIDE_INT gp_save_offset
;
355 HOST_WIDE_INT fp_save_offset
;
356 HOST_WIDE_INT acc_save_offset
;
357 HOST_WIDE_INT cop0_save_offset
;
359 /* Likewise, but giving offsets from the bottom of the frame. */
360 HOST_WIDE_INT gp_sp_offset
;
361 HOST_WIDE_INT fp_sp_offset
;
362 HOST_WIDE_INT acc_sp_offset
;
363 HOST_WIDE_INT cop0_sp_offset
;
365 /* Similar, but the value passed to _mcount. */
366 HOST_WIDE_INT ra_fp_offset
;
368 /* The offset of arg_pointer_rtx from the bottom of the frame. */
369 HOST_WIDE_INT arg_pointer_offset
;
371 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
372 HOST_WIDE_INT hard_frame_pointer_offset
;
375 struct GTY(()) machine_function
{
376 /* The next floating-point condition-code register to allocate
377 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
378 unsigned int next_fcc
;
380 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
381 rtx mips16_gp_pseudo_rtx
;
383 /* The number of extra stack bytes taken up by register varargs.
384 This area is allocated by the callee at the very top of the frame. */
387 /* The current frame information, calculated by mips_compute_frame_info. */
388 struct mips_frame_info frame
;
390 /* The register to use as the function's global pointer, or INVALID_REGNUM
391 if the function doesn't need one. */
392 unsigned int global_pointer
;
394 /* How many instructions it takes to load a label into $AT, or 0 if
395 this property hasn't yet been calculated. */
396 unsigned int load_label_num_insns
;
398 /* True if mips_adjust_insn_length should ignore an instruction's
400 bool ignore_hazard_length_p
;
402 /* True if the whole function is suitable for .set noreorder and
404 bool all_noreorder_p
;
406 /* True if the function has "inflexible" and "flexible" references
407 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
408 and mips_cfun_has_flexible_gp_ref_p for details. */
409 bool has_inflexible_gp_insn_p
;
410 bool has_flexible_gp_insn_p
;
412 /* True if the function's prologue must load the global pointer
413 value into pic_offset_table_rtx and store the same value in
414 the function's cprestore slot (if any). Even if this value
415 is currently false, we may decide to set it to true later;
416 see mips_must_initialize_gp_p () for details. */
417 bool must_initialize_gp_p
;
419 /* True if the current function must restore $gp after any potential
420 clobber. This value is only meaningful during the first post-epilogue
421 split_insns pass; see mips_must_initialize_gp_p () for details. */
422 bool must_restore_gp_when_clobbered_p
;
424 /* True if this is an interrupt handler. */
425 bool interrupt_handler_p
;
427 /* True if this is an interrupt handler that uses shadow registers. */
428 bool use_shadow_register_set_p
;
430 /* True if this is an interrupt handler that should keep interrupts
432 bool keep_interrupts_masked_p
;
434 /* True if this is an interrupt handler that should use DERET
436 bool use_debug_exception_return_p
;
439 /* Information about a single argument. */
440 struct mips_arg_info
{
441 /* True if the argument is passed in a floating-point register, or
442 would have been if we hadn't run out of registers. */
445 /* The number of words passed in registers, rounded up. */
446 unsigned int reg_words
;
448 /* For EABI, the offset of the first register from GP_ARG_FIRST or
449 FP_ARG_FIRST. For other ABIs, the offset of the first register from
450 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
451 comment for details).
453 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
455 unsigned int reg_offset
;
457 /* The number of words that must be passed on the stack, rounded up. */
458 unsigned int stack_words
;
460 /* The offset from the start of the stack overflow area of the argument's
461 first stack word. Only meaningful when STACK_WORDS is nonzero. */
462 unsigned int stack_offset
;
465 /* Information about an address described by mips_address_type.
471 REG is the base register and OFFSET is the constant offset.
474 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
475 is the type of symbol it references.
478 SYMBOL_TYPE is the type of symbol that the address references. */
479 struct mips_address_info
{
480 enum mips_address_type type
;
483 enum mips_symbol_type symbol_type
;
486 /* One stage in a constant building sequence. These sequences have
490 A = A CODE[1] VALUE[1]
491 A = A CODE[2] VALUE[2]
494 where A is an accumulator, each CODE[i] is a binary rtl operation
495 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
496 struct mips_integer_op
{
498 unsigned HOST_WIDE_INT value
;
501 /* The largest number of operations needed to load an integer constant.
502 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
503 When the lowest bit is clear, we can try, but reject a sequence with
504 an extra SLL at the end. */
505 #define MIPS_MAX_INTEGER_OPS 7
507 /* Information about a MIPS16e SAVE or RESTORE instruction. */
508 struct mips16e_save_restore_info
{
509 /* The number of argument registers saved by a SAVE instruction.
510 0 for RESTORE instructions. */
513 /* Bit X is set if the instruction saves or restores GPR X. */
516 /* The total number of bytes to allocate. */
520 /* Costs of various operations on the different architectures. */
522 struct mips_rtx_cost_data
524 unsigned short fp_add
;
525 unsigned short fp_mult_sf
;
526 unsigned short fp_mult_df
;
527 unsigned short fp_div_sf
;
528 unsigned short fp_div_df
;
529 unsigned short int_mult_si
;
530 unsigned short int_mult_di
;
531 unsigned short int_div_si
;
532 unsigned short int_div_di
;
533 unsigned short branch_cost
;
534 unsigned short memory_latency
;
537 /* Global variables for machine-dependent things. */
539 /* The -G setting, or the configuration's default small-data limit if
540 no -G option is given. */
541 static unsigned int mips_small_data_threshold
;
543 /* The number of file directives written by mips_output_filename. */
544 int num_source_filenames
;
546 /* The name that appeared in the last .file directive written by
547 mips_output_filename, or "" if mips_output_filename hasn't
548 written anything yet. */
549 const char *current_function_file
= "";
551 /* Arrays that map GCC register numbers to debugger register numbers. */
552 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
553 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
555 /* Information about the current function's epilogue, used only while
558 /* A list of queued REG_CFA_RESTORE notes. */
561 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
563 HOST_WIDE_INT cfa_offset
;
565 /* The offset of the CFA from the stack pointer while restoring
567 HOST_WIDE_INT cfa_restore_sp_offset
;
570 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
571 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
572 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
573 struct mips_asm_switch mips_noat
= { "at", 0 };
575 /* True if we're writing out a branch-likely instruction rather than a
577 static bool mips_branch_likely
;
579 /* The current instruction-set architecture. */
580 enum processor mips_arch
;
581 const struct mips_cpu_info
*mips_arch_info
;
583 /* The processor that we should tune the code for. */
584 enum processor mips_tune
;
585 const struct mips_cpu_info
*mips_tune_info
;
587 /* The ISA level associated with mips_arch. */
590 /* The ISA revision level. This is 0 for MIPS I to V and N for
594 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
595 static const struct mips_cpu_info
*mips_isa_option_info
;
597 /* Which cost information to use. */
598 static const struct mips_rtx_cost_data
*mips_cost
;
600 /* The ambient target flags, excluding MASK_MIPS16. */
601 static int mips_base_target_flags
;
603 /* The default compression mode. */
604 unsigned int mips_base_compression_flags
;
606 /* The ambient values of other global variables. */
607 static int mips_base_schedule_insns
; /* flag_schedule_insns */
608 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
609 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
610 static int mips_base_align_loops
; /* align_loops */
611 static int mips_base_align_jumps
; /* align_jumps */
612 static int mips_base_align_functions
; /* align_functions */
614 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
615 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
617 /* Index C is true if character C is a valid PRINT_OPERAND punctation
619 static bool mips_print_operand_punct
[256];
621 static GTY (()) int mips_output_filename_first_time
= 1;
623 /* mips_split_p[X] is true if symbols of type X can be split by
624 mips_split_symbol. */
625 bool mips_split_p
[NUM_SYMBOL_TYPES
];
627 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
628 can be split by mips_split_symbol. */
629 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
631 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
632 forced into a PC-relative constant pool. */
633 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
635 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
636 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
637 if they are matched by a special .md file pattern. */
638 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
640 /* Likewise for HIGHs. */
641 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
643 /* Target state for MIPS16. */
644 struct target_globals
*mips16_globals
;
646 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
647 and returned from mips_sched_reorder2. */
648 static int cached_can_issue_more
;
650 /* The stubs for various MIPS16 support functions, if used. */
651 static mips_one_only_stub
*mips16_rdhwr_stub
;
652 static mips_one_only_stub
*mips16_get_fcsr_stub
;
653 static mips_one_only_stub
*mips16_set_fcsr_stub
;
655 /* Index R is the smallest register class that contains register R. */
656 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
657 LEA_REGS
, LEA_REGS
, M16_STORE_REGS
, V1_REG
,
658 M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
,
659 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
660 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
661 M16_REGS
, M16_STORE_REGS
, LEA_REGS
, LEA_REGS
,
662 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
663 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
664 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
666 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
667 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
668 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
669 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
670 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
671 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
672 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
673 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
674 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
675 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
676 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
677 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
678 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
679 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
680 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
681 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
682 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
683 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
684 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
685 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
686 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
687 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
688 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
689 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
690 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
691 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
692 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
693 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
694 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
695 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
696 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
697 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
698 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
699 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
700 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
701 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
702 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
703 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
704 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
707 /* The value of TARGET_ATTRIBUTE_TABLE. */
708 static const struct attribute_spec mips_attribute_table
[] = {
709 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
711 { "long_call", 0, 0, false, true, true, NULL
, false },
712 { "far", 0, 0, false, true, true, NULL
, false },
713 { "near", 0, 0, false, true, true, NULL
, false },
714 /* We would really like to treat "mips16" and "nomips16" as type
715 attributes, but GCC doesn't provide the hooks we need to support
716 the right conversion rules. As declaration attributes, they affect
717 code generation but don't carry other semantics. */
718 { "mips16", 0, 0, true, false, false, NULL
, false },
719 { "nomips16", 0, 0, true, false, false, NULL
, false },
720 { "micromips", 0, 0, true, false, false, NULL
, false },
721 { "nomicromips", 0, 0, true, false, false, NULL
, false },
722 { "nocompression", 0, 0, true, false, false, NULL
, false },
723 /* Allow functions to be specified as interrupt handlers */
724 { "interrupt", 0, 0, false, true, true, NULL
, false },
725 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
726 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
727 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
728 { NULL
, 0, 0, false, false, false, NULL
, false }
731 /* A table describing all the processors GCC knows about; see
732 mips-cpus.def for details. */
733 static const struct mips_cpu_info mips_cpu_info_table
[] = {
734 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
735 { NAME, CPU, ISA, FLAGS },
736 #include "mips-cpus.def"
740 /* Default costs. If these are used for a processor we should look
741 up the actual costs. */
742 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
743 COSTS_N_INSNS (7), /* fp_mult_sf */ \
744 COSTS_N_INSNS (8), /* fp_mult_df */ \
745 COSTS_N_INSNS (23), /* fp_div_sf */ \
746 COSTS_N_INSNS (36), /* fp_div_df */ \
747 COSTS_N_INSNS (10), /* int_mult_si */ \
748 COSTS_N_INSNS (10), /* int_mult_di */ \
749 COSTS_N_INSNS (69), /* int_div_si */ \
750 COSTS_N_INSNS (69), /* int_div_di */ \
751 2, /* branch_cost */ \
752 4 /* memory_latency */
754 /* Floating-point costs for processors without an FPU. Just assume that
755 all floating-point libcalls are very expensive. */
756 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
757 COSTS_N_INSNS (256), /* fp_mult_sf */ \
758 COSTS_N_INSNS (256), /* fp_mult_df */ \
759 COSTS_N_INSNS (256), /* fp_div_sf */ \
760 COSTS_N_INSNS (256) /* fp_div_df */
762 /* Costs to use when optimizing for size. */
763 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
764 COSTS_N_INSNS (1), /* fp_add */
765 COSTS_N_INSNS (1), /* fp_mult_sf */
766 COSTS_N_INSNS (1), /* fp_mult_df */
767 COSTS_N_INSNS (1), /* fp_div_sf */
768 COSTS_N_INSNS (1), /* fp_div_df */
769 COSTS_N_INSNS (1), /* int_mult_si */
770 COSTS_N_INSNS (1), /* int_mult_di */
771 COSTS_N_INSNS (1), /* int_div_si */
772 COSTS_N_INSNS (1), /* int_div_di */
774 4 /* memory_latency */
777 /* Costs to use when optimizing for speed, indexed by processor. */
778 static const struct mips_rtx_cost_data
779 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
781 COSTS_N_INSNS (2), /* fp_add */
782 COSTS_N_INSNS (4), /* fp_mult_sf */
783 COSTS_N_INSNS (5), /* fp_mult_df */
784 COSTS_N_INSNS (12), /* fp_div_sf */
785 COSTS_N_INSNS (19), /* fp_div_df */
786 COSTS_N_INSNS (12), /* int_mult_si */
787 COSTS_N_INSNS (12), /* int_mult_di */
788 COSTS_N_INSNS (35), /* int_div_si */
789 COSTS_N_INSNS (35), /* int_div_di */
791 4 /* memory_latency */
795 COSTS_N_INSNS (6), /* int_mult_si */
796 COSTS_N_INSNS (6), /* int_mult_di */
797 COSTS_N_INSNS (36), /* int_div_si */
798 COSTS_N_INSNS (36), /* int_div_di */
800 4 /* memory_latency */
804 COSTS_N_INSNS (36), /* int_mult_si */
805 COSTS_N_INSNS (36), /* int_mult_di */
806 COSTS_N_INSNS (37), /* int_div_si */
807 COSTS_N_INSNS (37), /* int_div_di */
809 4 /* memory_latency */
813 COSTS_N_INSNS (4), /* int_mult_si */
814 COSTS_N_INSNS (11), /* int_mult_di */
815 COSTS_N_INSNS (36), /* int_div_si */
816 COSTS_N_INSNS (68), /* int_div_di */
818 4 /* memory_latency */
821 COSTS_N_INSNS (4), /* fp_add */
822 COSTS_N_INSNS (4), /* fp_mult_sf */
823 COSTS_N_INSNS (5), /* fp_mult_df */
824 COSTS_N_INSNS (17), /* fp_div_sf */
825 COSTS_N_INSNS (32), /* fp_div_df */
826 COSTS_N_INSNS (4), /* int_mult_si */
827 COSTS_N_INSNS (11), /* int_mult_di */
828 COSTS_N_INSNS (36), /* int_div_si */
829 COSTS_N_INSNS (68), /* int_div_di */
831 4 /* memory_latency */
834 COSTS_N_INSNS (4), /* fp_add */
835 COSTS_N_INSNS (4), /* fp_mult_sf */
836 COSTS_N_INSNS (5), /* fp_mult_df */
837 COSTS_N_INSNS (17), /* fp_div_sf */
838 COSTS_N_INSNS (32), /* fp_div_df */
839 COSTS_N_INSNS (4), /* int_mult_si */
840 COSTS_N_INSNS (7), /* int_mult_di */
841 COSTS_N_INSNS (42), /* int_div_si */
842 COSTS_N_INSNS (72), /* int_div_di */
844 4 /* memory_latency */
848 COSTS_N_INSNS (5), /* int_mult_si */
849 COSTS_N_INSNS (5), /* int_mult_di */
850 COSTS_N_INSNS (41), /* int_div_si */
851 COSTS_N_INSNS (41), /* int_div_di */
853 4 /* memory_latency */
856 COSTS_N_INSNS (8), /* fp_add */
857 COSTS_N_INSNS (8), /* fp_mult_sf */
858 COSTS_N_INSNS (10), /* fp_mult_df */
859 COSTS_N_INSNS (34), /* fp_div_sf */
860 COSTS_N_INSNS (64), /* fp_div_df */
861 COSTS_N_INSNS (5), /* int_mult_si */
862 COSTS_N_INSNS (5), /* int_mult_di */
863 COSTS_N_INSNS (41), /* int_div_si */
864 COSTS_N_INSNS (41), /* int_div_di */
866 4 /* memory_latency */
869 COSTS_N_INSNS (4), /* fp_add */
870 COSTS_N_INSNS (4), /* fp_mult_sf */
871 COSTS_N_INSNS (5), /* fp_mult_df */
872 COSTS_N_INSNS (17), /* fp_div_sf */
873 COSTS_N_INSNS (32), /* fp_div_df */
874 COSTS_N_INSNS (5), /* int_mult_si */
875 COSTS_N_INSNS (5), /* int_mult_di */
876 COSTS_N_INSNS (41), /* int_div_si */
877 COSTS_N_INSNS (41), /* int_div_di */
879 4 /* memory_latency */
883 COSTS_N_INSNS (5), /* int_mult_si */
884 COSTS_N_INSNS (5), /* int_mult_di */
885 COSTS_N_INSNS (41), /* int_div_si */
886 COSTS_N_INSNS (41), /* int_div_di */
888 4 /* memory_latency */
891 COSTS_N_INSNS (8), /* fp_add */
892 COSTS_N_INSNS (8), /* fp_mult_sf */
893 COSTS_N_INSNS (10), /* fp_mult_df */
894 COSTS_N_INSNS (34), /* fp_div_sf */
895 COSTS_N_INSNS (64), /* fp_div_df */
896 COSTS_N_INSNS (5), /* int_mult_si */
897 COSTS_N_INSNS (5), /* int_mult_di */
898 COSTS_N_INSNS (41), /* int_div_si */
899 COSTS_N_INSNS (41), /* int_div_di */
901 4 /* memory_latency */
904 COSTS_N_INSNS (4), /* fp_add */
905 COSTS_N_INSNS (4), /* fp_mult_sf */
906 COSTS_N_INSNS (5), /* fp_mult_df */
907 COSTS_N_INSNS (17), /* fp_div_sf */
908 COSTS_N_INSNS (32), /* fp_div_df */
909 COSTS_N_INSNS (5), /* int_mult_si */
910 COSTS_N_INSNS (5), /* int_mult_di */
911 COSTS_N_INSNS (41), /* int_div_si */
912 COSTS_N_INSNS (41), /* int_div_di */
914 4 /* memory_latency */
917 COSTS_N_INSNS (6), /* fp_add */
918 COSTS_N_INSNS (6), /* fp_mult_sf */
919 COSTS_N_INSNS (7), /* fp_mult_df */
920 COSTS_N_INSNS (25), /* fp_div_sf */
921 COSTS_N_INSNS (48), /* fp_div_df */
922 COSTS_N_INSNS (5), /* int_mult_si */
923 COSTS_N_INSNS (5), /* int_mult_di */
924 COSTS_N_INSNS (41), /* int_div_si */
925 COSTS_N_INSNS (41), /* int_div_di */
927 4 /* memory_latency */
944 COSTS_N_INSNS (5), /* int_mult_si */
945 COSTS_N_INSNS (5), /* int_mult_di */
946 COSTS_N_INSNS (72), /* int_div_si */
947 COSTS_N_INSNS (72), /* int_div_di */
949 4 /* memory_latency */
954 COSTS_N_INSNS (6), /* int_mult_si */
955 COSTS_N_INSNS (6), /* int_mult_di */
956 COSTS_N_INSNS (18), /* int_div_si */
957 COSTS_N_INSNS (35), /* int_div_di */
959 4 /* memory_latency */
962 COSTS_N_INSNS (2), /* fp_add */
963 COSTS_N_INSNS (4), /* fp_mult_sf */
964 COSTS_N_INSNS (5), /* fp_mult_df */
965 COSTS_N_INSNS (12), /* fp_div_sf */
966 COSTS_N_INSNS (19), /* fp_div_df */
967 COSTS_N_INSNS (2), /* int_mult_si */
968 COSTS_N_INSNS (2), /* int_mult_di */
969 COSTS_N_INSNS (35), /* int_div_si */
970 COSTS_N_INSNS (35), /* int_div_di */
972 4 /* memory_latency */
975 COSTS_N_INSNS (3), /* fp_add */
976 COSTS_N_INSNS (5), /* fp_mult_sf */
977 COSTS_N_INSNS (6), /* fp_mult_df */
978 COSTS_N_INSNS (15), /* fp_div_sf */
979 COSTS_N_INSNS (16), /* fp_div_df */
980 COSTS_N_INSNS (17), /* int_mult_si */
981 COSTS_N_INSNS (17), /* int_mult_di */
982 COSTS_N_INSNS (38), /* int_div_si */
983 COSTS_N_INSNS (38), /* int_div_di */
985 6 /* memory_latency */
988 COSTS_N_INSNS (6), /* fp_add */
989 COSTS_N_INSNS (7), /* fp_mult_sf */
990 COSTS_N_INSNS (8), /* fp_mult_df */
991 COSTS_N_INSNS (23), /* fp_div_sf */
992 COSTS_N_INSNS (36), /* fp_div_df */
993 COSTS_N_INSNS (10), /* int_mult_si */
994 COSTS_N_INSNS (10), /* int_mult_di */
995 COSTS_N_INSNS (69), /* int_div_si */
996 COSTS_N_INSNS (69), /* int_div_di */
998 6 /* memory_latency */
1010 /* The only costs that appear to be updated here are
1011 integer multiplication. */
1013 COSTS_N_INSNS (4), /* int_mult_si */
1014 COSTS_N_INSNS (6), /* int_mult_di */
1015 COSTS_N_INSNS (69), /* int_div_si */
1016 COSTS_N_INSNS (69), /* int_div_di */
1017 1, /* branch_cost */
1018 4 /* memory_latency */
1033 COSTS_N_INSNS (6), /* fp_add */
1034 COSTS_N_INSNS (4), /* fp_mult_sf */
1035 COSTS_N_INSNS (5), /* fp_mult_df */
1036 COSTS_N_INSNS (23), /* fp_div_sf */
1037 COSTS_N_INSNS (36), /* fp_div_df */
1038 COSTS_N_INSNS (5), /* int_mult_si */
1039 COSTS_N_INSNS (5), /* int_mult_di */
1040 COSTS_N_INSNS (36), /* int_div_si */
1041 COSTS_N_INSNS (36), /* int_div_di */
1042 1, /* branch_cost */
1043 4 /* memory_latency */
1046 COSTS_N_INSNS (6), /* fp_add */
1047 COSTS_N_INSNS (5), /* fp_mult_sf */
1048 COSTS_N_INSNS (6), /* fp_mult_df */
1049 COSTS_N_INSNS (30), /* fp_div_sf */
1050 COSTS_N_INSNS (59), /* fp_div_df */
1051 COSTS_N_INSNS (3), /* int_mult_si */
1052 COSTS_N_INSNS (4), /* int_mult_di */
1053 COSTS_N_INSNS (42), /* int_div_si */
1054 COSTS_N_INSNS (74), /* int_div_di */
1055 1, /* branch_cost */
1056 4 /* memory_latency */
1059 COSTS_N_INSNS (6), /* fp_add */
1060 COSTS_N_INSNS (5), /* fp_mult_sf */
1061 COSTS_N_INSNS (6), /* fp_mult_df */
1062 COSTS_N_INSNS (30), /* fp_div_sf */
1063 COSTS_N_INSNS (59), /* fp_div_df */
1064 COSTS_N_INSNS (5), /* int_mult_si */
1065 COSTS_N_INSNS (9), /* int_mult_di */
1066 COSTS_N_INSNS (42), /* int_div_si */
1067 COSTS_N_INSNS (74), /* int_div_di */
1068 1, /* branch_cost */
1069 4 /* memory_latency */
1072 COSTS_N_INSNS (4), /* fp_add */
1073 COSTS_N_INSNS (4), /* fp_mult_sf */
1074 COSTS_N_INSNS (256), /* fp_mult_df */
1075 COSTS_N_INSNS (8), /* fp_div_sf */
1076 COSTS_N_INSNS (256), /* fp_div_df */
1077 COSTS_N_INSNS (4), /* int_mult_si */
1078 COSTS_N_INSNS (256), /* int_mult_di */
1079 COSTS_N_INSNS (37), /* int_div_si */
1080 COSTS_N_INSNS (256), /* int_div_di */
1081 1, /* branch_cost */
1082 4 /* memory_latency */
1085 /* The only costs that are changed here are
1086 integer multiplication. */
1087 COSTS_N_INSNS (6), /* fp_add */
1088 COSTS_N_INSNS (7), /* fp_mult_sf */
1089 COSTS_N_INSNS (8), /* fp_mult_df */
1090 COSTS_N_INSNS (23), /* fp_div_sf */
1091 COSTS_N_INSNS (36), /* fp_div_df */
1092 COSTS_N_INSNS (5), /* int_mult_si */
1093 COSTS_N_INSNS (9), /* int_mult_di */
1094 COSTS_N_INSNS (69), /* int_div_si */
1095 COSTS_N_INSNS (69), /* int_div_di */
1096 1, /* branch_cost */
1097 4 /* memory_latency */
1103 /* The only costs that are changed here are
1104 integer multiplication. */
1105 COSTS_N_INSNS (6), /* fp_add */
1106 COSTS_N_INSNS (7), /* fp_mult_sf */
1107 COSTS_N_INSNS (8), /* fp_mult_df */
1108 COSTS_N_INSNS (23), /* fp_div_sf */
1109 COSTS_N_INSNS (36), /* fp_div_df */
1110 COSTS_N_INSNS (3), /* int_mult_si */
1111 COSTS_N_INSNS (8), /* int_mult_di */
1112 COSTS_N_INSNS (69), /* int_div_si */
1113 COSTS_N_INSNS (69), /* int_div_di */
1114 1, /* branch_cost */
1115 4 /* memory_latency */
1118 COSTS_N_INSNS (2), /* fp_add */
1119 COSTS_N_INSNS (2), /* fp_mult_sf */
1120 COSTS_N_INSNS (2), /* fp_mult_df */
1121 COSTS_N_INSNS (12), /* fp_div_sf */
1122 COSTS_N_INSNS (19), /* fp_div_df */
1123 COSTS_N_INSNS (5), /* int_mult_si */
1124 COSTS_N_INSNS (9), /* int_mult_di */
1125 COSTS_N_INSNS (34), /* int_div_si */
1126 COSTS_N_INSNS (66), /* int_div_di */
1127 1, /* branch_cost */
1128 4 /* memory_latency */
1131 /* These costs are the same as the SB-1A below. */
1132 COSTS_N_INSNS (4), /* fp_add */
1133 COSTS_N_INSNS (4), /* fp_mult_sf */
1134 COSTS_N_INSNS (4), /* fp_mult_df */
1135 COSTS_N_INSNS (24), /* fp_div_sf */
1136 COSTS_N_INSNS (32), /* fp_div_df */
1137 COSTS_N_INSNS (3), /* int_mult_si */
1138 COSTS_N_INSNS (4), /* int_mult_di */
1139 COSTS_N_INSNS (36), /* int_div_si */
1140 COSTS_N_INSNS (68), /* int_div_di */
1141 1, /* branch_cost */
1142 4 /* memory_latency */
1145 /* These costs are the same as the SB-1 above. */
1146 COSTS_N_INSNS (4), /* fp_add */
1147 COSTS_N_INSNS (4), /* fp_mult_sf */
1148 COSTS_N_INSNS (4), /* fp_mult_df */
1149 COSTS_N_INSNS (24), /* fp_div_sf */
1150 COSTS_N_INSNS (32), /* fp_div_df */
1151 COSTS_N_INSNS (3), /* int_mult_si */
1152 COSTS_N_INSNS (4), /* int_mult_di */
1153 COSTS_N_INSNS (36), /* int_div_si */
1154 COSTS_N_INSNS (68), /* int_div_di */
1155 1, /* branch_cost */
1156 4 /* memory_latency */
1163 COSTS_N_INSNS (8), /* int_mult_si */
1164 COSTS_N_INSNS (8), /* int_mult_di */
1165 COSTS_N_INSNS (72), /* int_div_si */
1166 COSTS_N_INSNS (72), /* int_div_di */
1167 1, /* branch_cost */
1168 4 /* memory_latency */
1171 /* These costs are the same as 5KF above. */
1172 COSTS_N_INSNS (4), /* fp_add */
1173 COSTS_N_INSNS (4), /* fp_mult_sf */
1174 COSTS_N_INSNS (5), /* fp_mult_df */
1175 COSTS_N_INSNS (17), /* fp_div_sf */
1176 COSTS_N_INSNS (32), /* fp_div_df */
1177 COSTS_N_INSNS (4), /* int_mult_si */
1178 COSTS_N_INSNS (11), /* int_mult_di */
1179 COSTS_N_INSNS (36), /* int_div_si */
1180 COSTS_N_INSNS (68), /* int_div_di */
1181 1, /* branch_cost */
1182 4 /* memory_latency */
1185 COSTS_N_INSNS (4), /* fp_add */
1186 COSTS_N_INSNS (5), /* fp_mult_sf */
1187 COSTS_N_INSNS (5), /* fp_mult_df */
1188 COSTS_N_INSNS (17), /* fp_div_sf */
1189 COSTS_N_INSNS (17), /* fp_div_df */
1190 COSTS_N_INSNS (5), /* int_mult_si */
1191 COSTS_N_INSNS (5), /* int_mult_di */
1192 COSTS_N_INSNS (8), /* int_div_si */
1193 COSTS_N_INSNS (8), /* int_div_di */
1194 2, /* branch_cost */
1195 10 /* memory_latency */
1199 static rtx
mips_find_pic_call_symbol (rtx
, rtx
, bool);
1200 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1202 static unsigned int mips_function_arg_boundary (enum machine_mode
, const_tree
);
1204 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1205 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1206 struct GTY (()) mflip_mips16_entry
{
1210 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1212 /* Hash table callbacks for mflip_mips16_htab. */
1215 mflip_mips16_htab_hash (const void *entry
)
1217 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1221 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1223 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1224 (const char *) name
) == 0;
1227 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1228 mode, false if it should next add an attribute for the opposite mode. */
1229 static GTY(()) bool mips16_flipper
;
1231 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1232 for -mflip-mips16. Return true if it should use "mips16" and false if
1233 it should use "nomips16". */
1236 mflip_mips16_use_mips16_p (tree decl
)
1238 struct mflip_mips16_entry
*entry
;
1242 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1244 /* Use the opposite of the command-line setting for anonymous decls. */
1245 if (!DECL_NAME (decl
))
1246 return !base_is_mips16
;
1248 if (!mflip_mips16_htab
)
1249 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1250 mflip_mips16_htab_eq
, NULL
);
1252 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1253 hash
= htab_hash_string (name
);
1254 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1255 entry
= (struct mflip_mips16_entry
*) *slot
;
1258 mips16_flipper
= !mips16_flipper
;
1259 entry
= ggc_alloc
<mflip_mips16_entry
> ();
1261 entry
->mips16_p
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1264 return entry
->mips16_p
;
1267 /* Predicates to test for presence of "near" and "far"/"long_call"
1268 attributes on the given TYPE. */
1271 mips_near_type_p (const_tree type
)
1273 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1277 mips_far_type_p (const_tree type
)
1279 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1280 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1284 /* Check if the interrupt attribute is set for a function. */
1287 mips_interrupt_type_p (tree type
)
1289 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1292 /* Check if the attribute to use shadow register set is set for a function. */
1295 mips_use_shadow_register_set_p (tree type
)
1297 return lookup_attribute ("use_shadow_register_set",
1298 TYPE_ATTRIBUTES (type
)) != NULL
;
1301 /* Check if the attribute to keep interrupts masked is set for a function. */
1304 mips_keep_interrupts_masked_p (tree type
)
1306 return lookup_attribute ("keep_interrupts_masked",
1307 TYPE_ATTRIBUTES (type
)) != NULL
;
1310 /* Check if the attribute to use debug exception return is set for
1314 mips_use_debug_exception_return_p (tree type
)
1316 return lookup_attribute ("use_debug_exception_return",
1317 TYPE_ATTRIBUTES (type
)) != NULL
;
1320 /* Return the set of compression modes that are explicitly required
1321 by the attributes in ATTRIBUTES. */
1324 mips_get_compress_on_flags (tree attributes
)
1326 unsigned int flags
= 0;
1328 if (lookup_attribute ("mips16", attributes
) != NULL
)
1329 flags
|= MASK_MIPS16
;
1331 if (lookup_attribute ("micromips", attributes
) != NULL
)
1332 flags
|= MASK_MICROMIPS
;
1337 /* Return the set of compression modes that are explicitly forbidden
1338 by the attributes in ATTRIBUTES. */
1341 mips_get_compress_off_flags (tree attributes
)
1343 unsigned int flags
= 0;
1345 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1346 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1348 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1349 flags
|= MASK_MIPS16
;
1351 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1352 flags
|= MASK_MICROMIPS
;
1357 /* Return the compression mode that should be used for function DECL.
1358 Return the ambient setting if DECL is null. */
1361 mips_get_compress_mode (tree decl
)
1363 unsigned int flags
, force_on
;
1365 flags
= mips_base_compression_flags
;
1368 /* Nested functions must use the same frame pointer as their
1369 parent and must therefore use the same ISA mode. */
1370 tree parent
= decl_function_context (decl
);
1373 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1376 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1381 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1385 mips_get_compress_on_name (unsigned int flags
)
1387 if (flags
== MASK_MIPS16
)
1392 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1396 mips_get_compress_off_name (unsigned int flags
)
1398 if (flags
== MASK_MIPS16
)
1400 if (flags
== MASK_MICROMIPS
)
1401 return "nomicromips";
1402 return "nocompression";
1405 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1408 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1410 /* Disallow mixed near/far attributes. */
1411 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1413 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1418 /* Implement TARGET_INSERT_ATTRIBUTES. */
1421 mips_insert_attributes (tree decl
, tree
*attributes
)
1424 unsigned int compression_flags
, nocompression_flags
;
1426 /* Check for "mips16" and "nomips16" attributes. */
1427 compression_flags
= mips_get_compress_on_flags (*attributes
);
1428 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1430 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1432 if (nocompression_flags
)
1433 error ("%qs attribute only applies to functions",
1434 mips_get_compress_off_name (nocompression_flags
));
1436 if (compression_flags
)
1437 error ("%qs attribute only applies to functions",
1438 mips_get_compress_on_name (nocompression_flags
));
1442 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1443 nocompression_flags
|=
1444 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1446 if (compression_flags
&& nocompression_flags
)
1447 error ("%qE cannot have both %qs and %qs attributes",
1448 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1449 mips_get_compress_off_name (nocompression_flags
));
1451 if (compression_flags
& MASK_MIPS16
1452 && compression_flags
& MASK_MICROMIPS
)
1453 error ("%qE cannot have both %qs and %qs attributes",
1454 DECL_NAME (decl
), "mips16", "micromips");
1456 if (TARGET_FLIP_MIPS16
1457 && !DECL_ARTIFICIAL (decl
)
1458 && compression_flags
== 0
1459 && nocompression_flags
== 0)
1461 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1462 "mips16" attribute, arbitrarily pick one. We must pick the same
1463 setting for duplicate declarations of a function. */
1464 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1465 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1466 name
= "nomicromips";
1467 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1472 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1475 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1479 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1480 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1482 error ("%qE redeclared with conflicting %qs attributes",
1483 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1485 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1486 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1488 error ("%qE redeclared with conflicting %qs attributes",
1489 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1491 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1492 DECL_ATTRIBUTES (newdecl
));
1495 /* Implement TARGET_CAN_INLINE_P. */
1498 mips_can_inline_p (tree caller
, tree callee
)
1500 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1502 return default_target_can_inline_p (caller
, callee
);
1505 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1506 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1509 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1511 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1513 *base_ptr
= XEXP (x
, 0);
1514 *offset_ptr
= INTVAL (XEXP (x
, 1));
1523 static unsigned int mips_build_integer (struct mips_integer_op
*,
1524 unsigned HOST_WIDE_INT
);
1526 /* A subroutine of mips_build_integer, with the same interface.
1527 Assume that the final action in the sequence should be a left shift. */
1530 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1532 unsigned int i
, shift
;
1534 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1535 since signed numbers are easier to load than unsigned ones. */
1537 while ((value
& 1) == 0)
1538 value
/= 2, shift
++;
1540 i
= mips_build_integer (codes
, value
);
1541 codes
[i
].code
= ASHIFT
;
1542 codes
[i
].value
= shift
;
1546 /* As for mips_build_shift, but assume that the final action will be
1547 an IOR or PLUS operation. */
1550 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1552 unsigned HOST_WIDE_INT high
;
1555 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1556 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1558 /* The constant is too complex to load with a simple LUI/ORI pair,
1559 so we want to give the recursive call as many trailing zeros as
1560 possible. In this case, we know bit 16 is set and that the
1561 low 16 bits form a negative number. If we subtract that number
1562 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1563 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1564 codes
[i
].code
= PLUS
;
1565 codes
[i
].value
= CONST_LOW_PART (value
);
1569 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1570 bits gives a value with at least 17 trailing zeros. */
1571 i
= mips_build_integer (codes
, high
);
1572 codes
[i
].code
= IOR
;
1573 codes
[i
].value
= value
& 0xffff;
1578 /* Fill CODES with a sequence of rtl operations to load VALUE.
1579 Return the number of operations needed. */
1582 mips_build_integer (struct mips_integer_op
*codes
,
1583 unsigned HOST_WIDE_INT value
)
1585 if (SMALL_OPERAND (value
)
1586 || SMALL_OPERAND_UNSIGNED (value
)
1587 || LUI_OPERAND (value
))
1589 /* The value can be loaded with a single instruction. */
1590 codes
[0].code
= UNKNOWN
;
1591 codes
[0].value
= value
;
1594 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1596 /* Either the constant is a simple LUI/ORI combination or its
1597 lowest bit is set. We don't want to shift in this case. */
1598 return mips_build_lower (codes
, value
);
1600 else if ((value
& 0xffff) == 0)
1602 /* The constant will need at least three actions. The lowest
1603 16 bits are clear, so the final action will be a shift. */
1604 return mips_build_shift (codes
, value
);
1608 /* The final action could be a shift, add or inclusive OR.
1609 Rather than use a complex condition to select the best
1610 approach, try both mips_build_shift and mips_build_lower
1611 and pick the one that gives the shortest sequence.
1612 Note that this case is only used once per constant. */
1613 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1614 unsigned int cost
, alt_cost
;
1616 cost
= mips_build_shift (codes
, value
);
1617 alt_cost
= mips_build_lower (alt_codes
, value
);
1618 if (alt_cost
< cost
)
1620 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1627 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1630 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1632 return mips_const_insns (x
) > 0;
1635 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1638 mips16_stub_function (const char *name
)
1642 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1643 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1647 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1648 support function. */
1651 mips16_stub_call_address (mips_one_only_stub
*stub
)
1653 rtx fn
= mips16_stub_function (stub
->get_name ());
1654 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
1655 if (!call_insn_operand (fn
, VOIDmode
))
1656 fn
= force_reg (Pmode
, fn
);
1660 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1662 class mips16_rdhwr_one_only_stub
: public mips_one_only_stub
1664 virtual const char *get_name ();
1665 virtual void output_body ();
1669 mips16_rdhwr_one_only_stub::get_name ()
1671 return "__mips16_rdhwr";
1675 mips16_rdhwr_one_only_stub::output_body ()
1677 fprintf (asm_out_file
,
1679 "\t.set\tmips32r2\n"
1680 "\t.set\tnoreorder\n"
1686 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1687 class mips16_get_fcsr_one_only_stub
: public mips_one_only_stub
1689 virtual const char *get_name ();
1690 virtual void output_body ();
1694 mips16_get_fcsr_one_only_stub::get_name ()
1696 return "__mips16_get_fcsr";
1700 mips16_get_fcsr_one_only_stub::output_body ()
1702 fprintf (asm_out_file
,
1704 "\tj\t$31\n", reg_names
[GET_FCSR_REGNUM
]);
1707 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1708 class mips16_set_fcsr_one_only_stub
: public mips_one_only_stub
1710 virtual const char *get_name ();
1711 virtual void output_body ();
1715 mips16_set_fcsr_one_only_stub::get_name ()
1717 return "__mips16_set_fcsr";
1721 mips16_set_fcsr_one_only_stub::output_body ()
1723 fprintf (asm_out_file
,
1725 "\tj\t$31\n", reg_names
[SET_FCSR_REGNUM
]);
1728 /* Return true if symbols of type TYPE require a GOT access. */
1731 mips_got_symbol_type_p (enum mips_symbol_type type
)
1735 case SYMBOL_GOT_PAGE_OFST
:
1736 case SYMBOL_GOT_DISP
:
1744 /* Return true if X is a thread-local symbol. */
1747 mips_tls_symbol_p (rtx x
)
1749 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1752 /* Return true if SYMBOL_REF X is associated with a global symbol
1753 (in the STB_GLOBAL sense). */
1756 mips_global_symbol_p (const_rtx x
)
1758 const_tree decl
= SYMBOL_REF_DECL (x
);
1761 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1763 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1764 or weak symbols. Relocations in the object file will be against
1765 the target symbol, so it's that symbol's binding that matters here. */
1766 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1769 /* Return true if function X is a libgcc MIPS16 stub function. */
1772 mips16_stub_function_p (const_rtx x
)
1774 return (GET_CODE (x
) == SYMBOL_REF
1775 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1778 /* Return true if function X is a locally-defined and locally-binding
1782 mips16_local_function_p (const_rtx x
)
1784 return (GET_CODE (x
) == SYMBOL_REF
1785 && SYMBOL_REF_LOCAL_P (x
)
1786 && !SYMBOL_REF_EXTERNAL_P (x
)
1787 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1790 /* Return true if SYMBOL_REF X binds locally. */
1793 mips_symbol_binds_local_p (const_rtx x
)
1795 return (SYMBOL_REF_DECL (x
)
1796 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1797 : SYMBOL_REF_LOCAL_P (x
));
1800 /* Return true if rtx constants of mode MODE should be put into a small
1804 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1806 return (!TARGET_EMBEDDED_DATA
1807 && TARGET_LOCAL_SDATA
1808 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1811 /* Return true if X should not be moved directly into register $25.
1812 We need this because many versions of GAS will treat "la $25,foo" as
1813 part of a call sequence and so allow a global "foo" to be lazily bound. */
1816 mips_dangerous_for_la25_p (rtx x
)
1818 return (!TARGET_EXPLICIT_RELOCS
1820 && GET_CODE (x
) == SYMBOL_REF
1821 && mips_global_symbol_p (x
));
1824 /* Return true if calls to X might need $25 to be valid on entry. */
1827 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1829 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1832 /* MIPS16 stub functions are guaranteed not to use $25. */
1833 if (mips16_stub_function_p (x
))
1836 if (GET_CODE (x
) == SYMBOL_REF
)
1838 /* If PLTs and copy relocations are available, the static linker
1839 will make sure that $25 is valid on entry to the target function. */
1840 if (TARGET_ABICALLS_PIC0
)
1843 /* Locally-defined functions use absolute accesses to set up
1844 the global pointer. */
1845 if (TARGET_ABSOLUTE_ABICALLS
1846 && mips_symbol_binds_local_p (x
)
1847 && !SYMBOL_REF_EXTERNAL_P (x
))
1854 /* Return the method that should be used to access SYMBOL_REF or
1855 LABEL_REF X in context CONTEXT. */
1857 static enum mips_symbol_type
1858 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1861 return SYMBOL_GOT_DISP
;
1863 if (GET_CODE (x
) == LABEL_REF
)
1865 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1866 code and if we know that the label is in the current function's
1867 text section. LABEL_REFs are used for jump tables as well as
1868 text labels, so we must check whether jump tables live in the
1870 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1871 && !LABEL_REF_NONLOCAL_P (x
))
1872 return SYMBOL_PC_RELATIVE
;
1874 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1875 return SYMBOL_GOT_PAGE_OFST
;
1877 return SYMBOL_ABSOLUTE
;
1880 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1882 if (SYMBOL_REF_TLS_MODEL (x
))
1885 if (CONSTANT_POOL_ADDRESS_P (x
))
1887 if (TARGET_MIPS16_TEXT_LOADS
)
1888 return SYMBOL_PC_RELATIVE
;
1890 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1891 return SYMBOL_PC_RELATIVE
;
1893 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1894 return SYMBOL_GP_RELATIVE
;
1897 /* Do not use small-data accesses for weak symbols; they may end up
1899 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1900 return SYMBOL_GP_RELATIVE
;
1902 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1904 if (TARGET_ABICALLS_PIC2
1905 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1907 /* There are three cases to consider:
1909 - o32 PIC (either with or without explicit relocs)
1910 - n32/n64 PIC without explicit relocs
1911 - n32/n64 PIC with explicit relocs
1913 In the first case, both local and global accesses will use an
1914 R_MIPS_GOT16 relocation. We must correctly predict which of
1915 the two semantics (local or global) the assembler and linker
1916 will apply. The choice depends on the symbol's binding rather
1917 than its visibility.
1919 In the second case, the assembler will not use R_MIPS_GOT16
1920 relocations, but it chooses between local and global accesses
1921 in the same way as for o32 PIC.
1923 In the third case we have more freedom since both forms of
1924 access will work for any kind of symbol. However, there seems
1925 little point in doing things differently. */
1926 if (mips_global_symbol_p (x
))
1927 return SYMBOL_GOT_DISP
;
1929 return SYMBOL_GOT_PAGE_OFST
;
1932 return SYMBOL_ABSOLUTE
;
1935 /* Classify the base of symbolic expression X, given that X appears in
1938 static enum mips_symbol_type
1939 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1943 split_const (x
, &x
, &offset
);
1944 if (UNSPEC_ADDRESS_P (x
))
1945 return UNSPEC_ADDRESS_TYPE (x
);
1947 return mips_classify_symbol (x
, context
);
1950 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1951 is the alignment in bytes of SYMBOL_REF X. */
1954 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1956 HOST_WIDE_INT align
;
1958 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1959 return IN_RANGE (offset
, 0, align
- 1);
1962 /* Return true if X is a symbolic constant that can be used in context
1963 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1966 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1967 enum mips_symbol_type
*symbol_type
)
1971 split_const (x
, &x
, &offset
);
1972 if (UNSPEC_ADDRESS_P (x
))
1974 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1975 x
= UNSPEC_ADDRESS (x
);
1977 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1979 *symbol_type
= mips_classify_symbol (x
, context
);
1980 if (*symbol_type
== SYMBOL_TLS
)
1986 if (offset
== const0_rtx
)
1989 /* Check whether a nonzero offset is valid for the underlying
1991 switch (*symbol_type
)
1993 case SYMBOL_ABSOLUTE
:
1994 case SYMBOL_64_HIGH
:
1997 /* If the target has 64-bit pointers and the object file only
1998 supports 32-bit symbols, the values of those symbols will be
1999 sign-extended. In this case we can't allow an arbitrary offset
2000 in case the 32-bit value X + OFFSET has a different sign from X. */
2001 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
2002 return offset_within_block_p (x
, INTVAL (offset
));
2004 /* In other cases the relocations can handle any offset. */
2007 case SYMBOL_PC_RELATIVE
:
2008 /* Allow constant pool references to be converted to LABEL+CONSTANT.
2009 In this case, we no longer have access to the underlying constant,
2010 but the original symbol-based access was known to be valid. */
2011 if (GET_CODE (x
) == LABEL_REF
)
2016 case SYMBOL_GP_RELATIVE
:
2017 /* Make sure that the offset refers to something within the
2018 same object block. This should guarantee that the final
2019 PC- or GP-relative offset is within the 16-bit limit. */
2020 return offset_within_block_p (x
, INTVAL (offset
));
2022 case SYMBOL_GOT_PAGE_OFST
:
2023 case SYMBOL_GOTOFF_PAGE
:
2024 /* If the symbol is global, the GOT entry will contain the symbol's
2025 address, and we will apply a 16-bit offset after loading it.
2026 If the symbol is local, the linker should provide enough local
2027 GOT entries for a 16-bit offset, but larger offsets may lead
2029 return SMALL_INT (offset
);
2033 /* There is no carry between the HI and LO REL relocations, so the
2034 offset is only valid if we know it won't lead to such a carry. */
2035 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
2037 case SYMBOL_GOT_DISP
:
2038 case SYMBOL_GOTOFF_DISP
:
2039 case SYMBOL_GOTOFF_CALL
:
2040 case SYMBOL_GOTOFF_LOADGP
:
2043 case SYMBOL_GOTTPREL
:
2051 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2052 single instruction. We rely on the fact that, in the worst case,
2053 all instructions involved in a MIPS16 address calculation are usually
2057 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
2059 if (mips_use_pcrel_pool_p
[(int) type
])
2061 if (mode
== MAX_MACHINE_MODE
)
2062 /* LEAs will be converted into constant-pool references by
2064 type
= SYMBOL_PC_RELATIVE
;
2066 /* The constant must be loaded and then dereferenced. */
2072 case SYMBOL_ABSOLUTE
:
2073 /* When using 64-bit symbols, we need 5 preparatory instructions,
2076 lui $at,%highest(symbol)
2077 daddiu $at,$at,%higher(symbol)
2079 daddiu $at,$at,%hi(symbol)
2082 The final address is then $at + %lo(symbol). With 32-bit
2083 symbols we just need a preparatory LUI for normal mode and
2084 a preparatory LI and SLL for MIPS16. */
2085 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
2087 case SYMBOL_GP_RELATIVE
:
2088 /* Treat GP-relative accesses as taking a single instruction on
2089 MIPS16 too; the copy of $gp can often be shared. */
2092 case SYMBOL_PC_RELATIVE
:
2093 /* PC-relative constants can be only be used with ADDIUPC,
2094 DADDIUPC, LWPC and LDPC. */
2095 if (mode
== MAX_MACHINE_MODE
2096 || GET_MODE_SIZE (mode
) == 4
2097 || GET_MODE_SIZE (mode
) == 8)
2100 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2103 case SYMBOL_GOT_DISP
:
2104 /* The constant will have to be loaded from the GOT before it
2105 is used in an address. */
2106 if (mode
!= MAX_MACHINE_MODE
)
2111 case SYMBOL_GOT_PAGE_OFST
:
2112 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2113 local/global classification is accurate. The worst cases are:
2115 (1) For local symbols when generating o32 or o64 code. The assembler
2121 ...and the final address will be $at + %lo(symbol).
2123 (2) For global symbols when -mxgot. The assembler will use:
2125 lui $at,%got_hi(symbol)
2128 ...and the final address will be $at + %got_lo(symbol). */
2131 case SYMBOL_GOTOFF_PAGE
:
2132 case SYMBOL_GOTOFF_DISP
:
2133 case SYMBOL_GOTOFF_CALL
:
2134 case SYMBOL_GOTOFF_LOADGP
:
2135 case SYMBOL_64_HIGH
:
2141 case SYMBOL_GOTTPREL
:
2144 /* A 16-bit constant formed by a single relocation, or a 32-bit
2145 constant formed from a high 16-bit relocation and a low 16-bit
2146 relocation. Use mips_split_p to determine which. 32-bit
2147 constants need an "lui; addiu" sequence for normal mode and
2148 an "li; sll; addiu" sequence for MIPS16 mode. */
2149 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2152 /* We don't treat a bare TLS symbol as a constant. */
2158 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2159 to load symbols of type TYPE into a register. Return 0 if the given
2160 type of symbol cannot be used as an immediate operand.
2162 Otherwise, return the number of instructions needed to load or store
2163 values of mode MODE to or from addresses of type TYPE. Return 0 if
2164 the given type of symbol is not valid in addresses.
2166 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2169 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
2171 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2174 /* A for_each_rtx callback. Stop the search if *X references a
2175 thread-local symbol. */
2178 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
2180 return mips_tls_symbol_p (*x
);
2183 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2186 mips_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2188 enum mips_symbol_type type
;
2191 /* There is no assembler syntax for expressing an address-sized
2193 if (GET_CODE (x
) == HIGH
)
2196 /* As an optimization, reject constants that mips_legitimize_move
2199 Suppose we have a multi-instruction sequence that loads constant C
2200 into register R. If R does not get allocated a hard register, and
2201 R is used in an operand that allows both registers and memory
2202 references, reload will consider forcing C into memory and using
2203 one of the instruction's memory alternatives. Returning false
2204 here will force it to use an input reload instead. */
2205 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2208 split_const (x
, &base
, &offset
);
2209 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2211 /* See whether we explicitly want these symbols in the pool. */
2212 if (mips_use_pcrel_pool_p
[(int) type
])
2215 /* The same optimization as for CONST_INT. */
2216 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2219 /* If MIPS16 constant pools live in the text section, they should
2220 not refer to anything that might need run-time relocation. */
2221 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2225 /* TLS symbols must be computed by mips_legitimize_move. */
2226 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
2232 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2233 constants when we're using a per-function constant pool. */
2236 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2237 const_rtx x ATTRIBUTE_UNUSED
)
2239 return !TARGET_MIPS16_PCREL_LOADS
;
2242 /* Return true if register REGNO is a valid base register for mode MODE.
2243 STRICT_P is true if REG_OK_STRICT is in effect. */
2246 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
2249 if (!HARD_REGISTER_NUM_P (regno
))
2253 regno
= reg_renumber
[regno
];
2256 /* These fake registers will be eliminated to either the stack or
2257 hard frame pointer, both of which are usually valid base registers.
2258 Reload deals with the cases where the eliminated form isn't valid. */
2259 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2262 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2263 values, nothing smaller. There are two problems here:
2265 (a) Instantiating virtual registers can introduce new uses of the
2266 stack pointer. If these virtual registers are valid addresses,
2267 the stack pointer should be too.
2269 (b) Most uses of the stack pointer are not made explicit until
2270 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2271 We don't know until that stage whether we'll be eliminating to the
2272 stack pointer (which needs the restriction) or the hard frame
2273 pointer (which doesn't).
2275 All in all, it seems more consistent to only enforce this restriction
2276 during and after reload. */
2277 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2278 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2280 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2283 /* Return true if X is a valid base register for mode MODE.
2284 STRICT_P is true if REG_OK_STRICT is in effect. */
2287 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2289 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2293 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2296 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2297 can address a value of mode MODE. */
2300 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2302 /* Check that X is a signed 16-bit number. */
2303 if (!const_arith_operand (x
, Pmode
))
2306 /* We may need to split multiword moves, so make sure that every word
2308 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2309 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2315 /* Return true if a LO_SUM can address a value of mode MODE when the
2316 LO_SUM symbol has type SYMBOL_TYPE. */
2319 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2321 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2323 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2326 /* Check that there is a known low-part relocation. */
2327 if (mips_lo_relocs
[symbol_type
] == NULL
)
2330 /* We may need to split multiword moves, so make sure that each word
2331 can be accessed without inducing a carry. This is mainly needed
2332 for o64, which has historically only guaranteed 64-bit alignment
2333 for 128-bit types. */
2334 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2335 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2341 /* Return true if X is a valid address for machine mode MODE. If it is,
2342 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2346 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2347 enum machine_mode mode
, bool strict_p
)
2349 switch (GET_CODE (x
))
2353 info
->type
= ADDRESS_REG
;
2355 info
->offset
= const0_rtx
;
2356 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2359 info
->type
= ADDRESS_REG
;
2360 info
->reg
= XEXP (x
, 0);
2361 info
->offset
= XEXP (x
, 1);
2362 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2363 && mips_valid_offset_p (info
->offset
, mode
));
2366 info
->type
= ADDRESS_LO_SUM
;
2367 info
->reg
= XEXP (x
, 0);
2368 info
->offset
= XEXP (x
, 1);
2369 /* We have to trust the creator of the LO_SUM to do something vaguely
2370 sane. Target-independent code that creates a LO_SUM should also
2371 create and verify the matching HIGH. Target-independent code that
2372 adds an offset to a LO_SUM must prove that the offset will not
2373 induce a carry. Failure to do either of these things would be
2374 a bug, and we are not required to check for it here. The MIPS
2375 backend itself should only create LO_SUMs for valid symbolic
2376 constants, with the high part being either a HIGH or a copy
2379 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2380 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2381 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2384 /* Small-integer addresses don't occur very often, but they
2385 are legitimate if $0 is a valid base register. */
2386 info
->type
= ADDRESS_CONST_INT
;
2387 return !TARGET_MIPS16
&& SMALL_INT (x
);
2392 info
->type
= ADDRESS_SYMBOLIC
;
2393 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2395 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2396 && !mips_split_p
[info
->symbol_type
]);
2403 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2406 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2408 struct mips_address_info addr
;
2410 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2413 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2416 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2418 struct mips_address_info addr
;
2420 return (mips_classify_address (&addr
, x
, mode
, false)
2421 && addr
.type
== ADDRESS_REG
2422 && addr
.reg
== stack_pointer_rtx
);
2425 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2426 address instruction. Note that such addresses are not considered
2427 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2428 is so restricted. */
2431 mips_lwxs_address_p (rtx addr
)
2434 && GET_CODE (addr
) == PLUS
2435 && REG_P (XEXP (addr
, 1)))
2437 rtx offset
= XEXP (addr
, 0);
2438 if (GET_CODE (offset
) == MULT
2439 && REG_P (XEXP (offset
, 0))
2440 && CONST_INT_P (XEXP (offset
, 1))
2441 && INTVAL (XEXP (offset
, 1)) == 4)
2447 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2448 indexed address instruction. Note that such addresses are
2449 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2450 sense, because their use is so restricted. */
2453 mips_lx_address_p (rtx addr
, enum machine_mode mode
)
2455 if (GET_CODE (addr
) != PLUS
2456 || !REG_P (XEXP (addr
, 0))
2457 || !REG_P (XEXP (addr
, 1)))
2459 if (ISA_HAS_LBX
&& mode
== QImode
)
2461 if (ISA_HAS_LHX
&& mode
== HImode
)
2463 if (ISA_HAS_LWX
&& mode
== SImode
)
2465 if (ISA_HAS_LDX
&& mode
== DImode
)
2470 /* Return true if a value at OFFSET bytes from base register BASE can be
2471 accessed using an unextended MIPS16 instruction. MODE is the mode of
2474 Usually the offset in an unextended instruction is a 5-bit field.
2475 The offset is unsigned and shifted left once for LH and SH, twice
2476 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2477 an 8-bit immediate field that's shifted left twice. */
2480 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2481 unsigned HOST_WIDE_INT offset
)
2483 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2485 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2486 return offset
< 256U * GET_MODE_SIZE (mode
);
2487 return offset
< 32U * GET_MODE_SIZE (mode
);
2492 /* Return the number of instructions needed to load or store a value
2493 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2494 length of one instruction. Return 0 if X isn't valid for MODE.
2495 Assume that multiword moves may need to be split into word moves
2496 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2500 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2502 struct mips_address_info addr
;
2505 /* BLKmode is used for single unaligned loads and stores and should
2506 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2507 meaningless, so we have to single it out as a special case one way
2509 if (mode
!= BLKmode
&& might_split_p
)
2510 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2514 if (mips_classify_address (&addr
, x
, mode
, false))
2519 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2520 UINTVAL (addr
.offset
)))
2524 case ADDRESS_LO_SUM
:
2525 return TARGET_MIPS16
? factor
* 2 : factor
;
2527 case ADDRESS_CONST_INT
:
2530 case ADDRESS_SYMBOLIC
:
2531 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2536 /* Return true if X fits within an unsigned field of BITS bits that is
2537 shifted left SHIFT bits before being used. */
2540 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2542 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2545 /* Return true if X fits within a signed field of BITS bits that is
2546 shifted left SHIFT bits before being used. */
2549 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2551 x
+= 1 << (bits
+ shift
- 1);
2552 return mips_unsigned_immediate_p (x
, bits
, shift
);
2555 /* Return true if X is legitimate for accessing values of mode MODE,
2556 if it is based on a MIPS16 register, and if the offset satisfies
2557 OFFSET_PREDICATE. */
2560 m16_based_address_p (rtx x
, enum machine_mode mode
,
2561 insn_operand_predicate_fn offset_predicate
)
2563 struct mips_address_info addr
;
2565 return (mips_classify_address (&addr
, x
, mode
, false)
2566 && addr
.type
== ADDRESS_REG
2567 && M16_REG_P (REGNO (addr
.reg
))
2568 && offset_predicate (addr
.offset
, mode
));
2571 /* Return true if X is a legitimate address that conforms to the requirements
2572 for a microMIPS LWSP or SWSP insn. */
2575 lwsp_swsp_address_p (rtx x
, enum machine_mode mode
)
2577 struct mips_address_info addr
;
2579 return (mips_classify_address (&addr
, x
, mode
, false)
2580 && addr
.type
== ADDRESS_REG
2581 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2582 && uw5_operand (addr
.offset
, mode
));
2585 /* Return true if X is a legitimate address with a 12-bit offset.
2586 MODE is the mode of the value being accessed. */
2589 umips_12bit_offset_address_p (rtx x
, enum machine_mode mode
)
2591 struct mips_address_info addr
;
2593 return (mips_classify_address (&addr
, x
, mode
, false)
2594 && addr
.type
== ADDRESS_REG
2595 && CONST_INT_P (addr
.offset
)
2596 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2599 /* Return the number of instructions needed to load constant X,
2600 assuming that BASE_INSN_LENGTH is the length of one instruction.
2601 Return 0 if X isn't a valid constant. */
2604 mips_const_insns (rtx x
)
2606 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2607 enum mips_symbol_type symbol_type
;
2610 switch (GET_CODE (x
))
2613 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2615 || !mips_split_p
[symbol_type
])
2618 /* This is simply an LUI for normal mode. It is an extended
2619 LI followed by an extended SLL for MIPS16. */
2620 return TARGET_MIPS16
? 4 : 1;
2624 /* Unsigned 8-bit constants can be loaded using an unextended
2625 LI instruction. Unsigned 16-bit constants can be loaded
2626 using an extended LI. Negative constants must be loaded
2627 using LI and then negated. */
2628 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2629 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2630 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2631 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2634 return mips_build_integer (codes
, INTVAL (x
));
2638 /* Allow zeros for normal mode, where we can use $0. */
2639 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2645 /* See if we can refer to X directly. */
2646 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2647 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2649 /* Otherwise try splitting the constant into a base and offset.
2650 If the offset is a 16-bit value, we can load the base address
2651 into a register and then use (D)ADDIU to add in the offset.
2652 If the offset is larger, we can load the base and offset
2653 into separate registers and add them together with (D)ADDU.
2654 However, the latter is only possible before reload; during
2655 and after reload, we must have the option of forcing the
2656 constant into the pool instead. */
2657 split_const (x
, &x
, &offset
);
2660 int n
= mips_const_insns (x
);
2663 if (SMALL_INT (offset
))
2665 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2666 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2673 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2681 /* X is a doubleword constant that can be handled by splitting it into
2682 two words and loading each word separately. Return the number of
2683 instructions required to do this, assuming that BASE_INSN_LENGTH
2684 is the length of one instruction. */
2687 mips_split_const_insns (rtx x
)
2689 unsigned int low
, high
;
2691 low
= mips_const_insns (mips_subword (x
, false));
2692 high
= mips_const_insns (mips_subword (x
, true));
2693 gcc_assert (low
> 0 && high
> 0);
2697 /* Return the number of instructions needed to implement INSN,
2698 given that it loads from or stores to MEM. Assume that
2699 BASE_INSN_LENGTH is the length of one instruction. */
2702 mips_load_store_insns (rtx mem
, rtx insn
)
2704 enum machine_mode mode
;
2708 gcc_assert (MEM_P (mem
));
2709 mode
= GET_MODE (mem
);
2711 /* Try to prove that INSN does not need to be split. */
2712 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2715 set
= single_set (insn
);
2716 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2717 might_split_p
= false;
2720 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2723 /* Return the number of instructions needed for an integer division,
2724 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2727 mips_idiv_insns (void)
2732 if (TARGET_CHECK_ZERO_DIV
)
2734 if (GENERATE_DIVIDE_TRAPS
)
2740 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2745 /* Emit a move from SRC to DEST. Assume that the move expanders can
2746 handle all moves if !can_create_pseudo_p (). The distinction is
2747 important because, unlike emit_move_insn, the move expanders know
2748 how to force Pmode objects into the constant pool even when the
2749 constant pool address is not itself legitimate. */
2752 mips_emit_move (rtx dest
, rtx src
)
2754 return (can_create_pseudo_p ()
2755 ? emit_move_insn (dest
, src
)
2756 : emit_move_insn_1 (dest
, src
));
2759 /* Emit a move from SRC to DEST, splitting compound moves into individual
2760 instructions. SPLIT_TYPE is the type of split to perform. */
2763 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
2765 if (mips_split_move_p (dest
, src
, split_type
))
2766 mips_split_move (dest
, src
, split_type
);
2768 mips_emit_move (dest
, src
);
2771 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2774 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2776 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2777 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2780 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2781 Return that new register. */
2784 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2788 reg
= gen_reg_rtx (mode
);
2789 mips_emit_unary (code
, reg
, op0
);
2793 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2796 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2798 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2799 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2802 /* Compute (CODE OP0 OP1) and store the result in a new register
2803 of mode MODE. Return that new register. */
2806 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2810 reg
= gen_reg_rtx (mode
);
2811 mips_emit_binary (code
, reg
, op0
, op1
);
2815 /* Copy VALUE to a register and return that register. If new pseudos
2816 are allowed, copy it into a new register, otherwise use DEST. */
2819 mips_force_temporary (rtx dest
, rtx value
)
2821 if (can_create_pseudo_p ())
2822 return force_reg (Pmode
, value
);
2825 mips_emit_move (dest
, value
);
2830 /* Emit a call sequence with call pattern PATTERN and return the call
2831 instruction itself (which is not necessarily the last instruction
2832 emitted). ORIG_ADDR is the original, unlegitimized address,
2833 ADDR is the legitimized form, and LAZY_P is true if the call
2834 address is lazily-bound. */
2837 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2841 insn
= emit_call_insn (pattern
);
2843 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2845 /* MIPS16 JALRs only take MIPS16 registers. If the target
2846 function requires $25 to be valid on entry, we must copy it
2847 there separately. The move instruction can be put in the
2848 call's delay slot. */
2849 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2850 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2851 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2855 /* Lazy-binding stubs require $gp to be valid on entry. */
2856 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2860 /* See the comment above load_call<mode> for details. */
2861 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2862 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2863 emit_insn (gen_update_got_version ());
2867 && TARGET_EXPLICIT_RELOCS
2868 && TARGET_CALL_CLOBBERED_GP
)
2870 rtx post_call_tmp_reg
= gen_rtx_REG (word_mode
, POST_CALL_TMP_REG
);
2871 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn
), post_call_tmp_reg
);
2877 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2878 then add CONST_INT OFFSET to the result. */
2881 mips_unspec_address_offset (rtx base
, rtx offset
,
2882 enum mips_symbol_type symbol_type
)
2884 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2885 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2886 if (offset
!= const0_rtx
)
2887 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2888 return gen_rtx_CONST (Pmode
, base
);
2891 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2892 type SYMBOL_TYPE. */
2895 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2899 split_const (address
, &base
, &offset
);
2900 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2903 /* If OP is an UNSPEC address, return the address to which it refers,
2904 otherwise return OP itself. */
2907 mips_strip_unspec_address (rtx op
)
2911 split_const (op
, &base
, &offset
);
2912 if (UNSPEC_ADDRESS_P (base
))
2913 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2917 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2918 high part to BASE and return the result. Just return BASE otherwise.
2919 TEMP is as for mips_force_temporary.
2921 The returned expression can be used as the first operand to a LO_SUM. */
2924 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2925 enum mips_symbol_type symbol_type
)
2927 if (mips_split_p
[symbol_type
])
2929 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2930 addr
= mips_force_temporary (temp
, addr
);
2931 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2936 /* Return an instruction that copies $gp into register REG. We want
2937 GCC to treat the register's value as constant, so that its value
2938 can be rematerialized on demand. */
2941 gen_load_const_gp (rtx reg
)
2943 return PMODE_INSN (gen_load_const_gp
, (reg
));
2946 /* Return a pseudo register that contains the value of $gp throughout
2947 the current function. Such registers are needed by MIPS16 functions,
2948 for which $gp itself is not a valid base register or addition operand. */
2951 mips16_gp_pseudo_reg (void)
2953 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2957 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2959 push_topmost_sequence ();
2961 scan
= get_insns ();
2962 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2963 scan
= NEXT_INSN (scan
);
2965 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2966 insn
= emit_insn_after (insn
, scan
);
2967 INSN_LOCATION (insn
) = 0;
2969 pop_topmost_sequence ();
2972 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2975 /* Return a base register that holds pic_offset_table_rtx.
2976 TEMP, if nonnull, is a scratch Pmode base register. */
2979 mips_pic_base_register (rtx temp
)
2982 return pic_offset_table_rtx
;
2984 if (currently_expanding_to_rtl
)
2985 return mips16_gp_pseudo_reg ();
2987 if (can_create_pseudo_p ())
2988 temp
= gen_reg_rtx (Pmode
);
2991 /* The first post-reload split exposes all references to $gp
2992 (both uses and definitions). All references must remain
2993 explicit after that point.
2995 It is safe to introduce uses of $gp at any time, so for
2996 simplicity, we do that before the split too. */
2997 mips_emit_move (temp
, pic_offset_table_rtx
);
2999 emit_insn (gen_load_const_gp (temp
));
3003 /* Return the RHS of a load_call<mode> insn. */
3006 mips_unspec_call (rtx reg
, rtx symbol
)
3010 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
3011 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
3014 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
3015 reference. Return NULL_RTX otherwise. */
3018 mips_strip_unspec_call (rtx src
)
3020 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
3021 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
3025 /* Create and return a GOT reference of type TYPE for address ADDR.
3026 TEMP, if nonnull, is a scratch Pmode base register. */
3029 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
3031 rtx base
, high
, lo_sum_symbol
;
3033 base
= mips_pic_base_register (temp
);
3035 /* If we used the temporary register to load $gp, we can't use
3036 it for the high part as well. */
3037 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
3040 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
3041 lo_sum_symbol
= mips_unspec_address (addr
, type
);
3043 if (type
== SYMBOL_GOTOFF_CALL
)
3044 return mips_unspec_call (high
, lo_sum_symbol
);
3046 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
3049 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3050 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3051 constant in that context and can be split into high and low parts.
3052 If so, and if LOW_OUT is nonnull, emit the high part and store the
3053 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3055 TEMP is as for mips_force_temporary and is used to load the high
3056 part into a register.
3058 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3059 a legitimize SET_SRC for an .md pattern, otherwise the low part
3060 is guaranteed to be a legitimate address for mode MODE. */
3063 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
3065 enum mips_symbol_context context
;
3066 enum mips_symbol_type symbol_type
;
3069 context
= (mode
== MAX_MACHINE_MODE
3070 ? SYMBOL_CONTEXT_LEA
3071 : SYMBOL_CONTEXT_MEM
);
3072 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
3074 addr
= XEXP (addr
, 0);
3075 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3076 && mips_symbol_insns (symbol_type
, mode
) > 0
3077 && mips_split_hi_p
[symbol_type
])
3080 switch (symbol_type
)
3082 case SYMBOL_GOT_PAGE_OFST
:
3083 /* The high part of a page/ofst pair is loaded from the GOT. */
3084 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
3095 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3096 && mips_symbol_insns (symbol_type
, mode
) > 0
3097 && mips_split_p
[symbol_type
])
3100 switch (symbol_type
)
3102 case SYMBOL_GOT_DISP
:
3103 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3104 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
3107 case SYMBOL_GP_RELATIVE
:
3108 high
= mips_pic_base_register (temp
);
3109 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3113 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
3114 high
= mips_force_temporary (temp
, high
);
3115 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3124 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3125 mips_force_temporary; it is only needed when OFFSET is not a
3129 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
3131 if (!SMALL_OPERAND (offset
))
3137 /* Load the full offset into a register so that we can use
3138 an unextended instruction for the address itself. */
3139 high
= GEN_INT (offset
);
3144 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3145 The addition inside the macro CONST_HIGH_PART may cause an
3146 overflow, so we need to force a sign-extension check. */
3147 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
3148 offset
= CONST_LOW_PART (offset
);
3150 high
= mips_force_temporary (temp
, high
);
3151 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
3153 return plus_constant (Pmode
, reg
, offset
);
3156 /* The __tls_get_attr symbol. */
3157 static GTY(()) rtx mips_tls_symbol
;
3159 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3160 the TLS symbol we are referencing and TYPE is the symbol type to use
3161 (either global dynamic or local dynamic). V0 is an RTX for the
3162 return value location. */
3165 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3169 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3171 if (!mips_tls_symbol
)
3172 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3174 loc
= mips_unspec_address (sym
, type
);
3178 emit_insn (gen_rtx_SET (Pmode
, a0
,
3179 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
3180 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3181 const0_rtx
, NULL_RTX
, false);
3182 RTL_CONST_CALL_P (insn
) = 1;
3183 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3184 insn
= get_insns ();
3191 /* Return a pseudo register that contains the current thread pointer. */
3194 mips_expand_thread_pointer (rtx tp
)
3200 if (!mips16_rdhwr_stub
)
3201 mips16_rdhwr_stub
= new mips16_rdhwr_one_only_stub ();
3202 fn
= mips16_stub_call_address (mips16_rdhwr_stub
);
3203 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3206 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3213 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3216 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3217 its address. The return value will be both a valid address and a valid
3218 SET_SRC (either a REG or a LO_SUM). */
3221 mips_legitimize_tls_address (rtx loc
)
3223 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3224 enum tls_model model
;
3226 model
= SYMBOL_REF_TLS_MODEL (loc
);
3227 /* Only TARGET_ABICALLS code can have more than one module; other
3228 code must be be static and should not use a GOT. All TLS models
3229 reduce to local exec in this situation. */
3230 if (!TARGET_ABICALLS
)
3231 model
= TLS_MODEL_LOCAL_EXEC
;
3235 case TLS_MODEL_GLOBAL_DYNAMIC
:
3236 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3237 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3238 dest
= gen_reg_rtx (Pmode
);
3239 emit_libcall_block (insn
, dest
, v0
, loc
);
3242 case TLS_MODEL_LOCAL_DYNAMIC
:
3243 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3244 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3245 tmp1
= gen_reg_rtx (Pmode
);
3247 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3248 share the LDM result with other LD model accesses. */
3249 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3251 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3253 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3254 if (mips_split_p
[SYMBOL_DTPREL
])
3256 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3257 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3260 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3261 0, 0, OPTAB_DIRECT
);
3264 case TLS_MODEL_INITIAL_EXEC
:
3265 tp
= mips_get_tp ();
3266 tmp1
= gen_reg_rtx (Pmode
);
3267 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3268 if (Pmode
== DImode
)
3269 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3271 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3272 dest
= gen_reg_rtx (Pmode
);
3273 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3276 case TLS_MODEL_LOCAL_EXEC
:
3277 tmp1
= mips_get_tp ();
3278 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3279 if (mips_split_p
[SYMBOL_TPREL
])
3281 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3282 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3285 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3286 0, 0, OPTAB_DIRECT
);
3295 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3299 mips16_expand_get_fcsr (rtx target
)
3301 if (!mips16_get_fcsr_stub
)
3302 mips16_get_fcsr_stub
= new mips16_get_fcsr_one_only_stub ();
3303 rtx fn
= mips16_stub_call_address (mips16_get_fcsr_stub
);
3304 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16
, (fn
)));
3305 emit_move_insn (target
, gen_rtx_REG (SImode
, GET_FCSR_REGNUM
));
3308 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3311 mips16_expand_set_fcsr (rtx newval
)
3313 if (!mips16_set_fcsr_stub
)
3314 mips16_set_fcsr_stub
= new mips16_set_fcsr_one_only_stub ();
3315 rtx fn
= mips16_stub_call_address (mips16_set_fcsr_stub
);
3316 emit_move_insn (gen_rtx_REG (SImode
, SET_FCSR_REGNUM
), newval
);
3317 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16
, (fn
)));
3320 /* If X is not a valid address for mode MODE, force it into a register. */
3323 mips_force_address (rtx x
, enum machine_mode mode
)
3325 if (!mips_legitimate_address_p (mode
, x
, false))
3326 x
= force_reg (Pmode
, x
);
3330 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3331 be legitimized in a way that the generic machinery might not expect,
3332 return a new address, otherwise return NULL. MODE is the mode of
3333 the memory being accessed. */
3336 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3337 enum machine_mode mode
)
3340 HOST_WIDE_INT offset
;
3342 if (mips_tls_symbol_p (x
))
3343 return mips_legitimize_tls_address (x
);
3345 /* See if the address can split into a high part and a LO_SUM. */
3346 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3347 return mips_force_address (addr
, mode
);
3349 /* Handle BASE + OFFSET using mips_add_offset. */
3350 mips_split_plus (x
, &base
, &offset
);
3353 if (!mips_valid_base_register_p (base
, mode
, false))
3354 base
= copy_to_mode_reg (Pmode
, base
);
3355 addr
= mips_add_offset (NULL
, base
, offset
);
3356 return mips_force_address (addr
, mode
);
3362 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3365 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3367 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3368 enum machine_mode mode
;
3369 unsigned int i
, num_ops
;
3372 mode
= GET_MODE (dest
);
3373 num_ops
= mips_build_integer (codes
, value
);
3375 /* Apply each binary operation to X. Invariant: X is a legitimate
3376 source operand for a SET pattern. */
3377 x
= GEN_INT (codes
[0].value
);
3378 for (i
= 1; i
< num_ops
; i
++)
3380 if (!can_create_pseudo_p ())
3382 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
3386 x
= force_reg (mode
, x
);
3387 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3390 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
3393 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3394 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3398 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
3402 /* Split moves of big integers into smaller pieces. */
3403 if (splittable_const_int_operand (src
, mode
))
3405 mips_move_integer (dest
, dest
, INTVAL (src
));
3409 /* Split moves of symbolic constants into high/low pairs. */
3410 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3412 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3416 /* Generate the appropriate access sequences for TLS symbols. */
3417 if (mips_tls_symbol_p (src
))
3419 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3423 /* If we have (const (plus symbol offset)), and that expression cannot
3424 be forced into memory, load the symbol first and add in the offset.
3425 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3426 forced into memory, as it usually produces better code. */
3427 split_const (src
, &base
, &offset
);
3428 if (offset
!= const0_rtx
3429 && (targetm
.cannot_force_const_mem (mode
, src
)
3430 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3432 base
= mips_force_temporary (dest
, base
);
3433 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3437 src
= force_const_mem (mode
, src
);
3439 /* When using explicit relocs, constant pool references are sometimes
3440 not legitimate addresses. */
3441 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3442 mips_emit_move (dest
, src
);
3445 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3446 sequence that is valid. */
3449 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
3451 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3453 mips_emit_move (dest
, force_reg (mode
, src
));
3457 /* We need to deal with constants that would be legitimate
3458 immediate_operands but aren't legitimate move_operands. */
3459 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3461 mips_legitimize_const_move (mode
, dest
, src
);
3462 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3468 /* Return true if value X in context CONTEXT is a small-data address
3469 that can be rewritten as a LO_SUM. */
3472 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3474 enum mips_symbol_type symbol_type
;
3476 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3477 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3478 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3479 && symbol_type
== SYMBOL_GP_RELATIVE
);
3482 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3483 containing MEM, or null if none. */
3486 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3488 enum mips_symbol_context context
;
3490 /* Ignore things like "g" constraints in asms. We make no particular
3491 guarantee about which symbolic constants are acceptable as asm operands
3492 versus which must be forced into a GPR. */
3493 if (GET_CODE (*loc
) == LO_SUM
|| GET_CODE (*loc
) == ASM_OPERANDS
)
3498 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3503 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3504 return mips_rewrite_small_data_p (*loc
, context
);
3507 /* Return true if OP refers to small data symbols directly, not through
3511 mips_small_data_pattern_p (rtx op
)
3513 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3516 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3517 DATA is the containing MEM, or null if none. */
3520 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3522 enum mips_symbol_context context
;
3526 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3530 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3531 if (mips_rewrite_small_data_p (*loc
, context
))
3532 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3534 if (GET_CODE (*loc
) == LO_SUM
)
3540 /* Rewrite instruction pattern PATTERN so that it refers to small data
3541 using explicit relocations. */
3544 mips_rewrite_small_data (rtx pattern
)
3546 pattern
= copy_insn (pattern
);
3547 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3551 /* The cost of loading values from the constant pool. It should be
3552 larger than the cost of any constant we want to synthesize inline. */
3553 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3555 /* Return the cost of X when used as an operand to the MIPS16 instruction
3556 that implements CODE. Return -1 if there is no such instruction, or if
3557 X is not a valid immediate operand for it. */
3560 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3567 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3568 other shifts are extended. The shift patterns truncate the shift
3569 count to the right size, so there are no out-of-range values. */
3570 if (IN_RANGE (x
, 1, 8))
3572 return COSTS_N_INSNS (1);
3575 if (IN_RANGE (x
, -128, 127))
3577 if (SMALL_OPERAND (x
))
3578 return COSTS_N_INSNS (1);
3582 /* Like LE, but reject the always-true case. */
3586 /* We add 1 to the immediate and use SLT. */
3589 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3592 if (IN_RANGE (x
, 0, 255))
3594 if (SMALL_OPERAND_UNSIGNED (x
))
3595 return COSTS_N_INSNS (1);
3600 /* Equality comparisons with 0 are cheap. */
3610 /* Return true if there is a non-MIPS16 instruction that implements CODE
3611 and if that instruction accepts X as an immediate operand. */
3614 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3621 /* All shift counts are truncated to a valid constant. */
3626 /* Likewise rotates, if the target supports rotates at all. */
3632 /* These instructions take 16-bit unsigned immediates. */
3633 return SMALL_OPERAND_UNSIGNED (x
);
3638 /* These instructions take 16-bit signed immediates. */
3639 return SMALL_OPERAND (x
);
3645 /* The "immediate" forms of these instructions are really
3646 implemented as comparisons with register 0. */
3651 /* Likewise, meaning that the only valid immediate operand is 1. */
3655 /* We add 1 to the immediate and use SLT. */
3656 return SMALL_OPERAND (x
+ 1);
3659 /* Likewise SLTU, but reject the always-true case. */
3660 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3664 /* The bit position and size are immediate operands. */
3665 return ISA_HAS_EXT_INS
;
3668 /* By default assume that $0 can be used for 0. */
3673 /* Return the cost of binary operation X, given that the instruction
3674 sequence for a word-sized or smaller operation has cost SINGLE_COST
3675 and that the sequence of a double-word operation has cost DOUBLE_COST.
3676 If SPEED is true, optimize for speed otherwise optimize for size. */
3679 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3683 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3688 + set_src_cost (XEXP (x
, 0), speed
)
3689 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3692 /* Return the cost of floating-point multiplications of mode MODE. */
3695 mips_fp_mult_cost (enum machine_mode mode
)
3697 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3700 /* Return the cost of floating-point divisions of mode MODE. */
3703 mips_fp_div_cost (enum machine_mode mode
)
3705 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3708 /* Return the cost of sign-extending OP to mode MODE, not including the
3709 cost of OP itself. */
3712 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3715 /* Extended loads are as cheap as unextended ones. */
3718 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3719 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3722 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3723 /* We can use SEB or SEH. */
3724 return COSTS_N_INSNS (1);
3726 /* We need to use a shift left and a shift right. */
3727 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3730 /* Return the cost of zero-extending OP to mode MODE, not including the
3731 cost of OP itself. */
3734 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3737 /* Extended loads are as cheap as unextended ones. */
3740 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3741 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3742 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3744 if (GENERATE_MIPS16E
)
3745 /* We can use ZEB or ZEH. */
3746 return COSTS_N_INSNS (1);
3749 /* We need to load 0xff or 0xffff into a register and use AND. */
3750 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3752 /* We can use ANDI. */
3753 return COSTS_N_INSNS (1);
3756 /* Return the cost of moving between two registers of mode MODE,
3757 assuming that the move will be in pieces of at most UNITS bytes. */
3760 mips_set_reg_reg_piece_cost (enum machine_mode mode
, unsigned int units
)
3762 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3765 /* Return the cost of moving between two registers of mode MODE. */
3768 mips_set_reg_reg_cost (enum machine_mode mode
)
3770 switch (GET_MODE_CLASS (mode
))
3773 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3776 case MODE_COMPLEX_FLOAT
:
3777 case MODE_VECTOR_FLOAT
:
3778 if (TARGET_HARD_FLOAT
)
3779 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3783 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3787 /* Implement TARGET_RTX_COSTS. */
3790 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3791 int *total
, bool speed
)
3793 enum machine_mode mode
= GET_MODE (x
);
3794 bool float_mode_p
= FLOAT_MODE_P (mode
);
3798 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3799 appear in the instruction stream, and the cost of a comparison is
3800 really the cost of the branch or scc condition. At the time of
3801 writing, GCC only uses an explicit outer COMPARE code when optabs
3802 is testing whether a constant is expensive enough to force into a
3803 register. We want optabs to pass such constants through the MIPS
3804 expanders instead, so make all constants very cheap here. */
3805 if (outer_code
== COMPARE
)
3807 gcc_assert (CONSTANT_P (x
));
3815 /* Treat *clear_upper32-style ANDs as having zero cost in the
3816 second operand. The cost is entirely in the first operand.
3818 ??? This is needed because we would otherwise try to CSE
3819 the constant operand. Although that's the right thing for
3820 instructions that continue to be a register operation throughout
3821 compilation, it is disastrous for instructions that could
3822 later be converted into a memory operation. */
3824 && outer_code
== AND
3825 && UINTVAL (x
) == 0xffffffff)
3833 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3842 /* When not optimizing for size, we care more about the cost
3843 of hot code, and hot code is often in a loop. If a constant
3844 operand needs to be forced into a register, we will often be
3845 able to hoist the constant load out of the loop, so the load
3846 should not contribute to the cost. */
3847 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3859 if (force_to_mem_operand (x
, VOIDmode
))
3861 *total
= COSTS_N_INSNS (1);
3864 cost
= mips_const_insns (x
);
3867 /* If the constant is likely to be stored in a GPR, SETs of
3868 single-insn constants are as cheap as register sets; we
3869 never want to CSE them.
3871 Don't reduce the cost of storing a floating-point zero in
3872 FPRs. If we have a zero in an FPR for other reasons, we
3873 can get better cfg-cleanup and delayed-branch results by
3874 using it consistently, rather than using $0 sometimes and
3875 an FPR at other times. Also, moves between floating-point
3876 registers are sometimes cheaper than (D)MTC1 $0. */
3878 && outer_code
== SET
3879 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3881 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3882 want to CSE the constant itself. It is usually better to
3883 have N copies of the last operation in the sequence and one
3884 shared copy of the other operations. (Note that this is
3885 not true for MIPS16 code, where the final operation in the
3886 sequence is often an extended instruction.)
3888 Also, if we have a CONST_INT, we don't know whether it is
3889 for a word or doubleword operation, so we cannot rely on
3890 the result of mips_build_integer. */
3891 else if (!TARGET_MIPS16
3892 && (outer_code
== SET
|| mode
== VOIDmode
))
3894 *total
= COSTS_N_INSNS (cost
);
3897 /* The value will need to be fetched from the constant pool. */
3898 *total
= CONSTANT_POOL_COST
;
3902 /* If the address is legitimate, return the number of
3903 instructions it needs. */
3905 cost
= mips_address_insns (addr
, mode
, true);
3908 *total
= COSTS_N_INSNS (cost
+ 1);
3911 /* Check for a scaled indexed address. */
3912 if (mips_lwxs_address_p (addr
)
3913 || mips_lx_address_p (addr
, mode
))
3915 *total
= COSTS_N_INSNS (2);
3918 /* Otherwise use the default handling. */
3922 *total
= COSTS_N_INSNS (6);
3926 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3930 /* Check for a *clear_upper32 pattern and treat it like a zero
3931 extension. See the pattern's comment for details. */
3934 && CONST_INT_P (XEXP (x
, 1))
3935 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3937 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3938 + set_src_cost (XEXP (x
, 0), speed
));
3941 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
3943 rtx op
= XEXP (x
, 0);
3944 if (GET_CODE (op
) == ASHIFT
3945 && CONST_INT_P (XEXP (op
, 1))
3946 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
3948 *total
= COSTS_N_INSNS (1) + set_src_cost (XEXP (op
, 0), speed
);
3952 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3953 a single instruction. */
3955 && GET_CODE (XEXP (x
, 0)) == NOT
3956 && GET_CODE (XEXP (x
, 1)) == NOT
)
3958 cost
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1;
3959 *total
= (COSTS_N_INSNS (cost
)
3960 + set_src_cost (XEXP (XEXP (x
, 0), 0), speed
)
3961 + set_src_cost (XEXP (XEXP (x
, 1), 0), speed
));
3969 /* Double-word operations use two single-word operations. */
3970 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3979 if (CONSTANT_P (XEXP (x
, 1)))
3980 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3983 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3989 *total
= mips_cost
->fp_add
;
3991 *total
= COSTS_N_INSNS (4);
3995 /* Low-part immediates need an extended MIPS16 instruction. */
3996 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3997 + set_src_cost (XEXP (x
, 0), speed
));
4012 /* Branch comparisons have VOIDmode, so use the first operand's
4014 mode
= GET_MODE (XEXP (x
, 0));
4015 if (FLOAT_MODE_P (mode
))
4017 *total
= mips_cost
->fp_add
;
4020 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4026 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
4027 && TARGET_FUSED_MADD
4028 && !HONOR_NANS (mode
)
4029 && !HONOR_SIGNED_ZEROS (mode
))
4031 /* See if we can use NMADD or NMSUB. See mips.md for the
4032 associated patterns. */
4033 rtx op0
= XEXP (x
, 0);
4034 rtx op1
= XEXP (x
, 1);
4035 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
4037 *total
= (mips_fp_mult_cost (mode
)
4038 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
4039 + set_src_cost (XEXP (op0
, 1), speed
)
4040 + set_src_cost (op1
, speed
));
4043 if (GET_CODE (op1
) == MULT
)
4045 *total
= (mips_fp_mult_cost (mode
)
4046 + set_src_cost (op0
, speed
)
4047 + set_src_cost (XEXP (op1
, 0), speed
)
4048 + set_src_cost (XEXP (op1
, 1), speed
));
4057 /* If this is part of a MADD or MSUB, treat the PLUS as
4059 if ((ISA_HAS_FP_MADD4_MSUB4
|| ISA_HAS_FP_MADD3_MSUB3
)
4060 && TARGET_FUSED_MADD
4061 && GET_CODE (XEXP (x
, 0)) == MULT
)
4064 *total
= mips_cost
->fp_add
;
4068 /* Double-word operations require three single-word operations and
4069 an SLTU. The MIPS16 version then needs to move the result of
4070 the SLTU from $24 to a MIPS16 register. */
4071 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
4072 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
4078 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
4079 && TARGET_FUSED_MADD
4080 && !HONOR_NANS (mode
)
4081 && HONOR_SIGNED_ZEROS (mode
))
4083 /* See if we can use NMADD or NMSUB. See mips.md for the
4084 associated patterns. */
4085 rtx op
= XEXP (x
, 0);
4086 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
4087 && GET_CODE (XEXP (op
, 0)) == MULT
)
4089 *total
= (mips_fp_mult_cost (mode
)
4090 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
4091 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
4092 + set_src_cost (XEXP (op
, 1), speed
));
4098 *total
= mips_cost
->fp_add
;
4100 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
4105 *total
= mips_fp_mult_cost (mode
);
4106 else if (mode
== DImode
&& !TARGET_64BIT
)
4107 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4108 where the mulsidi3 always includes an MFHI and an MFLO. */
4110 ? mips_cost
->int_mult_si
* 3 + 6
4111 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
4113 *total
= COSTS_N_INSNS (ISA_HAS_MUL3
? 1 : 2) + 1;
4114 else if (mode
== DImode
)
4115 *total
= mips_cost
->int_mult_di
;
4117 *total
= mips_cost
->int_mult_si
;
4121 /* Check for a reciprocal. */
4123 && ISA_HAS_FP_RECIP_RSQRT (mode
)
4124 && flag_unsafe_math_optimizations
4125 && XEXP (x
, 0) == CONST1_RTX (mode
))
4127 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
4128 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4129 division as being free. */
4130 *total
= set_src_cost (XEXP (x
, 1), speed
);
4132 *total
= (mips_fp_div_cost (mode
)
4133 + set_src_cost (XEXP (x
, 1), speed
));
4142 *total
= mips_fp_div_cost (mode
);
4151 /* It is our responsibility to make division by a power of 2
4152 as cheap as 2 register additions if we want the division
4153 expanders to be used for such operations; see the setting
4154 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4155 should always produce shorter code than using
4156 expand_sdiv2_pow2. */
4158 && CONST_INT_P (XEXP (x
, 1))
4159 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
4161 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
4164 *total
= COSTS_N_INSNS (mips_idiv_insns ());
4166 else if (mode
== DImode
)
4167 *total
= mips_cost
->int_div_di
;
4169 *total
= mips_cost
->int_div_si
;
4173 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
4177 if (outer_code
== SET
4179 && (GET_CODE (XEXP (x
, 0)) == TRUNCATE
4180 || GET_CODE (XEXP (x
, 0)) == SUBREG
)
4181 && GET_MODE (XEXP (x
, 0)) == QImode
4182 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4184 *total
= set_src_cost (XEXP (XEXP (x
, 0), 0), speed
);
4187 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4191 case UNSIGNED_FLOAT
:
4194 case FLOAT_TRUNCATE
:
4195 *total
= mips_cost
->fp_add
;
4199 if (register_operand (SET_DEST (x
), VOIDmode
)
4200 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4202 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4212 /* Implement TARGET_ADDRESS_COST. */
4215 mips_address_cost (rtx addr
, enum machine_mode mode
,
4216 addr_space_t as ATTRIBUTE_UNUSED
,
4217 bool speed ATTRIBUTE_UNUSED
)
4219 return mips_address_insns (addr
, mode
, false);
4222 /* Information about a single instruction in a multi-instruction
4224 struct mips_multi_member
{
4225 /* True if this is a label, false if it is code. */
4228 /* The output_asm_insn format of the instruction. */
4231 /* The operands to the instruction. */
4232 rtx operands
[MAX_RECOG_OPERANDS
];
4234 typedef struct mips_multi_member mips_multi_member
;
4236 /* The instructions that make up the current multi-insn sequence. */
4237 static vec
<mips_multi_member
> mips_multi_members
;
4239 /* How many instructions (as opposed to labels) are in the current
4240 multi-insn sequence. */
4241 static unsigned int mips_multi_num_insns
;
4243 /* Start a new multi-insn sequence. */
4246 mips_multi_start (void)
4248 mips_multi_members
.truncate (0);
4249 mips_multi_num_insns
= 0;
4252 /* Add a new, uninitialized member to the current multi-insn sequence. */
4254 static struct mips_multi_member
*
4255 mips_multi_add (void)
4257 mips_multi_member empty
;
4258 return mips_multi_members
.safe_push (empty
);
4261 /* Add a normal insn with the given asm format to the current multi-insn
4262 sequence. The other arguments are a null-terminated list of operands. */
4265 mips_multi_add_insn (const char *format
, ...)
4267 struct mips_multi_member
*member
;
4272 member
= mips_multi_add ();
4273 member
->is_label_p
= false;
4274 member
->format
= format
;
4275 va_start (ap
, format
);
4277 while ((op
= va_arg (ap
, rtx
)))
4278 member
->operands
[i
++] = op
;
4280 mips_multi_num_insns
++;
4283 /* Add the given label definition to the current multi-insn sequence.
4284 The definition should include the colon. */
4287 mips_multi_add_label (const char *label
)
4289 struct mips_multi_member
*member
;
4291 member
= mips_multi_add ();
4292 member
->is_label_p
= true;
4293 member
->format
= label
;
4296 /* Return the index of the last member of the current multi-insn sequence. */
4299 mips_multi_last_index (void)
4301 return mips_multi_members
.length () - 1;
4304 /* Add a copy of an existing instruction to the current multi-insn
4305 sequence. I is the index of the instruction that should be copied. */
4308 mips_multi_copy_insn (unsigned int i
)
4310 struct mips_multi_member
*member
;
4312 member
= mips_multi_add ();
4313 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4314 gcc_assert (!member
->is_label_p
);
4317 /* Change the operand of an existing instruction in the current
4318 multi-insn sequence. I is the index of the instruction,
4319 OP is the index of the operand, and X is the new value. */
4322 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4324 mips_multi_members
[i
].operands
[op
] = x
;
4327 /* Write out the asm code for the current multi-insn sequence. */
4330 mips_multi_write (void)
4332 struct mips_multi_member
*member
;
4335 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4336 if (member
->is_label_p
)
4337 fprintf (asm_out_file
, "%s\n", member
->format
);
4339 output_asm_insn (member
->format
, member
->operands
);
4342 /* Return one word of double-word value OP, taking into account the fixed
4343 endianness of certain registers. HIGH_P is true to select the high part,
4344 false to select the low part. */
4347 mips_subword (rtx op
, bool high_p
)
4349 unsigned int byte
, offset
;
4350 enum machine_mode mode
;
4352 mode
= GET_MODE (op
);
4353 if (mode
== VOIDmode
)
4354 mode
= TARGET_64BIT
? TImode
: DImode
;
4356 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4357 byte
= UNITS_PER_WORD
;
4361 if (FP_REG_RTX_P (op
))
4363 /* Paired FPRs are always ordered little-endian. */
4364 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4365 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4369 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4371 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4374 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4375 SPLIT_TYPE is the condition under which moves should be split. */
4378 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4380 return ((split_type
!= SPLIT_FOR_SPEED
4381 || mips_tuning_info
.fast_mult_zero_zero_p
)
4382 && src
== const0_rtx
4384 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4385 && (ISA_HAS_DSP_MULT
4386 ? ACC_REG_P (REGNO (dest
))
4387 : MD_REG_P (REGNO (dest
))));
4390 /* Return true if a move from SRC to DEST should be split into two.
4391 SPLIT_TYPE describes the split condition. */
4394 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4396 /* Check whether the move can be done using some variant of MULT $0,$0. */
4397 if (mips_mult_move_p (dest
, src
, split_type
))
4400 /* FPR-to-FPR moves can be done in a single instruction, if they're
4402 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4403 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4406 /* Check for floating-point loads and stores. */
4407 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4409 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4411 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4415 /* Otherwise split all multiword moves. */
4416 return size
> UNITS_PER_WORD
;
4419 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4420 SPLIT_TYPE describes the split condition. */
4423 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4427 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4428 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4430 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4431 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4432 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4433 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4434 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4435 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4436 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4437 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4438 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4439 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4440 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4441 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4442 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4443 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4447 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4449 low_dest
= mips_subword (dest
, false);
4450 mips_emit_move (low_dest
, mips_subword (src
, false));
4452 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4454 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4456 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4458 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4460 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4462 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4466 /* The operation can be split into two normal moves. Decide in
4467 which order to do them. */
4468 low_dest
= mips_subword (dest
, false);
4469 if (REG_P (low_dest
)
4470 && reg_overlap_mentioned_p (low_dest
, src
))
4472 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4473 mips_emit_move (low_dest
, mips_subword (src
, false));
4477 mips_emit_move (low_dest
, mips_subword (src
, false));
4478 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4483 /* Return the split type for instruction INSN. */
4485 static enum mips_split_type
4486 mips_insn_split_type (rtx insn
)
4488 basic_block bb
= BLOCK_FOR_INSN (insn
);
4491 if (optimize_bb_for_speed_p (bb
))
4492 return SPLIT_FOR_SPEED
;
4494 return SPLIT_FOR_SIZE
;
4496 /* Once CFG information has been removed, we should trust the optimization
4497 decisions made by previous passes and only split where necessary. */
4498 return SPLIT_IF_NECESSARY
;
4501 /* Return true if a move from SRC to DEST in INSN should be split. */
4504 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
4506 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
4509 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4513 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
4515 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
4518 /* Return the appropriate instructions to move SRC into DEST. Assume
4519 that SRC is operand 1 and DEST is operand 0. */
4522 mips_output_move (rtx dest
, rtx src
)
4524 enum rtx_code dest_code
, src_code
;
4525 enum machine_mode mode
;
4526 enum mips_symbol_type symbol_type
;
4529 dest_code
= GET_CODE (dest
);
4530 src_code
= GET_CODE (src
);
4531 mode
= GET_MODE (dest
);
4532 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4534 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4537 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4538 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4540 if (dest_code
== REG
)
4542 if (GP_REG_P (REGNO (dest
)))
4543 return "move\t%0,%z1";
4545 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4547 if (ISA_HAS_DSP_MULT
)
4548 return "mult\t%q0,%.,%.";
4550 return "mult\t%.,%.";
4553 /* Moves to HI are handled by special .md insns. */
4554 if (REGNO (dest
) == LO_REGNUM
)
4557 if (DSP_ACC_REG_P (REGNO (dest
)))
4559 static char retval
[] = "mt__\t%z1,%q0";
4561 retval
[2] = reg_names
[REGNO (dest
)][4];
4562 retval
[3] = reg_names
[REGNO (dest
)][5];
4566 if (FP_REG_P (REGNO (dest
)))
4567 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4569 if (ALL_COP_REG_P (REGNO (dest
)))
4571 static char retval
[] = "dmtc_\t%z1,%0";
4573 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4574 return dbl_p
? retval
: retval
+ 1;
4577 if (dest_code
== MEM
)
4578 switch (GET_MODE_SIZE (mode
))
4580 case 1: return "sb\t%z1,%0";
4581 case 2: return "sh\t%z1,%0";
4582 case 4: return "sw\t%z1,%0";
4583 case 8: return "sd\t%z1,%0";
4586 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4588 if (src_code
== REG
)
4590 /* Moves from HI are handled by special .md insns. */
4591 if (REGNO (src
) == LO_REGNUM
)
4593 /* When generating VR4120 or VR4130 code, we use MACC and
4594 DMACC instead of MFLO. This avoids both the normal
4595 MIPS III HI/LO hazards and the errata related to
4598 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4602 if (DSP_ACC_REG_P (REGNO (src
)))
4604 static char retval
[] = "mf__\t%0,%q1";
4606 retval
[2] = reg_names
[REGNO (src
)][4];
4607 retval
[3] = reg_names
[REGNO (src
)][5];
4611 if (FP_REG_P (REGNO (src
)))
4612 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4614 if (ALL_COP_REG_P (REGNO (src
)))
4616 static char retval
[] = "dmfc_\t%0,%1";
4618 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4619 return dbl_p
? retval
: retval
+ 1;
4623 if (src_code
== MEM
)
4624 switch (GET_MODE_SIZE (mode
))
4626 case 1: return "lbu\t%0,%1";
4627 case 2: return "lhu\t%0,%1";
4628 case 4: return "lw\t%0,%1";
4629 case 8: return "ld\t%0,%1";
4632 if (src_code
== CONST_INT
)
4634 /* Don't use the X format for the operand itself, because that
4635 will give out-of-range numbers for 64-bit hosts and 32-bit
4638 return "li\t%0,%1\t\t\t# %X1";
4640 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4643 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4647 if (src_code
== HIGH
)
4648 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4650 if (CONST_GP_P (src
))
4651 return "move\t%0,%1";
4653 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4654 && mips_lo_relocs
[symbol_type
] != 0)
4656 /* A signed 16-bit constant formed by applying a relocation
4657 operator to a symbolic address. */
4658 gcc_assert (!mips_split_p
[symbol_type
]);
4659 return "li\t%0,%R1";
4662 if (symbolic_operand (src
, VOIDmode
))
4664 gcc_assert (TARGET_MIPS16
4665 ? TARGET_MIPS16_TEXT_LOADS
4666 : !TARGET_EXPLICIT_RELOCS
);
4667 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4670 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4672 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4674 if (GET_MODE (dest
) == V2SFmode
)
4675 return "mov.ps\t%0,%1";
4677 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4680 if (dest_code
== MEM
)
4681 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4683 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4685 if (src_code
== MEM
)
4686 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4688 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4690 static char retval
[] = "l_c_\t%0,%1";
4692 retval
[1] = (dbl_p
? 'd' : 'w');
4693 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4696 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4698 static char retval
[] = "s_c_\t%1,%0";
4700 retval
[1] = (dbl_p
? 'd' : 'w');
4701 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4707 /* Return true if CMP1 is a suitable second operand for integer ordering
4708 test CODE. See also the *sCC patterns in mips.md. */
4711 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4717 return reg_or_0_operand (cmp1
, VOIDmode
);
4721 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4725 return arith_operand (cmp1
, VOIDmode
);
4728 return sle_operand (cmp1
, VOIDmode
);
4731 return sleu_operand (cmp1
, VOIDmode
);
4738 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4739 integer ordering test *CODE, or if an equivalent combination can
4740 be formed by adjusting *CODE and *CMP1. When returning true, update
4741 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4745 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4746 enum machine_mode mode
)
4748 HOST_WIDE_INT plus_one
;
4750 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4753 if (CONST_INT_P (*cmp1
))
4757 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4758 if (INTVAL (*cmp1
) < plus_one
)
4761 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4767 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4771 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4782 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4783 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4784 is nonnull, it's OK to set TARGET to the inverse of the result and
4785 flip *INVERT_PTR instead. */
4788 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4789 rtx target
, rtx cmp0
, rtx cmp1
)
4791 enum machine_mode mode
;
4793 /* First see if there is a MIPS instruction that can do this operation.
4794 If not, try doing the same for the inverse operation. If that also
4795 fails, force CMP1 into a register and try again. */
4796 mode
= GET_MODE (cmp0
);
4797 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4798 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4801 enum rtx_code inv_code
= reverse_condition (code
);
4802 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4804 cmp1
= force_reg (mode
, cmp1
);
4805 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4807 else if (invert_ptr
== 0)
4811 inv_target
= mips_force_binary (GET_MODE (target
),
4812 inv_code
, cmp0
, cmp1
);
4813 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4817 *invert_ptr
= !*invert_ptr
;
4818 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4823 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4824 The register will have the same mode as CMP0. */
4827 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4829 if (cmp1
== const0_rtx
)
4832 if (uns_arith_operand (cmp1
, VOIDmode
))
4833 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4834 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4836 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4837 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4840 /* Convert *CODE into a code that can be used in a floating-point
4841 scc instruction (C.cond.fmt). Return true if the values of
4842 the condition code registers will be inverted, with 0 indicating
4843 that the condition holds. */
4846 mips_reversed_fp_cond (enum rtx_code
*code
)
4853 *code
= reverse_condition_maybe_unordered (*code
);
4861 /* Allocate a floating-point condition-code register of mode MODE.
4863 These condition code registers are used for certain kinds
4864 of compound operation, such as compare and branches, vconds,
4865 and built-in functions. At expand time, their use is entirely
4866 controlled by MIPS-specific code and is entirely internal
4867 to these compound operations.
4869 We could (and did in the past) expose condition-code values
4870 as pseudo registers and leave the register allocator to pick
4871 appropriate registers. The problem is that it is not practically
4872 possible for the rtl optimizers to guarantee that no spills will
4873 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4874 therefore need spill and reload sequences to handle the worst case.
4876 Although such sequences do exist, they are very expensive and are
4877 not something we'd want to use. This is especially true of CCV2 and
4878 CCV4, where all the shuffling would greatly outweigh whatever benefit
4879 the vectorization itself provides.
4881 The main benefit of having more than one condition-code register
4882 is to allow the pipelining of operations, especially those involving
4883 comparisons and conditional moves. We don't really expect the
4884 registers to be live for long periods, and certainly never want
4885 them to be live across calls.
4887 Also, there should be no penalty attached to using all the available
4888 registers. They are simply bits in the same underlying FPU control
4891 We therefore expose the hardware registers from the outset and use
4892 a simple round-robin allocation scheme. */
4895 mips_allocate_fcc (enum machine_mode mode
)
4897 unsigned int regno
, count
;
4899 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
4903 else if (mode
== CCV2mode
)
4905 else if (mode
== CCV4mode
)
4910 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
4911 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
4912 cfun
->machine
->next_fcc
= 0;
4913 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
4914 cfun
->machine
->next_fcc
+= count
;
4915 return gen_rtx_REG (mode
, regno
);
4918 /* Convert a comparison into something that can be used in a branch or
4919 conditional move. On entry, *OP0 and *OP1 are the values being
4920 compared and *CODE is the code used to compare them.
4922 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4923 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4924 otherwise any standard branch condition can be used. The standard branch
4927 - EQ or NE between two registers.
4928 - any comparison between a register and zero. */
4931 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4936 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4938 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4940 else if (*code
== EQ
|| *code
== NE
)
4944 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4948 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4952 /* The comparison needs a separate scc instruction. Store the
4953 result of the scc in *OP0 and compare it against zero. */
4954 bool invert
= false;
4955 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4956 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4957 *code
= (invert
? EQ
: NE
);
4961 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4963 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4964 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4970 enum rtx_code cmp_code
;
4972 /* Floating-point tests use a separate C.cond.fmt comparison to
4973 set a condition code register. The branch or conditional move
4974 will then compare that register against zero.
4976 Set CMP_CODE to the code of the comparison instruction and
4977 *CODE to the code that the branch or move should use. */
4979 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4981 ? mips_allocate_fcc (CCmode
)
4982 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4984 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4988 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4989 and OPERAND[3]. Store the result in OPERANDS[0].
4991 On 64-bit targets, the mode of the comparison and target will always be
4992 SImode, thus possibly narrower than that of the comparison's operands. */
4995 mips_expand_scc (rtx operands
[])
4997 rtx target
= operands
[0];
4998 enum rtx_code code
= GET_CODE (operands
[1]);
4999 rtx op0
= operands
[2];
5000 rtx op1
= operands
[3];
5002 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
5004 if (code
== EQ
|| code
== NE
)
5007 && reg_imm10_operand (op1
, GET_MODE (op1
)))
5008 mips_emit_binary (code
, target
, op0
, op1
);
5011 rtx zie
= mips_zero_if_equal (op0
, op1
);
5012 mips_emit_binary (code
, target
, zie
, const0_rtx
);
5016 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
5019 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
5020 CODE and jump to OPERANDS[3] if the condition holds. */
5023 mips_expand_conditional_branch (rtx
*operands
)
5025 enum rtx_code code
= GET_CODE (operands
[0]);
5026 rtx op0
= operands
[1];
5027 rtx op1
= operands
[2];
5030 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
5031 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5032 emit_jump_insn (gen_condjump (condition
, operands
[3]));
5037 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5038 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5041 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
5042 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
5047 reversed_p
= mips_reversed_fp_cond (&cond
);
5048 cmp_result
= mips_allocate_fcc (CCV2mode
);
5049 emit_insn (gen_scc_ps (cmp_result
,
5050 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
5052 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
5055 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
5059 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5060 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5063 mips_expand_conditional_move (rtx
*operands
)
5066 enum rtx_code code
= GET_CODE (operands
[1]);
5067 rtx op0
= XEXP (operands
[1], 0);
5068 rtx op1
= XEXP (operands
[1], 1);
5070 mips_emit_compare (&code
, &op0
, &op1
, true);
5071 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
5072 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
5073 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
5074 operands
[2], operands
[3])));
5077 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5080 mips_expand_conditional_trap (rtx comparison
)
5083 enum machine_mode mode
;
5086 /* MIPS conditional trap instructions don't have GT or LE flavors,
5087 so we must swap the operands and convert to LT and GE respectively. */
5088 code
= GET_CODE (comparison
);
5095 code
= swap_condition (code
);
5096 op0
= XEXP (comparison
, 1);
5097 op1
= XEXP (comparison
, 0);
5101 op0
= XEXP (comparison
, 0);
5102 op1
= XEXP (comparison
, 1);
5106 mode
= GET_MODE (XEXP (comparison
, 0));
5107 op0
= force_reg (mode
, op0
);
5108 if (!arith_operand (op1
, mode
))
5109 op1
= force_reg (mode
, op1
);
5111 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
5112 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
5116 /* Initialize *CUM for a call to a function of type FNTYPE. */
5119 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
5121 memset (cum
, 0, sizeof (*cum
));
5122 cum
->prototype
= (fntype
&& prototype_p (fntype
));
5123 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
5126 /* Fill INFO with information about a single argument. CUM is the
5127 cumulative state for earlier arguments. MODE is the mode of this
5128 argument and TYPE is its type (if known). NAMED is true if this
5129 is a named (fixed) argument rather than a variable one. */
5132 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
5133 enum machine_mode mode
, const_tree type
, bool named
)
5135 bool doubleword_aligned_p
;
5136 unsigned int num_bytes
, num_words
, max_regs
;
5138 /* Work out the size of the argument. */
5139 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5140 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5142 /* Decide whether it should go in a floating-point register, assuming
5143 one is free. Later code checks for availability.
5145 The checks against UNITS_PER_FPVALUE handle the soft-float and
5146 single-float cases. */
5150 /* The EABI conventions have traditionally been defined in terms
5151 of TYPE_MODE, regardless of the actual type. */
5152 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5153 || mode
== V2SFmode
)
5154 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5159 /* Only leading floating-point scalars are passed in
5160 floating-point registers. We also handle vector floats the same
5161 say, which is OK because they are not covered by the standard ABI. */
5162 info
->fpr_p
= (!cum
->gp_reg_found
5163 && cum
->arg_number
< 2
5165 || SCALAR_FLOAT_TYPE_P (type
)
5166 || VECTOR_FLOAT_TYPE_P (type
))
5167 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5168 || mode
== V2SFmode
)
5169 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5174 /* Scalar, complex and vector floating-point types are passed in
5175 floating-point registers, as long as this is a named rather
5176 than a variable argument. */
5177 info
->fpr_p
= (named
5178 && (type
== 0 || FLOAT_TYPE_P (type
))
5179 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5180 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5181 || mode
== V2SFmode
)
5182 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5184 /* ??? According to the ABI documentation, the real and imaginary
5185 parts of complex floats should be passed in individual registers.
5186 The real and imaginary parts of stack arguments are supposed
5187 to be contiguous and there should be an extra word of padding
5190 This has two problems. First, it makes it impossible to use a
5191 single "void *" va_list type, since register and stack arguments
5192 are passed differently. (At the time of writing, MIPSpro cannot
5193 handle complex float varargs correctly.) Second, it's unclear
5194 what should happen when there is only one register free.
5196 For now, we assume that named complex floats should go into FPRs
5197 if there are two FPRs free, otherwise they should be passed in the
5198 same way as a struct containing two floats. */
5200 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5201 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5203 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5204 info
->fpr_p
= false;
5214 /* See whether the argument has doubleword alignment. */
5215 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5218 /* Set REG_OFFSET to the register count we're interested in.
5219 The EABI allocates the floating-point registers separately,
5220 but the other ABIs allocate them like integer registers. */
5221 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5225 /* Advance to an even register if the argument is doubleword-aligned. */
5226 if (doubleword_aligned_p
)
5227 info
->reg_offset
+= info
->reg_offset
& 1;
5229 /* Work out the offset of a stack argument. */
5230 info
->stack_offset
= cum
->stack_words
;
5231 if (doubleword_aligned_p
)
5232 info
->stack_offset
+= info
->stack_offset
& 1;
5234 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5236 /* Partition the argument between registers and stack. */
5237 info
->reg_words
= MIN (num_words
, max_regs
);
5238 info
->stack_words
= num_words
- info
->reg_words
;
5241 /* INFO describes a register argument that has the normal format for the
5242 argument's mode. Return the register it uses, assuming that FPRs are
5243 available if HARD_FLOAT_P. */
5246 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5248 if (!info
->fpr_p
|| !hard_float_p
)
5249 return GP_ARG_FIRST
+ info
->reg_offset
;
5250 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5251 /* In o32, the second argument is always passed in $f14
5252 for TARGET_DOUBLE_FLOAT, regardless of whether the
5253 first argument was a word or doubleword. */
5254 return FP_ARG_FIRST
+ 2;
5256 return FP_ARG_FIRST
+ info
->reg_offset
;
5259 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5262 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5264 return !TARGET_OLDABI
;
5267 /* Implement TARGET_FUNCTION_ARG. */
5270 mips_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
5271 const_tree type
, bool named
)
5273 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5274 struct mips_arg_info info
;
5276 /* We will be called with a mode of VOIDmode after the last argument
5277 has been seen. Whatever we return will be passed to the call expander.
5278 If we need a MIPS16 fp_code, return a REG with the code stored as
5280 if (mode
== VOIDmode
)
5282 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5283 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
5288 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5290 /* Return straight away if the whole argument is passed on the stack. */
5291 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5294 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5295 contains a double in its entirety, then that 64-bit chunk is passed
5296 in a floating-point register. */
5298 && TARGET_HARD_FLOAT
5301 && TREE_CODE (type
) == RECORD_TYPE
5302 && TYPE_SIZE_UNIT (type
)
5303 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
5307 /* First check to see if there is any such field. */
5308 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5309 if (TREE_CODE (field
) == FIELD_DECL
5310 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5311 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5312 && tree_fits_shwi_p (bit_position (field
))
5313 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5318 /* Now handle the special case by returning a PARALLEL
5319 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5320 chunks are passed in registers. */
5322 HOST_WIDE_INT bitpos
;
5325 /* assign_parms checks the mode of ENTRY_PARM, so we must
5326 use the actual mode here. */
5327 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5330 field
= TYPE_FIELDS (type
);
5331 for (i
= 0; i
< info
.reg_words
; i
++)
5335 for (; field
; field
= DECL_CHAIN (field
))
5336 if (TREE_CODE (field
) == FIELD_DECL
5337 && int_bit_position (field
) >= bitpos
)
5341 && int_bit_position (field
) == bitpos
5342 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5343 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5344 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5346 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
5349 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5350 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5352 bitpos
+= BITS_PER_WORD
;
5358 /* Handle the n32/n64 conventions for passing complex floating-point
5359 arguments in FPR pairs. The real part goes in the lower register
5360 and the imaginary part goes in the upper register. */
5363 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5366 enum machine_mode inner
;
5369 inner
= GET_MODE_INNER (mode
);
5370 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
5371 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
5373 /* Real part in registers, imaginary part on stack. */
5374 gcc_assert (info
.stack_words
== info
.reg_words
);
5375 return gen_rtx_REG (inner
, regno
);
5379 gcc_assert (info
.stack_words
== 0);
5380 real
= gen_rtx_EXPR_LIST (VOIDmode
,
5381 gen_rtx_REG (inner
, regno
),
5383 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
5385 regno
+ info
.reg_words
/ 2),
5386 GEN_INT (GET_MODE_SIZE (inner
)));
5387 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
5391 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
5394 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5397 mips_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
5398 const_tree type
, bool named
)
5400 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5401 struct mips_arg_info info
;
5403 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5406 cum
->gp_reg_found
= true;
5408 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5409 an explanation of what this code does. It assumes that we're using
5410 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5412 if (cum
->arg_number
< 2 && info
.fpr_p
)
5413 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5415 /* Advance the register count. This has the effect of setting
5416 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5417 argument required us to skip the final GPR and pass the whole
5418 argument on the stack. */
5419 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5420 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5421 else if (info
.reg_words
> 0)
5422 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5424 /* Advance the stack word count. */
5425 if (info
.stack_words
> 0)
5426 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5431 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5434 mips_arg_partial_bytes (cumulative_args_t cum
,
5435 enum machine_mode mode
, tree type
, bool named
)
5437 struct mips_arg_info info
;
5439 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5440 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5443 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5444 least PARM_BOUNDARY bits of alignment, but will be given anything up
5445 to STACK_BOUNDARY bits if the type requires it. */
5448 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5450 unsigned int alignment
;
5452 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5453 if (alignment
< PARM_BOUNDARY
)
5454 alignment
= PARM_BOUNDARY
;
5455 if (alignment
> STACK_BOUNDARY
)
5456 alignment
= STACK_BOUNDARY
;
5460 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5461 upward rather than downward. In other words, return true if the
5462 first byte of the stack slot has useful data, false if the last
5466 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
5468 /* On little-endian targets, the first byte of every stack argument
5469 is passed in the first byte of the stack slot. */
5470 if (!BYTES_BIG_ENDIAN
)
5473 /* Otherwise, integral types are padded downward: the last byte of a
5474 stack argument is passed in the last byte of the stack slot. */
5476 ? (INTEGRAL_TYPE_P (type
)
5477 || POINTER_TYPE_P (type
)
5478 || FIXED_POINT_TYPE_P (type
))
5479 : (SCALAR_INT_MODE_P (mode
)
5480 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5483 /* Big-endian o64 pads floating-point arguments downward. */
5484 if (mips_abi
== ABI_O64
)
5485 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5488 /* Other types are padded upward for o32, o64, n32 and n64. */
5489 if (mips_abi
!= ABI_EABI
)
5492 /* Arguments smaller than a stack slot are padded downward. */
5493 if (mode
!= BLKmode
)
5494 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5496 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5499 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5500 if the least significant byte of the register has useful data. Return
5501 the opposite if the most significant byte does. */
5504 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
5506 /* No shifting is required for floating-point arguments. */
5507 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5508 return !BYTES_BIG_ENDIAN
;
5510 /* Otherwise, apply the same padding to register arguments as we do
5511 to stack arguments. */
5512 return mips_pad_arg_upward (mode
, type
);
5515 /* Return nonzero when an argument must be passed by reference. */
5518 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5519 enum machine_mode mode
, const_tree type
,
5520 bool named ATTRIBUTE_UNUSED
)
5522 if (mips_abi
== ABI_EABI
)
5526 /* ??? How should SCmode be handled? */
5527 if (mode
== DImode
|| mode
== DFmode
5528 || mode
== DQmode
|| mode
== UDQmode
5529 || mode
== DAmode
|| mode
== UDAmode
)
5532 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5533 return size
== -1 || size
> UNITS_PER_WORD
;
5537 /* If we have a variable-sized parameter, we have no choice. */
5538 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5542 /* Implement TARGET_CALLEE_COPIES. */
5545 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5546 enum machine_mode mode ATTRIBUTE_UNUSED
,
5547 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5549 return mips_abi
== ABI_EABI
&& named
;
5552 /* See whether VALTYPE is a record whose fields should be returned in
5553 floating-point registers. If so, return the number of fields and
5554 list them in FIELDS (which should have two elements). Return 0
5557 For n32 & n64, a structure with one or two fields is returned in
5558 floating-point registers as long as every field has a floating-point
5562 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5570 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5574 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5576 if (TREE_CODE (field
) != FIELD_DECL
)
5579 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5585 fields
[i
++] = field
;
5590 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5591 a value in the most significant part of $2/$3 if:
5593 - the target is big-endian;
5595 - the value has a structure or union type (we generalize this to
5596 cover aggregates from other languages too); and
5598 - the structure is not returned in floating-point registers. */
5601 mips_return_in_msb (const_tree valtype
)
5605 return (TARGET_NEWABI
5606 && TARGET_BIG_ENDIAN
5607 && AGGREGATE_TYPE_P (valtype
)
5608 && mips_fpr_return_fields (valtype
, fields
) == 0);
5611 /* Return true if the function return value MODE will get returned in a
5612 floating-point register. */
5615 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5617 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5619 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5620 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5623 /* Return the representation of an FPR return register when the
5624 value being returned in FP_RETURN has mode VALUE_MODE and the
5625 return type itself has mode TYPE_MODE. On NewABI targets,
5626 the two modes may be different for structures like:
5628 struct __attribute__((packed)) foo { float f; }
5630 where we return the SFmode value of "f" in FP_RETURN, but where
5631 the structure itself has mode BLKmode. */
5634 mips_return_fpr_single (enum machine_mode type_mode
,
5635 enum machine_mode value_mode
)
5639 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5640 if (type_mode
!= value_mode
)
5642 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5643 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5648 /* Return a composite value in a pair of floating-point registers.
5649 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5650 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5653 For n32 & n64, $f0 always holds the first value and $f2 the second.
5654 Otherwise the values are packed together as closely as possible. */
5657 mips_return_fpr_pair (enum machine_mode mode
,
5658 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5659 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5663 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5664 return gen_rtx_PARALLEL
5667 gen_rtx_EXPR_LIST (VOIDmode
,
5668 gen_rtx_REG (mode1
, FP_RETURN
),
5670 gen_rtx_EXPR_LIST (VOIDmode
,
5671 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5672 GEN_INT (offset2
))));
5676 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5677 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5678 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5681 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5682 enum machine_mode mode
)
5690 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5691 func
= fn_decl_or_type
;
5695 mode
= TYPE_MODE (valtype
);
5696 unsigned_p
= TYPE_UNSIGNED (valtype
);
5698 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5699 return values, promote the mode here too. */
5700 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5702 /* Handle structures whose fields are returned in $f0/$f2. */
5703 switch (mips_fpr_return_fields (valtype
, fields
))
5706 return mips_return_fpr_single (mode
,
5707 TYPE_MODE (TREE_TYPE (fields
[0])));
5710 return mips_return_fpr_pair (mode
,
5711 TYPE_MODE (TREE_TYPE (fields
[0])),
5712 int_byte_position (fields
[0]),
5713 TYPE_MODE (TREE_TYPE (fields
[1])),
5714 int_byte_position (fields
[1]));
5717 /* If a value is passed in the most significant part of a register, see
5718 whether we have to round the mode up to a whole number of words. */
5719 if (mips_return_in_msb (valtype
))
5721 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5722 if (size
% UNITS_PER_WORD
!= 0)
5724 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5725 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5729 /* For EABI, the class of return register depends entirely on MODE.
5730 For example, "struct { some_type x; }" and "union { some_type x; }"
5731 are returned in the same way as a bare "some_type" would be.
5732 Other ABIs only use FPRs for scalar, complex or vector types. */
5733 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5734 return gen_rtx_REG (mode
, GP_RETURN
);
5739 /* Handle long doubles for n32 & n64. */
5741 return mips_return_fpr_pair (mode
,
5743 DImode
, GET_MODE_SIZE (mode
) / 2);
5745 if (mips_return_mode_in_fpr_p (mode
))
5747 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5748 return mips_return_fpr_pair (mode
,
5749 GET_MODE_INNER (mode
), 0,
5750 GET_MODE_INNER (mode
),
5751 GET_MODE_SIZE (mode
) / 2);
5753 return gen_rtx_REG (mode
, FP_RETURN
);
5757 return gen_rtx_REG (mode
, GP_RETURN
);
5760 /* Implement TARGET_FUNCTION_VALUE. */
5763 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5764 bool outgoing ATTRIBUTE_UNUSED
)
5766 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5769 /* Implement TARGET_LIBCALL_VALUE. */
5772 mips_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5774 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5777 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5779 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5780 Currently, R2 and F0 are only implemented here (C has no complex type). */
5783 mips_function_value_regno_p (const unsigned int regno
)
5785 if (regno
== GP_RETURN
5786 || regno
== FP_RETURN
5787 || (LONG_DOUBLE_TYPE_SIZE
== 128
5788 && FP_RETURN
!= GP_RETURN
5789 && regno
== FP_RETURN
+ 2))
5795 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5796 all BLKmode objects are returned in memory. Under the n32, n64
5797 and embedded ABIs, small structures are returned in a register.
5798 Objects with varying size must still be returned in memory, of
5802 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5804 return (TARGET_OLDABI
5805 ? TYPE_MODE (type
) == BLKmode
5806 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5809 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5812 mips_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
5813 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5816 CUMULATIVE_ARGS local_cum
;
5817 int gp_saved
, fp_saved
;
5819 /* The caller has advanced CUM up to, but not beyond, the last named
5820 argument. Advance a local copy of CUM past the last "real" named
5821 argument, to find out how many registers are left over. */
5822 local_cum
= *get_cumulative_args (cum
);
5823 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5826 /* Found out how many registers we need to save. */
5827 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5828 fp_saved
= (EABI_FLOAT_VARARGS_P
5829 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5838 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
5839 REG_PARM_STACK_SPACE (cfun
->decl
)
5840 - gp_saved
* UNITS_PER_WORD
);
5841 mem
= gen_frame_mem (BLKmode
, ptr
);
5842 set_mem_alias_set (mem
, get_varargs_alias_set ());
5844 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5849 /* We can't use move_block_from_reg, because it will use
5851 enum machine_mode mode
;
5854 /* Set OFF to the offset from virtual_incoming_args_rtx of
5855 the first float register. The FP save area lies below
5856 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5857 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5858 off
-= fp_saved
* UNITS_PER_FPREG
;
5860 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5862 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5863 i
+= MAX_FPRS_PER_FMT
)
5867 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
5868 mem
= gen_frame_mem (mode
, ptr
);
5869 set_mem_alias_set (mem
, get_varargs_alias_set ());
5870 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5871 off
+= UNITS_PER_HWFPVALUE
;
5875 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5876 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5877 + fp_saved
* UNITS_PER_FPREG
);
5880 /* Implement TARGET_BUILTIN_VA_LIST. */
5883 mips_build_builtin_va_list (void)
5885 if (EABI_FLOAT_VARARGS_P
)
5887 /* We keep 3 pointers, and two offsets.
5889 Two pointers are to the overflow area, which starts at the CFA.
5890 One of these is constant, for addressing into the GPR save area
5891 below it. The other is advanced up the stack through the
5894 The third pointer is to the bottom of the GPR save area.
5895 Since the FPR save area is just below it, we can address
5896 FPR slots off this pointer.
5898 We also keep two one-byte offsets, which are to be subtracted
5899 from the constant pointers to yield addresses in the GPR and
5900 FPR save areas. These are downcounted as float or non-float
5901 arguments are used, and when they get to zero, the argument
5902 must be obtained from the overflow region. */
5903 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5906 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5908 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5909 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5911 f_gtop
= build_decl (BUILTINS_LOCATION
,
5912 FIELD_DECL
, get_identifier ("__gpr_top"),
5914 f_ftop
= build_decl (BUILTINS_LOCATION
,
5915 FIELD_DECL
, get_identifier ("__fpr_top"),
5917 f_goff
= build_decl (BUILTINS_LOCATION
,
5918 FIELD_DECL
, get_identifier ("__gpr_offset"),
5919 unsigned_char_type_node
);
5920 f_foff
= build_decl (BUILTINS_LOCATION
,
5921 FIELD_DECL
, get_identifier ("__fpr_offset"),
5922 unsigned_char_type_node
);
5923 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5924 warn on every user file. */
5925 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5926 array
= build_array_type (unsigned_char_type_node
,
5927 build_index_type (index
));
5928 f_res
= build_decl (BUILTINS_LOCATION
,
5929 FIELD_DECL
, get_identifier ("__reserved"), array
);
5931 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5932 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5933 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5934 DECL_FIELD_CONTEXT (f_goff
) = record
;
5935 DECL_FIELD_CONTEXT (f_foff
) = record
;
5936 DECL_FIELD_CONTEXT (f_res
) = record
;
5938 TYPE_FIELDS (record
) = f_ovfl
;
5939 DECL_CHAIN (f_ovfl
) = f_gtop
;
5940 DECL_CHAIN (f_gtop
) = f_ftop
;
5941 DECL_CHAIN (f_ftop
) = f_goff
;
5942 DECL_CHAIN (f_goff
) = f_foff
;
5943 DECL_CHAIN (f_foff
) = f_res
;
5945 layout_type (record
);
5949 /* Otherwise, we use 'void *'. */
5950 return ptr_type_node
;
5953 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5956 mips_va_start (tree valist
, rtx nextarg
)
5958 if (EABI_FLOAT_VARARGS_P
)
5960 const CUMULATIVE_ARGS
*cum
;
5961 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5962 tree ovfl
, gtop
, ftop
, goff
, foff
;
5964 int gpr_save_area_size
;
5965 int fpr_save_area_size
;
5968 cum
= &crtl
->args
.info
;
5970 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5972 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5974 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5975 f_gtop
= DECL_CHAIN (f_ovfl
);
5976 f_ftop
= DECL_CHAIN (f_gtop
);
5977 f_goff
= DECL_CHAIN (f_ftop
);
5978 f_foff
= DECL_CHAIN (f_goff
);
5980 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5982 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5984 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5986 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5988 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5991 /* Emit code to initialize OVFL, which points to the next varargs
5992 stack argument. CUM->STACK_WORDS gives the number of stack
5993 words used by named arguments. */
5994 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5995 if (cum
->stack_words
> 0)
5996 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
5997 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5998 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6000 /* Emit code to initialize GTOP, the top of the GPR save area. */
6001 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
6002 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
6003 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6005 /* Emit code to initialize FTOP, the top of the FPR save area.
6006 This address is gpr_save_area_bytes below GTOP, rounded
6007 down to the next fp-aligned boundary. */
6008 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
6009 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
6010 fpr_offset
&= -UNITS_PER_FPVALUE
;
6012 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
6013 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
6014 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6016 /* Emit code to initialize GOFF, the offset from GTOP of the
6017 next GPR argument. */
6018 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
6019 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
6020 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6022 /* Likewise emit code to initialize FOFF, the offset from FTOP
6023 of the next FPR argument. */
6024 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
6025 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
6026 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6030 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
6031 std_expand_builtin_va_start (valist
, nextarg
);
6035 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6039 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6042 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
6043 unsigned HOST_WIDE_INT align
, boundary
;
6046 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6048 type
= build_pointer_type (type
);
6050 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
6051 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
6053 /* When we align parameter on stack for caller, if the parameter
6054 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6055 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6056 here with caller. */
6057 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
6058 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
6060 boundary
/= BITS_PER_UNIT
;
6062 /* Hoist the valist value into a temporary for the moment. */
6063 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
6065 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6066 requires greater alignment, we must perform dynamic alignment. */
6067 if (boundary
> align
)
6069 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6070 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
6071 gimplify_and_add (t
, pre_p
);
6073 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6074 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
6076 build_int_cst (TREE_TYPE (valist
), -boundary
)));
6077 gimplify_and_add (t
, pre_p
);
6082 /* If the actual alignment is less than the alignment of the type,
6083 adjust the type accordingly so that we don't assume strict alignment
6084 when dereferencing the pointer. */
6085 boundary
*= BITS_PER_UNIT
;
6086 if (boundary
< TYPE_ALIGN (type
))
6088 type
= build_variant_type_copy (type
);
6089 TYPE_ALIGN (type
) = boundary
;
6092 /* Compute the rounded size of the type. */
6093 type_size
= size_in_bytes (type
);
6094 rounded_size
= round_up (type_size
, align
);
6096 /* Reduce rounded_size so it's sharable with the postqueue. */
6097 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6101 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
6103 /* Small args are padded downward. */
6104 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
6105 rounded_size
, size_int (align
));
6106 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
6107 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
6108 addr
= fold_build_pointer_plus (addr
, t
);
6111 /* Compute new value for AP. */
6112 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
6113 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
6114 gimplify_and_add (t
, pre_p
);
6116 addr
= fold_convert (build_pointer_type (type
), addr
);
6119 addr
= build_va_arg_indirect_ref (addr
);
6121 return build_va_arg_indirect_ref (addr
);
6124 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6127 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6133 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
6135 type
= build_pointer_type (type
);
6137 if (!EABI_FLOAT_VARARGS_P
)
6138 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6141 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6142 tree ovfl
, top
, off
, align
;
6143 HOST_WIDE_INT size
, rsize
, osize
;
6146 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6147 f_gtop
= DECL_CHAIN (f_ovfl
);
6148 f_ftop
= DECL_CHAIN (f_gtop
);
6149 f_goff
= DECL_CHAIN (f_ftop
);
6150 f_foff
= DECL_CHAIN (f_goff
);
6154 TOP be the top of the GPR or FPR save area;
6155 OFF be the offset from TOP of the next register;
6156 ADDR_RTX be the address of the argument;
6157 SIZE be the number of bytes in the argument type;
6158 RSIZE be the number of bytes used to store the argument
6159 when it's in the register save area; and
6160 OSIZE be the number of bytes used to store it when it's
6161 in the stack overflow area.
6163 The code we want is:
6165 1: off &= -rsize; // round down
6168 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6173 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6174 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6178 [1] and [9] can sometimes be optimized away. */
6180 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6182 size
= int_size_in_bytes (type
);
6184 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6185 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6187 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6188 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6189 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6190 unshare_expr (valist
), f_foff
, NULL_TREE
);
6192 /* When va_start saves FPR arguments to the stack, each slot
6193 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6194 argument's precision. */
6195 rsize
= UNITS_PER_HWFPVALUE
;
6197 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6198 (= PARM_BOUNDARY bits). This can be different from RSIZE
6201 (1) On 32-bit targets when TYPE is a structure such as:
6203 struct s { float f; };
6205 Such structures are passed in paired FPRs, so RSIZE
6206 will be 8 bytes. However, the structure only takes
6207 up 4 bytes of memory, so OSIZE will only be 4.
6209 (2) In combinations such as -mgp64 -msingle-float
6210 -fshort-double. Doubles passed in registers will then take
6211 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6212 stack take up UNITS_PER_WORD bytes. */
6213 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6217 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6218 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6219 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6220 unshare_expr (valist
), f_goff
, NULL_TREE
);
6221 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6222 if (rsize
> UNITS_PER_WORD
)
6224 /* [1] Emit code for: off &= -rsize. */
6225 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6226 build_int_cst (TREE_TYPE (off
), -rsize
));
6227 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6232 /* [2] Emit code to branch if off == 0. */
6233 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6234 build_int_cst (TREE_TYPE (off
), 0));
6235 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6237 /* [5] Emit code for: off -= rsize. We do this as a form of
6238 post-decrement not available to C. */
6239 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6240 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6242 /* [4] Emit code for:
6243 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6244 t
= fold_convert (sizetype
, t
);
6245 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6246 t
= fold_build_pointer_plus (top
, t
);
6247 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6248 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6249 COND_EXPR_THEN (addr
) = t
;
6251 if (osize
> UNITS_PER_WORD
)
6253 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6254 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6255 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6256 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6257 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6258 unshare_expr (ovfl
), t
);
6263 /* [10, 11] Emit code for:
6264 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6266 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6267 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6268 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6269 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6271 /* String [9] and [10, 11] together. */
6273 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6274 COND_EXPR_ELSE (addr
) = t
;
6276 addr
= fold_convert (build_pointer_type (type
), addr
);
6277 addr
= build_va_arg_indirect_ref (addr
);
6281 addr
= build_va_arg_indirect_ref (addr
);
6286 /* Declare a unique, locally-binding function called NAME, then start
6290 mips_start_unique_function (const char *name
)
6294 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6295 get_identifier (name
),
6296 build_function_type_list (void_type_node
, NULL_TREE
));
6297 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6298 NULL_TREE
, void_type_node
);
6299 TREE_PUBLIC (decl
) = 1;
6300 TREE_STATIC (decl
) = 1;
6302 cgraph_create_node (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
6304 targetm
.asm_out
.unique_section (decl
, 0);
6305 switch_to_section (get_named_section (decl
, NULL
, 0));
6307 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6308 fputs ("\t.hidden\t", asm_out_file
);
6309 assemble_name (asm_out_file
, name
);
6310 putc ('\n', asm_out_file
);
6313 /* Start a definition of function NAME. MIPS16_P indicates whether the
6314 function contains MIPS16 code. */
6317 mips_start_function_definition (const char *name
, bool mips16_p
)
6320 fprintf (asm_out_file
, "\t.set\tmips16\n");
6322 fprintf (asm_out_file
, "\t.set\tnomips16\n");
6324 if (TARGET_MICROMIPS
)
6325 fprintf (asm_out_file
, "\t.set\tmicromips\n");
6326 #ifdef HAVE_GAS_MICROMIPS
6328 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
6331 if (!flag_inhibit_size_directive
)
6333 fputs ("\t.ent\t", asm_out_file
);
6334 assemble_name (asm_out_file
, name
);
6335 fputs ("\n", asm_out_file
);
6338 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
6340 /* Start the definition proper. */
6341 assemble_name (asm_out_file
, name
);
6342 fputs (":\n", asm_out_file
);
6345 /* End a function definition started by mips_start_function_definition. */
6348 mips_end_function_definition (const char *name
)
6350 if (!flag_inhibit_size_directive
)
6352 fputs ("\t.end\t", asm_out_file
);
6353 assemble_name (asm_out_file
, name
);
6354 fputs ("\n", asm_out_file
);
6358 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
6359 then free *STUB_PTR. */
6362 mips_finish_stub (mips_one_only_stub
**stub_ptr
)
6364 mips_one_only_stub
*stub
= *stub_ptr
;
6368 const char *name
= stub
->get_name ();
6369 mips_start_unique_function (name
);
6370 mips_start_function_definition (name
, false);
6371 stub
->output_body ();
6372 mips_end_function_definition (name
);
6377 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6380 mips_ok_for_lazy_binding_p (rtx x
)
6382 return (TARGET_USE_GOT
6383 && GET_CODE (x
) == SYMBOL_REF
6384 && !SYMBOL_REF_BIND_NOW_P (x
)
6385 && !mips_symbol_binds_local_p (x
));
6388 /* Load function address ADDR into register DEST. TYPE is as for
6389 mips_expand_call. Return true if we used an explicit lazy-binding
6393 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
6395 /* If we're generating PIC, and this call is to a global function,
6396 try to allow its address to be resolved lazily. This isn't
6397 possible for sibcalls when $gp is call-saved because the value
6398 of $gp on entry to the stub would be our caller's gp, not ours. */
6399 if (TARGET_EXPLICIT_RELOCS
6400 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
6401 && mips_ok_for_lazy_binding_p (addr
))
6403 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
6404 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
6409 mips_emit_move (dest
, addr
);
6414 /* Each locally-defined hard-float MIPS16 function has a local symbol
6415 associated with it. This hash table maps the function symbol (FUNC)
6416 to the local symbol (LOCAL). */
6417 struct GTY(()) mips16_local_alias
{
6421 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
6423 /* Hash table callbacks for mips16_local_aliases. */
6426 mips16_local_aliases_hash (const void *entry
)
6428 const struct mips16_local_alias
*alias
;
6430 alias
= (const struct mips16_local_alias
*) entry
;
6431 return htab_hash_string (XSTR (alias
->func
, 0));
6435 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
6437 const struct mips16_local_alias
*alias1
, *alias2
;
6439 alias1
= (const struct mips16_local_alias
*) entry1
;
6440 alias2
= (const struct mips16_local_alias
*) entry2
;
6441 return rtx_equal_p (alias1
->func
, alias2
->func
);
6444 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6445 Return a local alias for it, creating a new one if necessary. */
6448 mips16_local_alias (rtx func
)
6450 struct mips16_local_alias
*alias
, tmp_alias
;
6453 /* Create the hash table if this is the first call. */
6454 if (mips16_local_aliases
== NULL
)
6455 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
6456 mips16_local_aliases_eq
, NULL
);
6458 /* Look up the function symbol, creating a new entry if need be. */
6459 tmp_alias
.func
= func
;
6460 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
6461 gcc_assert (slot
!= NULL
);
6463 alias
= (struct mips16_local_alias
*) *slot
;
6466 const char *func_name
, *local_name
;
6469 /* Create a new SYMBOL_REF for the local symbol. The choice of
6470 __fn_local_* is based on the __fn_stub_* names that we've
6471 traditionally used for the non-MIPS16 stub. */
6472 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6473 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6474 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6475 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6477 /* Create a new structure to represent the mapping. */
6478 alias
= ggc_alloc
<struct mips16_local_alias
> ();
6480 alias
->local
= local
;
6483 return alias
->local
;
6486 /* A chained list of functions for which mips16_build_call_stub has already
6487 generated a stub. NAME is the name of the function and FP_RET_P is true
6488 if the function returns a value in floating-point registers. */
6489 struct mips16_stub
{
6490 struct mips16_stub
*next
;
6494 static struct mips16_stub
*mips16_stubs
;
6496 /* Return the two-character string that identifies floating-point
6497 return mode MODE in the name of a MIPS16 function stub. */
6500 mips16_call_stub_mode_suffix (enum machine_mode mode
)
6504 else if (mode
== DFmode
)
6506 else if (mode
== SCmode
)
6508 else if (mode
== DCmode
)
6510 else if (mode
== V2SFmode
)
6516 /* Write instructions to move a 32-bit value between general register
6517 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6518 from GPREG to FPREG and 'f' to move in the opposite direction. */
6521 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6523 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6524 reg_names
[gpreg
], reg_names
[fpreg
]);
6527 /* Likewise for 64-bit values. */
6530 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6533 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6534 reg_names
[gpreg
], reg_names
[fpreg
]);
6535 else if (TARGET_FLOAT64
)
6537 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6538 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6539 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6540 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6544 /* Move the least-significant word. */
6545 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6546 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6547 /* ...then the most significant word. */
6548 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6549 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6553 /* Write out code to move floating-point arguments into or out of
6554 general registers. FP_CODE is the code describing which arguments
6555 are present (see the comment above the definition of CUMULATIVE_ARGS
6556 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6559 mips_output_args_xfer (int fp_code
, char direction
)
6561 unsigned int gparg
, fparg
, f
;
6562 CUMULATIVE_ARGS cum
;
6564 /* This code only works for o32 and o64. */
6565 gcc_assert (TARGET_OLDABI
);
6567 mips_init_cumulative_args (&cum
, NULL
);
6569 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6571 enum machine_mode mode
;
6572 struct mips_arg_info info
;
6576 else if ((f
& 3) == 2)
6581 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6582 gparg
= mips_arg_regno (&info
, false);
6583 fparg
= mips_arg_regno (&info
, true);
6586 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6588 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6590 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6594 /* Write a MIPS16 stub for the current function. This stub is used
6595 for functions which take arguments in the floating-point registers.
6596 It is normal-mode code that moves the floating-point arguments
6597 into the general registers and then jumps to the MIPS16 code. */
6600 mips16_build_function_stub (void)
6602 const char *fnname
, *alias_name
, *separator
;
6603 char *secname
, *stubname
;
6608 /* Create the name of the stub, and its unique section. */
6609 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6610 alias
= mips16_local_alias (symbol
);
6612 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6613 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6614 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6615 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6617 /* Build a decl for the stub. */
6618 stubdecl
= build_decl (BUILTINS_LOCATION
,
6619 FUNCTION_DECL
, get_identifier (stubname
),
6620 build_function_type_list (void_type_node
, NULL_TREE
));
6621 set_decl_section_name (stubdecl
, build_string (strlen (secname
), secname
));
6622 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6623 RESULT_DECL
, NULL_TREE
, void_type_node
);
6625 /* Output a comment. */
6626 fprintf (asm_out_file
, "\t# Stub function for %s (",
6627 current_function_name ());
6629 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6631 fprintf (asm_out_file
, "%s%s", separator
,
6632 (f
& 3) == 1 ? "float" : "double");
6635 fprintf (asm_out_file
, ")\n");
6637 /* Start the function definition. */
6638 assemble_start_function (stubdecl
, stubname
);
6639 mips_start_function_definition (stubname
, false);
6641 /* If generating pic2 code, either set up the global pointer or
6643 if (TARGET_ABICALLS_PIC2
)
6645 if (TARGET_ABSOLUTE_ABICALLS
)
6646 fprintf (asm_out_file
, "\t.option\tpic0\n");
6649 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6650 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6651 target function is. Use a local GOT access when loading the
6652 symbol, to cut down on the number of unnecessary GOT entries
6653 for stubs that aren't needed. */
6654 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6659 /* Load the address of the MIPS16 function into $25. Do this first so
6660 that targets with coprocessor interlocks can use an MFC1 to fill the
6662 output_asm_insn ("la\t%^,%0", &symbol
);
6664 /* Move the arguments from floating-point registers to general registers. */
6665 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6667 /* Jump to the MIPS16 function. */
6668 output_asm_insn ("jr\t%^", NULL
);
6670 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6671 fprintf (asm_out_file
, "\t.option\tpic2\n");
6673 mips_end_function_definition (stubname
);
6675 /* If the linker needs to create a dynamic symbol for the target
6676 function, it will associate the symbol with the stub (which,
6677 unlike the target function, follows the proper calling conventions).
6678 It is therefore useful to have a local alias for the target function,
6679 so that it can still be identified as MIPS16 code. As an optimization,
6680 this symbol can also be used for indirect MIPS16 references from
6681 within this file. */
6682 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6684 switch_to_section (function_section (current_function_decl
));
6687 /* The current function is a MIPS16 function that returns a value in an FPR.
6688 Copy the return value from its soft-float to its hard-float location.
6689 libgcc2 has special non-MIPS16 helper functions for each case. */
6692 mips16_copy_fpr_return_value (void)
6694 rtx fn
, insn
, retval
;
6696 enum machine_mode return_mode
;
6699 return_type
= DECL_RESULT (current_function_decl
);
6700 return_mode
= DECL_MODE (return_type
);
6702 name
= ACONCAT (("__mips16_ret_",
6703 mips16_call_stub_mode_suffix (return_mode
),
6705 fn
= mips16_stub_function (name
);
6707 /* The function takes arguments in $2 (and possibly $3), so calls
6708 to it cannot be lazily bound. */
6709 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6711 /* Model the call as something that takes the GPR return value as
6712 argument and returns an "updated" value. */
6713 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6714 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6715 const0_rtx
, NULL_RTX
, false);
6716 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6719 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6720 RETVAL is the location of the return value, or null if this is
6721 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6722 arguments and FP_CODE is the code built by mips_function_arg;
6723 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6725 There are three alternatives:
6727 - If a stub was needed, emit the call and return the call insn itself.
6729 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6730 to the new target and return null.
6732 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6735 A stub is needed for calls to functions that, in normal mode,
6736 receive arguments in FPRs or return values in FPRs. The stub
6737 copies the arguments from their soft-float positions to their
6738 hard-float positions, calls the real function, then copies the
6739 return value from its hard-float position to its soft-float
6742 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6743 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6744 automatically redirects the JAL to the stub, otherwise the JAL
6745 continues to call FN directly. */
6748 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6752 struct mips16_stub
*l
;
6755 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6756 we were invoked with the -msoft-float option. */
6757 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6760 /* Figure out whether the value might come back in a floating-point
6762 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6764 /* We don't need to do anything if there were no floating-point
6765 arguments and the value will not be returned in a floating-point
6767 if (fp_code
== 0 && !fp_ret_p
)
6770 /* We don't need to do anything if this is a call to a special
6771 MIPS16 support function. */
6773 if (mips16_stub_function_p (fn
))
6776 /* If we're calling a locally-defined MIPS16 function, we know that
6777 it will return values in both the "soft-float" and "hard-float"
6778 registers. There is no need to use a stub to move the latter
6780 if (fp_code
== 0 && mips16_local_function_p (fn
))
6783 /* This code will only work for o32 and o64 abis. The other ABI's
6784 require more sophisticated support. */
6785 gcc_assert (TARGET_OLDABI
);
6787 /* If we're calling via a function pointer, use one of the magic
6788 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6789 Each stub expects the function address to arrive in register $2. */
6790 if (GET_CODE (fn
) != SYMBOL_REF
6791 || !call_insn_operand (fn
, VOIDmode
))
6794 rtx stub_fn
, insn
, addr
;
6797 /* If this is a locally-defined and locally-binding function,
6798 avoid the stub by calling the local alias directly. */
6799 if (mips16_local_function_p (fn
))
6801 *fn_ptr
= mips16_local_alias (fn
);
6805 /* Create a SYMBOL_REF for the libgcc.a function. */
6807 sprintf (buf
, "__mips16_call_stub_%s_%d",
6808 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6811 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6812 stub_fn
= mips16_stub_function (buf
);
6814 /* The function uses $2 as an argument, so calls to it
6815 cannot be lazily bound. */
6816 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6818 /* Load the target function into $2. */
6819 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6820 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6822 /* Emit the call. */
6823 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6824 args_size
, NULL_RTX
, lazy_p
);
6826 /* Tell GCC that this call does indeed use the value of $2. */
6827 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6829 /* If we are handling a floating-point return value, we need to
6830 save $18 in the function prologue. Putting a note on the
6831 call will mean that df_regs_ever_live_p ($18) will be true if the
6832 call is not eliminated, and we can check that in the prologue
6835 CALL_INSN_FUNCTION_USAGE (insn
) =
6836 gen_rtx_EXPR_LIST (VOIDmode
,
6837 gen_rtx_CLOBBER (VOIDmode
,
6838 gen_rtx_REG (word_mode
, 18)),
6839 CALL_INSN_FUNCTION_USAGE (insn
));
6844 /* We know the function we are going to call. If we have already
6845 built a stub, we don't need to do anything further. */
6846 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6847 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6848 if (strcmp (l
->name
, fnname
) == 0)
6853 const char *separator
;
6854 char *secname
, *stubname
;
6855 tree stubid
, stubdecl
;
6858 /* If the function does not return in FPRs, the special stub
6862 If the function does return in FPRs, the stub section is named
6863 .mips16.call.fp.FNNAME
6865 Build a decl for the stub. */
6866 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6868 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6870 stubid
= get_identifier (stubname
);
6871 stubdecl
= build_decl (BUILTINS_LOCATION
,
6872 FUNCTION_DECL
, stubid
,
6873 build_function_type_list (void_type_node
,
6875 set_decl_section_name (stubdecl
, build_string (strlen (secname
), secname
));
6876 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6877 RESULT_DECL
, NULL_TREE
,
6880 /* Output a comment. */
6881 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6883 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6887 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6889 fprintf (asm_out_file
, "%s%s", separator
,
6890 (f
& 3) == 1 ? "float" : "double");
6893 fprintf (asm_out_file
, ")\n");
6895 /* Start the function definition. */
6896 assemble_start_function (stubdecl
, stubname
);
6897 mips_start_function_definition (stubname
, false);
6901 fprintf (asm_out_file
, "\t.cfi_startproc\n");
6903 /* Create a fake CFA 4 bytes below the stack pointer.
6904 This works around unwinders (like libgcc's) that expect
6905 the CFA for non-signal frames to be unique. */
6906 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
6908 /* "Save" $sp in itself so we don't use the fake CFA.
6909 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6910 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
6914 /* Load the address of the MIPS16 function into $25. Do this
6915 first so that targets with coprocessor interlocks can use
6916 an MFC1 to fill the delay slot. */
6917 if (TARGET_EXPLICIT_RELOCS
)
6919 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6920 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6923 output_asm_insn ("la\t%^,%0", &fn
);
6926 /* Move the arguments from general registers to floating-point
6928 mips_output_args_xfer (fp_code
, 't');
6932 /* Save the return address in $18 and call the non-MIPS16 function.
6933 The stub's caller knows that $18 might be clobbered, even though
6934 $18 is usually a call-saved register. */
6935 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6936 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6937 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6938 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
6940 /* Move the result from floating-point registers to
6941 general registers. */
6942 switch (GET_MODE (retval
))
6945 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6947 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6949 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6950 TARGET_LITTLE_ENDIAN
6951 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6953 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6955 /* On 64-bit targets, complex floats are returned in
6956 a single GPR, such that "sd" on a suitably-aligned
6957 target would store the value correctly. */
6958 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6959 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6960 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6961 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6962 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6963 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6964 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6965 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6966 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6967 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6968 reg_names
[GP_RETURN
],
6969 reg_names
[GP_RETURN
],
6970 reg_names
[GP_RETURN
+ 1]);
6975 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6979 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6980 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6984 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6990 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6991 fprintf (asm_out_file
, "\t.cfi_endproc\n");
6995 /* Jump to the previously-loaded address. */
6996 output_asm_insn ("jr\t%^", NULL
);
6999 #ifdef ASM_DECLARE_FUNCTION_SIZE
7000 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
7003 mips_end_function_definition (stubname
);
7005 /* Record this stub. */
7006 l
= XNEW (struct mips16_stub
);
7007 l
->name
= xstrdup (fnname
);
7008 l
->fp_ret_p
= fp_ret_p
;
7009 l
->next
= mips16_stubs
;
7013 /* If we expect a floating-point return value, but we've built a
7014 stub which does not expect one, then we're in trouble. We can't
7015 use the existing stub, because it won't handle the floating-point
7016 value. We can't build a new stub, because the linker won't know
7017 which stub to use for the various calls in this object file.
7018 Fortunately, this case is illegal, since it means that a function
7019 was declared in two different ways in a single compilation. */
7020 if (fp_ret_p
&& !l
->fp_ret_p
)
7021 error ("cannot handle inconsistent calls to %qs", fnname
);
7023 if (retval
== NULL_RTX
)
7024 insn
= gen_call_internal_direct (fn
, args_size
);
7026 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
7027 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
7029 /* If we are calling a stub which handles a floating-point return
7030 value, we need to arrange to save $18 in the prologue. We do this
7031 by marking the function call as using the register. The prologue
7032 will later see that it is used, and emit code to save it. */
7034 CALL_INSN_FUNCTION_USAGE (insn
) =
7035 gen_rtx_EXPR_LIST (VOIDmode
,
7036 gen_rtx_CLOBBER (VOIDmode
,
7037 gen_rtx_REG (word_mode
, 18)),
7038 CALL_INSN_FUNCTION_USAGE (insn
));
7043 /* Expand a call of type TYPE. RESULT is where the result will go (null
7044 for "call"s and "sibcall"s), ADDR is the address of the function,
7045 ARGS_SIZE is the size of the arguments and AUX is the value passed
7046 to us by mips_function_arg. LAZY_P is true if this call already
7047 involves a lazily-bound function address (such as when calling
7048 functions through a MIPS16 hard-float stub).
7050 Return the call itself. */
7053 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
7054 rtx args_size
, rtx aux
, bool lazy_p
)
7056 rtx orig_addr
, pattern
, insn
;
7059 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
7060 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
7063 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
7068 if (!call_insn_operand (addr
, VOIDmode
))
7070 if (type
== MIPS_CALL_EPILOGUE
)
7071 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
7073 addr
= gen_reg_rtx (Pmode
);
7074 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
7079 rtx (*fn
) (rtx
, rtx
);
7081 if (type
== MIPS_CALL_SIBCALL
)
7082 fn
= gen_sibcall_internal
;
7084 fn
= gen_call_internal
;
7086 pattern
= fn (addr
, args_size
);
7088 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
7090 /* Handle return values created by mips_return_fpr_pair. */
7091 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
7094 if (type
== MIPS_CALL_SIBCALL
)
7095 fn
= gen_sibcall_value_multiple_internal
;
7097 fn
= gen_call_value_multiple_internal
;
7099 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
7100 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
7101 pattern
= fn (reg1
, addr
, args_size
, reg2
);
7105 rtx (*fn
) (rtx
, rtx
, rtx
);
7107 if (type
== MIPS_CALL_SIBCALL
)
7108 fn
= gen_sibcall_value_internal
;
7110 fn
= gen_call_value_internal
;
7112 /* Handle return values created by mips_return_fpr_single. */
7113 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
7114 result
= XEXP (XVECEXP (result
, 0, 0), 0);
7115 pattern
= fn (result
, addr
, args_size
);
7118 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
7121 /* Split call instruction INSN into a $gp-clobbering call and
7122 (where necessary) an instruction to restore $gp from its save slot.
7123 CALL_PATTERN is the pattern of the new call. */
7126 mips_split_call (rtx insn
, rtx call_pattern
)
7128 emit_call_insn (call_pattern
);
7129 if (!find_reg_note (insn
, REG_NORETURN
, 0))
7130 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
,
7131 POST_CALL_TMP_REG
));
7134 /* Return true if a call to DECL may need to use JALX. */
7137 mips_call_may_need_jalx_p (tree decl
)
7139 /* If the current translation unit would use a different mode for DECL,
7140 assume that the call needs JALX. */
7141 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
7144 /* mips_get_compress_mode is always accurate for locally-binding
7145 functions in the current translation unit. */
7146 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
7149 /* When -minterlink-compressed is in effect, assume that functions
7150 could use a different encoding mode unless an attribute explicitly
7151 tells us otherwise. */
7152 if (TARGET_INTERLINK_COMPRESSED
)
7154 if (!TARGET_COMPRESSION
7155 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
7157 if (TARGET_COMPRESSION
7158 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
7165 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7168 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7170 if (!TARGET_SIBCALLS
)
7173 /* Interrupt handlers need special epilogue code and therefore can't
7175 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7178 /* Direct Js are only possible to functions that use the same ISA encoding.
7179 There is no JX counterpoart of JALX. */
7181 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7182 && mips_call_may_need_jalx_p (decl
))
7185 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7186 require $gp to be valid on entry, so sibcalls can only use stubs
7187 if $gp is call-clobbered. */
7189 && TARGET_CALL_SAVED_GP
7190 && !TARGET_ABICALLS_PIC0
7191 && !targetm
.binds_local_p (decl
))
7198 /* Emit code to move general operand SRC into condition-code
7199 register DEST given that SCRATCH is a scratch TFmode FPR.
7206 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
7209 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
7213 /* Change the source to SFmode. */
7215 src
= adjust_address (src
, SFmode
, 0);
7216 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
7217 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
7219 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
7220 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
7222 mips_emit_move (copy_rtx (fp1
), src
);
7223 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
7224 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
7227 /* Implement MOVE_BY_PIECES_P. */
7230 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7234 /* movmemsi is meant to generate code that is at least as good as
7235 move_by_pieces. However, movmemsi effectively uses a by-pieces
7236 implementation both for moves smaller than a word and for
7237 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7238 bytes. We should allow the tree-level optimisers to do such
7239 moves by pieces, as it often exposes other optimization
7240 opportunities. We might as well continue to use movmemsi at
7241 the rtl level though, as it produces better code when
7242 scheduling is disabled (such as at -O). */
7243 if (currently_expanding_to_rtl
)
7245 if (align
< BITS_PER_WORD
)
7246 return size
< UNITS_PER_WORD
;
7247 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7249 /* The default value. If this becomes a target hook, we should
7250 call the default definition instead. */
7251 return (move_by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1)
7252 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7255 /* Implement STORE_BY_PIECES_P. */
7258 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7260 /* Storing by pieces involves moving constants into registers
7261 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7262 We need to decide whether it is cheaper to load the address of
7263 constant data into a register and use a block move instead. */
7265 /* If the data is only byte aligned, then:
7267 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7268 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7271 (a2) A block move of 4 bytes from aligned source data can use an
7272 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7273 4 SBs that we would generate when storing by pieces. */
7274 if (align
<= BITS_PER_UNIT
)
7277 /* If the data is 2-byte aligned, then:
7279 (b1) A block move of less than 4 bytes would use a combination of LBs,
7280 LHs, SBs and SHs. We get better code by using single-instruction
7281 LIs, SBs and SHs instead.
7283 (b2) A block move of 4 bytes from aligned source data would again use
7284 an LW/SWL/SWR sequence. In most cases, loading the address of
7285 the source data would require at least one extra instruction.
7286 It is often more efficient to use 2 single-instruction LIs and
7289 (b3) A block move of up to 3 additional bytes would be like (b1).
7291 (b4) A block move of 8 bytes from aligned source data can use two
7292 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7293 sequences are better than the 4 LIs and 4 SHs that we'd generate
7294 when storing by pieces.
7296 The reasoning for higher alignments is similar:
7298 (c1) A block move of less than 4 bytes would be the same as (b1).
7300 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7301 loading the address of the source data would typically require
7302 at least one extra instruction. It is generally better to use
7305 (c3) A block move of up to 3 additional bytes would be like (b1).
7307 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7308 LD/SD sequence, and in these cases we've traditionally preferred
7309 the memory copy over the more bulky constant moves. */
7313 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7314 Assume that the areas do not overlap. */
7317 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7319 HOST_WIDE_INT offset
, delta
;
7320 unsigned HOST_WIDE_INT bits
;
7322 enum machine_mode mode
;
7325 /* Work out how many bits to move at a time. If both operands have
7326 half-word alignment, it is usually better to move in half words.
7327 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7328 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7329 Otherwise move word-sized chunks. */
7330 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7331 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7332 bits
= BITS_PER_WORD
/ 2;
7334 bits
= BITS_PER_WORD
;
7336 mode
= mode_for_size (bits
, MODE_INT
, 0);
7337 delta
= bits
/ BITS_PER_UNIT
;
7339 /* Allocate a buffer for the temporary registers. */
7340 regs
= XALLOCAVEC (rtx
, length
/ delta
);
7342 /* Load as many BITS-sized chunks as possible. Use a normal load if
7343 the source has enough alignment, otherwise use left/right pairs. */
7344 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7346 regs
[i
] = gen_reg_rtx (mode
);
7347 if (MEM_ALIGN (src
) >= bits
)
7348 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
7351 rtx part
= adjust_address (src
, BLKmode
, offset
);
7352 set_mem_size (part
, delta
);
7353 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
7358 /* Copy the chunks to the destination. */
7359 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7360 if (MEM_ALIGN (dest
) >= bits
)
7361 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
7364 rtx part
= adjust_address (dest
, BLKmode
, offset
);
7365 set_mem_size (part
, delta
);
7366 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
7370 /* Mop up any left-over bytes. */
7371 if (offset
< length
)
7373 src
= adjust_address (src
, BLKmode
, offset
);
7374 dest
= adjust_address (dest
, BLKmode
, offset
);
7375 move_by_pieces (dest
, src
, length
- offset
,
7376 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
7380 /* Helper function for doing a loop-based block operation on memory
7381 reference MEM. Each iteration of the loop will operate on LENGTH
7384 Create a new base register for use within the loop and point it to
7385 the start of MEM. Create a new memory reference that uses this
7386 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7389 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
7390 rtx
*loop_reg
, rtx
*loop_mem
)
7392 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
7394 /* Although the new mem does not refer to a known location,
7395 it does keep up to LENGTH bytes of alignment. */
7396 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
7397 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
7400 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7401 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7402 the memory regions do not overlap. */
7405 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
7406 HOST_WIDE_INT bytes_per_iter
)
7408 rtx label
, src_reg
, dest_reg
, final_src
, test
;
7409 HOST_WIDE_INT leftover
;
7411 leftover
= length
% bytes_per_iter
;
7414 /* Create registers and memory references for use within the loop. */
7415 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
7416 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
7418 /* Calculate the value that SRC_REG should have after the last iteration
7420 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
7423 /* Emit the start of the loop. */
7424 label
= gen_label_rtx ();
7427 /* Emit the loop body. */
7428 mips_block_move_straight (dest
, src
, bytes_per_iter
);
7430 /* Move on to the next block. */
7431 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
7432 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
7434 /* Emit the loop condition. */
7435 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7436 if (Pmode
== DImode
)
7437 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7439 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7441 /* Mop up any left-over bytes. */
7443 mips_block_move_straight (dest
, src
, leftover
);
7446 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7447 memory reference SRC to memory reference DEST. */
7450 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7452 if (CONST_INT_P (length
))
7454 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7456 mips_block_move_straight (dest
, src
, INTVAL (length
));
7461 mips_block_move_loop (dest
, src
, INTVAL (length
),
7462 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7469 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7472 mips_expand_synci_loop (rtx begin
, rtx end
)
7474 rtx inc
, label
, end_label
, cmp_result
, mask
, length
;
7476 /* Create end_label. */
7477 end_label
= gen_label_rtx ();
7479 /* Check if begin equals end. */
7480 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7481 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7483 /* Load INC with the cache line size (rdhwr INC,$1). */
7484 inc
= gen_reg_rtx (Pmode
);
7485 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7487 /* Check if inc is 0. */
7488 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7489 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7491 /* Calculate mask. */
7492 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7494 /* Mask out begin by mask. */
7495 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7497 /* Calculate length. */
7498 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7500 /* Loop back to here. */
7501 label
= gen_label_rtx ();
7504 emit_insn (gen_synci (begin
));
7506 /* Update length. */
7507 mips_emit_binary (MINUS
, length
, length
, inc
);
7510 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7512 /* Check if length is greater than 0. */
7513 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7514 emit_jump_insn (gen_condjump (cmp_result
, label
));
7516 emit_label (end_label
);
7519 /* Expand a QI or HI mode atomic memory operation.
7521 GENERATOR contains a pointer to the gen_* function that generates
7522 the SI mode underlying atomic operation using masks that we
7525 RESULT is the return register for the operation. Its value is NULL
7528 MEM is the location of the atomic access.
7530 OLDVAL is the first operand for the operation.
7532 NEWVAL is the optional second operand for the operation. Its value
7533 is NULL if unused. */
7536 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7537 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7539 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7540 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7542 enum machine_mode mode
;
7544 mode
= GET_MODE (mem
);
7546 /* Compute the address of the containing SImode value. */
7547 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7548 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7549 force_reg (Pmode
, GEN_INT (-4)));
7551 /* Create a memory reference for it. */
7552 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7553 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7554 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7556 /* Work out the byte offset of the QImode or HImode value,
7557 counting from the least significant byte. */
7558 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7559 if (TARGET_BIG_ENDIAN
)
7560 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7562 /* Multiply by eight to convert the shift value from bytes to bits. */
7563 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7565 /* Make the final shift an SImode value, so that it can be used in
7566 SImode operations. */
7567 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7569 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7570 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7571 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7572 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7574 /* Compute the equivalent exclusive mask. */
7575 inverted_mask
= gen_reg_rtx (SImode
);
7576 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
7577 gen_rtx_NOT (SImode
, mask
)));
7579 /* Shift the old value into place. */
7580 if (oldval
!= const0_rtx
)
7582 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7583 oldval
= force_reg (SImode
, oldval
);
7584 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7587 /* Do the same for the new value. */
7588 if (newval
&& newval
!= const0_rtx
)
7590 newval
= convert_modes (SImode
, mode
, newval
, true);
7591 newval
= force_reg (SImode
, newval
);
7592 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7595 /* Do the SImode atomic access. */
7597 res
= gen_reg_rtx (SImode
);
7599 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7601 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7603 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7609 /* Shift and convert the result. */
7610 mips_emit_binary (AND
, res
, res
, mask
);
7611 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7612 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7616 /* Return true if it is possible to use left/right accesses for a
7617 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7618 When returning true, update *LEFT and *RIGHT as follows:
7620 *LEFT is a QImode reference to the first byte if big endian or
7621 the last byte if little endian. This address can be used in the
7622 left-side instructions (LWL, SWL, LDL, SDL).
7624 *RIGHT is a QImode reference to the opposite end of the field and
7625 can be used in the patterning right-side instruction. */
7628 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7629 rtx
*left
, rtx
*right
)
7633 /* Check that the size is valid. */
7634 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7637 /* We can only access byte-aligned values. Since we are always passed
7638 a reference to the first byte of the field, it is not necessary to
7639 do anything with BITPOS after this check. */
7640 if (bitpos
% BITS_PER_UNIT
!= 0)
7643 /* Reject aligned bitfields: we want to use a normal load or store
7644 instead of a left/right pair. */
7645 if (MEM_ALIGN (op
) >= width
)
7648 /* Get references to both ends of the field. */
7649 first
= adjust_address (op
, QImode
, 0);
7650 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7652 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7653 correspond to the MSB and RIGHT to the LSB. */
7654 if (TARGET_BIG_ENDIAN
)
7655 *left
= first
, *right
= last
;
7657 *left
= last
, *right
= first
;
7662 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7663 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7664 the operation is the equivalent of:
7666 (set DEST (*_extract SRC WIDTH BITPOS))
7668 Return true on success. */
7671 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7672 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7674 rtx left
, right
, temp
;
7675 rtx dest1
= NULL_RTX
;
7677 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7678 be a DImode, create a new temp and emit a zero extend at the end. */
7679 if (GET_MODE (dest
) == DImode
7681 && GET_MODE_BITSIZE (SImode
) == width
)
7684 dest
= gen_reg_rtx (SImode
);
7687 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
7690 temp
= gen_reg_rtx (GET_MODE (dest
));
7691 if (GET_MODE (dest
) == DImode
)
7693 emit_insn (gen_mov_ldl (temp
, src
, left
));
7694 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7698 emit_insn (gen_mov_lwl (temp
, src
, left
));
7699 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7702 /* If we were loading 32bits and the original register was DI then
7703 sign/zero extend into the orignal dest. */
7707 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7709 emit_insn (gen_extendsidi2 (dest1
, dest
));
7714 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7715 BITPOS and SRC are the operands passed to the expander; the operation
7716 is the equivalent of:
7718 (set (zero_extract DEST WIDTH BITPOS) SRC)
7720 Return true on success. */
7723 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7724 HOST_WIDE_INT bitpos
)
7727 enum machine_mode mode
;
7729 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
7732 mode
= mode_for_size (width
, MODE_INT
, 0);
7733 src
= gen_lowpart (mode
, src
);
7736 emit_insn (gen_mov_sdl (dest
, src
, left
));
7737 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7741 emit_insn (gen_mov_swl (dest
, src
, left
));
7742 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7747 /* Return true if X is a MEM with the same size as MODE. */
7750 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
7753 && MEM_SIZE_KNOWN_P (x
)
7754 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7757 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7758 source of an "ext" instruction or the destination of an "ins"
7759 instruction. OP must be a register operand and the following
7760 conditions must hold:
7762 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7763 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7764 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7766 Also reject lengths equal to a word as they are better handled
7767 by the move patterns. */
7770 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7772 if (!ISA_HAS_EXT_INS
7773 || !register_operand (op
, VOIDmode
)
7774 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7777 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7780 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7786 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7787 operation if MAXLEN is the maxium length of consecutive bits that
7788 can make up MASK. MODE is the mode of the operation. See
7789 mask_low_and_shift_len for the actual definition. */
7792 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7794 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7797 /* Return true iff OP1 and OP2 are valid operands together for the
7798 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7799 see the table in the comment before the pattern. */
7802 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7804 return (memory_operand (op1
, mode
)
7805 ? and_load_operand (op2
, mode
)
7806 : and_reg_operand (op2
, mode
));
7809 /* The canonical form of a mask-low-and-shift-left operation is
7810 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7811 cleared. Thus we need to shift MASK to the right before checking if it
7812 is a valid mask value. MODE is the mode of the operation. If true
7813 return the length of the mask, otherwise return -1. */
7816 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7818 HOST_WIDE_INT shval
;
7820 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7821 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7824 /* Return true if -msplit-addresses is selected and should be honored.
7826 -msplit-addresses is a half-way house between explicit relocations
7827 and the traditional assembler macros. It can split absolute 32-bit
7828 symbolic constants into a high/lo_sum pair but uses macros for other
7831 Like explicit relocation support for REL targets, it relies
7832 on GNU extensions in the assembler and the linker.
7834 Although this code should work for -O0, it has traditionally
7835 been treated as an optimization. */
7838 mips_split_addresses_p (void)
7840 return (TARGET_SPLIT_ADDRESSES
7844 && !ABI_HAS_64BIT_SYMBOLS
);
7847 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7850 mips_init_relocs (void)
7852 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7853 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7854 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
7855 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7856 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7858 if (TARGET_MIPS16_PCREL_LOADS
)
7859 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
7862 if (ABI_HAS_64BIT_SYMBOLS
)
7864 if (TARGET_EXPLICIT_RELOCS
)
7866 mips_split_p
[SYMBOL_64_HIGH
] = true;
7867 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7868 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7870 mips_split_p
[SYMBOL_64_MID
] = true;
7871 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7872 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7874 mips_split_p
[SYMBOL_64_LOW
] = true;
7875 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7876 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7878 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7879 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7884 if (TARGET_EXPLICIT_RELOCS
7885 || mips_split_addresses_p ()
7888 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7889 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7890 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7897 /* The high part is provided by a pseudo copy of $gp. */
7898 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7899 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7901 else if (TARGET_EXPLICIT_RELOCS
)
7902 /* Small data constants are kept whole until after reload,
7903 then lowered by mips_rewrite_small_data. */
7904 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7906 if (TARGET_EXPLICIT_RELOCS
)
7908 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7911 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7912 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7916 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7917 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7920 /* Expose the use of $28 as soon as possible. */
7921 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7925 /* The HIGH and LO_SUM are matched by special .md patterns. */
7926 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7928 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7929 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7930 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7932 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7933 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7934 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7939 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7941 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7942 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7944 /* Expose the use of $28 as soon as possible. */
7945 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7951 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7952 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7953 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7956 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7957 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7959 if (TARGET_MIPS16_PCREL_LOADS
)
7961 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
7962 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
7966 mips_split_p
[SYMBOL_DTPREL
] = true;
7967 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7968 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7970 mips_split_p
[SYMBOL_TPREL
] = true;
7971 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7972 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7975 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7976 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7979 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7980 in context CONTEXT. RELOCS is the array of relocations to use. */
7983 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7984 const char **relocs
)
7986 enum mips_symbol_type symbol_type
;
7989 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7990 gcc_assert (relocs
[symbol_type
]);
7992 fputs (relocs
[symbol_type
], file
);
7993 output_addr_const (file
, mips_strip_unspec_address (op
));
7994 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7999 /* Start a new block with the given asm switch enabled. If we need
8000 to print a directive, emit PREFIX before it and SUFFIX after it. */
8003 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8004 const char *prefix
, const char *suffix
)
8006 if (asm_switch
->nesting_level
== 0)
8007 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
8008 asm_switch
->nesting_level
++;
8011 /* Likewise, but end a block. */
8014 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8015 const char *prefix
, const char *suffix
)
8017 gcc_assert (asm_switch
->nesting_level
);
8018 asm_switch
->nesting_level
--;
8019 if (asm_switch
->nesting_level
== 0)
8020 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
8023 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
8024 that either print a complete line or print nothing. */
8027 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
8029 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
8033 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
8035 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
8038 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
8039 The punctuation characters are:
8041 '(' Start a nested ".set noreorder" block.
8042 ')' End a nested ".set noreorder" block.
8043 '[' Start a nested ".set noat" block.
8044 ']' End a nested ".set noat" block.
8045 '<' Start a nested ".set nomacro" block.
8046 '>' End a nested ".set nomacro" block.
8047 '*' Behave like %(%< if generating a delayed-branch sequence.
8048 '#' Print a nop if in a ".set noreorder" block.
8049 '/' Like '#', but do nothing within a delayed-branch sequence.
8050 '?' Print "l" if mips_branch_likely is true
8051 '~' Print a nop if mips_branch_likely is true
8052 '.' Print the name of the register with a hard-wired zero (zero or $0).
8053 '@' Print the name of the assembler temporary register (at or $1).
8054 '^' Print the name of the pic call-through register (t9 or $25).
8055 '+' Print the name of the gp register (usually gp or $28).
8056 '$' Print the name of the stack pointer register (sp or $29).
8057 ':' Print "c" to use the compact version if the delay slot is a nop.
8058 '!' Print "s" to use the short version if the delay slot contains a
8061 See also mips_init_print_operand_pucnt. */
8064 mips_print_operand_punctuation (FILE *file
, int ch
)
8069 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
8073 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
8077 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
8081 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
8085 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
8089 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
8093 if (final_sequence
!= 0)
8095 mips_print_operand_punctuation (file
, '(');
8096 mips_print_operand_punctuation (file
, '<');
8101 if (mips_noreorder
.nesting_level
> 0)
8102 fputs ("\n\tnop", file
);
8106 /* Print an extra newline so that the delayed insn is separated
8107 from the following ones. This looks neater and is consistent
8108 with non-nop delayed sequences. */
8109 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
8110 fputs ("\n\tnop\n", file
);
8114 if (mips_branch_likely
)
8119 if (mips_branch_likely
)
8120 fputs ("\n\tnop", file
);
8124 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
8128 fputs (reg_names
[AT_REGNUM
], file
);
8132 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
8136 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
8140 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
8144 /* When final_sequence is 0, the delay slot will be a nop. We can
8145 use the compact version for microMIPS. */
8146 if (final_sequence
== 0)
8151 /* If the delay slot instruction is short, then use the
8153 if (final_sequence
== 0
8154 || get_attr_length (XVECEXP (final_sequence
, 0, 1)) == 2)
8164 /* Initialize mips_print_operand_punct. */
8167 mips_init_print_operand_punct (void)
8171 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
8172 mips_print_operand_punct
[(unsigned char) *p
] = true;
8175 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8176 associated with condition CODE. Print the condition part of the
8180 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8194 /* Conveniently, the MIPS names for these conditions are the same
8195 as their RTL equivalents. */
8196 fputs (GET_RTX_NAME (code
), file
);
8200 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8205 /* Likewise floating-point branches. */
8208 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8213 fputs ("c1f", file
);
8217 fputs ("c1t", file
);
8221 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8226 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8229 mips_print_operand_punct_valid_p (unsigned char code
)
8231 return mips_print_operand_punct
[code
];
8234 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8236 'X' Print CONST_INT OP in hexadecimal format.
8237 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8238 'd' Print CONST_INT OP in decimal.
8239 'm' Print one less than CONST_INT OP in decimal.
8240 'h' Print the high-part relocation associated with OP, after stripping
8242 'R' Print the low-part relocation associated with OP.
8243 'C' Print the integer branch condition for comparison OP.
8244 'N' Print the inverse of the integer branch condition for comparison OP.
8245 'F' Print the FPU branch condition for comparison OP.
8246 'W' Print the inverse of the FPU branch condition for comparison OP.
8247 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8248 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8249 't' Like 'T', but with the EQ/NE cases reversed
8250 'Y' Print mips_fp_conditions[INTVAL (OP)]
8251 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8252 'q' Print a DSP accumulator register.
8253 'D' Print the second part of a double-word register or memory operand.
8254 'L' Print the low-order register in a double-word register operand.
8255 'M' Print high-order register in a double-word register operand.
8256 'z' Print $0 if OP is zero, otherwise print OP normally.
8257 'b' Print the address of a memory operand, without offset. */
8260 mips_print_operand (FILE *file
, rtx op
, int letter
)
8264 if (mips_print_operand_punct_valid_p (letter
))
8266 mips_print_operand_punctuation (file
, letter
);
8271 code
= GET_CODE (op
);
8276 if (CONST_INT_P (op
))
8277 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8279 output_operand_lossage ("invalid use of '%%%c'", letter
);
8283 if (CONST_INT_P (op
))
8284 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8286 output_operand_lossage ("invalid use of '%%%c'", letter
);
8290 if (CONST_INT_P (op
))
8291 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8293 output_operand_lossage ("invalid use of '%%%c'", letter
);
8297 if (CONST_INT_P (op
))
8298 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
8300 output_operand_lossage ("invalid use of '%%%c'", letter
);
8306 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
8310 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
8314 mips_print_int_branch_condition (file
, code
, letter
);
8318 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
8322 mips_print_float_branch_condition (file
, code
, letter
);
8326 mips_print_float_branch_condition (file
, reverse_condition (code
),
8333 int truth
= (code
== NE
) == (letter
== 'T');
8334 fputc ("zfnt"[truth
* 2 + ST_REG_P (REGNO (XEXP (op
, 0)))], file
);
8339 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
8340 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
8342 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8349 mips_print_operand (file
, op
, 0);
8355 if (code
== REG
&& MD_REG_P (REGNO (op
)))
8356 fprintf (file
, "$ac0");
8357 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
8358 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
8360 output_operand_lossage ("invalid use of '%%%c'", letter
);
8368 unsigned int regno
= REGNO (op
);
8369 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
8370 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
8373 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
8374 output_operand_lossage ("invalid use of '%%%c'", letter
);
8375 /* We need to print $0 .. $31 for COP0 registers. */
8376 if (COP0_REG_P (regno
))
8377 fprintf (file
, "$%s", ®_names
[regno
][4]);
8379 fprintf (file
, "%s", reg_names
[regno
]);
8385 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
8386 else if (letter
== 'b')
8388 gcc_assert (REG_P (XEXP (op
, 0)));
8389 mips_print_operand (file
, XEXP (op
, 0), 0);
8391 else if (letter
&& letter
!= 'z')
8392 output_operand_lossage ("invalid use of '%%%c'", letter
);
8394 output_address (XEXP (op
, 0));
8398 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
8399 fputs (reg_names
[GP_REG_FIRST
], file
);
8400 else if (letter
&& letter
!= 'z')
8401 output_operand_lossage ("invalid use of '%%%c'", letter
);
8402 else if (CONST_GP_P (op
))
8403 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
8405 output_addr_const (file
, mips_strip_unspec_address (op
));
8411 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8414 mips_print_operand_address (FILE *file
, rtx x
)
8416 struct mips_address_info addr
;
8418 if (mips_classify_address (&addr
, x
, word_mode
, true))
8422 mips_print_operand (file
, addr
.offset
, 0);
8423 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8426 case ADDRESS_LO_SUM
:
8427 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8429 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8432 case ADDRESS_CONST_INT
:
8433 output_addr_const (file
, x
);
8434 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8437 case ADDRESS_SYMBOLIC
:
8438 output_addr_const (file
, mips_strip_unspec_address (x
));
8444 /* Implement TARGET_ENCODE_SECTION_INFO. */
8447 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8449 default_encode_section_info (decl
, rtl
, first
);
8451 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8453 rtx symbol
= XEXP (rtl
, 0);
8454 tree type
= TREE_TYPE (decl
);
8456 /* Encode whether the symbol is short or long. */
8457 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8458 || mips_far_type_p (type
))
8459 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8463 /* Implement TARGET_SELECT_RTX_SECTION. */
8466 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
8467 unsigned HOST_WIDE_INT align
)
8469 /* ??? Consider using mergeable small data sections. */
8470 if (mips_rtx_constant_in_small_data_p (mode
))
8471 return get_named_section (NULL
, ".sdata", 0);
8473 return default_elf_select_rtx_section (mode
, x
, align
);
8476 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8478 The complication here is that, with the combination TARGET_ABICALLS
8479 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8480 absolute addresses, and should therefore not be included in the
8481 read-only part of a DSO. Handle such cases by selecting a normal
8482 data section instead of a read-only one. The logic apes that in
8483 default_function_rodata_section. */
8486 mips_function_rodata_section (tree decl
)
8488 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8489 return default_function_rodata_section (decl
);
8491 if (decl
&& DECL_SECTION_NAME (decl
))
8493 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8494 if (DECL_COMDAT_GROUP (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8496 char *rname
= ASTRDUP (name
);
8498 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8500 else if (flag_function_sections
8501 && flag_data_sections
8502 && strncmp (name
, ".text.", 6) == 0)
8504 char *rname
= ASTRDUP (name
);
8505 memcpy (rname
+ 1, "data", 4);
8506 return get_section (rname
, SECTION_WRITE
, decl
);
8509 return data_section
;
8512 /* Implement TARGET_IN_SMALL_DATA_P. */
8515 mips_in_small_data_p (const_tree decl
)
8517 unsigned HOST_WIDE_INT size
;
8519 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8522 /* We don't yet generate small-data references for -mabicalls
8523 or VxWorks RTP code. See the related -G handling in
8524 mips_option_override. */
8525 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8528 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8532 /* Reject anything that isn't in a known small-data section. */
8533 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8534 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8537 /* If a symbol is defined externally, the assembler will use the
8538 usual -G rules when deciding how to implement macros. */
8539 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8542 else if (TARGET_EMBEDDED_DATA
)
8544 /* Don't put constants into the small data section: we want them
8545 to be in ROM rather than RAM. */
8546 if (TREE_CODE (decl
) != VAR_DECL
)
8549 if (TREE_READONLY (decl
)
8550 && !TREE_SIDE_EFFECTS (decl
)
8551 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8555 /* Enforce -mlocal-sdata. */
8556 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8559 /* Enforce -mextern-sdata. */
8560 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8562 if (DECL_EXTERNAL (decl
))
8564 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8568 /* We have traditionally not treated zero-sized objects as small data,
8569 so this is now effectively part of the ABI. */
8570 size
= int_size_in_bytes (TREE_TYPE (decl
));
8571 return size
> 0 && size
<= mips_small_data_threshold
;
8574 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8575 anchors for small data: the GP register acts as an anchor in that
8576 case. We also don't want to use them for PC-relative accesses,
8577 where the PC acts as an anchor. */
8580 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8582 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8584 case SYMBOL_PC_RELATIVE
:
8585 case SYMBOL_GP_RELATIVE
:
8589 return default_use_anchors_for_symbol_p (symbol
);
8593 /* The MIPS debug format wants all automatic variables and arguments
8594 to be in terms of the virtual frame pointer (stack pointer before
8595 any adjustment in the function), while the MIPS 3.0 linker wants
8596 the frame pointer to be the stack pointer after the initial
8597 adjustment. So, we do the adjustment here. The arg pointer (which
8598 is eliminated) points to the virtual frame pointer, while the frame
8599 pointer (which may be eliminated) points to the stack pointer after
8600 the initial adjustments. */
8603 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8605 rtx offset2
= const0_rtx
;
8606 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8609 offset
= INTVAL (offset2
);
8611 if (reg
== stack_pointer_rtx
8612 || reg
== frame_pointer_rtx
8613 || reg
== hard_frame_pointer_rtx
)
8615 offset
-= cfun
->machine
->frame
.total_size
;
8616 if (reg
== hard_frame_pointer_rtx
)
8617 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8623 /* Implement ASM_OUTPUT_EXTERNAL. */
8626 mips_output_external (FILE *file
, tree decl
, const char *name
)
8628 default_elf_asm_output_external (file
, decl
, name
);
8630 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8631 set in order to avoid putting out names that are never really
8633 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8635 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8637 /* When using assembler macros, emit .extern directives for
8638 all small-data externs so that the assembler knows how
8641 In most cases it would be safe (though pointless) to emit
8642 .externs for other symbols too. One exception is when an
8643 object is within the -G limit but declared by the user to
8644 be in a section other than .sbss or .sdata. */
8645 fputs ("\t.extern\t", file
);
8646 assemble_name (file
, name
);
8647 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8648 int_size_in_bytes (TREE_TYPE (decl
)));
8653 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8656 mips_output_filename (FILE *stream
, const char *name
)
8658 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8660 if (write_symbols
== DWARF2_DEBUG
)
8662 else if (mips_output_filename_first_time
)
8664 mips_output_filename_first_time
= 0;
8665 num_source_filenames
+= 1;
8666 current_function_file
= name
;
8667 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8668 output_quoted_string (stream
, name
);
8669 putc ('\n', stream
);
8671 /* If we are emitting stabs, let dbxout.c handle this (except for
8672 the mips_output_filename_first_time case). */
8673 else if (write_symbols
== DBX_DEBUG
)
8675 else if (name
!= current_function_file
8676 && strcmp (name
, current_function_file
) != 0)
8678 num_source_filenames
+= 1;
8679 current_function_file
= name
;
8680 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8681 output_quoted_string (stream
, name
);
8682 putc ('\n', stream
);
8686 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8688 static void ATTRIBUTE_UNUSED
8689 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8694 fputs ("\t.dtprelword\t", file
);
8698 fputs ("\t.dtpreldword\t", file
);
8704 output_addr_const (file
, x
);
8705 fputs ("+0x8000", file
);
8708 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8711 mips_dwarf_register_span (rtx reg
)
8714 enum machine_mode mode
;
8716 /* By default, GCC maps increasing register numbers to increasing
8717 memory locations, but paired FPRs are always little-endian,
8718 regardless of the prevailing endianness. */
8719 mode
= GET_MODE (reg
);
8720 if (FP_REG_P (REGNO (reg
))
8721 && TARGET_BIG_ENDIAN
8722 && MAX_FPRS_PER_FMT
> 1
8723 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8725 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8726 high
= mips_subword (reg
, true);
8727 low
= mips_subword (reg
, false);
8728 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8734 /* DSP ALU can bypass data with no delays for the following pairs. */
8735 enum insn_code dspalu_bypass_table
[][2] =
8737 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
8738 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
8739 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
8740 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
8741 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
8742 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
8743 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
8744 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
8748 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
8751 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
8752 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
8753 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
8755 for (i
= 0; i
< num_bypass
; i
++)
8757 if (out_icode
== dspalu_bypass_table
[i
][0]
8758 && in_icode
== dspalu_bypass_table
[i
][1])
8764 /* Implement ASM_OUTPUT_ASCII. */
8767 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8773 fprintf (stream
, "\t.ascii\t\"");
8774 for (i
= 0; i
< len
; i
++)
8778 c
= (unsigned char) string
[i
];
8781 if (c
== '\\' || c
== '\"')
8783 putc ('\\', stream
);
8791 fprintf (stream
, "\\%03o", c
);
8795 if (cur_pos
> 72 && i
+1 < len
)
8798 fprintf (stream
, "\"\n\t.ascii\t\"");
8801 fprintf (stream
, "\"\n");
8804 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8805 Update *ADDR with the operand that should be printed. */
8808 mips_output_tls_reloc_directive (rtx
*addr
)
8810 enum mips_symbol_type type
;
8812 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
8813 *addr
= mips_strip_unspec_address (*addr
);
8817 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
8820 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
8827 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8828 macros, mark the symbol as written so that mips_asm_output_external
8829 won't emit an .extern for it. STREAM is the output file, NAME is the
8830 name of the symbol, INIT_STRING is the string that should be written
8831 before the symbol and FINAL_STRING is the string that should be
8832 written after it. FINAL_STRING is a printf format that consumes the
8833 remaining arguments. */
8836 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
8837 const char *final_string
, ...)
8841 fputs (init_string
, stream
);
8842 assemble_name (stream
, name
);
8843 va_start (ap
, final_string
);
8844 vfprintf (stream
, final_string
, ap
);
8847 if (!TARGET_EXPLICIT_RELOCS
)
8849 tree name_tree
= get_identifier (name
);
8850 TREE_ASM_WRITTEN (name_tree
) = 1;
8854 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8855 NAME is the name of the object and ALIGN is the required alignment
8856 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8857 alignment argument. */
8860 mips_declare_common_object (FILE *stream
, const char *name
,
8861 const char *init_string
,
8862 unsigned HOST_WIDE_INT size
,
8863 unsigned int align
, bool takes_alignment_p
)
8865 if (!takes_alignment_p
)
8867 size
+= (align
/ BITS_PER_UNIT
) - 1;
8868 size
-= size
% (align
/ BITS_PER_UNIT
);
8869 mips_declare_object (stream
, name
, init_string
,
8870 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8873 mips_declare_object (stream
, name
, init_string
,
8874 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
8875 size
, align
/ BITS_PER_UNIT
);
8878 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8879 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8882 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8883 unsigned HOST_WIDE_INT size
,
8886 /* If the target wants uninitialized const declarations in
8887 .rdata then don't put them in .comm. */
8888 if (TARGET_EMBEDDED_DATA
8889 && TARGET_UNINIT_CONST_IN_RODATA
8890 && TREE_CODE (decl
) == VAR_DECL
8891 && TREE_READONLY (decl
)
8892 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8894 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8895 targetm
.asm_out
.globalize_label (stream
, name
);
8897 switch_to_section (readonly_data_section
);
8898 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8899 mips_declare_object (stream
, name
, "",
8900 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8904 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8908 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8909 extern int size_directive_output
;
8911 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8912 definitions except that it uses mips_declare_object to emit the label. */
8915 mips_declare_object_name (FILE *stream
, const char *name
,
8916 tree decl ATTRIBUTE_UNUSED
)
8918 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8919 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8922 size_directive_output
= 0;
8923 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8927 size_directive_output
= 1;
8928 size
= int_size_in_bytes (TREE_TYPE (decl
));
8929 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8932 mips_declare_object (stream
, name
, "", ":\n");
8935 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8938 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8942 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8943 if (!flag_inhibit_size_directive
8944 && DECL_SIZE (decl
) != 0
8947 && DECL_INITIAL (decl
) == error_mark_node
8948 && !size_directive_output
)
8952 size_directive_output
= 1;
8953 size
= int_size_in_bytes (TREE_TYPE (decl
));
8954 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8959 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8960 with the current ABI. */
8963 mips_mdebug_abi_name (void)
8976 return TARGET_64BIT
? "eabi64" : "eabi32";
8982 /* Implement TARGET_ASM_FILE_START. */
8985 mips_file_start (void)
8987 default_file_start ();
8989 /* Generate a special section to describe the ABI switches used to
8990 produce the resultant binary. */
8992 /* Record the ABI itself. Modern versions of binutils encode
8993 this information in the ELF header flags, but GDB needs the
8994 information in order to correctly debug binaries produced by
8995 older binutils. See the function mips_gdbarch_init in
8997 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8998 mips_mdebug_abi_name ());
9000 /* There is no ELF header flag to distinguish long32 forms of the
9001 EABI from long64 forms. Emit a special section to help tools
9002 such as GDB. Do the same for o64, which is sometimes used with
9004 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
9005 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
9006 "\t.previous\n", TARGET_LONG64
? 64 : 32);
9008 /* Record the NaN encoding. */
9009 if (HAVE_AS_NAN
|| mips_nan
!= MIPS_IEEE_754_DEFAULT
)
9010 fprintf (asm_out_file
, "\t.nan\t%s\n",
9011 mips_nan
== MIPS_IEEE_754_2008
? "2008" : "legacy");
9013 #ifdef HAVE_AS_GNU_ATTRIBUTE
9017 /* No floating-point operations, -mno-float. */
9018 if (TARGET_NO_FLOAT
)
9020 /* Soft-float code, -msoft-float. */
9021 else if (!TARGET_HARD_FLOAT_ABI
)
9023 /* Single-float code, -msingle-float. */
9024 else if (!TARGET_DOUBLE_FLOAT
)
9026 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
9027 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
9029 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
9033 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
9037 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
9038 if (TARGET_ABICALLS
)
9040 fprintf (asm_out_file
, "\t.abicalls\n");
9041 if (TARGET_ABICALLS_PIC0
)
9042 fprintf (asm_out_file
, "\t.option\tpic0\n");
9045 if (flag_verbose_asm
)
9046 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9048 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
9051 /* Implement TARGET_ASM_CODE_END. */
9054 mips_code_end (void)
9056 mips_finish_stub (&mips16_rdhwr_stub
);
9057 mips_finish_stub (&mips16_get_fcsr_stub
);
9058 mips_finish_stub (&mips16_set_fcsr_stub
);
9061 /* Make the last instruction frame-related and note that it performs
9062 the operation described by FRAME_PATTERN. */
9065 mips_set_frame_expr (rtx frame_pattern
)
9069 insn
= get_last_insn ();
9070 RTX_FRAME_RELATED_P (insn
) = 1;
9071 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
9076 /* Return a frame-related rtx that stores REG at MEM.
9077 REG must be a single register. */
9080 mips_frame_set (rtx mem
, rtx reg
)
9084 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
9085 RTX_FRAME_RELATED_P (set
) = 1;
9090 /* Record that the epilogue has restored call-saved register REG. */
9093 mips_add_cfa_restore (rtx reg
)
9095 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
9096 mips_epilogue
.cfa_restores
);
9099 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9100 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9101 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9102 static const unsigned char mips16e_s2_s8_regs
[] = {
9103 30, 23, 22, 21, 20, 19, 18
9105 static const unsigned char mips16e_a0_a3_regs
[] = {
9109 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9110 ordered from the uppermost in memory to the lowest in memory. */
9111 static const unsigned char mips16e_save_restore_regs
[] = {
9112 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9115 /* Return the index of the lowest X in the range [0, SIZE) for which
9116 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9119 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
9124 for (i
= 0; i
< size
; i
++)
9125 if (BITSET_P (mask
, regs
[i
]))
9131 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9132 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9133 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9134 is true for all indexes (X, SIZE). */
9137 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
9138 unsigned int size
, unsigned int *num_regs_ptr
)
9142 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
9143 for (i
++; i
< size
; i
++)
9144 if (!BITSET_P (*mask_ptr
, regs
[i
]))
9147 *mask_ptr
|= 1 << regs
[i
];
9151 /* Return a simplified form of X using the register values in REG_VALUES.
9152 REG_VALUES[R] is the last value assigned to hard register R, or null
9153 if R has not been modified.
9155 This function is rather limited, but is good enough for our purposes. */
9158 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
9160 x
= avoid_constant_pool_reference (x
);
9164 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9165 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
9166 x0
, GET_MODE (XEXP (x
, 0)));
9169 if (ARITHMETIC_P (x
))
9171 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9172 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
9173 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
9177 && reg_values
[REGNO (x
)]
9178 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
9179 return reg_values
[REGNO (x
)];
9184 /* Return true if (set DEST SRC) stores an argument register into its
9185 caller-allocated save slot, storing the number of that argument
9186 register in *REGNO_PTR if so. REG_VALUES is as for
9187 mips16e_collect_propagate_value. */
9190 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
9191 unsigned int *regno_ptr
)
9193 unsigned int argno
, regno
;
9194 HOST_WIDE_INT offset
, required_offset
;
9197 /* Check that this is a word-mode store. */
9198 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
9201 /* Check that the register being saved is an unmodified argument
9203 regno
= REGNO (src
);
9204 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
9206 argno
= regno
- GP_ARG_FIRST
;
9208 /* Check whether the address is an appropriate stack-pointer or
9209 frame-pointer access. */
9210 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
9211 mips_split_plus (addr
, &base
, &offset
);
9212 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
9213 if (base
== hard_frame_pointer_rtx
)
9214 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9215 else if (base
!= stack_pointer_rtx
)
9217 if (offset
!= required_offset
)
9224 /* A subroutine of mips_expand_prologue, called only when generating
9225 MIPS16e SAVE instructions. Search the start of the function for any
9226 instructions that save argument registers into their caller-allocated
9227 save slots. Delete such instructions and return a value N such that
9228 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9229 instructions redundant. */
9232 mips16e_collect_argument_saves (void)
9234 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
9235 rtx insn
, next
, set
, dest
, src
;
9236 unsigned int nargs
, regno
;
9238 push_topmost_sequence ();
9240 memset (reg_values
, 0, sizeof (reg_values
));
9241 for (insn
= get_insns (); insn
; insn
= next
)
9243 next
= NEXT_INSN (insn
);
9244 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
9250 set
= PATTERN (insn
);
9251 if (GET_CODE (set
) != SET
)
9254 dest
= SET_DEST (set
);
9255 src
= SET_SRC (set
);
9256 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
9258 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
9261 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
9264 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
9265 reg_values
[REGNO (dest
)]
9266 = mips16e_collect_propagate_value (src
, reg_values
);
9270 pop_topmost_sequence ();
9275 /* Return a move between register REGNO and memory location SP + OFFSET.
9276 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9277 Make the move a load if RESTORE_P, otherwise make it a store. */
9280 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
9281 HOST_WIDE_INT offset
, unsigned int regno
)
9285 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
9287 reg
= gen_rtx_REG (SImode
, regno
);
9290 mips_add_cfa_restore (reg
);
9291 return gen_rtx_SET (VOIDmode
, reg
, mem
);
9294 return gen_rtx_SET (VOIDmode
, mem
, reg
);
9295 return mips_frame_set (mem
, reg
);
9298 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9299 The instruction must:
9301 - Allocate or deallocate SIZE bytes in total; SIZE is known
9304 - Save or restore as many registers in *MASK_PTR as possible.
9305 The instruction saves the first registers at the top of the
9306 allocated area, with the other registers below it.
9308 - Save NARGS argument registers above the allocated area.
9310 (NARGS is always zero if RESTORE_P.)
9312 The SAVE and RESTORE instructions cannot save and restore all general
9313 registers, so there may be some registers left over for the caller to
9314 handle. Destructively modify *MASK_PTR so that it contains the registers
9315 that still need to be saved or restored. The caller can save these
9316 registers in the memory immediately below *OFFSET_PTR, which is a
9317 byte offset from the bottom of the allocated stack area. */
9320 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
9321 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
9325 HOST_WIDE_INT offset
, top_offset
;
9326 unsigned int i
, regno
;
9329 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
9331 /* Calculate the number of elements in the PARALLEL. We need one element
9332 for the stack adjustment, one for each argument register save, and one
9333 for each additional register move. */
9335 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9336 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
9339 /* Create the final PARALLEL. */
9340 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
9343 /* Add the stack pointer adjustment. */
9344 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9345 plus_constant (Pmode
, stack_pointer_rtx
,
9346 restore_p
? size
: -size
));
9347 RTX_FRAME_RELATED_P (set
) = 1;
9348 XVECEXP (pattern
, 0, n
++) = set
;
9350 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9351 top_offset
= restore_p
? size
: 0;
9353 /* Save the arguments. */
9354 for (i
= 0; i
< nargs
; i
++)
9356 offset
= top_offset
+ i
* UNITS_PER_WORD
;
9357 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
9359 XVECEXP (pattern
, 0, n
++) = set
;
9362 /* Then fill in the other register moves. */
9363 offset
= top_offset
;
9364 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9366 regno
= mips16e_save_restore_regs
[i
];
9367 if (BITSET_P (*mask_ptr
, regno
))
9369 offset
-= UNITS_PER_WORD
;
9370 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
9371 XVECEXP (pattern
, 0, n
++) = set
;
9372 *mask_ptr
&= ~(1 << regno
);
9376 /* Tell the caller what offset it should use for the remaining registers. */
9377 *offset_ptr
= size
+ (offset
- top_offset
);
9379 gcc_assert (n
== XVECLEN (pattern
, 0));
9384 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9385 pointer. Return true if PATTERN matches the kind of instruction
9386 generated by mips16e_build_save_restore. If INFO is nonnull,
9387 initialize it when returning true. */
9390 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
9391 struct mips16e_save_restore_info
*info
)
9393 unsigned int i
, nargs
, mask
, extra
;
9394 HOST_WIDE_INT top_offset
, save_offset
, offset
;
9395 rtx set
, reg
, mem
, base
;
9398 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
9401 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9402 top_offset
= adjust
> 0 ? adjust
: 0;
9404 /* Interpret all other members of the PARALLEL. */
9405 save_offset
= top_offset
- UNITS_PER_WORD
;
9409 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
9411 /* Check that we have a SET. */
9412 set
= XVECEXP (pattern
, 0, n
);
9413 if (GET_CODE (set
) != SET
)
9416 /* Check that the SET is a load (if restoring) or a store
9418 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
9422 /* Check that the address is the sum of the stack pointer and a
9423 possibly-zero constant offset. */
9424 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
9425 if (base
!= stack_pointer_rtx
)
9428 /* Check that SET's other operand is a register. */
9429 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
9433 /* Check for argument saves. */
9434 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
9435 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
9437 else if (offset
== save_offset
)
9439 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
9440 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
9443 mask
|= 1 << REGNO (reg
);
9444 save_offset
-= UNITS_PER_WORD
;
9450 /* Check that the restrictions on register ranges are met. */
9452 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
9453 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
9454 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
9455 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
9459 /* Make sure that the topmost argument register is not saved twice.
9460 The checks above ensure that the same is then true for the other
9461 argument registers. */
9462 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9465 /* Pass back information, if requested. */
9468 info
->nargs
= nargs
;
9470 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9476 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9477 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9478 the null terminator. */
9481 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9482 unsigned int max_reg
)
9484 if (min_reg
!= max_reg
)
9485 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9487 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9491 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9492 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9495 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9497 static char buffer
[300];
9499 struct mips16e_save_restore_info info
;
9500 unsigned int i
, end
;
9503 /* Parse the pattern. */
9504 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9507 /* Add the mnemonic. */
9508 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9511 /* Save the arguments. */
9513 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9514 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9515 else if (info
.nargs
== 1)
9516 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9518 /* Emit the amount of stack space to allocate or deallocate. */
9519 s
+= sprintf (s
, "%d", (int) info
.size
);
9521 /* Save or restore $16. */
9522 if (BITSET_P (info
.mask
, 16))
9523 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9525 /* Save or restore $17. */
9526 if (BITSET_P (info
.mask
, 17))
9527 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9529 /* Save or restore registers in the range $s2...$s8, which
9530 mips16e_s2_s8_regs lists in decreasing order. Note that this
9531 is a software register range; the hardware registers are not
9532 numbered consecutively. */
9533 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9534 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9536 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9537 mips16e_s2_s8_regs
[i
]);
9539 /* Save or restore registers in the range $a0...$a3. */
9540 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9541 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9543 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9544 mips16e_a0_a3_regs
[end
- 1]);
9546 /* Save or restore $31. */
9547 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9548 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9553 /* Return true if the current function returns its value in a floating-point
9554 register in MIPS16 mode. */
9557 mips16_cfun_returns_in_fpr_p (void)
9559 tree return_type
= DECL_RESULT (current_function_decl
);
9560 return (TARGET_MIPS16
9561 && TARGET_HARD_FLOAT_ABI
9562 && !aggregate_value_p (return_type
, current_function_decl
)
9563 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9566 /* Return true if predicate PRED is true for at least one instruction.
9567 Cache the result in *CACHE, and assume that the result is true
9568 if *CACHE is already true. */
9571 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx
))
9577 push_topmost_sequence ();
9578 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9579 if (USEFUL_INSN_P (insn
) && pred (insn
))
9584 pop_topmost_sequence ();
9589 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9590 See mips_cfun_has_inflexible_gp_ref_p for details. */
9593 mips_insn_has_inflexible_gp_ref_p (rtx insn
)
9595 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9596 indicate that the target could be a traditional MIPS
9597 lazily-binding stub. */
9598 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9601 /* Return true if the current function refers to the global pointer
9602 in a way that forces $28 to be valid. This means that we can't
9603 change the choice of global pointer, even for NewABI code.
9605 One example of this (and one which needs several checks) is that
9606 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9607 (This restriction does not apply to PLTs.) */
9610 mips_cfun_has_inflexible_gp_ref_p (void)
9612 /* If the function has a nonlocal goto, $28 must hold the correct
9613 global pointer for the target function. That is, the target
9614 of the goto implicitly uses $28. */
9615 if (crtl
->has_nonlocal_goto
)
9618 if (TARGET_ABICALLS_PIC2
)
9620 /* Symbolic accesses implicitly use the global pointer unless
9621 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9622 might go to traditional MIPS lazy-binding stubs. */
9623 if (!TARGET_EXPLICIT_RELOCS
)
9626 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9627 can be lazily-bound. */
9631 /* MIPS16 functions that return in FPRs need to call an
9632 external libgcc routine. This call is only made explict
9633 during mips_expand_epilogue, and it too might be lazily bound. */
9634 if (mips16_cfun_returns_in_fpr_p ())
9638 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9639 mips_insn_has_inflexible_gp_ref_p
);
9642 /* Return true if INSN refers to the global pointer in a "flexible" way.
9643 See mips_cfun_has_flexible_gp_ref_p for details. */
9646 mips_insn_has_flexible_gp_ref_p (rtx insn
)
9648 return (get_attr_got (insn
) != GOT_UNSET
9649 || mips_small_data_pattern_p (PATTERN (insn
))
9650 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9653 /* Return true if the current function references the global pointer,
9654 but if those references do not inherently require the global pointer
9655 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9658 mips_cfun_has_flexible_gp_ref_p (void)
9660 /* Reload can sometimes introduce constant pool references
9661 into a function that otherwise didn't need them. For example,
9662 suppose we have an instruction like:
9664 (set (reg:DF R1) (float:DF (reg:SI R2)))
9666 If R2 turns out to be a constant such as 1, the instruction may
9667 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9668 the option of using this constant if R2 doesn't get allocated
9671 In cases like these, reload will have added the constant to the
9672 pool but no instruction will yet refer to it. */
9673 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9676 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9677 mips_insn_has_flexible_gp_ref_p
);
9680 /* Return the register that should be used as the global pointer
9681 within this function. Return INVALID_REGNUM if the function
9682 doesn't need a global pointer. */
9685 mips_global_pointer (void)
9689 /* $gp is always available unless we're using a GOT. */
9690 if (!TARGET_USE_GOT
)
9691 return GLOBAL_POINTER_REGNUM
;
9693 /* If there are inflexible references to $gp, we must use the
9694 standard register. */
9695 if (mips_cfun_has_inflexible_gp_ref_p ())
9696 return GLOBAL_POINTER_REGNUM
;
9698 /* If there are no current references to $gp, then the only uses
9699 we can introduce later are those involved in long branches. */
9700 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9701 return INVALID_REGNUM
;
9703 /* If the global pointer is call-saved, try to use a call-clobbered
9705 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9706 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9707 if (!df_regs_ever_live_p (regno
)
9708 && call_really_used_regs
[regno
]
9709 && !fixed_regs
[regno
]
9710 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9713 return GLOBAL_POINTER_REGNUM
;
9716 /* Return true if the current function's prologue must load the global
9717 pointer value into pic_offset_table_rtx and store the same value in
9718 the function's cprestore slot (if any).
9720 One problem we have to deal with is that, when emitting GOT-based
9721 position independent code, long-branch sequences will need to load
9722 the address of the branch target from the GOT. We don't know until
9723 the very end of compilation whether (and where) the function needs
9724 long branches, so we must ensure that _any_ branch can access the
9725 global pointer in some form. However, we do not want to pessimize
9726 the usual case in which all branches are short.
9728 We handle this as follows:
9730 (1) During reload, we set cfun->machine->global_pointer to
9731 INVALID_REGNUM if we _know_ that the current function
9732 doesn't need a global pointer. This is only valid if
9733 long branches don't need the GOT.
9735 Otherwise, we assume that we might need a global pointer
9736 and pick an appropriate register.
9738 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9739 we ensure that the global pointer is available at every
9740 block boundary bar entry and exit. We do this in one of two ways:
9742 - If the function has a cprestore slot, we ensure that this
9743 slot is valid at every branch. However, as explained in
9744 point (6) below, there is no guarantee that pic_offset_table_rtx
9745 itself is valid if new uses of the global pointer are introduced
9746 after the first post-epilogue split.
9748 We guarantee that the cprestore slot is valid by loading it
9749 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9750 this register live at every block boundary bar function entry
9751 and exit. It is then invalid to move the load (and thus the
9752 preceding store) across a block boundary.
9754 - If the function has no cprestore slot, we guarantee that
9755 pic_offset_table_rtx itself is valid at every branch.
9757 See mips_eh_uses for the handling of the register liveness.
9759 (3) During prologue and epilogue generation, we emit "ghost"
9760 placeholder instructions to manipulate the global pointer.
9762 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9763 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9764 that the function needs a global pointer. (There is no need to set
9765 them earlier than this, and doing it as late as possible leads to
9766 fewer false positives.)
9768 (5) If cfun->machine->must_initialize_gp_p is true during a
9769 split_insns pass, we split the ghost instructions into real
9770 instructions. These split instructions can then be optimized in
9771 the usual way. Otherwise, we keep the ghost instructions intact,
9772 and optimize for the case where they aren't needed. We still
9773 have the option of splitting them later, if we need to introduce
9774 new uses of the global pointer.
9776 For example, the scheduler ignores a ghost instruction that
9777 stores $28 to the stack, but it handles the split form of
9778 the ghost instruction as an ordinary store.
9780 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9781 is true during the first post-epilogue split_insns pass, we split
9782 calls and restore_gp patterns into instructions that explicitly
9783 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9784 we split these patterns into instructions that _don't_ load from
9787 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9788 time of the split, then any instructions that exist at that time
9789 can make free use of pic_offset_table_rtx. However, if we want
9790 to introduce new uses of the global pointer after the split,
9791 we must explicitly load the value from the cprestore slot, since
9792 pic_offset_table_rtx itself might not be valid at a given point
9795 The idea is that we want to be able to delete redundant
9796 loads from the cprestore slot in the usual case where no
9797 long branches are needed.
9799 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9800 of md_reorg, we decide whether the global pointer is needed for
9801 long branches. If so, we set cfun->machine->must_initialize_gp_p
9802 to true and split the ghost instructions into real instructions
9805 Note that the ghost instructions must have a zero length for three reasons:
9807 - Giving the length of the underlying $gp sequence might cause
9808 us to use long branches in cases where they aren't really needed.
9810 - They would perturb things like alignment calculations.
9812 - More importantly, the hazard detection in md_reorg relies on
9813 empty instructions having a zero length.
9815 If we find a long branch and split the ghost instructions at the
9816 end of md_reorg, the split could introduce more long branches.
9817 That isn't a problem though, because we still do the split before
9818 the final shorten_branches pass.
9820 This is extremely ugly, but it seems like the best compromise between
9821 correctness and efficiency. */
9824 mips_must_initialize_gp_p (void)
9826 return cfun
->machine
->must_initialize_gp_p
;
9829 /* Return true if REGNO is a register that is ordinarily call-clobbered
9830 but must nevertheless be preserved by an interrupt handler. */
9833 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
9835 if (MD_REG_P (regno
))
9838 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
9841 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
9843 /* $0 is hard-wired. */
9844 if (regno
== GP_REG_FIRST
)
9847 /* The interrupt handler can treat kernel registers as
9848 scratch registers. */
9849 if (KERNEL_REG_P (regno
))
9852 /* The function will return the stack pointer to its original value
9854 if (regno
== STACK_POINTER_REGNUM
)
9857 /* Otherwise, return true for registers that aren't ordinarily
9859 return call_really_used_regs
[regno
];
9865 /* Return true if the current function should treat register REGNO
9869 mips_cfun_call_saved_reg_p (unsigned int regno
)
9871 /* If the user makes an ordinarily-call-saved register global,
9872 that register is no longer call-saved. */
9873 if (global_regs
[regno
])
9876 /* Interrupt handlers need to save extra registers. */
9877 if (cfun
->machine
->interrupt_handler_p
9878 && mips_interrupt_extra_call_saved_reg_p (regno
))
9881 /* call_insns preserve $28 unless they explicitly say otherwise,
9882 so call_really_used_regs[] treats $28 as call-saved. However,
9883 we want the ABI property rather than the default call_insn
9885 return (regno
== GLOBAL_POINTER_REGNUM
9886 ? TARGET_CALL_SAVED_GP
9887 : !call_really_used_regs
[regno
]);
9890 /* Return true if the function body might clobber register REGNO.
9891 We know that REGNO is call-saved. */
9894 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
9896 /* Some functions should be treated as clobbering all call-saved
9898 if (crtl
->saves_all_registers
)
9901 /* DF handles cases where a register is explicitly referenced in
9902 the rtl. Incoming values are passed in call-clobbered registers,
9903 so we can assume that any live call-saved register is set within
9905 if (df_regs_ever_live_p (regno
))
9908 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9909 These clobbers are not explicit in the rtl. */
9910 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9913 /* If we're using a call-saved global pointer, the function's
9914 prologue will need to set it up. */
9915 if (cfun
->machine
->global_pointer
== regno
)
9918 /* The function's prologue will need to set the frame pointer if
9919 frame_pointer_needed. */
9920 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9923 /* If a MIPS16 function returns a value in FPRs, its epilogue
9924 will need to call an external libgcc routine. This yet-to-be
9925 generated call_insn will clobber $31. */
9926 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9929 /* If REGNO is ordinarily call-clobbered, we must assume that any
9930 called function could modify it. */
9931 if (cfun
->machine
->interrupt_handler_p
9933 && mips_interrupt_extra_call_saved_reg_p (regno
))
9939 /* Return true if the current function must save register REGNO. */
9942 mips_save_reg_p (unsigned int regno
)
9944 if (mips_cfun_call_saved_reg_p (regno
))
9946 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9949 /* Save both registers in an FPR pair if either one is used. This is
9950 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9951 register to be used without the even register. */
9952 if (FP_REG_P (regno
)
9953 && MAX_FPRS_PER_FMT
== 2
9954 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9958 /* We need to save the incoming return address if __builtin_eh_return
9959 is being used to set a different return address. */
9960 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9966 /* Populate the current function's mips_frame_info structure.
9968 MIPS stack frames look like:
9970 +-------------------------------+
9972 | incoming stack arguments |
9974 +-------------------------------+
9976 | caller-allocated save area |
9977 A | for register arguments |
9979 +-------------------------------+ <-- incoming stack pointer
9981 | callee-allocated save area |
9982 B | for arguments that are |
9983 | split between registers and |
9986 +-------------------------------+ <-- arg_pointer_rtx
9988 C | callee-allocated save area |
9989 | for register varargs |
9991 +-------------------------------+ <-- frame_pointer_rtx
9992 | | + cop0_sp_offset
9993 | COP0 reg save area | + UNITS_PER_WORD
9995 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9996 | | + UNITS_PER_WORD
9997 | accumulator save area |
9999 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
10000 | | + UNITS_PER_HWFPVALUE
10003 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
10004 | | + UNITS_PER_WORD
10007 +-------------------------------+ <-- frame_pointer_rtx with
10008 | | \ -fstack-protector
10009 | local variables | | var_size
10011 +-------------------------------+
10013 | $gp save area | | cprestore_size
10015 P +-------------------------------+ <-- hard_frame_pointer_rtx for
10017 | outgoing stack arguments | |
10019 +-------------------------------+ | args_size
10021 | caller-allocated save area | |
10022 | for register arguments | |
10024 +-------------------------------+ <-- stack_pointer_rtx
10025 frame_pointer_rtx without
10027 hard_frame_pointer_rtx for
10030 At least two of A, B and C will be empty.
10032 Dynamic stack allocations such as alloca insert data at point P.
10033 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
10034 hard_frame_pointer_rtx unchanged. */
10037 mips_compute_frame_info (void)
10039 struct mips_frame_info
*frame
;
10040 HOST_WIDE_INT offset
, size
;
10041 unsigned int regno
, i
;
10043 /* Set this function's interrupt properties. */
10044 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
10046 if (mips_isa_rev
< 2)
10047 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
10048 else if (TARGET_HARD_FLOAT
)
10049 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
10050 else if (TARGET_MIPS16
)
10051 error ("interrupt handlers cannot be MIPS16 functions");
10054 cfun
->machine
->interrupt_handler_p
= true;
10055 cfun
->machine
->use_shadow_register_set_p
=
10056 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
10057 cfun
->machine
->keep_interrupts_masked_p
=
10058 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
10059 cfun
->machine
->use_debug_exception_return_p
=
10060 mips_use_debug_exception_return_p (TREE_TYPE
10061 (current_function_decl
));
10065 frame
= &cfun
->machine
->frame
;
10066 memset (frame
, 0, sizeof (*frame
));
10067 size
= get_frame_size ();
10069 cfun
->machine
->global_pointer
= mips_global_pointer ();
10071 /* The first two blocks contain the outgoing argument area and the $gp save
10072 slot. This area isn't needed in leaf functions, but if the
10073 target-independent frame size is nonzero, we have already committed to
10074 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
10075 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
10077 /* The MIPS 3.0 linker does not like functions that dynamically
10078 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10079 looks like we are trying to create a second frame pointer to the
10080 function, so allocate some stack space to make it happy. */
10081 if (cfun
->calls_alloca
)
10082 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
10084 frame
->args_size
= 0;
10085 frame
->cprestore_size
= 0;
10089 frame
->args_size
= crtl
->outgoing_args_size
;
10090 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
10092 offset
= frame
->args_size
+ frame
->cprestore_size
;
10094 /* Move above the local variables. */
10095 frame
->var_size
= MIPS_STACK_ALIGN (size
);
10096 offset
+= frame
->var_size
;
10098 /* Find out which GPRs we need to save. */
10099 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
10100 if (mips_save_reg_p (regno
))
10103 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
10106 /* If this function calls eh_return, we must also save and restore the
10107 EH data registers. */
10108 if (crtl
->calls_eh_return
)
10109 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
10112 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
10115 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10116 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10117 save all later registers too. */
10118 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10120 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
10121 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
10122 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
10123 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
10126 /* Move above the GPR save area. */
10127 if (frame
->num_gp
> 0)
10129 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
10130 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
10133 /* Find out which FPRs we need to save. This loop must iterate over
10134 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10135 if (TARGET_HARD_FLOAT
)
10136 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
10137 if (mips_save_reg_p (regno
))
10139 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
10140 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
10143 /* Move above the FPR save area. */
10144 if (frame
->num_fp
> 0)
10146 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
10147 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
10150 /* Add in space for the interrupt context information. */
10151 if (cfun
->machine
->interrupt_handler_p
)
10154 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
10157 frame
->acc_mask
|= (1 << 0);
10160 /* Check accumulators 1, 2, 3. */
10161 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
10162 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
10165 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
10168 /* All interrupt context functions need space to preserve STATUS. */
10169 frame
->num_cop0_regs
++;
10171 /* If we don't keep interrupts masked, we need to save EPC. */
10172 if (!cfun
->machine
->keep_interrupts_masked_p
)
10173 frame
->num_cop0_regs
++;
10176 /* Move above the accumulator save area. */
10177 if (frame
->num_acc
> 0)
10179 /* Each accumulator needs 2 words. */
10180 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
10181 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
10184 /* Move above the COP0 register save area. */
10185 if (frame
->num_cop0_regs
> 0)
10187 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
10188 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
10191 /* Move above the callee-allocated varargs save area. */
10192 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
10193 frame
->arg_pointer_offset
= offset
;
10195 /* Move above the callee-allocated area for pretend stack arguments. */
10196 offset
+= crtl
->args
.pretend_args_size
;
10197 frame
->total_size
= offset
;
10199 /* Work out the offsets of the save areas from the top of the frame. */
10200 if (frame
->gp_sp_offset
> 0)
10201 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
10202 if (frame
->fp_sp_offset
> 0)
10203 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
10204 if (frame
->acc_sp_offset
> 0)
10205 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
10206 if (frame
->num_cop0_regs
> 0)
10207 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
10209 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10210 arguments. This tends to increase the chances of using unextended
10211 instructions for local variables and incoming arguments. */
10213 frame
->hard_frame_pointer_offset
= frame
->args_size
;
10216 /* Return the style of GP load sequence that is being used for the
10217 current function. */
10219 enum mips_loadgp_style
10220 mips_current_loadgp_style (void)
10222 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
10223 return LOADGP_NONE
;
10225 if (TARGET_RTP_PIC
)
10228 if (TARGET_ABSOLUTE_ABICALLS
)
10229 return LOADGP_ABSOLUTE
;
10231 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
10234 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10237 mips_frame_pointer_required (void)
10239 /* If the function contains dynamic stack allocations, we need to
10240 use the frame pointer to access the static parts of the frame. */
10241 if (cfun
->calls_alloca
)
10244 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10245 reload may be unable to compute the address of a local variable,
10246 since there is no way to add a large constant to the stack pointer
10247 without using a second temporary register. */
10250 mips_compute_frame_info ();
10251 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
10258 /* Make sure that we're not trying to eliminate to the wrong hard frame
10262 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10264 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
10267 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10268 or argument pointer. TO is either the stack pointer or hard frame
10272 mips_initial_elimination_offset (int from
, int to
)
10274 HOST_WIDE_INT offset
;
10276 mips_compute_frame_info ();
10278 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10281 case FRAME_POINTER_REGNUM
:
10282 if (FRAME_GROWS_DOWNWARD
)
10283 offset
= (cfun
->machine
->frame
.args_size
10284 + cfun
->machine
->frame
.cprestore_size
10285 + cfun
->machine
->frame
.var_size
);
10290 case ARG_POINTER_REGNUM
:
10291 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
10295 gcc_unreachable ();
10298 if (to
== HARD_FRAME_POINTER_REGNUM
)
10299 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10304 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10307 mips_extra_live_on_entry (bitmap regs
)
10309 if (TARGET_USE_GOT
)
10311 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10312 the global pointer. */
10313 if (!TARGET_ABSOLUTE_ABICALLS
)
10314 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10316 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10317 the global pointer. */
10319 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
10321 /* See the comment above load_call<mode> for details. */
10322 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
10326 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10330 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
10335 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
10338 /* Emit code to change the current function's return address to
10339 ADDRESS. SCRATCH is available as a scratch register, if needed.
10340 ADDRESS and SCRATCH are both word-mode GPRs. */
10343 mips_set_return_address (rtx address
, rtx scratch
)
10347 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
10348 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
10349 cfun
->machine
->frame
.gp_sp_offset
);
10350 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
10353 /* Return true if the current function has a cprestore slot. */
10356 mips_cfun_has_cprestore_slot_p (void)
10358 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
10359 && cfun
->machine
->frame
.cprestore_size
> 0);
10362 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10363 cprestore slot. LOAD_P is true if the caller wants to load from
10364 the cprestore slot; it is false if the caller wants to store to
10368 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
10371 const struct mips_frame_info
*frame
;
10373 frame
= &cfun
->machine
->frame
;
10374 /* .cprestore always uses the stack pointer instead of the frame pointer.
10375 We have a free choice for direct stores for non-MIPS16 functions,
10376 and for MIPS16 functions whose cprestore slot is in range of the
10377 stack pointer. Using the stack pointer would sometimes give more
10378 (early) scheduling freedom, but using the frame pointer would
10379 sometimes give more (late) scheduling freedom. It's hard to
10380 predict which applies to a given function, so let's keep things
10383 Loads must always use the frame pointer in functions that call
10384 alloca, and there's little benefit to using the stack pointer
10386 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
10388 *base
= hard_frame_pointer_rtx
;
10389 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
10393 *base
= stack_pointer_rtx
;
10394 *offset
= frame
->args_size
;
10398 /* Return true if X is the load or store address of the cprestore slot;
10399 LOAD_P says which. */
10402 mips_cprestore_address_p (rtx x
, bool load_p
)
10404 rtx given_base
, required_base
;
10405 HOST_WIDE_INT given_offset
, required_offset
;
10407 mips_split_plus (x
, &given_base
, &given_offset
);
10408 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
10409 return given_base
== required_base
&& given_offset
== required_offset
;
10412 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10413 going to load from it, false if we are going to store to it.
10414 Use TEMP as a temporary register if need be. */
10417 mips_cprestore_slot (rtx temp
, bool load_p
)
10420 HOST_WIDE_INT offset
;
10422 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
10423 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
10426 /* Emit instructions to save global pointer value GP into cprestore
10427 slot MEM. OFFSET is the offset that MEM applies to the base register.
10429 MEM may not be a legitimate address. If it isn't, TEMP is a
10430 temporary register that can be used, otherwise it is a SCRATCH. */
10433 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
10435 if (TARGET_CPRESTORE_DIRECTIVE
)
10437 gcc_assert (gp
== pic_offset_table_rtx
);
10438 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
10441 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
10444 /* Restore $gp from its save slot, using TEMP as a temporary base register
10445 if need be. This function is for o32 and o64 abicalls only.
10447 See mips_must_initialize_gp_p for details about how we manage the
10451 mips_restore_gp_from_cprestore_slot (rtx temp
)
10453 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
10455 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
10457 emit_note (NOTE_INSN_DELETED
);
10463 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10464 mips_emit_move (pic_offset_table_rtx
, temp
);
10467 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10468 if (!TARGET_EXPLICIT_RELOCS
)
10469 emit_insn (gen_blockage ());
10472 /* A function to save or store a register. The first argument is the
10473 register and the second is the stack slot. */
10474 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10476 /* Use FN to save or restore register REGNO. MODE is the register's
10477 mode and OFFSET is the offset of its save slot from the current
10481 mips_save_restore_reg (enum machine_mode mode
, int regno
,
10482 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10486 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10488 fn (gen_rtx_REG (mode
, regno
), mem
);
10491 /* Call FN for each accumlator that is saved by the current function.
10492 SP_OFFSET is the offset of the current stack pointer from the start
10496 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10498 HOST_WIDE_INT offset
;
10501 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10502 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10504 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10505 offset
-= UNITS_PER_WORD
;
10506 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10507 offset
-= UNITS_PER_WORD
;
10510 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10511 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10512 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10514 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10515 offset
-= UNITS_PER_WORD
;
10519 /* Save register REG to MEM. Make the instruction frame-related. */
10522 mips_save_reg (rtx reg
, rtx mem
)
10524 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
10528 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
10530 x1
= mips_frame_set (mips_subword (mem
, false),
10531 mips_subword (reg
, false));
10532 x2
= mips_frame_set (mips_subword (mem
, true),
10533 mips_subword (reg
, true));
10534 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10537 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10540 /* Capture the register combinations that are allowed in a SWM or LWM
10541 instruction. The entries are ordered by number of registers set in
10542 the mask. We also ignore the single register encodings because a
10543 normal SW/LW is preferred. */
10545 static const unsigned int umips_swm_mask
[17] = {
10546 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10547 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10548 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10549 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10553 static const unsigned int umips_swm_encoding
[17] = {
10554 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10557 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10558 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10559 stack pointer of the topmost save slot.
10561 Remove from *MASK all registers that were handled using LWM and SWM.
10562 Update *OFFSET so that it points to the first unused save slot. */
10565 umips_build_save_restore (mips_save_restore_fn fn
,
10566 unsigned *mask
, HOST_WIDE_INT
*offset
)
10570 rtx pattern
, set
, reg
, mem
;
10571 HOST_WIDE_INT this_offset
;
10574 /* Try matching $16 to $31 (s0 to ra). */
10575 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
10576 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
10579 if (i
== ARRAY_SIZE (umips_swm_mask
))
10582 /* Get the offset of the lowest save slot. */
10583 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
10584 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
10586 /* LWM/SWM can only support offsets from -2048 to 2047. */
10587 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
10590 /* Create the final PARALLEL. */
10591 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
10592 this_base
= stack_pointer_rtx
;
10594 /* For registers $16-$23 and $30. */
10595 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
10597 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10598 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10599 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
10600 *mask
&= ~(1 << regno
);
10601 reg
= gen_rtx_REG (SImode
, regno
);
10602 if (fn
== mips_save_reg
)
10603 set
= mips_frame_set (mem
, reg
);
10606 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10607 mips_add_cfa_restore (reg
);
10609 XVECEXP (pattern
, 0, j
) = set
;
10612 /* For register $31. */
10613 if (umips_swm_encoding
[i
] >> 4)
10615 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10616 *mask
&= ~(1 << 31);
10617 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10618 reg
= gen_rtx_REG (SImode
, 31);
10619 if (fn
== mips_save_reg
)
10620 set
= mips_frame_set (mem
, reg
);
10623 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10624 mips_add_cfa_restore (reg
);
10626 XVECEXP (pattern
, 0, j
) = set
;
10629 pattern
= emit_insn (pattern
);
10630 if (fn
== mips_save_reg
)
10631 RTX_FRAME_RELATED_P (pattern
) = 1;
10633 /* Adjust the last offset. */
10634 *offset
-= UNITS_PER_WORD
* nregs
;
10639 /* Call FN for each register that is saved by the current function.
10640 SP_OFFSET is the offset of the current stack pointer from the start
10644 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10645 mips_save_restore_fn fn
)
10647 enum machine_mode fpr_mode
;
10649 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
10650 HOST_WIDE_INT offset
;
10653 /* Save registers starting from high to low. The debuggers prefer at least
10654 the return register be stored at func+4, and also it allows us not to
10655 need a nop in the epilogue if at least one register is reloaded in
10656 addition to return address. */
10657 offset
= frame
->gp_sp_offset
- sp_offset
;
10658 mask
= frame
->mask
;
10660 if (TARGET_MICROMIPS
)
10661 umips_build_save_restore (fn
, &mask
, &offset
);
10663 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10664 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10666 /* Record the ra offset for use by mips_function_profiler. */
10667 if (regno
== RETURN_ADDR_REGNUM
)
10668 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10669 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10670 offset
-= UNITS_PER_WORD
;
10673 /* This loop must iterate over the same space as its companion in
10674 mips_compute_frame_info. */
10675 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10676 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10677 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10678 regno
>= FP_REG_FIRST
;
10679 regno
-= MAX_FPRS_PER_FMT
)
10680 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10682 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10683 offset
-= GET_MODE_SIZE (fpr_mode
);
10687 /* Return true if a move between register REGNO and its save slot (MEM)
10688 can be done in a single move. LOAD_P is true if we are loading
10689 from the slot, false if we are storing to it. */
10692 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10694 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10695 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10698 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10699 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10702 /* Emit a move from SRC to DEST, given that one of them is a register
10703 save slot and that the other is a register. TEMP is a temporary
10704 GPR of the same mode that is available if need be. */
10707 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10709 unsigned int regno
;
10714 regno
= REGNO (src
);
10719 regno
= REGNO (dest
);
10723 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
10725 /* We don't yet know whether we'll need this instruction or not.
10726 Postpone the decision by emitting a ghost move. This move
10727 is specifically not frame-related; only the split version is. */
10729 emit_insn (gen_move_gpdi (dest
, src
));
10731 emit_insn (gen_move_gpsi (dest
, src
));
10735 if (regno
== HI_REGNUM
)
10739 mips_emit_move (temp
, src
);
10741 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
10742 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
10744 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
10745 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
10750 emit_insn (gen_mfhidi_ti (temp
,
10751 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
10753 emit_insn (gen_mfhisi_di (temp
,
10754 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
10755 mips_emit_move (dest
, temp
);
10758 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
10759 mips_emit_move (dest
, src
);
10762 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
10763 mips_emit_move (temp
, src
);
10764 mips_emit_move (dest
, temp
);
10767 mips_set_frame_expr (mips_frame_set (dest
, src
));
10770 /* If we're generating n32 or n64 abicalls, and the current function
10771 does not use $28 as its global pointer, emit a cplocal directive.
10772 Use pic_offset_table_rtx as the argument to the directive. */
10775 mips_output_cplocal (void)
10777 if (!TARGET_EXPLICIT_RELOCS
10778 && mips_must_initialize_gp_p ()
10779 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
10780 output_asm_insn (".cplocal %+", 0);
10783 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10786 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10788 const char *fnname
;
10790 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10791 floating-point arguments. */
10793 && TARGET_HARD_FLOAT_ABI
10794 && crtl
->args
.info
.fp_code
!= 0)
10795 mips16_build_function_stub ();
10797 /* Get the function name the same way that toplev.c does before calling
10798 assemble_start_function. This is needed so that the name used here
10799 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10800 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10801 mips_start_function_definition (fnname
, TARGET_MIPS16
);
10803 /* Output MIPS-specific frame information. */
10804 if (!flag_inhibit_size_directive
)
10806 const struct mips_frame_info
*frame
;
10808 frame
= &cfun
->machine
->frame
;
10810 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10812 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
10813 "# vars= " HOST_WIDE_INT_PRINT_DEC
10815 ", args= " HOST_WIDE_INT_PRINT_DEC
10816 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
10817 reg_names
[frame_pointer_needed
10818 ? HARD_FRAME_POINTER_REGNUM
10819 : STACK_POINTER_REGNUM
],
10820 (frame_pointer_needed
10821 ? frame
->total_size
- frame
->hard_frame_pointer_offset
10822 : frame
->total_size
),
10823 reg_names
[RETURN_ADDR_REGNUM
],
10825 frame
->num_gp
, frame
->num_fp
,
10827 frame
->cprestore_size
);
10829 /* .mask MASK, OFFSET. */
10830 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10831 frame
->mask
, frame
->gp_save_offset
);
10833 /* .fmask MASK, OFFSET. */
10834 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10835 frame
->fmask
, frame
->fp_save_offset
);
10838 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10839 Also emit the ".set noreorder; .set nomacro" sequence for functions
10841 if (mips_must_initialize_gp_p ()
10842 && mips_current_loadgp_style () == LOADGP_OLDABI
)
10846 /* This is a fixed-form sequence. The position of the
10847 first two instructions is important because of the
10848 way _gp_disp is defined. */
10849 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10850 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10851 output_asm_insn ("sll\t$2,16", 0);
10852 output_asm_insn ("addu\t$2,$3", 0);
10856 /* .cpload must be in a .set noreorder but not a
10857 .set nomacro block. */
10858 mips_push_asm_switch (&mips_noreorder
);
10859 output_asm_insn (".cpload\t%^", 0);
10860 if (!cfun
->machine
->all_noreorder_p
)
10861 mips_pop_asm_switch (&mips_noreorder
);
10863 mips_push_asm_switch (&mips_nomacro
);
10866 else if (cfun
->machine
->all_noreorder_p
)
10868 mips_push_asm_switch (&mips_noreorder
);
10869 mips_push_asm_switch (&mips_nomacro
);
10872 /* Tell the assembler which register we're using as the global
10873 pointer. This is needed for thunks, since they can use either
10874 explicit relocs or assembler macros. */
10875 mips_output_cplocal ();
10878 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10881 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10882 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10884 const char *fnname
;
10886 /* Reinstate the normal $gp. */
10887 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
10888 mips_output_cplocal ();
10890 if (cfun
->machine
->all_noreorder_p
)
10892 mips_pop_asm_switch (&mips_nomacro
);
10893 mips_pop_asm_switch (&mips_noreorder
);
10896 /* Get the function name the same way that toplev.c does before calling
10897 assemble_start_function. This is needed so that the name used here
10898 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10899 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10900 mips_end_function_definition (fnname
);
10903 /* Emit an optimisation barrier for accesses to the current frame. */
10906 mips_frame_barrier (void)
10908 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
10912 /* The __gnu_local_gp symbol. */
10914 static GTY(()) rtx mips_gnu_local_gp
;
10916 /* If we're generating n32 or n64 abicalls, emit instructions
10917 to set up the global pointer. */
10920 mips_emit_loadgp (void)
10922 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
10924 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10925 switch (mips_current_loadgp_style ())
10927 case LOADGP_ABSOLUTE
:
10928 if (mips_gnu_local_gp
== NULL
)
10930 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
10931 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
10933 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
10934 (pic_reg
, mips_gnu_local_gp
)));
10937 case LOADGP_OLDABI
:
10938 /* Added by mips_output_function_prologue. */
10941 case LOADGP_NEWABI
:
10942 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
10943 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
10944 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
10945 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
10946 (pic_reg
, offset
, incoming_address
)));
10950 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
10951 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
10952 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
10960 emit_insn (PMODE_INSN (gen_copygp_mips16
,
10961 (pic_offset_table_rtx
, pic_reg
)));
10963 /* Emit a blockage if there are implicit uses of the GP register.
10964 This includes profiled functions, because FUNCTION_PROFILE uses
10966 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
10967 emit_insn (gen_loadgp_blockage ());
10970 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10972 #if PROBE_INTERVAL > 32768
10973 #error Cannot use indexed addressing mode for stack probing
10976 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10977 inclusive. These are offsets from the current stack pointer. */
10980 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
10983 sorry ("-fstack-check=specific not implemented for MIPS16");
10985 /* See if we have a constant small number of probes to generate. If so,
10986 that's the easy case. */
10987 if (first
+ size
<= 32768)
10991 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10992 it exceeds SIZE. If only one probe is needed, this will not
10993 generate any code. Then probe at FIRST + SIZE. */
10994 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
10995 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10998 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
11002 /* Otherwise, do the same as above, but in a loop. Note that we must be
11003 extra careful with variables wrapping around because we might be at
11004 the very top (or the very bottom) of the address space and we have
11005 to be able to handle this case properly; in particular, we use an
11006 equality test for the loop condition. */
11009 HOST_WIDE_INT rounded_size
;
11010 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
11011 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
11013 /* Sanity check for the addressing mode we're going to use. */
11014 gcc_assert (first
<= 32768);
11017 /* Step 1: round SIZE to the previous multiple of the interval. */
11019 rounded_size
= size
& -PROBE_INTERVAL
;
11022 /* Step 2: compute initial and final value of the loop counter. */
11024 /* TEST_ADDR = SP + FIRST. */
11025 emit_insn (gen_rtx_SET (VOIDmode
, r3
,
11026 plus_constant (Pmode
, stack_pointer_rtx
,
11029 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
11030 if (rounded_size
> 32768)
11032 emit_move_insn (r12
, GEN_INT (rounded_size
));
11033 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
11034 gen_rtx_MINUS (Pmode
, r3
, r12
)));
11037 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
11038 plus_constant (Pmode
, r3
, -rounded_size
)));
11041 /* Step 3: the loop
11043 while (TEST_ADDR != LAST_ADDR)
11045 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11049 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11050 until it is equal to ROUNDED_SIZE. */
11052 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
11055 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11056 that SIZE is equal to ROUNDED_SIZE. */
11058 if (size
!= rounded_size
)
11059 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
11062 /* Make sure nothing is scheduled before we are done. */
11063 emit_insn (gen_blockage ());
11066 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
11067 absolute addresses. */
11070 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
11072 static int labelno
= 0;
11073 char loop_lab
[32], end_lab
[32], tmp
[64];
11076 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
11077 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
11079 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
11081 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11084 strcpy (tmp
, "%(%<beq\t%0,%1,");
11085 output_asm_insn (strcat (tmp
, &end_lab
[1]), xops
);
11087 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11088 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
11089 if (TARGET_64BIT
&& TARGET_LONG64
)
11090 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
11092 output_asm_insn ("addiu\t%0,%0,%1", xops
);
11094 /* Probe at TEST_ADDR and branch. */
11095 fprintf (asm_out_file
, "\tb\t");
11096 assemble_name_raw (asm_out_file
, loop_lab
);
11097 fputc ('\n', asm_out_file
);
11099 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
11101 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
11103 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
11108 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
11111 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
11113 return REG_P (*x
) && KERNEL_REG_P (REGNO (*x
));
11116 /* Expand the "prologue" pattern. */
11119 mips_expand_prologue (void)
11121 const struct mips_frame_info
*frame
;
11122 HOST_WIDE_INT size
;
11123 unsigned int nargs
;
11126 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
11128 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11129 or implicitly. If so, we can commit to using a global pointer
11130 straight away, otherwise we need to defer the decision. */
11131 if (mips_cfun_has_inflexible_gp_ref_p ()
11132 || mips_cfun_has_flexible_gp_ref_p ())
11134 cfun
->machine
->must_initialize_gp_p
= true;
11135 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
11138 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
11141 frame
= &cfun
->machine
->frame
;
11142 size
= frame
->total_size
;
11144 if (flag_stack_usage_info
)
11145 current_function_static_stack_size
= size
;
11147 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
11149 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
11151 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
11152 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
,
11153 size
- STACK_CHECK_PROTECT
);
11156 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
11159 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11160 bytes beforehand; this is enough to cover the register save area
11161 without going out of range. */
11162 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
11163 || frame
->num_cop0_regs
> 0)
11165 HOST_WIDE_INT step1
;
11167 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
11168 if (GENERATE_MIPS16E_SAVE_RESTORE
)
11170 HOST_WIDE_INT offset
;
11171 unsigned int mask
, regno
;
11173 /* Try to merge argument stores into the save instruction. */
11174 nargs
= mips16e_collect_argument_saves ();
11176 /* Build the save instruction. */
11177 mask
= frame
->mask
;
11178 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
11180 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11181 mips_frame_barrier ();
11184 /* Check if we need to save other registers. */
11185 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11186 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11188 offset
-= UNITS_PER_WORD
;
11189 mips_save_restore_reg (word_mode
, regno
,
11190 offset
, mips_save_reg
);
11195 if (cfun
->machine
->interrupt_handler_p
)
11197 HOST_WIDE_INT offset
;
11200 /* If this interrupt is using a shadow register set, we need to
11201 get the stack pointer from the previous register set. */
11202 if (cfun
->machine
->use_shadow_register_set_p
)
11203 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
11204 stack_pointer_rtx
));
11206 if (!cfun
->machine
->keep_interrupts_masked_p
)
11208 /* Move from COP0 Cause to K0. */
11209 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
11210 gen_rtx_REG (SImode
,
11211 COP0_CAUSE_REG_NUM
)));
11212 /* Move from COP0 EPC to K1. */
11213 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11214 gen_rtx_REG (SImode
,
11215 COP0_EPC_REG_NUM
)));
11218 /* Allocate the first part of the frame. */
11219 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
11221 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11222 mips_frame_barrier ();
11225 /* Start at the uppermost location for saving. */
11226 offset
= frame
->cop0_sp_offset
- size
;
11227 if (!cfun
->machine
->keep_interrupts_masked_p
)
11229 /* Push EPC into its stack slot. */
11230 mem
= gen_frame_mem (word_mode
,
11231 plus_constant (Pmode
, stack_pointer_rtx
,
11233 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11234 offset
-= UNITS_PER_WORD
;
11237 /* Move from COP0 Status to K1. */
11238 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11239 gen_rtx_REG (SImode
,
11240 COP0_STATUS_REG_NUM
)));
11242 /* Right justify the RIPL in k0. */
11243 if (!cfun
->machine
->keep_interrupts_masked_p
)
11244 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
11245 gen_rtx_REG (SImode
, K0_REG_NUM
),
11246 GEN_INT (CAUSE_IPL
)));
11248 /* Push Status into its stack slot. */
11249 mem
= gen_frame_mem (word_mode
,
11250 plus_constant (Pmode
, stack_pointer_rtx
,
11252 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11253 offset
-= UNITS_PER_WORD
;
11255 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11256 if (!cfun
->machine
->keep_interrupts_masked_p
)
11257 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11260 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11262 if (!cfun
->machine
->keep_interrupts_masked_p
)
11263 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11264 IE is already the correct value, so we don't have to do
11265 anything explicit. */
11266 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11269 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11271 /* Disable interrupts by clearing the KSU, ERL, EXL,
11273 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11276 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11280 insn
= gen_add3_insn (stack_pointer_rtx
,
11283 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11284 mips_frame_barrier ();
11287 mips_for_each_saved_acc (size
, mips_save_reg
);
11288 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
11292 /* Allocate the rest of the frame. */
11295 if (SMALL_OPERAND (-size
))
11296 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
11298 GEN_INT (-size
)))) = 1;
11301 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
11304 /* There are no instructions to add or subtract registers
11305 from the stack pointer, so use the frame pointer as a
11306 temporary. We should always be using a frame pointer
11307 in this case anyway. */
11308 gcc_assert (frame_pointer_needed
);
11309 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11310 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
11311 hard_frame_pointer_rtx
,
11312 MIPS_PROLOGUE_TEMP (Pmode
)));
11313 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
11316 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
11318 MIPS_PROLOGUE_TEMP (Pmode
)));
11320 /* Describe the combined effect of the previous instructions. */
11321 mips_set_frame_expr
11322 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
11323 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
11325 mips_frame_barrier ();
11328 /* Set up the frame pointer, if we're using one. */
11329 if (frame_pointer_needed
)
11331 HOST_WIDE_INT offset
;
11333 offset
= frame
->hard_frame_pointer_offset
;
11336 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11337 RTX_FRAME_RELATED_P (insn
) = 1;
11339 else if (SMALL_OPERAND (offset
))
11341 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
11342 stack_pointer_rtx
, GEN_INT (offset
));
11343 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11347 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
11348 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11349 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
11350 hard_frame_pointer_rtx
,
11351 MIPS_PROLOGUE_TEMP (Pmode
)));
11352 mips_set_frame_expr
11353 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
11354 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
11358 mips_emit_loadgp ();
11360 /* Initialize the $gp save slot. */
11361 if (mips_cfun_has_cprestore_slot_p ())
11363 rtx base
, mem
, gp
, temp
;
11364 HOST_WIDE_INT offset
;
11366 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
11367 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11368 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11369 temp
= (SMALL_OPERAND (offset
)
11370 ? gen_rtx_SCRATCH (Pmode
)
11371 : MIPS_PROLOGUE_TEMP (Pmode
));
11372 emit_insn (PMODE_INSN (gen_potential_cprestore
,
11373 (mem
, GEN_INT (offset
), gp
, temp
)));
11375 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11376 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11377 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
11380 /* We need to search back to the last use of K0 or K1. */
11381 if (cfun
->machine
->interrupt_handler_p
)
11383 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
11385 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
11387 /* Emit a move from K1 to COP0 Status after insn. */
11388 gcc_assert (insn
!= NULL_RTX
);
11389 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11390 gen_rtx_REG (SImode
, K1_REG_NUM
)),
11394 /* If we are profiling, make sure no instructions are scheduled before
11395 the call to mcount. */
11397 emit_insn (gen_blockage ());
11400 /* Attach all pending register saves to the previous instruction.
11401 Return that instruction. */
11404 mips_epilogue_emit_cfa_restores (void)
11408 insn
= get_last_insn ();
11409 gcc_assert (insn
&& !REG_NOTES (insn
));
11410 if (mips_epilogue
.cfa_restores
)
11412 RTX_FRAME_RELATED_P (insn
) = 1;
11413 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
11414 mips_epilogue
.cfa_restores
= 0;
11419 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11420 now at REG + OFFSET. */
11423 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
11427 insn
= mips_epilogue_emit_cfa_restores ();
11428 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
11430 RTX_FRAME_RELATED_P (insn
) = 1;
11431 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
11432 plus_constant (Pmode
, reg
, offset
),
11434 mips_epilogue
.cfa_reg
= reg
;
11435 mips_epilogue
.cfa_offset
= offset
;
11439 /* Emit instructions to restore register REG from slot MEM. Also update
11440 the cfa_restores list. */
11443 mips_restore_reg (rtx reg
, rtx mem
)
11445 /* There's no MIPS16 instruction to load $31 directly. Load into
11446 $7 instead and adjust the return insn appropriately. */
11447 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
11448 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
11449 else if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
11451 mips_add_cfa_restore (mips_subword (reg
, true));
11452 mips_add_cfa_restore (mips_subword (reg
, false));
11455 mips_add_cfa_restore (reg
);
11457 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
11458 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
11459 /* The CFA is currently defined in terms of the register whose
11460 value we have just restored. Redefine the CFA in terms of
11461 the stack pointer. */
11462 mips_epilogue_set_cfa (stack_pointer_rtx
,
11463 mips_epilogue
.cfa_restore_sp_offset
);
11466 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11467 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11468 BASE, if not the stack pointer, is available as a temporary. */
11471 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
11473 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
11476 mips_frame_barrier ();
11477 if (offset
== const0_rtx
)
11479 emit_move_insn (stack_pointer_rtx
, base
);
11480 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11482 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
11484 emit_insn (gen_add3_insn (base
, base
, offset
));
11485 mips_epilogue_set_cfa (base
, new_frame_size
);
11486 emit_move_insn (stack_pointer_rtx
, base
);
11490 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
11491 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11495 /* Emit any instructions needed before a return. */
11498 mips_expand_before_return (void)
11500 /* When using a call-clobbered gp, we start out with unified call
11501 insns that include instructions to restore the gp. We then split
11502 these unified calls after reload. These split calls explicitly
11503 clobber gp, so there is no need to define
11504 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11506 For consistency, we should also insert an explicit clobber of $28
11507 before return insns, so that the post-reload optimizers know that
11508 the register is not live on exit. */
11509 if (TARGET_CALL_CLOBBERED_GP
)
11510 emit_clobber (pic_offset_table_rtx
);
11513 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11517 mips_expand_epilogue (bool sibcall_p
)
11519 const struct mips_frame_info
*frame
;
11520 HOST_WIDE_INT step1
, step2
;
11521 rtx base
, adjust
, insn
;
11522 bool use_jraddiusp_p
= false;
11524 if (!sibcall_p
&& mips_can_use_return_insn ())
11526 emit_jump_insn (gen_return ());
11530 /* In MIPS16 mode, if the return value should go into a floating-point
11531 register, we need to call a helper routine to copy it over. */
11532 if (mips16_cfun_returns_in_fpr_p ())
11533 mips16_copy_fpr_return_value ();
11535 /* Split the frame into two. STEP1 is the amount of stack we should
11536 deallocate before restoring the registers. STEP2 is the amount we
11537 should deallocate afterwards.
11539 Start off by assuming that no registers need to be restored. */
11540 frame
= &cfun
->machine
->frame
;
11541 step1
= frame
->total_size
;
11544 /* Work out which register holds the frame address. */
11545 if (!frame_pointer_needed
)
11546 base
= stack_pointer_rtx
;
11549 base
= hard_frame_pointer_rtx
;
11550 step1
-= frame
->hard_frame_pointer_offset
;
11552 mips_epilogue
.cfa_reg
= base
;
11553 mips_epilogue
.cfa_offset
= step1
;
11554 mips_epilogue
.cfa_restores
= NULL_RTX
;
11556 /* If we need to restore registers, deallocate as much stack as
11557 possible in the second step without going out of range. */
11558 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
11559 || frame
->num_cop0_regs
> 0)
11561 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
11565 /* Get an rtx for STEP1 that we can add to BASE. */
11566 adjust
= GEN_INT (step1
);
11567 if (!SMALL_OPERAND (step1
))
11569 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
11570 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
11572 mips_deallocate_stack (base
, adjust
, step2
);
11574 /* If we're using addressing macros, $gp is implicitly used by all
11575 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11577 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
11578 emit_insn (gen_blockage ());
11580 mips_epilogue
.cfa_restore_sp_offset
= step2
;
11581 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
11583 unsigned int regno
, mask
;
11584 HOST_WIDE_INT offset
;
11587 /* Generate the restore instruction. */
11588 mask
= frame
->mask
;
11589 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
11591 /* Restore any other registers manually. */
11592 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11593 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11595 offset
-= UNITS_PER_WORD
;
11596 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
11599 /* Restore the remaining registers and deallocate the final bit
11601 mips_frame_barrier ();
11602 emit_insn (restore
);
11603 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
11607 /* Restore the registers. */
11608 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
11609 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
11612 if (cfun
->machine
->interrupt_handler_p
)
11614 HOST_WIDE_INT offset
;
11617 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
11618 if (!cfun
->machine
->keep_interrupts_masked_p
)
11620 /* Restore the original EPC. */
11621 mem
= gen_frame_mem (word_mode
,
11622 plus_constant (Pmode
, stack_pointer_rtx
,
11624 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11625 offset
-= UNITS_PER_WORD
;
11627 /* Move to COP0 EPC. */
11628 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
11629 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11632 /* Restore the original Status. */
11633 mem
= gen_frame_mem (word_mode
,
11634 plus_constant (Pmode
, stack_pointer_rtx
,
11636 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11637 offset
-= UNITS_PER_WORD
;
11639 /* If we don't use shadow register set, we need to update SP. */
11640 if (!cfun
->machine
->use_shadow_register_set_p
)
11641 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11643 /* The choice of position is somewhat arbitrary in this case. */
11644 mips_epilogue_emit_cfa_restores ();
11646 /* Move to COP0 Status. */
11647 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11648 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11650 else if (TARGET_MICROMIPS
11651 && !crtl
->calls_eh_return
11654 && mips_unsigned_immediate_p (step2
, 5, 2))
11655 use_jraddiusp_p
= true;
11657 /* Deallocate the final bit of the frame. */
11658 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11661 if (!use_jraddiusp_p
)
11662 gcc_assert (!mips_epilogue
.cfa_restores
);
11664 /* Add in the __builtin_eh_return stack adjustment. We need to
11665 use a temporary in MIPS16 code. */
11666 if (crtl
->calls_eh_return
)
11670 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
11671 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
11672 MIPS_EPILOGUE_TEMP (Pmode
),
11673 EH_RETURN_STACKADJ_RTX
));
11674 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
11677 emit_insn (gen_add3_insn (stack_pointer_rtx
,
11679 EH_RETURN_STACKADJ_RTX
));
11684 mips_expand_before_return ();
11685 if (cfun
->machine
->interrupt_handler_p
)
11687 /* Interrupt handlers generate eret or deret. */
11688 if (cfun
->machine
->use_debug_exception_return_p
)
11689 emit_jump_insn (gen_mips_deret ());
11691 emit_jump_insn (gen_mips_eret ());
11697 /* When generating MIPS16 code, the normal
11698 mips_for_each_saved_gpr_and_fpr path will restore the return
11699 address into $7 rather than $31. */
11701 && !GENERATE_MIPS16E_SAVE_RESTORE
11702 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
11704 /* simple_returns cannot rely on values that are only available
11705 on paths through the epilogue (because return paths that do
11706 not pass through the epilogue may nevertheless reuse a
11707 simple_return that occurs at the end of the epilogue).
11708 Use a normal return here instead. */
11709 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
11710 pat
= gen_return_internal (reg
);
11712 else if (use_jraddiusp_p
)
11713 pat
= gen_jraddiusp (GEN_INT (step2
));
11716 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
11717 pat
= gen_simple_return_internal (reg
);
11719 emit_jump_insn (pat
);
11720 if (use_jraddiusp_p
)
11721 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
11725 /* Search from the beginning to the first use of K0 or K1. */
11726 if (cfun
->machine
->interrupt_handler_p
11727 && !cfun
->machine
->keep_interrupts_masked_p
)
11729 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11731 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
11733 gcc_assert (insn
!= NULL_RTX
);
11734 /* Insert disable interrupts before the first use of K0 or K1. */
11735 emit_insn_before (gen_mips_di (), insn
);
11736 emit_insn_before (gen_mips_ehb (), insn
);
11740 /* Return nonzero if this function is known to have a null epilogue.
11741 This allows the optimizer to omit jumps to jumps if no stack
11745 mips_can_use_return_insn (void)
11747 /* Interrupt handlers need to go through the epilogue. */
11748 if (cfun
->machine
->interrupt_handler_p
)
11751 if (!reload_completed
)
11757 /* In MIPS16 mode, a function that returns a floating-point value
11758 needs to arrange to copy the return value into the floating-point
11760 if (mips16_cfun_returns_in_fpr_p ())
11763 return cfun
->machine
->frame
.total_size
== 0;
11766 /* Return true if register REGNO can store a value of mode MODE.
11767 The result of this function is cached in mips_hard_regno_mode_ok. */
11770 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
11773 enum mode_class mclass
;
11775 if (mode
== CCV2mode
)
11776 return (ISA_HAS_8CC
11777 && ST_REG_P (regno
)
11778 && (regno
- ST_REG_FIRST
) % 2 == 0);
11780 if (mode
== CCV4mode
)
11781 return (ISA_HAS_8CC
11782 && ST_REG_P (regno
)
11783 && (regno
- ST_REG_FIRST
) % 4 == 0);
11785 if (mode
== CCmode
)
11786 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
11788 size
= GET_MODE_SIZE (mode
);
11789 mclass
= GET_MODE_CLASS (mode
);
11791 if (GP_REG_P (regno
))
11792 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
11794 if (FP_REG_P (regno
)
11795 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
11796 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
11798 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11799 if (TARGET_LOONGSON_VECTORS
11800 && (mode
== V2SImode
11801 || mode
== V4HImode
11802 || mode
== V8QImode
11803 || mode
== DImode
))
11806 if (mclass
== MODE_FLOAT
11807 || mclass
== MODE_COMPLEX_FLOAT
11808 || mclass
== MODE_VECTOR_FLOAT
)
11809 return size
<= UNITS_PER_FPVALUE
;
11811 /* Allow integer modes that fit into a single register. We need
11812 to put integers into FPRs when using instructions like CVT
11813 and TRUNC. There's no point allowing sizes smaller than a word,
11814 because the FPU has no appropriate load/store instructions. */
11815 if (mclass
== MODE_INT
)
11816 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
11819 if (ACC_REG_P (regno
)
11820 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
11822 if (MD_REG_P (regno
))
11824 /* After a multiplication or division, clobbering HI makes
11825 the value of LO unpredictable, and vice versa. This means
11826 that, for all interesting cases, HI and LO are effectively
11829 We model this by requiring that any value that uses HI
11831 if (size
<= UNITS_PER_WORD
* 2)
11832 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
11836 /* DSP accumulators do not have the same restrictions as
11837 HI and LO, so we can treat them as normal doubleword
11839 if (size
<= UNITS_PER_WORD
)
11842 if (size
<= UNITS_PER_WORD
* 2
11843 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
11848 if (ALL_COP_REG_P (regno
))
11849 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
11851 if (regno
== GOT_VERSION_REGNUM
)
11852 return mode
== SImode
;
11857 /* Implement HARD_REGNO_NREGS. */
11860 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
11862 if (ST_REG_P (regno
))
11863 /* The size of FP status registers is always 4, because they only hold
11864 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11865 return (GET_MODE_SIZE (mode
) + 3) / 4;
11867 if (FP_REG_P (regno
))
11868 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
11870 /* All other registers are word-sized. */
11871 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
11874 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11875 in mips_hard_regno_nregs. */
11878 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
11884 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
11885 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
11887 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
11888 size
= MIN (size
, 4);
11889 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
11891 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
11893 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
11894 size
= MIN (size
, UNITS_PER_FPREG
);
11895 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
11897 if (!hard_reg_set_empty_p (left
))
11898 size
= MIN (size
, UNITS_PER_WORD
);
11899 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
11902 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11905 mips_cannot_change_mode_class (enum machine_mode from
,
11906 enum machine_mode to
,
11907 enum reg_class rclass
)
11909 /* Allow conversions between different Loongson integer vectors,
11910 and between those vectors and DImode. */
11911 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
11912 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
11915 /* Otherwise, there are several problems with changing the modes of
11916 values in floating-point registers:
11918 - When a multi-word value is stored in paired floating-point
11919 registers, the first register always holds the low word. We
11920 therefore can't allow FPRs to change between single-word and
11921 multi-word modes on big-endian targets.
11923 - GCC assumes that each word of a multiword register can be
11924 accessed individually using SUBREGs. This is not true for
11925 floating-point registers if they are bigger than a word.
11927 - Loading a 32-bit value into a 64-bit floating-point register
11928 will not sign-extend the value, despite what LOAD_EXTEND_OP
11929 says. We can't allow FPRs to change from SImode to a wider
11930 mode on 64-bit targets.
11932 - If the FPU has already interpreted a value in one format, we
11933 must not ask it to treat the value as having a different
11936 We therefore disallow all mode changes involving FPRs. */
11938 return reg_classes_intersect_p (FP_REGS
, rclass
);
11941 /* Implement target hook small_register_classes_for_mode_p. */
11944 mips_small_register_classes_for_mode_p (enum machine_mode mode
11947 return TARGET_MIPS16
;
11950 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11953 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
11958 return TARGET_HARD_FLOAT
;
11961 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
11964 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
11971 /* Implement MODES_TIEABLE_P. */
11974 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
11976 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11977 prefer to put one of them in FPRs. */
11978 return (mode1
== mode2
11979 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
11980 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
11983 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11986 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
11988 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
11991 if (reg_class_subset_p (FP_REGS
, rclass
)
11992 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
11995 if (reg_class_subset_p (GR_REGS
, rclass
))
11998 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
12004 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
12005 Return a "canonical" class to represent it in later calculations. */
12008 mips_canonicalize_move_class (reg_class_t rclass
)
12010 /* All moves involving accumulator registers have the same cost. */
12011 if (reg_class_subset_p (rclass
, ACC_REGS
))
12014 /* Likewise promote subclasses of general registers to the most
12015 interesting containing class. */
12016 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
12018 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
12019 rclass
= GENERAL_REGS
;
12024 /* Return the cost of moving a value of mode MODE from a register of
12025 class FROM to a GPR. Return 0 for classes that are unions of other
12026 classes handled by this function. */
12029 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
12036 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12040 /* MFLO and MFHI. */
12048 /* LUI followed by MOVF. */
12054 /* This choice of value is historical. */
12062 /* Return the cost of moving a value of mode MODE from a GPR to a
12063 register of class TO. Return 0 for classes that are unions of
12064 other classes handled by this function. */
12067 mips_move_from_gpr_cost (enum machine_mode mode
, reg_class_t to
)
12073 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12077 /* MTLO and MTHI. */
12085 /* A secondary reload through an FPR scratch. */
12086 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
12087 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
12092 /* This choice of value is historical. */
12100 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
12101 maximum of the move costs for subclasses; regclass will work out
12102 the maximum for us. */
12105 mips_register_move_cost (enum machine_mode mode
,
12106 reg_class_t from
, reg_class_t to
)
12111 from
= mips_canonicalize_move_class (from
);
12112 to
= mips_canonicalize_move_class (to
);
12114 /* Handle moves that can be done without using general-purpose registers. */
12115 if (from
== FP_REGS
)
12117 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
12121 /* The sequence generated by mips_expand_fcc_reload. */
12125 /* Handle cases in which only one class deviates from the ideal. */
12126 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
12128 return mips_move_from_gpr_cost (mode
, to
);
12130 return mips_move_to_gpr_cost (mode
, from
);
12132 /* Handles cases that require a GPR temporary. */
12133 cost1
= mips_move_to_gpr_cost (mode
, from
);
12136 cost2
= mips_move_from_gpr_cost (mode
, to
);
12138 return cost1
+ cost2
;
12144 /* Implement TARGET_MEMORY_MOVE_COST. */
12147 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
12149 return (mips_cost
->memory_latency
12150 + memory_move_secondary_cost (mode
, rclass
, in
));
12153 /* Return the register class required for a secondary register when
12154 copying between one of the registers in RCLASS and value X, which
12155 has mode MODE. X is the source of the move if IN_P, otherwise it
12156 is the destination. Return NO_REGS if no secondary register is
12160 mips_secondary_reload_class (enum reg_class rclass
,
12161 enum machine_mode mode
, rtx x
, bool in_p
)
12165 /* If X is a constant that cannot be loaded into $25, it must be loaded
12166 into some other GPR. No other register class allows a direct move. */
12167 if (mips_dangerous_for_la25_p (x
))
12168 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
12170 regno
= true_regnum (x
);
12173 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12174 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
12180 /* Copying from accumulator registers to anywhere other than a general
12181 register requires a temporary general register. */
12182 if (reg_class_subset_p (rclass
, ACC_REGS
))
12183 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12184 if (ACC_REG_P (regno
))
12185 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12187 /* We can only copy a value to a condition code register from a
12188 floating-point register, and even then we require a scratch
12189 floating-point register. We can only copy a value out of a
12190 condition-code register into a general register. */
12191 if (reg_class_subset_p (rclass
, ST_REGS
))
12195 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12197 if (ST_REG_P (regno
))
12201 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12204 if (reg_class_subset_p (rclass
, FP_REGS
))
12207 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
12208 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12209 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12212 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
12213 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12216 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
12217 /* We can force the constant to memory and use lwc1
12218 and ldc1. As above, we will use pairs of lwc1s if
12219 ldc1 is not supported. */
12222 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
12223 /* In this case we can use mov.fmt. */
12226 /* Otherwise, we need to reload through an integer register. */
12229 if (FP_REG_P (regno
))
12230 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12235 /* Implement TARGET_MODE_REP_EXTENDED. */
12238 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
12240 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12241 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
12242 return SIGN_EXTEND
;
12247 /* Implement TARGET_VALID_POINTER_MODE. */
12250 mips_valid_pointer_mode (enum machine_mode mode
)
12252 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
12255 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12258 mips_vector_mode_supported_p (enum machine_mode mode
)
12263 return TARGET_PAIRED_SINGLE_FLOAT
;
12278 return TARGET_LOONGSON_VECTORS
;
12285 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12288 mips_scalar_mode_supported_p (enum machine_mode mode
)
12290 if (ALL_FIXED_POINT_MODE_P (mode
)
12291 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
12294 return default_scalar_mode_supported_p (mode
);
12297 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12299 static enum machine_mode
12300 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED
)
12302 if (TARGET_PAIRED_SINGLE_FLOAT
12308 /* Implement TARGET_INIT_LIBFUNCS. */
12311 mips_init_libfuncs (void)
12313 if (TARGET_FIX_VR4120
)
12315 /* Register the special divsi3 and modsi3 functions needed to work
12316 around VR4120 division errata. */
12317 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
12318 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
12321 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
12323 /* Register the MIPS16 -mhard-float stubs. */
12324 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
12325 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
12326 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
12327 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
12329 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
12330 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
12331 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
12332 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
12333 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
12334 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
12335 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
12337 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
12338 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
12339 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
12341 if (TARGET_DOUBLE_FLOAT
)
12343 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
12344 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
12345 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
12346 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
12348 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
12349 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
12350 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
12351 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
12352 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
12353 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
12354 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
12356 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
12357 "__mips16_extendsfdf2");
12358 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
12359 "__mips16_truncdfsf2");
12360 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
12361 "__mips16_fix_truncdfsi");
12362 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
12363 "__mips16_floatsidf");
12364 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
12365 "__mips16_floatunsidf");
12369 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12370 on an external non-MIPS16 routine to implement __sync_synchronize.
12371 Similarly for the rest of the ll/sc libfuncs. */
12374 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
12375 init_sync_libfuncs (UNITS_PER_WORD
);
12379 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12382 mips_process_load_label (rtx target
)
12384 rtx base
, gp
, intop
;
12385 HOST_WIDE_INT offset
;
12387 mips_multi_start ();
12391 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
12392 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12396 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
12397 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12401 gp
= pic_offset_table_rtx
;
12402 if (mips_cfun_has_cprestore_slot_p ())
12404 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
12405 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12406 if (!SMALL_OPERAND (offset
))
12408 intop
= GEN_INT (CONST_HIGH_PART (offset
));
12409 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
12410 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
12413 offset
= CONST_LOW_PART (offset
);
12415 intop
= GEN_INT (offset
);
12416 if (ISA_HAS_LOAD_DELAY
)
12417 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
12419 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
12421 if (ISA_HAS_LOAD_DELAY
)
12422 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
12424 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
12425 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
12430 /* Return the number of instructions needed to load a label into $AT. */
12432 static unsigned int
12433 mips_load_label_num_insns (void)
12435 if (cfun
->machine
->load_label_num_insns
== 0)
12437 mips_process_load_label (pc_rtx
);
12438 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
12440 return cfun
->machine
->load_label_num_insns
;
12443 /* Emit an asm sequence to start a noat block and load the address
12444 of a label into $1. */
12447 mips_output_load_label (rtx target
)
12449 mips_push_asm_switch (&mips_noat
);
12450 if (TARGET_EXPLICIT_RELOCS
)
12452 mips_process_load_label (target
);
12453 mips_multi_write ();
12457 if (Pmode
== DImode
)
12458 output_asm_insn ("dla\t%@,%0", &target
);
12460 output_asm_insn ("la\t%@,%0", &target
);
12464 /* Return the length of INSN. LENGTH is the initial length computed by
12465 attributes in the machine-description file. */
12468 mips_adjust_insn_length (rtx insn
, int length
)
12470 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12471 of a PIC long-branch sequence. Substitute the correct value. */
12472 if (length
== MAX_PIC_BRANCH_LENGTH
12474 && INSN_CODE (insn
) >= 0
12475 && get_attr_type (insn
) == TYPE_BRANCH
)
12477 /* Add the branch-over instruction and its delay slot, if this
12478 is a conditional branch. */
12479 length
= simplejump_p (insn
) ? 0 : 8;
12481 /* Add the size of a load into $AT. */
12482 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
12484 /* Add the length of an indirect jump, ignoring the delay slot. */
12485 length
+= TARGET_COMPRESSION
? 2 : 4;
12488 /* A unconditional jump has an unfilled delay slot if it is not part
12489 of a sequence. A conditional jump normally has a delay slot, but
12490 does not on MIPS16. */
12491 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
12492 length
+= TARGET_MIPS16
? 2 : 4;
12494 /* See how many nops might be needed to avoid hardware hazards. */
12495 if (!cfun
->machine
->ignore_hazard_length_p
12497 && INSN_CODE (insn
) >= 0)
12498 switch (get_attr_hazard (insn
))
12504 length
+= NOP_INSN_LENGTH
;
12508 length
+= NOP_INSN_LENGTH
* 2;
12515 /* Return the assembly code for INSN, which has the operands given by
12516 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12517 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12518 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12519 version of BRANCH_IF_TRUE. */
12522 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
12523 const char *branch_if_true
,
12524 const char *branch_if_false
)
12526 unsigned int length
;
12527 rtx taken
, not_taken
;
12529 gcc_assert (LABEL_P (operands
[0]));
12531 length
= get_attr_length (insn
);
12534 /* Just a simple conditional branch. */
12535 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
12536 return branch_if_true
;
12539 /* Generate a reversed branch around a direct jump. This fallback does
12540 not use branch-likely instructions. */
12541 mips_branch_likely
= false;
12542 not_taken
= gen_label_rtx ();
12543 taken
= operands
[0];
12545 /* Generate the reversed branch to NOT_TAKEN. */
12546 operands
[0] = not_taken
;
12547 output_asm_insn (branch_if_false
, operands
);
12549 /* If INSN has a delay slot, we must provide delay slots for both the
12550 branch to NOT_TAKEN and the conditional jump. We must also ensure
12551 that INSN's delay slot is executed in the appropriate cases. */
12552 if (final_sequence
)
12554 /* This first delay slot will always be executed, so use INSN's
12555 delay slot if is not annulled. */
12556 if (!INSN_ANNULLED_BRANCH_P (insn
))
12558 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12559 asm_out_file
, optimize
, 1, NULL
);
12560 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12563 output_asm_insn ("nop", 0);
12564 fprintf (asm_out_file
, "\n");
12567 /* Output the unconditional branch to TAKEN. */
12568 if (TARGET_ABSOLUTE_JUMPS
)
12569 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
12572 mips_output_load_label (taken
);
12573 output_asm_insn ("jr\t%@%]%/", 0);
12576 /* Now deal with its delay slot; see above. */
12577 if (final_sequence
)
12579 /* This delay slot will only be executed if the branch is taken.
12580 Use INSN's delay slot if is annulled. */
12581 if (INSN_ANNULLED_BRANCH_P (insn
))
12583 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12584 asm_out_file
, optimize
, 1, NULL
);
12585 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12588 output_asm_insn ("nop", 0);
12589 fprintf (asm_out_file
, "\n");
12592 /* Output NOT_TAKEN. */
12593 targetm
.asm_out
.internal_label (asm_out_file
, "L",
12594 CODE_LABEL_NUMBER (not_taken
));
12598 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12599 if some ordering condition is true. The condition is given by
12600 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12601 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12602 its second is always zero. */
12605 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
12607 const char *branch
[2];
12609 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12610 Make BRANCH[0] branch on the inverse condition. */
12611 switch (GET_CODE (operands
[1]))
12613 /* These cases are equivalent to comparisons against zero. */
12615 inverted_p
= !inverted_p
;
12616 /* Fall through. */
12618 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
12619 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
12622 /* These cases are always true or always false. */
12624 inverted_p
= !inverted_p
;
12625 /* Fall through. */
12627 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
12628 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
12632 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
12633 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
12636 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
12639 /* Start a block of code that needs access to the LL, SC and SYNC
12643 mips_start_ll_sc_sync_block (void)
12645 if (!ISA_HAS_LL_SC
)
12647 output_asm_insn (".set\tpush", 0);
12649 output_asm_insn (".set\tmips3", 0);
12651 output_asm_insn (".set\tmips2", 0);
12655 /* End a block started by mips_start_ll_sc_sync_block. */
12658 mips_end_ll_sc_sync_block (void)
12660 if (!ISA_HAS_LL_SC
)
12661 output_asm_insn (".set\tpop", 0);
12664 /* Output and/or return the asm template for a sync instruction. */
12667 mips_output_sync (void)
12669 mips_start_ll_sc_sync_block ();
12670 output_asm_insn ("sync", 0);
12671 mips_end_ll_sc_sync_block ();
12675 /* Return the asm template associated with sync_insn1 value TYPE.
12676 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12678 static const char *
12679 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
12683 case SYNC_INSN1_MOVE
:
12684 return "move\t%0,%z2";
12685 case SYNC_INSN1_LI
:
12686 return "li\t%0,%2";
12687 case SYNC_INSN1_ADDU
:
12688 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12689 case SYNC_INSN1_ADDIU
:
12690 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12691 case SYNC_INSN1_SUBU
:
12692 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12693 case SYNC_INSN1_AND
:
12694 return "and\t%0,%1,%z2";
12695 case SYNC_INSN1_ANDI
:
12696 return "andi\t%0,%1,%2";
12697 case SYNC_INSN1_OR
:
12698 return "or\t%0,%1,%z2";
12699 case SYNC_INSN1_ORI
:
12700 return "ori\t%0,%1,%2";
12701 case SYNC_INSN1_XOR
:
12702 return "xor\t%0,%1,%z2";
12703 case SYNC_INSN1_XORI
:
12704 return "xori\t%0,%1,%2";
12706 gcc_unreachable ();
12709 /* Return the asm template associated with sync_insn2 value TYPE. */
12711 static const char *
12712 mips_sync_insn2_template (enum attr_sync_insn2 type
)
12716 case SYNC_INSN2_NOP
:
12717 gcc_unreachable ();
12718 case SYNC_INSN2_AND
:
12719 return "and\t%0,%1,%z2";
12720 case SYNC_INSN2_XOR
:
12721 return "xor\t%0,%1,%z2";
12722 case SYNC_INSN2_NOT
:
12723 return "nor\t%0,%1,%.";
12725 gcc_unreachable ();
12728 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12729 the value of the one of the sync_* attributes. Return the operand
12730 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12731 have the associated attribute. */
12734 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
12737 default_value
= operands
[index
- 1];
12738 return default_value
;
12741 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12742 sequence for it. */
12745 mips_process_sync_loop (rtx insn
, rtx
*operands
)
12747 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
12748 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
12749 unsigned int tmp3_insn
;
12750 enum attr_sync_insn1 insn1
;
12751 enum attr_sync_insn2 insn2
;
12754 enum memmodel model
;
12756 /* Read an operand from the sync_WHAT attribute and store it in
12757 variable WHAT. DEFAULT is the default value if no attribute
12759 #define READ_OPERAND(WHAT, DEFAULT) \
12760 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12763 /* Read the memory. */
12764 READ_OPERAND (mem
, 0);
12766 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
12768 /* Read the other attributes. */
12769 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
12770 READ_OPERAND (oldval
, at
);
12771 READ_OPERAND (cmp
, 0);
12772 READ_OPERAND (newval
, at
);
12773 READ_OPERAND (inclusive_mask
, 0);
12774 READ_OPERAND (exclusive_mask
, 0);
12775 READ_OPERAND (required_oldval
, 0);
12776 READ_OPERAND (insn1_op2
, 0);
12777 insn1
= get_attr_sync_insn1 (insn
);
12778 insn2
= get_attr_sync_insn2 (insn
);
12780 /* Don't bother setting CMP result that is never used. */
12781 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
12784 memmodel_attr
= get_attr_sync_memmodel (insn
);
12785 switch (memmodel_attr
)
12788 model
= MEMMODEL_ACQ_REL
;
12791 model
= MEMMODEL_ACQUIRE
;
12794 model
= (enum memmodel
) INTVAL (operands
[memmodel_attr
]);
12797 mips_multi_start ();
12799 /* Output the release side of the memory barrier. */
12800 if (need_atomic_barrier_p (model
, true))
12802 if (required_oldval
== 0 && TARGET_OCTEON
)
12804 /* Octeon doesn't reorder reads, so a full barrier can be
12805 created by using SYNCW to order writes combined with the
12806 write from the following SC. When the SC successfully
12807 completes, we know that all preceding writes are also
12808 committed to the coherent memory system. It is possible
12809 for a single SYNCW to fail, but a pair of them will never
12810 fail, so we use two. */
12811 mips_multi_add_insn ("syncw", NULL
);
12812 mips_multi_add_insn ("syncw", NULL
);
12815 mips_multi_add_insn ("sync", NULL
);
12818 /* Output the branch-back label. */
12819 mips_multi_add_label ("1:");
12821 /* OLDVAL = *MEM. */
12822 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
12823 oldval
, mem
, NULL
);
12825 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12826 if (required_oldval
)
12828 if (inclusive_mask
== 0)
12832 gcc_assert (oldval
!= at
);
12833 mips_multi_add_insn ("and\t%0,%1,%2",
12834 at
, oldval
, inclusive_mask
, NULL
);
12837 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
12839 /* CMP = 0 [delay slot]. */
12841 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
12844 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12845 if (exclusive_mask
== 0)
12849 gcc_assert (oldval
!= at
);
12850 mips_multi_add_insn ("and\t%0,%1,%z2",
12851 at
, oldval
, exclusive_mask
, NULL
);
12855 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12857 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12858 at least one instruction in that case. */
12859 if (insn1
== SYNC_INSN1_MOVE
12860 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
12864 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
12865 newval
, oldval
, insn1_op2
, NULL
);
12869 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12870 if (insn2
== SYNC_INSN2_NOP
)
12874 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
12875 newval
, tmp2
, inclusive_mask
, NULL
);
12878 tmp3_insn
= mips_multi_last_index ();
12880 /* $AT = $TMP1 | $TMP3. */
12881 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
12883 mips_multi_set_operand (tmp3_insn
, 0, at
);
12888 gcc_assert (tmp1
!= tmp3
);
12889 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
12892 /* if (!commit (*MEM = $AT)) goto 1.
12894 This will sometimes be a delayed branch; see the write code below
12896 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
12897 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
12899 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12900 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
12902 mips_multi_copy_insn (tmp3_insn
);
12903 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
12905 else if (!(required_oldval
&& cmp
))
12906 mips_multi_add_insn ("nop", NULL
);
12908 /* CMP = 1 -- either standalone or in a delay slot. */
12909 if (required_oldval
&& cmp
)
12910 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
12912 /* Output the acquire side of the memory barrier. */
12913 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
12914 mips_multi_add_insn ("sync", NULL
);
12916 /* Output the exit label, if needed. */
12917 if (required_oldval
)
12918 mips_multi_add_label ("2:");
12920 #undef READ_OPERAND
12923 /* Output and/or return the asm template for sync loop INSN, which has
12924 the operands given by OPERANDS. */
12927 mips_output_sync_loop (rtx insn
, rtx
*operands
)
12929 mips_process_sync_loop (insn
, operands
);
12931 /* Use branch-likely instructions to work around the LL/SC R10000
12933 mips_branch_likely
= TARGET_FIX_R10000
;
12935 mips_push_asm_switch (&mips_noreorder
);
12936 mips_push_asm_switch (&mips_nomacro
);
12937 mips_push_asm_switch (&mips_noat
);
12938 mips_start_ll_sc_sync_block ();
12940 mips_multi_write ();
12942 mips_end_ll_sc_sync_block ();
12943 mips_pop_asm_switch (&mips_noat
);
12944 mips_pop_asm_switch (&mips_nomacro
);
12945 mips_pop_asm_switch (&mips_noreorder
);
12950 /* Return the number of individual instructions in sync loop INSN,
12951 which has the operands given by OPERANDS. */
12954 mips_sync_loop_insns (rtx insn
, rtx
*operands
)
12956 mips_process_sync_loop (insn
, operands
);
12957 return mips_multi_num_insns
;
12960 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12961 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12963 When working around R4000 and R4400 errata, we need to make sure that
12964 the division is not immediately followed by a shift[1][2]. We also
12965 need to stop the division from being put into a branch delay slot[3].
12966 The easiest way to avoid both problems is to add a nop after the
12967 division. When a divide-by-zero check is needed, this nop can be
12968 used to fill the branch delay slot.
12970 [1] If a double-word or a variable shift executes immediately
12971 after starting an integer division, the shift may give an
12972 incorrect result. See quotations of errata #16 and #28 from
12973 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12974 in mips.md for details.
12976 [2] A similar bug to [1] exists for all revisions of the
12977 R4000 and the R4400 when run in an MC configuration.
12978 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12980 "19. In this following sequence:
12982 ddiv (or ddivu or div or divu)
12983 dsll32 (or dsrl32, dsra32)
12985 if an MPT stall occurs, while the divide is slipping the cpu
12986 pipeline, then the following double shift would end up with an
12989 Workaround: The compiler needs to avoid generating any
12990 sequence with divide followed by extended double shift."
12992 This erratum is also present in "MIPS R4400MC Errata, Processor
12993 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12994 & 3.0" as errata #10 and #4, respectively.
12996 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12997 (also valid for MIPS R4000MC processors):
12999 "52. R4000SC: This bug does not apply for the R4000PC.
13001 There are two flavors of this bug:
13003 1) If the instruction just after divide takes an RF exception
13004 (tlb-refill, tlb-invalid) and gets an instruction cache
13005 miss (both primary and secondary) and the line which is
13006 currently in secondary cache at this index had the first
13007 data word, where the bits 5..2 are set, then R4000 would
13008 get a wrong result for the div.
13013 ------------------- # end-of page. -tlb-refill
13018 ------------------- # end-of page. -tlb-invalid
13021 2) If the divide is in the taken branch delay slot, where the
13022 target takes RF exception and gets an I-cache miss for the
13023 exception vector or where I-cache miss occurs for the
13024 target address, under the above mentioned scenarios, the
13025 div would get wrong results.
13028 j r2 # to next page mapped or unmapped
13029 div r8,r9 # this bug would be there as long
13030 # as there is an ICache miss and
13031 nop # the "data pattern" is present
13034 beq r0, r0, NextPage # to Next page
13038 This bug is present for div, divu, ddiv, and ddivu
13041 Workaround: For item 1), OS could make sure that the next page
13042 after the divide instruction is also mapped. For item 2), the
13043 compiler could make sure that the divide instruction is not in
13044 the branch delay slot."
13046 These processors have PRId values of 0x00004220 and 0x00004300 for
13047 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
13050 mips_output_division (const char *division
, rtx
*operands
)
13055 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
13057 output_asm_insn (s
, operands
);
13060 if (TARGET_CHECK_ZERO_DIV
)
13064 output_asm_insn (s
, operands
);
13065 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
13067 else if (GENERATE_DIVIDE_TRAPS
)
13069 /* Avoid long replay penalty on load miss by putting the trap before
13072 output_asm_insn ("teq\t%2,%.,7", operands
);
13075 output_asm_insn (s
, operands
);
13076 s
= "teq\t%2,%.,7";
13081 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
13082 output_asm_insn (s
, operands
);
13083 s
= "break\t7%)\n1:";
13089 /* Return true if destination of IN_INSN is used as add source in
13090 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
13091 madd.s dst, x, y, z
13092 madd.s a, dst, b, c */
13095 mips_fmadd_bypass (rtx out_insn
, rtx in_insn
)
13097 int dst_reg
, src_reg
;
13099 gcc_assert (get_attr_type (in_insn
) == TYPE_FMADD
);
13100 gcc_assert (get_attr_type (out_insn
) == TYPE_FMADD
);
13102 extract_insn (in_insn
);
13103 dst_reg
= REG_P (recog_data
.operand
[0]);
13105 extract_insn (out_insn
);
13106 src_reg
= REG_P (recog_data
.operand
[1]);
13108 if (dst_reg
== src_reg
)
13114 /* Return true if IN_INSN is a multiply-add or multiply-subtract
13115 instruction and if OUT_INSN assigns to the accumulator operand. */
13118 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
13120 enum attr_accum_in accum_in
;
13121 int accum_in_opnum
;
13124 if (recog_memoized (in_insn
) < 0)
13127 accum_in
= get_attr_accum_in (in_insn
);
13128 if (accum_in
== ACCUM_IN_NONE
)
13131 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
13133 extract_insn (in_insn
);
13134 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
13135 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
13137 return reg_set_p (accum_in_op
, out_insn
);
13140 /* True if the dependency between OUT_INSN and IN_INSN is on the store
13141 data rather than the address. We need this because the cprestore
13142 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
13143 which causes the default routine to abort. We just return false
13147 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
13149 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
13152 return !store_data_bypass_p (out_insn
, in_insn
);
13156 /* Variables and flags used in scheduler hooks when tuning for
13160 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13163 /* If true, then next ALU1/2 instruction will go to ALU1. */
13166 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13169 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13170 int alu1_core_unit_code
;
13171 int alu2_core_unit_code
;
13172 int falu1_core_unit_code
;
13173 int falu2_core_unit_code
;
13175 /* True if current cycle has a multi instruction.
13176 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13177 bool cycle_has_multi_p
;
13179 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13180 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13182 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13183 instruction to go ALU1. */
13184 rtx alu1_turn_enabled_insn
;
13185 rtx alu2_turn_enabled_insn
;
13186 rtx falu1_turn_enabled_insn
;
13187 rtx falu2_turn_enabled_insn
;
13190 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13191 dependencies have no cost, except on the 20Kc where output-dependence
13192 is treated like input-dependence. */
13195 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
13196 rtx dep ATTRIBUTE_UNUSED
, int cost
)
13198 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
13201 if (REG_NOTE_KIND (link
) != 0)
13206 /* Return the number of instructions that can be issued per cycle. */
13209 mips_issue_rate (void)
13213 case PROCESSOR_74KC
:
13214 case PROCESSOR_74KF2_1
:
13215 case PROCESSOR_74KF1_1
:
13216 case PROCESSOR_74KF3_2
:
13217 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13218 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13219 but in reality only a maximum of 3 insns can be issued as
13220 floating-point loads and stores also require a slot in the
13222 case PROCESSOR_R10000
:
13223 /* All R10K Processors are quad-issue (being the first MIPS
13224 processors to support this feature). */
13227 case PROCESSOR_20KC
:
13228 case PROCESSOR_R4130
:
13229 case PROCESSOR_R5400
:
13230 case PROCESSOR_R5500
:
13231 case PROCESSOR_R5900
:
13232 case PROCESSOR_R7000
:
13233 case PROCESSOR_R9000
:
13234 case PROCESSOR_OCTEON
:
13235 case PROCESSOR_OCTEON2
:
13238 case PROCESSOR_SB1
:
13239 case PROCESSOR_SB1A
:
13240 /* This is actually 4, but we get better performance if we claim 3.
13241 This is partly because of unwanted speculative code motion with the
13242 larger number, and partly because in most common cases we can't
13243 reach the theoretical max of 4. */
13246 case PROCESSOR_LOONGSON_2E
:
13247 case PROCESSOR_LOONGSON_2F
:
13248 case PROCESSOR_LOONGSON_3A
:
13249 case PROCESSOR_P5600
:
13252 case PROCESSOR_XLP
:
13253 return (reload_completed
? 4 : 3);
13260 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13263 mips_ls2_init_dfa_post_cycle_insn (void)
13266 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13267 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
13271 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13272 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
13276 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13277 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
13281 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13282 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
13285 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
13286 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
13287 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
13288 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
13291 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13292 Init data used in mips_dfa_post_advance_cycle. */
13295 mips_init_dfa_post_cycle_insn (void)
13297 if (TUNE_LOONGSON_2EF
)
13298 mips_ls2_init_dfa_post_cycle_insn ();
13301 /* Initialize STATE when scheduling for Loongson 2E/2F.
13302 Support round-robin dispatch scheme by enabling only one of
13303 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13307 mips_ls2_dfa_post_advance_cycle (state_t state
)
13309 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
13311 /* Though there are no non-pipelined ALU1 insns,
13312 we can get an instruction of type 'multi' before reload. */
13313 gcc_assert (mips_ls2
.cycle_has_multi_p
);
13314 mips_ls2
.alu1_turn_p
= false;
13317 mips_ls2
.cycle_has_multi_p
= false;
13319 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
13320 /* We have a non-pipelined alu instruction in the core,
13321 adjust round-robin counter. */
13322 mips_ls2
.alu1_turn_p
= true;
13324 if (mips_ls2
.alu1_turn_p
)
13326 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
13327 gcc_unreachable ();
13331 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
13332 gcc_unreachable ();
13335 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
13337 /* There are no non-pipelined FALU1 insns. */
13338 gcc_unreachable ();
13339 mips_ls2
.falu1_turn_p
= false;
13342 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
13343 /* We have a non-pipelined falu instruction in the core,
13344 adjust round-robin counter. */
13345 mips_ls2
.falu1_turn_p
= true;
13347 if (mips_ls2
.falu1_turn_p
)
13349 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
13350 gcc_unreachable ();
13354 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
13355 gcc_unreachable ();
13359 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13360 This hook is being called at the start of each cycle. */
13363 mips_dfa_post_advance_cycle (void)
13365 if (TUNE_LOONGSON_2EF
)
13366 mips_ls2_dfa_post_advance_cycle (curr_state
);
13369 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13370 be as wide as the scheduling freedom in the DFA. */
13373 mips_multipass_dfa_lookahead (void)
13375 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13379 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
13391 /* Remove the instruction at index LOWER from ready queue READY and
13392 reinsert it in front of the instruction at index HIGHER. LOWER must
13396 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
13401 new_head
= ready
[lower
];
13402 for (i
= lower
; i
< higher
; i
++)
13403 ready
[i
] = ready
[i
+ 1];
13404 ready
[i
] = new_head
;
13407 /* If the priority of the instruction at POS2 in the ready queue READY
13408 is within LIMIT units of that of the instruction at POS1, swap the
13409 instructions if POS2 is not already less than POS1. */
13412 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
13415 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
13419 temp
= ready
[pos1
];
13420 ready
[pos1
] = ready
[pos2
];
13421 ready
[pos2
] = temp
;
13425 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13426 that may clobber hi or lo. */
13427 static rtx mips_macc_chains_last_hilo
;
13429 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13430 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13433 mips_macc_chains_record (rtx insn
)
13435 if (get_attr_may_clobber_hilo (insn
))
13436 mips_macc_chains_last_hilo
= insn
;
13439 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13440 has NREADY elements, looking for a multiply-add or multiply-subtract
13441 instruction that is cumulative with mips_macc_chains_last_hilo.
13442 If there is one, promote it ahead of anything else that might
13443 clobber hi or lo. */
13446 mips_macc_chains_reorder (rtx
*ready
, int nready
)
13450 if (mips_macc_chains_last_hilo
!= 0)
13451 for (i
= nready
- 1; i
>= 0; i
--)
13452 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
13454 for (j
= nready
- 1; j
> i
; j
--)
13455 if (recog_memoized (ready
[j
]) >= 0
13456 && get_attr_may_clobber_hilo (ready
[j
]))
13458 mips_promote_ready (ready
, i
, j
);
13465 /* The last instruction to be scheduled. */
13466 static rtx vr4130_last_insn
;
13468 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13469 points to an rtx that is initially an instruction. Nullify the rtx
13470 if the instruction uses the value of register X. */
13473 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13478 insn_ptr
= (rtx
*) data
;
13481 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
13485 /* Return true if there is true register dependence between vr4130_last_insn
13489 vr4130_true_reg_dependence_p (rtx insn
)
13491 note_stores (PATTERN (vr4130_last_insn
),
13492 vr4130_true_reg_dependence_p_1
, &insn
);
13496 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13497 the ready queue and that INSN2 is the instruction after it, return
13498 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13499 in which INSN1 and INSN2 can probably issue in parallel, but for
13500 which (INSN2, INSN1) should be less sensitive to instruction
13501 alignment than (INSN1, INSN2). See 4130.md for more details. */
13504 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
13506 sd_iterator_def sd_it
;
13509 /* Check for the following case:
13511 1) there is some other instruction X with an anti dependence on INSN1;
13512 2) X has a higher priority than INSN2; and
13513 3) X is an arithmetic instruction (and thus has no unit restrictions).
13515 If INSN1 is the last instruction blocking X, it would better to
13516 choose (INSN1, X) over (INSN2, INSN1). */
13517 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
13518 if (DEP_TYPE (dep
) == REG_DEP_ANTI
13519 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
13520 && recog_memoized (DEP_CON (dep
)) >= 0
13521 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
13524 if (vr4130_last_insn
!= 0
13525 && recog_memoized (insn1
) >= 0
13526 && recog_memoized (insn2
) >= 0)
13528 /* See whether INSN1 and INSN2 use different execution units,
13529 or if they are both ALU-type instructions. If so, they can
13530 probably execute in parallel. */
13531 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
13532 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
13533 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
13535 /* If only one of the instructions has a dependence on
13536 vr4130_last_insn, prefer to schedule the other one first. */
13537 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
13538 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
13539 if (dep1_p
!= dep2_p
)
13542 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13543 is not an ALU-type instruction and if INSN1 uses the same
13544 execution unit. (Note that if this condition holds, we already
13545 know that INSN2 uses a different execution unit.) */
13546 if (class1
!= VR4130_CLASS_ALU
13547 && recog_memoized (vr4130_last_insn
) >= 0
13548 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
13555 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13556 queue with at least two instructions. Swap the first two if
13557 vr4130_swap_insns_p says that it could be worthwhile. */
13560 vr4130_reorder (rtx
*ready
, int nready
)
13562 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
13563 mips_promote_ready (ready
, nready
- 2, nready
- 1);
13566 /* Record whether last 74k AGEN instruction was a load or store. */
13567 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13569 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13570 resets to TYPE_UNKNOWN state. */
13573 mips_74k_agen_init (rtx insn
)
13575 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
13576 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13579 enum attr_type type
= get_attr_type (insn
);
13580 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
13581 mips_last_74k_agen_insn
= type
;
13585 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13586 loads to be grouped together, and multiple stores to be grouped
13587 together. Swap things around in the ready queue to make this happen. */
13590 mips_74k_agen_reorder (rtx
*ready
, int nready
)
13593 int store_pos
, load_pos
;
13598 for (i
= nready
- 1; i
>= 0; i
--)
13600 rtx insn
= ready
[i
];
13601 if (USEFUL_INSN_P (insn
))
13602 switch (get_attr_type (insn
))
13605 if (store_pos
== -1)
13610 if (load_pos
== -1)
13619 if (load_pos
== -1 || store_pos
== -1)
13622 switch (mips_last_74k_agen_insn
)
13625 /* Prefer to schedule loads since they have a higher latency. */
13627 /* Swap loads to the front of the queue. */
13628 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
13631 /* Swap stores to the front of the queue. */
13632 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
13639 /* Implement TARGET_SCHED_INIT. */
13642 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13643 int max_ready ATTRIBUTE_UNUSED
)
13645 mips_macc_chains_last_hilo
= 0;
13646 vr4130_last_insn
= 0;
13647 mips_74k_agen_init (NULL_RTX
);
13649 /* When scheduling for Loongson2, branch instructions go to ALU1,
13650 therefore basic block is most likely to start with round-robin counter
13651 pointed to ALU2. */
13652 mips_ls2
.alu1_turn_p
= false;
13653 mips_ls2
.falu1_turn_p
= true;
13656 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13659 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13660 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13662 if (!reload_completed
13663 && TUNE_MACC_CHAINS
13665 mips_macc_chains_reorder (ready
, *nreadyp
);
13667 if (reload_completed
13669 && !TARGET_VR4130_ALIGN
13671 vr4130_reorder (ready
, *nreadyp
);
13674 mips_74k_agen_reorder (ready
, *nreadyp
);
13677 /* Implement TARGET_SCHED_REORDER. */
13680 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13681 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13683 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13684 return mips_issue_rate ();
13687 /* Implement TARGET_SCHED_REORDER2. */
13690 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13691 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13693 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13694 return cached_can_issue_more
;
13697 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13700 mips_ls2_variable_issue (rtx insn
)
13702 if (mips_ls2
.alu1_turn_p
)
13704 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
13705 mips_ls2
.alu1_turn_p
= false;
13709 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
13710 mips_ls2
.alu1_turn_p
= true;
13713 if (mips_ls2
.falu1_turn_p
)
13715 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
13716 mips_ls2
.falu1_turn_p
= false;
13720 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
13721 mips_ls2
.falu1_turn_p
= true;
13724 if (recog_memoized (insn
) >= 0)
13725 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
13728 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13731 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13732 rtx insn
, int more
)
13734 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13735 if (USEFUL_INSN_P (insn
))
13737 if (get_attr_type (insn
) != TYPE_GHOST
)
13739 if (!reload_completed
&& TUNE_MACC_CHAINS
)
13740 mips_macc_chains_record (insn
);
13741 vr4130_last_insn
= insn
;
13743 mips_74k_agen_init (insn
);
13744 else if (TUNE_LOONGSON_2EF
)
13745 mips_ls2_variable_issue (insn
);
13748 /* Instructions of type 'multi' should all be split before
13749 the second scheduling pass. */
13750 gcc_assert (!reload_completed
13751 || recog_memoized (insn
) < 0
13752 || get_attr_type (insn
) != TYPE_MULTI
);
13754 cached_can_issue_more
= more
;
13758 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13759 return the first operand of the associated PREF or PREFX insn. */
13762 mips_prefetch_cookie (rtx write
, rtx locality
)
13764 /* store_streamed / load_streamed. */
13765 if (INTVAL (locality
) <= 0)
13766 return GEN_INT (INTVAL (write
) + 4);
13768 /* store / load. */
13769 if (INTVAL (locality
) <= 2)
13772 /* store_retained / load_retained. */
13773 return GEN_INT (INTVAL (write
) + 6);
13776 /* Flags that indicate when a built-in function is available.
13778 BUILTIN_AVAIL_NON_MIPS16
13779 The function is available on the current target if !TARGET_MIPS16.
13781 BUILTIN_AVAIL_MIPS16
13782 The function is available on the current target if TARGET_MIPS16. */
13783 #define BUILTIN_AVAIL_NON_MIPS16 1
13784 #define BUILTIN_AVAIL_MIPS16 2
13786 /* Declare an availability predicate for built-in functions that
13787 require non-MIPS16 mode and also require COND to be true.
13788 NAME is the main part of the predicate's name. */
13789 #define AVAIL_NON_MIPS16(NAME, COND) \
13790 static unsigned int \
13791 mips_builtin_avail_##NAME (void) \
13793 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13796 /* Declare an availability predicate for built-in functions that
13797 support both MIPS16 and non-MIPS16 code and also require COND
13798 to be true. NAME is the main part of the predicate's name. */
13799 #define AVAIL_ALL(NAME, COND) \
13800 static unsigned int \
13801 mips_builtin_avail_##NAME (void) \
13803 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
13806 /* This structure describes a single built-in function. */
13807 struct mips_builtin_description
{
13808 /* The code of the main .md file instruction. See mips_builtin_type
13809 for more information. */
13810 enum insn_code icode
;
13812 /* The floating-point comparison code to use with ICODE, if any. */
13813 enum mips_fp_condition cond
;
13815 /* The name of the built-in function. */
13818 /* Specifies how the function should be expanded. */
13819 enum mips_builtin_type builtin_type
;
13821 /* The function's prototype. */
13822 enum mips_function_type function_type
;
13824 /* Whether the function is available. */
13825 unsigned int (*avail
) (void);
13828 AVAIL_ALL (hard_float
, TARGET_HARD_FLOAT_ABI
)
13829 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
13830 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
13831 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
13832 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
13833 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
13834 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
13835 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
13836 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
13837 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
13838 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
13840 /* Construct a mips_builtin_description from the given arguments.
13842 INSN is the name of the associated instruction pattern, without the
13843 leading CODE_FOR_mips_.
13845 CODE is the floating-point condition code associated with the
13846 function. It can be 'f' if the field is not applicable.
13848 NAME is the name of the function itself, without the leading
13851 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13853 AVAIL is the name of the availability predicate, without the leading
13854 mips_builtin_avail_. */
13855 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13856 FUNCTION_TYPE, AVAIL) \
13857 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13858 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13859 mips_builtin_avail_ ## AVAIL }
13861 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13862 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13863 are as for MIPS_BUILTIN. */
13864 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13865 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13867 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13868 are subject to mips_builtin_avail_<AVAIL>. */
13869 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13870 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13871 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13872 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13873 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13875 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13876 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13877 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13878 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13879 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13880 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13882 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13883 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13885 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13886 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13888 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13889 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13892 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13893 are subject to mips_builtin_avail_mips3d. */
13894 #define CMP_4S_BUILTINS(INSN, COND) \
13895 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13896 MIPS_BUILTIN_CMP_ANY, \
13897 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13898 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13899 MIPS_BUILTIN_CMP_ALL, \
13900 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13902 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13903 instruction requires mips_builtin_avail_<AVAIL>. */
13904 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13905 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13906 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13908 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13909 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13912 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13913 #define CMP_BUILTINS(COND) \
13914 MOVTF_BUILTINS (c, COND, paired_single), \
13915 MOVTF_BUILTINS (cabs, COND, mips3d), \
13916 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13917 CMP_PS_BUILTINS (c, COND, paired_single), \
13918 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13919 CMP_4S_BUILTINS (c, COND), \
13920 CMP_4S_BUILTINS (cabs, COND)
13922 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13923 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13924 and AVAIL are as for MIPS_BUILTIN. */
13925 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13926 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13927 FUNCTION_TYPE, AVAIL)
13929 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13930 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13931 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13932 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13933 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13935 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13936 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13937 builtin_description field. */
13938 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13939 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13940 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13941 FUNCTION_TYPE, mips_builtin_avail_loongson }
13943 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13944 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13945 builtin_description field. */
13946 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13947 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13949 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13950 We use functions of this form when the same insn can be usefully applied
13951 to more than one datatype. */
13952 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13953 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13955 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13956 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13957 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13958 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13959 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13960 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13961 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13962 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13964 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13965 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13966 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13967 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13968 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13969 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13970 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13971 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13972 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13973 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13974 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13975 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13976 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13977 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13978 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13979 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13980 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13981 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13982 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13983 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13984 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13985 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13986 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13987 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13988 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13989 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13990 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13991 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13992 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13993 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13995 static const struct mips_builtin_description mips_builtins
[] = {
13996 #define MIPS_GET_FCSR 0
13997 DIRECT_BUILTIN (get_fcsr
, MIPS_USI_FTYPE_VOID
, hard_float
),
13998 #define MIPS_SET_FCSR 1
13999 DIRECT_NO_TARGET_BUILTIN (set_fcsr
, MIPS_VOID_FTYPE_USI
, hard_float
),
14001 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14002 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14003 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14004 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14005 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
14006 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
14007 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
14008 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
14010 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
14011 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14012 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14013 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14014 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14016 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
14017 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
14018 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14019 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
14020 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
14021 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14023 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
14024 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
14025 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14026 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
14027 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
14028 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14030 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
14032 /* Built-in functions for the SB-1 processor. */
14033 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
14035 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
14036 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14037 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14038 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14039 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14040 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14041 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14042 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14043 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14044 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14045 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14046 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14047 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14048 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14049 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
14050 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
14051 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
14052 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
14053 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
14054 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
14055 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
14056 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
14057 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
14058 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14059 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14060 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14061 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14062 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14063 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14064 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14065 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14066 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
14067 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14068 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14069 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14070 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
14071 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14072 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14073 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14074 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
14075 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
14076 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14077 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
14078 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
14079 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
14080 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14081 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
14082 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
14083 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14084 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14085 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14086 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14087 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14088 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14089 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14090 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14091 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14092 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14093 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14094 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14095 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
14096 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
14097 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14098 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14099 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14100 BPOSGE_BUILTIN (32, dsp
),
14102 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
14103 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
14104 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14105 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14106 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14107 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14108 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14109 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14110 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14111 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14112 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14113 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14114 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14115 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14116 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14117 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14118 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
14119 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
14120 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
14121 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14122 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
14123 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
14124 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
14125 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14126 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14127 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14128 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14129 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14130 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14131 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14132 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14133 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14134 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14135 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14136 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14138 /* Built-in functions for the DSP ASE (32-bit only). */
14139 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14140 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14141 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14142 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14143 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14144 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14145 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14146 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14147 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14148 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14149 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14150 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14151 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14152 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14153 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14154 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14155 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14156 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14157 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14158 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14159 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14160 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14161 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14162 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14163 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14164 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
14165 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
14167 /* Built-in functions for the DSP ASE (64-bit only). */
14168 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
14170 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14171 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14172 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14173 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14174 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14175 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14176 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14177 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14178 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14179 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14181 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14182 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
14183 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
14184 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
14185 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14186 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14187 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14188 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14189 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14190 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14191 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14192 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
14193 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14194 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14195 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14196 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14197 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
14198 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14199 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14200 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14201 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
14202 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14203 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14204 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14205 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14206 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14207 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14208 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14209 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14210 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14211 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14212 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14213 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14214 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14215 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14216 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14217 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14218 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14219 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
14220 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
14221 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14222 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14223 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14224 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14225 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14226 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14227 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14228 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14229 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
14230 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14231 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14232 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14233 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14234 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
14235 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
14236 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14237 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14238 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14239 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
14240 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14241 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
14242 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
14243 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14244 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14245 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14246 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14247 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14248 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14249 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14250 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14251 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14252 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14253 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14254 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14255 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14256 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14257 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14258 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14259 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14260 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14261 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14262 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14263 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14264 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
14265 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14266 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14267 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14268 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14269 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14270 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14271 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14272 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14273 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14274 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14275 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14276 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14277 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14278 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14279 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14280 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14282 /* Sundry other built-in functions. */
14283 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
14286 /* Index I is the function declaration for mips_builtins[I], or null if the
14287 function isn't defined on this target. */
14288 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
14290 /* MODE is a vector mode whose elements have type TYPE. Return the type
14291 of the vector itself. */
14294 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
14296 static tree types
[2 * (int) MAX_MACHINE_MODE
];
14299 mode_index
= (int) mode
;
14301 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
14302 mode_index
+= MAX_MACHINE_MODE
;
14304 if (types
[mode_index
] == NULL_TREE
)
14305 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
14306 return types
[mode_index
];
14309 /* Return a type for 'const volatile void *'. */
14312 mips_build_cvpointer_type (void)
14316 if (cache
== NULL_TREE
)
14317 cache
= build_pointer_type (build_qualified_type
14319 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
14323 /* Source-level argument types. */
14324 #define MIPS_ATYPE_VOID void_type_node
14325 #define MIPS_ATYPE_INT integer_type_node
14326 #define MIPS_ATYPE_POINTER ptr_type_node
14327 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14329 /* Standard mode-based argument types. */
14330 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14331 #define MIPS_ATYPE_SI intSI_type_node
14332 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14333 #define MIPS_ATYPE_DI intDI_type_node
14334 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14335 #define MIPS_ATYPE_SF float_type_node
14336 #define MIPS_ATYPE_DF double_type_node
14338 /* Vector argument types. */
14339 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14340 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14341 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14342 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14343 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14344 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14345 #define MIPS_ATYPE_UV2SI \
14346 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14347 #define MIPS_ATYPE_UV4HI \
14348 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14349 #define MIPS_ATYPE_UV8QI \
14350 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14352 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14353 their associated MIPS_ATYPEs. */
14354 #define MIPS_FTYPE_ATYPES1(A, B) \
14355 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14357 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14358 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14360 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14361 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14363 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14364 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14367 /* Return the function type associated with function prototype TYPE. */
14370 mips_build_function_type (enum mips_function_type type
)
14372 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
14374 if (types
[(int) type
] == NULL_TREE
)
14377 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14378 case MIPS_FTYPE_NAME##NUM ARGS: \
14379 types[(int) type] \
14380 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14383 #include "config/mips/mips-ftypes.def"
14384 #undef DEF_MIPS_FTYPE
14386 gcc_unreachable ();
14389 return types
[(int) type
];
14392 /* Implement TARGET_INIT_BUILTINS. */
14395 mips_init_builtins (void)
14397 const struct mips_builtin_description
*d
;
14400 /* Iterate through all of the bdesc arrays, initializing all of the
14401 builtin functions. */
14402 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
14404 d
= &mips_builtins
[i
];
14406 mips_builtin_decls
[i
]
14407 = add_builtin_function (d
->name
,
14408 mips_build_function_type (d
->function_type
),
14409 i
, BUILT_IN_MD
, NULL
, NULL
);
14413 /* Implement TARGET_BUILTIN_DECL. */
14416 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
14418 if (code
>= ARRAY_SIZE (mips_builtins
))
14419 return error_mark_node
;
14420 return mips_builtin_decls
[code
];
14423 /* Take argument ARGNO from EXP's argument list and convert it into
14424 an expand operand. Store the operand in *OP. */
14427 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
14428 unsigned int argno
)
14433 arg
= CALL_EXPR_ARG (exp
, argno
);
14434 value
= expand_normal (arg
);
14435 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
14438 /* Expand instruction ICODE as part of a built-in function sequence.
14439 Use the first NOPS elements of OPS as the instruction's operands.
14440 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14441 instruction has no target.
14443 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14446 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
14447 struct expand_operand
*ops
, bool has_target_p
)
14449 if (!maybe_expand_insn (icode
, nops
, ops
))
14451 error ("invalid argument to built-in function");
14452 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
14454 return has_target_p
? ops
[0].value
: const0_rtx
;
14457 /* Expand a floating-point comparison for built-in function call EXP.
14458 The first NARGS arguments are the values to be compared. ICODE is
14459 the .md pattern that does the comparison and COND is the condition
14460 that is being tested. Return an rtx for the result. */
14463 mips_expand_builtin_compare_1 (enum insn_code icode
,
14464 enum mips_fp_condition cond
,
14465 tree exp
, int nargs
)
14467 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14471 /* The instruction should have a target operand, an operand for each
14472 argument, and an operand for COND. */
14473 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
14475 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
14477 create_fixed_operand (&ops
[opno
++], output
);
14478 for (argno
= 0; argno
< nargs
; argno
++)
14479 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14480 create_integer_operand (&ops
[opno
++], (int) cond
);
14481 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
14484 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14485 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14486 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14487 suggests a good place to put the result. */
14490 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
14493 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14496 /* Map any target to operand 0. */
14499 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
14501 /* Map the arguments to the other operands. */
14502 gcc_assert (opno
+ call_expr_nargs (exp
)
14503 == insn_data
[icode
].n_generator_args
);
14504 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
14505 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14507 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
14510 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14511 function; TYPE says which. EXP is the CALL_EXPR that calls the
14512 function, ICODE is the instruction that should be used to compare
14513 the first two arguments, and COND is the condition it should test.
14514 TARGET, if nonnull, suggests a good place to put the result. */
14517 mips_expand_builtin_movtf (enum mips_builtin_type type
,
14518 enum insn_code icode
, enum mips_fp_condition cond
,
14519 rtx target
, tree exp
)
14521 struct expand_operand ops
[4];
14524 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
14525 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
14526 if (type
== MIPS_BUILTIN_MOVT
)
14528 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
14529 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
14533 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
14534 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
14536 create_fixed_operand (&ops
[3], cmp_result
);
14537 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
14541 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14542 into TARGET otherwise. Return TARGET. */
14545 mips_builtin_branch_and_move (rtx condition
, rtx target
,
14546 rtx value_if_true
, rtx value_if_false
)
14548 rtx true_label
, done_label
;
14550 true_label
= gen_label_rtx ();
14551 done_label
= gen_label_rtx ();
14553 /* First assume that CONDITION is false. */
14554 mips_emit_move (target
, value_if_false
);
14556 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14557 emit_jump_insn (gen_condjump (condition
, true_label
));
14558 emit_jump_insn (gen_jump (done_label
));
14561 /* Fix TARGET if CONDITION is true. */
14562 emit_label (true_label
);
14563 mips_emit_move (target
, value_if_true
);
14565 emit_label (done_label
);
14569 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14570 the CALL_EXPR that calls the function, ICODE is the code of the
14571 comparison instruction, and COND is the condition it should test.
14572 TARGET, if nonnull, suggests a good place to put the boolean result. */
14575 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
14576 enum insn_code icode
, enum mips_fp_condition cond
,
14577 rtx target
, tree exp
)
14579 rtx offset
, condition
, cmp_result
;
14581 if (target
== 0 || GET_MODE (target
) != SImode
)
14582 target
= gen_reg_rtx (SImode
);
14583 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
14584 call_expr_nargs (exp
));
14586 /* If the comparison sets more than one register, we define the result
14587 to be 0 if all registers are false and -1 if all registers are true.
14588 The value of the complete result is indeterminate otherwise. */
14589 switch (builtin_type
)
14591 case MIPS_BUILTIN_CMP_ALL
:
14592 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
14593 return mips_builtin_branch_and_move (condition
, target
,
14594 const0_rtx
, const1_rtx
);
14596 case MIPS_BUILTIN_CMP_UPPER
:
14597 case MIPS_BUILTIN_CMP_LOWER
:
14598 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
14599 condition
= gen_single_cc (cmp_result
, offset
);
14600 return mips_builtin_branch_and_move (condition
, target
,
14601 const1_rtx
, const0_rtx
);
14604 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
14605 return mips_builtin_branch_and_move (condition
, target
,
14606 const1_rtx
, const0_rtx
);
14610 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14611 if nonnull, suggests a good place to put the boolean result. */
14614 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
14616 rtx condition
, cmp_result
;
14619 if (target
== 0 || GET_MODE (target
) != SImode
)
14620 target
= gen_reg_rtx (SImode
);
14622 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
14624 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
14629 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
14630 return mips_builtin_branch_and_move (condition
, target
,
14631 const1_rtx
, const0_rtx
);
14634 /* Implement TARGET_EXPAND_BUILTIN. */
14637 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14638 enum machine_mode mode
, int ignore
)
14641 unsigned int fcode
, avail
;
14642 const struct mips_builtin_description
*d
;
14644 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14645 fcode
= DECL_FUNCTION_CODE (fndecl
);
14646 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
14647 d
= &mips_builtins
[fcode
];
14648 avail
= d
->avail ();
14649 gcc_assert (avail
!= 0);
14650 if (TARGET_MIPS16
&& !(avail
& BUILTIN_AVAIL_MIPS16
))
14652 error ("built-in function %qE not supported for MIPS16",
14653 DECL_NAME (fndecl
));
14654 return ignore
? const0_rtx
: CONST0_RTX (mode
);
14656 switch (d
->builtin_type
)
14658 case MIPS_BUILTIN_DIRECT
:
14659 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
14661 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
14662 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
14664 case MIPS_BUILTIN_MOVT
:
14665 case MIPS_BUILTIN_MOVF
:
14666 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
14667 d
->cond
, target
, exp
);
14669 case MIPS_BUILTIN_CMP_ANY
:
14670 case MIPS_BUILTIN_CMP_ALL
:
14671 case MIPS_BUILTIN_CMP_UPPER
:
14672 case MIPS_BUILTIN_CMP_LOWER
:
14673 case MIPS_BUILTIN_CMP_SINGLE
:
14674 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
14675 d
->cond
, target
, exp
);
14677 case MIPS_BUILTIN_BPOSGE32
:
14678 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
14680 gcc_unreachable ();
14683 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14684 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14685 struct mips16_constant
{
14686 struct mips16_constant
*next
;
14689 enum machine_mode mode
;
14692 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14693 first constant, HIGHEST_ADDRESS is the highest address that the first
14694 byte of the pool can have, and INSN_ADDRESS is the current instruction
14696 struct mips16_constant_pool
{
14697 struct mips16_constant
*first
;
14698 int highest_address
;
14702 /* Add constant VALUE to POOL and return its label. MODE is the
14703 value's mode (used for CONST_INTs, etc.). */
14706 mips16_add_constant (struct mips16_constant_pool
*pool
,
14707 rtx value
, enum machine_mode mode
)
14709 struct mips16_constant
**p
, *c
;
14710 bool first_of_size_p
;
14712 /* See whether the constant is already in the pool. If so, return the
14713 existing label, otherwise leave P pointing to the place where the
14714 constant should be added.
14716 Keep the pool sorted in increasing order of mode size so that we can
14717 reduce the number of alignments needed. */
14718 first_of_size_p
= true;
14719 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
14721 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
14722 return (*p
)->label
;
14723 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
14725 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
14726 first_of_size_p
= false;
14729 /* In the worst case, the constant needed by the earliest instruction
14730 will end up at the end of the pool. The entire pool must then be
14731 accessible from that instruction.
14733 When adding the first constant, set the pool's highest address to
14734 the address of the first out-of-range byte. Adjust this address
14735 downwards each time a new constant is added. */
14736 if (pool
->first
== 0)
14737 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14738 of the instruction with the lowest two bits clear. The base PC
14739 value for LDPC has the lowest three bits clear. Assume the worst
14740 case here; namely that the PC-relative instruction occupies the
14741 last 2 bytes in an aligned word. */
14742 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
14743 pool
->highest_address
-= GET_MODE_SIZE (mode
);
14744 if (first_of_size_p
)
14745 /* Take into account the worst possible padding due to alignment. */
14746 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
14748 /* Create a new entry. */
14749 c
= XNEW (struct mips16_constant
);
14752 c
->label
= gen_label_rtx ();
14759 /* Output constant VALUE after instruction INSN and return the last
14760 instruction emitted. MODE is the mode of the constant. */
14763 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
14765 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
14767 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
14768 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
14771 if (SCALAR_FLOAT_MODE_P (mode
))
14772 return emit_insn_after (gen_consttable_float (value
), insn
);
14774 if (VECTOR_MODE_P (mode
))
14778 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
14779 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
14780 CONST_VECTOR_ELT (value
, i
), insn
);
14784 gcc_unreachable ();
14787 /* Dump out the constants in CONSTANTS after INSN. */
14790 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
14792 struct mips16_constant
*c
, *next
;
14796 for (c
= constants
; c
!= NULL
; c
= next
)
14798 /* If necessary, increase the alignment of PC. */
14799 if (align
< GET_MODE_SIZE (c
->mode
))
14801 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
14802 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
14804 align
= GET_MODE_SIZE (c
->mode
);
14806 insn
= emit_label_after (c
->label
, insn
);
14807 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
14813 emit_barrier_after (insn
);
14816 /* Return the length of instruction INSN. */
14819 mips16_insn_length (rtx insn
)
14821 if (JUMP_TABLE_DATA_P (insn
))
14823 rtx body
= PATTERN (insn
);
14824 if (GET_CODE (body
) == ADDR_VEC
)
14825 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
14826 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
14827 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
14829 gcc_unreachable ();
14831 return get_attr_length (insn
);
14834 /* If *X is a symbolic constant that refers to the constant pool, add
14835 the constant to POOL and rewrite *X to use the constant's label. */
14838 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
14840 rtx base
, offset
, label
;
14842 split_const (*x
, &base
, &offset
);
14843 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
14845 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
14846 get_pool_mode (base
));
14847 base
= gen_rtx_LABEL_REF (Pmode
, label
);
14848 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
14852 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14853 INSN is the instruction we're rewriting and POOL points to the current
14855 struct mips16_rewrite_pool_refs_info
{
14857 struct mips16_constant_pool
*pool
;
14860 /* Rewrite *X so that constant pool references refer to the constant's
14861 label instead. DATA points to a mips16_rewrite_pool_refs_info
14865 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
14867 struct mips16_rewrite_pool_refs_info
*info
=
14868 (struct mips16_rewrite_pool_refs_info
*) data
;
14870 if (force_to_mem_operand (*x
, Pmode
))
14872 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
14873 validate_change (info
->insn
, x
, mem
, false);
14878 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
14882 /* Don't rewrite the __mips16_rdwr symbol. */
14883 if (GET_CODE (*x
) == UNSPEC
&& XINT (*x
, 1) == UNSPEC_TLS_GET_TP
)
14886 if (TARGET_MIPS16_TEXT_LOADS
)
14887 mips16_rewrite_pool_constant (info
->pool
, x
);
14889 return GET_CODE (*x
) == CONST
? -1 : 0;
14892 /* Return whether CFG is used in mips_reorg. */
14895 mips_cfg_in_reorg (void)
14897 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
14898 || TARGET_RELAX_PIC_CALLS
);
14901 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14902 otherwise assume that they are already split. */
14905 mips16_lay_out_constants (bool split_p
)
14907 struct mips16_constant_pool pool
;
14908 struct mips16_rewrite_pool_refs_info info
;
14911 if (!TARGET_MIPS16_PCREL_LOADS
)
14916 if (mips_cfg_in_reorg ())
14917 split_all_insns ();
14919 split_all_insns_noflow ();
14922 memset (&pool
, 0, sizeof (pool
));
14923 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14925 /* Rewrite constant pool references in INSN. */
14926 if (USEFUL_INSN_P (insn
))
14930 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
14933 pool
.insn_address
+= mips16_insn_length (insn
);
14935 if (pool
.first
!= NULL
)
14937 /* If there are no natural barriers between the first user of
14938 the pool and the highest acceptable address, we'll need to
14939 create a new instruction to jump around the constant pool.
14940 In the worst case, this instruction will be 4 bytes long.
14942 If it's too late to do this transformation after INSN,
14943 do it immediately before INSN. */
14944 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
14948 label
= gen_label_rtx ();
14950 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
14951 JUMP_LABEL (jump
) = label
;
14952 LABEL_NUSES (label
) = 1;
14953 barrier
= emit_barrier_after (jump
);
14955 emit_label_after (label
, barrier
);
14956 pool
.insn_address
+= 4;
14959 /* See whether the constant pool is now out of range of the first
14960 user. If so, output the constants after the previous barrier.
14961 Note that any instructions between BARRIER and INSN (inclusive)
14962 will use negative offsets to refer to the pool. */
14963 if (pool
.insn_address
> pool
.highest_address
)
14965 mips16_emit_constants (pool
.first
, barrier
);
14969 else if (BARRIER_P (insn
))
14973 mips16_emit_constants (pool
.first
, get_last_insn ());
14976 /* Return true if it is worth r10k_simplify_address's while replacing
14977 an address with X. We are looking for constants, and for addresses
14978 at a known offset from the incoming stack pointer. */
14981 r10k_simplified_address_p (rtx x
)
14983 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
14985 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
14988 /* X is an expression that appears in INSN. Try to use the UD chains
14989 to simplify it, returning the simplified form on success and the
14990 original form otherwise. Replace the incoming value of $sp with
14991 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14994 r10k_simplify_address (rtx x
, rtx insn
)
14996 rtx newx
, op0
, op1
, set
, def_insn
, note
;
14998 struct df_link
*defs
;
15003 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
15004 if (op0
!= XEXP (x
, 0))
15005 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
15006 op0
, GET_MODE (XEXP (x
, 0)));
15008 else if (BINARY_P (x
))
15010 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
15011 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
15012 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
15013 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
15015 else if (GET_CODE (x
) == LO_SUM
)
15017 /* LO_SUMs can be offset from HIGHs, if we know they won't
15018 overflow. See mips_classify_address for the rationale behind
15020 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
15021 if (GET_CODE (op0
) == HIGH
)
15022 newx
= XEXP (x
, 1);
15024 else if (REG_P (x
))
15026 /* Uses are recorded by regno_reg_rtx, not X itself. */
15027 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
15029 defs
= DF_REF_CHAIN (use
);
15031 /* Require a single definition. */
15032 if (defs
&& defs
->next
== NULL
)
15035 if (DF_REF_IS_ARTIFICIAL (def
))
15037 /* Replace the incoming value of $sp with
15038 virtual_incoming_args_rtx. */
15039 if (x
== stack_pointer_rtx
15040 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR_FOR_FN (cfun
))
15041 newx
= virtual_incoming_args_rtx
;
15043 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
15046 /* Make sure that DEF_INSN is a single set of REG. */
15047 def_insn
= DF_REF_INSN (def
);
15048 if (NONJUMP_INSN_P (def_insn
))
15050 set
= single_set (def_insn
);
15051 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
15053 /* Prefer to use notes, since the def-use chains
15054 are often shorter. */
15055 note
= find_reg_equal_equiv_note (def_insn
);
15057 newx
= XEXP (note
, 0);
15059 newx
= SET_SRC (set
);
15060 newx
= r10k_simplify_address (newx
, def_insn
);
15066 if (newx
&& r10k_simplified_address_p (newx
))
15071 /* Return true if ADDRESS is known to be an uncached address
15072 on R10K systems. */
15075 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
15077 unsigned HOST_WIDE_INT upper
;
15079 /* Check for KSEG1. */
15080 if (address
+ 0x60000000 < 0x20000000)
15083 /* Check for uncached XKPHYS addresses. */
15084 if (Pmode
== DImode
)
15086 upper
= (address
>> 40) & 0xf9ffff;
15087 if (upper
== 0x900000 || upper
== 0xb80000)
15093 /* Return true if we can prove that an access to address X in instruction
15094 INSN would be safe from R10K speculation. This X is a general
15095 expression; it might not be a legitimate address. */
15098 r10k_safe_address_p (rtx x
, rtx insn
)
15101 HOST_WIDE_INT offset_val
;
15103 x
= r10k_simplify_address (x
, insn
);
15105 /* Check for references to the stack frame. It doesn't really matter
15106 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
15107 allows us to assume that accesses to any part of the eventual frame
15108 is safe from speculation at any point in the function. */
15109 mips_split_plus (x
, &base
, &offset_val
);
15110 if (base
== virtual_incoming_args_rtx
15111 && offset_val
>= -cfun
->machine
->frame
.total_size
15112 && offset_val
< cfun
->machine
->frame
.args_size
)
15115 /* Check for uncached addresses. */
15116 if (CONST_INT_P (x
))
15117 return r10k_uncached_address_p (INTVAL (x
));
15119 /* Check for accesses to a static object. */
15120 split_const (x
, &base
, &offset
);
15121 return offset_within_block_p (base
, INTVAL (offset
));
15124 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
15125 an in-range access to an automatic variable, or to an object with
15126 a link-time-constant address. */
15129 r10k_safe_mem_expr_p (tree expr
, unsigned HOST_WIDE_INT offset
)
15131 HOST_WIDE_INT bitoffset
, bitsize
;
15132 tree inner
, var_offset
;
15133 enum machine_mode mode
;
15134 int unsigned_p
, volatile_p
;
15136 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
15137 &unsigned_p
, &volatile_p
, false);
15138 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
15141 offset
+= bitoffset
/ BITS_PER_UNIT
;
15142 return offset
< tree_to_uhwi (DECL_SIZE_UNIT (inner
));
15145 /* A for_each_rtx callback for which DATA points to the instruction
15146 containing *X. Stop the search if we find a MEM that is not safe
15147 from R10K speculation. */
15150 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
15159 && MEM_OFFSET_KNOWN_P (mem
)
15160 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
15163 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
15169 /* A note_stores callback for which DATA points to an instruction pointer.
15170 If *DATA is nonnull, make it null if it X contains a MEM that is not
15171 safe from R10K speculation. */
15174 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
15179 insn_ptr
= (rtx
*) data
;
15180 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
15181 *insn_ptr
= NULL_RTX
;
15184 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
15185 Return nonzero if the call is not to a declared function. */
15188 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
15197 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
15203 /* Return true if instruction INSN needs to be protected by an R10K
15207 r10k_needs_protection_p (rtx insn
)
15210 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
15212 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
15214 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
15215 return insn
== NULL_RTX
;
15218 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
15221 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15222 edge is unconditional. */
15225 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
15230 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
15231 if (!single_succ_p (e
->src
)
15232 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
15233 || (e
->flags
& EDGE_COMPLEX
) != 0)
15238 /* Implement -mr10k-cache-barrier= for the current function. */
15241 r10k_insert_cache_barriers (void)
15243 int *rev_post_order
;
15246 sbitmap protected_bbs
;
15247 rtx insn
, end
, unprotected_region
;
15251 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15255 /* Calculate dominators. */
15256 calculate_dominance_info (CDI_DOMINATORS
);
15258 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15259 X is protected by a cache barrier. */
15260 protected_bbs
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
15261 bitmap_clear (protected_bbs
);
15263 /* Iterate over the basic blocks in reverse post-order. */
15264 rev_post_order
= XNEWVEC (int, last_basic_block_for_fn (cfun
));
15265 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
15266 for (i
= 0; i
< n
; i
++)
15268 bb
= BASIC_BLOCK_FOR_FN (cfun
, rev_post_order
[i
]);
15270 /* If this block is only reached by unconditional edges, and if the
15271 source of every edge is protected, the beginning of the block is
15273 if (r10k_protected_bb_p (bb
, protected_bbs
))
15274 unprotected_region
= NULL_RTX
;
15276 unprotected_region
= pc_rtx
;
15277 end
= NEXT_INSN (BB_END (bb
));
15279 /* UNPROTECTED_REGION is:
15281 - null if we are processing a protected region,
15282 - pc_rtx if we are processing an unprotected region but have
15283 not yet found the first instruction in it
15284 - the first instruction in an unprotected region otherwise. */
15285 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
15287 if (unprotected_region
&& USEFUL_INSN_P (insn
))
15289 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
15290 /* This CACHE instruction protects the following code. */
15291 unprotected_region
= NULL_RTX
;
15294 /* See if INSN is the first instruction in this
15295 unprotected region. */
15296 if (unprotected_region
== pc_rtx
)
15297 unprotected_region
= insn
;
15299 /* See if INSN needs to be protected. If so,
15300 we must insert a cache barrier somewhere between
15301 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15302 clear which position is better performance-wise,
15303 but as a tie-breaker, we assume that it is better
15304 to allow delay slots to be back-filled where
15305 possible, and that it is better not to insert
15306 barriers in the middle of already-scheduled code.
15307 We therefore insert the barrier at the beginning
15309 if (r10k_needs_protection_p (insn
))
15311 emit_insn_before (gen_r10k_cache_barrier (),
15312 unprotected_region
);
15313 unprotected_region
= NULL_RTX
;
15319 /* The called function is not required to protect the exit path.
15320 The code that follows a call is therefore unprotected. */
15321 unprotected_region
= pc_rtx
;
15324 /* Record whether the end of this block is protected. */
15325 if (unprotected_region
== NULL_RTX
)
15326 bitmap_set_bit (protected_bbs
, bb
->index
);
15328 XDELETEVEC (rev_post_order
);
15330 sbitmap_free (protected_bbs
);
15332 free_dominance_info (CDI_DOMINATORS
);
15335 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15336 otherwise. If INSN has two call rtx, then store the second one in
15340 mips_call_expr_from_insn (rtx insn
, rtx
*second_call
)
15345 if (!CALL_P (insn
))
15348 x
= PATTERN (insn
);
15349 if (GET_CODE (x
) == PARALLEL
)
15351 /* Calls returning complex values have two CALL rtx. Look for the second
15352 one here, and return it via the SECOND_CALL arg. */
15353 x2
= XVECEXP (x
, 0, 1);
15354 if (GET_CODE (x2
) == SET
)
15356 if (GET_CODE (x2
) == CALL
)
15359 x
= XVECEXP (x
, 0, 0);
15361 if (GET_CODE (x
) == SET
)
15363 gcc_assert (GET_CODE (x
) == CALL
);
15368 /* REG is set in DEF. See if the definition is one of the ways we load a
15369 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15370 If it is, return the symbol reference of the function, otherwise return
15373 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15374 the values of source registers, otherwise treat such registers as
15375 having an unknown value. */
15378 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
15382 if (DF_REF_IS_ARTIFICIAL (def
))
15385 def_insn
= DF_REF_INSN (def
);
15386 set
= single_set (def_insn
);
15387 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
15389 rtx note
, src
, symbol
;
15391 /* First see whether the source is a plain symbol. This is used
15392 when calling symbols that are not lazily bound. */
15393 src
= SET_SRC (set
);
15394 if (GET_CODE (src
) == SYMBOL_REF
)
15397 /* Handle %call16 references. */
15398 symbol
= mips_strip_unspec_call (src
);
15401 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15405 /* If we have something more complicated, look for a
15406 REG_EQUAL or REG_EQUIV note. */
15407 note
= find_reg_equal_equiv_note (def_insn
);
15408 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
15409 return XEXP (note
, 0);
15411 /* Follow at most one simple register copy. Such copies are
15412 interesting in cases like:
15416 locally_binding_fn (...);
15421 locally_binding_fn (...);
15423 locally_binding_fn (...);
15425 where the load of locally_binding_fn can legitimately be
15426 hoisted or shared. However, we do not expect to see complex
15427 chains of copies, so a full worklist solution to the problem
15428 would probably be overkill. */
15429 if (recurse_p
&& REG_P (src
))
15430 return mips_find_pic_call_symbol (def_insn
, src
, false);
15436 /* Find the definition of the use of REG in INSN. See if the definition
15437 is one of the ways we load a register with a symbol address for a
15438 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15439 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15440 mips_pic_call_symbol_from_set. */
15443 mips_find_pic_call_symbol (rtx insn
, rtx reg
, bool recurse_p
)
15446 struct df_link
*defs
;
15449 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
15452 defs
= DF_REF_CHAIN (use
);
15455 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15459 /* If we have more than one definition, they need to be identical. */
15460 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
15464 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15465 if (!rtx_equal_p (symbol
, other
))
15472 /* Replace the args_size operand of the call expression CALL with the
15473 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15476 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
15480 args_size
= XEXP (call
, 1);
15481 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
15482 gen_rtvec (2, args_size
, symbol
),
15486 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15487 if instead of the arg_size argument it contains the call attributes. If
15488 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15489 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15493 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
15495 rtx args_size
, symbol
;
15497 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
15500 args_size
= operands
[args_size_opno
];
15501 if (GET_CODE (args_size
) != UNSPEC
)
15503 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
15505 symbol
= XVECEXP (args_size
, 0, 1);
15506 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15508 operands
[args_size_opno
] = symbol
;
15512 /* Use DF to annotate PIC indirect calls with the function symbol they
15516 mips_annotate_pic_calls (void)
15521 FOR_EACH_BB_FN (bb
, cfun
)
15522 FOR_BB_INSNS (bb
, insn
)
15524 rtx call
, reg
, symbol
, second_call
;
15527 call
= mips_call_expr_from_insn (insn
, &second_call
);
15530 gcc_assert (MEM_P (XEXP (call
, 0)));
15531 reg
= XEXP (XEXP (call
, 0), 0);
15535 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
15538 mips_annotate_pic_call_expr (call
, symbol
);
15540 mips_annotate_pic_call_expr (second_call
, symbol
);
15545 /* A temporary variable used by for_each_rtx callbacks, etc. */
15546 static rtx mips_sim_insn
;
15548 /* A structure representing the state of the processor pipeline.
15549 Used by the mips_sim_* family of functions. */
15551 /* The maximum number of instructions that can be issued in a cycle.
15552 (Caches mips_issue_rate.) */
15553 unsigned int issue_rate
;
15555 /* The current simulation time. */
15558 /* How many more instructions can be issued in the current cycle. */
15559 unsigned int insns_left
;
15561 /* LAST_SET[X].INSN is the last instruction to set register X.
15562 LAST_SET[X].TIME is the time at which that instruction was issued.
15563 INSN is null if no instruction has yet set register X. */
15567 } last_set
[FIRST_PSEUDO_REGISTER
];
15569 /* The pipeline's current DFA state. */
15573 /* Reset STATE to the initial simulation state. */
15576 mips_sim_reset (struct mips_sim
*state
)
15578 curr_state
= state
->dfa_state
;
15581 state
->insns_left
= state
->issue_rate
;
15582 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
15583 state_reset (curr_state
);
15585 targetm
.sched
.init (0, false, 0);
15586 advance_state (curr_state
);
15589 /* Initialize STATE before its first use. DFA_STATE points to an
15590 allocated but uninitialized DFA state. */
15593 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
15595 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
15596 targetm
.sched
.init_dfa_pre_cycle_insn ();
15598 if (targetm
.sched
.init_dfa_post_cycle_insn
)
15599 targetm
.sched
.init_dfa_post_cycle_insn ();
15601 state
->issue_rate
= mips_issue_rate ();
15602 state
->dfa_state
= dfa_state
;
15603 mips_sim_reset (state
);
15606 /* Advance STATE by one clock cycle. */
15609 mips_sim_next_cycle (struct mips_sim
*state
)
15611 curr_state
= state
->dfa_state
;
15614 state
->insns_left
= state
->issue_rate
;
15615 advance_state (curr_state
);
15618 /* Advance simulation state STATE until instruction INSN can read
15622 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
15624 unsigned int regno
, end_regno
;
15626 end_regno
= END_REGNO (reg
);
15627 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
15628 if (state
->last_set
[regno
].insn
!= 0)
15632 t
= (state
->last_set
[regno
].time
15633 + insn_latency (state
->last_set
[regno
].insn
, insn
));
15634 while (state
->time
< t
)
15635 mips_sim_next_cycle (state
);
15639 /* A for_each_rtx callback. If *X is a register, advance simulation state
15640 DATA until mips_sim_insn can read the register's value. */
15643 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
15646 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
15650 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15653 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
15655 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
15658 /* Advance simulation state STATE until all of INSN's register
15659 dependencies are satisfied. */
15662 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
15664 mips_sim_insn
= insn
;
15665 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
15668 /* Advance simulation state STATE until the units required by
15669 instruction INSN are available. */
15672 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
15676 tmp_state
= alloca (state_size ());
15677 while (state
->insns_left
== 0
15678 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
15679 state_transition (tmp_state
, insn
) >= 0))
15680 mips_sim_next_cycle (state
);
15683 /* Advance simulation state STATE until INSN is ready to issue. */
15686 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
15688 mips_sim_wait_regs (state
, insn
);
15689 mips_sim_wait_units (state
, insn
);
15692 /* mips_sim_insn has just set X. Update the LAST_SET array
15693 in simulation state DATA. */
15696 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
15698 struct mips_sim
*state
;
15700 state
= (struct mips_sim
*) data
;
15703 unsigned int regno
, end_regno
;
15705 end_regno
= END_REGNO (x
);
15706 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
15708 state
->last_set
[regno
].insn
= mips_sim_insn
;
15709 state
->last_set
[regno
].time
= state
->time
;
15714 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15715 can issue immediately (i.e., that mips_sim_wait_insn has already
15719 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
15721 curr_state
= state
->dfa_state
;
15723 state_transition (curr_state
, insn
);
15724 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
15725 state
->insns_left
);
15727 mips_sim_insn
= insn
;
15728 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
15731 /* Simulate issuing a NOP in state STATE. */
15734 mips_sim_issue_nop (struct mips_sim
*state
)
15736 if (state
->insns_left
== 0)
15737 mips_sim_next_cycle (state
);
15738 state
->insns_left
--;
15741 /* Update simulation state STATE so that it's ready to accept the instruction
15742 after INSN. INSN should be part of the main rtl chain, not a member of a
15746 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
15748 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15750 mips_sim_issue_nop (state
);
15752 switch (GET_CODE (SEQ_BEGIN (insn
)))
15756 /* We can't predict the processor state after a call or label. */
15757 mips_sim_reset (state
);
15761 /* The delay slots of branch likely instructions are only executed
15762 when the branch is taken. Therefore, if the caller has simulated
15763 the delay slot instruction, STATE does not really reflect the state
15764 of the pipeline for the instruction after the delay slot. Also,
15765 branch likely instructions tend to incur a penalty when not taken,
15766 so there will probably be an extra delay between the branch and
15767 the instruction after the delay slot. */
15768 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
15769 mips_sim_reset (state
);
15777 /* Use simulator state STATE to calculate the execution time of
15778 instruction sequence SEQ. */
15780 static unsigned int
15781 mips_seq_time (struct mips_sim
*state
, rtx seq
)
15783 mips_sim_reset (state
);
15784 for (rtx insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
15786 mips_sim_wait_insn (state
, insn
);
15787 mips_sim_issue_insn (state
, insn
);
15789 return state
->time
;
15792 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15793 setting SETTING, using STATE to simulate instruction sequences. */
15795 static unsigned int
15796 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
15798 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
15801 enum machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
15802 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
15803 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
15805 /* If the target provides mulsidi3_32bit then that's the most likely
15806 consumer of the result. Test for bypasses. */
15807 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
15809 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
15810 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
15813 unsigned int time
= mips_seq_time (state
, get_insns ());
15818 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15819 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15820 Prefer MULT -- which is shorter -- in the event of a tie. */
15823 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
15826 /* No MTLO or MTHI available. */
15827 mips_tuning_info
.fast_mult_zero_zero_p
= true;
15830 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
15831 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
15832 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
15836 /* Set up costs based on the current architecture and tuning settings. */
15839 mips_set_tuning_info (void)
15841 if (mips_tuning_info
.initialized_p
15842 && mips_tuning_info
.arch
== mips_arch
15843 && mips_tuning_info
.tune
== mips_tune
15844 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
15847 mips_tuning_info
.arch
= mips_arch
;
15848 mips_tuning_info
.tune
= mips_tune
;
15849 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
15850 mips_tuning_info
.initialized_p
= true;
15854 struct mips_sim state
;
15855 mips_sim_init (&state
, alloca (state_size ()));
15857 mips_set_fast_mult_zero_zero_p (&state
);
15862 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15865 mips_expand_to_rtl_hook (void)
15867 /* We need to call this at a point where we can safely create sequences
15868 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15869 need to call it at a point where the DFA infrastructure is not
15870 already in use, so we can't just call it lazily on demand.
15872 At present, mips_tuning_info is only needed during post-expand
15873 RTL passes such as split_insns, so this hook should be early enough.
15874 We may need to move the call elsewhere if mips_tuning_info starts
15875 to be used for other things (such as rtx_costs, or expanders that
15876 could be called during gimple optimization). */
15877 mips_set_tuning_info ();
15880 /* The VR4130 pipeline issues aligned pairs of instructions together,
15881 but it stalls the second instruction if it depends on the first.
15882 In order to cut down the amount of logic required, this dependence
15883 check is not based on a full instruction decode. Instead, any non-SPECIAL
15884 instruction is assumed to modify the register specified by bits 20-16
15885 (which is usually the "rt" field).
15887 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15888 input, so we can end up with a false dependence between the branch
15889 and its delay slot. If this situation occurs in instruction INSN,
15890 try to avoid it by swapping rs and rt. */
15893 vr4130_avoid_branch_rt_conflict (rtx insn
)
15897 first
= SEQ_BEGIN (insn
);
15898 second
= SEQ_END (insn
);
15900 && NONJUMP_INSN_P (second
)
15901 && GET_CODE (PATTERN (first
)) == SET
15902 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
15903 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
15905 /* Check for the right kind of condition. */
15906 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
15907 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
15908 && REG_P (XEXP (cond
, 0))
15909 && REG_P (XEXP (cond
, 1))
15910 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
15911 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
15913 /* SECOND mentions the rt register but not the rs register. */
15914 rtx tmp
= XEXP (cond
, 0);
15915 XEXP (cond
, 0) = XEXP (cond
, 1);
15916 XEXP (cond
, 1) = tmp
;
15921 /* Implement -mvr4130-align. Go through each basic block and simulate the
15922 processor pipeline. If we find that a pair of instructions could execute
15923 in parallel, and the first of those instructions is not 8-byte aligned,
15924 insert a nop to make it aligned. */
15927 vr4130_align_insns (void)
15929 struct mips_sim state
;
15930 rtx insn
, subinsn
, last
, last2
, next
;
15935 /* LAST is the last instruction before INSN to have a nonzero length.
15936 LAST2 is the last such instruction before LAST. */
15940 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15943 mips_sim_init (&state
, alloca (state_size ()));
15944 for (insn
= get_insns (); insn
!= 0; insn
= next
)
15946 unsigned int length
;
15948 next
= NEXT_INSN (insn
);
15950 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15951 This isn't really related to the alignment pass, but we do it on
15952 the fly to avoid a separate instruction walk. */
15953 vr4130_avoid_branch_rt_conflict (insn
);
15955 length
= get_attr_length (insn
);
15956 if (length
> 0 && USEFUL_INSN_P (insn
))
15957 FOR_EACH_SUBINSN (subinsn
, insn
)
15959 mips_sim_wait_insn (&state
, subinsn
);
15961 /* If we want this instruction to issue in parallel with the
15962 previous one, make sure that the previous instruction is
15963 aligned. There are several reasons why this isn't worthwhile
15964 when the second instruction is a call:
15966 - Calls are less likely to be performance critical,
15967 - There's a good chance that the delay slot can execute
15968 in parallel with the call.
15969 - The return address would then be unaligned.
15971 In general, if we're going to insert a nop between instructions
15972 X and Y, it's better to insert it immediately after X. That
15973 way, if the nop makes Y aligned, it will also align any labels
15974 between X and Y. */
15975 if (state
.insns_left
!= state
.issue_rate
15976 && !CALL_P (subinsn
))
15978 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
15980 /* SUBINSN is the first instruction in INSN and INSN is
15981 aligned. We want to align the previous instruction
15982 instead, so insert a nop between LAST2 and LAST.
15984 Note that LAST could be either a single instruction
15985 or a branch with a delay slot. In the latter case,
15986 LAST, like INSN, is already aligned, but the delay
15987 slot must have some extra delay that stops it from
15988 issuing at the same time as the branch. We therefore
15989 insert a nop before the branch in order to align its
15991 gcc_assert (last2
);
15992 emit_insn_after (gen_nop (), last2
);
15995 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
15997 /* SUBINSN is the delay slot of INSN, but INSN is
15998 currently unaligned. Insert a nop between
15999 LAST and INSN to align it. */
16001 emit_insn_after (gen_nop (), last
);
16005 mips_sim_issue_insn (&state
, subinsn
);
16007 mips_sim_finish_insn (&state
, insn
);
16009 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
16010 length
= get_attr_length (insn
);
16013 /* If the instruction is an asm statement or multi-instruction
16014 mips.md patern, the length is only an estimate. Insert an
16015 8 byte alignment after it so that the following instructions
16016 can be handled correctly. */
16017 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
16018 && (recog_memoized (insn
) < 0 || length
>= 8))
16020 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
16021 next
= NEXT_INSN (next
);
16022 mips_sim_next_cycle (&state
);
16025 else if (length
& 4)
16026 aligned_p
= !aligned_p
;
16031 /* See whether INSN is an aligned label. */
16032 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
16038 /* This structure records that the current function has a LO_SUM
16039 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
16040 the largest offset applied to BASE by all such LO_SUMs. */
16041 struct mips_lo_sum_offset
{
16043 HOST_WIDE_INT offset
;
16046 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
16049 mips_hash_base (rtx base
)
16051 int do_not_record_p
;
16053 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
16056 /* Hashtable helpers. */
16058 struct mips_lo_sum_offset_hasher
: typed_free_remove
<mips_lo_sum_offset
>
16060 typedef mips_lo_sum_offset value_type
;
16061 typedef rtx_def compare_type
;
16062 static inline hashval_t
hash (const value_type
*);
16063 static inline bool equal (const value_type
*, const compare_type
*);
16066 /* Hash-table callbacks for mips_lo_sum_offsets. */
16069 mips_lo_sum_offset_hasher::hash (const value_type
*entry
)
16071 return mips_hash_base (entry
->base
);
16075 mips_lo_sum_offset_hasher::equal (const value_type
*entry
,
16076 const compare_type
*value
)
16078 return rtx_equal_p (entry
->base
, value
);
16081 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
16083 /* Look up symbolic constant X in HTAB, which is a hash table of
16084 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
16085 paired with a recorded LO_SUM, otherwise record X in the table. */
16088 mips_lo_sum_offset_lookup (mips_offset_table htab
, rtx x
,
16089 enum insert_option option
)
16092 mips_lo_sum_offset
**slot
;
16093 struct mips_lo_sum_offset
*entry
;
16095 /* Split X into a base and offset. */
16096 split_const (x
, &base
, &offset
);
16097 if (UNSPEC_ADDRESS_P (base
))
16098 base
= UNSPEC_ADDRESS (base
);
16100 /* Look up the base in the hash table. */
16101 slot
= htab
.find_slot_with_hash (base
, mips_hash_base (base
), option
);
16105 entry
= (struct mips_lo_sum_offset
*) *slot
;
16106 if (option
== INSERT
)
16110 entry
= XNEW (struct mips_lo_sum_offset
);
16111 entry
->base
= base
;
16112 entry
->offset
= INTVAL (offset
);
16117 if (INTVAL (offset
) > entry
->offset
)
16118 entry
->offset
= INTVAL (offset
);
16121 return INTVAL (offset
) <= entry
->offset
;
16124 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
16125 Record every LO_SUM in *LOC. */
16128 mips_record_lo_sum (rtx
*loc
, void *data
)
16130 if (GET_CODE (*loc
) == LO_SUM
)
16131 mips_lo_sum_offset_lookup (*(mips_offset_table
*) data
,
16132 XEXP (*loc
, 1), INSERT
);
16136 /* Return true if INSN is a SET of an orphaned high-part relocation.
16137 HTAB is a hash table of mips_lo_sum_offsets that describes all the
16138 LO_SUMs in the current function. */
16141 mips_orphaned_high_part_p (mips_offset_table htab
, rtx insn
)
16143 enum mips_symbol_type type
;
16146 set
= single_set (insn
);
16149 /* Check for %his. */
16151 if (GET_CODE (x
) == HIGH
16152 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
16153 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
16155 /* Check for local %gots (and %got_pages, which is redundant but OK). */
16156 if (GET_CODE (x
) == UNSPEC
16157 && XINT (x
, 1) == UNSPEC_LOAD_GOT
16158 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
16159 SYMBOL_CONTEXT_LEA
, &type
)
16160 && type
== SYMBOL_GOTOFF_PAGE
)
16161 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
16166 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
16167 INSN and a previous instruction, avoid it by inserting nops after
16170 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
16171 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
16172 before using the value of that register. *HILO_DELAY counts the
16173 number of instructions since the last hilo hazard (that is,
16174 the number of instructions since the last MFLO or MFHI).
16176 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
16177 for the next instruction.
16179 LO_REG is an rtx for the LO register, used in dependence checking. */
16182 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
16183 rtx
*delayed_reg
, rtx lo_reg
)
16188 pattern
= PATTERN (insn
);
16190 /* Do not put the whole function in .set noreorder if it contains
16191 an asm statement. We don't know whether there will be hazards
16192 between the asm statement and the gcc-generated code. */
16193 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
16194 cfun
->machine
->all_noreorder_p
= false;
16196 /* Ignore zero-length instructions (barriers and the like). */
16197 ninsns
= get_attr_length (insn
) / 4;
16201 /* Work out how many nops are needed. Note that we only care about
16202 registers that are explicitly mentioned in the instruction's pattern.
16203 It doesn't matter that calls use the argument registers or that they
16204 clobber hi and lo. */
16205 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
16206 nops
= 2 - *hilo_delay
;
16207 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
16212 /* Insert the nops between this instruction and the previous one.
16213 Each new nop takes us further from the last hilo hazard. */
16214 *hilo_delay
+= nops
;
16216 emit_insn_after (gen_hazard_nop (), after
);
16218 /* Set up the state for the next instruction. */
16219 *hilo_delay
+= ninsns
;
16221 if (INSN_CODE (insn
) >= 0)
16222 switch (get_attr_hazard (insn
))
16232 set
= single_set (insn
);
16234 *delayed_reg
= SET_DEST (set
);
16239 /* Go through the instruction stream and insert nops where necessary.
16240 Also delete any high-part relocations whose partnering low parts
16241 are now all dead. See if the whole function can then be put into
16242 .set noreorder and .set nomacro. */
16245 mips_reorg_process_insns (void)
16247 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
16249 mips_offset_table htab
;
16251 /* Force all instructions to be split into their final form. */
16252 split_all_insns_noflow ();
16254 /* Recalculate instruction lengths without taking nops into account. */
16255 cfun
->machine
->ignore_hazard_length_p
= true;
16256 shorten_branches (get_insns ());
16258 cfun
->machine
->all_noreorder_p
= true;
16260 /* We don't track MIPS16 PC-relative offsets closely enough to make
16261 a good job of "set .noreorder" code in MIPS16 mode. */
16263 cfun
->machine
->all_noreorder_p
= false;
16265 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16266 if (!TARGET_EXPLICIT_RELOCS
)
16267 cfun
->machine
->all_noreorder_p
= false;
16269 /* Profiled functions can't be all noreorder because the profiler
16270 support uses assembler macros. */
16272 cfun
->machine
->all_noreorder_p
= false;
16274 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16275 all noreorder because we rely on the assembler to work around some
16276 errata. The R5900 too has several bugs. */
16277 if (TARGET_FIX_VR4120
16278 || TARGET_FIX_RM7000
16280 || TARGET_MIPS5900
)
16281 cfun
->machine
->all_noreorder_p
= false;
16283 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16284 MFHI instructions. Note that we avoid using MFLO and MFHI if
16285 the VR4130 MACC and DMACC instructions are available instead;
16286 see the *mfhilo_{si,di}_macc patterns. */
16287 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
16288 cfun
->machine
->all_noreorder_p
= false;
16292 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16293 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16294 FOR_EACH_SUBINSN (subinsn
, insn
)
16295 if (USEFUL_INSN_P (subinsn
))
16297 rtx body
= PATTERN (insn
);
16298 int noperands
= asm_noperands (body
);
16299 if (noperands
>= 0)
16301 rtx
*ops
= XALLOCAVEC (rtx
, noperands
);
16302 bool *used
= XALLOCAVEC (bool, noperands
);
16303 const char *string
= decode_asm_operands (body
, ops
, NULL
, NULL
,
16305 get_referenced_operands (string
, used
, noperands
);
16306 for (int i
= 0; i
< noperands
; ++i
)
16308 for_each_rtx (&ops
[i
], mips_record_lo_sum
, &htab
);
16311 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, &htab
);
16317 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
16319 /* Make a second pass over the instructions. Delete orphaned
16320 high-part relocations or turn them into NOPs. Avoid hazards
16321 by inserting NOPs. */
16322 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
16324 next_insn
= NEXT_INSN (insn
);
16325 if (USEFUL_INSN_P (insn
))
16327 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
16329 /* If we find an orphaned high-part relocation in a delay
16330 slot, it's easier to turn that instruction into a NOP than
16331 to delete it. The delay slot will be a NOP either way. */
16332 FOR_EACH_SUBINSN (subinsn
, insn
)
16333 if (INSN_P (subinsn
))
16335 if (mips_orphaned_high_part_p (htab
, subinsn
))
16337 PATTERN (subinsn
) = gen_nop ();
16338 INSN_CODE (subinsn
) = CODE_FOR_nop
;
16340 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
16341 &delayed_reg
, lo_reg
);
16347 /* INSN is a single instruction. Delete it if it's an
16348 orphaned high-part relocation. */
16349 if (mips_orphaned_high_part_p (htab
, insn
))
16350 delete_insn (insn
);
16351 /* Also delete cache barriers if the last instruction
16352 was an annulled branch. INSN will not be speculatively
16354 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
16356 && JUMP_P (SEQ_BEGIN (last_insn
))
16357 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
16358 delete_insn (insn
);
16361 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
16362 &delayed_reg
, lo_reg
);
16372 /* Return true if the function has a long branch instruction. */
16375 mips_has_long_branch_p (void)
16380 /* We need up-to-date instruction lengths. */
16381 shorten_branches (get_insns ());
16383 /* Look for a branch that is longer than normal. The normal length for
16384 non-MIPS16 branches is 8, because the length includes the delay slot.
16385 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16386 but they have no delay slot. */
16387 normal_length
= (TARGET_MIPS16
? 4 : 8);
16388 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16389 FOR_EACH_SUBINSN (subinsn
, insn
)
16390 if (JUMP_P (subinsn
)
16391 && get_attr_length (subinsn
) > normal_length
16392 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
16398 /* If we are using a GOT, but have not decided to use a global pointer yet,
16399 see whether we need one to implement long branches. Convert the ghost
16400 global-pointer instructions into real ones if so. */
16403 mips_expand_ghost_gp_insns (void)
16405 /* Quick exit if we already know that we will or won't need a
16407 if (!TARGET_USE_GOT
16408 || cfun
->machine
->global_pointer
== INVALID_REGNUM
16409 || mips_must_initialize_gp_p ())
16412 /* Run a full check for long branches. */
16413 if (!mips_has_long_branch_p ())
16416 /* We've now established that we need $gp. */
16417 cfun
->machine
->must_initialize_gp_p
= true;
16418 split_all_insns_noflow ();
16423 /* Subroutine of mips_reorg to manage passes that require DF. */
16426 mips_df_reorg (void)
16428 /* Create def-use chains. */
16429 df_set_flags (DF_EQ_NOTES
);
16430 df_chain_add_problem (DF_UD_CHAIN
);
16433 if (TARGET_RELAX_PIC_CALLS
)
16434 mips_annotate_pic_calls ();
16436 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
16437 r10k_insert_cache_barriers ();
16439 df_finish_pass (false);
16442 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16443 called very late in mips_reorg, but the caller is required to run
16444 mips16_lay_out_constants on the result. */
16447 mips16_load_branch_target (rtx dest
, rtx src
)
16449 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
16453 if (mips_cfun_has_cprestore_slot_p ())
16454 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
16456 mips_emit_move (dest
, pic_offset_table_rtx
);
16457 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
16458 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
16459 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16460 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
16461 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16462 gen_rtx_LO_SUM (Pmode
, dest
, low
)));
16466 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
16467 mips_emit_move (dest
, src
);
16471 /* If we're compiling a MIPS16 function, look for and split any long branches.
16472 This must be called after all other instruction modifications in
16476 mips16_split_long_branches (void)
16478 bool something_changed
;
16480 if (!TARGET_MIPS16
)
16483 /* Loop until the alignments for all targets are sufficient. */
16488 shorten_branches (get_insns ());
16489 something_changed
= false;
16490 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16492 && get_attr_length (insn
) > 4
16493 && (any_condjump_p (insn
) || any_uncondjump_p (insn
)))
16495 rtx old_label
, new_label
, temp
, saved_temp
;
16496 rtx target
, jump
, jump_sequence
;
16500 /* Free up a MIPS16 register by saving it in $1. */
16501 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
16502 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
16503 emit_move_insn (saved_temp
, temp
);
16505 /* Load the branch target into TEMP. */
16506 old_label
= JUMP_LABEL (insn
);
16507 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
16508 mips16_load_branch_target (temp
, target
);
16510 /* Jump to the target and restore the register's
16512 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
16513 (temp
, temp
, saved_temp
)));
16514 JUMP_LABEL (jump
) = old_label
;
16515 LABEL_NUSES (old_label
)++;
16517 /* Rewrite any symbolic references that are supposed to use
16518 a PC-relative constant pool. */
16519 mips16_lay_out_constants (false);
16521 if (simplejump_p (insn
))
16522 /* We're going to replace INSN with a longer form. */
16523 new_label
= NULL_RTX
;
16526 /* Create a branch-around label for the original
16528 new_label
= gen_label_rtx ();
16529 emit_label (new_label
);
16532 jump_sequence
= get_insns ();
16535 emit_insn_after (jump_sequence
, insn
);
16537 invert_jump (insn
, new_label
, false);
16539 delete_insn (insn
);
16540 something_changed
= true;
16543 while (something_changed
);
16546 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16551 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16552 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16553 to date if the CFG is available. */
16554 if (mips_cfg_in_reorg ())
16555 compute_bb_for_insn ();
16556 mips16_lay_out_constants (true);
16557 if (mips_cfg_in_reorg ())
16560 free_bb_for_insn ();
16564 /* We use a machine specific pass to do a second machine dependent reorg
16565 pass after delay branch scheduling. */
16567 static unsigned int
16568 mips_machine_reorg2 (void)
16570 mips_reorg_process_insns ();
16572 && TARGET_EXPLICIT_RELOCS
16574 && TARGET_VR4130_ALIGN
)
16575 vr4130_align_insns ();
16576 if (mips_expand_ghost_gp_insns ())
16577 /* The expansion could invalidate some of the VR4130 alignment
16578 optimizations, but this should be an extremely rare case anyhow. */
16579 mips_reorg_process_insns ();
16580 mips16_split_long_branches ();
16586 const pass_data pass_data_mips_machine_reorg2
=
16588 RTL_PASS
, /* type */
16589 "mach2", /* name */
16590 OPTGROUP_NONE
, /* optinfo_flags */
16591 true, /* has_execute */
16592 TV_MACH_DEP
, /* tv_id */
16593 0, /* properties_required */
16594 0, /* properties_provided */
16595 0, /* properties_destroyed */
16596 0, /* todo_flags_start */
16597 0, /* todo_flags_finish */
16600 class pass_mips_machine_reorg2
: public rtl_opt_pass
16603 pass_mips_machine_reorg2(gcc::context
*ctxt
)
16604 : rtl_opt_pass(pass_data_mips_machine_reorg2
, ctxt
)
16607 /* opt_pass methods: */
16608 virtual unsigned int execute (function
*) { return mips_machine_reorg2 (); }
16610 }; // class pass_mips_machine_reorg2
16612 } // anon namespace
16615 make_pass_mips_machine_reorg2 (gcc::context
*ctxt
)
16617 return new pass_mips_machine_reorg2 (ctxt
);
16621 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16622 in order to avoid duplicating too much logic from elsewhere. */
16625 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
16626 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
16629 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
16630 bool use_sibcall_p
;
16632 /* Pretend to be a post-reload pass while generating rtl. */
16633 reload_completed
= 1;
16635 /* Mark the end of the (empty) prologue. */
16636 emit_note (NOTE_INSN_PROLOGUE_END
);
16638 /* Determine if we can use a sibcall to call FUNCTION directly. */
16639 fnaddr
= XEXP (DECL_RTL (function
), 0);
16640 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
16641 && const_call_insn_operand (fnaddr
, Pmode
));
16643 /* Determine if we need to load FNADDR from the GOT. */
16645 && (mips_got_symbol_type_p
16646 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
16648 /* Pick a global pointer. Use a call-clobbered register if
16649 TARGET_CALL_SAVED_GP. */
16650 cfun
->machine
->global_pointer
16651 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
16652 cfun
->machine
->must_initialize_gp_p
= true;
16653 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
16655 /* Set up the global pointer for n32 or n64 abicalls. */
16656 mips_emit_loadgp ();
16659 /* We need two temporary registers in some cases. */
16660 temp1
= gen_rtx_REG (Pmode
, 2);
16661 temp2
= gen_rtx_REG (Pmode
, 3);
16663 /* Find out which register contains the "this" pointer. */
16664 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
16665 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
16667 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
16669 /* Add DELTA to THIS_RTX. */
16672 rtx offset
= GEN_INT (delta
);
16673 if (!SMALL_OPERAND (delta
))
16675 mips_emit_move (temp1
, offset
);
16678 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
16681 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16682 if (vcall_offset
!= 0)
16686 /* Set TEMP1 to *THIS_RTX. */
16687 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
16689 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16690 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
16692 /* Load the offset and add it to THIS_RTX. */
16693 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
16694 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
16697 /* Jump to the target function. Use a sibcall if direct jumps are
16698 allowed, otherwise load the address into a register first. */
16701 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
16702 SIBLING_CALL_P (insn
) = 1;
16706 /* This is messy. GAS treats "la $25,foo" as part of a call
16707 sequence and may allow a global "foo" to be lazily bound.
16708 The general move patterns therefore reject this combination.
16710 In this context, lazy binding would actually be OK
16711 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16712 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16713 We must therefore load the address via a temporary
16714 register if mips_dangerous_for_la25_p.
16716 If we jump to the temporary register rather than $25,
16717 the assembler can use the move insn to fill the jump's
16720 We can use the same technique for MIPS16 code, where $25
16721 is not a valid JR register. */
16722 if (TARGET_USE_PIC_FN_ADDR_REG
16724 && !mips_dangerous_for_la25_p (fnaddr
))
16725 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
16726 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
16728 if (TARGET_USE_PIC_FN_ADDR_REG
16729 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
16730 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
16731 emit_jump_insn (gen_indirect_jump (temp1
));
16734 /* Run just enough of rest_of_compilation. This sequence was
16735 "borrowed" from alpha.c. */
16736 insn
= get_insns ();
16737 split_all_insns_noflow ();
16738 mips16_lay_out_constants (true);
16739 shorten_branches (insn
);
16740 final_start_function (insn
, file
, 1);
16741 final (insn
, file
, 1);
16742 final_end_function ();
16744 /* Clean up the vars set above. Note that final_end_function resets
16745 the global pointer for us. */
16746 reload_completed
= 0;
16750 /* The last argument passed to mips_set_compression_mode,
16751 or negative if the function hasn't been called yet. */
16752 static unsigned int old_compression_mode
= -1;
16754 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16755 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16758 mips_set_compression_mode (unsigned int compression_mode
)
16761 if (compression_mode
== old_compression_mode
)
16764 /* Restore base settings of various flags. */
16765 target_flags
= mips_base_target_flags
;
16766 flag_schedule_insns
= mips_base_schedule_insns
;
16767 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
16768 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
16769 align_loops
= mips_base_align_loops
;
16770 align_jumps
= mips_base_align_jumps
;
16771 align_functions
= mips_base_align_functions
;
16772 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
16773 target_flags
|= compression_mode
;
16775 if (compression_mode
& MASK_MIPS16
)
16777 /* Switch to MIPS16 mode. */
16778 target_flags
|= MASK_MIPS16
;
16780 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16781 target_flags
&= ~MASK_SYNCI
;
16783 /* Don't run the scheduler before reload, since it tends to
16784 increase register pressure. */
16785 flag_schedule_insns
= 0;
16787 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16788 the whole function to be in a single section. */
16789 flag_reorder_blocks_and_partition
= 0;
16791 /* Don't move loop invariants, because it tends to increase
16792 register pressure. It also introduces an extra move in cases
16793 where the constant is the first operand in a two-operand binary
16794 instruction, or when it forms a register argument to a functon
16796 flag_move_loop_invariants
= 0;
16798 target_flags
|= MASK_EXPLICIT_RELOCS
;
16800 /* Experiments suggest we get the best overall section-anchor
16801 results from using the range of an unextended LW or SW. Code
16802 that makes heavy use of byte or short accesses can do better
16803 with ranges of 0...31 and 0...63 respectively, but most code is
16804 sensitive to the range of LW and SW instead. */
16805 targetm
.min_anchor_offset
= 0;
16806 targetm
.max_anchor_offset
= 127;
16808 targetm
.const_anchor
= 0;
16810 /* MIPS16 has no BAL instruction. */
16811 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
16813 /* The R4000 errata don't apply to any known MIPS16 cores.
16814 It's simpler to make the R4000 fixes and MIPS16 mode
16815 mutually exclusive. */
16816 target_flags
&= ~MASK_FIX_R4000
;
16818 if (flag_pic
&& !TARGET_OLDABI
)
16819 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16822 sorry ("MIPS16 -mxgot code");
16824 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
16825 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16829 /* Switch to microMIPS or the standard encoding. */
16831 if (TARGET_MICROMIPS
)
16832 /* Avoid branch likely. */
16833 target_flags
&= ~MASK_BRANCHLIKELY
;
16835 /* Provide default values for align_* for 64-bit targets. */
16838 if (align_loops
== 0)
16840 if (align_jumps
== 0)
16842 if (align_functions
== 0)
16843 align_functions
= 8;
16846 targetm
.min_anchor_offset
= -32768;
16847 targetm
.max_anchor_offset
= 32767;
16849 targetm
.const_anchor
= 0x8000;
16852 /* (Re)initialize MIPS target internals for new ISA. */
16853 mips_init_relocs ();
16855 if (compression_mode
& MASK_MIPS16
)
16857 if (!mips16_globals
)
16858 mips16_globals
= save_target_globals_default_opts ();
16860 restore_target_globals (mips16_globals
);
16863 restore_target_globals (&default_target_globals
);
16865 old_compression_mode
= compression_mode
;
16868 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16869 function should use the MIPS16 or microMIPS ISA and switch modes
16873 mips_set_current_function (tree fndecl
)
16875 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
16878 /* Allocate a chunk of memory for per-function machine-dependent data. */
16880 static struct machine_function
*
16881 mips_init_machine_status (void)
16883 return ggc_cleared_alloc
<machine_function
> ();
16886 /* Return the processor associated with the given ISA level, or null
16887 if the ISA isn't valid. */
16889 static const struct mips_cpu_info
*
16890 mips_cpu_info_from_isa (int isa
)
16894 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16895 if (mips_cpu_info_table
[i
].isa
== isa
)
16896 return mips_cpu_info_table
+ i
;
16901 /* Return a mips_cpu_info entry determined by an option valued
16904 static const struct mips_cpu_info
*
16905 mips_cpu_info_from_opt (int opt
)
16909 case MIPS_ARCH_OPTION_FROM_ABI
:
16910 /* 'from-abi' selects the most compatible architecture for the
16911 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16912 ABIs. For the EABIs, we have to decide whether we're using
16913 the 32-bit or 64-bit version. */
16914 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
16915 : ABI_NEEDS_64BIT_REGS
? 3
16916 : (TARGET_64BIT
? 3 : 1));
16918 case MIPS_ARCH_OPTION_NATIVE
:
16919 gcc_unreachable ();
16922 return &mips_cpu_info_table
[opt
];
16926 /* Return a default mips_cpu_info entry, given that no -march= option
16927 was explicitly specified. */
16929 static const struct mips_cpu_info
*
16930 mips_default_arch (void)
16932 #if defined (MIPS_CPU_STRING_DEFAULT)
16934 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16935 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
16936 return mips_cpu_info_table
+ i
;
16937 gcc_unreachable ();
16938 #elif defined (MIPS_ISA_DEFAULT)
16939 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
16941 /* 'from-abi' makes a good default: you get whatever the ABI
16943 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
16947 /* Set up globals to generate code for the ISA or processor
16948 described by INFO. */
16951 mips_set_architecture (const struct mips_cpu_info
*info
)
16955 mips_arch_info
= info
;
16956 mips_arch
= info
->cpu
;
16957 mips_isa
= info
->isa
;
16961 mips_isa_rev
= (mips_isa
& 31) + 1;
16965 /* Likewise for tuning. */
16968 mips_set_tune (const struct mips_cpu_info
*info
)
16972 mips_tune_info
= info
;
16973 mips_tune
= info
->cpu
;
16977 /* Implement TARGET_OPTION_OVERRIDE. */
16980 mips_option_override (void)
16982 int i
, start
, regno
, mode
;
16984 if (global_options_set
.x_mips_isa_option
)
16985 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
16987 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16988 SUBTARGET_OVERRIDE_OPTIONS
;
16991 /* MIPS16 and microMIPS cannot coexist. */
16992 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
16993 error ("unsupported combination: %s", "-mips16 -mmicromips");
16995 /* Save the base compression state and process flags as though we
16996 were generating uncompressed code. */
16997 mips_base_compression_flags
= TARGET_COMPRESSION
;
16998 target_flags
&= ~TARGET_COMPRESSION
;
17000 /* -mno-float overrides -mhard-float and -msoft-float. */
17001 if (TARGET_NO_FLOAT
)
17003 target_flags
|= MASK_SOFT_FLOAT_ABI
;
17004 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
17007 if (TARGET_FLIP_MIPS16
)
17008 TARGET_INTERLINK_COMPRESSED
= 1;
17010 /* Set the small data limit. */
17011 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
17013 : MIPS_DEFAULT_GVALUE
);
17015 /* The following code determines the architecture and register size.
17016 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
17017 The GAS and GCC code should be kept in sync as much as possible. */
17019 if (global_options_set
.x_mips_arch_option
)
17020 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
17022 if (mips_isa_option_info
!= 0)
17024 if (mips_arch_info
== 0)
17025 mips_set_architecture (mips_isa_option_info
);
17026 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
17027 error ("%<-%s%> conflicts with the other architecture options, "
17028 "which specify a %s processor",
17029 mips_isa_option_info
->name
,
17030 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
17033 if (mips_arch_info
== 0)
17034 mips_set_architecture (mips_default_arch ());
17036 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
17037 error ("%<-march=%s%> is not compatible with the selected ABI",
17038 mips_arch_info
->name
);
17040 /* Optimize for mips_arch, unless -mtune selects a different processor. */
17041 if (global_options_set
.x_mips_tune_option
)
17042 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
17044 if (mips_tune_info
== 0)
17045 mips_set_tune (mips_arch_info
);
17047 if ((target_flags_explicit
& MASK_64BIT
) != 0)
17049 /* The user specified the size of the integer registers. Make sure
17050 it agrees with the ABI and ISA. */
17051 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
17052 error ("%<-mgp64%> used with a 32-bit processor");
17053 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
17054 error ("%<-mgp32%> used with a 64-bit ABI");
17055 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
17056 error ("%<-mgp64%> used with a 32-bit ABI");
17060 /* Infer the integer register size from the ABI and processor.
17061 Restrict ourselves to 32-bit registers if that's all the
17062 processor has, or if the ABI cannot handle 64-bit registers. */
17063 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
17064 target_flags
&= ~MASK_64BIT
;
17066 target_flags
|= MASK_64BIT
;
17069 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
17071 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
17072 error ("unsupported combination: %s", "-mfp64 -msingle-float");
17073 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
17074 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
17075 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
17077 if (!ISA_HAS_MXHC1
)
17078 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
17079 " the target supports the mfhc1 and mthc1 instructions");
17080 else if (mips_abi
!= ABI_32
)
17081 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
17087 /* -msingle-float selects 32-bit float registers. Otherwise the
17088 float registers should be the same size as the integer ones. */
17089 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
17090 target_flags
|= MASK_FLOAT64
;
17092 target_flags
&= ~MASK_FLOAT64
;
17095 /* End of code shared with GAS. */
17097 /* The R5900 FPU only supports single precision. */
17098 if (TARGET_MIPS5900
&& TARGET_HARD_FLOAT_ABI
&& TARGET_DOUBLE_FLOAT
)
17099 error ("unsupported combination: %s",
17100 "-march=r5900 -mhard-float -mdouble-float");
17102 /* If a -mlong* option was given, check that it matches the ABI,
17103 otherwise infer the -mlong* setting from the other options. */
17104 if ((target_flags_explicit
& MASK_LONG64
) != 0)
17108 if (mips_abi
== ABI_N32
)
17109 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
17110 else if (mips_abi
== ABI_32
)
17111 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
17112 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
17113 /* We have traditionally allowed non-abicalls code to use
17114 an LP64 form of o64. However, it would take a bit more
17115 effort to support the combination of 32-bit GOT entries
17116 and 64-bit pointers, so we treat the abicalls case as
17118 error ("the combination of %qs and %qs is incompatible with %qs",
17119 "-mabi=o64", "-mabicalls", "-mlong64");
17123 if (mips_abi
== ABI_64
)
17124 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
17129 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
17130 target_flags
|= MASK_LONG64
;
17132 target_flags
&= ~MASK_LONG64
;
17135 if (!TARGET_OLDABI
)
17136 flag_pcc_struct_return
= 0;
17138 /* Decide which rtx_costs structure to use. */
17140 mips_cost
= &mips_rtx_cost_optimize_size
;
17142 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
17144 /* If the user hasn't specified a branch cost, use the processor's
17146 if (mips_branch_cost
== 0)
17147 mips_branch_cost
= mips_cost
->branch_cost
;
17149 /* If neither -mbranch-likely nor -mno-branch-likely was given
17150 on the command line, set MASK_BRANCHLIKELY based on the target
17151 architecture and tuning flags. Annulled delay slots are a
17152 size win, so we only consider the processor-specific tuning
17153 for !optimize_size. */
17154 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
17156 if (ISA_HAS_BRANCHLIKELY
17158 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
17159 target_flags
|= MASK_BRANCHLIKELY
;
17161 target_flags
&= ~MASK_BRANCHLIKELY
;
17163 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
17164 warning (0, "the %qs architecture does not support branch-likely"
17165 " instructions", mips_arch_info
->name
);
17167 /* If the user hasn't specified -mimadd or -mno-imadd set
17168 MASK_IMADD based on the target architecture and tuning
17170 if ((target_flags_explicit
& MASK_IMADD
) == 0)
17172 if (ISA_HAS_MADD_MSUB
&&
17173 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
17174 target_flags
|= MASK_IMADD
;
17176 target_flags
&= ~MASK_IMADD
;
17178 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
17179 warning (0, "the %qs architecture does not support madd or msub"
17180 " instructions", mips_arch_info
->name
);
17182 /* The effect of -mabicalls isn't defined for the EABI. */
17183 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
17185 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
17186 target_flags
&= ~MASK_ABICALLS
;
17189 /* PIC requires -mabicalls. */
17192 if (mips_abi
== ABI_EABI
)
17193 error ("cannot generate position-independent code for %qs",
17195 else if (!TARGET_ABICALLS
)
17196 error ("position-independent code requires %qs", "-mabicalls");
17199 if (TARGET_ABICALLS_PIC2
)
17200 /* We need to set flag_pic for executables as well as DSOs
17201 because we may reference symbols that are not defined in
17202 the final executable. (MIPS does not use things like
17203 copy relocs, for example.)
17205 There is a body of code that uses __PIC__ to distinguish
17206 between -mabicalls and -mno-abicalls code. The non-__PIC__
17207 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
17208 long as any indirect jumps use $25. */
17211 /* -mvr4130-align is a "speed over size" optimization: it usually produces
17212 faster code, but at the expense of more nops. Enable it at -O3 and
17214 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
17215 target_flags
|= MASK_VR4130_ALIGN
;
17217 /* Prefer a call to memcpy over inline code when optimizing for size,
17218 though see MOVE_RATIO in mips.h. */
17219 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
17220 target_flags
|= MASK_MEMCPY
;
17222 /* If we have a nonzero small-data limit, check that the -mgpopt
17223 setting is consistent with the other target flags. */
17224 if (mips_small_data_threshold
> 0)
17228 if (!TARGET_EXPLICIT_RELOCS
)
17229 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17231 TARGET_LOCAL_SDATA
= false;
17232 TARGET_EXTERN_SDATA
= false;
17236 if (TARGET_VXWORKS_RTP
)
17237 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17239 if (TARGET_ABICALLS
)
17240 warning (0, "cannot use small-data accesses for %qs",
17245 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17246 for all its floating point. */
17247 if (mips_nan
!= MIPS_IEEE_754_2008
)
17249 REAL_MODE_FORMAT (SFmode
) = &mips_single_format
;
17250 REAL_MODE_FORMAT (DFmode
) = &mips_double_format
;
17251 REAL_MODE_FORMAT (TFmode
) = &mips_quad_format
;
17254 /* Make sure that the user didn't turn off paired single support when
17255 MIPS-3D support is requested. */
17257 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
17258 && !TARGET_PAIRED_SINGLE_FLOAT
)
17259 error ("%<-mips3d%> requires %<-mpaired-single%>");
17261 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17263 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
17265 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17266 and TARGET_HARD_FLOAT_ABI are both true. */
17267 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
17269 error ("%qs must be used with %qs",
17270 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
17271 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
17272 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
17276 /* Make sure that -mpaired-single is only used on ISAs that support it.
17277 We must disable it otherwise since it relies on other ISA properties
17278 like ISA_HAS_8CC having their normal values. */
17279 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
17281 error ("the %qs architecture does not support paired-single"
17282 " instructions", mips_arch_info
->name
);
17283 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
17287 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
17288 && !TARGET_CACHE_BUILTIN
)
17290 error ("%qs requires a target that provides the %qs instruction",
17291 "-mr10k-cache-barrier", "cache");
17292 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
17295 /* If TARGET_DSPR2, enable TARGET_DSP. */
17299 /* .eh_frame addresses should be the same width as a C pointer.
17300 Most MIPS ABIs support only one pointer size, so the assembler
17301 will usually know exactly how big an .eh_frame address is.
17303 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17304 originally defined to use 64-bit pointers (i.e. it is LP64), and
17305 this is still the default mode. However, we also support an n32-like
17306 ILP32 mode, which is selected by -mlong32. The problem is that the
17307 assembler has traditionally not had an -mlong option, so it has
17308 traditionally not known whether we're using the ILP32 or LP64 form.
17310 As it happens, gas versions up to and including 2.19 use _32-bit_
17311 addresses for EABI64 .cfi_* directives. This is wrong for the
17312 default LP64 mode, so we can't use the directives by default.
17313 Moreover, since gas's current behavior is at odds with gcc's
17314 default behavior, it seems unwise to rely on future versions
17315 of gas behaving the same way. We therefore avoid using .cfi
17316 directives for -mlong32 as well. */
17317 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
17318 flag_dwarf2_cfi_asm
= 0;
17320 /* .cfi_* directives generate a read-only section, so fall back on
17321 manual .eh_frame creation if we need the section to be writable. */
17322 if (TARGET_WRITABLE_EH_FRAME
)
17323 flag_dwarf2_cfi_asm
= 0;
17325 mips_init_print_operand_punct ();
17327 /* Set up array to map GCC register number to debug register number.
17328 Ignore the special purpose register numbers. */
17330 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17332 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
17333 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
17334 mips_dwarf_regno
[i
] = i
;
17336 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
17339 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
17340 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
17341 mips_dbx_regno
[i
] = i
+ start
;
17343 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
17344 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
17345 mips_dbx_regno
[i
] = i
+ start
;
17347 /* Accumulator debug registers use big-endian ordering. */
17348 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
17349 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
17350 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
17351 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
17352 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
17354 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
17355 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
17358 /* Set up mips_hard_regno_mode_ok. */
17359 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
17360 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
17361 mips_hard_regno_mode_ok
[mode
][regno
]
17362 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
17364 /* Function to allocate machine-dependent function status. */
17365 init_machine_status
= &mips_init_machine_status
;
17367 /* Default to working around R4000 errata only if the processor
17368 was selected explicitly. */
17369 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
17370 && strcmp (mips_arch_info
->name
, "r4000") == 0)
17371 target_flags
|= MASK_FIX_R4000
;
17373 /* Default to working around R4400 errata only if the processor
17374 was selected explicitly. */
17375 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
17376 && strcmp (mips_arch_info
->name
, "r4400") == 0)
17377 target_flags
|= MASK_FIX_R4400
;
17379 /* Default to working around R10000 errata only if the processor
17380 was selected explicitly. */
17381 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
17382 && strcmp (mips_arch_info
->name
, "r10000") == 0)
17383 target_flags
|= MASK_FIX_R10000
;
17385 /* Make sure that branch-likely instructions available when using
17386 -mfix-r10000. The instructions are not available if either:
17388 1. -mno-branch-likely was passed.
17389 2. The selected ISA does not support branch-likely and
17390 the command line does not include -mbranch-likely. */
17391 if (TARGET_FIX_R10000
17392 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
17393 ? !ISA_HAS_BRANCHLIKELY
17394 : !TARGET_BRANCHLIKELY
))
17395 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17397 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
17399 warning (0, "the %qs architecture does not support the synci "
17400 "instruction", mips_arch_info
->name
);
17401 target_flags
&= ~MASK_SYNCI
;
17404 /* Only optimize PIC indirect calls if they are actually required. */
17405 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
17406 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17408 /* Save base state of options. */
17409 mips_base_target_flags
= target_flags
;
17410 mips_base_schedule_insns
= flag_schedule_insns
;
17411 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
17412 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
17413 mips_base_align_loops
= align_loops
;
17414 mips_base_align_jumps
= align_jumps
;
17415 mips_base_align_functions
= align_functions
;
17417 /* Now select the ISA mode.
17419 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17420 later if required. */
17421 mips_set_compression_mode (0);
17423 /* We register a second machine specific reorg pass after delay slot
17424 filling. Registering the pass must be done at start up. It's
17425 convenient to do it here. */
17426 opt_pass
*new_pass
= make_pass_mips_machine_reorg2 (g
);
17427 struct register_pass_info insert_pass_mips_machine_reorg2
=
17429 new_pass
, /* pass */
17430 "dbr", /* reference_pass_name */
17431 1, /* ref_pass_instance_number */
17432 PASS_POS_INSERT_AFTER
/* po_op */
17434 register_pass (&insert_pass_mips_machine_reorg2
);
17436 if (TARGET_HARD_FLOAT_ABI
&& TARGET_MIPS5900
)
17437 REAL_MODE_FORMAT (SFmode
) = &spu_single_format
;
17440 /* Swap the register information for registers I and I + 1, which
17441 currently have the wrong endianness. Note that the registers'
17442 fixedness and call-clobberedness might have been set on the
17446 mips_swap_registers (unsigned int i
)
17451 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17452 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17454 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
17455 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
17456 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
17457 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
17463 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17466 mips_conditional_register_usage (void)
17471 /* These DSP control register fields are global. */
17472 global_regs
[CCDSP_PO_REGNUM
] = 1;
17473 global_regs
[CCDSP_SC_REGNUM
] = 1;
17476 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17477 reg_class_contents
[(int) DSP_ACC_REGS
]);
17479 if (!TARGET_HARD_FLOAT
)
17481 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17482 reg_class_contents
[(int) FP_REGS
]);
17483 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17484 reg_class_contents
[(int) ST_REGS
]);
17486 else if (!ISA_HAS_8CC
)
17488 /* We only have a single condition-code register. We implement
17489 this by fixing all the condition-code registers and generating
17490 RTL that refers directly to ST_REG_FIRST. */
17491 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17492 reg_class_contents
[(int) ST_REGS
]);
17493 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
17494 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
17498 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17499 are call-saved, and saving them via a MIPS16 register would
17500 probably waste more time than just reloading the value.
17502 We permit the $t temporary registers when optimizing for speed
17503 but not when optimizing for space because using them results in
17504 code that is larger (but faster) then not using them. We do
17505 allow $24 (t8) because it is used in CMP and CMPI instructions
17506 and $25 (t9) because it is used as the function call address in
17509 fixed_regs
[18] = call_used_regs
[18] = 1;
17510 fixed_regs
[19] = call_used_regs
[19] = 1;
17511 fixed_regs
[20] = call_used_regs
[20] = 1;
17512 fixed_regs
[21] = call_used_regs
[21] = 1;
17513 fixed_regs
[22] = call_used_regs
[22] = 1;
17514 fixed_regs
[23] = call_used_regs
[23] = 1;
17515 fixed_regs
[26] = call_used_regs
[26] = 1;
17516 fixed_regs
[27] = call_used_regs
[27] = 1;
17517 fixed_regs
[30] = call_used_regs
[30] = 1;
17520 fixed_regs
[8] = call_used_regs
[8] = 1;
17521 fixed_regs
[9] = call_used_regs
[9] = 1;
17522 fixed_regs
[10] = call_used_regs
[10] = 1;
17523 fixed_regs
[11] = call_used_regs
[11] = 1;
17524 fixed_regs
[12] = call_used_regs
[12] = 1;
17525 fixed_regs
[13] = call_used_regs
[13] = 1;
17526 fixed_regs
[14] = call_used_regs
[14] = 1;
17527 fixed_regs
[15] = call_used_regs
[15] = 1;
17530 /* Do not allow HI and LO to be treated as register operands.
17531 There are no MTHI or MTLO instructions (or any real need
17532 for them) and one-way registers cannot easily be reloaded. */
17533 AND_COMPL_HARD_REG_SET (operand_reg_set
,
17534 reg_class_contents
[(int) MD_REGS
]);
17536 /* $f20-$f23 are call-clobbered for n64. */
17537 if (mips_abi
== ABI_64
)
17540 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
17541 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17543 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17545 if (mips_abi
== ABI_N32
)
17548 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
17549 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17551 /* Make sure that double-register accumulator values are correctly
17552 ordered for the current endianness. */
17553 if (TARGET_LITTLE_ENDIAN
)
17555 unsigned int regno
;
17557 mips_swap_registers (MD_REG_FIRST
);
17558 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
17559 mips_swap_registers (regno
);
17563 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
17564 other registers for instructions for which it is possible. This
17565 encourages the compiler to use CMP in cases where an XOR would
17566 require some register shuffling. */
17569 mips_order_regs_for_local_alloc (void)
17573 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17574 reg_alloc_order
[i
] = i
;
17578 /* It really doesn't matter where we put register 0, since it is
17579 a fixed register anyhow. */
17580 reg_alloc_order
[0] = 24;
17581 reg_alloc_order
[24] = 0;
17585 /* Implement EH_USES. */
17588 mips_eh_uses (unsigned int regno
)
17590 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
17592 /* We need to force certain registers to be live in order to handle
17593 PIC long branches correctly. See mips_must_initialize_gp_p for
17595 if (mips_cfun_has_cprestore_slot_p ())
17597 if (regno
== CPRESTORE_SLOT_REGNUM
)
17602 if (cfun
->machine
->global_pointer
== regno
)
17610 /* Implement EPILOGUE_USES. */
17613 mips_epilogue_uses (unsigned int regno
)
17615 /* Say that the epilogue uses the return address register. Note that
17616 in the case of sibcalls, the values "used by the epilogue" are
17617 considered live at the start of the called function. */
17618 if (regno
== RETURN_ADDR_REGNUM
)
17621 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17622 See the comment above load_call<mode> for details. */
17623 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
17626 /* An interrupt handler must preserve some registers that are
17627 ordinarily call-clobbered. */
17628 if (cfun
->machine
->interrupt_handler_p
17629 && mips_interrupt_extra_call_saved_reg_p (regno
))
17635 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17638 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
17640 return REG_P (*x
) && REGNO (*x
) == AT_REGNUM
;
17643 /* Return true if INSN needs to be wrapped in ".set noat".
17644 INSN has NOPERANDS operands, stored in OPVEC. */
17647 mips_need_noat_wrapper_p (rtx insn
, rtx
*opvec
, int noperands
)
17651 if (recog_memoized (insn
) >= 0)
17652 for (i
= 0; i
< noperands
; i
++)
17653 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
17658 /* Implement FINAL_PRESCAN_INSN. */
17661 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
17663 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17664 mips_push_asm_switch (&mips_noat
);
17667 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17670 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx insn
,
17671 rtx
*opvec
, int noperands
)
17673 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17674 mips_pop_asm_switch (&mips_noat
);
17677 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17678 EXT_CODE is the code of the extension used. Return NULL if widening
17679 multiplication shouldn't be used. */
17682 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
17686 signed_p
= ext_code
== SIGN_EXTEND
;
17689 /* Don't use widening multiplication with MULT when we have DMUL. Even
17690 with the extension of its input operands DMUL is faster. Note that
17691 the extension is not needed for signed multiplication. In order to
17692 ensure that we always remove the redundant sign-extension in this
17693 case we still expand mulsidi3 for DMUL. */
17695 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
17698 ? gen_mulsidi3_64bit_mips16
17699 : gen_umulsidi3_64bit_mips16
);
17700 if (TARGET_FIX_R4000
)
17702 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
17708 ? gen_mulsidi3_32bit_mips16
17709 : gen_umulsidi3_32bit_mips16
);
17710 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
17711 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
17712 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
17716 /* Return true if PATTERN matches the kind of instruction generated by
17717 umips_build_save_restore. SAVE_P is true for store. */
17720 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
17724 HOST_WIDE_INT first_offset
= 0;
17725 rtx first_base
= 0;
17726 unsigned int regmask
= 0;
17728 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
17730 rtx set
, reg
, mem
, this_base
;
17731 HOST_WIDE_INT this_offset
;
17733 /* Check that we have a SET. */
17734 set
= XVECEXP (pattern
, 0, n
);
17735 if (GET_CODE (set
) != SET
)
17738 /* Check that the SET is a load (if restoring) or a store
17740 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17741 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
17744 /* Check that the address is the sum of base and a possibly-zero
17745 constant offset. Determine if the offset is in range. */
17746 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
17747 if (!REG_P (this_base
))
17752 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
17754 first_base
= this_base
;
17755 first_offset
= this_offset
;
17759 /* Check that the save slots are consecutive. */
17760 if (REGNO (this_base
) != REGNO (first_base
)
17761 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
17765 /* Check that SET's other operand is a register. */
17766 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
17770 regmask
|= 1 << REGNO (reg
);
17773 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
17774 if (regmask
== umips_swm_mask
[i
])
17780 /* Return the assembly instruction for microMIPS LWM or SWM.
17781 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17784 umips_output_save_restore (bool save_p
, rtx pattern
)
17786 static char buffer
[300];
17789 HOST_WIDE_INT offset
;
17790 rtx base
, mem
, set
, last_set
, last_reg
;
17792 /* Parse the pattern. */
17793 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
17795 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
17797 n
= XVECLEN (pattern
, 0);
17799 set
= XVECEXP (pattern
, 0, 0);
17800 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17801 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
17803 last_set
= XVECEXP (pattern
, 0, n
- 1);
17804 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
17806 if (REGNO (last_reg
) == 31)
17809 gcc_assert (n
<= 9);
17813 s
+= sprintf (s
, "%s,", reg_names
[16]);
17815 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
17817 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
17820 if (REGNO (last_reg
) == 31)
17821 s
+= sprintf (s
, "%s,", reg_names
[31]);
17823 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
17827 /* Return true if MEM1 and MEM2 use the same base register, and the
17828 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17829 register into (from) which the contents of MEM1 will be loaded
17830 (stored), depending on the value of LOAD_P.
17831 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17834 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
17835 rtx first_reg
, rtx mem1
, rtx mem2
)
17838 HOST_WIDE_INT offset1
, offset2
;
17840 if (!MEM_P (mem1
) || !MEM_P (mem2
))
17843 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
17844 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
17846 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
17849 /* Avoid invalid load pair instructions. */
17850 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
17853 /* We must avoid this case for anti-dependence.
17856 first_reg is $2, but the base is $3. */
17859 && REGNO (first_reg
) + 1 == REGNO (base1
))
17862 if (offset2
!= offset1
+ 4)
17865 if (!UMIPS_12BIT_OFFSET_P (offset1
))
17871 /* OPERANDS describes the operands to a pair of SETs, in the order
17872 dest1, src1, dest2, src2. Return true if the operands can be used
17873 in an LWP or SWP instruction; LOAD_P says which. */
17876 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
17878 rtx reg1
, reg2
, mem1
, mem2
;
17882 reg1
= operands
[0];
17883 reg2
= operands
[2];
17884 mem1
= operands
[1];
17885 mem2
= operands
[3];
17889 reg1
= operands
[1];
17890 reg2
= operands
[3];
17891 mem1
= operands
[0];
17892 mem2
= operands
[2];
17895 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17896 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
17898 if (REGNO (reg1
) == REGNO (reg2
) + 1)
17899 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
17904 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17905 the first register is REG and the first memory slot is MEM.
17906 LOAD_P is true for LWP. */
17909 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
17911 rtx ops
[] = {reg
, mem
};
17914 output_asm_insn ("lwp\t%0,%1", ops
);
17916 output_asm_insn ("swp\t%0,%1", ops
);
17919 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17920 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17923 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
17925 rtx reg1
, reg2
, mem1
, mem2
;
17928 reg1
= operands
[0];
17929 reg2
= operands
[2];
17930 mem1
= operands
[1];
17931 mem2
= operands
[3];
17935 reg1
= operands
[1];
17936 reg2
= operands
[3];
17937 mem1
= operands
[0];
17938 mem2
= operands
[2];
17941 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17943 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
17947 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
17948 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
17951 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17954 umips_movep_target_p (rtx reg1
, rtx reg2
)
17956 int regno1
, regno2
, pair
;
17958 static const int match
[8] = {
17959 0x00000060, /* 5, 6 */
17960 0x000000a0, /* 5, 7 */
17961 0x000000c0, /* 6, 7 */
17962 0x00200010, /* 4, 21 */
17963 0x00400010, /* 4, 22 */
17964 0x00000030, /* 4, 5 */
17965 0x00000050, /* 4, 6 */
17966 0x00000090 /* 4, 7 */
17969 if (!REG_P (reg1
) || !REG_P (reg2
))
17972 regno1
= REGNO (reg1
);
17973 regno2
= REGNO (reg2
);
17975 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
17978 pair
= (1 << regno1
) | (1 << regno2
);
17980 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
17981 if (pair
== match
[i
])
17987 /* Return the size in bytes of the trampoline code, padded to
17988 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17989 function address immediately follow. */
17992 mips_trampoline_code_size (void)
17994 if (TARGET_USE_PIC_FN_ADDR_REG
)
17996 else if (ptr_mode
== DImode
)
17998 else if (ISA_HAS_LOAD_DELAY
)
18004 /* Implement TARGET_TRAMPOLINE_INIT. */
18007 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
18009 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
18012 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
18014 /* Work out the offsets of the pointers from the start of the
18015 trampoline code. */
18016 end_addr_offset
= mips_trampoline_code_size ();
18017 static_chain_offset
= end_addr_offset
;
18018 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
18020 /* Get pointers to the beginning and end of the code block. */
18021 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
18022 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
18024 #define OP(X) gen_int_mode (X, SImode)
18026 /* Build up the code in TRAMPOLINE. */
18028 if (TARGET_USE_PIC_FN_ADDR_REG
)
18030 /* $25 contains the address of the trampoline. Emit code of the form:
18032 l[wd] $1, target_function_offset($25)
18033 l[wd] $static_chain, static_chain_offset($25)
18036 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
18037 target_function_offset
,
18038 PIC_FUNCTION_ADDR_REGNUM
));
18039 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18040 static_chain_offset
,
18041 PIC_FUNCTION_ADDR_REGNUM
));
18042 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
18043 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
18045 else if (ptr_mode
== DImode
)
18047 /* It's too cumbersome to create the full 64-bit address, so let's
18053 1: l[wd] $25, target_function_offset - 12($31)
18054 l[wd] $static_chain, static_chain_offset - 12($31)
18058 where 12 is the offset of "1:" from the start of the code block. */
18059 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
18060 trampoline
[i
++] = OP (MIPS_BAL (1));
18061 trampoline
[i
++] = OP (MIPS_NOP
);
18062 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
18063 target_function_offset
- 12,
18064 RETURN_ADDR_REGNUM
));
18065 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18066 static_chain_offset
- 12,
18067 RETURN_ADDR_REGNUM
));
18068 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18069 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
18073 /* If the target has load delays, emit:
18075 lui $1, %hi(end_addr)
18076 lw $25, %lo(end_addr + ...)($1)
18077 lw $static_chain, %lo(end_addr + ...)($1)
18083 lui $1, %hi(end_addr)
18084 lw $25, %lo(end_addr + ...)($1)
18086 lw $static_chain, %lo(end_addr + ...)($1). */
18088 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
18089 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
18090 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
18091 NULL
, false, OPTAB_WIDEN
);
18092 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
18093 NULL
, false, OPTAB_WIDEN
);
18094 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
18096 /* Emit the LUI. */
18097 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
18098 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
18099 NULL
, false, OPTAB_WIDEN
);
18101 /* Emit the load of the target function. */
18102 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
18103 target_function_offset
- end_addr_offset
,
18105 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
18106 NULL
, false, OPTAB_WIDEN
);
18108 /* Emit the JR here, if we can. */
18109 if (!ISA_HAS_LOAD_DELAY
)
18110 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18112 /* Emit the load of the static chain register. */
18113 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18114 static_chain_offset
- end_addr_offset
,
18116 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
18117 NULL
, false, OPTAB_WIDEN
);
18119 /* Emit the JR, if we couldn't above. */
18120 if (ISA_HAS_LOAD_DELAY
)
18122 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18123 trampoline
[i
++] = OP (MIPS_NOP
);
18129 /* Copy the trampoline code. Leave any padding uninitialized. */
18130 for (j
= 0; j
< i
; j
++)
18132 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
18133 mips_emit_move (mem
, trampoline
[j
]);
18136 /* Set up the static chain pointer field. */
18137 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
18138 mips_emit_move (mem
, chain_value
);
18140 /* Set up the target function field. */
18141 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
18142 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
18144 /* Flush the code part of the trampoline. */
18145 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
18146 emit_insn (gen_clear_cache (addr
, end_addr
));
18149 /* Implement FUNCTION_PROFILER. */
18151 void mips_function_profiler (FILE *file
)
18154 sorry ("mips16 function profiling");
18155 if (TARGET_LONG_CALLS
)
18157 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
18158 if (Pmode
== DImode
)
18159 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
18161 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
18163 mips_push_asm_switch (&mips_noat
);
18164 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
18165 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
18166 /* _mcount treats $2 as the static chain register. */
18167 if (cfun
->static_chain_decl
!= NULL
)
18168 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
18169 reg_names
[STATIC_CHAIN_REGNUM
]);
18170 if (TARGET_MCOUNT_RA_ADDRESS
)
18172 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
18173 ra save location. */
18174 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
18175 /* ra not saved, pass zero. */
18176 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
18178 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
18179 Pmode
== DImode
? "dla" : "la", reg_names
[12],
18180 cfun
->machine
->frame
.ra_fp_offset
,
18181 reg_names
[STACK_POINTER_REGNUM
]);
18183 if (!TARGET_NEWABI
)
18185 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
18186 TARGET_64BIT
? "dsubu" : "subu",
18187 reg_names
[STACK_POINTER_REGNUM
],
18188 reg_names
[STACK_POINTER_REGNUM
],
18189 Pmode
== DImode
? 16 : 8);
18191 if (TARGET_LONG_CALLS
)
18192 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
18194 fprintf (file
, "\tjal\t_mcount\n");
18195 mips_pop_asm_switch (&mips_noat
);
18196 /* _mcount treats $2 as the static chain register. */
18197 if (cfun
->static_chain_decl
!= NULL
)
18198 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
18202 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
18203 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
18204 when TARGET_LOONGSON_VECTORS is true. */
18206 static unsigned HOST_WIDE_INT
18207 mips_shift_truncation_mask (enum machine_mode mode
)
18209 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
18212 return GET_MODE_BITSIZE (mode
) - 1;
18215 /* Implement TARGET_PREPARE_PCH_SAVE. */
18218 mips_prepare_pch_save (void)
18220 /* We are called in a context where the current MIPS16 vs. non-MIPS16
18221 setting should be irrelevant. The question then is: which setting
18222 makes most sense at load time?
18224 The PCH is loaded before the first token is read. We should never
18225 have switched into MIPS16 mode by that point, and thus should not
18226 have populated mips16_globals. Nor can we load the entire contents
18227 of mips16_globals from the PCH file, because mips16_globals contains
18228 a combination of GGC and non-GGC data.
18230 There is therefore no point in trying save the GGC part of
18231 mips16_globals to the PCH file, or to preserve MIPS16ness across
18232 the PCH save and load. The loading compiler would not have access
18233 to the non-GGC parts of mips16_globals (either from the PCH file,
18234 or from a copy that the loading compiler generated itself) and would
18235 have to call target_reinit anyway.
18237 It therefore seems best to switch back to non-MIPS16 mode at
18238 save time, and to ensure that mips16_globals remains null after
18240 mips_set_compression_mode (0);
18241 mips16_globals
= 0;
18244 /* Generate or test for an insn that supports a constant permutation. */
18246 #define MAX_VECT_LEN 8
18248 struct expand_vec_perm_d
18250 rtx target
, op0
, op1
;
18251 unsigned char perm
[MAX_VECT_LEN
];
18252 enum machine_mode vmode
;
18253 unsigned char nelt
;
18258 /* Construct (set target (vec_select op0 (parallel perm))) and
18259 return true if that's a valid instruction in the active ISA. */
18262 mips_expand_vselect (rtx target
, rtx op0
,
18263 const unsigned char *perm
, unsigned nelt
)
18265 rtx rperm
[MAX_VECT_LEN
], x
;
18268 for (i
= 0; i
< nelt
; ++i
)
18269 rperm
[i
] = GEN_INT (perm
[i
]);
18271 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
18272 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
18273 x
= gen_rtx_SET (VOIDmode
, target
, x
);
18276 if (recog_memoized (x
) < 0)
18284 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18287 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
18288 const unsigned char *perm
, unsigned nelt
)
18290 enum machine_mode v2mode
;
18293 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
18294 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
18295 return mips_expand_vselect (target
, x
, perm
, nelt
);
18298 /* Recognize patterns for even-odd extraction. */
18301 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
18303 unsigned i
, odd
, nelt
= d
->nelt
;
18304 rtx t0
, t1
, t2
, t3
;
18306 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18308 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18315 for (i
= 1; i
< nelt
; ++i
)
18316 if (d
->perm
[i
] != i
* 2 + odd
)
18322 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18323 t0
= gen_reg_rtx (d
->vmode
);
18324 t1
= gen_reg_rtx (d
->vmode
);
18328 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
18329 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
18331 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
18333 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
18337 t2
= gen_reg_rtx (d
->vmode
);
18338 t3
= gen_reg_rtx (d
->vmode
);
18339 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
18340 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
18341 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
18342 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
18344 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
18346 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
18350 gcc_unreachable ();
18355 /* Recognize patterns for the Loongson PSHUFH instruction. */
18358 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
18363 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18365 if (d
->vmode
!= V4HImode
)
18370 /* Convert the selector into the packed 8-bit form for pshufh. */
18371 /* Recall that loongson is little-endian only. No big-endian
18372 adjustment required. */
18373 for (i
= mask
= 0; i
< 4; i
++)
18374 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
18375 rmask
= force_reg (SImode
, GEN_INT (mask
));
18377 if (d
->one_vector_p
)
18378 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
18381 rtx t0
, t1
, x
, merge
, rmerge
[4];
18383 t0
= gen_reg_rtx (V4HImode
);
18384 t1
= gen_reg_rtx (V4HImode
);
18385 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
18386 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
18388 for (i
= 0; i
< 4; ++i
)
18389 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
18390 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
18391 merge
= force_reg (V4HImode
, merge
);
18393 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
18394 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18396 x
= gen_rtx_NOT (V4HImode
, merge
);
18397 x
= gen_rtx_AND (V4HImode
, x
, t0
);
18398 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18400 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
18401 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
18407 /* Recognize broadcast patterns for the Loongson. */
18410 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
18415 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18417 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18418 if (d
->vmode
!= V8QImode
)
18420 if (!d
->one_vector_p
)
18424 for (i
= 1; i
< 8; ++i
)
18425 if (d
->perm
[i
] != elt
)
18431 /* With one interleave we put two of the desired element adjacent. */
18432 t0
= gen_reg_rtx (V8QImode
);
18434 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
18436 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
18438 /* Shuffle that one HImode element into all locations. */
18441 t1
= gen_reg_rtx (V4HImode
);
18442 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
18443 force_reg (SImode
, GEN_INT (elt
))));
18445 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
18450 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
18452 unsigned int i
, nelt
= d
->nelt
;
18453 unsigned char perm2
[MAX_VECT_LEN
];
18455 if (d
->one_vector_p
)
18457 /* Try interleave with alternating operands. */
18458 memcpy (perm2
, d
->perm
, sizeof(perm2
));
18459 for (i
= 1; i
< nelt
; i
+= 2)
18461 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
18466 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
18470 /* Try again with swapped operands. */
18471 for (i
= 0; i
< nelt
; ++i
)
18472 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
18473 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
18477 if (mips_expand_vpc_loongson_even_odd (d
))
18479 if (mips_expand_vpc_loongson_pshufh (d
))
18481 if (mips_expand_vpc_loongson_bcast (d
))
18486 /* Expand a vec_perm_const pattern. */
18489 mips_expand_vec_perm_const (rtx operands
[4])
18491 struct expand_vec_perm_d d
;
18492 int i
, nelt
, which
;
18493 unsigned char orig_perm
[MAX_VECT_LEN
];
18497 d
.target
= operands
[0];
18498 d
.op0
= operands
[1];
18499 d
.op1
= operands
[2];
18502 d
.vmode
= GET_MODE (d
.target
);
18503 gcc_assert (VECTOR_MODE_P (d
.vmode
));
18504 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18505 d
.testing_p
= false;
18507 for (i
= which
= 0; i
< nelt
; ++i
)
18509 rtx e
= XVECEXP (sel
, 0, i
);
18510 int ei
= INTVAL (e
) & (2 * nelt
- 1);
18511 which
|= (ei
< nelt
? 1 : 2);
18514 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18522 d
.one_vector_p
= false;
18523 if (!rtx_equal_p (d
.op0
, d
.op1
))
18528 for (i
= 0; i
< nelt
; ++i
)
18529 d
.perm
[i
] &= nelt
- 1;
18531 d
.one_vector_p
= true;
18536 d
.one_vector_p
= true;
18540 ok
= mips_expand_vec_perm_const_1 (&d
);
18542 /* If we were given a two-vector permutation which just happened to
18543 have both input vectors equal, we folded this into a one-vector
18544 permutation. There are several loongson patterns that are matched
18545 via direct vec_select+vec_concat expansion, but we do not have
18546 support in mips_expand_vec_perm_const_1 to guess the adjustment
18547 that should be made for a single operand. Just try again with
18548 the original permutation. */
18549 if (!ok
&& which
== 3)
18551 d
.op0
= operands
[1];
18552 d
.op1
= operands
[2];
18553 d
.one_vector_p
= false;
18554 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18555 ok
= mips_expand_vec_perm_const_1 (&d
);
18561 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18564 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
18565 const unsigned char *sel
)
18567 struct expand_vec_perm_d d
;
18568 unsigned int i
, nelt
, which
;
18572 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18573 d
.testing_p
= true;
18574 memcpy (d
.perm
, sel
, nelt
);
18576 /* Categorize the set of elements in the selector. */
18577 for (i
= which
= 0; i
< nelt
; ++i
)
18579 unsigned char e
= d
.perm
[i
];
18580 gcc_assert (e
< 2 * nelt
);
18581 which
|= (e
< nelt
? 1 : 2);
18584 /* For all elements from second vector, fold the elements to first. */
18586 for (i
= 0; i
< nelt
; ++i
)
18589 /* Check whether the mask can be applied to the vector type. */
18590 d
.one_vector_p
= (which
!= 3);
18592 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
18593 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
18594 if (!d
.one_vector_p
)
18595 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
18598 ret
= mips_expand_vec_perm_const_1 (&d
);
18604 /* Expand an integral vector unpack operation. */
18607 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
18609 enum machine_mode imode
= GET_MODE (operands
[1]);
18610 rtx (*unpack
) (rtx
, rtx
, rtx
);
18611 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
18612 rtx tmp
, dest
, zero
;
18618 unpack
= gen_loongson_punpckhbh
;
18620 unpack
= gen_loongson_punpcklbh
;
18621 cmpgt
= gen_loongson_pcmpgtb
;
18625 unpack
= gen_loongson_punpckhhw
;
18627 unpack
= gen_loongson_punpcklhw
;
18628 cmpgt
= gen_loongson_pcmpgth
;
18631 gcc_unreachable ();
18634 zero
= force_reg (imode
, CONST0_RTX (imode
));
18639 tmp
= gen_reg_rtx (imode
);
18640 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
18643 dest
= gen_reg_rtx (imode
);
18644 emit_insn (unpack (dest
, operands
[1], tmp
));
18646 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
18649 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18652 mips_constant_elt_p (rtx x
)
18654 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
18657 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18660 mips_expand_vi_broadcast (enum machine_mode vmode
, rtx target
, rtx elt
)
18662 struct expand_vec_perm_d d
;
18666 if (elt
!= const0_rtx
)
18667 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
18669 elt
= gen_lowpart (DImode
, elt
);
18671 t1
= gen_reg_rtx (vmode
);
18675 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
18678 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
18681 gcc_unreachable ();
18684 memset (&d
, 0, sizeof (d
));
18689 d
.nelt
= GET_MODE_NUNITS (vmode
);
18690 d
.one_vector_p
= true;
18692 ok
= mips_expand_vec_perm_const_1 (&d
);
18696 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18697 elements of VALS with zeros, copy the constant vector to TARGET. */
18700 mips_expand_vi_constant (enum machine_mode vmode
, unsigned nelt
,
18701 rtx target
, rtx vals
)
18703 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
18706 for (i
= 0; i
< nelt
; ++i
)
18708 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
18709 RTVEC_ELT (vec
, i
) = const0_rtx
;
18712 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
18716 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18719 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
18721 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
18723 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
18724 GEN_INT (one_var
)));
18727 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18730 mips_expand_vi_general (enum machine_mode vmode
, enum machine_mode imode
,
18731 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
18733 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
18734 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
18737 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
18739 for (i
= 0; i
< nelt
; ++i
)
18741 rtx x
= XVECEXP (vals
, 0, i
);
18742 if (!mips_constant_elt_p (x
))
18743 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
18746 emit_move_insn (target
, mem
);
18749 /* Expand a vector initialization. */
18752 mips_expand_vector_init (rtx target
, rtx vals
)
18754 enum machine_mode vmode
= GET_MODE (target
);
18755 enum machine_mode imode
= GET_MODE_INNER (vmode
);
18756 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
18757 unsigned nvar
= 0, one_var
= -1u;
18758 bool all_same
= true;
18761 for (i
= 0; i
< nelt
; ++i
)
18763 x
= XVECEXP (vals
, 0, i
);
18764 if (!mips_constant_elt_p (x
))
18765 nvar
++, one_var
= i
;
18766 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
18770 /* Load constants from the pool, or whatever's handy. */
18773 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
18777 /* For two-part initialization, always use CONCAT. */
18780 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
18781 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
18782 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
18783 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18787 /* Loongson is the only cpu with vectors with more elements. */
18788 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
18790 /* If all values are identical, broadcast the value. */
18793 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
18797 /* If we've only got one non-variable V4HImode, use PINSRH. */
18798 if (nvar
== 1 && vmode
== V4HImode
)
18800 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
18804 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
18807 /* Expand a vector reduction. */
18810 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
18812 enum machine_mode vmode
= GET_MODE (in
);
18813 unsigned char perm2
[2];
18814 rtx last
, next
, fold
, x
;
18818 fold
= gen_reg_rtx (vmode
);
18822 /* Use PUL/PLU to produce { L, H } op { H, L }.
18823 By reversing the pair order, rather than a pure interleave high,
18824 we avoid erroneous exceptional conditions that we might otherwise
18825 produce from the computation of H op H. */
18828 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
18833 /* Use interleave to produce { H, L } op { H, H }. */
18834 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
18838 /* Perform the first reduction with interleave,
18839 and subsequent reductions with shifts. */
18840 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
18842 next
= gen_reg_rtx (vmode
);
18843 emit_insn (gen (next
, last
, fold
));
18846 fold
= gen_reg_rtx (vmode
);
18847 x
= force_reg (SImode
, GEN_INT (16));
18848 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
18852 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
18854 next
= gen_reg_rtx (vmode
);
18855 emit_insn (gen (next
, last
, fold
));
18858 fold
= gen_reg_rtx (vmode
);
18859 x
= force_reg (SImode
, GEN_INT (16));
18860 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18862 next
= gen_reg_rtx (vmode
);
18863 emit_insn (gen (next
, last
, fold
));
18866 fold
= gen_reg_rtx (vmode
);
18867 x
= force_reg (SImode
, GEN_INT (8));
18868 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18872 gcc_unreachable ();
18875 emit_insn (gen (target
, last
, fold
));
18878 /* Expand a vector minimum/maximum. */
18881 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
18882 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
18884 enum machine_mode vmode
= GET_MODE (target
);
18887 tc
= gen_reg_rtx (vmode
);
18888 t0
= gen_reg_rtx (vmode
);
18889 t1
= gen_reg_rtx (vmode
);
18892 emit_insn (cmp (tc
, op0
, op1
));
18894 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
18895 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18897 x
= gen_rtx_NOT (vmode
, tc
);
18898 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
18899 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18901 x
= gen_rtx_IOR (vmode
, t0
, t1
);
18902 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18905 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
18908 mips_case_values_threshold (void)
18910 /* In MIPS16 mode using a larger case threshold generates smaller code. */
18911 if (TARGET_MIPS16
&& optimize_size
)
18914 return default_case_values_threshold ();
18917 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
18920 mips_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
18922 if (!TARGET_HARD_FLOAT_ABI
)
18924 tree exceptions_var
= create_tmp_var (MIPS_ATYPE_USI
, NULL
);
18925 tree fcsr_orig_var
= create_tmp_var (MIPS_ATYPE_USI
, NULL
);
18926 tree fcsr_mod_var
= create_tmp_var (MIPS_ATYPE_USI
, NULL
);
18927 tree get_fcsr
= mips_builtin_decls
[MIPS_GET_FCSR
];
18928 tree set_fcsr
= mips_builtin_decls
[MIPS_SET_FCSR
];
18929 tree get_fcsr_hold_call
= build_call_expr (get_fcsr
, 0);
18930 tree hold_assign_orig
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
18931 fcsr_orig_var
, get_fcsr_hold_call
);
18932 tree hold_mod_val
= build2 (BIT_AND_EXPR
, MIPS_ATYPE_USI
, fcsr_orig_var
,
18933 build_int_cst (MIPS_ATYPE_USI
, 0xfffff003));
18934 tree hold_assign_mod
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
18935 fcsr_mod_var
, hold_mod_val
);
18936 tree set_fcsr_hold_call
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
18937 tree hold_all
= build2 (COMPOUND_EXPR
, MIPS_ATYPE_USI
,
18938 hold_assign_orig
, hold_assign_mod
);
18939 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_all
,
18940 set_fcsr_hold_call
);
18942 *clear
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
18944 tree get_fcsr_update_call
= build_call_expr (get_fcsr
, 0);
18945 *update
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
18946 exceptions_var
, get_fcsr_update_call
);
18947 tree set_fcsr_update_call
= build_call_expr (set_fcsr
, 1, fcsr_orig_var
);
18948 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
18949 set_fcsr_update_call
);
18950 tree atomic_feraiseexcept
18951 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
18952 tree int_exceptions_var
= fold_convert (integer_type_node
,
18954 tree atomic_feraiseexcept_call
= build_call_expr (atomic_feraiseexcept
,
18955 1, int_exceptions_var
);
18956 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
18957 atomic_feraiseexcept_call
);
18960 /* Initialize the GCC target structure. */
18961 #undef TARGET_ASM_ALIGNED_HI_OP
18962 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18963 #undef TARGET_ASM_ALIGNED_SI_OP
18964 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18965 #undef TARGET_ASM_ALIGNED_DI_OP
18966 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18968 #undef TARGET_OPTION_OVERRIDE
18969 #define TARGET_OPTION_OVERRIDE mips_option_override
18971 #undef TARGET_LEGITIMIZE_ADDRESS
18972 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18974 #undef TARGET_ASM_FUNCTION_PROLOGUE
18975 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18976 #undef TARGET_ASM_FUNCTION_EPILOGUE
18977 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18978 #undef TARGET_ASM_SELECT_RTX_SECTION
18979 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18980 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18981 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18983 #undef TARGET_SCHED_INIT
18984 #define TARGET_SCHED_INIT mips_sched_init
18985 #undef TARGET_SCHED_REORDER
18986 #define TARGET_SCHED_REORDER mips_sched_reorder
18987 #undef TARGET_SCHED_REORDER2
18988 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18989 #undef TARGET_SCHED_VARIABLE_ISSUE
18990 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18991 #undef TARGET_SCHED_ADJUST_COST
18992 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18993 #undef TARGET_SCHED_ISSUE_RATE
18994 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18995 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18996 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18997 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18998 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18999 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
19000 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
19001 mips_multipass_dfa_lookahead
19002 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
19003 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
19004 mips_small_register_classes_for_mode_p
19006 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
19007 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
19009 #undef TARGET_INSERT_ATTRIBUTES
19010 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
19011 #undef TARGET_MERGE_DECL_ATTRIBUTES
19012 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
19013 #undef TARGET_CAN_INLINE_P
19014 #define TARGET_CAN_INLINE_P mips_can_inline_p
19015 #undef TARGET_SET_CURRENT_FUNCTION
19016 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
19018 #undef TARGET_VALID_POINTER_MODE
19019 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
19020 #undef TARGET_REGISTER_MOVE_COST
19021 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
19022 #undef TARGET_MEMORY_MOVE_COST
19023 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
19024 #undef TARGET_RTX_COSTS
19025 #define TARGET_RTX_COSTS mips_rtx_costs
19026 #undef TARGET_ADDRESS_COST
19027 #define TARGET_ADDRESS_COST mips_address_cost
19029 #undef TARGET_IN_SMALL_DATA_P
19030 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
19032 #undef TARGET_MACHINE_DEPENDENT_REORG
19033 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
19035 #undef TARGET_PREFERRED_RELOAD_CLASS
19036 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
19038 #undef TARGET_EXPAND_TO_RTL_HOOK
19039 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
19040 #undef TARGET_ASM_FILE_START
19041 #define TARGET_ASM_FILE_START mips_file_start
19042 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
19043 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
19044 #undef TARGET_ASM_CODE_END
19045 #define TARGET_ASM_CODE_END mips_code_end
19047 #undef TARGET_INIT_LIBFUNCS
19048 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
19050 #undef TARGET_BUILD_BUILTIN_VA_LIST
19051 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
19052 #undef TARGET_EXPAND_BUILTIN_VA_START
19053 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
19054 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
19055 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
19057 #undef TARGET_PROMOTE_FUNCTION_MODE
19058 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
19059 #undef TARGET_PROMOTE_PROTOTYPES
19060 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
19062 #undef TARGET_FUNCTION_VALUE
19063 #define TARGET_FUNCTION_VALUE mips_function_value
19064 #undef TARGET_LIBCALL_VALUE
19065 #define TARGET_LIBCALL_VALUE mips_libcall_value
19066 #undef TARGET_FUNCTION_VALUE_REGNO_P
19067 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
19068 #undef TARGET_RETURN_IN_MEMORY
19069 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
19070 #undef TARGET_RETURN_IN_MSB
19071 #define TARGET_RETURN_IN_MSB mips_return_in_msb
19073 #undef TARGET_ASM_OUTPUT_MI_THUNK
19074 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
19075 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
19076 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
19078 #undef TARGET_PRINT_OPERAND
19079 #define TARGET_PRINT_OPERAND mips_print_operand
19080 #undef TARGET_PRINT_OPERAND_ADDRESS
19081 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
19082 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
19083 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
19085 #undef TARGET_SETUP_INCOMING_VARARGS
19086 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
19087 #undef TARGET_STRICT_ARGUMENT_NAMING
19088 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
19089 #undef TARGET_MUST_PASS_IN_STACK
19090 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
19091 #undef TARGET_PASS_BY_REFERENCE
19092 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
19093 #undef TARGET_CALLEE_COPIES
19094 #define TARGET_CALLEE_COPIES mips_callee_copies
19095 #undef TARGET_ARG_PARTIAL_BYTES
19096 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
19097 #undef TARGET_FUNCTION_ARG
19098 #define TARGET_FUNCTION_ARG mips_function_arg
19099 #undef TARGET_FUNCTION_ARG_ADVANCE
19100 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
19101 #undef TARGET_FUNCTION_ARG_BOUNDARY
19102 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
19104 #undef TARGET_MODE_REP_EXTENDED
19105 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
19107 #undef TARGET_VECTOR_MODE_SUPPORTED_P
19108 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
19110 #undef TARGET_SCALAR_MODE_SUPPORTED_P
19111 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
19113 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
19114 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
19116 #undef TARGET_INIT_BUILTINS
19117 #define TARGET_INIT_BUILTINS mips_init_builtins
19118 #undef TARGET_BUILTIN_DECL
19119 #define TARGET_BUILTIN_DECL mips_builtin_decl
19120 #undef TARGET_EXPAND_BUILTIN
19121 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
19123 #undef TARGET_HAVE_TLS
19124 #define TARGET_HAVE_TLS HAVE_AS_TLS
19126 #undef TARGET_CANNOT_FORCE_CONST_MEM
19127 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
19129 #undef TARGET_LEGITIMATE_CONSTANT_P
19130 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
19132 #undef TARGET_ENCODE_SECTION_INFO
19133 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
19135 #undef TARGET_ATTRIBUTE_TABLE
19136 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
19137 /* All our function attributes are related to how out-of-line copies should
19138 be compiled or called. They don't in themselves prevent inlining. */
19139 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
19140 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
19142 #undef TARGET_EXTRA_LIVE_ON_ENTRY
19143 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
19145 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
19146 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
19147 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
19148 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
19150 #undef TARGET_COMP_TYPE_ATTRIBUTES
19151 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
19153 #ifdef HAVE_AS_DTPRELWORD
19154 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
19155 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
19157 #undef TARGET_DWARF_REGISTER_SPAN
19158 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
19160 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
19161 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
19163 #undef TARGET_LEGITIMATE_ADDRESS_P
19164 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
19166 #undef TARGET_FRAME_POINTER_REQUIRED
19167 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
19169 #undef TARGET_CAN_ELIMINATE
19170 #define TARGET_CAN_ELIMINATE mips_can_eliminate
19172 #undef TARGET_CONDITIONAL_REGISTER_USAGE
19173 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
19175 #undef TARGET_TRAMPOLINE_INIT
19176 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
19178 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
19179 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
19181 #undef TARGET_SHIFT_TRUNCATION_MASK
19182 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
19184 #undef TARGET_PREPARE_PCH_SAVE
19185 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
19187 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
19188 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
19190 #undef TARGET_CASE_VALUES_THRESHOLD
19191 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
19193 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
19194 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
19196 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
19197 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
19199 struct gcc_target targetm
= TARGET_INITIALIZER
;
19201 #include "gt-mips.h"