1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-95, 1996 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-flags.h"
37 #include "insn-attr.h"
38 #include "insn-codes.h"
42 #undef MAX /* sys/param.h may also define these */
47 #include <sys/types.h>
60 #if defined(USG) || defined(NO_STAB_H)
61 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
63 #include <stab.h> /* On BSD, use the system's stab.h. */
67 #define STAB_CODE_TYPE enum __stab_debug_code
69 #define STAB_CODE_TYPE int
74 extern char *getenv ();
75 extern char *mktemp ();
77 extern rtx
adj_offsettable_operand ();
78 extern rtx
copy_to_reg ();
81 extern tree
lookup_name ();
82 extern void pfatal_with_name ();
83 extern void warning ();
85 extern FILE *asm_out_file
;
87 /* Enumeration for all of the relational tests, so that we can build
88 arrays indexed by the test type, and not worry about the order
105 /* Global variables for machine-dependent things. */
107 /* Threshold for data being put into the small data/bss area, instead
108 of the normal data area (references to the small data/bss area take
109 1 instruction, and use the global pointer, references to the normal
110 data area takes 2 instructions). */
111 int mips_section_threshold
= -1;
113 /* Count the number of .file directives, so that .loc is up to date. */
114 int num_source_filenames
= 0;
116 /* Count the number of sdb related labels are generated (to find block
117 start and end boundaries). */
118 int sdb_label_count
= 0;
120 /* Next label # for each statement for Silicon Graphics IRIS systems. */
123 /* Non-zero if inside of a function, because the stupid MIPS asm can't
124 handle .files inside of functions. */
125 int inside_function
= 0;
127 /* Files to separate the text and the data output, so that all of the data
128 can be emitted before the text, which will mean that the assembler will
129 generate smaller code, based on the global pointer. */
130 FILE *asm_out_data_file
;
131 FILE *asm_out_text_file
;
133 /* Linked list of all externals that are to be emitted when optimizing
134 for the global pointer if they haven't been declared by the end of
135 the program with an appropriate .comm or initialization. */
138 struct extern_list
*next
; /* next external */
139 char *name
; /* name of the external */
140 int size
; /* size in bytes */
143 /* Name of the file containing the current function. */
144 char *current_function_file
= "";
146 /* Warning given that Mips ECOFF can't support changing files
147 within a function. */
148 int file_in_function_warning
= FALSE
;
150 /* Whether to suppress issuing .loc's because the user attempted
151 to change the filename within a function. */
152 int ignore_line_number
= FALSE
;
154 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
160 /* The next branch instruction is a branch likely, not branch normal. */
161 int mips_branch_likely
;
163 /* Count of delay slots and how many are filled. */
164 int dslots_load_total
;
165 int dslots_load_filled
;
166 int dslots_jump_total
;
167 int dslots_jump_filled
;
169 /* # of nops needed by previous insn */
170 int dslots_number_nops
;
172 /* Number of 1/2/3 word references to data items (ie, not jal's). */
175 /* registers to check for load delay */
176 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
178 /* Cached operands, and operator to compare for use in set/branch on
182 /* what type of branch to use */
183 enum cmp_type branch_type
;
185 /* Number of previously seen half-pic pointers and references. */
186 static int prev_half_pic_ptrs
= 0;
187 static int prev_half_pic_refs
= 0;
189 /* which cpu are we scheduling for */
190 enum processor_type mips_cpu
;
192 /* which instruction set architecture to use. */
195 #ifdef MIPS_ABI_DEFAULT
196 /* which ABI to use. This is defined to a constant in mips.h if the target
197 doesn't support multiple ABIs. */
198 enum mips_abi_type mips_abi
;
201 /* Strings to hold which cpu and instruction set architecture to use. */
202 char *mips_cpu_string
; /* for -mcpu=<xxx> */
203 char *mips_isa_string
; /* for -mips{1,2,3,4} */
204 char *mips_abi_string
; /* for -mabi={o32,32,n32,n64,64,eabi} */
206 /* If TRUE, we split addresses into their high and low parts in the RTL. */
207 int mips_split_addresses
;
209 /* Generating calls to position independent functions? */
210 enum mips_abicalls_type mips_abicalls
;
212 /* High and low marks for floating point values which we will accept
213 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
214 initialized in override_options. */
215 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
217 /* Array giving truth value on whether or not a given hard register
218 can support a given mode. */
219 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
221 /* Current frame information calculated by compute_frame_size. */
222 struct mips_frame_info current_frame_info
;
224 /* Zero structure to initialize current_frame_info. */
225 struct mips_frame_info zero_frame_info
;
227 /* Temporary filename used to buffer .text until end of program
229 static char *temp_filename
;
231 /* Pseudo-reg holding the address of the current function when
232 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
233 by mips_finalize_pic if it was created. */
234 rtx embedded_pic_fnaddr_rtx
;
236 /* List of all MIPS punctuation characters used by print_operand. */
237 char mips_print_operand_punct
[256];
239 /* Map GCC register number to debugger register number. */
240 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
242 /* Buffer to use to enclose a load/store operation with %{ %} to
243 turn on .set volatile. */
244 static char volatile_buffer
[60];
246 /* Hardware names for the registers. If -mrnames is used, this
247 will be overwritten with mips_sw_reg_names. */
249 char mips_reg_names
[][8] =
251 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
252 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
253 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
254 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
255 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
256 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
257 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
258 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
259 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
260 "$fcc5","$fcc6","$fcc7","$rap"
263 /* Mips software names for the registers, used to overwrite the
264 mips_reg_names array. */
266 char mips_sw_reg_names
[][8] =
268 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
269 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
270 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
271 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
272 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
273 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
274 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
275 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
276 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
277 "$fcc5","$fcc6","$fcc7","$rap"
280 /* Map hard register number to register class */
281 enum reg_class mips_regno_to_class
[] =
283 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
284 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
285 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
286 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
287 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
288 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
289 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
290 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
291 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
292 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
293 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
294 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
295 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
296 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
297 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
298 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
299 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
300 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
301 ST_REGS
, ST_REGS
, ST_REGS
, GR_REGS
304 /* Map register constraint character to register class. */
305 enum reg_class mips_char_to_class
[256] =
307 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
308 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
309 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
310 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
311 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
312 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
313 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
314 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
315 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
316 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
317 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
318 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
319 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
320 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
321 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
322 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
323 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
324 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
325 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
326 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
327 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
328 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
329 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
330 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
331 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
332 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
333 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
334 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
335 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
336 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
337 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
338 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
339 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
340 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
341 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
342 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
343 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
344 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
345 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
346 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
347 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
348 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
349 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
350 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
351 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
352 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
353 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
354 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
355 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
356 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
357 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
358 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
359 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
360 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
361 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
362 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
363 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
364 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
365 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
366 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
367 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
368 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
369 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
370 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
374 /* Return truth value of whether OP can be used as an operands
375 where a register or 16 bit unsigned integer is needed. */
378 uns_arith_operand (op
, mode
)
380 enum machine_mode mode
;
382 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
385 return register_operand (op
, mode
);
388 /* Return truth value of whether OP can be used as an operands
389 where a 16 bit integer is needed */
392 arith_operand (op
, mode
)
394 enum machine_mode mode
;
396 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
399 return register_operand (op
, mode
);
402 /* Return truth value of whether OP can be used as an operand in a two
403 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
406 arith32_operand (op
, mode
)
408 enum machine_mode mode
;
410 if (GET_CODE (op
) == CONST_INT
)
413 return register_operand (op
, mode
);
416 /* Return truth value of whether OP is a integer which fits in 16 bits */
421 enum machine_mode mode
;
423 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
426 /* Return truth value of whether OP is a 32 bit integer which is too big to
427 be loaded with one instruction. */
432 enum machine_mode mode
;
436 if (GET_CODE (op
) != CONST_INT
)
440 if ((value
& ~0x0000ffff) == 0) /* ior reg,$r0,value */
443 if (((unsigned long)(value
+ 32768)) <= 32767) /* subu reg,$r0,value */
446 if ((value
& 0x0000ffff) == 0) /* lui reg,value>>16 */
452 /* Return truth value of whether OP is a register or the constant 0. */
455 reg_or_0_operand (op
, mode
)
457 enum machine_mode mode
;
459 switch (GET_CODE (op
))
465 return (INTVAL (op
) == 0);
468 if (op
!= CONST0_RTX (mode
))
475 return register_operand (op
, mode
);
481 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
484 mips_const_double_ok (op
, mode
)
486 enum machine_mode mode
;
490 if (GET_CODE (op
) != CONST_DOUBLE
)
493 if (mode
== VOIDmode
)
496 if (mode
!= SFmode
&& mode
!= DFmode
)
499 if (op
== CONST0_RTX (mode
))
502 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
503 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
506 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
508 if (REAL_VALUE_ISNAN (d
))
511 if (REAL_VALUE_NEGATIVE (d
))
512 d
= REAL_VALUE_NEGATE (d
);
516 if (REAL_VALUES_LESS (d
, dfhigh
)
517 && REAL_VALUES_LESS (dflow
, d
))
522 if (REAL_VALUES_LESS (d
, sfhigh
)
523 && REAL_VALUES_LESS (sflow
, d
))
530 /* Accept the floating point constant 1 in the appropriate mode. */
533 const_float_1_operand (op
, mode
)
535 enum machine_mode mode
;
538 static REAL_VALUE_TYPE onedf
;
539 static REAL_VALUE_TYPE onesf
;
540 static int one_initialized
;
542 if (GET_CODE (op
) != CONST_DOUBLE
543 || mode
!= GET_MODE (op
)
544 || (mode
!= DFmode
&& mode
!= SFmode
))
547 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
549 /* We only initialize these values if we need them, since we will
550 never get called unless mips_isa >= 4. */
551 if (! one_initialized
)
553 onedf
= REAL_VALUE_ATOF ("1.0", DFmode
);
554 onesf
= REAL_VALUE_ATOF ("1.0", SFmode
);
555 one_initialized
= TRUE
;
559 return REAL_VALUES_EQUAL (d
, onedf
);
561 return REAL_VALUES_EQUAL (d
, onesf
);
564 /* Return truth value if a memory operand fits in a single instruction
565 (ie, register + small offset). */
568 simple_memory_operand (op
, mode
)
570 enum machine_mode mode
;
572 rtx addr
, plus0
, plus1
;
574 /* Eliminate non-memory operations */
575 if (GET_CODE (op
) != MEM
)
578 /* dword operations really put out 2 instructions, so eliminate them. */
579 /* ??? This isn't strictly correct. It is OK to accept multiword modes
580 here, since the length attributes are being set correctly, but only
581 if the address is offsettable. LO_SUM is not offsettable. */
582 if (GET_MODE_SIZE (GET_MODE (op
)) > UNITS_PER_WORD
)
585 /* Decode the address now. */
587 switch (GET_CODE (addr
))
597 return SMALL_INT (op
);
600 plus0
= XEXP (addr
, 0);
601 plus1
= XEXP (addr
, 1);
602 if (GET_CODE (plus0
) == REG
603 && GET_CODE (plus1
) == CONST_INT
604 && SMALL_INT (plus1
))
607 else if (GET_CODE (plus1
) == REG
608 && GET_CODE (plus0
) == CONST_INT
609 && SMALL_INT (plus0
))
616 /* We used to allow small symbol refs here (ie, stuff in .sdata
617 or .sbss), but this causes some bugs in G++. Also, it won't
618 interfere if the MIPS linker rewrites the store instruction
619 because the function is PIC. */
621 case LABEL_REF
: /* never gp relative */
625 /* If -G 0, we can never have a GP relative memory operation.
626 Also, save some time if not optimizing. */
631 rtx offset
= const0_rtx
;
632 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
633 if (GET_CODE (op
) != SYMBOL_REF
)
636 /* let's be paranoid.... */
637 if (! SMALL_INT (offset
))
643 return SYMBOL_REF_FLAG (addr
);
650 /* Return true if the code of this rtx pattern is EQ or NE. */
653 equality_op (op
, mode
)
655 enum machine_mode mode
;
657 if (mode
!= GET_MODE (op
))
660 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
663 /* Return true if the code is a relational operations (EQ, LE, etc.) */
668 enum machine_mode mode
;
670 if (mode
!= GET_MODE (op
))
673 return (GET_RTX_CLASS (GET_CODE (op
)) == '<');
676 /* Return true if the operand is either the PC or a label_ref. */
679 pc_or_label_operand (op
, mode
)
681 enum machine_mode mode
;
686 if (GET_CODE (op
) == LABEL_REF
)
692 /* Test for a valid operand for a call instruction.
693 Don't allow the arg pointer register or virtual regs
694 since they may change into reg + const, which the patterns
698 call_insn_operand (op
, mode
)
700 enum machine_mode mode
;
702 if (CONSTANT_ADDRESS_P (op
)
703 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
704 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
705 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)))
710 /* Return true if OPERAND is valid as a source operand for a move
714 move_operand (op
, mode
)
716 enum machine_mode mode
;
718 return (general_operand (op
, mode
)
719 && ! (mips_split_addresses
&& mips_check_split (op
, mode
)));
722 /* Return true if OPERAND is valid as a source operand for movdi.
723 This accepts not only general_operand, but also sign extended
724 constants and registers. We need to accept sign extended constants
725 in case a sign extended register which is used in an expression,
726 and is equivalent to a constant, is spilled. */
729 movdi_operand (op
, mode
)
731 enum machine_mode mode
;
735 && GET_CODE (op
) == SIGN_EXTEND
736 && GET_MODE (op
) == DImode
737 && (GET_MODE (XEXP (op
, 0)) == SImode
738 || (GET_CODE (XEXP (op
, 0)) == CONST_INT
739 && GET_MODE (XEXP (op
, 0)) == VOIDmode
))
740 && (register_operand (XEXP (op
, 0), SImode
)
741 || immediate_operand (XEXP (op
, 0), SImode
)))
744 return general_operand (op
, mode
);
747 /* Like register_operand, but when in 64 bit mode also accept a sign
748 extend of a 32 bit register, since the value is known to be already
752 se_register_operand (op
, mode
)
754 enum machine_mode mode
;
758 && GET_CODE (op
) == SIGN_EXTEND
759 && GET_MODE (op
) == DImode
760 && GET_MODE (XEXP (op
, 0)) == SImode
761 && register_operand (XEXP (op
, 0), SImode
))
764 return register_operand (op
, mode
);
767 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
768 extend of a 32 bit register, since the value is known to be already
772 se_reg_or_0_operand (op
, mode
)
774 enum machine_mode mode
;
778 && GET_CODE (op
) == SIGN_EXTEND
779 && GET_MODE (op
) == DImode
780 && GET_MODE (XEXP (op
, 0)) == SImode
781 && register_operand (XEXP (op
, 0), SImode
))
784 return reg_or_0_operand (op
, mode
);
787 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
788 extend of a 32 bit register, since the value is known to be already
792 se_uns_arith_operand (op
, mode
)
794 enum machine_mode mode
;
798 && GET_CODE (op
) == SIGN_EXTEND
799 && GET_MODE (op
) == DImode
800 && GET_MODE (XEXP (op
, 0)) == SImode
801 && register_operand (XEXP (op
, 0), SImode
))
804 return uns_arith_operand (op
, mode
);
807 /* Like arith_operand, but when in 64 bit mode also accept a sign
808 extend of a 32 bit register, since the value is known to be already
812 se_arith_operand (op
, mode
)
814 enum machine_mode mode
;
818 && GET_CODE (op
) == SIGN_EXTEND
819 && GET_MODE (op
) == DImode
820 && GET_MODE (XEXP (op
, 0)) == SImode
821 && register_operand (XEXP (op
, 0), SImode
))
824 return arith_operand (op
, mode
);
827 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
828 extend of a 32 bit register, since the value is known to be already
832 se_nonmemory_operand (op
, mode
)
834 enum machine_mode mode
;
838 && GET_CODE (op
) == SIGN_EXTEND
839 && GET_MODE (op
) == DImode
840 && GET_MODE (XEXP (op
, 0)) == SImode
841 && register_operand (XEXP (op
, 0), SImode
))
844 return nonmemory_operand (op
, mode
);
847 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
848 sign extend of a 32 bit register, since the value is known to be
849 already sign extended. */
852 se_nonimmediate_operand (op
, mode
)
854 enum machine_mode mode
;
858 && GET_CODE (op
) == SIGN_EXTEND
859 && GET_MODE (op
) == DImode
860 && GET_MODE (XEXP (op
, 0)) == SImode
861 && register_operand (XEXP (op
, 0), SImode
))
864 return nonimmediate_operand (op
, mode
);
867 /* Return true if we split the address into high and low parts. */
869 /* ??? We should also handle reg+array somewhere. We get four
870 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
871 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
872 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
873 out of the address, then we have 4 instructions to combine. Perhaps
874 add a 3->2 define_split for combine. */
876 /* ??? We could also split a CONST_INT here if it is a large_int().
877 However, it doesn't seem to be very useful to have %hi(constant).
878 We would be better off by doing the masking ourselves and then putting
879 the explicit high part of the constant in the RTL. This will give better
880 optimization. Also, %hi(constant) needs assembler changes to work.
881 There is already a define_split that does this. */
884 mips_check_split (address
, mode
)
886 enum machine_mode mode
;
888 /* ??? This is the same check used in simple_memory_operand.
889 We use it here because LO_SUM is not offsettable. */
890 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
893 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
894 || (GET_CODE (address
) == CONST
895 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
896 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
897 || GET_CODE (address
) == LABEL_REF
)
903 /* Returns an operand string for the given instruction's delay slot,
904 after updating filled delay slot statistics.
906 We assume that operands[0] is the target register that is set.
908 In order to check the next insn, most of this functionality is moved
909 to FINAL_PRESCAN_INSN, and we just set the global variables that
912 /* ??? This function no longer does anything useful, because final_prescan_insn
913 now will never emit a nop. */
916 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
917 char *ret
; /* normal string to return */
918 enum delay_type type
; /* type of delay */
919 rtx operands
[]; /* operands to use */
920 rtx cur_insn
; /* current insn */
922 register rtx set_reg
;
923 register enum machine_mode mode
;
924 register rtx next_insn
= (cur_insn
) ? NEXT_INSN (cur_insn
) : (rtx
)0;
925 register int num_nops
;
927 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
930 else if (type
== DELAY_HILO
)
936 /* Make sure that we don't put nop's after labels. */
937 next_insn
= NEXT_INSN (cur_insn
);
938 while (next_insn
!= (rtx
)0 && GET_CODE (next_insn
) == NOTE
)
939 next_insn
= NEXT_INSN (next_insn
);
941 dslots_load_total
+= num_nops
;
942 if (TARGET_DEBUG_F_MODE
944 || type
== DELAY_NONE
945 || operands
== (rtx
*)0
946 || cur_insn
== (rtx
)0
947 || next_insn
== (rtx
)0
948 || GET_CODE (next_insn
) == CODE_LABEL
949 || (set_reg
= operands
[0]) == (rtx
)0)
951 dslots_number_nops
= 0;
952 mips_load_reg
= (rtx
)0;
953 mips_load_reg2
= (rtx
)0;
954 mips_load_reg3
= (rtx
)0;
955 mips_load_reg4
= (rtx
)0;
959 set_reg
= operands
[0];
960 if (set_reg
== (rtx
)0)
963 while (GET_CODE (set_reg
) == SUBREG
)
964 set_reg
= SUBREG_REG (set_reg
);
966 mode
= GET_MODE (set_reg
);
967 dslots_number_nops
= num_nops
;
968 mips_load_reg
= set_reg
;
969 if (GET_MODE_SIZE (mode
)
970 > (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
971 mips_load_reg2
= gen_rtx (REG
, SImode
, REGNO (set_reg
) + 1);
975 if (type
== DELAY_HILO
)
977 mips_load_reg3
= gen_rtx (REG
, SImode
, MD_REG_FIRST
);
978 mips_load_reg4
= gen_rtx (REG
, SImode
, MD_REG_FIRST
+1);
990 /* Determine whether a memory reference takes one (based off of the GP pointer),
991 two (normal), or three (label + reg) instructions, and bump the appropriate
992 counter for -mstats. */
995 mips_count_memory_refs (op
, num
)
1001 rtx addr
, plus0
, plus1
;
1002 enum rtx_code code0
, code1
;
1005 if (TARGET_DEBUG_B_MODE
)
1007 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
1011 /* Skip MEM if passed, otherwise handle movsi of address. */
1012 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
1014 /* Loop, going through the address RTL */
1018 switch (GET_CODE (addr
))
1029 plus0
= XEXP (addr
, 0);
1030 plus1
= XEXP (addr
, 1);
1031 code0
= GET_CODE (plus0
);
1032 code1
= GET_CODE (plus1
);
1042 if (code0
== CONST_INT
)
1057 if (code1
== CONST_INT
)
1064 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
1071 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
1081 n_words
= 2; /* always 2 words */
1085 addr
= XEXP (addr
, 0);
1090 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1099 n_words
+= additional
;
1103 num_refs
[n_words
-1] += num
;
1107 /* Return RTL for the offset from the current function to the
1111 embedded_pic_offset (x
)
1114 if (embedded_pic_fnaddr_rtx
== NULL
)
1118 embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
1120 /* Output code at function start to initialize the pseudo-reg. */
1121 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1122 inline functions, because it is called after RTL for the function
1123 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1124 does not get copied, and ends up not matching the rest of the RTL.
1125 This solution works, but means that we get unnecessary code to
1126 initialize this value every time a function is inlined into another
1129 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx
,
1130 XEXP (DECL_RTL (current_function_decl
), 0)));
1131 seq
= gen_sequence ();
1133 push_topmost_sequence ();
1134 emit_insn_after (seq
, get_insns ());
1135 pop_topmost_sequence ();
1138 return gen_rtx (CONST
, Pmode
,
1139 gen_rtx (MINUS
, Pmode
, x
,
1140 XEXP (DECL_RTL (current_function_decl
), 0)));
1143 /* Return the appropriate instructions to move one operand to another. */
1146 mips_move_1word (operands
, insn
, unsignedp
)
1152 rtx op0
= operands
[0];
1153 rtx op1
= operands
[1];
1154 enum rtx_code code0
= GET_CODE (op0
);
1155 enum rtx_code code1
= GET_CODE (op1
);
1156 enum machine_mode mode
= GET_MODE (op0
);
1157 int subreg_word0
= 0;
1158 int subreg_word1
= 0;
1159 enum delay_type delay
= DELAY_NONE
;
1161 while (code0
== SUBREG
)
1163 subreg_word0
+= SUBREG_WORD (op0
);
1164 op0
= SUBREG_REG (op0
);
1165 code0
= GET_CODE (op0
);
1168 while (code1
== SUBREG
)
1170 subreg_word1
+= SUBREG_WORD (op1
);
1171 op1
= SUBREG_REG (op1
);
1172 code1
= GET_CODE (op1
);
1175 /* For our purposes, a condition code mode is the same as SImode. */
1181 int regno0
= REGNO (op0
) + subreg_word0
;
1185 int regno1
= REGNO (op1
) + subreg_word1
;
1187 /* Just in case, don't do anything for assigning a register
1188 to itself, unless we are filling a delay slot. */
1189 if (regno0
== regno1
&& set_nomacro
== 0)
1192 else if (GP_REG_P (regno0
))
1194 if (GP_REG_P (regno1
))
1195 ret
= "move\t%0,%1";
1197 else if (MD_REG_P (regno1
))
1200 if (regno1
!= HILO_REGNUM
)
1206 else if (ST_REG_P (regno1
) && mips_isa
>= 4)
1207 ret
= "li\t%0,1\n\tmovf\t%0,%.,%1";
1212 if (FP_REG_P (regno1
))
1213 ret
= "mfc1\t%0,%1";
1215 else if (regno1
== FPSW_REGNUM
&& mips_isa
< 4)
1216 ret
= "cfc1\t%0,$31";
1220 else if (FP_REG_P (regno0
))
1222 if (GP_REG_P (regno1
))
1225 ret
= "mtc1\t%1,%0";
1228 if (FP_REG_P (regno1
))
1229 ret
= "mov.s\t%0,%1";
1232 else if (MD_REG_P (regno0
))
1234 if (GP_REG_P (regno1
))
1237 if (regno0
!= HILO_REGNUM
)
1242 else if (regno0
== FPSW_REGNUM
&& mips_isa
< 4)
1244 if (GP_REG_P (regno1
))
1247 ret
= "ctc1\t%0,$31";
1252 else if (code1
== MEM
)
1257 mips_count_memory_refs (op1
, 1);
1259 if (GP_REG_P (regno0
))
1261 /* For loads, use the mode of the memory item, instead of the
1262 target, so zero/sign extend can use this code as well. */
1263 switch (GET_MODE (op1
))
1272 ret
= ((unsignedp
&& TARGET_64BIT
)
1277 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
1280 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
1285 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
1288 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1290 int i
= strlen (ret
);
1291 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1294 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1295 ret
= volatile_buffer
;
1299 else if (code1
== CONST_INT
1300 || (code1
== CONST_DOUBLE
1301 && GET_MODE (op1
) == VOIDmode
))
1303 if (code1
== CONST_DOUBLE
)
1305 /* This can happen when storing constants into long long
1306 bitfields. Just store the least significant word of
1308 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
1311 if (INTVAL (op1
) == 0)
1313 if (GP_REG_P (regno0
))
1314 ret
= "move\t%0,%z1";
1316 else if (FP_REG_P (regno0
))
1319 ret
= "mtc1\t%z1,%0";
1322 else if (MD_REG_P (regno0
))
1329 else if (GP_REG_P (regno0
))
1330 /* Don't use X format, because that will give out of range
1331 numbers for 64 bit host and 32 bit target. */
1332 ret
= "li\t%0,%1\t\t\t# %X1";
1335 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
1337 if (op1
== CONST0_RTX (SFmode
))
1339 if (GP_REG_P (regno0
))
1340 ret
= "move\t%0,%.";
1342 else if (FP_REG_P (regno0
))
1345 ret
= "mtc1\t%.,%0";
1352 ret
= "li.s\t%0,%1";
1356 else if (code1
== LABEL_REF
)
1359 mips_count_memory_refs (op1
, 1);
1364 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
1366 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
1368 rtx offset
= const0_rtx
;
1370 if (GET_CODE (op1
) == CONST
)
1371 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
1373 if (GET_CODE (op1
) == SYMBOL_REF
)
1375 operands
[2] = HALF_PIC_PTR (op1
);
1378 mips_count_memory_refs (operands
[2], 1);
1380 if (INTVAL (offset
) == 0)
1383 ret
= (unsignedp
&& TARGET_64BIT
1389 dslots_load_total
++;
1390 operands
[3] = offset
;
1391 if (unsignedp
&& TARGET_64BIT
)
1392 ret
= (SMALL_INT (offset
))
1393 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1394 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1396 ret
= (SMALL_INT (offset
))
1397 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1398 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1405 mips_count_memory_refs (op1
, 1);
1411 else if (code1
== PLUS
)
1413 rtx add_op0
= XEXP (op1
, 0);
1414 rtx add_op1
= XEXP (op1
, 1);
1416 if (GET_CODE (XEXP (op1
, 1)) == REG
&& GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
1418 add_op0
= XEXP (op1
, 1); /* reverse operands */
1419 add_op1
= XEXP (op1
, 0);
1422 operands
[2] = add_op0
;
1423 operands
[3] = add_op1
;
1424 ret
= "add%:\t%0,%2,%3";
1427 else if (code1
== HIGH
)
1429 operands
[1] = XEXP (op1
, 0);
1430 ret
= "lui\t%0,%%hi(%1)";
1434 else if (code0
== MEM
)
1437 mips_count_memory_refs (op0
, 1);
1441 int regno1
= REGNO (op1
) + subreg_word1
;
1443 if (GP_REG_P (regno1
))
1448 case SFmode
: ret
= "sw\t%1,%0"; break;
1449 case SImode
: ret
= "sw\t%1,%0"; break;
1450 case HImode
: ret
= "sh\t%1,%0"; break;
1451 case QImode
: ret
= "sb\t%1,%0"; break;
1455 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
1459 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1464 case SFmode
: ret
= "sw\t%z1,%0"; break;
1465 case SImode
: ret
= "sw\t%z1,%0"; break;
1466 case HImode
: ret
= "sh\t%z1,%0"; break;
1467 case QImode
: ret
= "sb\t%z1,%0"; break;
1471 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
1476 case SFmode
: ret
= "sw\t%.,%0"; break;
1477 case SImode
: ret
= "sw\t%.,%0"; break;
1478 case HImode
: ret
= "sh\t%.,%0"; break;
1479 case QImode
: ret
= "sb\t%.,%0"; break;
1483 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1485 int i
= strlen (ret
);
1486 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1489 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1490 ret
= volatile_buffer
;
1494 if (ret
== (char *)0)
1496 abort_with_insn (insn
, "Bad move");
1500 if (delay
!= DELAY_NONE
)
1501 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1507 /* Return the appropriate instructions to move 2 words */
1510 mips_move_2words (operands
, insn
)
1515 rtx op0
= operands
[0];
1516 rtx op1
= operands
[1];
1517 enum rtx_code code0
= GET_CODE (operands
[0]);
1518 enum rtx_code code1
= GET_CODE (operands
[1]);
1519 int subreg_word0
= 0;
1520 int subreg_word1
= 0;
1521 enum delay_type delay
= DELAY_NONE
;
1523 while (code0
== SUBREG
)
1525 subreg_word0
+= SUBREG_WORD (op0
);
1526 op0
= SUBREG_REG (op0
);
1527 code0
= GET_CODE (op0
);
1530 if (code1
== SIGN_EXTEND
)
1532 op1
= XEXP (op1
, 0);
1533 code1
= GET_CODE (op1
);
1536 while (code1
== SUBREG
)
1538 subreg_word1
+= SUBREG_WORD (op1
);
1539 op1
= SUBREG_REG (op1
);
1540 code1
= GET_CODE (op1
);
1544 if (GET_CODE (operands
[1]) == SIGN_EXTEND
1546 && code1
!= CONST_INT
1547 /* The following three can happen as the result of a questionable
1549 && code1
!= LABEL_REF
1550 && code1
!= SYMBOL_REF
1556 int regno0
= REGNO (op0
) + subreg_word0
;
1560 int regno1
= REGNO (op1
) + subreg_word1
;
1562 /* Just in case, don't do anything for assigning a register
1563 to itself, unless we are filling a delay slot. */
1564 if (regno0
== regno1
&& set_nomacro
== 0)
1567 else if (FP_REG_P (regno0
))
1569 if (FP_REG_P (regno1
))
1570 ret
= "mov.d\t%0,%1";
1578 abort_with_insn (insn
, "Bad move");
1579 #ifdef TARGET_FP_CALL_32
1580 if (FP_CALL_GP_REG_P (regno1
))
1581 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1584 ret
= "dmtc1\t%1,%0";
1587 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1591 else if (FP_REG_P (regno1
))
1597 abort_with_insn (insn
, "Bad move");
1598 #ifdef TARGET_FP_CALL_32
1599 if (FP_CALL_GP_REG_P (regno0
))
1600 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1603 ret
= "dmfc1\t%0,%1";
1606 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1609 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
))
1614 if (regno0
!= HILO_REGNUM
)
1616 else if (regno1
== 0)
1617 ret
= "mtlo\t%.\n\tmthi\t%.";
1620 ret
= "mthi\t%M1\n\tmtlo\t%L1";
1623 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
1628 if (regno1
!= HILO_REGNUM
)
1632 ret
= "mfhi\t%M0\n\tmflo\t%L0";
1635 else if (TARGET_64BIT
)
1636 ret
= "move\t%0,%1";
1638 else if (regno0
!= (regno1
+1))
1639 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
1642 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
1645 else if (code1
== CONST_DOUBLE
)
1647 /* Move zero from $0 unless !TARGET_64BIT and recipient
1648 is 64-bit fp reg, in which case generate a constant. */
1649 if (op1
!= CONST0_RTX (GET_MODE (op1
))
1650 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
1652 if (GET_MODE (op1
) == DFmode
)
1655 #ifdef TARGET_FP_CALL_32
1656 if (FP_CALL_GP_REG_P (regno0
))
1658 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
1660 split_double (op1
, operands
+ 2, operands
+ 3);
1661 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1664 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1668 ret
= "li.d\t%0,%1";
1671 else if (TARGET_64BIT
)
1676 split_double (op1
, operands
+ 2, operands
+ 3);
1677 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1683 if (GP_REG_P (regno0
))
1685 #ifdef TARGET_FP_CALL_32
1686 && ! FP_CALL_GP_REG_P (regno0
)
1690 : "move\t%0,%.\n\tmove\t%D0,%.";
1692 else if (FP_REG_P (regno0
))
1695 ret
= (TARGET_64BIT
)
1697 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1702 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1704 if (GP_REG_P (regno0
))
1705 ret
= (TARGET_64BIT
)
1707 : "move\t%0,%.\n\tmove\t%D0,%.";
1709 else if (FP_REG_P (regno0
))
1712 ret
= (TARGET_64BIT
)
1716 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1718 else if (MD_REG_P (regno0
))
1721 if (regno0
!= HILO_REGNUM
)
1724 ret
= "mtlo\t%.\n\tmthi\t%.";
1728 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
&& GP_REG_P (regno0
))
1732 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
1733 ret
= "li\t%0,%1\t\t# %X1";
1734 else if (HOST_BITS_PER_WIDE_INT
< 64)
1735 /* We can't use 'X' for negative numbers, because then we won't
1736 get the right value for the upper 32 bits. */
1737 ret
= ((INTVAL (op1
) < 0) ? "dli\t%0,%1\t\t\t# %X1"
1738 : "dli\t%0,%X1\t\t# %1");
1740 /* We must use 'X', because otherwise LONG_MIN will print as
1741 a number that the assembler won't accept. */
1742 ret
= "dli\t%0,%X1\t\t# %1";
1744 else if (HOST_BITS_PER_WIDE_INT
< 64)
1746 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
1747 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1751 /* We use multiple shifts here, to avoid warnings about out
1752 of range shifts on 32 bit hosts. */
1753 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
1754 operands
[1] = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
1755 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1759 else if (code1
== MEM
)
1764 mips_count_memory_refs (op1
, 2);
1766 if (FP_REG_P (regno0
))
1769 else if (TARGET_64BIT
)
1771 #ifdef TARGET_FP_CALL_32
1772 if (FP_CALL_GP_REG_P (regno0
))
1774 if (offsettable_address_p (FALSE
, SImode
, op1
))
1775 ret
= "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1777 ret
= "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1784 else if (offsettable_address_p (1, DFmode
, XEXP (op1
, 0)))
1786 operands
[2] = adj_offsettable_operand (op1
, 4);
1787 if (reg_mentioned_p (op0
, op1
))
1788 ret
= "lw\t%D0,%2\n\tlw\t%0,%1";
1790 ret
= "lw\t%0,%1\n\tlw\t%D0,%2";
1793 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1795 int i
= strlen (ret
);
1796 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1799 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1800 ret
= volatile_buffer
;
1804 else if (code1
== LABEL_REF
1805 || code1
== SYMBOL_REF
1809 mips_count_memory_refs (op1
, 2);
1811 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
1812 /* We deliberately remove the 'a' from '%1', so that we don't
1813 have to add SIGN_EXTEND support to print_operand_address.
1814 print_operand will just call print_operand_address in this
1815 case, so there is no problem. */
1818 ret
= "dla\t%0,%a1";
1822 else if (code0
== MEM
)
1826 int regno1
= REGNO (op1
) + subreg_word1
;
1828 if (FP_REG_P (regno1
))
1831 else if (TARGET_64BIT
)
1833 #ifdef TARGET_FP_CALL_32
1834 if (FP_CALL_GP_REG_P (regno1
))
1835 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1841 else if (offsettable_address_p (1, DFmode
, XEXP (op0
, 0)))
1843 operands
[2] = adj_offsettable_operand (op0
, 4);
1844 ret
= "sw\t%1,%0\n\tsw\t%D1,%2";
1848 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
1849 || (code1
== CONST_DOUBLE
1850 && op1
== CONST0_RTX (GET_MODE (op1
))))
1852 || offsettable_address_p (1, DFmode
, XEXP (op0
, 0))))
1858 operands
[2] = adj_offsettable_operand (op0
, 4);
1859 ret
= "sw\t%.,%0\n\tsw\t%.,%2";
1864 mips_count_memory_refs (op0
, 2);
1866 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1868 int i
= strlen (ret
);
1869 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1872 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1873 ret
= volatile_buffer
;
1877 if (ret
== (char *)0)
1879 abort_with_insn (insn
, "Bad move");
1883 if (delay
!= DELAY_NONE
)
1884 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1890 /* Provide the costs of an addressing mode that contains ADDR.
1891 If ADDR is not a valid address, its cost is irrelevant. */
1894 mips_address_cost (addr
)
1897 switch (GET_CODE (addr
))
1910 rtx offset
= const0_rtx
;
1911 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
1912 if (GET_CODE (addr
) == LABEL_REF
)
1915 if (GET_CODE (addr
) != SYMBOL_REF
)
1918 if (! SMALL_INT (offset
))
1924 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1928 register rtx plus0
= XEXP (addr
, 0);
1929 register rtx plus1
= XEXP (addr
, 1);
1931 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1933 plus0
= XEXP (addr
, 1);
1934 plus1
= XEXP (addr
, 0);
1937 if (GET_CODE (plus0
) != REG
)
1940 switch (GET_CODE (plus1
))
1946 return (SMALL_INT (plus1
) ? 1 : 2);
1953 return mips_address_cost (plus1
) + 1;
1961 /* Return true if X is an address which needs a temporary register when
1962 reloaded while generating PIC code. */
1965 pic_address_needs_scratch (x
)
1968 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1969 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1970 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1971 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1972 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1978 /* Make normal rtx_code into something we can index from an array */
1980 static enum internal_test
1981 map_test_to_internal_test (test_code
)
1982 enum rtx_code test_code
;
1984 enum internal_test test
= ITEST_MAX
;
1989 case EQ
: test
= ITEST_EQ
; break;
1990 case NE
: test
= ITEST_NE
; break;
1991 case GT
: test
= ITEST_GT
; break;
1992 case GE
: test
= ITEST_GE
; break;
1993 case LT
: test
= ITEST_LT
; break;
1994 case LE
: test
= ITEST_LE
; break;
1995 case GTU
: test
= ITEST_GTU
; break;
1996 case GEU
: test
= ITEST_GEU
; break;
1997 case LTU
: test
= ITEST_LTU
; break;
1998 case LEU
: test
= ITEST_LEU
; break;
2005 /* Generate the code to compare two integer values. The return value is:
2006 (reg:SI xx) The pseudo register the comparison is in
2007 (rtx)0 No register, generate a simple branch.
2009 ??? This is called with result nonzero by the Scond patterns in
2010 mips.md. These patterns are called with a target in the mode of
2011 the Scond instruction pattern. Since this must be a constant, we
2012 must use SImode. This means that if RESULT is non-zero, it will
2013 always be an SImode register, even if TARGET_64BIT is true. We
2014 cope with this by calling convert_move rather than emit_move_insn.
2015 This will sometimes lead to an unnecessary extension of the result;
2027 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
2028 enum rtx_code test_code
; /* relational test (EQ, etc) */
2029 rtx result
; /* result to store comp. or 0 if branch */
2030 rtx cmp0
; /* first operand to compare */
2031 rtx cmp1
; /* second operand to compare */
2032 int *p_invert
; /* NULL or ptr to hold whether branch needs */
2033 /* to reverse its test */
2036 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
2037 int const_low
; /* low bound of constant we can accept */
2038 int const_high
; /* high bound of constant we can accept */
2039 int const_add
; /* constant to add (convert LE -> LT) */
2040 int reverse_regs
; /* reverse registers in test */
2041 int invert_const
; /* != 0 if invert value if cmp1 is constant */
2042 int invert_reg
; /* != 0 if invert value if cmp1 is register */
2043 int unsignedp
; /* != 0 for unsigned comparisons. */
2046 static struct cmp_info info
[ (int)ITEST_MAX
] = {
2048 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2049 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2050 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2051 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2052 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2053 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2054 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2055 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2056 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2057 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2060 enum internal_test test
;
2061 enum machine_mode mode
;
2062 struct cmp_info
*p_info
;
2069 test
= map_test_to_internal_test (test_code
);
2070 if (test
== ITEST_MAX
)
2073 p_info
= &info
[ (int)test
];
2074 eqne_p
= (p_info
->test_code
== XOR
);
2076 mode
= GET_MODE (cmp0
);
2077 if (mode
== VOIDmode
)
2078 mode
= GET_MODE (cmp1
);
2080 /* Eliminate simple branches */
2081 branch_p
= (result
== (rtx
)0);
2084 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
2086 /* Comparisons against zero are simple branches */
2087 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
2090 /* Test for beq/bne. */
2095 /* allocate a pseudo to calculate the value in. */
2096 result
= gen_reg_rtx (mode
);
2099 /* Make sure we can handle any constants given to us. */
2100 if (GET_CODE (cmp0
) == CONST_INT
)
2101 cmp0
= force_reg (mode
, cmp0
);
2103 if (GET_CODE (cmp1
) == CONST_INT
)
2105 HOST_WIDE_INT value
= INTVAL (cmp1
);
2106 if (value
< p_info
->const_low
2107 || value
> p_info
->const_high
2108 /* ??? Why? And why wasn't the similar code below modified too? */
2110 && HOST_BITS_PER_WIDE_INT
< 64
2111 && p_info
->const_add
!= 0
2112 && ((p_info
->unsignedp
2113 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
2115 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
2116 != (p_info
->const_add
> 0))))
2117 cmp1
= force_reg (mode
, cmp1
);
2120 /* See if we need to invert the result. */
2121 invert
= (GET_CODE (cmp1
) == CONST_INT
)
2122 ? p_info
->invert_const
2123 : p_info
->invert_reg
;
2125 if (p_invert
!= (int *)0)
2131 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2132 Comparison between two registers, may involve switching operands. */
2133 if (GET_CODE (cmp1
) == CONST_INT
)
2135 if (p_info
->const_add
!= 0)
2137 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
2138 /* If modification of cmp1 caused overflow,
2139 we would get the wrong answer if we follow the usual path;
2140 thus, x > 0xffffffffU would turn into x > 0U. */
2141 if ((p_info
->unsignedp
2142 ? (unsigned HOST_WIDE_INT
) new > INTVAL (cmp1
)
2143 : new > INTVAL (cmp1
))
2144 != (p_info
->const_add
> 0))
2146 /* This test is always true, but if INVERT is true then
2147 the result of the test needs to be inverted so 0 should
2148 be returned instead. */
2149 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
2153 cmp1
= GEN_INT (new);
2156 else if (p_info
->reverse_regs
)
2163 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
2167 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
2168 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
2171 if (test
== ITEST_NE
)
2173 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
2177 else if (test
== ITEST_EQ
)
2179 reg2
= (invert
) ? gen_reg_rtx (mode
) : result
;
2180 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
2185 convert_move (result
, gen_rtx (XOR
, mode
, reg
, const1_rtx
), 0);
2191 /* Emit the common code for doing conditional branches.
2192 operand[0] is the label to jump to.
2193 The comparison operands are saved away by cmp{si,di,sf,df}. */
2196 gen_conditional_branch (operands
, test_code
)
2198 enum rtx_code test_code
;
2200 enum cmp_type type
= branch_type
;
2201 rtx cmp0
= branch_cmp
[0];
2202 rtx cmp1
= branch_cmp
[1];
2203 enum machine_mode mode
;
2211 abort_with_insn (gen_rtx (test_code
, VOIDmode
, cmp0
, cmp1
), "bad test");
2215 mode
= type
== CMP_SI
? SImode
: DImode
;
2217 reg
= gen_int_relational (test_code
, NULL_RTX
, cmp0
, cmp1
, &invert
);
2224 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
2226 /* We don't want to build a comparison against a non-zero
2228 cmp1
= force_reg (mode
, cmp1
);
2235 reg
= gen_rtx (REG
, CCmode
, FPSW_REGNUM
);
2237 reg
= gen_reg_rtx (CCmode
);
2239 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2240 0 in the instruction built below. The MIPS FPU handles
2241 inequality testing by testing for equality and looking for a
2243 emit_insn (gen_rtx (SET
, VOIDmode
,
2245 gen_rtx (test_code
== NE
? EQ
: test_code
,
2246 CCmode
, cmp0
, cmp1
)));
2248 test_code
= test_code
== NE
? EQ
: NE
;
2256 /* Generate the branch. */
2258 label1
= gen_rtx (LABEL_REF
, VOIDmode
, operands
[0]);
2267 emit_jump_insn (gen_rtx (SET
, VOIDmode
,
2269 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
2270 gen_rtx (test_code
, mode
, cmp0
, cmp1
),
2275 /* Emit the common code for conditional moves. OPERANDS is the array
2276 of operands passed to the conditional move defined_expand. */
2279 gen_conditional_move (operands
)
2282 rtx op0
= branch_cmp
[0];
2283 rtx op1
= branch_cmp
[1];
2284 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
2285 enum rtx_code cmp_code
= GET_CODE (operands
[1]);
2286 enum rtx_code move_code
= NE
;
2287 enum machine_mode op_mode
= GET_MODE (operands
[0]);
2288 enum machine_mode cmp_mode
;
2291 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
2310 op0
= force_reg (mode
, branch_cmp
[1]);
2311 op1
= branch_cmp
[0];
2315 op0
= force_reg (mode
, branch_cmp
[1]);
2316 op1
= branch_cmp
[0];
2327 op0
= force_reg (mode
, branch_cmp
[1]);
2328 op1
= branch_cmp
[0];
2332 op0
= force_reg (mode
, branch_cmp
[1]);
2333 op1
= branch_cmp
[0];
2349 if (mode
== SImode
|| mode
== DImode
)
2351 else if (mode
== SFmode
|| mode
== DFmode
)
2356 cmp_reg
= gen_reg_rtx (cmp_mode
);
2357 emit_insn (gen_rtx (SET
, cmp_mode
,
2359 gen_rtx (cmp_code
, cmp_mode
, op0
, op1
)));
2360 emit_insn (gen_rtx (SET
, op_mode
,
2362 gen_rtx (IF_THEN_ELSE
, op_mode
,
2363 gen_rtx (move_code
, VOIDmode
,
2365 CONST0_RTX (SImode
)),
2370 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2376 temp<last> = src[MAX_MOVE_REGS-1];
2380 dest[MAX_MOVE_REGS-1] = temp<last>;
2381 src += MAX_MOVE_REGS;
2382 dest += MAX_MOVE_REGS;
2383 } while (src != final);
2385 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2386 registers are needed.
2388 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2389 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2390 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2392 #define MAX_MOVE_REGS 4
2393 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2396 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
)
2397 rtx dest_reg
; /* register holding destination address */
2398 rtx src_reg
; /* register holding source address */
2399 int bytes
; /* # bytes to move */
2400 int align
; /* alignment */
2401 rtx orig_dest
; /* original dest for change_address */
2402 rtx orig_src
; /* original source for making a reg note */
2404 rtx dest_mem
= change_address (orig_dest
, BLKmode
, dest_reg
);
2405 rtx src_mem
= change_address (orig_src
, BLKmode
, src_reg
);
2406 rtx align_rtx
= GEN_INT (align
);
2412 if (bytes
< 2*MAX_MOVE_BYTES
)
2415 leftover
= bytes
% MAX_MOVE_BYTES
;
2418 label
= gen_label_rtx ();
2419 final_src
= gen_reg_rtx (Pmode
);
2420 bytes_rtx
= GEN_INT (bytes
);
2426 emit_insn (gen_movdi (final_src
, bytes_rtx
));
2427 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
2431 emit_insn (gen_movsi (final_src
, bytes_rtx
));
2432 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2438 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
2440 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
2445 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
2446 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
2449 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
2450 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
2451 emit_insn (gen_cmpdi (src_reg
, final_src
));
2455 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
2456 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
2457 emit_insn (gen_cmpsi (src_reg
, final_src
));
2459 emit_jump_insn (gen_bne (label
));
2462 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
,
2467 /* Use a library function to move some bytes. */
2470 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2475 /* We want to pass the size as Pmode, which will normally be SImode
2476 but will be DImode if we are using 64 bit longs and pointers. */
2477 if (GET_MODE (bytes_rtx
) != VOIDmode
2478 && GET_MODE (bytes_rtx
) != Pmode
)
2479 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, TRUE
);
2481 #ifdef TARGET_MEM_FUNCTIONS
2482 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0,
2486 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2487 TREE_UNSIGNED (sizetype
)),
2488 TYPE_MODE (sizetype
));
2490 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "bcopy"), 0,
2494 convert_to_mode (TYPE_MODE (integer_type_node
),
2496 TREE_UNSIGNED (integer_type_node
)),
2497 TYPE_MODE (integer_type_node
));
2502 /* Expand string/block move operations.
2504 operands[0] is the pointer to the destination.
2505 operands[1] is the pointer to the source.
2506 operands[2] is the number of bytes to move.
2507 operands[3] is the alignment. */
2510 expand_block_move (operands
)
2513 rtx bytes_rtx
= operands
[2];
2514 rtx align_rtx
= operands
[3];
2515 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2516 int bytes
= (constp
? INTVAL (bytes_rtx
) : 0);
2517 int align
= INTVAL (align_rtx
);
2518 rtx orig_src
= operands
[1];
2519 rtx orig_dest
= operands
[0];
2523 if (constp
&& bytes
<= 0)
2526 if (align
> UNITS_PER_WORD
)
2527 align
= UNITS_PER_WORD
;
2529 /* Move the address into scratch registers. */
2530 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2531 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2534 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2536 else if (constp
&& bytes
<= 2*MAX_MOVE_BYTES
)
2537 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
2539 change_address (orig_src
, BLKmode
,
2541 bytes_rtx
, align_rtx
));
2543 else if (constp
&& align
>= UNITS_PER_WORD
&& optimize
)
2544 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
);
2546 else if (constp
&& optimize
)
2548 /* If the alignment is not word aligned, generate a test at
2549 runtime, to see whether things wound up aligned, and we
2550 can use the faster lw/sw instead ulw/usw. */
2552 rtx temp
= gen_reg_rtx (Pmode
);
2553 rtx aligned_label
= gen_label_rtx ();
2554 rtx join_label
= gen_label_rtx ();
2555 int leftover
= bytes
% MAX_MOVE_BYTES
;
2561 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
2562 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2563 emit_insn (gen_cmpdi (temp
, const0_rtx
));
2567 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
2568 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2569 emit_insn (gen_cmpsi (temp
, const0_rtx
));
2571 emit_jump_insn (gen_beq (aligned_label
));
2573 /* Unaligned loop. */
2574 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_dest
, orig_src
);
2575 emit_jump_insn (gen_jump (join_label
));
2579 emit_label (aligned_label
);
2580 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_dest
,
2582 emit_label (join_label
);
2584 /* Bytes at the end of the loop. */
2586 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
2588 change_address (orig_src
, BLKmode
,
2595 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2599 /* Emit load/stores for a small constant block_move.
2601 operands[0] is the memory address of the destination.
2602 operands[1] is the memory address of the source.
2603 operands[2] is the number of bytes to move.
2604 operands[3] is the alignment.
2605 operands[4] is a temp register.
2606 operands[5] is a temp register.
2608 operands[3+num_regs] is the last temp register.
2610 The block move type can be one of the following:
2611 BLOCK_MOVE_NORMAL Do all of the block move.
2612 BLOCK_MOVE_NOT_LAST Do all but the last store.
2613 BLOCK_MOVE_LAST Do just the last store. */
2616 output_block_move (insn
, operands
, num_regs
, move_type
)
2620 enum block_move_type move_type
;
2622 rtx dest_reg
= XEXP (operands
[0], 0);
2623 rtx src_reg
= XEXP (operands
[1], 0);
2624 int bytes
= INTVAL (operands
[2]);
2625 int align
= INTVAL (operands
[3]);
2628 int use_lwl_lwr
= FALSE
;
2629 int last_operand
= num_regs
+4;
2635 char *load
; /* load insn without nop */
2636 char *load_nop
; /* load insn with trailing nop */
2637 char *store
; /* store insn */
2638 char *final
; /* if last_store used: NULL or swr */
2639 char *last_store
; /* last store instruction */
2640 int offset
; /* current offset */
2641 enum machine_mode mode
; /* mode to use on (MEM) */
2644 /* Detect a bug in GCC, where it can give us a register
2645 the same as one of the addressing registers and reduce
2646 the number of registers available. */
2648 i
< last_operand
&& safe_regs
< (sizeof(xoperands
) / sizeof(xoperands
[0]));
2651 if (!reg_mentioned_p (operands
[i
], operands
[0])
2652 && !reg_mentioned_p (operands
[i
], operands
[1]))
2654 xoperands
[safe_regs
++] = operands
[i
];
2657 if (safe_regs
< last_operand
)
2659 xoperands
[0] = operands
[0];
2660 xoperands
[1] = operands
[1];
2661 xoperands
[2] = operands
[2];
2662 xoperands
[3] = operands
[3];
2663 return output_block_move (insn
, xoperands
, safe_regs
-4, move_type
);
2666 /* If we are given global or static addresses, and we would be
2667 emitting a few instructions, try to save time by using a
2668 temporary register for the pointer. */
2669 if (num_regs
> 2 && (bytes
> 2*align
|| move_type
!= BLOCK_MOVE_NORMAL
))
2671 if (CONSTANT_P (src_reg
))
2674 mips_count_memory_refs (operands
[1], 1);
2676 src_reg
= operands
[ 3 + num_regs
-- ];
2677 if (move_type
!= BLOCK_MOVE_LAST
)
2679 xoperands
[1] = operands
[1];
2680 xoperands
[0] = src_reg
;
2681 if (Pmode
== DImode
)
2682 output_asm_insn ("dla\t%0,%1", xoperands
);
2684 output_asm_insn ("la\t%0,%1", xoperands
);
2688 if (CONSTANT_P (dest_reg
))
2691 mips_count_memory_refs (operands
[0], 1);
2693 dest_reg
= operands
[ 3 + num_regs
-- ];
2694 if (move_type
!= BLOCK_MOVE_LAST
)
2696 xoperands
[1] = operands
[0];
2697 xoperands
[0] = dest_reg
;
2698 if (Pmode
== DImode
)
2699 output_asm_insn ("dla\t%0,%1", xoperands
);
2701 output_asm_insn ("la\t%0,%1", xoperands
);
2706 /* ??? We really shouldn't get any LO_SUM addresses here, because they
2707 are not offsettable, however, offsettable_address_p says they are
2708 offsettable. I think this is a bug in offsettable_address_p.
2709 For expediency, we fix this by just loading the address into a register
2710 if we happen to get one. */
2712 if (GET_CODE (src_reg
) == LO_SUM
)
2714 src_reg
= operands
[ 3 + num_regs
-- ];
2715 if (move_type
!= BLOCK_MOVE_LAST
)
2717 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
2718 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2719 xoperands
[0] = src_reg
;
2720 if (Pmode
== DImode
)
2721 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2723 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2727 if (GET_CODE (dest_reg
) == LO_SUM
)
2729 dest_reg
= operands
[ 3 + num_regs
-- ];
2730 if (move_type
!= BLOCK_MOVE_LAST
)
2732 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
2733 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
2734 xoperands
[0] = dest_reg
;
2735 if (Pmode
== DImode
)
2736 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2738 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2742 if (num_regs
> (sizeof (load_store
) / sizeof (load_store
[0])))
2743 num_regs
= (sizeof (load_store
) / sizeof (load_store
[0]));
2745 else if (num_regs
< 1)
2746 abort_with_insn (insn
, "Cannot do block move, not enough scratch registers");
2750 load_store
[num
].offset
= offset
;
2752 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
2754 load_store
[num
].load
= "ld\t%0,%1";
2755 load_store
[num
].load_nop
= "ld\t%0,%1%#";
2756 load_store
[num
].store
= "sd\t%0,%1";
2757 load_store
[num
].last_store
= "sd\t%0,%1";
2758 load_store
[num
].final
= (char *)0;
2759 load_store
[num
].mode
= DImode
;
2764 /* ??? Fails because of a MIPS assembler bug? */
2765 else if (TARGET_64BIT
&& bytes
>= 8)
2767 if (BYTES_BIG_ENDIAN
)
2769 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
2770 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
2771 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
2772 load_store
[num
].last_store
= "sdr\t%0,%2";
2773 load_store
[num
].final
= "sdl\t%0,%1";
2777 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
2778 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
2779 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
2780 load_store
[num
].last_store
= "sdr\t%0,%1";
2781 load_store
[num
].final
= "sdl\t%0,%2";
2783 load_store
[num
].mode
= DImode
;
2789 else if (bytes
>= 4 && align
>= 4)
2791 load_store
[num
].load
= "lw\t%0,%1";
2792 load_store
[num
].load_nop
= "lw\t%0,%1%#";
2793 load_store
[num
].store
= "sw\t%0,%1";
2794 load_store
[num
].last_store
= "sw\t%0,%1";
2795 load_store
[num
].final
= (char *)0;
2796 load_store
[num
].mode
= SImode
;
2801 else if (bytes
>= 4)
2803 if (BYTES_BIG_ENDIAN
)
2805 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
2806 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2807 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
2808 load_store
[num
].last_store
= "swr\t%0,%2";
2809 load_store
[num
].final
= "swl\t%0,%1";
2813 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
2814 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2815 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
2816 load_store
[num
].last_store
= "swr\t%0,%1";
2817 load_store
[num
].final
= "swl\t%0,%2";
2819 load_store
[num
].mode
= SImode
;
2825 else if (bytes
>= 2 && align
>= 2)
2827 load_store
[num
].load
= "lh\t%0,%1";
2828 load_store
[num
].load_nop
= "lh\t%0,%1%#";
2829 load_store
[num
].store
= "sh\t%0,%1";
2830 load_store
[num
].last_store
= "sh\t%0,%1";
2831 load_store
[num
].final
= (char *)0;
2832 load_store
[num
].mode
= HImode
;
2839 load_store
[num
].load
= "lb\t%0,%1";
2840 load_store
[num
].load_nop
= "lb\t%0,%1%#";
2841 load_store
[num
].store
= "sb\t%0,%1";
2842 load_store
[num
].last_store
= "sb\t%0,%1";
2843 load_store
[num
].final
= (char *)0;
2844 load_store
[num
].mode
= QImode
;
2849 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2851 dslots_load_total
++;
2852 dslots_load_filled
++;
2854 if (CONSTANT_P (src_reg
))
2855 mips_count_memory_refs (src_reg
, 1);
2857 if (CONSTANT_P (dest_reg
))
2858 mips_count_memory_refs (dest_reg
, 1);
2861 /* Emit load/stores now if we have run out of registers or are
2862 at the end of the move. */
2864 if (++num
== num_regs
|| bytes
== 0)
2866 /* If only load/store, we need a NOP after the load. */
2869 load_store
[0].load
= load_store
[0].load_nop
;
2870 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2871 dslots_load_filled
--;
2874 if (move_type
!= BLOCK_MOVE_LAST
)
2876 for (i
= 0; i
< num
; i
++)
2883 if (GET_MODE (operands
[i
+4]) != load_store
[i
].mode
)
2884 operands
[i
+4] = gen_rtx (REG
, load_store
[i
].mode
, REGNO (operands
[i
+4]));
2886 offset
= load_store
[i
].offset
;
2887 xoperands
[0] = operands
[i
+4];
2888 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2889 plus_constant (src_reg
, offset
));
2894 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2895 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2896 plus_constant (src_reg
,
2901 output_asm_insn (load_store
[i
].load
, xoperands
);
2905 for (i
= 0; i
< num
; i
++)
2907 int last_p
= (i
== num
-1 && bytes
== 0);
2908 int offset
= load_store
[i
].offset
;
2910 xoperands
[0] = operands
[i
+4];
2911 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2912 plus_constant (dest_reg
, offset
));
2918 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2919 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2920 plus_constant (dest_reg
,
2925 if (move_type
== BLOCK_MOVE_NORMAL
)
2926 output_asm_insn (load_store
[i
].store
, xoperands
);
2928 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
2931 output_asm_insn (load_store
[i
].store
, xoperands
);
2933 else if (load_store
[i
].final
!= (char *)0)
2934 output_asm_insn (load_store
[i
].final
, xoperands
);
2938 output_asm_insn (load_store
[i
].last_store
, xoperands
);
2941 num
= 0; /* reset load_store */
2942 use_lwl_lwr
= FALSE
;
2950 /* Argument support functions. */
2952 /* Initialize CUMULATIVE_ARGS for a function. */
2955 init_cumulative_args (cum
, fntype
, libname
)
2956 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
2957 tree fntype
; /* tree ptr for function decl */
2958 rtx libname
; /* SYMBOL_REF of library name or 0 */
2960 static CUMULATIVE_ARGS zero_cum
;
2961 tree param
, next_param
;
2963 if (TARGET_DEBUG_E_MODE
)
2965 fprintf (stderr
, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
2967 fputc ('\n', stderr
);
2971 tree ret_type
= TREE_TYPE (fntype
);
2972 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
2973 tree_code_name
[ (int)TREE_CODE (fntype
) ],
2974 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
2980 /* Determine if this function has variable arguments. This is
2981 indicated by the last argument being 'void_type_mode' if there
2982 are no variable arguments. The standard MIPS calling sequence
2983 passes all arguments in the general purpose registers in this
2986 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
2990 next_param
= TREE_CHAIN (param
);
2991 if (next_param
== (tree
)0 && TREE_VALUE (param
) != void_type_node
)
2992 cum
->gp_reg_found
= 1;
2996 /* Advance the argument to the next argument position. */
2999 function_arg_advance (cum
, mode
, type
, named
)
3000 CUMULATIVE_ARGS
*cum
; /* current arg information */
3001 enum machine_mode mode
; /* current arg mode */
3002 tree type
; /* type of the argument or 0 if lib support */
3003 int named
; /* whether or not the argument was named */
3005 if (TARGET_DEBUG_E_MODE
)
3007 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
3008 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
3018 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3019 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3021 cum
->gp_reg_found
= 1;
3022 cum
->arg_words
+= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
3027 cum
->gp_reg_found
= 1;
3028 cum
->arg_words
+= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3033 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3034 cum
->fp_arg_words
++;
3040 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
3041 cum
->fp_arg_words
+= (TARGET_64BIT
? 1 : 2);
3043 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3047 cum
->gp_reg_found
= 1;
3048 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3054 cum
->gp_reg_found
= 1;
3060 /* Return an RTL expression containing the register for the given mode,
3061 or 0 if the argument is to be passed on the stack. */
3064 function_arg (cum
, mode
, type
, named
)
3065 CUMULATIVE_ARGS
*cum
; /* current arg information */
3066 enum machine_mode mode
; /* current arg mode */
3067 tree type
; /* type of the argument or 0 if lib support */
3068 int named
; /* != 0 for normal args, == 0 for ... args */
3073 int *arg_words
= &cum
->arg_words
;
3074 int struct_p
= ((type
!= (tree
)0)
3075 && (TREE_CODE (type
) == RECORD_TYPE
3076 || TREE_CODE (type
) == UNION_TYPE
));
3078 if (TARGET_DEBUG_E_MODE
)
3080 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
3081 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
3084 cum
->last_arg_fp
= 0;
3088 if (mips_abi
== ABI_32
)
3090 if (cum
->gp_reg_found
|| cum
->arg_number
>= 2 || TARGET_SOFT_FLOAT
)
3091 regbase
= GP_ARG_FIRST
;
3094 regbase
= FP_ARG_FIRST
;
3095 /* If the first arg was a float in a floating point register,
3096 then set bias to align this float arg properly. */
3097 if (cum
->arg_words
== 1)
3101 else if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3104 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3105 cum
->last_arg_fp
= 1;
3106 arg_words
= &cum
->fp_arg_words
;
3107 regbase
= FP_ARG_FIRST
;
3110 regbase
= (TARGET_SOFT_FLOAT
|| ! named
? GP_ARG_FIRST
: FP_ARG_FIRST
);
3116 if (mips_abi
== ABI_EABI
3117 && ! TARGET_SOFT_FLOAT
3118 && ! TARGET_SINGLE_FLOAT
)
3119 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3121 cum
->arg_words
+= cum
->arg_words
& 1;
3123 if (mips_abi
== ABI_32
)
3124 regbase
= ((cum
->gp_reg_found
3125 || TARGET_SOFT_FLOAT
3126 || TARGET_SINGLE_FLOAT
3127 || cum
->arg_number
>= 2)
3130 else if (mips_abi
== ABI_EABI
3131 && ! TARGET_SOFT_FLOAT
3132 && ! TARGET_SINGLE_FLOAT
)
3134 cum
->last_arg_fp
= 1;
3135 arg_words
= &cum
->fp_arg_words
;
3136 regbase
= FP_ARG_FIRST
;
3139 regbase
= (TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
|| ! named
3140 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
3144 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3145 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3148 /* Drops through. */
3150 if (type
!= (tree
)0 && TYPE_ALIGN (type
) > BITS_PER_WORD
3151 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3152 cum
->arg_words
+= (cum
->arg_words
& 1);
3153 regbase
= GP_ARG_FIRST
;
3160 regbase
= GP_ARG_FIRST
;
3165 cum
->arg_words
+= (cum
->arg_words
& 1);
3166 regbase
= GP_ARG_FIRST
;
3169 if (*arg_words
>= MAX_ARGS_IN_REGISTERS
)
3171 if (TARGET_DEBUG_E_MODE
)
3172 fprintf (stderr
, "<stack>%s\n", struct_p
? ", [struct]" : "");
3181 if (! type
|| TREE_CODE (type
) != RECORD_TYPE
|| mips_abi
== ABI_32
3182 || mips_abi
== ABI_EABI
|| ! named
)
3183 ret
= gen_rtx (REG
, mode
, regbase
+ *arg_words
+ bias
);
3186 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3187 structure contains a double in its entirety, then that 64 bit
3188 chunk is passed in a floating point register. */
3191 /* First check to see if there is any such field. */
3192 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3193 if (TREE_CODE (field
) == FIELD_DECL
3194 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3195 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
3196 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3197 % BITS_PER_WORD
== 0))
3201 ret
= gen_rtx (REG
, mode
, regbase
+ *arg_words
+ bias
);
3204 /* Now handle the special case by returning a PARALLEL
3205 indicating where each 64 bit chunk goes. */
3211 /* ??? If this is a packed structure, then the last hunk won't
3214 /* ??? If this is a structure with a single double field,
3215 it would be more convenient to return (REG:DI %fX) than
3216 a parallel. However, we would have to modify the mips
3217 backend to allow DImode values in fp registers. */
3219 chunks
= TREE_INT_CST_LOW (TYPE_SIZE (type
)) / BITS_PER_WORD
;
3220 if (chunks
+ *arg_words
+ bias
> MAX_ARGS_IN_REGISTERS
)
3221 chunks
= MAX_ARGS_IN_REGISTERS
- *arg_words
- bias
;
3223 /* assign_parms checks the mode of ENTRY_PARM, so we must
3224 use the actual mode here. */
3225 ret
= gen_rtx (PARALLEL
, mode
, rtvec_alloc (chunks
));
3228 regno
= regbase
+ *arg_words
+ bias
;
3229 field
= TYPE_FIELDS (type
);
3230 for (i
= 0; i
< chunks
; i
++)
3234 for (; field
; field
= TREE_CHAIN (field
))
3235 if (TREE_CODE (field
) == FIELD_DECL
3236 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3241 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
)) == bitpos
3242 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3243 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
3244 reg
= gen_rtx (REG
, DFmode
,
3245 regno
+ FP_ARG_FIRST
- GP_ARG_FIRST
);
3247 reg
= gen_rtx (REG
, word_mode
, regno
);
3249 XVECEXP (ret
, 0, i
) = gen_rtx (EXPR_LIST
, VOIDmode
, reg
,
3250 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3258 if (TARGET_DEBUG_E_MODE
)
3259 fprintf (stderr
, "%s%s\n", reg_names
[regbase
+ *arg_words
+ bias
],
3260 struct_p
? ", [struct]" : "");
3262 /* The following is a hack in order to pass 1 byte structures
3263 the same way that the MIPS compiler does (namely by passing
3264 the structure in the high byte or half word of the register).
3265 This also makes varargs work. If we have such a structure,
3266 we save the adjustment RTL, and the call define expands will
3267 emit them. For the VOIDmode argument (argument after the
3268 last real argument), pass back a parallel vector holding each
3269 of the adjustments. */
3271 /* ??? function_arg can be called more than once for each argument.
3272 As a result, we compute more adjustments than we need here.
3273 See the CUMULATIVE_ARGS definition in mips.h. */
3275 /* ??? This scheme requires everything smaller than the word size to
3276 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3277 that would mean every int needs to be shifted left, which is very
3278 inefficient. Let's not carry this compatibility to the 64 bit
3279 calling convention for now. */
3281 if (struct_p
&& int_size_in_bytes (type
) < UNITS_PER_WORD
3282 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3284 rtx amount
= GEN_INT (BITS_PER_WORD
3285 - int_size_in_bytes (type
) * BITS_PER_UNIT
);
3286 rtx reg
= gen_rtx (REG
, word_mode
, regbase
+ *arg_words
+ bias
);
3288 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashldi3 (reg
, reg
, amount
);
3290 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashlsi3 (reg
, reg
, amount
);
3294 if (mode
== VOIDmode
&& cum
->num_adjusts
> 0)
3295 ret
= gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec_v (cum
->num_adjusts
, cum
->adjust
));
3302 function_arg_partial_nregs (cum
, mode
, type
, named
)
3303 CUMULATIVE_ARGS
*cum
; /* current arg information */
3304 enum machine_mode mode
; /* current arg mode */
3305 tree type
; /* type of the argument or 0 if lib support */
3306 int named
; /* != 0 for normal args, == 0 for ... args */
3308 if ((mode
== BLKmode
3309 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3310 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3311 && cum
->arg_words
< MAX_ARGS_IN_REGISTERS
3312 && mips_abi
!= ABI_EABI
)
3315 if (mode
== BLKmode
)
3316 words
= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3319 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3321 if (words
+ cum
->arg_words
<= MAX_ARGS_IN_REGISTERS
)
3322 return 0; /* structure fits in registers */
3324 if (TARGET_DEBUG_E_MODE
)
3325 fprintf (stderr
, "function_arg_partial_nregs = %d\n",
3326 MAX_ARGS_IN_REGISTERS
- cum
->arg_words
);
3328 return MAX_ARGS_IN_REGISTERS
- cum
->arg_words
;
3331 else if (mode
== DImode
&& cum
->arg_words
== MAX_ARGS_IN_REGISTERS
-1
3333 && mips_abi
!= ABI_EABI
)
3335 if (TARGET_DEBUG_E_MODE
)
3336 fprintf (stderr
, "function_arg_partial_nregs = 1\n");
3344 /* Abort after printing out a specific insn. */
3347 abort_with_insn (insn
, reason
)
3356 /* Write a message to stderr (for use in macros expanded in files that do not
3357 include stdio.h). */
3363 fprintf (stderr
, s
, s1
, s2
);
3373 fprintf (stderr
, "compiling '%s' in '%s'\n",
3374 (current_function_name
!= (char *)0) ? current_function_name
: "<toplevel>",
3375 (current_function_file
!= (char *)0) ? current_function_file
: "<no file>");
3378 #endif /* SIGINFO */
3381 /* Set up the threshold for data to go into the small data area, instead
3382 of the normal data area, and detect any conflicts in the switches. */
3387 register int i
, start
;
3389 register enum machine_mode mode
;
3391 mips_section_threshold
= (g_switch_set
) ? g_switch_value
: MIPS_DEFAULT_GVALUE
;
3393 if (mips_section_threshold
<= 0)
3394 target_flags
&= ~MASK_GPOPT
;
3396 target_flags
|= MASK_GPOPT
;
3398 /* Get the architectural level. */
3399 if (mips_isa_string
== (char *)0)
3401 #ifdef MIPS_ISA_DEFAULT
3402 mips_isa
= MIPS_ISA_DEFAULT
;
3408 else if (isdigit (*mips_isa_string
))
3410 mips_isa
= atoi (mips_isa_string
);
3411 if (mips_isa
< 1 || mips_isa
> 4)
3413 error ("-mips%d not supported", mips_isa
);
3420 error ("bad value (%s) for -mips switch", mips_isa_string
);
3424 #ifdef MIPS_ABI_DEFAULT
3425 /* Get the ABI to use. Currently this code is only used for Irix 6. */
3426 if (mips_abi_string
== (char *) 0)
3427 mips_abi
= MIPS_ABI_DEFAULT
;
3428 else if (! strcmp (mips_abi_string
, "32")
3429 || ! strcmp (mips_abi_string
, "o32"))
3431 else if (! strcmp (mips_abi_string
, "n32"))
3433 else if (! strcmp (mips_abi_string
, "64")
3434 || ! strcmp (mips_abi_string
, "n64"))
3436 else if (! strcmp (mips_abi_string
, "eabi"))
3437 mips_abi
= ABI_EABI
;
3439 error ("bad value (%s) for -mabi= switch", mips_abi_string
);
3441 /* A specified ISA defaults the ABI if it was not specified. */
3442 if (mips_abi_string
== 0 && mips_isa_string
&& mips_abi
!= ABI_EABI
)
3449 /* A specified ABI defaults the ISA if it was not specified. */
3450 else if (mips_isa_string
== 0 && mips_abi_string
&& mips_abi
!= ABI_EABI
)
3452 if (mips_abi
== ABI_32
)
3454 else if (mips_abi
== ABI_N32
)
3459 /* If both ABI and ISA were specified, check for conflicts. */
3460 else if (mips_isa_string
&& mips_abi_string
)
3462 if ((mips_isa
<= 2 && (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
3463 || (mips_isa
>= 3 && mips_abi
== ABI_32
))
3464 error ("-mabi=%s does not support -mips%d", mips_abi_string
, mips_isa
);
3467 /* Override TARGET_DEFAULT if necessary. */
3468 if (mips_abi
== ABI_32
)
3469 target_flags
&= ~ (MASK_FLOAT64
|MASK_64BIT
);
3471 /* In the EABI in 64 bit mode, longs and pointers are 64 bits. */
3472 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
3473 target_flags
|= MASK_LONG64
;
3475 /* ??? This doesn't work yet, so don't let people try to use it. */
3476 if (mips_abi
== ABI_32
)
3477 error ("The -mabi=32 support does not work yet.");
3479 if (mips_abi_string
)
3480 error ("This target does not support the -mabi switch.");
3483 #ifdef MIPS_CPU_STRING_DEFAULT
3484 /* ??? There is a minor inconsistency here. If the user specifies an ISA
3485 greater than that supported by the default processor, then the user gets
3486 an error. Normally, the compiler will just default to the base level cpu
3487 for the indicated isa. */
3488 if (mips_cpu_string
== (char *)0)
3489 mips_cpu_string
= MIPS_CPU_STRING_DEFAULT
;
3492 /* Identify the processor type */
3493 if (mips_cpu_string
== (char *)0
3494 || !strcmp (mips_cpu_string
, "default")
3495 || !strcmp (mips_cpu_string
, "DEFAULT"))
3500 mips_cpu_string
= "3000";
3501 mips_cpu
= PROCESSOR_R3000
;
3504 mips_cpu_string
= "6000";
3505 mips_cpu
= PROCESSOR_R6000
;
3508 mips_cpu_string
= "4000";
3509 mips_cpu
= PROCESSOR_R4000
;
3512 mips_cpu_string
= "8000";
3513 mips_cpu
= PROCESSOR_R8000
;
3520 char *p
= mips_cpu_string
;
3523 /* We need to cope with the various "vr" prefixes for the NEC 4300
3524 and 4100 processors. */
3525 if (*p
== 'v' || *p
== 'V')
3530 if (*p
== 'r' || *p
== 'R')
3533 /* Since there is no difference between a R2000 and R3000 in
3534 terms of the scheduler, we collapse them into just an R3000. */
3536 mips_cpu
= PROCESSOR_DEFAULT
;
3540 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
3541 mips_cpu
= PROCESSOR_R3000
;
3545 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
3546 mips_cpu
= PROCESSOR_R3000
;
3550 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
3551 mips_cpu
= PROCESSOR_R4000
;
3552 /* The vr4100 is a non-FP ISA III processor with some extra
3554 else if (!strcmp (p
, "4100")) {
3555 mips_cpu
= PROCESSOR_R4100
;
3556 target_flags
|= MASK_SOFT_FLOAT
;
3558 /* The vr4300 is a standard ISA III processor, but with a different
3560 else if (!strcmp (p
, "4300"))
3561 mips_cpu
= PROCESSOR_R4300
;
3562 /* The r4400 is exactly the same as the r4000 from the compiler's
3564 else if (!strcmp (p
, "4400"))
3565 mips_cpu
= PROCESSOR_R4000
;
3566 else if (!strcmp (p
, "4600"))
3567 mips_cpu
= PROCESSOR_R4600
;
3568 else if (!strcmp (p
, "4650"))
3569 mips_cpu
= PROCESSOR_R4650
;
3573 if (!strcmp (p
, "5000") || !strcmp (p
, "5k") || !strcmp (p
, "5K"))
3574 mips_cpu
= PROCESSOR_R5000
;
3578 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
3579 mips_cpu
= PROCESSOR_R6000
;
3583 if (!strcmp (p
, "8000"))
3584 mips_cpu
= PROCESSOR_R8000
;
3588 if (!strcmp (p
, "orion"))
3589 mips_cpu
= PROCESSOR_R4600
;
3594 && mips_cpu
!= PROCESSOR_R4300
3595 && mips_cpu
!= PROCESSOR_R4100
3596 && mips_cpu
!= PROCESSOR_R5000
)
3597 mips_cpu
= PROCESSOR_DEFAULT
;
3599 if (mips_cpu
== PROCESSOR_DEFAULT
)
3601 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
3602 mips_cpu_string
= "default";
3606 if ((mips_cpu
== PROCESSOR_R3000
&& mips_isa
> 1)
3607 || (mips_cpu
== PROCESSOR_R6000
&& mips_isa
> 2)
3608 || ((mips_cpu
== PROCESSOR_R4000
3609 || mips_cpu
== PROCESSOR_R4100
3610 || mips_cpu
== PROCESSOR_R4300
3611 || mips_cpu
== PROCESSOR_R4600
3612 || mips_cpu
== PROCESSOR_R4650
)
3614 error ("-mcpu=%s does not support -mips%d", mips_cpu_string
, mips_isa
);
3616 /* make sure sizes of ints/longs/etc. are ok */
3620 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3622 else if (TARGET_LONG64
)
3623 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3625 else if (TARGET_FLOAT64
)
3626 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3628 else if (TARGET_64BIT
)
3629 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3632 if (mips_abi
!= ABI_32
)
3633 flag_pcc_struct_return
= 0;
3635 /* Tell halfpic.c that we have half-pic code if we do. */
3636 if (TARGET_HALF_PIC
)
3639 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3640 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3641 /* ??? -non_shared turns off pic code generation, but this is not
3643 if (TARGET_ABICALLS
)
3645 mips_abicalls
= MIPS_ABICALLS_YES
;
3647 if (mips_section_threshold
> 0)
3648 warning ("-G is incompatible with PIC code which is the default");
3651 mips_abicalls
= MIPS_ABICALLS_NO
;
3653 /* -membedded-pic is a form of PIC code suitable for embedded
3654 systems. All calls are made using PC relative addressing, and
3655 all data is addressed using the $gp register. This requires gas,
3656 which does most of the work, and GNU ld, which automatically
3657 expands PC relative calls which are out of range into a longer
3658 instruction sequence. All gcc really does differently is
3659 generate a different sequence for a switch. */
3660 if (TARGET_EMBEDDED_PIC
)
3663 if (TARGET_ABICALLS
)
3664 warning ("-membedded-pic and -mabicalls are incompatible");
3666 warning ("-G and -membedded-pic are incompatible");
3667 /* Setting mips_section_threshold is not required, because gas
3668 will force everything to be GP addressable anyhow, but
3669 setting it will cause gcc to make better estimates of the
3670 number of instructions required to access a particular data
3672 mips_section_threshold
= 0x7fffffff;
3675 /* ??? This does not work when target addresses are DImode.
3676 This is because we are missing DImode high/lo_sum patterns. */
3678 if (TARGET_GAS
&& optimize
&& ! flag_pic
&& Pmode
== SImode
)
3679 mips_split_addresses
= 1;
3681 mips_split_addresses
= 0;
3683 /* -mrnames says to use the MIPS software convention for register
3684 names instead of the hardware names (ie, $a0 instead of $4).
3685 We do this by switching the names in mips_reg_names, which the
3686 reg_names points into via the REGISTER_NAMES macro. */
3688 if (TARGET_NAME_REGS
)
3689 bcopy ((char *) mips_sw_reg_names
, (char *) mips_reg_names
, sizeof (mips_reg_names
));
3691 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3692 is currently being compiled. */
3694 if (getenv ("GCC_SIGINFO") != (char *)0)
3696 struct sigaction action
;
3697 action
.sa_handler
= siginfo
;
3699 action
.sa_flags
= SA_RESTART
;
3700 sigaction (SIGINFO
, &action
, (struct sigaction
*)0);
3705 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3706 /* If -mstats and -quiet, make stderr line buffered. */
3707 if (quiet_flag
&& TARGET_STATS
)
3708 setvbuf (stderr
, (char *)0, _IOLBF
, BUFSIZ
);
3712 /* Initialize the high and low values for legitimate floating point
3713 constants. Rather than trying to get the accuracy down to the
3714 last bit, just use approximate ranges. */
3715 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
3716 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
3717 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
3718 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
3720 mips_print_operand_punct
['?'] = TRUE
;
3721 mips_print_operand_punct
['#'] = TRUE
;
3722 mips_print_operand_punct
['&'] = TRUE
;
3723 mips_print_operand_punct
['!'] = TRUE
;
3724 mips_print_operand_punct
['*'] = TRUE
;
3725 mips_print_operand_punct
['@'] = TRUE
;
3726 mips_print_operand_punct
['.'] = TRUE
;
3727 mips_print_operand_punct
['('] = TRUE
;
3728 mips_print_operand_punct
[')'] = TRUE
;
3729 mips_print_operand_punct
['['] = TRUE
;
3730 mips_print_operand_punct
[']'] = TRUE
;
3731 mips_print_operand_punct
['<'] = TRUE
;
3732 mips_print_operand_punct
['>'] = TRUE
;
3733 mips_print_operand_punct
['{'] = TRUE
;
3734 mips_print_operand_punct
['}'] = TRUE
;
3735 mips_print_operand_punct
['^'] = TRUE
;
3737 mips_char_to_class
['d'] = GR_REGS
;
3738 mips_char_to_class
['f'] = ((TARGET_HARD_FLOAT
) ? FP_REGS
: NO_REGS
);
3739 mips_char_to_class
['h'] = HI_REG
;
3740 mips_char_to_class
['l'] = LO_REG
;
3741 mips_char_to_class
['a'] = HILO_REG
;
3742 mips_char_to_class
['x'] = MD_REGS
;
3743 mips_char_to_class
['b'] = ALL_REGS
;
3744 mips_char_to_class
['y'] = GR_REGS
;
3745 mips_char_to_class
['z'] = ST_REGS
;
3747 /* Set up array to map GCC register number to debug register number.
3748 Ignore the special purpose register numbers. */
3750 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3751 mips_dbx_regno
[i
] = -1;
3753 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
3754 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
3755 mips_dbx_regno
[i
] = i
+ start
;
3757 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
3758 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
3759 mips_dbx_regno
[i
] = i
+ start
;
3761 /* Set up array giving whether a given register can hold a given mode.
3762 At present, restrict ints from being in FP registers, because reload
3763 is a little enthusiastic about storing extra values in FP registers,
3764 and this is not good for things like OS kernels. Also, due to the
3765 mandatory delay, it is as fast to load from cached memory as to move
3766 from the FP register. */
3768 for (mode
= VOIDmode
;
3769 mode
!= MAX_MACHINE_MODE
;
3770 mode
= (enum machine_mode
)((int)mode
+ 1))
3772 register int size
= GET_MODE_SIZE (mode
);
3773 register enum mode_class
class = GET_MODE_CLASS (mode
);
3775 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3782 temp
= (regno
== FPSW_REGNUM
);
3784 temp
= (ST_REG_P (regno
)
3786 || FP_REG_P (regno
));
3789 else if (GP_REG_P (regno
))
3790 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
3792 else if (FP_REG_P (regno
))
3793 temp
= ((TARGET_FLOAT64
|| ((regno
& 1) == 0))
3794 && (class == MODE_FLOAT
3795 || class == MODE_COMPLEX_FLOAT
3796 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
3797 && (! TARGET_SINGLE_FLOAT
|| size
<= 4));
3799 else if (MD_REG_P (regno
))
3800 temp
= (class == MODE_INT
3801 && (size
<= UNITS_PER_WORD
3802 || (regno
== MD_REG_FIRST
&& size
== 2 * UNITS_PER_WORD
)));
3807 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
3814 * The MIPS debug format wants all automatic variables and arguments
3815 * to be in terms of the virtual frame pointer (stack pointer before
3816 * any adjustment in the function), while the MIPS 3.0 linker wants
3817 * the frame pointer to be the stack pointer after the initial
3818 * adjustment. So, we do the adjustment here. The arg pointer (which
3819 * is eliminated) points to the virtual frame pointer, while the frame
3820 * pointer (which may be eliminated) points to the stack pointer after
3821 * the initial adjustments.
3825 mips_debugger_offset (addr
, offset
)
3829 rtx offset2
= const0_rtx
;
3830 rtx reg
= eliminate_constant_term (addr
, &offset2
);
3833 offset
= INTVAL (offset2
);
3835 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
)
3837 int frame_size
= (!current_frame_info
.initialized
)
3838 ? compute_frame_size (get_frame_size ())
3839 : current_frame_info
.total_size
;
3841 offset
= offset
- frame_size
;
3843 /* sdbout_parms does not want this to crash for unrecognized cases. */
3845 else if (reg
!= arg_pointer_rtx
)
3846 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer.");
3853 /* A C compound statement to output to stdio stream STREAM the
3854 assembler syntax for an instruction operand X. X is an RTL
3857 CODE is a value that can be used to specify one of several ways
3858 of printing the operand. It is used when identical operands
3859 must be printed differently depending on the context. CODE
3860 comes from the `%' specification that was used to request
3861 printing of the operand. If the specification was just `%DIGIT'
3862 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3863 is the ASCII code for LTR.
3865 If X is a register, this macro should print the register's name.
3866 The names can be found in an array `reg_names' whose type is
3867 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3869 When the machine description has a specification `%PUNCT' (a `%'
3870 followed by a punctuation character), this macro is called with
3871 a null pointer for X and the punctuation character for CODE.
3873 The MIPS specific codes are:
3875 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3876 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3877 'd' output integer constant in decimal,
3878 'z' if the operand is 0, use $0 instead of normal operand.
3879 'D' print second register of double-word register operand.
3880 'L' print low-order register of double-word register operand.
3881 'M' print high-order register of double-word register operand.
3882 'C' print part of opcode for a branch condition.
3883 'N' print part of opcode for a branch condition, inverted.
3884 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3885 'B' print 'z' for EQ, 'n' for NE
3886 'b' print 'n' for EQ, 'z' for NE
3887 'T' print 'f' for EQ, 't' for NE
3888 't' print 't' for EQ, 'f' for NE
3889 'Z' print register and a comma, but print nothing for $fcc0
3890 '(' Turn on .set noreorder
3891 ')' Turn on .set reorder
3892 '[' Turn on .set noat
3894 '<' Turn on .set nomacro
3895 '>' Turn on .set macro
3896 '{' Turn on .set volatile (not GAS)
3897 '}' Turn on .set novolatile (not GAS)
3898 '&' Turn on .set noreorder if filling delay slots
3899 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3900 '!' Turn on .set nomacro if filling delay slots
3901 '#' Print nop if in a .set noreorder section.
3902 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3903 '@' Print the name of the assembler temporary register (at or $1).
3904 '.' Print the name of the register with a hard-wired zero (zero or $0).
3905 '^' Print the name of the pic call-through register (t9 or $25). */
3908 print_operand (file
, op
, letter
)
3909 FILE *file
; /* file to write to */
3910 rtx op
; /* operand to print */
3911 int letter
; /* %<letter> or 0 */
3913 register enum rtx_code code
;
3915 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
3920 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter
);
3924 if (mips_branch_likely
)
3929 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
3933 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
3937 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
3941 if (final_sequence
!= 0 && set_noreorder
++ == 0)
3942 fputs (".set\tnoreorder\n\t", file
);
3946 if (final_sequence
!= 0)
3948 if (set_noreorder
++ == 0)
3949 fputs (".set\tnoreorder\n\t", file
);
3951 if (set_nomacro
++ == 0)
3952 fputs (".set\tnomacro\n\t", file
);
3957 if (final_sequence
!= 0 && set_nomacro
++ == 0)
3958 fputs ("\n\t.set\tnomacro", file
);
3962 if (set_noreorder
!= 0)
3963 fputs ("\n\tnop", file
);
3965 else if (TARGET_STATS
)
3966 fputs ("\n\t#nop", file
);
3971 if (set_noreorder
++ == 0)
3972 fputs (".set\tnoreorder\n\t", file
);
3976 if (set_noreorder
== 0)
3977 error ("internal error: %%) found without a %%( in assembler pattern");
3979 else if (--set_noreorder
== 0)
3980 fputs ("\n\t.set\treorder", file
);
3985 if (set_noat
++ == 0)
3986 fputs (".set\tnoat\n\t", file
);
3991 error ("internal error: %%] found without a %%[ in assembler pattern");
3993 else if (--set_noat
== 0)
3994 fputs ("\n\t.set\tat", file
);
3999 if (set_nomacro
++ == 0)
4000 fputs (".set\tnomacro\n\t", file
);
4004 if (set_nomacro
== 0)
4005 error ("internal error: %%> found without a %%< in assembler pattern");
4007 else if (--set_nomacro
== 0)
4008 fputs ("\n\t.set\tmacro", file
);
4013 if (set_volatile
++ == 0)
4014 fprintf (file
, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS
) ? "" : "#");
4018 if (set_volatile
== 0)
4019 error ("internal error: %%} found without a %%{ in assembler pattern");
4021 else if (--set_volatile
== 0)
4022 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
4031 error ("PRINT_OPERAND null pointer");
4035 code
= GET_CODE (op
);
4037 if (code
== SIGN_EXTEND
)
4040 code
= GET_CODE (op
);
4046 case EQ
: fputs ("eq", file
); break;
4047 case NE
: fputs ("ne", file
); break;
4048 case GT
: fputs ("gt", file
); break;
4049 case GE
: fputs ("ge", file
); break;
4050 case LT
: fputs ("lt", file
); break;
4051 case LE
: fputs ("le", file
); break;
4052 case GTU
: fputs ("gtu", file
); break;
4053 case GEU
: fputs ("geu", file
); break;
4054 case LTU
: fputs ("ltu", file
); break;
4055 case LEU
: fputs ("leu", file
); break;
4058 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
4061 else if (letter
== 'N')
4064 case EQ
: fputs ("ne", file
); break;
4065 case NE
: fputs ("eq", file
); break;
4066 case GT
: fputs ("le", file
); break;
4067 case GE
: fputs ("lt", file
); break;
4068 case LT
: fputs ("ge", file
); break;
4069 case LE
: fputs ("gt", file
); break;
4070 case GTU
: fputs ("leu", file
); break;
4071 case GEU
: fputs ("ltu", file
); break;
4072 case LTU
: fputs ("geu", file
); break;
4073 case LEU
: fputs ("gtu", file
); break;
4076 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
4079 else if (letter
== 'S')
4083 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
4084 assemble_name (file
, buffer
);
4087 else if (letter
== 'Z')
4089 register int regnum
;
4093 regnum
= REGNO (op
);
4094 if (! ST_REG_P (regnum
))
4096 if (regnum
!= ST_REG_FIRST
)
4097 fprintf (file
, "%s,", reg_names
[regnum
]);
4100 else if (code
== REG
|| code
== SUBREG
)
4102 register int regnum
;
4105 regnum
= REGNO (op
);
4107 regnum
= true_regnum (op
);
4109 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
4110 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
4114 fprintf (file
, "%s", reg_names
[regnum
]);
4117 else if (code
== MEM
)
4118 output_address (XEXP (op
, 0));
4120 else if (code
== CONST_DOUBLE
4121 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
4126 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
4127 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
4131 else if ((letter
== 'x') && (GET_CODE(op
) == CONST_INT
))
4132 fprintf (file
, "0x%04x", 0xffff & (INTVAL(op
)));
4134 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
4135 && HOST_BITS_PER_WIDE_INT
== 32)
4136 fprintf (file
, "0x%08x", INTVAL(op
));
4138 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
4139 && HOST_BITS_PER_WIDE_INT
== 64)
4140 fprintf (file
, "0x%016lx", INTVAL(op
));
4142 else if ((letter
== 'd') && (GET_CODE(op
) == CONST_INT
))
4143 fprintf (file
, "%d", (INTVAL(op
)));
4145 else if (letter
== 'z'
4146 && (GET_CODE (op
) == CONST_INT
)
4147 && INTVAL (op
) == 0)
4148 fputs (reg_names
[GP_REG_FIRST
], file
);
4150 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
4151 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter
);
4153 else if (letter
== 'B')
4154 fputs (code
== EQ
? "z" : "n", file
);
4155 else if (letter
== 'b')
4156 fputs (code
== EQ
? "n" : "z", file
);
4157 else if (letter
== 'T')
4158 fputs (code
== EQ
? "f" : "t", file
);
4159 else if (letter
== 't')
4160 fputs (code
== EQ
? "t" : "f", file
);
4163 output_addr_const (file
, op
);
4167 /* A C compound statement to output to stdio stream STREAM the
4168 assembler syntax for an instruction operand that is a memory
4169 reference whose address is ADDR. ADDR is an RTL expression.
4171 On some machines, the syntax for a symbolic address depends on
4172 the section that the address refers to. On these machines,
4173 define the macro `ENCODE_SECTION_INFO' to store the information
4174 into the `symbol_ref', and then check for it here. */
4177 print_operand_address (file
, addr
)
4182 error ("PRINT_OPERAND_ADDRESS, null pointer");
4185 switch (GET_CODE (addr
))
4188 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
4192 if (REGNO (addr
) == ARG_POINTER_REGNUM
)
4193 abort_with_insn (addr
, "Arg pointer not eliminated.");
4195 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
4200 register rtx arg0
= XEXP (addr
, 0);
4201 register rtx arg1
= XEXP (addr
, 1);
4203 if (! mips_split_addresses
)
4204 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4206 if (GET_CODE (arg0
) != REG
)
4207 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4209 fprintf (file
, "%%lo(");
4210 print_operand_address (file
, arg1
);
4211 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
4217 register rtx reg
= (rtx
)0;
4218 register rtx offset
= (rtx
)0;
4219 register rtx arg0
= XEXP (addr
, 0);
4220 register rtx arg1
= XEXP (addr
, 1);
4222 if (GET_CODE (arg0
) == REG
)
4226 if (GET_CODE (offset
) == REG
)
4227 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
4229 else if (GET_CODE (arg1
) == REG
)
4234 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
4236 output_addr_const (file
, addr
);
4240 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
4242 if (!CONSTANT_P (offset
))
4243 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4245 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
4246 abort_with_insn (addr
, "Arg pointer not eliminated.");
4248 output_addr_const (file
, offset
);
4249 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
4257 output_addr_const (file
, addr
);
4263 /* If optimizing for the global pointer, keep track of all of
4264 the externs, so that at the end of the file, we can emit
4265 the appropriate .extern declaration for them, before writing
4266 out the text section. We assume that all names passed to
4267 us are in the permanent obstack, so that they will be valid
4268 at the end of the compilation.
4270 If we have -G 0, or the extern size is unknown, don't bother
4271 emitting the .externs. */
4274 mips_output_external (file
, decl
, name
)
4279 register struct extern_list
*p
;
4283 && ((TREE_CODE (decl
)) != FUNCTION_DECL
)
4284 && ((len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0))
4286 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4287 p
->next
= extern_head
;
4293 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4294 if (TREE_CODE (decl
) == FUNCTION_DECL
4295 /* ??? Don't include alloca, since gcc will always expand it
4296 inline. If we don't do this, libg++ fails to build. */
4297 && strcmp (name
, "alloca")
4298 /* ??? Don't include __builtin_next_arg, because then gcc will not
4299 bootstrap under Irix 5.1. */
4300 && strcmp (name
, "__builtin_next_arg"))
4302 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4303 p
->next
= extern_head
;
4313 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4315 mips_output_external_libcall (file
, name
)
4319 register struct extern_list
*p
;
4321 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4322 p
->next
= extern_head
;
4332 /* Compute a string to use as a temporary file name. */
4334 /* On MSDOS, write temp files in current dir
4335 because there's no place else we can expect to use. */
4338 #define P_tmpdir "./"
4346 char *base
= getenv ("TMPDIR");
4349 if (base
== (char *)0)
4352 if (access (P_tmpdir
, R_OK
| W_OK
) == 0)
4356 if (access ("/usr/tmp", R_OK
| W_OK
) == 0)
4362 len
= strlen (base
);
4363 /* temp_filename is global, so we must use malloc, not alloca. */
4364 temp_filename
= (char *) xmalloc (len
+ sizeof("/ctXXXXXX"));
4365 strcpy (temp_filename
, base
);
4366 if (len
> 0 && temp_filename
[len
-1] != '/')
4367 temp_filename
[len
++] = '/';
4369 strcpy (temp_filename
+ len
, "ctXXXXXX");
4370 mktemp (temp_filename
);
4372 stream
= fopen (temp_filename
, "w+");
4374 pfatal_with_name (temp_filename
);
4377 /* In MSDOS, we cannot unlink the temporary file until we are finished using
4378 it. Otherwise, we delete it now, so that it will be gone even if the
4379 compiler happens to crash. */
4380 unlink (temp_filename
);
4386 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
4387 for .file's that start within a function. If we are smuggling stabs, try to
4388 put out a MIPS ECOFF file and a stab. */
4391 mips_output_filename (stream
, name
)
4395 static int first_time
= TRUE
;
4396 char ltext_label_name
[100];
4402 current_function_file
= name
;
4403 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4404 /* This tells mips-tfile that stabs will follow. */
4405 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
4406 fprintf (stream
, "\t#@stabs\n");
4409 else if (write_symbols
== DBX_DEBUG
)
4411 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
4412 fprintf (stream
, "%s ", ASM_STABS_OP
);
4413 output_quoted_string (stream
, name
);
4414 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
4417 else if (name
!= current_function_file
4418 && strcmp (name
, current_function_file
) != 0)
4420 if (inside_function
&& !TARGET_GAS
)
4422 if (!file_in_function_warning
)
4424 file_in_function_warning
= TRUE
;
4425 ignore_line_number
= TRUE
;
4426 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
4432 current_function_file
= name
;
4433 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4439 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4440 as well as a .loc, since it is possible that MIPS ECOFF might not be
4441 able to represent the location for inlines that come from a different
4445 mips_output_lineno (stream
, line
)
4449 if (write_symbols
== DBX_DEBUG
)
4452 fprintf (stream
, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
4453 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
4454 LOCAL_LABEL_PREFIX
, sym_lineno
);
4459 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
4460 (ignore_line_number
) ? "#" : "",
4461 num_source_filenames
, line
);
4463 LABEL_AFTER_LOC (stream
);
4468 /* If defined, a C statement to be executed just prior to the
4469 output of assembler code for INSN, to modify the extracted
4470 operands so they will be output differently.
4472 Here the argument OPVEC is the vector containing the operands
4473 extracted from INSN, and NOPERANDS is the number of elements of
4474 the vector which contain meaningful data for this insn. The
4475 contents of this vector are what will be used to convert the
4476 insn template into assembler code, so you can change the
4477 assembler output by changing the contents of the vector.
4479 We use it to check if the current insn needs a nop in front of it
4480 because of load delays, and also to update the delay slot
4483 /* ??? There is no real need for this function, because it never actually
4484 emits a NOP anymore. */
4487 final_prescan_insn (insn
, opvec
, noperands
)
4492 if (dslots_number_nops
> 0)
4494 rtx pattern
= PATTERN (insn
);
4495 int length
= get_attr_length (insn
);
4497 /* Do we need to emit a NOP? */
4499 || (mips_load_reg
!= (rtx
)0 && reg_mentioned_p (mips_load_reg
, pattern
))
4500 || (mips_load_reg2
!= (rtx
)0 && reg_mentioned_p (mips_load_reg2
, pattern
))
4501 || (mips_load_reg3
!= (rtx
)0 && reg_mentioned_p (mips_load_reg3
, pattern
))
4502 || (mips_load_reg4
!= (rtx
)0 && reg_mentioned_p (mips_load_reg4
, pattern
)))
4503 fputs ("\t#nop\n", asm_out_file
);
4506 dslots_load_filled
++;
4508 while (--dslots_number_nops
> 0)
4509 fputs ("\t#nop\n", asm_out_file
);
4511 mips_load_reg
= (rtx
)0;
4512 mips_load_reg2
= (rtx
)0;
4513 mips_load_reg3
= (rtx
)0;
4514 mips_load_reg4
= (rtx
)0;
4519 enum rtx_code code
= GET_CODE (insn
);
4520 if (code
== JUMP_INSN
|| code
== CALL_INSN
)
4521 dslots_jump_total
++;
4526 /* Output at beginning of assembler file.
4527 If we are optimizing to use the global pointer, create a temporary
4528 file to hold all of the text stuff, and write it out to the end.
4529 This is needed because the MIPS assembler is evidently one pass,
4530 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4531 declaration when the code is processed, it generates a two
4532 instruction sequence. */
4535 mips_asm_file_start (stream
)
4538 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
4540 /* Versions of the MIPS assembler before 2.20 generate errors
4541 if a branch inside of a .set noreorder section jumps to a
4542 label outside of the .set noreorder section. Revision 2.20
4543 just set nobopt silently rather than fixing the bug. */
4545 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
4546 fprintf (stream
, "\t.set\tnobopt\n");
4548 /* Generate the pseudo ops that System V.4 wants. */
4549 #ifndef ABICALLS_ASM_OP
4550 #define ABICALLS_ASM_OP ".abicalls"
4552 if (TARGET_ABICALLS
)
4553 /* ??? but do not want this (or want pic0) if -non-shared? */
4554 fprintf (stream
, "\t%s\n", ABICALLS_ASM_OP
);
4556 /* Start a section, so that the first .popsection directive is guaranteed
4557 to have a previously defined section to pop back to. */
4558 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
4559 fprintf (stream
, "\t.section\t.text\n");
4561 /* This code exists so that we can put all externs before all symbol
4562 references. This is necessary for the assembler's global pointer
4563 optimizations to work. */
4564 /* ??? Current versions of gas do not require that externs occur before
4565 symbol references. This means that this code is unnecessary when
4566 gas is being used. This gas feature hasn't been well tested as yet
4570 asm_out_data_file
= stream
;
4571 asm_out_text_file
= make_temp_file ();
4574 asm_out_data_file
= asm_out_text_file
= stream
;
4576 if (flag_verbose_asm
)
4577 fprintf (stream
, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
4579 mips_section_threshold
, mips_cpu_string
, mips_isa
);
4583 /* If we are optimizing the global pointer, emit the text section now
4584 and any small externs which did not have .comm, etc that are
4585 needed. Also, give a warning if the data area is more than 32K and
4586 -pic because 3 instructions are needed to reference the data
4590 mips_asm_file_end (file
)
4595 struct extern_list
*p
;
4599 HALF_PIC_FINISH (file
);
4605 for (p
= extern_head
; p
!= 0; p
= p
->next
)
4607 name_tree
= get_identifier (p
->name
);
4609 /* Positively ensure only one .extern for any given symbol. */
4610 if (! TREE_ASM_WRITTEN (name_tree
))
4612 TREE_ASM_WRITTEN (name_tree
) = 1;
4613 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4615 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
4619 fputs ("\t.extern\t", file
);
4620 assemble_name (file
, p
->name
);
4621 fprintf (file
, ", %d\n", p
->size
);
4629 fprintf (file
, "\n\t.text\n");
4630 rewind (asm_out_text_file
);
4631 if (ferror (asm_out_text_file
))
4632 fatal_io_error (temp_filename
);
4634 while ((len
= fread (buffer
, 1, sizeof (buffer
), asm_out_text_file
)) > 0)
4635 if (fwrite (buffer
, 1, len
, file
) != len
)
4636 pfatal_with_name (asm_file_name
);
4639 pfatal_with_name (temp_filename
);
4641 if (fclose (asm_out_text_file
) != 0)
4642 pfatal_with_name (temp_filename
);
4645 unlink (temp_filename
);
4651 /* Emit either a label, .comm, or .lcomm directive, and mark
4652 that the symbol is used, so that we don't emit an .extern
4653 for it in mips_asm_file_end. */
4656 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
4663 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
4664 assemble_name (stream
, name
);
4665 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
4669 tree name_tree
= get_identifier (name
);
4670 TREE_ASM_WRITTEN (name_tree
) = 1;
4675 /* Output a double precision value to the assembler. If both the
4676 host and target are IEEE, emit the values in hex. */
4679 mips_output_double (stream
, value
)
4681 REAL_VALUE_TYPE value
;
4683 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4685 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
4687 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4688 value_long
[0], value
, value_long
[1]);
4690 fprintf (stream
, "\t.double\t%.20g\n", value
);
4695 /* Output a single precision value to the assembler. If both the
4696 host and target are IEEE, emit the values in hex. */
4699 mips_output_float (stream
, value
)
4701 REAL_VALUE_TYPE value
;
4703 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4705 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
4707 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
4709 fprintf (stream
, "\t.float\t%.12g\n", value
);
4714 /* Return TRUE if any register used in the epilogue is used. This to insure
4715 any insn put into the epilogue delay slots is safe. */
4718 epilogue_reg_mentioned_p (insn
)
4723 register enum rtx_code code
;
4729 if (GET_CODE (insn
) == LABEL_REF
)
4732 code
= GET_CODE (insn
);
4736 regno
= REGNO (insn
);
4737 if (regno
== STACK_POINTER_REGNUM
)
4740 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4743 if (!call_used_regs
[regno
])
4746 if (regno
!= MIPS_TEMP1_REGNUM
&& regno
!= MIPS_TEMP2_REGNUM
)
4749 if (!current_frame_info
.initialized
)
4750 compute_frame_size (get_frame_size ());
4752 return (current_frame_info
.total_size
>= 32768);
4762 fmt
= GET_RTX_FORMAT (code
);
4763 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4768 for (j
= XVECLEN (insn
, i
) - 1; j
>= 0; j
--)
4769 if (epilogue_reg_mentioned_p (XVECEXP (insn
, i
, j
)))
4772 else if (fmt
[i
] == 'e' && epilogue_reg_mentioned_p (XEXP (insn
, i
)))
4779 /* Return the bytes needed to compute the frame pointer from the current
4782 Mips stack frames look like:
4784 Before call After call
4785 +-----------------------+ +-----------------------+
4788 | caller's temps. | | caller's temps. |
4790 +-----------------------+ +-----------------------+
4792 | arguments on stack. | | arguments on stack. |
4794 +-----------------------+ +-----------------------+
4795 | 4 words to save | | 4 words to save |
4796 | arguments passed | | arguments passed |
4797 | in registers, even | | in registers, even |
4798 SP->| if not passed. | VFP->| if not passed. |
4799 +-----------------------+ +-----------------------+
4801 | fp register save |
4803 +-----------------------+
4805 | gp register save |
4807 +-----------------------+
4811 +-----------------------+
4813 | alloca allocations |
4815 +-----------------------+
4817 | GP save for V.4 abi |
4819 +-----------------------+
4821 | arguments on stack |
4823 +-----------------------+
4825 | arguments passed |
4826 | in registers, even |
4827 low SP->| if not passed. |
4828 memory +-----------------------+
4833 compute_frame_size (size
)
4834 int size
; /* # of var. bytes allocated */
4837 long total_size
; /* # bytes that the entire frame takes up */
4838 long var_size
; /* # bytes that variables take up */
4839 long args_size
; /* # bytes that outgoing arguments take up */
4840 long extra_size
; /* # extra bytes */
4841 long gp_reg_rounded
; /* # bytes needed to store gp after rounding */
4842 long gp_reg_size
; /* # bytes needed to store gp regs */
4843 long fp_reg_size
; /* # bytes needed to store fp regs */
4844 long mask
; /* mask of saved gp registers */
4845 long fmask
; /* mask of saved fp registers */
4846 int fp_inc
; /* 1 or 2 depending on the size of fp regs */
4847 long fp_bits
; /* bitmask to use for each fp register */
4853 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
4854 var_size
= MIPS_STACK_ALIGN (size
);
4855 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
4857 /* The MIPS 3.0 linker does not like functions that dynamically
4858 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4859 looks like we are trying to create a second frame pointer to the
4860 function, so allocate some stack space to make it happy. */
4862 if (args_size
== 0 && current_function_calls_alloca
)
4863 args_size
= 4*UNITS_PER_WORD
;
4865 total_size
= var_size
+ args_size
+ extra_size
;
4867 /* Calculate space needed for gp registers. */
4868 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4870 if (MUST_SAVE_REGISTER (regno
))
4872 gp_reg_size
+= UNITS_PER_WORD
;
4873 mask
|= 1L << (regno
- GP_REG_FIRST
);
4877 /* Calculate space needed for fp registers. */
4878 if (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
)
4889 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= fp_inc
)
4891 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
4893 fp_reg_size
+= fp_inc
* UNITS_PER_FPREG
;
4894 fmask
|= fp_bits
<< (regno
- FP_REG_FIRST
);
4898 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4899 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
4901 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4902 for leaf routines (total_size == extra_size) to save the gp reg.
4903 The gp reg is callee saved in the 64 bit ABI, so all routines must
4905 if (total_size
== extra_size
&& (mips_abi
== ABI_32
|| mips_abi
== ABI_EABI
))
4906 total_size
= extra_size
= 0;
4907 else if (TARGET_ABICALLS
)
4909 /* Add the context-pointer to the saved registers. */
4910 gp_reg_size
+= UNITS_PER_WORD
;
4911 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
4912 total_size
-= gp_reg_rounded
;
4913 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4914 total_size
+= gp_reg_rounded
;
4917 /* Add in space reserved on the stack by the callee for storing arguments
4918 passed in registers. */
4919 if (mips_abi
!= ABI_32
)
4920 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
4922 /* Save other computed information. */
4923 current_frame_info
.total_size
= total_size
;
4924 current_frame_info
.var_size
= var_size
;
4925 current_frame_info
.args_size
= args_size
;
4926 current_frame_info
.extra_size
= extra_size
;
4927 current_frame_info
.gp_reg_size
= gp_reg_size
;
4928 current_frame_info
.fp_reg_size
= fp_reg_size
;
4929 current_frame_info
.mask
= mask
;
4930 current_frame_info
.fmask
= fmask
;
4931 current_frame_info
.initialized
= reload_completed
;
4932 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
4933 current_frame_info
.num_fp
= fp_reg_size
/ (fp_inc
* UNITS_PER_FPREG
);
4937 unsigned long offset
= (args_size
+ extra_size
+ var_size
4938 + gp_reg_size
- UNITS_PER_WORD
);
4939 current_frame_info
.gp_sp_offset
= offset
;
4940 current_frame_info
.gp_save_offset
= offset
- total_size
;
4944 current_frame_info
.gp_sp_offset
= 0;
4945 current_frame_info
.gp_save_offset
= 0;
4951 unsigned long offset
= (args_size
+ extra_size
+ var_size
4952 + gp_reg_rounded
+ fp_reg_size
4953 - fp_inc
* UNITS_PER_FPREG
);
4954 current_frame_info
.fp_sp_offset
= offset
;
4955 current_frame_info
.fp_save_offset
= offset
- total_size
;
4959 current_frame_info
.fp_sp_offset
= 0;
4960 current_frame_info
.fp_save_offset
= 0;
4963 /* Ok, we're done. */
4968 /* Common code to emit the insns (or to write the instructions to a file)
4969 to save/restore registers.
4971 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4972 is not modified within save_restore_insns. */
4974 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4977 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
4978 int store_p
; /* true if this is prologue */
4979 rtx large_reg
; /* register holding large offset constant or NULL */
4980 long large_offset
; /* large constant offset value */
4981 FILE *file
; /* file to write instructions to instead of making RTL */
4983 long mask
= current_frame_info
.mask
;
4984 long fmask
= current_frame_info
.fmask
;
4993 if (frame_pointer_needed
&& !BITSET_P (mask
, FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
4996 if (mask
== 0 && fmask
== 0)
4999 /* Save registers starting from high to low. The debuggers prefer
5000 at least the return register be stored at func+4, and also it
5001 allows us not to need a nop in the epilog if at least one
5002 register is reloaded in addition to return address. */
5004 /* Save GP registers if needed. */
5007 /* Pick which pointer to use as a base register. For small
5008 frames, just use the stack pointer. Otherwise, use a
5009 temporary register. Save 2 cycles if the save area is near
5010 the end of a large frame, by reusing the constant created in
5011 the prologue/epilogue to adjust the stack frame. */
5013 gp_offset
= current_frame_info
.gp_sp_offset
;
5014 end_offset
= gp_offset
- (current_frame_info
.gp_reg_size
- UNITS_PER_WORD
);
5016 if (gp_offset
< 0 || end_offset
< 0)
5017 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
5018 gp_offset
, end_offset
);
5020 else if (gp_offset
< 32768)
5022 base_reg_rtx
= stack_pointer_rtx
;
5026 else if (large_reg
!= (rtx
)0
5027 && (((unsigned long)(large_offset
- gp_offset
)) < 32768)
5028 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
5030 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5031 base_offset
= large_offset
;
5032 if (file
== (FILE *)0)
5035 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5037 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5038 RTX_FRAME_RELATED_P (insn
) = 1;
5041 fprintf (file
, "\t%s\t%s,%s,%s\n",
5042 TARGET_LONG64
? "daddu" : "addu",
5043 reg_names
[MIPS_TEMP2_REGNUM
],
5044 reg_names
[REGNO (large_reg
)],
5045 reg_names
[STACK_POINTER_REGNUM
]);
5050 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5051 base_offset
= gp_offset
;
5052 if (file
== (FILE *)0)
5054 insn
= emit_move_insn (base_reg_rtx
, GEN_INT (gp_offset
));
5055 RTX_FRAME_RELATED_P (insn
) = 1;
5057 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5059 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5060 RTX_FRAME_RELATED_P (insn
) = 1;
5063 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5064 reg_names
[MIPS_TEMP2_REGNUM
],
5067 TARGET_LONG64
? "daddu" : "addu",
5068 reg_names
[MIPS_TEMP2_REGNUM
],
5069 reg_names
[MIPS_TEMP2_REGNUM
],
5070 reg_names
[STACK_POINTER_REGNUM
]);
5073 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
5075 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
5077 if (file
== (FILE *)0)
5079 rtx reg_rtx
= gen_rtx (REG
, word_mode
, regno
);
5080 rtx mem_rtx
= gen_rtx (MEM
, word_mode
,
5081 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5082 GEN_INT (gp_offset
- base_offset
)));
5086 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
5087 RTX_FRAME_RELATED_P (insn
) = 1;
5089 else if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
5090 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
5091 emit_move_insn (reg_rtx
, mem_rtx
);
5095 if (store_p
|| !TARGET_ABICALLS
|| mips_abi
!= ABI_32
5096 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
5097 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5099 ? (store_p
) ? "sd" : "ld"
5100 : (store_p
) ? "sw" : "lw"),
5102 gp_offset
- base_offset
,
5103 reg_names
[REGNO(base_reg_rtx
)]);
5106 gp_offset
-= UNITS_PER_WORD
;
5112 base_reg_rtx
= (rtx
)0; /* Make sure these are initialized */
5116 /* Save floating point registers if needed. */
5119 int fp_inc
= (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
) ? 1 : 2;
5120 int fp_size
= fp_inc
* UNITS_PER_FPREG
;
5122 /* Pick which pointer to use as a base register. */
5123 fp_offset
= current_frame_info
.fp_sp_offset
;
5124 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
- fp_size
);
5126 if (fp_offset
< 0 || end_offset
< 0)
5127 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
5128 fp_offset
, end_offset
);
5130 else if (fp_offset
< 32768)
5132 base_reg_rtx
= stack_pointer_rtx
;
5136 else if (base_reg_rtx
!= (rtx
)0
5137 && (((unsigned long)(base_offset
- fp_offset
)) < 32768)
5138 && (((unsigned long)(base_offset
- end_offset
)) < 32768))
5140 ; /* already set up for gp registers above */
5143 else if (large_reg
!= (rtx
)0
5144 && (((unsigned long)(large_offset
- fp_offset
)) < 32768)
5145 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
5147 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5148 base_offset
= large_offset
;
5149 if (file
== (FILE *)0)
5152 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5154 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5155 RTX_FRAME_RELATED_P (insn
) = 1;
5158 fprintf (file
, "\t%s\t%s,%s,%s\n",
5159 TARGET_LONG64
? "daddu" : "addu",
5160 reg_names
[MIPS_TEMP2_REGNUM
],
5161 reg_names
[REGNO (large_reg
)],
5162 reg_names
[STACK_POINTER_REGNUM
]);
5167 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5168 base_offset
= fp_offset
;
5169 if (file
== (FILE *)0)
5171 insn
= emit_move_insn (base_reg_rtx
, GEN_INT (fp_offset
));
5172 RTX_FRAME_RELATED_P (insn
) = 1;
5174 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5176 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5177 RTX_FRAME_RELATED_P (insn
) = 1;
5180 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5181 reg_names
[MIPS_TEMP2_REGNUM
],
5184 TARGET_LONG64
? "daddu" : "addu",
5185 reg_names
[MIPS_TEMP2_REGNUM
],
5186 reg_names
[MIPS_TEMP2_REGNUM
],
5187 reg_names
[STACK_POINTER_REGNUM
]);
5190 for (regno
= FP_REG_LAST
-1; regno
>= FP_REG_FIRST
; regno
-= fp_inc
)
5192 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
5194 if (file
== (FILE *)0)
5196 enum machine_mode sz
=
5197 TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5198 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
5199 rtx mem_rtx
= gen_rtx (MEM
, sz
,
5200 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5201 GEN_INT (fp_offset
- base_offset
)));
5205 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
5206 RTX_FRAME_RELATED_P (insn
) = 1;
5209 emit_move_insn (reg_rtx
, mem_rtx
);
5212 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5213 (TARGET_SINGLE_FLOAT
5214 ? ((store_p
) ? "s.s" : "l.s")
5215 : ((store_p
) ? "s.d" : "l.d")),
5217 fp_offset
- base_offset
,
5218 reg_names
[REGNO(base_reg_rtx
)]);
5221 fp_offset
-= fp_size
;
5228 /* Set up the stack and frame (if desired) for the function. */
5231 function_prologue (file
, size
)
5236 long tsize
= current_frame_info
.total_size
;
5238 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
5240 #ifdef SDB_DEBUGGING_INFO
5241 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
5242 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
5245 inside_function
= 1;
5247 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5248 /* Get the function name the same way that toplev.c does before calling
5249 assemble_start_function. This is needed so that the name used here
5250 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5251 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5253 fputs ("\t.ent\t", file
);
5254 assemble_name (file
, fnname
);
5257 assemble_name (file
, fnname
);
5258 fputs (":\n", file
);
5261 fprintf (file
, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5262 reg_names
[ (frame_pointer_needed
) ? FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
],
5264 reg_names
[31 + GP_REG_FIRST
],
5265 current_frame_info
.var_size
,
5266 current_frame_info
.num_gp
,
5267 current_frame_info
.num_fp
,
5268 current_function_outgoing_args_size
,
5269 current_frame_info
.extra_size
);
5271 fprintf (file
, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
5272 current_frame_info
.mask
,
5273 current_frame_info
.gp_save_offset
,
5274 current_frame_info
.fmask
,
5275 current_frame_info
.fp_save_offset
);
5277 if (TARGET_ABICALLS
&& mips_abi
== ABI_32
)
5279 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5281 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
5282 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
5285 fprintf (file
, "\t%s\t%s,%s,%d\n",
5286 (TARGET_LONG64
? "dsubu" : "subu"),
5287 sp_str
, sp_str
, tsize
);
5288 fprintf (file
, "\t.cprestore %d\n", current_frame_info
.args_size
);
5294 /* Expand the prologue into a bunch of separate insns. */
5297 mips_expand_prologue ()
5301 rtx tmp_rtx
= (rtx
)0;
5302 char *arg_name
= (char *)0;
5303 tree fndecl
= current_function_decl
;
5304 tree fntype
= TREE_TYPE (fndecl
);
5305 tree fnargs
= DECL_ARGUMENTS (fndecl
);
5310 CUMULATIVE_ARGS args_so_far
;
5312 /* If struct value address is treated as the first argument, make it so. */
5313 if (aggregate_value_p (DECL_RESULT (fndecl
))
5314 && ! current_function_returns_pcc_struct
5315 && struct_value_incoming_rtx
== 0)
5317 tree type
= build_pointer_type (fntype
);
5318 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
5319 DECL_ARG_TYPE (function_result_decl
) = type
;
5320 TREE_CHAIN (function_result_decl
) = fnargs
;
5321 fnargs
= function_result_decl
;
5324 /* Determine the last argument, and get its name. */
5326 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, (rtx
)0, 0);
5327 regno
= GP_ARG_FIRST
;
5329 for (cur_arg
= fnargs
; cur_arg
!= (tree
)0; cur_arg
= next_arg
)
5331 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
5332 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
5335 if (TREE_ADDRESSABLE (passed_type
))
5337 passed_type
= build_pointer_type (passed_type
);
5338 passed_mode
= Pmode
;
5341 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
5347 /* passed in a register, so will get homed automatically */
5348 if (GET_MODE (entry_parm
) == BLKmode
)
5349 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
5351 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
5353 regno
= REGNO (entry_parm
) + words
- 1;
5357 regno
= GP_ARG_LAST
+1;
5361 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
5363 next_arg
= TREE_CHAIN (cur_arg
);
5364 if (next_arg
== (tree
)0)
5366 if (DECL_NAME (cur_arg
))
5367 arg_name
= IDENTIFIER_POINTER (DECL_NAME (cur_arg
));
5373 /* In order to pass small structures by value in registers
5374 compatibly with the MIPS compiler, we need to shift the value
5375 into the high part of the register. Function_arg has encoded a
5376 PARALLEL rtx, holding a vector of adjustments to be made as the
5377 next_arg_reg variable, so we split up the insns, and emit them
5380 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
5381 if (next_arg_reg
!= (rtx
)0 && GET_CODE (next_arg_reg
) == PARALLEL
)
5383 rtvec adjust
= XVEC (next_arg_reg
, 0);
5384 int num
= GET_NUM_ELEM (adjust
);
5386 for (i
= 0; i
< num
; i
++)
5388 rtx pattern
= RTVEC_ELT (adjust
, i
);
5389 if (GET_CODE (pattern
) != SET
5390 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
5391 abort_with_insn (pattern
, "Insn is not a shift");
5393 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
5394 emit_insn (pattern
);
5398 tsize
= compute_frame_size (get_frame_size ());
5400 /* If this function is a varargs function, store any registers that
5401 would normally hold arguments ($4 - $7) on the stack. */
5402 if (mips_abi
== ABI_32
5403 && ((TYPE_ARG_TYPES (fntype
) != 0
5404 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
))) != void_type_node
))
5405 || (arg_name
!= (char *)0
5406 && ((arg_name
[0] == '_' && strcmp (arg_name
, "__builtin_va_alist") == 0)
5407 || (arg_name
[0] == 'v' && strcmp (arg_name
, "va_alist") == 0)))))
5409 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
5410 rtx ptr
= stack_pointer_rtx
;
5412 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
5413 if (TARGET_ABICALLS
)
5416 for (; regno
<= GP_ARG_LAST
; regno
++)
5419 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
5420 emit_move_insn (gen_rtx (MEM
, word_mode
, ptr
),
5421 gen_rtx (REG
, word_mode
, regno
));
5422 offset
+= UNITS_PER_WORD
;
5428 rtx tsize_rtx
= GEN_INT (tsize
);
5430 /* If we are doing svr4-abi, sp move is done by function_prologue. */
5431 if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
)
5437 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5438 insn
= emit_move_insn (tmp_rtx
, tsize_rtx
);
5439 RTX_FRAME_RELATED_P (insn
) = 1;
5440 tsize_rtx
= tmp_rtx
;
5444 insn
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5447 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5450 RTX_FRAME_RELATED_P (insn
) = 1;
5453 save_restore_insns (TRUE
, tmp_rtx
, tsize
, (FILE *)0);
5455 if (frame_pointer_needed
)
5460 insn
= emit_insn (gen_movdi (frame_pointer_rtx
, stack_pointer_rtx
));
5462 insn
= emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
5464 RTX_FRAME_RELATED_P (insn
) = 1;
5467 if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
)
5468 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0)));
5471 /* If we are profiling, make sure no instructions are scheduled before
5472 the call to mcount. */
5474 if (profile_flag
|| profile_block_flag
)
5475 emit_insn (gen_blockage ());
5479 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
5481 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5482 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5485 function_epilogue (file
, size
)
5491 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5492 char *t1_str
= reg_names
[MIPS_TEMP1_REGNUM
];
5493 rtx epilogue_delay
= current_function_epilogue_delay_list
;
5494 int noreorder
= (epilogue_delay
!= 0);
5495 int noepilogue
= FALSE
;
5496 int load_nop
= FALSE
;
5498 rtx tmp_rtx
= (rtx
)0;
5502 /* The epilogue does not depend on any registers, but the stack
5503 registers, so we assume that if we have 1 pending nop, it can be
5504 ignored, and 2 it must be filled (2 nops occur for integer
5505 multiply and divide). */
5507 if (dslots_number_nops
> 0)
5509 if (dslots_number_nops
== 1)
5511 dslots_number_nops
= 0;
5512 dslots_load_filled
++;
5516 while (--dslots_number_nops
> 0)
5517 fputs ("\t#nop\n", asm_out_file
);
5524 fputs ("\t.set\tat\n", file
);
5525 error ("internal gcc error: .set noat left on in epilogue");
5528 if (set_nomacro
!= 0)
5531 fputs ("\t.set\tmacro\n", file
);
5532 error ("internal gcc error: .set nomacro left on in epilogue");
5535 if (set_noreorder
!= 0)
5538 fputs ("\t.set\treorder\n", file
);
5539 error ("internal gcc error: .set noreorder left on in epilogue");
5542 if (set_volatile
!= 0)
5545 fprintf (file
, "\t%s.set\tnovolatile\n", (TARGET_MIPS_AS
) ? "" : "#");
5546 error ("internal gcc error: .set volatile left on in epilogue");
5549 size
= MIPS_STACK_ALIGN (size
);
5550 tsize
= (!current_frame_info
.initialized
)
5551 ? compute_frame_size (size
)
5552 : current_frame_info
.total_size
;
5554 if (tsize
== 0 && epilogue_delay
== 0)
5556 rtx insn
= get_last_insn ();
5558 /* If the last insn was a BARRIER, we don't have to write any code
5559 because a jump (aka return) was put there. */
5560 if (GET_CODE (insn
) == NOTE
)
5561 insn
= prev_nonnote_insn (insn
);
5562 if (insn
&& GET_CODE (insn
) == BARRIER
)
5570 /* In the reload sequence, we don't need to fill the load delay
5571 slots for most of the loads, also see if we can fill the final
5572 delay slot if not otherwise filled by the reload sequence. */
5575 fprintf (file
, "\t.set\tnoreorder\n");
5579 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n", t1_str
, (long)tsize
, (long)tsize
);
5580 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5583 if (frame_pointer_needed
)
5584 fprintf (file
, "\tmove\t%s,%s\t\t\t# sp not trusted here\n",
5585 sp_str
, reg_names
[FRAME_POINTER_REGNUM
]);
5587 save_restore_insns (FALSE
, tmp_rtx
, tsize
, file
);
5589 load_only_r31
= (((current_frame_info
.mask
5590 & ~ (TARGET_ABICALLS
&& mips_abi
== ABI_32
5591 ? PIC_OFFSET_TABLE_MASK
: 0))
5593 && current_frame_info
.fmask
== 0);
5597 /* If the only register saved is the return address, we need a
5598 nop, unless we have an instruction to put into it. Otherwise
5599 we don't since reloading multiple registers doesn't reference
5600 the register being loaded. */
5605 final_scan_insn (XEXP (epilogue_delay
, 0),
5609 1); /* nopeepholes */
5612 fprintf (file
, "\tnop\n");
5617 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5620 fprintf (file
, "\t%s\t%s,%s,%s\n",
5621 TARGET_LONG64
? "daddu" : "addu",
5622 sp_str
, sp_str
, t1_str
);
5625 fprintf (file
, "\t%s\t%s,%s,%d\n",
5626 TARGET_LONG64
? "daddu" : "addu",
5627 sp_str
, sp_str
, tsize
);
5629 else if (!load_only_r31
&& epilogue_delay
!= 0)
5630 final_scan_insn (XEXP (epilogue_delay
, 0),
5634 1); /* nopeepholes */
5636 fprintf (file
, "\t.set\treorder\n");
5642 fprintf (file
, "\t%s\t%s,%s,%s\n",
5643 TARGET_LONG64
? "daddu" : "addu",
5644 sp_str
, sp_str
, t1_str
);
5647 fprintf (file
, "\t%s\t%s,%s,%d\n",
5648 TARGET_LONG64
? "daddu" : "addu",
5649 sp_str
, sp_str
, tsize
);
5651 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5655 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5656 /* Get the function name the same way that toplev.c does before calling
5657 assemble_start_function. This is needed so that the name used here
5658 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5659 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5661 fputs ("\t.end\t", file
);
5662 assemble_name (file
, fnname
);
5668 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
5669 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
5670 int num_regs
= num_gp_regs
+ num_fp_regs
;
5671 char *name
= fnname
;
5676 dslots_load_total
+= num_regs
;
5679 dslots_jump_total
++;
5683 dslots_load_filled
+= num_regs
;
5685 /* If the only register saved is the return register, we
5686 can't fill this register's delay slot. */
5688 if (load_only_r31
&& epilogue_delay
== 0)
5689 dslots_load_filled
--;
5691 if (tsize
> 0 || (!load_only_r31
&& epilogue_delay
!= 0))
5692 dslots_jump_filled
++;
5696 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5698 (frame_pointer_needed
) ? 'y' : 'n',
5699 ((current_frame_info
.mask
& RA_MASK
) != 0) ? 'n' : 'y',
5700 (current_function_calls_alloca
) ? 'y' : 'n',
5701 (current_function_calls_setjmp
) ? 'y' : 'n',
5702 (long)current_frame_info
.total_size
,
5703 (long)current_function_outgoing_args_size
,
5704 num_gp_regs
, num_fp_regs
,
5705 dslots_load_total
, dslots_load_filled
,
5706 dslots_jump_total
, dslots_jump_filled
,
5707 num_refs
[0], num_refs
[1], num_refs
[2]);
5709 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
5711 fprintf (stderr
, " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
5712 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
5715 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
5717 fprintf (stderr
, " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
5718 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
5721 fputc ('\n', stderr
);
5724 /* Reset state info for each function. */
5725 inside_function
= FALSE
;
5726 ignore_line_number
= FALSE
;
5727 dslots_load_total
= 0;
5728 dslots_jump_total
= 0;
5729 dslots_load_filled
= 0;
5730 dslots_jump_filled
= 0;
5734 mips_load_reg
= (rtx
)0;
5735 mips_load_reg2
= (rtx
)0;
5736 current_frame_info
= zero_frame_info
;
5738 /* Restore the output file if optimizing the GP (optimizing the GP causes
5739 the text to be diverted to a tempfile, so that data decls come before
5740 references to the data). */
5743 asm_out_file
= asm_out_data_file
;
5747 /* Expand the epilogue into a bunch of separate insns. */
5750 mips_expand_epilogue ()
5752 long tsize
= current_frame_info
.total_size
;
5753 rtx tsize_rtx
= GEN_INT (tsize
);
5754 rtx tmp_rtx
= (rtx
)0;
5758 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5759 emit_move_insn (tmp_rtx
, tsize_rtx
);
5760 tsize_rtx
= tmp_rtx
;
5765 if (frame_pointer_needed
)
5768 emit_insn (gen_movdi (stack_pointer_rtx
, frame_pointer_rtx
));
5770 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
5773 save_restore_insns (FALSE
, tmp_rtx
, tsize
, (FILE *)0);
5776 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5779 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5783 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
, GP_REG_FIRST
+31)));
5787 /* Define the number of delay slots needed for the function epilogue.
5789 On the mips, we need a slot if either no stack has been allocated,
5790 or the only register saved is the return register. */
5793 mips_epilogue_delay_slots ()
5795 if (!current_frame_info
.initialized
)
5796 (void) compute_frame_size (get_frame_size ());
5798 if (current_frame_info
.total_size
== 0)
5801 if (current_frame_info
.mask
== RA_MASK
&& current_frame_info
.fmask
== 0)
5808 /* Return true if this function is known to have a null epilogue.
5809 This allows the optimizer to omit jumps to jumps if no stack
5813 simple_epilogue_p ()
5815 if (!reload_completed
)
5818 if (current_frame_info
.initialized
)
5819 return current_frame_info
.total_size
== 0;
5821 return (compute_frame_size (get_frame_size ())) == 0;
5824 /* Choose the section to use for the constant rtx expression X that has
5827 mips_select_rtx_section (mode
, x
)
5828 enum machine_mode mode
;
5831 if (TARGET_EMBEDDED_DATA
)
5833 /* For embedded applications, always put constants in read-only data,
5834 in order to reduce RAM usage. */
5835 READONLY_DATA_SECTION ();
5839 /* For hosted applications, always put constants in small data if
5840 possible, as this gives the best performance. */
5842 if (GET_MODE_SIZE (mode
) <= mips_section_threshold
5843 && mips_section_threshold
> 0)
5844 SMALL_DATA_SECTION ();
5846 READONLY_DATA_SECTION ();
5850 /* Choose the section to use for DECL. RELOC is true if its value contains
5851 any relocatable expression. */
5853 mips_select_section (decl
, reloc
)
5857 int size
= int_size_in_bytes (TREE_TYPE (decl
));
5859 if (TARGET_EMBEDDED_PIC
5860 && TREE_CODE (decl
) == STRING_CST
5861 && !flag_writable_strings
)
5863 /* For embedded position independent code, put constant strings
5864 in the text section, because the data section is limited to
5869 else if (TARGET_EMBEDDED_DATA
)
5871 /* For embedded applications, always put an object in read-only data
5872 if possible, in order to reduce RAM usage. */
5874 if (((TREE_CODE (decl
) == VAR_DECL
5875 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5876 && DECL_INITIAL (decl
)
5877 && (DECL_INITIAL (decl
) == error_mark_node
5878 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5879 /* Deal with calls from output_constant_def_contents. */
5880 || (TREE_CODE (decl
) != VAR_DECL
5881 && (TREE_CODE (decl
) != STRING_CST
5882 || !flag_writable_strings
)))
5883 && ! (flag_pic
&& reloc
))
5884 READONLY_DATA_SECTION ();
5885 else if (size
> 0 && size
<= mips_section_threshold
)
5886 SMALL_DATA_SECTION ();
5892 /* For hosted applications, always put an object in small data if
5893 possible, as this gives the best performance. */
5895 if (size
> 0 && size
<= mips_section_threshold
)
5896 SMALL_DATA_SECTION ();
5897 else if (((TREE_CODE (decl
) == VAR_DECL
5898 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5899 && DECL_INITIAL (decl
)
5900 && (DECL_INITIAL (decl
) == error_mark_node
5901 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5902 /* Deal with calls from output_constant_def_contents. */
5903 || (TREE_CODE (decl
) != VAR_DECL
5904 && (TREE_CODE (decl
) != STRING_CST
5905 || !flag_writable_strings
)))
5906 && ! (flag_pic
&& reloc
))
5907 READONLY_DATA_SECTION ();
5913 #ifdef MIPS_ABI_DEFAULT
5914 /* Support functions for the 64 bit ABI. */
5916 /* Return register to use for a function return value with VALTYPE for function
5920 mips_function_value (valtype
, func
)
5924 int reg
= GP_RETURN
;
5925 enum machine_mode mode
= TYPE_MODE (valtype
);
5926 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5928 /* ??? How should we return complex float? */
5929 if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5931 if (TARGET_SINGLE_FLOAT
5932 && (mclass
== MODE_FLOAT
5933 ? GET_MODE_SIZE (mode
) > 4
5934 : GET_MODE_SIZE (mode
) / 2 > 4))
5939 else if (TREE_CODE (valtype
) == RECORD_TYPE
5940 && mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
5942 /* A struct with only one or two floating point fields is returned in
5943 the floating point registers. */
5944 tree field
, fields
[2];
5947 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
5948 field
= TREE_CHAIN (field
))
5950 if (TREE_CODE (field
) != FIELD_DECL
)
5952 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
5955 fields
[i
++] = field
;
5958 /* Must check i, so that we reject structures with no elements. */
5963 /* The structure has DImode, but we don't allow DImode values
5964 in FP registers, so we use a PARALLEL even though it isn't
5965 strictly necessary. */
5966 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
5968 return gen_rtx (PARALLEL
, mode
,
5970 gen_rtx (EXPR_LIST
, VOIDmode
,
5971 gen_rtx (REG
, field_mode
, FP_RETURN
),
5976 enum machine_mode first_mode
5977 = TYPE_MODE (TREE_TYPE (fields
[0]));
5978 enum machine_mode second_mode
5979 = TYPE_MODE (TREE_TYPE (fields
[1]));
5981 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[0]));
5983 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[1]));
5985 return gen_rtx (PARALLEL
, mode
,
5987 gen_rtx (EXPR_LIST
, VOIDmode
,
5988 gen_rtx (REG
, first_mode
, FP_RETURN
),
5989 GEN_INT (first_offset
/ BITS_PER_UNIT
)),
5990 gen_rtx (EXPR_LIST
, VOIDmode
,
5991 gen_rtx (REG
, second_mode
, FP_RETURN
+ 2),
5992 GEN_INT (second_offset
/ BITS_PER_UNIT
))));
5997 return gen_rtx (REG
, mode
, reg
);
6000 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
6001 nonzero when an argument must be passed by reference. */
6004 function_arg_pass_by_reference (cum
, mode
, type
, named
)
6005 CUMULATIVE_ARGS
*cum
;
6006 enum machine_mode mode
;
6012 if (mips_abi
!= ABI_EABI
)
6015 /* ??? How should SCmode be handled? */
6016 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
6019 size
= int_size_in_bytes (type
);
6020 return size
== -1 || size
> UNITS_PER_WORD
;
6025 /* This function returns the register class required for a secondary
6026 register when copying between one of the registers in CLASS, and X,
6027 using MODE. If IN_P is nonzero, the copy is going from X to the
6028 register, otherwise the register is the source. A return value of
6029 NO_REGS means that no secondary register is required. */
6032 mips_secondary_reload_class (class, mode
, x
, in_p
)
6033 enum reg_class
class;
6034 enum machine_mode mode
;
6040 if (GET_CODE (x
) == SIGN_EXTEND
)
6046 /* We may be called with reg_renumber NULL from regclass.
6047 ??? This is probably a bug. */
6049 regno
= true_regnum (x
);
6052 while (GET_CODE (x
) == SUBREG
)
6054 off
+= SUBREG_WORD (x
);
6057 if (GET_CODE (x
) == REG
)
6058 regno
= REGNO (x
) + off
;
6061 else if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
6062 regno
= true_regnum (x
);
6064 /* We always require a general register when copying anything to
6065 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
6066 to a general register, or when copying from register 0. */
6067 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
6071 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
6075 if (regno
== HILO_REGNUM
)
6079 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
6084 /* Copying from HI or LO to anywhere other than a general register
6085 requires a general register. */
6086 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
6088 if (GP_REG_P (regno
))
6092 if (MD_REG_P (regno
))
6094 if (class == GR_REGS
)
6099 /* We can only copy a value to a condition code register from a
6100 floating point register, and even then we require a scratch
6101 floating point register. We can only copy a value out of a
6102 condition code register into a general register. */
6103 if (class == ST_REGS
)
6107 if (GP_REG_P (regno
))
6111 if (ST_REG_P (regno
))
6115 if (class == GR_REGS
)