1 /* Subroutines for insn-output.c for MIPS
2 Contributed by A. Lichnewsky, lich@inria.inria.fr.
3 Changes by Michael Meissner, meissner@osf.org.
4 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
5 Brendan Eich, brendan@microunity.com.
6 Copyright (C) 1989, 1990, 1991, 1993, 1994 Free Software Foundation, Inc.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
24 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
25 calling convention in 64 bit mode. It doesn't work though, and should
26 be replaced with something better designed. */
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "insn-flags.h"
36 #include "insn-attr.h"
37 #include "insn-codes.h"
41 #undef MAX /* sys/param.h may also define these */
46 #include <sys/types.h>
59 #if defined(USG) || defined(NO_STAB_H)
60 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
62 #include <stab.h> /* On BSD, use the system's stab.h. */
66 #define STAB_CODE_TYPE enum __stab_debug_code
68 #define STAB_CODE_TYPE int
73 extern char *getenv ();
74 extern char *mktemp ();
76 extern rtx
adj_offsettable_operand ();
77 extern rtx
copy_to_reg ();
80 extern tree
lookup_name ();
81 extern void pfatal_with_name ();
82 extern void warning ();
84 extern tree current_function_decl
;
85 extern FILE *asm_out_file
;
87 /* Enumeration for all of the relational tests, so that we can build
88 arrays indexed by the test type, and not worry about the order
105 /* Global variables for machine-dependent things. */
107 /* Threshold for data being put into the small data/bss area, instead
108 of the normal data area (references to the small data/bss area take
109 1 instruction, and use the global pointer, references to the normal
110 data area takes 2 instructions). */
111 int mips_section_threshold
= -1;
113 /* Count the number of .file directives, so that .loc is up to date. */
114 int num_source_filenames
= 0;
116 /* Count the number of sdb related labels are generated (to find block
117 start and end boundaries). */
118 int sdb_label_count
= 0;
120 /* Next label # for each statment for Silicon Graphics IRIS systems. */
123 /* Non-zero if inside of a function, because the stupid MIPS asm can't
124 handle .files inside of functions. */
125 int inside_function
= 0;
127 /* Files to separate the text and the data output, so that all of the data
128 can be emitted before the text, which will mean that the assembler will
129 generate smaller code, based on the global pointer. */
130 FILE *asm_out_data_file
;
131 FILE *asm_out_text_file
;
133 /* Linked list of all externals that are to be emitted when optimizing
134 for the global pointer if they haven't been declared by the end of
135 the program with an appropriate .comm or initialization. */
138 struct extern_list
*next
; /* next external */
139 char *name
; /* name of the external */
140 int size
; /* size in bytes */
143 /* Name of the file containing the current function. */
144 char *current_function_file
= "";
146 /* Warning given that Mips ECOFF can't support changing files
147 within a function. */
148 int file_in_function_warning
= FALSE
;
150 /* Whether to suppress issuing .loc's because the user attempted
151 to change the filename within a function. */
152 int ignore_line_number
= FALSE
;
154 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
160 /* The next branch instruction is a branch likely, not branch normal. */
161 int mips_branch_likely
;
163 /* Count of delay slots and how many are filled. */
164 int dslots_load_total
;
165 int dslots_load_filled
;
166 int dslots_jump_total
;
167 int dslots_jump_filled
;
169 /* # of nops needed by previous insn */
170 int dslots_number_nops
;
172 /* Number of 1/2/3 word references to data items (ie, not jal's). */
175 /* registers to check for load delay */
176 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
178 /* Cached operands, and operator to compare for use in set/branch on
182 /* what type of branch to use */
183 enum cmp_type branch_type
;
185 /* Number of previously seen half-pic pointers and references. */
186 static int prev_half_pic_ptrs
= 0;
187 static int prev_half_pic_refs
= 0;
189 /* which cpu are we scheduling for */
190 enum processor_type mips_cpu
;
192 /* which instruction set architecture to use. */
195 /* Strings to hold which cpu and instruction set architecture to use. */
196 char *mips_cpu_string
; /* for -mcpu=<xxx> */
197 char *mips_isa_string
; /* for -mips{1,2,3} */
199 /* Generating calls to position independent functions? */
200 enum mips_abicalls_type mips_abicalls
;
202 /* High and low marks for floating point values which we will accept
203 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
204 initialized in override_options. */
205 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
207 /* Array giving truth value on whether or not a given hard register
208 can support a given mode. */
209 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
211 /* Current frame information calculated by compute_frame_size. */
212 struct mips_frame_info current_frame_info
;
214 /* Zero structure to initialize current_frame_info. */
215 struct mips_frame_info zero_frame_info
;
217 /* Temporary filename used to buffer .text until end of program
219 static char *temp_filename
;
221 /* Pseudo-reg holding the address of the current function when
222 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
223 by mips_finalize_pic if it was created. */
224 rtx embedded_pic_fnaddr_rtx
;
226 /* List of all MIPS punctuation characters used by print_operand. */
227 char mips_print_operand_punct
[256];
229 /* Map GCC register number to debugger register number. */
230 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
232 /* Buffer to use to enclose a load/store operation with %{ %} to
233 turn on .set volatile. */
234 static char volatile_buffer
[60];
236 /* Hardware names for the registers. If -mrnames is used, this
237 will be overwritten with mips_sw_reg_names. */
239 char mips_reg_names
[][8] =
241 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
242 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
243 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
244 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
245 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
246 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
247 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
248 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
252 /* Mips software names for the registers, used to overwrite the
253 mips_reg_names array. */
255 char mips_sw_reg_names
[][8] =
257 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
258 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
259 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
260 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
261 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
262 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
263 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
264 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
268 /* Map hard register number to register class */
269 enum reg_class mips_regno_to_class
[] =
271 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
272 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
273 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
274 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
275 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
276 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
277 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
278 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
279 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
280 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
281 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
282 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
283 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
284 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
285 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
286 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
287 HI_REG
, LO_REG
, ST_REGS
290 /* Map register constraint character to register class. */
291 enum reg_class mips_char_to_class
[256] =
293 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
294 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
295 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
296 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
297 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
298 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
299 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
300 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
301 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
302 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
303 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
304 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
305 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
306 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
307 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
308 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
309 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
310 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
311 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
312 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
313 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
314 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
315 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
316 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
317 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
318 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
319 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
320 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
321 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
322 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
323 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
324 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
325 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
326 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
327 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
328 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
329 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
330 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
331 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
332 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
333 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
334 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
335 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
336 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
337 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
338 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
339 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
340 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
341 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
342 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
343 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
344 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
345 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
346 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
347 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
348 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
349 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
350 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
351 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
352 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
353 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
354 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
355 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
356 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
360 /* Return truth value of whether OP can be used as an operands
361 where a register or 16 bit unsigned integer is needed. */
364 uns_arith_operand (op
, mode
)
366 enum machine_mode mode
;
368 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
371 return register_operand (op
, mode
);
374 /* Return truth value of whether OP can be used as an operands
375 where a 16 bit integer is needed */
378 arith_operand (op
, mode
)
380 enum machine_mode mode
;
382 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
385 return register_operand (op
, mode
);
388 /* Return truth value of whether OP can be used as an operand in a two
389 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
392 arith32_operand (op
, mode
)
394 enum machine_mode mode
;
396 if (GET_CODE (op
) == CONST_INT
)
399 return register_operand (op
, mode
);
402 /* Return truth value of whether OP is a integer which fits in 16 bits */
407 enum machine_mode mode
;
409 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
412 /* Return truth value of whether OP is an integer which is too big to
413 be loaded with one instruction. */
418 enum machine_mode mode
;
422 if (GET_CODE (op
) != CONST_INT
)
426 if ((value
& ~0x0000ffff) == 0) /* ior reg,$r0,value */
429 if (((unsigned long)(value
+ 32768)) <= 32767) /* subu reg,$r0,value */
432 if ((value
& 0x0000ffff) == 0 /* lui reg,value>>16 */
433 && ((value
& ~2147483647) == 0 /* signed value */
434 || (value
& ~2147483647) == ~2147483647))
440 /* Return truth value of whether OP is a register or the constant 0. */
443 reg_or_0_operand (op
, mode
)
445 enum machine_mode mode
;
447 switch (GET_CODE (op
))
453 return (INTVAL (op
) == 0);
456 if (op
!= CONST0_RTX (mode
))
463 return register_operand (op
, mode
);
469 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
472 mips_const_double_ok (op
, mode
)
474 enum machine_mode mode
;
478 if (GET_CODE (op
) != CONST_DOUBLE
)
481 if (mode
== VOIDmode
)
484 if (mode
!= SFmode
&& mode
!= DFmode
)
487 if (op
== CONST0_RTX (mode
))
490 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
492 if (REAL_VALUE_ISNAN (d
))
495 if (REAL_VALUE_NEGATIVE (d
))
496 d
= REAL_VALUE_NEGATE (d
);
500 if (REAL_VALUES_LESS (d
, dfhigh
)
501 && REAL_VALUES_LESS (dflow
, d
))
506 if (REAL_VALUES_LESS (d
, sfhigh
)
507 && REAL_VALUES_LESS (sflow
, d
))
514 /* Return truth value if a memory operand fits in a single instruction
515 (ie, register + small offset). */
518 simple_memory_operand (op
, mode
)
520 enum machine_mode mode
;
522 rtx addr
, plus0
, plus1
;
524 /* Eliminate non-memory operations */
525 if (GET_CODE (op
) != MEM
)
528 /* dword operations really put out 2 instructions, so eliminate them. */
529 if (GET_MODE_SIZE (GET_MODE (op
)) > UNITS_PER_WORD
)
532 /* Decode the address now. */
534 switch (GET_CODE (addr
))
543 return SMALL_INT (op
);
546 plus0
= XEXP (addr
, 0);
547 plus1
= XEXP (addr
, 1);
548 if (GET_CODE (plus0
) == REG
549 && GET_CODE (plus1
) == CONST_INT
550 && SMALL_INT (plus1
))
553 else if (GET_CODE (plus1
) == REG
554 && GET_CODE (plus0
) == CONST_INT
555 && SMALL_INT (plus0
))
562 /* We used to allow small symbol refs here (ie, stuff in .sdata
563 or .sbss), but this causes some bugs in G++. Also, it won't
564 interfere if the MIPS linker rewrites the store instruction
565 because the function is PIC. */
567 case LABEL_REF
: /* never gp relative */
571 /* If -G 0, we can never have a GP relative memory operation.
572 Also, save some time if not optimizing. */
577 rtx offset
= const0_rtx
;
578 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
579 if (GET_CODE (op
) != SYMBOL_REF
)
582 /* let's be paranoid.... */
583 if (! SMALL_INT (offset
))
589 return SYMBOL_REF_FLAG (addr
);
596 /* Return true if the code of this rtx pattern is EQ or NE. */
599 equality_op (op
, mode
)
601 enum machine_mode mode
;
603 if (mode
!= GET_MODE (op
))
606 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
609 /* Return true if the code is a relational operations (EQ, LE, etc.) */
614 enum machine_mode mode
;
616 if (mode
!= GET_MODE (op
))
619 return (GET_RTX_CLASS (GET_CODE (op
)) == '<');
622 /* Return true if the operand is either the PC or a label_ref. */
625 pc_or_label_operand (op
, mode
)
627 enum machine_mode mode
;
632 if (GET_CODE (op
) == LABEL_REF
)
638 /* Test for a valid operand for a call instruction.
639 Don't allow the arg pointer register or virtual regs
640 since they may change into reg + const, which the patterns
644 call_insn_operand (op
, mode
)
646 enum machine_mode mode
;
648 if (GET_CODE (op
) == MEM
649 && (CONSTANT_ADDRESS_P (XEXP (op
, 0))
650 || (GET_CODE (XEXP (op
, 0)) == REG
651 && XEXP (op
, 0) != arg_pointer_rtx
652 && !(REGNO (XEXP (op
, 0)) >= FIRST_PSEUDO_REGISTER
653 && REGNO (XEXP (op
, 0)) <= LAST_VIRTUAL_REGISTER
))))
658 /* Returns an operand string for the given instruction's delay slot,
659 after updating filled delay slot statistics.
661 We assume that operands[0] is the target register that is set.
663 In order to check the next insn, most of this functionality is moved
664 to FINAL_PRESCAN_INSN, and we just set the global variables that
667 /* ??? This function no longer does anything useful, because final_prescan_insn
668 now will never emit a nop. */
671 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
672 char *ret
; /* normal string to return */
673 enum delay_type type
; /* type of delay */
674 rtx operands
[]; /* operands to use */
675 rtx cur_insn
; /* current insn */
677 register rtx set_reg
;
678 register enum machine_mode mode
;
679 register rtx next_insn
= (cur_insn
) ? NEXT_INSN (cur_insn
) : (rtx
)0;
680 register int num_nops
;
682 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
685 else if (type
== DELAY_HILO
)
691 /* Make sure that we don't put nop's after labels. */
692 next_insn
= NEXT_INSN (cur_insn
);
693 while (next_insn
!= (rtx
)0 && GET_CODE (next_insn
) == NOTE
)
694 next_insn
= NEXT_INSN (next_insn
);
696 dslots_load_total
+= num_nops
;
697 if (TARGET_DEBUG_F_MODE
699 || type
== DELAY_NONE
700 || operands
== (rtx
*)0
701 || cur_insn
== (rtx
)0
702 || next_insn
== (rtx
)0
703 || GET_CODE (next_insn
) == CODE_LABEL
704 || (set_reg
= operands
[0]) == (rtx
)0)
706 dslots_number_nops
= 0;
707 mips_load_reg
= (rtx
)0;
708 mips_load_reg2
= (rtx
)0;
709 mips_load_reg3
= (rtx
)0;
710 mips_load_reg4
= (rtx
)0;
714 set_reg
= operands
[0];
715 if (set_reg
== (rtx
)0)
718 while (GET_CODE (set_reg
) == SUBREG
)
719 set_reg
= SUBREG_REG (set_reg
);
721 mode
= GET_MODE (set_reg
);
722 dslots_number_nops
= num_nops
;
723 mips_load_reg
= set_reg
;
724 if (GET_MODE_SIZE (mode
)
725 > (FP_REG_P (set_reg
) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
726 mips_load_reg2
= gen_rtx (REG
, SImode
, REGNO (set_reg
) + 1);
730 if (type
== DELAY_HILO
)
732 mips_load_reg3
= gen_rtx (REG
, SImode
, MD_REG_FIRST
);
733 mips_load_reg4
= gen_rtx (REG
, SImode
, MD_REG_FIRST
+1);
745 /* Determine whether a memory reference takes one (based off of the GP pointer),
746 two (normal), or three (label + reg) instructions, and bump the appropriate
747 counter for -mstats. */
750 mips_count_memory_refs (op
, num
)
756 rtx addr
, plus0
, plus1
;
757 enum rtx_code code0
, code1
;
760 if (TARGET_DEBUG_B_MODE
)
762 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
766 /* Skip MEM if passed, otherwise handle movsi of address. */
767 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
769 /* Loop, going through the address RTL */
773 switch (GET_CODE (addr
))
783 plus0
= XEXP (addr
, 0);
784 plus1
= XEXP (addr
, 1);
785 code0
= GET_CODE (plus0
);
786 code1
= GET_CODE (plus1
);
796 if (code0
== CONST_INT
)
811 if (code1
== CONST_INT
)
818 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
825 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
835 n_words
= 2; /* always 2 words */
839 addr
= XEXP (addr
, 0);
844 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
853 n_words
+= additional
;
857 num_refs
[n_words
-1] += num
;
861 /* Return RTL for the offset from the current function to the
865 embedded_pic_offset (x
)
868 if (embedded_pic_fnaddr_rtx
== NULL
)
869 embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
870 return gen_rtx (CONST
, Pmode
,
871 gen_rtx (MINUS
, Pmode
, x
,
872 XEXP (DECL_RTL (current_function_decl
), 0)));
875 /* Return the appropriate instructions to move one operand to another. */
878 mips_move_1word (operands
, insn
, unsignedp
)
884 rtx op0
= operands
[0];
885 rtx op1
= operands
[1];
886 enum rtx_code code0
= GET_CODE (op0
);
887 enum rtx_code code1
= GET_CODE (op1
);
888 enum machine_mode mode
= GET_MODE (op0
);
889 int subreg_word0
= 0;
890 int subreg_word1
= 0;
891 enum delay_type delay
= DELAY_NONE
;
893 while (code0
== SUBREG
)
895 subreg_word0
+= SUBREG_WORD (op0
);
896 op0
= SUBREG_REG (op0
);
897 code0
= GET_CODE (op0
);
900 while (code1
== SUBREG
)
902 subreg_word1
+= SUBREG_WORD (op1
);
903 op1
= SUBREG_REG (op1
);
904 code1
= GET_CODE (op1
);
909 int regno0
= REGNO (op0
) + subreg_word0
;
913 int regno1
= REGNO (op1
) + subreg_word1
;
915 /* Just in case, don't do anything for assigning a register
916 to itself, unless we are filling a delay slot. */
917 if (regno0
== regno1
&& set_nomacro
== 0)
920 else if (GP_REG_P (regno0
))
922 if (GP_REG_P (regno1
))
925 else if (MD_REG_P (regno1
))
934 if (FP_REG_P (regno1
))
937 else if (regno1
== FPSW_REGNUM
)
938 ret
= "cfc1\t%0,$31";
942 else if (FP_REG_P (regno0
))
944 if (GP_REG_P (regno1
))
950 if (FP_REG_P (regno1
))
951 ret
= "mov.s\t%0,%1";
954 else if (MD_REG_P (regno0
))
956 if (GP_REG_P (regno1
))
963 else if (regno0
== FPSW_REGNUM
)
965 if (GP_REG_P (regno1
))
968 ret
= "ctc1\t%0,$31";
973 else if (code1
== MEM
)
978 mips_count_memory_refs (op1
, 1);
980 if (GP_REG_P (regno0
))
982 /* For loads, use the mode of the memory item, instead of the
983 target, so zero/sign extend can use this code as well. */
984 switch (GET_MODE (op1
))
992 ret
= ((unsignedp
&& TARGET_64BIT
)
997 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
1000 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
1005 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
1008 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1010 int i
= strlen (ret
);
1011 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1014 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1015 ret
= volatile_buffer
;
1019 else if (code1
== CONST_INT
1020 || (code1
== CONST_DOUBLE
1021 && GET_MODE (op1
) == VOIDmode
))
1023 if (code1
== CONST_DOUBLE
)
1025 /* This can happen when storing constants into long long
1026 bitfields. Just store the least significant word of
1028 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
1031 if (INTVAL (op1
) == 0)
1033 if (GP_REG_P (regno0
))
1034 ret
= "move\t%0,%z1";
1036 else if (FP_REG_P (regno0
))
1039 ret
= "mtc1\t%z1,%0";
1043 else if (GP_REG_P (regno0
))
1044 ret
= (INTVAL (op1
) < 0) ? "li\t%0,%1\t\t\t# %X1" : "li\t%0,%X1\t\t# %1";
1047 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
1049 if (op1
== CONST0_RTX (SFmode
))
1051 if (GP_REG_P (regno0
))
1052 ret
= "move\t%0,%.";
1054 else if (FP_REG_P (regno0
))
1057 ret
= "mtc1\t%.,%0";
1064 ret
= "li.s\t%0,%1";
1068 else if (code1
== LABEL_REF
)
1071 mips_count_memory_refs (op1
, 1);
1076 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
1078 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
1080 rtx offset
= const0_rtx
;
1082 if (GET_CODE (op1
) == CONST
)
1083 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
1085 if (GET_CODE (op1
) == SYMBOL_REF
)
1087 operands
[2] = HALF_PIC_PTR (op1
);
1090 mips_count_memory_refs (operands
[2], 1);
1092 if (INTVAL (offset
) == 0)
1095 ret
= (unsignedp
&& TARGET_64BIT
1101 dslots_load_total
++;
1102 operands
[3] = offset
;
1103 if (unsignedp
&& TARGET_64BIT
)
1104 ret
= (SMALL_INT (offset
))
1105 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1106 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1108 ret
= (SMALL_INT (offset
))
1109 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1110 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1117 mips_count_memory_refs (op1
, 1);
1123 else if (code1
== PLUS
)
1125 rtx add_op0
= XEXP (op1
, 0);
1126 rtx add_op1
= XEXP (op1
, 1);
1128 if (GET_CODE (XEXP (op1
, 1)) == REG
&& GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
1130 add_op0
= XEXP (op1
, 1); /* reverse operands */
1131 add_op1
= XEXP (op1
, 0);
1134 operands
[2] = add_op0
;
1135 operands
[3] = add_op1
;
1136 ret
= "add%:\t%0,%2,%3";
1140 else if (code0
== MEM
)
1143 mips_count_memory_refs (op0
, 1);
1147 int regno1
= REGNO (op1
) + subreg_word1
;
1149 if (GP_REG_P (regno1
))
1154 case SFmode
: ret
= "sw\t%1,%0"; break;
1155 case SImode
: ret
= "sw\t%1,%0"; break;
1156 case HImode
: ret
= "sh\t%1,%0"; break;
1157 case QImode
: ret
= "sb\t%1,%0"; break;
1161 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
1165 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1170 case SFmode
: ret
= "sw\t%z1,%0"; break;
1171 case SImode
: ret
= "sw\t%z1,%0"; break;
1172 case HImode
: ret
= "sh\t%z1,%0"; break;
1173 case QImode
: ret
= "sb\t%z1,%0"; break;
1177 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
1182 case SFmode
: ret
= "sw\t%.,%0"; break;
1183 case SImode
: ret
= "sw\t%.,%0"; break;
1184 case HImode
: ret
= "sh\t%.,%0"; break;
1185 case QImode
: ret
= "sb\t%.,%0"; break;
1189 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1191 int i
= strlen (ret
);
1192 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1195 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1196 ret
= volatile_buffer
;
1200 if (ret
== (char *)0)
1202 abort_with_insn (insn
, "Bad move");
1206 if (delay
!= DELAY_NONE
)
1207 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1213 /* Return the appropriate instructions to move 2 words */
1216 mips_move_2words (operands
, insn
)
1221 rtx op0
= operands
[0];
1222 rtx op1
= operands
[1];
1223 enum rtx_code code0
= GET_CODE (operands
[0]);
1224 enum rtx_code code1
= GET_CODE (operands
[1]);
1225 int subreg_word0
= 0;
1226 int subreg_word1
= 0;
1227 enum delay_type delay
= DELAY_NONE
;
1229 while (code0
== SUBREG
)
1231 subreg_word0
+= SUBREG_WORD (op0
);
1232 op0
= SUBREG_REG (op0
);
1233 code0
= GET_CODE (op0
);
1236 while (code1
== SUBREG
)
1238 subreg_word1
+= SUBREG_WORD (op1
);
1239 op1
= SUBREG_REG (op1
);
1240 code1
= GET_CODE (op1
);
1245 int regno0
= REGNO (op0
) + subreg_word0
;
1249 int regno1
= REGNO (op1
) + subreg_word1
;
1251 /* Just in case, don't do anything for assigning a register
1252 to itself, unless we are filling a delay slot. */
1253 if (regno0
== regno1
&& set_nomacro
== 0)
1256 else if (FP_REG_P (regno0
))
1258 if (FP_REG_P (regno1
))
1259 ret
= "mov.d\t%0,%1";
1267 abort_with_insn (insn
, "Bad move");
1268 #ifdef TARGET_FP_CALL_32
1269 if (FP_CALL_GP_REG_P (regno1
))
1270 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1273 ret
= "dmtc1\t%1,%0";
1276 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1280 else if (FP_REG_P (regno1
))
1286 abort_with_insn (insn
, "Bad move");
1287 #ifdef TARGET_FP_CALL_32
1288 if (FP_CALL_GP_REG_P (regno0
))
1289 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1292 ret
= "dmfc1\t%0,%1";
1295 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1298 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
))
1304 ret
= "mthi\t%M1\n\tmtlo\t%L1";
1307 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
1313 ret
= "mfhi\t%M0\n\tmflo\t%L0";
1316 else if (TARGET_64BIT
)
1317 ret
= "move\t%0,%1";
1319 else if (regno0
!= (regno1
+1))
1320 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
1323 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
1326 else if (code1
== CONST_DOUBLE
)
1328 /* Move zero from $0 unless !TARGET_64BIT and recipient
1329 is 64-bit fp reg, in which case generate a constant. */
1330 if (op1
!= CONST0_RTX (GET_MODE (op1
))
1331 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
1333 if (GET_MODE (op1
) == DFmode
)
1336 #ifdef TARGET_FP_CALL_32
1337 if (FP_CALL_GP_REG_P (regno0
))
1339 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
1341 split_double (op1
, operands
+ 2, operands
+ 3);
1342 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1345 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1349 ret
= "li.d\t%0,%1";
1352 else if (TARGET_FLOAT64
)
1357 split_double (op1
, operands
+ 2, operands
+ 3);
1358 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1364 if (GP_REG_P (regno0
))
1366 #ifdef TARGET_FP_CALL_32
1367 && ! FP_CALL_GP_REG_P (regno0
)
1371 : "move\t%0,%.\n\tmove\t%D0,%.";
1373 else if (FP_REG_P (regno0
))
1376 ret
= (TARGET_64BIT
)
1378 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1383 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1385 if (GP_REG_P (regno0
))
1386 ret
= (TARGET_64BIT
)
1388 : "move\t%0,%.\n\tmove\t%D0,%.";
1390 else if (FP_REG_P (regno0
))
1393 ret
= (TARGET_64BIT
)
1397 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1401 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
&& GP_REG_P (regno0
))
1407 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
1408 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1412 else if (code1
== MEM
)
1417 mips_count_memory_refs (op1
, 2);
1419 if (FP_REG_P (regno0
))
1422 else if (TARGET_64BIT
)
1424 #ifdef TARGET_FP_CALL_32
1425 if (FP_CALL_GP_REG_P (regno0
))
1427 if (offsettable_address_p (FALSE
, SImode
, op1
))
1428 ret
= "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1430 ret
= "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1437 else if (offsettable_address_p (1, DFmode
, XEXP (op1
, 0)))
1439 operands
[2] = adj_offsettable_operand (op1
, 4);
1440 if (reg_mentioned_p (op0
, op1
))
1441 ret
= "lw\t%D0,%2\n\tlw\t%0,%1";
1443 ret
= "lw\t%0,%1\n\tlw\t%D0,%2";
1446 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1448 int i
= strlen (ret
);
1449 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1452 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1453 ret
= volatile_buffer
;
1457 else if (code1
== LABEL_REF
1458 || code1
== SYMBOL_REF
1463 return mips_move_1word (operands
, insn
, 0);
1467 else if (code0
== MEM
)
1471 int regno1
= REGNO (op1
) + subreg_word1
;
1473 if (FP_REG_P (regno1
))
1476 else if (TARGET_64BIT
)
1478 #ifdef TARGET_FP_CALL_32
1479 if (FP_CALL_GP_REG_P (regno1
))
1480 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1486 else if (offsettable_address_p (1, DFmode
, XEXP (op0
, 0)))
1488 operands
[2] = adj_offsettable_operand (op0
, 4);
1489 ret
= "sw\t%1,%0\n\tsw\t%D1,%2";
1493 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
1494 || (code1
== CONST_DOUBLE
1495 && op1
== CONST0_RTX (GET_MODE (op1
))))
1497 || offsettable_address_p (1, DFmode
, XEXP (op0
, 0))))
1503 operands
[2] = adj_offsettable_operand (op0
, 4);
1504 ret
= "sw\t%.,%0\n\tsw\t%.,%2";
1509 mips_count_memory_refs (op0
, 2);
1511 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1513 int i
= strlen (ret
);
1514 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1517 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1518 ret
= volatile_buffer
;
1522 if (ret
== (char *)0)
1524 abort_with_insn (insn
, "Bad move");
1528 if (delay
!= DELAY_NONE
)
1529 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1535 /* Provide the costs of an addressing mode that contains ADDR.
1536 If ADDR is not a valid address, its cost is irrelevant. */
1539 mips_address_cost (addr
)
1542 switch (GET_CODE (addr
))
1556 rtx offset
= const0_rtx
;
1557 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
1558 if (GET_CODE (addr
) == LABEL_REF
)
1561 if (GET_CODE (addr
) != SYMBOL_REF
)
1564 if (! SMALL_INT (offset
))
1570 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1574 register rtx plus0
= XEXP (addr
, 0);
1575 register rtx plus1
= XEXP (addr
, 1);
1577 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1579 plus0
= XEXP (addr
, 1);
1580 plus1
= XEXP (addr
, 0);
1583 if (GET_CODE (plus0
) != REG
)
1586 switch (GET_CODE (plus1
))
1592 return (SMALL_INT (plus1
) ? 1 : 2);
1599 return mips_address_cost (plus1
) + 1;
1607 /* Return true if X is an address which needs a temporary register when
1608 reloaded while generating PIC code. */
1611 pic_address_needs_scratch (x
)
1614 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1615 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1616 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1617 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1618 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1624 /* Make normal rtx_code into something we can index from an array */
1626 static enum internal_test
1627 map_test_to_internal_test (test_code
)
1628 enum rtx_code test_code
;
1630 enum internal_test test
= ITEST_MAX
;
1635 case EQ
: test
= ITEST_EQ
; break;
1636 case NE
: test
= ITEST_NE
; break;
1637 case GT
: test
= ITEST_GT
; break;
1638 case GE
: test
= ITEST_GE
; break;
1639 case LT
: test
= ITEST_LT
; break;
1640 case LE
: test
= ITEST_LE
; break;
1641 case GTU
: test
= ITEST_GTU
; break;
1642 case GEU
: test
= ITEST_GEU
; break;
1643 case LTU
: test
= ITEST_LTU
; break;
1644 case LEU
: test
= ITEST_LEU
; break;
1651 /* Generate the code to compare two integer values. The return value is:
1652 (reg:SI xx) The pseudo register the comparison is in
1653 (rtx)0 No register, generate a simple branch.
1655 ??? This is called with result nonzero by the Scond patterns in
1656 mips.md. These patterns are called with a target in the mode of
1657 the Scond instruction pattern. Since this must be a constant, we
1658 must use SImode. This means that if RESULT is non-zero, it will
1659 always be an SImode register, even if TARGET_64BIT is true. We
1660 cope with this by calling convert_move rather than emit_move_insn.
1661 This will sometimes lead to an unnecessary extension of the result;
1673 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
1674 enum rtx_code test_code
; /* relational test (EQ, etc) */
1675 rtx result
; /* result to store comp. or 0 if branch */
1676 rtx cmp0
; /* first operand to compare */
1677 rtx cmp1
; /* second operand to compare */
1678 int *p_invert
; /* NULL or ptr to hold whether branch needs */
1679 /* to reverse its test */
1682 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
1683 int const_low
; /* low bound of constant we can accept */
1684 int const_high
; /* high bound of constant we can accept */
1685 int const_add
; /* constant to add (convert LE -> LT) */
1686 int reverse_regs
; /* reverse registers in test */
1687 int invert_const
; /* != 0 if invert value if cmp1 is constant */
1688 int invert_reg
; /* != 0 if invert value if cmp1 is register */
1689 int unsignedp
; /* != 0 for unsigned comparisons. */
1692 static struct cmp_info info
[ (int)ITEST_MAX
] = {
1694 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
1695 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
1696 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
1697 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
1698 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
1699 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
1700 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
1701 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
1702 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
1703 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
1706 enum internal_test test
;
1707 enum machine_mode mode
;
1708 struct cmp_info
*p_info
;
1715 test
= map_test_to_internal_test (test_code
);
1716 if (test
== ITEST_MAX
)
1719 p_info
= &info
[ (int)test
];
1720 eqne_p
= (p_info
->test_code
== XOR
);
1722 mode
= GET_MODE (cmp0
);
1723 if (mode
== VOIDmode
)
1724 mode
= GET_MODE (cmp1
);
1726 /* Eliminate simple branches */
1727 branch_p
= (result
== (rtx
)0);
1730 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
1732 /* Comparisons against zero are simple branches */
1733 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
1736 /* Test for beq/bne. */
1741 /* allocate a pseudo to calculate the value in. */
1742 result
= gen_reg_rtx (mode
);
1745 /* Make sure we can handle any constants given to us. */
1746 if (GET_CODE (cmp0
) == CONST_INT
)
1747 cmp0
= force_reg (mode
, cmp0
);
1749 if (GET_CODE (cmp1
) == CONST_INT
)
1751 HOST_WIDE_INT value
= INTVAL (cmp1
);
1752 if (value
< p_info
->const_low
1753 || value
> p_info
->const_high
1754 /* ??? Why? And why wasn't the similar code below modified too? */
1756 && HOST_BITS_PER_WIDE_INT
< 64
1757 && p_info
->const_add
!= 0
1758 && ((p_info
->unsignedp
1759 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
1761 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
1762 != (p_info
->const_add
> 0))))
1763 cmp1
= force_reg (mode
, cmp1
);
1766 /* See if we need to invert the result. */
1767 invert
= (GET_CODE (cmp1
) == CONST_INT
)
1768 ? p_info
->invert_const
1769 : p_info
->invert_reg
;
1771 if (p_invert
!= (int *)0)
1777 /* Comparison to constants, may involve adding 1 to change a LT into LE.
1778 Comparison between two registers, may involve switching operands. */
1779 if (GET_CODE (cmp1
) == CONST_INT
)
1781 if (p_info
->const_add
!= 0)
1783 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
1784 /* If modification of cmp1 caused overflow,
1785 we would get the wrong answer if we follow the usual path;
1786 thus, x > 0xffffffffu would turn into x > 0u. */
1787 if ((p_info
->unsignedp
1788 ? (unsigned HOST_WIDE_INT
) new > INTVAL (cmp1
)
1789 : new > INTVAL (cmp1
))
1790 != (p_info
->const_add
> 0))
1792 /* This test is always true, but if INVERT is true then
1793 the result of the test needs to be inverted so 0 should
1794 be returned instead. */
1795 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
1799 cmp1
= GEN_INT (new);
1802 else if (p_info
->reverse_regs
)
1809 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
1813 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
1814 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
1817 if (test
== ITEST_NE
)
1819 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
1823 else if (test
== ITEST_EQ
)
1825 reg2
= (invert
) ? gen_reg_rtx (mode
) : result
;
1826 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
1831 convert_move (result
, gen_rtx (XOR
, mode
, reg
, const1_rtx
), 0);
1837 /* Emit the common code for doing conditional branches.
1838 operand[0] is the label to jump to.
1839 The comparison operands are saved away by cmp{si,di,sf,df}. */
1842 gen_conditional_branch (operands
, test_code
)
1844 enum rtx_code test_code
;
1846 static enum machine_mode mode_map
[(int)CMP_MAX
][(int)ITEST_MAX
] = {
1873 CC_REV_FPmode
, /* ne */
1885 CC_REV_FPmode
, /* ne */
1897 enum machine_mode mode
;
1898 enum cmp_type type
= branch_type
;
1899 rtx cmp0
= branch_cmp
[0];
1900 rtx cmp1
= branch_cmp
[1];
1901 rtx label1
= gen_rtx (LABEL_REF
, VOIDmode
, operands
[0]);
1902 rtx label2
= pc_rtx
;
1905 enum internal_test test
= map_test_to_internal_test (test_code
);
1907 if (test
== ITEST_MAX
)
1913 /* Get the machine mode to use (CCmode, CC_EQmode, CC_FPmode, or CC_REV_FPmode). */
1914 mode
= mode_map
[(int)type
][(int)test
];
1915 if (mode
== VOIDmode
)
1925 reg
= gen_int_relational (test_code
, (rtx
)0, cmp0
, cmp1
, &invert
);
1933 /* Make sure not non-zero constant if ==/!= */
1934 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
1935 cmp1
= force_reg (mode
, cmp1
);
1942 rtx reg
= gen_rtx (REG
, mode
, FPSW_REGNUM
);
1943 emit_insn (gen_rtx (SET
, VOIDmode
, reg
, gen_rtx (test_code
, mode
, cmp0
, cmp1
)));
1951 /* Generate the jump */
1958 emit_jump_insn (gen_rtx (SET
, VOIDmode
,
1960 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
1961 gen_rtx (test_code
, mode
, cmp0
, cmp1
),
1968 abort_with_insn (gen_rtx (test_code
, mode
, cmp0
, cmp1
), "bad test");
1973 /* Internal code to generate the load and store of one word/short/byte.
1974 The load is emitted directly, and the store insn is returned. */
1976 #define UNITS_PER_MIPS_DWORD 8
1977 #define UNITS_PER_MIPS_WORD 4
1978 #define UNITS_PER_MIPS_HWORD 2
1981 block_move_load_store (dest_reg
, src_reg
, p_bytes
, p_offset
, align
, orig_src
)
1982 rtx src_reg
; /* register holding source memory address */
1983 rtx dest_reg
; /* register holding dest. memory address */
1984 int *p_bytes
; /* pointer to # bytes remaining */
1985 int *p_offset
; /* pointer to current offset */
1986 int align
; /* alignment */
1987 rtx orig_src
; /* original source for making a reg note */
1989 int bytes
; /* # bytes remaining */
1990 int offset
; /* offset to use */
1991 int size
; /* size in bytes of load/store */
1992 enum machine_mode mode
; /* mode to use for load/store */
1993 rtx reg
; /* temporary register */
1994 rtx src_addr
; /* source address */
1995 rtx dest_addr
; /* destination address */
1996 rtx insn
; /* insn of the load */
1997 rtx orig_src_addr
; /* original source address */
1998 rtx (*load_func
)(); /* function to generate load insn */
1999 rtx (*store_func
)(); /* function to generate destination insn */
2002 if (bytes
<= 0 || align
<= 0)
2005 if (bytes
>= UNITS_PER_MIPS_DWORD
&& align
>= UNIS_PER_MIPS_DWORD
)
2008 size
= UNITS_PER_MIPS_DWORD
;
2009 load_func
= gen_movdi
;
2010 store_func
= gen_movdi
;
2012 else if (bytes
>= UNITS_PER_MIPS_WORD
&& align
>= UNITS_PER_MIPS_WORD
)
2015 size
= UNITS_PER_MIPS_WORD
;
2016 load_func
= gen_movsi
;
2017 store_func
= gen_movsi
;
2021 /* Don't generate unaligned moves here, rather defer those to the
2022 general movestrsi_internal pattern.
2023 If this gets commented back in, then should add the dword equivalent. */
2024 else if (bytes
>= UNITS_PER_MIPS_WORD
)
2027 size
= UNITS_PER_MIPS_WORD
;
2028 load_func
= gen_movsi_ulw
;
2029 store_func
= gen_movsi_usw
;
2033 else if (bytes
>= UNITS_PER_MIPS_SHORT
&& align
>= UNITS_PER_MIPS_SHORT
)
2036 size
= UNITS_PER_MIPS_SHORT
;
2037 load_func
= gen_movhi
;
2038 store_func
= gen_movhi
;
2045 load_func
= gen_movqi
;
2046 store_func
= gen_movqi
;
2050 *p_offset
= offset
+ size
;
2051 *p_bytes
= bytes
- size
;
2056 dest_addr
= dest_reg
;
2060 src_addr
= gen_rtx (PLUS
, Pmode
, src_reg
, GEN_INT (offset
));
2061 dest_addr
= gen_rtx (PLUS
, Pmode
, dest_reg
, GEN_INT (offset
));
2064 reg
= gen_reg_rtx (mode
);
2065 insn
= emit_insn ((*load_func
) (reg
, gen_rtx (MEM
, mode
, src_addr
)));
2066 orig_src_addr
= XEXP (orig_src
, 0);
2067 if (CONSTANT_P (orig_src_addr
))
2068 REG_NOTES (insn
) = gen_rtx (EXPR_LIST
, REG_EQUIV
,
2069 plus_constant (orig_src_addr
, offset
),
2072 return (*store_func
) (gen_rtx (MEM
, mode
, dest_addr
), reg
);
2077 /* Write a series of loads/stores to move some bytes. Generate load/stores as follows:
2089 This way, no NOP's are needed, except at the end, and only
2090 two temp registers are needed. Two delay slots are used
2091 in deference to the R4000. */
2095 block_move_sequence (dest_reg
, src_reg
, bytes
, align
, orig_src
)
2096 rtx dest_reg
; /* register holding destination address */
2097 rtx src_reg
; /* register holding source address */
2098 int bytes
; /* # bytes to move */
2099 int align
; /* max alignment to assume */
2100 rtx orig_src
; /* original source for making a reg note */
2103 rtx prev2_store
= (rtx
)0;
2104 rtx prev_store
= (rtx
)0;
2105 rtx cur_store
= (rtx
)0;
2109 /* Is there a store to do? */
2111 emit_insn (prev2_store
);
2113 prev2_store
= prev_store
;
2114 prev_store
= cur_store
;
2115 cur_store
= block_move_load_store (dest_reg
, src_reg
,
2120 /* Finish up last three stores. */
2122 emit_insn (prev2_store
);
2125 emit_insn (prev_store
);
2128 emit_insn (cur_store
);
2133 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2139 temp<last> = src[MAX_MOVE_REGS-1];
2143 dest[MAX_MOVE_REGS-1] = temp<last>;
2144 src += MAX_MOVE_REGS;
2145 dest += MAX_MOVE_REGS;
2146 } while (src != final);
2148 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2149 registers are needed.
2151 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2152 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2153 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2155 #define MAX_MOVE_REGS 4
2156 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2158 /* ??? Should add code to use DWORD load/stores. */
2161 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_src
)
2162 rtx dest_reg
; /* register holding destination address */
2163 rtx src_reg
; /* register holding source address */
2164 int bytes
; /* # bytes to move */
2165 int align
; /* alignment */
2166 rtx orig_src
; /* original source for making a reg note */
2168 rtx dest_mem
= gen_rtx (MEM
, BLKmode
, dest_reg
);
2169 rtx src_mem
= gen_rtx (MEM
, BLKmode
, src_reg
);
2170 rtx align_rtx
= GEN_INT (align
);
2176 if (bytes
< 2*MAX_MOVE_BYTES
)
2179 leftover
= bytes
% MAX_MOVE_BYTES
;
2182 label
= gen_label_rtx ();
2183 final_src
= gen_reg_rtx (Pmode
);
2184 bytes_rtx
= GEN_INT (bytes
);
2190 emit_insn (gen_movdi (final_src
, bytes_rtx
));
2191 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
2195 emit_insn (gen_movsi (final_src
, bytes_rtx
));
2196 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2202 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
2204 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
2209 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
2210 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
2213 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
2214 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
2215 emit_insn (gen_cmpdi (src_reg
, final_src
));
2219 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
2220 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
2221 emit_insn (gen_cmpsi (src_reg
, final_src
));
2223 emit_jump_insn (gen_bne (label
));
2226 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
,
2232 /* Use a library function to move some bytes. */
2235 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2240 /* We want to pass the size as Pmode, which will normally be SImode
2241 but will be DImode if we are using 64 bit longs and pointers. */
2242 if (GET_MODE (bytes_rtx
) != VOIDmode
2243 && GET_MODE (bytes_rtx
) != Pmode
)
2244 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, TRUE
);
2246 #ifdef TARGET_MEM_FUNCTIONS
2247 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0,
2253 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "bcopy"), 0,
2262 /* Expand string/block move operations.
2264 operands[0] is the pointer to the destination.
2265 operands[1] is the pointer to the source.
2266 operands[2] is the number of bytes to move.
2267 operands[3] is the alignment. */
2270 expand_block_move (operands
)
2273 rtx bytes_rtx
= operands
[2];
2274 rtx align_rtx
= operands
[3];
2275 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2276 int bytes
= (constp
? INTVAL (bytes_rtx
) : 0);
2277 int align
= INTVAL (align_rtx
);
2278 rtx orig_src
= operands
[1];
2282 if (constp
&& bytes
<= 0)
2285 if (align
> UNITS_PER_WORD
)
2286 align
= UNITS_PER_WORD
;
2288 /* Move the address into scratch registers. */
2289 dest_reg
= copy_addr_to_reg (XEXP (operands
[0], 0));
2290 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2293 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2296 else if (constp
&& bytes
<= 3*align
)
2297 block_move_sequence (dest_reg
, src_reg
, bytes
, align
, orig_src
);
2300 else if (constp
&& bytes
<= 2*MAX_MOVE_BYTES
)
2301 emit_insn (gen_movstrsi_internal (gen_rtx (MEM
, BLKmode
, dest_reg
),
2302 gen_rtx (MEM
, BLKmode
, src_reg
),
2303 bytes_rtx
, align_rtx
));
2305 else if (constp
&& align
>= UNITS_PER_WORD
&& optimize
)
2306 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_src
);
2308 else if (constp
&& optimize
)
2310 /* If the alignment is not word aligned, generate a test at
2311 runtime, to see whether things wound up aligned, and we
2312 can use the faster lw/sw instead ulw/usw. */
2314 rtx temp
= gen_reg_rtx (Pmode
);
2315 rtx aligned_label
= gen_label_rtx ();
2316 rtx join_label
= gen_label_rtx ();
2317 int leftover
= bytes
% MAX_MOVE_BYTES
;
2323 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
2324 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2325 emit_insn (gen_cmpdi (temp
, const0_rtx
));
2329 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
2330 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2331 emit_insn (gen_cmpsi (temp
, const0_rtx
));
2333 emit_jump_insn (gen_beq (aligned_label
));
2335 /* Unaligned loop. */
2336 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_src
);
2337 emit_jump_insn (gen_jump (join_label
));
2341 emit_label (aligned_label
);
2342 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_src
);
2343 emit_label (join_label
);
2345 /* Bytes at the end of the loop. */
2349 if (leftover
<= 3*align
)
2350 block_move_sequence (dest_reg
, src_reg
, leftover
, align
, orig_src
);
2354 emit_insn (gen_movstrsi_internal (gen_rtx (MEM
, BLKmode
, dest_reg
),
2355 gen_rtx (MEM
, BLKmode
, src_reg
),
2362 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2366 /* Emit load/stores for a small constant block_move.
2368 operands[0] is the memory address of the destination.
2369 operands[1] is the memory address of the source.
2370 operands[2] is the number of bytes to move.
2371 operands[3] is the alignment.
2372 operands[4] is a temp register.
2373 operands[5] is a temp register.
2375 operands[3+num_regs] is the last temp register.
2377 The block move type can be one of the following:
2378 BLOCK_MOVE_NORMAL Do all of the block move.
2379 BLOCK_MOVE_NOT_LAST Do all but the last store.
2380 BLOCK_MOVE_LAST Do just the last store. */
2383 output_block_move (insn
, operands
, num_regs
, move_type
)
2387 enum block_move_type move_type
;
2389 rtx dest_reg
= XEXP (operands
[0], 0);
2390 rtx src_reg
= XEXP (operands
[1], 0);
2391 int bytes
= INTVAL (operands
[2]);
2392 int align
= INTVAL (operands
[3]);
2395 int use_lwl_lwr
= FALSE
;
2396 int last_operand
= num_regs
+4;
2402 char *load
; /* load insn without nop */
2403 char *load_nop
; /* load insn with trailing nop */
2404 char *store
; /* store insn */
2405 char *final
; /* if last_store used: NULL or swr */
2406 char *last_store
; /* last store instruction */
2407 int offset
; /* current offset */
2408 enum machine_mode mode
; /* mode to use on (MEM) */
2411 /* Detect a bug in GCC, where it can give us a register
2412 the same as one of the addressing registers and reduce
2413 the number of registers available. */
2415 i
< last_operand
&& safe_regs
< (sizeof(xoperands
) / sizeof(xoperands
[0]));
2418 if (!reg_mentioned_p (operands
[i
], operands
[0])
2419 && !reg_mentioned_p (operands
[i
], operands
[1]))
2421 xoperands
[safe_regs
++] = operands
[i
];
2424 if (safe_regs
< last_operand
)
2426 xoperands
[0] = operands
[0];
2427 xoperands
[1] = operands
[1];
2428 xoperands
[2] = operands
[2];
2429 xoperands
[3] = operands
[3];
2430 return output_block_move (insn
, xoperands
, safe_regs
-4, move_type
);
2433 /* If we are given global or static addresses, and we would be
2434 emitting a few instructions, try to save time by using a
2435 temporary register for the pointer. */
2436 if (num_regs
> 2 && (bytes
> 2*align
|| move_type
!= BLOCK_MOVE_NORMAL
))
2438 if (CONSTANT_P (src_reg
))
2441 mips_count_memory_refs (operands
[1], 1);
2443 src_reg
= operands
[ 3 + num_regs
-- ];
2444 if (move_type
!= BLOCK_MOVE_LAST
)
2446 xoperands
[1] = operands
[1];
2447 xoperands
[0] = src_reg
;
2448 output_asm_insn ("la\t%0,%1", xoperands
);
2452 if (CONSTANT_P (dest_reg
))
2455 mips_count_memory_refs (operands
[0], 1);
2457 dest_reg
= operands
[ 3 + num_regs
-- ];
2458 if (move_type
!= BLOCK_MOVE_LAST
)
2460 xoperands
[1] = operands
[0];
2461 xoperands
[0] = dest_reg
;
2462 output_asm_insn ("la\t%0,%1", xoperands
);
2467 if (num_regs
> (sizeof (load_store
) / sizeof (load_store
[0])))
2468 num_regs
= (sizeof (load_store
) / sizeof (load_store
[0]));
2470 else if (num_regs
< 1)
2471 abort_with_insn (insn
, "Cannot do block move, not enough scratch registers");
2475 load_store
[num
].offset
= offset
;
2477 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
2479 load_store
[num
].load
= "ld\t%0,%1";
2480 load_store
[num
].load_nop
= "ld\t%0,%1%#";
2481 load_store
[num
].store
= "sd\t%0,%1";
2482 load_store
[num
].last_store
= "sd\t%0,%1";
2483 load_store
[num
].final
= (char *)0;
2484 load_store
[num
].mode
= DImode
;
2489 /* ??? Fails because of a MIPS assembler bug? */
2490 else if (TARGET_64BIT
&& bytes
>= 8)
2492 if (BYTES_BIG_ENDIAN
)
2494 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
2495 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
2496 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
2497 load_store
[num
].last_store
= "sdr\t%0,%2";
2498 load_store
[num
].final
= "sdl\t%0,%1";
2502 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
2503 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
2504 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
2505 load_store
[num
].last_store
= "sdr\t%0,%1";
2506 load_store
[num
].final
= "sdl\t%0,%2";
2508 load_store
[num
].mode
= DImode
;
2514 else if (bytes
>= 4 && align
>= 4)
2516 load_store
[num
].load
= "lw\t%0,%1";
2517 load_store
[num
].load_nop
= "lw\t%0,%1%#";
2518 load_store
[num
].store
= "sw\t%0,%1";
2519 load_store
[num
].last_store
= "sw\t%0,%1";
2520 load_store
[num
].final
= (char *)0;
2521 load_store
[num
].mode
= SImode
;
2526 else if (bytes
>= 4)
2528 if (BYTES_BIG_ENDIAN
)
2530 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
2531 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2532 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
2533 load_store
[num
].last_store
= "swr\t%0,%2";
2534 load_store
[num
].final
= "swl\t%0,%1";
2538 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
2539 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2540 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
2541 load_store
[num
].last_store
= "swr\t%0,%1";
2542 load_store
[num
].final
= "swl\t%0,%2";
2544 load_store
[num
].mode
= SImode
;
2550 else if (bytes
>= 2 && align
>= 2)
2552 load_store
[num
].load
= "lh\t%0,%1";
2553 load_store
[num
].load_nop
= "lh\t%0,%1%#";
2554 load_store
[num
].store
= "sh\t%0,%1";
2555 load_store
[num
].last_store
= "sh\t%0,%1";
2556 load_store
[num
].final
= (char *)0;
2557 load_store
[num
].mode
= HImode
;
2564 load_store
[num
].load
= "lb\t%0,%1";
2565 load_store
[num
].load_nop
= "lb\t%0,%1%#";
2566 load_store
[num
].store
= "sb\t%0,%1";
2567 load_store
[num
].last_store
= "sb\t%0,%1";
2568 load_store
[num
].final
= (char *)0;
2569 load_store
[num
].mode
= QImode
;
2574 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2576 dslots_load_total
++;
2577 dslots_load_filled
++;
2579 if (CONSTANT_P (src_reg
))
2580 mips_count_memory_refs (src_reg
, 1);
2582 if (CONSTANT_P (dest_reg
))
2583 mips_count_memory_refs (dest_reg
, 1);
2586 /* Emit load/stores now if we have run out of registers or are
2587 at the end of the move. */
2589 if (++num
== num_regs
|| bytes
== 0)
2591 /* If only load/store, we need a NOP after the load. */
2594 load_store
[0].load
= load_store
[0].load_nop
;
2595 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2596 dslots_load_filled
--;
2599 if (move_type
!= BLOCK_MOVE_LAST
)
2601 for (i
= 0; i
< num
; i
++)
2608 if (GET_MODE (operands
[i
+4]) != load_store
[i
].mode
)
2609 operands
[i
+4] = gen_rtx (REG
, load_store
[i
].mode
, REGNO (operands
[i
+4]));
2611 offset
= load_store
[i
].offset
;
2612 xoperands
[0] = operands
[i
+4];
2613 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2614 plus_constant (src_reg
, offset
));
2619 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2620 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2621 plus_constant (src_reg
,
2626 output_asm_insn (load_store
[i
].load
, xoperands
);
2630 for (i
= 0; i
< num
; i
++)
2632 int last_p
= (i
== num
-1 && bytes
== 0);
2633 int offset
= load_store
[i
].offset
;
2635 xoperands
[0] = operands
[i
+4];
2636 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2637 plus_constant (dest_reg
, offset
));
2643 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2644 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2645 plus_constant (dest_reg
,
2650 if (move_type
== BLOCK_MOVE_NORMAL
)
2651 output_asm_insn (load_store
[i
].store
, xoperands
);
2653 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
2656 output_asm_insn (load_store
[i
].store
, xoperands
);
2658 else if (load_store
[i
].final
!= (char *)0)
2659 output_asm_insn (load_store
[i
].final
, xoperands
);
2663 output_asm_insn (load_store
[i
].last_store
, xoperands
);
2666 num
= 0; /* reset load_store */
2667 use_lwl_lwr
= FALSE
;
2675 /* Argument support functions. */
2677 /* Initialize CUMULATIVE_ARGS for a function. */
2680 init_cumulative_args (cum
, fntype
, libname
)
2681 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
2682 tree fntype
; /* tree ptr for function decl */
2683 rtx libname
; /* SYMBOL_REF of library name or 0 */
2685 static CUMULATIVE_ARGS zero_cum
;
2686 tree param
, next_param
;
2688 if (TARGET_DEBUG_E_MODE
)
2690 fprintf (stderr
, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
2692 fputc ('\n', stderr
);
2696 tree ret_type
= TREE_TYPE (fntype
);
2697 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
2698 tree_code_name
[ (int)TREE_CODE (fntype
) ],
2699 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
2705 /* Determine if this function has variable arguments. This is
2706 indicated by the last argument being 'void_type_mode' if there
2707 are no variable arguments. The standard MIPS calling sequence
2708 passes all arguments in the general purpose registers in this
2711 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
2715 next_param
= TREE_CHAIN (param
);
2716 if (next_param
== (tree
)0 && TREE_VALUE (param
) != void_type_node
)
2717 cum
->gp_reg_found
= 1;
2721 /* Advance the argument to the next argument position. */
2724 function_arg_advance (cum
, mode
, type
, named
)
2725 CUMULATIVE_ARGS
*cum
; /* current arg information */
2726 enum machine_mode mode
; /* current arg mode */
2727 tree type
; /* type of the argument or 0 if lib support */
2728 int named
; /* whether or not the argument was named */
2730 if (TARGET_DEBUG_E_MODE
)
2732 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
2733 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
2743 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
2744 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
2746 cum
->gp_reg_found
= 1;
2747 cum
->arg_words
+= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
2752 cum
->gp_reg_found
= 1;
2753 cum
->arg_words
+= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
2762 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
2766 cum
->gp_reg_found
= 1;
2767 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
2773 cum
->gp_reg_found
= 1;
2779 /* Return an RTL expression containing the register for the given mode,
2780 or 0 if the argument is to be passed on the stack. */
2783 function_arg (cum
, mode
, type
, named
)
2784 CUMULATIVE_ARGS
*cum
; /* current arg information */
2785 enum machine_mode mode
; /* current arg mode */
2786 tree type
; /* type of the argument or 0 if lib support */
2787 int named
; /* != 0 for normal args, == 0 for ... args */
2792 int struct_p
= ((type
!= (tree
)0)
2793 && (TREE_CODE (type
) == RECORD_TYPE
2794 || TREE_CODE (type
) == UNION_TYPE
));
2796 if (TARGET_DEBUG_E_MODE
)
2798 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
2799 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
2805 if (cum
->gp_reg_found
|| cum
->arg_number
>= 2 || TARGET_SOFT_FLOAT
)
2806 regbase
= GP_ARG_FIRST
;
2809 regbase
= FP_ARG_FIRST
;
2810 /* If the first arg was a float in a floating point register,
2811 then set bias to align this float arg properly. */
2812 if (cum
->arg_words
== 1)
2820 cum
->arg_words
+= (cum
->arg_words
& 1);
2821 regbase
= (cum
->gp_reg_found
|| TARGET_SOFT_FLOAT
|| cum
->arg_number
>= 2
2827 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
2828 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
2831 /* Drops through. */
2833 if (type
!= (tree
)0 && TYPE_ALIGN (type
) > BITS_PER_WORD
2835 cum
->arg_words
+= (cum
->arg_words
& 1);
2837 regbase
= GP_ARG_FIRST
;
2844 regbase
= GP_ARG_FIRST
;
2849 cum
->arg_words
+= (cum
->arg_words
& 1);
2850 regbase
= GP_ARG_FIRST
;
2853 if (cum
->arg_words
>= MAX_ARGS_IN_REGISTERS
)
2855 if (TARGET_DEBUG_E_MODE
)
2856 fprintf (stderr
, "<stack>%s\n", struct_p
? ", [struct]" : "");
2865 ret
= gen_rtx (REG
, mode
, regbase
+ cum
->arg_words
+ bias
);
2867 if (TARGET_DEBUG_E_MODE
)
2868 fprintf (stderr
, "%s%s\n", reg_names
[regbase
+ cum
->arg_words
+ bias
],
2869 struct_p
? ", [struct]" : "");
2871 /* The following is a hack in order to pass 1 byte structures
2872 the same way that the MIPS compiler does (namely by passing
2873 the structure in the high byte or half word of the register).
2874 This also makes varargs work. If we have such a structure,
2875 we save the adjustment RTL, and the call define expands will
2876 emit them. For the VOIDmode argument (argument after the
2877 last real argument), pass back a parallel vector holding each
2878 of the adjustments. */
2880 /* ??? function_arg can be called more than once for each argument.
2881 As a result, we compute more adjustments than we need here.
2882 See the CUMULATIVE_ARGS definition in mips.h. */
2884 /* ??? This scheme requires everything smaller than the word size to
2885 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
2886 that would mean every int needs to be shifted left, which is very
2887 inefficient. Let's not carry this compatibility to the 64 bit
2888 calling convention for now. */
2890 if (struct_p
&& int_size_in_bytes (type
) < UNITS_PER_WORD
2893 rtx amount
= GEN_INT (BITS_PER_WORD
2894 - int_size_in_bytes (type
) * BITS_PER_UNIT
);
2895 rtx reg
= gen_rtx (REG
, word_mode
, regbase
+ cum
->arg_words
+ bias
);
2897 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashldi3 (reg
, reg
, amount
);
2899 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashlsi3 (reg
, reg
, amount
);
2903 if (mode
== VOIDmode
&& cum
->num_adjusts
> 0)
2904 ret
= gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec_v (cum
->num_adjusts
, cum
->adjust
));
2911 function_arg_partial_nregs (cum
, mode
, type
, named
)
2912 CUMULATIVE_ARGS
*cum
; /* current arg information */
2913 enum machine_mode mode
; /* current arg mode */
2914 tree type
; /* type of the argument or 0 if lib support */
2915 int named
; /* != 0 for normal args, == 0 for ... args */
2917 if ((mode
== BLKmode
2918 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
2919 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
2920 && cum
->arg_words
< MAX_ARGS_IN_REGISTERS
)
2923 if (mode
== BLKmode
)
2924 words
= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
2927 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2929 if (words
+ cum
->arg_words
<= MAX_ARGS_IN_REGISTERS
)
2930 return 0; /* structure fits in registers */
2932 if (TARGET_DEBUG_E_MODE
)
2933 fprintf (stderr
, "function_arg_partial_nregs = %d\n",
2934 MAX_ARGS_IN_REGISTERS
- cum
->arg_words
);
2936 return MAX_ARGS_IN_REGISTERS
- cum
->arg_words
;
2939 else if (mode
== DImode
&& cum
->arg_words
== MAX_ARGS_IN_REGISTERS
-1
2942 if (TARGET_DEBUG_E_MODE
)
2943 fprintf (stderr
, "function_arg_partial_nregs = 1\n");
2952 /* Print the options used in the assembly file. */
2954 static struct {char *name
; int value
;} target_switches
[]
2965 int mask
= TARGET_DEFAULT
;
2967 /* Allow assembly language comparisons with -mdebug eliminating the
2968 compiler version number and switch lists. */
2970 if (TARGET_DEBUG_MODE
)
2973 fprintf (out
, "\n # %s %s", language_string
, version_string
);
2974 #ifdef TARGET_VERSION_INTERNAL
2975 TARGET_VERSION_INTERNAL (out
);
2978 fprintf (out
, " compiled by GNU C\n\n");
2980 fprintf (out
, " compiled by CC\n\n");
2983 fprintf (out
, " # Cc1 defaults:");
2985 for (j
= 0; j
< sizeof target_switches
/ sizeof target_switches
[0]; j
++)
2987 if (target_switches
[j
].name
[0] != '\0'
2988 && target_switches
[j
].value
> 0
2989 && (target_switches
[j
].value
& mask
) == target_switches
[j
].value
)
2991 mask
&= ~ target_switches
[j
].value
;
2992 len
= strlen (target_switches
[j
].name
) + 1;
2993 if (len
+ line_len
> 79)
2996 fputs ("\n #", out
);
2998 fprintf (out
, " -m%s", target_switches
[j
].name
);
3003 fprintf (out
, "\n\n # Cc1 arguments (-G value = %d, Cpu = %s, ISA = %d):",
3004 mips_section_threshold
, mips_cpu_string
, mips_isa
);
3007 for (p
= &save_argv
[1]; *p
!= (char *)0; p
++)
3012 len
= strlen (arg
) + 1;
3013 if (len
+ line_len
> 79)
3016 fputs ("\n #", out
);
3018 fprintf (out
, " %s", *p
);
3023 fputs ("\n\n", out
);
3027 /* Abort after printing out a specific insn. */
3030 abort_with_insn (insn
, reason
)
3039 /* Write a message to stderr (for use in macros expanded in files that do not
3040 include stdio.h). */
3046 fprintf (stderr
, s
, s1
, s2
);
3056 fprintf (stderr
, "compiling '%s' in '%s'\n",
3057 (current_function_name
!= (char *)0) ? current_function_name
: "<toplevel>",
3058 (current_function_file
!= (char *)0) ? current_function_file
: "<no file>");
3061 #endif /* SIGINFO */
3064 /* Set up the threshold for data to go into the small data area, instead
3065 of the normal data area, and detect any conflicts in the switches. */
3070 register int i
, start
;
3072 register enum machine_mode mode
;
3074 mips_section_threshold
= (g_switch_set
) ? g_switch_value
: MIPS_DEFAULT_GVALUE
;
3076 if (mips_section_threshold
<= 0)
3077 target_flags
&= ~MASK_GPOPT
;
3079 target_flags
|= MASK_GPOPT
;
3081 /* Get the architectural level. */
3082 if (mips_isa_string
== (char *)0)
3084 #ifdef MIPS_ISA_DEFAULT
3085 mips_isa
= MIPS_ISA_DEFAULT
;
3091 else if (isdigit (*mips_isa_string
))
3093 mips_isa
= atoi (mips_isa_string
);
3094 if (mips_isa
< 1 || mips_isa
> 3)
3096 error ("-mips%d not supported", mips_isa
);
3103 error ("bad value (%s) for -mips switch", mips_isa_string
);
3107 /* Identify the processor type */
3108 if (mips_cpu_string
== (char *)0
3109 || !strcmp (mips_cpu_string
, "default")
3110 || !strcmp (mips_cpu_string
, "DEFAULT"))
3115 mips_cpu_string
= "3000";
3116 mips_cpu
= PROCESSOR_R3000
;
3119 mips_cpu_string
= "6000";
3120 mips_cpu
= PROCESSOR_R6000
;
3123 mips_cpu_string
= "4000";
3124 mips_cpu
= PROCESSOR_R4000
;
3128 #ifdef MIPS_CPU_DEFAULT
3129 if (mips_isa_string
== (char *)0)
3131 mips_cpu_string
= MIPS_CPU_STRING_DEFAULT
;
3132 mips_cpu
= MIPS_CPU_DEFAULT
;
3139 char *p
= mips_cpu_string
;
3141 if (*p
== 'r' || *p
== 'R')
3144 /* Since there is no difference between a R2000 and R3000 in
3145 terms of the scheduler, we collapse them into just an R3000. */
3147 mips_cpu
= PROCESSOR_DEFAULT
;
3151 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
3152 mips_cpu
= PROCESSOR_R3000
;
3156 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
3157 mips_cpu
= PROCESSOR_R3000
;
3161 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
3162 mips_cpu
= PROCESSOR_R4000
;
3163 /* The r4400 is exactly the same as the r4000 from the compiler's
3165 else if (!strcmp (p
, "4400"))
3166 mips_cpu
= PROCESSOR_R4000
;
3167 else if (!strcmp (p
, "4600"))
3168 mips_cpu
= PROCESSOR_R4600
;
3172 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
3173 mips_cpu
= PROCESSOR_R6000
;
3177 if (!strcmp (p
, "orion"))
3178 mips_cpu
= PROCESSOR_R4600
;
3182 if (mips_cpu
== PROCESSOR_DEFAULT
)
3184 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
3185 mips_cpu_string
= "default";
3189 if ((mips_cpu
== PROCESSOR_R3000
&& mips_isa
> 1)
3190 || (mips_cpu
== PROCESSOR_R6000
&& mips_isa
> 2))
3191 error ("-mcpu=%s does not support -mips%d", mips_cpu_string
, mips_isa
);
3193 /* make sure sizes of ints/longs/etc. are ok */
3197 fatal ("Only MIPS-III CPUs can support 64 bit ints");
3199 else if (TARGET_LONG64
)
3200 fatal ("Only MIPS-III CPUs can support 64 bit longs");
3202 else if (TARGET_FLOAT64
)
3203 fatal ("Only MIPS-III CPUs can support 64 bit fp registers");
3205 else if (TARGET_64BIT
)
3206 fatal ("Only MIPS-III CPUs can support 64 bit gp registers");
3209 /* Tell halfpic.c that we have half-pic code if we do. */
3210 if (TARGET_HALF_PIC
)
3213 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3214 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3215 /* ??? -non_shared turns off pic code generation, but this is not
3217 if (TARGET_ABICALLS
)
3219 mips_abicalls
= MIPS_ABICALLS_YES
;
3221 if (mips_section_threshold
> 0)
3222 warning ("-G is incompatible with PIC code which is the default");
3225 mips_abicalls
= MIPS_ABICALLS_NO
;
3227 /* -membedded-pic is a form of PIC code suitable for embedded
3228 systems. All calls are made using PC relative addressing, and
3229 all data is addressed using the $gp register. This requires gas,
3230 which does most of the work, and GNU ld, which automatically
3231 expands PC relative calls which are out of range into a longer
3232 instruction sequence. All gcc really does differently is
3233 generate a different sequence for a switch. */
3234 if (TARGET_EMBEDDED_PIC
)
3237 if (TARGET_ABICALLS
)
3238 warning ("-membedded-pic and -mabicalls are incompatible");
3240 warning ("-G and -membedded-pic are incompatible");
3241 /* Setting mips_section_threshold is not required, because gas
3242 will force everything to be GP addressable anyhow, but
3243 setting it will cause gcc to make better estimates of the
3244 number of instructions required to access a particular data
3246 mips_section_threshold
= 0x7fffffff;
3249 /* -mrnames says to use the MIPS software convention for register
3250 names instead of the hardware names (ie, $a0 instead of $4).
3251 We do this by switching the names in mips_reg_names, which the
3252 reg_names points into via the REGISTER_NAMES macro. */
3254 if (TARGET_NAME_REGS
)
3255 bcopy ((char *) mips_sw_reg_names
, (char *) mips_reg_names
, sizeof (mips_reg_names
));
3257 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3258 is currently being compiled. */
3260 if (getenv ("GCC_SIGINFO") != (char *)0)
3262 struct sigaction action
;
3263 action
.sa_handler
= siginfo
;
3265 action
.sa_flags
= SA_RESTART
;
3266 sigaction (SIGINFO
, &action
, (struct sigaction
*)0);
3271 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3272 /* If -mstats and -quiet, make stderr line buffered. */
3273 if (quiet_flag
&& TARGET_STATS
)
3274 setvbuf (stderr
, (char *)0, _IOLBF
, BUFSIZ
);
3278 /* Initialize the high and low values for legitimate floating point
3279 constants. Rather than trying to get the accuracy down to the
3280 last bit, just use approximate ranges. */
3281 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
3282 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
3283 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
3284 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
3286 mips_print_operand_punct
['?'] = TRUE
;
3287 mips_print_operand_punct
['#'] = TRUE
;
3288 mips_print_operand_punct
['&'] = TRUE
;
3289 mips_print_operand_punct
['!'] = TRUE
;
3290 mips_print_operand_punct
['*'] = TRUE
;
3291 mips_print_operand_punct
['@'] = TRUE
;
3292 mips_print_operand_punct
['.'] = TRUE
;
3293 mips_print_operand_punct
['('] = TRUE
;
3294 mips_print_operand_punct
[')'] = TRUE
;
3295 mips_print_operand_punct
['['] = TRUE
;
3296 mips_print_operand_punct
[']'] = TRUE
;
3297 mips_print_operand_punct
['<'] = TRUE
;
3298 mips_print_operand_punct
['>'] = TRUE
;
3299 mips_print_operand_punct
['{'] = TRUE
;
3300 mips_print_operand_punct
['}'] = TRUE
;
3301 mips_print_operand_punct
['^'] = TRUE
;
3303 mips_char_to_class
['d'] = GR_REGS
;
3304 mips_char_to_class
['f'] = ((TARGET_HARD_FLOAT
) ? FP_REGS
: NO_REGS
);
3305 mips_char_to_class
['h'] = HI_REG
;
3306 mips_char_to_class
['l'] = LO_REG
;
3307 mips_char_to_class
['x'] = MD_REGS
;
3308 mips_char_to_class
['y'] = GR_REGS
;
3309 mips_char_to_class
['z'] = ST_REGS
;
3311 /* Set up array to map GCC register number to debug register number.
3312 Ignore the special purpose register numbers. */
3314 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3315 mips_dbx_regno
[i
] = -1;
3317 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
3318 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
3319 mips_dbx_regno
[i
] = i
+ start
;
3321 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
3322 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
3323 mips_dbx_regno
[i
] = i
+ start
;
3325 /* Set up array giving whether a given register can hold a given mode.
3326 At present, restrict ints from being in FP registers, because reload
3327 is a little enthusiastic about storing extra values in FP registers,
3328 and this is not good for things like OS kernels. Also, due to the
3329 mandatory delay, it is as fast to load from cached memory as to move
3330 from the FP register. */
3332 for (mode
= VOIDmode
;
3333 mode
!= MAX_MACHINE_MODE
;
3334 mode
= (enum machine_mode
)((int)mode
+ 1))
3336 register int size
= GET_MODE_SIZE (mode
);
3337 register enum mode_class
class = GET_MODE_CLASS (mode
);
3339 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3343 if (mode
== CC_FPmode
|| mode
== CC_REV_FPmode
)
3344 temp
= (regno
== FPSW_REGNUM
);
3346 else if (GP_REG_P (regno
))
3347 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
3349 else if (FP_REG_P (regno
))
3350 temp
= ((TARGET_FLOAT64
|| ((regno
& 1) == 0))
3351 && (class == MODE_FLOAT
3352 || class == MODE_COMPLEX_FLOAT
3353 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
)));
3355 else if (MD_REG_P (regno
))
3358 temp
= (mode
== DImode
3359 || (regno
== MD_REG_FIRST
&& mode
== TImode
));
3361 temp
= (mode
== SImode
3362 || (regno
== MD_REG_FIRST
&& mode
== DImode
));
3368 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
3375 * The MIPS debug format wants all automatic variables and arguments
3376 * to be in terms of the virtual frame pointer (stack pointer before
3377 * any adjustment in the function), while the MIPS 3.0 linker wants
3378 * the frame pointer to be the stack pointer after the initial
3379 * adjustment. So, we do the adjustment here. The arg pointer (which
3380 * is eliminated) points to the virtual frame pointer, while the frame
3381 * pointer (which may be eliminated) points to the stack pointer after
3382 * the initial adjustments.
3386 mips_debugger_offset (addr
, offset
)
3390 rtx offset2
= const0_rtx
;
3391 rtx reg
= eliminate_constant_term (addr
, &offset2
);
3394 offset
= INTVAL (offset2
);
3396 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
)
3398 int frame_size
= (!current_frame_info
.initialized
)
3399 ? compute_frame_size (get_frame_size ())
3400 : current_frame_info
.total_size
;
3402 offset
= offset
- frame_size
;
3404 /* sdbout_parms does not want this to crash for unrecognized cases. */
3406 else if (reg
!= arg_pointer_rtx
)
3407 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer.");
3414 /* A C compound statement to output to stdio stream STREAM the
3415 assembler syntax for an instruction operand X. X is an RTL
3418 CODE is a value that can be used to specify one of several ways
3419 of printing the operand. It is used when identical operands
3420 must be printed differently depending on the context. CODE
3421 comes from the `%' specification that was used to request
3422 printing of the operand. If the specification was just `%DIGIT'
3423 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3424 is the ASCII code for LTR.
3426 If X is a register, this macro should print the register's name.
3427 The names can be found in an array `reg_names' whose type is
3428 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3430 When the machine description has a specification `%PUNCT' (a `%'
3431 followed by a punctuation character), this macro is called with
3432 a null pointer for X and the punctuation character for CODE.
3434 The MIPS specific codes are:
3436 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3437 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3438 'd' output integer constant in decimal,
3439 'z' if the operand is 0, use $0 instead of normal operand.
3440 'D' print second register of double-word register operand.
3441 'L' print low-order register of double-word register operand.
3442 'M' print high-order register of double-word register operand.
3443 'C' print part of opcode for a branch condition.
3444 'N' print part of opcode for a branch condition, inverted.
3445 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3446 '(' Turn on .set noreorder
3447 ')' Turn on .set reorder
3448 '[' Turn on .set noat
3450 '<' Turn on .set nomacro
3451 '>' Turn on .set macro
3452 '{' Turn on .set volatile (not GAS)
3453 '}' Turn on .set novolatile (not GAS)
3454 '&' Turn on .set noreorder if filling delay slots
3455 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3456 '!' Turn on .set nomacro if filling delay slots
3457 '#' Print nop if in a .set noreorder section.
3458 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3459 '@' Print the name of the assembler temporary register (at or $1).
3460 '.' Print the name of the register with a hard-wired zero (zero or $0).
3461 '^' Print the name of the pic call-through register (t9 or $25). */
3464 print_operand (file
, op
, letter
)
3465 FILE *file
; /* file to write to */
3466 rtx op
; /* operand to print */
3467 int letter
; /* %<letter> or 0 */
3469 register enum rtx_code code
;
3471 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
3476 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter
);
3480 if (mips_branch_likely
)
3485 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
3489 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
3493 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
3497 if (final_sequence
!= 0 && set_noreorder
++ == 0)
3498 fputs (".set\tnoreorder\n\t", file
);
3502 if (final_sequence
!= 0)
3504 if (set_noreorder
++ == 0)
3505 fputs (".set\tnoreorder\n\t", file
);
3507 if (set_nomacro
++ == 0)
3508 fputs (".set\tnomacro\n\t", file
);
3513 if (final_sequence
!= 0 && set_nomacro
++ == 0)
3514 fputs ("\n\t.set\tnomacro", file
);
3518 if (set_noreorder
!= 0)
3519 fputs ("\n\tnop", file
);
3521 else if (TARGET_STATS
)
3522 fputs ("\n\t#nop", file
);
3527 if (set_noreorder
++ == 0)
3528 fputs (".set\tnoreorder\n\t", file
);
3532 if (set_noreorder
== 0)
3533 error ("internal error: %%) found without a %%( in assembler pattern");
3535 else if (--set_noreorder
== 0)
3536 fputs ("\n\t.set\treorder", file
);
3541 if (set_noat
++ == 0)
3542 fputs (".set\tnoat\n\t", file
);
3547 error ("internal error: %%] found without a %%[ in assembler pattern");
3549 else if (--set_noat
== 0)
3550 fputs ("\n\t.set\tat", file
);
3555 if (set_nomacro
++ == 0)
3556 fputs (".set\tnomacro\n\t", file
);
3560 if (set_nomacro
== 0)
3561 error ("internal error: %%> found without a %%< in assembler pattern");
3563 else if (--set_nomacro
== 0)
3564 fputs ("\n\t.set\tmacro", file
);
3569 if (set_volatile
++ == 0)
3570 fprintf (file
, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS
) ? "" : "#");
3574 if (set_volatile
== 0)
3575 error ("internal error: %%} found without a %%{ in assembler pattern");
3577 else if (--set_volatile
== 0)
3578 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
3587 error ("PRINT_OPERAND null pointer");
3591 code
= GET_CODE (op
);
3595 case EQ
: fputs ("eq", file
); break;
3596 case NE
: fputs ("ne", file
); break;
3597 case GT
: fputs ("gt", file
); break;
3598 case GE
: fputs ("ge", file
); break;
3599 case LT
: fputs ("lt", file
); break;
3600 case LE
: fputs ("le", file
); break;
3601 case GTU
: fputs ("gtu", file
); break;
3602 case GEU
: fputs ("geu", file
); break;
3603 case LTU
: fputs ("ltu", file
); break;
3604 case LEU
: fputs ("leu", file
); break;
3607 abort_with_insn (op
, "PRINT_OPERAND, illegal insn for %%C");
3610 else if (letter
== 'N')
3613 case EQ
: fputs ("ne", file
); break;
3614 case NE
: fputs ("eq", file
); break;
3615 case GT
: fputs ("le", file
); break;
3616 case GE
: fputs ("lt", file
); break;
3617 case LT
: fputs ("ge", file
); break;
3618 case LE
: fputs ("gt", file
); break;
3619 case GTU
: fputs ("leu", file
); break;
3620 case GEU
: fputs ("ltu", file
); break;
3621 case LTU
: fputs ("geu", file
); break;
3622 case LEU
: fputs ("gtu", file
); break;
3625 abort_with_insn (op
, "PRINT_OPERAND, illegal insn for %%N");
3628 else if (letter
== 'S')
3632 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
3633 assemble_name (file
, buffer
);
3636 else if (code
== REG
)
3638 register int regnum
= REGNO (op
);
3640 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
3641 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
3645 fprintf (file
, "%s", reg_names
[regnum
]);
3648 else if (code
== MEM
)
3649 output_address (XEXP (op
, 0));
3651 else if (code
== CONST_DOUBLE
3652 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
3657 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
3658 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
3662 else if ((letter
== 'x') && (GET_CODE(op
) == CONST_INT
))
3663 fprintf (file
, "0x%04x", 0xffff & (INTVAL(op
)));
3665 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
))
3666 fprintf (file
, "0x%08x", INTVAL(op
));
3668 else if ((letter
== 'd') && (GET_CODE(op
) == CONST_INT
))
3669 fprintf (file
, "%d", (INTVAL(op
)));
3671 else if (letter
== 'z'
3672 && (GET_CODE (op
) == CONST_INT
)
3673 && INTVAL (op
) == 0)
3674 fputs (reg_names
[GP_REG_FIRST
], file
);
3676 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
3677 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter
);
3680 output_addr_const (file
, op
);
3684 /* A C compound statement to output to stdio stream STREAM the
3685 assembler syntax for an instruction operand that is a memory
3686 reference whose address is ADDR. ADDR is an RTL expression.
3688 On some machines, the syntax for a symbolic address depends on
3689 the section that the address refers to. On these machines,
3690 define the macro `ENCODE_SECTION_INFO' to store the information
3691 into the `symbol_ref', and then check for it here. */
3694 print_operand_address (file
, addr
)
3699 error ("PRINT_OPERAND_ADDRESS, null pointer");
3702 switch (GET_CODE (addr
))
3705 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, illegal insn #1");
3709 if (REGNO (addr
) == ARG_POINTER_REGNUM
)
3710 abort_with_insn (addr
, "Arg pointer not eliminated.");
3712 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
3717 register rtx reg
= (rtx
)0;
3718 register rtx offset
= (rtx
)0;
3719 register rtx arg0
= XEXP (addr
, 0);
3720 register rtx arg1
= XEXP (addr
, 1);
3722 if (GET_CODE (arg0
) == REG
)
3726 if (GET_CODE (offset
) == REG
)
3727 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
3729 else if (GET_CODE (arg1
) == REG
)
3734 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
3736 output_addr_const (file
, addr
);
3740 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
3742 if (!CONSTANT_P (offset
))
3743 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, illegal insn #2");
3745 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
3746 abort_with_insn (addr
, "Arg pointer not eliminated.");
3748 output_addr_const (file
, offset
);
3749 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
3757 output_addr_const (file
, addr
);
3763 /* If optimizing for the global pointer, keep track of all of
3764 the externs, so that at the end of the file, we can emit
3765 the appropriate .extern declaration for them, before writing
3766 out the text section. We assume that all names passed to
3767 us are in the permanent obstack, so that they will be valid
3768 at the end of the compilation.
3770 If we have -G 0, or the extern size is unknown, don't bother
3771 emitting the .externs. */
3774 mips_output_external (file
, decl
, name
)
3779 register struct extern_list
*p
;
3783 && ((TREE_CODE (decl
)) != FUNCTION_DECL
)
3784 && ((len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0))
3786 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
3787 p
->next
= extern_head
;
3793 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
3794 if (TREE_CODE (decl
) == FUNCTION_DECL
3795 /* ??? Don't include alloca, since gcc will always expand it
3796 inline. If we don't do this, libg++ fails to build. */
3797 && strcmp (name
, "alloca")
3798 /* ??? Don't include __builtin_next_arg, because then gcc will not
3799 bootstrap under Irix 5.1. */
3800 && strcmp (name
, "__builtin_next_arg"))
3802 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
3803 p
->next
= extern_head
;
3813 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
3815 mips_output_external_libcall (file
, name
)
3819 register struct extern_list
*p
;
3821 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
3822 p
->next
= extern_head
;
3832 /* Compute a string to use as a temporary file name. */
3834 /* On MSDOS, write temp files in current dir
3835 because there's no place else we can expect to use. */
3838 #define P_tmpdir "./"
3846 char *base
= getenv ("TMPDIR");
3849 if (base
== (char *)0)
3852 if (access (P_tmpdir
, R_OK
| W_OK
) == 0)
3856 if (access ("/usr/tmp", R_OK
| W_OK
) == 0)
3862 len
= strlen (base
);
3863 /* temp_filename is global, so we must use malloc, not alloca. */
3864 temp_filename
= (char *) xmalloc (len
+ sizeof("/ctXXXXXX"));
3865 strcpy (temp_filename
, base
);
3866 if (len
> 0 && temp_filename
[len
-1] != '/')
3867 temp_filename
[len
++] = '/';
3869 strcpy (temp_filename
+ len
, "ctXXXXXX");
3870 mktemp (temp_filename
);
3872 stream
= fopen (temp_filename
, "w+");
3874 pfatal_with_name (temp_filename
);
3877 /* In MSDOS, we cannot unlink the temporary file until we are finished using
3878 it. Otherwise, we delete it now, so that it will be gone even if the
3879 compiler happens to crash. */
3880 unlink (temp_filename
);
3886 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
3887 for .file's that start within a function. If we are smuggling stabs, try to
3888 put out a MIPS ECOFF file and a stab. */
3891 mips_output_filename (stream
, name
)
3895 static int first_time
= TRUE
;
3896 char ltext_label_name
[100];
3902 current_function_file
= name
;
3903 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
3904 output_quoted_string (stream
, name
);
3905 fprintf (stream
, "\n");
3906 /* This tells mips-tfile that stabs will follow. */
3907 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
3908 fprintf (stream
, "\t#@stabs\n");
3911 else if (write_symbols
== DBX_DEBUG
)
3913 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
3914 fprintf (stream
, "%s ", ASM_STABS_OP
);
3915 output_quoted_string (stream
, name
);
3916 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
3919 else if (name
!= current_function_file
3920 && strcmp (name
, current_function_file
) != 0)
3922 if (inside_function
&& !TARGET_GAS
)
3924 if (!file_in_function_warning
)
3926 file_in_function_warning
= TRUE
;
3927 ignore_line_number
= TRUE
;
3928 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
3931 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
3937 current_function_file
= name
;
3938 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
3940 output_quoted_string (stream
, name
);
3941 fprintf (stream
, "\n");
3946 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
3947 as well as a .loc, since it is possible that MIPS ECOFF might not be
3948 able to represent the location for inlines that come from a different
3952 mips_output_lineno (stream
, line
)
3956 if (write_symbols
== DBX_DEBUG
)
3959 fprintf (stream
, "$LM%d:\n\t%s %d,0,%d,$LM%d\n",
3960 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
3965 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
3966 (ignore_line_number
) ? "#" : "",
3967 num_source_filenames
, line
);
3969 LABEL_AFTER_LOC (stream
);
3974 /* If defined, a C statement to be executed just prior to the
3975 output of assembler code for INSN, to modify the extracted
3976 operands so they will be output differently.
3978 Here the argument OPVEC is the vector containing the operands
3979 extracted from INSN, and NOPERANDS is the number of elements of
3980 the vector which contain meaningful data for this insn. The
3981 contents of this vector are what will be used to convert the
3982 insn template into assembler code, so you can change the
3983 assembler output by changing the contents of the vector.
3985 We use it to check if the current insn needs a nop in front of it
3986 because of load delays, and also to update the delay slot
3989 /* ??? There is no real need for this function, because it never actually
3990 emits a NOP anymore. */
3993 final_prescan_insn (insn
, opvec
, noperands
)
3998 if (dslots_number_nops
> 0)
4000 rtx pattern
= PATTERN (insn
);
4001 int length
= get_attr_length (insn
);
4003 /* Do we need to emit a NOP? */
4005 || (mips_load_reg
!= (rtx
)0 && reg_mentioned_p (mips_load_reg
, pattern
))
4006 || (mips_load_reg2
!= (rtx
)0 && reg_mentioned_p (mips_load_reg2
, pattern
))
4007 || (mips_load_reg3
!= (rtx
)0 && reg_mentioned_p (mips_load_reg3
, pattern
))
4008 || (mips_load_reg4
!= (rtx
)0 && reg_mentioned_p (mips_load_reg4
, pattern
)))
4009 fputs ("\t#nop\n", asm_out_file
);
4012 dslots_load_filled
++;
4014 while (--dslots_number_nops
> 0)
4015 fputs ("\t#nop\n", asm_out_file
);
4017 mips_load_reg
= (rtx
)0;
4018 mips_load_reg2
= (rtx
)0;
4019 mips_load_reg3
= (rtx
)0;
4020 mips_load_reg4
= (rtx
)0;
4025 enum rtx_code code
= GET_CODE (insn
);
4026 if (code
== JUMP_INSN
|| code
== CALL_INSN
)
4027 dslots_jump_total
++;
4032 /* Output at beginning of assembler file.
4033 If we are optimizing to use the global pointer, create a temporary
4034 file to hold all of the text stuff, and write it out to the end.
4035 This is needed because the MIPS assembler is evidently one pass,
4036 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4037 declaration when the code is processed, it generates a two
4038 instruction sequence. */
4041 mips_asm_file_start (stream
)
4044 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
4046 /* Versions of the MIPS assembler before 2.20 generate errors
4047 if a branch inside of a .set noreorder section jumps to a
4048 label outside of the .set noreorder section. Revision 2.20
4049 just set nobopt silently rather than fixing the bug. */
4051 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
4052 fprintf (stream
, "\t.set\tnobopt\n");
4054 /* Generate the pseudo ops that System V.4 wants. */
4055 #ifndef ABICALLS_ASM_OP
4056 #define ABICALLS_ASM_OP ".abicalls"
4058 if (TARGET_ABICALLS
)
4059 /* ??? but do not want this (or want pic0) if -non-shared? */
4060 fprintf (stream
, "\t%s\n", ABICALLS_ASM_OP
);
4062 /* This code exists so that we can put all externs before all symbol
4063 references. This is necessary for the assembler's global pointer
4064 optimizations to work. */
4065 /* ??? Current versions of gas do not require that externs occur before
4066 symbol references. This means that this code is unnecessary when
4067 gas is being used. This gas feature hasn't been well tested as yet
4071 asm_out_data_file
= stream
;
4072 asm_out_text_file
= make_temp_file ();
4075 asm_out_data_file
= asm_out_text_file
= stream
;
4077 print_options (stream
);
4081 /* If we are optimizing the global pointer, emit the text section now
4082 and any small externs which did not have .comm, etc that are
4083 needed. Also, give a warning if the data area is more than 32K and
4084 -pic because 3 instructions are needed to reference the data
4088 mips_asm_file_end (file
)
4093 struct extern_list
*p
;
4097 HALF_PIC_FINISH (file
);
4103 for (p
= extern_head
; p
!= 0; p
= p
->next
)
4105 name_tree
= get_identifier (p
->name
);
4107 /* Positively ensure only one .extern for any given symbol. */
4108 if (! TREE_ASM_WRITTEN (name_tree
))
4110 TREE_ASM_WRITTEN (name_tree
) = 1;
4111 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4113 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
4117 fputs ("\t.extern\t", file
);
4118 assemble_name (file
, p
->name
);
4119 fprintf (file
, ", %d\n", p
->size
);
4127 fprintf (file
, "\n\t.text\n");
4128 rewind (asm_out_text_file
);
4129 if (ferror (asm_out_text_file
))
4130 fatal_io_error (temp_filename
);
4132 while ((len
= fread (buffer
, 1, sizeof (buffer
), asm_out_text_file
)) > 0)
4133 if (fwrite (buffer
, 1, len
, file
) != len
)
4134 pfatal_with_name (asm_file_name
);
4137 pfatal_with_name (temp_filename
);
4139 if (fclose (asm_out_text_file
) != 0)
4140 pfatal_with_name (temp_filename
);
4143 unlink (temp_filename
);
4149 /* Emit either a label, .comm, or .lcomm directive, and mark
4150 that the symbol is used, so that we don't emit an .extern
4151 for it in mips_asm_file_end. */
4154 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
4161 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
4162 assemble_name (stream
, name
);
4163 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
4167 tree name_tree
= get_identifier (name
);
4168 TREE_ASM_WRITTEN (name_tree
) = 1;
4173 /* Output a double precision value to the assembler. If both the
4174 host and target are IEEE, emit the values in hex. */
4177 mips_output_double (stream
, value
)
4179 REAL_VALUE_TYPE value
;
4181 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4183 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
4185 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4186 value_long
[0], value
, value_long
[1]);
4188 fprintf (stream
, "\t.double\t%.20g\n", value
);
4193 /* Output a single precision value to the assembler. If both the
4194 host and target are IEEE, emit the values in hex. */
4197 mips_output_float (stream
, value
)
4199 REAL_VALUE_TYPE value
;
4201 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4203 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
4205 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
4207 fprintf (stream
, "\t.float\t%.12g\n", value
);
4212 /* Return TRUE if any register used in the epilogue is used. This to insure
4213 any insn put into the epilogue delay slots is safe. */
4216 epilogue_reg_mentioned_p (insn
)
4221 register enum rtx_code code
;
4227 if (GET_CODE (insn
) == LABEL_REF
)
4230 code
= GET_CODE (insn
);
4234 regno
= REGNO (insn
);
4235 if (regno
== STACK_POINTER_REGNUM
)
4238 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4241 if (!call_used_regs
[regno
])
4244 if (regno
!= MIPS_TEMP1_REGNUM
&& regno
!= MIPS_TEMP2_REGNUM
)
4247 if (!current_frame_info
.initialized
)
4248 compute_frame_size (get_frame_size ());
4250 return (current_frame_info
.total_size
>= 32768);
4260 fmt
= GET_RTX_FORMAT (code
);
4261 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4266 for (j
= XVECLEN (insn
, i
) - 1; j
>= 0; j
--)
4267 if (epilogue_reg_mentioned_p (XVECEXP (insn
, i
, j
)))
4270 else if (fmt
[i
] == 'e' && epilogue_reg_mentioned_p (XEXP (insn
, i
)))
4278 /* When generating embedded PIC code we may need to get the address of
4279 the current function. We will need it if we take the address of
4280 any symbol in the .text section. */
4283 mips_finalize_pic ()
4287 if (! TARGET_EMBEDDED_PIC
)
4289 if (embedded_pic_fnaddr_rtx
== NULL
)
4294 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx
,
4295 XEXP (DECL_RTL (current_function_decl
), 0)));
4297 seq
= gen_sequence ();
4299 emit_insn_after (seq
, get_insns ());
4301 embedded_pic_fnaddr_rtx
= NULL
;
4305 /* Return the bytes needed to compute the frame pointer from the current
4308 Mips stack frames look like:
4310 Before call After call
4311 +-----------------------+ +-----------------------+
4314 | caller's temps. | | caller's temps. |
4316 +-----------------------+ +-----------------------+
4318 | arguments on stack. | | arguments on stack. |
4320 +-----------------------+ +-----------------------+
4321 | 4 words to save | | 4 words to save |
4322 | arguments passed | | arguments passed |
4323 | in registers, even | | in registers, even |
4324 SP->| if not passed. | VFP->| if not passed. |
4325 +-----------------------+ +-----------------------+
4327 | fp register save |
4329 +-----------------------+
4331 | gp register save |
4333 +-----------------------+
4337 +-----------------------+
4339 | alloca allocations |
4341 +-----------------------+
4343 | GP save for V.4 abi |
4345 +-----------------------+
4347 | arguments on stack |
4349 +-----------------------+
4351 | arguments passed |
4352 | in registers, even |
4353 low SP->| if not passed. |
4354 memory +-----------------------+
4359 compute_frame_size (size
)
4360 int size
; /* # of var. bytes allocated */
4363 long total_size
; /* # bytes that the entire frame takes up */
4364 long var_size
; /* # bytes that variables take up */
4365 long args_size
; /* # bytes that outgoing arguments take up */
4366 long extra_size
; /* # extra bytes */
4367 long gp_reg_rounded
; /* # bytes needed to store gp after rounding */
4368 long gp_reg_size
; /* # bytes needed to store gp regs */
4369 long fp_reg_size
; /* # bytes needed to store fp regs */
4370 long mask
; /* mask of saved gp registers */
4371 long fmask
; /* mask of saved fp registers */
4372 int fp_inc
; /* 1 or 2 depending on the size of fp regs */
4373 long fp_bits
; /* bitmask to use for each fp register */
4379 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
4380 var_size
= MIPS_STACK_ALIGN (size
);
4381 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
4383 /* The MIPS 3.0 linker does not like functions that dynamically
4384 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4385 looks like we are trying to create a second frame pointer to the
4386 function, so allocate some stack space to make it happy. */
4388 if (args_size
== 0 && current_function_calls_alloca
)
4389 args_size
= 4*UNITS_PER_WORD
;
4391 total_size
= var_size
+ args_size
+ extra_size
;
4393 /* Calculate space needed for gp registers. */
4394 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4396 if (MUST_SAVE_REGISTER (regno
))
4398 gp_reg_size
+= UNITS_PER_WORD
;
4399 mask
|= 1L << (regno
- GP_REG_FIRST
);
4403 /* Calculate space needed for fp registers. */
4415 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= fp_inc
)
4417 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
4419 fp_reg_size
+= fp_inc
* UNITS_PER_FPREG
;
4420 fmask
|= fp_bits
<< (regno
- FP_REG_FIRST
);
4424 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4425 total_size
+= gp_reg_rounded
+ fp_reg_size
;
4427 if (total_size
== extra_size
)
4428 total_size
= extra_size
= 0;
4429 else if (TARGET_ABICALLS
)
4431 /* Add the context-pointer to the saved registers. */
4432 gp_reg_size
+= UNITS_PER_WORD
;
4433 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
4434 total_size
-= gp_reg_rounded
;
4435 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4436 total_size
+= gp_reg_rounded
;
4439 /* Save other computed information. */
4440 current_frame_info
.total_size
= total_size
;
4441 current_frame_info
.var_size
= var_size
;
4442 current_frame_info
.args_size
= args_size
;
4443 current_frame_info
.extra_size
= extra_size
;
4444 current_frame_info
.gp_reg_size
= gp_reg_size
;
4445 current_frame_info
.fp_reg_size
= fp_reg_size
;
4446 current_frame_info
.mask
= mask
;
4447 current_frame_info
.fmask
= fmask
;
4448 current_frame_info
.initialized
= reload_completed
;
4449 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
4450 current_frame_info
.num_fp
= fp_reg_size
/ (fp_inc
* UNITS_PER_FPREG
);
4454 unsigned long offset
= args_size
+ extra_size
+ var_size
4455 + gp_reg_size
- UNITS_PER_WORD
;
4456 current_frame_info
.gp_sp_offset
= offset
;
4457 current_frame_info
.gp_save_offset
= offset
- total_size
;
4461 current_frame_info
.gp_sp_offset
= 0;
4462 current_frame_info
.gp_save_offset
= 0;
4468 unsigned long offset
= (args_size
+ extra_size
+ var_size
4469 + gp_reg_rounded
+ fp_reg_size
4470 - fp_inc
* UNITS_PER_FPREG
);
4471 current_frame_info
.fp_sp_offset
= offset
;
4472 current_frame_info
.fp_save_offset
= offset
- total_size
+ UNITS_PER_WORD
;
4476 current_frame_info
.fp_sp_offset
= 0;
4477 current_frame_info
.fp_save_offset
= 0;
4480 /* Ok, we're done. */
4485 /* Common code to emit the insns (or to write the instructions to a file)
4486 to save/restore registers.
4488 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4489 is not modified within save_restore_insns. */
4491 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4494 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
4495 int store_p
; /* true if this is prologue */
4496 rtx large_reg
; /* register holding large offset constant or NULL */
4497 long large_offset
; /* large constant offset value */
4498 FILE *file
; /* file to write instructions to instead of making RTL */
4500 long mask
= current_frame_info
.mask
;
4501 long fmask
= current_frame_info
.fmask
;
4509 if (frame_pointer_needed
&& !BITSET_P (mask
, FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
4512 if (mask
== 0 && fmask
== 0)
4515 /* Save registers starting from high to low. The debuggers prefer
4516 at least the return register be stored at func+4, and also it
4517 allows us not to need a nop in the epilog if at least one
4518 register is reloaded in addition to return address. */
4520 /* Save GP registers if needed. */
4523 /* Pick which pointer to use as a base register. For small
4524 frames, just use the stack pointer. Otherwise, use a
4525 temporary register. Save 2 cycles if the save area is near
4526 the end of a large frame, by reusing the constant created in
4527 the prologue/epilogue to adjust the stack frame. */
4529 gp_offset
= current_frame_info
.gp_sp_offset
;
4530 end_offset
= gp_offset
- (current_frame_info
.gp_reg_size
- UNITS_PER_WORD
);
4532 if (gp_offset
< 0 || end_offset
< 0)
4533 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
4534 gp_offset
, end_offset
);
4536 else if (gp_offset
< 32768)
4538 base_reg_rtx
= stack_pointer_rtx
;
4542 else if (large_reg
!= (rtx
)0
4543 && (((unsigned long)(large_offset
- gp_offset
)) < 32768)
4544 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
4546 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4547 base_offset
= large_offset
;
4548 if (file
== (FILE *)0)
4551 emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4553 emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4556 fprintf (file
, "\t%s\t%s,%s,%s\n",
4557 TARGET_LONG64
? "daddu" : "addu",
4558 reg_names
[MIPS_TEMP2_REGNUM
],
4559 reg_names
[REGNO (large_reg
)],
4560 reg_names
[STACK_POINTER_REGNUM
]);
4565 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4566 base_offset
= gp_offset
;
4567 if (file
== (FILE *)0)
4569 emit_move_insn (base_reg_rtx
, GEN_INT (gp_offset
));
4571 emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
4573 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
4576 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
4577 reg_names
[MIPS_TEMP2_REGNUM
],
4580 TARGET_LONG64
? "daddu" : "addu",
4581 reg_names
[MIPS_TEMP2_REGNUM
],
4582 reg_names
[MIPS_TEMP2_REGNUM
],
4583 reg_names
[STACK_POINTER_REGNUM
]);
4586 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
4588 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
4590 if (file
== (FILE *)0)
4592 rtx reg_rtx
= gen_rtx (REG
, word_mode
, regno
);
4593 rtx mem_rtx
= gen_rtx (MEM
, word_mode
,
4594 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
4595 GEN_INT (gp_offset
- base_offset
)));
4598 emit_move_insn (mem_rtx
, reg_rtx
);
4599 else if (!TARGET_ABICALLS
4600 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
4601 emit_move_insn (reg_rtx
, mem_rtx
);
4605 if (store_p
|| !TARGET_ABICALLS
4606 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
4607 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
4609 ? (store_p
) ? "sd" : "ld"
4610 : (store_p
) ? "sw" : "lw"),
4612 gp_offset
- base_offset
,
4613 reg_names
[REGNO(base_reg_rtx
)]);
4616 gp_offset
-= UNITS_PER_WORD
;
4622 base_reg_rtx
= (rtx
)0; /* Make sure these are initialzed */
4626 /* Save floating point registers if needed. */
4629 int fp_inc
= (TARGET_FLOAT64
) ? 1 : 2;
4630 int fp_size
= fp_inc
* UNITS_PER_FPREG
;
4632 /* Pick which pointer to use as a base register. */
4633 fp_offset
= current_frame_info
.fp_sp_offset
;
4634 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
- fp_size
);
4636 if (fp_offset
< 0 || end_offset
< 0)
4637 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
4638 fp_offset
, end_offset
);
4640 else if (fp_offset
< 32768)
4642 base_reg_rtx
= stack_pointer_rtx
;
4646 else if (base_reg_rtx
!= (rtx
)0
4647 && (((unsigned long)(base_offset
- fp_offset
)) < 32768)
4648 && (((unsigned long)(base_offset
- end_offset
)) < 32768))
4650 ; /* already set up for gp registers above */
4653 else if (large_reg
!= (rtx
)0
4654 && (((unsigned long)(large_offset
- fp_offset
)) < 32768)
4655 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
4657 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4658 base_offset
= large_offset
;
4659 if (file
== (FILE *)0)
4662 emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4664 emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4667 fprintf (file
, "\t%s\t%s,%s,%s\n",
4668 TARGET_LONG64
? "daddu" : "addu",
4669 reg_names
[MIPS_TEMP2_REGNUM
],
4670 reg_names
[REGNO (large_reg
)],
4671 reg_names
[STACK_POINTER_REGNUM
]);
4676 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4677 base_offset
= fp_offset
;
4678 if (file
== (FILE *)0)
4680 emit_move_insn (base_reg_rtx
, GEN_INT (fp_offset
));
4682 emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
4684 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
4687 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
4688 reg_names
[MIPS_TEMP2_REGNUM
],
4691 TARGET_LONG64
? "daddu" : "addu",
4692 reg_names
[MIPS_TEMP2_REGNUM
],
4693 reg_names
[MIPS_TEMP2_REGNUM
],
4694 reg_names
[STACK_POINTER_REGNUM
]);
4697 for (regno
= FP_REG_LAST
-1; regno
>= FP_REG_FIRST
; regno
-= fp_inc
)
4699 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
4701 if (file
== (FILE *)0)
4703 rtx reg_rtx
= gen_rtx (REG
, DFmode
, regno
);
4704 rtx mem_rtx
= gen_rtx (MEM
, DFmode
,
4705 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
4706 GEN_INT (fp_offset
- base_offset
)));
4709 emit_move_insn (mem_rtx
, reg_rtx
);
4711 emit_move_insn (reg_rtx
, mem_rtx
);
4714 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
4715 (store_p
) ? "s.d" : "l.d",
4717 fp_offset
- base_offset
,
4718 reg_names
[REGNO(base_reg_rtx
)]);
4721 fp_offset
-= fp_size
;
4728 /* Set up the stack and frame (if desired) for the function. */
4731 function_prologue (file
, size
)
4735 long tsize
= current_frame_info
.total_size
;
4737 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
4739 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
4740 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
4742 inside_function
= 1;
4743 fputs ("\t.ent\t", file
);
4744 assemble_name (file
, current_function_name
);
4747 assemble_name (file
, current_function_name
);
4748 fputs (":\n", file
);
4750 fprintf (file
, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
4751 reg_names
[ (frame_pointer_needed
) ? FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
],
4753 reg_names
[31 + GP_REG_FIRST
],
4754 current_frame_info
.var_size
,
4755 current_frame_info
.num_gp
,
4756 current_frame_info
.num_fp
,
4757 current_function_outgoing_args_size
,
4758 current_frame_info
.extra_size
);
4760 fprintf (file
, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
4761 current_frame_info
.mask
,
4762 current_frame_info
.gp_save_offset
,
4763 current_frame_info
.fmask
,
4764 current_frame_info
.fp_save_offset
);
4766 if (TARGET_ABICALLS
)
4768 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
4770 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
4771 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
4774 fprintf (file
, "\t%s\t%s,%s,%d\n",
4775 (TARGET_LONG64
? "dsubu" : "subu"),
4776 sp_str
, sp_str
, tsize
);
4777 fprintf (file
, "\t.cprestore %d\n", current_frame_info
.args_size
);
4783 /* Expand the prologue into a bunch of separate insns. */
4786 mips_expand_prologue ()
4790 rtx tmp_rtx
= (rtx
)0;
4791 char *arg_name
= (char *)0;
4792 tree fndecl
= current_function_decl
;
4793 tree fntype
= TREE_TYPE (fndecl
);
4794 tree fnargs
= (TREE_CODE (fntype
) != METHOD_TYPE
)
4795 ? DECL_ARGUMENTS (fndecl
)
4801 CUMULATIVE_ARGS args_so_far
;
4803 /* If struct value address is treated as the first argument, make it so. */
4804 if (aggregate_value_p (DECL_RESULT (fndecl
))
4805 && ! current_function_returns_pcc_struct
4806 && struct_value_incoming_rtx
== 0)
4808 tree type
= build_pointer_type (fntype
);
4809 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
4810 DECL_ARG_TYPE (function_result_decl
) = type
;
4811 TREE_CHAIN (function_result_decl
) = fnargs
;
4812 fnargs
= function_result_decl
;
4815 /* Determine the last argument, and get its name. */
4817 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, (rtx
)0);
4818 regno
= GP_ARG_FIRST
;
4820 for (cur_arg
= fnargs
; cur_arg
!= (tree
)0; cur_arg
= next_arg
)
4822 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
4823 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
4826 if (TYPE_NEEDS_CONSTRUCTING (passed_type
))
4828 passed_type
= build_pointer_type (passed_type
);
4829 passed_mode
= Pmode
;
4832 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
4838 /* passed in a register, so will get homed automatically */
4839 if (GET_MODE (entry_parm
) == BLKmode
)
4840 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
4842 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
4844 regno
= REGNO (entry_parm
) + words
- 1;
4848 regno
= GP_ARG_LAST
+1;
4852 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
4854 next_arg
= TREE_CHAIN (cur_arg
);
4855 if (next_arg
== (tree
)0)
4857 if (DECL_NAME (cur_arg
))
4858 arg_name
= IDENTIFIER_POINTER (DECL_NAME (cur_arg
));
4864 /* In order to pass small structures by value in registers
4865 compatibly with the MIPS compiler, we need to shift the value
4866 into the high part of the register. Function_arg has encoded a
4867 PARALLEL rtx, holding a vector of adjustments to be made as the
4868 next_arg_reg variable, so we split up the insns, and emit them
4871 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
4872 if (next_arg_reg
!= (rtx
)0 && GET_CODE (next_arg_reg
) == PARALLEL
)
4874 rtvec adjust
= XVEC (next_arg_reg
, 0);
4875 int num
= GET_NUM_ELEM (adjust
);
4877 for (i
= 0; i
< num
; i
++)
4879 rtx pattern
= RTVEC_ELT (adjust
, i
);
4880 if (GET_CODE (pattern
) != SET
4881 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
4882 abort_with_insn (pattern
, "Insn is not a shift");
4884 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
4885 emit_insn (pattern
);
4889 tsize
= compute_frame_size (get_frame_size ());
4891 /* If this function is a varargs function, store any registers that
4892 would normally hold arguments ($4 - $7) on the stack. */
4893 if ((TYPE_ARG_TYPES (fntype
) != 0
4894 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
))) != void_type_node
))
4895 || (arg_name
!= (char *)0
4896 && ((arg_name
[0] == '_' && strcmp (arg_name
, "__builtin_va_alist") == 0)
4897 || (arg_name
[0] == 'v' && strcmp (arg_name
, "va_alist") == 0))))
4899 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
4900 rtx ptr
= stack_pointer_rtx
;
4902 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
4903 if (TARGET_ABICALLS
)
4906 for (; regno
<= GP_ARG_LAST
; regno
++)
4909 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
4910 emit_move_insn (gen_rtx (MEM
, word_mode
, ptr
),
4911 gen_rtx (REG
, word_mode
, regno
));
4912 offset
+= UNITS_PER_WORD
;
4918 rtx tsize_rtx
= GEN_INT (tsize
);
4920 /* If we are doing svr4-abi, sp move is done by function_prologue. */
4921 if (!TARGET_ABICALLS
)
4925 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
4926 emit_move_insn (tmp_rtx
, tsize_rtx
);
4927 tsize_rtx
= tmp_rtx
;
4931 emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
4934 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
4938 save_restore_insns (TRUE
, tmp_rtx
, tsize
, (FILE *)0);
4940 if (frame_pointer_needed
)
4943 emit_insn (gen_movdi (frame_pointer_rtx
, stack_pointer_rtx
));
4945 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
4949 /* If we are profiling, make sure no instructions are scheduled before
4950 the call to mcount. */
4952 if (profile_flag
|| profile_block_flag
)
4953 emit_insn (gen_blockage ());
4957 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
4959 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
4960 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
4963 function_epilogue (file
, size
)
4968 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
4969 char *t1_str
= reg_names
[MIPS_TEMP1_REGNUM
];
4970 rtx epilogue_delay
= current_function_epilogue_delay_list
;
4971 int noreorder
= (epilogue_delay
!= 0);
4972 int noepilogue
= FALSE
;
4973 int load_nop
= FALSE
;
4975 rtx tmp_rtx
= (rtx
)0;
4979 /* The epilogue does not depend on any registers, but the stack
4980 registers, so we assume that if we have 1 pending nop, it can be
4981 ignored, and 2 it must be filled (2 nops occur for integer
4982 multiply and divide). */
4984 if (dslots_number_nops
> 0)
4986 if (dslots_number_nops
== 1)
4988 dslots_number_nops
= 0;
4989 dslots_load_filled
++;
4993 while (--dslots_number_nops
> 0)
4994 fputs ("\t#nop\n", asm_out_file
);
5001 fputs ("\t.set\tat\n", file
);
5002 error ("internal gcc error: .set noat left on in epilogue");
5005 if (set_nomacro
!= 0)
5008 fputs ("\t.set\tmacro\n", file
);
5009 error ("internal gcc error: .set nomacro left on in epilogue");
5012 if (set_noreorder
!= 0)
5015 fputs ("\t.set\treorder\n", file
);
5016 error ("internal gcc error: .set noreorder left on in epilogue");
5019 if (set_volatile
!= 0)
5022 fprintf (file
, "\t%s.set\tnovolatile\n", (TARGET_MIPS_AS
) ? "" : "#");
5023 error ("internal gcc error: .set volatile left on in epilogue");
5026 size
= MIPS_STACK_ALIGN (size
);
5027 tsize
= (!current_frame_info
.initialized
)
5028 ? compute_frame_size (size
)
5029 : current_frame_info
.total_size
;
5031 if (tsize
== 0 && epilogue_delay
== 0)
5033 rtx insn
= get_last_insn ();
5035 /* If the last insn was a BARRIER, we don't have to write any code
5036 because a jump (aka return) was put there. */
5037 if (GET_CODE (insn
) == NOTE
)
5038 insn
= prev_nonnote_insn (insn
);
5039 if (insn
&& GET_CODE (insn
) == BARRIER
)
5047 /* In the reload sequence, we don't need to fill the load delay
5048 slots for most of the loads, also see if we can fill the final
5049 delay slot if not otherwise filled by the reload sequence. */
5052 fprintf (file
, "\t.set\tnoreorder\n");
5056 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n", t1_str
, (long)tsize
, (long)tsize
);
5057 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5060 if (frame_pointer_needed
)
5061 fprintf (file
, "\tmove\t%s,%s\t\t\t# sp not trusted here\n",
5062 sp_str
, reg_names
[FRAME_POINTER_REGNUM
]);
5064 save_restore_insns (FALSE
, tmp_rtx
, tsize
, file
);
5066 load_only_r31
= (((current_frame_info
.mask
5067 & ~ (TARGET_ABICALLS
? PIC_OFFSET_TABLE_MASK
: 0))
5069 && current_frame_info
.fmask
== 0);
5073 /* If the only register saved is the return address, we need a
5074 nop, unless we have an instruction to put into it. Otherwise
5075 we don't since reloading multiple registers doesn't reference
5076 the register being loaded. */
5081 final_scan_insn (XEXP (epilogue_delay
, 0),
5085 1); /* nopeepholes */
5088 fprintf (file
, "\tnop\n");
5093 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5096 fprintf (file
, "\t%s\t%s,%s,%s\n",
5097 TARGET_LONG64
? "daddu" : "addu",
5098 sp_str
, sp_str
, t1_str
);
5101 fprintf (file
, "\t%s\t%s,%s,%d\n",
5102 TARGET_LONG64
? "daddu" : "addu",
5103 sp_str
, sp_str
, tsize
);
5105 else if (!load_only_r31
&& epilogue_delay
!= 0)
5106 final_scan_insn (XEXP (epilogue_delay
, 0),
5110 1); /* nopeepholes */
5112 fprintf (file
, "\t.set\treorder\n");
5118 fprintf (file
, "\t%s\t%s,%s,%s\n",
5119 TARGET_LONG64
? "daddu" : "addu",
5120 sp_str
, sp_str
, t1_str
);
5123 fprintf (file
, "\t%s\t%s,%s,%d\n",
5124 TARGET_LONG64
? "daddu" : "addu",
5125 sp_str
, sp_str
, tsize
);
5127 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5131 fputs ("\t.end\t", file
);
5132 assemble_name (file
, current_function_name
);
5137 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
5138 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
5139 int num_regs
= num_gp_regs
+ num_fp_regs
;
5140 char *name
= current_function_name
;
5145 dslots_load_total
+= num_regs
;
5148 dslots_jump_total
++;
5152 dslots_load_filled
+= num_regs
;
5154 /* If the only register saved is the return register, we
5155 can't fill this register's delay slot. */
5157 if (load_only_r31
&& epilogue_delay
== 0)
5158 dslots_load_filled
--;
5160 if (tsize
> 0 || (!load_only_r31
&& epilogue_delay
!= 0))
5161 dslots_jump_filled
++;
5165 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5167 (frame_pointer_needed
) ? 'y' : 'n',
5168 ((current_frame_info
.mask
& RA_MASK
) != 0) ? 'n' : 'y',
5169 (current_function_calls_alloca
) ? 'y' : 'n',
5170 (current_function_calls_setjmp
) ? 'y' : 'n',
5171 (long)current_frame_info
.total_size
,
5172 (long)current_function_outgoing_args_size
,
5173 num_gp_regs
, num_fp_regs
,
5174 dslots_load_total
, dslots_load_filled
,
5175 dslots_jump_total
, dslots_jump_filled
,
5176 num_refs
[0], num_refs
[1], num_refs
[2]);
5178 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
5180 fprintf (stderr
, " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
5181 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
5184 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
5186 fprintf (stderr
, " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
5187 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
5190 fputc ('\n', stderr
);
5193 /* Reset state info for each function. */
5194 inside_function
= FALSE
;
5195 ignore_line_number
= FALSE
;
5196 dslots_load_total
= 0;
5197 dslots_jump_total
= 0;
5198 dslots_load_filled
= 0;
5199 dslots_jump_filled
= 0;
5203 mips_load_reg
= (rtx
)0;
5204 mips_load_reg2
= (rtx
)0;
5205 current_frame_info
= zero_frame_info
;
5207 /* Restore the output file if optimizing the GP (optimizing the GP causes
5208 the text to be diverted to a tempfile, so that data decls come before
5209 references to the data). */
5212 asm_out_file
= asm_out_data_file
;
5216 /* Expand the epilogue into a bunch of separate insns. */
5219 mips_expand_epilogue ()
5221 long tsize
= current_frame_info
.total_size
;
5222 rtx tsize_rtx
= GEN_INT (tsize
);
5223 rtx tmp_rtx
= (rtx
)0;
5227 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5228 emit_move_insn (tmp_rtx
, tsize_rtx
);
5229 tsize_rtx
= tmp_rtx
;
5234 if (frame_pointer_needed
)
5237 emit_insn (gen_movdi (stack_pointer_rtx
, frame_pointer_rtx
));
5239 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
5242 save_restore_insns (FALSE
, tmp_rtx
, tsize
, (FILE *)0);
5245 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5248 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5252 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
, GP_REG_FIRST
+31)));
5256 /* Define the number of delay slots needed for the function epilogue.
5258 On the mips, we need a slot if either no stack has been allocated,
5259 or the only register saved is the return register. */
5262 mips_epilogue_delay_slots ()
5264 if (!current_frame_info
.initialized
)
5265 (void) compute_frame_size (get_frame_size ());
5267 if (current_frame_info
.total_size
== 0)
5270 if (current_frame_info
.mask
== RA_MASK
&& current_frame_info
.fmask
== 0)
5277 /* Return true if this function is known to have a null epilogue.
5278 This allows the optimizer to omit jumps to jumps if no stack
5282 simple_epilogue_p ()
5284 if (!reload_completed
)
5287 if (current_frame_info
.initialized
)
5288 return current_frame_info
.total_size
== 0;
5290 return (compute_frame_size (get_frame_size ())) == 0;
5293 /* Choose the section to use for the constant rtx expression X that has
5296 mips_select_rtx_section (mode
, x
)
5297 enum machine_mode mode
;
5300 if (TARGET_EMBEDDED_DATA
)
5302 /* For embedded applications, always put constants in read-only data,
5303 in order to reduce RAM usage. */
5308 /* For hosted applications, always put constants in small data if
5309 possible, as this gives the best performance. */
5311 if (GET_MODE_SIZE (mode
) <= mips_section_threshold
5312 && mips_section_threshold
> 0)
5319 /* Choose the section to use for DECL. RELOC is true if its value contains
5320 any relocatable expression. */
5322 mips_select_section (decl
, reloc
)
5326 int size
= int_size_in_bytes (TREE_TYPE (decl
));
5328 if (TARGET_EMBEDDED_PIC
5329 && TREE_CODE (decl
) == STRING_CST
5330 && !flag_writable_strings
)
5332 /* For embedded position independent code, put constant strings
5333 in the text section, because the data section is limited to
5338 else if (TARGET_EMBEDDED_DATA
)
5340 /* For embedded applications, always put an object in read-only data
5341 if possible, in order to reduce RAM usage. */
5343 if (((TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5344 && DECL_INITIAL (decl
)
5345 && (DECL_INITIAL (decl
) == error_mark_node
5346 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5347 /* Deal with calls from output_constant_def_contents. */
5348 || (TREE_CODE (decl
) != VAR_DECL
5349 && (TREE_CODE (decl
) != STRING_CST
5350 || !flag_writable_strings
)))
5351 && ! (flag_pic
&& reloc
))
5353 else if (size
> 0 && size
<= mips_section_threshold
)
5360 /* For hosted applications, always put an object in small data if
5361 possible, as this gives the best performance. */
5363 if (size
> 0 && size
<= mips_section_threshold
)
5365 else if (((TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5366 && DECL_INITIAL (decl
)
5367 && (DECL_INITIAL (decl
) == error_mark_node
5368 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5369 /* Deal with calls from output_constant_def_contents. */
5370 || (TREE_CODE (decl
) != VAR_DECL
5371 && (TREE_CODE (decl
) != STRING_CST
5372 || !flag_writable_strings
)))
5373 && ! (flag_pic
&& reloc
))