1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-95, 1996 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-flags.h"
37 #include "insn-attr.h"
38 #include "insn-codes.h"
42 #undef MAX /* sys/param.h may also define these */
47 #include <sys/types.h>
60 #if defined(USG) || defined(NO_STAB_H)
61 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
63 #include <stab.h> /* On BSD, use the system's stab.h. */
67 #define STAB_CODE_TYPE enum __stab_debug_code
69 #define STAB_CODE_TYPE int
74 extern char *getenv ();
75 extern char *mktemp ();
77 extern rtx
adj_offsettable_operand ();
78 extern rtx
copy_to_reg ();
81 extern tree
lookup_name ();
82 extern void pfatal_with_name ();
83 extern void warning ();
85 extern FILE *asm_out_file
;
87 /* Enumeration for all of the relational tests, so that we can build
88 arrays indexed by the test type, and not worry about the order
105 /* Global variables for machine-dependent things. */
107 /* Threshold for data being put into the small data/bss area, instead
108 of the normal data area (references to the small data/bss area take
109 1 instruction, and use the global pointer, references to the normal
110 data area takes 2 instructions). */
111 int mips_section_threshold
= -1;
113 /* Count the number of .file directives, so that .loc is up to date. */
114 int num_source_filenames
= 0;
116 /* Count the number of sdb related labels are generated (to find block
117 start and end boundaries). */
118 int sdb_label_count
= 0;
120 /* Next label # for each statement for Silicon Graphics IRIS systems. */
123 /* Non-zero if inside of a function, because the stupid MIPS asm can't
124 handle .files inside of functions. */
125 int inside_function
= 0;
127 /* Files to separate the text and the data output, so that all of the data
128 can be emitted before the text, which will mean that the assembler will
129 generate smaller code, based on the global pointer. */
130 FILE *asm_out_data_file
;
131 FILE *asm_out_text_file
;
133 /* Linked list of all externals that are to be emitted when optimizing
134 for the global pointer if they haven't been declared by the end of
135 the program with an appropriate .comm or initialization. */
138 struct extern_list
*next
; /* next external */
139 char *name
; /* name of the external */
140 int size
; /* size in bytes */
143 /* Name of the file containing the current function. */
144 char *current_function_file
= "";
146 /* Warning given that Mips ECOFF can't support changing files
147 within a function. */
148 int file_in_function_warning
= FALSE
;
150 /* Whether to suppress issuing .loc's because the user attempted
151 to change the filename within a function. */
152 int ignore_line_number
= FALSE
;
154 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
160 /* The next branch instruction is a branch likely, not branch normal. */
161 int mips_branch_likely
;
163 /* Count of delay slots and how many are filled. */
164 int dslots_load_total
;
165 int dslots_load_filled
;
166 int dslots_jump_total
;
167 int dslots_jump_filled
;
169 /* # of nops needed by previous insn */
170 int dslots_number_nops
;
172 /* Number of 1/2/3 word references to data items (ie, not jal's). */
175 /* registers to check for load delay */
176 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
178 /* Cached operands, and operator to compare for use in set/branch on
182 /* what type of branch to use */
183 enum cmp_type branch_type
;
185 /* Number of previously seen half-pic pointers and references. */
186 static int prev_half_pic_ptrs
= 0;
187 static int prev_half_pic_refs
= 0;
189 /* which cpu are we scheduling for */
190 enum processor_type mips_cpu
;
192 /* which instruction set architecture to use. */
195 #ifdef MIPS_ABI_DEFAULT
196 /* which ABI to use. This is defined to a constant in mips.h if the target
197 doesn't support multiple ABIs. */
198 enum mips_abi_type mips_abi
;
201 /* Strings to hold which cpu and instruction set architecture to use. */
202 char *mips_cpu_string
; /* for -mcpu=<xxx> */
203 char *mips_isa_string
; /* for -mips{1,2,3,4} */
204 char *mips_abi_string
; /* for -mabi={o32,32,n32,n64,64} */
206 /* If TRUE, we split addresses into their high and low parts in the RTL. */
207 int mips_split_addresses
;
209 /* Generating calls to position independent functions? */
210 enum mips_abicalls_type mips_abicalls
;
212 /* High and low marks for floating point values which we will accept
213 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
214 initialized in override_options. */
215 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
217 /* Array giving truth value on whether or not a given hard register
218 can support a given mode. */
219 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
221 /* Current frame information calculated by compute_frame_size. */
222 struct mips_frame_info current_frame_info
;
224 /* Zero structure to initialize current_frame_info. */
225 struct mips_frame_info zero_frame_info
;
227 /* Temporary filename used to buffer .text until end of program
229 static char *temp_filename
;
231 /* Pseudo-reg holding the address of the current function when
232 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
233 by mips_finalize_pic if it was created. */
234 rtx embedded_pic_fnaddr_rtx
;
236 /* List of all MIPS punctuation characters used by print_operand. */
237 char mips_print_operand_punct
[256];
239 /* Map GCC register number to debugger register number. */
240 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
242 /* Buffer to use to enclose a load/store operation with %{ %} to
243 turn on .set volatile. */
244 static char volatile_buffer
[60];
246 /* Hardware names for the registers. If -mrnames is used, this
247 will be overwritten with mips_sw_reg_names. */
249 char mips_reg_names
[][8] =
251 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
252 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
253 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
254 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
255 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
256 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
257 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
258 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
259 "hi", "lo", "accum","$fcr31","$rap"
262 /* Mips software names for the registers, used to overwrite the
263 mips_reg_names array. */
265 char mips_sw_reg_names
[][8] =
267 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
268 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
269 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
270 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
271 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
272 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
273 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
274 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
275 "hi", "lo", "accum","$fcr31","$rap"
278 /* Map hard register number to register class */
279 enum reg_class mips_regno_to_class
[] =
281 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
282 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
283 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
284 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
285 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
286 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
287 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
288 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
289 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
290 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
291 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
292 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
293 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
294 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
295 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
296 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
297 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
301 /* Map register constraint character to register class. */
302 enum reg_class mips_char_to_class
[256] =
304 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
305 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
306 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
307 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
308 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
309 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
310 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
311 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
312 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
313 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
314 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
315 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
316 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
317 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
318 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
319 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
320 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
321 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
322 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
323 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
324 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
325 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
326 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
327 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
328 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
329 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
330 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
331 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
332 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
333 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
334 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
335 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
336 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
337 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
338 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
339 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
340 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
341 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
342 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
343 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
344 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
345 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
346 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
347 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
348 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
349 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
350 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
351 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
352 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
353 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
354 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
355 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
356 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
357 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
358 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
359 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
360 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
361 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
362 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
363 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
364 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
365 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
366 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
367 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
371 /* Return truth value of whether OP can be used as an operands
372 where a register or 16 bit unsigned integer is needed. */
375 uns_arith_operand (op
, mode
)
377 enum machine_mode mode
;
379 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
382 return register_operand (op
, mode
);
385 /* Return truth value of whether OP can be used as an operands
386 where a 16 bit integer is needed */
389 arith_operand (op
, mode
)
391 enum machine_mode mode
;
393 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
396 return register_operand (op
, mode
);
399 /* Return truth value of whether OP can be used as an operand in a two
400 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
403 arith32_operand (op
, mode
)
405 enum machine_mode mode
;
407 if (GET_CODE (op
) == CONST_INT
)
410 return register_operand (op
, mode
);
413 /* Return truth value of whether OP is a integer which fits in 16 bits */
418 enum machine_mode mode
;
420 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
423 /* Return truth value of whether OP is a 32 bit integer which is too big to
424 be loaded with one instruction. */
429 enum machine_mode mode
;
433 if (GET_CODE (op
) != CONST_INT
)
437 if ((value
& ~0x0000ffff) == 0) /* ior reg,$r0,value */
440 if (((unsigned long)(value
+ 32768)) <= 32767) /* subu reg,$r0,value */
443 if ((value
& 0x0000ffff) == 0) /* lui reg,value>>16 */
449 /* Return truth value of whether OP is a register or the constant 0. */
452 reg_or_0_operand (op
, mode
)
454 enum machine_mode mode
;
456 switch (GET_CODE (op
))
462 return (INTVAL (op
) == 0);
465 if (op
!= CONST0_RTX (mode
))
472 return register_operand (op
, mode
);
478 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
481 mips_const_double_ok (op
, mode
)
483 enum machine_mode mode
;
487 if (GET_CODE (op
) != CONST_DOUBLE
)
490 if (mode
== VOIDmode
)
493 if (mode
!= SFmode
&& mode
!= DFmode
)
496 if (op
== CONST0_RTX (mode
))
499 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
500 if (mips_abi
!= ABI_32
)
503 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
505 if (REAL_VALUE_ISNAN (d
))
508 if (REAL_VALUE_NEGATIVE (d
))
509 d
= REAL_VALUE_NEGATE (d
);
513 if (REAL_VALUES_LESS (d
, dfhigh
)
514 && REAL_VALUES_LESS (dflow
, d
))
519 if (REAL_VALUES_LESS (d
, sfhigh
)
520 && REAL_VALUES_LESS (sflow
, d
))
527 /* Return truth value if a memory operand fits in a single instruction
528 (ie, register + small offset). */
531 simple_memory_operand (op
, mode
)
533 enum machine_mode mode
;
535 rtx addr
, plus0
, plus1
;
537 /* Eliminate non-memory operations */
538 if (GET_CODE (op
) != MEM
)
541 /* dword operations really put out 2 instructions, so eliminate them. */
542 /* ??? This isn't strictly correct. It is OK to accept multiword modes
543 here, since the length attributes are being set correctly, but only
544 if the address is offsettable. LO_SUM is not offsettable. */
545 if (GET_MODE_SIZE (GET_MODE (op
)) > UNITS_PER_WORD
)
548 /* Decode the address now. */
550 switch (GET_CODE (addr
))
560 return SMALL_INT (op
);
563 plus0
= XEXP (addr
, 0);
564 plus1
= XEXP (addr
, 1);
565 if (GET_CODE (plus0
) == REG
566 && GET_CODE (plus1
) == CONST_INT
567 && SMALL_INT (plus1
))
570 else if (GET_CODE (plus1
) == REG
571 && GET_CODE (plus0
) == CONST_INT
572 && SMALL_INT (plus0
))
579 /* We used to allow small symbol refs here (ie, stuff in .sdata
580 or .sbss), but this causes some bugs in G++. Also, it won't
581 interfere if the MIPS linker rewrites the store instruction
582 because the function is PIC. */
584 case LABEL_REF
: /* never gp relative */
588 /* If -G 0, we can never have a GP relative memory operation.
589 Also, save some time if not optimizing. */
594 rtx offset
= const0_rtx
;
595 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
596 if (GET_CODE (op
) != SYMBOL_REF
)
599 /* let's be paranoid.... */
600 if (! SMALL_INT (offset
))
606 return SYMBOL_REF_FLAG (addr
);
613 /* Return true if the code of this rtx pattern is EQ or NE. */
616 equality_op (op
, mode
)
618 enum machine_mode mode
;
620 if (mode
!= GET_MODE (op
))
623 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
626 /* Return true if the code is a relational operations (EQ, LE, etc.) */
631 enum machine_mode mode
;
633 if (mode
!= GET_MODE (op
))
636 return (GET_RTX_CLASS (GET_CODE (op
)) == '<');
639 /* Return true if the operand is either the PC or a label_ref. */
642 pc_or_label_operand (op
, mode
)
644 enum machine_mode mode
;
649 if (GET_CODE (op
) == LABEL_REF
)
655 /* Test for a valid operand for a call instruction.
656 Don't allow the arg pointer register or virtual regs
657 since they may change into reg + const, which the patterns
661 call_insn_operand (op
, mode
)
663 enum machine_mode mode
;
665 if (CONSTANT_ADDRESS_P (op
)
666 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
667 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
668 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)))
673 /* Return true if OPERAND is valid as a source operand for a move
677 move_operand (op
, mode
)
679 enum machine_mode mode
;
681 return (general_operand (op
, mode
)
682 && ! (mips_split_addresses
&& mips_check_split (op
, mode
)));
685 /* Return true if we split the address into high and low parts. */
687 /* ??? We should also handle reg+array somewhere. We get four
688 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
689 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
690 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
691 out of the address, then we have 4 instructions to combine. Perhaps
692 add a 3->2 define_split for combine. */
694 /* ??? We could also split a CONST_INT here if it is a large_int().
695 However, it doesn't seem to be very useful to have %hi(constant).
696 We would be better off by doing the masking ourselves and then putting
697 the explicit high part of the constant in the RTL. This will give better
698 optimization. Also, %hi(constant) needs assembler changes to work.
699 There is already a define_split that does this. */
702 mips_check_split (address
, mode
)
704 enum machine_mode mode
;
706 /* ??? This is the same check used in simple_memory_operand.
707 We use it here because LO_SUM is not offsettable. */
708 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
711 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
712 || (GET_CODE (address
) == CONST
713 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
714 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
715 || GET_CODE (address
) == LABEL_REF
)
721 /* Returns an operand string for the given instruction's delay slot,
722 after updating filled delay slot statistics.
724 We assume that operands[0] is the target register that is set.
726 In order to check the next insn, most of this functionality is moved
727 to FINAL_PRESCAN_INSN, and we just set the global variables that
730 /* ??? This function no longer does anything useful, because final_prescan_insn
731 now will never emit a nop. */
734 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
735 char *ret
; /* normal string to return */
736 enum delay_type type
; /* type of delay */
737 rtx operands
[]; /* operands to use */
738 rtx cur_insn
; /* current insn */
740 register rtx set_reg
;
741 register enum machine_mode mode
;
742 register rtx next_insn
= (cur_insn
) ? NEXT_INSN (cur_insn
) : (rtx
)0;
743 register int num_nops
;
745 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
748 else if (type
== DELAY_HILO
)
754 /* Make sure that we don't put nop's after labels. */
755 next_insn
= NEXT_INSN (cur_insn
);
756 while (next_insn
!= (rtx
)0 && GET_CODE (next_insn
) == NOTE
)
757 next_insn
= NEXT_INSN (next_insn
);
759 dslots_load_total
+= num_nops
;
760 if (TARGET_DEBUG_F_MODE
762 || type
== DELAY_NONE
763 || operands
== (rtx
*)0
764 || cur_insn
== (rtx
)0
765 || next_insn
== (rtx
)0
766 || GET_CODE (next_insn
) == CODE_LABEL
767 || (set_reg
= operands
[0]) == (rtx
)0)
769 dslots_number_nops
= 0;
770 mips_load_reg
= (rtx
)0;
771 mips_load_reg2
= (rtx
)0;
772 mips_load_reg3
= (rtx
)0;
773 mips_load_reg4
= (rtx
)0;
777 set_reg
= operands
[0];
778 if (set_reg
== (rtx
)0)
781 while (GET_CODE (set_reg
) == SUBREG
)
782 set_reg
= SUBREG_REG (set_reg
);
784 mode
= GET_MODE (set_reg
);
785 dslots_number_nops
= num_nops
;
786 mips_load_reg
= set_reg
;
787 if (GET_MODE_SIZE (mode
)
788 > (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
789 mips_load_reg2
= gen_rtx (REG
, SImode
, REGNO (set_reg
) + 1);
793 if (type
== DELAY_HILO
)
795 mips_load_reg3
= gen_rtx (REG
, SImode
, MD_REG_FIRST
);
796 mips_load_reg4
= gen_rtx (REG
, SImode
, MD_REG_FIRST
+1);
808 /* Determine whether a memory reference takes one (based off of the GP pointer),
809 two (normal), or three (label + reg) instructions, and bump the appropriate
810 counter for -mstats. */
813 mips_count_memory_refs (op
, num
)
819 rtx addr
, plus0
, plus1
;
820 enum rtx_code code0
, code1
;
823 if (TARGET_DEBUG_B_MODE
)
825 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
829 /* Skip MEM if passed, otherwise handle movsi of address. */
830 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
832 /* Loop, going through the address RTL */
836 switch (GET_CODE (addr
))
847 plus0
= XEXP (addr
, 0);
848 plus1
= XEXP (addr
, 1);
849 code0
= GET_CODE (plus0
);
850 code1
= GET_CODE (plus1
);
860 if (code0
== CONST_INT
)
875 if (code1
== CONST_INT
)
882 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
889 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
899 n_words
= 2; /* always 2 words */
903 addr
= XEXP (addr
, 0);
908 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
917 n_words
+= additional
;
921 num_refs
[n_words
-1] += num
;
925 /* Return RTL for the offset from the current function to the
929 embedded_pic_offset (x
)
932 if (embedded_pic_fnaddr_rtx
== NULL
)
936 embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
938 /* Output code at function start to initialize the pseudo-reg. */
939 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
940 inline functions, because it is called after RTL for the function
941 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
942 does not get copied, and ends up not matching the rest of the RTL.
943 This solution works, but means that we get unnecessary code to
944 initialize this value every time a function is inlined into another
947 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx
,
948 XEXP (DECL_RTL (current_function_decl
), 0)));
949 seq
= gen_sequence ();
951 push_topmost_sequence ();
952 emit_insn_after (seq
, get_insns ());
953 pop_topmost_sequence ();
956 return gen_rtx (CONST
, Pmode
,
957 gen_rtx (MINUS
, Pmode
, x
,
958 XEXP (DECL_RTL (current_function_decl
), 0)));
961 /* Return the appropriate instructions to move one operand to another. */
964 mips_move_1word (operands
, insn
, unsignedp
)
970 rtx op0
= operands
[0];
971 rtx op1
= operands
[1];
972 enum rtx_code code0
= GET_CODE (op0
);
973 enum rtx_code code1
= GET_CODE (op1
);
974 enum machine_mode mode
= GET_MODE (op0
);
975 int subreg_word0
= 0;
976 int subreg_word1
= 0;
977 enum delay_type delay
= DELAY_NONE
;
979 while (code0
== SUBREG
)
981 subreg_word0
+= SUBREG_WORD (op0
);
982 op0
= SUBREG_REG (op0
);
983 code0
= GET_CODE (op0
);
986 while (code1
== SUBREG
)
988 subreg_word1
+= SUBREG_WORD (op1
);
989 op1
= SUBREG_REG (op1
);
990 code1
= GET_CODE (op1
);
995 int regno0
= REGNO (op0
) + subreg_word0
;
999 int regno1
= REGNO (op1
) + subreg_word1
;
1001 /* Just in case, don't do anything for assigning a register
1002 to itself, unless we are filling a delay slot. */
1003 if (regno0
== regno1
&& set_nomacro
== 0)
1006 else if (GP_REG_P (regno0
))
1008 if (GP_REG_P (regno1
))
1009 ret
= "move\t%0,%1";
1011 else if (MD_REG_P (regno1
))
1014 if (regno1
!= HILO_REGNUM
)
1023 if (FP_REG_P (regno1
))
1024 ret
= "mfc1\t%0,%1";
1026 else if (regno1
== FPSW_REGNUM
)
1027 ret
= "cfc1\t%0,$31";
1031 else if (FP_REG_P (regno0
))
1033 if (GP_REG_P (regno1
))
1036 ret
= "mtc1\t%1,%0";
1039 if (FP_REG_P (regno1
))
1040 ret
= "mov.s\t%0,%1";
1043 else if (MD_REG_P (regno0
))
1045 if (GP_REG_P (regno1
))
1048 if (regno0
!= HILO_REGNUM
)
1053 else if (regno0
== FPSW_REGNUM
)
1055 if (GP_REG_P (regno1
))
1058 ret
= "ctc1\t%0,$31";
1063 else if (code1
== MEM
)
1068 mips_count_memory_refs (op1
, 1);
1070 if (GP_REG_P (regno0
))
1072 /* For loads, use the mode of the memory item, instead of the
1073 target, so zero/sign extend can use this code as well. */
1074 switch (GET_MODE (op1
))
1082 ret
= ((unsignedp
&& TARGET_64BIT
)
1087 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
1090 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
1095 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
1098 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1100 int i
= strlen (ret
);
1101 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1104 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1105 ret
= volatile_buffer
;
1109 else if (code1
== CONST_INT
1110 || (code1
== CONST_DOUBLE
1111 && GET_MODE (op1
) == VOIDmode
))
1113 if (code1
== CONST_DOUBLE
)
1115 /* This can happen when storing constants into long long
1116 bitfields. Just store the least significant word of
1118 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
1121 if (INTVAL (op1
) == 0)
1123 if (GP_REG_P (regno0
))
1124 ret
= "move\t%0,%z1";
1126 else if (FP_REG_P (regno0
))
1129 ret
= "mtc1\t%z1,%0";
1132 else if (MD_REG_P (regno0
))
1139 else if (GP_REG_P (regno0
))
1140 /* Don't use X format, because that will give out of range
1141 numbers for 64 bit host and 32 bit target. */
1142 ret
= "li\t%0,%1\t\t\t# %X1";
1145 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
1147 if (op1
== CONST0_RTX (SFmode
))
1149 if (GP_REG_P (regno0
))
1150 ret
= "move\t%0,%.";
1152 else if (FP_REG_P (regno0
))
1155 ret
= "mtc1\t%.,%0";
1162 ret
= "li.s\t%0,%1";
1166 else if (code1
== LABEL_REF
)
1169 mips_count_memory_refs (op1
, 1);
1174 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
1176 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
1178 rtx offset
= const0_rtx
;
1180 if (GET_CODE (op1
) == CONST
)
1181 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
1183 if (GET_CODE (op1
) == SYMBOL_REF
)
1185 operands
[2] = HALF_PIC_PTR (op1
);
1188 mips_count_memory_refs (operands
[2], 1);
1190 if (INTVAL (offset
) == 0)
1193 ret
= (unsignedp
&& TARGET_64BIT
1199 dslots_load_total
++;
1200 operands
[3] = offset
;
1201 if (unsignedp
&& TARGET_64BIT
)
1202 ret
= (SMALL_INT (offset
))
1203 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1204 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1206 ret
= (SMALL_INT (offset
))
1207 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1208 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1215 mips_count_memory_refs (op1
, 1);
1221 else if (code1
== PLUS
)
1223 rtx add_op0
= XEXP (op1
, 0);
1224 rtx add_op1
= XEXP (op1
, 1);
1226 if (GET_CODE (XEXP (op1
, 1)) == REG
&& GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
1228 add_op0
= XEXP (op1
, 1); /* reverse operands */
1229 add_op1
= XEXP (op1
, 0);
1232 operands
[2] = add_op0
;
1233 operands
[3] = add_op1
;
1234 ret
= "add%:\t%0,%2,%3";
1237 else if (code1
== HIGH
)
1239 operands
[1] = XEXP (op1
, 0);
1240 ret
= "lui\t%0,%%hi(%1)";
1244 else if (code0
== MEM
)
1247 mips_count_memory_refs (op0
, 1);
1251 int regno1
= REGNO (op1
) + subreg_word1
;
1253 if (GP_REG_P (regno1
))
1258 case SFmode
: ret
= "sw\t%1,%0"; break;
1259 case SImode
: ret
= "sw\t%1,%0"; break;
1260 case HImode
: ret
= "sh\t%1,%0"; break;
1261 case QImode
: ret
= "sb\t%1,%0"; break;
1265 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
1269 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1274 case SFmode
: ret
= "sw\t%z1,%0"; break;
1275 case SImode
: ret
= "sw\t%z1,%0"; break;
1276 case HImode
: ret
= "sh\t%z1,%0"; break;
1277 case QImode
: ret
= "sb\t%z1,%0"; break;
1281 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
1286 case SFmode
: ret
= "sw\t%.,%0"; break;
1287 case SImode
: ret
= "sw\t%.,%0"; break;
1288 case HImode
: ret
= "sh\t%.,%0"; break;
1289 case QImode
: ret
= "sb\t%.,%0"; break;
1293 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1295 int i
= strlen (ret
);
1296 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1299 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1300 ret
= volatile_buffer
;
1304 if (ret
== (char *)0)
1306 abort_with_insn (insn
, "Bad move");
1310 if (delay
!= DELAY_NONE
)
1311 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1317 /* Return the appropriate instructions to move 2 words */
1320 mips_move_2words (operands
, insn
)
1325 rtx op0
= operands
[0];
1326 rtx op1
= operands
[1];
1327 enum rtx_code code0
= GET_CODE (operands
[0]);
1328 enum rtx_code code1
= GET_CODE (operands
[1]);
1329 int subreg_word0
= 0;
1330 int subreg_word1
= 0;
1331 enum delay_type delay
= DELAY_NONE
;
1333 while (code0
== SUBREG
)
1335 subreg_word0
+= SUBREG_WORD (op0
);
1336 op0
= SUBREG_REG (op0
);
1337 code0
= GET_CODE (op0
);
1340 while (code1
== SUBREG
)
1342 subreg_word1
+= SUBREG_WORD (op1
);
1343 op1
= SUBREG_REG (op1
);
1344 code1
= GET_CODE (op1
);
1349 int regno0
= REGNO (op0
) + subreg_word0
;
1353 int regno1
= REGNO (op1
) + subreg_word1
;
1355 /* Just in case, don't do anything for assigning a register
1356 to itself, unless we are filling a delay slot. */
1357 if (regno0
== regno1
&& set_nomacro
== 0)
1360 else if (FP_REG_P (regno0
))
1362 if (FP_REG_P (regno1
))
1363 ret
= "mov.d\t%0,%1";
1371 abort_with_insn (insn
, "Bad move");
1372 #ifdef TARGET_FP_CALL_32
1373 if (FP_CALL_GP_REG_P (regno1
))
1374 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1377 ret
= "dmtc1\t%1,%0";
1380 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1384 else if (FP_REG_P (regno1
))
1390 abort_with_insn (insn
, "Bad move");
1391 #ifdef TARGET_FP_CALL_32
1392 if (FP_CALL_GP_REG_P (regno0
))
1393 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1396 ret
= "dmfc1\t%0,%1";
1399 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1402 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
))
1407 if (regno0
!= HILO_REGNUM
)
1409 else if (regno1
== 0)
1410 ret
= "mtlo\t%.\n\tmthi\t%.";
1413 ret
= "mthi\t%M1\n\tmtlo\t%L1";
1416 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
1421 if (regno1
!= HILO_REGNUM
)
1425 ret
= "mfhi\t%M0\n\tmflo\t%L0";
1428 else if (TARGET_64BIT
)
1429 ret
= "move\t%0,%1";
1431 else if (regno0
!= (regno1
+1))
1432 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
1435 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
1438 else if (code1
== CONST_DOUBLE
)
1440 /* Move zero from $0 unless !TARGET_64BIT and recipient
1441 is 64-bit fp reg, in which case generate a constant. */
1442 if (op1
!= CONST0_RTX (GET_MODE (op1
))
1443 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
1445 if (GET_MODE (op1
) == DFmode
)
1448 #ifdef TARGET_FP_CALL_32
1449 if (FP_CALL_GP_REG_P (regno0
))
1451 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
1453 split_double (op1
, operands
+ 2, operands
+ 3);
1454 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1457 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1461 ret
= "li.d\t%0,%1";
1464 else if (TARGET_64BIT
)
1469 split_double (op1
, operands
+ 2, operands
+ 3);
1470 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1476 if (GP_REG_P (regno0
))
1478 #ifdef TARGET_FP_CALL_32
1479 && ! FP_CALL_GP_REG_P (regno0
)
1483 : "move\t%0,%.\n\tmove\t%D0,%.";
1485 else if (FP_REG_P (regno0
))
1488 ret
= (TARGET_64BIT
)
1490 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1495 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1497 if (GP_REG_P (regno0
))
1498 ret
= (TARGET_64BIT
)
1500 : "move\t%0,%.\n\tmove\t%D0,%.";
1502 else if (FP_REG_P (regno0
))
1505 ret
= (TARGET_64BIT
)
1509 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1511 else if (MD_REG_P (regno0
))
1514 if (regno0
!= HILO_REGNUM
)
1517 ret
= "mtlo\t%.\n\tmthi\t%.";
1521 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
&& GP_REG_P (regno0
))
1525 if (HOST_BITS_PER_WIDE_INT
< 64)
1526 /* We can't use 'X' for negative numbers, because then we won't
1527 get the right value for the upper 32 bits. */
1528 ret
= ((INTVAL (op1
) < 0) ? "dli\t%0,%1\t\t\t# %X1"
1529 : "dli\t%0,%X1\t\t# %1");
1531 /* We must use 'X', because otherwise LONG_MIN will print as
1532 a number that the assembler won't accept. */
1533 ret
= "dli\t%0,%X1\t\t# %1";
1535 else if (HOST_BITS_PER_WIDE_INT
< 64)
1537 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
1538 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1542 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 32);
1543 operands
[1] = GEN_INT (INTVAL (operands
[1]) << 32 >> 32);
1544 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1548 else if (code1
== MEM
)
1553 mips_count_memory_refs (op1
, 2);
1555 if (FP_REG_P (regno0
))
1558 else if (TARGET_64BIT
)
1560 #ifdef TARGET_FP_CALL_32
1561 if (FP_CALL_GP_REG_P (regno0
))
1563 if (offsettable_address_p (FALSE
, SImode
, op1
))
1564 ret
= "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1566 ret
= "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1573 else if (offsettable_address_p (1, DFmode
, XEXP (op1
, 0)))
1575 operands
[2] = adj_offsettable_operand (op1
, 4);
1576 if (reg_mentioned_p (op0
, op1
))
1577 ret
= "lw\t%D0,%2\n\tlw\t%0,%1";
1579 ret
= "lw\t%0,%1\n\tlw\t%D0,%2";
1582 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1584 int i
= strlen (ret
);
1585 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1588 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1589 ret
= volatile_buffer
;
1593 else if (code1
== LABEL_REF
1594 || code1
== SYMBOL_REF
1598 mips_count_memory_refs (op1
, 2);
1600 ret
= "dla\t%0,%a1";
1604 else if (code0
== MEM
)
1608 int regno1
= REGNO (op1
) + subreg_word1
;
1610 if (FP_REG_P (regno1
))
1613 else if (TARGET_64BIT
)
1615 #ifdef TARGET_FP_CALL_32
1616 if (FP_CALL_GP_REG_P (regno1
))
1617 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1623 else if (offsettable_address_p (1, DFmode
, XEXP (op0
, 0)))
1625 operands
[2] = adj_offsettable_operand (op0
, 4);
1626 ret
= "sw\t%1,%0\n\tsw\t%D1,%2";
1630 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
1631 || (code1
== CONST_DOUBLE
1632 && op1
== CONST0_RTX (GET_MODE (op1
))))
1634 || offsettable_address_p (1, DFmode
, XEXP (op0
, 0))))
1640 operands
[2] = adj_offsettable_operand (op0
, 4);
1641 ret
= "sw\t%.,%0\n\tsw\t%.,%2";
1646 mips_count_memory_refs (op0
, 2);
1648 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1650 int i
= strlen (ret
);
1651 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1654 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1655 ret
= volatile_buffer
;
1659 if (ret
== (char *)0)
1661 abort_with_insn (insn
, "Bad move");
1665 if (delay
!= DELAY_NONE
)
1666 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1672 /* Provide the costs of an addressing mode that contains ADDR.
1673 If ADDR is not a valid address, its cost is irrelevant. */
1676 mips_address_cost (addr
)
1679 switch (GET_CODE (addr
))
1692 rtx offset
= const0_rtx
;
1693 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
1694 if (GET_CODE (addr
) == LABEL_REF
)
1697 if (GET_CODE (addr
) != SYMBOL_REF
)
1700 if (! SMALL_INT (offset
))
1706 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1710 register rtx plus0
= XEXP (addr
, 0);
1711 register rtx plus1
= XEXP (addr
, 1);
1713 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1715 plus0
= XEXP (addr
, 1);
1716 plus1
= XEXP (addr
, 0);
1719 if (GET_CODE (plus0
) != REG
)
1722 switch (GET_CODE (plus1
))
1728 return (SMALL_INT (plus1
) ? 1 : 2);
1735 return mips_address_cost (plus1
) + 1;
1743 /* Return true if X is an address which needs a temporary register when
1744 reloaded while generating PIC code. */
1747 pic_address_needs_scratch (x
)
1750 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1751 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1752 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1753 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1754 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1760 /* Make normal rtx_code into something we can index from an array */
1762 static enum internal_test
1763 map_test_to_internal_test (test_code
)
1764 enum rtx_code test_code
;
1766 enum internal_test test
= ITEST_MAX
;
1771 case EQ
: test
= ITEST_EQ
; break;
1772 case NE
: test
= ITEST_NE
; break;
1773 case GT
: test
= ITEST_GT
; break;
1774 case GE
: test
= ITEST_GE
; break;
1775 case LT
: test
= ITEST_LT
; break;
1776 case LE
: test
= ITEST_LE
; break;
1777 case GTU
: test
= ITEST_GTU
; break;
1778 case GEU
: test
= ITEST_GEU
; break;
1779 case LTU
: test
= ITEST_LTU
; break;
1780 case LEU
: test
= ITEST_LEU
; break;
1787 /* Generate the code to compare two integer values. The return value is:
1788 (reg:SI xx) The pseudo register the comparison is in
1789 (rtx)0 No register, generate a simple branch.
1791 ??? This is called with result nonzero by the Scond patterns in
1792 mips.md. These patterns are called with a target in the mode of
1793 the Scond instruction pattern. Since this must be a constant, we
1794 must use SImode. This means that if RESULT is non-zero, it will
1795 always be an SImode register, even if TARGET_64BIT is true. We
1796 cope with this by calling convert_move rather than emit_move_insn.
1797 This will sometimes lead to an unnecessary extension of the result;
1809 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
1810 enum rtx_code test_code
; /* relational test (EQ, etc) */
1811 rtx result
; /* result to store comp. or 0 if branch */
1812 rtx cmp0
; /* first operand to compare */
1813 rtx cmp1
; /* second operand to compare */
1814 int *p_invert
; /* NULL or ptr to hold whether branch needs */
1815 /* to reverse its test */
1818 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
1819 int const_low
; /* low bound of constant we can accept */
1820 int const_high
; /* high bound of constant we can accept */
1821 int const_add
; /* constant to add (convert LE -> LT) */
1822 int reverse_regs
; /* reverse registers in test */
1823 int invert_const
; /* != 0 if invert value if cmp1 is constant */
1824 int invert_reg
; /* != 0 if invert value if cmp1 is register */
1825 int unsignedp
; /* != 0 for unsigned comparisons. */
1828 static struct cmp_info info
[ (int)ITEST_MAX
] = {
1830 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
1831 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
1832 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
1833 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
1834 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
1835 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
1836 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
1837 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
1838 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
1839 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
1842 enum internal_test test
;
1843 enum machine_mode mode
;
1844 struct cmp_info
*p_info
;
1851 test
= map_test_to_internal_test (test_code
);
1852 if (test
== ITEST_MAX
)
1855 p_info
= &info
[ (int)test
];
1856 eqne_p
= (p_info
->test_code
== XOR
);
1858 mode
= GET_MODE (cmp0
);
1859 if (mode
== VOIDmode
)
1860 mode
= GET_MODE (cmp1
);
1862 /* Eliminate simple branches */
1863 branch_p
= (result
== (rtx
)0);
1866 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
1868 /* Comparisons against zero are simple branches */
1869 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
1872 /* Test for beq/bne. */
1877 /* allocate a pseudo to calculate the value in. */
1878 result
= gen_reg_rtx (mode
);
1881 /* Make sure we can handle any constants given to us. */
1882 if (GET_CODE (cmp0
) == CONST_INT
)
1883 cmp0
= force_reg (mode
, cmp0
);
1885 if (GET_CODE (cmp1
) == CONST_INT
)
1887 HOST_WIDE_INT value
= INTVAL (cmp1
);
1888 if (value
< p_info
->const_low
1889 || value
> p_info
->const_high
1890 /* ??? Why? And why wasn't the similar code below modified too? */
1892 && HOST_BITS_PER_WIDE_INT
< 64
1893 && p_info
->const_add
!= 0
1894 && ((p_info
->unsignedp
1895 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
1897 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
1898 != (p_info
->const_add
> 0))))
1899 cmp1
= force_reg (mode
, cmp1
);
1902 /* See if we need to invert the result. */
1903 invert
= (GET_CODE (cmp1
) == CONST_INT
)
1904 ? p_info
->invert_const
1905 : p_info
->invert_reg
;
1907 if (p_invert
!= (int *)0)
1913 /* Comparison to constants, may involve adding 1 to change a LT into LE.
1914 Comparison between two registers, may involve switching operands. */
1915 if (GET_CODE (cmp1
) == CONST_INT
)
1917 if (p_info
->const_add
!= 0)
1919 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
1920 /* If modification of cmp1 caused overflow,
1921 we would get the wrong answer if we follow the usual path;
1922 thus, x > 0xffffffffU would turn into x > 0U. */
1923 if ((p_info
->unsignedp
1924 ? (unsigned HOST_WIDE_INT
) new > INTVAL (cmp1
)
1925 : new > INTVAL (cmp1
))
1926 != (p_info
->const_add
> 0))
1928 /* This test is always true, but if INVERT is true then
1929 the result of the test needs to be inverted so 0 should
1930 be returned instead. */
1931 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
1935 cmp1
= GEN_INT (new);
1938 else if (p_info
->reverse_regs
)
1945 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
1949 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
1950 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
1953 if (test
== ITEST_NE
)
1955 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
1959 else if (test
== ITEST_EQ
)
1961 reg2
= (invert
) ? gen_reg_rtx (mode
) : result
;
1962 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
1967 convert_move (result
, gen_rtx (XOR
, mode
, reg
, const1_rtx
), 0);
1973 /* Emit the common code for doing conditional branches.
1974 operand[0] is the label to jump to.
1975 The comparison operands are saved away by cmp{si,di,sf,df}. */
1978 gen_conditional_branch (operands
, test_code
)
1980 enum rtx_code test_code
;
1982 static enum machine_mode mode_map
[(int)CMP_MAX
][(int)ITEST_MAX
] = {
2009 CC_REV_FPmode
, /* ne */
2021 CC_REV_FPmode
, /* ne */
2033 enum machine_mode mode
;
2034 enum cmp_type type
= branch_type
;
2035 rtx cmp0
= branch_cmp
[0];
2036 rtx cmp1
= branch_cmp
[1];
2037 rtx label1
= gen_rtx (LABEL_REF
, VOIDmode
, operands
[0]);
2038 rtx label2
= pc_rtx
;
2041 enum internal_test test
= map_test_to_internal_test (test_code
);
2043 if (test
== ITEST_MAX
)
2049 /* Get the machine mode to use (CCmode, CC_EQmode, CC_FPmode, or CC_REV_FPmode). */
2050 mode
= mode_map
[(int)type
][(int)test
];
2051 if (mode
== VOIDmode
)
2061 reg
= gen_int_relational (test_code
, (rtx
)0, cmp0
, cmp1
, &invert
);
2069 /* Make sure not non-zero constant if ==/!= */
2070 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
2071 cmp1
= force_reg (mode
, cmp1
);
2078 rtx reg
= gen_rtx (REG
, mode
, FPSW_REGNUM
);
2079 emit_insn (gen_rtx (SET
, VOIDmode
, reg
, gen_rtx (test_code
, mode
, cmp0
, cmp1
)));
2087 /* Generate the jump */
2094 emit_jump_insn (gen_rtx (SET
, VOIDmode
,
2096 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
2097 gen_rtx (test_code
, mode
, cmp0
, cmp1
),
2104 abort_with_insn (gen_rtx (test_code
, mode
, cmp0
, cmp1
), "bad test");
2109 /* Internal code to generate the load and store of one word/short/byte.
2110 The load is emitted directly, and the store insn is returned. */
2112 #define UNITS_PER_MIPS_DWORD 8
2113 #define UNITS_PER_MIPS_WORD 4
2114 #define UNITS_PER_MIPS_HWORD 2
2117 block_move_load_store (dest_reg
, src_reg
, p_bytes
, p_offset
, align
, orig_src
)
2118 rtx src_reg
; /* register holding source memory address */
2119 rtx dest_reg
; /* register holding dest. memory address */
2120 int *p_bytes
; /* pointer to # bytes remaining */
2121 int *p_offset
; /* pointer to current offset */
2122 int align
; /* alignment */
2123 rtx orig_src
; /* original source for making a reg note */
2125 int bytes
; /* # bytes remaining */
2126 int offset
; /* offset to use */
2127 int size
; /* size in bytes of load/store */
2128 enum machine_mode mode
; /* mode to use for load/store */
2129 rtx reg
; /* temporary register */
2130 rtx src_addr
; /* source address */
2131 rtx dest_addr
; /* destination address */
2132 rtx insn
; /* insn of the load */
2133 rtx orig_src_addr
; /* original source address */
2134 rtx (*load_func
)(); /* function to generate load insn */
2135 rtx (*store_func
)(); /* function to generate destination insn */
2138 if (bytes
<= 0 || align
<= 0)
2141 if (bytes
>= UNITS_PER_MIPS_DWORD
&& align
>= UNIS_PER_MIPS_DWORD
)
2144 size
= UNITS_PER_MIPS_DWORD
;
2145 load_func
= gen_movdi
;
2146 store_func
= gen_movdi
;
2148 else if (bytes
>= UNITS_PER_MIPS_WORD
&& align
>= UNITS_PER_MIPS_WORD
)
2151 size
= UNITS_PER_MIPS_WORD
;
2152 load_func
= gen_movsi
;
2153 store_func
= gen_movsi
;
2157 /* Don't generate unaligned moves here, rather defer those to the
2158 general movestrsi_internal pattern.
2159 If this gets commented back in, then should add the dword equivalent. */
2160 else if (bytes
>= UNITS_PER_MIPS_WORD
)
2163 size
= UNITS_PER_MIPS_WORD
;
2164 load_func
= gen_movsi_ulw
;
2165 store_func
= gen_movsi_usw
;
2169 else if (bytes
>= UNITS_PER_MIPS_SHORT
&& align
>= UNITS_PER_MIPS_SHORT
)
2172 size
= UNITS_PER_MIPS_SHORT
;
2173 load_func
= gen_movhi
;
2174 store_func
= gen_movhi
;
2181 load_func
= gen_movqi
;
2182 store_func
= gen_movqi
;
2186 *p_offset
= offset
+ size
;
2187 *p_bytes
= bytes
- size
;
2192 dest_addr
= dest_reg
;
2196 src_addr
= gen_rtx (PLUS
, Pmode
, src_reg
, GEN_INT (offset
));
2197 dest_addr
= gen_rtx (PLUS
, Pmode
, dest_reg
, GEN_INT (offset
));
2200 reg
= gen_reg_rtx (mode
);
2201 insn
= emit_insn ((*load_func
) (reg
, gen_rtx (MEM
, mode
, src_addr
)));
2202 orig_src_addr
= XEXP (orig_src
, 0);
2203 if (CONSTANT_P (orig_src_addr
))
2204 REG_NOTES (insn
) = gen_rtx (EXPR_LIST
, REG_EQUIV
,
2205 plus_constant (orig_src_addr
, offset
),
2208 return (*store_func
) (gen_rtx (MEM
, mode
, dest_addr
), reg
);
2213 /* Write a series of loads/stores to move some bytes. Generate load/stores as follows:
2225 This way, no NOP's are needed, except at the end, and only
2226 two temp registers are needed. Two delay slots are used
2227 in deference to the R4000. */
2231 block_move_sequence (dest_reg
, src_reg
, bytes
, align
, orig_src
)
2232 rtx dest_reg
; /* register holding destination address */
2233 rtx src_reg
; /* register holding source address */
2234 int bytes
; /* # bytes to move */
2235 int align
; /* max alignment to assume */
2236 rtx orig_src
; /* original source for making a reg note */
2239 rtx prev2_store
= (rtx
)0;
2240 rtx prev_store
= (rtx
)0;
2241 rtx cur_store
= (rtx
)0;
2245 /* Is there a store to do? */
2247 emit_insn (prev2_store
);
2249 prev2_store
= prev_store
;
2250 prev_store
= cur_store
;
2251 cur_store
= block_move_load_store (dest_reg
, src_reg
,
2256 /* Finish up last three stores. */
2258 emit_insn (prev2_store
);
2261 emit_insn (prev_store
);
2264 emit_insn (cur_store
);
2269 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2275 temp<last> = src[MAX_MOVE_REGS-1];
2279 dest[MAX_MOVE_REGS-1] = temp<last>;
2280 src += MAX_MOVE_REGS;
2281 dest += MAX_MOVE_REGS;
2282 } while (src != final);
2284 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2285 registers are needed.
2287 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2288 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2289 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2291 #define MAX_MOVE_REGS 4
2292 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2294 /* ??? Should add code to use DWORD load/stores. */
2297 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_src
)
2298 rtx dest_reg
; /* register holding destination address */
2299 rtx src_reg
; /* register holding source address */
2300 int bytes
; /* # bytes to move */
2301 int align
; /* alignment */
2302 rtx orig_src
; /* original source for making a reg note */
2304 rtx dest_mem
= gen_rtx (MEM
, BLKmode
, dest_reg
);
2305 rtx src_mem
= gen_rtx (MEM
, BLKmode
, src_reg
);
2306 rtx align_rtx
= GEN_INT (align
);
2312 if (bytes
< 2*MAX_MOVE_BYTES
)
2315 leftover
= bytes
% MAX_MOVE_BYTES
;
2318 label
= gen_label_rtx ();
2319 final_src
= gen_reg_rtx (Pmode
);
2320 bytes_rtx
= GEN_INT (bytes
);
2326 emit_insn (gen_movdi (final_src
, bytes_rtx
));
2327 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
2331 emit_insn (gen_movsi (final_src
, bytes_rtx
));
2332 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2338 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
2340 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
2345 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
2346 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
2349 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
2350 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
2351 emit_insn (gen_cmpdi (src_reg
, final_src
));
2355 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
2356 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
2357 emit_insn (gen_cmpsi (src_reg
, final_src
));
2359 emit_jump_insn (gen_bne (label
));
2362 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
,
2368 /* Use a library function to move some bytes. */
2371 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2376 /* We want to pass the size as Pmode, which will normally be SImode
2377 but will be DImode if we are using 64 bit longs and pointers. */
2378 if (GET_MODE (bytes_rtx
) != VOIDmode
2379 && GET_MODE (bytes_rtx
) != Pmode
)
2380 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, TRUE
);
2382 #ifdef TARGET_MEM_FUNCTIONS
2383 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0,
2387 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2388 TREE_UNSIGNED (sizetype
)),
2389 TYPE_MODE (sizetype
));
2391 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "bcopy"), 0,
2395 convert_to_mode (TYPE_MODE (integer_type_node
),
2397 TREE_UNSIGNED (integer_type_node
)),
2398 TYPE_MODE (integer_type_node
));
2403 /* Expand string/block move operations.
2405 operands[0] is the pointer to the destination.
2406 operands[1] is the pointer to the source.
2407 operands[2] is the number of bytes to move.
2408 operands[3] is the alignment. */
2411 expand_block_move (operands
)
2414 rtx bytes_rtx
= operands
[2];
2415 rtx align_rtx
= operands
[3];
2416 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2417 int bytes
= (constp
? INTVAL (bytes_rtx
) : 0);
2418 int align
= INTVAL (align_rtx
);
2419 rtx orig_src
= operands
[1];
2423 if (constp
&& bytes
<= 0)
2426 if (align
> UNITS_PER_WORD
)
2427 align
= UNITS_PER_WORD
;
2429 /* Move the address into scratch registers. */
2430 dest_reg
= copy_addr_to_reg (XEXP (operands
[0], 0));
2431 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2434 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2437 else if (constp
&& bytes
<= 3*align
)
2438 block_move_sequence (dest_reg
, src_reg
, bytes
, align
, orig_src
);
2441 else if (constp
&& bytes
<= 2*MAX_MOVE_BYTES
)
2442 emit_insn (gen_movstrsi_internal (change_address (operands
[0],
2444 change_address (orig_src
, BLKmode
,
2446 bytes_rtx
, align_rtx
));
2448 else if (constp
&& align
>= UNITS_PER_WORD
&& optimize
)
2449 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_src
);
2451 else if (constp
&& optimize
)
2453 /* If the alignment is not word aligned, generate a test at
2454 runtime, to see whether things wound up aligned, and we
2455 can use the faster lw/sw instead ulw/usw. */
2457 rtx temp
= gen_reg_rtx (Pmode
);
2458 rtx aligned_label
= gen_label_rtx ();
2459 rtx join_label
= gen_label_rtx ();
2460 int leftover
= bytes
% MAX_MOVE_BYTES
;
2466 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
2467 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2468 emit_insn (gen_cmpdi (temp
, const0_rtx
));
2472 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
2473 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2474 emit_insn (gen_cmpsi (temp
, const0_rtx
));
2476 emit_jump_insn (gen_beq (aligned_label
));
2478 /* Unaligned loop. */
2479 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_src
);
2480 emit_jump_insn (gen_jump (join_label
));
2484 emit_label (aligned_label
);
2485 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_src
);
2486 emit_label (join_label
);
2488 /* Bytes at the end of the loop. */
2492 if (leftover
<= 3*align
)
2493 block_move_sequence (dest_reg
, src_reg
, leftover
, align
, orig_src
);
2497 emit_insn (gen_movstrsi_internal (gen_rtx (MEM
, BLKmode
, dest_reg
),
2498 gen_rtx (MEM
, BLKmode
, src_reg
),
2505 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2509 /* Emit load/stores for a small constant block_move.
2511 operands[0] is the memory address of the destination.
2512 operands[1] is the memory address of the source.
2513 operands[2] is the number of bytes to move.
2514 operands[3] is the alignment.
2515 operands[4] is a temp register.
2516 operands[5] is a temp register.
2518 operands[3+num_regs] is the last temp register.
2520 The block move type can be one of the following:
2521 BLOCK_MOVE_NORMAL Do all of the block move.
2522 BLOCK_MOVE_NOT_LAST Do all but the last store.
2523 BLOCK_MOVE_LAST Do just the last store. */
2526 output_block_move (insn
, operands
, num_regs
, move_type
)
2530 enum block_move_type move_type
;
2532 rtx dest_reg
= XEXP (operands
[0], 0);
2533 rtx src_reg
= XEXP (operands
[1], 0);
2534 int bytes
= INTVAL (operands
[2]);
2535 int align
= INTVAL (operands
[3]);
2538 int use_lwl_lwr
= FALSE
;
2539 int last_operand
= num_regs
+4;
2545 char *load
; /* load insn without nop */
2546 char *load_nop
; /* load insn with trailing nop */
2547 char *store
; /* store insn */
2548 char *final
; /* if last_store used: NULL or swr */
2549 char *last_store
; /* last store instruction */
2550 int offset
; /* current offset */
2551 enum machine_mode mode
; /* mode to use on (MEM) */
2554 /* Detect a bug in GCC, where it can give us a register
2555 the same as one of the addressing registers and reduce
2556 the number of registers available. */
2558 i
< last_operand
&& safe_regs
< (sizeof(xoperands
) / sizeof(xoperands
[0]));
2561 if (!reg_mentioned_p (operands
[i
], operands
[0])
2562 && !reg_mentioned_p (operands
[i
], operands
[1]))
2564 xoperands
[safe_regs
++] = operands
[i
];
2567 if (safe_regs
< last_operand
)
2569 xoperands
[0] = operands
[0];
2570 xoperands
[1] = operands
[1];
2571 xoperands
[2] = operands
[2];
2572 xoperands
[3] = operands
[3];
2573 return output_block_move (insn
, xoperands
, safe_regs
-4, move_type
);
2576 /* If we are given global or static addresses, and we would be
2577 emitting a few instructions, try to save time by using a
2578 temporary register for the pointer. */
2579 if (num_regs
> 2 && (bytes
> 2*align
|| move_type
!= BLOCK_MOVE_NORMAL
))
2581 if (CONSTANT_P (src_reg
))
2584 mips_count_memory_refs (operands
[1], 1);
2586 src_reg
= operands
[ 3 + num_regs
-- ];
2587 if (move_type
!= BLOCK_MOVE_LAST
)
2589 xoperands
[1] = operands
[1];
2590 xoperands
[0] = src_reg
;
2591 if (Pmode
== DImode
)
2592 output_asm_insn ("dla\t%0,%1", xoperands
);
2594 output_asm_insn ("la\t%0,%1", xoperands
);
2598 if (CONSTANT_P (dest_reg
))
2601 mips_count_memory_refs (operands
[0], 1);
2603 dest_reg
= operands
[ 3 + num_regs
-- ];
2604 if (move_type
!= BLOCK_MOVE_LAST
)
2606 xoperands
[1] = operands
[0];
2607 xoperands
[0] = dest_reg
;
2608 if (Pmode
== DImode
)
2609 output_asm_insn ("dla\t%0,%1", xoperands
);
2611 output_asm_insn ("la\t%0,%1", xoperands
);
2616 /* ??? We really shouldn't get any LO_SUM addresses here, because they
2617 are not offsettable, however, offsettable_address_p says they are
2618 offsettable. I think this is a bug in offsettable_address_p.
2619 For expediency, we fix this by just loading the address into a register
2620 if we happen to get one. */
2622 if (GET_CODE (src_reg
) == LO_SUM
)
2624 src_reg
= operands
[ 3 + num_regs
-- ];
2625 if (move_type
!= BLOCK_MOVE_LAST
)
2627 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
2628 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2629 xoperands
[0] = src_reg
;
2630 if (Pmode
== DImode
)
2631 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2633 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2637 if (GET_CODE (dest_reg
) == LO_SUM
)
2639 dest_reg
= operands
[ 3 + num_regs
-- ];
2640 if (move_type
!= BLOCK_MOVE_LAST
)
2642 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
2643 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
2644 xoperands
[0] = dest_reg
;
2645 if (Pmode
== DImode
)
2646 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2648 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2652 if (num_regs
> (sizeof (load_store
) / sizeof (load_store
[0])))
2653 num_regs
= (sizeof (load_store
) / sizeof (load_store
[0]));
2655 else if (num_regs
< 1)
2656 abort_with_insn (insn
, "Cannot do block move, not enough scratch registers");
2660 load_store
[num
].offset
= offset
;
2662 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
2664 load_store
[num
].load
= "ld\t%0,%1";
2665 load_store
[num
].load_nop
= "ld\t%0,%1%#";
2666 load_store
[num
].store
= "sd\t%0,%1";
2667 load_store
[num
].last_store
= "sd\t%0,%1";
2668 load_store
[num
].final
= (char *)0;
2669 load_store
[num
].mode
= DImode
;
2674 /* ??? Fails because of a MIPS assembler bug? */
2675 else if (TARGET_64BIT
&& bytes
>= 8)
2677 if (BYTES_BIG_ENDIAN
)
2679 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
2680 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
2681 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
2682 load_store
[num
].last_store
= "sdr\t%0,%2";
2683 load_store
[num
].final
= "sdl\t%0,%1";
2687 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
2688 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
2689 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
2690 load_store
[num
].last_store
= "sdr\t%0,%1";
2691 load_store
[num
].final
= "sdl\t%0,%2";
2693 load_store
[num
].mode
= DImode
;
2699 else if (bytes
>= 4 && align
>= 4)
2701 load_store
[num
].load
= "lw\t%0,%1";
2702 load_store
[num
].load_nop
= "lw\t%0,%1%#";
2703 load_store
[num
].store
= "sw\t%0,%1";
2704 load_store
[num
].last_store
= "sw\t%0,%1";
2705 load_store
[num
].final
= (char *)0;
2706 load_store
[num
].mode
= SImode
;
2711 else if (bytes
>= 4)
2713 if (BYTES_BIG_ENDIAN
)
2715 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
2716 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2717 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
2718 load_store
[num
].last_store
= "swr\t%0,%2";
2719 load_store
[num
].final
= "swl\t%0,%1";
2723 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
2724 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2725 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
2726 load_store
[num
].last_store
= "swr\t%0,%1";
2727 load_store
[num
].final
= "swl\t%0,%2";
2729 load_store
[num
].mode
= SImode
;
2735 else if (bytes
>= 2 && align
>= 2)
2737 load_store
[num
].load
= "lh\t%0,%1";
2738 load_store
[num
].load_nop
= "lh\t%0,%1%#";
2739 load_store
[num
].store
= "sh\t%0,%1";
2740 load_store
[num
].last_store
= "sh\t%0,%1";
2741 load_store
[num
].final
= (char *)0;
2742 load_store
[num
].mode
= HImode
;
2749 load_store
[num
].load
= "lb\t%0,%1";
2750 load_store
[num
].load_nop
= "lb\t%0,%1%#";
2751 load_store
[num
].store
= "sb\t%0,%1";
2752 load_store
[num
].last_store
= "sb\t%0,%1";
2753 load_store
[num
].final
= (char *)0;
2754 load_store
[num
].mode
= QImode
;
2759 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2761 dslots_load_total
++;
2762 dslots_load_filled
++;
2764 if (CONSTANT_P (src_reg
))
2765 mips_count_memory_refs (src_reg
, 1);
2767 if (CONSTANT_P (dest_reg
))
2768 mips_count_memory_refs (dest_reg
, 1);
2771 /* Emit load/stores now if we have run out of registers or are
2772 at the end of the move. */
2774 if (++num
== num_regs
|| bytes
== 0)
2776 /* If only load/store, we need a NOP after the load. */
2779 load_store
[0].load
= load_store
[0].load_nop
;
2780 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2781 dslots_load_filled
--;
2784 if (move_type
!= BLOCK_MOVE_LAST
)
2786 for (i
= 0; i
< num
; i
++)
2793 if (GET_MODE (operands
[i
+4]) != load_store
[i
].mode
)
2794 operands
[i
+4] = gen_rtx (REG
, load_store
[i
].mode
, REGNO (operands
[i
+4]));
2796 offset
= load_store
[i
].offset
;
2797 xoperands
[0] = operands
[i
+4];
2798 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2799 plus_constant (src_reg
, offset
));
2804 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2805 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2806 plus_constant (src_reg
,
2811 output_asm_insn (load_store
[i
].load
, xoperands
);
2815 for (i
= 0; i
< num
; i
++)
2817 int last_p
= (i
== num
-1 && bytes
== 0);
2818 int offset
= load_store
[i
].offset
;
2820 xoperands
[0] = operands
[i
+4];
2821 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2822 plus_constant (dest_reg
, offset
));
2828 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2829 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2830 plus_constant (dest_reg
,
2835 if (move_type
== BLOCK_MOVE_NORMAL
)
2836 output_asm_insn (load_store
[i
].store
, xoperands
);
2838 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
2841 output_asm_insn (load_store
[i
].store
, xoperands
);
2843 else if (load_store
[i
].final
!= (char *)0)
2844 output_asm_insn (load_store
[i
].final
, xoperands
);
2848 output_asm_insn (load_store
[i
].last_store
, xoperands
);
2851 num
= 0; /* reset load_store */
2852 use_lwl_lwr
= FALSE
;
2860 /* Argument support functions. */
2862 /* Initialize CUMULATIVE_ARGS for a function. */
2865 init_cumulative_args (cum
, fntype
, libname
)
2866 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
2867 tree fntype
; /* tree ptr for function decl */
2868 rtx libname
; /* SYMBOL_REF of library name or 0 */
2870 static CUMULATIVE_ARGS zero_cum
;
2871 tree param
, next_param
;
2873 if (TARGET_DEBUG_E_MODE
)
2875 fprintf (stderr
, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
2877 fputc ('\n', stderr
);
2881 tree ret_type
= TREE_TYPE (fntype
);
2882 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
2883 tree_code_name
[ (int)TREE_CODE (fntype
) ],
2884 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
2890 /* Determine if this function has variable arguments. This is
2891 indicated by the last argument being 'void_type_mode' if there
2892 are no variable arguments. The standard MIPS calling sequence
2893 passes all arguments in the general purpose registers in this
2896 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
2900 next_param
= TREE_CHAIN (param
);
2901 if (next_param
== (tree
)0 && TREE_VALUE (param
) != void_type_node
)
2902 cum
->gp_reg_found
= 1;
2906 /* Advance the argument to the next argument position. */
2909 function_arg_advance (cum
, mode
, type
, named
)
2910 CUMULATIVE_ARGS
*cum
; /* current arg information */
2911 enum machine_mode mode
; /* current arg mode */
2912 tree type
; /* type of the argument or 0 if lib support */
2913 int named
; /* whether or not the argument was named */
2915 if (TARGET_DEBUG_E_MODE
)
2917 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
2918 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
2928 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
2929 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
2931 cum
->gp_reg_found
= 1;
2932 cum
->arg_words
+= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
2937 cum
->gp_reg_found
= 1;
2938 cum
->arg_words
+= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
2947 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
2951 cum
->gp_reg_found
= 1;
2952 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
2958 cum
->gp_reg_found
= 1;
2964 /* Return an RTL expression containing the register for the given mode,
2965 or 0 if the argument is to be passed on the stack. */
2968 function_arg (cum
, mode
, type
, named
)
2969 CUMULATIVE_ARGS
*cum
; /* current arg information */
2970 enum machine_mode mode
; /* current arg mode */
2971 tree type
; /* type of the argument or 0 if lib support */
2972 int named
; /* != 0 for normal args, == 0 for ... args */
2977 int struct_p
= ((type
!= (tree
)0)
2978 && (TREE_CODE (type
) == RECORD_TYPE
2979 || TREE_CODE (type
) == UNION_TYPE
));
2981 if (TARGET_DEBUG_E_MODE
)
2983 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
2984 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
2990 if (mips_abi
== ABI_32
)
2992 if (cum
->gp_reg_found
|| cum
->arg_number
>= 2 || TARGET_SOFT_FLOAT
)
2993 regbase
= GP_ARG_FIRST
;
2996 regbase
= FP_ARG_FIRST
;
2997 /* If the first arg was a float in a floating point register,
2998 then set bias to align this float arg properly. */
2999 if (cum
->arg_words
== 1)
3004 regbase
= (TARGET_SOFT_FLOAT
|| ! named
? GP_ARG_FIRST
: FP_ARG_FIRST
);
3009 cum
->arg_words
+= (cum
->arg_words
& 1);
3010 if (mips_abi
== ABI_32
)
3011 regbase
= ((cum
->gp_reg_found
3012 || TARGET_SOFT_FLOAT
3013 || TARGET_SINGLE_FLOAT
3014 || cum
->arg_number
>= 2)
3018 regbase
= (TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
|| ! named
3019 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
3023 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3024 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3027 /* Drops through. */
3029 if (type
!= (tree
)0 && TYPE_ALIGN (type
) > BITS_PER_WORD
3031 cum
->arg_words
+= (cum
->arg_words
& 1);
3033 regbase
= GP_ARG_FIRST
;
3040 regbase
= GP_ARG_FIRST
;
3045 cum
->arg_words
+= (cum
->arg_words
& 1);
3046 regbase
= GP_ARG_FIRST
;
3049 if (cum
->arg_words
>= MAX_ARGS_IN_REGISTERS
)
3051 if (TARGET_DEBUG_E_MODE
)
3052 fprintf (stderr
, "<stack>%s\n", struct_p
? ", [struct]" : "");
3061 if (! type
|| TREE_CODE (type
) != RECORD_TYPE
|| mips_abi
== ABI_32
3063 ret
= gen_rtx (REG
, mode
, regbase
+ cum
->arg_words
+ bias
);
3066 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3067 structure contains a double in its entirety, then that 64 bit
3068 chunk is passed in a floating point register. */
3071 /* First check to see if there is any such field. */
3072 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3073 if (TREE_CODE (field
) == FIELD_DECL
3074 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3075 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
3076 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3077 % BITS_PER_WORD
== 0))
3081 ret
= gen_rtx (REG
, mode
, regbase
+ cum
->arg_words
+ bias
);
3084 /* Now handle the special case by returning a PARALLEL
3085 indicating where each 64 bit chunk goes. */
3091 /* ??? If this is a packed structure, then the last hunk won't
3094 /* ??? If this is a structure with a single double field,
3095 it would be more convenient to return (REG:DI %fX) than
3096 a parallel. However, we would have to modify the mips
3097 backend to allow DImode values in fp registers. */
3099 chunks
= TREE_INT_CST_LOW (TYPE_SIZE (type
)) / BITS_PER_WORD
;
3100 if (chunks
+ cum
->arg_words
+ bias
> MAX_ARGS_IN_REGISTERS
)
3101 chunks
= MAX_ARGS_IN_REGISTERS
- cum
->arg_words
- bias
;
3103 /* assign_parms checks the mode of ENTRY_PARM, so we must
3104 use the actual mode here. */
3105 ret
= gen_rtx (PARALLEL
, mode
, rtvec_alloc (chunks
));
3108 regno
= regbase
+ cum
->arg_words
+ bias
;
3109 field
= TYPE_FIELDS (type
);
3110 for (i
= 0; i
< chunks
; i
++)
3114 for (; field
; field
= TREE_CHAIN (field
))
3115 if (TREE_CODE (field
) == FIELD_DECL
3116 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3121 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
)) == bitpos
3122 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3123 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
3124 reg
= gen_rtx (REG
, DFmode
,
3125 regno
+ FP_ARG_FIRST
- GP_ARG_FIRST
);
3127 reg
= gen_rtx (REG
, word_mode
, regno
);
3129 XVECEXP (ret
, 0, i
) = gen_rtx (EXPR_LIST
, VOIDmode
, reg
,
3130 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3138 if (TARGET_DEBUG_E_MODE
)
3139 fprintf (stderr
, "%s%s\n", reg_names
[regbase
+ cum
->arg_words
+ bias
],
3140 struct_p
? ", [struct]" : "");
3142 /* The following is a hack in order to pass 1 byte structures
3143 the same way that the MIPS compiler does (namely by passing
3144 the structure in the high byte or half word of the register).
3145 This also makes varargs work. If we have such a structure,
3146 we save the adjustment RTL, and the call define expands will
3147 emit them. For the VOIDmode argument (argument after the
3148 last real argument), pass back a parallel vector holding each
3149 of the adjustments. */
3151 /* ??? function_arg can be called more than once for each argument.
3152 As a result, we compute more adjustments than we need here.
3153 See the CUMULATIVE_ARGS definition in mips.h. */
3155 /* ??? This scheme requires everything smaller than the word size to
3156 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3157 that would mean every int needs to be shifted left, which is very
3158 inefficient. Let's not carry this compatibility to the 64 bit
3159 calling convention for now. */
3161 if (struct_p
&& int_size_in_bytes (type
) < UNITS_PER_WORD
3164 rtx amount
= GEN_INT (BITS_PER_WORD
3165 - int_size_in_bytes (type
) * BITS_PER_UNIT
);
3166 rtx reg
= gen_rtx (REG
, word_mode
, regbase
+ cum
->arg_words
+ bias
);
3168 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashldi3 (reg
, reg
, amount
);
3170 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashlsi3 (reg
, reg
, amount
);
3174 if (mode
== VOIDmode
&& cum
->num_adjusts
> 0)
3175 ret
= gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec_v (cum
->num_adjusts
, cum
->adjust
));
3182 function_arg_partial_nregs (cum
, mode
, type
, named
)
3183 CUMULATIVE_ARGS
*cum
; /* current arg information */
3184 enum machine_mode mode
; /* current arg mode */
3185 tree type
; /* type of the argument or 0 if lib support */
3186 int named
; /* != 0 for normal args, == 0 for ... args */
3188 if ((mode
== BLKmode
3189 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3190 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3191 && cum
->arg_words
< MAX_ARGS_IN_REGISTERS
)
3194 if (mode
== BLKmode
)
3195 words
= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3198 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3200 if (words
+ cum
->arg_words
<= MAX_ARGS_IN_REGISTERS
)
3201 return 0; /* structure fits in registers */
3203 if (TARGET_DEBUG_E_MODE
)
3204 fprintf (stderr
, "function_arg_partial_nregs = %d\n",
3205 MAX_ARGS_IN_REGISTERS
- cum
->arg_words
);
3207 return MAX_ARGS_IN_REGISTERS
- cum
->arg_words
;
3210 else if (mode
== DImode
&& cum
->arg_words
== MAX_ARGS_IN_REGISTERS
-1
3213 if (TARGET_DEBUG_E_MODE
)
3214 fprintf (stderr
, "function_arg_partial_nregs = 1\n");
3222 /* Abort after printing out a specific insn. */
3225 abort_with_insn (insn
, reason
)
3234 /* Write a message to stderr (for use in macros expanded in files that do not
3235 include stdio.h). */
3241 fprintf (stderr
, s
, s1
, s2
);
3251 fprintf (stderr
, "compiling '%s' in '%s'\n",
3252 (current_function_name
!= (char *)0) ? current_function_name
: "<toplevel>",
3253 (current_function_file
!= (char *)0) ? current_function_file
: "<no file>");
3256 #endif /* SIGINFO */
3259 /* Set up the threshold for data to go into the small data area, instead
3260 of the normal data area, and detect any conflicts in the switches. */
3265 register int i
, start
;
3267 register enum machine_mode mode
;
3269 mips_section_threshold
= (g_switch_set
) ? g_switch_value
: MIPS_DEFAULT_GVALUE
;
3271 if (mips_section_threshold
<= 0)
3272 target_flags
&= ~MASK_GPOPT
;
3274 target_flags
|= MASK_GPOPT
;
3276 /* Get the architectural level. */
3277 if (mips_isa_string
== (char *)0)
3279 #ifdef MIPS_ISA_DEFAULT
3280 mips_isa
= MIPS_ISA_DEFAULT
;
3286 else if (isdigit (*mips_isa_string
))
3288 mips_isa
= atoi (mips_isa_string
);
3289 if (mips_isa
< 1 || mips_isa
> 4)
3291 error ("-mips%d not supported", mips_isa
);
3298 error ("bad value (%s) for -mips switch", mips_isa_string
);
3302 #ifdef MIPS_ABI_DEFAULT
3303 /* Get the ABI to use. Currently this code is only used for Irix 6. */
3304 if (mips_abi_string
== (char *) 0)
3305 mips_abi
= MIPS_ABI_DEFAULT
;
3306 else if (! strcmp (mips_abi_string
, "32")
3307 || ! strcmp (mips_abi_string
, "o32"))
3309 else if (! strcmp (mips_abi_string
, "n32"))
3311 else if (! strcmp (mips_abi_string
, "64")
3312 || ! strcmp (mips_abi_string
, "n64"))
3315 error ("bad value (%s) for -mabi= switch", mips_abi_string
);
3317 /* A specified ISA defaults the ABI if it was not specified. */
3318 if (mips_abi_string
== 0 && mips_isa_string
)
3325 /* A specified ABI defaults the ISA if it was not specified. */
3326 else if (mips_isa_string
== 0 && mips_abi_string
)
3328 if (mips_abi
== ABI_32
)
3330 else if (mips_abi
== ABI_N32
)
3335 /* If both ABI and ISA were specified, check for conflicts. */
3336 else if (mips_isa_string
&& mips_abi_string
)
3338 if ((mips_isa
<= 2 && (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
3339 || (mips_isa
>= 3 && mips_abi
== ABI_32
))
3340 error ("-mabi=%s does not support -mips%d", mips_abi_string
, mips_isa
);
3343 /* Override TARGET_DEFAULT if necessary. */
3344 if (mips_abi
== ABI_32
)
3345 target_flags
&= ~ (MASK_FLOAT64
|MASK_64BIT
);
3347 /* ??? This doesn't work yet, so don't let people try to use it. */
3348 if (mips_abi
== ABI_32
)
3349 error ("The -mabi=32 support does not work yet.");
3351 if (mips_abi_string
)
3352 error ("This target does not support the -mabi switch.");
3355 #ifdef MIPS_CPU_STRING_DEFAULT
3356 /* ??? There is a minor inconsistency here. If the user specifies an ISA
3357 greater than that supported by the default processor, then the user gets
3358 an error. Normally, the compiler will just default to the base level cpu
3359 for the indicated isa. */
3360 if (mips_cpu_string
== (char *)0)
3361 mips_cpu_string
= MIPS_CPU_STRING_DEFAULT
;
3364 /* Identify the processor type */
3365 if (mips_cpu_string
== (char *)0
3366 || !strcmp (mips_cpu_string
, "default")
3367 || !strcmp (mips_cpu_string
, "DEFAULT"))
3372 mips_cpu_string
= "3000";
3373 mips_cpu
= PROCESSOR_R3000
;
3376 mips_cpu_string
= "6000";
3377 mips_cpu
= PROCESSOR_R6000
;
3380 mips_cpu_string
= "4000";
3381 mips_cpu
= PROCESSOR_R4000
;
3384 mips_cpu_string
= "8000";
3385 mips_cpu
= PROCESSOR_R8000
;
3392 char *p
= mips_cpu_string
;
3395 /* We need to cope with the various "vr" prefixes for the NEC 4300
3396 and 4100 processors. */
3397 if (*p
== 'v' || *p
== 'V')
3402 if (*p
== 'r' || *p
== 'R')
3405 /* Since there is no difference between a R2000 and R3000 in
3406 terms of the scheduler, we collapse them into just an R3000. */
3408 mips_cpu
= PROCESSOR_DEFAULT
;
3412 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
3413 mips_cpu
= PROCESSOR_R3000
;
3417 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
3418 mips_cpu
= PROCESSOR_R3000
;
3422 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
3423 mips_cpu
= PROCESSOR_R4000
;
3424 /* The vr4100 is a non-FP ISA III processor with some extra
3426 else if (!strcmp (p
, "4100")) {
3427 mips_cpu
= PROCESSOR_R4100
;
3428 target_flags
|= MASK_SOFT_FLOAT
;
3430 /* The vr4300 is a standard ISA III processor, but with a different
3432 else if (!strcmp (p
, "4300"))
3433 mips_cpu
= PROCESSOR_R4300
;
3434 /* The r4400 is exactly the same as the r4000 from the compiler's
3436 else if (!strcmp (p
, "4400"))
3437 mips_cpu
= PROCESSOR_R4000
;
3438 else if (!strcmp (p
, "4600"))
3439 mips_cpu
= PROCESSOR_R4600
;
3440 else if (!strcmp (p
, "4650"))
3441 mips_cpu
= PROCESSOR_R4650
;
3445 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
3446 mips_cpu
= PROCESSOR_R6000
;
3450 if (!strcmp (p
, "8000"))
3451 mips_cpu
= PROCESSOR_R8000
;
3455 if (!strcmp (p
, "orion"))
3456 mips_cpu
= PROCESSOR_R4600
;
3460 if (seen_v
&& mips_cpu
!= PROCESSOR_R4300
&& mips_cpu
!= PROCESSOR_R4100
)
3461 mips_cpu
= PROCESSOR_DEFAULT
;
3463 if (mips_cpu
== PROCESSOR_DEFAULT
)
3465 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
3466 mips_cpu_string
= "default";
3470 if ((mips_cpu
== PROCESSOR_R3000
&& mips_isa
> 1)
3471 || (mips_cpu
== PROCESSOR_R6000
&& mips_isa
> 2)
3472 || ((mips_cpu
== PROCESSOR_R4000
3473 || mips_cpu
== PROCESSOR_R4100
3474 || mips_cpu
== PROCESSOR_R4300
3475 || mips_cpu
== PROCESSOR_R4600
3476 || mips_cpu
== PROCESSOR_R4650
)
3478 error ("-mcpu=%s does not support -mips%d", mips_cpu_string
, mips_isa
);
3480 /* make sure sizes of ints/longs/etc. are ok */
3484 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3486 else if (TARGET_LONG64
)
3487 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3489 else if (TARGET_FLOAT64
)
3490 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3492 else if (TARGET_64BIT
)
3493 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3496 if (mips_abi
!= ABI_32
)
3497 flag_pcc_struct_return
= 0;
3499 /* Tell halfpic.c that we have half-pic code if we do. */
3500 if (TARGET_HALF_PIC
)
3503 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3504 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3505 /* ??? -non_shared turns off pic code generation, but this is not
3507 if (TARGET_ABICALLS
)
3509 mips_abicalls
= MIPS_ABICALLS_YES
;
3511 if (mips_section_threshold
> 0)
3512 warning ("-G is incompatible with PIC code which is the default");
3515 mips_abicalls
= MIPS_ABICALLS_NO
;
3517 /* -membedded-pic is a form of PIC code suitable for embedded
3518 systems. All calls are made using PC relative addressing, and
3519 all data is addressed using the $gp register. This requires gas,
3520 which does most of the work, and GNU ld, which automatically
3521 expands PC relative calls which are out of range into a longer
3522 instruction sequence. All gcc really does differently is
3523 generate a different sequence for a switch. */
3524 if (TARGET_EMBEDDED_PIC
)
3527 if (TARGET_ABICALLS
)
3528 warning ("-membedded-pic and -mabicalls are incompatible");
3530 warning ("-G and -membedded-pic are incompatible");
3531 /* Setting mips_section_threshold is not required, because gas
3532 will force everything to be GP addressable anyhow, but
3533 setting it will cause gcc to make better estimates of the
3534 number of instructions required to access a particular data
3536 mips_section_threshold
= 0x7fffffff;
3539 /* ??? This does not work when target addresses are DImode.
3540 This is because we are missing DImode high/lo_sum patterns. */
3542 if (TARGET_GAS
&& optimize
&& ! flag_pic
&& Pmode
== SImode
)
3543 mips_split_addresses
= 1;
3545 mips_split_addresses
= 0;
3547 /* -mrnames says to use the MIPS software convention for register
3548 names instead of the hardware names (ie, $a0 instead of $4).
3549 We do this by switching the names in mips_reg_names, which the
3550 reg_names points into via the REGISTER_NAMES macro. */
3552 if (TARGET_NAME_REGS
)
3553 bcopy ((char *) mips_sw_reg_names
, (char *) mips_reg_names
, sizeof (mips_reg_names
));
3555 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3556 is currently being compiled. */
3558 if (getenv ("GCC_SIGINFO") != (char *)0)
3560 struct sigaction action
;
3561 action
.sa_handler
= siginfo
;
3563 action
.sa_flags
= SA_RESTART
;
3564 sigaction (SIGINFO
, &action
, (struct sigaction
*)0);
3569 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3570 /* If -mstats and -quiet, make stderr line buffered. */
3571 if (quiet_flag
&& TARGET_STATS
)
3572 setvbuf (stderr
, (char *)0, _IOLBF
, BUFSIZ
);
3576 /* Initialize the high and low values for legitimate floating point
3577 constants. Rather than trying to get the accuracy down to the
3578 last bit, just use approximate ranges. */
3579 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
3580 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
3581 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
3582 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
3584 mips_print_operand_punct
['?'] = TRUE
;
3585 mips_print_operand_punct
['#'] = TRUE
;
3586 mips_print_operand_punct
['&'] = TRUE
;
3587 mips_print_operand_punct
['!'] = TRUE
;
3588 mips_print_operand_punct
['*'] = TRUE
;
3589 mips_print_operand_punct
['@'] = TRUE
;
3590 mips_print_operand_punct
['.'] = TRUE
;
3591 mips_print_operand_punct
['('] = TRUE
;
3592 mips_print_operand_punct
[')'] = TRUE
;
3593 mips_print_operand_punct
['['] = TRUE
;
3594 mips_print_operand_punct
[']'] = TRUE
;
3595 mips_print_operand_punct
['<'] = TRUE
;
3596 mips_print_operand_punct
['>'] = TRUE
;
3597 mips_print_operand_punct
['{'] = TRUE
;
3598 mips_print_operand_punct
['}'] = TRUE
;
3599 mips_print_operand_punct
['^'] = TRUE
;
3601 mips_char_to_class
['d'] = GR_REGS
;
3602 mips_char_to_class
['f'] = ((TARGET_HARD_FLOAT
) ? FP_REGS
: NO_REGS
);
3603 mips_char_to_class
['h'] = HI_REG
;
3604 mips_char_to_class
['l'] = LO_REG
;
3605 mips_char_to_class
['a'] = HILO_REG
;
3606 mips_char_to_class
['x'] = MD_REGS
;
3607 mips_char_to_class
['b'] = ALL_REGS
;
3608 mips_char_to_class
['y'] = GR_REGS
;
3609 mips_char_to_class
['z'] = ST_REGS
;
3611 /* Set up array to map GCC register number to debug register number.
3612 Ignore the special purpose register numbers. */
3614 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3615 mips_dbx_regno
[i
] = -1;
3617 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
3618 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
3619 mips_dbx_regno
[i
] = i
+ start
;
3621 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
3622 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
3623 mips_dbx_regno
[i
] = i
+ start
;
3625 /* Set up array giving whether a given register can hold a given mode.
3626 At present, restrict ints from being in FP registers, because reload
3627 is a little enthusiastic about storing extra values in FP registers,
3628 and this is not good for things like OS kernels. Also, due to the
3629 mandatory delay, it is as fast to load from cached memory as to move
3630 from the FP register. */
3632 for (mode
= VOIDmode
;
3633 mode
!= MAX_MACHINE_MODE
;
3634 mode
= (enum machine_mode
)((int)mode
+ 1))
3636 register int size
= GET_MODE_SIZE (mode
);
3637 register enum mode_class
class = GET_MODE_CLASS (mode
);
3639 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3643 if (mode
== CC_FPmode
|| mode
== CC_REV_FPmode
)
3644 temp
= (regno
== FPSW_REGNUM
);
3646 else if (GP_REG_P (regno
))
3647 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
3649 else if (FP_REG_P (regno
))
3650 temp
= ((TARGET_FLOAT64
|| ((regno
& 1) == 0))
3651 && (class == MODE_FLOAT
3652 || class == MODE_COMPLEX_FLOAT
3653 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
3654 && (! TARGET_SINGLE_FLOAT
|| size
<= 4));
3656 else if (MD_REG_P (regno
))
3657 temp
= (class == MODE_INT
3658 && (size
<= UNITS_PER_WORD
3659 || (regno
== MD_REG_FIRST
&& size
== 2 * UNITS_PER_WORD
)));
3664 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
3671 * The MIPS debug format wants all automatic variables and arguments
3672 * to be in terms of the virtual frame pointer (stack pointer before
3673 * any adjustment in the function), while the MIPS 3.0 linker wants
3674 * the frame pointer to be the stack pointer after the initial
3675 * adjustment. So, we do the adjustment here. The arg pointer (which
3676 * is eliminated) points to the virtual frame pointer, while the frame
3677 * pointer (which may be eliminated) points to the stack pointer after
3678 * the initial adjustments.
3682 mips_debugger_offset (addr
, offset
)
3686 rtx offset2
= const0_rtx
;
3687 rtx reg
= eliminate_constant_term (addr
, &offset2
);
3690 offset
= INTVAL (offset2
);
3692 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
)
3694 int frame_size
= (!current_frame_info
.initialized
)
3695 ? compute_frame_size (get_frame_size ())
3696 : current_frame_info
.total_size
;
3698 offset
= offset
- frame_size
;
3700 /* sdbout_parms does not want this to crash for unrecognized cases. */
3702 else if (reg
!= arg_pointer_rtx
)
3703 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer.");
3710 /* A C compound statement to output to stdio stream STREAM the
3711 assembler syntax for an instruction operand X. X is an RTL
3714 CODE is a value that can be used to specify one of several ways
3715 of printing the operand. It is used when identical operands
3716 must be printed differently depending on the context. CODE
3717 comes from the `%' specification that was used to request
3718 printing of the operand. If the specification was just `%DIGIT'
3719 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3720 is the ASCII code for LTR.
3722 If X is a register, this macro should print the register's name.
3723 The names can be found in an array `reg_names' whose type is
3724 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3726 When the machine description has a specification `%PUNCT' (a `%'
3727 followed by a punctuation character), this macro is called with
3728 a null pointer for X and the punctuation character for CODE.
3730 The MIPS specific codes are:
3732 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3733 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3734 'd' output integer constant in decimal,
3735 'z' if the operand is 0, use $0 instead of normal operand.
3736 'D' print second register of double-word register operand.
3737 'L' print low-order register of double-word register operand.
3738 'M' print high-order register of double-word register operand.
3739 'C' print part of opcode for a branch condition.
3740 'N' print part of opcode for a branch condition, inverted.
3741 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3742 'B' print 'z' for EQ, 'n' for NE
3743 'b' print 'n' for EQ, 'z' for NE
3744 'T' print 'f' for EQ, 't' for NE
3745 't' print 't' for EQ, 'f' for NE
3746 '(' Turn on .set noreorder
3747 ')' Turn on .set reorder
3748 '[' Turn on .set noat
3750 '<' Turn on .set nomacro
3751 '>' Turn on .set macro
3752 '{' Turn on .set volatile (not GAS)
3753 '}' Turn on .set novolatile (not GAS)
3754 '&' Turn on .set noreorder if filling delay slots
3755 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3756 '!' Turn on .set nomacro if filling delay slots
3757 '#' Print nop if in a .set noreorder section.
3758 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3759 '@' Print the name of the assembler temporary register (at or $1).
3760 '.' Print the name of the register with a hard-wired zero (zero or $0).
3761 '^' Print the name of the pic call-through register (t9 or $25). */
3764 print_operand (file
, op
, letter
)
3765 FILE *file
; /* file to write to */
3766 rtx op
; /* operand to print */
3767 int letter
; /* %<letter> or 0 */
3769 register enum rtx_code code
;
3771 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
3776 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter
);
3780 if (mips_branch_likely
)
3785 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
3789 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
3793 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
3797 if (final_sequence
!= 0 && set_noreorder
++ == 0)
3798 fputs (".set\tnoreorder\n\t", file
);
3802 if (final_sequence
!= 0)
3804 if (set_noreorder
++ == 0)
3805 fputs (".set\tnoreorder\n\t", file
);
3807 if (set_nomacro
++ == 0)
3808 fputs (".set\tnomacro\n\t", file
);
3813 if (final_sequence
!= 0 && set_nomacro
++ == 0)
3814 fputs ("\n\t.set\tnomacro", file
);
3818 if (set_noreorder
!= 0)
3819 fputs ("\n\tnop", file
);
3821 else if (TARGET_STATS
)
3822 fputs ("\n\t#nop", file
);
3827 if (set_noreorder
++ == 0)
3828 fputs (".set\tnoreorder\n\t", file
);
3832 if (set_noreorder
== 0)
3833 error ("internal error: %%) found without a %%( in assembler pattern");
3835 else if (--set_noreorder
== 0)
3836 fputs ("\n\t.set\treorder", file
);
3841 if (set_noat
++ == 0)
3842 fputs (".set\tnoat\n\t", file
);
3847 error ("internal error: %%] found without a %%[ in assembler pattern");
3849 else if (--set_noat
== 0)
3850 fputs ("\n\t.set\tat", file
);
3855 if (set_nomacro
++ == 0)
3856 fputs (".set\tnomacro\n\t", file
);
3860 if (set_nomacro
== 0)
3861 error ("internal error: %%> found without a %%< in assembler pattern");
3863 else if (--set_nomacro
== 0)
3864 fputs ("\n\t.set\tmacro", file
);
3869 if (set_volatile
++ == 0)
3870 fprintf (file
, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS
) ? "" : "#");
3874 if (set_volatile
== 0)
3875 error ("internal error: %%} found without a %%{ in assembler pattern");
3877 else if (--set_volatile
== 0)
3878 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
3887 error ("PRINT_OPERAND null pointer");
3891 code
= GET_CODE (op
);
3895 case EQ
: fputs ("eq", file
); break;
3896 case NE
: fputs ("ne", file
); break;
3897 case GT
: fputs ("gt", file
); break;
3898 case GE
: fputs ("ge", file
); break;
3899 case LT
: fputs ("lt", file
); break;
3900 case LE
: fputs ("le", file
); break;
3901 case GTU
: fputs ("gtu", file
); break;
3902 case GEU
: fputs ("geu", file
); break;
3903 case LTU
: fputs ("ltu", file
); break;
3904 case LEU
: fputs ("leu", file
); break;
3907 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
3910 else if (letter
== 'N')
3913 case EQ
: fputs ("ne", file
); break;
3914 case NE
: fputs ("eq", file
); break;
3915 case GT
: fputs ("le", file
); break;
3916 case GE
: fputs ("lt", file
); break;
3917 case LT
: fputs ("ge", file
); break;
3918 case LE
: fputs ("gt", file
); break;
3919 case GTU
: fputs ("leu", file
); break;
3920 case GEU
: fputs ("ltu", file
); break;
3921 case LTU
: fputs ("geu", file
); break;
3922 case LEU
: fputs ("gtu", file
); break;
3925 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
3928 else if (letter
== 'S')
3932 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
3933 assemble_name (file
, buffer
);
3936 else if (code
== REG
)
3938 register int regnum
= REGNO (op
);
3940 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
3941 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
3945 fprintf (file
, "%s", reg_names
[regnum
]);
3948 else if (code
== MEM
)
3949 output_address (XEXP (op
, 0));
3951 else if (code
== CONST_DOUBLE
3952 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
3957 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
3958 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
3962 else if ((letter
== 'x') && (GET_CODE(op
) == CONST_INT
))
3963 fprintf (file
, "0x%04x", 0xffff & (INTVAL(op
)));
3965 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
3966 && HOST_BITS_PER_WIDE_INT
== 32)
3967 fprintf (file
, "0x%08x", INTVAL(op
));
3969 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
3970 && HOST_BITS_PER_WIDE_INT
== 64)
3971 fprintf (file
, "0x%016lx", INTVAL(op
));
3973 else if ((letter
== 'd') && (GET_CODE(op
) == CONST_INT
))
3974 fprintf (file
, "%d", (INTVAL(op
)));
3976 else if (letter
== 'z'
3977 && (GET_CODE (op
) == CONST_INT
)
3978 && INTVAL (op
) == 0)
3979 fputs (reg_names
[GP_REG_FIRST
], file
);
3981 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
3982 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter
);
3984 else if (letter
== 'B')
3985 fputs (code
== EQ
? "z" : "n", file
);
3986 else if (letter
== 'b')
3987 fputs (code
== EQ
? "n" : "z", file
);
3988 else if (letter
== 'T')
3989 fputs (code
== EQ
? "f" : "t", file
);
3990 else if (letter
== 't')
3991 fputs (code
== EQ
? "t" : "f", file
);
3994 output_addr_const (file
, op
);
3998 /* A C compound statement to output to stdio stream STREAM the
3999 assembler syntax for an instruction operand that is a memory
4000 reference whose address is ADDR. ADDR is an RTL expression.
4002 On some machines, the syntax for a symbolic address depends on
4003 the section that the address refers to. On these machines,
4004 define the macro `ENCODE_SECTION_INFO' to store the information
4005 into the `symbol_ref', and then check for it here. */
4008 print_operand_address (file
, addr
)
4013 error ("PRINT_OPERAND_ADDRESS, null pointer");
4016 switch (GET_CODE (addr
))
4019 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
4023 if (REGNO (addr
) == ARG_POINTER_REGNUM
)
4024 abort_with_insn (addr
, "Arg pointer not eliminated.");
4026 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
4031 register rtx arg0
= XEXP (addr
, 0);
4032 register rtx arg1
= XEXP (addr
, 1);
4034 if (! mips_split_addresses
)
4035 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4037 if (GET_CODE (arg0
) != REG
)
4038 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4040 fprintf (file
, "%%lo(");
4041 print_operand_address (file
, arg1
);
4042 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
4048 register rtx reg
= (rtx
)0;
4049 register rtx offset
= (rtx
)0;
4050 register rtx arg0
= XEXP (addr
, 0);
4051 register rtx arg1
= XEXP (addr
, 1);
4053 if (GET_CODE (arg0
) == REG
)
4057 if (GET_CODE (offset
) == REG
)
4058 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
4060 else if (GET_CODE (arg1
) == REG
)
4065 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
4067 output_addr_const (file
, addr
);
4071 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
4073 if (!CONSTANT_P (offset
))
4074 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4076 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
4077 abort_with_insn (addr
, "Arg pointer not eliminated.");
4079 output_addr_const (file
, offset
);
4080 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
4088 output_addr_const (file
, addr
);
4094 /* If optimizing for the global pointer, keep track of all of
4095 the externs, so that at the end of the file, we can emit
4096 the appropriate .extern declaration for them, before writing
4097 out the text section. We assume that all names passed to
4098 us are in the permanent obstack, so that they will be valid
4099 at the end of the compilation.
4101 If we have -G 0, or the extern size is unknown, don't bother
4102 emitting the .externs. */
4105 mips_output_external (file
, decl
, name
)
4110 register struct extern_list
*p
;
4114 && ((TREE_CODE (decl
)) != FUNCTION_DECL
)
4115 && ((len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0))
4117 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4118 p
->next
= extern_head
;
4124 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4125 if (TREE_CODE (decl
) == FUNCTION_DECL
4126 /* ??? Don't include alloca, since gcc will always expand it
4127 inline. If we don't do this, libg++ fails to build. */
4128 && strcmp (name
, "alloca")
4129 /* ??? Don't include __builtin_next_arg, because then gcc will not
4130 bootstrap under Irix 5.1. */
4131 && strcmp (name
, "__builtin_next_arg"))
4133 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4134 p
->next
= extern_head
;
4144 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4146 mips_output_external_libcall (file
, name
)
4150 register struct extern_list
*p
;
4152 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4153 p
->next
= extern_head
;
4163 /* Compute a string to use as a temporary file name. */
4165 /* On MSDOS, write temp files in current dir
4166 because there's no place else we can expect to use. */
4169 #define P_tmpdir "./"
4177 char *base
= getenv ("TMPDIR");
4180 if (base
== (char *)0)
4183 if (access (P_tmpdir
, R_OK
| W_OK
) == 0)
4187 if (access ("/usr/tmp", R_OK
| W_OK
) == 0)
4193 len
= strlen (base
);
4194 /* temp_filename is global, so we must use malloc, not alloca. */
4195 temp_filename
= (char *) xmalloc (len
+ sizeof("/ctXXXXXX"));
4196 strcpy (temp_filename
, base
);
4197 if (len
> 0 && temp_filename
[len
-1] != '/')
4198 temp_filename
[len
++] = '/';
4200 strcpy (temp_filename
+ len
, "ctXXXXXX");
4201 mktemp (temp_filename
);
4203 stream
= fopen (temp_filename
, "w+");
4205 pfatal_with_name (temp_filename
);
4208 /* In MSDOS, we cannot unlink the temporary file until we are finished using
4209 it. Otherwise, we delete it now, so that it will be gone even if the
4210 compiler happens to crash. */
4211 unlink (temp_filename
);
4217 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
4218 for .file's that start within a function. If we are smuggling stabs, try to
4219 put out a MIPS ECOFF file and a stab. */
4222 mips_output_filename (stream
, name
)
4226 static int first_time
= TRUE
;
4227 char ltext_label_name
[100];
4233 current_function_file
= name
;
4234 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4235 /* This tells mips-tfile that stabs will follow. */
4236 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
4237 fprintf (stream
, "\t#@stabs\n");
4240 else if (write_symbols
== DBX_DEBUG
)
4242 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
4243 fprintf (stream
, "%s ", ASM_STABS_OP
);
4244 output_quoted_string (stream
, name
);
4245 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
4248 else if (name
!= current_function_file
4249 && strcmp (name
, current_function_file
) != 0)
4251 if (inside_function
&& !TARGET_GAS
)
4253 if (!file_in_function_warning
)
4255 file_in_function_warning
= TRUE
;
4256 ignore_line_number
= TRUE
;
4257 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
4263 current_function_file
= name
;
4264 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4270 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4271 as well as a .loc, since it is possible that MIPS ECOFF might not be
4272 able to represent the location for inlines that come from a different
4276 mips_output_lineno (stream
, line
)
4280 if (write_symbols
== DBX_DEBUG
)
4283 fprintf (stream
, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
4284 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
4285 LOCAL_LABEL_PREFIX
, sym_lineno
);
4290 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
4291 (ignore_line_number
) ? "#" : "",
4292 num_source_filenames
, line
);
4294 LABEL_AFTER_LOC (stream
);
4299 /* If defined, a C statement to be executed just prior to the
4300 output of assembler code for INSN, to modify the extracted
4301 operands so they will be output differently.
4303 Here the argument OPVEC is the vector containing the operands
4304 extracted from INSN, and NOPERANDS is the number of elements of
4305 the vector which contain meaningful data for this insn. The
4306 contents of this vector are what will be used to convert the
4307 insn template into assembler code, so you can change the
4308 assembler output by changing the contents of the vector.
4310 We use it to check if the current insn needs a nop in front of it
4311 because of load delays, and also to update the delay slot
4314 /* ??? There is no real need for this function, because it never actually
4315 emits a NOP anymore. */
4318 final_prescan_insn (insn
, opvec
, noperands
)
4323 if (dslots_number_nops
> 0)
4325 rtx pattern
= PATTERN (insn
);
4326 int length
= get_attr_length (insn
);
4328 /* Do we need to emit a NOP? */
4330 || (mips_load_reg
!= (rtx
)0 && reg_mentioned_p (mips_load_reg
, pattern
))
4331 || (mips_load_reg2
!= (rtx
)0 && reg_mentioned_p (mips_load_reg2
, pattern
))
4332 || (mips_load_reg3
!= (rtx
)0 && reg_mentioned_p (mips_load_reg3
, pattern
))
4333 || (mips_load_reg4
!= (rtx
)0 && reg_mentioned_p (mips_load_reg4
, pattern
)))
4334 fputs ("\t#nop\n", asm_out_file
);
4337 dslots_load_filled
++;
4339 while (--dslots_number_nops
> 0)
4340 fputs ("\t#nop\n", asm_out_file
);
4342 mips_load_reg
= (rtx
)0;
4343 mips_load_reg2
= (rtx
)0;
4344 mips_load_reg3
= (rtx
)0;
4345 mips_load_reg4
= (rtx
)0;
4350 enum rtx_code code
= GET_CODE (insn
);
4351 if (code
== JUMP_INSN
|| code
== CALL_INSN
)
4352 dslots_jump_total
++;
4357 /* Output at beginning of assembler file.
4358 If we are optimizing to use the global pointer, create a temporary
4359 file to hold all of the text stuff, and write it out to the end.
4360 This is needed because the MIPS assembler is evidently one pass,
4361 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4362 declaration when the code is processed, it generates a two
4363 instruction sequence. */
4366 mips_asm_file_start (stream
)
4369 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
4371 /* Versions of the MIPS assembler before 2.20 generate errors
4372 if a branch inside of a .set noreorder section jumps to a
4373 label outside of the .set noreorder section. Revision 2.20
4374 just set nobopt silently rather than fixing the bug. */
4376 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
4377 fprintf (stream
, "\t.set\tnobopt\n");
4379 /* Generate the pseudo ops that System V.4 wants. */
4380 #ifndef ABICALLS_ASM_OP
4381 #define ABICALLS_ASM_OP ".abicalls"
4383 if (TARGET_ABICALLS
)
4384 /* ??? but do not want this (or want pic0) if -non-shared? */
4385 fprintf (stream
, "\t%s\n", ABICALLS_ASM_OP
);
4387 /* Start a section, so that the first .popsection directive is guaranteed
4388 to have a previously defined section to pop back to. */
4389 if (mips_abi
!= ABI_32
)
4390 fprintf (stream
, "\t.section\t.text\n");
4392 /* This code exists so that we can put all externs before all symbol
4393 references. This is necessary for the assembler's global pointer
4394 optimizations to work. */
4395 /* ??? Current versions of gas do not require that externs occur before
4396 symbol references. This means that this code is unnecessary when
4397 gas is being used. This gas feature hasn't been well tested as yet
4401 asm_out_data_file
= stream
;
4402 asm_out_text_file
= make_temp_file ();
4405 asm_out_data_file
= asm_out_text_file
= stream
;
4407 if (flag_verbose_asm
)
4408 fprintf (stream
, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
4410 mips_section_threshold
, mips_cpu_string
, mips_isa
);
4414 /* If we are optimizing the global pointer, emit the text section now
4415 and any small externs which did not have .comm, etc that are
4416 needed. Also, give a warning if the data area is more than 32K and
4417 -pic because 3 instructions are needed to reference the data
4421 mips_asm_file_end (file
)
4426 struct extern_list
*p
;
4430 HALF_PIC_FINISH (file
);
4436 for (p
= extern_head
; p
!= 0; p
= p
->next
)
4438 name_tree
= get_identifier (p
->name
);
4440 /* Positively ensure only one .extern for any given symbol. */
4441 if (! TREE_ASM_WRITTEN (name_tree
))
4443 TREE_ASM_WRITTEN (name_tree
) = 1;
4444 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4446 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
4450 fputs ("\t.extern\t", file
);
4451 assemble_name (file
, p
->name
);
4452 fprintf (file
, ", %d\n", p
->size
);
4460 fprintf (file
, "\n\t.text\n");
4461 rewind (asm_out_text_file
);
4462 if (ferror (asm_out_text_file
))
4463 fatal_io_error (temp_filename
);
4465 while ((len
= fread (buffer
, 1, sizeof (buffer
), asm_out_text_file
)) > 0)
4466 if (fwrite (buffer
, 1, len
, file
) != len
)
4467 pfatal_with_name (asm_file_name
);
4470 pfatal_with_name (temp_filename
);
4472 if (fclose (asm_out_text_file
) != 0)
4473 pfatal_with_name (temp_filename
);
4476 unlink (temp_filename
);
4482 /* Emit either a label, .comm, or .lcomm directive, and mark
4483 that the symbol is used, so that we don't emit an .extern
4484 for it in mips_asm_file_end. */
4487 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
4494 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
4495 assemble_name (stream
, name
);
4496 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
4500 tree name_tree
= get_identifier (name
);
4501 TREE_ASM_WRITTEN (name_tree
) = 1;
4506 /* Output a double precision value to the assembler. If both the
4507 host and target are IEEE, emit the values in hex. */
4510 mips_output_double (stream
, value
)
4512 REAL_VALUE_TYPE value
;
4514 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4516 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
4518 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4519 value_long
[0], value
, value_long
[1]);
4521 fprintf (stream
, "\t.double\t%.20g\n", value
);
4526 /* Output a single precision value to the assembler. If both the
4527 host and target are IEEE, emit the values in hex. */
4530 mips_output_float (stream
, value
)
4532 REAL_VALUE_TYPE value
;
4534 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4536 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
4538 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
4540 fprintf (stream
, "\t.float\t%.12g\n", value
);
4545 /* Return TRUE if any register used in the epilogue is used. This to insure
4546 any insn put into the epilogue delay slots is safe. */
4549 epilogue_reg_mentioned_p (insn
)
4554 register enum rtx_code code
;
4560 if (GET_CODE (insn
) == LABEL_REF
)
4563 code
= GET_CODE (insn
);
4567 regno
= REGNO (insn
);
4568 if (regno
== STACK_POINTER_REGNUM
)
4571 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4574 if (!call_used_regs
[regno
])
4577 if (regno
!= MIPS_TEMP1_REGNUM
&& regno
!= MIPS_TEMP2_REGNUM
)
4580 if (!current_frame_info
.initialized
)
4581 compute_frame_size (get_frame_size ());
4583 return (current_frame_info
.total_size
>= 32768);
4593 fmt
= GET_RTX_FORMAT (code
);
4594 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4599 for (j
= XVECLEN (insn
, i
) - 1; j
>= 0; j
--)
4600 if (epilogue_reg_mentioned_p (XVECEXP (insn
, i
, j
)))
4603 else if (fmt
[i
] == 'e' && epilogue_reg_mentioned_p (XEXP (insn
, i
)))
4610 /* Return the bytes needed to compute the frame pointer from the current
4613 Mips stack frames look like:
4615 Before call After call
4616 +-----------------------+ +-----------------------+
4619 | caller's temps. | | caller's temps. |
4621 +-----------------------+ +-----------------------+
4623 | arguments on stack. | | arguments on stack. |
4625 +-----------------------+ +-----------------------+
4626 | 4 words to save | | 4 words to save |
4627 | arguments passed | | arguments passed |
4628 | in registers, even | | in registers, even |
4629 SP->| if not passed. | VFP->| if not passed. |
4630 +-----------------------+ +-----------------------+
4632 | fp register save |
4634 +-----------------------+
4636 | gp register save |
4638 +-----------------------+
4642 +-----------------------+
4644 | alloca allocations |
4646 +-----------------------+
4648 | GP save for V.4 abi |
4650 +-----------------------+
4652 | arguments on stack |
4654 +-----------------------+
4656 | arguments passed |
4657 | in registers, even |
4658 low SP->| if not passed. |
4659 memory +-----------------------+
4664 compute_frame_size (size
)
4665 int size
; /* # of var. bytes allocated */
4668 long total_size
; /* # bytes that the entire frame takes up */
4669 long var_size
; /* # bytes that variables take up */
4670 long args_size
; /* # bytes that outgoing arguments take up */
4671 long extra_size
; /* # extra bytes */
4672 long gp_reg_rounded
; /* # bytes needed to store gp after rounding */
4673 long gp_reg_size
; /* # bytes needed to store gp regs */
4674 long fp_reg_size
; /* # bytes needed to store fp regs */
4675 long mask
; /* mask of saved gp registers */
4676 long fmask
; /* mask of saved fp registers */
4677 int fp_inc
; /* 1 or 2 depending on the size of fp regs */
4678 long fp_bits
; /* bitmask to use for each fp register */
4684 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
4685 var_size
= MIPS_STACK_ALIGN (size
);
4686 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
4688 /* The MIPS 3.0 linker does not like functions that dynamically
4689 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4690 looks like we are trying to create a second frame pointer to the
4691 function, so allocate some stack space to make it happy. */
4693 if (args_size
== 0 && current_function_calls_alloca
)
4694 args_size
= 4*UNITS_PER_WORD
;
4696 total_size
= var_size
+ args_size
+ extra_size
;
4698 /* Calculate space needed for gp registers. */
4699 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4701 if (MUST_SAVE_REGISTER (regno
))
4703 gp_reg_size
+= UNITS_PER_WORD
;
4704 mask
|= 1L << (regno
- GP_REG_FIRST
);
4708 /* Calculate space needed for fp registers. */
4709 if (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
)
4720 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= fp_inc
)
4722 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
4724 fp_reg_size
+= fp_inc
* UNITS_PER_FPREG
;
4725 fmask
|= fp_bits
<< (regno
- FP_REG_FIRST
);
4729 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4730 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
4732 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4733 for leaf routines (total_size == extra_size) to save the gp reg.
4734 The gp reg is callee saved in the 64 bit ABI, so all routines must
4736 if (total_size
== extra_size
&& mips_abi
== ABI_32
)
4737 total_size
= extra_size
= 0;
4738 else if (TARGET_ABICALLS
)
4740 /* Add the context-pointer to the saved registers. */
4741 gp_reg_size
+= UNITS_PER_WORD
;
4742 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
4743 total_size
-= gp_reg_rounded
;
4744 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4745 total_size
+= gp_reg_rounded
;
4748 /* Add in space reserved on the stack by the callee for storing arguments
4749 passed in registers. */
4750 if (mips_abi
!= ABI_32
)
4751 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
4753 /* Save other computed information. */
4754 current_frame_info
.total_size
= total_size
;
4755 current_frame_info
.var_size
= var_size
;
4756 current_frame_info
.args_size
= args_size
;
4757 current_frame_info
.extra_size
= extra_size
;
4758 current_frame_info
.gp_reg_size
= gp_reg_size
;
4759 current_frame_info
.fp_reg_size
= fp_reg_size
;
4760 current_frame_info
.mask
= mask
;
4761 current_frame_info
.fmask
= fmask
;
4762 current_frame_info
.initialized
= reload_completed
;
4763 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
4764 current_frame_info
.num_fp
= fp_reg_size
/ (fp_inc
* UNITS_PER_FPREG
);
4768 unsigned long offset
= (args_size
+ extra_size
+ var_size
4769 + gp_reg_size
- UNITS_PER_WORD
);
4770 current_frame_info
.gp_sp_offset
= offset
;
4771 current_frame_info
.gp_save_offset
= offset
- total_size
;
4775 current_frame_info
.gp_sp_offset
= 0;
4776 current_frame_info
.gp_save_offset
= 0;
4782 unsigned long offset
= (args_size
+ extra_size
+ var_size
4783 + gp_reg_rounded
+ fp_reg_size
4784 - fp_inc
* UNITS_PER_FPREG
);
4785 current_frame_info
.fp_sp_offset
= offset
;
4786 current_frame_info
.fp_save_offset
= offset
- total_size
+ UNITS_PER_WORD
;
4790 current_frame_info
.fp_sp_offset
= 0;
4791 current_frame_info
.fp_save_offset
= 0;
4794 /* Ok, we're done. */
4799 /* Common code to emit the insns (or to write the instructions to a file)
4800 to save/restore registers.
4802 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4803 is not modified within save_restore_insns. */
4805 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4808 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
4809 int store_p
; /* true if this is prologue */
4810 rtx large_reg
; /* register holding large offset constant or NULL */
4811 long large_offset
; /* large constant offset value */
4812 FILE *file
; /* file to write instructions to instead of making RTL */
4814 long mask
= current_frame_info
.mask
;
4815 long fmask
= current_frame_info
.fmask
;
4823 if (frame_pointer_needed
&& !BITSET_P (mask
, FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
4826 if (mask
== 0 && fmask
== 0)
4829 /* Save registers starting from high to low. The debuggers prefer
4830 at least the return register be stored at func+4, and also it
4831 allows us not to need a nop in the epilog if at least one
4832 register is reloaded in addition to return address. */
4834 /* Save GP registers if needed. */
4837 /* Pick which pointer to use as a base register. For small
4838 frames, just use the stack pointer. Otherwise, use a
4839 temporary register. Save 2 cycles if the save area is near
4840 the end of a large frame, by reusing the constant created in
4841 the prologue/epilogue to adjust the stack frame. */
4843 gp_offset
= current_frame_info
.gp_sp_offset
;
4844 end_offset
= gp_offset
- (current_frame_info
.gp_reg_size
- UNITS_PER_WORD
);
4846 if (gp_offset
< 0 || end_offset
< 0)
4847 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
4848 gp_offset
, end_offset
);
4850 else if (gp_offset
< 32768)
4852 base_reg_rtx
= stack_pointer_rtx
;
4856 else if (large_reg
!= (rtx
)0
4857 && (((unsigned long)(large_offset
- gp_offset
)) < 32768)
4858 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
4860 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4861 base_offset
= large_offset
;
4862 if (file
== (FILE *)0)
4865 emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4867 emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4870 fprintf (file
, "\t%s\t%s,%s,%s\n",
4871 TARGET_LONG64
? "daddu" : "addu",
4872 reg_names
[MIPS_TEMP2_REGNUM
],
4873 reg_names
[REGNO (large_reg
)],
4874 reg_names
[STACK_POINTER_REGNUM
]);
4879 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4880 base_offset
= gp_offset
;
4881 if (file
== (FILE *)0)
4883 emit_move_insn (base_reg_rtx
, GEN_INT (gp_offset
));
4885 emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
4887 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
4890 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
4891 reg_names
[MIPS_TEMP2_REGNUM
],
4894 TARGET_LONG64
? "daddu" : "addu",
4895 reg_names
[MIPS_TEMP2_REGNUM
],
4896 reg_names
[MIPS_TEMP2_REGNUM
],
4897 reg_names
[STACK_POINTER_REGNUM
]);
4900 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
4902 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
4904 if (file
== (FILE *)0)
4906 rtx reg_rtx
= gen_rtx (REG
, word_mode
, regno
);
4907 rtx mem_rtx
= gen_rtx (MEM
, word_mode
,
4908 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
4909 GEN_INT (gp_offset
- base_offset
)));
4912 emit_move_insn (mem_rtx
, reg_rtx
);
4913 else if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
4914 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
4915 emit_move_insn (reg_rtx
, mem_rtx
);
4919 if (store_p
|| !TARGET_ABICALLS
|| mips_abi
!= ABI_32
4920 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
4921 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
4923 ? (store_p
) ? "sd" : "ld"
4924 : (store_p
) ? "sw" : "lw"),
4926 gp_offset
- base_offset
,
4927 reg_names
[REGNO(base_reg_rtx
)]);
4930 gp_offset
-= UNITS_PER_WORD
;
4936 base_reg_rtx
= (rtx
)0; /* Make sure these are initialized */
4940 /* Save floating point registers if needed. */
4943 int fp_inc
= (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
) ? 1 : 2;
4944 int fp_size
= fp_inc
* UNITS_PER_FPREG
;
4946 /* Pick which pointer to use as a base register. */
4947 fp_offset
= current_frame_info
.fp_sp_offset
;
4948 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
- fp_size
);
4950 if (fp_offset
< 0 || end_offset
< 0)
4951 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
4952 fp_offset
, end_offset
);
4954 else if (fp_offset
< 32768)
4956 base_reg_rtx
= stack_pointer_rtx
;
4960 else if (base_reg_rtx
!= (rtx
)0
4961 && (((unsigned long)(base_offset
- fp_offset
)) < 32768)
4962 && (((unsigned long)(base_offset
- end_offset
)) < 32768))
4964 ; /* already set up for gp registers above */
4967 else if (large_reg
!= (rtx
)0
4968 && (((unsigned long)(large_offset
- fp_offset
)) < 32768)
4969 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
4971 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4972 base_offset
= large_offset
;
4973 if (file
== (FILE *)0)
4976 emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4978 emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4981 fprintf (file
, "\t%s\t%s,%s,%s\n",
4982 TARGET_LONG64
? "daddu" : "addu",
4983 reg_names
[MIPS_TEMP2_REGNUM
],
4984 reg_names
[REGNO (large_reg
)],
4985 reg_names
[STACK_POINTER_REGNUM
]);
4990 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4991 base_offset
= fp_offset
;
4992 if (file
== (FILE *)0)
4994 emit_move_insn (base_reg_rtx
, GEN_INT (fp_offset
));
4996 emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
4998 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5001 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5002 reg_names
[MIPS_TEMP2_REGNUM
],
5005 TARGET_LONG64
? "daddu" : "addu",
5006 reg_names
[MIPS_TEMP2_REGNUM
],
5007 reg_names
[MIPS_TEMP2_REGNUM
],
5008 reg_names
[STACK_POINTER_REGNUM
]);
5011 for (regno
= FP_REG_LAST
-1; regno
>= FP_REG_FIRST
; regno
-= fp_inc
)
5013 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
5015 if (file
== (FILE *)0)
5017 enum machine_mode sz
=
5018 TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5019 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
5020 rtx mem_rtx
= gen_rtx (MEM
, sz
,
5021 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5022 GEN_INT (fp_offset
- base_offset
)));
5025 emit_move_insn (mem_rtx
, reg_rtx
);
5027 emit_move_insn (reg_rtx
, mem_rtx
);
5030 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5031 (TARGET_SINGLE_FLOAT
5032 ? ((store_p
) ? "s.s" : "l.s")
5033 : ((store_p
) ? "s.d" : "l.d")),
5035 fp_offset
- base_offset
,
5036 reg_names
[REGNO(base_reg_rtx
)]);
5039 fp_offset
-= fp_size
;
5046 /* Set up the stack and frame (if desired) for the function. */
5049 function_prologue (file
, size
)
5054 long tsize
= current_frame_info
.total_size
;
5056 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
5058 #ifdef SDB_DEBUGGING_INFO
5059 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
5060 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
5063 /* Get the function name the same way that toplev.c does before calling
5064 assemble_start_function. This is needed so that the name used here
5065 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5066 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5068 inside_function
= 1;
5069 fputs ("\t.ent\t", file
);
5070 assemble_name (file
, fnname
);
5073 assemble_name (file
, fnname
);
5074 fputs (":\n", file
);
5076 fprintf (file
, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5077 reg_names
[ (frame_pointer_needed
) ? FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
],
5079 reg_names
[31 + GP_REG_FIRST
],
5080 current_frame_info
.var_size
,
5081 current_frame_info
.num_gp
,
5082 current_frame_info
.num_fp
,
5083 current_function_outgoing_args_size
,
5084 current_frame_info
.extra_size
);
5086 fprintf (file
, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
5087 current_frame_info
.mask
,
5088 current_frame_info
.gp_save_offset
,
5089 current_frame_info
.fmask
,
5090 current_frame_info
.fp_save_offset
);
5092 if (TARGET_ABICALLS
&& mips_abi
== ABI_32
)
5094 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5096 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
5097 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
5100 fprintf (file
, "\t%s\t%s,%s,%d\n",
5101 (TARGET_LONG64
? "dsubu" : "subu"),
5102 sp_str
, sp_str
, tsize
);
5103 fprintf (file
, "\t.cprestore %d\n", current_frame_info
.args_size
);
5109 /* Expand the prologue into a bunch of separate insns. */
5112 mips_expand_prologue ()
5116 rtx tmp_rtx
= (rtx
)0;
5117 char *arg_name
= (char *)0;
5118 tree fndecl
= current_function_decl
;
5119 tree fntype
= TREE_TYPE (fndecl
);
5120 tree fnargs
= DECL_ARGUMENTS (fndecl
);
5125 CUMULATIVE_ARGS args_so_far
;
5127 /* If struct value address is treated as the first argument, make it so. */
5128 if (aggregate_value_p (DECL_RESULT (fndecl
))
5129 && ! current_function_returns_pcc_struct
5130 && struct_value_incoming_rtx
== 0)
5132 tree type
= build_pointer_type (fntype
);
5133 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
5134 DECL_ARG_TYPE (function_result_decl
) = type
;
5135 TREE_CHAIN (function_result_decl
) = fnargs
;
5136 fnargs
= function_result_decl
;
5139 /* Determine the last argument, and get its name. */
5141 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, (rtx
)0, 0);
5142 regno
= GP_ARG_FIRST
;
5144 for (cur_arg
= fnargs
; cur_arg
!= (tree
)0; cur_arg
= next_arg
)
5146 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
5147 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
5150 if (TREE_ADDRESSABLE (passed_type
))
5152 passed_type
= build_pointer_type (passed_type
);
5153 passed_mode
= Pmode
;
5156 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
5162 /* passed in a register, so will get homed automatically */
5163 if (GET_MODE (entry_parm
) == BLKmode
)
5164 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
5166 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
5168 regno
= REGNO (entry_parm
) + words
- 1;
5172 regno
= GP_ARG_LAST
+1;
5176 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
5178 next_arg
= TREE_CHAIN (cur_arg
);
5179 if (next_arg
== (tree
)0)
5181 if (DECL_NAME (cur_arg
))
5182 arg_name
= IDENTIFIER_POINTER (DECL_NAME (cur_arg
));
5188 /* In order to pass small structures by value in registers
5189 compatibly with the MIPS compiler, we need to shift the value
5190 into the high part of the register. Function_arg has encoded a
5191 PARALLEL rtx, holding a vector of adjustments to be made as the
5192 next_arg_reg variable, so we split up the insns, and emit them
5195 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
5196 if (next_arg_reg
!= (rtx
)0 && GET_CODE (next_arg_reg
) == PARALLEL
)
5198 rtvec adjust
= XVEC (next_arg_reg
, 0);
5199 int num
= GET_NUM_ELEM (adjust
);
5201 for (i
= 0; i
< num
; i
++)
5203 rtx pattern
= RTVEC_ELT (adjust
, i
);
5204 if (GET_CODE (pattern
) != SET
5205 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
5206 abort_with_insn (pattern
, "Insn is not a shift");
5208 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
5209 emit_insn (pattern
);
5213 tsize
= compute_frame_size (get_frame_size ());
5215 /* If this function is a varargs function, store any registers that
5216 would normally hold arguments ($4 - $7) on the stack. */
5217 if (mips_abi
== ABI_32
5218 && ((TYPE_ARG_TYPES (fntype
) != 0
5219 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
))) != void_type_node
))
5220 || (arg_name
!= (char *)0
5221 && ((arg_name
[0] == '_' && strcmp (arg_name
, "__builtin_va_alist") == 0)
5222 || (arg_name
[0] == 'v' && strcmp (arg_name
, "va_alist") == 0)))))
5224 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
5225 rtx ptr
= stack_pointer_rtx
;
5227 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
5228 if (TARGET_ABICALLS
)
5231 for (; regno
<= GP_ARG_LAST
; regno
++)
5234 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
5235 emit_move_insn (gen_rtx (MEM
, word_mode
, ptr
),
5236 gen_rtx (REG
, word_mode
, regno
));
5237 offset
+= UNITS_PER_WORD
;
5243 rtx tsize_rtx
= GEN_INT (tsize
);
5245 /* If we are doing svr4-abi, sp move is done by function_prologue. */
5246 if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
)
5250 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5251 emit_move_insn (tmp_rtx
, tsize_rtx
);
5252 tsize_rtx
= tmp_rtx
;
5256 emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5259 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5263 save_restore_insns (TRUE
, tmp_rtx
, tsize
, (FILE *)0);
5265 if (frame_pointer_needed
)
5268 emit_insn (gen_movdi (frame_pointer_rtx
, stack_pointer_rtx
));
5270 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
5273 if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
)
5274 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0)));
5277 /* If we are profiling, make sure no instructions are scheduled before
5278 the call to mcount. */
5280 if (profile_flag
|| profile_block_flag
)
5281 emit_insn (gen_blockage ());
5285 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
5287 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5288 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5291 function_epilogue (file
, size
)
5297 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5298 char *t1_str
= reg_names
[MIPS_TEMP1_REGNUM
];
5299 rtx epilogue_delay
= current_function_epilogue_delay_list
;
5300 int noreorder
= (epilogue_delay
!= 0);
5301 int noepilogue
= FALSE
;
5302 int load_nop
= FALSE
;
5304 rtx tmp_rtx
= (rtx
)0;
5308 /* The epilogue does not depend on any registers, but the stack
5309 registers, so we assume that if we have 1 pending nop, it can be
5310 ignored, and 2 it must be filled (2 nops occur for integer
5311 multiply and divide). */
5313 if (dslots_number_nops
> 0)
5315 if (dslots_number_nops
== 1)
5317 dslots_number_nops
= 0;
5318 dslots_load_filled
++;
5322 while (--dslots_number_nops
> 0)
5323 fputs ("\t#nop\n", asm_out_file
);
5330 fputs ("\t.set\tat\n", file
);
5331 error ("internal gcc error: .set noat left on in epilogue");
5334 if (set_nomacro
!= 0)
5337 fputs ("\t.set\tmacro\n", file
);
5338 error ("internal gcc error: .set nomacro left on in epilogue");
5341 if (set_noreorder
!= 0)
5344 fputs ("\t.set\treorder\n", file
);
5345 error ("internal gcc error: .set noreorder left on in epilogue");
5348 if (set_volatile
!= 0)
5351 fprintf (file
, "\t%s.set\tnovolatile\n", (TARGET_MIPS_AS
) ? "" : "#");
5352 error ("internal gcc error: .set volatile left on in epilogue");
5355 size
= MIPS_STACK_ALIGN (size
);
5356 tsize
= (!current_frame_info
.initialized
)
5357 ? compute_frame_size (size
)
5358 : current_frame_info
.total_size
;
5360 if (tsize
== 0 && epilogue_delay
== 0)
5362 rtx insn
= get_last_insn ();
5364 /* If the last insn was a BARRIER, we don't have to write any code
5365 because a jump (aka return) was put there. */
5366 if (GET_CODE (insn
) == NOTE
)
5367 insn
= prev_nonnote_insn (insn
);
5368 if (insn
&& GET_CODE (insn
) == BARRIER
)
5376 /* In the reload sequence, we don't need to fill the load delay
5377 slots for most of the loads, also see if we can fill the final
5378 delay slot if not otherwise filled by the reload sequence. */
5381 fprintf (file
, "\t.set\tnoreorder\n");
5385 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n", t1_str
, (long)tsize
, (long)tsize
);
5386 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5389 if (frame_pointer_needed
)
5390 fprintf (file
, "\tmove\t%s,%s\t\t\t# sp not trusted here\n",
5391 sp_str
, reg_names
[FRAME_POINTER_REGNUM
]);
5393 save_restore_insns (FALSE
, tmp_rtx
, tsize
, file
);
5395 load_only_r31
= (((current_frame_info
.mask
5396 & ~ (TARGET_ABICALLS
&& mips_abi
== ABI_32
5397 ? PIC_OFFSET_TABLE_MASK
: 0))
5399 && current_frame_info
.fmask
== 0);
5403 /* If the only register saved is the return address, we need a
5404 nop, unless we have an instruction to put into it. Otherwise
5405 we don't since reloading multiple registers doesn't reference
5406 the register being loaded. */
5411 final_scan_insn (XEXP (epilogue_delay
, 0),
5415 1); /* nopeepholes */
5418 fprintf (file
, "\tnop\n");
5423 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5426 fprintf (file
, "\t%s\t%s,%s,%s\n",
5427 TARGET_LONG64
? "daddu" : "addu",
5428 sp_str
, sp_str
, t1_str
);
5431 fprintf (file
, "\t%s\t%s,%s,%d\n",
5432 TARGET_LONG64
? "daddu" : "addu",
5433 sp_str
, sp_str
, tsize
);
5435 else if (!load_only_r31
&& epilogue_delay
!= 0)
5436 final_scan_insn (XEXP (epilogue_delay
, 0),
5440 1); /* nopeepholes */
5442 fprintf (file
, "\t.set\treorder\n");
5448 fprintf (file
, "\t%s\t%s,%s,%s\n",
5449 TARGET_LONG64
? "daddu" : "addu",
5450 sp_str
, sp_str
, t1_str
);
5453 fprintf (file
, "\t%s\t%s,%s,%d\n",
5454 TARGET_LONG64
? "daddu" : "addu",
5455 sp_str
, sp_str
, tsize
);
5457 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5461 /* Get the function name the same way that toplev.c does before calling
5462 assemble_start_function. This is needed so that the name used here
5463 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5464 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5466 fputs ("\t.end\t", file
);
5467 assemble_name (file
, fnname
);
5472 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
5473 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
5474 int num_regs
= num_gp_regs
+ num_fp_regs
;
5475 char *name
= fnname
;
5480 dslots_load_total
+= num_regs
;
5483 dslots_jump_total
++;
5487 dslots_load_filled
+= num_regs
;
5489 /* If the only register saved is the return register, we
5490 can't fill this register's delay slot. */
5492 if (load_only_r31
&& epilogue_delay
== 0)
5493 dslots_load_filled
--;
5495 if (tsize
> 0 || (!load_only_r31
&& epilogue_delay
!= 0))
5496 dslots_jump_filled
++;
5500 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5502 (frame_pointer_needed
) ? 'y' : 'n',
5503 ((current_frame_info
.mask
& RA_MASK
) != 0) ? 'n' : 'y',
5504 (current_function_calls_alloca
) ? 'y' : 'n',
5505 (current_function_calls_setjmp
) ? 'y' : 'n',
5506 (long)current_frame_info
.total_size
,
5507 (long)current_function_outgoing_args_size
,
5508 num_gp_regs
, num_fp_regs
,
5509 dslots_load_total
, dslots_load_filled
,
5510 dslots_jump_total
, dslots_jump_filled
,
5511 num_refs
[0], num_refs
[1], num_refs
[2]);
5513 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
5515 fprintf (stderr
, " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
5516 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
5519 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
5521 fprintf (stderr
, " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
5522 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
5525 fputc ('\n', stderr
);
5528 /* Reset state info for each function. */
5529 inside_function
= FALSE
;
5530 ignore_line_number
= FALSE
;
5531 dslots_load_total
= 0;
5532 dslots_jump_total
= 0;
5533 dslots_load_filled
= 0;
5534 dslots_jump_filled
= 0;
5538 mips_load_reg
= (rtx
)0;
5539 mips_load_reg2
= (rtx
)0;
5540 current_frame_info
= zero_frame_info
;
5542 /* Restore the output file if optimizing the GP (optimizing the GP causes
5543 the text to be diverted to a tempfile, so that data decls come before
5544 references to the data). */
5547 asm_out_file
= asm_out_data_file
;
5551 /* Expand the epilogue into a bunch of separate insns. */
5554 mips_expand_epilogue ()
5556 long tsize
= current_frame_info
.total_size
;
5557 rtx tsize_rtx
= GEN_INT (tsize
);
5558 rtx tmp_rtx
= (rtx
)0;
5562 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5563 emit_move_insn (tmp_rtx
, tsize_rtx
);
5564 tsize_rtx
= tmp_rtx
;
5569 if (frame_pointer_needed
)
5572 emit_insn (gen_movdi (stack_pointer_rtx
, frame_pointer_rtx
));
5574 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
5577 save_restore_insns (FALSE
, tmp_rtx
, tsize
, (FILE *)0);
5580 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5583 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5587 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
, GP_REG_FIRST
+31)));
5591 /* Define the number of delay slots needed for the function epilogue.
5593 On the mips, we need a slot if either no stack has been allocated,
5594 or the only register saved is the return register. */
5597 mips_epilogue_delay_slots ()
5599 if (!current_frame_info
.initialized
)
5600 (void) compute_frame_size (get_frame_size ());
5602 if (current_frame_info
.total_size
== 0)
5605 if (current_frame_info
.mask
== RA_MASK
&& current_frame_info
.fmask
== 0)
5612 /* Return true if this function is known to have a null epilogue.
5613 This allows the optimizer to omit jumps to jumps if no stack
5617 simple_epilogue_p ()
5619 if (!reload_completed
)
5622 if (current_frame_info
.initialized
)
5623 return current_frame_info
.total_size
== 0;
5625 return (compute_frame_size (get_frame_size ())) == 0;
5628 /* Choose the section to use for the constant rtx expression X that has
5631 mips_select_rtx_section (mode
, x
)
5632 enum machine_mode mode
;
5635 if (TARGET_EMBEDDED_DATA
)
5637 /* For embedded applications, always put constants in read-only data,
5638 in order to reduce RAM usage. */
5639 READONLY_DATA_SECTION ();
5643 /* For hosted applications, always put constants in small data if
5644 possible, as this gives the best performance. */
5646 if (GET_MODE_SIZE (mode
) <= mips_section_threshold
5647 && mips_section_threshold
> 0)
5648 SMALL_DATA_SECTION ();
5650 READONLY_DATA_SECTION ();
5654 /* Choose the section to use for DECL. RELOC is true if its value contains
5655 any relocatable expression. */
5657 mips_select_section (decl
, reloc
)
5661 int size
= int_size_in_bytes (TREE_TYPE (decl
));
5663 if (TARGET_EMBEDDED_PIC
5664 && TREE_CODE (decl
) == STRING_CST
5665 && !flag_writable_strings
)
5667 /* For embedded position independent code, put constant strings
5668 in the text section, because the data section is limited to
5673 else if (TARGET_EMBEDDED_DATA
)
5675 /* For embedded applications, always put an object in read-only data
5676 if possible, in order to reduce RAM usage. */
5678 if (((TREE_CODE (decl
) == VAR_DECL
5679 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5680 && DECL_INITIAL (decl
)
5681 && (DECL_INITIAL (decl
) == error_mark_node
5682 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5683 /* Deal with calls from output_constant_def_contents. */
5684 || (TREE_CODE (decl
) != VAR_DECL
5685 && (TREE_CODE (decl
) != STRING_CST
5686 || !flag_writable_strings
)))
5687 && ! (flag_pic
&& reloc
))
5688 READONLY_DATA_SECTION ();
5689 else if (size
> 0 && size
<= mips_section_threshold
)
5690 SMALL_DATA_SECTION ();
5696 /* For hosted applications, always put an object in small data if
5697 possible, as this gives the best performance. */
5699 if (size
> 0 && size
<= mips_section_threshold
)
5700 SMALL_DATA_SECTION ();
5701 else if (((TREE_CODE (decl
) == VAR_DECL
5702 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5703 && DECL_INITIAL (decl
)
5704 && (DECL_INITIAL (decl
) == error_mark_node
5705 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5706 /* Deal with calls from output_constant_def_contents. */
5707 || (TREE_CODE (decl
) != VAR_DECL
5708 && (TREE_CODE (decl
) != STRING_CST
5709 || !flag_writable_strings
)))
5710 && ! (flag_pic
&& reloc
))
5711 READONLY_DATA_SECTION ();
5717 #ifdef MIPS_ABI_DEFAULT
5718 /* Support functions for the 64 bit ABI. */
5720 /* Return register to use for a function return value with VALTYPE for function
5724 mips_function_value (valtype
, func
)
5728 int reg
= GP_RETURN
;
5729 enum machine_mode mode
= TYPE_MODE (valtype
);
5730 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5732 /* ??? How should we return complex float? */
5733 if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5735 else if (TREE_CODE (valtype
) == RECORD_TYPE
&& mips_abi
!= ABI_32
)
5737 /* A struct with only one or two floating point fields is returned in
5738 the floating point registers. */
5739 tree field
, fields
[2];
5742 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
5743 field
= TREE_CHAIN (field
))
5745 if (TREE_CODE (field
) != FIELD_DECL
)
5747 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
5750 fields
[i
++] = field
;
5753 /* Must check i, so that we reject structures with no elements. */
5758 /* The structure has DImode, but we don't allow DImode values
5759 in FP registers, so we use a PARALLEL even though it isn't
5760 strictly necessary. */
5761 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
5763 return gen_rtx (PARALLEL
, mode
,
5765 gen_rtx (EXPR_LIST
, VOIDmode
,
5766 gen_rtx (REG
, field_mode
, FP_RETURN
),
5771 enum machine_mode first_mode
5772 = TYPE_MODE (TREE_TYPE (fields
[0]));
5773 enum machine_mode second_mode
5774 = TYPE_MODE (TREE_TYPE (fields
[1]));
5776 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[0]));
5778 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[1]));
5780 return gen_rtx (PARALLEL
, mode
,
5782 gen_rtx (EXPR_LIST
, VOIDmode
,
5783 gen_rtx (REG
, first_mode
, FP_RETURN
),
5784 GEN_INT (first_offset
/ BITS_PER_UNIT
)),
5785 gen_rtx (EXPR_LIST
, VOIDmode
,
5786 gen_rtx (REG
, second_mode
, FP_RETURN
+ 2),
5787 GEN_INT (second_offset
/ BITS_PER_UNIT
))));
5792 return gen_rtx (REG
, mode
, reg
);
5796 /* This function returns the register class required for a secondary
5797 register when copying between one of the registers in CLASS, and X,
5798 using MODE. If IN_P is nonzero, the copy is going from X to the
5799 register, otherwise the register is the source. A return value of
5800 NO_REGS means that no secondary register is required. */
5803 mips_secondary_reload_class (class, mode
, x
, in_p
)
5804 enum reg_class
class;
5805 enum machine_mode mode
;
5811 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
5812 regno
= true_regnum (x
);
5814 /* We always require a general register when copying anything to
5815 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
5816 to a general register, or when copying from register 0. */
5817 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
5821 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
5825 if (regno
== HILO_REGNUM
)
5829 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
5834 /* Copying from HI or LO to anywhere other than a general register
5835 requires a general register. */
5836 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
5838 if (GP_REG_P (regno
))
5842 if (MD_REG_P (regno
))
5844 if (class == GR_REGS
)