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(function_arg): Add explicit checks for FIELD_DECLs.
[gcc.git] / gcc / config / mips / mips.c
1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-95, 1996 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
28
29 #include "config.h"
30 #include "rtl.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-flags.h"
37 #include "insn-attr.h"
38 #include "insn-codes.h"
39 #include "recog.h"
40 #include "output.h"
41
42 #undef MAX /* sys/param.h may also define these */
43 #undef MIN
44
45 #include <stdio.h>
46 #include <signal.h>
47 #include <sys/types.h>
48 #include <sys/file.h>
49 #include <ctype.h>
50 #include "tree.h"
51 #include "expr.h"
52 #include "flags.h"
53
54 #ifndef R_OK
55 #define R_OK 4
56 #define W_OK 2
57 #define X_OK 1
58 #endif
59
60 #if defined(USG) || defined(NO_STAB_H)
61 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
62 #else
63 #include <stab.h> /* On BSD, use the system's stab.h. */
64 #endif /* not USG */
65
66 #ifdef __GNU_STAB__
67 #define STAB_CODE_TYPE enum __stab_debug_code
68 #else
69 #define STAB_CODE_TYPE int
70 #endif
71
72 extern void abort ();
73 extern int atoi ();
74 extern char *getenv ();
75 extern char *mktemp ();
76
77 extern rtx adj_offsettable_operand ();
78 extern rtx copy_to_reg ();
79 extern void error ();
80 extern void fatal ();
81 extern tree lookup_name ();
82 extern void pfatal_with_name ();
83 extern void warning ();
84
85 extern FILE *asm_out_file;
86
87 /* Enumeration for all of the relational tests, so that we can build
88 arrays indexed by the test type, and not worry about the order
89 of EQ, NE, etc. */
90
91 enum internal_test {
92 ITEST_EQ,
93 ITEST_NE,
94 ITEST_GT,
95 ITEST_GE,
96 ITEST_LT,
97 ITEST_LE,
98 ITEST_GTU,
99 ITEST_GEU,
100 ITEST_LTU,
101 ITEST_LEU,
102 ITEST_MAX
103 };
104
105 /* Global variables for machine-dependent things. */
106
107 /* Threshold for data being put into the small data/bss area, instead
108 of the normal data area (references to the small data/bss area take
109 1 instruction, and use the global pointer, references to the normal
110 data area takes 2 instructions). */
111 int mips_section_threshold = -1;
112
113 /* Count the number of .file directives, so that .loc is up to date. */
114 int num_source_filenames = 0;
115
116 /* Count the number of sdb related labels are generated (to find block
117 start and end boundaries). */
118 int sdb_label_count = 0;
119
120 /* Next label # for each statement for Silicon Graphics IRIS systems. */
121 int sym_lineno = 0;
122
123 /* Non-zero if inside of a function, because the stupid MIPS asm can't
124 handle .files inside of functions. */
125 int inside_function = 0;
126
127 /* Files to separate the text and the data output, so that all of the data
128 can be emitted before the text, which will mean that the assembler will
129 generate smaller code, based on the global pointer. */
130 FILE *asm_out_data_file;
131 FILE *asm_out_text_file;
132
133 /* Linked list of all externals that are to be emitted when optimizing
134 for the global pointer if they haven't been declared by the end of
135 the program with an appropriate .comm or initialization. */
136
137 struct extern_list {
138 struct extern_list *next; /* next external */
139 char *name; /* name of the external */
140 int size; /* size in bytes */
141 } *extern_head = 0;
142
143 /* Name of the file containing the current function. */
144 char *current_function_file = "";
145
146 /* Warning given that Mips ECOFF can't support changing files
147 within a function. */
148 int file_in_function_warning = FALSE;
149
150 /* Whether to suppress issuing .loc's because the user attempted
151 to change the filename within a function. */
152 int ignore_line_number = FALSE;
153
154 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
155 int set_noreorder;
156 int set_noat;
157 int set_nomacro;
158 int set_volatile;
159
160 /* The next branch instruction is a branch likely, not branch normal. */
161 int mips_branch_likely;
162
163 /* Count of delay slots and how many are filled. */
164 int dslots_load_total;
165 int dslots_load_filled;
166 int dslots_jump_total;
167 int dslots_jump_filled;
168
169 /* # of nops needed by previous insn */
170 int dslots_number_nops;
171
172 /* Number of 1/2/3 word references to data items (ie, not jal's). */
173 int num_refs[3];
174
175 /* registers to check for load delay */
176 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
177
178 /* Cached operands, and operator to compare for use in set/branch on
179 condition codes. */
180 rtx branch_cmp[2];
181
182 /* what type of branch to use */
183 enum cmp_type branch_type;
184
185 /* Number of previously seen half-pic pointers and references. */
186 static int prev_half_pic_ptrs = 0;
187 static int prev_half_pic_refs = 0;
188
189 /* which cpu are we scheduling for */
190 enum processor_type mips_cpu;
191
192 /* which instruction set architecture to use. */
193 int mips_isa;
194
195 #ifdef MIPS_ABI_DEFAULT
196 /* which ABI to use. This is defined to a constant in mips.h if the target
197 doesn't support multiple ABIs. */
198 enum mips_abi_type mips_abi;
199 #endif
200
201 /* Strings to hold which cpu and instruction set architecture to use. */
202 char *mips_cpu_string; /* for -mcpu=<xxx> */
203 char *mips_isa_string; /* for -mips{1,2,3,4} */
204 char *mips_abi_string; /* for -mabi={o32,32,n32,n64,64} */
205
206 /* If TRUE, we split addresses into their high and low parts in the RTL. */
207 int mips_split_addresses;
208
209 /* Generating calls to position independent functions? */
210 enum mips_abicalls_type mips_abicalls;
211
212 /* High and low marks for floating point values which we will accept
213 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
214 initialized in override_options. */
215 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
216
217 /* Array giving truth value on whether or not a given hard register
218 can support a given mode. */
219 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
220
221 /* Current frame information calculated by compute_frame_size. */
222 struct mips_frame_info current_frame_info;
223
224 /* Zero structure to initialize current_frame_info. */
225 struct mips_frame_info zero_frame_info;
226
227 /* Temporary filename used to buffer .text until end of program
228 for -mgpopt. */
229 static char *temp_filename;
230
231 /* Pseudo-reg holding the address of the current function when
232 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
233 by mips_finalize_pic if it was created. */
234 rtx embedded_pic_fnaddr_rtx;
235
236 /* List of all MIPS punctuation characters used by print_operand. */
237 char mips_print_operand_punct[256];
238
239 /* Map GCC register number to debugger register number. */
240 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
241
242 /* Buffer to use to enclose a load/store operation with %{ %} to
243 turn on .set volatile. */
244 static char volatile_buffer[60];
245
246 /* Hardware names for the registers. If -mrnames is used, this
247 will be overwritten with mips_sw_reg_names. */
248
249 char mips_reg_names[][8] =
250 {
251 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
252 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
253 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
254 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
255 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
256 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
257 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
258 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
259 "hi", "lo", "accum","$fcr31","$rap"
260 };
261
262 /* Mips software names for the registers, used to overwrite the
263 mips_reg_names array. */
264
265 char mips_sw_reg_names[][8] =
266 {
267 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
268 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
269 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
270 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
271 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
272 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
273 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
274 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
275 "hi", "lo", "accum","$fcr31","$rap"
276 };
277
278 /* Map hard register number to register class */
279 enum reg_class mips_regno_to_class[] =
280 {
281 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
282 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
283 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
284 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
285 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
286 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
287 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
288 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
289 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
290 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
291 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
292 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
293 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
294 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
295 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
296 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
297 HI_REG, LO_REG, HILO_REG, ST_REGS,
298 GR_REGS
299 };
300
301 /* Map register constraint character to register class. */
302 enum reg_class mips_char_to_class[256] =
303 {
304 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
305 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
306 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
307 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
308 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
309 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
310 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
311 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
312 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
313 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
314 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
315 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
316 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
317 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
318 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
319 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
320 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
321 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
322 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
323 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
324 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
325 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
326 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
327 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
328 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
329 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
330 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
331 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
332 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
333 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
334 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
335 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
336 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
337 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
338 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
339 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
340 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
341 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
342 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
343 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
344 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
345 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
346 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
347 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
348 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
349 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
350 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
351 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
352 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
353 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
354 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
355 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
356 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
357 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
358 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
359 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
360 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
361 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
362 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
363 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
364 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
365 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
366 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
367 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
368 };
369
370 \f
371 /* Return truth value of whether OP can be used as an operands
372 where a register or 16 bit unsigned integer is needed. */
373
374 int
375 uns_arith_operand (op, mode)
376 rtx op;
377 enum machine_mode mode;
378 {
379 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
380 return TRUE;
381
382 return register_operand (op, mode);
383 }
384
385 /* Return truth value of whether OP can be used as an operands
386 where a 16 bit integer is needed */
387
388 int
389 arith_operand (op, mode)
390 rtx op;
391 enum machine_mode mode;
392 {
393 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
394 return TRUE;
395
396 return register_operand (op, mode);
397 }
398
399 /* Return truth value of whether OP can be used as an operand in a two
400 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
401
402 int
403 arith32_operand (op, mode)
404 rtx op;
405 enum machine_mode mode;
406 {
407 if (GET_CODE (op) == CONST_INT)
408 return TRUE;
409
410 return register_operand (op, mode);
411 }
412
413 /* Return truth value of whether OP is a integer which fits in 16 bits */
414
415 int
416 small_int (op, mode)
417 rtx op;
418 enum machine_mode mode;
419 {
420 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
421 }
422
423 /* Return truth value of whether OP is a 32 bit integer which is too big to
424 be loaded with one instruction. */
425
426 int
427 large_int (op, mode)
428 rtx op;
429 enum machine_mode mode;
430 {
431 HOST_WIDE_INT value;
432
433 if (GET_CODE (op) != CONST_INT)
434 return FALSE;
435
436 value = INTVAL (op);
437 if ((value & ~0x0000ffff) == 0) /* ior reg,$r0,value */
438 return FALSE;
439
440 if (((unsigned long)(value + 32768)) <= 32767) /* subu reg,$r0,value */
441 return FALSE;
442
443 if ((value & 0x0000ffff) == 0) /* lui reg,value>>16 */
444 return FALSE;
445
446 return TRUE;
447 }
448
449 /* Return truth value of whether OP is a register or the constant 0. */
450
451 int
452 reg_or_0_operand (op, mode)
453 rtx op;
454 enum machine_mode mode;
455 {
456 switch (GET_CODE (op))
457 {
458 default:
459 break;
460
461 case CONST_INT:
462 return (INTVAL (op) == 0);
463
464 case CONST_DOUBLE:
465 if (op != CONST0_RTX (mode))
466 return FALSE;
467
468 return TRUE;
469
470 case REG:
471 case SUBREG:
472 return register_operand (op, mode);
473 }
474
475 return FALSE;
476 }
477
478 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
479
480 int
481 mips_const_double_ok (op, mode)
482 rtx op;
483 enum machine_mode mode;
484 {
485 REAL_VALUE_TYPE d;
486
487 if (GET_CODE (op) != CONST_DOUBLE)
488 return FALSE;
489
490 if (mode == VOIDmode)
491 return TRUE;
492
493 if (mode != SFmode && mode != DFmode)
494 return FALSE;
495
496 if (op == CONST0_RTX (mode))
497 return TRUE;
498
499 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
500 if (mips_abi != ABI_32)
501 return FALSE;
502
503 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
504
505 if (REAL_VALUE_ISNAN (d))
506 return FALSE;
507
508 if (REAL_VALUE_NEGATIVE (d))
509 d = REAL_VALUE_NEGATE (d);
510
511 if (mode == DFmode)
512 {
513 if (REAL_VALUES_LESS (d, dfhigh)
514 && REAL_VALUES_LESS (dflow, d))
515 return TRUE;
516 }
517 else
518 {
519 if (REAL_VALUES_LESS (d, sfhigh)
520 && REAL_VALUES_LESS (sflow, d))
521 return TRUE;
522 }
523
524 return FALSE;
525 }
526
527 /* Return truth value if a memory operand fits in a single instruction
528 (ie, register + small offset). */
529
530 int
531 simple_memory_operand (op, mode)
532 rtx op;
533 enum machine_mode mode;
534 {
535 rtx addr, plus0, plus1;
536
537 /* Eliminate non-memory operations */
538 if (GET_CODE (op) != MEM)
539 return FALSE;
540
541 /* dword operations really put out 2 instructions, so eliminate them. */
542 /* ??? This isn't strictly correct. It is OK to accept multiword modes
543 here, since the length attributes are being set correctly, but only
544 if the address is offsettable. LO_SUM is not offsettable. */
545 if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD)
546 return FALSE;
547
548 /* Decode the address now. */
549 addr = XEXP (op, 0);
550 switch (GET_CODE (addr))
551 {
552 default:
553 break;
554
555 case REG:
556 case LO_SUM:
557 return TRUE;
558
559 case CONST_INT:
560 return SMALL_INT (op);
561
562 case PLUS:
563 plus0 = XEXP (addr, 0);
564 plus1 = XEXP (addr, 1);
565 if (GET_CODE (plus0) == REG
566 && GET_CODE (plus1) == CONST_INT
567 && SMALL_INT (plus1))
568 return TRUE;
569
570 else if (GET_CODE (plus1) == REG
571 && GET_CODE (plus0) == CONST_INT
572 && SMALL_INT (plus0))
573 return TRUE;
574
575 else
576 return FALSE;
577
578 #if 0
579 /* We used to allow small symbol refs here (ie, stuff in .sdata
580 or .sbss), but this causes some bugs in G++. Also, it won't
581 interfere if the MIPS linker rewrites the store instruction
582 because the function is PIC. */
583
584 case LABEL_REF: /* never gp relative */
585 break;
586
587 case CONST:
588 /* If -G 0, we can never have a GP relative memory operation.
589 Also, save some time if not optimizing. */
590 if (!TARGET_GP_OPT)
591 return FALSE;
592
593 {
594 rtx offset = const0_rtx;
595 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
596 if (GET_CODE (op) != SYMBOL_REF)
597 return FALSE;
598
599 /* let's be paranoid.... */
600 if (! SMALL_INT (offset))
601 return FALSE;
602 }
603 /* fall through */
604
605 case SYMBOL_REF:
606 return SYMBOL_REF_FLAG (addr);
607 #endif
608 }
609
610 return FALSE;
611 }
612
613 /* Return true if the code of this rtx pattern is EQ or NE. */
614
615 int
616 equality_op (op, mode)
617 rtx op;
618 enum machine_mode mode;
619 {
620 if (mode != GET_MODE (op))
621 return FALSE;
622
623 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
624 }
625
626 /* Return true if the code is a relational operations (EQ, LE, etc.) */
627
628 int
629 cmp_op (op, mode)
630 rtx op;
631 enum machine_mode mode;
632 {
633 if (mode != GET_MODE (op))
634 return FALSE;
635
636 return (GET_RTX_CLASS (GET_CODE (op)) == '<');
637 }
638
639 /* Return true if the operand is either the PC or a label_ref. */
640
641 int
642 pc_or_label_operand (op, mode)
643 rtx op;
644 enum machine_mode mode;
645 {
646 if (op == pc_rtx)
647 return TRUE;
648
649 if (GET_CODE (op) == LABEL_REF)
650 return TRUE;
651
652 return FALSE;
653 }
654
655 /* Test for a valid operand for a call instruction.
656 Don't allow the arg pointer register or virtual regs
657 since they may change into reg + const, which the patterns
658 can't handle yet. */
659
660 int
661 call_insn_operand (op, mode)
662 rtx op;
663 enum machine_mode mode;
664 {
665 if (CONSTANT_ADDRESS_P (op)
666 || (GET_CODE (op) == REG && op != arg_pointer_rtx
667 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
668 && REGNO (op) <= LAST_VIRTUAL_REGISTER)))
669 return 1;
670 return 0;
671 }
672
673 /* Return true if OPERAND is valid as a source operand for a move
674 instruction. */
675
676 int
677 move_operand (op, mode)
678 rtx op;
679 enum machine_mode mode;
680 {
681 return (general_operand (op, mode)
682 && ! (mips_split_addresses && mips_check_split (op, mode)));
683 }
684
685 /* Return true if we split the address into high and low parts. */
686
687 /* ??? We should also handle reg+array somewhere. We get four
688 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
689 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
690 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
691 out of the address, then we have 4 instructions to combine. Perhaps
692 add a 3->2 define_split for combine. */
693
694 /* ??? We could also split a CONST_INT here if it is a large_int().
695 However, it doesn't seem to be very useful to have %hi(constant).
696 We would be better off by doing the masking ourselves and then putting
697 the explicit high part of the constant in the RTL. This will give better
698 optimization. Also, %hi(constant) needs assembler changes to work.
699 There is already a define_split that does this. */
700
701 int
702 mips_check_split (address, mode)
703 rtx address;
704 enum machine_mode mode;
705 {
706 /* ??? This is the same check used in simple_memory_operand.
707 We use it here because LO_SUM is not offsettable. */
708 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
709 return 0;
710
711 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
712 || (GET_CODE (address) == CONST
713 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
714 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
715 || GET_CODE (address) == LABEL_REF)
716 return 1;
717
718 return 0;
719 }
720 \f
721 /* Returns an operand string for the given instruction's delay slot,
722 after updating filled delay slot statistics.
723
724 We assume that operands[0] is the target register that is set.
725
726 In order to check the next insn, most of this functionality is moved
727 to FINAL_PRESCAN_INSN, and we just set the global variables that
728 it needs. */
729
730 /* ??? This function no longer does anything useful, because final_prescan_insn
731 now will never emit a nop. */
732
733 char *
734 mips_fill_delay_slot (ret, type, operands, cur_insn)
735 char *ret; /* normal string to return */
736 enum delay_type type; /* type of delay */
737 rtx operands[]; /* operands to use */
738 rtx cur_insn; /* current insn */
739 {
740 register rtx set_reg;
741 register enum machine_mode mode;
742 register rtx next_insn = (cur_insn) ? NEXT_INSN (cur_insn) : (rtx)0;
743 register int num_nops;
744
745 if (type == DELAY_LOAD || type == DELAY_FCMP)
746 num_nops = 1;
747
748 else if (type == DELAY_HILO)
749 num_nops = 2;
750
751 else
752 num_nops = 0;
753
754 /* Make sure that we don't put nop's after labels. */
755 next_insn = NEXT_INSN (cur_insn);
756 while (next_insn != (rtx)0 && GET_CODE (next_insn) == NOTE)
757 next_insn = NEXT_INSN (next_insn);
758
759 dslots_load_total += num_nops;
760 if (TARGET_DEBUG_F_MODE
761 || !optimize
762 || type == DELAY_NONE
763 || operands == (rtx *)0
764 || cur_insn == (rtx)0
765 || next_insn == (rtx)0
766 || GET_CODE (next_insn) == CODE_LABEL
767 || (set_reg = operands[0]) == (rtx)0)
768 {
769 dslots_number_nops = 0;
770 mips_load_reg = (rtx)0;
771 mips_load_reg2 = (rtx)0;
772 mips_load_reg3 = (rtx)0;
773 mips_load_reg4 = (rtx)0;
774 return ret;
775 }
776
777 set_reg = operands[0];
778 if (set_reg == (rtx)0)
779 return ret;
780
781 while (GET_CODE (set_reg) == SUBREG)
782 set_reg = SUBREG_REG (set_reg);
783
784 mode = GET_MODE (set_reg);
785 dslots_number_nops = num_nops;
786 mips_load_reg = set_reg;
787 if (GET_MODE_SIZE (mode)
788 > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
789 mips_load_reg2 = gen_rtx (REG, SImode, REGNO (set_reg) + 1);
790 else
791 mips_load_reg2 = 0;
792
793 if (type == DELAY_HILO)
794 {
795 mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST);
796 mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1);
797 }
798 else
799 {
800 mips_load_reg3 = 0;
801 mips_load_reg4 = 0;
802 }
803
804 return ret;
805 }
806
807 \f
808 /* Determine whether a memory reference takes one (based off of the GP pointer),
809 two (normal), or three (label + reg) instructions, and bump the appropriate
810 counter for -mstats. */
811
812 void
813 mips_count_memory_refs (op, num)
814 rtx op;
815 int num;
816 {
817 int additional = 0;
818 int n_words = 0;
819 rtx addr, plus0, plus1;
820 enum rtx_code code0, code1;
821 int looping;
822
823 if (TARGET_DEBUG_B_MODE)
824 {
825 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
826 debug_rtx (op);
827 }
828
829 /* Skip MEM if passed, otherwise handle movsi of address. */
830 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
831
832 /* Loop, going through the address RTL */
833 do
834 {
835 looping = FALSE;
836 switch (GET_CODE (addr))
837 {
838 default:
839 break;
840
841 case REG:
842 case CONST_INT:
843 case LO_SUM:
844 break;
845
846 case PLUS:
847 plus0 = XEXP (addr, 0);
848 plus1 = XEXP (addr, 1);
849 code0 = GET_CODE (plus0);
850 code1 = GET_CODE (plus1);
851
852 if (code0 == REG)
853 {
854 additional++;
855 addr = plus1;
856 looping = TRUE;
857 continue;
858 }
859
860 if (code0 == CONST_INT)
861 {
862 addr = plus1;
863 looping = TRUE;
864 continue;
865 }
866
867 if (code1 == REG)
868 {
869 additional++;
870 addr = plus0;
871 looping = TRUE;
872 continue;
873 }
874
875 if (code1 == CONST_INT)
876 {
877 addr = plus0;
878 looping = TRUE;
879 continue;
880 }
881
882 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
883 {
884 addr = plus0;
885 looping = TRUE;
886 continue;
887 }
888
889 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
890 {
891 addr = plus1;
892 looping = TRUE;
893 continue;
894 }
895
896 break;
897
898 case LABEL_REF:
899 n_words = 2; /* always 2 words */
900 break;
901
902 case CONST:
903 addr = XEXP (addr, 0);
904 looping = TRUE;
905 continue;
906
907 case SYMBOL_REF:
908 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
909 break;
910 }
911 }
912 while (looping);
913
914 if (n_words == 0)
915 return;
916
917 n_words += additional;
918 if (n_words > 3)
919 n_words = 3;
920
921 num_refs[n_words-1] += num;
922 }
923
924 \f
925 /* Return RTL for the offset from the current function to the
926 argument. */
927
928 rtx
929 embedded_pic_offset (x)
930 rtx x;
931 {
932 if (embedded_pic_fnaddr_rtx == NULL)
933 {
934 rtx seq;
935
936 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
937
938 /* Output code at function start to initialize the pseudo-reg. */
939 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
940 inline functions, because it is called after RTL for the function
941 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
942 does not get copied, and ends up not matching the rest of the RTL.
943 This solution works, but means that we get unnecessary code to
944 initialize this value every time a function is inlined into another
945 function. */
946 start_sequence ();
947 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
948 XEXP (DECL_RTL (current_function_decl), 0)));
949 seq = gen_sequence ();
950 end_sequence ();
951 push_topmost_sequence ();
952 emit_insn_after (seq, get_insns ());
953 pop_topmost_sequence ();
954 }
955
956 return gen_rtx (CONST, Pmode,
957 gen_rtx (MINUS, Pmode, x,
958 XEXP (DECL_RTL (current_function_decl), 0)));
959 }
960
961 /* Return the appropriate instructions to move one operand to another. */
962
963 char *
964 mips_move_1word (operands, insn, unsignedp)
965 rtx operands[];
966 rtx insn;
967 int unsignedp;
968 {
969 char *ret = 0;
970 rtx op0 = operands[0];
971 rtx op1 = operands[1];
972 enum rtx_code code0 = GET_CODE (op0);
973 enum rtx_code code1 = GET_CODE (op1);
974 enum machine_mode mode = GET_MODE (op0);
975 int subreg_word0 = 0;
976 int subreg_word1 = 0;
977 enum delay_type delay = DELAY_NONE;
978
979 while (code0 == SUBREG)
980 {
981 subreg_word0 += SUBREG_WORD (op0);
982 op0 = SUBREG_REG (op0);
983 code0 = GET_CODE (op0);
984 }
985
986 while (code1 == SUBREG)
987 {
988 subreg_word1 += SUBREG_WORD (op1);
989 op1 = SUBREG_REG (op1);
990 code1 = GET_CODE (op1);
991 }
992
993 if (code0 == REG)
994 {
995 int regno0 = REGNO (op0) + subreg_word0;
996
997 if (code1 == REG)
998 {
999 int regno1 = REGNO (op1) + subreg_word1;
1000
1001 /* Just in case, don't do anything for assigning a register
1002 to itself, unless we are filling a delay slot. */
1003 if (regno0 == regno1 && set_nomacro == 0)
1004 ret = "";
1005
1006 else if (GP_REG_P (regno0))
1007 {
1008 if (GP_REG_P (regno1))
1009 ret = "move\t%0,%1";
1010
1011 else if (MD_REG_P (regno1))
1012 {
1013 delay = DELAY_HILO;
1014 if (regno1 != HILO_REGNUM)
1015 ret = "mf%1\t%0";
1016 else
1017 ret = "mflo\t%0";
1018 }
1019
1020 else
1021 {
1022 delay = DELAY_LOAD;
1023 if (FP_REG_P (regno1))
1024 ret = "mfc1\t%0,%1";
1025
1026 else if (regno1 == FPSW_REGNUM)
1027 ret = "cfc1\t%0,$31";
1028 }
1029 }
1030
1031 else if (FP_REG_P (regno0))
1032 {
1033 if (GP_REG_P (regno1))
1034 {
1035 delay = DELAY_LOAD;
1036 ret = "mtc1\t%1,%0";
1037 }
1038
1039 if (FP_REG_P (regno1))
1040 ret = "mov.s\t%0,%1";
1041 }
1042
1043 else if (MD_REG_P (regno0))
1044 {
1045 if (GP_REG_P (regno1))
1046 {
1047 delay = DELAY_HILO;
1048 if (regno0 != HILO_REGNUM)
1049 ret = "mt%0\t%1";
1050 }
1051 }
1052
1053 else if (regno0 == FPSW_REGNUM)
1054 {
1055 if (GP_REG_P (regno1))
1056 {
1057 delay = DELAY_LOAD;
1058 ret = "ctc1\t%0,$31";
1059 }
1060 }
1061 }
1062
1063 else if (code1 == MEM)
1064 {
1065 delay = DELAY_LOAD;
1066
1067 if (TARGET_STATS)
1068 mips_count_memory_refs (op1, 1);
1069
1070 if (GP_REG_P (regno0))
1071 {
1072 /* For loads, use the mode of the memory item, instead of the
1073 target, so zero/sign extend can use this code as well. */
1074 switch (GET_MODE (op1))
1075 {
1076 default:
1077 break;
1078 case SFmode:
1079 ret = "lw\t%0,%1";
1080 break;
1081 case SImode:
1082 ret = ((unsignedp && TARGET_64BIT)
1083 ? "lwu\t%0,%1"
1084 : "lw\t%0,%1");
1085 break;
1086 case HImode:
1087 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1088 break;
1089 case QImode:
1090 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1091 break;
1092 }
1093 }
1094
1095 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1096 ret = "l.s\t%0,%1";
1097
1098 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1099 {
1100 int i = strlen (ret);
1101 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1102 abort ();
1103
1104 sprintf (volatile_buffer, "%%{%s%%}", ret);
1105 ret = volatile_buffer;
1106 }
1107 }
1108
1109 else if (code1 == CONST_INT
1110 || (code1 == CONST_DOUBLE
1111 && GET_MODE (op1) == VOIDmode))
1112 {
1113 if (code1 == CONST_DOUBLE)
1114 {
1115 /* This can happen when storing constants into long long
1116 bitfields. Just store the least significant word of
1117 the value. */
1118 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1119 }
1120
1121 if (INTVAL (op1) == 0)
1122 {
1123 if (GP_REG_P (regno0))
1124 ret = "move\t%0,%z1";
1125
1126 else if (FP_REG_P (regno0))
1127 {
1128 delay = DELAY_LOAD;
1129 ret = "mtc1\t%z1,%0";
1130 }
1131
1132 else if (MD_REG_P (regno0))
1133 {
1134 delay = DELAY_HILO;
1135 ret = "mt%0\t%.";
1136 }
1137 }
1138
1139 else if (GP_REG_P (regno0))
1140 /* Don't use X format, because that will give out of range
1141 numbers for 64 bit host and 32 bit target. */
1142 ret = "li\t%0,%1\t\t\t# %X1";
1143 }
1144
1145 else if (code1 == CONST_DOUBLE && mode == SFmode)
1146 {
1147 if (op1 == CONST0_RTX (SFmode))
1148 {
1149 if (GP_REG_P (regno0))
1150 ret = "move\t%0,%.";
1151
1152 else if (FP_REG_P (regno0))
1153 {
1154 delay = DELAY_LOAD;
1155 ret = "mtc1\t%.,%0";
1156 }
1157 }
1158
1159 else
1160 {
1161 delay = DELAY_LOAD;
1162 ret = "li.s\t%0,%1";
1163 }
1164 }
1165
1166 else if (code1 == LABEL_REF)
1167 {
1168 if (TARGET_STATS)
1169 mips_count_memory_refs (op1, 1);
1170
1171 ret = "la\t%0,%a1";
1172 }
1173
1174 else if (code1 == SYMBOL_REF || code1 == CONST)
1175 {
1176 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
1177 {
1178 rtx offset = const0_rtx;
1179
1180 if (GET_CODE (op1) == CONST)
1181 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
1182
1183 if (GET_CODE (op1) == SYMBOL_REF)
1184 {
1185 operands[2] = HALF_PIC_PTR (op1);
1186
1187 if (TARGET_STATS)
1188 mips_count_memory_refs (operands[2], 1);
1189
1190 if (INTVAL (offset) == 0)
1191 {
1192 delay = DELAY_LOAD;
1193 ret = (unsignedp && TARGET_64BIT
1194 ? "lwu\t%0,%2"
1195 : "lw\t%0,%2");
1196 }
1197 else
1198 {
1199 dslots_load_total++;
1200 operands[3] = offset;
1201 if (unsignedp && TARGET_64BIT)
1202 ret = (SMALL_INT (offset))
1203 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1204 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1205 else
1206 ret = (SMALL_INT (offset))
1207 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1208 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1209 }
1210 }
1211 }
1212 else
1213 {
1214 if (TARGET_STATS)
1215 mips_count_memory_refs (op1, 1);
1216
1217 ret = "la\t%0,%a1";
1218 }
1219 }
1220
1221 else if (code1 == PLUS)
1222 {
1223 rtx add_op0 = XEXP (op1, 0);
1224 rtx add_op1 = XEXP (op1, 1);
1225
1226 if (GET_CODE (XEXP (op1, 1)) == REG && GET_CODE (XEXP (op1, 0)) == CONST_INT)
1227 {
1228 add_op0 = XEXP (op1, 1); /* reverse operands */
1229 add_op1 = XEXP (op1, 0);
1230 }
1231
1232 operands[2] = add_op0;
1233 operands[3] = add_op1;
1234 ret = "add%:\t%0,%2,%3";
1235 }
1236
1237 else if (code1 == HIGH)
1238 {
1239 operands[1] = XEXP (op1, 0);
1240 ret = "lui\t%0,%%hi(%1)";
1241 }
1242 }
1243
1244 else if (code0 == MEM)
1245 {
1246 if (TARGET_STATS)
1247 mips_count_memory_refs (op0, 1);
1248
1249 if (code1 == REG)
1250 {
1251 int regno1 = REGNO (op1) + subreg_word1;
1252
1253 if (GP_REG_P (regno1))
1254 {
1255 switch (mode)
1256 {
1257 default: break;
1258 case SFmode: ret = "sw\t%1,%0"; break;
1259 case SImode: ret = "sw\t%1,%0"; break;
1260 case HImode: ret = "sh\t%1,%0"; break;
1261 case QImode: ret = "sb\t%1,%0"; break;
1262 }
1263 }
1264
1265 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
1266 ret = "s.s\t%1,%0";
1267 }
1268
1269 else if (code1 == CONST_INT && INTVAL (op1) == 0)
1270 {
1271 switch (mode)
1272 {
1273 default: break;
1274 case SFmode: ret = "sw\t%z1,%0"; break;
1275 case SImode: ret = "sw\t%z1,%0"; break;
1276 case HImode: ret = "sh\t%z1,%0"; break;
1277 case QImode: ret = "sb\t%z1,%0"; break;
1278 }
1279 }
1280
1281 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
1282 {
1283 switch (mode)
1284 {
1285 default: break;
1286 case SFmode: ret = "sw\t%.,%0"; break;
1287 case SImode: ret = "sw\t%.,%0"; break;
1288 case HImode: ret = "sh\t%.,%0"; break;
1289 case QImode: ret = "sb\t%.,%0"; break;
1290 }
1291 }
1292
1293 if (ret != (char *)0 && MEM_VOLATILE_P (op0))
1294 {
1295 int i = strlen (ret);
1296 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1297 abort ();
1298
1299 sprintf (volatile_buffer, "%%{%s%%}", ret);
1300 ret = volatile_buffer;
1301 }
1302 }
1303
1304 if (ret == (char *)0)
1305 {
1306 abort_with_insn (insn, "Bad move");
1307 return 0;
1308 }
1309
1310 if (delay != DELAY_NONE)
1311 return mips_fill_delay_slot (ret, delay, operands, insn);
1312
1313 return ret;
1314 }
1315
1316 \f
1317 /* Return the appropriate instructions to move 2 words */
1318
1319 char *
1320 mips_move_2words (operands, insn)
1321 rtx operands[];
1322 rtx insn;
1323 {
1324 char *ret = 0;
1325 rtx op0 = operands[0];
1326 rtx op1 = operands[1];
1327 enum rtx_code code0 = GET_CODE (operands[0]);
1328 enum rtx_code code1 = GET_CODE (operands[1]);
1329 int subreg_word0 = 0;
1330 int subreg_word1 = 0;
1331 enum delay_type delay = DELAY_NONE;
1332
1333 while (code0 == SUBREG)
1334 {
1335 subreg_word0 += SUBREG_WORD (op0);
1336 op0 = SUBREG_REG (op0);
1337 code0 = GET_CODE (op0);
1338 }
1339
1340 while (code1 == SUBREG)
1341 {
1342 subreg_word1 += SUBREG_WORD (op1);
1343 op1 = SUBREG_REG (op1);
1344 code1 = GET_CODE (op1);
1345 }
1346
1347 if (code0 == REG)
1348 {
1349 int regno0 = REGNO (op0) + subreg_word0;
1350
1351 if (code1 == REG)
1352 {
1353 int regno1 = REGNO (op1) + subreg_word1;
1354
1355 /* Just in case, don't do anything for assigning a register
1356 to itself, unless we are filling a delay slot. */
1357 if (regno0 == regno1 && set_nomacro == 0)
1358 ret = "";
1359
1360 else if (FP_REG_P (regno0))
1361 {
1362 if (FP_REG_P (regno1))
1363 ret = "mov.d\t%0,%1";
1364
1365 else
1366 {
1367 delay = DELAY_LOAD;
1368 if (TARGET_FLOAT64)
1369 {
1370 if (!TARGET_64BIT)
1371 abort_with_insn (insn, "Bad move");
1372 #ifdef TARGET_FP_CALL_32
1373 if (FP_CALL_GP_REG_P (regno1))
1374 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1375 else
1376 #endif
1377 ret = "dmtc1\t%1,%0";
1378 }
1379 else
1380 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1381 }
1382 }
1383
1384 else if (FP_REG_P (regno1))
1385 {
1386 delay = DELAY_LOAD;
1387 if (TARGET_FLOAT64)
1388 {
1389 if (!TARGET_64BIT)
1390 abort_with_insn (insn, "Bad move");
1391 #ifdef TARGET_FP_CALL_32
1392 if (FP_CALL_GP_REG_P (regno0))
1393 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1394 else
1395 #endif
1396 ret = "dmfc1\t%0,%1";
1397 }
1398 else
1399 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1400 }
1401
1402 else if (MD_REG_P (regno0) && GP_REG_P (regno1))
1403 {
1404 delay = DELAY_HILO;
1405 if (TARGET_64BIT)
1406 {
1407 if (regno0 != HILO_REGNUM)
1408 ret = "mt%0\t%1";
1409 else if (regno1 == 0)
1410 ret = "mtlo\t%.\n\tmthi\t%.";
1411 }
1412 else
1413 ret = "mthi\t%M1\n\tmtlo\t%L1";
1414 }
1415
1416 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
1417 {
1418 delay = DELAY_HILO;
1419 if (TARGET_64BIT)
1420 {
1421 if (regno1 != HILO_REGNUM)
1422 ret = "mf%1\t%0";
1423 }
1424 else
1425 ret = "mfhi\t%M0\n\tmflo\t%L0";
1426 }
1427
1428 else if (TARGET_64BIT)
1429 ret = "move\t%0,%1";
1430
1431 else if (regno0 != (regno1+1))
1432 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
1433
1434 else
1435 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
1436 }
1437
1438 else if (code1 == CONST_DOUBLE)
1439 {
1440 /* Move zero from $0 unless !TARGET_64BIT and recipient
1441 is 64-bit fp reg, in which case generate a constant. */
1442 if (op1 != CONST0_RTX (GET_MODE (op1))
1443 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
1444 {
1445 if (GET_MODE (op1) == DFmode)
1446 {
1447 delay = DELAY_LOAD;
1448 #ifdef TARGET_FP_CALL_32
1449 if (FP_CALL_GP_REG_P (regno0))
1450 {
1451 if (TARGET_FLOAT64 && !TARGET_64BIT)
1452 {
1453 split_double (op1, operands + 2, operands + 3);
1454 ret = "li\t%0,%2\n\tli\t%D0,%3";
1455 }
1456 else
1457 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1458 }
1459 else
1460 #endif
1461 ret = "li.d\t%0,%1";
1462 }
1463
1464 else if (TARGET_64BIT)
1465 ret = "dli\t%0,%1";
1466
1467 else
1468 {
1469 split_double (op1, operands + 2, operands + 3);
1470 ret = "li\t%0,%2\n\tli\t%D0,%3";
1471 }
1472 }
1473
1474 else
1475 {
1476 if (GP_REG_P (regno0))
1477 ret = (TARGET_64BIT
1478 #ifdef TARGET_FP_CALL_32
1479 && ! FP_CALL_GP_REG_P (regno0)
1480 #endif
1481 )
1482 ? "move\t%0,%."
1483 : "move\t%0,%.\n\tmove\t%D0,%.";
1484
1485 else if (FP_REG_P (regno0))
1486 {
1487 delay = DELAY_LOAD;
1488 ret = (TARGET_64BIT)
1489 ? "dmtc1\t%.,%0"
1490 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1491 }
1492 }
1493 }
1494
1495 else if (code1 == CONST_INT && INTVAL (op1) == 0)
1496 {
1497 if (GP_REG_P (regno0))
1498 ret = (TARGET_64BIT)
1499 ? "move\t%0,%."
1500 : "move\t%0,%.\n\tmove\t%D0,%.";
1501
1502 else if (FP_REG_P (regno0))
1503 {
1504 delay = DELAY_LOAD;
1505 ret = (TARGET_64BIT)
1506 ? "dmtc1\t%.,%0"
1507 : (TARGET_FLOAT64
1508 ? "li.d\t%0,%1"
1509 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1510 }
1511 else if (MD_REG_P (regno0))
1512 {
1513 delay = DELAY_HILO;
1514 if (regno0 != HILO_REGNUM)
1515 ret = "mt%0\t%.\n";
1516 else
1517 ret = "mtlo\t%.\n\tmthi\t%.";
1518 }
1519 }
1520
1521 else if (code1 == CONST_INT && GET_MODE (op0) == DImode && GP_REG_P (regno0))
1522 {
1523 if (TARGET_64BIT)
1524 {
1525 if (HOST_BITS_PER_WIDE_INT < 64)
1526 /* We can't use 'X' for negative numbers, because then we won't
1527 get the right value for the upper 32 bits. */
1528 ret = ((INTVAL (op1) < 0) ? "dli\t%0,%1\t\t\t# %X1"
1529 : "dli\t%0,%X1\t\t# %1");
1530 else
1531 /* We must use 'X', because otherwise LONG_MIN will print as
1532 a number that the assembler won't accept. */
1533 ret = "dli\t%0,%X1\t\t# %1";
1534 }
1535 else if (HOST_BITS_PER_WIDE_INT < 64)
1536 {
1537 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
1538 ret = "li\t%M0,%2\n\tli\t%L0,%1";
1539 }
1540 else
1541 {
1542 operands[2] = GEN_INT (INTVAL (operands[1]) >> 32);
1543 operands[1] = GEN_INT (INTVAL (operands[1]) << 32 >> 32);
1544 ret = "li\t%M0,%2\n\tli\t%L0,%1";
1545 }
1546 }
1547
1548 else if (code1 == MEM)
1549 {
1550 delay = DELAY_LOAD;
1551
1552 if (TARGET_STATS)
1553 mips_count_memory_refs (op1, 2);
1554
1555 if (FP_REG_P (regno0))
1556 ret = "l.d\t%0,%1";
1557
1558 else if (TARGET_64BIT)
1559 {
1560 #ifdef TARGET_FP_CALL_32
1561 if (FP_CALL_GP_REG_P (regno0))
1562 {
1563 if (offsettable_address_p (FALSE, SImode, op1))
1564 ret = "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1565 else
1566 ret = "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1567 }
1568 else
1569 #endif
1570 ret = "ld\t%0,%1";
1571 }
1572
1573 else if (offsettable_address_p (1, DFmode, XEXP (op1, 0)))
1574 {
1575 operands[2] = adj_offsettable_operand (op1, 4);
1576 if (reg_mentioned_p (op0, op1))
1577 ret = "lw\t%D0,%2\n\tlw\t%0,%1";
1578 else
1579 ret = "lw\t%0,%1\n\tlw\t%D0,%2";
1580 }
1581
1582 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1583 {
1584 int i = strlen (ret);
1585 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1586 abort ();
1587
1588 sprintf (volatile_buffer, "%%{%s%%}", ret);
1589 ret = volatile_buffer;
1590 }
1591 }
1592
1593 else if (code1 == LABEL_REF
1594 || code1 == SYMBOL_REF
1595 || code1 == CONST)
1596 {
1597 if (TARGET_STATS)
1598 mips_count_memory_refs (op1, 2);
1599
1600 ret = "dla\t%0,%a1";
1601 }
1602 }
1603
1604 else if (code0 == MEM)
1605 {
1606 if (code1 == REG)
1607 {
1608 int regno1 = REGNO (op1) + subreg_word1;
1609
1610 if (FP_REG_P (regno1))
1611 ret = "s.d\t%1,%0";
1612
1613 else if (TARGET_64BIT)
1614 {
1615 #ifdef TARGET_FP_CALL_32
1616 if (FP_CALL_GP_REG_P (regno1))
1617 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1618 else
1619 #endif
1620 ret = "sd\t%1,%0";
1621 }
1622
1623 else if (offsettable_address_p (1, DFmode, XEXP (op0, 0)))
1624 {
1625 operands[2] = adj_offsettable_operand (op0, 4);
1626 ret = "sw\t%1,%0\n\tsw\t%D1,%2";
1627 }
1628 }
1629
1630 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
1631 || (code1 == CONST_DOUBLE
1632 && op1 == CONST0_RTX (GET_MODE (op1))))
1633 && (TARGET_64BIT
1634 || offsettable_address_p (1, DFmode, XEXP (op0, 0))))
1635 {
1636 if (TARGET_64BIT)
1637 ret = "sd\t%.,%0";
1638 else
1639 {
1640 operands[2] = adj_offsettable_operand (op0, 4);
1641 ret = "sw\t%.,%0\n\tsw\t%.,%2";
1642 }
1643 }
1644
1645 if (TARGET_STATS)
1646 mips_count_memory_refs (op0, 2);
1647
1648 if (ret != (char *)0 && MEM_VOLATILE_P (op0))
1649 {
1650 int i = strlen (ret);
1651 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1652 abort ();
1653
1654 sprintf (volatile_buffer, "%%{%s%%}", ret);
1655 ret = volatile_buffer;
1656 }
1657 }
1658
1659 if (ret == (char *)0)
1660 {
1661 abort_with_insn (insn, "Bad move");
1662 return 0;
1663 }
1664
1665 if (delay != DELAY_NONE)
1666 return mips_fill_delay_slot (ret, delay, operands, insn);
1667
1668 return ret;
1669 }
1670
1671 \f
1672 /* Provide the costs of an addressing mode that contains ADDR.
1673 If ADDR is not a valid address, its cost is irrelevant. */
1674
1675 int
1676 mips_address_cost (addr)
1677 rtx addr;
1678 {
1679 switch (GET_CODE (addr))
1680 {
1681 default:
1682 break;
1683
1684 case LO_SUM:
1685 return 1;
1686
1687 case LABEL_REF:
1688 return 2;
1689
1690 case CONST:
1691 {
1692 rtx offset = const0_rtx;
1693 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
1694 if (GET_CODE (addr) == LABEL_REF)
1695 return 2;
1696
1697 if (GET_CODE (addr) != SYMBOL_REF)
1698 return 4;
1699
1700 if (! SMALL_INT (offset))
1701 return 2;
1702 }
1703 /* fall through */
1704
1705 case SYMBOL_REF:
1706 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
1707
1708 case PLUS:
1709 {
1710 register rtx plus0 = XEXP (addr, 0);
1711 register rtx plus1 = XEXP (addr, 1);
1712
1713 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1714 {
1715 plus0 = XEXP (addr, 1);
1716 plus1 = XEXP (addr, 0);
1717 }
1718
1719 if (GET_CODE (plus0) != REG)
1720 break;
1721
1722 switch (GET_CODE (plus1))
1723 {
1724 default:
1725 break;
1726
1727 case CONST_INT:
1728 return (SMALL_INT (plus1) ? 1 : 2);
1729
1730 case CONST:
1731 case SYMBOL_REF:
1732 case LABEL_REF:
1733 case HIGH:
1734 case LO_SUM:
1735 return mips_address_cost (plus1) + 1;
1736 }
1737 }
1738 }
1739
1740 return 4;
1741 }
1742
1743 /* Return true if X is an address which needs a temporary register when
1744 reloaded while generating PIC code. */
1745
1746 int
1747 pic_address_needs_scratch (x)
1748 rtx x;
1749 {
1750 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1751 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
1752 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1753 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1754 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
1755 return 1;
1756
1757 return 0;
1758 }
1759 \f
1760 /* Make normal rtx_code into something we can index from an array */
1761
1762 static enum internal_test
1763 map_test_to_internal_test (test_code)
1764 enum rtx_code test_code;
1765 {
1766 enum internal_test test = ITEST_MAX;
1767
1768 switch (test_code)
1769 {
1770 default: break;
1771 case EQ: test = ITEST_EQ; break;
1772 case NE: test = ITEST_NE; break;
1773 case GT: test = ITEST_GT; break;
1774 case GE: test = ITEST_GE; break;
1775 case LT: test = ITEST_LT; break;
1776 case LE: test = ITEST_LE; break;
1777 case GTU: test = ITEST_GTU; break;
1778 case GEU: test = ITEST_GEU; break;
1779 case LTU: test = ITEST_LTU; break;
1780 case LEU: test = ITEST_LEU; break;
1781 }
1782
1783 return test;
1784 }
1785
1786 \f
1787 /* Generate the code to compare two integer values. The return value is:
1788 (reg:SI xx) The pseudo register the comparison is in
1789 (rtx)0 No register, generate a simple branch.
1790
1791 ??? This is called with result nonzero by the Scond patterns in
1792 mips.md. These patterns are called with a target in the mode of
1793 the Scond instruction pattern. Since this must be a constant, we
1794 must use SImode. This means that if RESULT is non-zero, it will
1795 always be an SImode register, even if TARGET_64BIT is true. We
1796 cope with this by calling convert_move rather than emit_move_insn.
1797 This will sometimes lead to an unnecessary extension of the result;
1798 for example:
1799
1800 long long
1801 foo (long long i)
1802 {
1803 return i < 5;
1804 }
1805
1806 */
1807
1808 rtx
1809 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
1810 enum rtx_code test_code; /* relational test (EQ, etc) */
1811 rtx result; /* result to store comp. or 0 if branch */
1812 rtx cmp0; /* first operand to compare */
1813 rtx cmp1; /* second operand to compare */
1814 int *p_invert; /* NULL or ptr to hold whether branch needs */
1815 /* to reverse its test */
1816 {
1817 struct cmp_info {
1818 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
1819 int const_low; /* low bound of constant we can accept */
1820 int const_high; /* high bound of constant we can accept */
1821 int const_add; /* constant to add (convert LE -> LT) */
1822 int reverse_regs; /* reverse registers in test */
1823 int invert_const; /* != 0 if invert value if cmp1 is constant */
1824 int invert_reg; /* != 0 if invert value if cmp1 is register */
1825 int unsignedp; /* != 0 for unsigned comparisons. */
1826 };
1827
1828 static struct cmp_info info[ (int)ITEST_MAX ] = {
1829
1830 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
1831 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
1832 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
1833 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
1834 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
1835 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
1836 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
1837 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
1838 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
1839 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
1840 };
1841
1842 enum internal_test test;
1843 enum machine_mode mode;
1844 struct cmp_info *p_info;
1845 int branch_p;
1846 int eqne_p;
1847 int invert;
1848 rtx reg;
1849 rtx reg2;
1850
1851 test = map_test_to_internal_test (test_code);
1852 if (test == ITEST_MAX)
1853 abort ();
1854
1855 p_info = &info[ (int)test ];
1856 eqne_p = (p_info->test_code == XOR);
1857
1858 mode = GET_MODE (cmp0);
1859 if (mode == VOIDmode)
1860 mode = GET_MODE (cmp1);
1861
1862 /* Eliminate simple branches */
1863 branch_p = (result == (rtx)0);
1864 if (branch_p)
1865 {
1866 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
1867 {
1868 /* Comparisons against zero are simple branches */
1869 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
1870 return (rtx)0;
1871
1872 /* Test for beq/bne. */
1873 if (eqne_p)
1874 return (rtx)0;
1875 }
1876
1877 /* allocate a pseudo to calculate the value in. */
1878 result = gen_reg_rtx (mode);
1879 }
1880
1881 /* Make sure we can handle any constants given to us. */
1882 if (GET_CODE (cmp0) == CONST_INT)
1883 cmp0 = force_reg (mode, cmp0);
1884
1885 if (GET_CODE (cmp1) == CONST_INT)
1886 {
1887 HOST_WIDE_INT value = INTVAL (cmp1);
1888 if (value < p_info->const_low
1889 || value > p_info->const_high
1890 /* ??? Why? And why wasn't the similar code below modified too? */
1891 || (TARGET_64BIT
1892 && HOST_BITS_PER_WIDE_INT < 64
1893 && p_info->const_add != 0
1894 && ((p_info->unsignedp
1895 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
1896 > INTVAL (cmp1))
1897 : (value + p_info->const_add) > INTVAL (cmp1))
1898 != (p_info->const_add > 0))))
1899 cmp1 = force_reg (mode, cmp1);
1900 }
1901
1902 /* See if we need to invert the result. */
1903 invert = (GET_CODE (cmp1) == CONST_INT)
1904 ? p_info->invert_const
1905 : p_info->invert_reg;
1906
1907 if (p_invert != (int *)0)
1908 {
1909 *p_invert = invert;
1910 invert = FALSE;
1911 }
1912
1913 /* Comparison to constants, may involve adding 1 to change a LT into LE.
1914 Comparison between two registers, may involve switching operands. */
1915 if (GET_CODE (cmp1) == CONST_INT)
1916 {
1917 if (p_info->const_add != 0)
1918 {
1919 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
1920 /* If modification of cmp1 caused overflow,
1921 we would get the wrong answer if we follow the usual path;
1922 thus, x > 0xffffffffU would turn into x > 0U. */
1923 if ((p_info->unsignedp
1924 ? (unsigned HOST_WIDE_INT) new > INTVAL (cmp1)
1925 : new > INTVAL (cmp1))
1926 != (p_info->const_add > 0))
1927 {
1928 /* This test is always true, but if INVERT is true then
1929 the result of the test needs to be inverted so 0 should
1930 be returned instead. */
1931 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
1932 return result;
1933 }
1934 else
1935 cmp1 = GEN_INT (new);
1936 }
1937 }
1938 else if (p_info->reverse_regs)
1939 {
1940 rtx temp = cmp0;
1941 cmp0 = cmp1;
1942 cmp1 = temp;
1943 }
1944
1945 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
1946 reg = cmp0;
1947 else
1948 {
1949 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
1950 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
1951 }
1952
1953 if (test == ITEST_NE)
1954 {
1955 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
1956 invert = FALSE;
1957 }
1958
1959 else if (test == ITEST_EQ)
1960 {
1961 reg2 = (invert) ? gen_reg_rtx (mode) : result;
1962 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
1963 reg = reg2;
1964 }
1965
1966 if (invert)
1967 convert_move (result, gen_rtx (XOR, mode, reg, const1_rtx), 0);
1968
1969 return result;
1970 }
1971
1972 \f
1973 /* Emit the common code for doing conditional branches.
1974 operand[0] is the label to jump to.
1975 The comparison operands are saved away by cmp{si,di,sf,df}. */
1976
1977 void
1978 gen_conditional_branch (operands, test_code)
1979 rtx operands[];
1980 enum rtx_code test_code;
1981 {
1982 static enum machine_mode mode_map[(int)CMP_MAX][(int)ITEST_MAX] = {
1983 { /* CMP_SI */
1984 SImode, /* eq */
1985 SImode, /* ne */
1986 SImode, /* gt */
1987 SImode, /* ge */
1988 SImode, /* lt */
1989 SImode, /* le */
1990 SImode, /* gtu */
1991 SImode, /* geu */
1992 SImode, /* ltu */
1993 SImode, /* leu */
1994 },
1995 { /* CMP_DI */
1996 DImode, /* eq */
1997 DImode, /* ne */
1998 DImode, /* gt */
1999 DImode, /* ge */
2000 DImode, /* lt */
2001 DImode, /* le */
2002 DImode, /* gtu */
2003 DImode, /* geu */
2004 DImode, /* ltu */
2005 DImode, /* leu */
2006 },
2007 { /* CMP_SF */
2008 CC_FPmode, /* eq */
2009 CC_REV_FPmode, /* ne */
2010 CC_FPmode, /* gt */
2011 CC_FPmode, /* ge */
2012 CC_FPmode, /* lt */
2013 CC_FPmode, /* le */
2014 VOIDmode, /* gtu */
2015 VOIDmode, /* geu */
2016 VOIDmode, /* ltu */
2017 VOIDmode, /* leu */
2018 },
2019 { /* CMP_DF */
2020 CC_FPmode, /* eq */
2021 CC_REV_FPmode, /* ne */
2022 CC_FPmode, /* gt */
2023 CC_FPmode, /* ge */
2024 CC_FPmode, /* lt */
2025 CC_FPmode, /* le */
2026 VOIDmode, /* gtu */
2027 VOIDmode, /* geu */
2028 VOIDmode, /* ltu */
2029 VOIDmode, /* leu */
2030 },
2031 };
2032
2033 enum machine_mode mode;
2034 enum cmp_type type = branch_type;
2035 rtx cmp0 = branch_cmp[0];
2036 rtx cmp1 = branch_cmp[1];
2037 rtx label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]);
2038 rtx label2 = pc_rtx;
2039 rtx reg = (rtx)0;
2040 int invert = 0;
2041 enum internal_test test = map_test_to_internal_test (test_code);
2042
2043 if (test == ITEST_MAX)
2044 {
2045 mode = word_mode;
2046 goto fail;
2047 }
2048
2049 /* Get the machine mode to use (CCmode, CC_EQmode, CC_FPmode, or CC_REV_FPmode). */
2050 mode = mode_map[(int)type][(int)test];
2051 if (mode == VOIDmode)
2052 goto fail;
2053
2054 switch (type)
2055 {
2056 default:
2057 goto fail;
2058
2059 case CMP_SI:
2060 case CMP_DI:
2061 reg = gen_int_relational (test_code, (rtx)0, cmp0, cmp1, &invert);
2062 if (reg != (rtx)0)
2063 {
2064 cmp0 = reg;
2065 cmp1 = const0_rtx;
2066 test_code = NE;
2067 }
2068
2069 /* Make sure not non-zero constant if ==/!= */
2070 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
2071 cmp1 = force_reg (mode, cmp1);
2072
2073 break;
2074
2075 case CMP_DF:
2076 case CMP_SF:
2077 {
2078 rtx reg = gen_rtx (REG, mode, FPSW_REGNUM);
2079 emit_insn (gen_rtx (SET, VOIDmode, reg, gen_rtx (test_code, mode, cmp0, cmp1)));
2080 cmp0 = reg;
2081 cmp1 = const0_rtx;
2082 test_code = NE;
2083 }
2084 break;
2085 }
2086
2087 /* Generate the jump */
2088 if (invert)
2089 {
2090 label2 = label1;
2091 label1 = pc_rtx;
2092 }
2093
2094 emit_jump_insn (gen_rtx (SET, VOIDmode,
2095 pc_rtx,
2096 gen_rtx (IF_THEN_ELSE, VOIDmode,
2097 gen_rtx (test_code, mode, cmp0, cmp1),
2098 label1,
2099 label2)));
2100
2101 return;
2102
2103 fail:
2104 abort_with_insn (gen_rtx (test_code, mode, cmp0, cmp1), "bad test");
2105 }
2106
2107 \f
2108 #if 0
2109 /* Internal code to generate the load and store of one word/short/byte.
2110 The load is emitted directly, and the store insn is returned. */
2111
2112 #define UNITS_PER_MIPS_DWORD 8
2113 #define UNITS_PER_MIPS_WORD 4
2114 #define UNITS_PER_MIPS_HWORD 2
2115
2116 static rtx
2117 block_move_load_store (dest_reg, src_reg, p_bytes, p_offset, align, orig_src)
2118 rtx src_reg; /* register holding source memory address */
2119 rtx dest_reg; /* register holding dest. memory address */
2120 int *p_bytes; /* pointer to # bytes remaining */
2121 int *p_offset; /* pointer to current offset */
2122 int align; /* alignment */
2123 rtx orig_src; /* original source for making a reg note */
2124 {
2125 int bytes; /* # bytes remaining */
2126 int offset; /* offset to use */
2127 int size; /* size in bytes of load/store */
2128 enum machine_mode mode; /* mode to use for load/store */
2129 rtx reg; /* temporary register */
2130 rtx src_addr; /* source address */
2131 rtx dest_addr; /* destination address */
2132 rtx insn; /* insn of the load */
2133 rtx orig_src_addr; /* original source address */
2134 rtx (*load_func)(); /* function to generate load insn */
2135 rtx (*store_func)(); /* function to generate destination insn */
2136
2137 bytes = *p_bytes;
2138 if (bytes <= 0 || align <= 0)
2139 abort ();
2140
2141 if (bytes >= UNITS_PER_MIPS_DWORD && align >= UNIS_PER_MIPS_DWORD)
2142 {
2143 mode = DImode;
2144 size = UNITS_PER_MIPS_DWORD;
2145 load_func = gen_movdi;
2146 store_func = gen_movdi;
2147 }
2148 else if (bytes >= UNITS_PER_MIPS_WORD && align >= UNITS_PER_MIPS_WORD)
2149 {
2150 mode = SImode;
2151 size = UNITS_PER_MIPS_WORD;
2152 load_func = gen_movsi;
2153 store_func = gen_movsi;
2154 }
2155
2156 #if 0
2157 /* Don't generate unaligned moves here, rather defer those to the
2158 general movestrsi_internal pattern.
2159 If this gets commented back in, then should add the dword equivalent. */
2160 else if (bytes >= UNITS_PER_MIPS_WORD)
2161 {
2162 mode = SImode;
2163 size = UNITS_PER_MIPS_WORD;
2164 load_func = gen_movsi_ulw;
2165 store_func = gen_movsi_usw;
2166 }
2167 #endif
2168
2169 else if (bytes >= UNITS_PER_MIPS_SHORT && align >= UNITS_PER_MIPS_SHORT)
2170 {
2171 mode = HImode;
2172 size = UNITS_PER_MIPS_SHORT;
2173 load_func = gen_movhi;
2174 store_func = gen_movhi;
2175 }
2176
2177 else
2178 {
2179 mode = QImode;
2180 size = 1;
2181 load_func = gen_movqi;
2182 store_func = gen_movqi;
2183 }
2184
2185 offset = *p_offset;
2186 *p_offset = offset + size;
2187 *p_bytes = bytes - size;
2188
2189 if (offset == 0)
2190 {
2191 src_addr = src_reg;
2192 dest_addr = dest_reg;
2193 }
2194 else
2195 {
2196 src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset));
2197 dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset));
2198 }
2199
2200 reg = gen_reg_rtx (mode);
2201 insn = emit_insn ((*load_func) (reg, gen_rtx (MEM, mode, src_addr)));
2202 orig_src_addr = XEXP (orig_src, 0);
2203 if (CONSTANT_P (orig_src_addr))
2204 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUIV,
2205 plus_constant (orig_src_addr, offset),
2206 REG_NOTES (insn));
2207
2208 return (*store_func) (gen_rtx (MEM, mode, dest_addr), reg);
2209 }
2210 #endif
2211
2212 \f
2213 /* Write a series of loads/stores to move some bytes. Generate load/stores as follows:
2214
2215 load 1
2216 load 2
2217 load 3
2218 store 1
2219 load 4
2220 store 2
2221 load 5
2222 store 3
2223 ...
2224
2225 This way, no NOP's are needed, except at the end, and only
2226 two temp registers are needed. Two delay slots are used
2227 in deference to the R4000. */
2228
2229 #if 0
2230 static void
2231 block_move_sequence (dest_reg, src_reg, bytes, align, orig_src)
2232 rtx dest_reg; /* register holding destination address */
2233 rtx src_reg; /* register holding source address */
2234 int bytes; /* # bytes to move */
2235 int align; /* max alignment to assume */
2236 rtx orig_src; /* original source for making a reg note */
2237 {
2238 int offset = 0;
2239 rtx prev2_store = (rtx)0;
2240 rtx prev_store = (rtx)0;
2241 rtx cur_store = (rtx)0;
2242
2243 while (bytes > 0)
2244 {
2245 /* Is there a store to do? */
2246 if (prev2_store)
2247 emit_insn (prev2_store);
2248
2249 prev2_store = prev_store;
2250 prev_store = cur_store;
2251 cur_store = block_move_load_store (dest_reg, src_reg,
2252 &bytes, &offset,
2253 align, orig_src);
2254 }
2255
2256 /* Finish up last three stores. */
2257 if (prev2_store)
2258 emit_insn (prev2_store);
2259
2260 if (prev_store)
2261 emit_insn (prev_store);
2262
2263 if (cur_store)
2264 emit_insn (cur_store);
2265 }
2266 #endif
2267
2268 \f
2269 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2270
2271 do {
2272 temp1 = src[0];
2273 temp2 = src[1];
2274 ...
2275 temp<last> = src[MAX_MOVE_REGS-1];
2276 dest[0] = temp1;
2277 dest[1] = temp2;
2278 ...
2279 dest[MAX_MOVE_REGS-1] = temp<last>;
2280 src += MAX_MOVE_REGS;
2281 dest += MAX_MOVE_REGS;
2282 } while (src != final);
2283
2284 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2285 registers are needed.
2286
2287 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2288 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2289 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2290
2291 #define MAX_MOVE_REGS 4
2292 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2293
2294 /* ??? Should add code to use DWORD load/stores. */
2295
2296 static void
2297 block_move_loop (dest_reg, src_reg, bytes, align, orig_src)
2298 rtx dest_reg; /* register holding destination address */
2299 rtx src_reg; /* register holding source address */
2300 int bytes; /* # bytes to move */
2301 int align; /* alignment */
2302 rtx orig_src; /* original source for making a reg note */
2303 {
2304 rtx dest_mem = gen_rtx (MEM, BLKmode, dest_reg);
2305 rtx src_mem = gen_rtx (MEM, BLKmode, src_reg);
2306 rtx align_rtx = GEN_INT (align);
2307 rtx label;
2308 rtx final_src;
2309 rtx bytes_rtx;
2310 int leftover;
2311
2312 if (bytes < 2*MAX_MOVE_BYTES)
2313 abort ();
2314
2315 leftover = bytes % MAX_MOVE_BYTES;
2316 bytes -= leftover;
2317
2318 label = gen_label_rtx ();
2319 final_src = gen_reg_rtx (Pmode);
2320 bytes_rtx = GEN_INT (bytes);
2321
2322 if (bytes > 0x7fff)
2323 {
2324 if (TARGET_LONG64)
2325 {
2326 emit_insn (gen_movdi (final_src, bytes_rtx));
2327 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
2328 }
2329 else
2330 {
2331 emit_insn (gen_movsi (final_src, bytes_rtx));
2332 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2333 }
2334 }
2335 else
2336 {
2337 if (TARGET_LONG64)
2338 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
2339 else
2340 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
2341 }
2342
2343 emit_label (label);
2344
2345 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
2346 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
2347 if (TARGET_LONG64)
2348 {
2349 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
2350 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
2351 emit_insn (gen_cmpdi (src_reg, final_src));
2352 }
2353 else
2354 {
2355 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
2356 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
2357 emit_insn (gen_cmpsi (src_reg, final_src));
2358 }
2359 emit_jump_insn (gen_bne (label));
2360
2361 if (leftover)
2362 emit_insn (gen_movstrsi_internal (dest_mem, src_mem,
2363 GEN_INT (leftover),
2364 align_rtx));
2365 }
2366
2367 \f
2368 /* Use a library function to move some bytes. */
2369
2370 static void
2371 block_move_call (dest_reg, src_reg, bytes_rtx)
2372 rtx dest_reg;
2373 rtx src_reg;
2374 rtx bytes_rtx;
2375 {
2376 /* We want to pass the size as Pmode, which will normally be SImode
2377 but will be DImode if we are using 64 bit longs and pointers. */
2378 if (GET_MODE (bytes_rtx) != VOIDmode
2379 && GET_MODE (bytes_rtx) != Pmode)
2380 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, TRUE);
2381
2382 #ifdef TARGET_MEM_FUNCTIONS
2383 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2384 VOIDmode, 3,
2385 dest_reg, Pmode,
2386 src_reg, Pmode,
2387 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2388 TREE_UNSIGNED (sizetype)),
2389 TYPE_MODE (sizetype));
2390 #else
2391 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2392 VOIDmode, 3,
2393 src_reg, Pmode,
2394 dest_reg, Pmode,
2395 convert_to_mode (TYPE_MODE (integer_type_node),
2396 bytes_rtx,
2397 TREE_UNSIGNED (integer_type_node)),
2398 TYPE_MODE (integer_type_node));
2399 #endif
2400 }
2401
2402 \f
2403 /* Expand string/block move operations.
2404
2405 operands[0] is the pointer to the destination.
2406 operands[1] is the pointer to the source.
2407 operands[2] is the number of bytes to move.
2408 operands[3] is the alignment. */
2409
2410 void
2411 expand_block_move (operands)
2412 rtx operands[];
2413 {
2414 rtx bytes_rtx = operands[2];
2415 rtx align_rtx = operands[3];
2416 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2417 int bytes = (constp ? INTVAL (bytes_rtx) : 0);
2418 int align = INTVAL (align_rtx);
2419 rtx orig_src = operands[1];
2420 rtx src_reg;
2421 rtx dest_reg;
2422
2423 if (constp && bytes <= 0)
2424 return;
2425
2426 if (align > UNITS_PER_WORD)
2427 align = UNITS_PER_WORD;
2428
2429 /* Move the address into scratch registers. */
2430 dest_reg = copy_addr_to_reg (XEXP (operands[0], 0));
2431 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2432
2433 if (TARGET_MEMCPY)
2434 block_move_call (dest_reg, src_reg, bytes_rtx);
2435
2436 #if 0
2437 else if (constp && bytes <= 3*align)
2438 block_move_sequence (dest_reg, src_reg, bytes, align, orig_src);
2439 #endif
2440
2441 else if (constp && bytes <= 2*MAX_MOVE_BYTES)
2442 emit_insn (gen_movstrsi_internal (change_address (operands[0],
2443 BLKmode, dest_reg),
2444 change_address (orig_src, BLKmode,
2445 src_reg),
2446 bytes_rtx, align_rtx));
2447
2448 else if (constp && align >= UNITS_PER_WORD && optimize)
2449 block_move_loop (dest_reg, src_reg, bytes, align, orig_src);
2450
2451 else if (constp && optimize)
2452 {
2453 /* If the alignment is not word aligned, generate a test at
2454 runtime, to see whether things wound up aligned, and we
2455 can use the faster lw/sw instead ulw/usw. */
2456
2457 rtx temp = gen_reg_rtx (Pmode);
2458 rtx aligned_label = gen_label_rtx ();
2459 rtx join_label = gen_label_rtx ();
2460 int leftover = bytes % MAX_MOVE_BYTES;
2461
2462 bytes -= leftover;
2463
2464 if (TARGET_LONG64)
2465 {
2466 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
2467 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD-1)));
2468 emit_insn (gen_cmpdi (temp, const0_rtx));
2469 }
2470 else
2471 {
2472 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
2473 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD-1)));
2474 emit_insn (gen_cmpsi (temp, const0_rtx));
2475 }
2476 emit_jump_insn (gen_beq (aligned_label));
2477
2478 /* Unaligned loop. */
2479 block_move_loop (dest_reg, src_reg, bytes, 1, orig_src);
2480 emit_jump_insn (gen_jump (join_label));
2481 emit_barrier ();
2482
2483 /* Aligned loop. */
2484 emit_label (aligned_label);
2485 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_src);
2486 emit_label (join_label);
2487
2488 /* Bytes at the end of the loop. */
2489 if (leftover)
2490 {
2491 #if 0
2492 if (leftover <= 3*align)
2493 block_move_sequence (dest_reg, src_reg, leftover, align, orig_src);
2494
2495 else
2496 #endif
2497 emit_insn (gen_movstrsi_internal (gen_rtx (MEM, BLKmode, dest_reg),
2498 gen_rtx (MEM, BLKmode, src_reg),
2499 GEN_INT (leftover),
2500 GEN_INT (align)));
2501 }
2502 }
2503
2504 else
2505 block_move_call (dest_reg, src_reg, bytes_rtx);
2506 }
2507
2508 \f
2509 /* Emit load/stores for a small constant block_move.
2510
2511 operands[0] is the memory address of the destination.
2512 operands[1] is the memory address of the source.
2513 operands[2] is the number of bytes to move.
2514 operands[3] is the alignment.
2515 operands[4] is a temp register.
2516 operands[5] is a temp register.
2517 ...
2518 operands[3+num_regs] is the last temp register.
2519
2520 The block move type can be one of the following:
2521 BLOCK_MOVE_NORMAL Do all of the block move.
2522 BLOCK_MOVE_NOT_LAST Do all but the last store.
2523 BLOCK_MOVE_LAST Do just the last store. */
2524
2525 char *
2526 output_block_move (insn, operands, num_regs, move_type)
2527 rtx insn;
2528 rtx operands[];
2529 int num_regs;
2530 enum block_move_type move_type;
2531 {
2532 rtx dest_reg = XEXP (operands[0], 0);
2533 rtx src_reg = XEXP (operands[1], 0);
2534 int bytes = INTVAL (operands[2]);
2535 int align = INTVAL (operands[3]);
2536 int num = 0;
2537 int offset = 0;
2538 int use_lwl_lwr = FALSE;
2539 int last_operand = num_regs+4;
2540 int safe_regs = 4;
2541 int i;
2542 rtx xoperands[10];
2543
2544 struct {
2545 char *load; /* load insn without nop */
2546 char *load_nop; /* load insn with trailing nop */
2547 char *store; /* store insn */
2548 char *final; /* if last_store used: NULL or swr */
2549 char *last_store; /* last store instruction */
2550 int offset; /* current offset */
2551 enum machine_mode mode; /* mode to use on (MEM) */
2552 } load_store[4];
2553
2554 /* Detect a bug in GCC, where it can give us a register
2555 the same as one of the addressing registers and reduce
2556 the number of registers available. */
2557 for (i = 4;
2558 i < last_operand && safe_regs < (sizeof(xoperands) / sizeof(xoperands[0]));
2559 i++)
2560 {
2561 if (!reg_mentioned_p (operands[i], operands[0])
2562 && !reg_mentioned_p (operands[i], operands[1]))
2563
2564 xoperands[safe_regs++] = operands[i];
2565 }
2566
2567 if (safe_regs < last_operand)
2568 {
2569 xoperands[0] = operands[0];
2570 xoperands[1] = operands[1];
2571 xoperands[2] = operands[2];
2572 xoperands[3] = operands[3];
2573 return output_block_move (insn, xoperands, safe_regs-4, move_type);
2574 }
2575
2576 /* If we are given global or static addresses, and we would be
2577 emitting a few instructions, try to save time by using a
2578 temporary register for the pointer. */
2579 if (num_regs > 2 && (bytes > 2*align || move_type != BLOCK_MOVE_NORMAL))
2580 {
2581 if (CONSTANT_P (src_reg))
2582 {
2583 if (TARGET_STATS)
2584 mips_count_memory_refs (operands[1], 1);
2585
2586 src_reg = operands[ 3 + num_regs-- ];
2587 if (move_type != BLOCK_MOVE_LAST)
2588 {
2589 xoperands[1] = operands[1];
2590 xoperands[0] = src_reg;
2591 if (Pmode == DImode)
2592 output_asm_insn ("dla\t%0,%1", xoperands);
2593 else
2594 output_asm_insn ("la\t%0,%1", xoperands);
2595 }
2596 }
2597
2598 if (CONSTANT_P (dest_reg))
2599 {
2600 if (TARGET_STATS)
2601 mips_count_memory_refs (operands[0], 1);
2602
2603 dest_reg = operands[ 3 + num_regs-- ];
2604 if (move_type != BLOCK_MOVE_LAST)
2605 {
2606 xoperands[1] = operands[0];
2607 xoperands[0] = dest_reg;
2608 if (Pmode == DImode)
2609 output_asm_insn ("dla\t%0,%1", xoperands);
2610 else
2611 output_asm_insn ("la\t%0,%1", xoperands);
2612 }
2613 }
2614 }
2615
2616 /* ??? We really shouldn't get any LO_SUM addresses here, because they
2617 are not offsettable, however, offsettable_address_p says they are
2618 offsettable. I think this is a bug in offsettable_address_p.
2619 For expediency, we fix this by just loading the address into a register
2620 if we happen to get one. */
2621
2622 if (GET_CODE (src_reg) == LO_SUM)
2623 {
2624 src_reg = operands[ 3 + num_regs-- ];
2625 if (move_type != BLOCK_MOVE_LAST)
2626 {
2627 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
2628 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
2629 xoperands[0] = src_reg;
2630 if (Pmode == DImode)
2631 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
2632 else
2633 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
2634 }
2635 }
2636
2637 if (GET_CODE (dest_reg) == LO_SUM)
2638 {
2639 dest_reg = operands[ 3 + num_regs-- ];
2640 if (move_type != BLOCK_MOVE_LAST)
2641 {
2642 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
2643 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
2644 xoperands[0] = dest_reg;
2645 if (Pmode == DImode)
2646 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
2647 else
2648 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
2649 }
2650 }
2651
2652 if (num_regs > (sizeof (load_store) / sizeof (load_store[0])))
2653 num_regs = (sizeof (load_store) / sizeof (load_store[0]));
2654
2655 else if (num_regs < 1)
2656 abort_with_insn (insn, "Cannot do block move, not enough scratch registers");
2657
2658 while (bytes > 0)
2659 {
2660 load_store[num].offset = offset;
2661
2662 if (TARGET_64BIT && bytes >= 8 && align >= 8)
2663 {
2664 load_store[num].load = "ld\t%0,%1";
2665 load_store[num].load_nop = "ld\t%0,%1%#";
2666 load_store[num].store = "sd\t%0,%1";
2667 load_store[num].last_store = "sd\t%0,%1";
2668 load_store[num].final = (char *)0;
2669 load_store[num].mode = DImode;
2670 offset += 8;
2671 bytes -= 8;
2672 }
2673
2674 /* ??? Fails because of a MIPS assembler bug? */
2675 else if (TARGET_64BIT && bytes >= 8)
2676 {
2677 if (BYTES_BIG_ENDIAN)
2678 {
2679 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
2680 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
2681 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
2682 load_store[num].last_store = "sdr\t%0,%2";
2683 load_store[num].final = "sdl\t%0,%1";
2684 }
2685 else
2686 {
2687 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
2688 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
2689 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
2690 load_store[num].last_store = "sdr\t%0,%1";
2691 load_store[num].final = "sdl\t%0,%2";
2692 }
2693 load_store[num].mode = DImode;
2694 offset += 8;
2695 bytes -= 8;
2696 use_lwl_lwr = TRUE;
2697 }
2698
2699 else if (bytes >= 4 && align >= 4)
2700 {
2701 load_store[num].load = "lw\t%0,%1";
2702 load_store[num].load_nop = "lw\t%0,%1%#";
2703 load_store[num].store = "sw\t%0,%1";
2704 load_store[num].last_store = "sw\t%0,%1";
2705 load_store[num].final = (char *)0;
2706 load_store[num].mode = SImode;
2707 offset += 4;
2708 bytes -= 4;
2709 }
2710
2711 else if (bytes >= 4)
2712 {
2713 if (BYTES_BIG_ENDIAN)
2714 {
2715 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
2716 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2717 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
2718 load_store[num].last_store = "swr\t%0,%2";
2719 load_store[num].final = "swl\t%0,%1";
2720 }
2721 else
2722 {
2723 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
2724 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2725 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
2726 load_store[num].last_store = "swr\t%0,%1";
2727 load_store[num].final = "swl\t%0,%2";
2728 }
2729 load_store[num].mode = SImode;
2730 offset += 4;
2731 bytes -= 4;
2732 use_lwl_lwr = TRUE;
2733 }
2734
2735 else if (bytes >= 2 && align >= 2)
2736 {
2737 load_store[num].load = "lh\t%0,%1";
2738 load_store[num].load_nop = "lh\t%0,%1%#";
2739 load_store[num].store = "sh\t%0,%1";
2740 load_store[num].last_store = "sh\t%0,%1";
2741 load_store[num].final = (char *)0;
2742 load_store[num].mode = HImode;
2743 offset += 2;
2744 bytes -= 2;
2745 }
2746
2747 else
2748 {
2749 load_store[num].load = "lb\t%0,%1";
2750 load_store[num].load_nop = "lb\t%0,%1%#";
2751 load_store[num].store = "sb\t%0,%1";
2752 load_store[num].last_store = "sb\t%0,%1";
2753 load_store[num].final = (char *)0;
2754 load_store[num].mode = QImode;
2755 offset++;
2756 bytes--;
2757 }
2758
2759 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
2760 {
2761 dslots_load_total++;
2762 dslots_load_filled++;
2763
2764 if (CONSTANT_P (src_reg))
2765 mips_count_memory_refs (src_reg, 1);
2766
2767 if (CONSTANT_P (dest_reg))
2768 mips_count_memory_refs (dest_reg, 1);
2769 }
2770
2771 /* Emit load/stores now if we have run out of registers or are
2772 at the end of the move. */
2773
2774 if (++num == num_regs || bytes == 0)
2775 {
2776 /* If only load/store, we need a NOP after the load. */
2777 if (num == 1)
2778 {
2779 load_store[0].load = load_store[0].load_nop;
2780 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
2781 dslots_load_filled--;
2782 }
2783
2784 if (move_type != BLOCK_MOVE_LAST)
2785 {
2786 for (i = 0; i < num; i++)
2787 {
2788 int offset;
2789
2790 if (!operands[i+4])
2791 abort ();
2792
2793 if (GET_MODE (operands[i+4]) != load_store[i].mode)
2794 operands[i+4] = gen_rtx (REG, load_store[i].mode, REGNO (operands[i+4]));
2795
2796 offset = load_store[i].offset;
2797 xoperands[0] = operands[i+4];
2798 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
2799 plus_constant (src_reg, offset));
2800
2801 if (use_lwl_lwr)
2802 {
2803 int extra_offset;
2804 extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
2805 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
2806 plus_constant (src_reg,
2807 extra_offset
2808 + offset));
2809 }
2810
2811 output_asm_insn (load_store[i].load, xoperands);
2812 }
2813 }
2814
2815 for (i = 0; i < num; i++)
2816 {
2817 int last_p = (i == num-1 && bytes == 0);
2818 int offset = load_store[i].offset;
2819
2820 xoperands[0] = operands[i+4];
2821 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
2822 plus_constant (dest_reg, offset));
2823
2824
2825 if (use_lwl_lwr)
2826 {
2827 int extra_offset;
2828 extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
2829 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
2830 plus_constant (dest_reg,
2831 extra_offset
2832 + offset));
2833 }
2834
2835 if (move_type == BLOCK_MOVE_NORMAL)
2836 output_asm_insn (load_store[i].store, xoperands);
2837
2838 else if (move_type == BLOCK_MOVE_NOT_LAST)
2839 {
2840 if (!last_p)
2841 output_asm_insn (load_store[i].store, xoperands);
2842
2843 else if (load_store[i].final != (char *)0)
2844 output_asm_insn (load_store[i].final, xoperands);
2845 }
2846
2847 else if (last_p)
2848 output_asm_insn (load_store[i].last_store, xoperands);
2849 }
2850
2851 num = 0; /* reset load_store */
2852 use_lwl_lwr = FALSE;
2853 }
2854 }
2855
2856 return "";
2857 }
2858
2859 \f
2860 /* Argument support functions. */
2861
2862 /* Initialize CUMULATIVE_ARGS for a function. */
2863
2864 void
2865 init_cumulative_args (cum, fntype, libname)
2866 CUMULATIVE_ARGS *cum; /* argument info to initialize */
2867 tree fntype; /* tree ptr for function decl */
2868 rtx libname; /* SYMBOL_REF of library name or 0 */
2869 {
2870 static CUMULATIVE_ARGS zero_cum;
2871 tree param, next_param;
2872
2873 if (TARGET_DEBUG_E_MODE)
2874 {
2875 fprintf (stderr, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
2876 if (!fntype)
2877 fputc ('\n', stderr);
2878
2879 else
2880 {
2881 tree ret_type = TREE_TYPE (fntype);
2882 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
2883 tree_code_name[ (int)TREE_CODE (fntype) ],
2884 tree_code_name[ (int)TREE_CODE (ret_type) ]);
2885 }
2886 }
2887
2888 *cum = zero_cum;
2889
2890 /* Determine if this function has variable arguments. This is
2891 indicated by the last argument being 'void_type_mode' if there
2892 are no variable arguments. The standard MIPS calling sequence
2893 passes all arguments in the general purpose registers in this
2894 case. */
2895
2896 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
2897 param != (tree)0;
2898 param = next_param)
2899 {
2900 next_param = TREE_CHAIN (param);
2901 if (next_param == (tree)0 && TREE_VALUE (param) != void_type_node)
2902 cum->gp_reg_found = 1;
2903 }
2904 }
2905
2906 /* Advance the argument to the next argument position. */
2907
2908 void
2909 function_arg_advance (cum, mode, type, named)
2910 CUMULATIVE_ARGS *cum; /* current arg information */
2911 enum machine_mode mode; /* current arg mode */
2912 tree type; /* type of the argument or 0 if lib support */
2913 int named; /* whether or not the argument was named */
2914 {
2915 if (TARGET_DEBUG_E_MODE)
2916 fprintf (stderr,
2917 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
2918 cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode),
2919 type, named);
2920
2921 cum->arg_number++;
2922 switch (mode)
2923 {
2924 case VOIDmode:
2925 break;
2926
2927 default:
2928 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
2929 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
2930 abort ();
2931 cum->gp_reg_found = 1;
2932 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
2933 / UNITS_PER_WORD);
2934 break;
2935
2936 case BLKmode:
2937 cum->gp_reg_found = 1;
2938 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
2939 / UNITS_PER_WORD);
2940 break;
2941
2942 case SFmode:
2943 cum->arg_words++;
2944 break;
2945
2946 case DFmode:
2947 cum->arg_words += (TARGET_64BIT ? 1 : 2);
2948 break;
2949
2950 case DImode:
2951 cum->gp_reg_found = 1;
2952 cum->arg_words += (TARGET_64BIT ? 1 : 2);
2953 break;
2954
2955 case QImode:
2956 case HImode:
2957 case SImode:
2958 cum->gp_reg_found = 1;
2959 cum->arg_words++;
2960 break;
2961 }
2962 }
2963
2964 /* Return an RTL expression containing the register for the given mode,
2965 or 0 if the argument is to be passed on the stack. */
2966
2967 struct rtx_def *
2968 function_arg (cum, mode, type, named)
2969 CUMULATIVE_ARGS *cum; /* current arg information */
2970 enum machine_mode mode; /* current arg mode */
2971 tree type; /* type of the argument or 0 if lib support */
2972 int named; /* != 0 for normal args, == 0 for ... args */
2973 {
2974 rtx ret;
2975 int regbase = -1;
2976 int bias = 0;
2977 int struct_p = ((type != (tree)0)
2978 && (TREE_CODE (type) == RECORD_TYPE
2979 || TREE_CODE (type) == UNION_TYPE));
2980
2981 if (TARGET_DEBUG_E_MODE)
2982 fprintf (stderr,
2983 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
2984 cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode),
2985 type, named);
2986
2987 switch (mode)
2988 {
2989 case SFmode:
2990 if (mips_abi == ABI_32)
2991 {
2992 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
2993 regbase = GP_ARG_FIRST;
2994 else
2995 {
2996 regbase = FP_ARG_FIRST;
2997 /* If the first arg was a float in a floating point register,
2998 then set bias to align this float arg properly. */
2999 if (cum->arg_words == 1)
3000 bias = 1;
3001 }
3002 }
3003 else
3004 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
3005 break;
3006
3007 case DFmode:
3008 if (! TARGET_64BIT)
3009 cum->arg_words += (cum->arg_words & 1);
3010 if (mips_abi == ABI_32)
3011 regbase = ((cum->gp_reg_found
3012 || TARGET_SOFT_FLOAT
3013 || TARGET_SINGLE_FLOAT
3014 || cum->arg_number >= 2)
3015 ? GP_ARG_FIRST
3016 : FP_ARG_FIRST);
3017 else
3018 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
3019 ? GP_ARG_FIRST : FP_ARG_FIRST);
3020 break;
3021
3022 default:
3023 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3024 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3025 abort ();
3026
3027 /* Drops through. */
3028 case BLKmode:
3029 if (type != (tree)0 && TYPE_ALIGN (type) > BITS_PER_WORD
3030 && ! TARGET_64BIT)
3031 cum->arg_words += (cum->arg_words & 1);
3032
3033 regbase = GP_ARG_FIRST;
3034 break;
3035
3036 case VOIDmode:
3037 case QImode:
3038 case HImode:
3039 case SImode:
3040 regbase = GP_ARG_FIRST;
3041 break;
3042
3043 case DImode:
3044 if (! TARGET_64BIT)
3045 cum->arg_words += (cum->arg_words & 1);
3046 regbase = GP_ARG_FIRST;
3047 }
3048
3049 if (cum->arg_words >= MAX_ARGS_IN_REGISTERS)
3050 {
3051 if (TARGET_DEBUG_E_MODE)
3052 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
3053
3054 ret = (rtx)0;
3055 }
3056 else
3057 {
3058 if (regbase == -1)
3059 abort ();
3060
3061 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
3062 || ! named)
3063 ret = gen_rtx (REG, mode, regbase + cum->arg_words + bias);
3064 else
3065 {
3066 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3067 structure contains a double in its entirety, then that 64 bit
3068 chunk is passed in a floating point register. */
3069 tree field;
3070
3071 /* First check to see if there is any such field. */
3072 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3073 if (TREE_CODE (field) == FIELD_DECL
3074 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3075 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3076 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3077 % BITS_PER_WORD == 0))
3078 break;
3079
3080 if (! field)
3081 ret = gen_rtx (REG, mode, regbase + cum->arg_words + bias);
3082 else
3083 {
3084 /* Now handle the special case by returning a PARALLEL
3085 indicating where each 64 bit chunk goes. */
3086 int chunks;
3087 int bitpos;
3088 int regno;
3089 int i;
3090
3091 /* ??? If this is a packed structure, then the last hunk won't
3092 be 64 bits. */
3093
3094 /* ??? If this is a structure with a single double field,
3095 it would be more convenient to return (REG:DI %fX) than
3096 a parallel. However, we would have to modify the mips
3097 backend to allow DImode values in fp registers. */
3098
3099 chunks = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_WORD;
3100 if (chunks + cum->arg_words + bias > MAX_ARGS_IN_REGISTERS)
3101 chunks = MAX_ARGS_IN_REGISTERS - cum->arg_words - bias;
3102
3103 /* assign_parms checks the mode of ENTRY_PARM, so we must
3104 use the actual mode here. */
3105 ret = gen_rtx (PARALLEL, mode, rtvec_alloc (chunks));
3106
3107 bitpos = 0;
3108 regno = regbase + cum->arg_words + bias;
3109 field = TYPE_FIELDS (type);
3110 for (i = 0; i < chunks; i++)
3111 {
3112 rtx reg;
3113
3114 for (; field; field = TREE_CHAIN (field))
3115 if (TREE_CODE (field) == FIELD_DECL
3116 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3117 >= bitpos))
3118 break;
3119
3120 if (field
3121 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) == bitpos
3122 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3123 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3124 reg = gen_rtx (REG, DFmode,
3125 regno + FP_ARG_FIRST - GP_ARG_FIRST);
3126 else
3127 reg = gen_rtx (REG, word_mode, regno);
3128
3129 XVECEXP (ret, 0, i) = gen_rtx (EXPR_LIST, VOIDmode, reg,
3130 GEN_INT (bitpos / BITS_PER_UNIT));
3131
3132 bitpos += 64;
3133 regno++;
3134 }
3135 }
3136 }
3137
3138 if (TARGET_DEBUG_E_MODE)
3139 fprintf (stderr, "%s%s\n", reg_names[regbase + cum->arg_words + bias],
3140 struct_p ? ", [struct]" : "");
3141
3142 /* The following is a hack in order to pass 1 byte structures
3143 the same way that the MIPS compiler does (namely by passing
3144 the structure in the high byte or half word of the register).
3145 This also makes varargs work. If we have such a structure,
3146 we save the adjustment RTL, and the call define expands will
3147 emit them. For the VOIDmode argument (argument after the
3148 last real argument), pass back a parallel vector holding each
3149 of the adjustments. */
3150
3151 /* ??? function_arg can be called more than once for each argument.
3152 As a result, we compute more adjustments than we need here.
3153 See the CUMULATIVE_ARGS definition in mips.h. */
3154
3155 /* ??? This scheme requires everything smaller than the word size to
3156 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3157 that would mean every int needs to be shifted left, which is very
3158 inefficient. Let's not carry this compatibility to the 64 bit
3159 calling convention for now. */
3160
3161 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
3162 && ! TARGET_64BIT)
3163 {
3164 rtx amount = GEN_INT (BITS_PER_WORD
3165 - int_size_in_bytes (type) * BITS_PER_UNIT);
3166 rtx reg = gen_rtx (REG, word_mode, regbase + cum->arg_words + bias);
3167 if (TARGET_64BIT)
3168 cum->adjust[ cum->num_adjusts++ ] = gen_ashldi3 (reg, reg, amount);
3169 else
3170 cum->adjust[ cum->num_adjusts++ ] = gen_ashlsi3 (reg, reg, amount);
3171 }
3172 }
3173
3174 if (mode == VOIDmode && cum->num_adjusts > 0)
3175 ret = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (cum->num_adjusts, cum->adjust));
3176
3177 return ret;
3178 }
3179
3180
3181 int
3182 function_arg_partial_nregs (cum, mode, type, named)
3183 CUMULATIVE_ARGS *cum; /* current arg information */
3184 enum machine_mode mode; /* current arg mode */
3185 tree type; /* type of the argument or 0 if lib support */
3186 int named; /* != 0 for normal args, == 0 for ... args */
3187 {
3188 if ((mode == BLKmode
3189 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3190 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3191 && cum->arg_words < MAX_ARGS_IN_REGISTERS)
3192 {
3193 int words;
3194 if (mode == BLKmode)
3195 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3196 / UNITS_PER_WORD);
3197 else
3198 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3199
3200 if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS)
3201 return 0; /* structure fits in registers */
3202
3203 if (TARGET_DEBUG_E_MODE)
3204 fprintf (stderr, "function_arg_partial_nregs = %d\n",
3205 MAX_ARGS_IN_REGISTERS - cum->arg_words);
3206
3207 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
3208 }
3209
3210 else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1
3211 && ! TARGET_64BIT)
3212 {
3213 if (TARGET_DEBUG_E_MODE)
3214 fprintf (stderr, "function_arg_partial_nregs = 1\n");
3215
3216 return 1;
3217 }
3218
3219 return 0;
3220 }
3221 \f
3222 /* Abort after printing out a specific insn. */
3223
3224 void
3225 abort_with_insn (insn, reason)
3226 rtx insn;
3227 char *reason;
3228 {
3229 error (reason);
3230 debug_rtx (insn);
3231 abort ();
3232 }
3233
3234 /* Write a message to stderr (for use in macros expanded in files that do not
3235 include stdio.h). */
3236
3237 void
3238 trace (s, s1, s2)
3239 char *s, *s1, *s2;
3240 {
3241 fprintf (stderr, s, s1, s2);
3242 }
3243
3244 \f
3245 #ifdef SIGINFO
3246
3247 static void
3248 siginfo (signo)
3249 int signo;
3250 {
3251 fprintf (stderr, "compiling '%s' in '%s'\n",
3252 (current_function_name != (char *)0) ? current_function_name : "<toplevel>",
3253 (current_function_file != (char *)0) ? current_function_file : "<no file>");
3254 fflush (stderr);
3255 }
3256 #endif /* SIGINFO */
3257
3258 \f
3259 /* Set up the threshold for data to go into the small data area, instead
3260 of the normal data area, and detect any conflicts in the switches. */
3261
3262 void
3263 override_options ()
3264 {
3265 register int i, start;
3266 register int regno;
3267 register enum machine_mode mode;
3268
3269 mips_section_threshold = (g_switch_set) ? g_switch_value : MIPS_DEFAULT_GVALUE;
3270
3271 if (mips_section_threshold <= 0)
3272 target_flags &= ~MASK_GPOPT;
3273 else if (optimize)
3274 target_flags |= MASK_GPOPT;
3275
3276 /* Get the architectural level. */
3277 if (mips_isa_string == (char *)0)
3278 {
3279 #ifdef MIPS_ISA_DEFAULT
3280 mips_isa = MIPS_ISA_DEFAULT;
3281 #else
3282 mips_isa = 1;
3283 #endif
3284 }
3285
3286 else if (isdigit (*mips_isa_string))
3287 {
3288 mips_isa = atoi (mips_isa_string);
3289 if (mips_isa < 1 || mips_isa > 4)
3290 {
3291 error ("-mips%d not supported", mips_isa);
3292 mips_isa = 1;
3293 }
3294 }
3295
3296 else
3297 {
3298 error ("bad value (%s) for -mips switch", mips_isa_string);
3299 mips_isa = 1;
3300 }
3301
3302 #ifdef MIPS_ABI_DEFAULT
3303 /* Get the ABI to use. Currently this code is only used for Irix 6. */
3304 if (mips_abi_string == (char *) 0)
3305 mips_abi = MIPS_ABI_DEFAULT;
3306 else if (! strcmp (mips_abi_string, "32")
3307 || ! strcmp (mips_abi_string, "o32"))
3308 mips_abi = ABI_32;
3309 else if (! strcmp (mips_abi_string, "n32"))
3310 mips_abi = ABI_N32;
3311 else if (! strcmp (mips_abi_string, "64")
3312 || ! strcmp (mips_abi_string, "n64"))
3313 mips_abi = ABI_64;
3314 else
3315 error ("bad value (%s) for -mabi= switch", mips_abi_string);
3316
3317 /* A specified ISA defaults the ABI if it was not specified. */
3318 if (mips_abi_string == 0 && mips_isa_string)
3319 {
3320 if (mips_isa <= 2)
3321 mips_abi = ABI_32;
3322 else
3323 mips_abi = ABI_64;
3324 }
3325 /* A specified ABI defaults the ISA if it was not specified. */
3326 else if (mips_isa_string == 0 && mips_abi_string)
3327 {
3328 if (mips_abi == ABI_32)
3329 mips_isa = 1;
3330 else if (mips_abi == ABI_N32)
3331 mips_isa = 3;
3332 else
3333 mips_isa = 4;
3334 }
3335 /* If both ABI and ISA were specified, check for conflicts. */
3336 else if (mips_isa_string && mips_abi_string)
3337 {
3338 if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64))
3339 || (mips_isa >= 3 && mips_abi == ABI_32))
3340 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
3341 }
3342
3343 /* Override TARGET_DEFAULT if necessary. */
3344 if (mips_abi == ABI_32)
3345 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
3346
3347 /* ??? This doesn't work yet, so don't let people try to use it. */
3348 if (mips_abi == ABI_32)
3349 error ("The -mabi=32 support does not work yet.");
3350 #else
3351 if (mips_abi_string)
3352 error ("This target does not support the -mabi switch.");
3353 #endif
3354
3355 #ifdef MIPS_CPU_STRING_DEFAULT
3356 /* ??? There is a minor inconsistency here. If the user specifies an ISA
3357 greater than that supported by the default processor, then the user gets
3358 an error. Normally, the compiler will just default to the base level cpu
3359 for the indicated isa. */
3360 if (mips_cpu_string == (char *)0)
3361 mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
3362 #endif
3363
3364 /* Identify the processor type */
3365 if (mips_cpu_string == (char *)0
3366 || !strcmp (mips_cpu_string, "default")
3367 || !strcmp (mips_cpu_string, "DEFAULT"))
3368 {
3369 switch (mips_isa)
3370 {
3371 default:
3372 mips_cpu_string = "3000";
3373 mips_cpu = PROCESSOR_R3000;
3374 break;
3375 case 2:
3376 mips_cpu_string = "6000";
3377 mips_cpu = PROCESSOR_R6000;
3378 break;
3379 case 3:
3380 mips_cpu_string = "4000";
3381 mips_cpu = PROCESSOR_R4000;
3382 break;
3383 case 4:
3384 mips_cpu_string = "8000";
3385 mips_cpu = PROCESSOR_R8000;
3386 break;
3387 }
3388 }
3389
3390 else
3391 {
3392 char *p = mips_cpu_string;
3393 int seen_v = FALSE;
3394
3395 /* We need to cope with the various "vr" prefixes for the NEC 4300
3396 and 4100 processors. */
3397 if (*p == 'v' || *p == 'V')
3398 {
3399 seen_v = TRUE;
3400 p++;
3401 }
3402 if (*p == 'r' || *p == 'R')
3403 p++;
3404
3405 /* Since there is no difference between a R2000 and R3000 in
3406 terms of the scheduler, we collapse them into just an R3000. */
3407
3408 mips_cpu = PROCESSOR_DEFAULT;
3409 switch (*p)
3410 {
3411 case '2':
3412 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
3413 mips_cpu = PROCESSOR_R3000;
3414 break;
3415
3416 case '3':
3417 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
3418 mips_cpu = PROCESSOR_R3000;
3419 break;
3420
3421 case '4':
3422 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
3423 mips_cpu = PROCESSOR_R4000;
3424 /* The vr4100 is a non-FP ISA III processor with some extra
3425 instructions. */
3426 else if (!strcmp (p, "4100")) {
3427 mips_cpu = PROCESSOR_R4100;
3428 target_flags |= MASK_SOFT_FLOAT ;
3429 }
3430 /* The vr4300 is a standard ISA III processor, but with a different
3431 pipeline. */
3432 else if (!strcmp (p, "4300"))
3433 mips_cpu = PROCESSOR_R4300;
3434 /* The r4400 is exactly the same as the r4000 from the compiler's
3435 viewpoint. */
3436 else if (!strcmp (p, "4400"))
3437 mips_cpu = PROCESSOR_R4000;
3438 else if (!strcmp (p, "4600"))
3439 mips_cpu = PROCESSOR_R4600;
3440 else if (!strcmp (p, "4650"))
3441 mips_cpu = PROCESSOR_R4650;
3442 break;
3443
3444 case '6':
3445 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
3446 mips_cpu = PROCESSOR_R6000;
3447 break;
3448
3449 case '8':
3450 if (!strcmp (p, "8000"))
3451 mips_cpu = PROCESSOR_R8000;
3452 break;
3453
3454 case 'o':
3455 if (!strcmp (p, "orion"))
3456 mips_cpu = PROCESSOR_R4600;
3457 break;
3458 }
3459
3460 if (seen_v && mips_cpu != PROCESSOR_R4300 && mips_cpu != PROCESSOR_R4100)
3461 mips_cpu = PROCESSOR_DEFAULT;
3462
3463 if (mips_cpu == PROCESSOR_DEFAULT)
3464 {
3465 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
3466 mips_cpu_string = "default";
3467 }
3468 }
3469
3470 if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
3471 || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
3472 || ((mips_cpu == PROCESSOR_R4000
3473 || mips_cpu == PROCESSOR_R4100
3474 || mips_cpu == PROCESSOR_R4300
3475 || mips_cpu == PROCESSOR_R4600
3476 || mips_cpu == PROCESSOR_R4650)
3477 && mips_isa > 3))
3478 error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
3479
3480 /* make sure sizes of ints/longs/etc. are ok */
3481 if (mips_isa < 3)
3482 {
3483 if (TARGET_INT64)
3484 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3485
3486 else if (TARGET_LONG64)
3487 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3488
3489 else if (TARGET_FLOAT64)
3490 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3491
3492 else if (TARGET_64BIT)
3493 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3494 }
3495
3496 if (mips_abi != ABI_32)
3497 flag_pcc_struct_return = 0;
3498
3499 /* Tell halfpic.c that we have half-pic code if we do. */
3500 if (TARGET_HALF_PIC)
3501 HALF_PIC_INIT ();
3502
3503 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3504 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3505 /* ??? -non_shared turns off pic code generation, but this is not
3506 implemented. */
3507 if (TARGET_ABICALLS)
3508 {
3509 mips_abicalls = MIPS_ABICALLS_YES;
3510 flag_pic = 1;
3511 if (mips_section_threshold > 0)
3512 warning ("-G is incompatible with PIC code which is the default");
3513 }
3514 else
3515 mips_abicalls = MIPS_ABICALLS_NO;
3516
3517 /* -membedded-pic is a form of PIC code suitable for embedded
3518 systems. All calls are made using PC relative addressing, and
3519 all data is addressed using the $gp register. This requires gas,
3520 which does most of the work, and GNU ld, which automatically
3521 expands PC relative calls which are out of range into a longer
3522 instruction sequence. All gcc really does differently is
3523 generate a different sequence for a switch. */
3524 if (TARGET_EMBEDDED_PIC)
3525 {
3526 flag_pic = 1;
3527 if (TARGET_ABICALLS)
3528 warning ("-membedded-pic and -mabicalls are incompatible");
3529 if (g_switch_set)
3530 warning ("-G and -membedded-pic are incompatible");
3531 /* Setting mips_section_threshold is not required, because gas
3532 will force everything to be GP addressable anyhow, but
3533 setting it will cause gcc to make better estimates of the
3534 number of instructions required to access a particular data
3535 item. */
3536 mips_section_threshold = 0x7fffffff;
3537 }
3538
3539 /* ??? This does not work when target addresses are DImode.
3540 This is because we are missing DImode high/lo_sum patterns. */
3541
3542 if (TARGET_GAS && optimize && ! flag_pic && Pmode == SImode)
3543 mips_split_addresses = 1;
3544 else
3545 mips_split_addresses = 0;
3546
3547 /* -mrnames says to use the MIPS software convention for register
3548 names instead of the hardware names (ie, $a0 instead of $4).
3549 We do this by switching the names in mips_reg_names, which the
3550 reg_names points into via the REGISTER_NAMES macro. */
3551
3552 if (TARGET_NAME_REGS)
3553 bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names, sizeof (mips_reg_names));
3554
3555 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3556 is currently being compiled. */
3557 #ifdef SIGINFO
3558 if (getenv ("GCC_SIGINFO") != (char *)0)
3559 {
3560 struct sigaction action;
3561 action.sa_handler = siginfo;
3562 action.sa_mask = 0;
3563 action.sa_flags = SA_RESTART;
3564 sigaction (SIGINFO, &action, (struct sigaction *)0);
3565 }
3566 #endif
3567
3568 #if defined(_IOLBF)
3569 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3570 /* If -mstats and -quiet, make stderr line buffered. */
3571 if (quiet_flag && TARGET_STATS)
3572 setvbuf (stderr, (char *)0, _IOLBF, BUFSIZ);
3573 #endif
3574 #endif
3575
3576 /* Initialize the high and low values for legitimate floating point
3577 constants. Rather than trying to get the accuracy down to the
3578 last bit, just use approximate ranges. */
3579 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
3580 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
3581 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
3582 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
3583
3584 mips_print_operand_punct['?'] = TRUE;
3585 mips_print_operand_punct['#'] = TRUE;
3586 mips_print_operand_punct['&'] = TRUE;
3587 mips_print_operand_punct['!'] = TRUE;
3588 mips_print_operand_punct['*'] = TRUE;
3589 mips_print_operand_punct['@'] = TRUE;
3590 mips_print_operand_punct['.'] = TRUE;
3591 mips_print_operand_punct['('] = TRUE;
3592 mips_print_operand_punct[')'] = TRUE;
3593 mips_print_operand_punct['['] = TRUE;
3594 mips_print_operand_punct[']'] = TRUE;
3595 mips_print_operand_punct['<'] = TRUE;
3596 mips_print_operand_punct['>'] = TRUE;
3597 mips_print_operand_punct['{'] = TRUE;
3598 mips_print_operand_punct['}'] = TRUE;
3599 mips_print_operand_punct['^'] = TRUE;
3600
3601 mips_char_to_class['d'] = GR_REGS;
3602 mips_char_to_class['f'] = ((TARGET_HARD_FLOAT) ? FP_REGS : NO_REGS);
3603 mips_char_to_class['h'] = HI_REG;
3604 mips_char_to_class['l'] = LO_REG;
3605 mips_char_to_class['a'] = HILO_REG;
3606 mips_char_to_class['x'] = MD_REGS;
3607 mips_char_to_class['b'] = ALL_REGS;
3608 mips_char_to_class['y'] = GR_REGS;
3609 mips_char_to_class['z'] = ST_REGS;
3610
3611 /* Set up array to map GCC register number to debug register number.
3612 Ignore the special purpose register numbers. */
3613
3614 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3615 mips_dbx_regno[i] = -1;
3616
3617 start = GP_DBX_FIRST - GP_REG_FIRST;
3618 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
3619 mips_dbx_regno[i] = i + start;
3620
3621 start = FP_DBX_FIRST - FP_REG_FIRST;
3622 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
3623 mips_dbx_regno[i] = i + start;
3624
3625 /* Set up array giving whether a given register can hold a given mode.
3626 At present, restrict ints from being in FP registers, because reload
3627 is a little enthusiastic about storing extra values in FP registers,
3628 and this is not good for things like OS kernels. Also, due to the
3629 mandatory delay, it is as fast to load from cached memory as to move
3630 from the FP register. */
3631
3632 for (mode = VOIDmode;
3633 mode != MAX_MACHINE_MODE;
3634 mode = (enum machine_mode)((int)mode + 1))
3635 {
3636 register int size = GET_MODE_SIZE (mode);
3637 register enum mode_class class = GET_MODE_CLASS (mode);
3638
3639 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
3640 {
3641 register int temp;
3642
3643 if (mode == CC_FPmode || mode == CC_REV_FPmode)
3644 temp = (regno == FPSW_REGNUM);
3645
3646 else if (GP_REG_P (regno))
3647 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
3648
3649 else if (FP_REG_P (regno))
3650 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
3651 && (class == MODE_FLOAT
3652 || class == MODE_COMPLEX_FLOAT
3653 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
3654 && (! TARGET_SINGLE_FLOAT || size <= 4));
3655
3656 else if (MD_REG_P (regno))
3657 temp = (class == MODE_INT
3658 && (size <= UNITS_PER_WORD
3659 || (regno == MD_REG_FIRST && size == 2 * UNITS_PER_WORD)));
3660
3661 else
3662 temp = FALSE;
3663
3664 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
3665 }
3666 }
3667 }
3668
3669 \f
3670 /*
3671 * The MIPS debug format wants all automatic variables and arguments
3672 * to be in terms of the virtual frame pointer (stack pointer before
3673 * any adjustment in the function), while the MIPS 3.0 linker wants
3674 * the frame pointer to be the stack pointer after the initial
3675 * adjustment. So, we do the adjustment here. The arg pointer (which
3676 * is eliminated) points to the virtual frame pointer, while the frame
3677 * pointer (which may be eliminated) points to the stack pointer after
3678 * the initial adjustments.
3679 */
3680
3681 int
3682 mips_debugger_offset (addr, offset)
3683 rtx addr;
3684 int offset;
3685 {
3686 rtx offset2 = const0_rtx;
3687 rtx reg = eliminate_constant_term (addr, &offset2);
3688
3689 if (!offset)
3690 offset = INTVAL (offset2);
3691
3692 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx)
3693 {
3694 int frame_size = (!current_frame_info.initialized)
3695 ? compute_frame_size (get_frame_size ())
3696 : current_frame_info.total_size;
3697
3698 offset = offset - frame_size;
3699 }
3700 /* sdbout_parms does not want this to crash for unrecognized cases. */
3701 #if 0
3702 else if (reg != arg_pointer_rtx)
3703 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
3704 #endif
3705
3706 return offset;
3707 }
3708
3709 \f
3710 /* A C compound statement to output to stdio stream STREAM the
3711 assembler syntax for an instruction operand X. X is an RTL
3712 expression.
3713
3714 CODE is a value that can be used to specify one of several ways
3715 of printing the operand. It is used when identical operands
3716 must be printed differently depending on the context. CODE
3717 comes from the `%' specification that was used to request
3718 printing of the operand. If the specification was just `%DIGIT'
3719 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3720 is the ASCII code for LTR.
3721
3722 If X is a register, this macro should print the register's name.
3723 The names can be found in an array `reg_names' whose type is
3724 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3725
3726 When the machine description has a specification `%PUNCT' (a `%'
3727 followed by a punctuation character), this macro is called with
3728 a null pointer for X and the punctuation character for CODE.
3729
3730 The MIPS specific codes are:
3731
3732 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3733 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3734 'd' output integer constant in decimal,
3735 'z' if the operand is 0, use $0 instead of normal operand.
3736 'D' print second register of double-word register operand.
3737 'L' print low-order register of double-word register operand.
3738 'M' print high-order register of double-word register operand.
3739 'C' print part of opcode for a branch condition.
3740 'N' print part of opcode for a branch condition, inverted.
3741 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3742 'B' print 'z' for EQ, 'n' for NE
3743 'b' print 'n' for EQ, 'z' for NE
3744 'T' print 'f' for EQ, 't' for NE
3745 't' print 't' for EQ, 'f' for NE
3746 '(' Turn on .set noreorder
3747 ')' Turn on .set reorder
3748 '[' Turn on .set noat
3749 ']' Turn on .set at
3750 '<' Turn on .set nomacro
3751 '>' Turn on .set macro
3752 '{' Turn on .set volatile (not GAS)
3753 '}' Turn on .set novolatile (not GAS)
3754 '&' Turn on .set noreorder if filling delay slots
3755 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3756 '!' Turn on .set nomacro if filling delay slots
3757 '#' Print nop if in a .set noreorder section.
3758 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3759 '@' Print the name of the assembler temporary register (at or $1).
3760 '.' Print the name of the register with a hard-wired zero (zero or $0).
3761 '^' Print the name of the pic call-through register (t9 or $25). */
3762
3763 void
3764 print_operand (file, op, letter)
3765 FILE *file; /* file to write to */
3766 rtx op; /* operand to print */
3767 int letter; /* %<letter> or 0 */
3768 {
3769 register enum rtx_code code;
3770
3771 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
3772 {
3773 switch (letter)
3774 {
3775 default:
3776 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
3777 break;
3778
3779 case '?':
3780 if (mips_branch_likely)
3781 putc ('l', file);
3782 break;
3783
3784 case '@':
3785 fputs (reg_names [GP_REG_FIRST + 1], file);
3786 break;
3787
3788 case '^':
3789 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
3790 break;
3791
3792 case '.':
3793 fputs (reg_names [GP_REG_FIRST + 0], file);
3794 break;
3795
3796 case '&':
3797 if (final_sequence != 0 && set_noreorder++ == 0)
3798 fputs (".set\tnoreorder\n\t", file);
3799 break;
3800
3801 case '*':
3802 if (final_sequence != 0)
3803 {
3804 if (set_noreorder++ == 0)
3805 fputs (".set\tnoreorder\n\t", file);
3806
3807 if (set_nomacro++ == 0)
3808 fputs (".set\tnomacro\n\t", file);
3809 }
3810 break;
3811
3812 case '!':
3813 if (final_sequence != 0 && set_nomacro++ == 0)
3814 fputs ("\n\t.set\tnomacro", file);
3815 break;
3816
3817 case '#':
3818 if (set_noreorder != 0)
3819 fputs ("\n\tnop", file);
3820
3821 else if (TARGET_STATS)
3822 fputs ("\n\t#nop", file);
3823
3824 break;
3825
3826 case '(':
3827 if (set_noreorder++ == 0)
3828 fputs (".set\tnoreorder\n\t", file);
3829 break;
3830
3831 case ')':
3832 if (set_noreorder == 0)
3833 error ("internal error: %%) found without a %%( in assembler pattern");
3834
3835 else if (--set_noreorder == 0)
3836 fputs ("\n\t.set\treorder", file);
3837
3838 break;
3839
3840 case '[':
3841 if (set_noat++ == 0)
3842 fputs (".set\tnoat\n\t", file);
3843 break;
3844
3845 case ']':
3846 if (set_noat == 0)
3847 error ("internal error: %%] found without a %%[ in assembler pattern");
3848
3849 else if (--set_noat == 0)
3850 fputs ("\n\t.set\tat", file);
3851
3852 break;
3853
3854 case '<':
3855 if (set_nomacro++ == 0)
3856 fputs (".set\tnomacro\n\t", file);
3857 break;
3858
3859 case '>':
3860 if (set_nomacro == 0)
3861 error ("internal error: %%> found without a %%< in assembler pattern");
3862
3863 else if (--set_nomacro == 0)
3864 fputs ("\n\t.set\tmacro", file);
3865
3866 break;
3867
3868 case '{':
3869 if (set_volatile++ == 0)
3870 fprintf (file, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS) ? "" : "#");
3871 break;
3872
3873 case '}':
3874 if (set_volatile == 0)
3875 error ("internal error: %%} found without a %%{ in assembler pattern");
3876
3877 else if (--set_volatile == 0)
3878 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
3879
3880 break;
3881 }
3882 return;
3883 }
3884
3885 if (! op)
3886 {
3887 error ("PRINT_OPERAND null pointer");
3888 return;
3889 }
3890
3891 code = GET_CODE (op);
3892 if (letter == 'C')
3893 switch (code)
3894 {
3895 case EQ: fputs ("eq", file); break;
3896 case NE: fputs ("ne", file); break;
3897 case GT: fputs ("gt", file); break;
3898 case GE: fputs ("ge", file); break;
3899 case LT: fputs ("lt", file); break;
3900 case LE: fputs ("le", file); break;
3901 case GTU: fputs ("gtu", file); break;
3902 case GEU: fputs ("geu", file); break;
3903 case LTU: fputs ("ltu", file); break;
3904 case LEU: fputs ("leu", file); break;
3905
3906 default:
3907 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
3908 }
3909
3910 else if (letter == 'N')
3911 switch (code)
3912 {
3913 case EQ: fputs ("ne", file); break;
3914 case NE: fputs ("eq", file); break;
3915 case GT: fputs ("le", file); break;
3916 case GE: fputs ("lt", file); break;
3917 case LT: fputs ("ge", file); break;
3918 case LE: fputs ("gt", file); break;
3919 case GTU: fputs ("leu", file); break;
3920 case GEU: fputs ("ltu", file); break;
3921 case LTU: fputs ("geu", file); break;
3922 case LEU: fputs ("gtu", file); break;
3923
3924 default:
3925 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
3926 }
3927
3928 else if (letter == 'S')
3929 {
3930 char buffer[100];
3931
3932 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
3933 assemble_name (file, buffer);
3934 }
3935
3936 else if (code == REG)
3937 {
3938 register int regnum = REGNO (op);
3939
3940 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
3941 || (letter == 'L' && WORDS_BIG_ENDIAN)
3942 || letter == 'D')
3943 regnum++;
3944
3945 fprintf (file, "%s", reg_names[regnum]);
3946 }
3947
3948 else if (code == MEM)
3949 output_address (XEXP (op, 0));
3950
3951 else if (code == CONST_DOUBLE
3952 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
3953 {
3954 REAL_VALUE_TYPE d;
3955 char s[30];
3956
3957 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
3958 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
3959 fprintf (file, s);
3960 }
3961
3962 else if ((letter == 'x') && (GET_CODE(op) == CONST_INT))
3963 fprintf (file, "0x%04x", 0xffff & (INTVAL(op)));
3964
3965 else if ((letter == 'X') && (GET_CODE(op) == CONST_INT)
3966 && HOST_BITS_PER_WIDE_INT == 32)
3967 fprintf (file, "0x%08x", INTVAL(op));
3968
3969 else if ((letter == 'X') && (GET_CODE(op) == CONST_INT)
3970 && HOST_BITS_PER_WIDE_INT == 64)
3971 fprintf (file, "0x%016lx", INTVAL(op));
3972
3973 else if ((letter == 'd') && (GET_CODE(op) == CONST_INT))
3974 fprintf (file, "%d", (INTVAL(op)));
3975
3976 else if (letter == 'z'
3977 && (GET_CODE (op) == CONST_INT)
3978 && INTVAL (op) == 0)
3979 fputs (reg_names[GP_REG_FIRST], file);
3980
3981 else if (letter == 'd' || letter == 'x' || letter == 'X')
3982 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter);
3983
3984 else if (letter == 'B')
3985 fputs (code == EQ ? "z" : "n", file);
3986 else if (letter == 'b')
3987 fputs (code == EQ ? "n" : "z", file);
3988 else if (letter == 'T')
3989 fputs (code == EQ ? "f" : "t", file);
3990 else if (letter == 't')
3991 fputs (code == EQ ? "t" : "f", file);
3992
3993 else
3994 output_addr_const (file, op);
3995 }
3996
3997 \f
3998 /* A C compound statement to output to stdio stream STREAM the
3999 assembler syntax for an instruction operand that is a memory
4000 reference whose address is ADDR. ADDR is an RTL expression.
4001
4002 On some machines, the syntax for a symbolic address depends on
4003 the section that the address refers to. On these machines,
4004 define the macro `ENCODE_SECTION_INFO' to store the information
4005 into the `symbol_ref', and then check for it here. */
4006
4007 void
4008 print_operand_address (file, addr)
4009 FILE *file;
4010 rtx addr;
4011 {
4012 if (!addr)
4013 error ("PRINT_OPERAND_ADDRESS, null pointer");
4014
4015 else
4016 switch (GET_CODE (addr))
4017 {
4018 default:
4019 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
4020 break;
4021
4022 case REG:
4023 if (REGNO (addr) == ARG_POINTER_REGNUM)
4024 abort_with_insn (addr, "Arg pointer not eliminated.");
4025
4026 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
4027 break;
4028
4029 case LO_SUM:
4030 {
4031 register rtx arg0 = XEXP (addr, 0);
4032 register rtx arg1 = XEXP (addr, 1);
4033
4034 if (! mips_split_addresses)
4035 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4036
4037 if (GET_CODE (arg0) != REG)
4038 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4039
4040 fprintf (file, "%%lo(");
4041 print_operand_address (file, arg1);
4042 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
4043 }
4044 break;
4045
4046 case PLUS:
4047 {
4048 register rtx reg = (rtx)0;
4049 register rtx offset = (rtx)0;
4050 register rtx arg0 = XEXP (addr, 0);
4051 register rtx arg1 = XEXP (addr, 1);
4052
4053 if (GET_CODE (arg0) == REG)
4054 {
4055 reg = arg0;
4056 offset = arg1;
4057 if (GET_CODE (offset) == REG)
4058 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
4059 }
4060 else if (GET_CODE (arg1) == REG)
4061 {
4062 reg = arg1;
4063 offset = arg0;
4064 }
4065 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
4066 {
4067 output_addr_const (file, addr);
4068 break;
4069 }
4070 else
4071 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
4072
4073 if (!CONSTANT_P (offset))
4074 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4075
4076 if (REGNO (reg) == ARG_POINTER_REGNUM)
4077 abort_with_insn (addr, "Arg pointer not eliminated.");
4078
4079 output_addr_const (file, offset);
4080 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
4081 }
4082 break;
4083
4084 case LABEL_REF:
4085 case SYMBOL_REF:
4086 case CONST_INT:
4087 case CONST:
4088 output_addr_const (file, addr);
4089 break;
4090 }
4091 }
4092
4093 \f
4094 /* If optimizing for the global pointer, keep track of all of
4095 the externs, so that at the end of the file, we can emit
4096 the appropriate .extern declaration for them, before writing
4097 out the text section. We assume that all names passed to
4098 us are in the permanent obstack, so that they will be valid
4099 at the end of the compilation.
4100
4101 If we have -G 0, or the extern size is unknown, don't bother
4102 emitting the .externs. */
4103
4104 int
4105 mips_output_external (file, decl, name)
4106 FILE *file;
4107 tree decl;
4108 char *name;
4109 {
4110 register struct extern_list *p;
4111 int len;
4112
4113 if (TARGET_GP_OPT
4114 && ((TREE_CODE (decl)) != FUNCTION_DECL)
4115 && ((len = int_size_in_bytes (TREE_TYPE (decl))) > 0))
4116 {
4117 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
4118 p->next = extern_head;
4119 p->name = name;
4120 p->size = len;
4121 extern_head = p;
4122 }
4123
4124 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4125 if (TREE_CODE (decl) == FUNCTION_DECL
4126 /* ??? Don't include alloca, since gcc will always expand it
4127 inline. If we don't do this, libg++ fails to build. */
4128 && strcmp (name, "alloca")
4129 /* ??? Don't include __builtin_next_arg, because then gcc will not
4130 bootstrap under Irix 5.1. */
4131 && strcmp (name, "__builtin_next_arg"))
4132 {
4133 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
4134 p->next = extern_head;
4135 p->name = name;
4136 p->size = -1;
4137 extern_head = p;
4138 }
4139 #endif
4140
4141 return 0;
4142 }
4143
4144 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4145 int
4146 mips_output_external_libcall (file, name)
4147 FILE *file;
4148 char *name;
4149 {
4150 register struct extern_list *p;
4151
4152 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
4153 p->next = extern_head;
4154 p->name = name;
4155 p->size = -1;
4156 extern_head = p;
4157
4158 return 0;
4159 }
4160 #endif
4161
4162 \f
4163 /* Compute a string to use as a temporary file name. */
4164
4165 /* On MSDOS, write temp files in current dir
4166 because there's no place else we can expect to use. */
4167 #if __MSDOS__
4168 #ifndef P_tmpdir
4169 #define P_tmpdir "./"
4170 #endif
4171 #endif
4172
4173 static FILE *
4174 make_temp_file ()
4175 {
4176 FILE *stream;
4177 char *base = getenv ("TMPDIR");
4178 int len;
4179
4180 if (base == (char *)0)
4181 {
4182 #ifdef P_tmpdir
4183 if (access (P_tmpdir, R_OK | W_OK) == 0)
4184 base = P_tmpdir;
4185 else
4186 #endif
4187 if (access ("/usr/tmp", R_OK | W_OK) == 0)
4188 base = "/usr/tmp/";
4189 else
4190 base = "/tmp/";
4191 }
4192
4193 len = strlen (base);
4194 /* temp_filename is global, so we must use malloc, not alloca. */
4195 temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX"));
4196 strcpy (temp_filename, base);
4197 if (len > 0 && temp_filename[len-1] != '/')
4198 temp_filename[len++] = '/';
4199
4200 strcpy (temp_filename + len, "ctXXXXXX");
4201 mktemp (temp_filename);
4202
4203 stream = fopen (temp_filename, "w+");
4204 if (!stream)
4205 pfatal_with_name (temp_filename);
4206
4207 #ifndef __MSDOS__
4208 /* In MSDOS, we cannot unlink the temporary file until we are finished using
4209 it. Otherwise, we delete it now, so that it will be gone even if the
4210 compiler happens to crash. */
4211 unlink (temp_filename);
4212 #endif
4213 return stream;
4214 }
4215
4216 \f
4217 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
4218 for .file's that start within a function. If we are smuggling stabs, try to
4219 put out a MIPS ECOFF file and a stab. */
4220
4221 void
4222 mips_output_filename (stream, name)
4223 FILE *stream;
4224 char *name;
4225 {
4226 static int first_time = TRUE;
4227 char ltext_label_name[100];
4228
4229 if (first_time)
4230 {
4231 first_time = FALSE;
4232 SET_FILE_NUMBER ();
4233 current_function_file = name;
4234 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
4235 /* This tells mips-tfile that stabs will follow. */
4236 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
4237 fprintf (stream, "\t#@stabs\n");
4238 }
4239
4240 else if (write_symbols == DBX_DEBUG)
4241 {
4242 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
4243 fprintf (stream, "%s ", ASM_STABS_OP);
4244 output_quoted_string (stream, name);
4245 fprintf (stream, ",%d,0,0,%s\n", N_SOL, &ltext_label_name[1]);
4246 }
4247
4248 else if (name != current_function_file
4249 && strcmp (name, current_function_file) != 0)
4250 {
4251 if (inside_function && !TARGET_GAS)
4252 {
4253 if (!file_in_function_warning)
4254 {
4255 file_in_function_warning = TRUE;
4256 ignore_line_number = TRUE;
4257 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
4258 }
4259 }
4260 else
4261 {
4262 SET_FILE_NUMBER ();
4263 current_function_file = name;
4264 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
4265 }
4266 }
4267 }
4268
4269 \f
4270 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4271 as well as a .loc, since it is possible that MIPS ECOFF might not be
4272 able to represent the location for inlines that come from a different
4273 file. */
4274
4275 void
4276 mips_output_lineno (stream, line)
4277 FILE *stream;
4278 int line;
4279 {
4280 if (write_symbols == DBX_DEBUG)
4281 {
4282 ++sym_lineno;
4283 fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
4284 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
4285 LOCAL_LABEL_PREFIX, sym_lineno);
4286 }
4287
4288 else
4289 {
4290 fprintf (stream, "\n\t%s.loc\t%d %d\n",
4291 (ignore_line_number) ? "#" : "",
4292 num_source_filenames, line);
4293
4294 LABEL_AFTER_LOC (stream);
4295 }
4296 }
4297
4298 \f
4299 /* If defined, a C statement to be executed just prior to the
4300 output of assembler code for INSN, to modify the extracted
4301 operands so they will be output differently.
4302
4303 Here the argument OPVEC is the vector containing the operands
4304 extracted from INSN, and NOPERANDS is the number of elements of
4305 the vector which contain meaningful data for this insn. The
4306 contents of this vector are what will be used to convert the
4307 insn template into assembler code, so you can change the
4308 assembler output by changing the contents of the vector.
4309
4310 We use it to check if the current insn needs a nop in front of it
4311 because of load delays, and also to update the delay slot
4312 statistics. */
4313
4314 /* ??? There is no real need for this function, because it never actually
4315 emits a NOP anymore. */
4316
4317 void
4318 final_prescan_insn (insn, opvec, noperands)
4319 rtx insn;
4320 rtx opvec[];
4321 int noperands;
4322 {
4323 if (dslots_number_nops > 0)
4324 {
4325 rtx pattern = PATTERN (insn);
4326 int length = get_attr_length (insn);
4327
4328 /* Do we need to emit a NOP? */
4329 if (length == 0
4330 || (mips_load_reg != (rtx)0 && reg_mentioned_p (mips_load_reg, pattern))
4331 || (mips_load_reg2 != (rtx)0 && reg_mentioned_p (mips_load_reg2, pattern))
4332 || (mips_load_reg3 != (rtx)0 && reg_mentioned_p (mips_load_reg3, pattern))
4333 || (mips_load_reg4 != (rtx)0 && reg_mentioned_p (mips_load_reg4, pattern)))
4334 fputs ("\t#nop\n", asm_out_file);
4335
4336 else
4337 dslots_load_filled++;
4338
4339 while (--dslots_number_nops > 0)
4340 fputs ("\t#nop\n", asm_out_file);
4341
4342 mips_load_reg = (rtx)0;
4343 mips_load_reg2 = (rtx)0;
4344 mips_load_reg3 = (rtx)0;
4345 mips_load_reg4 = (rtx)0;
4346 }
4347
4348 if (TARGET_STATS)
4349 {
4350 enum rtx_code code = GET_CODE (insn);
4351 if (code == JUMP_INSN || code == CALL_INSN)
4352 dslots_jump_total++;
4353 }
4354 }
4355
4356 \f
4357 /* Output at beginning of assembler file.
4358 If we are optimizing to use the global pointer, create a temporary
4359 file to hold all of the text stuff, and write it out to the end.
4360 This is needed because the MIPS assembler is evidently one pass,
4361 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4362 declaration when the code is processed, it generates a two
4363 instruction sequence. */
4364
4365 void
4366 mips_asm_file_start (stream)
4367 FILE *stream;
4368 {
4369 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
4370
4371 /* Versions of the MIPS assembler before 2.20 generate errors
4372 if a branch inside of a .set noreorder section jumps to a
4373 label outside of the .set noreorder section. Revision 2.20
4374 just set nobopt silently rather than fixing the bug. */
4375
4376 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
4377 fprintf (stream, "\t.set\tnobopt\n");
4378
4379 /* Generate the pseudo ops that System V.4 wants. */
4380 #ifndef ABICALLS_ASM_OP
4381 #define ABICALLS_ASM_OP ".abicalls"
4382 #endif
4383 if (TARGET_ABICALLS)
4384 /* ??? but do not want this (or want pic0) if -non-shared? */
4385 fprintf (stream, "\t%s\n", ABICALLS_ASM_OP);
4386
4387 /* Start a section, so that the first .popsection directive is guaranteed
4388 to have a previously defined section to pop back to. */
4389 if (mips_abi != ABI_32)
4390 fprintf (stream, "\t.section\t.text\n");
4391
4392 /* This code exists so that we can put all externs before all symbol
4393 references. This is necessary for the assembler's global pointer
4394 optimizations to work. */
4395 /* ??? Current versions of gas do not require that externs occur before
4396 symbol references. This means that this code is unnecessary when
4397 gas is being used. This gas feature hasn't been well tested as yet
4398 though. */
4399 if (TARGET_GP_OPT)
4400 {
4401 asm_out_data_file = stream;
4402 asm_out_text_file = make_temp_file ();
4403 }
4404 else
4405 asm_out_data_file = asm_out_text_file = stream;
4406
4407 if (flag_verbose_asm)
4408 fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
4409 ASM_COMMENT_START,
4410 mips_section_threshold, mips_cpu_string, mips_isa);
4411 }
4412
4413 \f
4414 /* If we are optimizing the global pointer, emit the text section now
4415 and any small externs which did not have .comm, etc that are
4416 needed. Also, give a warning if the data area is more than 32K and
4417 -pic because 3 instructions are needed to reference the data
4418 pointers. */
4419
4420 void
4421 mips_asm_file_end (file)
4422 FILE *file;
4423 {
4424 char buffer[8192];
4425 tree name_tree;
4426 struct extern_list *p;
4427 int len;
4428
4429 if (HALF_PIC_P ())
4430 HALF_PIC_FINISH (file);
4431
4432 if (extern_head)
4433 {
4434 fputs ("\n", file);
4435
4436 for (p = extern_head; p != 0; p = p->next)
4437 {
4438 name_tree = get_identifier (p->name);
4439
4440 /* Positively ensure only one .extern for any given symbol. */
4441 if (! TREE_ASM_WRITTEN (name_tree))
4442 {
4443 TREE_ASM_WRITTEN (name_tree) = 1;
4444 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4445 if (p->size == -1)
4446 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
4447 else
4448 #endif
4449 {
4450 fputs ("\t.extern\t", file);
4451 assemble_name (file, p->name);
4452 fprintf (file, ", %d\n", p->size);
4453 }
4454 }
4455 }
4456 }
4457
4458 if (TARGET_GP_OPT)
4459 {
4460 fprintf (file, "\n\t.text\n");
4461 rewind (asm_out_text_file);
4462 if (ferror (asm_out_text_file))
4463 fatal_io_error (temp_filename);
4464
4465 while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
4466 if (fwrite (buffer, 1, len, file) != len)
4467 pfatal_with_name (asm_file_name);
4468
4469 if (len < 0)
4470 pfatal_with_name (temp_filename);
4471
4472 if (fclose (asm_out_text_file) != 0)
4473 pfatal_with_name (temp_filename);
4474
4475 #ifdef __MSDOS__
4476 unlink (temp_filename);
4477 #endif
4478 }
4479 }
4480
4481 \f
4482 /* Emit either a label, .comm, or .lcomm directive, and mark
4483 that the symbol is used, so that we don't emit an .extern
4484 for it in mips_asm_file_end. */
4485
4486 void
4487 mips_declare_object (stream, name, init_string, final_string, size)
4488 FILE *stream;
4489 char *name;
4490 char *init_string;
4491 char *final_string;
4492 int size;
4493 {
4494 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
4495 assemble_name (stream, name);
4496 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
4497
4498 if (TARGET_GP_OPT)
4499 {
4500 tree name_tree = get_identifier (name);
4501 TREE_ASM_WRITTEN (name_tree) = 1;
4502 }
4503 }
4504
4505 \f
4506 /* Output a double precision value to the assembler. If both the
4507 host and target are IEEE, emit the values in hex. */
4508
4509 void
4510 mips_output_double (stream, value)
4511 FILE *stream;
4512 REAL_VALUE_TYPE value;
4513 {
4514 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4515 long value_long[2];
4516 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
4517
4518 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4519 value_long[0], value, value_long[1]);
4520 #else
4521 fprintf (stream, "\t.double\t%.20g\n", value);
4522 #endif
4523 }
4524
4525
4526 /* Output a single precision value to the assembler. If both the
4527 host and target are IEEE, emit the values in hex. */
4528
4529 void
4530 mips_output_float (stream, value)
4531 FILE *stream;
4532 REAL_VALUE_TYPE value;
4533 {
4534 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4535 long value_long;
4536 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
4537
4538 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
4539 #else
4540 fprintf (stream, "\t.float\t%.12g\n", value);
4541 #endif
4542 }
4543
4544 \f
4545 /* Return TRUE if any register used in the epilogue is used. This to insure
4546 any insn put into the epilogue delay slots is safe. */
4547
4548 int
4549 epilogue_reg_mentioned_p (insn)
4550 rtx insn;
4551 {
4552 register char *fmt;
4553 register int i;
4554 register enum rtx_code code;
4555 register int regno;
4556
4557 if (insn == (rtx)0)
4558 return 0;
4559
4560 if (GET_CODE (insn) == LABEL_REF)
4561 return 0;
4562
4563 code = GET_CODE (insn);
4564 switch (code)
4565 {
4566 case REG:
4567 regno = REGNO (insn);
4568 if (regno == STACK_POINTER_REGNUM)
4569 return 1;
4570
4571 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
4572 return 1;
4573
4574 if (!call_used_regs[regno])
4575 return 1;
4576
4577 if (regno != MIPS_TEMP1_REGNUM && regno != MIPS_TEMP2_REGNUM)
4578 return 0;
4579
4580 if (!current_frame_info.initialized)
4581 compute_frame_size (get_frame_size ());
4582
4583 return (current_frame_info.total_size >= 32768);
4584
4585 case SCRATCH:
4586 case CC0:
4587 case PC:
4588 case CONST_INT:
4589 case CONST_DOUBLE:
4590 return 0;
4591 }
4592
4593 fmt = GET_RTX_FORMAT (code);
4594 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4595 {
4596 if (fmt[i] == 'E')
4597 {
4598 register int j;
4599 for (j = XVECLEN (insn, i) - 1; j >= 0; j--)
4600 if (epilogue_reg_mentioned_p (XVECEXP (insn, i, j)))
4601 return 1;
4602 }
4603 else if (fmt[i] == 'e' && epilogue_reg_mentioned_p (XEXP (insn, i)))
4604 return 1;
4605 }
4606
4607 return 0;
4608 }
4609 \f
4610 /* Return the bytes needed to compute the frame pointer from the current
4611 stack pointer.
4612
4613 Mips stack frames look like:
4614
4615 Before call After call
4616 +-----------------------+ +-----------------------+
4617 high | | | |
4618 mem. | | | |
4619 | caller's temps. | | caller's temps. |
4620 | | | |
4621 +-----------------------+ +-----------------------+
4622 | | | |
4623 | arguments on stack. | | arguments on stack. |
4624 | | | |
4625 +-----------------------+ +-----------------------+
4626 | 4 words to save | | 4 words to save |
4627 | arguments passed | | arguments passed |
4628 | in registers, even | | in registers, even |
4629 SP->| if not passed. | VFP->| if not passed. |
4630 +-----------------------+ +-----------------------+
4631 | |
4632 | fp register save |
4633 | |
4634 +-----------------------+
4635 | |
4636 | gp register save |
4637 | |
4638 +-----------------------+
4639 | |
4640 | local variables |
4641 | |
4642 +-----------------------+
4643 | |
4644 | alloca allocations |
4645 | |
4646 +-----------------------+
4647 | |
4648 | GP save for V.4 abi |
4649 | |
4650 +-----------------------+
4651 | |
4652 | arguments on stack |
4653 | |
4654 +-----------------------+
4655 | 4 words to save |
4656 | arguments passed |
4657 | in registers, even |
4658 low SP->| if not passed. |
4659 memory +-----------------------+
4660
4661 */
4662
4663 long
4664 compute_frame_size (size)
4665 int size; /* # of var. bytes allocated */
4666 {
4667 int regno;
4668 long total_size; /* # bytes that the entire frame takes up */
4669 long var_size; /* # bytes that variables take up */
4670 long args_size; /* # bytes that outgoing arguments take up */
4671 long extra_size; /* # extra bytes */
4672 long gp_reg_rounded; /* # bytes needed to store gp after rounding */
4673 long gp_reg_size; /* # bytes needed to store gp regs */
4674 long fp_reg_size; /* # bytes needed to store fp regs */
4675 long mask; /* mask of saved gp registers */
4676 long fmask; /* mask of saved fp registers */
4677 int fp_inc; /* 1 or 2 depending on the size of fp regs */
4678 long fp_bits; /* bitmask to use for each fp register */
4679
4680 gp_reg_size = 0;
4681 fp_reg_size = 0;
4682 mask = 0;
4683 fmask = 0;
4684 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
4685 var_size = MIPS_STACK_ALIGN (size);
4686 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
4687
4688 /* The MIPS 3.0 linker does not like functions that dynamically
4689 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4690 looks like we are trying to create a second frame pointer to the
4691 function, so allocate some stack space to make it happy. */
4692
4693 if (args_size == 0 && current_function_calls_alloca)
4694 args_size = 4*UNITS_PER_WORD;
4695
4696 total_size = var_size + args_size + extra_size;
4697
4698 /* Calculate space needed for gp registers. */
4699 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
4700 {
4701 if (MUST_SAVE_REGISTER (regno))
4702 {
4703 gp_reg_size += UNITS_PER_WORD;
4704 mask |= 1L << (regno - GP_REG_FIRST);
4705 }
4706 }
4707
4708 /* Calculate space needed for fp registers. */
4709 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
4710 {
4711 fp_inc = 1;
4712 fp_bits = 1;
4713 }
4714 else
4715 {
4716 fp_inc = 2;
4717 fp_bits = 3;
4718 }
4719
4720 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += fp_inc)
4721 {
4722 if (regs_ever_live[regno] && !call_used_regs[regno])
4723 {
4724 fp_reg_size += fp_inc * UNITS_PER_FPREG;
4725 fmask |= fp_bits << (regno - FP_REG_FIRST);
4726 }
4727 }
4728
4729 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
4730 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
4731
4732 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4733 for leaf routines (total_size == extra_size) to save the gp reg.
4734 The gp reg is callee saved in the 64 bit ABI, so all routines must
4735 save the gp reg. */
4736 if (total_size == extra_size && mips_abi == ABI_32)
4737 total_size = extra_size = 0;
4738 else if (TARGET_ABICALLS)
4739 {
4740 /* Add the context-pointer to the saved registers. */
4741 gp_reg_size += UNITS_PER_WORD;
4742 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
4743 total_size -= gp_reg_rounded;
4744 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
4745 total_size += gp_reg_rounded;
4746 }
4747
4748 /* Add in space reserved on the stack by the callee for storing arguments
4749 passed in registers. */
4750 if (mips_abi != ABI_32)
4751 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
4752
4753 /* Save other computed information. */
4754 current_frame_info.total_size = total_size;
4755 current_frame_info.var_size = var_size;
4756 current_frame_info.args_size = args_size;
4757 current_frame_info.extra_size = extra_size;
4758 current_frame_info.gp_reg_size = gp_reg_size;
4759 current_frame_info.fp_reg_size = fp_reg_size;
4760 current_frame_info.mask = mask;
4761 current_frame_info.fmask = fmask;
4762 current_frame_info.initialized = reload_completed;
4763 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
4764 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
4765
4766 if (mask)
4767 {
4768 unsigned long offset = (args_size + extra_size + var_size
4769 + gp_reg_size - UNITS_PER_WORD);
4770 current_frame_info.gp_sp_offset = offset;
4771 current_frame_info.gp_save_offset = offset - total_size;
4772 }
4773 else
4774 {
4775 current_frame_info.gp_sp_offset = 0;
4776 current_frame_info.gp_save_offset = 0;
4777 }
4778
4779
4780 if (fmask)
4781 {
4782 unsigned long offset = (args_size + extra_size + var_size
4783 + gp_reg_rounded + fp_reg_size
4784 - fp_inc * UNITS_PER_FPREG);
4785 current_frame_info.fp_sp_offset = offset;
4786 current_frame_info.fp_save_offset = offset - total_size + UNITS_PER_WORD;
4787 }
4788 else
4789 {
4790 current_frame_info.fp_sp_offset = 0;
4791 current_frame_info.fp_save_offset = 0;
4792 }
4793
4794 /* Ok, we're done. */
4795 return total_size;
4796 }
4797
4798 \f
4799 /* Common code to emit the insns (or to write the instructions to a file)
4800 to save/restore registers.
4801
4802 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4803 is not modified within save_restore_insns. */
4804
4805 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4806
4807 static void
4808 save_restore_insns (store_p, large_reg, large_offset, file)
4809 int store_p; /* true if this is prologue */
4810 rtx large_reg; /* register holding large offset constant or NULL */
4811 long large_offset; /* large constant offset value */
4812 FILE *file; /* file to write instructions to instead of making RTL */
4813 {
4814 long mask = current_frame_info.mask;
4815 long fmask = current_frame_info.fmask;
4816 int regno;
4817 rtx base_reg_rtx;
4818 long base_offset;
4819 long gp_offset;
4820 long fp_offset;
4821 long end_offset;
4822
4823 if (frame_pointer_needed && !BITSET_P (mask, FRAME_POINTER_REGNUM - GP_REG_FIRST))
4824 abort ();
4825
4826 if (mask == 0 && fmask == 0)
4827 return;
4828
4829 /* Save registers starting from high to low. The debuggers prefer
4830 at least the return register be stored at func+4, and also it
4831 allows us not to need a nop in the epilog if at least one
4832 register is reloaded in addition to return address. */
4833
4834 /* Save GP registers if needed. */
4835 if (mask)
4836 {
4837 /* Pick which pointer to use as a base register. For small
4838 frames, just use the stack pointer. Otherwise, use a
4839 temporary register. Save 2 cycles if the save area is near
4840 the end of a large frame, by reusing the constant created in
4841 the prologue/epilogue to adjust the stack frame. */
4842
4843 gp_offset = current_frame_info.gp_sp_offset;
4844 end_offset = gp_offset - (current_frame_info.gp_reg_size - UNITS_PER_WORD);
4845
4846 if (gp_offset < 0 || end_offset < 0)
4847 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
4848 gp_offset, end_offset);
4849
4850 else if (gp_offset < 32768)
4851 {
4852 base_reg_rtx = stack_pointer_rtx;
4853 base_offset = 0;
4854 }
4855
4856 else if (large_reg != (rtx)0
4857 && (((unsigned long)(large_offset - gp_offset)) < 32768)
4858 && (((unsigned long)(large_offset - end_offset)) < 32768))
4859 {
4860 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
4861 base_offset = large_offset;
4862 if (file == (FILE *)0)
4863 {
4864 if (TARGET_LONG64)
4865 emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
4866 else
4867 emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
4868 }
4869 else
4870 fprintf (file, "\t%s\t%s,%s,%s\n",
4871 TARGET_LONG64 ? "daddu" : "addu",
4872 reg_names[MIPS_TEMP2_REGNUM],
4873 reg_names[REGNO (large_reg)],
4874 reg_names[STACK_POINTER_REGNUM]);
4875 }
4876
4877 else
4878 {
4879 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
4880 base_offset = gp_offset;
4881 if (file == (FILE *)0)
4882 {
4883 emit_move_insn (base_reg_rtx, GEN_INT (gp_offset));
4884 if (TARGET_LONG64)
4885 emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
4886 else
4887 emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
4888 }
4889 else
4890 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
4891 reg_names[MIPS_TEMP2_REGNUM],
4892 (long)base_offset,
4893 (long)base_offset,
4894 TARGET_LONG64 ? "daddu" : "addu",
4895 reg_names[MIPS_TEMP2_REGNUM],
4896 reg_names[MIPS_TEMP2_REGNUM],
4897 reg_names[STACK_POINTER_REGNUM]);
4898 }
4899
4900 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
4901 {
4902 if (BITSET_P (mask, regno - GP_REG_FIRST))
4903 {
4904 if (file == (FILE *)0)
4905 {
4906 rtx reg_rtx = gen_rtx (REG, word_mode, regno);
4907 rtx mem_rtx = gen_rtx (MEM, word_mode,
4908 gen_rtx (PLUS, Pmode, base_reg_rtx,
4909 GEN_INT (gp_offset - base_offset)));
4910
4911 if (store_p)
4912 emit_move_insn (mem_rtx, reg_rtx);
4913 else if (!TARGET_ABICALLS || mips_abi != ABI_32
4914 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
4915 emit_move_insn (reg_rtx, mem_rtx);
4916 }
4917 else
4918 {
4919 if (store_p || !TARGET_ABICALLS || mips_abi != ABI_32
4920 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
4921 fprintf (file, "\t%s\t%s,%ld(%s)\n",
4922 (TARGET_64BIT
4923 ? (store_p) ? "sd" : "ld"
4924 : (store_p) ? "sw" : "lw"),
4925 reg_names[regno],
4926 gp_offset - base_offset,
4927 reg_names[REGNO(base_reg_rtx)]);
4928
4929 }
4930 gp_offset -= UNITS_PER_WORD;
4931 }
4932 }
4933 }
4934 else
4935 {
4936 base_reg_rtx = (rtx)0; /* Make sure these are initialized */
4937 base_offset = 0;
4938 }
4939
4940 /* Save floating point registers if needed. */
4941 if (fmask)
4942 {
4943 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
4944 int fp_size = fp_inc * UNITS_PER_FPREG;
4945
4946 /* Pick which pointer to use as a base register. */
4947 fp_offset = current_frame_info.fp_sp_offset;
4948 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
4949
4950 if (fp_offset < 0 || end_offset < 0)
4951 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
4952 fp_offset, end_offset);
4953
4954 else if (fp_offset < 32768)
4955 {
4956 base_reg_rtx = stack_pointer_rtx;
4957 base_offset = 0;
4958 }
4959
4960 else if (base_reg_rtx != (rtx)0
4961 && (((unsigned long)(base_offset - fp_offset)) < 32768)
4962 && (((unsigned long)(base_offset - end_offset)) < 32768))
4963 {
4964 ; /* already set up for gp registers above */
4965 }
4966
4967 else if (large_reg != (rtx)0
4968 && (((unsigned long)(large_offset - fp_offset)) < 32768)
4969 && (((unsigned long)(large_offset - end_offset)) < 32768))
4970 {
4971 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
4972 base_offset = large_offset;
4973 if (file == (FILE *)0)
4974 {
4975 if (TARGET_LONG64)
4976 emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
4977 else
4978 emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
4979 }
4980 else
4981 fprintf (file, "\t%s\t%s,%s,%s\n",
4982 TARGET_LONG64 ? "daddu" : "addu",
4983 reg_names[MIPS_TEMP2_REGNUM],
4984 reg_names[REGNO (large_reg)],
4985 reg_names[STACK_POINTER_REGNUM]);
4986 }
4987
4988 else
4989 {
4990 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
4991 base_offset = fp_offset;
4992 if (file == (FILE *)0)
4993 {
4994 emit_move_insn (base_reg_rtx, GEN_INT (fp_offset));
4995 if (TARGET_LONG64)
4996 emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
4997 else
4998 emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
4999 }
5000 else
5001 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5002 reg_names[MIPS_TEMP2_REGNUM],
5003 (long)base_offset,
5004 (long)base_offset,
5005 TARGET_LONG64 ? "daddu" : "addu",
5006 reg_names[MIPS_TEMP2_REGNUM],
5007 reg_names[MIPS_TEMP2_REGNUM],
5008 reg_names[STACK_POINTER_REGNUM]);
5009 }
5010
5011 for (regno = FP_REG_LAST-1; regno >= FP_REG_FIRST; regno -= fp_inc)
5012 {
5013 if (BITSET_P (fmask, regno - FP_REG_FIRST))
5014 {
5015 if (file == (FILE *)0)
5016 {
5017 enum machine_mode sz =
5018 TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5019 rtx reg_rtx = gen_rtx (REG, sz, regno);
5020 rtx mem_rtx = gen_rtx (MEM, sz,
5021 gen_rtx (PLUS, Pmode, base_reg_rtx,
5022 GEN_INT (fp_offset - base_offset)));
5023
5024 if (store_p)
5025 emit_move_insn (mem_rtx, reg_rtx);
5026 else
5027 emit_move_insn (reg_rtx, mem_rtx);
5028 }
5029 else
5030 fprintf (file, "\t%s\t%s,%ld(%s)\n",
5031 (TARGET_SINGLE_FLOAT
5032 ? ((store_p) ? "s.s" : "l.s")
5033 : ((store_p) ? "s.d" : "l.d")),
5034 reg_names[regno],
5035 fp_offset - base_offset,
5036 reg_names[REGNO(base_reg_rtx)]);
5037
5038
5039 fp_offset -= fp_size;
5040 }
5041 }
5042 }
5043 }
5044
5045 \f
5046 /* Set up the stack and frame (if desired) for the function. */
5047
5048 void
5049 function_prologue (file, size)
5050 FILE *file;
5051 int size;
5052 {
5053 char *fnname;
5054 long tsize = current_frame_info.total_size;
5055
5056 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
5057
5058 #ifdef SDB_DEBUGGING_INFO
5059 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
5060 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
5061 #endif
5062
5063 /* Get the function name the same way that toplev.c does before calling
5064 assemble_start_function. This is needed so that the name used here
5065 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5066 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
5067
5068 inside_function = 1;
5069 fputs ("\t.ent\t", file);
5070 assemble_name (file, fnname);
5071 fputs ("\n", file);
5072
5073 assemble_name (file, fnname);
5074 fputs (":\n", file);
5075
5076 fprintf (file, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5077 reg_names[ (frame_pointer_needed) ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ],
5078 tsize,
5079 reg_names[31 + GP_REG_FIRST],
5080 current_frame_info.var_size,
5081 current_frame_info.num_gp,
5082 current_frame_info.num_fp,
5083 current_function_outgoing_args_size,
5084 current_frame_info.extra_size);
5085
5086 fprintf (file, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
5087 current_frame_info.mask,
5088 current_frame_info.gp_save_offset,
5089 current_frame_info.fmask,
5090 current_frame_info.fp_save_offset);
5091
5092 if (TARGET_ABICALLS && mips_abi == ABI_32)
5093 {
5094 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5095
5096 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
5097 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
5098 if (tsize > 0)
5099 {
5100 fprintf (file, "\t%s\t%s,%s,%d\n",
5101 (TARGET_LONG64 ? "dsubu" : "subu"),
5102 sp_str, sp_str, tsize);
5103 fprintf (file, "\t.cprestore %d\n", current_frame_info.args_size);
5104 }
5105 }
5106 }
5107
5108 \f
5109 /* Expand the prologue into a bunch of separate insns. */
5110
5111 void
5112 mips_expand_prologue ()
5113 {
5114 int regno;
5115 long tsize;
5116 rtx tmp_rtx = (rtx)0;
5117 char *arg_name = (char *)0;
5118 tree fndecl = current_function_decl;
5119 tree fntype = TREE_TYPE (fndecl);
5120 tree fnargs = DECL_ARGUMENTS (fndecl);
5121 rtx next_arg_reg;
5122 int i;
5123 tree next_arg;
5124 tree cur_arg;
5125 CUMULATIVE_ARGS args_so_far;
5126
5127 /* If struct value address is treated as the first argument, make it so. */
5128 if (aggregate_value_p (DECL_RESULT (fndecl))
5129 && ! current_function_returns_pcc_struct
5130 && struct_value_incoming_rtx == 0)
5131 {
5132 tree type = build_pointer_type (fntype);
5133 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
5134 DECL_ARG_TYPE (function_result_decl) = type;
5135 TREE_CHAIN (function_result_decl) = fnargs;
5136 fnargs = function_result_decl;
5137 }
5138
5139 /* Determine the last argument, and get its name. */
5140
5141 INIT_CUMULATIVE_ARGS (args_so_far, fntype, (rtx)0, 0);
5142 regno = GP_ARG_FIRST;
5143
5144 for (cur_arg = fnargs; cur_arg != (tree)0; cur_arg = next_arg)
5145 {
5146 tree passed_type = DECL_ARG_TYPE (cur_arg);
5147 enum machine_mode passed_mode = TYPE_MODE (passed_type);
5148 rtx entry_parm;
5149
5150 if (TREE_ADDRESSABLE (passed_type))
5151 {
5152 passed_type = build_pointer_type (passed_type);
5153 passed_mode = Pmode;
5154 }
5155
5156 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
5157
5158 if (entry_parm)
5159 {
5160 int words;
5161
5162 /* passed in a register, so will get homed automatically */
5163 if (GET_MODE (entry_parm) == BLKmode)
5164 words = (int_size_in_bytes (passed_type) + 3) / 4;
5165 else
5166 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
5167
5168 regno = REGNO (entry_parm) + words - 1;
5169 }
5170 else
5171 {
5172 regno = GP_ARG_LAST+1;
5173 break;
5174 }
5175
5176 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
5177
5178 next_arg = TREE_CHAIN (cur_arg);
5179 if (next_arg == (tree)0)
5180 {
5181 if (DECL_NAME (cur_arg))
5182 arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg));
5183
5184 break;
5185 }
5186 }
5187
5188 /* In order to pass small structures by value in registers
5189 compatibly with the MIPS compiler, we need to shift the value
5190 into the high part of the register. Function_arg has encoded a
5191 PARALLEL rtx, holding a vector of adjustments to be made as the
5192 next_arg_reg variable, so we split up the insns, and emit them
5193 separately. */
5194
5195 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
5196 if (next_arg_reg != (rtx)0 && GET_CODE (next_arg_reg) == PARALLEL)
5197 {
5198 rtvec adjust = XVEC (next_arg_reg, 0);
5199 int num = GET_NUM_ELEM (adjust);
5200
5201 for (i = 0; i < num; i++)
5202 {
5203 rtx pattern = RTVEC_ELT (adjust, i);
5204 if (GET_CODE (pattern) != SET
5205 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
5206 abort_with_insn (pattern, "Insn is not a shift");
5207
5208 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
5209 emit_insn (pattern);
5210 }
5211 }
5212
5213 tsize = compute_frame_size (get_frame_size ());
5214
5215 /* If this function is a varargs function, store any registers that
5216 would normally hold arguments ($4 - $7) on the stack. */
5217 if (mips_abi == ABI_32
5218 && ((TYPE_ARG_TYPES (fntype) != 0
5219 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
5220 || (arg_name != (char *)0
5221 && ((arg_name[0] == '_' && strcmp (arg_name, "__builtin_va_alist") == 0)
5222 || (arg_name[0] == 'v' && strcmp (arg_name, "va_alist") == 0)))))
5223 {
5224 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
5225 rtx ptr = stack_pointer_rtx;
5226
5227 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
5228 if (TARGET_ABICALLS)
5229 offset += tsize;
5230
5231 for (; regno <= GP_ARG_LAST; regno++)
5232 {
5233 if (offset != 0)
5234 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
5235 emit_move_insn (gen_rtx (MEM, word_mode, ptr),
5236 gen_rtx (REG, word_mode, regno));
5237 offset += UNITS_PER_WORD;
5238 }
5239 }
5240
5241 if (tsize > 0)
5242 {
5243 rtx tsize_rtx = GEN_INT (tsize);
5244
5245 /* If we are doing svr4-abi, sp move is done by function_prologue. */
5246 if (!TARGET_ABICALLS || mips_abi != ABI_32)
5247 {
5248 if (tsize > 32767)
5249 {
5250 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
5251 emit_move_insn (tmp_rtx, tsize_rtx);
5252 tsize_rtx = tmp_rtx;
5253 }
5254
5255 if (TARGET_LONG64)
5256 emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
5257 tsize_rtx));
5258 else
5259 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
5260 tsize_rtx));
5261 }
5262
5263 save_restore_insns (TRUE, tmp_rtx, tsize, (FILE *)0);
5264
5265 if (frame_pointer_needed)
5266 {
5267 if (TARGET_64BIT)
5268 emit_insn (gen_movdi (frame_pointer_rtx, stack_pointer_rtx));
5269 else
5270 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
5271 }
5272
5273 if (TARGET_ABICALLS && mips_abi != ABI_32)
5274 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0)));
5275 }
5276
5277 /* If we are profiling, make sure no instructions are scheduled before
5278 the call to mcount. */
5279
5280 if (profile_flag || profile_block_flag)
5281 emit_insn (gen_blockage ());
5282 }
5283
5284 \f
5285 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
5286
5287 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5288 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5289
5290 void
5291 function_epilogue (file, size)
5292 FILE *file;
5293 int size;
5294 {
5295 char *fnname;
5296 long tsize;
5297 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5298 char *t1_str = reg_names[MIPS_TEMP1_REGNUM];
5299 rtx epilogue_delay = current_function_epilogue_delay_list;
5300 int noreorder = (epilogue_delay != 0);
5301 int noepilogue = FALSE;
5302 int load_nop = FALSE;
5303 int load_only_r31;
5304 rtx tmp_rtx = (rtx)0;
5305 rtx restore_rtx;
5306 int i;
5307
5308 /* The epilogue does not depend on any registers, but the stack
5309 registers, so we assume that if we have 1 pending nop, it can be
5310 ignored, and 2 it must be filled (2 nops occur for integer
5311 multiply and divide). */
5312
5313 if (dslots_number_nops > 0)
5314 {
5315 if (dslots_number_nops == 1)
5316 {
5317 dslots_number_nops = 0;
5318 dslots_load_filled++;
5319 }
5320 else
5321 {
5322 while (--dslots_number_nops > 0)
5323 fputs ("\t#nop\n", asm_out_file);
5324 }
5325 }
5326
5327 if (set_noat != 0)
5328 {
5329 set_noat = 0;
5330 fputs ("\t.set\tat\n", file);
5331 error ("internal gcc error: .set noat left on in epilogue");
5332 }
5333
5334 if (set_nomacro != 0)
5335 {
5336 set_nomacro = 0;
5337 fputs ("\t.set\tmacro\n", file);
5338 error ("internal gcc error: .set nomacro left on in epilogue");
5339 }
5340
5341 if (set_noreorder != 0)
5342 {
5343 set_noreorder = 0;
5344 fputs ("\t.set\treorder\n", file);
5345 error ("internal gcc error: .set noreorder left on in epilogue");
5346 }
5347
5348 if (set_volatile != 0)
5349 {
5350 set_volatile = 0;
5351 fprintf (file, "\t%s.set\tnovolatile\n", (TARGET_MIPS_AS) ? "" : "#");
5352 error ("internal gcc error: .set volatile left on in epilogue");
5353 }
5354
5355 size = MIPS_STACK_ALIGN (size);
5356 tsize = (!current_frame_info.initialized)
5357 ? compute_frame_size (size)
5358 : current_frame_info.total_size;
5359
5360 if (tsize == 0 && epilogue_delay == 0)
5361 {
5362 rtx insn = get_last_insn ();
5363
5364 /* If the last insn was a BARRIER, we don't have to write any code
5365 because a jump (aka return) was put there. */
5366 if (GET_CODE (insn) == NOTE)
5367 insn = prev_nonnote_insn (insn);
5368 if (insn && GET_CODE (insn) == BARRIER)
5369 noepilogue = TRUE;
5370
5371 noreorder = FALSE;
5372 }
5373
5374 if (!noepilogue)
5375 {
5376 /* In the reload sequence, we don't need to fill the load delay
5377 slots for most of the loads, also see if we can fill the final
5378 delay slot if not otherwise filled by the reload sequence. */
5379
5380 if (noreorder)
5381 fprintf (file, "\t.set\tnoreorder\n");
5382
5383 if (tsize > 32767)
5384 {
5385 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n", t1_str, (long)tsize, (long)tsize);
5386 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
5387 }
5388
5389 if (frame_pointer_needed)
5390 fprintf (file, "\tmove\t%s,%s\t\t\t# sp not trusted here\n",
5391 sp_str, reg_names[FRAME_POINTER_REGNUM]);
5392
5393 save_restore_insns (FALSE, tmp_rtx, tsize, file);
5394
5395 load_only_r31 = (((current_frame_info.mask
5396 & ~ (TARGET_ABICALLS && mips_abi == ABI_32
5397 ? PIC_OFFSET_TABLE_MASK : 0))
5398 == RA_MASK)
5399 && current_frame_info.fmask == 0);
5400
5401 if (noreorder)
5402 {
5403 /* If the only register saved is the return address, we need a
5404 nop, unless we have an instruction to put into it. Otherwise
5405 we don't since reloading multiple registers doesn't reference
5406 the register being loaded. */
5407
5408 if (load_only_r31)
5409 {
5410 if (epilogue_delay)
5411 final_scan_insn (XEXP (epilogue_delay, 0),
5412 file,
5413 1, /* optimize */
5414 -2, /* prescan */
5415 1); /* nopeepholes */
5416 else
5417 {
5418 fprintf (file, "\tnop\n");
5419 load_nop = TRUE;
5420 }
5421 }
5422
5423 fprintf (file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 31]);
5424
5425 if (tsize > 32767)
5426 fprintf (file, "\t%s\t%s,%s,%s\n",
5427 TARGET_LONG64 ? "daddu" : "addu",
5428 sp_str, sp_str, t1_str);
5429
5430 else if (tsize > 0)
5431 fprintf (file, "\t%s\t%s,%s,%d\n",
5432 TARGET_LONG64 ? "daddu" : "addu",
5433 sp_str, sp_str, tsize);
5434
5435 else if (!load_only_r31 && epilogue_delay != 0)
5436 final_scan_insn (XEXP (epilogue_delay, 0),
5437 file,
5438 1, /* optimize */
5439 -2, /* prescan */
5440 1); /* nopeepholes */
5441
5442 fprintf (file, "\t.set\treorder\n");
5443 }
5444
5445 else
5446 {
5447 if (tsize > 32767)
5448 fprintf (file, "\t%s\t%s,%s,%s\n",
5449 TARGET_LONG64 ? "daddu" : "addu",
5450 sp_str, sp_str, t1_str);
5451
5452 else if (tsize > 0)
5453 fprintf (file, "\t%s\t%s,%s,%d\n",
5454 TARGET_LONG64 ? "daddu" : "addu",
5455 sp_str, sp_str, tsize);
5456
5457 fprintf (file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 31]);
5458 }
5459 }
5460
5461 /* Get the function name the same way that toplev.c does before calling
5462 assemble_start_function. This is needed so that the name used here
5463 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5464 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
5465
5466 fputs ("\t.end\t", file);
5467 assemble_name (file, fnname);
5468 fputs ("\n", file);
5469
5470 if (TARGET_STATS)
5471 {
5472 int num_gp_regs = current_frame_info.gp_reg_size / 4;
5473 int num_fp_regs = current_frame_info.fp_reg_size / 8;
5474 int num_regs = num_gp_regs + num_fp_regs;
5475 char *name = fnname;
5476
5477 if (name[0] == '*')
5478 name++;
5479
5480 dslots_load_total += num_regs;
5481
5482 if (!noepilogue)
5483 dslots_jump_total++;
5484
5485 if (noreorder)
5486 {
5487 dslots_load_filled += num_regs;
5488
5489 /* If the only register saved is the return register, we
5490 can't fill this register's delay slot. */
5491
5492 if (load_only_r31 && epilogue_delay == 0)
5493 dslots_load_filled--;
5494
5495 if (tsize > 0 || (!load_only_r31 && epilogue_delay != 0))
5496 dslots_jump_filled++;
5497 }
5498
5499 fprintf (stderr,
5500 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5501 name,
5502 (frame_pointer_needed) ? 'y' : 'n',
5503 ((current_frame_info.mask & RA_MASK) != 0) ? 'n' : 'y',
5504 (current_function_calls_alloca) ? 'y' : 'n',
5505 (current_function_calls_setjmp) ? 'y' : 'n',
5506 (long)current_frame_info.total_size,
5507 (long)current_function_outgoing_args_size,
5508 num_gp_regs, num_fp_regs,
5509 dslots_load_total, dslots_load_filled,
5510 dslots_jump_total, dslots_jump_filled,
5511 num_refs[0], num_refs[1], num_refs[2]);
5512
5513 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
5514 {
5515 fprintf (stderr, " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
5516 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
5517 }
5518
5519 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
5520 {
5521 fprintf (stderr, " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
5522 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
5523 }
5524
5525 fputc ('\n', stderr);
5526 }
5527
5528 /* Reset state info for each function. */
5529 inside_function = FALSE;
5530 ignore_line_number = FALSE;
5531 dslots_load_total = 0;
5532 dslots_jump_total = 0;
5533 dslots_load_filled = 0;
5534 dslots_jump_filled = 0;
5535 num_refs[0] = 0;
5536 num_refs[1] = 0;
5537 num_refs[2] = 0;
5538 mips_load_reg = (rtx)0;
5539 mips_load_reg2 = (rtx)0;
5540 current_frame_info = zero_frame_info;
5541
5542 /* Restore the output file if optimizing the GP (optimizing the GP causes
5543 the text to be diverted to a tempfile, so that data decls come before
5544 references to the data). */
5545
5546 if (TARGET_GP_OPT)
5547 asm_out_file = asm_out_data_file;
5548 }
5549
5550 \f
5551 /* Expand the epilogue into a bunch of separate insns. */
5552
5553 void
5554 mips_expand_epilogue ()
5555 {
5556 long tsize = current_frame_info.total_size;
5557 rtx tsize_rtx = GEN_INT (tsize);
5558 rtx tmp_rtx = (rtx)0;
5559
5560 if (tsize > 32767)
5561 {
5562 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
5563 emit_move_insn (tmp_rtx, tsize_rtx);
5564 tsize_rtx = tmp_rtx;
5565 }
5566
5567 if (tsize > 0)
5568 {
5569 if (frame_pointer_needed)
5570 {
5571 if (TARGET_LONG64)
5572 emit_insn (gen_movdi (stack_pointer_rtx, frame_pointer_rtx));
5573 else
5574 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
5575 }
5576
5577 save_restore_insns (FALSE, tmp_rtx, tsize, (FILE *)0);
5578
5579 if (TARGET_LONG64)
5580 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
5581 tsize_rtx));
5582 else
5583 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
5584 tsize_rtx));
5585 }
5586
5587 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode, GP_REG_FIRST+31)));
5588 }
5589
5590 \f
5591 /* Define the number of delay slots needed for the function epilogue.
5592
5593 On the mips, we need a slot if either no stack has been allocated,
5594 or the only register saved is the return register. */
5595
5596 int
5597 mips_epilogue_delay_slots ()
5598 {
5599 if (!current_frame_info.initialized)
5600 (void) compute_frame_size (get_frame_size ());
5601
5602 if (current_frame_info.total_size == 0)
5603 return 1;
5604
5605 if (current_frame_info.mask == RA_MASK && current_frame_info.fmask == 0)
5606 return 1;
5607
5608 return 0;
5609 }
5610
5611 \f
5612 /* Return true if this function is known to have a null epilogue.
5613 This allows the optimizer to omit jumps to jumps if no stack
5614 was created. */
5615
5616 int
5617 simple_epilogue_p ()
5618 {
5619 if (!reload_completed)
5620 return 0;
5621
5622 if (current_frame_info.initialized)
5623 return current_frame_info.total_size == 0;
5624
5625 return (compute_frame_size (get_frame_size ())) == 0;
5626 }
5627 \f
5628 /* Choose the section to use for the constant rtx expression X that has
5629 mode MODE. */
5630
5631 mips_select_rtx_section (mode, x)
5632 enum machine_mode mode;
5633 rtx x;
5634 {
5635 if (TARGET_EMBEDDED_DATA)
5636 {
5637 /* For embedded applications, always put constants in read-only data,
5638 in order to reduce RAM usage. */
5639 READONLY_DATA_SECTION ();
5640 }
5641 else
5642 {
5643 /* For hosted applications, always put constants in small data if
5644 possible, as this gives the best performance. */
5645
5646 if (GET_MODE_SIZE (mode) <= mips_section_threshold
5647 && mips_section_threshold > 0)
5648 SMALL_DATA_SECTION ();
5649 else
5650 READONLY_DATA_SECTION ();
5651 }
5652 }
5653
5654 /* Choose the section to use for DECL. RELOC is true if its value contains
5655 any relocatable expression. */
5656
5657 mips_select_section (decl, reloc)
5658 tree decl;
5659 int reloc;
5660 {
5661 int size = int_size_in_bytes (TREE_TYPE (decl));
5662
5663 if (TARGET_EMBEDDED_PIC
5664 && TREE_CODE (decl) == STRING_CST
5665 && !flag_writable_strings)
5666 {
5667 /* For embedded position independent code, put constant strings
5668 in the text section, because the data section is limited to
5669 64K in size. */
5670
5671 text_section ();
5672 }
5673 else if (TARGET_EMBEDDED_DATA)
5674 {
5675 /* For embedded applications, always put an object in read-only data
5676 if possible, in order to reduce RAM usage. */
5677
5678 if (((TREE_CODE (decl) == VAR_DECL
5679 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
5680 && DECL_INITIAL (decl)
5681 && (DECL_INITIAL (decl) == error_mark_node
5682 || TREE_CONSTANT (DECL_INITIAL (decl))))
5683 /* Deal with calls from output_constant_def_contents. */
5684 || (TREE_CODE (decl) != VAR_DECL
5685 && (TREE_CODE (decl) != STRING_CST
5686 || !flag_writable_strings)))
5687 && ! (flag_pic && reloc))
5688 READONLY_DATA_SECTION ();
5689 else if (size > 0 && size <= mips_section_threshold)
5690 SMALL_DATA_SECTION ();
5691 else
5692 data_section ();
5693 }
5694 else
5695 {
5696 /* For hosted applications, always put an object in small data if
5697 possible, as this gives the best performance. */
5698
5699 if (size > 0 && size <= mips_section_threshold)
5700 SMALL_DATA_SECTION ();
5701 else if (((TREE_CODE (decl) == VAR_DECL
5702 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
5703 && DECL_INITIAL (decl)
5704 && (DECL_INITIAL (decl) == error_mark_node
5705 || TREE_CONSTANT (DECL_INITIAL (decl))))
5706 /* Deal with calls from output_constant_def_contents. */
5707 || (TREE_CODE (decl) != VAR_DECL
5708 && (TREE_CODE (decl) != STRING_CST
5709 || !flag_writable_strings)))
5710 && ! (flag_pic && reloc))
5711 READONLY_DATA_SECTION ();
5712 else
5713 data_section ();
5714 }
5715 }
5716 \f
5717 #ifdef MIPS_ABI_DEFAULT
5718 /* Support functions for the 64 bit ABI. */
5719
5720 /* Return register to use for a function return value with VALTYPE for function
5721 FUNC. */
5722
5723 rtx
5724 mips_function_value (valtype, func)
5725 tree valtype;
5726 tree func;
5727 {
5728 int reg = GP_RETURN;
5729 enum machine_mode mode = TYPE_MODE (valtype);
5730 enum mode_class mclass = GET_MODE_CLASS (mode);
5731
5732 /* ??? How should we return complex float? */
5733 if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
5734 reg = FP_RETURN;
5735 else if (TREE_CODE (valtype) == RECORD_TYPE && mips_abi != ABI_32)
5736 {
5737 /* A struct with only one or two floating point fields is returned in
5738 the floating point registers. */
5739 tree field, fields[2];
5740 int i;
5741
5742 for (i = 0, field = TYPE_FIELDS (valtype); field;
5743 field = TREE_CHAIN (field))
5744 {
5745 if (TREE_CODE (field) != FIELD_DECL)
5746 continue;
5747 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
5748 break;
5749
5750 fields[i++] = field;
5751 }
5752
5753 /* Must check i, so that we reject structures with no elements. */
5754 if (! field)
5755 {
5756 if (i == 1)
5757 {
5758 /* The structure has DImode, but we don't allow DImode values
5759 in FP registers, so we use a PARALLEL even though it isn't
5760 strictly necessary. */
5761 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
5762
5763 return gen_rtx (PARALLEL, mode,
5764 gen_rtvec (1,
5765 gen_rtx (EXPR_LIST, VOIDmode,
5766 gen_rtx (REG, field_mode, FP_RETURN),
5767 const0_rtx)));
5768 }
5769 else if (i == 2)
5770 {
5771 enum machine_mode first_mode
5772 = TYPE_MODE (TREE_TYPE (fields[0]));
5773 enum machine_mode second_mode
5774 = TYPE_MODE (TREE_TYPE (fields[1]));
5775 int first_offset
5776 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[0]));
5777 int second_offset
5778 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[1]));
5779
5780 return gen_rtx (PARALLEL, mode,
5781 gen_rtvec (2,
5782 gen_rtx (EXPR_LIST, VOIDmode,
5783 gen_rtx (REG, first_mode, FP_RETURN),
5784 GEN_INT (first_offset / BITS_PER_UNIT)),
5785 gen_rtx (EXPR_LIST, VOIDmode,
5786 gen_rtx (REG, second_mode, FP_RETURN + 2),
5787 GEN_INT (second_offset / BITS_PER_UNIT))));
5788 }
5789 }
5790 }
5791
5792 return gen_rtx (REG, mode, reg);
5793 }
5794 #endif
5795
5796 /* This function returns the register class required for a secondary
5797 register when copying between one of the registers in CLASS, and X,
5798 using MODE. If IN_P is nonzero, the copy is going from X to the
5799 register, otherwise the register is the source. A return value of
5800 NO_REGS means that no secondary register is required. */
5801
5802 enum reg_class
5803 mips_secondary_reload_class (class, mode, x, in_p)
5804 enum reg_class class;
5805 enum machine_mode mode;
5806 rtx x;
5807 int in_p;
5808 {
5809 int regno = -1;
5810
5811 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
5812 regno = true_regnum (x);
5813
5814 /* We always require a general register when copying anything to
5815 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
5816 to a general register, or when copying from register 0. */
5817 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
5818 {
5819 if (! in_p
5820 && GP_REG_P (regno)
5821 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
5822 return NO_REGS;
5823 return GR_REGS;
5824 }
5825 if (regno == HILO_REGNUM)
5826 {
5827 if (in_p
5828 && class == GR_REGS
5829 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
5830 return NO_REGS;
5831 return GR_REGS;
5832 }
5833
5834 /* Copying from HI or LO to anywhere other than a general register
5835 requires a general register. */
5836 if (class == HI_REG || class == LO_REG || class == MD_REGS)
5837 {
5838 if (GP_REG_P (regno))
5839 return NO_REGS;
5840 return GR_REGS;
5841 }
5842 if (MD_REG_P (regno))
5843 {
5844 if (class == GR_REGS)
5845 return NO_REGS;
5846 return GR_REGS;
5847 }
5848
5849 return NO_REGS;
5850 }