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(mips_isa_string): Add mips4 to comment.
[gcc.git] / gcc / config / mips / mips.c
1 /* Subroutines for insn-output.c for MIPS
2 Contributed by A. Lichnewsky, lich@inria.inria.fr.
3 Changes by Michael Meissner, meissner@osf.org.
4 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
5 Brendan Eich, brendan@microunity.com.
6 Copyright (C) 1989, 90, 91, 93, 94, 1995 Free Software Foundation, Inc.
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23
24 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
25 calling convention in 64 bit mode. It doesn't work though, and should
26 be replaced with something better designed. */
27
28 #include "config.h"
29 #include "rtl.h"
30 #include "regs.h"
31 #include "hard-reg-set.h"
32 #include "real.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "insn-flags.h"
36 #include "insn-attr.h"
37 #include "insn-codes.h"
38 #include "recog.h"
39 #include "output.h"
40
41 #undef MAX /* sys/param.h may also define these */
42 #undef MIN
43
44 #include <stdio.h>
45 #include <signal.h>
46 #include <sys/types.h>
47 #include <sys/file.h>
48 #include <ctype.h>
49 #include "tree.h"
50 #include "expr.h"
51 #include "flags.h"
52
53 #ifndef R_OK
54 #define R_OK 4
55 #define W_OK 2
56 #define X_OK 1
57 #endif
58
59 #if defined(USG) || defined(NO_STAB_H)
60 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
61 #else
62 #include <stab.h> /* On BSD, use the system's stab.h. */
63 #endif /* not USG */
64
65 #ifdef __GNU_STAB__
66 #define STAB_CODE_TYPE enum __stab_debug_code
67 #else
68 #define STAB_CODE_TYPE int
69 #endif
70
71 extern void abort ();
72 extern int atoi ();
73 extern char *getenv ();
74 extern char *mktemp ();
75
76 extern rtx adj_offsettable_operand ();
77 extern rtx copy_to_reg ();
78 extern void error ();
79 extern void fatal ();
80 extern tree lookup_name ();
81 extern void pfatal_with_name ();
82 extern void warning ();
83
84 extern tree current_function_decl;
85 extern FILE *asm_out_file;
86
87 /* Enumeration for all of the relational tests, so that we can build
88 arrays indexed by the test type, and not worry about the order
89 of EQ, NE, etc. */
90
91 enum internal_test {
92 ITEST_EQ,
93 ITEST_NE,
94 ITEST_GT,
95 ITEST_GE,
96 ITEST_LT,
97 ITEST_LE,
98 ITEST_GTU,
99 ITEST_GEU,
100 ITEST_LTU,
101 ITEST_LEU,
102 ITEST_MAX
103 };
104
105 /* Global variables for machine-dependent things. */
106
107 /* Threshold for data being put into the small data/bss area, instead
108 of the normal data area (references to the small data/bss area take
109 1 instruction, and use the global pointer, references to the normal
110 data area takes 2 instructions). */
111 int mips_section_threshold = -1;
112
113 /* Count the number of .file directives, so that .loc is up to date. */
114 int num_source_filenames = 0;
115
116 /* Count the number of sdb related labels are generated (to find block
117 start and end boundaries). */
118 int sdb_label_count = 0;
119
120 /* Next label # for each statment for Silicon Graphics IRIS systems. */
121 int sym_lineno = 0;
122
123 /* Non-zero if inside of a function, because the stupid MIPS asm can't
124 handle .files inside of functions. */
125 int inside_function = 0;
126
127 /* Files to separate the text and the data output, so that all of the data
128 can be emitted before the text, which will mean that the assembler will
129 generate smaller code, based on the global pointer. */
130 FILE *asm_out_data_file;
131 FILE *asm_out_text_file;
132
133 /* Linked list of all externals that are to be emitted when optimizing
134 for the global pointer if they haven't been declared by the end of
135 the program with an appropriate .comm or initialization. */
136
137 struct extern_list {
138 struct extern_list *next; /* next external */
139 char *name; /* name of the external */
140 int size; /* size in bytes */
141 } *extern_head = 0;
142
143 /* Name of the file containing the current function. */
144 char *current_function_file = "";
145
146 /* Warning given that Mips ECOFF can't support changing files
147 within a function. */
148 int file_in_function_warning = FALSE;
149
150 /* Whether to suppress issuing .loc's because the user attempted
151 to change the filename within a function. */
152 int ignore_line_number = FALSE;
153
154 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
155 int set_noreorder;
156 int set_noat;
157 int set_nomacro;
158 int set_volatile;
159
160 /* The next branch instruction is a branch likely, not branch normal. */
161 int mips_branch_likely;
162
163 /* Count of delay slots and how many are filled. */
164 int dslots_load_total;
165 int dslots_load_filled;
166 int dslots_jump_total;
167 int dslots_jump_filled;
168
169 /* # of nops needed by previous insn */
170 int dslots_number_nops;
171
172 /* Number of 1/2/3 word references to data items (ie, not jal's). */
173 int num_refs[3];
174
175 /* registers to check for load delay */
176 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
177
178 /* Cached operands, and operator to compare for use in set/branch on
179 condition codes. */
180 rtx branch_cmp[2];
181
182 /* what type of branch to use */
183 enum cmp_type branch_type;
184
185 /* Number of previously seen half-pic pointers and references. */
186 static int prev_half_pic_ptrs = 0;
187 static int prev_half_pic_refs = 0;
188
189 /* which cpu are we scheduling for */
190 enum processor_type mips_cpu;
191
192 /* which instruction set architecture to use. */
193 int mips_isa;
194
195 /* Strings to hold which cpu and instruction set architecture to use. */
196 char *mips_cpu_string; /* for -mcpu=<xxx> */
197 char *mips_isa_string; /* for -mips{1,2,3,4} */
198
199 /* Generating calls to position independent functions? */
200 enum mips_abicalls_type mips_abicalls;
201
202 /* High and low marks for floating point values which we will accept
203 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
204 initialized in override_options. */
205 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
206
207 /* Array giving truth value on whether or not a given hard register
208 can support a given mode. */
209 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
210
211 /* Current frame information calculated by compute_frame_size. */
212 struct mips_frame_info current_frame_info;
213
214 /* Zero structure to initialize current_frame_info. */
215 struct mips_frame_info zero_frame_info;
216
217 /* Temporary filename used to buffer .text until end of program
218 for -mgpopt. */
219 static char *temp_filename;
220
221 /* Pseudo-reg holding the address of the current function when
222 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
223 by mips_finalize_pic if it was created. */
224 rtx embedded_pic_fnaddr_rtx;
225
226 /* List of all MIPS punctuation characters used by print_operand. */
227 char mips_print_operand_punct[256];
228
229 /* Map GCC register number to debugger register number. */
230 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
231
232 /* Buffer to use to enclose a load/store operation with %{ %} to
233 turn on .set volatile. */
234 static char volatile_buffer[60];
235
236 /* Hardware names for the registers. If -mrnames is used, this
237 will be overwritten with mips_sw_reg_names. */
238
239 char mips_reg_names[][8] =
240 {
241 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
242 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
243 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
244 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
245 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
246 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
247 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
248 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
249 "hi", "lo", "$fcr31"
250 };
251
252 /* Mips software names for the registers, used to overwrite the
253 mips_reg_names array. */
254
255 char mips_sw_reg_names[][8] =
256 {
257 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
258 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
259 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
260 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
261 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
262 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
263 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
264 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
265 "hi", "lo", "$fcr31"
266 };
267
268 /* Map hard register number to register class */
269 enum reg_class mips_regno_to_class[] =
270 {
271 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
272 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
273 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
274 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
275 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
276 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
277 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
278 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
279 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
280 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
281 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
282 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
283 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
284 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
285 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
286 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
287 HI_REG, LO_REG, ST_REGS
288 };
289
290 /* Map register constraint character to register class. */
291 enum reg_class mips_char_to_class[256] =
292 {
293 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
294 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
295 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
296 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
297 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
298 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
299 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
300 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
301 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
302 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
303 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
304 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
305 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
306 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
307 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
308 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
309 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
310 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
311 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
312 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
313 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
314 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
315 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
316 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
317 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
318 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
319 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
320 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
321 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
322 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
323 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
324 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
325 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
326 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
327 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
328 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
329 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
330 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
331 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
332 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
333 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
334 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
335 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
336 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
337 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
338 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
339 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
340 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
341 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
342 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
343 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
344 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
345 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
346 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
347 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
348 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
349 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
350 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
351 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
352 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
353 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
354 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
355 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
356 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
357 };
358
359 \f
360 /* Return truth value of whether OP can be used as an operands
361 where a register or 16 bit unsigned integer is needed. */
362
363 int
364 uns_arith_operand (op, mode)
365 rtx op;
366 enum machine_mode mode;
367 {
368 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
369 return TRUE;
370
371 return register_operand (op, mode);
372 }
373
374 /* Return truth value of whether OP can be used as an operands
375 where a 16 bit integer is needed */
376
377 int
378 arith_operand (op, mode)
379 rtx op;
380 enum machine_mode mode;
381 {
382 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
383 return TRUE;
384
385 return register_operand (op, mode);
386 }
387
388 /* Return truth value of whether OP can be used as an operand in a two
389 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
390
391 int
392 arith32_operand (op, mode)
393 rtx op;
394 enum machine_mode mode;
395 {
396 if (GET_CODE (op) == CONST_INT)
397 return TRUE;
398
399 return register_operand (op, mode);
400 }
401
402 /* Return truth value of whether OP is a integer which fits in 16 bits */
403
404 int
405 small_int (op, mode)
406 rtx op;
407 enum machine_mode mode;
408 {
409 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
410 }
411
412 /* Return truth value of whether OP is a 32 bit integer which is too big to
413 be loaded with one instruction. */
414
415 int
416 large_int (op, mode)
417 rtx op;
418 enum machine_mode mode;
419 {
420 HOST_WIDE_INT value;
421
422 if (GET_CODE (op) != CONST_INT)
423 return FALSE;
424
425 value = INTVAL (op);
426 if ((value & ~0x0000ffff) == 0) /* ior reg,$r0,value */
427 return FALSE;
428
429 if (((unsigned long)(value + 32768)) <= 32767) /* subu reg,$r0,value */
430 return FALSE;
431
432 if ((value & 0x0000ffff) == 0) /* lui reg,value>>16 */
433 return FALSE;
434
435 return TRUE;
436 }
437
438 /* Return truth value of whether OP is a register or the constant 0. */
439
440 int
441 reg_or_0_operand (op, mode)
442 rtx op;
443 enum machine_mode mode;
444 {
445 switch (GET_CODE (op))
446 {
447 default:
448 break;
449
450 case CONST_INT:
451 return (INTVAL (op) == 0);
452
453 case CONST_DOUBLE:
454 if (op != CONST0_RTX (mode))
455 return FALSE;
456
457 return TRUE;
458
459 case REG:
460 case SUBREG:
461 return register_operand (op, mode);
462 }
463
464 return FALSE;
465 }
466
467 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
468
469 int
470 mips_const_double_ok (op, mode)
471 rtx op;
472 enum machine_mode mode;
473 {
474 REAL_VALUE_TYPE d;
475
476 if (GET_CODE (op) != CONST_DOUBLE)
477 return FALSE;
478
479 if (mode == VOIDmode)
480 return TRUE;
481
482 if (mode != SFmode && mode != DFmode)
483 return FALSE;
484
485 if (op == CONST0_RTX (mode))
486 return TRUE;
487
488 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
489 if (ABI_64BIT)
490 return FALSE;
491
492 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
493
494 if (REAL_VALUE_ISNAN (d))
495 return FALSE;
496
497 if (REAL_VALUE_NEGATIVE (d))
498 d = REAL_VALUE_NEGATE (d);
499
500 if (mode == DFmode)
501 {
502 if (REAL_VALUES_LESS (d, dfhigh)
503 && REAL_VALUES_LESS (dflow, d))
504 return TRUE;
505 }
506 else
507 {
508 if (REAL_VALUES_LESS (d, sfhigh)
509 && REAL_VALUES_LESS (sflow, d))
510 return TRUE;
511 }
512
513 return FALSE;
514 }
515
516 /* Return truth value if a memory operand fits in a single instruction
517 (ie, register + small offset). */
518
519 int
520 simple_memory_operand (op, mode)
521 rtx op;
522 enum machine_mode mode;
523 {
524 rtx addr, plus0, plus1;
525
526 /* Eliminate non-memory operations */
527 if (GET_CODE (op) != MEM)
528 return FALSE;
529
530 /* dword operations really put out 2 instructions, so eliminate them. */
531 if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD)
532 return FALSE;
533
534 /* Decode the address now. */
535 addr = XEXP (op, 0);
536 switch (GET_CODE (addr))
537 {
538 default:
539 break;
540
541 case REG:
542 return TRUE;
543
544 case CONST_INT:
545 return SMALL_INT (op);
546
547 case PLUS:
548 plus0 = XEXP (addr, 0);
549 plus1 = XEXP (addr, 1);
550 if (GET_CODE (plus0) == REG
551 && GET_CODE (plus1) == CONST_INT
552 && SMALL_INT (plus1))
553 return TRUE;
554
555 else if (GET_CODE (plus1) == REG
556 && GET_CODE (plus0) == CONST_INT
557 && SMALL_INT (plus0))
558 return TRUE;
559
560 else
561 return FALSE;
562
563 #if 0
564 /* We used to allow small symbol refs here (ie, stuff in .sdata
565 or .sbss), but this causes some bugs in G++. Also, it won't
566 interfere if the MIPS linker rewrites the store instruction
567 because the function is PIC. */
568
569 case LABEL_REF: /* never gp relative */
570 break;
571
572 case CONST:
573 /* If -G 0, we can never have a GP relative memory operation.
574 Also, save some time if not optimizing. */
575 if (!TARGET_GP_OPT)
576 return FALSE;
577
578 {
579 rtx offset = const0_rtx;
580 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
581 if (GET_CODE (op) != SYMBOL_REF)
582 return FALSE;
583
584 /* let's be paranoid.... */
585 if (! SMALL_INT (offset))
586 return FALSE;
587 }
588 /* fall through */
589
590 case SYMBOL_REF:
591 return SYMBOL_REF_FLAG (addr);
592 #endif
593 }
594
595 return FALSE;
596 }
597
598 /* Return true if the code of this rtx pattern is EQ or NE. */
599
600 int
601 equality_op (op, mode)
602 rtx op;
603 enum machine_mode mode;
604 {
605 if (mode != GET_MODE (op))
606 return FALSE;
607
608 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
609 }
610
611 /* Return true if the code is a relational operations (EQ, LE, etc.) */
612
613 int
614 cmp_op (op, mode)
615 rtx op;
616 enum machine_mode mode;
617 {
618 if (mode != GET_MODE (op))
619 return FALSE;
620
621 return (GET_RTX_CLASS (GET_CODE (op)) == '<');
622 }
623
624 /* Return true if the operand is either the PC or a label_ref. */
625
626 int
627 pc_or_label_operand (op, mode)
628 rtx op;
629 enum machine_mode mode;
630 {
631 if (op == pc_rtx)
632 return TRUE;
633
634 if (GET_CODE (op) == LABEL_REF)
635 return TRUE;
636
637 return FALSE;
638 }
639
640 /* Test for a valid operand for a call instruction.
641 Don't allow the arg pointer register or virtual regs
642 since they may change into reg + const, which the patterns
643 can't handle yet. */
644
645 int
646 call_insn_operand (op, mode)
647 rtx op;
648 enum machine_mode mode;
649 {
650 if (GET_CODE (op) == MEM
651 && (CONSTANT_ADDRESS_P (XEXP (op, 0))
652 || (GET_CODE (XEXP (op, 0)) == REG
653 && XEXP (op, 0) != arg_pointer_rtx
654 && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
655 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
656 return 1;
657 return 0;
658 }
659 \f
660 /* Returns an operand string for the given instruction's delay slot,
661 after updating filled delay slot statistics.
662
663 We assume that operands[0] is the target register that is set.
664
665 In order to check the next insn, most of this functionality is moved
666 to FINAL_PRESCAN_INSN, and we just set the global variables that
667 it needs. */
668
669 /* ??? This function no longer does anything useful, because final_prescan_insn
670 now will never emit a nop. */
671
672 char *
673 mips_fill_delay_slot (ret, type, operands, cur_insn)
674 char *ret; /* normal string to return */
675 enum delay_type type; /* type of delay */
676 rtx operands[]; /* operands to use */
677 rtx cur_insn; /* current insn */
678 {
679 register rtx set_reg;
680 register enum machine_mode mode;
681 register rtx next_insn = (cur_insn) ? NEXT_INSN (cur_insn) : (rtx)0;
682 register int num_nops;
683
684 if (type == DELAY_LOAD || type == DELAY_FCMP)
685 num_nops = 1;
686
687 else if (type == DELAY_HILO)
688 num_nops = 2;
689
690 else
691 num_nops = 0;
692
693 /* Make sure that we don't put nop's after labels. */
694 next_insn = NEXT_INSN (cur_insn);
695 while (next_insn != (rtx)0 && GET_CODE (next_insn) == NOTE)
696 next_insn = NEXT_INSN (next_insn);
697
698 dslots_load_total += num_nops;
699 if (TARGET_DEBUG_F_MODE
700 || !optimize
701 || type == DELAY_NONE
702 || operands == (rtx *)0
703 || cur_insn == (rtx)0
704 || next_insn == (rtx)0
705 || GET_CODE (next_insn) == CODE_LABEL
706 || (set_reg = operands[0]) == (rtx)0)
707 {
708 dslots_number_nops = 0;
709 mips_load_reg = (rtx)0;
710 mips_load_reg2 = (rtx)0;
711 mips_load_reg3 = (rtx)0;
712 mips_load_reg4 = (rtx)0;
713 return ret;
714 }
715
716 set_reg = operands[0];
717 if (set_reg == (rtx)0)
718 return ret;
719
720 while (GET_CODE (set_reg) == SUBREG)
721 set_reg = SUBREG_REG (set_reg);
722
723 mode = GET_MODE (set_reg);
724 dslots_number_nops = num_nops;
725 mips_load_reg = set_reg;
726 if (GET_MODE_SIZE (mode)
727 > (FP_REG_P (set_reg) ? UNITS_PER_FPREG : UNITS_PER_WORD))
728 mips_load_reg2 = gen_rtx (REG, SImode, REGNO (set_reg) + 1);
729 else
730 mips_load_reg2 = 0;
731
732 if (type == DELAY_HILO)
733 {
734 mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST);
735 mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1);
736 }
737 else
738 {
739 mips_load_reg3 = 0;
740 mips_load_reg4 = 0;
741 }
742
743 return ret;
744 }
745
746 \f
747 /* Determine whether a memory reference takes one (based off of the GP pointer),
748 two (normal), or three (label + reg) instructions, and bump the appropriate
749 counter for -mstats. */
750
751 void
752 mips_count_memory_refs (op, num)
753 rtx op;
754 int num;
755 {
756 int additional = 0;
757 int n_words = 0;
758 rtx addr, plus0, plus1;
759 enum rtx_code code0, code1;
760 int looping;
761
762 if (TARGET_DEBUG_B_MODE)
763 {
764 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
765 debug_rtx (op);
766 }
767
768 /* Skip MEM if passed, otherwise handle movsi of address. */
769 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
770
771 /* Loop, going through the address RTL */
772 do
773 {
774 looping = FALSE;
775 switch (GET_CODE (addr))
776 {
777 default:
778 break;
779
780 case REG:
781 case CONST_INT:
782 break;
783
784 case PLUS:
785 plus0 = XEXP (addr, 0);
786 plus1 = XEXP (addr, 1);
787 code0 = GET_CODE (plus0);
788 code1 = GET_CODE (plus1);
789
790 if (code0 == REG)
791 {
792 additional++;
793 addr = plus1;
794 looping = TRUE;
795 continue;
796 }
797
798 if (code0 == CONST_INT)
799 {
800 addr = plus1;
801 looping = TRUE;
802 continue;
803 }
804
805 if (code1 == REG)
806 {
807 additional++;
808 addr = plus0;
809 looping = TRUE;
810 continue;
811 }
812
813 if (code1 == CONST_INT)
814 {
815 addr = plus0;
816 looping = TRUE;
817 continue;
818 }
819
820 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
821 {
822 addr = plus0;
823 looping = TRUE;
824 continue;
825 }
826
827 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
828 {
829 addr = plus1;
830 looping = TRUE;
831 continue;
832 }
833
834 break;
835
836 case LABEL_REF:
837 n_words = 2; /* always 2 words */
838 break;
839
840 case CONST:
841 addr = XEXP (addr, 0);
842 looping = TRUE;
843 continue;
844
845 case SYMBOL_REF:
846 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
847 break;
848 }
849 }
850 while (looping);
851
852 if (n_words == 0)
853 return;
854
855 n_words += additional;
856 if (n_words > 3)
857 n_words = 3;
858
859 num_refs[n_words-1] += num;
860 }
861
862 \f
863 /* Return RTL for the offset from the current function to the
864 argument. */
865
866 rtx
867 embedded_pic_offset (x)
868 rtx x;
869 {
870 if (embedded_pic_fnaddr_rtx == NULL)
871 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
872 return gen_rtx (CONST, Pmode,
873 gen_rtx (MINUS, Pmode, x,
874 XEXP (DECL_RTL (current_function_decl), 0)));
875 }
876
877 /* Return the appropriate instructions to move one operand to another. */
878
879 char *
880 mips_move_1word (operands, insn, unsignedp)
881 rtx operands[];
882 rtx insn;
883 int unsignedp;
884 {
885 char *ret = 0;
886 rtx op0 = operands[0];
887 rtx op1 = operands[1];
888 enum rtx_code code0 = GET_CODE (op0);
889 enum rtx_code code1 = GET_CODE (op1);
890 enum machine_mode mode = GET_MODE (op0);
891 int subreg_word0 = 0;
892 int subreg_word1 = 0;
893 enum delay_type delay = DELAY_NONE;
894
895 while (code0 == SUBREG)
896 {
897 subreg_word0 += SUBREG_WORD (op0);
898 op0 = SUBREG_REG (op0);
899 code0 = GET_CODE (op0);
900 }
901
902 while (code1 == SUBREG)
903 {
904 subreg_word1 += SUBREG_WORD (op1);
905 op1 = SUBREG_REG (op1);
906 code1 = GET_CODE (op1);
907 }
908
909 if (code0 == REG)
910 {
911 int regno0 = REGNO (op0) + subreg_word0;
912
913 if (code1 == REG)
914 {
915 int regno1 = REGNO (op1) + subreg_word1;
916
917 /* Just in case, don't do anything for assigning a register
918 to itself, unless we are filling a delay slot. */
919 if (regno0 == regno1 && set_nomacro == 0)
920 ret = "";
921
922 else if (GP_REG_P (regno0))
923 {
924 if (GP_REG_P (regno1))
925 ret = "move\t%0,%1";
926
927 else if (MD_REG_P (regno1))
928 {
929 delay = DELAY_HILO;
930 ret = "mf%1\t%0";
931 }
932
933 else
934 {
935 delay = DELAY_LOAD;
936 if (FP_REG_P (regno1))
937 ret = "mfc1\t%0,%1";
938
939 else if (regno1 == FPSW_REGNUM)
940 ret = "cfc1\t%0,$31";
941 }
942 }
943
944 else if (FP_REG_P (regno0))
945 {
946 if (GP_REG_P (regno1))
947 {
948 delay = DELAY_LOAD;
949 ret = "mtc1\t%1,%0";
950 }
951
952 if (FP_REG_P (regno1))
953 ret = "mov.s\t%0,%1";
954 }
955
956 else if (MD_REG_P (regno0))
957 {
958 if (GP_REG_P (regno1))
959 {
960 delay = DELAY_HILO;
961 ret = "mt%0\t%1";
962 }
963 }
964
965 else if (regno0 == FPSW_REGNUM)
966 {
967 if (GP_REG_P (regno1))
968 {
969 delay = DELAY_LOAD;
970 ret = "ctc1\t%0,$31";
971 }
972 }
973 }
974
975 else if (code1 == MEM)
976 {
977 delay = DELAY_LOAD;
978
979 if (TARGET_STATS)
980 mips_count_memory_refs (op1, 1);
981
982 if (GP_REG_P (regno0))
983 {
984 /* For loads, use the mode of the memory item, instead of the
985 target, so zero/sign extend can use this code as well. */
986 switch (GET_MODE (op1))
987 {
988 default:
989 break;
990 case SFmode:
991 ret = "lw\t%0,%1";
992 break;
993 case SImode:
994 ret = ((unsignedp && TARGET_64BIT)
995 ? "lwu\t%0,%1"
996 : "lw\t%0,%1");
997 break;
998 case HImode:
999 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1000 break;
1001 case QImode:
1002 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1003 break;
1004 }
1005 }
1006
1007 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1008 ret = "l.s\t%0,%1";
1009
1010 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1011 {
1012 int i = strlen (ret);
1013 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1014 abort ();
1015
1016 sprintf (volatile_buffer, "%%{%s%%}", ret);
1017 ret = volatile_buffer;
1018 }
1019 }
1020
1021 else if (code1 == CONST_INT
1022 || (code1 == CONST_DOUBLE
1023 && GET_MODE (op1) == VOIDmode))
1024 {
1025 if (code1 == CONST_DOUBLE)
1026 {
1027 /* This can happen when storing constants into long long
1028 bitfields. Just store the least significant word of
1029 the value. */
1030 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1031 }
1032
1033 if (INTVAL (op1) == 0)
1034 {
1035 if (GP_REG_P (regno0))
1036 ret = "move\t%0,%z1";
1037
1038 else if (FP_REG_P (regno0))
1039 {
1040 delay = DELAY_LOAD;
1041 ret = "mtc1\t%z1,%0";
1042 }
1043 }
1044
1045 else if (GP_REG_P (regno0))
1046 ret = (INTVAL (op1) < 0) ? "li\t%0,%1\t\t\t# %X1" : "li\t%0,%X1\t\t# %1";
1047 }
1048
1049 else if (code1 == CONST_DOUBLE && mode == SFmode)
1050 {
1051 if (op1 == CONST0_RTX (SFmode))
1052 {
1053 if (GP_REG_P (regno0))
1054 ret = "move\t%0,%.";
1055
1056 else if (FP_REG_P (regno0))
1057 {
1058 delay = DELAY_LOAD;
1059 ret = "mtc1\t%.,%0";
1060 }
1061 }
1062
1063 else
1064 {
1065 delay = DELAY_LOAD;
1066 ret = "li.s\t%0,%1";
1067 }
1068 }
1069
1070 else if (code1 == LABEL_REF)
1071 {
1072 if (TARGET_STATS)
1073 mips_count_memory_refs (op1, 1);
1074
1075 ret = "la\t%0,%a1";
1076 }
1077
1078 else if (code1 == SYMBOL_REF || code1 == CONST)
1079 {
1080 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
1081 {
1082 rtx offset = const0_rtx;
1083
1084 if (GET_CODE (op1) == CONST)
1085 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
1086
1087 if (GET_CODE (op1) == SYMBOL_REF)
1088 {
1089 operands[2] = HALF_PIC_PTR (op1);
1090
1091 if (TARGET_STATS)
1092 mips_count_memory_refs (operands[2], 1);
1093
1094 if (INTVAL (offset) == 0)
1095 {
1096 delay = DELAY_LOAD;
1097 ret = (unsignedp && TARGET_64BIT
1098 ? "lwu\t%0,%2"
1099 : "lw\t%0,%2");
1100 }
1101 else
1102 {
1103 dslots_load_total++;
1104 operands[3] = offset;
1105 if (unsignedp && TARGET_64BIT)
1106 ret = (SMALL_INT (offset))
1107 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1108 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1109 else
1110 ret = (SMALL_INT (offset))
1111 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1112 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1113 }
1114 }
1115 }
1116 else
1117 {
1118 if (TARGET_STATS)
1119 mips_count_memory_refs (op1, 1);
1120
1121 ret = "la\t%0,%a1";
1122 }
1123 }
1124
1125 else if (code1 == PLUS)
1126 {
1127 rtx add_op0 = XEXP (op1, 0);
1128 rtx add_op1 = XEXP (op1, 1);
1129
1130 if (GET_CODE (XEXP (op1, 1)) == REG && GET_CODE (XEXP (op1, 0)) == CONST_INT)
1131 {
1132 add_op0 = XEXP (op1, 1); /* reverse operands */
1133 add_op1 = XEXP (op1, 0);
1134 }
1135
1136 operands[2] = add_op0;
1137 operands[3] = add_op1;
1138 ret = "add%:\t%0,%2,%3";
1139 }
1140 }
1141
1142 else if (code0 == MEM)
1143 {
1144 if (TARGET_STATS)
1145 mips_count_memory_refs (op0, 1);
1146
1147 if (code1 == REG)
1148 {
1149 int regno1 = REGNO (op1) + subreg_word1;
1150
1151 if (GP_REG_P (regno1))
1152 {
1153 switch (mode)
1154 {
1155 default: break;
1156 case SFmode: ret = "sw\t%1,%0"; break;
1157 case SImode: ret = "sw\t%1,%0"; break;
1158 case HImode: ret = "sh\t%1,%0"; break;
1159 case QImode: ret = "sb\t%1,%0"; break;
1160 }
1161 }
1162
1163 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
1164 ret = "s.s\t%1,%0";
1165 }
1166
1167 else if (code1 == CONST_INT && INTVAL (op1) == 0)
1168 {
1169 switch (mode)
1170 {
1171 default: break;
1172 case SFmode: ret = "sw\t%z1,%0"; break;
1173 case SImode: ret = "sw\t%z1,%0"; break;
1174 case HImode: ret = "sh\t%z1,%0"; break;
1175 case QImode: ret = "sb\t%z1,%0"; break;
1176 }
1177 }
1178
1179 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
1180 {
1181 switch (mode)
1182 {
1183 default: break;
1184 case SFmode: ret = "sw\t%.,%0"; break;
1185 case SImode: ret = "sw\t%.,%0"; break;
1186 case HImode: ret = "sh\t%.,%0"; break;
1187 case QImode: ret = "sb\t%.,%0"; break;
1188 }
1189 }
1190
1191 if (ret != (char *)0 && MEM_VOLATILE_P (op0))
1192 {
1193 int i = strlen (ret);
1194 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1195 abort ();
1196
1197 sprintf (volatile_buffer, "%%{%s%%}", ret);
1198 ret = volatile_buffer;
1199 }
1200 }
1201
1202 if (ret == (char *)0)
1203 {
1204 abort_with_insn (insn, "Bad move");
1205 return 0;
1206 }
1207
1208 if (delay != DELAY_NONE)
1209 return mips_fill_delay_slot (ret, delay, operands, insn);
1210
1211 return ret;
1212 }
1213
1214 \f
1215 /* Return the appropriate instructions to move 2 words */
1216
1217 char *
1218 mips_move_2words (operands, insn)
1219 rtx operands[];
1220 rtx insn;
1221 {
1222 char *ret = 0;
1223 rtx op0 = operands[0];
1224 rtx op1 = operands[1];
1225 enum rtx_code code0 = GET_CODE (operands[0]);
1226 enum rtx_code code1 = GET_CODE (operands[1]);
1227 int subreg_word0 = 0;
1228 int subreg_word1 = 0;
1229 enum delay_type delay = DELAY_NONE;
1230
1231 while (code0 == SUBREG)
1232 {
1233 subreg_word0 += SUBREG_WORD (op0);
1234 op0 = SUBREG_REG (op0);
1235 code0 = GET_CODE (op0);
1236 }
1237
1238 while (code1 == SUBREG)
1239 {
1240 subreg_word1 += SUBREG_WORD (op1);
1241 op1 = SUBREG_REG (op1);
1242 code1 = GET_CODE (op1);
1243 }
1244
1245 if (code0 == REG)
1246 {
1247 int regno0 = REGNO (op0) + subreg_word0;
1248
1249 if (code1 == REG)
1250 {
1251 int regno1 = REGNO (op1) + subreg_word1;
1252
1253 /* Just in case, don't do anything for assigning a register
1254 to itself, unless we are filling a delay slot. */
1255 if (regno0 == regno1 && set_nomacro == 0)
1256 ret = "";
1257
1258 else if (FP_REG_P (regno0))
1259 {
1260 if (FP_REG_P (regno1))
1261 ret = "mov.d\t%0,%1";
1262
1263 else
1264 {
1265 delay = DELAY_LOAD;
1266 if (TARGET_FLOAT64)
1267 {
1268 if (!TARGET_64BIT)
1269 abort_with_insn (insn, "Bad move");
1270 #ifdef TARGET_FP_CALL_32
1271 if (FP_CALL_GP_REG_P (regno1))
1272 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1273 else
1274 #endif
1275 ret = "dmtc1\t%1,%0";
1276 }
1277 else
1278 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1279 }
1280 }
1281
1282 else if (FP_REG_P (regno1))
1283 {
1284 delay = DELAY_LOAD;
1285 if (TARGET_FLOAT64)
1286 {
1287 if (!TARGET_64BIT)
1288 abort_with_insn (insn, "Bad move");
1289 #ifdef TARGET_FP_CALL_32
1290 if (FP_CALL_GP_REG_P (regno0))
1291 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1292 else
1293 #endif
1294 ret = "dmfc1\t%0,%1";
1295 }
1296 else
1297 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1298 }
1299
1300 else if (MD_REG_P (regno0) && GP_REG_P (regno1))
1301 {
1302 delay = DELAY_HILO;
1303 if (TARGET_64BIT)
1304 ret = "mt%0\t%1";
1305 else
1306 ret = "mthi\t%M1\n\tmtlo\t%L1";
1307 }
1308
1309 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
1310 {
1311 delay = DELAY_HILO;
1312 if (TARGET_64BIT)
1313 ret = "mf%1\t%0";
1314 else
1315 ret = "mfhi\t%M0\n\tmflo\t%L0";
1316 }
1317
1318 else if (TARGET_64BIT)
1319 ret = "move\t%0,%1";
1320
1321 else if (regno0 != (regno1+1))
1322 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
1323
1324 else
1325 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
1326 }
1327
1328 else if (code1 == CONST_DOUBLE)
1329 {
1330 /* Move zero from $0 unless !TARGET_64BIT and recipient
1331 is 64-bit fp reg, in which case generate a constant. */
1332 if (op1 != CONST0_RTX (GET_MODE (op1))
1333 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
1334 {
1335 if (GET_MODE (op1) == DFmode)
1336 {
1337 delay = DELAY_LOAD;
1338 #ifdef TARGET_FP_CALL_32
1339 if (FP_CALL_GP_REG_P (regno0))
1340 {
1341 if (TARGET_FLOAT64 && !TARGET_64BIT)
1342 {
1343 split_double (op1, operands + 2, operands + 3);
1344 ret = "li\t%0,%2\n\tli\t%D0,%3";
1345 }
1346 else
1347 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1348 }
1349 else
1350 #endif
1351 ret = "li.d\t%0,%1";
1352 }
1353
1354 else if (TARGET_64BIT)
1355 ret = "dli\t%0,%1";
1356
1357 else
1358 {
1359 split_double (op1, operands + 2, operands + 3);
1360 ret = "li\t%0,%2\n\tli\t%D0,%3";
1361 }
1362 }
1363
1364 else
1365 {
1366 if (GP_REG_P (regno0))
1367 ret = (TARGET_64BIT
1368 #ifdef TARGET_FP_CALL_32
1369 && ! FP_CALL_GP_REG_P (regno0)
1370 #endif
1371 )
1372 ? "move\t%0,%."
1373 : "move\t%0,%.\n\tmove\t%D0,%.";
1374
1375 else if (FP_REG_P (regno0))
1376 {
1377 delay = DELAY_LOAD;
1378 ret = (TARGET_64BIT)
1379 ? "dmtc1\t%.,%0"
1380 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1381 }
1382 }
1383 }
1384
1385 else if (code1 == CONST_INT && INTVAL (op1) == 0)
1386 {
1387 if (GP_REG_P (regno0))
1388 ret = (TARGET_64BIT)
1389 ? "move\t%0,%."
1390 : "move\t%0,%.\n\tmove\t%D0,%.";
1391
1392 else if (FP_REG_P (regno0))
1393 {
1394 delay = DELAY_LOAD;
1395 ret = (TARGET_64BIT)
1396 ? "dmtc1\t%.,%0"
1397 : (TARGET_FLOAT64
1398 ? "li.d\t%0,%1"
1399 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1400 }
1401 }
1402
1403 else if (code1 == CONST_INT && GET_MODE (op0) == DImode && GP_REG_P (regno0))
1404 {
1405 if (TARGET_64BIT)
1406 {
1407 if (HOST_BITS_PER_WIDE_INT < 64)
1408 /* We can't use 'X' for negative numbers, because then we won't
1409 get the right value for the upper 32 bits. */
1410 ret = ((INTVAL (op1) < 0) ? "dli\t%0,%1\t\t\t# %X1"
1411 : "dli\t%0,%X1\t\t# %1");
1412 else
1413 /* We must use 'X', because otherwise LONG_MIN will print as
1414 a number that the assembler won't accept. */
1415 ret = "dli\t%0,%X1\t\t# %1";
1416 }
1417 else
1418 {
1419 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
1420 ret = "li\t%M0,%2\n\tli\t%L0,%1";
1421 }
1422 }
1423
1424 else if (code1 == MEM)
1425 {
1426 delay = DELAY_LOAD;
1427
1428 if (TARGET_STATS)
1429 mips_count_memory_refs (op1, 2);
1430
1431 if (FP_REG_P (regno0))
1432 ret = "l.d\t%0,%1";
1433
1434 else if (TARGET_64BIT)
1435 {
1436 #ifdef TARGET_FP_CALL_32
1437 if (FP_CALL_GP_REG_P (regno0))
1438 {
1439 if (offsettable_address_p (FALSE, SImode, op1))
1440 ret = "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1441 else
1442 ret = "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1443 }
1444 else
1445 #endif
1446 ret = "ld\t%0,%1";
1447 }
1448
1449 else if (offsettable_address_p (1, DFmode, XEXP (op1, 0)))
1450 {
1451 operands[2] = adj_offsettable_operand (op1, 4);
1452 if (reg_mentioned_p (op0, op1))
1453 ret = "lw\t%D0,%2\n\tlw\t%0,%1";
1454 else
1455 ret = "lw\t%0,%1\n\tlw\t%D0,%2";
1456 }
1457
1458 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1459 {
1460 int i = strlen (ret);
1461 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1462 abort ();
1463
1464 sprintf (volatile_buffer, "%%{%s%%}", ret);
1465 ret = volatile_buffer;
1466 }
1467 }
1468
1469 else if (code1 == LABEL_REF
1470 || code1 == SYMBOL_REF
1471 || code1 == CONST)
1472 {
1473 if (TARGET_STATS)
1474 mips_count_memory_refs (op1, 2);
1475
1476 ret = "dla\t%0,%a1";
1477 }
1478 }
1479
1480 else if (code0 == MEM)
1481 {
1482 if (code1 == REG)
1483 {
1484 int regno1 = REGNO (op1) + subreg_word1;
1485
1486 if (FP_REG_P (regno1))
1487 ret = "s.d\t%1,%0";
1488
1489 else if (TARGET_64BIT)
1490 {
1491 #ifdef TARGET_FP_CALL_32
1492 if (FP_CALL_GP_REG_P (regno1))
1493 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1494 else
1495 #endif
1496 ret = "sd\t%1,%0";
1497 }
1498
1499 else if (offsettable_address_p (1, DFmode, XEXP (op0, 0)))
1500 {
1501 operands[2] = adj_offsettable_operand (op0, 4);
1502 ret = "sw\t%1,%0\n\tsw\t%D1,%2";
1503 }
1504 }
1505
1506 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
1507 || (code1 == CONST_DOUBLE
1508 && op1 == CONST0_RTX (GET_MODE (op1))))
1509 && (TARGET_64BIT
1510 || offsettable_address_p (1, DFmode, XEXP (op0, 0))))
1511 {
1512 if (TARGET_64BIT)
1513 ret = "sd\t%.,%0";
1514 else
1515 {
1516 operands[2] = adj_offsettable_operand (op0, 4);
1517 ret = "sw\t%.,%0\n\tsw\t%.,%2";
1518 }
1519 }
1520
1521 if (TARGET_STATS)
1522 mips_count_memory_refs (op0, 2);
1523
1524 if (ret != (char *)0 && MEM_VOLATILE_P (op0))
1525 {
1526 int i = strlen (ret);
1527 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1528 abort ();
1529
1530 sprintf (volatile_buffer, "%%{%s%%}", ret);
1531 ret = volatile_buffer;
1532 }
1533 }
1534
1535 if (ret == (char *)0)
1536 {
1537 abort_with_insn (insn, "Bad move");
1538 return 0;
1539 }
1540
1541 if (delay != DELAY_NONE)
1542 return mips_fill_delay_slot (ret, delay, operands, insn);
1543
1544 return ret;
1545 }
1546
1547 \f
1548 /* Provide the costs of an addressing mode that contains ADDR.
1549 If ADDR is not a valid address, its cost is irrelevant. */
1550
1551 int
1552 mips_address_cost (addr)
1553 rtx addr;
1554 {
1555 switch (GET_CODE (addr))
1556 {
1557 default:
1558 break;
1559
1560 case LO_SUM:
1561 case HIGH:
1562 return 1;
1563
1564 case LABEL_REF:
1565 return 2;
1566
1567 case CONST:
1568 {
1569 rtx offset = const0_rtx;
1570 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
1571 if (GET_CODE (addr) == LABEL_REF)
1572 return 2;
1573
1574 if (GET_CODE (addr) != SYMBOL_REF)
1575 return 4;
1576
1577 if (! SMALL_INT (offset))
1578 return 2;
1579 }
1580 /* fall through */
1581
1582 case SYMBOL_REF:
1583 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
1584
1585 case PLUS:
1586 {
1587 register rtx plus0 = XEXP (addr, 0);
1588 register rtx plus1 = XEXP (addr, 1);
1589
1590 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1591 {
1592 plus0 = XEXP (addr, 1);
1593 plus1 = XEXP (addr, 0);
1594 }
1595
1596 if (GET_CODE (plus0) != REG)
1597 break;
1598
1599 switch (GET_CODE (plus1))
1600 {
1601 default:
1602 break;
1603
1604 case CONST_INT:
1605 return (SMALL_INT (plus1) ? 1 : 2);
1606
1607 case CONST:
1608 case SYMBOL_REF:
1609 case LABEL_REF:
1610 case HIGH:
1611 case LO_SUM:
1612 return mips_address_cost (plus1) + 1;
1613 }
1614 }
1615 }
1616
1617 return 4;
1618 }
1619
1620 /* Return true if X is an address which needs a temporary register when
1621 reloaded while generating PIC code. */
1622
1623 int
1624 pic_address_needs_scratch (x)
1625 rtx x;
1626 {
1627 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1628 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
1629 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1630 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1631 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
1632 return 1;
1633
1634 return 0;
1635 }
1636 \f
1637 /* Make normal rtx_code into something we can index from an array */
1638
1639 static enum internal_test
1640 map_test_to_internal_test (test_code)
1641 enum rtx_code test_code;
1642 {
1643 enum internal_test test = ITEST_MAX;
1644
1645 switch (test_code)
1646 {
1647 default: break;
1648 case EQ: test = ITEST_EQ; break;
1649 case NE: test = ITEST_NE; break;
1650 case GT: test = ITEST_GT; break;
1651 case GE: test = ITEST_GE; break;
1652 case LT: test = ITEST_LT; break;
1653 case LE: test = ITEST_LE; break;
1654 case GTU: test = ITEST_GTU; break;
1655 case GEU: test = ITEST_GEU; break;
1656 case LTU: test = ITEST_LTU; break;
1657 case LEU: test = ITEST_LEU; break;
1658 }
1659
1660 return test;
1661 }
1662
1663 \f
1664 /* Generate the code to compare two integer values. The return value is:
1665 (reg:SI xx) The pseudo register the comparison is in
1666 (rtx)0 No register, generate a simple branch.
1667
1668 ??? This is called with result nonzero by the Scond patterns in
1669 mips.md. These patterns are called with a target in the mode of
1670 the Scond instruction pattern. Since this must be a constant, we
1671 must use SImode. This means that if RESULT is non-zero, it will
1672 always be an SImode register, even if TARGET_64BIT is true. We
1673 cope with this by calling convert_move rather than emit_move_insn.
1674 This will sometimes lead to an unnecessary extension of the result;
1675 for example:
1676
1677 long long
1678 foo (long long i)
1679 {
1680 return i < 5;
1681 }
1682
1683 */
1684
1685 rtx
1686 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
1687 enum rtx_code test_code; /* relational test (EQ, etc) */
1688 rtx result; /* result to store comp. or 0 if branch */
1689 rtx cmp0; /* first operand to compare */
1690 rtx cmp1; /* second operand to compare */
1691 int *p_invert; /* NULL or ptr to hold whether branch needs */
1692 /* to reverse its test */
1693 {
1694 struct cmp_info {
1695 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
1696 int const_low; /* low bound of constant we can accept */
1697 int const_high; /* high bound of constant we can accept */
1698 int const_add; /* constant to add (convert LE -> LT) */
1699 int reverse_regs; /* reverse registers in test */
1700 int invert_const; /* != 0 if invert value if cmp1 is constant */
1701 int invert_reg; /* != 0 if invert value if cmp1 is register */
1702 int unsignedp; /* != 0 for unsigned comparisons. */
1703 };
1704
1705 static struct cmp_info info[ (int)ITEST_MAX ] = {
1706
1707 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
1708 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
1709 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
1710 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
1711 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
1712 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
1713 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
1714 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
1715 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
1716 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
1717 };
1718
1719 enum internal_test test;
1720 enum machine_mode mode;
1721 struct cmp_info *p_info;
1722 int branch_p;
1723 int eqne_p;
1724 int invert;
1725 rtx reg;
1726 rtx reg2;
1727
1728 test = map_test_to_internal_test (test_code);
1729 if (test == ITEST_MAX)
1730 abort ();
1731
1732 p_info = &info[ (int)test ];
1733 eqne_p = (p_info->test_code == XOR);
1734
1735 mode = GET_MODE (cmp0);
1736 if (mode == VOIDmode)
1737 mode = GET_MODE (cmp1);
1738
1739 /* Eliminate simple branches */
1740 branch_p = (result == (rtx)0);
1741 if (branch_p)
1742 {
1743 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
1744 {
1745 /* Comparisons against zero are simple branches */
1746 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
1747 return (rtx)0;
1748
1749 /* Test for beq/bne. */
1750 if (eqne_p)
1751 return (rtx)0;
1752 }
1753
1754 /* allocate a pseudo to calculate the value in. */
1755 result = gen_reg_rtx (mode);
1756 }
1757
1758 /* Make sure we can handle any constants given to us. */
1759 if (GET_CODE (cmp0) == CONST_INT)
1760 cmp0 = force_reg (mode, cmp0);
1761
1762 if (GET_CODE (cmp1) == CONST_INT)
1763 {
1764 HOST_WIDE_INT value = INTVAL (cmp1);
1765 if (value < p_info->const_low
1766 || value > p_info->const_high
1767 /* ??? Why? And why wasn't the similar code below modified too? */
1768 || (TARGET_64BIT
1769 && HOST_BITS_PER_WIDE_INT < 64
1770 && p_info->const_add != 0
1771 && ((p_info->unsignedp
1772 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
1773 > INTVAL (cmp1))
1774 : (value + p_info->const_add) > INTVAL (cmp1))
1775 != (p_info->const_add > 0))))
1776 cmp1 = force_reg (mode, cmp1);
1777 }
1778
1779 /* See if we need to invert the result. */
1780 invert = (GET_CODE (cmp1) == CONST_INT)
1781 ? p_info->invert_const
1782 : p_info->invert_reg;
1783
1784 if (p_invert != (int *)0)
1785 {
1786 *p_invert = invert;
1787 invert = FALSE;
1788 }
1789
1790 /* Comparison to constants, may involve adding 1 to change a LT into LE.
1791 Comparison between two registers, may involve switching operands. */
1792 if (GET_CODE (cmp1) == CONST_INT)
1793 {
1794 if (p_info->const_add != 0)
1795 {
1796 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
1797 /* If modification of cmp1 caused overflow,
1798 we would get the wrong answer if we follow the usual path;
1799 thus, x > 0xffffffffu would turn into x > 0u. */
1800 if ((p_info->unsignedp
1801 ? (unsigned HOST_WIDE_INT) new > INTVAL (cmp1)
1802 : new > INTVAL (cmp1))
1803 != (p_info->const_add > 0))
1804 {
1805 /* This test is always true, but if INVERT is true then
1806 the result of the test needs to be inverted so 0 should
1807 be returned instead. */
1808 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
1809 return result;
1810 }
1811 else
1812 cmp1 = GEN_INT (new);
1813 }
1814 }
1815 else if (p_info->reverse_regs)
1816 {
1817 rtx temp = cmp0;
1818 cmp0 = cmp1;
1819 cmp1 = temp;
1820 }
1821
1822 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
1823 reg = cmp0;
1824 else
1825 {
1826 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
1827 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
1828 }
1829
1830 if (test == ITEST_NE)
1831 {
1832 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
1833 invert = FALSE;
1834 }
1835
1836 else if (test == ITEST_EQ)
1837 {
1838 reg2 = (invert) ? gen_reg_rtx (mode) : result;
1839 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
1840 reg = reg2;
1841 }
1842
1843 if (invert)
1844 convert_move (result, gen_rtx (XOR, mode, reg, const1_rtx), 0);
1845
1846 return result;
1847 }
1848
1849 \f
1850 /* Emit the common code for doing conditional branches.
1851 operand[0] is the label to jump to.
1852 The comparison operands are saved away by cmp{si,di,sf,df}. */
1853
1854 void
1855 gen_conditional_branch (operands, test_code)
1856 rtx operands[];
1857 enum rtx_code test_code;
1858 {
1859 static enum machine_mode mode_map[(int)CMP_MAX][(int)ITEST_MAX] = {
1860 { /* CMP_SI */
1861 SImode, /* eq */
1862 SImode, /* ne */
1863 SImode, /* gt */
1864 SImode, /* ge */
1865 SImode, /* lt */
1866 SImode, /* le */
1867 SImode, /* gtu */
1868 SImode, /* geu */
1869 SImode, /* ltu */
1870 SImode, /* leu */
1871 },
1872 { /* CMP_DI */
1873 DImode, /* eq */
1874 DImode, /* ne */
1875 DImode, /* gt */
1876 DImode, /* ge */
1877 DImode, /* lt */
1878 DImode, /* le */
1879 DImode, /* gtu */
1880 DImode, /* geu */
1881 DImode, /* ltu */
1882 DImode, /* leu */
1883 },
1884 { /* CMP_SF */
1885 CC_FPmode, /* eq */
1886 CC_REV_FPmode, /* ne */
1887 CC_FPmode, /* gt */
1888 CC_FPmode, /* ge */
1889 CC_FPmode, /* lt */
1890 CC_FPmode, /* le */
1891 VOIDmode, /* gtu */
1892 VOIDmode, /* geu */
1893 VOIDmode, /* ltu */
1894 VOIDmode, /* leu */
1895 },
1896 { /* CMP_DF */
1897 CC_FPmode, /* eq */
1898 CC_REV_FPmode, /* ne */
1899 CC_FPmode, /* gt */
1900 CC_FPmode, /* ge */
1901 CC_FPmode, /* lt */
1902 CC_FPmode, /* le */
1903 VOIDmode, /* gtu */
1904 VOIDmode, /* geu */
1905 VOIDmode, /* ltu */
1906 VOIDmode, /* leu */
1907 },
1908 };
1909
1910 enum machine_mode mode;
1911 enum cmp_type type = branch_type;
1912 rtx cmp0 = branch_cmp[0];
1913 rtx cmp1 = branch_cmp[1];
1914 rtx label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]);
1915 rtx label2 = pc_rtx;
1916 rtx reg = (rtx)0;
1917 int invert = 0;
1918 enum internal_test test = map_test_to_internal_test (test_code);
1919
1920 if (test == ITEST_MAX)
1921 {
1922 mode = word_mode;
1923 goto fail;
1924 }
1925
1926 /* Get the machine mode to use (CCmode, CC_EQmode, CC_FPmode, or CC_REV_FPmode). */
1927 mode = mode_map[(int)type][(int)test];
1928 if (mode == VOIDmode)
1929 goto fail;
1930
1931 switch (type)
1932 {
1933 default:
1934 goto fail;
1935
1936 case CMP_SI:
1937 case CMP_DI:
1938 reg = gen_int_relational (test_code, (rtx)0, cmp0, cmp1, &invert);
1939 if (reg != (rtx)0)
1940 {
1941 cmp0 = reg;
1942 cmp1 = const0_rtx;
1943 test_code = NE;
1944 }
1945
1946 /* Make sure not non-zero constant if ==/!= */
1947 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
1948 cmp1 = force_reg (mode, cmp1);
1949
1950 break;
1951
1952 case CMP_DF:
1953 case CMP_SF:
1954 {
1955 rtx reg = gen_rtx (REG, mode, FPSW_REGNUM);
1956 emit_insn (gen_rtx (SET, VOIDmode, reg, gen_rtx (test_code, mode, cmp0, cmp1)));
1957 cmp0 = reg;
1958 cmp1 = const0_rtx;
1959 test_code = NE;
1960 }
1961 break;
1962 }
1963
1964 /* Generate the jump */
1965 if (invert)
1966 {
1967 label2 = label1;
1968 label1 = pc_rtx;
1969 }
1970
1971 emit_jump_insn (gen_rtx (SET, VOIDmode,
1972 pc_rtx,
1973 gen_rtx (IF_THEN_ELSE, VOIDmode,
1974 gen_rtx (test_code, mode, cmp0, cmp1),
1975 label1,
1976 label2)));
1977
1978 return;
1979
1980 fail:
1981 abort_with_insn (gen_rtx (test_code, mode, cmp0, cmp1), "bad test");
1982 }
1983
1984 \f
1985 #if 0
1986 /* Internal code to generate the load and store of one word/short/byte.
1987 The load is emitted directly, and the store insn is returned. */
1988
1989 #define UNITS_PER_MIPS_DWORD 8
1990 #define UNITS_PER_MIPS_WORD 4
1991 #define UNITS_PER_MIPS_HWORD 2
1992
1993 static rtx
1994 block_move_load_store (dest_reg, src_reg, p_bytes, p_offset, align, orig_src)
1995 rtx src_reg; /* register holding source memory address */
1996 rtx dest_reg; /* register holding dest. memory address */
1997 int *p_bytes; /* pointer to # bytes remaining */
1998 int *p_offset; /* pointer to current offset */
1999 int align; /* alignment */
2000 rtx orig_src; /* original source for making a reg note */
2001 {
2002 int bytes; /* # bytes remaining */
2003 int offset; /* offset to use */
2004 int size; /* size in bytes of load/store */
2005 enum machine_mode mode; /* mode to use for load/store */
2006 rtx reg; /* temporary register */
2007 rtx src_addr; /* source address */
2008 rtx dest_addr; /* destination address */
2009 rtx insn; /* insn of the load */
2010 rtx orig_src_addr; /* original source address */
2011 rtx (*load_func)(); /* function to generate load insn */
2012 rtx (*store_func)(); /* function to generate destination insn */
2013
2014 bytes = *p_bytes;
2015 if (bytes <= 0 || align <= 0)
2016 abort ();
2017
2018 if (bytes >= UNITS_PER_MIPS_DWORD && align >= UNIS_PER_MIPS_DWORD)
2019 {
2020 mode = DImode;
2021 size = UNITS_PER_MIPS_DWORD;
2022 load_func = gen_movdi;
2023 store_func = gen_movdi;
2024 }
2025 else if (bytes >= UNITS_PER_MIPS_WORD && align >= UNITS_PER_MIPS_WORD)
2026 {
2027 mode = SImode;
2028 size = UNITS_PER_MIPS_WORD;
2029 load_func = gen_movsi;
2030 store_func = gen_movsi;
2031 }
2032
2033 #if 0
2034 /* Don't generate unaligned moves here, rather defer those to the
2035 general movestrsi_internal pattern.
2036 If this gets commented back in, then should add the dword equivalent. */
2037 else if (bytes >= UNITS_PER_MIPS_WORD)
2038 {
2039 mode = SImode;
2040 size = UNITS_PER_MIPS_WORD;
2041 load_func = gen_movsi_ulw;
2042 store_func = gen_movsi_usw;
2043 }
2044 #endif
2045
2046 else if (bytes >= UNITS_PER_MIPS_SHORT && align >= UNITS_PER_MIPS_SHORT)
2047 {
2048 mode = HImode;
2049 size = UNITS_PER_MIPS_SHORT;
2050 load_func = gen_movhi;
2051 store_func = gen_movhi;
2052 }
2053
2054 else
2055 {
2056 mode = QImode;
2057 size = 1;
2058 load_func = gen_movqi;
2059 store_func = gen_movqi;
2060 }
2061
2062 offset = *p_offset;
2063 *p_offset = offset + size;
2064 *p_bytes = bytes - size;
2065
2066 if (offset == 0)
2067 {
2068 src_addr = src_reg;
2069 dest_addr = dest_reg;
2070 }
2071 else
2072 {
2073 src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset));
2074 dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset));
2075 }
2076
2077 reg = gen_reg_rtx (mode);
2078 insn = emit_insn ((*load_func) (reg, gen_rtx (MEM, mode, src_addr)));
2079 orig_src_addr = XEXP (orig_src, 0);
2080 if (CONSTANT_P (orig_src_addr))
2081 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUIV,
2082 plus_constant (orig_src_addr, offset),
2083 REG_NOTES (insn));
2084
2085 return (*store_func) (gen_rtx (MEM, mode, dest_addr), reg);
2086 }
2087 #endif
2088
2089 \f
2090 /* Write a series of loads/stores to move some bytes. Generate load/stores as follows:
2091
2092 load 1
2093 load 2
2094 load 3
2095 store 1
2096 load 4
2097 store 2
2098 load 5
2099 store 3
2100 ...
2101
2102 This way, no NOP's are needed, except at the end, and only
2103 two temp registers are needed. Two delay slots are used
2104 in deference to the R4000. */
2105
2106 #if 0
2107 static void
2108 block_move_sequence (dest_reg, src_reg, bytes, align, orig_src)
2109 rtx dest_reg; /* register holding destination address */
2110 rtx src_reg; /* register holding source address */
2111 int bytes; /* # bytes to move */
2112 int align; /* max alignment to assume */
2113 rtx orig_src; /* original source for making a reg note */
2114 {
2115 int offset = 0;
2116 rtx prev2_store = (rtx)0;
2117 rtx prev_store = (rtx)0;
2118 rtx cur_store = (rtx)0;
2119
2120 while (bytes > 0)
2121 {
2122 /* Is there a store to do? */
2123 if (prev2_store)
2124 emit_insn (prev2_store);
2125
2126 prev2_store = prev_store;
2127 prev_store = cur_store;
2128 cur_store = block_move_load_store (dest_reg, src_reg,
2129 &bytes, &offset,
2130 align, orig_src);
2131 }
2132
2133 /* Finish up last three stores. */
2134 if (prev2_store)
2135 emit_insn (prev2_store);
2136
2137 if (prev_store)
2138 emit_insn (prev_store);
2139
2140 if (cur_store)
2141 emit_insn (cur_store);
2142 }
2143 #endif
2144
2145 \f
2146 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2147
2148 do {
2149 temp1 = src[0];
2150 temp2 = src[1];
2151 ...
2152 temp<last> = src[MAX_MOVE_REGS-1];
2153 dest[0] = temp1;
2154 dest[1] = temp2;
2155 ...
2156 dest[MAX_MOVE_REGS-1] = temp<last>;
2157 src += MAX_MOVE_REGS;
2158 dest += MAX_MOVE_REGS;
2159 } while (src != final);
2160
2161 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2162 registers are needed.
2163
2164 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2165 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2166 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2167
2168 #define MAX_MOVE_REGS 4
2169 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2170
2171 /* ??? Should add code to use DWORD load/stores. */
2172
2173 static void
2174 block_move_loop (dest_reg, src_reg, bytes, align, orig_src)
2175 rtx dest_reg; /* register holding destination address */
2176 rtx src_reg; /* register holding source address */
2177 int bytes; /* # bytes to move */
2178 int align; /* alignment */
2179 rtx orig_src; /* original source for making a reg note */
2180 {
2181 rtx dest_mem = gen_rtx (MEM, BLKmode, dest_reg);
2182 rtx src_mem = gen_rtx (MEM, BLKmode, src_reg);
2183 rtx align_rtx = GEN_INT (align);
2184 rtx label;
2185 rtx final_src;
2186 rtx bytes_rtx;
2187 int leftover;
2188
2189 if (bytes < 2*MAX_MOVE_BYTES)
2190 abort ();
2191
2192 leftover = bytes % MAX_MOVE_BYTES;
2193 bytes -= leftover;
2194
2195 label = gen_label_rtx ();
2196 final_src = gen_reg_rtx (Pmode);
2197 bytes_rtx = GEN_INT (bytes);
2198
2199 if (bytes > 0x7fff)
2200 {
2201 if (TARGET_LONG64)
2202 {
2203 emit_insn (gen_movdi (final_src, bytes_rtx));
2204 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
2205 }
2206 else
2207 {
2208 emit_insn (gen_movsi (final_src, bytes_rtx));
2209 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2210 }
2211 }
2212 else
2213 {
2214 if (TARGET_LONG64)
2215 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
2216 else
2217 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
2218 }
2219
2220 emit_label (label);
2221
2222 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
2223 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
2224 if (TARGET_LONG64)
2225 {
2226 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
2227 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
2228 emit_insn (gen_cmpdi (src_reg, final_src));
2229 }
2230 else
2231 {
2232 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
2233 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
2234 emit_insn (gen_cmpsi (src_reg, final_src));
2235 }
2236 emit_jump_insn (gen_bne (label));
2237
2238 if (leftover)
2239 emit_insn (gen_movstrsi_internal (dest_mem, src_mem,
2240 GEN_INT (leftover),
2241 align_rtx));
2242 }
2243
2244 \f
2245 /* Use a library function to move some bytes. */
2246
2247 static void
2248 block_move_call (dest_reg, src_reg, bytes_rtx)
2249 rtx dest_reg;
2250 rtx src_reg;
2251 rtx bytes_rtx;
2252 {
2253 /* We want to pass the size as Pmode, which will normally be SImode
2254 but will be DImode if we are using 64 bit longs and pointers. */
2255 if (GET_MODE (bytes_rtx) != VOIDmode
2256 && GET_MODE (bytes_rtx) != Pmode)
2257 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, TRUE);
2258
2259 #ifdef TARGET_MEM_FUNCTIONS
2260 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2261 VOIDmode, 3,
2262 dest_reg, Pmode,
2263 src_reg, Pmode,
2264 bytes_rtx, Pmode);
2265 #else
2266 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2267 VOIDmode, 3,
2268 src_reg, Pmode,
2269 dest_reg, Pmode,
2270 bytes_rtx, Pmode);
2271 #endif
2272 }
2273
2274 \f
2275 /* Expand string/block move operations.
2276
2277 operands[0] is the pointer to the destination.
2278 operands[1] is the pointer to the source.
2279 operands[2] is the number of bytes to move.
2280 operands[3] is the alignment. */
2281
2282 void
2283 expand_block_move (operands)
2284 rtx operands[];
2285 {
2286 rtx bytes_rtx = operands[2];
2287 rtx align_rtx = operands[3];
2288 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2289 int bytes = (constp ? INTVAL (bytes_rtx) : 0);
2290 int align = INTVAL (align_rtx);
2291 rtx orig_src = operands[1];
2292 rtx src_reg;
2293 rtx dest_reg;
2294
2295 if (constp && bytes <= 0)
2296 return;
2297
2298 if (align > UNITS_PER_WORD)
2299 align = UNITS_PER_WORD;
2300
2301 /* Move the address into scratch registers. */
2302 dest_reg = copy_addr_to_reg (XEXP (operands[0], 0));
2303 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2304
2305 if (TARGET_MEMCPY)
2306 block_move_call (dest_reg, src_reg, bytes_rtx);
2307
2308 #if 0
2309 else if (constp && bytes <= 3*align)
2310 block_move_sequence (dest_reg, src_reg, bytes, align, orig_src);
2311 #endif
2312
2313 else if (constp && bytes <= 2*MAX_MOVE_BYTES)
2314 emit_insn (gen_movstrsi_internal (gen_rtx (MEM, BLKmode, dest_reg),
2315 gen_rtx (MEM, BLKmode, src_reg),
2316 bytes_rtx, align_rtx));
2317
2318 else if (constp && align >= UNITS_PER_WORD && optimize)
2319 block_move_loop (dest_reg, src_reg, bytes, align, orig_src);
2320
2321 else if (constp && optimize)
2322 {
2323 /* If the alignment is not word aligned, generate a test at
2324 runtime, to see whether things wound up aligned, and we
2325 can use the faster lw/sw instead ulw/usw. */
2326
2327 rtx temp = gen_reg_rtx (Pmode);
2328 rtx aligned_label = gen_label_rtx ();
2329 rtx join_label = gen_label_rtx ();
2330 int leftover = bytes % MAX_MOVE_BYTES;
2331
2332 bytes -= leftover;
2333
2334 if (TARGET_LONG64)
2335 {
2336 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
2337 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD-1)));
2338 emit_insn (gen_cmpdi (temp, const0_rtx));
2339 }
2340 else
2341 {
2342 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
2343 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD-1)));
2344 emit_insn (gen_cmpsi (temp, const0_rtx));
2345 }
2346 emit_jump_insn (gen_beq (aligned_label));
2347
2348 /* Unaligned loop. */
2349 block_move_loop (dest_reg, src_reg, bytes, 1, orig_src);
2350 emit_jump_insn (gen_jump (join_label));
2351 emit_barrier ();
2352
2353 /* Aligned loop. */
2354 emit_label (aligned_label);
2355 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_src);
2356 emit_label (join_label);
2357
2358 /* Bytes at the end of the loop. */
2359 if (leftover)
2360 {
2361 #if 0
2362 if (leftover <= 3*align)
2363 block_move_sequence (dest_reg, src_reg, leftover, align, orig_src);
2364
2365 else
2366 #endif
2367 emit_insn (gen_movstrsi_internal (gen_rtx (MEM, BLKmode, dest_reg),
2368 gen_rtx (MEM, BLKmode, src_reg),
2369 GEN_INT (leftover),
2370 GEN_INT (align)));
2371 }
2372 }
2373
2374 else
2375 block_move_call (dest_reg, src_reg, bytes_rtx);
2376 }
2377
2378 \f
2379 /* Emit load/stores for a small constant block_move.
2380
2381 operands[0] is the memory address of the destination.
2382 operands[1] is the memory address of the source.
2383 operands[2] is the number of bytes to move.
2384 operands[3] is the alignment.
2385 operands[4] is a temp register.
2386 operands[5] is a temp register.
2387 ...
2388 operands[3+num_regs] is the last temp register.
2389
2390 The block move type can be one of the following:
2391 BLOCK_MOVE_NORMAL Do all of the block move.
2392 BLOCK_MOVE_NOT_LAST Do all but the last store.
2393 BLOCK_MOVE_LAST Do just the last store. */
2394
2395 char *
2396 output_block_move (insn, operands, num_regs, move_type)
2397 rtx insn;
2398 rtx operands[];
2399 int num_regs;
2400 enum block_move_type move_type;
2401 {
2402 rtx dest_reg = XEXP (operands[0], 0);
2403 rtx src_reg = XEXP (operands[1], 0);
2404 int bytes = INTVAL (operands[2]);
2405 int align = INTVAL (operands[3]);
2406 int num = 0;
2407 int offset = 0;
2408 int use_lwl_lwr = FALSE;
2409 int last_operand = num_regs+4;
2410 int safe_regs = 4;
2411 int i;
2412 rtx xoperands[10];
2413
2414 struct {
2415 char *load; /* load insn without nop */
2416 char *load_nop; /* load insn with trailing nop */
2417 char *store; /* store insn */
2418 char *final; /* if last_store used: NULL or swr */
2419 char *last_store; /* last store instruction */
2420 int offset; /* current offset */
2421 enum machine_mode mode; /* mode to use on (MEM) */
2422 } load_store[4];
2423
2424 /* Detect a bug in GCC, where it can give us a register
2425 the same as one of the addressing registers and reduce
2426 the number of registers available. */
2427 for (i = 4;
2428 i < last_operand && safe_regs < (sizeof(xoperands) / sizeof(xoperands[0]));
2429 i++)
2430 {
2431 if (!reg_mentioned_p (operands[i], operands[0])
2432 && !reg_mentioned_p (operands[i], operands[1]))
2433
2434 xoperands[safe_regs++] = operands[i];
2435 }
2436
2437 if (safe_regs < last_operand)
2438 {
2439 xoperands[0] = operands[0];
2440 xoperands[1] = operands[1];
2441 xoperands[2] = operands[2];
2442 xoperands[3] = operands[3];
2443 return output_block_move (insn, xoperands, safe_regs-4, move_type);
2444 }
2445
2446 /* If we are given global or static addresses, and we would be
2447 emitting a few instructions, try to save time by using a
2448 temporary register for the pointer. */
2449 if (num_regs > 2 && (bytes > 2*align || move_type != BLOCK_MOVE_NORMAL))
2450 {
2451 if (CONSTANT_P (src_reg))
2452 {
2453 if (TARGET_STATS)
2454 mips_count_memory_refs (operands[1], 1);
2455
2456 src_reg = operands[ 3 + num_regs-- ];
2457 if (move_type != BLOCK_MOVE_LAST)
2458 {
2459 xoperands[1] = operands[1];
2460 xoperands[0] = src_reg;
2461 if (Pmode == DImode)
2462 output_asm_insn ("dla\t%0,%1", xoperands);
2463 else
2464 output_asm_insn ("la\t%0,%1", xoperands);
2465 }
2466 }
2467
2468 if (CONSTANT_P (dest_reg))
2469 {
2470 if (TARGET_STATS)
2471 mips_count_memory_refs (operands[0], 1);
2472
2473 dest_reg = operands[ 3 + num_regs-- ];
2474 if (move_type != BLOCK_MOVE_LAST)
2475 {
2476 xoperands[1] = operands[0];
2477 xoperands[0] = dest_reg;
2478 if (Pmode == DImode)
2479 output_asm_insn ("dla\t%0,%1", xoperands);
2480 else
2481 output_asm_insn ("la\t%0,%1", xoperands);
2482 }
2483 }
2484 }
2485
2486 if (num_regs > (sizeof (load_store) / sizeof (load_store[0])))
2487 num_regs = (sizeof (load_store) / sizeof (load_store[0]));
2488
2489 else if (num_regs < 1)
2490 abort_with_insn (insn, "Cannot do block move, not enough scratch registers");
2491
2492 while (bytes > 0)
2493 {
2494 load_store[num].offset = offset;
2495
2496 if (TARGET_64BIT && bytes >= 8 && align >= 8)
2497 {
2498 load_store[num].load = "ld\t%0,%1";
2499 load_store[num].load_nop = "ld\t%0,%1%#";
2500 load_store[num].store = "sd\t%0,%1";
2501 load_store[num].last_store = "sd\t%0,%1";
2502 load_store[num].final = (char *)0;
2503 load_store[num].mode = DImode;
2504 offset += 8;
2505 bytes -= 8;
2506 }
2507
2508 /* ??? Fails because of a MIPS assembler bug? */
2509 else if (TARGET_64BIT && bytes >= 8)
2510 {
2511 if (BYTES_BIG_ENDIAN)
2512 {
2513 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
2514 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
2515 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
2516 load_store[num].last_store = "sdr\t%0,%2";
2517 load_store[num].final = "sdl\t%0,%1";
2518 }
2519 else
2520 {
2521 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
2522 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
2523 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
2524 load_store[num].last_store = "sdr\t%0,%1";
2525 load_store[num].final = "sdl\t%0,%2";
2526 }
2527 load_store[num].mode = DImode;
2528 offset += 8;
2529 bytes -= 8;
2530 use_lwl_lwr = TRUE;
2531 }
2532
2533 else if (bytes >= 4 && align >= 4)
2534 {
2535 load_store[num].load = "lw\t%0,%1";
2536 load_store[num].load_nop = "lw\t%0,%1%#";
2537 load_store[num].store = "sw\t%0,%1";
2538 load_store[num].last_store = "sw\t%0,%1";
2539 load_store[num].final = (char *)0;
2540 load_store[num].mode = SImode;
2541 offset += 4;
2542 bytes -= 4;
2543 }
2544
2545 else if (bytes >= 4)
2546 {
2547 if (BYTES_BIG_ENDIAN)
2548 {
2549 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
2550 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2551 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
2552 load_store[num].last_store = "swr\t%0,%2";
2553 load_store[num].final = "swl\t%0,%1";
2554 }
2555 else
2556 {
2557 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
2558 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2559 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
2560 load_store[num].last_store = "swr\t%0,%1";
2561 load_store[num].final = "swl\t%0,%2";
2562 }
2563 load_store[num].mode = SImode;
2564 offset += 4;
2565 bytes -= 4;
2566 use_lwl_lwr = TRUE;
2567 }
2568
2569 else if (bytes >= 2 && align >= 2)
2570 {
2571 load_store[num].load = "lh\t%0,%1";
2572 load_store[num].load_nop = "lh\t%0,%1%#";
2573 load_store[num].store = "sh\t%0,%1";
2574 load_store[num].last_store = "sh\t%0,%1";
2575 load_store[num].final = (char *)0;
2576 load_store[num].mode = HImode;
2577 offset += 2;
2578 bytes -= 2;
2579 }
2580
2581 else
2582 {
2583 load_store[num].load = "lb\t%0,%1";
2584 load_store[num].load_nop = "lb\t%0,%1%#";
2585 load_store[num].store = "sb\t%0,%1";
2586 load_store[num].last_store = "sb\t%0,%1";
2587 load_store[num].final = (char *)0;
2588 load_store[num].mode = QImode;
2589 offset++;
2590 bytes--;
2591 }
2592
2593 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
2594 {
2595 dslots_load_total++;
2596 dslots_load_filled++;
2597
2598 if (CONSTANT_P (src_reg))
2599 mips_count_memory_refs (src_reg, 1);
2600
2601 if (CONSTANT_P (dest_reg))
2602 mips_count_memory_refs (dest_reg, 1);
2603 }
2604
2605 /* Emit load/stores now if we have run out of registers or are
2606 at the end of the move. */
2607
2608 if (++num == num_regs || bytes == 0)
2609 {
2610 /* If only load/store, we need a NOP after the load. */
2611 if (num == 1)
2612 {
2613 load_store[0].load = load_store[0].load_nop;
2614 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
2615 dslots_load_filled--;
2616 }
2617
2618 if (move_type != BLOCK_MOVE_LAST)
2619 {
2620 for (i = 0; i < num; i++)
2621 {
2622 int offset;
2623
2624 if (!operands[i+4])
2625 abort ();
2626
2627 if (GET_MODE (operands[i+4]) != load_store[i].mode)
2628 operands[i+4] = gen_rtx (REG, load_store[i].mode, REGNO (operands[i+4]));
2629
2630 offset = load_store[i].offset;
2631 xoperands[0] = operands[i+4];
2632 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
2633 plus_constant (src_reg, offset));
2634
2635 if (use_lwl_lwr)
2636 {
2637 int extra_offset;
2638 extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
2639 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
2640 plus_constant (src_reg,
2641 extra_offset
2642 + offset));
2643 }
2644
2645 output_asm_insn (load_store[i].load, xoperands);
2646 }
2647 }
2648
2649 for (i = 0; i < num; i++)
2650 {
2651 int last_p = (i == num-1 && bytes == 0);
2652 int offset = load_store[i].offset;
2653
2654 xoperands[0] = operands[i+4];
2655 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
2656 plus_constant (dest_reg, offset));
2657
2658
2659 if (use_lwl_lwr)
2660 {
2661 int extra_offset;
2662 extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
2663 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
2664 plus_constant (dest_reg,
2665 extra_offset
2666 + offset));
2667 }
2668
2669 if (move_type == BLOCK_MOVE_NORMAL)
2670 output_asm_insn (load_store[i].store, xoperands);
2671
2672 else if (move_type == BLOCK_MOVE_NOT_LAST)
2673 {
2674 if (!last_p)
2675 output_asm_insn (load_store[i].store, xoperands);
2676
2677 else if (load_store[i].final != (char *)0)
2678 output_asm_insn (load_store[i].final, xoperands);
2679 }
2680
2681 else if (last_p)
2682 output_asm_insn (load_store[i].last_store, xoperands);
2683 }
2684
2685 num = 0; /* reset load_store */
2686 use_lwl_lwr = FALSE;
2687 }
2688 }
2689
2690 return "";
2691 }
2692
2693 \f
2694 /* Argument support functions. */
2695
2696 /* Initialize CUMULATIVE_ARGS for a function. */
2697
2698 void
2699 init_cumulative_args (cum, fntype, libname)
2700 CUMULATIVE_ARGS *cum; /* argument info to initialize */
2701 tree fntype; /* tree ptr for function decl */
2702 rtx libname; /* SYMBOL_REF of library name or 0 */
2703 {
2704 static CUMULATIVE_ARGS zero_cum;
2705 tree param, next_param;
2706
2707 if (TARGET_DEBUG_E_MODE)
2708 {
2709 fprintf (stderr, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
2710 if (!fntype)
2711 fputc ('\n', stderr);
2712
2713 else
2714 {
2715 tree ret_type = TREE_TYPE (fntype);
2716 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
2717 tree_code_name[ (int)TREE_CODE (fntype) ],
2718 tree_code_name[ (int)TREE_CODE (ret_type) ]);
2719 }
2720 }
2721
2722 *cum = zero_cum;
2723
2724 /* Determine if this function has variable arguments. This is
2725 indicated by the last argument being 'void_type_mode' if there
2726 are no variable arguments. The standard MIPS calling sequence
2727 passes all arguments in the general purpose registers in this
2728 case. */
2729
2730 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
2731 param != (tree)0;
2732 param = next_param)
2733 {
2734 next_param = TREE_CHAIN (param);
2735 if (next_param == (tree)0 && TREE_VALUE (param) != void_type_node)
2736 cum->gp_reg_found = 1;
2737 }
2738 }
2739
2740 /* Advance the argument to the next argument position. */
2741
2742 void
2743 function_arg_advance (cum, mode, type, named)
2744 CUMULATIVE_ARGS *cum; /* current arg information */
2745 enum machine_mode mode; /* current arg mode */
2746 tree type; /* type of the argument or 0 if lib support */
2747 int named; /* whether or not the argument was named */
2748 {
2749 if (TARGET_DEBUG_E_MODE)
2750 fprintf (stderr,
2751 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
2752 cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode),
2753 type, named);
2754
2755 cum->arg_number++;
2756 switch (mode)
2757 {
2758 case VOIDmode:
2759 break;
2760
2761 default:
2762 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
2763 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
2764 abort ();
2765 cum->gp_reg_found = 1;
2766 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
2767 / UNITS_PER_WORD);
2768 break;
2769
2770 case BLKmode:
2771 cum->gp_reg_found = 1;
2772 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
2773 / UNITS_PER_WORD);
2774 break;
2775
2776 case SFmode:
2777 cum->arg_words++;
2778 break;
2779
2780 case DFmode:
2781 cum->arg_words += (TARGET_64BIT ? 1 : 2);
2782 break;
2783
2784 case DImode:
2785 cum->gp_reg_found = 1;
2786 cum->arg_words += (TARGET_64BIT ? 1 : 2);
2787 break;
2788
2789 case QImode:
2790 case HImode:
2791 case SImode:
2792 cum->gp_reg_found = 1;
2793 cum->arg_words++;
2794 break;
2795 }
2796 }
2797
2798 /* Return an RTL expression containing the register for the given mode,
2799 or 0 if the argument is to be passed on the stack. */
2800
2801 struct rtx_def *
2802 function_arg (cum, mode, type, named)
2803 CUMULATIVE_ARGS *cum; /* current arg information */
2804 enum machine_mode mode; /* current arg mode */
2805 tree type; /* type of the argument or 0 if lib support */
2806 int named; /* != 0 for normal args, == 0 for ... args */
2807 {
2808 rtx ret;
2809 int regbase = -1;
2810 int bias = 0;
2811 int struct_p = ((type != (tree)0)
2812 && (TREE_CODE (type) == RECORD_TYPE
2813 || TREE_CODE (type) == UNION_TYPE));
2814
2815 if (TARGET_DEBUG_E_MODE)
2816 fprintf (stderr,
2817 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
2818 cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode),
2819 type, named);
2820
2821 switch (mode)
2822 {
2823 case SFmode:
2824 if (! ABI_64BIT || mips_isa < 3)
2825 {
2826 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
2827 regbase = GP_ARG_FIRST;
2828 else
2829 {
2830 regbase = FP_ARG_FIRST;
2831 /* If the first arg was a float in a floating point register,
2832 then set bias to align this float arg properly. */
2833 if (cum->arg_words == 1)
2834 bias = 1;
2835 }
2836 }
2837 else
2838 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
2839 break;
2840
2841 case DFmode:
2842 if (! TARGET_64BIT)
2843 cum->arg_words += (cum->arg_words & 1);
2844 if (! ABI_64BIT || mips_isa < 3)
2845 regbase = ((cum->gp_reg_found
2846 || TARGET_SOFT_FLOAT
2847 || TARGET_SINGLE_FLOAT
2848 || cum->arg_number >= 2)
2849 ? GP_ARG_FIRST
2850 : FP_ARG_FIRST);
2851 else
2852 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
2853 ? GP_ARG_FIRST : FP_ARG_FIRST);
2854 break;
2855
2856 default:
2857 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
2858 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
2859 abort ();
2860
2861 /* Drops through. */
2862 case BLKmode:
2863 if (type != (tree)0 && TYPE_ALIGN (type) > BITS_PER_WORD
2864 && ! TARGET_64BIT)
2865 cum->arg_words += (cum->arg_words & 1);
2866
2867 regbase = GP_ARG_FIRST;
2868 break;
2869
2870 case VOIDmode:
2871 case QImode:
2872 case HImode:
2873 case SImode:
2874 regbase = GP_ARG_FIRST;
2875 break;
2876
2877 case DImode:
2878 if (! TARGET_64BIT)
2879 cum->arg_words += (cum->arg_words & 1);
2880 regbase = GP_ARG_FIRST;
2881 }
2882
2883 if (cum->arg_words >= MAX_ARGS_IN_REGISTERS)
2884 {
2885 if (TARGET_DEBUG_E_MODE)
2886 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
2887
2888 ret = (rtx)0;
2889 }
2890 else
2891 {
2892 if (regbase == -1)
2893 abort ();
2894
2895 ret = gen_rtx (REG, mode, regbase + cum->arg_words + bias);
2896
2897 if (TARGET_DEBUG_E_MODE)
2898 fprintf (stderr, "%s%s\n", reg_names[regbase + cum->arg_words + bias],
2899 struct_p ? ", [struct]" : "");
2900
2901 /* The following is a hack in order to pass 1 byte structures
2902 the same way that the MIPS compiler does (namely by passing
2903 the structure in the high byte or half word of the register).
2904 This also makes varargs work. If we have such a structure,
2905 we save the adjustment RTL, and the call define expands will
2906 emit them. For the VOIDmode argument (argument after the
2907 last real argument), pass back a parallel vector holding each
2908 of the adjustments. */
2909
2910 /* ??? function_arg can be called more than once for each argument.
2911 As a result, we compute more adjustments than we need here.
2912 See the CUMULATIVE_ARGS definition in mips.h. */
2913
2914 /* ??? This scheme requires everything smaller than the word size to
2915 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
2916 that would mean every int needs to be shifted left, which is very
2917 inefficient. Let's not carry this compatibility to the 64 bit
2918 calling convention for now. */
2919
2920 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
2921 && ! TARGET_64BIT)
2922 {
2923 rtx amount = GEN_INT (BITS_PER_WORD
2924 - int_size_in_bytes (type) * BITS_PER_UNIT);
2925 rtx reg = gen_rtx (REG, word_mode, regbase + cum->arg_words + bias);
2926 if (TARGET_64BIT)
2927 cum->adjust[ cum->num_adjusts++ ] = gen_ashldi3 (reg, reg, amount);
2928 else
2929 cum->adjust[ cum->num_adjusts++ ] = gen_ashlsi3 (reg, reg, amount);
2930 }
2931 }
2932
2933 if (mode == VOIDmode && cum->num_adjusts > 0)
2934 ret = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (cum->num_adjusts, cum->adjust));
2935
2936 return ret;
2937 }
2938
2939
2940 int
2941 function_arg_partial_nregs (cum, mode, type, named)
2942 CUMULATIVE_ARGS *cum; /* current arg information */
2943 enum machine_mode mode; /* current arg mode */
2944 tree type; /* type of the argument or 0 if lib support */
2945 int named; /* != 0 for normal args, == 0 for ... args */
2946 {
2947 if ((mode == BLKmode
2948 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
2949 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
2950 && cum->arg_words < MAX_ARGS_IN_REGISTERS)
2951 {
2952 int words;
2953 if (mode == BLKmode)
2954 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
2955 / UNITS_PER_WORD);
2956 else
2957 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2958
2959 if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS)
2960 return 0; /* structure fits in registers */
2961
2962 if (TARGET_DEBUG_E_MODE)
2963 fprintf (stderr, "function_arg_partial_nregs = %d\n",
2964 MAX_ARGS_IN_REGISTERS - cum->arg_words);
2965
2966 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
2967 }
2968
2969 else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1
2970 && ! TARGET_64BIT)
2971 {
2972 if (TARGET_DEBUG_E_MODE)
2973 fprintf (stderr, "function_arg_partial_nregs = 1\n");
2974
2975 return 1;
2976 }
2977
2978 return 0;
2979 }
2980
2981 \f
2982 /* Print the options used in the assembly file. */
2983
2984 static struct {char *name; int value;} target_switches []
2985 = TARGET_SWITCHES;
2986
2987 void
2988 print_options (out)
2989 FILE *out;
2990 {
2991 int line_len;
2992 int len;
2993 int j;
2994 char **p;
2995 int mask = TARGET_DEFAULT;
2996
2997 /* Allow assembly language comparisons with -mdebug eliminating the
2998 compiler version number and switch lists. */
2999
3000 if (TARGET_DEBUG_MODE)
3001 return;
3002
3003 fprintf (out, "\n # %s %s", language_string, version_string);
3004 #ifdef TARGET_VERSION_INTERNAL
3005 TARGET_VERSION_INTERNAL (out);
3006 #endif
3007 #ifdef __GNUC__
3008 fprintf (out, " compiled by GNU C\n\n");
3009 #else
3010 fprintf (out, " compiled by CC\n\n");
3011 #endif
3012
3013 fprintf (out, " # Cc1 defaults:");
3014 line_len = 32767;
3015 for (j = 0; j < sizeof target_switches / sizeof target_switches[0]; j++)
3016 {
3017 if (target_switches[j].name[0] != '\0'
3018 && target_switches[j].value > 0
3019 && (target_switches[j].value & mask) == target_switches[j].value)
3020 {
3021 mask &= ~ target_switches[j].value;
3022 len = strlen (target_switches[j].name) + 1;
3023 if (len + line_len > 79)
3024 {
3025 line_len = 2;
3026 fputs ("\n #", out);
3027 }
3028 fprintf (out, " -m%s", target_switches[j].name);
3029 line_len += len;
3030 }
3031 }
3032
3033 fprintf (out, "\n\n # Cc1 arguments (-G value = %d, Cpu = %s, ISA = %d):",
3034 mips_section_threshold, mips_cpu_string, mips_isa);
3035
3036 line_len = 32767;
3037 for (p = &save_argv[1]; *p != (char *)0; p++)
3038 {
3039 char *arg = *p;
3040 if (*arg == '-')
3041 {
3042 len = strlen (arg) + 1;
3043 if (len + line_len > 79)
3044 {
3045 line_len = 2;
3046 fputs ("\n #", out);
3047 }
3048 fprintf (out, " %s", *p);
3049 line_len += len;
3050 }
3051 }
3052
3053 fputs ("\n\n", out);
3054 }
3055
3056 \f
3057 /* Abort after printing out a specific insn. */
3058
3059 void
3060 abort_with_insn (insn, reason)
3061 rtx insn;
3062 char *reason;
3063 {
3064 error (reason);
3065 debug_rtx (insn);
3066 abort ();
3067 }
3068
3069 /* Write a message to stderr (for use in macros expanded in files that do not
3070 include stdio.h). */
3071
3072 void
3073 trace (s, s1, s2)
3074 char *s, *s1, *s2;
3075 {
3076 fprintf (stderr, s, s1, s2);
3077 }
3078
3079 \f
3080 #ifdef SIGINFO
3081
3082 static void
3083 siginfo (signo)
3084 int signo;
3085 {
3086 fprintf (stderr, "compiling '%s' in '%s'\n",
3087 (current_function_name != (char *)0) ? current_function_name : "<toplevel>",
3088 (current_function_file != (char *)0) ? current_function_file : "<no file>");
3089 fflush (stderr);
3090 }
3091 #endif /* SIGINFO */
3092
3093 \f
3094 /* Set up the threshold for data to go into the small data area, instead
3095 of the normal data area, and detect any conflicts in the switches. */
3096
3097 void
3098 override_options ()
3099 {
3100 register int i, start;
3101 register int regno;
3102 register enum machine_mode mode;
3103
3104 mips_section_threshold = (g_switch_set) ? g_switch_value : MIPS_DEFAULT_GVALUE;
3105
3106 if (mips_section_threshold <= 0)
3107 target_flags &= ~MASK_GPOPT;
3108 else if (optimize)
3109 target_flags |= MASK_GPOPT;
3110
3111 /* Get the architectural level. */
3112 if (mips_isa_string == (char *)0)
3113 {
3114 #ifdef MIPS_ISA_DEFAULT
3115 mips_isa = MIPS_ISA_DEFAULT;
3116 #else
3117 mips_isa = 1;
3118 #endif
3119 }
3120
3121 else if (isdigit (*mips_isa_string))
3122 {
3123 mips_isa = atoi (mips_isa_string);
3124 if (mips_isa < 1 || mips_isa > 4)
3125 {
3126 error ("-mips%d not supported", mips_isa);
3127 mips_isa = 1;
3128 }
3129 }
3130
3131 else
3132 {
3133 error ("bad value (%s) for -mips switch", mips_isa_string);
3134 mips_isa = 1;
3135 }
3136
3137 /* Identify the processor type */
3138 if (mips_cpu_string == (char *)0
3139 || !strcmp (mips_cpu_string, "default")
3140 || !strcmp (mips_cpu_string, "DEFAULT"))
3141 {
3142 switch (mips_isa)
3143 {
3144 default:
3145 mips_cpu_string = "3000";
3146 mips_cpu = PROCESSOR_R3000;
3147 break;
3148 case 2:
3149 mips_cpu_string = "6000";
3150 mips_cpu = PROCESSOR_R6000;
3151 break;
3152 case 3:
3153 mips_cpu_string = "4000";
3154 mips_cpu = PROCESSOR_R4000;
3155 break;
3156 case 4:
3157 mips_cpu_string = "8000";
3158 mips_cpu = PROCESSOR_R8000;
3159 break;
3160 }
3161
3162 #ifdef MIPS_CPU_DEFAULT
3163 if (mips_isa_string == (char *)0)
3164 {
3165 mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
3166 mips_cpu = MIPS_CPU_DEFAULT;
3167 }
3168 #endif
3169 }
3170
3171 else
3172 {
3173 char *p = mips_cpu_string;
3174
3175 if (*p == 'r' || *p == 'R')
3176 p++;
3177
3178 /* Since there is no difference between a R2000 and R3000 in
3179 terms of the scheduler, we collapse them into just an R3000. */
3180
3181 mips_cpu = PROCESSOR_DEFAULT;
3182 switch (*p)
3183 {
3184 case '2':
3185 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
3186 mips_cpu = PROCESSOR_R3000;
3187 break;
3188
3189 case '3':
3190 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
3191 mips_cpu = PROCESSOR_R3000;
3192 break;
3193
3194 case '4':
3195 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
3196 mips_cpu = PROCESSOR_R4000;
3197 /* The r4400 is exactly the same as the r4000 from the compiler's
3198 viewpoint. */
3199 else if (!strcmp (p, "4400"))
3200 mips_cpu = PROCESSOR_R4000;
3201 else if (!strcmp (p, "4600"))
3202 mips_cpu = PROCESSOR_R4600;
3203 /* Although the r4650 adds a couple of instructions, it uses
3204 the r4600 pipeline. */
3205 else if (!strcmp (p, "4650"))
3206 mips_cpu = PROCESSOR_R4600;
3207 break;
3208
3209 case '6':
3210 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
3211 mips_cpu = PROCESSOR_R6000;
3212 break;
3213
3214 case '8':
3215 if (!strcmp (p, "8000"))
3216 mips_cpu = PROCESSOR_R8000;
3217 break;
3218
3219 case 'o':
3220 if (!strcmp (p, "orion"))
3221 mips_cpu = PROCESSOR_R4600;
3222 break;
3223 }
3224
3225 if (mips_cpu == PROCESSOR_DEFAULT)
3226 {
3227 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
3228 mips_cpu_string = "default";
3229 }
3230 }
3231
3232 if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
3233 || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
3234 || ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R4600)
3235 && mips_isa > 3))
3236 error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
3237
3238 /* make sure sizes of ints/longs/etc. are ok */
3239 if (mips_isa < 3)
3240 {
3241 if (TARGET_INT64)
3242 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3243
3244 else if (TARGET_LONG64)
3245 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3246
3247 else if (TARGET_FLOAT64)
3248 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3249
3250 else if (TARGET_64BIT)
3251 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3252 }
3253
3254 if (ABI_64BIT && mips_isa >= 3)
3255 flag_pcc_struct_return = 0;
3256
3257 /* Tell halfpic.c that we have half-pic code if we do. */
3258 if (TARGET_HALF_PIC)
3259 HALF_PIC_INIT ();
3260
3261 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3262 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3263 /* ??? -non_shared turns off pic code generation, but this is not
3264 implemented. */
3265 if (TARGET_ABICALLS)
3266 {
3267 mips_abicalls = MIPS_ABICALLS_YES;
3268 flag_pic = 1;
3269 if (mips_section_threshold > 0)
3270 warning ("-G is incompatible with PIC code which is the default");
3271 }
3272 else
3273 mips_abicalls = MIPS_ABICALLS_NO;
3274
3275 /* -membedded-pic is a form of PIC code suitable for embedded
3276 systems. All calls are made using PC relative addressing, and
3277 all data is addressed using the $gp register. This requires gas,
3278 which does most of the work, and GNU ld, which automatically
3279 expands PC relative calls which are out of range into a longer
3280 instruction sequence. All gcc really does differently is
3281 generate a different sequence for a switch. */
3282 if (TARGET_EMBEDDED_PIC)
3283 {
3284 flag_pic = 1;
3285 if (TARGET_ABICALLS)
3286 warning ("-membedded-pic and -mabicalls are incompatible");
3287 if (g_switch_set)
3288 warning ("-G and -membedded-pic are incompatible");
3289 /* Setting mips_section_threshold is not required, because gas
3290 will force everything to be GP addressable anyhow, but
3291 setting it will cause gcc to make better estimates of the
3292 number of instructions required to access a particular data
3293 item. */
3294 mips_section_threshold = 0x7fffffff;
3295 }
3296
3297 /* -mrnames says to use the MIPS software convention for register
3298 names instead of the hardware names (ie, $a0 instead of $4).
3299 We do this by switching the names in mips_reg_names, which the
3300 reg_names points into via the REGISTER_NAMES macro. */
3301
3302 if (TARGET_NAME_REGS)
3303 bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names, sizeof (mips_reg_names));
3304
3305 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3306 is currently being compiled. */
3307 #ifdef SIGINFO
3308 if (getenv ("GCC_SIGINFO") != (char *)0)
3309 {
3310 struct sigaction action;
3311 action.sa_handler = siginfo;
3312 action.sa_mask = 0;
3313 action.sa_flags = SA_RESTART;
3314 sigaction (SIGINFO, &action, (struct sigaction *)0);
3315 }
3316 #endif
3317
3318 #if defined(_IOLBF)
3319 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3320 /* If -mstats and -quiet, make stderr line buffered. */
3321 if (quiet_flag && TARGET_STATS)
3322 setvbuf (stderr, (char *)0, _IOLBF, BUFSIZ);
3323 #endif
3324 #endif
3325
3326 /* Initialize the high and low values for legitimate floating point
3327 constants. Rather than trying to get the accuracy down to the
3328 last bit, just use approximate ranges. */
3329 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
3330 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
3331 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
3332 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
3333
3334 mips_print_operand_punct['?'] = TRUE;
3335 mips_print_operand_punct['#'] = TRUE;
3336 mips_print_operand_punct['&'] = TRUE;
3337 mips_print_operand_punct['!'] = TRUE;
3338 mips_print_operand_punct['*'] = TRUE;
3339 mips_print_operand_punct['@'] = TRUE;
3340 mips_print_operand_punct['.'] = TRUE;
3341 mips_print_operand_punct['('] = TRUE;
3342 mips_print_operand_punct[')'] = TRUE;
3343 mips_print_operand_punct['['] = TRUE;
3344 mips_print_operand_punct[']'] = TRUE;
3345 mips_print_operand_punct['<'] = TRUE;
3346 mips_print_operand_punct['>'] = TRUE;
3347 mips_print_operand_punct['{'] = TRUE;
3348 mips_print_operand_punct['}'] = TRUE;
3349 mips_print_operand_punct['^'] = TRUE;
3350
3351 mips_char_to_class['d'] = GR_REGS;
3352 mips_char_to_class['f'] = ((TARGET_HARD_FLOAT) ? FP_REGS : NO_REGS);
3353 mips_char_to_class['h'] = HI_REG;
3354 mips_char_to_class['l'] = LO_REG;
3355 mips_char_to_class['x'] = MD_REGS;
3356 mips_char_to_class['y'] = GR_REGS;
3357 mips_char_to_class['z'] = ST_REGS;
3358
3359 /* Set up array to map GCC register number to debug register number.
3360 Ignore the special purpose register numbers. */
3361
3362 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3363 mips_dbx_regno[i] = -1;
3364
3365 start = GP_DBX_FIRST - GP_REG_FIRST;
3366 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
3367 mips_dbx_regno[i] = i + start;
3368
3369 start = FP_DBX_FIRST - FP_REG_FIRST;
3370 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
3371 mips_dbx_regno[i] = i + start;
3372
3373 /* Set up array giving whether a given register can hold a given mode.
3374 At present, restrict ints from being in FP registers, because reload
3375 is a little enthusiastic about storing extra values in FP registers,
3376 and this is not good for things like OS kernels. Also, due to the
3377 mandatory delay, it is as fast to load from cached memory as to move
3378 from the FP register. */
3379
3380 for (mode = VOIDmode;
3381 mode != MAX_MACHINE_MODE;
3382 mode = (enum machine_mode)((int)mode + 1))
3383 {
3384 register int size = GET_MODE_SIZE (mode);
3385 register enum mode_class class = GET_MODE_CLASS (mode);
3386
3387 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
3388 {
3389 register int temp;
3390
3391 if (mode == CC_FPmode || mode == CC_REV_FPmode)
3392 temp = (regno == FPSW_REGNUM);
3393
3394 else if (GP_REG_P (regno))
3395 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
3396
3397 else if (FP_REG_P (regno))
3398 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
3399 && (class == MODE_FLOAT
3400 || class == MODE_COMPLEX_FLOAT
3401 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
3402 && (! TARGET_SINGLE_FLOAT || size <= 4));
3403
3404 else if (MD_REG_P (regno))
3405 temp = (size <= UNITS_PER_WORD
3406 || (regno == MD_REG_FIRST && size == 2 * UNITS_PER_WORD));
3407
3408 else
3409 temp = FALSE;
3410
3411 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
3412 }
3413 }
3414 }
3415
3416 \f
3417 /*
3418 * The MIPS debug format wants all automatic variables and arguments
3419 * to be in terms of the virtual frame pointer (stack pointer before
3420 * any adjustment in the function), while the MIPS 3.0 linker wants
3421 * the frame pointer to be the stack pointer after the initial
3422 * adjustment. So, we do the adjustment here. The arg pointer (which
3423 * is eliminated) points to the virtual frame pointer, while the frame
3424 * pointer (which may be eliminated) points to the stack pointer after
3425 * the initial adjustments.
3426 */
3427
3428 int
3429 mips_debugger_offset (addr, offset)
3430 rtx addr;
3431 int offset;
3432 {
3433 rtx offset2 = const0_rtx;
3434 rtx reg = eliminate_constant_term (addr, &offset2);
3435
3436 if (!offset)
3437 offset = INTVAL (offset2);
3438
3439 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx)
3440 {
3441 int frame_size = (!current_frame_info.initialized)
3442 ? compute_frame_size (get_frame_size ())
3443 : current_frame_info.total_size;
3444
3445 offset = offset - frame_size;
3446 }
3447 /* sdbout_parms does not want this to crash for unrecognized cases. */
3448 #if 0
3449 else if (reg != arg_pointer_rtx)
3450 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
3451 #endif
3452
3453 return offset;
3454 }
3455
3456 \f
3457 /* A C compound statement to output to stdio stream STREAM the
3458 assembler syntax for an instruction operand X. X is an RTL
3459 expression.
3460
3461 CODE is a value that can be used to specify one of several ways
3462 of printing the operand. It is used when identical operands
3463 must be printed differently depending on the context. CODE
3464 comes from the `%' specification that was used to request
3465 printing of the operand. If the specification was just `%DIGIT'
3466 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3467 is the ASCII code for LTR.
3468
3469 If X is a register, this macro should print the register's name.
3470 The names can be found in an array `reg_names' whose type is
3471 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3472
3473 When the machine description has a specification `%PUNCT' (a `%'
3474 followed by a punctuation character), this macro is called with
3475 a null pointer for X and the punctuation character for CODE.
3476
3477 The MIPS specific codes are:
3478
3479 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3480 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3481 'd' output integer constant in decimal,
3482 'z' if the operand is 0, use $0 instead of normal operand.
3483 'D' print second register of double-word register operand.
3484 'L' print low-order register of double-word register operand.
3485 'M' print high-order register of double-word register operand.
3486 'C' print part of opcode for a branch condition.
3487 'N' print part of opcode for a branch condition, inverted.
3488 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3489 'B' print 'z' for EQ, 'n' for NE
3490 'b' print 'n' for EQ, 'z' for NE
3491 'T' print 'f' for EQ, 't' for NE
3492 't' print 't' for EQ, 'f' for NE
3493 '(' Turn on .set noreorder
3494 ')' Turn on .set reorder
3495 '[' Turn on .set noat
3496 ']' Turn on .set at
3497 '<' Turn on .set nomacro
3498 '>' Turn on .set macro
3499 '{' Turn on .set volatile (not GAS)
3500 '}' Turn on .set novolatile (not GAS)
3501 '&' Turn on .set noreorder if filling delay slots
3502 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3503 '!' Turn on .set nomacro if filling delay slots
3504 '#' Print nop if in a .set noreorder section.
3505 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3506 '@' Print the name of the assembler temporary register (at or $1).
3507 '.' Print the name of the register with a hard-wired zero (zero or $0).
3508 '^' Print the name of the pic call-through register (t9 or $25). */
3509
3510 void
3511 print_operand (file, op, letter)
3512 FILE *file; /* file to write to */
3513 rtx op; /* operand to print */
3514 int letter; /* %<letter> or 0 */
3515 {
3516 register enum rtx_code code;
3517
3518 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
3519 {
3520 switch (letter)
3521 {
3522 default:
3523 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
3524 break;
3525
3526 case '?':
3527 if (mips_branch_likely)
3528 putc ('l', file);
3529 break;
3530
3531 case '@':
3532 fputs (reg_names [GP_REG_FIRST + 1], file);
3533 break;
3534
3535 case '^':
3536 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
3537 break;
3538
3539 case '.':
3540 fputs (reg_names [GP_REG_FIRST + 0], file);
3541 break;
3542
3543 case '&':
3544 if (final_sequence != 0 && set_noreorder++ == 0)
3545 fputs (".set\tnoreorder\n\t", file);
3546 break;
3547
3548 case '*':
3549 if (final_sequence != 0)
3550 {
3551 if (set_noreorder++ == 0)
3552 fputs (".set\tnoreorder\n\t", file);
3553
3554 if (set_nomacro++ == 0)
3555 fputs (".set\tnomacro\n\t", file);
3556 }
3557 break;
3558
3559 case '!':
3560 if (final_sequence != 0 && set_nomacro++ == 0)
3561 fputs ("\n\t.set\tnomacro", file);
3562 break;
3563
3564 case '#':
3565 if (set_noreorder != 0)
3566 fputs ("\n\tnop", file);
3567
3568 else if (TARGET_STATS)
3569 fputs ("\n\t#nop", file);
3570
3571 break;
3572
3573 case '(':
3574 if (set_noreorder++ == 0)
3575 fputs (".set\tnoreorder\n\t", file);
3576 break;
3577
3578 case ')':
3579 if (set_noreorder == 0)
3580 error ("internal error: %%) found without a %%( in assembler pattern");
3581
3582 else if (--set_noreorder == 0)
3583 fputs ("\n\t.set\treorder", file);
3584
3585 break;
3586
3587 case '[':
3588 if (set_noat++ == 0)
3589 fputs (".set\tnoat\n\t", file);
3590 break;
3591
3592 case ']':
3593 if (set_noat == 0)
3594 error ("internal error: %%] found without a %%[ in assembler pattern");
3595
3596 else if (--set_noat == 0)
3597 fputs ("\n\t.set\tat", file);
3598
3599 break;
3600
3601 case '<':
3602 if (set_nomacro++ == 0)
3603 fputs (".set\tnomacro\n\t", file);
3604 break;
3605
3606 case '>':
3607 if (set_nomacro == 0)
3608 error ("internal error: %%> found without a %%< in assembler pattern");
3609
3610 else if (--set_nomacro == 0)
3611 fputs ("\n\t.set\tmacro", file);
3612
3613 break;
3614
3615 case '{':
3616 if (set_volatile++ == 0)
3617 fprintf (file, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS) ? "" : "#");
3618 break;
3619
3620 case '}':
3621 if (set_volatile == 0)
3622 error ("internal error: %%} found without a %%{ in assembler pattern");
3623
3624 else if (--set_volatile == 0)
3625 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
3626
3627 break;
3628 }
3629 return;
3630 }
3631
3632 if (! op)
3633 {
3634 error ("PRINT_OPERAND null pointer");
3635 return;
3636 }
3637
3638 code = GET_CODE (op);
3639 if (letter == 'C')
3640 switch (code)
3641 {
3642 case EQ: fputs ("eq", file); break;
3643 case NE: fputs ("ne", file); break;
3644 case GT: fputs ("gt", file); break;
3645 case GE: fputs ("ge", file); break;
3646 case LT: fputs ("lt", file); break;
3647 case LE: fputs ("le", file); break;
3648 case GTU: fputs ("gtu", file); break;
3649 case GEU: fputs ("geu", file); break;
3650 case LTU: fputs ("ltu", file); break;
3651 case LEU: fputs ("leu", file); break;
3652
3653 default:
3654 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
3655 }
3656
3657 else if (letter == 'N')
3658 switch (code)
3659 {
3660 case EQ: fputs ("ne", file); break;
3661 case NE: fputs ("eq", file); break;
3662 case GT: fputs ("le", file); break;
3663 case GE: fputs ("lt", file); break;
3664 case LT: fputs ("ge", file); break;
3665 case LE: fputs ("gt", file); break;
3666 case GTU: fputs ("leu", file); break;
3667 case GEU: fputs ("ltu", file); break;
3668 case LTU: fputs ("geu", file); break;
3669 case LEU: fputs ("gtu", file); break;
3670
3671 default:
3672 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
3673 }
3674
3675 else if (letter == 'S')
3676 {
3677 char buffer[100];
3678
3679 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
3680 assemble_name (file, buffer);
3681 }
3682
3683 else if (code == REG)
3684 {
3685 register int regnum = REGNO (op);
3686
3687 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
3688 || (letter == 'L' && WORDS_BIG_ENDIAN)
3689 || letter == 'D')
3690 regnum++;
3691
3692 fprintf (file, "%s", reg_names[regnum]);
3693 }
3694
3695 else if (code == MEM)
3696 output_address (XEXP (op, 0));
3697
3698 else if (code == CONST_DOUBLE
3699 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
3700 {
3701 REAL_VALUE_TYPE d;
3702 char s[30];
3703
3704 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
3705 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
3706 fprintf (file, s);
3707 }
3708
3709 else if ((letter == 'x') && (GET_CODE(op) == CONST_INT))
3710 fprintf (file, "0x%04x", 0xffff & (INTVAL(op)));
3711
3712 else if ((letter == 'X') && (GET_CODE(op) == CONST_INT)
3713 && HOST_BITS_PER_WIDE_INT == 32)
3714 fprintf (file, "0x%08x", INTVAL(op));
3715
3716 else if ((letter == 'X') && (GET_CODE(op) == CONST_INT)
3717 && HOST_BITS_PER_WIDE_INT == 64)
3718 fprintf (file, "0x%016lx", INTVAL(op));
3719
3720 else if ((letter == 'd') && (GET_CODE(op) == CONST_INT))
3721 fprintf (file, "%d", (INTVAL(op)));
3722
3723 else if (letter == 'z'
3724 && (GET_CODE (op) == CONST_INT)
3725 && INTVAL (op) == 0)
3726 fputs (reg_names[GP_REG_FIRST], file);
3727
3728 else if (letter == 'd' || letter == 'x' || letter == 'X')
3729 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter);
3730
3731 else if (letter == 'B')
3732 fputs (code == EQ ? "z" : "n", file);
3733 else if (letter == 'b')
3734 fputs (code == EQ ? "n" : "z", file);
3735 else if (letter == 'T')
3736 fputs (code == EQ ? "f" : "t", file);
3737 else if (letter == 't')
3738 fputs (code == EQ ? "t" : "f", file);
3739
3740 else
3741 output_addr_const (file, op);
3742 }
3743
3744 \f
3745 /* A C compound statement to output to stdio stream STREAM the
3746 assembler syntax for an instruction operand that is a memory
3747 reference whose address is ADDR. ADDR is an RTL expression.
3748
3749 On some machines, the syntax for a symbolic address depends on
3750 the section that the address refers to. On these machines,
3751 define the macro `ENCODE_SECTION_INFO' to store the information
3752 into the `symbol_ref', and then check for it here. */
3753
3754 void
3755 print_operand_address (file, addr)
3756 FILE *file;
3757 rtx addr;
3758 {
3759 if (!addr)
3760 error ("PRINT_OPERAND_ADDRESS, null pointer");
3761
3762 else
3763 switch (GET_CODE (addr))
3764 {
3765 default:
3766 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
3767 break;
3768
3769 case REG:
3770 if (REGNO (addr) == ARG_POINTER_REGNUM)
3771 abort_with_insn (addr, "Arg pointer not eliminated.");
3772
3773 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
3774 break;
3775
3776 case PLUS:
3777 {
3778 register rtx reg = (rtx)0;
3779 register rtx offset = (rtx)0;
3780 register rtx arg0 = XEXP (addr, 0);
3781 register rtx arg1 = XEXP (addr, 1);
3782
3783 if (GET_CODE (arg0) == REG)
3784 {
3785 reg = arg0;
3786 offset = arg1;
3787 if (GET_CODE (offset) == REG)
3788 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
3789 }
3790 else if (GET_CODE (arg1) == REG)
3791 {
3792 reg = arg1;
3793 offset = arg0;
3794 }
3795 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
3796 {
3797 output_addr_const (file, addr);
3798 break;
3799 }
3800 else
3801 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
3802
3803 if (!CONSTANT_P (offset))
3804 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
3805
3806 if (REGNO (reg) == ARG_POINTER_REGNUM)
3807 abort_with_insn (addr, "Arg pointer not eliminated.");
3808
3809 output_addr_const (file, offset);
3810 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
3811 }
3812 break;
3813
3814 case LABEL_REF:
3815 case SYMBOL_REF:
3816 case CONST_INT:
3817 case CONST:
3818 output_addr_const (file, addr);
3819 break;
3820 }
3821 }
3822
3823 \f
3824 /* If optimizing for the global pointer, keep track of all of
3825 the externs, so that at the end of the file, we can emit
3826 the appropriate .extern declaration for them, before writing
3827 out the text section. We assume that all names passed to
3828 us are in the permanent obstack, so that they will be valid
3829 at the end of the compilation.
3830
3831 If we have -G 0, or the extern size is unknown, don't bother
3832 emitting the .externs. */
3833
3834 int
3835 mips_output_external (file, decl, name)
3836 FILE *file;
3837 tree decl;
3838 char *name;
3839 {
3840 register struct extern_list *p;
3841 int len;
3842
3843 if (TARGET_GP_OPT
3844 && ((TREE_CODE (decl)) != FUNCTION_DECL)
3845 && ((len = int_size_in_bytes (TREE_TYPE (decl))) > 0))
3846 {
3847 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
3848 p->next = extern_head;
3849 p->name = name;
3850 p->size = len;
3851 extern_head = p;
3852 }
3853
3854 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
3855 if (TREE_CODE (decl) == FUNCTION_DECL
3856 /* ??? Don't include alloca, since gcc will always expand it
3857 inline. If we don't do this, libg++ fails to build. */
3858 && strcmp (name, "alloca")
3859 /* ??? Don't include __builtin_next_arg, because then gcc will not
3860 bootstrap under Irix 5.1. */
3861 && strcmp (name, "__builtin_next_arg"))
3862 {
3863 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
3864 p->next = extern_head;
3865 p->name = name;
3866 p->size = -1;
3867 extern_head = p;
3868 }
3869 #endif
3870
3871 return 0;
3872 }
3873
3874 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
3875 int
3876 mips_output_external_libcall (file, name)
3877 FILE *file;
3878 char *name;
3879 {
3880 register struct extern_list *p;
3881
3882 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
3883 p->next = extern_head;
3884 p->name = name;
3885 p->size = -1;
3886 extern_head = p;
3887
3888 return 0;
3889 }
3890 #endif
3891
3892 \f
3893 /* Compute a string to use as a temporary file name. */
3894
3895 /* On MSDOS, write temp files in current dir
3896 because there's no place else we can expect to use. */
3897 #if __MSDOS__
3898 #ifndef P_tmpdir
3899 #define P_tmpdir "./"
3900 #endif
3901 #endif
3902
3903 static FILE *
3904 make_temp_file ()
3905 {
3906 FILE *stream;
3907 char *base = getenv ("TMPDIR");
3908 int len;
3909
3910 if (base == (char *)0)
3911 {
3912 #ifdef P_tmpdir
3913 if (access (P_tmpdir, R_OK | W_OK) == 0)
3914 base = P_tmpdir;
3915 else
3916 #endif
3917 if (access ("/usr/tmp", R_OK | W_OK) == 0)
3918 base = "/usr/tmp/";
3919 else
3920 base = "/tmp/";
3921 }
3922
3923 len = strlen (base);
3924 /* temp_filename is global, so we must use malloc, not alloca. */
3925 temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX"));
3926 strcpy (temp_filename, base);
3927 if (len > 0 && temp_filename[len-1] != '/')
3928 temp_filename[len++] = '/';
3929
3930 strcpy (temp_filename + len, "ctXXXXXX");
3931 mktemp (temp_filename);
3932
3933 stream = fopen (temp_filename, "w+");
3934 if (!stream)
3935 pfatal_with_name (temp_filename);
3936
3937 #ifndef __MSDOS__
3938 /* In MSDOS, we cannot unlink the temporary file until we are finished using
3939 it. Otherwise, we delete it now, so that it will be gone even if the
3940 compiler happens to crash. */
3941 unlink (temp_filename);
3942 #endif
3943 return stream;
3944 }
3945
3946 \f
3947 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
3948 for .file's that start within a function. If we are smuggling stabs, try to
3949 put out a MIPS ECOFF file and a stab. */
3950
3951 void
3952 mips_output_filename (stream, name)
3953 FILE *stream;
3954 char *name;
3955 {
3956 static int first_time = TRUE;
3957 char ltext_label_name[100];
3958
3959 if (first_time)
3960 {
3961 first_time = FALSE;
3962 SET_FILE_NUMBER ();
3963 current_function_file = name;
3964 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
3965 /* This tells mips-tfile that stabs will follow. */
3966 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
3967 fprintf (stream, "\t#@stabs\n");
3968 }
3969
3970 else if (write_symbols == DBX_DEBUG)
3971 {
3972 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
3973 fprintf (stream, "%s ", ASM_STABS_OP);
3974 output_quoted_string (stream, name);
3975 fprintf (stream, ",%d,0,0,%s\n", N_SOL, &ltext_label_name[1]);
3976 }
3977
3978 else if (name != current_function_file
3979 && strcmp (name, current_function_file) != 0)
3980 {
3981 if (inside_function && !TARGET_GAS)
3982 {
3983 if (!file_in_function_warning)
3984 {
3985 file_in_function_warning = TRUE;
3986 ignore_line_number = TRUE;
3987 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
3988 }
3989 }
3990 else
3991 {
3992 SET_FILE_NUMBER ();
3993 current_function_file = name;
3994 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
3995 }
3996 }
3997 }
3998
3999 \f
4000 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4001 as well as a .loc, since it is possible that MIPS ECOFF might not be
4002 able to represent the location for inlines that come from a different
4003 file. */
4004
4005 void
4006 mips_output_lineno (stream, line)
4007 FILE *stream;
4008 int line;
4009 {
4010 if (write_symbols == DBX_DEBUG)
4011 {
4012 ++sym_lineno;
4013 fprintf (stream, "$LM%d:\n\t%s %d,0,%d,$LM%d\n",
4014 sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno);
4015 }
4016
4017 else
4018 {
4019 fprintf (stream, "\n\t%s.loc\t%d %d\n",
4020 (ignore_line_number) ? "#" : "",
4021 num_source_filenames, line);
4022
4023 LABEL_AFTER_LOC (stream);
4024 }
4025 }
4026
4027 \f
4028 /* If defined, a C statement to be executed just prior to the
4029 output of assembler code for INSN, to modify the extracted
4030 operands so they will be output differently.
4031
4032 Here the argument OPVEC is the vector containing the operands
4033 extracted from INSN, and NOPERANDS is the number of elements of
4034 the vector which contain meaningful data for this insn. The
4035 contents of this vector are what will be used to convert the
4036 insn template into assembler code, so you can change the
4037 assembler output by changing the contents of the vector.
4038
4039 We use it to check if the current insn needs a nop in front of it
4040 because of load delays, and also to update the delay slot
4041 statistics. */
4042
4043 /* ??? There is no real need for this function, because it never actually
4044 emits a NOP anymore. */
4045
4046 void
4047 final_prescan_insn (insn, opvec, noperands)
4048 rtx insn;
4049 rtx opvec[];
4050 int noperands;
4051 {
4052 if (dslots_number_nops > 0)
4053 {
4054 rtx pattern = PATTERN (insn);
4055 int length = get_attr_length (insn);
4056
4057 /* Do we need to emit a NOP? */
4058 if (length == 0
4059 || (mips_load_reg != (rtx)0 && reg_mentioned_p (mips_load_reg, pattern))
4060 || (mips_load_reg2 != (rtx)0 && reg_mentioned_p (mips_load_reg2, pattern))
4061 || (mips_load_reg3 != (rtx)0 && reg_mentioned_p (mips_load_reg3, pattern))
4062 || (mips_load_reg4 != (rtx)0 && reg_mentioned_p (mips_load_reg4, pattern)))
4063 fputs ("\t#nop\n", asm_out_file);
4064
4065 else
4066 dslots_load_filled++;
4067
4068 while (--dslots_number_nops > 0)
4069 fputs ("\t#nop\n", asm_out_file);
4070
4071 mips_load_reg = (rtx)0;
4072 mips_load_reg2 = (rtx)0;
4073 mips_load_reg3 = (rtx)0;
4074 mips_load_reg4 = (rtx)0;
4075 }
4076
4077 if (TARGET_STATS)
4078 {
4079 enum rtx_code code = GET_CODE (insn);
4080 if (code == JUMP_INSN || code == CALL_INSN)
4081 dslots_jump_total++;
4082 }
4083 }
4084
4085 \f
4086 /* Output at beginning of assembler file.
4087 If we are optimizing to use the global pointer, create a temporary
4088 file to hold all of the text stuff, and write it out to the end.
4089 This is needed because the MIPS assembler is evidently one pass,
4090 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4091 declaration when the code is processed, it generates a two
4092 instruction sequence. */
4093
4094 void
4095 mips_asm_file_start (stream)
4096 FILE *stream;
4097 {
4098 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
4099
4100 /* Versions of the MIPS assembler before 2.20 generate errors
4101 if a branch inside of a .set noreorder section jumps to a
4102 label outside of the .set noreorder section. Revision 2.20
4103 just set nobopt silently rather than fixing the bug. */
4104
4105 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
4106 fprintf (stream, "\t.set\tnobopt\n");
4107
4108 /* Generate the pseudo ops that System V.4 wants. */
4109 #ifndef ABICALLS_ASM_OP
4110 #define ABICALLS_ASM_OP ".abicalls"
4111 #endif
4112 if (TARGET_ABICALLS)
4113 /* ??? but do not want this (or want pic0) if -non-shared? */
4114 fprintf (stream, "\t%s\n", ABICALLS_ASM_OP);
4115
4116 /* Start a section, so that the first .popsection directive is guaranteed
4117 to have a previously defined section to pop back to. */
4118 if (ABI_64BIT && mips_isa >= 3)
4119 fprintf (stream, "\t.section\t.text\n");
4120
4121 /* This code exists so that we can put all externs before all symbol
4122 references. This is necessary for the assembler's global pointer
4123 optimizations to work. */
4124 /* ??? Current versions of gas do not require that externs occur before
4125 symbol references. This means that this code is unnecessary when
4126 gas is being used. This gas feature hasn't been well tested as yet
4127 though. */
4128 if (TARGET_GP_OPT)
4129 {
4130 asm_out_data_file = stream;
4131 asm_out_text_file = make_temp_file ();
4132 }
4133 else
4134 asm_out_data_file = asm_out_text_file = stream;
4135
4136 print_options (stream);
4137 }
4138
4139 \f
4140 /* If we are optimizing the global pointer, emit the text section now
4141 and any small externs which did not have .comm, etc that are
4142 needed. Also, give a warning if the data area is more than 32K and
4143 -pic because 3 instructions are needed to reference the data
4144 pointers. */
4145
4146 void
4147 mips_asm_file_end (file)
4148 FILE *file;
4149 {
4150 char buffer[8192];
4151 tree name_tree;
4152 struct extern_list *p;
4153 int len;
4154
4155 if (HALF_PIC_P ())
4156 HALF_PIC_FINISH (file);
4157
4158 if (extern_head)
4159 {
4160 fputs ("\n", file);
4161
4162 for (p = extern_head; p != 0; p = p->next)
4163 {
4164 name_tree = get_identifier (p->name);
4165
4166 /* Positively ensure only one .extern for any given symbol. */
4167 if (! TREE_ASM_WRITTEN (name_tree))
4168 {
4169 TREE_ASM_WRITTEN (name_tree) = 1;
4170 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4171 if (p->size == -1)
4172 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
4173 else
4174 #endif
4175 {
4176 fputs ("\t.extern\t", file);
4177 assemble_name (file, p->name);
4178 fprintf (file, ", %d\n", p->size);
4179 }
4180 }
4181 }
4182 }
4183
4184 if (TARGET_GP_OPT)
4185 {
4186 fprintf (file, "\n\t.text\n");
4187 rewind (asm_out_text_file);
4188 if (ferror (asm_out_text_file))
4189 fatal_io_error (temp_filename);
4190
4191 while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
4192 if (fwrite (buffer, 1, len, file) != len)
4193 pfatal_with_name (asm_file_name);
4194
4195 if (len < 0)
4196 pfatal_with_name (temp_filename);
4197
4198 if (fclose (asm_out_text_file) != 0)
4199 pfatal_with_name (temp_filename);
4200
4201 #ifdef __MSDOS__
4202 unlink (temp_filename);
4203 #endif
4204 }
4205 }
4206
4207 \f
4208 /* Emit either a label, .comm, or .lcomm directive, and mark
4209 that the symbol is used, so that we don't emit an .extern
4210 for it in mips_asm_file_end. */
4211
4212 void
4213 mips_declare_object (stream, name, init_string, final_string, size)
4214 FILE *stream;
4215 char *name;
4216 char *init_string;
4217 char *final_string;
4218 int size;
4219 {
4220 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
4221 assemble_name (stream, name);
4222 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
4223
4224 if (TARGET_GP_OPT)
4225 {
4226 tree name_tree = get_identifier (name);
4227 TREE_ASM_WRITTEN (name_tree) = 1;
4228 }
4229 }
4230
4231 \f
4232 /* Output a double precision value to the assembler. If both the
4233 host and target are IEEE, emit the values in hex. */
4234
4235 void
4236 mips_output_double (stream, value)
4237 FILE *stream;
4238 REAL_VALUE_TYPE value;
4239 {
4240 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4241 long value_long[2];
4242 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
4243
4244 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4245 value_long[0], value, value_long[1]);
4246 #else
4247 fprintf (stream, "\t.double\t%.20g\n", value);
4248 #endif
4249 }
4250
4251
4252 /* Output a single precision value to the assembler. If both the
4253 host and target are IEEE, emit the values in hex. */
4254
4255 void
4256 mips_output_float (stream, value)
4257 FILE *stream;
4258 REAL_VALUE_TYPE value;
4259 {
4260 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4261 long value_long;
4262 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
4263
4264 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
4265 #else
4266 fprintf (stream, "\t.float\t%.12g\n", value);
4267 #endif
4268 }
4269
4270 \f
4271 /* Return TRUE if any register used in the epilogue is used. This to insure
4272 any insn put into the epilogue delay slots is safe. */
4273
4274 int
4275 epilogue_reg_mentioned_p (insn)
4276 rtx insn;
4277 {
4278 register char *fmt;
4279 register int i;
4280 register enum rtx_code code;
4281 register int regno;
4282
4283 if (insn == (rtx)0)
4284 return 0;
4285
4286 if (GET_CODE (insn) == LABEL_REF)
4287 return 0;
4288
4289 code = GET_CODE (insn);
4290 switch (code)
4291 {
4292 case REG:
4293 regno = REGNO (insn);
4294 if (regno == STACK_POINTER_REGNUM)
4295 return 1;
4296
4297 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
4298 return 1;
4299
4300 if (!call_used_regs[regno])
4301 return 1;
4302
4303 if (regno != MIPS_TEMP1_REGNUM && regno != MIPS_TEMP2_REGNUM)
4304 return 0;
4305
4306 if (!current_frame_info.initialized)
4307 compute_frame_size (get_frame_size ());
4308
4309 return (current_frame_info.total_size >= 32768);
4310
4311 case SCRATCH:
4312 case CC0:
4313 case PC:
4314 case CONST_INT:
4315 case CONST_DOUBLE:
4316 return 0;
4317 }
4318
4319 fmt = GET_RTX_FORMAT (code);
4320 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4321 {
4322 if (fmt[i] == 'E')
4323 {
4324 register int j;
4325 for (j = XVECLEN (insn, i) - 1; j >= 0; j--)
4326 if (epilogue_reg_mentioned_p (XVECEXP (insn, i, j)))
4327 return 1;
4328 }
4329 else if (fmt[i] == 'e' && epilogue_reg_mentioned_p (XEXP (insn, i)))
4330 return 1;
4331 }
4332
4333 return 0;
4334 }
4335
4336 \f
4337 /* When generating embedded PIC code we may need to get the address of
4338 the current function. We will need it if we take the address of
4339 any symbol in the .text section. */
4340
4341 void
4342 mips_finalize_pic ()
4343 {
4344 rtx seq;
4345
4346 if (! TARGET_EMBEDDED_PIC)
4347 return;
4348 if (embedded_pic_fnaddr_rtx == NULL)
4349 return;
4350
4351 start_sequence ();
4352
4353 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
4354 XEXP (DECL_RTL (current_function_decl), 0)));
4355
4356 seq = gen_sequence ();
4357 end_sequence ();
4358 emit_insn_after (seq, get_insns ());
4359
4360 embedded_pic_fnaddr_rtx = NULL;
4361 }
4362
4363 \f
4364 /* Return the bytes needed to compute the frame pointer from the current
4365 stack pointer.
4366
4367 Mips stack frames look like:
4368
4369 Before call After call
4370 +-----------------------+ +-----------------------+
4371 high | | | |
4372 mem. | | | |
4373 | caller's temps. | | caller's temps. |
4374 | | | |
4375 +-----------------------+ +-----------------------+
4376 | | | |
4377 | arguments on stack. | | arguments on stack. |
4378 | | | |
4379 +-----------------------+ +-----------------------+
4380 | 4 words to save | | 4 words to save |
4381 | arguments passed | | arguments passed |
4382 | in registers, even | | in registers, even |
4383 SP->| if not passed. | VFP->| if not passed. |
4384 +-----------------------+ +-----------------------+
4385 | |
4386 | fp register save |
4387 | |
4388 +-----------------------+
4389 | |
4390 | gp register save |
4391 | |
4392 +-----------------------+
4393 | |
4394 | local variables |
4395 | |
4396 +-----------------------+
4397 | |
4398 | alloca allocations |
4399 | |
4400 +-----------------------+
4401 | |
4402 | GP save for V.4 abi |
4403 | |
4404 +-----------------------+
4405 | |
4406 | arguments on stack |
4407 | |
4408 +-----------------------+
4409 | 4 words to save |
4410 | arguments passed |
4411 | in registers, even |
4412 low SP->| if not passed. |
4413 memory +-----------------------+
4414
4415 */
4416
4417 long
4418 compute_frame_size (size)
4419 int size; /* # of var. bytes allocated */
4420 {
4421 int regno;
4422 long total_size; /* # bytes that the entire frame takes up */
4423 long var_size; /* # bytes that variables take up */
4424 long args_size; /* # bytes that outgoing arguments take up */
4425 long extra_size; /* # extra bytes */
4426 long gp_reg_rounded; /* # bytes needed to store gp after rounding */
4427 long gp_reg_size; /* # bytes needed to store gp regs */
4428 long fp_reg_size; /* # bytes needed to store fp regs */
4429 long mask; /* mask of saved gp registers */
4430 long fmask; /* mask of saved fp registers */
4431 int fp_inc; /* 1 or 2 depending on the size of fp regs */
4432 long fp_bits; /* bitmask to use for each fp register */
4433
4434 gp_reg_size = 0;
4435 fp_reg_size = 0;
4436 mask = 0;
4437 fmask = 0;
4438 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
4439 var_size = MIPS_STACK_ALIGN (size);
4440 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
4441
4442 /* The MIPS 3.0 linker does not like functions that dynamically
4443 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4444 looks like we are trying to create a second frame pointer to the
4445 function, so allocate some stack space to make it happy. */
4446
4447 if (args_size == 0 && current_function_calls_alloca)
4448 args_size = 4*UNITS_PER_WORD;
4449
4450 total_size = var_size + args_size + extra_size;
4451
4452 /* Calculate space needed for gp registers. */
4453 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
4454 {
4455 if (MUST_SAVE_REGISTER (regno))
4456 {
4457 gp_reg_size += UNITS_PER_WORD;
4458 mask |= 1L << (regno - GP_REG_FIRST);
4459 }
4460 }
4461
4462 /* Calculate space needed for fp registers. */
4463 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
4464 {
4465 fp_inc = 1;
4466 fp_bits = 1;
4467 }
4468 else
4469 {
4470 fp_inc = 2;
4471 fp_bits = 3;
4472 }
4473
4474 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += fp_inc)
4475 {
4476 if (regs_ever_live[regno] && !call_used_regs[regno])
4477 {
4478 fp_reg_size += fp_inc * UNITS_PER_FPREG;
4479 fmask |= fp_bits << (regno - FP_REG_FIRST);
4480 }
4481 }
4482
4483 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
4484 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
4485
4486 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4487 for leaf routines (total_size == extra_size) to save the gp reg.
4488 The gp reg is callee saved in the 64 bit ABI, so all routines must
4489 save the gp reg. */
4490 if (total_size == extra_size && ! (ABI_64BIT && mips_isa >= 3))
4491 total_size = extra_size = 0;
4492 else if (TARGET_ABICALLS)
4493 {
4494 /* Add the context-pointer to the saved registers. */
4495 gp_reg_size += UNITS_PER_WORD;
4496 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
4497 total_size -= gp_reg_rounded;
4498 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
4499 total_size += gp_reg_rounded;
4500 }
4501
4502 /* Add in space reserved on the stack by the callee for storing arguments
4503 passed in registers. */
4504 if (ABI_64BIT && mips_isa >= 3)
4505 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
4506
4507 /* Save other computed information. */
4508 current_frame_info.total_size = total_size;
4509 current_frame_info.var_size = var_size;
4510 current_frame_info.args_size = args_size;
4511 current_frame_info.extra_size = extra_size;
4512 current_frame_info.gp_reg_size = gp_reg_size;
4513 current_frame_info.fp_reg_size = fp_reg_size;
4514 current_frame_info.mask = mask;
4515 current_frame_info.fmask = fmask;
4516 current_frame_info.initialized = reload_completed;
4517 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
4518 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
4519
4520 if (mask)
4521 {
4522 unsigned long offset = (args_size + extra_size + var_size
4523 + gp_reg_size - UNITS_PER_WORD);
4524 current_frame_info.gp_sp_offset = offset;
4525 current_frame_info.gp_save_offset = offset - total_size;
4526 }
4527 else
4528 {
4529 current_frame_info.gp_sp_offset = 0;
4530 current_frame_info.gp_save_offset = 0;
4531 }
4532
4533
4534 if (fmask)
4535 {
4536 unsigned long offset = (args_size + extra_size + var_size
4537 + gp_reg_rounded + fp_reg_size
4538 - fp_inc * UNITS_PER_FPREG);
4539 current_frame_info.fp_sp_offset = offset;
4540 current_frame_info.fp_save_offset = offset - total_size + UNITS_PER_WORD;
4541 }
4542 else
4543 {
4544 current_frame_info.fp_sp_offset = 0;
4545 current_frame_info.fp_save_offset = 0;
4546 }
4547
4548 /* Ok, we're done. */
4549 return total_size;
4550 }
4551
4552 \f
4553 /* Common code to emit the insns (or to write the instructions to a file)
4554 to save/restore registers.
4555
4556 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4557 is not modified within save_restore_insns. */
4558
4559 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4560
4561 static void
4562 save_restore_insns (store_p, large_reg, large_offset, file)
4563 int store_p; /* true if this is prologue */
4564 rtx large_reg; /* register holding large offset constant or NULL */
4565 long large_offset; /* large constant offset value */
4566 FILE *file; /* file to write instructions to instead of making RTL */
4567 {
4568 long mask = current_frame_info.mask;
4569 long fmask = current_frame_info.fmask;
4570 int regno;
4571 rtx base_reg_rtx;
4572 long base_offset;
4573 long gp_offset;
4574 long fp_offset;
4575 long end_offset;
4576
4577 if (frame_pointer_needed && !BITSET_P (mask, FRAME_POINTER_REGNUM - GP_REG_FIRST))
4578 abort ();
4579
4580 if (mask == 0 && fmask == 0)
4581 return;
4582
4583 /* Save registers starting from high to low. The debuggers prefer
4584 at least the return register be stored at func+4, and also it
4585 allows us not to need a nop in the epilog if at least one
4586 register is reloaded in addition to return address. */
4587
4588 /* Save GP registers if needed. */
4589 if (mask)
4590 {
4591 /* Pick which pointer to use as a base register. For small
4592 frames, just use the stack pointer. Otherwise, use a
4593 temporary register. Save 2 cycles if the save area is near
4594 the end of a large frame, by reusing the constant created in
4595 the prologue/epilogue to adjust the stack frame. */
4596
4597 gp_offset = current_frame_info.gp_sp_offset;
4598 end_offset = gp_offset - (current_frame_info.gp_reg_size - UNITS_PER_WORD);
4599
4600 if (gp_offset < 0 || end_offset < 0)
4601 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
4602 gp_offset, end_offset);
4603
4604 else if (gp_offset < 32768)
4605 {
4606 base_reg_rtx = stack_pointer_rtx;
4607 base_offset = 0;
4608 }
4609
4610 else if (large_reg != (rtx)0
4611 && (((unsigned long)(large_offset - gp_offset)) < 32768)
4612 && (((unsigned long)(large_offset - end_offset)) < 32768))
4613 {
4614 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
4615 base_offset = large_offset;
4616 if (file == (FILE *)0)
4617 {
4618 if (TARGET_LONG64)
4619 emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
4620 else
4621 emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
4622 }
4623 else
4624 fprintf (file, "\t%s\t%s,%s,%s\n",
4625 TARGET_LONG64 ? "daddu" : "addu",
4626 reg_names[MIPS_TEMP2_REGNUM],
4627 reg_names[REGNO (large_reg)],
4628 reg_names[STACK_POINTER_REGNUM]);
4629 }
4630
4631 else
4632 {
4633 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
4634 base_offset = gp_offset;
4635 if (file == (FILE *)0)
4636 {
4637 emit_move_insn (base_reg_rtx, GEN_INT (gp_offset));
4638 if (TARGET_LONG64)
4639 emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
4640 else
4641 emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
4642 }
4643 else
4644 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
4645 reg_names[MIPS_TEMP2_REGNUM],
4646 (long)base_offset,
4647 (long)base_offset,
4648 TARGET_LONG64 ? "daddu" : "addu",
4649 reg_names[MIPS_TEMP2_REGNUM],
4650 reg_names[MIPS_TEMP2_REGNUM],
4651 reg_names[STACK_POINTER_REGNUM]);
4652 }
4653
4654 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
4655 {
4656 if (BITSET_P (mask, regno - GP_REG_FIRST))
4657 {
4658 if (file == (FILE *)0)
4659 {
4660 rtx reg_rtx = gen_rtx (REG, word_mode, regno);
4661 rtx mem_rtx = gen_rtx (MEM, word_mode,
4662 gen_rtx (PLUS, Pmode, base_reg_rtx,
4663 GEN_INT (gp_offset - base_offset)));
4664
4665 if (store_p)
4666 emit_move_insn (mem_rtx, reg_rtx);
4667 else if (!TARGET_ABICALLS || (ABI_64BIT && mips_isa >= 3)
4668 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
4669 emit_move_insn (reg_rtx, mem_rtx);
4670 }
4671 else
4672 {
4673 if (store_p || !TARGET_ABICALLS || (ABI_64BIT && mips_isa >= 3)
4674 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
4675 fprintf (file, "\t%s\t%s,%ld(%s)\n",
4676 (TARGET_64BIT
4677 ? (store_p) ? "sd" : "ld"
4678 : (store_p) ? "sw" : "lw"),
4679 reg_names[regno],
4680 gp_offset - base_offset,
4681 reg_names[REGNO(base_reg_rtx)]);
4682
4683 }
4684 gp_offset -= UNITS_PER_WORD;
4685 }
4686 }
4687 }
4688 else
4689 {
4690 base_reg_rtx = (rtx)0; /* Make sure these are initialzed */
4691 base_offset = 0;
4692 }
4693
4694 /* Save floating point registers if needed. */
4695 if (fmask)
4696 {
4697 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
4698 int fp_size = fp_inc * UNITS_PER_FPREG;
4699
4700 /* Pick which pointer to use as a base register. */
4701 fp_offset = current_frame_info.fp_sp_offset;
4702 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
4703
4704 if (fp_offset < 0 || end_offset < 0)
4705 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
4706 fp_offset, end_offset);
4707
4708 else if (fp_offset < 32768)
4709 {
4710 base_reg_rtx = stack_pointer_rtx;
4711 base_offset = 0;
4712 }
4713
4714 else if (base_reg_rtx != (rtx)0
4715 && (((unsigned long)(base_offset - fp_offset)) < 32768)
4716 && (((unsigned long)(base_offset - end_offset)) < 32768))
4717 {
4718 ; /* already set up for gp registers above */
4719 }
4720
4721 else if (large_reg != (rtx)0
4722 && (((unsigned long)(large_offset - fp_offset)) < 32768)
4723 && (((unsigned long)(large_offset - end_offset)) < 32768))
4724 {
4725 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
4726 base_offset = large_offset;
4727 if (file == (FILE *)0)
4728 {
4729 if (TARGET_LONG64)
4730 emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
4731 else
4732 emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
4733 }
4734 else
4735 fprintf (file, "\t%s\t%s,%s,%s\n",
4736 TARGET_LONG64 ? "daddu" : "addu",
4737 reg_names[MIPS_TEMP2_REGNUM],
4738 reg_names[REGNO (large_reg)],
4739 reg_names[STACK_POINTER_REGNUM]);
4740 }
4741
4742 else
4743 {
4744 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
4745 base_offset = fp_offset;
4746 if (file == (FILE *)0)
4747 {
4748 emit_move_insn (base_reg_rtx, GEN_INT (fp_offset));
4749 if (TARGET_LONG64)
4750 emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
4751 else
4752 emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
4753 }
4754 else
4755 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
4756 reg_names[MIPS_TEMP2_REGNUM],
4757 (long)base_offset,
4758 (long)base_offset,
4759 TARGET_LONG64 ? "daddu" : "addu",
4760 reg_names[MIPS_TEMP2_REGNUM],
4761 reg_names[MIPS_TEMP2_REGNUM],
4762 reg_names[STACK_POINTER_REGNUM]);
4763 }
4764
4765 for (regno = FP_REG_LAST-1; regno >= FP_REG_FIRST; regno -= fp_inc)
4766 {
4767 if (BITSET_P (fmask, regno - FP_REG_FIRST))
4768 {
4769 if (file == (FILE *)0)
4770 {
4771 enum machine_mode sz =
4772 TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4773 rtx reg_rtx = gen_rtx (REG, sz, regno);
4774 rtx mem_rtx = gen_rtx (MEM, sz,
4775 gen_rtx (PLUS, Pmode, base_reg_rtx,
4776 GEN_INT (fp_offset - base_offset)));
4777
4778 if (store_p)
4779 emit_move_insn (mem_rtx, reg_rtx);
4780 else
4781 emit_move_insn (reg_rtx, mem_rtx);
4782 }
4783 else
4784 fprintf (file, "\t%s\t%s,%ld(%s)\n",
4785 (TARGET_SINGLE_FLOAT
4786 ? ((store_p) ? "s.s" : "l.s")
4787 : ((store_p) ? "s.d" : "l.d")),
4788 reg_names[regno],
4789 fp_offset - base_offset,
4790 reg_names[REGNO(base_reg_rtx)]);
4791
4792
4793 fp_offset -= fp_size;
4794 }
4795 }
4796 }
4797 }
4798
4799 \f
4800 /* Set up the stack and frame (if desired) for the function. */
4801
4802 void
4803 function_prologue (file, size)
4804 FILE *file;
4805 int size;
4806 {
4807 long tsize = current_frame_info.total_size;
4808
4809 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
4810
4811 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
4812 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
4813
4814 inside_function = 1;
4815 fputs ("\t.ent\t", file);
4816 assemble_name (file, current_function_name);
4817 fputs ("\n", file);
4818
4819 assemble_name (file, current_function_name);
4820 fputs (":\n", file);
4821
4822 fprintf (file, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
4823 reg_names[ (frame_pointer_needed) ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ],
4824 tsize,
4825 reg_names[31 + GP_REG_FIRST],
4826 current_frame_info.var_size,
4827 current_frame_info.num_gp,
4828 current_frame_info.num_fp,
4829 current_function_outgoing_args_size,
4830 current_frame_info.extra_size);
4831
4832 fprintf (file, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
4833 current_frame_info.mask,
4834 current_frame_info.gp_save_offset,
4835 current_frame_info.fmask,
4836 current_frame_info.fp_save_offset);
4837
4838 if (TARGET_ABICALLS && ! (ABI_64BIT && mips_isa >= 3))
4839 {
4840 char *sp_str = reg_names[STACK_POINTER_REGNUM];
4841
4842 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
4843 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
4844 if (tsize > 0)
4845 {
4846 fprintf (file, "\t%s\t%s,%s,%d\n",
4847 (TARGET_LONG64 ? "dsubu" : "subu"),
4848 sp_str, sp_str, tsize);
4849 fprintf (file, "\t.cprestore %d\n", current_frame_info.args_size);
4850 }
4851 }
4852 }
4853
4854 \f
4855 /* Expand the prologue into a bunch of separate insns. */
4856
4857 void
4858 mips_expand_prologue ()
4859 {
4860 int regno;
4861 long tsize;
4862 rtx tmp_rtx = (rtx)0;
4863 char *arg_name = (char *)0;
4864 tree fndecl = current_function_decl;
4865 tree fntype = TREE_TYPE (fndecl);
4866 tree fnargs = (TREE_CODE (fntype) != METHOD_TYPE)
4867 ? DECL_ARGUMENTS (fndecl)
4868 : 0;
4869 rtx next_arg_reg;
4870 int i;
4871 tree next_arg;
4872 tree cur_arg;
4873 CUMULATIVE_ARGS args_so_far;
4874
4875 /* If struct value address is treated as the first argument, make it so. */
4876 if (aggregate_value_p (DECL_RESULT (fndecl))
4877 && ! current_function_returns_pcc_struct
4878 && struct_value_incoming_rtx == 0)
4879 {
4880 tree type = build_pointer_type (fntype);
4881 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
4882 DECL_ARG_TYPE (function_result_decl) = type;
4883 TREE_CHAIN (function_result_decl) = fnargs;
4884 fnargs = function_result_decl;
4885 }
4886
4887 /* Determine the last argument, and get its name. */
4888
4889 INIT_CUMULATIVE_ARGS (args_so_far, fntype, (rtx)0);
4890 regno = GP_ARG_FIRST;
4891
4892 for (cur_arg = fnargs; cur_arg != (tree)0; cur_arg = next_arg)
4893 {
4894 tree passed_type = DECL_ARG_TYPE (cur_arg);
4895 enum machine_mode passed_mode = TYPE_MODE (passed_type);
4896 rtx entry_parm;
4897
4898 if (TYPE_NEEDS_CONSTRUCTING (passed_type))
4899 {
4900 passed_type = build_pointer_type (passed_type);
4901 passed_mode = Pmode;
4902 }
4903
4904 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
4905
4906 if (entry_parm)
4907 {
4908 int words;
4909
4910 /* passed in a register, so will get homed automatically */
4911 if (GET_MODE (entry_parm) == BLKmode)
4912 words = (int_size_in_bytes (passed_type) + 3) / 4;
4913 else
4914 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
4915
4916 regno = REGNO (entry_parm) + words - 1;
4917 }
4918 else
4919 {
4920 regno = GP_ARG_LAST+1;
4921 break;
4922 }
4923
4924 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
4925
4926 next_arg = TREE_CHAIN (cur_arg);
4927 if (next_arg == (tree)0)
4928 {
4929 if (DECL_NAME (cur_arg))
4930 arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg));
4931
4932 break;
4933 }
4934 }
4935
4936 /* In order to pass small structures by value in registers
4937 compatibly with the MIPS compiler, we need to shift the value
4938 into the high part of the register. Function_arg has encoded a
4939 PARALLEL rtx, holding a vector of adjustments to be made as the
4940 next_arg_reg variable, so we split up the insns, and emit them
4941 separately. */
4942
4943 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
4944 if (next_arg_reg != (rtx)0 && GET_CODE (next_arg_reg) == PARALLEL)
4945 {
4946 rtvec adjust = XVEC (next_arg_reg, 0);
4947 int num = GET_NUM_ELEM (adjust);
4948
4949 for (i = 0; i < num; i++)
4950 {
4951 rtx pattern = RTVEC_ELT (adjust, i);
4952 if (GET_CODE (pattern) != SET
4953 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
4954 abort_with_insn (pattern, "Insn is not a shift");
4955
4956 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
4957 emit_insn (pattern);
4958 }
4959 }
4960
4961 tsize = compute_frame_size (get_frame_size ());
4962
4963 /* If this function is a varargs function, store any registers that
4964 would normally hold arguments ($4 - $7) on the stack. */
4965 if ((! ABI_64BIT || mips_isa < 3)
4966 && ((TYPE_ARG_TYPES (fntype) != 0
4967 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
4968 || (arg_name != (char *)0
4969 && ((arg_name[0] == '_' && strcmp (arg_name, "__builtin_va_alist") == 0)
4970 || (arg_name[0] == 'v' && strcmp (arg_name, "va_alist") == 0)))))
4971 {
4972 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
4973 rtx ptr = stack_pointer_rtx;
4974
4975 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
4976 if (TARGET_ABICALLS && ! (ABI_64BIT && mips_isa >= 3))
4977 offset += tsize;
4978
4979 for (; regno <= GP_ARG_LAST; regno++)
4980 {
4981 if (offset != 0)
4982 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
4983 emit_move_insn (gen_rtx (MEM, word_mode, ptr),
4984 gen_rtx (REG, word_mode, regno));
4985 offset += UNITS_PER_WORD;
4986 }
4987 }
4988
4989 if (tsize > 0)
4990 {
4991 rtx tsize_rtx = GEN_INT (tsize);
4992
4993 /* If we are doing svr4-abi, sp move is done by function_prologue. */
4994 if (!TARGET_ABICALLS || (ABI_64BIT && mips_isa >= 3))
4995 {
4996 if (tsize > 32767)
4997 {
4998 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
4999 emit_move_insn (tmp_rtx, tsize_rtx);
5000 tsize_rtx = tmp_rtx;
5001 }
5002
5003 if (TARGET_LONG64)
5004 emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
5005 tsize_rtx));
5006 else
5007 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
5008 tsize_rtx));
5009 }
5010
5011 save_restore_insns (TRUE, tmp_rtx, tsize, (FILE *)0);
5012
5013 if (frame_pointer_needed)
5014 {
5015 if (TARGET_64BIT)
5016 emit_insn (gen_movdi (frame_pointer_rtx, stack_pointer_rtx));
5017 else
5018 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
5019 }
5020
5021 if (TARGET_ABICALLS && (ABI_64BIT && mips_isa >= 3))
5022 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0)));
5023 }
5024
5025 /* If we are profiling, make sure no instructions are scheduled before
5026 the call to mcount. */
5027
5028 if (profile_flag || profile_block_flag)
5029 emit_insn (gen_blockage ());
5030 }
5031
5032 \f
5033 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
5034
5035 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5036 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5037
5038 void
5039 function_epilogue (file, size)
5040 FILE *file;
5041 int size;
5042 {
5043 long tsize;
5044 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5045 char *t1_str = reg_names[MIPS_TEMP1_REGNUM];
5046 rtx epilogue_delay = current_function_epilogue_delay_list;
5047 int noreorder = (epilogue_delay != 0);
5048 int noepilogue = FALSE;
5049 int load_nop = FALSE;
5050 int load_only_r31;
5051 rtx tmp_rtx = (rtx)0;
5052 rtx restore_rtx;
5053 int i;
5054
5055 /* The epilogue does not depend on any registers, but the stack
5056 registers, so we assume that if we have 1 pending nop, it can be
5057 ignored, and 2 it must be filled (2 nops occur for integer
5058 multiply and divide). */
5059
5060 if (dslots_number_nops > 0)
5061 {
5062 if (dslots_number_nops == 1)
5063 {
5064 dslots_number_nops = 0;
5065 dslots_load_filled++;
5066 }
5067 else
5068 {
5069 while (--dslots_number_nops > 0)
5070 fputs ("\t#nop\n", asm_out_file);
5071 }
5072 }
5073
5074 if (set_noat != 0)
5075 {
5076 set_noat = 0;
5077 fputs ("\t.set\tat\n", file);
5078 error ("internal gcc error: .set noat left on in epilogue");
5079 }
5080
5081 if (set_nomacro != 0)
5082 {
5083 set_nomacro = 0;
5084 fputs ("\t.set\tmacro\n", file);
5085 error ("internal gcc error: .set nomacro left on in epilogue");
5086 }
5087
5088 if (set_noreorder != 0)
5089 {
5090 set_noreorder = 0;
5091 fputs ("\t.set\treorder\n", file);
5092 error ("internal gcc error: .set noreorder left on in epilogue");
5093 }
5094
5095 if (set_volatile != 0)
5096 {
5097 set_volatile = 0;
5098 fprintf (file, "\t%s.set\tnovolatile\n", (TARGET_MIPS_AS) ? "" : "#");
5099 error ("internal gcc error: .set volatile left on in epilogue");
5100 }
5101
5102 size = MIPS_STACK_ALIGN (size);
5103 tsize = (!current_frame_info.initialized)
5104 ? compute_frame_size (size)
5105 : current_frame_info.total_size;
5106
5107 if (tsize == 0 && epilogue_delay == 0)
5108 {
5109 rtx insn = get_last_insn ();
5110
5111 /* If the last insn was a BARRIER, we don't have to write any code
5112 because a jump (aka return) was put there. */
5113 if (GET_CODE (insn) == NOTE)
5114 insn = prev_nonnote_insn (insn);
5115 if (insn && GET_CODE (insn) == BARRIER)
5116 noepilogue = TRUE;
5117
5118 noreorder = FALSE;
5119 }
5120
5121 if (!noepilogue)
5122 {
5123 /* In the reload sequence, we don't need to fill the load delay
5124 slots for most of the loads, also see if we can fill the final
5125 delay slot if not otherwise filled by the reload sequence. */
5126
5127 if (noreorder)
5128 fprintf (file, "\t.set\tnoreorder\n");
5129
5130 if (tsize > 32767)
5131 {
5132 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n", t1_str, (long)tsize, (long)tsize);
5133 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
5134 }
5135
5136 if (frame_pointer_needed)
5137 fprintf (file, "\tmove\t%s,%s\t\t\t# sp not trusted here\n",
5138 sp_str, reg_names[FRAME_POINTER_REGNUM]);
5139
5140 save_restore_insns (FALSE, tmp_rtx, tsize, file);
5141
5142 load_only_r31 = (((current_frame_info.mask
5143 & ~ (TARGET_ABICALLS && ! (ABI_64BIT && mips_isa >= 3)
5144 ? PIC_OFFSET_TABLE_MASK : 0))
5145 == RA_MASK)
5146 && current_frame_info.fmask == 0);
5147
5148 if (noreorder)
5149 {
5150 /* If the only register saved is the return address, we need a
5151 nop, unless we have an instruction to put into it. Otherwise
5152 we don't since reloading multiple registers doesn't reference
5153 the register being loaded. */
5154
5155 if (load_only_r31)
5156 {
5157 if (epilogue_delay)
5158 final_scan_insn (XEXP (epilogue_delay, 0),
5159 file,
5160 1, /* optimize */
5161 -2, /* prescan */
5162 1); /* nopeepholes */
5163 else
5164 {
5165 fprintf (file, "\tnop\n");
5166 load_nop = TRUE;
5167 }
5168 }
5169
5170 fprintf (file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 31]);
5171
5172 if (tsize > 32767)
5173 fprintf (file, "\t%s\t%s,%s,%s\n",
5174 TARGET_LONG64 ? "daddu" : "addu",
5175 sp_str, sp_str, t1_str);
5176
5177 else if (tsize > 0)
5178 fprintf (file, "\t%s\t%s,%s,%d\n",
5179 TARGET_LONG64 ? "daddu" : "addu",
5180 sp_str, sp_str, tsize);
5181
5182 else if (!load_only_r31 && epilogue_delay != 0)
5183 final_scan_insn (XEXP (epilogue_delay, 0),
5184 file,
5185 1, /* optimize */
5186 -2, /* prescan */
5187 1); /* nopeepholes */
5188
5189 fprintf (file, "\t.set\treorder\n");
5190 }
5191
5192 else
5193 {
5194 if (tsize > 32767)
5195 fprintf (file, "\t%s\t%s,%s,%s\n",
5196 TARGET_LONG64 ? "daddu" : "addu",
5197 sp_str, sp_str, t1_str);
5198
5199 else if (tsize > 0)
5200 fprintf (file, "\t%s\t%s,%s,%d\n",
5201 TARGET_LONG64 ? "daddu" : "addu",
5202 sp_str, sp_str, tsize);
5203
5204 fprintf (file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 31]);
5205 }
5206 }
5207
5208 fputs ("\t.end\t", file);
5209 assemble_name (file, current_function_name);
5210 fputs ("\n", file);
5211
5212 if (TARGET_STATS)
5213 {
5214 int num_gp_regs = current_frame_info.gp_reg_size / 4;
5215 int num_fp_regs = current_frame_info.fp_reg_size / 8;
5216 int num_regs = num_gp_regs + num_fp_regs;
5217 char *name = current_function_name;
5218
5219 if (name[0] == '*')
5220 name++;
5221
5222 dslots_load_total += num_regs;
5223
5224 if (!noepilogue)
5225 dslots_jump_total++;
5226
5227 if (noreorder)
5228 {
5229 dslots_load_filled += num_regs;
5230
5231 /* If the only register saved is the return register, we
5232 can't fill this register's delay slot. */
5233
5234 if (load_only_r31 && epilogue_delay == 0)
5235 dslots_load_filled--;
5236
5237 if (tsize > 0 || (!load_only_r31 && epilogue_delay != 0))
5238 dslots_jump_filled++;
5239 }
5240
5241 fprintf (stderr,
5242 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5243 name,
5244 (frame_pointer_needed) ? 'y' : 'n',
5245 ((current_frame_info.mask & RA_MASK) != 0) ? 'n' : 'y',
5246 (current_function_calls_alloca) ? 'y' : 'n',
5247 (current_function_calls_setjmp) ? 'y' : 'n',
5248 (long)current_frame_info.total_size,
5249 (long)current_function_outgoing_args_size,
5250 num_gp_regs, num_fp_regs,
5251 dslots_load_total, dslots_load_filled,
5252 dslots_jump_total, dslots_jump_filled,
5253 num_refs[0], num_refs[1], num_refs[2]);
5254
5255 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
5256 {
5257 fprintf (stderr, " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
5258 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
5259 }
5260
5261 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
5262 {
5263 fprintf (stderr, " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
5264 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
5265 }
5266
5267 fputc ('\n', stderr);
5268 }
5269
5270 /* Reset state info for each function. */
5271 inside_function = FALSE;
5272 ignore_line_number = FALSE;
5273 dslots_load_total = 0;
5274 dslots_jump_total = 0;
5275 dslots_load_filled = 0;
5276 dslots_jump_filled = 0;
5277 num_refs[0] = 0;
5278 num_refs[1] = 0;
5279 num_refs[2] = 0;
5280 mips_load_reg = (rtx)0;
5281 mips_load_reg2 = (rtx)0;
5282 current_frame_info = zero_frame_info;
5283
5284 /* Restore the output file if optimizing the GP (optimizing the GP causes
5285 the text to be diverted to a tempfile, so that data decls come before
5286 references to the data). */
5287
5288 if (TARGET_GP_OPT)
5289 asm_out_file = asm_out_data_file;
5290 }
5291
5292 \f
5293 /* Expand the epilogue into a bunch of separate insns. */
5294
5295 void
5296 mips_expand_epilogue ()
5297 {
5298 long tsize = current_frame_info.total_size;
5299 rtx tsize_rtx = GEN_INT (tsize);
5300 rtx tmp_rtx = (rtx)0;
5301
5302 if (tsize > 32767)
5303 {
5304 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
5305 emit_move_insn (tmp_rtx, tsize_rtx);
5306 tsize_rtx = tmp_rtx;
5307 }
5308
5309 if (tsize > 0)
5310 {
5311 if (frame_pointer_needed)
5312 {
5313 if (TARGET_LONG64)
5314 emit_insn (gen_movdi (stack_pointer_rtx, frame_pointer_rtx));
5315 else
5316 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
5317 }
5318
5319 save_restore_insns (FALSE, tmp_rtx, tsize, (FILE *)0);
5320
5321 if (TARGET_LONG64)
5322 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
5323 tsize_rtx));
5324 else
5325 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
5326 tsize_rtx));
5327 }
5328
5329 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode, GP_REG_FIRST+31)));
5330 }
5331
5332 \f
5333 /* Define the number of delay slots needed for the function epilogue.
5334
5335 On the mips, we need a slot if either no stack has been allocated,
5336 or the only register saved is the return register. */
5337
5338 int
5339 mips_epilogue_delay_slots ()
5340 {
5341 if (!current_frame_info.initialized)
5342 (void) compute_frame_size (get_frame_size ());
5343
5344 if (current_frame_info.total_size == 0)
5345 return 1;
5346
5347 if (current_frame_info.mask == RA_MASK && current_frame_info.fmask == 0)
5348 return 1;
5349
5350 return 0;
5351 }
5352
5353 \f
5354 /* Return true if this function is known to have a null epilogue.
5355 This allows the optimizer to omit jumps to jumps if no stack
5356 was created. */
5357
5358 int
5359 simple_epilogue_p ()
5360 {
5361 if (!reload_completed)
5362 return 0;
5363
5364 if (current_frame_info.initialized)
5365 return current_frame_info.total_size == 0;
5366
5367 return (compute_frame_size (get_frame_size ())) == 0;
5368 }
5369 \f
5370 /* Choose the section to use for the constant rtx expression X that has
5371 mode MODE. */
5372
5373 mips_select_rtx_section (mode, x)
5374 enum machine_mode mode;
5375 rtx x;
5376 {
5377 if (TARGET_EMBEDDED_DATA)
5378 {
5379 /* For embedded applications, always put constants in read-only data,
5380 in order to reduce RAM usage. */
5381 rdata_section ();
5382 }
5383 else
5384 {
5385 /* For hosted applications, always put constants in small data if
5386 possible, as this gives the best performance. */
5387
5388 if (GET_MODE_SIZE (mode) <= mips_section_threshold
5389 && mips_section_threshold > 0)
5390 sdata_section ();
5391 else
5392 rdata_section ();
5393 }
5394 }
5395
5396 /* Choose the section to use for DECL. RELOC is true if its value contains
5397 any relocatable expression. */
5398
5399 mips_select_section (decl, reloc)
5400 tree decl;
5401 int reloc;
5402 {
5403 int size = int_size_in_bytes (TREE_TYPE (decl));
5404
5405 if (TARGET_EMBEDDED_PIC
5406 && TREE_CODE (decl) == STRING_CST
5407 && !flag_writable_strings)
5408 {
5409 /* For embedded position independent code, put constant strings
5410 in the text section, because the data section is limited to
5411 64K in size. */
5412
5413 text_section ();
5414 }
5415 else if (TARGET_EMBEDDED_DATA)
5416 {
5417 /* For embedded applications, always put an object in read-only data
5418 if possible, in order to reduce RAM usage. */
5419
5420 if (((TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
5421 && DECL_INITIAL (decl)
5422 && (DECL_INITIAL (decl) == error_mark_node
5423 || TREE_CONSTANT (DECL_INITIAL (decl))))
5424 /* Deal with calls from output_constant_def_contents. */
5425 || (TREE_CODE (decl) != VAR_DECL
5426 && (TREE_CODE (decl) != STRING_CST
5427 || !flag_writable_strings)))
5428 && ! (flag_pic && reloc))
5429 rdata_section ();
5430 else if (size > 0 && size <= mips_section_threshold)
5431 sdata_section ();
5432 else
5433 data_section ();
5434 }
5435 else
5436 {
5437 /* For hosted applications, always put an object in small data if
5438 possible, as this gives the best performance. */
5439
5440 if (size > 0 && size <= mips_section_threshold)
5441 sdata_section ();
5442 else if (((TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
5443 && DECL_INITIAL (decl)
5444 && (DECL_INITIAL (decl) == error_mark_node
5445 || TREE_CONSTANT (DECL_INITIAL (decl))))
5446 /* Deal with calls from output_constant_def_contents. */
5447 || (TREE_CODE (decl) != VAR_DECL
5448 && (TREE_CODE (decl) != STRING_CST
5449 || !flag_writable_strings)))
5450 && ! (flag_pic && reloc))
5451 rdata_section ();
5452 else
5453 data_section ();
5454 }
5455 }
5456 \f
5457 #if ABI_64BIT
5458 /* Support functions for the 64 bit ABI. */
5459
5460 /* Return the register to be used for word INDEX of a variable with type TYPE
5461 being passed starting at general purpose reg REGNO.
5462
5463 If the word being passed is a single field of a structure which has type
5464 double, then pass it in a floating point reg instead of a general purpose
5465 reg. Otherwise, we return the default value REGNO + INDEX. */
5466
5467 rtx
5468 type_dependent_reg (regno, index, type)
5469 int regno;
5470 int index;
5471 tree type;
5472 {
5473 tree field;
5474 tree offset;
5475
5476 /* If type isn't a structure type, return the default value now. */
5477 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_isa < 3)
5478 return gen_rtx (REG, word_mode, regno + index);
5479
5480 /* Iterate through the structure fields to find which one corresponds to
5481 this index. */
5482 offset = size_int (index * BITS_PER_WORD);
5483 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5484 {
5485 if (! tree_int_cst_lt (DECL_FIELD_BITPOS (field), offset))
5486 break;
5487 }
5488
5489 if (field && tree_int_cst_equal (DECL_FIELD_BITPOS (field), offset)
5490 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
5491 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5492 return gen_rtx (REG, DFmode,
5493 regno + index + FP_ARG_FIRST - GP_ARG_FIRST);
5494 else
5495 return gen_rtx (REG, word_mode, regno + index);
5496 }
5497
5498 /* Return register to use for a function return value with VALTYPE for function
5499 FUNC. */
5500
5501 rtx
5502 mips_function_value (valtype, func)
5503 tree valtype;
5504 tree func;
5505 {
5506 int reg = GP_RETURN;
5507 enum machine_mode mode = TYPE_MODE (valtype);
5508 enum mode_class mclass = GET_MODE_CLASS (mode);
5509
5510 if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
5511 reg = FP_RETURN;
5512 else if (TREE_CODE (valtype) == RECORD_TYPE && mips_isa >= 3)
5513 {
5514 /* A struct with only one or two floating point fields is returned in
5515 the floating point registers. */
5516 tree field;
5517 int i;
5518
5519 for (i = 0, field = TYPE_FIELDS (valtype); field;
5520 field = TREE_CHAIN (field), i++)
5521 {
5522 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
5523 break;
5524 }
5525
5526 if (! field)
5527 reg = FP_RETURN;
5528 }
5529
5530 return gen_rtx (REG, mode, reg);
5531 }
5532 #endif
5533
5534 /* Moving the HI or LO register somewhere requires a general register. */
5535
5536 enum reg_class
5537 mips_secondary_reload_class (class, mode, x)
5538 enum reg_class class;
5539 enum machine_mode mode;
5540 rtx x;
5541 {
5542 if (class != HI_REG && class != LO_REG && class != MD_REGS)
5543 return NO_REGS;
5544
5545 if (GET_CODE (x) == REG)
5546 {
5547 int regno = true_regnum (x);
5548
5549 if (regno >= GP_REG_FIRST && regno <= GP_REG_LAST)
5550 return NO_REGS;
5551 }
5552
5553 return GR_REGS;
5554 }