1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
46 #include "hash-table.h"
49 #include "target-def.h"
50 #include "common/common-target.h"
51 #include "langhooks.h"
52 #include "sched-int.h"
55 #include "diagnostic.h"
56 #include "target-globals.h"
58 #include "tree-pass.h"
60 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
61 #define UNSPEC_ADDRESS_P(X) \
62 (GET_CODE (X) == UNSPEC \
63 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
64 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
66 /* Extract the symbol or label from UNSPEC wrapper X. */
67 #define UNSPEC_ADDRESS(X) \
70 /* Extract the symbol type from UNSPEC wrapper X. */
71 #define UNSPEC_ADDRESS_TYPE(X) \
72 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
74 /* The maximum distance between the top of the stack frame and the
75 value $sp has when we save and restore registers.
77 The value for normal-mode code must be a SMALL_OPERAND and must
78 preserve the maximum stack alignment. We therefore use a value
79 of 0x7ff0 in this case.
81 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
82 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_COMPRESSION ? 0x7ff0 \
95 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 /* ??? This test exists through the compiler, perhaps it should be
101 #define USEFUL_INSN_P(INSN) \
102 (NONDEBUG_INSN_P (INSN) \
103 && GET_CODE (PATTERN (INSN)) != USE \
104 && GET_CODE (PATTERN (INSN)) != CLOBBER)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Return the opcode for a ptr_mode load of the form:
131 l[wd] DEST, OFFSET(BASE). */
132 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
133 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
138 /* Return the opcode to move register SRC into register DEST. */
139 #define MIPS_MOVE(DEST, SRC) \
140 ((TARGET_64BIT ? 0x2d : 0x21) \
144 /* Return the opcode for:
147 #define MIPS_LUI(DEST, VALUE) \
148 ((0xf << 26) | ((DEST) << 16) | (VALUE))
150 /* Return the opcode to jump to register DEST. */
151 #define MIPS_JR(DEST) \
152 (((DEST) << 21) | 0x8)
154 /* Return the opcode for:
156 bal . + (1 + OFFSET) * 4. */
157 #define MIPS_BAL(OFFSET) \
158 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
160 /* Return the usual opcode for a nop. */
163 /* Classifies an address.
166 A natural register + offset address. The register satisfies
167 mips_valid_base_register_p and the offset is a const_arith_operand.
170 A LO_SUM rtx. The first operand is a valid base register and
171 the second operand is a symbolic address.
174 A signed 16-bit constant address.
177 A constant symbolic address. */
178 enum mips_address_type
{
185 /* Macros to create an enumeration identifier for a function prototype. */
186 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
187 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
188 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
189 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
191 /* Classifies the prototype of a built-in function. */
192 enum mips_function_type
{
193 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
194 #include "config/mips/mips-ftypes.def"
195 #undef DEF_MIPS_FTYPE
199 /* Specifies how a built-in function should be converted into rtl. */
200 enum mips_builtin_type
{
201 /* The function corresponds directly to an .md pattern. The return
202 value is mapped to operand 0 and the arguments are mapped to
203 operands 1 and above. */
206 /* The function corresponds directly to an .md pattern. There is no return
207 value and the arguments are mapped to operands 0 and above. */
208 MIPS_BUILTIN_DIRECT_NO_TARGET
,
210 /* The function corresponds to a comparison instruction followed by
211 a mips_cond_move_tf_ps pattern. The first two arguments are the
212 values to compare and the second two arguments are the vector
213 operands for the movt.ps or movf.ps instruction (in assembly order). */
217 /* The function corresponds to a V2SF comparison instruction. Operand 0
218 of this instruction is the result of the comparison, which has mode
219 CCV2 or CCV4. The function arguments are mapped to operands 1 and
220 above. The function's return value is an SImode boolean that is
221 true under the following conditions:
223 MIPS_BUILTIN_CMP_ANY: one of the registers is true
224 MIPS_BUILTIN_CMP_ALL: all of the registers are true
225 MIPS_BUILTIN_CMP_LOWER: the first register is true
226 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
227 MIPS_BUILTIN_CMP_ANY
,
228 MIPS_BUILTIN_CMP_ALL
,
229 MIPS_BUILTIN_CMP_UPPER
,
230 MIPS_BUILTIN_CMP_LOWER
,
232 /* As above, but the instruction only sets a single $fcc register. */
233 MIPS_BUILTIN_CMP_SINGLE
,
235 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
236 MIPS_BUILTIN_BPOSGE32
239 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
240 #define MIPS_FP_CONDITIONS(MACRO) \
258 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
259 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
260 enum mips_fp_condition
{
261 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
264 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
265 #define STRINGIFY(X) #X
266 static const char *const mips_fp_conditions
[] = {
267 MIPS_FP_CONDITIONS (STRINGIFY
)
270 /* Tuning information that is automatically derived from other sources
271 (such as the scheduler). */
273 /* The architecture and tuning settings that this structure describes. */
277 /* True if this structure describes MIPS16 settings. */
280 /* True if the structure has been initialized. */
283 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
284 when optimizing for speed. */
285 bool fast_mult_zero_zero_p
;
288 /* Information about a function's frame layout. */
289 struct GTY(()) mips_frame_info
{
290 /* The size of the frame in bytes. */
291 HOST_WIDE_INT total_size
;
293 /* The number of bytes allocated to variables. */
294 HOST_WIDE_INT var_size
;
296 /* The number of bytes allocated to outgoing function arguments. */
297 HOST_WIDE_INT args_size
;
299 /* The number of bytes allocated to the .cprestore slot, or 0 if there
301 HOST_WIDE_INT cprestore_size
;
303 /* Bit X is set if the function saves or restores GPR X. */
306 /* Likewise FPR X. */
309 /* Likewise doubleword accumulator X ($acX). */
310 unsigned int acc_mask
;
312 /* The number of GPRs, FPRs, doubleword accumulators and COP0
316 unsigned int num_acc
;
317 unsigned int num_cop0_regs
;
319 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
320 save slots from the top of the frame, or zero if no such slots are
322 HOST_WIDE_INT gp_save_offset
;
323 HOST_WIDE_INT fp_save_offset
;
324 HOST_WIDE_INT acc_save_offset
;
325 HOST_WIDE_INT cop0_save_offset
;
327 /* Likewise, but giving offsets from the bottom of the frame. */
328 HOST_WIDE_INT gp_sp_offset
;
329 HOST_WIDE_INT fp_sp_offset
;
330 HOST_WIDE_INT acc_sp_offset
;
331 HOST_WIDE_INT cop0_sp_offset
;
333 /* Similar, but the value passed to _mcount. */
334 HOST_WIDE_INT ra_fp_offset
;
336 /* The offset of arg_pointer_rtx from the bottom of the frame. */
337 HOST_WIDE_INT arg_pointer_offset
;
339 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
340 HOST_WIDE_INT hard_frame_pointer_offset
;
343 struct GTY(()) machine_function
{
344 /* The next floating-point condition-code register to allocate
345 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
346 unsigned int next_fcc
;
348 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
349 rtx mips16_gp_pseudo_rtx
;
351 /* The number of extra stack bytes taken up by register varargs.
352 This area is allocated by the callee at the very top of the frame. */
355 /* The current frame information, calculated by mips_compute_frame_info. */
356 struct mips_frame_info frame
;
358 /* The register to use as the function's global pointer, or INVALID_REGNUM
359 if the function doesn't need one. */
360 unsigned int global_pointer
;
362 /* How many instructions it takes to load a label into $AT, or 0 if
363 this property hasn't yet been calculated. */
364 unsigned int load_label_num_insns
;
366 /* True if mips_adjust_insn_length should ignore an instruction's
368 bool ignore_hazard_length_p
;
370 /* True if the whole function is suitable for .set noreorder and
372 bool all_noreorder_p
;
374 /* True if the function has "inflexible" and "flexible" references
375 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
376 and mips_cfun_has_flexible_gp_ref_p for details. */
377 bool has_inflexible_gp_insn_p
;
378 bool has_flexible_gp_insn_p
;
380 /* True if the function's prologue must load the global pointer
381 value into pic_offset_table_rtx and store the same value in
382 the function's cprestore slot (if any). Even if this value
383 is currently false, we may decide to set it to true later;
384 see mips_must_initialize_gp_p () for details. */
385 bool must_initialize_gp_p
;
387 /* True if the current function must restore $gp after any potential
388 clobber. This value is only meaningful during the first post-epilogue
389 split_insns pass; see mips_must_initialize_gp_p () for details. */
390 bool must_restore_gp_when_clobbered_p
;
392 /* True if this is an interrupt handler. */
393 bool interrupt_handler_p
;
395 /* True if this is an interrupt handler that uses shadow registers. */
396 bool use_shadow_register_set_p
;
398 /* True if this is an interrupt handler that should keep interrupts
400 bool keep_interrupts_masked_p
;
402 /* True if this is an interrupt handler that should use DERET
404 bool use_debug_exception_return_p
;
407 /* Information about a single argument. */
408 struct mips_arg_info
{
409 /* True if the argument is passed in a floating-point register, or
410 would have been if we hadn't run out of registers. */
413 /* The number of words passed in registers, rounded up. */
414 unsigned int reg_words
;
416 /* For EABI, the offset of the first register from GP_ARG_FIRST or
417 FP_ARG_FIRST. For other ABIs, the offset of the first register from
418 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
419 comment for details).
421 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
423 unsigned int reg_offset
;
425 /* The number of words that must be passed on the stack, rounded up. */
426 unsigned int stack_words
;
428 /* The offset from the start of the stack overflow area of the argument's
429 first stack word. Only meaningful when STACK_WORDS is nonzero. */
430 unsigned int stack_offset
;
433 /* Information about an address described by mips_address_type.
439 REG is the base register and OFFSET is the constant offset.
442 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
443 is the type of symbol it references.
446 SYMBOL_TYPE is the type of symbol that the address references. */
447 struct mips_address_info
{
448 enum mips_address_type type
;
451 enum mips_symbol_type symbol_type
;
454 /* One stage in a constant building sequence. These sequences have
458 A = A CODE[1] VALUE[1]
459 A = A CODE[2] VALUE[2]
462 where A is an accumulator, each CODE[i] is a binary rtl operation
463 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
464 struct mips_integer_op
{
466 unsigned HOST_WIDE_INT value
;
469 /* The largest number of operations needed to load an integer constant.
470 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
471 When the lowest bit is clear, we can try, but reject a sequence with
472 an extra SLL at the end. */
473 #define MIPS_MAX_INTEGER_OPS 7
475 /* Information about a MIPS16e SAVE or RESTORE instruction. */
476 struct mips16e_save_restore_info
{
477 /* The number of argument registers saved by a SAVE instruction.
478 0 for RESTORE instructions. */
481 /* Bit X is set if the instruction saves or restores GPR X. */
484 /* The total number of bytes to allocate. */
488 /* Costs of various operations on the different architectures. */
490 struct mips_rtx_cost_data
492 unsigned short fp_add
;
493 unsigned short fp_mult_sf
;
494 unsigned short fp_mult_df
;
495 unsigned short fp_div_sf
;
496 unsigned short fp_div_df
;
497 unsigned short int_mult_si
;
498 unsigned short int_mult_di
;
499 unsigned short int_div_si
;
500 unsigned short int_div_di
;
501 unsigned short branch_cost
;
502 unsigned short memory_latency
;
505 /* Global variables for machine-dependent things. */
507 /* The -G setting, or the configuration's default small-data limit if
508 no -G option is given. */
509 static unsigned int mips_small_data_threshold
;
511 /* The number of file directives written by mips_output_filename. */
512 int num_source_filenames
;
514 /* The name that appeared in the last .file directive written by
515 mips_output_filename, or "" if mips_output_filename hasn't
516 written anything yet. */
517 const char *current_function_file
= "";
519 /* Arrays that map GCC register numbers to debugger register numbers. */
520 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
521 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
523 /* Information about the current function's epilogue, used only while
526 /* A list of queued REG_CFA_RESTORE notes. */
529 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
531 HOST_WIDE_INT cfa_offset
;
533 /* The offset of the CFA from the stack pointer while restoring
535 HOST_WIDE_INT cfa_restore_sp_offset
;
538 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
539 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
540 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
541 struct mips_asm_switch mips_noat
= { "at", 0 };
543 /* True if we're writing out a branch-likely instruction rather than a
545 static bool mips_branch_likely
;
547 /* The current instruction-set architecture. */
548 enum processor mips_arch
;
549 const struct mips_cpu_info
*mips_arch_info
;
551 /* The processor that we should tune the code for. */
552 enum processor mips_tune
;
553 const struct mips_cpu_info
*mips_tune_info
;
555 /* The ISA level associated with mips_arch. */
558 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
559 static const struct mips_cpu_info
*mips_isa_option_info
;
561 /* Which cost information to use. */
562 static const struct mips_rtx_cost_data
*mips_cost
;
564 /* The ambient target flags, excluding MASK_MIPS16. */
565 static int mips_base_target_flags
;
567 /* The default compression mode. */
568 unsigned int mips_base_compression_flags
;
570 /* The ambient values of other global variables. */
571 static int mips_base_schedule_insns
; /* flag_schedule_insns */
572 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
573 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
574 static int mips_base_align_loops
; /* align_loops */
575 static int mips_base_align_jumps
; /* align_jumps */
576 static int mips_base_align_functions
; /* align_functions */
578 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
579 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
581 /* Index C is true if character C is a valid PRINT_OPERAND punctation
583 static bool mips_print_operand_punct
[256];
585 static GTY (()) int mips_output_filename_first_time
= 1;
587 /* mips_split_p[X] is true if symbols of type X can be split by
588 mips_split_symbol. */
589 bool mips_split_p
[NUM_SYMBOL_TYPES
];
591 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
592 can be split by mips_split_symbol. */
593 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
595 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
596 forced into a PC-relative constant pool. */
597 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
599 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
600 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
601 if they are matched by a special .md file pattern. */
602 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
604 /* Likewise for HIGHs. */
605 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
607 /* Target state for MIPS16. */
608 struct target_globals
*mips16_globals
;
610 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
611 and returned from mips_sched_reorder2. */
612 static int cached_can_issue_more
;
614 /* True if the output uses __mips16_rdhwr. */
615 static bool mips_need_mips16_rdhwr_p
;
617 /* Index R is the smallest register class that contains register R. */
618 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
619 LEA_REGS
, LEA_REGS
, M16_REGS
, V1_REG
,
620 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
621 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
622 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
623 M16_REGS
, M16_REGS
, LEA_REGS
, LEA_REGS
,
624 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
625 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
626 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
627 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
628 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
629 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
630 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
631 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
632 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
633 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
634 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
635 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
636 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
637 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
638 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
639 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
640 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
641 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
642 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
643 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
644 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
645 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
646 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
647 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
648 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
649 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
650 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
651 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
652 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
653 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
654 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
655 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
656 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
657 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
658 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
659 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
660 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
661 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
662 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
663 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
664 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
665 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
668 /* The value of TARGET_ATTRIBUTE_TABLE. */
669 static const struct attribute_spec mips_attribute_table
[] = {
670 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
672 { "long_call", 0, 0, false, true, true, NULL
, false },
673 { "far", 0, 0, false, true, true, NULL
, false },
674 { "near", 0, 0, false, true, true, NULL
, false },
675 /* We would really like to treat "mips16" and "nomips16" as type
676 attributes, but GCC doesn't provide the hooks we need to support
677 the right conversion rules. As declaration attributes, they affect
678 code generation but don't carry other semantics. */
679 { "mips16", 0, 0, true, false, false, NULL
, false },
680 { "nomips16", 0, 0, true, false, false, NULL
, false },
681 { "micromips", 0, 0, true, false, false, NULL
, false },
682 { "nomicromips", 0, 0, true, false, false, NULL
, false },
683 { "nocompression", 0, 0, true, false, false, NULL
, false },
684 /* Allow functions to be specified as interrupt handlers */
685 { "interrupt", 0, 0, false, true, true, NULL
, false },
686 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
687 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
688 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
689 { NULL
, 0, 0, false, false, false, NULL
, false }
692 /* A table describing all the processors GCC knows about; see
693 mips-cpus.def for details. */
694 static const struct mips_cpu_info mips_cpu_info_table
[] = {
695 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
696 { NAME, CPU, ISA, FLAGS },
697 #include "mips-cpus.def"
701 /* Default costs. If these are used for a processor we should look
702 up the actual costs. */
703 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
704 COSTS_N_INSNS (7), /* fp_mult_sf */ \
705 COSTS_N_INSNS (8), /* fp_mult_df */ \
706 COSTS_N_INSNS (23), /* fp_div_sf */ \
707 COSTS_N_INSNS (36), /* fp_div_df */ \
708 COSTS_N_INSNS (10), /* int_mult_si */ \
709 COSTS_N_INSNS (10), /* int_mult_di */ \
710 COSTS_N_INSNS (69), /* int_div_si */ \
711 COSTS_N_INSNS (69), /* int_div_di */ \
712 2, /* branch_cost */ \
713 4 /* memory_latency */
715 /* Floating-point costs for processors without an FPU. Just assume that
716 all floating-point libcalls are very expensive. */
717 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
718 COSTS_N_INSNS (256), /* fp_mult_sf */ \
719 COSTS_N_INSNS (256), /* fp_mult_df */ \
720 COSTS_N_INSNS (256), /* fp_div_sf */ \
721 COSTS_N_INSNS (256) /* fp_div_df */
723 /* Costs to use when optimizing for size. */
724 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
725 COSTS_N_INSNS (1), /* fp_add */
726 COSTS_N_INSNS (1), /* fp_mult_sf */
727 COSTS_N_INSNS (1), /* fp_mult_df */
728 COSTS_N_INSNS (1), /* fp_div_sf */
729 COSTS_N_INSNS (1), /* fp_div_df */
730 COSTS_N_INSNS (1), /* int_mult_si */
731 COSTS_N_INSNS (1), /* int_mult_di */
732 COSTS_N_INSNS (1), /* int_div_si */
733 COSTS_N_INSNS (1), /* int_div_di */
735 4 /* memory_latency */
738 /* Costs to use when optimizing for speed, indexed by processor. */
739 static const struct mips_rtx_cost_data
740 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
742 COSTS_N_INSNS (2), /* fp_add */
743 COSTS_N_INSNS (4), /* fp_mult_sf */
744 COSTS_N_INSNS (5), /* fp_mult_df */
745 COSTS_N_INSNS (12), /* fp_div_sf */
746 COSTS_N_INSNS (19), /* fp_div_df */
747 COSTS_N_INSNS (12), /* int_mult_si */
748 COSTS_N_INSNS (12), /* int_mult_di */
749 COSTS_N_INSNS (35), /* int_div_si */
750 COSTS_N_INSNS (35), /* int_div_di */
752 4 /* memory_latency */
756 COSTS_N_INSNS (6), /* int_mult_si */
757 COSTS_N_INSNS (6), /* int_mult_di */
758 COSTS_N_INSNS (36), /* int_div_si */
759 COSTS_N_INSNS (36), /* int_div_di */
761 4 /* memory_latency */
765 COSTS_N_INSNS (36), /* int_mult_si */
766 COSTS_N_INSNS (36), /* int_mult_di */
767 COSTS_N_INSNS (37), /* int_div_si */
768 COSTS_N_INSNS (37), /* int_div_di */
770 4 /* memory_latency */
774 COSTS_N_INSNS (4), /* int_mult_si */
775 COSTS_N_INSNS (11), /* int_mult_di */
776 COSTS_N_INSNS (36), /* int_div_si */
777 COSTS_N_INSNS (68), /* int_div_di */
779 4 /* memory_latency */
782 COSTS_N_INSNS (4), /* fp_add */
783 COSTS_N_INSNS (4), /* fp_mult_sf */
784 COSTS_N_INSNS (5), /* fp_mult_df */
785 COSTS_N_INSNS (17), /* fp_div_sf */
786 COSTS_N_INSNS (32), /* fp_div_df */
787 COSTS_N_INSNS (4), /* int_mult_si */
788 COSTS_N_INSNS (11), /* int_mult_di */
789 COSTS_N_INSNS (36), /* int_div_si */
790 COSTS_N_INSNS (68), /* int_div_di */
792 4 /* memory_latency */
795 COSTS_N_INSNS (4), /* fp_add */
796 COSTS_N_INSNS (4), /* fp_mult_sf */
797 COSTS_N_INSNS (5), /* fp_mult_df */
798 COSTS_N_INSNS (17), /* fp_div_sf */
799 COSTS_N_INSNS (32), /* fp_div_df */
800 COSTS_N_INSNS (4), /* int_mult_si */
801 COSTS_N_INSNS (7), /* int_mult_di */
802 COSTS_N_INSNS (42), /* int_div_si */
803 COSTS_N_INSNS (72), /* int_div_di */
805 4 /* memory_latency */
809 COSTS_N_INSNS (5), /* int_mult_si */
810 COSTS_N_INSNS (5), /* int_mult_di */
811 COSTS_N_INSNS (41), /* int_div_si */
812 COSTS_N_INSNS (41), /* int_div_di */
814 4 /* memory_latency */
817 COSTS_N_INSNS (8), /* fp_add */
818 COSTS_N_INSNS (8), /* fp_mult_sf */
819 COSTS_N_INSNS (10), /* fp_mult_df */
820 COSTS_N_INSNS (34), /* fp_div_sf */
821 COSTS_N_INSNS (64), /* fp_div_df */
822 COSTS_N_INSNS (5), /* int_mult_si */
823 COSTS_N_INSNS (5), /* int_mult_di */
824 COSTS_N_INSNS (41), /* int_div_si */
825 COSTS_N_INSNS (41), /* int_div_di */
827 4 /* memory_latency */
830 COSTS_N_INSNS (4), /* fp_add */
831 COSTS_N_INSNS (4), /* fp_mult_sf */
832 COSTS_N_INSNS (5), /* fp_mult_df */
833 COSTS_N_INSNS (17), /* fp_div_sf */
834 COSTS_N_INSNS (32), /* fp_div_df */
835 COSTS_N_INSNS (5), /* int_mult_si */
836 COSTS_N_INSNS (5), /* int_mult_di */
837 COSTS_N_INSNS (41), /* int_div_si */
838 COSTS_N_INSNS (41), /* int_div_di */
840 4 /* memory_latency */
844 COSTS_N_INSNS (5), /* int_mult_si */
845 COSTS_N_INSNS (5), /* int_mult_di */
846 COSTS_N_INSNS (41), /* int_div_si */
847 COSTS_N_INSNS (41), /* int_div_di */
849 4 /* memory_latency */
852 COSTS_N_INSNS (8), /* fp_add */
853 COSTS_N_INSNS (8), /* fp_mult_sf */
854 COSTS_N_INSNS (10), /* fp_mult_df */
855 COSTS_N_INSNS (34), /* fp_div_sf */
856 COSTS_N_INSNS (64), /* fp_div_df */
857 COSTS_N_INSNS (5), /* int_mult_si */
858 COSTS_N_INSNS (5), /* int_mult_di */
859 COSTS_N_INSNS (41), /* int_div_si */
860 COSTS_N_INSNS (41), /* int_div_di */
862 4 /* memory_latency */
865 COSTS_N_INSNS (4), /* fp_add */
866 COSTS_N_INSNS (4), /* fp_mult_sf */
867 COSTS_N_INSNS (5), /* fp_mult_df */
868 COSTS_N_INSNS (17), /* fp_div_sf */
869 COSTS_N_INSNS (32), /* fp_div_df */
870 COSTS_N_INSNS (5), /* int_mult_si */
871 COSTS_N_INSNS (5), /* int_mult_di */
872 COSTS_N_INSNS (41), /* int_div_si */
873 COSTS_N_INSNS (41), /* int_div_di */
875 4 /* memory_latency */
878 COSTS_N_INSNS (6), /* fp_add */
879 COSTS_N_INSNS (6), /* fp_mult_sf */
880 COSTS_N_INSNS (7), /* fp_mult_df */
881 COSTS_N_INSNS (25), /* fp_div_sf */
882 COSTS_N_INSNS (48), /* fp_div_df */
883 COSTS_N_INSNS (5), /* int_mult_si */
884 COSTS_N_INSNS (5), /* int_mult_di */
885 COSTS_N_INSNS (41), /* int_div_si */
886 COSTS_N_INSNS (41), /* int_div_di */
888 4 /* memory_latency */
905 COSTS_N_INSNS (5), /* int_mult_si */
906 COSTS_N_INSNS (5), /* int_mult_di */
907 COSTS_N_INSNS (72), /* int_div_si */
908 COSTS_N_INSNS (72), /* int_div_di */
910 4 /* memory_latency */
915 COSTS_N_INSNS (6), /* int_mult_si */
916 COSTS_N_INSNS (6), /* int_mult_di */
917 COSTS_N_INSNS (18), /* int_div_si */
918 COSTS_N_INSNS (35), /* int_div_di */
920 4 /* memory_latency */
923 COSTS_N_INSNS (2), /* fp_add */
924 COSTS_N_INSNS (4), /* fp_mult_sf */
925 COSTS_N_INSNS (5), /* fp_mult_df */
926 COSTS_N_INSNS (12), /* fp_div_sf */
927 COSTS_N_INSNS (19), /* fp_div_df */
928 COSTS_N_INSNS (2), /* int_mult_si */
929 COSTS_N_INSNS (2), /* int_mult_di */
930 COSTS_N_INSNS (35), /* int_div_si */
931 COSTS_N_INSNS (35), /* int_div_di */
933 4 /* memory_latency */
936 COSTS_N_INSNS (3), /* fp_add */
937 COSTS_N_INSNS (5), /* fp_mult_sf */
938 COSTS_N_INSNS (6), /* fp_mult_df */
939 COSTS_N_INSNS (15), /* fp_div_sf */
940 COSTS_N_INSNS (16), /* fp_div_df */
941 COSTS_N_INSNS (17), /* int_mult_si */
942 COSTS_N_INSNS (17), /* int_mult_di */
943 COSTS_N_INSNS (38), /* int_div_si */
944 COSTS_N_INSNS (38), /* int_div_di */
946 6 /* memory_latency */
949 COSTS_N_INSNS (6), /* fp_add */
950 COSTS_N_INSNS (7), /* fp_mult_sf */
951 COSTS_N_INSNS (8), /* fp_mult_df */
952 COSTS_N_INSNS (23), /* fp_div_sf */
953 COSTS_N_INSNS (36), /* fp_div_df */
954 COSTS_N_INSNS (10), /* int_mult_si */
955 COSTS_N_INSNS (10), /* int_mult_di */
956 COSTS_N_INSNS (69), /* int_div_si */
957 COSTS_N_INSNS (69), /* int_div_di */
959 6 /* memory_latency */
971 /* The only costs that appear to be updated here are
972 integer multiplication. */
974 COSTS_N_INSNS (4), /* int_mult_si */
975 COSTS_N_INSNS (6), /* int_mult_di */
976 COSTS_N_INSNS (69), /* int_div_si */
977 COSTS_N_INSNS (69), /* int_div_di */
979 4 /* memory_latency */
994 COSTS_N_INSNS (6), /* fp_add */
995 COSTS_N_INSNS (4), /* fp_mult_sf */
996 COSTS_N_INSNS (5), /* fp_mult_df */
997 COSTS_N_INSNS (23), /* fp_div_sf */
998 COSTS_N_INSNS (36), /* fp_div_df */
999 COSTS_N_INSNS (5), /* int_mult_si */
1000 COSTS_N_INSNS (5), /* int_mult_di */
1001 COSTS_N_INSNS (36), /* int_div_si */
1002 COSTS_N_INSNS (36), /* int_div_di */
1003 1, /* branch_cost */
1004 4 /* memory_latency */
1007 COSTS_N_INSNS (6), /* fp_add */
1008 COSTS_N_INSNS (5), /* fp_mult_sf */
1009 COSTS_N_INSNS (6), /* fp_mult_df */
1010 COSTS_N_INSNS (30), /* fp_div_sf */
1011 COSTS_N_INSNS (59), /* fp_div_df */
1012 COSTS_N_INSNS (3), /* int_mult_si */
1013 COSTS_N_INSNS (4), /* int_mult_di */
1014 COSTS_N_INSNS (42), /* int_div_si */
1015 COSTS_N_INSNS (74), /* int_div_di */
1016 1, /* branch_cost */
1017 4 /* memory_latency */
1020 COSTS_N_INSNS (6), /* fp_add */
1021 COSTS_N_INSNS (5), /* fp_mult_sf */
1022 COSTS_N_INSNS (6), /* fp_mult_df */
1023 COSTS_N_INSNS (30), /* fp_div_sf */
1024 COSTS_N_INSNS (59), /* fp_div_df */
1025 COSTS_N_INSNS (5), /* int_mult_si */
1026 COSTS_N_INSNS (9), /* int_mult_di */
1027 COSTS_N_INSNS (42), /* int_div_si */
1028 COSTS_N_INSNS (74), /* int_div_di */
1029 1, /* branch_cost */
1030 4 /* memory_latency */
1033 /* The only costs that are changed here are
1034 integer multiplication. */
1035 COSTS_N_INSNS (6), /* fp_add */
1036 COSTS_N_INSNS (7), /* fp_mult_sf */
1037 COSTS_N_INSNS (8), /* fp_mult_df */
1038 COSTS_N_INSNS (23), /* fp_div_sf */
1039 COSTS_N_INSNS (36), /* fp_div_df */
1040 COSTS_N_INSNS (5), /* int_mult_si */
1041 COSTS_N_INSNS (9), /* int_mult_di */
1042 COSTS_N_INSNS (69), /* int_div_si */
1043 COSTS_N_INSNS (69), /* int_div_di */
1044 1, /* branch_cost */
1045 4 /* memory_latency */
1051 /* The only costs that are changed here are
1052 integer multiplication. */
1053 COSTS_N_INSNS (6), /* fp_add */
1054 COSTS_N_INSNS (7), /* fp_mult_sf */
1055 COSTS_N_INSNS (8), /* fp_mult_df */
1056 COSTS_N_INSNS (23), /* fp_div_sf */
1057 COSTS_N_INSNS (36), /* fp_div_df */
1058 COSTS_N_INSNS (3), /* int_mult_si */
1059 COSTS_N_INSNS (8), /* int_mult_di */
1060 COSTS_N_INSNS (69), /* int_div_si */
1061 COSTS_N_INSNS (69), /* int_div_di */
1062 1, /* branch_cost */
1063 4 /* memory_latency */
1066 COSTS_N_INSNS (2), /* fp_add */
1067 COSTS_N_INSNS (2), /* fp_mult_sf */
1068 COSTS_N_INSNS (2), /* fp_mult_df */
1069 COSTS_N_INSNS (12), /* fp_div_sf */
1070 COSTS_N_INSNS (19), /* fp_div_df */
1071 COSTS_N_INSNS (5), /* int_mult_si */
1072 COSTS_N_INSNS (9), /* int_mult_di */
1073 COSTS_N_INSNS (34), /* int_div_si */
1074 COSTS_N_INSNS (66), /* int_div_di */
1075 1, /* branch_cost */
1076 4 /* memory_latency */
1079 /* These costs are the same as the SB-1A below. */
1080 COSTS_N_INSNS (4), /* fp_add */
1081 COSTS_N_INSNS (4), /* fp_mult_sf */
1082 COSTS_N_INSNS (4), /* fp_mult_df */
1083 COSTS_N_INSNS (24), /* fp_div_sf */
1084 COSTS_N_INSNS (32), /* fp_div_df */
1085 COSTS_N_INSNS (3), /* int_mult_si */
1086 COSTS_N_INSNS (4), /* int_mult_di */
1087 COSTS_N_INSNS (36), /* int_div_si */
1088 COSTS_N_INSNS (68), /* int_div_di */
1089 1, /* branch_cost */
1090 4 /* memory_latency */
1093 /* These costs are the same as the SB-1 above. */
1094 COSTS_N_INSNS (4), /* fp_add */
1095 COSTS_N_INSNS (4), /* fp_mult_sf */
1096 COSTS_N_INSNS (4), /* fp_mult_df */
1097 COSTS_N_INSNS (24), /* fp_div_sf */
1098 COSTS_N_INSNS (32), /* fp_div_df */
1099 COSTS_N_INSNS (3), /* int_mult_si */
1100 COSTS_N_INSNS (4), /* int_mult_di */
1101 COSTS_N_INSNS (36), /* int_div_si */
1102 COSTS_N_INSNS (68), /* int_div_di */
1103 1, /* branch_cost */
1104 4 /* memory_latency */
1111 COSTS_N_INSNS (8), /* int_mult_si */
1112 COSTS_N_INSNS (8), /* int_mult_di */
1113 COSTS_N_INSNS (72), /* int_div_si */
1114 COSTS_N_INSNS (72), /* int_div_di */
1115 1, /* branch_cost */
1116 4 /* memory_latency */
1119 /* These costs are the same as 5KF above. */
1120 COSTS_N_INSNS (4), /* fp_add */
1121 COSTS_N_INSNS (4), /* fp_mult_sf */
1122 COSTS_N_INSNS (5), /* fp_mult_df */
1123 COSTS_N_INSNS (17), /* fp_div_sf */
1124 COSTS_N_INSNS (32), /* fp_div_df */
1125 COSTS_N_INSNS (4), /* int_mult_si */
1126 COSTS_N_INSNS (11), /* int_mult_di */
1127 COSTS_N_INSNS (36), /* int_div_si */
1128 COSTS_N_INSNS (68), /* int_div_di */
1129 1, /* branch_cost */
1130 4 /* memory_latency */
1134 static rtx
mips_find_pic_call_symbol (rtx
, rtx
, bool);
1135 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1137 static unsigned int mips_function_arg_boundary (enum machine_mode
, const_tree
);
1139 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1140 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1141 struct GTY (()) mflip_mips16_entry
{
1145 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1147 /* Hash table callbacks for mflip_mips16_htab. */
1150 mflip_mips16_htab_hash (const void *entry
)
1152 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1156 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1158 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1159 (const char *) name
) == 0;
1162 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1163 mode, false if it should next add an attribute for the opposite mode. */
1164 static GTY(()) bool mips16_flipper
;
1166 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1167 for -mflip-mips16. Return true if it should use "mips16" and false if
1168 it should use "nomips16". */
1171 mflip_mips16_use_mips16_p (tree decl
)
1173 struct mflip_mips16_entry
*entry
;
1177 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1179 /* Use the opposite of the command-line setting for anonymous decls. */
1180 if (!DECL_NAME (decl
))
1181 return !base_is_mips16
;
1183 if (!mflip_mips16_htab
)
1184 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1185 mflip_mips16_htab_eq
, NULL
);
1187 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1188 hash
= htab_hash_string (name
);
1189 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1190 entry
= (struct mflip_mips16_entry
*) *slot
;
1193 mips16_flipper
= !mips16_flipper
;
1194 entry
= ggc_alloc_mflip_mips16_entry ();
1196 entry
->mips16_p
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1199 return entry
->mips16_p
;
1202 /* Predicates to test for presence of "near" and "far"/"long_call"
1203 attributes on the given TYPE. */
1206 mips_near_type_p (const_tree type
)
1208 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1212 mips_far_type_p (const_tree type
)
1214 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1215 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1219 /* Check if the interrupt attribute is set for a function. */
1222 mips_interrupt_type_p (tree type
)
1224 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1227 /* Check if the attribute to use shadow register set is set for a function. */
1230 mips_use_shadow_register_set_p (tree type
)
1232 return lookup_attribute ("use_shadow_register_set",
1233 TYPE_ATTRIBUTES (type
)) != NULL
;
1236 /* Check if the attribute to keep interrupts masked is set for a function. */
1239 mips_keep_interrupts_masked_p (tree type
)
1241 return lookup_attribute ("keep_interrupts_masked",
1242 TYPE_ATTRIBUTES (type
)) != NULL
;
1245 /* Check if the attribute to use debug exception return is set for
1249 mips_use_debug_exception_return_p (tree type
)
1251 return lookup_attribute ("use_debug_exception_return",
1252 TYPE_ATTRIBUTES (type
)) != NULL
;
1255 /* Return the set of compression modes that are explicitly required
1256 by the attributes in ATTRIBUTES. */
1259 mips_get_compress_on_flags (tree attributes
)
1261 unsigned int flags
= 0;
1263 if (lookup_attribute ("mips16", attributes
) != NULL
)
1264 flags
|= MASK_MIPS16
;
1266 if (lookup_attribute ("micromips", attributes
) != NULL
)
1267 flags
|= MASK_MICROMIPS
;
1272 /* Return the set of compression modes that are explicitly forbidden
1273 by the attributes in ATTRIBUTES. */
1276 mips_get_compress_off_flags (tree attributes
)
1278 unsigned int flags
= 0;
1280 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1281 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1283 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1284 flags
|= MASK_MIPS16
;
1286 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1287 flags
|= MASK_MICROMIPS
;
1292 /* Return the compression mode that should be used for function DECL.
1293 Return the ambient setting if DECL is null. */
1296 mips_get_compress_mode (tree decl
)
1298 unsigned int flags
, force_on
;
1300 flags
= mips_base_compression_flags
;
1303 /* Nested functions must use the same frame pointer as their
1304 parent and must therefore use the same ISA mode. */
1305 tree parent
= decl_function_context (decl
);
1308 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1311 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1316 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1320 mips_get_compress_on_name (unsigned int flags
)
1322 if (flags
== MASK_MIPS16
)
1327 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1331 mips_get_compress_off_name (unsigned int flags
)
1333 if (flags
== MASK_MIPS16
)
1335 if (flags
== MASK_MICROMIPS
)
1336 return "nomicromips";
1337 return "nocompression";
1340 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1343 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1345 /* Disallow mixed near/far attributes. */
1346 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1348 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1353 /* Implement TARGET_INSERT_ATTRIBUTES. */
1356 mips_insert_attributes (tree decl
, tree
*attributes
)
1359 unsigned int compression_flags
, nocompression_flags
;
1361 /* Check for "mips16" and "nomips16" attributes. */
1362 compression_flags
= mips_get_compress_on_flags (*attributes
);
1363 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1365 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1367 if (nocompression_flags
)
1368 error ("%qs attribute only applies to functions",
1369 mips_get_compress_off_name (nocompression_flags
));
1371 if (compression_flags
)
1372 error ("%qs attribute only applies to functions",
1373 mips_get_compress_on_name (nocompression_flags
));
1377 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1378 nocompression_flags
|=
1379 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1381 if (compression_flags
&& nocompression_flags
)
1382 error ("%qE cannot have both %qs and %qs attributes",
1383 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1384 mips_get_compress_off_name (nocompression_flags
));
1386 if (compression_flags
& MASK_MIPS16
1387 && compression_flags
& MASK_MICROMIPS
)
1388 error ("%qE cannot have both %qs and %qs attributes",
1389 DECL_NAME (decl
), "mips16", "micromips");
1391 if (TARGET_FLIP_MIPS16
1392 && !DECL_ARTIFICIAL (decl
)
1393 && compression_flags
== 0
1394 && nocompression_flags
== 0)
1396 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1397 "mips16" attribute, arbitrarily pick one. We must pick the same
1398 setting for duplicate declarations of a function. */
1399 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1400 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1401 name
= "nomicromips";
1402 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1407 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1410 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1414 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1415 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1417 error ("%qE redeclared with conflicting %qs attributes",
1418 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1420 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1421 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1423 error ("%qE redeclared with conflicting %qs attributes",
1424 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1426 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1427 DECL_ATTRIBUTES (newdecl
));
1430 /* Implement TARGET_CAN_INLINE_P. */
1433 mips_can_inline_p (tree caller
, tree callee
)
1435 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1437 return default_target_can_inline_p (caller
, callee
);
1440 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1441 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1444 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1446 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1448 *base_ptr
= XEXP (x
, 0);
1449 *offset_ptr
= INTVAL (XEXP (x
, 1));
1458 static unsigned int mips_build_integer (struct mips_integer_op
*,
1459 unsigned HOST_WIDE_INT
);
1461 /* A subroutine of mips_build_integer, with the same interface.
1462 Assume that the final action in the sequence should be a left shift. */
1465 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1467 unsigned int i
, shift
;
1469 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1470 since signed numbers are easier to load than unsigned ones. */
1472 while ((value
& 1) == 0)
1473 value
/= 2, shift
++;
1475 i
= mips_build_integer (codes
, value
);
1476 codes
[i
].code
= ASHIFT
;
1477 codes
[i
].value
= shift
;
1481 /* As for mips_build_shift, but assume that the final action will be
1482 an IOR or PLUS operation. */
1485 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1487 unsigned HOST_WIDE_INT high
;
1490 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1491 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1493 /* The constant is too complex to load with a simple LUI/ORI pair,
1494 so we want to give the recursive call as many trailing zeros as
1495 possible. In this case, we know bit 16 is set and that the
1496 low 16 bits form a negative number. If we subtract that number
1497 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1498 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1499 codes
[i
].code
= PLUS
;
1500 codes
[i
].value
= CONST_LOW_PART (value
);
1504 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1505 bits gives a value with at least 17 trailing zeros. */
1506 i
= mips_build_integer (codes
, high
);
1507 codes
[i
].code
= IOR
;
1508 codes
[i
].value
= value
& 0xffff;
1513 /* Fill CODES with a sequence of rtl operations to load VALUE.
1514 Return the number of operations needed. */
1517 mips_build_integer (struct mips_integer_op
*codes
,
1518 unsigned HOST_WIDE_INT value
)
1520 if (SMALL_OPERAND (value
)
1521 || SMALL_OPERAND_UNSIGNED (value
)
1522 || LUI_OPERAND (value
))
1524 /* The value can be loaded with a single instruction. */
1525 codes
[0].code
= UNKNOWN
;
1526 codes
[0].value
= value
;
1529 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1531 /* Either the constant is a simple LUI/ORI combination or its
1532 lowest bit is set. We don't want to shift in this case. */
1533 return mips_build_lower (codes
, value
);
1535 else if ((value
& 0xffff) == 0)
1537 /* The constant will need at least three actions. The lowest
1538 16 bits are clear, so the final action will be a shift. */
1539 return mips_build_shift (codes
, value
);
1543 /* The final action could be a shift, add or inclusive OR.
1544 Rather than use a complex condition to select the best
1545 approach, try both mips_build_shift and mips_build_lower
1546 and pick the one that gives the shortest sequence.
1547 Note that this case is only used once per constant. */
1548 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1549 unsigned int cost
, alt_cost
;
1551 cost
= mips_build_shift (codes
, value
);
1552 alt_cost
= mips_build_lower (alt_codes
, value
);
1553 if (alt_cost
< cost
)
1555 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1562 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1565 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1567 return mips_const_insns (x
) > 0;
1570 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1573 mips16_stub_function (const char *name
)
1577 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1578 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1582 /* Return true if symbols of type TYPE require a GOT access. */
1585 mips_got_symbol_type_p (enum mips_symbol_type type
)
1589 case SYMBOL_GOT_PAGE_OFST
:
1590 case SYMBOL_GOT_DISP
:
1598 /* Return true if X is a thread-local symbol. */
1601 mips_tls_symbol_p (rtx x
)
1603 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1606 /* Return true if SYMBOL_REF X is associated with a global symbol
1607 (in the STB_GLOBAL sense). */
1610 mips_global_symbol_p (const_rtx x
)
1612 const_tree decl
= SYMBOL_REF_DECL (x
);
1615 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1617 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1618 or weak symbols. Relocations in the object file will be against
1619 the target symbol, so it's that symbol's binding that matters here. */
1620 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1623 /* Return true if function X is a libgcc MIPS16 stub function. */
1626 mips16_stub_function_p (const_rtx x
)
1628 return (GET_CODE (x
) == SYMBOL_REF
1629 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1632 /* Return true if function X is a locally-defined and locally-binding
1636 mips16_local_function_p (const_rtx x
)
1638 return (GET_CODE (x
) == SYMBOL_REF
1639 && SYMBOL_REF_LOCAL_P (x
)
1640 && !SYMBOL_REF_EXTERNAL_P (x
)
1641 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1644 /* Return true if SYMBOL_REF X binds locally. */
1647 mips_symbol_binds_local_p (const_rtx x
)
1649 return (SYMBOL_REF_DECL (x
)
1650 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1651 : SYMBOL_REF_LOCAL_P (x
));
1654 /* Return true if rtx constants of mode MODE should be put into a small
1658 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1660 return (!TARGET_EMBEDDED_DATA
1661 && TARGET_LOCAL_SDATA
1662 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1665 /* Return true if X should not be moved directly into register $25.
1666 We need this because many versions of GAS will treat "la $25,foo" as
1667 part of a call sequence and so allow a global "foo" to be lazily bound. */
1670 mips_dangerous_for_la25_p (rtx x
)
1672 return (!TARGET_EXPLICIT_RELOCS
1674 && GET_CODE (x
) == SYMBOL_REF
1675 && mips_global_symbol_p (x
));
1678 /* Return true if calls to X might need $25 to be valid on entry. */
1681 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1683 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1686 /* MIPS16 stub functions are guaranteed not to use $25. */
1687 if (mips16_stub_function_p (x
))
1690 if (GET_CODE (x
) == SYMBOL_REF
)
1692 /* If PLTs and copy relocations are available, the static linker
1693 will make sure that $25 is valid on entry to the target function. */
1694 if (TARGET_ABICALLS_PIC0
)
1697 /* Locally-defined functions use absolute accesses to set up
1698 the global pointer. */
1699 if (TARGET_ABSOLUTE_ABICALLS
1700 && mips_symbol_binds_local_p (x
)
1701 && !SYMBOL_REF_EXTERNAL_P (x
))
1708 /* Return the method that should be used to access SYMBOL_REF or
1709 LABEL_REF X in context CONTEXT. */
1711 static enum mips_symbol_type
1712 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1715 return SYMBOL_GOT_DISP
;
1717 if (GET_CODE (x
) == LABEL_REF
)
1719 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1720 code and if we know that the label is in the current function's
1721 text section. LABEL_REFs are used for jump tables as well as
1722 text labels, so we must check whether jump tables live in the
1724 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1725 && !LABEL_REF_NONLOCAL_P (x
))
1726 return SYMBOL_PC_RELATIVE
;
1728 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1729 return SYMBOL_GOT_PAGE_OFST
;
1731 return SYMBOL_ABSOLUTE
;
1734 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1736 if (SYMBOL_REF_TLS_MODEL (x
))
1739 if (CONSTANT_POOL_ADDRESS_P (x
))
1741 if (TARGET_MIPS16_TEXT_LOADS
)
1742 return SYMBOL_PC_RELATIVE
;
1744 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1745 return SYMBOL_PC_RELATIVE
;
1747 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1748 return SYMBOL_GP_RELATIVE
;
1751 /* Do not use small-data accesses for weak symbols; they may end up
1753 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1754 return SYMBOL_GP_RELATIVE
;
1756 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1758 if (TARGET_ABICALLS_PIC2
1759 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1761 /* There are three cases to consider:
1763 - o32 PIC (either with or without explicit relocs)
1764 - n32/n64 PIC without explicit relocs
1765 - n32/n64 PIC with explicit relocs
1767 In the first case, both local and global accesses will use an
1768 R_MIPS_GOT16 relocation. We must correctly predict which of
1769 the two semantics (local or global) the assembler and linker
1770 will apply. The choice depends on the symbol's binding rather
1771 than its visibility.
1773 In the second case, the assembler will not use R_MIPS_GOT16
1774 relocations, but it chooses between local and global accesses
1775 in the same way as for o32 PIC.
1777 In the third case we have more freedom since both forms of
1778 access will work for any kind of symbol. However, there seems
1779 little point in doing things differently. */
1780 if (mips_global_symbol_p (x
))
1781 return SYMBOL_GOT_DISP
;
1783 return SYMBOL_GOT_PAGE_OFST
;
1786 return SYMBOL_ABSOLUTE
;
1789 /* Classify the base of symbolic expression X, given that X appears in
1792 static enum mips_symbol_type
1793 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1797 split_const (x
, &x
, &offset
);
1798 if (UNSPEC_ADDRESS_P (x
))
1799 return UNSPEC_ADDRESS_TYPE (x
);
1801 return mips_classify_symbol (x
, context
);
1804 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1805 is the alignment in bytes of SYMBOL_REF X. */
1808 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1810 HOST_WIDE_INT align
;
1812 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1813 return IN_RANGE (offset
, 0, align
- 1);
1816 /* Return true if X is a symbolic constant that can be used in context
1817 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1820 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1821 enum mips_symbol_type
*symbol_type
)
1825 split_const (x
, &x
, &offset
);
1826 if (UNSPEC_ADDRESS_P (x
))
1828 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1829 x
= UNSPEC_ADDRESS (x
);
1831 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1833 *symbol_type
= mips_classify_symbol (x
, context
);
1834 if (*symbol_type
== SYMBOL_TLS
)
1840 if (offset
== const0_rtx
)
1843 /* Check whether a nonzero offset is valid for the underlying
1845 switch (*symbol_type
)
1847 case SYMBOL_ABSOLUTE
:
1848 case SYMBOL_64_HIGH
:
1851 /* If the target has 64-bit pointers and the object file only
1852 supports 32-bit symbols, the values of those symbols will be
1853 sign-extended. In this case we can't allow an arbitrary offset
1854 in case the 32-bit value X + OFFSET has a different sign from X. */
1855 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1856 return offset_within_block_p (x
, INTVAL (offset
));
1858 /* In other cases the relocations can handle any offset. */
1861 case SYMBOL_PC_RELATIVE
:
1862 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1863 In this case, we no longer have access to the underlying constant,
1864 but the original symbol-based access was known to be valid. */
1865 if (GET_CODE (x
) == LABEL_REF
)
1870 case SYMBOL_GP_RELATIVE
:
1871 /* Make sure that the offset refers to something within the
1872 same object block. This should guarantee that the final
1873 PC- or GP-relative offset is within the 16-bit limit. */
1874 return offset_within_block_p (x
, INTVAL (offset
));
1876 case SYMBOL_GOT_PAGE_OFST
:
1877 case SYMBOL_GOTOFF_PAGE
:
1878 /* If the symbol is global, the GOT entry will contain the symbol's
1879 address, and we will apply a 16-bit offset after loading it.
1880 If the symbol is local, the linker should provide enough local
1881 GOT entries for a 16-bit offset, but larger offsets may lead
1883 return SMALL_INT (offset
);
1887 /* There is no carry between the HI and LO REL relocations, so the
1888 offset is only valid if we know it won't lead to such a carry. */
1889 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1891 case SYMBOL_GOT_DISP
:
1892 case SYMBOL_GOTOFF_DISP
:
1893 case SYMBOL_GOTOFF_CALL
:
1894 case SYMBOL_GOTOFF_LOADGP
:
1897 case SYMBOL_GOTTPREL
:
1905 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1906 single instruction. We rely on the fact that, in the worst case,
1907 all instructions involved in a MIPS16 address calculation are usually
1911 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1913 if (mips_use_pcrel_pool_p
[(int) type
])
1915 if (mode
== MAX_MACHINE_MODE
)
1916 /* LEAs will be converted into constant-pool references by
1918 type
= SYMBOL_PC_RELATIVE
;
1920 /* The constant must be loaded and then dereferenced. */
1926 case SYMBOL_ABSOLUTE
:
1927 /* When using 64-bit symbols, we need 5 preparatory instructions,
1930 lui $at,%highest(symbol)
1931 daddiu $at,$at,%higher(symbol)
1933 daddiu $at,$at,%hi(symbol)
1936 The final address is then $at + %lo(symbol). With 32-bit
1937 symbols we just need a preparatory LUI for normal mode and
1938 a preparatory LI and SLL for MIPS16. */
1939 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1941 case SYMBOL_GP_RELATIVE
:
1942 /* Treat GP-relative accesses as taking a single instruction on
1943 MIPS16 too; the copy of $gp can often be shared. */
1946 case SYMBOL_PC_RELATIVE
:
1947 /* PC-relative constants can be only be used with ADDIUPC,
1948 DADDIUPC, LWPC and LDPC. */
1949 if (mode
== MAX_MACHINE_MODE
1950 || GET_MODE_SIZE (mode
) == 4
1951 || GET_MODE_SIZE (mode
) == 8)
1954 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1957 case SYMBOL_GOT_DISP
:
1958 /* The constant will have to be loaded from the GOT before it
1959 is used in an address. */
1960 if (mode
!= MAX_MACHINE_MODE
)
1965 case SYMBOL_GOT_PAGE_OFST
:
1966 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1967 local/global classification is accurate. The worst cases are:
1969 (1) For local symbols when generating o32 or o64 code. The assembler
1975 ...and the final address will be $at + %lo(symbol).
1977 (2) For global symbols when -mxgot. The assembler will use:
1979 lui $at,%got_hi(symbol)
1982 ...and the final address will be $at + %got_lo(symbol). */
1985 case SYMBOL_GOTOFF_PAGE
:
1986 case SYMBOL_GOTOFF_DISP
:
1987 case SYMBOL_GOTOFF_CALL
:
1988 case SYMBOL_GOTOFF_LOADGP
:
1989 case SYMBOL_64_HIGH
:
1995 case SYMBOL_GOTTPREL
:
1998 /* A 16-bit constant formed by a single relocation, or a 32-bit
1999 constant formed from a high 16-bit relocation and a low 16-bit
2000 relocation. Use mips_split_p to determine which. 32-bit
2001 constants need an "lui; addiu" sequence for normal mode and
2002 an "li; sll; addiu" sequence for MIPS16 mode. */
2003 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2006 /* We don't treat a bare TLS symbol as a constant. */
2012 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2013 to load symbols of type TYPE into a register. Return 0 if the given
2014 type of symbol cannot be used as an immediate operand.
2016 Otherwise, return the number of instructions needed to load or store
2017 values of mode MODE to or from addresses of type TYPE. Return 0 if
2018 the given type of symbol is not valid in addresses.
2020 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2023 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
2025 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2028 /* A for_each_rtx callback. Stop the search if *X references a
2029 thread-local symbol. */
2032 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
2034 return mips_tls_symbol_p (*x
);
2037 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2040 mips_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2042 enum mips_symbol_type type
;
2045 /* There is no assembler syntax for expressing an address-sized
2047 if (GET_CODE (x
) == HIGH
)
2050 /* As an optimization, reject constants that mips_legitimize_move
2053 Suppose we have a multi-instruction sequence that loads constant C
2054 into register R. If R does not get allocated a hard register, and
2055 R is used in an operand that allows both registers and memory
2056 references, reload will consider forcing C into memory and using
2057 one of the instruction's memory alternatives. Returning false
2058 here will force it to use an input reload instead. */
2059 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2062 split_const (x
, &base
, &offset
);
2063 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2065 /* See whether we explicitly want these symbols in the pool. */
2066 if (mips_use_pcrel_pool_p
[(int) type
])
2069 /* The same optimization as for CONST_INT. */
2070 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2073 /* If MIPS16 constant pools live in the text section, they should
2074 not refer to anything that might need run-time relocation. */
2075 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2079 /* TLS symbols must be computed by mips_legitimize_move. */
2080 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
2086 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2087 constants when we're using a per-function constant pool. */
2090 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2091 const_rtx x ATTRIBUTE_UNUSED
)
2093 return !TARGET_MIPS16_PCREL_LOADS
;
2096 /* Return true if register REGNO is a valid base register for mode MODE.
2097 STRICT_P is true if REG_OK_STRICT is in effect. */
2100 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
2103 if (!HARD_REGISTER_NUM_P (regno
))
2107 regno
= reg_renumber
[regno
];
2110 /* These fake registers will be eliminated to either the stack or
2111 hard frame pointer, both of which are usually valid base registers.
2112 Reload deals with the cases where the eliminated form isn't valid. */
2113 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2116 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2117 values, nothing smaller. There are two problems here:
2119 (a) Instantiating virtual registers can introduce new uses of the
2120 stack pointer. If these virtual registers are valid addresses,
2121 the stack pointer should be too.
2123 (b) Most uses of the stack pointer are not made explicit until
2124 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2125 We don't know until that stage whether we'll be eliminating to the
2126 stack pointer (which needs the restriction) or the hard frame
2127 pointer (which doesn't).
2129 All in all, it seems more consistent to only enforce this restriction
2130 during and after reload. */
2131 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2132 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2134 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2137 /* Return true if X is a valid base register for mode MODE.
2138 STRICT_P is true if REG_OK_STRICT is in effect. */
2141 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2143 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2147 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2150 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2151 can address a value of mode MODE. */
2154 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2156 /* Check that X is a signed 16-bit number. */
2157 if (!const_arith_operand (x
, Pmode
))
2160 /* We may need to split multiword moves, so make sure that every word
2162 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2163 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2169 /* Return true if a LO_SUM can address a value of mode MODE when the
2170 LO_SUM symbol has type SYMBOL_TYPE. */
2173 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2175 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2177 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2180 /* Check that there is a known low-part relocation. */
2181 if (mips_lo_relocs
[symbol_type
] == NULL
)
2184 /* We may need to split multiword moves, so make sure that each word
2185 can be accessed without inducing a carry. This is mainly needed
2186 for o64, which has historically only guaranteed 64-bit alignment
2187 for 128-bit types. */
2188 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2189 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2195 /* Return true if X is a valid address for machine mode MODE. If it is,
2196 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2200 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2201 enum machine_mode mode
, bool strict_p
)
2203 switch (GET_CODE (x
))
2207 info
->type
= ADDRESS_REG
;
2209 info
->offset
= const0_rtx
;
2210 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2213 info
->type
= ADDRESS_REG
;
2214 info
->reg
= XEXP (x
, 0);
2215 info
->offset
= XEXP (x
, 1);
2216 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2217 && mips_valid_offset_p (info
->offset
, mode
));
2220 info
->type
= ADDRESS_LO_SUM
;
2221 info
->reg
= XEXP (x
, 0);
2222 info
->offset
= XEXP (x
, 1);
2223 /* We have to trust the creator of the LO_SUM to do something vaguely
2224 sane. Target-independent code that creates a LO_SUM should also
2225 create and verify the matching HIGH. Target-independent code that
2226 adds an offset to a LO_SUM must prove that the offset will not
2227 induce a carry. Failure to do either of these things would be
2228 a bug, and we are not required to check for it here. The MIPS
2229 backend itself should only create LO_SUMs for valid symbolic
2230 constants, with the high part being either a HIGH or a copy
2233 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2234 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2235 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2238 /* Small-integer addresses don't occur very often, but they
2239 are legitimate if $0 is a valid base register. */
2240 info
->type
= ADDRESS_CONST_INT
;
2241 return !TARGET_MIPS16
&& SMALL_INT (x
);
2246 info
->type
= ADDRESS_SYMBOLIC
;
2247 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2249 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2250 && !mips_split_p
[info
->symbol_type
]);
2257 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2260 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2262 struct mips_address_info addr
;
2264 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2267 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2270 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2272 struct mips_address_info addr
;
2274 return (mips_classify_address (&addr
, x
, mode
, false)
2275 && addr
.type
== ADDRESS_REG
2276 && addr
.reg
== stack_pointer_rtx
);
2279 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2280 address instruction. Note that such addresses are not considered
2281 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2282 is so restricted. */
2285 mips_lwxs_address_p (rtx addr
)
2288 && GET_CODE (addr
) == PLUS
2289 && REG_P (XEXP (addr
, 1)))
2291 rtx offset
= XEXP (addr
, 0);
2292 if (GET_CODE (offset
) == MULT
2293 && REG_P (XEXP (offset
, 0))
2294 && CONST_INT_P (XEXP (offset
, 1))
2295 && INTVAL (XEXP (offset
, 1)) == 4)
2301 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2302 indexed address instruction. Note that such addresses are
2303 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2304 sense, because their use is so restricted. */
2307 mips_lx_address_p (rtx addr
, enum machine_mode mode
)
2309 if (GET_CODE (addr
) != PLUS
2310 || !REG_P (XEXP (addr
, 0))
2311 || !REG_P (XEXP (addr
, 1)))
2313 if (ISA_HAS_LBX
&& mode
== QImode
)
2315 if (ISA_HAS_LHX
&& mode
== HImode
)
2317 if (ISA_HAS_LWX
&& mode
== SImode
)
2319 if (ISA_HAS_LDX
&& mode
== DImode
)
2324 /* Return true if a value at OFFSET bytes from base register BASE can be
2325 accessed using an unextended MIPS16 instruction. MODE is the mode of
2328 Usually the offset in an unextended instruction is a 5-bit field.
2329 The offset is unsigned and shifted left once for LH and SH, twice
2330 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2331 an 8-bit immediate field that's shifted left twice. */
2334 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2335 unsigned HOST_WIDE_INT offset
)
2337 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2339 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2340 return offset
< 256U * GET_MODE_SIZE (mode
);
2341 return offset
< 32U * GET_MODE_SIZE (mode
);
2346 /* Return the number of instructions needed to load or store a value
2347 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2348 length of one instruction. Return 0 if X isn't valid for MODE.
2349 Assume that multiword moves may need to be split into word moves
2350 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2354 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2356 struct mips_address_info addr
;
2359 /* BLKmode is used for single unaligned loads and stores and should
2360 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2361 meaningless, so we have to single it out as a special case one way
2363 if (mode
!= BLKmode
&& might_split_p
)
2364 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2368 if (mips_classify_address (&addr
, x
, mode
, false))
2373 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2374 UINTVAL (addr
.offset
)))
2378 case ADDRESS_LO_SUM
:
2379 return TARGET_MIPS16
? factor
* 2 : factor
;
2381 case ADDRESS_CONST_INT
:
2384 case ADDRESS_SYMBOLIC
:
2385 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2390 /* Return true if X fits within an unsigned field of BITS bits that is
2391 shifted left SHIFT bits before being used. */
2394 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2396 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2399 /* Return true if X fits within a signed field of BITS bits that is
2400 shifted left SHIFT bits before being used. */
2403 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2405 x
+= 1 << (bits
+ shift
- 1);
2406 return mips_unsigned_immediate_p (x
, bits
, shift
);
2409 /* Return true if X is legitimate for accessing values of mode MODE,
2410 if it is based on a MIPS16 register, and if the offset satisfies
2411 OFFSET_PREDICATE. */
2414 m16_based_address_p (rtx x
, enum machine_mode mode
,
2415 insn_operand_predicate_fn offset_predicate
)
2417 struct mips_address_info addr
;
2419 return (mips_classify_address (&addr
, x
, mode
, false)
2420 && addr
.type
== ADDRESS_REG
2421 && M16_REG_P (REGNO (addr
.reg
))
2422 && offset_predicate (addr
.offset
, mode
));
2425 /* Return true if X is a legitimate address that conforms to the requirements
2426 for a microMIPS LWSP or SWSP insn. */
2429 lwsp_swsp_address_p (rtx x
, enum machine_mode mode
)
2431 struct mips_address_info addr
;
2433 return (mips_classify_address (&addr
, x
, mode
, false)
2434 && addr
.type
== ADDRESS_REG
2435 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2436 && uw5_operand (addr
.offset
, mode
));
2439 /* Return true if X is a legitimate address with a 12-bit offset.
2440 MODE is the mode of the value being accessed. */
2443 umips_12bit_offset_address_p (rtx x
, enum machine_mode mode
)
2445 struct mips_address_info addr
;
2447 return (mips_classify_address (&addr
, x
, mode
, false)
2448 && addr
.type
== ADDRESS_REG
2449 && CONST_INT_P (addr
.offset
)
2450 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2453 /* Return the number of instructions needed to load constant X,
2454 assuming that BASE_INSN_LENGTH is the length of one instruction.
2455 Return 0 if X isn't a valid constant. */
2458 mips_const_insns (rtx x
)
2460 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2461 enum mips_symbol_type symbol_type
;
2464 switch (GET_CODE (x
))
2467 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2469 || !mips_split_p
[symbol_type
])
2472 /* This is simply an LUI for normal mode. It is an extended
2473 LI followed by an extended SLL for MIPS16. */
2474 return TARGET_MIPS16
? 4 : 1;
2478 /* Unsigned 8-bit constants can be loaded using an unextended
2479 LI instruction. Unsigned 16-bit constants can be loaded
2480 using an extended LI. Negative constants must be loaded
2481 using LI and then negated. */
2482 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2483 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2484 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2485 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2488 return mips_build_integer (codes
, INTVAL (x
));
2492 /* Allow zeros for normal mode, where we can use $0. */
2493 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2499 /* See if we can refer to X directly. */
2500 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2501 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2503 /* Otherwise try splitting the constant into a base and offset.
2504 If the offset is a 16-bit value, we can load the base address
2505 into a register and then use (D)ADDIU to add in the offset.
2506 If the offset is larger, we can load the base and offset
2507 into separate registers and add them together with (D)ADDU.
2508 However, the latter is only possible before reload; during
2509 and after reload, we must have the option of forcing the
2510 constant into the pool instead. */
2511 split_const (x
, &x
, &offset
);
2514 int n
= mips_const_insns (x
);
2517 if (SMALL_INT (offset
))
2519 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2520 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2527 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2535 /* X is a doubleword constant that can be handled by splitting it into
2536 two words and loading each word separately. Return the number of
2537 instructions required to do this, assuming that BASE_INSN_LENGTH
2538 is the length of one instruction. */
2541 mips_split_const_insns (rtx x
)
2543 unsigned int low
, high
;
2545 low
= mips_const_insns (mips_subword (x
, false));
2546 high
= mips_const_insns (mips_subword (x
, true));
2547 gcc_assert (low
> 0 && high
> 0);
2551 /* Return the number of instructions needed to implement INSN,
2552 given that it loads from or stores to MEM. Assume that
2553 BASE_INSN_LENGTH is the length of one instruction. */
2556 mips_load_store_insns (rtx mem
, rtx insn
)
2558 enum machine_mode mode
;
2562 gcc_assert (MEM_P (mem
));
2563 mode
= GET_MODE (mem
);
2565 /* Try to prove that INSN does not need to be split. */
2566 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2569 set
= single_set (insn
);
2570 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2571 might_split_p
= false;
2574 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2577 /* Return the number of instructions needed for an integer division,
2578 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2581 mips_idiv_insns (void)
2586 if (TARGET_CHECK_ZERO_DIV
)
2588 if (GENERATE_DIVIDE_TRAPS
)
2594 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2599 /* Emit a move from SRC to DEST. Assume that the move expanders can
2600 handle all moves if !can_create_pseudo_p (). The distinction is
2601 important because, unlike emit_move_insn, the move expanders know
2602 how to force Pmode objects into the constant pool even when the
2603 constant pool address is not itself legitimate. */
2606 mips_emit_move (rtx dest
, rtx src
)
2608 return (can_create_pseudo_p ()
2609 ? emit_move_insn (dest
, src
)
2610 : emit_move_insn_1 (dest
, src
));
2613 /* Emit a move from SRC to DEST, splitting compound moves into individual
2614 instructions. SPLIT_TYPE is the type of split to perform. */
2617 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
2619 if (mips_split_move_p (dest
, src
, split_type
))
2620 mips_split_move (dest
, src
, split_type
);
2622 mips_emit_move (dest
, src
);
2625 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2628 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2630 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2631 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2634 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2635 Return that new register. */
2638 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2642 reg
= gen_reg_rtx (mode
);
2643 mips_emit_unary (code
, reg
, op0
);
2647 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2650 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2652 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2653 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2656 /* Compute (CODE OP0 OP1) and store the result in a new register
2657 of mode MODE. Return that new register. */
2660 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2664 reg
= gen_reg_rtx (mode
);
2665 mips_emit_binary (code
, reg
, op0
, op1
);
2669 /* Copy VALUE to a register and return that register. If new pseudos
2670 are allowed, copy it into a new register, otherwise use DEST. */
2673 mips_force_temporary (rtx dest
, rtx value
)
2675 if (can_create_pseudo_p ())
2676 return force_reg (Pmode
, value
);
2679 mips_emit_move (dest
, value
);
2684 /* Emit a call sequence with call pattern PATTERN and return the call
2685 instruction itself (which is not necessarily the last instruction
2686 emitted). ORIG_ADDR is the original, unlegitimized address,
2687 ADDR is the legitimized form, and LAZY_P is true if the call
2688 address is lazily-bound. */
2691 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2695 insn
= emit_call_insn (pattern
);
2697 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2699 /* MIPS16 JALRs only take MIPS16 registers. If the target
2700 function requires $25 to be valid on entry, we must copy it
2701 there separately. The move instruction can be put in the
2702 call's delay slot. */
2703 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2704 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2705 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2709 /* Lazy-binding stubs require $gp to be valid on entry. */
2710 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2714 /* See the comment above load_call<mode> for details. */
2715 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2716 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2717 emit_insn (gen_update_got_version ());
2722 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2723 then add CONST_INT OFFSET to the result. */
2726 mips_unspec_address_offset (rtx base
, rtx offset
,
2727 enum mips_symbol_type symbol_type
)
2729 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2730 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2731 if (offset
!= const0_rtx
)
2732 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2733 return gen_rtx_CONST (Pmode
, base
);
2736 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2737 type SYMBOL_TYPE. */
2740 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2744 split_const (address
, &base
, &offset
);
2745 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2748 /* If OP is an UNSPEC address, return the address to which it refers,
2749 otherwise return OP itself. */
2752 mips_strip_unspec_address (rtx op
)
2756 split_const (op
, &base
, &offset
);
2757 if (UNSPEC_ADDRESS_P (base
))
2758 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2762 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2763 high part to BASE and return the result. Just return BASE otherwise.
2764 TEMP is as for mips_force_temporary.
2766 The returned expression can be used as the first operand to a LO_SUM. */
2769 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2770 enum mips_symbol_type symbol_type
)
2772 if (mips_split_p
[symbol_type
])
2774 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2775 addr
= mips_force_temporary (temp
, addr
);
2776 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2781 /* Return an instruction that copies $gp into register REG. We want
2782 GCC to treat the register's value as constant, so that its value
2783 can be rematerialized on demand. */
2786 gen_load_const_gp (rtx reg
)
2788 return PMODE_INSN (gen_load_const_gp
, (reg
));
2791 /* Return a pseudo register that contains the value of $gp throughout
2792 the current function. Such registers are needed by MIPS16 functions,
2793 for which $gp itself is not a valid base register or addition operand. */
2796 mips16_gp_pseudo_reg (void)
2798 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2802 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2804 push_topmost_sequence ();
2806 scan
= get_insns ();
2807 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2808 scan
= NEXT_INSN (scan
);
2810 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2811 insn
= emit_insn_after (insn
, scan
);
2812 INSN_LOCATION (insn
) = 0;
2814 pop_topmost_sequence ();
2817 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2820 /* Return a base register that holds pic_offset_table_rtx.
2821 TEMP, if nonnull, is a scratch Pmode base register. */
2824 mips_pic_base_register (rtx temp
)
2827 return pic_offset_table_rtx
;
2829 if (currently_expanding_to_rtl
)
2830 return mips16_gp_pseudo_reg ();
2832 if (can_create_pseudo_p ())
2833 temp
= gen_reg_rtx (Pmode
);
2836 /* The first post-reload split exposes all references to $gp
2837 (both uses and definitions). All references must remain
2838 explicit after that point.
2840 It is safe to introduce uses of $gp at any time, so for
2841 simplicity, we do that before the split too. */
2842 mips_emit_move (temp
, pic_offset_table_rtx
);
2844 emit_insn (gen_load_const_gp (temp
));
2848 /* Return the RHS of a load_call<mode> insn. */
2851 mips_unspec_call (rtx reg
, rtx symbol
)
2855 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
2856 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
2859 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2860 reference. Return NULL_RTX otherwise. */
2863 mips_strip_unspec_call (rtx src
)
2865 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
2866 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
2870 /* Create and return a GOT reference of type TYPE for address ADDR.
2871 TEMP, if nonnull, is a scratch Pmode base register. */
2874 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
2876 rtx base
, high
, lo_sum_symbol
;
2878 base
= mips_pic_base_register (temp
);
2880 /* If we used the temporary register to load $gp, we can't use
2881 it for the high part as well. */
2882 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
2885 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
2886 lo_sum_symbol
= mips_unspec_address (addr
, type
);
2888 if (type
== SYMBOL_GOTOFF_CALL
)
2889 return mips_unspec_call (high
, lo_sum_symbol
);
2891 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
2894 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2895 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2896 constant in that context and can be split into high and low parts.
2897 If so, and if LOW_OUT is nonnull, emit the high part and store the
2898 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2900 TEMP is as for mips_force_temporary and is used to load the high
2901 part into a register.
2903 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2904 a legitimize SET_SRC for an .md pattern, otherwise the low part
2905 is guaranteed to be a legitimate address for mode MODE. */
2908 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
2910 enum mips_symbol_context context
;
2911 enum mips_symbol_type symbol_type
;
2914 context
= (mode
== MAX_MACHINE_MODE
2915 ? SYMBOL_CONTEXT_LEA
2916 : SYMBOL_CONTEXT_MEM
);
2917 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
2919 addr
= XEXP (addr
, 0);
2920 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2921 && mips_symbol_insns (symbol_type
, mode
) > 0
2922 && mips_split_hi_p
[symbol_type
])
2925 switch (symbol_type
)
2927 case SYMBOL_GOT_PAGE_OFST
:
2928 /* The high part of a page/ofst pair is loaded from the GOT. */
2929 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
2940 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2941 && mips_symbol_insns (symbol_type
, mode
) > 0
2942 && mips_split_p
[symbol_type
])
2945 switch (symbol_type
)
2947 case SYMBOL_GOT_DISP
:
2948 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2949 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
2952 case SYMBOL_GP_RELATIVE
:
2953 high
= mips_pic_base_register (temp
);
2954 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2958 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2959 high
= mips_force_temporary (temp
, high
);
2960 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2969 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2970 mips_force_temporary; it is only needed when OFFSET is not a
2974 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2976 if (!SMALL_OPERAND (offset
))
2982 /* Load the full offset into a register so that we can use
2983 an unextended instruction for the address itself. */
2984 high
= GEN_INT (offset
);
2989 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2990 The addition inside the macro CONST_HIGH_PART may cause an
2991 overflow, so we need to force a sign-extension check. */
2992 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
2993 offset
= CONST_LOW_PART (offset
);
2995 high
= mips_force_temporary (temp
, high
);
2996 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
2998 return plus_constant (Pmode
, reg
, offset
);
3001 /* The __tls_get_attr symbol. */
3002 static GTY(()) rtx mips_tls_symbol
;
3004 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3005 the TLS symbol we are referencing and TYPE is the symbol type to use
3006 (either global dynamic or local dynamic). V0 is an RTX for the
3007 return value location. */
3010 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3014 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3016 if (!mips_tls_symbol
)
3017 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3019 loc
= mips_unspec_address (sym
, type
);
3023 emit_insn (gen_rtx_SET (Pmode
, a0
,
3024 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
3025 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3026 const0_rtx
, NULL_RTX
, false);
3027 RTL_CONST_CALL_P (insn
) = 1;
3028 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3029 insn
= get_insns ();
3036 /* Return a pseudo register that contains the current thread pointer. */
3039 mips_expand_thread_pointer (rtx tp
)
3045 mips_need_mips16_rdhwr_p
= true;
3046 fn
= mips16_stub_function ("__mips16_rdhwr");
3047 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
3048 if (!call_insn_operand (fn
, VOIDmode
))
3049 fn
= force_reg (Pmode
, fn
);
3050 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3053 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3060 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3063 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3064 its address. The return value will be both a valid address and a valid
3065 SET_SRC (either a REG or a LO_SUM). */
3068 mips_legitimize_tls_address (rtx loc
)
3070 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3071 enum tls_model model
;
3073 model
= SYMBOL_REF_TLS_MODEL (loc
);
3074 /* Only TARGET_ABICALLS code can have more than one module; other
3075 code must be be static and should not use a GOT. All TLS models
3076 reduce to local exec in this situation. */
3077 if (!TARGET_ABICALLS
)
3078 model
= TLS_MODEL_LOCAL_EXEC
;
3082 case TLS_MODEL_GLOBAL_DYNAMIC
:
3083 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3084 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3085 dest
= gen_reg_rtx (Pmode
);
3086 emit_libcall_block (insn
, dest
, v0
, loc
);
3089 case TLS_MODEL_LOCAL_DYNAMIC
:
3090 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3091 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3092 tmp1
= gen_reg_rtx (Pmode
);
3094 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3095 share the LDM result with other LD model accesses. */
3096 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3098 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3100 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3101 if (mips_split_p
[SYMBOL_DTPREL
])
3103 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3104 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3107 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3108 0, 0, OPTAB_DIRECT
);
3111 case TLS_MODEL_INITIAL_EXEC
:
3112 tp
= mips_get_tp ();
3113 tmp1
= gen_reg_rtx (Pmode
);
3114 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3115 if (Pmode
== DImode
)
3116 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3118 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3119 dest
= gen_reg_rtx (Pmode
);
3120 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3123 case TLS_MODEL_LOCAL_EXEC
:
3124 tmp1
= mips_get_tp ();
3125 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3126 if (mips_split_p
[SYMBOL_TPREL
])
3128 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3129 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3132 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3133 0, 0, OPTAB_DIRECT
);
3142 /* If X is not a valid address for mode MODE, force it into a register. */
3145 mips_force_address (rtx x
, enum machine_mode mode
)
3147 if (!mips_legitimate_address_p (mode
, x
, false))
3148 x
= force_reg (Pmode
, x
);
3152 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3153 be legitimized in a way that the generic machinery might not expect,
3154 return a new address, otherwise return NULL. MODE is the mode of
3155 the memory being accessed. */
3158 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3159 enum machine_mode mode
)
3162 HOST_WIDE_INT offset
;
3164 if (mips_tls_symbol_p (x
))
3165 return mips_legitimize_tls_address (x
);
3167 /* See if the address can split into a high part and a LO_SUM. */
3168 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3169 return mips_force_address (addr
, mode
);
3171 /* Handle BASE + OFFSET using mips_add_offset. */
3172 mips_split_plus (x
, &base
, &offset
);
3175 if (!mips_valid_base_register_p (base
, mode
, false))
3176 base
= copy_to_mode_reg (Pmode
, base
);
3177 addr
= mips_add_offset (NULL
, base
, offset
);
3178 return mips_force_address (addr
, mode
);
3184 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3187 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3189 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3190 enum machine_mode mode
;
3191 unsigned int i
, num_ops
;
3194 mode
= GET_MODE (dest
);
3195 num_ops
= mips_build_integer (codes
, value
);
3197 /* Apply each binary operation to X. Invariant: X is a legitimate
3198 source operand for a SET pattern. */
3199 x
= GEN_INT (codes
[0].value
);
3200 for (i
= 1; i
< num_ops
; i
++)
3202 if (!can_create_pseudo_p ())
3204 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
3208 x
= force_reg (mode
, x
);
3209 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3212 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
3215 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3216 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3220 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
3224 /* Split moves of big integers into smaller pieces. */
3225 if (splittable_const_int_operand (src
, mode
))
3227 mips_move_integer (dest
, dest
, INTVAL (src
));
3231 /* Split moves of symbolic constants into high/low pairs. */
3232 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3234 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3238 /* Generate the appropriate access sequences for TLS symbols. */
3239 if (mips_tls_symbol_p (src
))
3241 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3245 /* If we have (const (plus symbol offset)), and that expression cannot
3246 be forced into memory, load the symbol first and add in the offset.
3247 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3248 forced into memory, as it usually produces better code. */
3249 split_const (src
, &base
, &offset
);
3250 if (offset
!= const0_rtx
3251 && (targetm
.cannot_force_const_mem (mode
, src
)
3252 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3254 base
= mips_force_temporary (dest
, base
);
3255 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3259 src
= force_const_mem (mode
, src
);
3261 /* When using explicit relocs, constant pool references are sometimes
3262 not legitimate addresses. */
3263 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3264 mips_emit_move (dest
, src
);
3267 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3268 sequence that is valid. */
3271 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
3273 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3275 mips_emit_move (dest
, force_reg (mode
, src
));
3279 /* We need to deal with constants that would be legitimate
3280 immediate_operands but aren't legitimate move_operands. */
3281 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3283 mips_legitimize_const_move (mode
, dest
, src
);
3284 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3290 /* Return true if value X in context CONTEXT is a small-data address
3291 that can be rewritten as a LO_SUM. */
3294 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3296 enum mips_symbol_type symbol_type
;
3298 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3299 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3300 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3301 && symbol_type
== SYMBOL_GP_RELATIVE
);
3304 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3305 containing MEM, or null if none. */
3308 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3310 enum mips_symbol_context context
;
3312 /* Ignore things like "g" constraints in asms. We make no particular
3313 guarantee about which symbolic constants are acceptable as asm operands
3314 versus which must be forced into a GPR. */
3315 if (GET_CODE (*loc
) == LO_SUM
|| GET_CODE (*loc
) == ASM_OPERANDS
)
3320 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3325 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3326 return mips_rewrite_small_data_p (*loc
, context
);
3329 /* Return true if OP refers to small data symbols directly, not through
3333 mips_small_data_pattern_p (rtx op
)
3335 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3338 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3339 DATA is the containing MEM, or null if none. */
3342 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3344 enum mips_symbol_context context
;
3348 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3352 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3353 if (mips_rewrite_small_data_p (*loc
, context
))
3354 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3356 if (GET_CODE (*loc
) == LO_SUM
)
3362 /* Rewrite instruction pattern PATTERN so that it refers to small data
3363 using explicit relocations. */
3366 mips_rewrite_small_data (rtx pattern
)
3368 pattern
= copy_insn (pattern
);
3369 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3373 /* The cost of loading values from the constant pool. It should be
3374 larger than the cost of any constant we want to synthesize inline. */
3375 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3377 /* Return the cost of X when used as an operand to the MIPS16 instruction
3378 that implements CODE. Return -1 if there is no such instruction, or if
3379 X is not a valid immediate operand for it. */
3382 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3389 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3390 other shifts are extended. The shift patterns truncate the shift
3391 count to the right size, so there are no out-of-range values. */
3392 if (IN_RANGE (x
, 1, 8))
3394 return COSTS_N_INSNS (1);
3397 if (IN_RANGE (x
, -128, 127))
3399 if (SMALL_OPERAND (x
))
3400 return COSTS_N_INSNS (1);
3404 /* Like LE, but reject the always-true case. */
3408 /* We add 1 to the immediate and use SLT. */
3411 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3414 if (IN_RANGE (x
, 0, 255))
3416 if (SMALL_OPERAND_UNSIGNED (x
))
3417 return COSTS_N_INSNS (1);
3422 /* Equality comparisons with 0 are cheap. */
3432 /* Return true if there is a non-MIPS16 instruction that implements CODE
3433 and if that instruction accepts X as an immediate operand. */
3436 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3443 /* All shift counts are truncated to a valid constant. */
3448 /* Likewise rotates, if the target supports rotates at all. */
3454 /* These instructions take 16-bit unsigned immediates. */
3455 return SMALL_OPERAND_UNSIGNED (x
);
3460 /* These instructions take 16-bit signed immediates. */
3461 return SMALL_OPERAND (x
);
3467 /* The "immediate" forms of these instructions are really
3468 implemented as comparisons with register 0. */
3473 /* Likewise, meaning that the only valid immediate operand is 1. */
3477 /* We add 1 to the immediate and use SLT. */
3478 return SMALL_OPERAND (x
+ 1);
3481 /* Likewise SLTU, but reject the always-true case. */
3482 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3486 /* The bit position and size are immediate operands. */
3487 return ISA_HAS_EXT_INS
;
3490 /* By default assume that $0 can be used for 0. */
3495 /* Return the cost of binary operation X, given that the instruction
3496 sequence for a word-sized or smaller operation has cost SINGLE_COST
3497 and that the sequence of a double-word operation has cost DOUBLE_COST.
3498 If SPEED is true, optimize for speed otherwise optimize for size. */
3501 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3505 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3510 + set_src_cost (XEXP (x
, 0), speed
)
3511 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3514 /* Return the cost of floating-point multiplications of mode MODE. */
3517 mips_fp_mult_cost (enum machine_mode mode
)
3519 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3522 /* Return the cost of floating-point divisions of mode MODE. */
3525 mips_fp_div_cost (enum machine_mode mode
)
3527 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3530 /* Return the cost of sign-extending OP to mode MODE, not including the
3531 cost of OP itself. */
3534 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3537 /* Extended loads are as cheap as unextended ones. */
3540 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3541 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3544 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3545 /* We can use SEB or SEH. */
3546 return COSTS_N_INSNS (1);
3548 /* We need to use a shift left and a shift right. */
3549 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3552 /* Return the cost of zero-extending OP to mode MODE, not including the
3553 cost of OP itself. */
3556 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3559 /* Extended loads are as cheap as unextended ones. */
3562 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3563 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3564 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3566 if (GENERATE_MIPS16E
)
3567 /* We can use ZEB or ZEH. */
3568 return COSTS_N_INSNS (1);
3571 /* We need to load 0xff or 0xffff into a register and use AND. */
3572 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3574 /* We can use ANDI. */
3575 return COSTS_N_INSNS (1);
3578 /* Return the cost of moving between two registers of mode MODE,
3579 assuming that the move will be in pieces of at most UNITS bytes. */
3582 mips_set_reg_reg_piece_cost (enum machine_mode mode
, unsigned int units
)
3584 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3587 /* Return the cost of moving between two registers of mode MODE. */
3590 mips_set_reg_reg_cost (enum machine_mode mode
)
3592 switch (GET_MODE_CLASS (mode
))
3595 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3598 case MODE_COMPLEX_FLOAT
:
3599 case MODE_VECTOR_FLOAT
:
3600 if (TARGET_HARD_FLOAT
)
3601 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3605 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3609 /* Return the cost of an operand X that can be trucated for free.
3610 SPEED says whether we're optimizing for size or speed. */
3613 mips_truncated_op_cost (rtx x
, bool speed
)
3615 if (GET_CODE (x
) == TRUNCATE
)
3617 return set_src_cost (x
, speed
);
3620 /* Implement TARGET_RTX_COSTS. */
3623 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3624 int *total
, bool speed
)
3626 enum machine_mode mode
= GET_MODE (x
);
3627 bool float_mode_p
= FLOAT_MODE_P (mode
);
3631 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3632 appear in the instruction stream, and the cost of a comparison is
3633 really the cost of the branch or scc condition. At the time of
3634 writing, GCC only uses an explicit outer COMPARE code when optabs
3635 is testing whether a constant is expensive enough to force into a
3636 register. We want optabs to pass such constants through the MIPS
3637 expanders instead, so make all constants very cheap here. */
3638 if (outer_code
== COMPARE
)
3640 gcc_assert (CONSTANT_P (x
));
3648 /* Treat *clear_upper32-style ANDs as having zero cost in the
3649 second operand. The cost is entirely in the first operand.
3651 ??? This is needed because we would otherwise try to CSE
3652 the constant operand. Although that's the right thing for
3653 instructions that continue to be a register operation throughout
3654 compilation, it is disastrous for instructions that could
3655 later be converted into a memory operation. */
3657 && outer_code
== AND
3658 && UINTVAL (x
) == 0xffffffff)
3666 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3675 /* When not optimizing for size, we care more about the cost
3676 of hot code, and hot code is often in a loop. If a constant
3677 operand needs to be forced into a register, we will often be
3678 able to hoist the constant load out of the loop, so the load
3679 should not contribute to the cost. */
3680 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3692 if (force_to_mem_operand (x
, VOIDmode
))
3694 *total
= COSTS_N_INSNS (1);
3697 cost
= mips_const_insns (x
);
3700 /* If the constant is likely to be stored in a GPR, SETs of
3701 single-insn constants are as cheap as register sets; we
3702 never want to CSE them.
3704 Don't reduce the cost of storing a floating-point zero in
3705 FPRs. If we have a zero in an FPR for other reasons, we
3706 can get better cfg-cleanup and delayed-branch results by
3707 using it consistently, rather than using $0 sometimes and
3708 an FPR at other times. Also, moves between floating-point
3709 registers are sometimes cheaper than (D)MTC1 $0. */
3711 && outer_code
== SET
3712 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3714 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3715 want to CSE the constant itself. It is usually better to
3716 have N copies of the last operation in the sequence and one
3717 shared copy of the other operations. (Note that this is
3718 not true for MIPS16 code, where the final operation in the
3719 sequence is often an extended instruction.)
3721 Also, if we have a CONST_INT, we don't know whether it is
3722 for a word or doubleword operation, so we cannot rely on
3723 the result of mips_build_integer. */
3724 else if (!TARGET_MIPS16
3725 && (outer_code
== SET
|| mode
== VOIDmode
))
3727 *total
= COSTS_N_INSNS (cost
);
3730 /* The value will need to be fetched from the constant pool. */
3731 *total
= CONSTANT_POOL_COST
;
3735 /* If the address is legitimate, return the number of
3736 instructions it needs. */
3738 cost
= mips_address_insns (addr
, mode
, true);
3741 *total
= COSTS_N_INSNS (cost
+ 1);
3744 /* Check for a scaled indexed address. */
3745 if (mips_lwxs_address_p (addr
)
3746 || mips_lx_address_p (addr
, mode
))
3748 *total
= COSTS_N_INSNS (2);
3751 /* Otherwise use the default handling. */
3755 *total
= COSTS_N_INSNS (6);
3759 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3763 /* Check for a *clear_upper32 pattern and treat it like a zero
3764 extension. See the pattern's comment for details. */
3767 && CONST_INT_P (XEXP (x
, 1))
3768 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3770 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3771 + set_src_cost (XEXP (x
, 0), speed
));
3774 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
3776 rtx op
= XEXP (x
, 0);
3777 if (GET_CODE (op
) == ASHIFT
3778 && CONST_INT_P (XEXP (op
, 1))
3779 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
3781 *total
= COSTS_N_INSNS (1) + set_src_cost (XEXP (op
, 0), speed
);
3790 /* Double-word operations use two single-word operations. */
3791 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3800 if (CONSTANT_P (XEXP (x
, 1)))
3801 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3804 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3810 *total
= mips_cost
->fp_add
;
3812 *total
= COSTS_N_INSNS (4);
3816 /* Low-part immediates need an extended MIPS16 instruction. */
3817 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3818 + set_src_cost (XEXP (x
, 0), speed
));
3833 /* Branch comparisons have VOIDmode, so use the first operand's
3835 mode
= GET_MODE (XEXP (x
, 0));
3836 if (FLOAT_MODE_P (mode
))
3838 *total
= mips_cost
->fp_add
;
3841 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3847 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3848 && TARGET_FUSED_MADD
3849 && !HONOR_NANS (mode
)
3850 && !HONOR_SIGNED_ZEROS (mode
))
3852 /* See if we can use NMADD or NMSUB. See mips.md for the
3853 associated patterns. */
3854 rtx op0
= XEXP (x
, 0);
3855 rtx op1
= XEXP (x
, 1);
3856 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3858 *total
= (mips_fp_mult_cost (mode
)
3859 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
3860 + set_src_cost (XEXP (op0
, 1), speed
)
3861 + set_src_cost (op1
, speed
));
3864 if (GET_CODE (op1
) == MULT
)
3866 *total
= (mips_fp_mult_cost (mode
)
3867 + set_src_cost (op0
, speed
)
3868 + set_src_cost (XEXP (op1
, 0), speed
)
3869 + set_src_cost (XEXP (op1
, 1), speed
));
3878 /* If this is part of a MADD or MSUB, treat the PLUS as
3881 && TARGET_FUSED_MADD
3882 && GET_CODE (XEXP (x
, 0)) == MULT
)
3885 *total
= mips_cost
->fp_add
;
3889 /* Double-word operations require three single-word operations and
3890 an SLTU. The MIPS16 version then needs to move the result of
3891 the SLTU from $24 to a MIPS16 register. */
3892 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3893 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
3899 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3900 && TARGET_FUSED_MADD
3901 && !HONOR_NANS (mode
)
3902 && HONOR_SIGNED_ZEROS (mode
))
3904 /* See if we can use NMADD or NMSUB. See mips.md for the
3905 associated patterns. */
3906 rtx op
= XEXP (x
, 0);
3907 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3908 && GET_CODE (XEXP (op
, 0)) == MULT
)
3910 *total
= (mips_fp_mult_cost (mode
)
3911 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
3912 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
3913 + set_src_cost (XEXP (op
, 1), speed
));
3919 *total
= mips_cost
->fp_add
;
3921 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3926 *total
= mips_fp_mult_cost (mode
);
3927 else if (mode
== DImode
&& !TARGET_64BIT
)
3928 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3929 where the mulsidi3 always includes an MFHI and an MFLO. */
3931 ? mips_cost
->int_mult_si
* 3 + 6
3932 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
3934 *total
= COSTS_N_INSNS (ISA_HAS_MUL3
? 1 : 2);
3935 else if (mode
== DImode
)
3936 *total
= mips_cost
->int_mult_di
;
3938 *total
= mips_cost
->int_mult_si
;
3942 /* Check for a reciprocal. */
3945 && flag_unsafe_math_optimizations
3946 && XEXP (x
, 0) == CONST1_RTX (mode
))
3948 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
3949 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3950 division as being free. */
3951 *total
= set_src_cost (XEXP (x
, 1), speed
);
3953 *total
= (mips_fp_div_cost (mode
)
3954 + set_src_cost (XEXP (x
, 1), speed
));
3963 *total
= mips_fp_div_cost (mode
);
3972 /* It is our responsibility to make division by a power of 2
3973 as cheap as 2 register additions if we want the division
3974 expanders to be used for such operations; see the setting
3975 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3976 should always produce shorter code than using
3977 expand_sdiv2_pow2. */
3979 && CONST_INT_P (XEXP (x
, 1))
3980 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
3982 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
3985 *total
= COSTS_N_INSNS (mips_idiv_insns ());
3987 else if (mode
== DImode
)
3988 *total
= mips_cost
->int_div_di
;
3990 *total
= mips_cost
->int_div_si
;
3994 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
3998 if (outer_code
== SET
4000 && GET_MODE (XEXP (x
, 0)) == QImode
4001 && GET_CODE (XEXP (x
, 0)) == PLUS
)
4003 rtx plus
= XEXP (x
, 0);
4004 *total
= (COSTS_N_INSNS (1)
4005 + mips_truncated_op_cost (XEXP (plus
, 0), speed
)
4006 + mips_truncated_op_cost (XEXP (plus
, 1), speed
));
4009 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4013 case UNSIGNED_FLOAT
:
4016 case FLOAT_TRUNCATE
:
4017 *total
= mips_cost
->fp_add
;
4021 if (register_operand (SET_DEST (x
), VOIDmode
)
4022 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4024 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4034 /* Implement TARGET_ADDRESS_COST. */
4037 mips_address_cost (rtx addr
, enum machine_mode mode
,
4038 addr_space_t as ATTRIBUTE_UNUSED
,
4039 bool speed ATTRIBUTE_UNUSED
)
4041 return mips_address_insns (addr
, mode
, false);
4044 /* Information about a single instruction in a multi-instruction
4046 struct mips_multi_member
{
4047 /* True if this is a label, false if it is code. */
4050 /* The output_asm_insn format of the instruction. */
4053 /* The operands to the instruction. */
4054 rtx operands
[MAX_RECOG_OPERANDS
];
4056 typedef struct mips_multi_member mips_multi_member
;
4058 /* The instructions that make up the current multi-insn sequence. */
4059 static vec
<mips_multi_member
> mips_multi_members
;
4061 /* How many instructions (as opposed to labels) are in the current
4062 multi-insn sequence. */
4063 static unsigned int mips_multi_num_insns
;
4065 /* Start a new multi-insn sequence. */
4068 mips_multi_start (void)
4070 mips_multi_members
.truncate (0);
4071 mips_multi_num_insns
= 0;
4074 /* Add a new, uninitialized member to the current multi-insn sequence. */
4076 static struct mips_multi_member
*
4077 mips_multi_add (void)
4079 mips_multi_member empty
;
4080 return mips_multi_members
.safe_push (empty
);
4083 /* Add a normal insn with the given asm format to the current multi-insn
4084 sequence. The other arguments are a null-terminated list of operands. */
4087 mips_multi_add_insn (const char *format
, ...)
4089 struct mips_multi_member
*member
;
4094 member
= mips_multi_add ();
4095 member
->is_label_p
= false;
4096 member
->format
= format
;
4097 va_start (ap
, format
);
4099 while ((op
= va_arg (ap
, rtx
)))
4100 member
->operands
[i
++] = op
;
4102 mips_multi_num_insns
++;
4105 /* Add the given label definition to the current multi-insn sequence.
4106 The definition should include the colon. */
4109 mips_multi_add_label (const char *label
)
4111 struct mips_multi_member
*member
;
4113 member
= mips_multi_add ();
4114 member
->is_label_p
= true;
4115 member
->format
= label
;
4118 /* Return the index of the last member of the current multi-insn sequence. */
4121 mips_multi_last_index (void)
4123 return mips_multi_members
.length () - 1;
4126 /* Add a copy of an existing instruction to the current multi-insn
4127 sequence. I is the index of the instruction that should be copied. */
4130 mips_multi_copy_insn (unsigned int i
)
4132 struct mips_multi_member
*member
;
4134 member
= mips_multi_add ();
4135 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4136 gcc_assert (!member
->is_label_p
);
4139 /* Change the operand of an existing instruction in the current
4140 multi-insn sequence. I is the index of the instruction,
4141 OP is the index of the operand, and X is the new value. */
4144 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4146 mips_multi_members
[i
].operands
[op
] = x
;
4149 /* Write out the asm code for the current multi-insn sequence. */
4152 mips_multi_write (void)
4154 struct mips_multi_member
*member
;
4157 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4158 if (member
->is_label_p
)
4159 fprintf (asm_out_file
, "%s\n", member
->format
);
4161 output_asm_insn (member
->format
, member
->operands
);
4164 /* Return one word of double-word value OP, taking into account the fixed
4165 endianness of certain registers. HIGH_P is true to select the high part,
4166 false to select the low part. */
4169 mips_subword (rtx op
, bool high_p
)
4171 unsigned int byte
, offset
;
4172 enum machine_mode mode
;
4174 mode
= GET_MODE (op
);
4175 if (mode
== VOIDmode
)
4176 mode
= TARGET_64BIT
? TImode
: DImode
;
4178 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4179 byte
= UNITS_PER_WORD
;
4183 if (FP_REG_RTX_P (op
))
4185 /* Paired FPRs are always ordered little-endian. */
4186 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4187 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4191 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4193 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4196 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4197 SPLIT_TYPE is the condition under which moves should be split. */
4200 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4202 return ((split_type
!= SPLIT_FOR_SPEED
4203 || mips_tuning_info
.fast_mult_zero_zero_p
)
4204 && src
== const0_rtx
4206 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4207 && (ISA_HAS_DSP_MULT
4208 ? ACC_REG_P (REGNO (dest
))
4209 : MD_REG_P (REGNO (dest
))));
4212 /* Return true if a move from SRC to DEST should be split into two.
4213 SPLIT_TYPE describes the split condition. */
4216 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4218 /* Check whether the move can be done using some variant of MULT $0,$0. */
4219 if (mips_mult_move_p (dest
, src
, split_type
))
4222 /* FPR-to-FPR moves can be done in a single instruction, if they're
4224 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4225 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4228 /* Check for floating-point loads and stores. */
4229 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4231 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4233 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4237 /* Otherwise split all multiword moves. */
4238 return size
> UNITS_PER_WORD
;
4241 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4242 SPLIT_TYPE describes the split condition. */
4245 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4249 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4250 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4252 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4253 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4254 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4255 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4256 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4257 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4258 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4259 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4260 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4261 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4262 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4263 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4264 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4265 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4269 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4271 low_dest
= mips_subword (dest
, false);
4272 mips_emit_move (low_dest
, mips_subword (src
, false));
4274 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4276 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4278 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4280 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4282 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4284 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4288 /* The operation can be split into two normal moves. Decide in
4289 which order to do them. */
4290 low_dest
= mips_subword (dest
, false);
4291 if (REG_P (low_dest
)
4292 && reg_overlap_mentioned_p (low_dest
, src
))
4294 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4295 mips_emit_move (low_dest
, mips_subword (src
, false));
4299 mips_emit_move (low_dest
, mips_subword (src
, false));
4300 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4305 /* Return the split type for instruction INSN. */
4307 static enum mips_split_type
4308 mips_insn_split_type (rtx insn
)
4310 basic_block bb
= BLOCK_FOR_INSN (insn
);
4313 if (optimize_bb_for_speed_p (bb
))
4314 return SPLIT_FOR_SPEED
;
4316 return SPLIT_FOR_SIZE
;
4318 /* Once CFG information has been removed, we should trust the optimization
4319 decisions made by previous passes and only split where necessary. */
4320 return SPLIT_IF_NECESSARY
;
4323 /* Return true if a move from SRC to DEST in INSN should be split. */
4326 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
4328 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
4331 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4335 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
4337 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
4340 /* Return the appropriate instructions to move SRC into DEST. Assume
4341 that SRC is operand 1 and DEST is operand 0. */
4344 mips_output_move (rtx dest
, rtx src
)
4346 enum rtx_code dest_code
, src_code
;
4347 enum machine_mode mode
;
4348 enum mips_symbol_type symbol_type
;
4351 dest_code
= GET_CODE (dest
);
4352 src_code
= GET_CODE (src
);
4353 mode
= GET_MODE (dest
);
4354 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4356 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4359 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4360 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4362 if (dest_code
== REG
)
4364 if (GP_REG_P (REGNO (dest
)))
4365 return "move\t%0,%z1";
4367 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4369 if (ISA_HAS_DSP_MULT
)
4370 return "mult\t%q0,%.,%.";
4372 return "mult\t%.,%.";
4375 /* Moves to HI are handled by special .md insns. */
4376 if (REGNO (dest
) == LO_REGNUM
)
4379 if (DSP_ACC_REG_P (REGNO (dest
)))
4381 static char retval
[] = "mt__\t%z1,%q0";
4383 retval
[2] = reg_names
[REGNO (dest
)][4];
4384 retval
[3] = reg_names
[REGNO (dest
)][5];
4388 if (FP_REG_P (REGNO (dest
)))
4389 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4391 if (ALL_COP_REG_P (REGNO (dest
)))
4393 static char retval
[] = "dmtc_\t%z1,%0";
4395 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4396 return dbl_p
? retval
: retval
+ 1;
4399 if (dest_code
== MEM
)
4400 switch (GET_MODE_SIZE (mode
))
4402 case 1: return "sb\t%z1,%0";
4403 case 2: return "sh\t%z1,%0";
4404 case 4: return "sw\t%z1,%0";
4405 case 8: return "sd\t%z1,%0";
4408 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4410 if (src_code
== REG
)
4412 /* Moves from HI are handled by special .md insns. */
4413 if (REGNO (src
) == LO_REGNUM
)
4415 /* When generating VR4120 or VR4130 code, we use MACC and
4416 DMACC instead of MFLO. This avoids both the normal
4417 MIPS III HI/LO hazards and the errata related to
4420 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4424 if (DSP_ACC_REG_P (REGNO (src
)))
4426 static char retval
[] = "mf__\t%0,%q1";
4428 retval
[2] = reg_names
[REGNO (src
)][4];
4429 retval
[3] = reg_names
[REGNO (src
)][5];
4433 if (FP_REG_P (REGNO (src
)))
4434 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4436 if (ALL_COP_REG_P (REGNO (src
)))
4438 static char retval
[] = "dmfc_\t%0,%1";
4440 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4441 return dbl_p
? retval
: retval
+ 1;
4445 if (src_code
== MEM
)
4446 switch (GET_MODE_SIZE (mode
))
4448 case 1: return "lbu\t%0,%1";
4449 case 2: return "lhu\t%0,%1";
4450 case 4: return "lw\t%0,%1";
4451 case 8: return "ld\t%0,%1";
4454 if (src_code
== CONST_INT
)
4456 /* Don't use the X format for the operand itself, because that
4457 will give out-of-range numbers for 64-bit hosts and 32-bit
4460 return "li\t%0,%1\t\t\t# %X1";
4462 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4465 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4469 if (src_code
== HIGH
)
4470 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4472 if (CONST_GP_P (src
))
4473 return "move\t%0,%1";
4475 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4476 && mips_lo_relocs
[symbol_type
] != 0)
4478 /* A signed 16-bit constant formed by applying a relocation
4479 operator to a symbolic address. */
4480 gcc_assert (!mips_split_p
[symbol_type
]);
4481 return "li\t%0,%R1";
4484 if (symbolic_operand (src
, VOIDmode
))
4486 gcc_assert (TARGET_MIPS16
4487 ? TARGET_MIPS16_TEXT_LOADS
4488 : !TARGET_EXPLICIT_RELOCS
);
4489 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4492 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4494 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4496 if (GET_MODE (dest
) == V2SFmode
)
4497 return "mov.ps\t%0,%1";
4499 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4502 if (dest_code
== MEM
)
4503 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4505 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4507 if (src_code
== MEM
)
4508 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4510 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4512 static char retval
[] = "l_c_\t%0,%1";
4514 retval
[1] = (dbl_p
? 'd' : 'w');
4515 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4518 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4520 static char retval
[] = "s_c_\t%1,%0";
4522 retval
[1] = (dbl_p
? 'd' : 'w');
4523 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4529 /* Return true if CMP1 is a suitable second operand for integer ordering
4530 test CODE. See also the *sCC patterns in mips.md. */
4533 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4539 return reg_or_0_operand (cmp1
, VOIDmode
);
4543 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4547 return arith_operand (cmp1
, VOIDmode
);
4550 return sle_operand (cmp1
, VOIDmode
);
4553 return sleu_operand (cmp1
, VOIDmode
);
4560 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4561 integer ordering test *CODE, or if an equivalent combination can
4562 be formed by adjusting *CODE and *CMP1. When returning true, update
4563 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4567 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4568 enum machine_mode mode
)
4570 HOST_WIDE_INT plus_one
;
4572 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4575 if (CONST_INT_P (*cmp1
))
4579 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4580 if (INTVAL (*cmp1
) < plus_one
)
4583 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4589 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4593 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4604 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4605 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4606 is nonnull, it's OK to set TARGET to the inverse of the result and
4607 flip *INVERT_PTR instead. */
4610 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4611 rtx target
, rtx cmp0
, rtx cmp1
)
4613 enum machine_mode mode
;
4615 /* First see if there is a MIPS instruction that can do this operation.
4616 If not, try doing the same for the inverse operation. If that also
4617 fails, force CMP1 into a register and try again. */
4618 mode
= GET_MODE (cmp0
);
4619 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4620 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4623 enum rtx_code inv_code
= reverse_condition (code
);
4624 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4626 cmp1
= force_reg (mode
, cmp1
);
4627 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4629 else if (invert_ptr
== 0)
4633 inv_target
= mips_force_binary (GET_MODE (target
),
4634 inv_code
, cmp0
, cmp1
);
4635 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4639 *invert_ptr
= !*invert_ptr
;
4640 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4645 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4646 The register will have the same mode as CMP0. */
4649 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4651 if (cmp1
== const0_rtx
)
4654 if (uns_arith_operand (cmp1
, VOIDmode
))
4655 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4656 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4658 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4659 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4662 /* Convert *CODE into a code that can be used in a floating-point
4663 scc instruction (C.cond.fmt). Return true if the values of
4664 the condition code registers will be inverted, with 0 indicating
4665 that the condition holds. */
4668 mips_reversed_fp_cond (enum rtx_code
*code
)
4675 *code
= reverse_condition_maybe_unordered (*code
);
4683 /* Allocate a floating-point condition-code register of mode MODE.
4685 These condition code registers are used for certain kinds
4686 of compound operation, such as compare and branches, vconds,
4687 and built-in functions. At expand time, their use is entirely
4688 controlled by MIPS-specific code and is entirely internal
4689 to these compound operations.
4691 We could (and did in the past) expose condition-code values
4692 as pseudo registers and leave the register allocator to pick
4693 appropriate registers. The problem is that it is not practically
4694 possible for the rtl optimizers to guarantee that no spills will
4695 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4696 therefore need spill and reload sequences to handle the worst case.
4698 Although such sequences do exist, they are very expensive and are
4699 not something we'd want to use. This is especially true of CCV2 and
4700 CCV4, where all the shuffling would greatly outweigh whatever benefit
4701 the vectorization itself provides.
4703 The main benefit of having more than one condition-code register
4704 is to allow the pipelining of operations, especially those involving
4705 comparisons and conditional moves. We don't really expect the
4706 registers to be live for long periods, and certainly never want
4707 them to be live across calls.
4709 Also, there should be no penalty attached to using all the available
4710 registers. They are simply bits in the same underlying FPU control
4713 We therefore expose the hardware registers from the outset and use
4714 a simple round-robin allocation scheme. */
4717 mips_allocate_fcc (enum machine_mode mode
)
4719 unsigned int regno
, count
;
4721 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
4725 else if (mode
== CCV2mode
)
4727 else if (mode
== CCV4mode
)
4732 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
4733 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
4734 cfun
->machine
->next_fcc
= 0;
4735 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
4736 cfun
->machine
->next_fcc
+= count
;
4737 return gen_rtx_REG (mode
, regno
);
4740 /* Convert a comparison into something that can be used in a branch or
4741 conditional move. On entry, *OP0 and *OP1 are the values being
4742 compared and *CODE is the code used to compare them.
4744 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4745 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4746 otherwise any standard branch condition can be used. The standard branch
4749 - EQ or NE between two registers.
4750 - any comparison between a register and zero. */
4753 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4758 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4760 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4762 else if (*code
== EQ
|| *code
== NE
)
4766 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4770 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4774 /* The comparison needs a separate scc instruction. Store the
4775 result of the scc in *OP0 and compare it against zero. */
4776 bool invert
= false;
4777 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4778 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4779 *code
= (invert
? EQ
: NE
);
4783 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4785 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4786 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4792 enum rtx_code cmp_code
;
4794 /* Floating-point tests use a separate C.cond.fmt comparison to
4795 set a condition code register. The branch or conditional move
4796 will then compare that register against zero.
4798 Set CMP_CODE to the code of the comparison instruction and
4799 *CODE to the code that the branch or move should use. */
4801 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4803 ? mips_allocate_fcc (CCmode
)
4804 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4806 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4810 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4811 and OPERAND[3]. Store the result in OPERANDS[0].
4813 On 64-bit targets, the mode of the comparison and target will always be
4814 SImode, thus possibly narrower than that of the comparison's operands. */
4817 mips_expand_scc (rtx operands
[])
4819 rtx target
= operands
[0];
4820 enum rtx_code code
= GET_CODE (operands
[1]);
4821 rtx op0
= operands
[2];
4822 rtx op1
= operands
[3];
4824 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
4826 if (code
== EQ
|| code
== NE
)
4829 && reg_imm10_operand (op1
, GET_MODE (op1
)))
4830 mips_emit_binary (code
, target
, op0
, op1
);
4833 rtx zie
= mips_zero_if_equal (op0
, op1
);
4834 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4838 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
4841 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4842 CODE and jump to OPERANDS[3] if the condition holds. */
4845 mips_expand_conditional_branch (rtx
*operands
)
4847 enum rtx_code code
= GET_CODE (operands
[0]);
4848 rtx op0
= operands
[1];
4849 rtx op1
= operands
[2];
4852 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
4853 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
4854 emit_jump_insn (gen_condjump (condition
, operands
[3]));
4859 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4860 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4863 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
4864 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
4869 reversed_p
= mips_reversed_fp_cond (&cond
);
4870 cmp_result
= mips_allocate_fcc (CCV2mode
);
4871 emit_insn (gen_scc_ps (cmp_result
,
4872 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
4874 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
4877 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
4881 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4882 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4885 mips_expand_conditional_move (rtx
*operands
)
4888 enum rtx_code code
= GET_CODE (operands
[1]);
4889 rtx op0
= XEXP (operands
[1], 0);
4890 rtx op1
= XEXP (operands
[1], 1);
4892 mips_emit_compare (&code
, &op0
, &op1
, true);
4893 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
4894 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
4895 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
4896 operands
[2], operands
[3])));
4899 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4902 mips_expand_conditional_trap (rtx comparison
)
4905 enum machine_mode mode
;
4908 /* MIPS conditional trap instructions don't have GT or LE flavors,
4909 so we must swap the operands and convert to LT and GE respectively. */
4910 code
= GET_CODE (comparison
);
4917 code
= swap_condition (code
);
4918 op0
= XEXP (comparison
, 1);
4919 op1
= XEXP (comparison
, 0);
4923 op0
= XEXP (comparison
, 0);
4924 op1
= XEXP (comparison
, 1);
4928 mode
= GET_MODE (XEXP (comparison
, 0));
4929 op0
= force_reg (mode
, op0
);
4930 if (!arith_operand (op1
, mode
))
4931 op1
= force_reg (mode
, op1
);
4933 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
4934 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
4938 /* Initialize *CUM for a call to a function of type FNTYPE. */
4941 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
4943 memset (cum
, 0, sizeof (*cum
));
4944 cum
->prototype
= (fntype
&& prototype_p (fntype
));
4945 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
4948 /* Fill INFO with information about a single argument. CUM is the
4949 cumulative state for earlier arguments. MODE is the mode of this
4950 argument and TYPE is its type (if known). NAMED is true if this
4951 is a named (fixed) argument rather than a variable one. */
4954 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
4955 enum machine_mode mode
, const_tree type
, bool named
)
4957 bool doubleword_aligned_p
;
4958 unsigned int num_bytes
, num_words
, max_regs
;
4960 /* Work out the size of the argument. */
4961 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4962 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4964 /* Decide whether it should go in a floating-point register, assuming
4965 one is free. Later code checks for availability.
4967 The checks against UNITS_PER_FPVALUE handle the soft-float and
4968 single-float cases. */
4972 /* The EABI conventions have traditionally been defined in terms
4973 of TYPE_MODE, regardless of the actual type. */
4974 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4975 || mode
== V2SFmode
)
4976 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4981 /* Only leading floating-point scalars are passed in
4982 floating-point registers. We also handle vector floats the same
4983 say, which is OK because they are not covered by the standard ABI. */
4984 info
->fpr_p
= (!cum
->gp_reg_found
4985 && cum
->arg_number
< 2
4987 || SCALAR_FLOAT_TYPE_P (type
)
4988 || VECTOR_FLOAT_TYPE_P (type
))
4989 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4990 || mode
== V2SFmode
)
4991 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4996 /* Scalar, complex and vector floating-point types are passed in
4997 floating-point registers, as long as this is a named rather
4998 than a variable argument. */
4999 info
->fpr_p
= (named
5000 && (type
== 0 || FLOAT_TYPE_P (type
))
5001 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5002 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5003 || mode
== V2SFmode
)
5004 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5006 /* ??? According to the ABI documentation, the real and imaginary
5007 parts of complex floats should be passed in individual registers.
5008 The real and imaginary parts of stack arguments are supposed
5009 to be contiguous and there should be an extra word of padding
5012 This has two problems. First, it makes it impossible to use a
5013 single "void *" va_list type, since register and stack arguments
5014 are passed differently. (At the time of writing, MIPSpro cannot
5015 handle complex float varargs correctly.) Second, it's unclear
5016 what should happen when there is only one register free.
5018 For now, we assume that named complex floats should go into FPRs
5019 if there are two FPRs free, otherwise they should be passed in the
5020 same way as a struct containing two floats. */
5022 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5023 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5025 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5026 info
->fpr_p
= false;
5036 /* See whether the argument has doubleword alignment. */
5037 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5040 /* Set REG_OFFSET to the register count we're interested in.
5041 The EABI allocates the floating-point registers separately,
5042 but the other ABIs allocate them like integer registers. */
5043 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5047 /* Advance to an even register if the argument is doubleword-aligned. */
5048 if (doubleword_aligned_p
)
5049 info
->reg_offset
+= info
->reg_offset
& 1;
5051 /* Work out the offset of a stack argument. */
5052 info
->stack_offset
= cum
->stack_words
;
5053 if (doubleword_aligned_p
)
5054 info
->stack_offset
+= info
->stack_offset
& 1;
5056 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5058 /* Partition the argument between registers and stack. */
5059 info
->reg_words
= MIN (num_words
, max_regs
);
5060 info
->stack_words
= num_words
- info
->reg_words
;
5063 /* INFO describes a register argument that has the normal format for the
5064 argument's mode. Return the register it uses, assuming that FPRs are
5065 available if HARD_FLOAT_P. */
5068 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5070 if (!info
->fpr_p
|| !hard_float_p
)
5071 return GP_ARG_FIRST
+ info
->reg_offset
;
5072 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5073 /* In o32, the second argument is always passed in $f14
5074 for TARGET_DOUBLE_FLOAT, regardless of whether the
5075 first argument was a word or doubleword. */
5076 return FP_ARG_FIRST
+ 2;
5078 return FP_ARG_FIRST
+ info
->reg_offset
;
5081 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5084 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5086 return !TARGET_OLDABI
;
5089 /* Implement TARGET_FUNCTION_ARG. */
5092 mips_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
5093 const_tree type
, bool named
)
5095 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5096 struct mips_arg_info info
;
5098 /* We will be called with a mode of VOIDmode after the last argument
5099 has been seen. Whatever we return will be passed to the call expander.
5100 If we need a MIPS16 fp_code, return a REG with the code stored as
5102 if (mode
== VOIDmode
)
5104 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5105 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
5110 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5112 /* Return straight away if the whole argument is passed on the stack. */
5113 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5116 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5117 contains a double in its entirety, then that 64-bit chunk is passed
5118 in a floating-point register. */
5120 && TARGET_HARD_FLOAT
5123 && TREE_CODE (type
) == RECORD_TYPE
5124 && TYPE_SIZE_UNIT (type
)
5125 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
5129 /* First check to see if there is any such field. */
5130 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5131 if (TREE_CODE (field
) == FIELD_DECL
5132 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5133 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5134 && host_integerp (bit_position (field
), 0)
5135 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5140 /* Now handle the special case by returning a PARALLEL
5141 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5142 chunks are passed in registers. */
5144 HOST_WIDE_INT bitpos
;
5147 /* assign_parms checks the mode of ENTRY_PARM, so we must
5148 use the actual mode here. */
5149 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5152 field
= TYPE_FIELDS (type
);
5153 for (i
= 0; i
< info
.reg_words
; i
++)
5157 for (; field
; field
= DECL_CHAIN (field
))
5158 if (TREE_CODE (field
) == FIELD_DECL
5159 && int_bit_position (field
) >= bitpos
)
5163 && int_bit_position (field
) == bitpos
5164 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5165 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5166 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5168 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
5171 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5172 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5174 bitpos
+= BITS_PER_WORD
;
5180 /* Handle the n32/n64 conventions for passing complex floating-point
5181 arguments in FPR pairs. The real part goes in the lower register
5182 and the imaginary part goes in the upper register. */
5185 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5188 enum machine_mode inner
;
5191 inner
= GET_MODE_INNER (mode
);
5192 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
5193 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
5195 /* Real part in registers, imaginary part on stack. */
5196 gcc_assert (info
.stack_words
== info
.reg_words
);
5197 return gen_rtx_REG (inner
, regno
);
5201 gcc_assert (info
.stack_words
== 0);
5202 real
= gen_rtx_EXPR_LIST (VOIDmode
,
5203 gen_rtx_REG (inner
, regno
),
5205 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
5207 regno
+ info
.reg_words
/ 2),
5208 GEN_INT (GET_MODE_SIZE (inner
)));
5209 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
5213 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
5216 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5219 mips_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
5220 const_tree type
, bool named
)
5222 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5223 struct mips_arg_info info
;
5225 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5228 cum
->gp_reg_found
= true;
5230 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5231 an explanation of what this code does. It assumes that we're using
5232 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5234 if (cum
->arg_number
< 2 && info
.fpr_p
)
5235 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5237 /* Advance the register count. This has the effect of setting
5238 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5239 argument required us to skip the final GPR and pass the whole
5240 argument on the stack. */
5241 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5242 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5243 else if (info
.reg_words
> 0)
5244 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5246 /* Advance the stack word count. */
5247 if (info
.stack_words
> 0)
5248 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5253 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5256 mips_arg_partial_bytes (cumulative_args_t cum
,
5257 enum machine_mode mode
, tree type
, bool named
)
5259 struct mips_arg_info info
;
5261 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5262 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5265 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5266 least PARM_BOUNDARY bits of alignment, but will be given anything up
5267 to STACK_BOUNDARY bits if the type requires it. */
5270 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5272 unsigned int alignment
;
5274 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5275 if (alignment
< PARM_BOUNDARY
)
5276 alignment
= PARM_BOUNDARY
;
5277 if (alignment
> STACK_BOUNDARY
)
5278 alignment
= STACK_BOUNDARY
;
5282 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5283 upward rather than downward. In other words, return true if the
5284 first byte of the stack slot has useful data, false if the last
5288 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
5290 /* On little-endian targets, the first byte of every stack argument
5291 is passed in the first byte of the stack slot. */
5292 if (!BYTES_BIG_ENDIAN
)
5295 /* Otherwise, integral types are padded downward: the last byte of a
5296 stack argument is passed in the last byte of the stack slot. */
5298 ? (INTEGRAL_TYPE_P (type
)
5299 || POINTER_TYPE_P (type
)
5300 || FIXED_POINT_TYPE_P (type
))
5301 : (SCALAR_INT_MODE_P (mode
)
5302 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5305 /* Big-endian o64 pads floating-point arguments downward. */
5306 if (mips_abi
== ABI_O64
)
5307 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5310 /* Other types are padded upward for o32, o64, n32 and n64. */
5311 if (mips_abi
!= ABI_EABI
)
5314 /* Arguments smaller than a stack slot are padded downward. */
5315 if (mode
!= BLKmode
)
5316 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5318 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5321 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5322 if the least significant byte of the register has useful data. Return
5323 the opposite if the most significant byte does. */
5326 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
5328 /* No shifting is required for floating-point arguments. */
5329 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5330 return !BYTES_BIG_ENDIAN
;
5332 /* Otherwise, apply the same padding to register arguments as we do
5333 to stack arguments. */
5334 return mips_pad_arg_upward (mode
, type
);
5337 /* Return nonzero when an argument must be passed by reference. */
5340 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5341 enum machine_mode mode
, const_tree type
,
5342 bool named ATTRIBUTE_UNUSED
)
5344 if (mips_abi
== ABI_EABI
)
5348 /* ??? How should SCmode be handled? */
5349 if (mode
== DImode
|| mode
== DFmode
5350 || mode
== DQmode
|| mode
== UDQmode
5351 || mode
== DAmode
|| mode
== UDAmode
)
5354 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5355 return size
== -1 || size
> UNITS_PER_WORD
;
5359 /* If we have a variable-sized parameter, we have no choice. */
5360 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5364 /* Implement TARGET_CALLEE_COPIES. */
5367 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5368 enum machine_mode mode ATTRIBUTE_UNUSED
,
5369 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5371 return mips_abi
== ABI_EABI
&& named
;
5374 /* See whether VALTYPE is a record whose fields should be returned in
5375 floating-point registers. If so, return the number of fields and
5376 list them in FIELDS (which should have two elements). Return 0
5379 For n32 & n64, a structure with one or two fields is returned in
5380 floating-point registers as long as every field has a floating-point
5384 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5392 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5396 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5398 if (TREE_CODE (field
) != FIELD_DECL
)
5401 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5407 fields
[i
++] = field
;
5412 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5413 a value in the most significant part of $2/$3 if:
5415 - the target is big-endian;
5417 - the value has a structure or union type (we generalize this to
5418 cover aggregates from other languages too); and
5420 - the structure is not returned in floating-point registers. */
5423 mips_return_in_msb (const_tree valtype
)
5427 return (TARGET_NEWABI
5428 && TARGET_BIG_ENDIAN
5429 && AGGREGATE_TYPE_P (valtype
)
5430 && mips_fpr_return_fields (valtype
, fields
) == 0);
5433 /* Return true if the function return value MODE will get returned in a
5434 floating-point register. */
5437 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5439 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5441 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5442 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5445 /* Return the representation of an FPR return register when the
5446 value being returned in FP_RETURN has mode VALUE_MODE and the
5447 return type itself has mode TYPE_MODE. On NewABI targets,
5448 the two modes may be different for structures like:
5450 struct __attribute__((packed)) foo { float f; }
5452 where we return the SFmode value of "f" in FP_RETURN, but where
5453 the structure itself has mode BLKmode. */
5456 mips_return_fpr_single (enum machine_mode type_mode
,
5457 enum machine_mode value_mode
)
5461 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5462 if (type_mode
!= value_mode
)
5464 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5465 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5470 /* Return a composite value in a pair of floating-point registers.
5471 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5472 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5475 For n32 & n64, $f0 always holds the first value and $f2 the second.
5476 Otherwise the values are packed together as closely as possible. */
5479 mips_return_fpr_pair (enum machine_mode mode
,
5480 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5481 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5485 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5486 return gen_rtx_PARALLEL
5489 gen_rtx_EXPR_LIST (VOIDmode
,
5490 gen_rtx_REG (mode1
, FP_RETURN
),
5492 gen_rtx_EXPR_LIST (VOIDmode
,
5493 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5494 GEN_INT (offset2
))));
5498 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5499 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5500 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5503 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5504 enum machine_mode mode
)
5512 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5513 func
= fn_decl_or_type
;
5517 mode
= TYPE_MODE (valtype
);
5518 unsigned_p
= TYPE_UNSIGNED (valtype
);
5520 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5521 return values, promote the mode here too. */
5522 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5524 /* Handle structures whose fields are returned in $f0/$f2. */
5525 switch (mips_fpr_return_fields (valtype
, fields
))
5528 return mips_return_fpr_single (mode
,
5529 TYPE_MODE (TREE_TYPE (fields
[0])));
5532 return mips_return_fpr_pair (mode
,
5533 TYPE_MODE (TREE_TYPE (fields
[0])),
5534 int_byte_position (fields
[0]),
5535 TYPE_MODE (TREE_TYPE (fields
[1])),
5536 int_byte_position (fields
[1]));
5539 /* If a value is passed in the most significant part of a register, see
5540 whether we have to round the mode up to a whole number of words. */
5541 if (mips_return_in_msb (valtype
))
5543 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5544 if (size
% UNITS_PER_WORD
!= 0)
5546 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5547 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5551 /* For EABI, the class of return register depends entirely on MODE.
5552 For example, "struct { some_type x; }" and "union { some_type x; }"
5553 are returned in the same way as a bare "some_type" would be.
5554 Other ABIs only use FPRs for scalar, complex or vector types. */
5555 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5556 return gen_rtx_REG (mode
, GP_RETURN
);
5561 /* Handle long doubles for n32 & n64. */
5563 return mips_return_fpr_pair (mode
,
5565 DImode
, GET_MODE_SIZE (mode
) / 2);
5567 if (mips_return_mode_in_fpr_p (mode
))
5569 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5570 return mips_return_fpr_pair (mode
,
5571 GET_MODE_INNER (mode
), 0,
5572 GET_MODE_INNER (mode
),
5573 GET_MODE_SIZE (mode
) / 2);
5575 return gen_rtx_REG (mode
, FP_RETURN
);
5579 return gen_rtx_REG (mode
, GP_RETURN
);
5582 /* Implement TARGET_FUNCTION_VALUE. */
5585 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5586 bool outgoing ATTRIBUTE_UNUSED
)
5588 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5591 /* Implement TARGET_LIBCALL_VALUE. */
5594 mips_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5596 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5599 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5601 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5602 Currently, R2 and F0 are only implemented here (C has no complex type). */
5605 mips_function_value_regno_p (const unsigned int regno
)
5607 if (regno
== GP_RETURN
5608 || regno
== FP_RETURN
5609 || (LONG_DOUBLE_TYPE_SIZE
== 128
5610 && FP_RETURN
!= GP_RETURN
5611 && regno
== FP_RETURN
+ 2))
5617 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5618 all BLKmode objects are returned in memory. Under the n32, n64
5619 and embedded ABIs, small structures are returned in a register.
5620 Objects with varying size must still be returned in memory, of
5624 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5626 return (TARGET_OLDABI
5627 ? TYPE_MODE (type
) == BLKmode
5628 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5631 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5634 mips_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
5635 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5638 CUMULATIVE_ARGS local_cum
;
5639 int gp_saved
, fp_saved
;
5641 /* The caller has advanced CUM up to, but not beyond, the last named
5642 argument. Advance a local copy of CUM past the last "real" named
5643 argument, to find out how many registers are left over. */
5644 local_cum
= *get_cumulative_args (cum
);
5645 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5648 /* Found out how many registers we need to save. */
5649 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5650 fp_saved
= (EABI_FLOAT_VARARGS_P
5651 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5660 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
5661 REG_PARM_STACK_SPACE (cfun
->decl
)
5662 - gp_saved
* UNITS_PER_WORD
);
5663 mem
= gen_frame_mem (BLKmode
, ptr
);
5664 set_mem_alias_set (mem
, get_varargs_alias_set ());
5666 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5671 /* We can't use move_block_from_reg, because it will use
5673 enum machine_mode mode
;
5676 /* Set OFF to the offset from virtual_incoming_args_rtx of
5677 the first float register. The FP save area lies below
5678 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5679 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5680 off
-= fp_saved
* UNITS_PER_FPREG
;
5682 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5684 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5685 i
+= MAX_FPRS_PER_FMT
)
5689 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
5690 mem
= gen_frame_mem (mode
, ptr
);
5691 set_mem_alias_set (mem
, get_varargs_alias_set ());
5692 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5693 off
+= UNITS_PER_HWFPVALUE
;
5697 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5698 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5699 + fp_saved
* UNITS_PER_FPREG
);
5702 /* Implement TARGET_BUILTIN_VA_LIST. */
5705 mips_build_builtin_va_list (void)
5707 if (EABI_FLOAT_VARARGS_P
)
5709 /* We keep 3 pointers, and two offsets.
5711 Two pointers are to the overflow area, which starts at the CFA.
5712 One of these is constant, for addressing into the GPR save area
5713 below it. The other is advanced up the stack through the
5716 The third pointer is to the bottom of the GPR save area.
5717 Since the FPR save area is just below it, we can address
5718 FPR slots off this pointer.
5720 We also keep two one-byte offsets, which are to be subtracted
5721 from the constant pointers to yield addresses in the GPR and
5722 FPR save areas. These are downcounted as float or non-float
5723 arguments are used, and when they get to zero, the argument
5724 must be obtained from the overflow region. */
5725 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5728 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5730 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5731 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5733 f_gtop
= build_decl (BUILTINS_LOCATION
,
5734 FIELD_DECL
, get_identifier ("__gpr_top"),
5736 f_ftop
= build_decl (BUILTINS_LOCATION
,
5737 FIELD_DECL
, get_identifier ("__fpr_top"),
5739 f_goff
= build_decl (BUILTINS_LOCATION
,
5740 FIELD_DECL
, get_identifier ("__gpr_offset"),
5741 unsigned_char_type_node
);
5742 f_foff
= build_decl (BUILTINS_LOCATION
,
5743 FIELD_DECL
, get_identifier ("__fpr_offset"),
5744 unsigned_char_type_node
);
5745 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5746 warn on every user file. */
5747 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5748 array
= build_array_type (unsigned_char_type_node
,
5749 build_index_type (index
));
5750 f_res
= build_decl (BUILTINS_LOCATION
,
5751 FIELD_DECL
, get_identifier ("__reserved"), array
);
5753 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5754 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5755 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5756 DECL_FIELD_CONTEXT (f_goff
) = record
;
5757 DECL_FIELD_CONTEXT (f_foff
) = record
;
5758 DECL_FIELD_CONTEXT (f_res
) = record
;
5760 TYPE_FIELDS (record
) = f_ovfl
;
5761 DECL_CHAIN (f_ovfl
) = f_gtop
;
5762 DECL_CHAIN (f_gtop
) = f_ftop
;
5763 DECL_CHAIN (f_ftop
) = f_goff
;
5764 DECL_CHAIN (f_goff
) = f_foff
;
5765 DECL_CHAIN (f_foff
) = f_res
;
5767 layout_type (record
);
5771 /* Otherwise, we use 'void *'. */
5772 return ptr_type_node
;
5775 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5778 mips_va_start (tree valist
, rtx nextarg
)
5780 if (EABI_FLOAT_VARARGS_P
)
5782 const CUMULATIVE_ARGS
*cum
;
5783 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5784 tree ovfl
, gtop
, ftop
, goff
, foff
;
5786 int gpr_save_area_size
;
5787 int fpr_save_area_size
;
5790 cum
= &crtl
->args
.info
;
5792 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5794 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5796 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5797 f_gtop
= DECL_CHAIN (f_ovfl
);
5798 f_ftop
= DECL_CHAIN (f_gtop
);
5799 f_goff
= DECL_CHAIN (f_ftop
);
5800 f_foff
= DECL_CHAIN (f_goff
);
5802 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5804 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5806 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5808 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5810 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5813 /* Emit code to initialize OVFL, which points to the next varargs
5814 stack argument. CUM->STACK_WORDS gives the number of stack
5815 words used by named arguments. */
5816 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5817 if (cum
->stack_words
> 0)
5818 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
5819 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5820 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5822 /* Emit code to initialize GTOP, the top of the GPR save area. */
5823 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5824 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5825 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5827 /* Emit code to initialize FTOP, the top of the FPR save area.
5828 This address is gpr_save_area_bytes below GTOP, rounded
5829 down to the next fp-aligned boundary. */
5830 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5831 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5832 fpr_offset
&= -UNITS_PER_FPVALUE
;
5834 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
5835 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5836 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5838 /* Emit code to initialize GOFF, the offset from GTOP of the
5839 next GPR argument. */
5840 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5841 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
5842 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5844 /* Likewise emit code to initialize FOFF, the offset from FTOP
5845 of the next FPR argument. */
5846 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5847 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
5848 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5852 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
5853 std_expand_builtin_va_start (valist
, nextarg
);
5857 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5861 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5864 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
5865 unsigned HOST_WIDE_INT align
, boundary
;
5868 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
5870 type
= build_pointer_type (type
);
5872 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
5873 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
5875 /* When we align parameter on stack for caller, if the parameter
5876 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5877 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5878 here with caller. */
5879 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
5880 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
5882 boundary
/= BITS_PER_UNIT
;
5884 /* Hoist the valist value into a temporary for the moment. */
5885 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
5887 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5888 requires greater alignment, we must perform dynamic alignment. */
5889 if (boundary
> align
)
5891 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5892 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
5893 gimplify_and_add (t
, pre_p
);
5895 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5896 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
5898 build_int_cst (TREE_TYPE (valist
), -boundary
)));
5899 gimplify_and_add (t
, pre_p
);
5904 /* If the actual alignment is less than the alignment of the type,
5905 adjust the type accordingly so that we don't assume strict alignment
5906 when dereferencing the pointer. */
5907 boundary
*= BITS_PER_UNIT
;
5908 if (boundary
< TYPE_ALIGN (type
))
5910 type
= build_variant_type_copy (type
);
5911 TYPE_ALIGN (type
) = boundary
;
5914 /* Compute the rounded size of the type. */
5915 type_size
= size_in_bytes (type
);
5916 rounded_size
= round_up (type_size
, align
);
5918 /* Reduce rounded_size so it's sharable with the postqueue. */
5919 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
5923 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
5925 /* Small args are padded downward. */
5926 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
5927 rounded_size
, size_int (align
));
5928 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
5929 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
5930 addr
= fold_build_pointer_plus (addr
, t
);
5933 /* Compute new value for AP. */
5934 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
5935 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
5936 gimplify_and_add (t
, pre_p
);
5938 addr
= fold_convert (build_pointer_type (type
), addr
);
5941 addr
= build_va_arg_indirect_ref (addr
);
5943 return build_va_arg_indirect_ref (addr
);
5946 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5949 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5955 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
5957 type
= build_pointer_type (type
);
5959 if (!EABI_FLOAT_VARARGS_P
)
5960 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5963 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5964 tree ovfl
, top
, off
, align
;
5965 HOST_WIDE_INT size
, rsize
, osize
;
5968 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5969 f_gtop
= DECL_CHAIN (f_ovfl
);
5970 f_ftop
= DECL_CHAIN (f_gtop
);
5971 f_goff
= DECL_CHAIN (f_ftop
);
5972 f_foff
= DECL_CHAIN (f_goff
);
5976 TOP be the top of the GPR or FPR save area;
5977 OFF be the offset from TOP of the next register;
5978 ADDR_RTX be the address of the argument;
5979 SIZE be the number of bytes in the argument type;
5980 RSIZE be the number of bytes used to store the argument
5981 when it's in the register save area; and
5982 OSIZE be the number of bytes used to store it when it's
5983 in the stack overflow area.
5985 The code we want is:
5987 1: off &= -rsize; // round down
5990 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5995 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5996 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6000 [1] and [9] can sometimes be optimized away. */
6002 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6004 size
= int_size_in_bytes (type
);
6006 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6007 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6009 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6010 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6011 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6012 unshare_expr (valist
), f_foff
, NULL_TREE
);
6014 /* When va_start saves FPR arguments to the stack, each slot
6015 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6016 argument's precision. */
6017 rsize
= UNITS_PER_HWFPVALUE
;
6019 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6020 (= PARM_BOUNDARY bits). This can be different from RSIZE
6023 (1) On 32-bit targets when TYPE is a structure such as:
6025 struct s { float f; };
6027 Such structures are passed in paired FPRs, so RSIZE
6028 will be 8 bytes. However, the structure only takes
6029 up 4 bytes of memory, so OSIZE will only be 4.
6031 (2) In combinations such as -mgp64 -msingle-float
6032 -fshort-double. Doubles passed in registers will then take
6033 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6034 stack take up UNITS_PER_WORD bytes. */
6035 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6039 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6040 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6041 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6042 unshare_expr (valist
), f_goff
, NULL_TREE
);
6043 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6044 if (rsize
> UNITS_PER_WORD
)
6046 /* [1] Emit code for: off &= -rsize. */
6047 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6048 build_int_cst (TREE_TYPE (off
), -rsize
));
6049 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6054 /* [2] Emit code to branch if off == 0. */
6055 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6056 build_int_cst (TREE_TYPE (off
), 0));
6057 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6059 /* [5] Emit code for: off -= rsize. We do this as a form of
6060 post-decrement not available to C. */
6061 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6062 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6064 /* [4] Emit code for:
6065 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6066 t
= fold_convert (sizetype
, t
);
6067 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6068 t
= fold_build_pointer_plus (top
, t
);
6069 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6070 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6071 COND_EXPR_THEN (addr
) = t
;
6073 if (osize
> UNITS_PER_WORD
)
6075 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6076 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6077 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6078 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6079 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6080 unshare_expr (ovfl
), t
);
6085 /* [10, 11] Emit code for:
6086 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6088 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6089 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6090 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6091 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6093 /* String [9] and [10, 11] together. */
6095 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6096 COND_EXPR_ELSE (addr
) = t
;
6098 addr
= fold_convert (build_pointer_type (type
), addr
);
6099 addr
= build_va_arg_indirect_ref (addr
);
6103 addr
= build_va_arg_indirect_ref (addr
);
6108 /* Declare a unique, locally-binding function called NAME, then start
6112 mips_start_unique_function (const char *name
)
6116 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6117 get_identifier (name
),
6118 build_function_type_list (void_type_node
, NULL_TREE
));
6119 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6120 NULL_TREE
, void_type_node
);
6121 TREE_PUBLIC (decl
) = 1;
6122 TREE_STATIC (decl
) = 1;
6124 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
6126 targetm
.asm_out
.unique_section (decl
, 0);
6127 switch_to_section (get_named_section (decl
, NULL
, 0));
6129 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6130 fputs ("\t.hidden\t", asm_out_file
);
6131 assemble_name (asm_out_file
, name
);
6132 putc ('\n', asm_out_file
);
6135 /* Start a definition of function NAME. MIPS16_P indicates whether the
6136 function contains MIPS16 code. */
6139 mips_start_function_definition (const char *name
, bool mips16_p
)
6142 fprintf (asm_out_file
, "\t.set\tmips16\n");
6144 fprintf (asm_out_file
, "\t.set\tnomips16\n");
6146 if (TARGET_MICROMIPS
)
6147 fprintf (asm_out_file
, "\t.set\tmicromips\n");
6148 #ifdef HAVE_GAS_MICROMIPS
6150 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
6153 if (!flag_inhibit_size_directive
)
6155 fputs ("\t.ent\t", asm_out_file
);
6156 assemble_name (asm_out_file
, name
);
6157 fputs ("\n", asm_out_file
);
6160 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
6162 /* Start the definition proper. */
6163 assemble_name (asm_out_file
, name
);
6164 fputs (":\n", asm_out_file
);
6167 /* End a function definition started by mips_start_function_definition. */
6170 mips_end_function_definition (const char *name
)
6172 if (!flag_inhibit_size_directive
)
6174 fputs ("\t.end\t", asm_out_file
);
6175 assemble_name (asm_out_file
, name
);
6176 fputs ("\n", asm_out_file
);
6180 /* Output a definition of the __mips16_rdhwr function. */
6183 mips_output_mips16_rdhwr (void)
6187 name
= "__mips16_rdhwr";
6188 mips_start_unique_function (name
);
6189 mips_start_function_definition (name
, false);
6190 fprintf (asm_out_file
,
6192 "\t.set\tmips32r2\n"
6193 "\t.set\tnoreorder\n"
6197 mips_end_function_definition (name
);
6200 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6203 mips_ok_for_lazy_binding_p (rtx x
)
6205 return (TARGET_USE_GOT
6206 && GET_CODE (x
) == SYMBOL_REF
6207 && !SYMBOL_REF_BIND_NOW_P (x
)
6208 && !mips_symbol_binds_local_p (x
));
6211 /* Load function address ADDR into register DEST. TYPE is as for
6212 mips_expand_call. Return true if we used an explicit lazy-binding
6216 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
6218 /* If we're generating PIC, and this call is to a global function,
6219 try to allow its address to be resolved lazily. This isn't
6220 possible for sibcalls when $gp is call-saved because the value
6221 of $gp on entry to the stub would be our caller's gp, not ours. */
6222 if (TARGET_EXPLICIT_RELOCS
6223 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
6224 && mips_ok_for_lazy_binding_p (addr
))
6226 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
6227 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
6232 mips_emit_move (dest
, addr
);
6237 /* Each locally-defined hard-float MIPS16 function has a local symbol
6238 associated with it. This hash table maps the function symbol (FUNC)
6239 to the local symbol (LOCAL). */
6240 struct GTY(()) mips16_local_alias
{
6244 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
6246 /* Hash table callbacks for mips16_local_aliases. */
6249 mips16_local_aliases_hash (const void *entry
)
6251 const struct mips16_local_alias
*alias
;
6253 alias
= (const struct mips16_local_alias
*) entry
;
6254 return htab_hash_string (XSTR (alias
->func
, 0));
6258 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
6260 const struct mips16_local_alias
*alias1
, *alias2
;
6262 alias1
= (const struct mips16_local_alias
*) entry1
;
6263 alias2
= (const struct mips16_local_alias
*) entry2
;
6264 return rtx_equal_p (alias1
->func
, alias2
->func
);
6267 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6268 Return a local alias for it, creating a new one if necessary. */
6271 mips16_local_alias (rtx func
)
6273 struct mips16_local_alias
*alias
, tmp_alias
;
6276 /* Create the hash table if this is the first call. */
6277 if (mips16_local_aliases
== NULL
)
6278 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
6279 mips16_local_aliases_eq
, NULL
);
6281 /* Look up the function symbol, creating a new entry if need be. */
6282 tmp_alias
.func
= func
;
6283 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
6284 gcc_assert (slot
!= NULL
);
6286 alias
= (struct mips16_local_alias
*) *slot
;
6289 const char *func_name
, *local_name
;
6292 /* Create a new SYMBOL_REF for the local symbol. The choice of
6293 __fn_local_* is based on the __fn_stub_* names that we've
6294 traditionally used for the non-MIPS16 stub. */
6295 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6296 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6297 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6298 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6300 /* Create a new structure to represent the mapping. */
6301 alias
= ggc_alloc_mips16_local_alias ();
6303 alias
->local
= local
;
6306 return alias
->local
;
6309 /* A chained list of functions for which mips16_build_call_stub has already
6310 generated a stub. NAME is the name of the function and FP_RET_P is true
6311 if the function returns a value in floating-point registers. */
6312 struct mips16_stub
{
6313 struct mips16_stub
*next
;
6317 static struct mips16_stub
*mips16_stubs
;
6319 /* Return the two-character string that identifies floating-point
6320 return mode MODE in the name of a MIPS16 function stub. */
6323 mips16_call_stub_mode_suffix (enum machine_mode mode
)
6327 else if (mode
== DFmode
)
6329 else if (mode
== SCmode
)
6331 else if (mode
== DCmode
)
6333 else if (mode
== V2SFmode
)
6339 /* Write instructions to move a 32-bit value between general register
6340 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6341 from GPREG to FPREG and 'f' to move in the opposite direction. */
6344 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6346 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6347 reg_names
[gpreg
], reg_names
[fpreg
]);
6350 /* Likewise for 64-bit values. */
6353 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6356 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6357 reg_names
[gpreg
], reg_names
[fpreg
]);
6358 else if (TARGET_FLOAT64
)
6360 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6361 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6362 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6363 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6367 /* Move the least-significant word. */
6368 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6369 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6370 /* ...then the most significant word. */
6371 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6372 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6376 /* Write out code to move floating-point arguments into or out of
6377 general registers. FP_CODE is the code describing which arguments
6378 are present (see the comment above the definition of CUMULATIVE_ARGS
6379 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6382 mips_output_args_xfer (int fp_code
, char direction
)
6384 unsigned int gparg
, fparg
, f
;
6385 CUMULATIVE_ARGS cum
;
6387 /* This code only works for o32 and o64. */
6388 gcc_assert (TARGET_OLDABI
);
6390 mips_init_cumulative_args (&cum
, NULL
);
6392 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6394 enum machine_mode mode
;
6395 struct mips_arg_info info
;
6399 else if ((f
& 3) == 2)
6404 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6405 gparg
= mips_arg_regno (&info
, false);
6406 fparg
= mips_arg_regno (&info
, true);
6409 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6411 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6413 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6417 /* Write a MIPS16 stub for the current function. This stub is used
6418 for functions which take arguments in the floating-point registers.
6419 It is normal-mode code that moves the floating-point arguments
6420 into the general registers and then jumps to the MIPS16 code. */
6423 mips16_build_function_stub (void)
6425 const char *fnname
, *alias_name
, *separator
;
6426 char *secname
, *stubname
;
6431 /* Create the name of the stub, and its unique section. */
6432 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6433 alias
= mips16_local_alias (symbol
);
6435 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6436 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6437 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6438 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6440 /* Build a decl for the stub. */
6441 stubdecl
= build_decl (BUILTINS_LOCATION
,
6442 FUNCTION_DECL
, get_identifier (stubname
),
6443 build_function_type_list (void_type_node
, NULL_TREE
));
6444 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6445 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6446 RESULT_DECL
, NULL_TREE
, void_type_node
);
6448 /* Output a comment. */
6449 fprintf (asm_out_file
, "\t# Stub function for %s (",
6450 current_function_name ());
6452 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6454 fprintf (asm_out_file
, "%s%s", separator
,
6455 (f
& 3) == 1 ? "float" : "double");
6458 fprintf (asm_out_file
, ")\n");
6460 /* Start the function definition. */
6461 assemble_start_function (stubdecl
, stubname
);
6462 mips_start_function_definition (stubname
, false);
6464 /* If generating pic2 code, either set up the global pointer or
6466 if (TARGET_ABICALLS_PIC2
)
6468 if (TARGET_ABSOLUTE_ABICALLS
)
6469 fprintf (asm_out_file
, "\t.option\tpic0\n");
6472 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6473 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6474 target function is. Use a local GOT access when loading the
6475 symbol, to cut down on the number of unnecessary GOT entries
6476 for stubs that aren't needed. */
6477 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6482 /* Load the address of the MIPS16 function into $25. Do this first so
6483 that targets with coprocessor interlocks can use an MFC1 to fill the
6485 output_asm_insn ("la\t%^,%0", &symbol
);
6487 /* Move the arguments from floating-point registers to general registers. */
6488 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6490 /* Jump to the MIPS16 function. */
6491 output_asm_insn ("jr\t%^", NULL
);
6493 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6494 fprintf (asm_out_file
, "\t.option\tpic2\n");
6496 mips_end_function_definition (stubname
);
6498 /* If the linker needs to create a dynamic symbol for the target
6499 function, it will associate the symbol with the stub (which,
6500 unlike the target function, follows the proper calling conventions).
6501 It is therefore useful to have a local alias for the target function,
6502 so that it can still be identified as MIPS16 code. As an optimization,
6503 this symbol can also be used for indirect MIPS16 references from
6504 within this file. */
6505 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6507 switch_to_section (function_section (current_function_decl
));
6510 /* The current function is a MIPS16 function that returns a value in an FPR.
6511 Copy the return value from its soft-float to its hard-float location.
6512 libgcc2 has special non-MIPS16 helper functions for each case. */
6515 mips16_copy_fpr_return_value (void)
6517 rtx fn
, insn
, retval
;
6519 enum machine_mode return_mode
;
6522 return_type
= DECL_RESULT (current_function_decl
);
6523 return_mode
= DECL_MODE (return_type
);
6525 name
= ACONCAT (("__mips16_ret_",
6526 mips16_call_stub_mode_suffix (return_mode
),
6528 fn
= mips16_stub_function (name
);
6530 /* The function takes arguments in $2 (and possibly $3), so calls
6531 to it cannot be lazily bound. */
6532 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6534 /* Model the call as something that takes the GPR return value as
6535 argument and returns an "updated" value. */
6536 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6537 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6538 const0_rtx
, NULL_RTX
, false);
6539 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6542 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6543 RETVAL is the location of the return value, or null if this is
6544 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6545 arguments and FP_CODE is the code built by mips_function_arg;
6546 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6548 There are three alternatives:
6550 - If a stub was needed, emit the call and return the call insn itself.
6552 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6553 to the new target and return null.
6555 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6558 A stub is needed for calls to functions that, in normal mode,
6559 receive arguments in FPRs or return values in FPRs. The stub
6560 copies the arguments from their soft-float positions to their
6561 hard-float positions, calls the real function, then copies the
6562 return value from its hard-float position to its soft-float
6565 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6566 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6567 automatically redirects the JAL to the stub, otherwise the JAL
6568 continues to call FN directly. */
6571 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6575 struct mips16_stub
*l
;
6578 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6579 we were invoked with the -msoft-float option. */
6580 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6583 /* Figure out whether the value might come back in a floating-point
6585 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6587 /* We don't need to do anything if there were no floating-point
6588 arguments and the value will not be returned in a floating-point
6590 if (fp_code
== 0 && !fp_ret_p
)
6593 /* We don't need to do anything if this is a call to a special
6594 MIPS16 support function. */
6596 if (mips16_stub_function_p (fn
))
6599 /* If we're calling a locally-defined MIPS16 function, we know that
6600 it will return values in both the "soft-float" and "hard-float"
6601 registers. There is no need to use a stub to move the latter
6603 if (fp_code
== 0 && mips16_local_function_p (fn
))
6606 /* This code will only work for o32 and o64 abis. The other ABI's
6607 require more sophisticated support. */
6608 gcc_assert (TARGET_OLDABI
);
6610 /* If we're calling via a function pointer, use one of the magic
6611 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6612 Each stub expects the function address to arrive in register $2. */
6613 if (GET_CODE (fn
) != SYMBOL_REF
6614 || !call_insn_operand (fn
, VOIDmode
))
6617 rtx stub_fn
, insn
, addr
;
6620 /* If this is a locally-defined and locally-binding function,
6621 avoid the stub by calling the local alias directly. */
6622 if (mips16_local_function_p (fn
))
6624 *fn_ptr
= mips16_local_alias (fn
);
6628 /* Create a SYMBOL_REF for the libgcc.a function. */
6630 sprintf (buf
, "__mips16_call_stub_%s_%d",
6631 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6634 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6635 stub_fn
= mips16_stub_function (buf
);
6637 /* The function uses $2 as an argument, so calls to it
6638 cannot be lazily bound. */
6639 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6641 /* Load the target function into $2. */
6642 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6643 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6645 /* Emit the call. */
6646 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6647 args_size
, NULL_RTX
, lazy_p
);
6649 /* Tell GCC that this call does indeed use the value of $2. */
6650 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6652 /* If we are handling a floating-point return value, we need to
6653 save $18 in the function prologue. Putting a note on the
6654 call will mean that df_regs_ever_live_p ($18) will be true if the
6655 call is not eliminated, and we can check that in the prologue
6658 CALL_INSN_FUNCTION_USAGE (insn
) =
6659 gen_rtx_EXPR_LIST (VOIDmode
,
6660 gen_rtx_CLOBBER (VOIDmode
,
6661 gen_rtx_REG (word_mode
, 18)),
6662 CALL_INSN_FUNCTION_USAGE (insn
));
6667 /* We know the function we are going to call. If we have already
6668 built a stub, we don't need to do anything further. */
6669 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6670 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6671 if (strcmp (l
->name
, fnname
) == 0)
6676 const char *separator
;
6677 char *secname
, *stubname
;
6678 tree stubid
, stubdecl
;
6681 /* If the function does not return in FPRs, the special stub
6685 If the function does return in FPRs, the stub section is named
6686 .mips16.call.fp.FNNAME
6688 Build a decl for the stub. */
6689 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6691 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6693 stubid
= get_identifier (stubname
);
6694 stubdecl
= build_decl (BUILTINS_LOCATION
,
6695 FUNCTION_DECL
, stubid
,
6696 build_function_type_list (void_type_node
,
6698 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6699 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6700 RESULT_DECL
, NULL_TREE
,
6703 /* Output a comment. */
6704 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6706 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6710 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6712 fprintf (asm_out_file
, "%s%s", separator
,
6713 (f
& 3) == 1 ? "float" : "double");
6716 fprintf (asm_out_file
, ")\n");
6718 /* Start the function definition. */
6719 assemble_start_function (stubdecl
, stubname
);
6720 mips_start_function_definition (stubname
, false);
6724 fprintf (asm_out_file
, "\t.cfi_startproc\n");
6726 /* Create a fake CFA 4 bytes below the stack pointer.
6727 This works around unwinders (like libgcc's) that expect
6728 the CFA for non-signal frames to be unique. */
6729 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
6731 /* "Save" $sp in itself so we don't use the fake CFA.
6732 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6733 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
6737 /* Load the address of the MIPS16 function into $25. Do this
6738 first so that targets with coprocessor interlocks can use
6739 an MFC1 to fill the delay slot. */
6740 if (TARGET_EXPLICIT_RELOCS
)
6742 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6743 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6746 output_asm_insn ("la\t%^,%0", &fn
);
6749 /* Move the arguments from general registers to floating-point
6751 mips_output_args_xfer (fp_code
, 't');
6755 /* Save the return address in $18 and call the non-MIPS16 function.
6756 The stub's caller knows that $18 might be clobbered, even though
6757 $18 is usually a call-saved register. */
6758 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6759 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6760 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6761 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
6763 /* Move the result from floating-point registers to
6764 general registers. */
6765 switch (GET_MODE (retval
))
6768 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6770 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6772 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6773 TARGET_LITTLE_ENDIAN
6774 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6776 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6778 /* On 64-bit targets, complex floats are returned in
6779 a single GPR, such that "sd" on a suitably-aligned
6780 target would store the value correctly. */
6781 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6782 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6783 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6784 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6785 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6786 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6787 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6788 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6789 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6790 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6791 reg_names
[GP_RETURN
],
6792 reg_names
[GP_RETURN
],
6793 reg_names
[GP_RETURN
+ 1]);
6798 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6802 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6803 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6807 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6813 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6814 fprintf (asm_out_file
, "\t.cfi_endproc\n");
6818 /* Jump to the previously-loaded address. */
6819 output_asm_insn ("jr\t%^", NULL
);
6822 #ifdef ASM_DECLARE_FUNCTION_SIZE
6823 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6826 mips_end_function_definition (stubname
);
6828 /* Record this stub. */
6829 l
= XNEW (struct mips16_stub
);
6830 l
->name
= xstrdup (fnname
);
6831 l
->fp_ret_p
= fp_ret_p
;
6832 l
->next
= mips16_stubs
;
6836 /* If we expect a floating-point return value, but we've built a
6837 stub which does not expect one, then we're in trouble. We can't
6838 use the existing stub, because it won't handle the floating-point
6839 value. We can't build a new stub, because the linker won't know
6840 which stub to use for the various calls in this object file.
6841 Fortunately, this case is illegal, since it means that a function
6842 was declared in two different ways in a single compilation. */
6843 if (fp_ret_p
&& !l
->fp_ret_p
)
6844 error ("cannot handle inconsistent calls to %qs", fnname
);
6846 if (retval
== NULL_RTX
)
6847 insn
= gen_call_internal_direct (fn
, args_size
);
6849 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
6850 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
6852 /* If we are calling a stub which handles a floating-point return
6853 value, we need to arrange to save $18 in the prologue. We do this
6854 by marking the function call as using the register. The prologue
6855 will later see that it is used, and emit code to save it. */
6857 CALL_INSN_FUNCTION_USAGE (insn
) =
6858 gen_rtx_EXPR_LIST (VOIDmode
,
6859 gen_rtx_CLOBBER (VOIDmode
,
6860 gen_rtx_REG (word_mode
, 18)),
6861 CALL_INSN_FUNCTION_USAGE (insn
));
6866 /* Expand a call of type TYPE. RESULT is where the result will go (null
6867 for "call"s and "sibcall"s), ADDR is the address of the function,
6868 ARGS_SIZE is the size of the arguments and AUX is the value passed
6869 to us by mips_function_arg. LAZY_P is true if this call already
6870 involves a lazily-bound function address (such as when calling
6871 functions through a MIPS16 hard-float stub).
6873 Return the call itself. */
6876 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
6877 rtx args_size
, rtx aux
, bool lazy_p
)
6879 rtx orig_addr
, pattern
, insn
;
6882 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
6883 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
6886 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
6891 if (!call_insn_operand (addr
, VOIDmode
))
6893 if (type
== MIPS_CALL_EPILOGUE
)
6894 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
6896 addr
= gen_reg_rtx (Pmode
);
6897 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
6902 rtx (*fn
) (rtx
, rtx
);
6904 if (type
== MIPS_CALL_SIBCALL
)
6905 fn
= gen_sibcall_internal
;
6907 fn
= gen_call_internal
;
6909 pattern
= fn (addr
, args_size
);
6911 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
6913 /* Handle return values created by mips_return_fpr_pair. */
6914 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
6917 if (type
== MIPS_CALL_SIBCALL
)
6918 fn
= gen_sibcall_value_multiple_internal
;
6920 fn
= gen_call_value_multiple_internal
;
6922 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
6923 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
6924 pattern
= fn (reg1
, addr
, args_size
, reg2
);
6928 rtx (*fn
) (rtx
, rtx
, rtx
);
6930 if (type
== MIPS_CALL_SIBCALL
)
6931 fn
= gen_sibcall_value_internal
;
6933 fn
= gen_call_value_internal
;
6935 /* Handle return values created by mips_return_fpr_single. */
6936 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
6937 result
= XEXP (XVECEXP (result
, 0, 0), 0);
6938 pattern
= fn (result
, addr
, args_size
);
6941 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
6944 /* Split call instruction INSN into a $gp-clobbering call and
6945 (where necessary) an instruction to restore $gp from its save slot.
6946 CALL_PATTERN is the pattern of the new call. */
6949 mips_split_call (rtx insn
, rtx call_pattern
)
6951 emit_call_insn (call_pattern
);
6952 if (!find_reg_note (insn
, REG_NORETURN
, 0))
6953 /* Pick a temporary register that is suitable for both MIPS16 and
6954 non-MIPS16 code. $4 and $5 are used for returning complex double
6955 values in soft-float code, so $6 is the first suitable candidate. */
6956 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 2));
6959 /* Return true if a call to DECL may need to use JALX. */
6962 mips_call_may_need_jalx_p (tree decl
)
6964 /* If the current translation unit would use a different mode for DECL,
6965 assume that the call needs JALX. */
6966 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
6969 /* mips_get_compress_mode is always accurate for locally-binding
6970 functions in the current translation unit. */
6971 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
6974 /* When -minterlink-compressed is in effect, assume that functions
6975 could use a different encoding mode unless an attribute explicitly
6976 tells us otherwise. */
6977 if (TARGET_INTERLINK_COMPRESSED
)
6979 if (!TARGET_COMPRESSION
6980 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
6982 if (TARGET_COMPRESSION
6983 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
6990 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6993 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
6995 if (!TARGET_SIBCALLS
)
6998 /* Interrupt handlers need special epilogue code and therefore can't
7000 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7003 /* Direct Js are only possible to functions that use the same ISA encoding.
7004 There is no JX counterpoart of JALX. */
7006 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7007 && mips_call_may_need_jalx_p (decl
))
7010 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7011 require $gp to be valid on entry, so sibcalls can only use stubs
7012 if $gp is call-clobbered. */
7014 && TARGET_CALL_SAVED_GP
7015 && !TARGET_ABICALLS_PIC0
7016 && !targetm
.binds_local_p (decl
))
7023 /* Emit code to move general operand SRC into condition-code
7024 register DEST given that SCRATCH is a scratch TFmode FPR.
7031 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
7034 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
7038 /* Change the source to SFmode. */
7040 src
= adjust_address (src
, SFmode
, 0);
7041 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
7042 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
7044 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
7045 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
7047 mips_emit_move (copy_rtx (fp1
), src
);
7048 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
7049 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
7052 /* Implement MOVE_BY_PIECES_P. */
7055 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7059 /* movmemsi is meant to generate code that is at least as good as
7060 move_by_pieces. However, movmemsi effectively uses a by-pieces
7061 implementation both for moves smaller than a word and for
7062 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7063 bytes. We should allow the tree-level optimisers to do such
7064 moves by pieces, as it often exposes other optimization
7065 opportunities. We might as well continue to use movmemsi at
7066 the rtl level though, as it produces better code when
7067 scheduling is disabled (such as at -O). */
7068 if (currently_expanding_to_rtl
)
7070 if (align
< BITS_PER_WORD
)
7071 return size
< UNITS_PER_WORD
;
7072 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7074 /* The default value. If this becomes a target hook, we should
7075 call the default definition instead. */
7076 return (move_by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1)
7077 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7080 /* Implement STORE_BY_PIECES_P. */
7083 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7085 /* Storing by pieces involves moving constants into registers
7086 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7087 We need to decide whether it is cheaper to load the address of
7088 constant data into a register and use a block move instead. */
7090 /* If the data is only byte aligned, then:
7092 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7093 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7096 (a2) A block move of 4 bytes from aligned source data can use an
7097 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7098 4 SBs that we would generate when storing by pieces. */
7099 if (align
<= BITS_PER_UNIT
)
7102 /* If the data is 2-byte aligned, then:
7104 (b1) A block move of less than 4 bytes would use a combination of LBs,
7105 LHs, SBs and SHs. We get better code by using single-instruction
7106 LIs, SBs and SHs instead.
7108 (b2) A block move of 4 bytes from aligned source data would again use
7109 an LW/SWL/SWR sequence. In most cases, loading the address of
7110 the source data would require at least one extra instruction.
7111 It is often more efficient to use 2 single-instruction LIs and
7114 (b3) A block move of up to 3 additional bytes would be like (b1).
7116 (b4) A block move of 8 bytes from aligned source data can use two
7117 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7118 sequences are better than the 4 LIs and 4 SHs that we'd generate
7119 when storing by pieces.
7121 The reasoning for higher alignments is similar:
7123 (c1) A block move of less than 4 bytes would be the same as (b1).
7125 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7126 loading the address of the source data would typically require
7127 at least one extra instruction. It is generally better to use
7130 (c3) A block move of up to 3 additional bytes would be like (b1).
7132 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7133 LD/SD sequence, and in these cases we've traditionally preferred
7134 the memory copy over the more bulky constant moves. */
7138 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7139 Assume that the areas do not overlap. */
7142 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7144 HOST_WIDE_INT offset
, delta
;
7145 unsigned HOST_WIDE_INT bits
;
7147 enum machine_mode mode
;
7150 /* Work out how many bits to move at a time. If both operands have
7151 half-word alignment, it is usually better to move in half words.
7152 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7153 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7154 Otherwise move word-sized chunks. */
7155 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7156 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7157 bits
= BITS_PER_WORD
/ 2;
7159 bits
= BITS_PER_WORD
;
7161 mode
= mode_for_size (bits
, MODE_INT
, 0);
7162 delta
= bits
/ BITS_PER_UNIT
;
7164 /* Allocate a buffer for the temporary registers. */
7165 regs
= XALLOCAVEC (rtx
, length
/ delta
);
7167 /* Load as many BITS-sized chunks as possible. Use a normal load if
7168 the source has enough alignment, otherwise use left/right pairs. */
7169 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7171 regs
[i
] = gen_reg_rtx (mode
);
7172 if (MEM_ALIGN (src
) >= bits
)
7173 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
7176 rtx part
= adjust_address (src
, BLKmode
, offset
);
7177 set_mem_size (part
, delta
);
7178 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
7183 /* Copy the chunks to the destination. */
7184 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7185 if (MEM_ALIGN (dest
) >= bits
)
7186 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
7189 rtx part
= adjust_address (dest
, BLKmode
, offset
);
7190 set_mem_size (part
, delta
);
7191 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
7195 /* Mop up any left-over bytes. */
7196 if (offset
< length
)
7198 src
= adjust_address (src
, BLKmode
, offset
);
7199 dest
= adjust_address (dest
, BLKmode
, offset
);
7200 move_by_pieces (dest
, src
, length
- offset
,
7201 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
7205 /* Helper function for doing a loop-based block operation on memory
7206 reference MEM. Each iteration of the loop will operate on LENGTH
7209 Create a new base register for use within the loop and point it to
7210 the start of MEM. Create a new memory reference that uses this
7211 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7214 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
7215 rtx
*loop_reg
, rtx
*loop_mem
)
7217 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
7219 /* Although the new mem does not refer to a known location,
7220 it does keep up to LENGTH bytes of alignment. */
7221 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
7222 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
7225 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7226 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7227 the memory regions do not overlap. */
7230 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
7231 HOST_WIDE_INT bytes_per_iter
)
7233 rtx label
, src_reg
, dest_reg
, final_src
, test
;
7234 HOST_WIDE_INT leftover
;
7236 leftover
= length
% bytes_per_iter
;
7239 /* Create registers and memory references for use within the loop. */
7240 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
7241 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
7243 /* Calculate the value that SRC_REG should have after the last iteration
7245 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
7248 /* Emit the start of the loop. */
7249 label
= gen_label_rtx ();
7252 /* Emit the loop body. */
7253 mips_block_move_straight (dest
, src
, bytes_per_iter
);
7255 /* Move on to the next block. */
7256 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
7257 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
7259 /* Emit the loop condition. */
7260 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7261 if (Pmode
== DImode
)
7262 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7264 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7266 /* Mop up any left-over bytes. */
7268 mips_block_move_straight (dest
, src
, leftover
);
7271 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7272 memory reference SRC to memory reference DEST. */
7275 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7277 if (CONST_INT_P (length
))
7279 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7281 mips_block_move_straight (dest
, src
, INTVAL (length
));
7286 mips_block_move_loop (dest
, src
, INTVAL (length
),
7287 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7294 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7297 mips_expand_synci_loop (rtx begin
, rtx end
)
7299 rtx inc
, label
, end_label
, cmp_result
, mask
, length
;
7301 /* Create end_label. */
7302 end_label
= gen_label_rtx ();
7304 /* Check if begin equals end. */
7305 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7306 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7308 /* Load INC with the cache line size (rdhwr INC,$1). */
7309 inc
= gen_reg_rtx (Pmode
);
7310 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7312 /* Check if inc is 0. */
7313 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7314 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7316 /* Calculate mask. */
7317 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7319 /* Mask out begin by mask. */
7320 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7322 /* Calculate length. */
7323 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7325 /* Loop back to here. */
7326 label
= gen_label_rtx ();
7329 emit_insn (gen_synci (begin
));
7331 /* Update length. */
7332 mips_emit_binary (MINUS
, length
, length
, inc
);
7335 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7337 /* Check if length is greater than 0. */
7338 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7339 emit_jump_insn (gen_condjump (cmp_result
, label
));
7341 emit_label (end_label
);
7344 /* Expand a QI or HI mode atomic memory operation.
7346 GENERATOR contains a pointer to the gen_* function that generates
7347 the SI mode underlying atomic operation using masks that we
7350 RESULT is the return register for the operation. Its value is NULL
7353 MEM is the location of the atomic access.
7355 OLDVAL is the first operand for the operation.
7357 NEWVAL is the optional second operand for the operation. Its value
7358 is NULL if unused. */
7361 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7362 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7364 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7365 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7367 enum machine_mode mode
;
7369 mode
= GET_MODE (mem
);
7371 /* Compute the address of the containing SImode value. */
7372 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7373 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7374 force_reg (Pmode
, GEN_INT (-4)));
7376 /* Create a memory reference for it. */
7377 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7378 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7379 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7381 /* Work out the byte offset of the QImode or HImode value,
7382 counting from the least significant byte. */
7383 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7384 if (TARGET_BIG_ENDIAN
)
7385 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7387 /* Multiply by eight to convert the shift value from bytes to bits. */
7388 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7390 /* Make the final shift an SImode value, so that it can be used in
7391 SImode operations. */
7392 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7394 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7395 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7396 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7397 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7399 /* Compute the equivalent exclusive mask. */
7400 inverted_mask
= gen_reg_rtx (SImode
);
7401 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
7402 gen_rtx_NOT (SImode
, mask
)));
7404 /* Shift the old value into place. */
7405 if (oldval
!= const0_rtx
)
7407 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7408 oldval
= force_reg (SImode
, oldval
);
7409 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7412 /* Do the same for the new value. */
7413 if (newval
&& newval
!= const0_rtx
)
7415 newval
= convert_modes (SImode
, mode
, newval
, true);
7416 newval
= force_reg (SImode
, newval
);
7417 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7420 /* Do the SImode atomic access. */
7422 res
= gen_reg_rtx (SImode
);
7424 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7426 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7428 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7434 /* Shift and convert the result. */
7435 mips_emit_binary (AND
, res
, res
, mask
);
7436 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7437 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7441 /* Return true if it is possible to use left/right accesses for a
7442 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7443 When returning true, update *LEFT and *RIGHT as follows:
7445 *LEFT is a QImode reference to the first byte if big endian or
7446 the last byte if little endian. This address can be used in the
7447 left-side instructions (LWL, SWL, LDL, SDL).
7449 *RIGHT is a QImode reference to the opposite end of the field and
7450 can be used in the patterning right-side instruction. */
7453 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7454 rtx
*left
, rtx
*right
)
7458 /* Check that the size is valid. */
7459 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7462 /* We can only access byte-aligned values. Since we are always passed
7463 a reference to the first byte of the field, it is not necessary to
7464 do anything with BITPOS after this check. */
7465 if (bitpos
% BITS_PER_UNIT
!= 0)
7468 /* Reject aligned bitfields: we want to use a normal load or store
7469 instead of a left/right pair. */
7470 if (MEM_ALIGN (op
) >= width
)
7473 /* Get references to both ends of the field. */
7474 first
= adjust_address (op
, QImode
, 0);
7475 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7477 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7478 correspond to the MSB and RIGHT to the LSB. */
7479 if (TARGET_BIG_ENDIAN
)
7480 *left
= first
, *right
= last
;
7482 *left
= last
, *right
= first
;
7487 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7488 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7489 the operation is the equivalent of:
7491 (set DEST (*_extract SRC WIDTH BITPOS))
7493 Return true on success. */
7496 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7497 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7499 rtx left
, right
, temp
;
7500 rtx dest1
= NULL_RTX
;
7502 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7503 be a DImode, create a new temp and emit a zero extend at the end. */
7504 if (GET_MODE (dest
) == DImode
7506 && GET_MODE_BITSIZE (SImode
) == width
)
7509 dest
= gen_reg_rtx (SImode
);
7512 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
7515 temp
= gen_reg_rtx (GET_MODE (dest
));
7516 if (GET_MODE (dest
) == DImode
)
7518 emit_insn (gen_mov_ldl (temp
, src
, left
));
7519 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7523 emit_insn (gen_mov_lwl (temp
, src
, left
));
7524 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7527 /* If we were loading 32bits and the original register was DI then
7528 sign/zero extend into the orignal dest. */
7532 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7534 emit_insn (gen_extendsidi2 (dest1
, dest
));
7539 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7540 BITPOS and SRC are the operands passed to the expander; the operation
7541 is the equivalent of:
7543 (set (zero_extract DEST WIDTH BITPOS) SRC)
7545 Return true on success. */
7548 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7549 HOST_WIDE_INT bitpos
)
7552 enum machine_mode mode
;
7554 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
7557 mode
= mode_for_size (width
, MODE_INT
, 0);
7558 src
= gen_lowpart (mode
, src
);
7561 emit_insn (gen_mov_sdl (dest
, src
, left
));
7562 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7566 emit_insn (gen_mov_swl (dest
, src
, left
));
7567 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7572 /* Return true if X is a MEM with the same size as MODE. */
7575 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
7578 && MEM_SIZE_KNOWN_P (x
)
7579 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7582 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7583 source of an "ext" instruction or the destination of an "ins"
7584 instruction. OP must be a register operand and the following
7585 conditions must hold:
7587 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7588 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7589 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7591 Also reject lengths equal to a word as they are better handled
7592 by the move patterns. */
7595 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7597 if (!ISA_HAS_EXT_INS
7598 || !register_operand (op
, VOIDmode
)
7599 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7602 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7605 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7611 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7612 operation if MAXLEN is the maxium length of consecutive bits that
7613 can make up MASK. MODE is the mode of the operation. See
7614 mask_low_and_shift_len for the actual definition. */
7617 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7619 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7622 /* Return true iff OP1 and OP2 are valid operands together for the
7623 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7624 see the table in the comment before the pattern. */
7627 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7629 return (memory_operand (op1
, mode
)
7630 ? and_load_operand (op2
, mode
)
7631 : and_reg_operand (op2
, mode
));
7634 /* The canonical form of a mask-low-and-shift-left operation is
7635 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7636 cleared. Thus we need to shift MASK to the right before checking if it
7637 is a valid mask value. MODE is the mode of the operation. If true
7638 return the length of the mask, otherwise return -1. */
7641 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7643 HOST_WIDE_INT shval
;
7645 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7646 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7649 /* Return true if -msplit-addresses is selected and should be honored.
7651 -msplit-addresses is a half-way house between explicit relocations
7652 and the traditional assembler macros. It can split absolute 32-bit
7653 symbolic constants into a high/lo_sum pair but uses macros for other
7656 Like explicit relocation support for REL targets, it relies
7657 on GNU extensions in the assembler and the linker.
7659 Although this code should work for -O0, it has traditionally
7660 been treated as an optimization. */
7663 mips_split_addresses_p (void)
7665 return (TARGET_SPLIT_ADDRESSES
7669 && !ABI_HAS_64BIT_SYMBOLS
);
7672 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7675 mips_init_relocs (void)
7677 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7678 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7679 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
7680 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7681 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7683 if (TARGET_MIPS16_PCREL_LOADS
)
7684 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
7687 if (ABI_HAS_64BIT_SYMBOLS
)
7689 if (TARGET_EXPLICIT_RELOCS
)
7691 mips_split_p
[SYMBOL_64_HIGH
] = true;
7692 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7693 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7695 mips_split_p
[SYMBOL_64_MID
] = true;
7696 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7697 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7699 mips_split_p
[SYMBOL_64_LOW
] = true;
7700 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7701 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7703 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7704 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7709 if (TARGET_EXPLICIT_RELOCS
7710 || mips_split_addresses_p ()
7713 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7714 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7715 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7722 /* The high part is provided by a pseudo copy of $gp. */
7723 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7724 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7726 else if (TARGET_EXPLICIT_RELOCS
)
7727 /* Small data constants are kept whole until after reload,
7728 then lowered by mips_rewrite_small_data. */
7729 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7731 if (TARGET_EXPLICIT_RELOCS
)
7733 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7736 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7737 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7741 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7742 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7745 /* Expose the use of $28 as soon as possible. */
7746 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7750 /* The HIGH and LO_SUM are matched by special .md patterns. */
7751 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7753 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7754 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7755 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7757 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7758 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7759 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7764 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7766 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7767 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7769 /* Expose the use of $28 as soon as possible. */
7770 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7776 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7777 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7778 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7781 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7782 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7784 if (TARGET_MIPS16_PCREL_LOADS
)
7786 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
7787 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
7791 mips_split_p
[SYMBOL_DTPREL
] = true;
7792 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7793 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7795 mips_split_p
[SYMBOL_TPREL
] = true;
7796 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7797 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7800 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7801 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7804 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7805 in context CONTEXT. RELOCS is the array of relocations to use. */
7808 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7809 const char **relocs
)
7811 enum mips_symbol_type symbol_type
;
7814 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7815 gcc_assert (relocs
[symbol_type
]);
7817 fputs (relocs
[symbol_type
], file
);
7818 output_addr_const (file
, mips_strip_unspec_address (op
));
7819 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7824 /* Start a new block with the given asm switch enabled. If we need
7825 to print a directive, emit PREFIX before it and SUFFIX after it. */
7828 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7829 const char *prefix
, const char *suffix
)
7831 if (asm_switch
->nesting_level
== 0)
7832 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
7833 asm_switch
->nesting_level
++;
7836 /* Likewise, but end a block. */
7839 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7840 const char *prefix
, const char *suffix
)
7842 gcc_assert (asm_switch
->nesting_level
);
7843 asm_switch
->nesting_level
--;
7844 if (asm_switch
->nesting_level
== 0)
7845 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
7848 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7849 that either print a complete line or print nothing. */
7852 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
7854 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
7858 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
7860 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
7863 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7864 The punctuation characters are:
7866 '(' Start a nested ".set noreorder" block.
7867 ')' End a nested ".set noreorder" block.
7868 '[' Start a nested ".set noat" block.
7869 ']' End a nested ".set noat" block.
7870 '<' Start a nested ".set nomacro" block.
7871 '>' End a nested ".set nomacro" block.
7872 '*' Behave like %(%< if generating a delayed-branch sequence.
7873 '#' Print a nop if in a ".set noreorder" block.
7874 '/' Like '#', but do nothing within a delayed-branch sequence.
7875 '?' Print "l" if mips_branch_likely is true
7876 '~' Print a nop if mips_branch_likely is true
7877 '.' Print the name of the register with a hard-wired zero (zero or $0).
7878 '@' Print the name of the assembler temporary register (at or $1).
7879 '^' Print the name of the pic call-through register (t9 or $25).
7880 '+' Print the name of the gp register (usually gp or $28).
7881 '$' Print the name of the stack pointer register (sp or $29).
7882 ':' Print "c" to use the compact version if the delay slot is a nop.
7883 '!' Print "s" to use the short version if the delay slot contains a
7886 See also mips_init_print_operand_pucnt. */
7889 mips_print_operand_punctuation (FILE *file
, int ch
)
7894 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
7898 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
7902 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
7906 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
7910 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
7914 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
7918 if (final_sequence
!= 0)
7920 mips_print_operand_punctuation (file
, '(');
7921 mips_print_operand_punctuation (file
, '<');
7926 if (mips_noreorder
.nesting_level
> 0)
7927 fputs ("\n\tnop", file
);
7931 /* Print an extra newline so that the delayed insn is separated
7932 from the following ones. This looks neater and is consistent
7933 with non-nop delayed sequences. */
7934 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
7935 fputs ("\n\tnop\n", file
);
7939 if (mips_branch_likely
)
7944 if (mips_branch_likely
)
7945 fputs ("\n\tnop", file
);
7949 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
7953 fputs (reg_names
[AT_REGNUM
], file
);
7957 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
7961 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
7965 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
7969 /* When final_sequence is 0, the delay slot will be a nop. We can
7970 use the compact version for microMIPS. */
7971 if (final_sequence
== 0)
7976 /* If the delay slot instruction is short, then use the
7978 if (final_sequence
== 0
7979 || get_attr_length (XVECEXP (final_sequence
, 0, 1)) == 2)
7989 /* Initialize mips_print_operand_punct. */
7992 mips_init_print_operand_punct (void)
7996 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
7997 mips_print_operand_punct
[(unsigned char) *p
] = true;
8000 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8001 associated with condition CODE. Print the condition part of the
8005 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8019 /* Conveniently, the MIPS names for these conditions are the same
8020 as their RTL equivalents. */
8021 fputs (GET_RTX_NAME (code
), file
);
8025 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8030 /* Likewise floating-point branches. */
8033 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8038 fputs ("c1f", file
);
8042 fputs ("c1t", file
);
8046 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8051 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8054 mips_print_operand_punct_valid_p (unsigned char code
)
8056 return mips_print_operand_punct
[code
];
8059 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8061 'X' Print CONST_INT OP in hexadecimal format.
8062 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8063 'd' Print CONST_INT OP in decimal.
8064 'm' Print one less than CONST_INT OP in decimal.
8065 'h' Print the high-part relocation associated with OP, after stripping
8067 'R' Print the low-part relocation associated with OP.
8068 'C' Print the integer branch condition for comparison OP.
8069 'N' Print the inverse of the integer branch condition for comparison OP.
8070 'F' Print the FPU branch condition for comparison OP.
8071 'W' Print the inverse of the FPU branch condition for comparison OP.
8072 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8073 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8074 't' Like 'T', but with the EQ/NE cases reversed
8075 'Y' Print mips_fp_conditions[INTVAL (OP)]
8076 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8077 'q' Print a DSP accumulator register.
8078 'D' Print the second part of a double-word register or memory operand.
8079 'L' Print the low-order register in a double-word register operand.
8080 'M' Print high-order register in a double-word register operand.
8081 'z' Print $0 if OP is zero, otherwise print OP normally.
8082 'b' Print the address of a memory operand, without offset. */
8085 mips_print_operand (FILE *file
, rtx op
, int letter
)
8089 if (mips_print_operand_punct_valid_p (letter
))
8091 mips_print_operand_punctuation (file
, letter
);
8096 code
= GET_CODE (op
);
8101 if (CONST_INT_P (op
))
8102 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8104 output_operand_lossage ("invalid use of '%%%c'", letter
);
8108 if (CONST_INT_P (op
))
8109 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8111 output_operand_lossage ("invalid use of '%%%c'", letter
);
8115 if (CONST_INT_P (op
))
8116 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8118 output_operand_lossage ("invalid use of '%%%c'", letter
);
8122 if (CONST_INT_P (op
))
8123 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
8125 output_operand_lossage ("invalid use of '%%%c'", letter
);
8131 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
8135 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
8139 mips_print_int_branch_condition (file
, code
, letter
);
8143 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
8147 mips_print_float_branch_condition (file
, code
, letter
);
8151 mips_print_float_branch_condition (file
, reverse_condition (code
),
8158 int truth
= (code
== NE
) == (letter
== 'T');
8159 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
8164 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
8165 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
8167 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8174 mips_print_operand (file
, op
, 0);
8180 if (code
== REG
&& MD_REG_P (REGNO (op
)))
8181 fprintf (file
, "$ac0");
8182 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
8183 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
8185 output_operand_lossage ("invalid use of '%%%c'", letter
);
8193 unsigned int regno
= REGNO (op
);
8194 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
8195 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
8198 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
8199 output_operand_lossage ("invalid use of '%%%c'", letter
);
8200 /* We need to print $0 .. $31 for COP0 registers. */
8201 if (COP0_REG_P (regno
))
8202 fprintf (file
, "$%s", ®_names
[regno
][4]);
8204 fprintf (file
, "%s", reg_names
[regno
]);
8210 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
8211 else if (letter
== 'b')
8213 gcc_assert (REG_P (XEXP (op
, 0)));
8214 mips_print_operand (file
, XEXP (op
, 0), 0);
8216 else if (letter
&& letter
!= 'z')
8217 output_operand_lossage ("invalid use of '%%%c'", letter
);
8219 output_address (XEXP (op
, 0));
8223 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
8224 fputs (reg_names
[GP_REG_FIRST
], file
);
8225 else if (letter
&& letter
!= 'z')
8226 output_operand_lossage ("invalid use of '%%%c'", letter
);
8227 else if (CONST_GP_P (op
))
8228 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
8230 output_addr_const (file
, mips_strip_unspec_address (op
));
8236 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8239 mips_print_operand_address (FILE *file
, rtx x
)
8241 struct mips_address_info addr
;
8243 if (mips_classify_address (&addr
, x
, word_mode
, true))
8247 mips_print_operand (file
, addr
.offset
, 0);
8248 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8251 case ADDRESS_LO_SUM
:
8252 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8254 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8257 case ADDRESS_CONST_INT
:
8258 output_addr_const (file
, x
);
8259 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8262 case ADDRESS_SYMBOLIC
:
8263 output_addr_const (file
, mips_strip_unspec_address (x
));
8269 /* Implement TARGET_ENCODE_SECTION_INFO. */
8272 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8274 default_encode_section_info (decl
, rtl
, first
);
8276 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8278 rtx symbol
= XEXP (rtl
, 0);
8279 tree type
= TREE_TYPE (decl
);
8281 /* Encode whether the symbol is short or long. */
8282 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8283 || mips_far_type_p (type
))
8284 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8288 /* Implement TARGET_SELECT_RTX_SECTION. */
8291 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
8292 unsigned HOST_WIDE_INT align
)
8294 /* ??? Consider using mergeable small data sections. */
8295 if (mips_rtx_constant_in_small_data_p (mode
))
8296 return get_named_section (NULL
, ".sdata", 0);
8298 return default_elf_select_rtx_section (mode
, x
, align
);
8301 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8303 The complication here is that, with the combination TARGET_ABICALLS
8304 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8305 absolute addresses, and should therefore not be included in the
8306 read-only part of a DSO. Handle such cases by selecting a normal
8307 data section instead of a read-only one. The logic apes that in
8308 default_function_rodata_section. */
8311 mips_function_rodata_section (tree decl
)
8313 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8314 return default_function_rodata_section (decl
);
8316 if (decl
&& DECL_SECTION_NAME (decl
))
8318 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8319 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8321 char *rname
= ASTRDUP (name
);
8323 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8325 else if (flag_function_sections
8326 && flag_data_sections
8327 && strncmp (name
, ".text.", 6) == 0)
8329 char *rname
= ASTRDUP (name
);
8330 memcpy (rname
+ 1, "data", 4);
8331 return get_section (rname
, SECTION_WRITE
, decl
);
8334 return data_section
;
8337 /* Implement TARGET_IN_SMALL_DATA_P. */
8340 mips_in_small_data_p (const_tree decl
)
8342 unsigned HOST_WIDE_INT size
;
8344 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8347 /* We don't yet generate small-data references for -mabicalls
8348 or VxWorks RTP code. See the related -G handling in
8349 mips_option_override. */
8350 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8353 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8357 /* Reject anything that isn't in a known small-data section. */
8358 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8359 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8362 /* If a symbol is defined externally, the assembler will use the
8363 usual -G rules when deciding how to implement macros. */
8364 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8367 else if (TARGET_EMBEDDED_DATA
)
8369 /* Don't put constants into the small data section: we want them
8370 to be in ROM rather than RAM. */
8371 if (TREE_CODE (decl
) != VAR_DECL
)
8374 if (TREE_READONLY (decl
)
8375 && !TREE_SIDE_EFFECTS (decl
)
8376 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8380 /* Enforce -mlocal-sdata. */
8381 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8384 /* Enforce -mextern-sdata. */
8385 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8387 if (DECL_EXTERNAL (decl
))
8389 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8393 /* We have traditionally not treated zero-sized objects as small data,
8394 so this is now effectively part of the ABI. */
8395 size
= int_size_in_bytes (TREE_TYPE (decl
));
8396 return size
> 0 && size
<= mips_small_data_threshold
;
8399 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8400 anchors for small data: the GP register acts as an anchor in that
8401 case. We also don't want to use them for PC-relative accesses,
8402 where the PC acts as an anchor. */
8405 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8407 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8409 case SYMBOL_PC_RELATIVE
:
8410 case SYMBOL_GP_RELATIVE
:
8414 return default_use_anchors_for_symbol_p (symbol
);
8418 /* The MIPS debug format wants all automatic variables and arguments
8419 to be in terms of the virtual frame pointer (stack pointer before
8420 any adjustment in the function), while the MIPS 3.0 linker wants
8421 the frame pointer to be the stack pointer after the initial
8422 adjustment. So, we do the adjustment here. The arg pointer (which
8423 is eliminated) points to the virtual frame pointer, while the frame
8424 pointer (which may be eliminated) points to the stack pointer after
8425 the initial adjustments. */
8428 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8430 rtx offset2
= const0_rtx
;
8431 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8434 offset
= INTVAL (offset2
);
8436 if (reg
== stack_pointer_rtx
8437 || reg
== frame_pointer_rtx
8438 || reg
== hard_frame_pointer_rtx
)
8440 offset
-= cfun
->machine
->frame
.total_size
;
8441 if (reg
== hard_frame_pointer_rtx
)
8442 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8448 /* Implement ASM_OUTPUT_EXTERNAL. */
8451 mips_output_external (FILE *file
, tree decl
, const char *name
)
8453 default_elf_asm_output_external (file
, decl
, name
);
8455 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8456 set in order to avoid putting out names that are never really
8458 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8460 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8462 /* When using assembler macros, emit .extern directives for
8463 all small-data externs so that the assembler knows how
8466 In most cases it would be safe (though pointless) to emit
8467 .externs for other symbols too. One exception is when an
8468 object is within the -G limit but declared by the user to
8469 be in a section other than .sbss or .sdata. */
8470 fputs ("\t.extern\t", file
);
8471 assemble_name (file
, name
);
8472 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8473 int_size_in_bytes (TREE_TYPE (decl
)));
8478 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8481 mips_output_filename (FILE *stream
, const char *name
)
8483 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8485 if (write_symbols
== DWARF2_DEBUG
)
8487 else if (mips_output_filename_first_time
)
8489 mips_output_filename_first_time
= 0;
8490 num_source_filenames
+= 1;
8491 current_function_file
= name
;
8492 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8493 output_quoted_string (stream
, name
);
8494 putc ('\n', stream
);
8496 /* If we are emitting stabs, let dbxout.c handle this (except for
8497 the mips_output_filename_first_time case). */
8498 else if (write_symbols
== DBX_DEBUG
)
8500 else if (name
!= current_function_file
8501 && strcmp (name
, current_function_file
) != 0)
8503 num_source_filenames
+= 1;
8504 current_function_file
= name
;
8505 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8506 output_quoted_string (stream
, name
);
8507 putc ('\n', stream
);
8511 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8513 static void ATTRIBUTE_UNUSED
8514 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8519 fputs ("\t.dtprelword\t", file
);
8523 fputs ("\t.dtpreldword\t", file
);
8529 output_addr_const (file
, x
);
8530 fputs ("+0x8000", file
);
8533 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8536 mips_dwarf_register_span (rtx reg
)
8539 enum machine_mode mode
;
8541 /* By default, GCC maps increasing register numbers to increasing
8542 memory locations, but paired FPRs are always little-endian,
8543 regardless of the prevailing endianness. */
8544 mode
= GET_MODE (reg
);
8545 if (FP_REG_P (REGNO (reg
))
8546 && TARGET_BIG_ENDIAN
8547 && MAX_FPRS_PER_FMT
> 1
8548 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8550 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8551 high
= mips_subword (reg
, true);
8552 low
= mips_subword (reg
, false);
8553 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8559 /* DSP ALU can bypass data with no delays for the following pairs. */
8560 enum insn_code dspalu_bypass_table
[][2] =
8562 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
8563 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
8564 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
8565 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
8566 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
8567 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
8568 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
8569 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
8573 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
8576 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
8577 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
8578 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
8580 for (i
= 0; i
< num_bypass
; i
++)
8582 if (out_icode
== dspalu_bypass_table
[i
][0]
8583 && in_icode
== dspalu_bypass_table
[i
][1])
8589 /* Implement ASM_OUTPUT_ASCII. */
8592 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8598 fprintf (stream
, "\t.ascii\t\"");
8599 for (i
= 0; i
< len
; i
++)
8603 c
= (unsigned char) string
[i
];
8606 if (c
== '\\' || c
== '\"')
8608 putc ('\\', stream
);
8616 fprintf (stream
, "\\%03o", c
);
8620 if (cur_pos
> 72 && i
+1 < len
)
8623 fprintf (stream
, "\"\n\t.ascii\t\"");
8626 fprintf (stream
, "\"\n");
8629 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8630 Update *ADDR with the operand that should be printed. */
8633 mips_output_tls_reloc_directive (rtx
*addr
)
8635 enum mips_symbol_type type
;
8637 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
8638 *addr
= mips_strip_unspec_address (*addr
);
8642 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
8645 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
8652 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8653 macros, mark the symbol as written so that mips_asm_output_external
8654 won't emit an .extern for it. STREAM is the output file, NAME is the
8655 name of the symbol, INIT_STRING is the string that should be written
8656 before the symbol and FINAL_STRING is the string that should be
8657 written after it. FINAL_STRING is a printf format that consumes the
8658 remaining arguments. */
8661 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
8662 const char *final_string
, ...)
8666 fputs (init_string
, stream
);
8667 assemble_name (stream
, name
);
8668 va_start (ap
, final_string
);
8669 vfprintf (stream
, final_string
, ap
);
8672 if (!TARGET_EXPLICIT_RELOCS
)
8674 tree name_tree
= get_identifier (name
);
8675 TREE_ASM_WRITTEN (name_tree
) = 1;
8679 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8680 NAME is the name of the object and ALIGN is the required alignment
8681 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8682 alignment argument. */
8685 mips_declare_common_object (FILE *stream
, const char *name
,
8686 const char *init_string
,
8687 unsigned HOST_WIDE_INT size
,
8688 unsigned int align
, bool takes_alignment_p
)
8690 if (!takes_alignment_p
)
8692 size
+= (align
/ BITS_PER_UNIT
) - 1;
8693 size
-= size
% (align
/ BITS_PER_UNIT
);
8694 mips_declare_object (stream
, name
, init_string
,
8695 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8698 mips_declare_object (stream
, name
, init_string
,
8699 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
8700 size
, align
/ BITS_PER_UNIT
);
8703 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8704 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8707 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8708 unsigned HOST_WIDE_INT size
,
8711 /* If the target wants uninitialized const declarations in
8712 .rdata then don't put them in .comm. */
8713 if (TARGET_EMBEDDED_DATA
8714 && TARGET_UNINIT_CONST_IN_RODATA
8715 && TREE_CODE (decl
) == VAR_DECL
8716 && TREE_READONLY (decl
)
8717 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8719 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8720 targetm
.asm_out
.globalize_label (stream
, name
);
8722 switch_to_section (readonly_data_section
);
8723 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8724 mips_declare_object (stream
, name
, "",
8725 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8729 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8733 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8734 extern int size_directive_output
;
8736 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8737 definitions except that it uses mips_declare_object to emit the label. */
8740 mips_declare_object_name (FILE *stream
, const char *name
,
8741 tree decl ATTRIBUTE_UNUSED
)
8743 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8744 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8747 size_directive_output
= 0;
8748 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8752 size_directive_output
= 1;
8753 size
= int_size_in_bytes (TREE_TYPE (decl
));
8754 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8757 mips_declare_object (stream
, name
, "", ":\n");
8760 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8763 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8767 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8768 if (!flag_inhibit_size_directive
8769 && DECL_SIZE (decl
) != 0
8772 && DECL_INITIAL (decl
) == error_mark_node
8773 && !size_directive_output
)
8777 size_directive_output
= 1;
8778 size
= int_size_in_bytes (TREE_TYPE (decl
));
8779 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8784 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8785 with the current ABI. */
8788 mips_mdebug_abi_name (void)
8801 return TARGET_64BIT
? "eabi64" : "eabi32";
8807 /* Implement TARGET_ASM_FILE_START. */
8810 mips_file_start (void)
8812 default_file_start ();
8814 /* Generate a special section to describe the ABI switches used to
8815 produce the resultant binary. */
8817 /* Record the ABI itself. Modern versions of binutils encode
8818 this information in the ELF header flags, but GDB needs the
8819 information in order to correctly debug binaries produced by
8820 older binutils. See the function mips_gdbarch_init in
8822 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8823 mips_mdebug_abi_name ());
8825 /* There is no ELF header flag to distinguish long32 forms of the
8826 EABI from long64 forms. Emit a special section to help tools
8827 such as GDB. Do the same for o64, which is sometimes used with
8829 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
8830 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
8831 "\t.previous\n", TARGET_LONG64
? 64 : 32);
8833 #ifdef HAVE_AS_GNU_ATTRIBUTE
8837 /* No floating-point operations, -mno-float. */
8838 if (TARGET_NO_FLOAT
)
8840 /* Soft-float code, -msoft-float. */
8841 else if (!TARGET_HARD_FLOAT_ABI
)
8843 /* Single-float code, -msingle-float. */
8844 else if (!TARGET_DOUBLE_FLOAT
)
8846 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8847 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
8849 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8853 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
8857 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8858 if (TARGET_ABICALLS
)
8860 fprintf (asm_out_file
, "\t.abicalls\n");
8861 if (TARGET_ABICALLS_PIC0
)
8862 fprintf (asm_out_file
, "\t.option\tpic0\n");
8865 if (flag_verbose_asm
)
8866 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8868 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
8871 /* Implement TARGET_ASM_CODE_END. */
8874 mips_code_end (void)
8876 if (mips_need_mips16_rdhwr_p
)
8877 mips_output_mips16_rdhwr ();
8880 /* Make the last instruction frame-related and note that it performs
8881 the operation described by FRAME_PATTERN. */
8884 mips_set_frame_expr (rtx frame_pattern
)
8888 insn
= get_last_insn ();
8889 RTX_FRAME_RELATED_P (insn
) = 1;
8890 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8895 /* Return a frame-related rtx that stores REG at MEM.
8896 REG must be a single register. */
8899 mips_frame_set (rtx mem
, rtx reg
)
8903 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
8904 RTX_FRAME_RELATED_P (set
) = 1;
8909 /* Record that the epilogue has restored call-saved register REG. */
8912 mips_add_cfa_restore (rtx reg
)
8914 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
8915 mips_epilogue
.cfa_restores
);
8918 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8919 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8920 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8921 static const unsigned char mips16e_s2_s8_regs
[] = {
8922 30, 23, 22, 21, 20, 19, 18
8924 static const unsigned char mips16e_a0_a3_regs
[] = {
8928 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8929 ordered from the uppermost in memory to the lowest in memory. */
8930 static const unsigned char mips16e_save_restore_regs
[] = {
8931 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8934 /* Return the index of the lowest X in the range [0, SIZE) for which
8935 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8938 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
8943 for (i
= 0; i
< size
; i
++)
8944 if (BITSET_P (mask
, regs
[i
]))
8950 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8951 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8952 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8953 is true for all indexes (X, SIZE). */
8956 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
8957 unsigned int size
, unsigned int *num_regs_ptr
)
8961 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
8962 for (i
++; i
< size
; i
++)
8963 if (!BITSET_P (*mask_ptr
, regs
[i
]))
8966 *mask_ptr
|= 1 << regs
[i
];
8970 /* Return a simplified form of X using the register values in REG_VALUES.
8971 REG_VALUES[R] is the last value assigned to hard register R, or null
8972 if R has not been modified.
8974 This function is rather limited, but is good enough for our purposes. */
8977 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
8979 x
= avoid_constant_pool_reference (x
);
8983 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8984 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
8985 x0
, GET_MODE (XEXP (x
, 0)));
8988 if (ARITHMETIC_P (x
))
8990 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8991 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
8992 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
8996 && reg_values
[REGNO (x
)]
8997 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
8998 return reg_values
[REGNO (x
)];
9003 /* Return true if (set DEST SRC) stores an argument register into its
9004 caller-allocated save slot, storing the number of that argument
9005 register in *REGNO_PTR if so. REG_VALUES is as for
9006 mips16e_collect_propagate_value. */
9009 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
9010 unsigned int *regno_ptr
)
9012 unsigned int argno
, regno
;
9013 HOST_WIDE_INT offset
, required_offset
;
9016 /* Check that this is a word-mode store. */
9017 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
9020 /* Check that the register being saved is an unmodified argument
9022 regno
= REGNO (src
);
9023 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
9025 argno
= regno
- GP_ARG_FIRST
;
9027 /* Check whether the address is an appropriate stack-pointer or
9028 frame-pointer access. */
9029 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
9030 mips_split_plus (addr
, &base
, &offset
);
9031 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
9032 if (base
== hard_frame_pointer_rtx
)
9033 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9034 else if (base
!= stack_pointer_rtx
)
9036 if (offset
!= required_offset
)
9043 /* A subroutine of mips_expand_prologue, called only when generating
9044 MIPS16e SAVE instructions. Search the start of the function for any
9045 instructions that save argument registers into their caller-allocated
9046 save slots. Delete such instructions and return a value N such that
9047 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9048 instructions redundant. */
9051 mips16e_collect_argument_saves (void)
9053 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
9054 rtx insn
, next
, set
, dest
, src
;
9055 unsigned int nargs
, regno
;
9057 push_topmost_sequence ();
9059 memset (reg_values
, 0, sizeof (reg_values
));
9060 for (insn
= get_insns (); insn
; insn
= next
)
9062 next
= NEXT_INSN (insn
);
9063 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
9069 set
= PATTERN (insn
);
9070 if (GET_CODE (set
) != SET
)
9073 dest
= SET_DEST (set
);
9074 src
= SET_SRC (set
);
9075 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
9077 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
9080 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
9083 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
9084 reg_values
[REGNO (dest
)]
9085 = mips16e_collect_propagate_value (src
, reg_values
);
9089 pop_topmost_sequence ();
9094 /* Return a move between register REGNO and memory location SP + OFFSET.
9095 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9096 Make the move a load if RESTORE_P, otherwise make it a store. */
9099 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
9100 HOST_WIDE_INT offset
, unsigned int regno
)
9104 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
9106 reg
= gen_rtx_REG (SImode
, regno
);
9109 mips_add_cfa_restore (reg
);
9110 return gen_rtx_SET (VOIDmode
, reg
, mem
);
9113 return gen_rtx_SET (VOIDmode
, mem
, reg
);
9114 return mips_frame_set (mem
, reg
);
9117 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9118 The instruction must:
9120 - Allocate or deallocate SIZE bytes in total; SIZE is known
9123 - Save or restore as many registers in *MASK_PTR as possible.
9124 The instruction saves the first registers at the top of the
9125 allocated area, with the other registers below it.
9127 - Save NARGS argument registers above the allocated area.
9129 (NARGS is always zero if RESTORE_P.)
9131 The SAVE and RESTORE instructions cannot save and restore all general
9132 registers, so there may be some registers left over for the caller to
9133 handle. Destructively modify *MASK_PTR so that it contains the registers
9134 that still need to be saved or restored. The caller can save these
9135 registers in the memory immediately below *OFFSET_PTR, which is a
9136 byte offset from the bottom of the allocated stack area. */
9139 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
9140 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
9144 HOST_WIDE_INT offset
, top_offset
;
9145 unsigned int i
, regno
;
9148 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
9150 /* Calculate the number of elements in the PARALLEL. We need one element
9151 for the stack adjustment, one for each argument register save, and one
9152 for each additional register move. */
9154 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9155 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
9158 /* Create the final PARALLEL. */
9159 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
9162 /* Add the stack pointer adjustment. */
9163 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9164 plus_constant (Pmode
, stack_pointer_rtx
,
9165 restore_p
? size
: -size
));
9166 RTX_FRAME_RELATED_P (set
) = 1;
9167 XVECEXP (pattern
, 0, n
++) = set
;
9169 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9170 top_offset
= restore_p
? size
: 0;
9172 /* Save the arguments. */
9173 for (i
= 0; i
< nargs
; i
++)
9175 offset
= top_offset
+ i
* UNITS_PER_WORD
;
9176 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
9178 XVECEXP (pattern
, 0, n
++) = set
;
9181 /* Then fill in the other register moves. */
9182 offset
= top_offset
;
9183 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9185 regno
= mips16e_save_restore_regs
[i
];
9186 if (BITSET_P (*mask_ptr
, regno
))
9188 offset
-= UNITS_PER_WORD
;
9189 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
9190 XVECEXP (pattern
, 0, n
++) = set
;
9191 *mask_ptr
&= ~(1 << regno
);
9195 /* Tell the caller what offset it should use for the remaining registers. */
9196 *offset_ptr
= size
+ (offset
- top_offset
);
9198 gcc_assert (n
== XVECLEN (pattern
, 0));
9203 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9204 pointer. Return true if PATTERN matches the kind of instruction
9205 generated by mips16e_build_save_restore. If INFO is nonnull,
9206 initialize it when returning true. */
9209 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
9210 struct mips16e_save_restore_info
*info
)
9212 unsigned int i
, nargs
, mask
, extra
;
9213 HOST_WIDE_INT top_offset
, save_offset
, offset
;
9214 rtx set
, reg
, mem
, base
;
9217 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
9220 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9221 top_offset
= adjust
> 0 ? adjust
: 0;
9223 /* Interpret all other members of the PARALLEL. */
9224 save_offset
= top_offset
- UNITS_PER_WORD
;
9228 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
9230 /* Check that we have a SET. */
9231 set
= XVECEXP (pattern
, 0, n
);
9232 if (GET_CODE (set
) != SET
)
9235 /* Check that the SET is a load (if restoring) or a store
9237 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
9241 /* Check that the address is the sum of the stack pointer and a
9242 possibly-zero constant offset. */
9243 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
9244 if (base
!= stack_pointer_rtx
)
9247 /* Check that SET's other operand is a register. */
9248 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
9252 /* Check for argument saves. */
9253 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
9254 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
9256 else if (offset
== save_offset
)
9258 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
9259 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
9262 mask
|= 1 << REGNO (reg
);
9263 save_offset
-= UNITS_PER_WORD
;
9269 /* Check that the restrictions on register ranges are met. */
9271 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
9272 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
9273 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
9274 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
9278 /* Make sure that the topmost argument register is not saved twice.
9279 The checks above ensure that the same is then true for the other
9280 argument registers. */
9281 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9284 /* Pass back information, if requested. */
9287 info
->nargs
= nargs
;
9289 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9295 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9296 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9297 the null terminator. */
9300 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9301 unsigned int max_reg
)
9303 if (min_reg
!= max_reg
)
9304 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9306 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9310 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9311 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9314 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9316 static char buffer
[300];
9318 struct mips16e_save_restore_info info
;
9319 unsigned int i
, end
;
9322 /* Parse the pattern. */
9323 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9326 /* Add the mnemonic. */
9327 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9330 /* Save the arguments. */
9332 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9333 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9334 else if (info
.nargs
== 1)
9335 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9337 /* Emit the amount of stack space to allocate or deallocate. */
9338 s
+= sprintf (s
, "%d", (int) info
.size
);
9340 /* Save or restore $16. */
9341 if (BITSET_P (info
.mask
, 16))
9342 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9344 /* Save or restore $17. */
9345 if (BITSET_P (info
.mask
, 17))
9346 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9348 /* Save or restore registers in the range $s2...$s8, which
9349 mips16e_s2_s8_regs lists in decreasing order. Note that this
9350 is a software register range; the hardware registers are not
9351 numbered consecutively. */
9352 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9353 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9355 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9356 mips16e_s2_s8_regs
[i
]);
9358 /* Save or restore registers in the range $a0...$a3. */
9359 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9360 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9362 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9363 mips16e_a0_a3_regs
[end
- 1]);
9365 /* Save or restore $31. */
9366 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9367 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9372 /* Return true if the current function returns its value in a floating-point
9373 register in MIPS16 mode. */
9376 mips16_cfun_returns_in_fpr_p (void)
9378 tree return_type
= DECL_RESULT (current_function_decl
);
9379 return (TARGET_MIPS16
9380 && TARGET_HARD_FLOAT_ABI
9381 && !aggregate_value_p (return_type
, current_function_decl
)
9382 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9385 /* Return true if predicate PRED is true for at least one instruction.
9386 Cache the result in *CACHE, and assume that the result is true
9387 if *CACHE is already true. */
9390 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx
))
9396 push_topmost_sequence ();
9397 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9398 if (USEFUL_INSN_P (insn
) && pred (insn
))
9403 pop_topmost_sequence ();
9408 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9409 See mips_cfun_has_inflexible_gp_ref_p for details. */
9412 mips_insn_has_inflexible_gp_ref_p (rtx insn
)
9414 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9415 indicate that the target could be a traditional MIPS
9416 lazily-binding stub. */
9417 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9420 /* Return true if the current function refers to the global pointer
9421 in a way that forces $28 to be valid. This means that we can't
9422 change the choice of global pointer, even for NewABI code.
9424 One example of this (and one which needs several checks) is that
9425 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9426 (This restriction does not apply to PLTs.) */
9429 mips_cfun_has_inflexible_gp_ref_p (void)
9431 /* If the function has a nonlocal goto, $28 must hold the correct
9432 global pointer for the target function. That is, the target
9433 of the goto implicitly uses $28. */
9434 if (crtl
->has_nonlocal_goto
)
9437 if (TARGET_ABICALLS_PIC2
)
9439 /* Symbolic accesses implicitly use the global pointer unless
9440 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9441 might go to traditional MIPS lazy-binding stubs. */
9442 if (!TARGET_EXPLICIT_RELOCS
)
9445 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9446 can be lazily-bound. */
9450 /* MIPS16 functions that return in FPRs need to call an
9451 external libgcc routine. This call is only made explict
9452 during mips_expand_epilogue, and it too might be lazily bound. */
9453 if (mips16_cfun_returns_in_fpr_p ())
9457 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9458 mips_insn_has_inflexible_gp_ref_p
);
9461 /* Return true if INSN refers to the global pointer in a "flexible" way.
9462 See mips_cfun_has_flexible_gp_ref_p for details. */
9465 mips_insn_has_flexible_gp_ref_p (rtx insn
)
9467 return (get_attr_got (insn
) != GOT_UNSET
9468 || mips_small_data_pattern_p (PATTERN (insn
))
9469 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9472 /* Return true if the current function references the global pointer,
9473 but if those references do not inherently require the global pointer
9474 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9477 mips_cfun_has_flexible_gp_ref_p (void)
9479 /* Reload can sometimes introduce constant pool references
9480 into a function that otherwise didn't need them. For example,
9481 suppose we have an instruction like:
9483 (set (reg:DF R1) (float:DF (reg:SI R2)))
9485 If R2 turns out to be a constant such as 1, the instruction may
9486 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9487 the option of using this constant if R2 doesn't get allocated
9490 In cases like these, reload will have added the constant to the
9491 pool but no instruction will yet refer to it. */
9492 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9495 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9496 mips_insn_has_flexible_gp_ref_p
);
9499 /* Return the register that should be used as the global pointer
9500 within this function. Return INVALID_REGNUM if the function
9501 doesn't need a global pointer. */
9504 mips_global_pointer (void)
9508 /* $gp is always available unless we're using a GOT. */
9509 if (!TARGET_USE_GOT
)
9510 return GLOBAL_POINTER_REGNUM
;
9512 /* If there are inflexible references to $gp, we must use the
9513 standard register. */
9514 if (mips_cfun_has_inflexible_gp_ref_p ())
9515 return GLOBAL_POINTER_REGNUM
;
9517 /* If there are no current references to $gp, then the only uses
9518 we can introduce later are those involved in long branches. */
9519 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9520 return INVALID_REGNUM
;
9522 /* If the global pointer is call-saved, try to use a call-clobbered
9524 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9525 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9526 if (!df_regs_ever_live_p (regno
)
9527 && call_really_used_regs
[regno
]
9528 && !fixed_regs
[regno
]
9529 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9532 return GLOBAL_POINTER_REGNUM
;
9535 /* Return true if the current function's prologue must load the global
9536 pointer value into pic_offset_table_rtx and store the same value in
9537 the function's cprestore slot (if any).
9539 One problem we have to deal with is that, when emitting GOT-based
9540 position independent code, long-branch sequences will need to load
9541 the address of the branch target from the GOT. We don't know until
9542 the very end of compilation whether (and where) the function needs
9543 long branches, so we must ensure that _any_ branch can access the
9544 global pointer in some form. However, we do not want to pessimize
9545 the usual case in which all branches are short.
9547 We handle this as follows:
9549 (1) During reload, we set cfun->machine->global_pointer to
9550 INVALID_REGNUM if we _know_ that the current function
9551 doesn't need a global pointer. This is only valid if
9552 long branches don't need the GOT.
9554 Otherwise, we assume that we might need a global pointer
9555 and pick an appropriate register.
9557 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9558 we ensure that the global pointer is available at every
9559 block boundary bar entry and exit. We do this in one of two ways:
9561 - If the function has a cprestore slot, we ensure that this
9562 slot is valid at every branch. However, as explained in
9563 point (6) below, there is no guarantee that pic_offset_table_rtx
9564 itself is valid if new uses of the global pointer are introduced
9565 after the first post-epilogue split.
9567 We guarantee that the cprestore slot is valid by loading it
9568 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9569 this register live at every block boundary bar function entry
9570 and exit. It is then invalid to move the load (and thus the
9571 preceding store) across a block boundary.
9573 - If the function has no cprestore slot, we guarantee that
9574 pic_offset_table_rtx itself is valid at every branch.
9576 See mips_eh_uses for the handling of the register liveness.
9578 (3) During prologue and epilogue generation, we emit "ghost"
9579 placeholder instructions to manipulate the global pointer.
9581 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9582 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9583 that the function needs a global pointer. (There is no need to set
9584 them earlier than this, and doing it as late as possible leads to
9585 fewer false positives.)
9587 (5) If cfun->machine->must_initialize_gp_p is true during a
9588 split_insns pass, we split the ghost instructions into real
9589 instructions. These split instructions can then be optimized in
9590 the usual way. Otherwise, we keep the ghost instructions intact,
9591 and optimize for the case where they aren't needed. We still
9592 have the option of splitting them later, if we need to introduce
9593 new uses of the global pointer.
9595 For example, the scheduler ignores a ghost instruction that
9596 stores $28 to the stack, but it handles the split form of
9597 the ghost instruction as an ordinary store.
9599 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9600 is true during the first post-epilogue split_insns pass, we split
9601 calls and restore_gp patterns into instructions that explicitly
9602 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9603 we split these patterns into instructions that _don't_ load from
9606 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9607 time of the split, then any instructions that exist at that time
9608 can make free use of pic_offset_table_rtx. However, if we want
9609 to introduce new uses of the global pointer after the split,
9610 we must explicitly load the value from the cprestore slot, since
9611 pic_offset_table_rtx itself might not be valid at a given point
9614 The idea is that we want to be able to delete redundant
9615 loads from the cprestore slot in the usual case where no
9616 long branches are needed.
9618 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9619 of md_reorg, we decide whether the global pointer is needed for
9620 long branches. If so, we set cfun->machine->must_initialize_gp_p
9621 to true and split the ghost instructions into real instructions
9624 Note that the ghost instructions must have a zero length for three reasons:
9626 - Giving the length of the underlying $gp sequence might cause
9627 us to use long branches in cases where they aren't really needed.
9629 - They would perturb things like alignment calculations.
9631 - More importantly, the hazard detection in md_reorg relies on
9632 empty instructions having a zero length.
9634 If we find a long branch and split the ghost instructions at the
9635 end of md_reorg, the split could introduce more long branches.
9636 That isn't a problem though, because we still do the split before
9637 the final shorten_branches pass.
9639 This is extremely ugly, but it seems like the best compromise between
9640 correctness and efficiency. */
9643 mips_must_initialize_gp_p (void)
9645 return cfun
->machine
->must_initialize_gp_p
;
9648 /* Return true if REGNO is a register that is ordinarily call-clobbered
9649 but must nevertheless be preserved by an interrupt handler. */
9652 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
9654 if (MD_REG_P (regno
))
9657 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
9660 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
9662 /* $0 is hard-wired. */
9663 if (regno
== GP_REG_FIRST
)
9666 /* The interrupt handler can treat kernel registers as
9667 scratch registers. */
9668 if (KERNEL_REG_P (regno
))
9671 /* The function will return the stack pointer to its original value
9673 if (regno
== STACK_POINTER_REGNUM
)
9676 /* Otherwise, return true for registers that aren't ordinarily
9678 return call_really_used_regs
[regno
];
9684 /* Return true if the current function should treat register REGNO
9688 mips_cfun_call_saved_reg_p (unsigned int regno
)
9690 /* If the user makes an ordinarily-call-saved register global,
9691 that register is no longer call-saved. */
9692 if (global_regs
[regno
])
9695 /* Interrupt handlers need to save extra registers. */
9696 if (cfun
->machine
->interrupt_handler_p
9697 && mips_interrupt_extra_call_saved_reg_p (regno
))
9700 /* call_insns preserve $28 unless they explicitly say otherwise,
9701 so call_really_used_regs[] treats $28 as call-saved. However,
9702 we want the ABI property rather than the default call_insn
9704 return (regno
== GLOBAL_POINTER_REGNUM
9705 ? TARGET_CALL_SAVED_GP
9706 : !call_really_used_regs
[regno
]);
9709 /* Return true if the function body might clobber register REGNO.
9710 We know that REGNO is call-saved. */
9713 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
9715 /* Some functions should be treated as clobbering all call-saved
9717 if (crtl
->saves_all_registers
)
9720 /* DF handles cases where a register is explicitly referenced in
9721 the rtl. Incoming values are passed in call-clobbered registers,
9722 so we can assume that any live call-saved register is set within
9724 if (df_regs_ever_live_p (regno
))
9727 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9728 These clobbers are not explicit in the rtl. */
9729 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9732 /* If we're using a call-saved global pointer, the function's
9733 prologue will need to set it up. */
9734 if (cfun
->machine
->global_pointer
== regno
)
9737 /* The function's prologue will need to set the frame pointer if
9738 frame_pointer_needed. */
9739 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9742 /* If a MIPS16 function returns a value in FPRs, its epilogue
9743 will need to call an external libgcc routine. This yet-to-be
9744 generated call_insn will clobber $31. */
9745 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9748 /* If REGNO is ordinarily call-clobbered, we must assume that any
9749 called function could modify it. */
9750 if (cfun
->machine
->interrupt_handler_p
9752 && mips_interrupt_extra_call_saved_reg_p (regno
))
9758 /* Return true if the current function must save register REGNO. */
9761 mips_save_reg_p (unsigned int regno
)
9763 if (mips_cfun_call_saved_reg_p (regno
))
9765 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9768 /* Save both registers in an FPR pair if either one is used. This is
9769 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9770 register to be used without the even register. */
9771 if (FP_REG_P (regno
)
9772 && MAX_FPRS_PER_FMT
== 2
9773 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9777 /* We need to save the incoming return address if __builtin_eh_return
9778 is being used to set a different return address. */
9779 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9785 /* Populate the current function's mips_frame_info structure.
9787 MIPS stack frames look like:
9789 +-------------------------------+
9791 | incoming stack arguments |
9793 +-------------------------------+
9795 | caller-allocated save area |
9796 A | for register arguments |
9798 +-------------------------------+ <-- incoming stack pointer
9800 | callee-allocated save area |
9801 B | for arguments that are |
9802 | split between registers and |
9805 +-------------------------------+ <-- arg_pointer_rtx
9807 C | callee-allocated save area |
9808 | for register varargs |
9810 +-------------------------------+ <-- frame_pointer_rtx
9811 | | + cop0_sp_offset
9812 | COP0 reg save area | + UNITS_PER_WORD
9814 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9815 | | + UNITS_PER_WORD
9816 | accumulator save area |
9818 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9819 | | + UNITS_PER_HWFPVALUE
9822 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9823 | | + UNITS_PER_WORD
9826 +-------------------------------+ <-- frame_pointer_rtx with
9827 | | \ -fstack-protector
9828 | local variables | | var_size
9830 +-------------------------------+
9832 | $gp save area | | cprestore_size
9834 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9836 | outgoing stack arguments | |
9838 +-------------------------------+ | args_size
9840 | caller-allocated save area | |
9841 | for register arguments | |
9843 +-------------------------------+ <-- stack_pointer_rtx
9844 frame_pointer_rtx without
9846 hard_frame_pointer_rtx for
9849 At least two of A, B and C will be empty.
9851 Dynamic stack allocations such as alloca insert data at point P.
9852 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9853 hard_frame_pointer_rtx unchanged. */
9856 mips_compute_frame_info (void)
9858 struct mips_frame_info
*frame
;
9859 HOST_WIDE_INT offset
, size
;
9860 unsigned int regno
, i
;
9862 /* Set this function's interrupt properties. */
9863 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
9866 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9867 else if (TARGET_HARD_FLOAT
)
9868 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9869 else if (TARGET_MIPS16
)
9870 error ("interrupt handlers cannot be MIPS16 functions");
9873 cfun
->machine
->interrupt_handler_p
= true;
9874 cfun
->machine
->use_shadow_register_set_p
=
9875 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
9876 cfun
->machine
->keep_interrupts_masked_p
=
9877 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
9878 cfun
->machine
->use_debug_exception_return_p
=
9879 mips_use_debug_exception_return_p (TREE_TYPE
9880 (current_function_decl
));
9884 frame
= &cfun
->machine
->frame
;
9885 memset (frame
, 0, sizeof (*frame
));
9886 size
= get_frame_size ();
9888 cfun
->machine
->global_pointer
= mips_global_pointer ();
9890 /* The first two blocks contain the outgoing argument area and the $gp save
9891 slot. This area isn't needed in leaf functions, but if the
9892 target-independent frame size is nonzero, we have already committed to
9893 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9894 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
9896 /* The MIPS 3.0 linker does not like functions that dynamically
9897 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9898 looks like we are trying to create a second frame pointer to the
9899 function, so allocate some stack space to make it happy. */
9900 if (cfun
->calls_alloca
)
9901 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
9903 frame
->args_size
= 0;
9904 frame
->cprestore_size
= 0;
9908 frame
->args_size
= crtl
->outgoing_args_size
;
9909 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
9911 offset
= frame
->args_size
+ frame
->cprestore_size
;
9913 /* Move above the local variables. */
9914 frame
->var_size
= MIPS_STACK_ALIGN (size
);
9915 offset
+= frame
->var_size
;
9917 /* Find out which GPRs we need to save. */
9918 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9919 if (mips_save_reg_p (regno
))
9922 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
9925 /* If this function calls eh_return, we must also save and restore the
9926 EH data registers. */
9927 if (crtl
->calls_eh_return
)
9928 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
9931 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
9934 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9935 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9936 save all later registers too. */
9937 if (GENERATE_MIPS16E_SAVE_RESTORE
)
9939 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
9940 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
9941 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
9942 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
9945 /* Move above the GPR save area. */
9946 if (frame
->num_gp
> 0)
9948 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
9949 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
9952 /* Find out which FPRs we need to save. This loop must iterate over
9953 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9954 if (TARGET_HARD_FLOAT
)
9955 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
9956 if (mips_save_reg_p (regno
))
9958 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
9959 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
9962 /* Move above the FPR save area. */
9963 if (frame
->num_fp
> 0)
9965 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
9966 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
9969 /* Add in space for the interrupt context information. */
9970 if (cfun
->machine
->interrupt_handler_p
)
9973 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
9976 frame
->acc_mask
|= (1 << 0);
9979 /* Check accumulators 1, 2, 3. */
9980 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
9981 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
9984 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
9987 /* All interrupt context functions need space to preserve STATUS. */
9988 frame
->num_cop0_regs
++;
9990 /* If we don't keep interrupts masked, we need to save EPC. */
9991 if (!cfun
->machine
->keep_interrupts_masked_p
)
9992 frame
->num_cop0_regs
++;
9995 /* Move above the accumulator save area. */
9996 if (frame
->num_acc
> 0)
9998 /* Each accumulator needs 2 words. */
9999 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
10000 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
10003 /* Move above the COP0 register save area. */
10004 if (frame
->num_cop0_regs
> 0)
10006 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
10007 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
10010 /* Move above the callee-allocated varargs save area. */
10011 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
10012 frame
->arg_pointer_offset
= offset
;
10014 /* Move above the callee-allocated area for pretend stack arguments. */
10015 offset
+= crtl
->args
.pretend_args_size
;
10016 frame
->total_size
= offset
;
10018 /* Work out the offsets of the save areas from the top of the frame. */
10019 if (frame
->gp_sp_offset
> 0)
10020 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
10021 if (frame
->fp_sp_offset
> 0)
10022 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
10023 if (frame
->acc_sp_offset
> 0)
10024 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
10025 if (frame
->num_cop0_regs
> 0)
10026 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
10028 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10029 arguments. This tends to increase the chances of using unextended
10030 instructions for local variables and incoming arguments. */
10032 frame
->hard_frame_pointer_offset
= frame
->args_size
;
10035 /* Return the style of GP load sequence that is being used for the
10036 current function. */
10038 enum mips_loadgp_style
10039 mips_current_loadgp_style (void)
10041 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
10042 return LOADGP_NONE
;
10044 if (TARGET_RTP_PIC
)
10047 if (TARGET_ABSOLUTE_ABICALLS
)
10048 return LOADGP_ABSOLUTE
;
10050 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
10053 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10056 mips_frame_pointer_required (void)
10058 /* If the function contains dynamic stack allocations, we need to
10059 use the frame pointer to access the static parts of the frame. */
10060 if (cfun
->calls_alloca
)
10063 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10064 reload may be unable to compute the address of a local variable,
10065 since there is no way to add a large constant to the stack pointer
10066 without using a second temporary register. */
10069 mips_compute_frame_info ();
10070 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
10077 /* Make sure that we're not trying to eliminate to the wrong hard frame
10081 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10083 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
10086 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10087 or argument pointer. TO is either the stack pointer or hard frame
10091 mips_initial_elimination_offset (int from
, int to
)
10093 HOST_WIDE_INT offset
;
10095 mips_compute_frame_info ();
10097 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10100 case FRAME_POINTER_REGNUM
:
10101 if (FRAME_GROWS_DOWNWARD
)
10102 offset
= (cfun
->machine
->frame
.args_size
10103 + cfun
->machine
->frame
.cprestore_size
10104 + cfun
->machine
->frame
.var_size
);
10109 case ARG_POINTER_REGNUM
:
10110 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
10114 gcc_unreachable ();
10117 if (to
== HARD_FRAME_POINTER_REGNUM
)
10118 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10123 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10126 mips_extra_live_on_entry (bitmap regs
)
10128 if (TARGET_USE_GOT
)
10130 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10131 the global pointer. */
10132 if (!TARGET_ABSOLUTE_ABICALLS
)
10133 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10135 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10136 the global pointer. */
10138 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
10140 /* See the comment above load_call<mode> for details. */
10141 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
10145 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10149 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
10154 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
10157 /* Emit code to change the current function's return address to
10158 ADDRESS. SCRATCH is available as a scratch register, if needed.
10159 ADDRESS and SCRATCH are both word-mode GPRs. */
10162 mips_set_return_address (rtx address
, rtx scratch
)
10166 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
10167 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
10168 cfun
->machine
->frame
.gp_sp_offset
);
10169 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
10172 /* Return true if the current function has a cprestore slot. */
10175 mips_cfun_has_cprestore_slot_p (void)
10177 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
10178 && cfun
->machine
->frame
.cprestore_size
> 0);
10181 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10182 cprestore slot. LOAD_P is true if the caller wants to load from
10183 the cprestore slot; it is false if the caller wants to store to
10187 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
10190 const struct mips_frame_info
*frame
;
10192 frame
= &cfun
->machine
->frame
;
10193 /* .cprestore always uses the stack pointer instead of the frame pointer.
10194 We have a free choice for direct stores for non-MIPS16 functions,
10195 and for MIPS16 functions whose cprestore slot is in range of the
10196 stack pointer. Using the stack pointer would sometimes give more
10197 (early) scheduling freedom, but using the frame pointer would
10198 sometimes give more (late) scheduling freedom. It's hard to
10199 predict which applies to a given function, so let's keep things
10202 Loads must always use the frame pointer in functions that call
10203 alloca, and there's little benefit to using the stack pointer
10205 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
10207 *base
= hard_frame_pointer_rtx
;
10208 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
10212 *base
= stack_pointer_rtx
;
10213 *offset
= frame
->args_size
;
10217 /* Return true if X is the load or store address of the cprestore slot;
10218 LOAD_P says which. */
10221 mips_cprestore_address_p (rtx x
, bool load_p
)
10223 rtx given_base
, required_base
;
10224 HOST_WIDE_INT given_offset
, required_offset
;
10226 mips_split_plus (x
, &given_base
, &given_offset
);
10227 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
10228 return given_base
== required_base
&& given_offset
== required_offset
;
10231 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10232 going to load from it, false if we are going to store to it.
10233 Use TEMP as a temporary register if need be. */
10236 mips_cprestore_slot (rtx temp
, bool load_p
)
10239 HOST_WIDE_INT offset
;
10241 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
10242 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
10245 /* Emit instructions to save global pointer value GP into cprestore
10246 slot MEM. OFFSET is the offset that MEM applies to the base register.
10248 MEM may not be a legitimate address. If it isn't, TEMP is a
10249 temporary register that can be used, otherwise it is a SCRATCH. */
10252 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
10254 if (TARGET_CPRESTORE_DIRECTIVE
)
10256 gcc_assert (gp
== pic_offset_table_rtx
);
10257 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
10260 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
10263 /* Restore $gp from its save slot, using TEMP as a temporary base register
10264 if need be. This function is for o32 and o64 abicalls only.
10266 See mips_must_initialize_gp_p for details about how we manage the
10270 mips_restore_gp_from_cprestore_slot (rtx temp
)
10272 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
10274 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
10276 emit_note (NOTE_INSN_DELETED
);
10282 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10283 mips_emit_move (pic_offset_table_rtx
, temp
);
10286 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10287 if (!TARGET_EXPLICIT_RELOCS
)
10288 emit_insn (gen_blockage ());
10291 /* A function to save or store a register. The first argument is the
10292 register and the second is the stack slot. */
10293 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10295 /* Use FN to save or restore register REGNO. MODE is the register's
10296 mode and OFFSET is the offset of its save slot from the current
10300 mips_save_restore_reg (enum machine_mode mode
, int regno
,
10301 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10305 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10307 fn (gen_rtx_REG (mode
, regno
), mem
);
10310 /* Call FN for each accumlator that is saved by the current function.
10311 SP_OFFSET is the offset of the current stack pointer from the start
10315 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10317 HOST_WIDE_INT offset
;
10320 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10321 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10323 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10324 offset
-= UNITS_PER_WORD
;
10325 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10326 offset
-= UNITS_PER_WORD
;
10329 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10330 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10331 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10333 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10334 offset
-= UNITS_PER_WORD
;
10338 /* Save register REG to MEM. Make the instruction frame-related. */
10341 mips_save_reg (rtx reg
, rtx mem
)
10343 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
10347 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
10349 x1
= mips_frame_set (mips_subword (mem
, false),
10350 mips_subword (reg
, false));
10351 x2
= mips_frame_set (mips_subword (mem
, true),
10352 mips_subword (reg
, true));
10353 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10356 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10359 /* Capture the register combinations that are allowed in a SWM or LWM
10360 instruction. The entries are ordered by number of registers set in
10361 the mask. We also ignore the single register encodings because a
10362 normal SW/LW is preferred. */
10364 static const unsigned int umips_swm_mask
[17] = {
10365 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10366 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10367 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10368 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10372 static const unsigned int umips_swm_encoding
[17] = {
10373 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10376 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10377 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10378 stack pointer of the topmost save slot.
10380 Remove from *MASK all registers that were handled using LWM and SWM.
10381 Update *OFFSET so that it points to the first unused save slot. */
10384 umips_build_save_restore (mips_save_restore_fn fn
,
10385 unsigned *mask
, HOST_WIDE_INT
*offset
)
10389 rtx pattern
, set
, reg
, mem
;
10390 HOST_WIDE_INT this_offset
;
10393 /* Try matching $16 to $31 (s0 to ra). */
10394 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
10395 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
10398 if (i
== ARRAY_SIZE (umips_swm_mask
))
10401 /* Get the offset of the lowest save slot. */
10402 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
10403 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
10405 /* LWM/SWM can only support offsets from -2048 to 2047. */
10406 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
10409 /* Create the final PARALLEL. */
10410 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
10411 this_base
= stack_pointer_rtx
;
10413 /* For registers $16-$23 and $30. */
10414 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
10416 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10417 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10418 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
10419 *mask
&= ~(1 << regno
);
10420 reg
= gen_rtx_REG (SImode
, regno
);
10421 if (fn
== mips_save_reg
)
10422 set
= mips_frame_set (mem
, reg
);
10425 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10426 mips_add_cfa_restore (reg
);
10428 XVECEXP (pattern
, 0, j
) = set
;
10431 /* For register $31. */
10432 if (umips_swm_encoding
[i
] >> 4)
10434 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10435 *mask
&= ~(1 << 31);
10436 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10437 reg
= gen_rtx_REG (SImode
, 31);
10438 if (fn
== mips_save_reg
)
10439 set
= mips_frame_set (mem
, reg
);
10442 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10443 mips_add_cfa_restore (reg
);
10445 XVECEXP (pattern
, 0, j
) = set
;
10448 pattern
= emit_insn (pattern
);
10449 if (fn
== mips_save_reg
)
10450 RTX_FRAME_RELATED_P (pattern
) = 1;
10452 /* Adjust the last offset. */
10453 *offset
-= UNITS_PER_WORD
* nregs
;
10458 /* Call FN for each register that is saved by the current function.
10459 SP_OFFSET is the offset of the current stack pointer from the start
10463 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10464 mips_save_restore_fn fn
)
10466 enum machine_mode fpr_mode
;
10468 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
10469 HOST_WIDE_INT offset
;
10472 /* Save registers starting from high to low. The debuggers prefer at least
10473 the return register be stored at func+4, and also it allows us not to
10474 need a nop in the epilogue if at least one register is reloaded in
10475 addition to return address. */
10476 offset
= frame
->gp_sp_offset
- sp_offset
;
10477 mask
= frame
->mask
;
10479 if (TARGET_MICROMIPS
)
10480 umips_build_save_restore (fn
, &mask
, &offset
);
10482 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10483 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10485 /* Record the ra offset for use by mips_function_profiler. */
10486 if (regno
== RETURN_ADDR_REGNUM
)
10487 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10488 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10489 offset
-= UNITS_PER_WORD
;
10492 /* This loop must iterate over the same space as its companion in
10493 mips_compute_frame_info. */
10494 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10495 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10496 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10497 regno
>= FP_REG_FIRST
;
10498 regno
-= MAX_FPRS_PER_FMT
)
10499 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10501 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10502 offset
-= GET_MODE_SIZE (fpr_mode
);
10506 /* Return true if a move between register REGNO and its save slot (MEM)
10507 can be done in a single move. LOAD_P is true if we are loading
10508 from the slot, false if we are storing to it. */
10511 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10513 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10514 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10517 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10518 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10521 /* Emit a move from SRC to DEST, given that one of them is a register
10522 save slot and that the other is a register. TEMP is a temporary
10523 GPR of the same mode that is available if need be. */
10526 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10528 unsigned int regno
;
10533 regno
= REGNO (src
);
10538 regno
= REGNO (dest
);
10542 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
10544 /* We don't yet know whether we'll need this instruction or not.
10545 Postpone the decision by emitting a ghost move. This move
10546 is specifically not frame-related; only the split version is. */
10548 emit_insn (gen_move_gpdi (dest
, src
));
10550 emit_insn (gen_move_gpsi (dest
, src
));
10554 if (regno
== HI_REGNUM
)
10558 mips_emit_move (temp
, src
);
10560 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
10561 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
10563 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
10564 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
10569 emit_insn (gen_mfhidi_ti (temp
,
10570 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
10572 emit_insn (gen_mfhisi_di (temp
,
10573 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
10574 mips_emit_move (dest
, temp
);
10577 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
10578 mips_emit_move (dest
, src
);
10581 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
10582 mips_emit_move (temp
, src
);
10583 mips_emit_move (dest
, temp
);
10586 mips_set_frame_expr (mips_frame_set (dest
, src
));
10589 /* If we're generating n32 or n64 abicalls, and the current function
10590 does not use $28 as its global pointer, emit a cplocal directive.
10591 Use pic_offset_table_rtx as the argument to the directive. */
10594 mips_output_cplocal (void)
10596 if (!TARGET_EXPLICIT_RELOCS
10597 && mips_must_initialize_gp_p ()
10598 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
10599 output_asm_insn (".cplocal %+", 0);
10602 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10605 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10607 const char *fnname
;
10609 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10610 floating-point arguments. */
10612 && TARGET_HARD_FLOAT_ABI
10613 && crtl
->args
.info
.fp_code
!= 0)
10614 mips16_build_function_stub ();
10616 /* Get the function name the same way that toplev.c does before calling
10617 assemble_start_function. This is needed so that the name used here
10618 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10619 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10620 mips_start_function_definition (fnname
, TARGET_MIPS16
);
10622 /* Output MIPS-specific frame information. */
10623 if (!flag_inhibit_size_directive
)
10625 const struct mips_frame_info
*frame
;
10627 frame
= &cfun
->machine
->frame
;
10629 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10631 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
10632 "# vars= " HOST_WIDE_INT_PRINT_DEC
10634 ", args= " HOST_WIDE_INT_PRINT_DEC
10635 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
10636 reg_names
[frame_pointer_needed
10637 ? HARD_FRAME_POINTER_REGNUM
10638 : STACK_POINTER_REGNUM
],
10639 (frame_pointer_needed
10640 ? frame
->total_size
- frame
->hard_frame_pointer_offset
10641 : frame
->total_size
),
10642 reg_names
[RETURN_ADDR_REGNUM
],
10644 frame
->num_gp
, frame
->num_fp
,
10646 frame
->cprestore_size
);
10648 /* .mask MASK, OFFSET. */
10649 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10650 frame
->mask
, frame
->gp_save_offset
);
10652 /* .fmask MASK, OFFSET. */
10653 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10654 frame
->fmask
, frame
->fp_save_offset
);
10657 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10658 Also emit the ".set noreorder; .set nomacro" sequence for functions
10660 if (mips_must_initialize_gp_p ()
10661 && mips_current_loadgp_style () == LOADGP_OLDABI
)
10665 /* This is a fixed-form sequence. The position of the
10666 first two instructions is important because of the
10667 way _gp_disp is defined. */
10668 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10669 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10670 output_asm_insn ("sll\t$2,16", 0);
10671 output_asm_insn ("addu\t$2,$3", 0);
10675 /* .cpload must be in a .set noreorder but not a
10676 .set nomacro block. */
10677 mips_push_asm_switch (&mips_noreorder
);
10678 output_asm_insn (".cpload\t%^", 0);
10679 if (!cfun
->machine
->all_noreorder_p
)
10680 mips_pop_asm_switch (&mips_noreorder
);
10682 mips_push_asm_switch (&mips_nomacro
);
10685 else if (cfun
->machine
->all_noreorder_p
)
10687 mips_push_asm_switch (&mips_noreorder
);
10688 mips_push_asm_switch (&mips_nomacro
);
10691 /* Tell the assembler which register we're using as the global
10692 pointer. This is needed for thunks, since they can use either
10693 explicit relocs or assembler macros. */
10694 mips_output_cplocal ();
10697 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10700 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10701 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10703 const char *fnname
;
10705 /* Reinstate the normal $gp. */
10706 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
10707 mips_output_cplocal ();
10709 if (cfun
->machine
->all_noreorder_p
)
10711 mips_pop_asm_switch (&mips_nomacro
);
10712 mips_pop_asm_switch (&mips_noreorder
);
10715 /* Get the function name the same way that toplev.c does before calling
10716 assemble_start_function. This is needed so that the name used here
10717 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10718 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10719 mips_end_function_definition (fnname
);
10722 /* Emit an optimisation barrier for accesses to the current frame. */
10725 mips_frame_barrier (void)
10727 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
10731 /* The __gnu_local_gp symbol. */
10733 static GTY(()) rtx mips_gnu_local_gp
;
10735 /* If we're generating n32 or n64 abicalls, emit instructions
10736 to set up the global pointer. */
10739 mips_emit_loadgp (void)
10741 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
10743 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10744 switch (mips_current_loadgp_style ())
10746 case LOADGP_ABSOLUTE
:
10747 if (mips_gnu_local_gp
== NULL
)
10749 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
10750 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
10752 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
10753 (pic_reg
, mips_gnu_local_gp
)));
10756 case LOADGP_OLDABI
:
10757 /* Added by mips_output_function_prologue. */
10760 case LOADGP_NEWABI
:
10761 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
10762 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
10763 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
10764 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
10765 (pic_reg
, offset
, incoming_address
)));
10769 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
10770 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
10771 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
10779 emit_insn (PMODE_INSN (gen_copygp_mips16
,
10780 (pic_offset_table_rtx
, pic_reg
)));
10782 /* Emit a blockage if there are implicit uses of the GP register.
10783 This includes profiled functions, because FUNCTION_PROFILE uses
10785 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
10786 emit_insn (gen_loadgp_blockage ());
10789 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10791 #if PROBE_INTERVAL > 32768
10792 #error Cannot use indexed addressing mode for stack probing
10795 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10796 inclusive. These are offsets from the current stack pointer. */
10799 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
10802 sorry ("-fstack-check=specific not implemented for MIPS16");
10804 /* See if we have a constant small number of probes to generate. If so,
10805 that's the easy case. */
10806 if (first
+ size
<= 32768)
10810 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10811 it exceeds SIZE. If only one probe is needed, this will not
10812 generate any code. Then probe at FIRST + SIZE. */
10813 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
10814 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10817 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10821 /* Otherwise, do the same as above, but in a loop. Note that we must be
10822 extra careful with variables wrapping around because we might be at
10823 the very top (or the very bottom) of the address space and we have
10824 to be able to handle this case properly; in particular, we use an
10825 equality test for the loop condition. */
10828 HOST_WIDE_INT rounded_size
;
10829 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
10830 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
10832 /* Sanity check for the addressing mode we're going to use. */
10833 gcc_assert (first
<= 32768);
10836 /* Step 1: round SIZE to the previous multiple of the interval. */
10838 rounded_size
= size
& -PROBE_INTERVAL
;
10841 /* Step 2: compute initial and final value of the loop counter. */
10843 /* TEST_ADDR = SP + FIRST. */
10844 emit_insn (gen_rtx_SET (VOIDmode
, r3
,
10845 plus_constant (Pmode
, stack_pointer_rtx
,
10848 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10849 if (rounded_size
> 32768)
10851 emit_move_insn (r12
, GEN_INT (rounded_size
));
10852 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10853 gen_rtx_MINUS (Pmode
, r3
, r12
)));
10856 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10857 plus_constant (Pmode
, r3
, -rounded_size
)));
10860 /* Step 3: the loop
10862 while (TEST_ADDR != LAST_ADDR)
10864 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10868 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10869 until it is equal to ROUNDED_SIZE. */
10871 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
10874 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10875 that SIZE is equal to ROUNDED_SIZE. */
10877 if (size
!= rounded_size
)
10878 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
10881 /* Make sure nothing is scheduled before we are done. */
10882 emit_insn (gen_blockage ());
10885 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
10886 absolute addresses. */
10889 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
10891 static int labelno
= 0;
10892 char loop_lab
[32], end_lab
[32], tmp
[64];
10895 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
10896 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
10898 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
10900 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10903 strcpy (tmp
, "%(%<beq\t%0,%1,");
10904 output_asm_insn (strcat (tmp
, &end_lab
[1]), xops
);
10906 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10907 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
10908 if (TARGET_64BIT
&& TARGET_LONG64
)
10909 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
10911 output_asm_insn ("addiu\t%0,%0,%1", xops
);
10913 /* Probe at TEST_ADDR and branch. */
10914 fprintf (asm_out_file
, "\tb\t");
10915 assemble_name_raw (asm_out_file
, loop_lab
);
10916 fputc ('\n', asm_out_file
);
10918 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
10920 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
10922 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
10927 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10930 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
10932 return REG_P (*x
) && KERNEL_REG_P (REGNO (*x
));
10935 /* Expand the "prologue" pattern. */
10938 mips_expand_prologue (void)
10940 const struct mips_frame_info
*frame
;
10941 HOST_WIDE_INT size
;
10942 unsigned int nargs
;
10945 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
10947 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10948 or implicitly. If so, we can commit to using a global pointer
10949 straight away, otherwise we need to defer the decision. */
10950 if (mips_cfun_has_inflexible_gp_ref_p ()
10951 || mips_cfun_has_flexible_gp_ref_p ())
10953 cfun
->machine
->must_initialize_gp_p
= true;
10954 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
10957 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
10960 frame
= &cfun
->machine
->frame
;
10961 size
= frame
->total_size
;
10963 if (flag_stack_usage_info
)
10964 current_function_static_stack_size
= size
;
10966 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
10967 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
10969 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10970 bytes beforehand; this is enough to cover the register save area
10971 without going out of range. */
10972 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
10973 || frame
->num_cop0_regs
> 0)
10975 HOST_WIDE_INT step1
;
10977 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
10978 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10980 HOST_WIDE_INT offset
;
10981 unsigned int mask
, regno
;
10983 /* Try to merge argument stores into the save instruction. */
10984 nargs
= mips16e_collect_argument_saves ();
10986 /* Build the save instruction. */
10987 mask
= frame
->mask
;
10988 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
10990 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10991 mips_frame_barrier ();
10994 /* Check if we need to save other registers. */
10995 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
10996 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10998 offset
-= UNITS_PER_WORD
;
10999 mips_save_restore_reg (word_mode
, regno
,
11000 offset
, mips_save_reg
);
11005 if (cfun
->machine
->interrupt_handler_p
)
11007 HOST_WIDE_INT offset
;
11010 /* If this interrupt is using a shadow register set, we need to
11011 get the stack pointer from the previous register set. */
11012 if (cfun
->machine
->use_shadow_register_set_p
)
11013 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
11014 stack_pointer_rtx
));
11016 if (!cfun
->machine
->keep_interrupts_masked_p
)
11018 /* Move from COP0 Cause to K0. */
11019 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
11020 gen_rtx_REG (SImode
,
11021 COP0_CAUSE_REG_NUM
)));
11022 /* Move from COP0 EPC to K1. */
11023 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11024 gen_rtx_REG (SImode
,
11025 COP0_EPC_REG_NUM
)));
11028 /* Allocate the first part of the frame. */
11029 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
11031 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11032 mips_frame_barrier ();
11035 /* Start at the uppermost location for saving. */
11036 offset
= frame
->cop0_sp_offset
- size
;
11037 if (!cfun
->machine
->keep_interrupts_masked_p
)
11039 /* Push EPC into its stack slot. */
11040 mem
= gen_frame_mem (word_mode
,
11041 plus_constant (Pmode
, stack_pointer_rtx
,
11043 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11044 offset
-= UNITS_PER_WORD
;
11047 /* Move from COP0 Status to K1. */
11048 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11049 gen_rtx_REG (SImode
,
11050 COP0_STATUS_REG_NUM
)));
11052 /* Right justify the RIPL in k0. */
11053 if (!cfun
->machine
->keep_interrupts_masked_p
)
11054 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
11055 gen_rtx_REG (SImode
, K0_REG_NUM
),
11056 GEN_INT (CAUSE_IPL
)));
11058 /* Push Status into its stack slot. */
11059 mem
= gen_frame_mem (word_mode
,
11060 plus_constant (Pmode
, stack_pointer_rtx
,
11062 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11063 offset
-= UNITS_PER_WORD
;
11065 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11066 if (!cfun
->machine
->keep_interrupts_masked_p
)
11067 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11070 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11072 if (!cfun
->machine
->keep_interrupts_masked_p
)
11073 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11074 IE is already the correct value, so we don't have to do
11075 anything explicit. */
11076 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11079 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11081 /* Disable interrupts by clearing the KSU, ERL, EXL,
11083 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11086 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11090 insn
= gen_add3_insn (stack_pointer_rtx
,
11093 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11094 mips_frame_barrier ();
11097 mips_for_each_saved_acc (size
, mips_save_reg
);
11098 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
11102 /* Allocate the rest of the frame. */
11105 if (SMALL_OPERAND (-size
))
11106 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
11108 GEN_INT (-size
)))) = 1;
11111 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
11114 /* There are no instructions to add or subtract registers
11115 from the stack pointer, so use the frame pointer as a
11116 temporary. We should always be using a frame pointer
11117 in this case anyway. */
11118 gcc_assert (frame_pointer_needed
);
11119 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11120 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
11121 hard_frame_pointer_rtx
,
11122 MIPS_PROLOGUE_TEMP (Pmode
)));
11123 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
11126 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
11128 MIPS_PROLOGUE_TEMP (Pmode
)));
11130 /* Describe the combined effect of the previous instructions. */
11131 mips_set_frame_expr
11132 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
11133 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
11135 mips_frame_barrier ();
11138 /* Set up the frame pointer, if we're using one. */
11139 if (frame_pointer_needed
)
11141 HOST_WIDE_INT offset
;
11143 offset
= frame
->hard_frame_pointer_offset
;
11146 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11147 RTX_FRAME_RELATED_P (insn
) = 1;
11149 else if (SMALL_OPERAND (offset
))
11151 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
11152 stack_pointer_rtx
, GEN_INT (offset
));
11153 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11157 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
11158 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11159 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
11160 hard_frame_pointer_rtx
,
11161 MIPS_PROLOGUE_TEMP (Pmode
)));
11162 mips_set_frame_expr
11163 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
11164 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
11168 mips_emit_loadgp ();
11170 /* Initialize the $gp save slot. */
11171 if (mips_cfun_has_cprestore_slot_p ())
11173 rtx base
, mem
, gp
, temp
;
11174 HOST_WIDE_INT offset
;
11176 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
11177 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11178 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11179 temp
= (SMALL_OPERAND (offset
)
11180 ? gen_rtx_SCRATCH (Pmode
)
11181 : MIPS_PROLOGUE_TEMP (Pmode
));
11182 emit_insn (PMODE_INSN (gen_potential_cprestore
,
11183 (mem
, GEN_INT (offset
), gp
, temp
)));
11185 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11186 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11187 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
11190 /* We need to search back to the last use of K0 or K1. */
11191 if (cfun
->machine
->interrupt_handler_p
)
11193 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
11195 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
11197 /* Emit a move from K1 to COP0 Status after insn. */
11198 gcc_assert (insn
!= NULL_RTX
);
11199 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11200 gen_rtx_REG (SImode
, K1_REG_NUM
)),
11204 /* If we are profiling, make sure no instructions are scheduled before
11205 the call to mcount. */
11207 emit_insn (gen_blockage ());
11210 /* Attach all pending register saves to the previous instruction.
11211 Return that instruction. */
11214 mips_epilogue_emit_cfa_restores (void)
11218 insn
= get_last_insn ();
11219 gcc_assert (insn
&& !REG_NOTES (insn
));
11220 if (mips_epilogue
.cfa_restores
)
11222 RTX_FRAME_RELATED_P (insn
) = 1;
11223 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
11224 mips_epilogue
.cfa_restores
= 0;
11229 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11230 now at REG + OFFSET. */
11233 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
11237 insn
= mips_epilogue_emit_cfa_restores ();
11238 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
11240 RTX_FRAME_RELATED_P (insn
) = 1;
11241 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
11242 plus_constant (Pmode
, reg
, offset
),
11244 mips_epilogue
.cfa_reg
= reg
;
11245 mips_epilogue
.cfa_offset
= offset
;
11249 /* Emit instructions to restore register REG from slot MEM. Also update
11250 the cfa_restores list. */
11253 mips_restore_reg (rtx reg
, rtx mem
)
11255 /* There's no MIPS16 instruction to load $31 directly. Load into
11256 $7 instead and adjust the return insn appropriately. */
11257 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
11258 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
11259 else if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
11261 mips_add_cfa_restore (mips_subword (reg
, true));
11262 mips_add_cfa_restore (mips_subword (reg
, false));
11265 mips_add_cfa_restore (reg
);
11267 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
11268 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
11269 /* The CFA is currently defined in terms of the register whose
11270 value we have just restored. Redefine the CFA in terms of
11271 the stack pointer. */
11272 mips_epilogue_set_cfa (stack_pointer_rtx
,
11273 mips_epilogue
.cfa_restore_sp_offset
);
11276 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11277 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11278 BASE, if not the stack pointer, is available as a temporary. */
11281 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
11283 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
11286 mips_frame_barrier ();
11287 if (offset
== const0_rtx
)
11289 emit_move_insn (stack_pointer_rtx
, base
);
11290 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11292 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
11294 emit_insn (gen_add3_insn (base
, base
, offset
));
11295 mips_epilogue_set_cfa (base
, new_frame_size
);
11296 emit_move_insn (stack_pointer_rtx
, base
);
11300 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
11301 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11305 /* Emit any instructions needed before a return. */
11308 mips_expand_before_return (void)
11310 /* When using a call-clobbered gp, we start out with unified call
11311 insns that include instructions to restore the gp. We then split
11312 these unified calls after reload. These split calls explicitly
11313 clobber gp, so there is no need to define
11314 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11316 For consistency, we should also insert an explicit clobber of $28
11317 before return insns, so that the post-reload optimizers know that
11318 the register is not live on exit. */
11319 if (TARGET_CALL_CLOBBERED_GP
)
11320 emit_clobber (pic_offset_table_rtx
);
11323 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11327 mips_expand_epilogue (bool sibcall_p
)
11329 const struct mips_frame_info
*frame
;
11330 HOST_WIDE_INT step1
, step2
;
11331 rtx base
, adjust
, insn
;
11332 bool use_jraddiusp_p
= false;
11334 if (!sibcall_p
&& mips_can_use_return_insn ())
11336 emit_jump_insn (gen_return ());
11340 /* In MIPS16 mode, if the return value should go into a floating-point
11341 register, we need to call a helper routine to copy it over. */
11342 if (mips16_cfun_returns_in_fpr_p ())
11343 mips16_copy_fpr_return_value ();
11345 /* Split the frame into two. STEP1 is the amount of stack we should
11346 deallocate before restoring the registers. STEP2 is the amount we
11347 should deallocate afterwards.
11349 Start off by assuming that no registers need to be restored. */
11350 frame
= &cfun
->machine
->frame
;
11351 step1
= frame
->total_size
;
11354 /* Work out which register holds the frame address. */
11355 if (!frame_pointer_needed
)
11356 base
= stack_pointer_rtx
;
11359 base
= hard_frame_pointer_rtx
;
11360 step1
-= frame
->hard_frame_pointer_offset
;
11362 mips_epilogue
.cfa_reg
= base
;
11363 mips_epilogue
.cfa_offset
= step1
;
11364 mips_epilogue
.cfa_restores
= NULL_RTX
;
11366 /* If we need to restore registers, deallocate as much stack as
11367 possible in the second step without going out of range. */
11368 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
11369 || frame
->num_cop0_regs
> 0)
11371 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
11375 /* Get an rtx for STEP1 that we can add to BASE. */
11376 adjust
= GEN_INT (step1
);
11377 if (!SMALL_OPERAND (step1
))
11379 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
11380 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
11382 mips_deallocate_stack (base
, adjust
, step2
);
11384 /* If we're using addressing macros, $gp is implicitly used by all
11385 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11387 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
11388 emit_insn (gen_blockage ());
11390 mips_epilogue
.cfa_restore_sp_offset
= step2
;
11391 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
11393 unsigned int regno
, mask
;
11394 HOST_WIDE_INT offset
;
11397 /* Generate the restore instruction. */
11398 mask
= frame
->mask
;
11399 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
11401 /* Restore any other registers manually. */
11402 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11403 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11405 offset
-= UNITS_PER_WORD
;
11406 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
11409 /* Restore the remaining registers and deallocate the final bit
11411 mips_frame_barrier ();
11412 emit_insn (restore
);
11413 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
11417 /* Restore the registers. */
11418 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
11419 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
11422 if (cfun
->machine
->interrupt_handler_p
)
11424 HOST_WIDE_INT offset
;
11427 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
11428 if (!cfun
->machine
->keep_interrupts_masked_p
)
11430 /* Restore the original EPC. */
11431 mem
= gen_frame_mem (word_mode
,
11432 plus_constant (Pmode
, stack_pointer_rtx
,
11434 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11435 offset
-= UNITS_PER_WORD
;
11437 /* Move to COP0 EPC. */
11438 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
11439 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11442 /* Restore the original Status. */
11443 mem
= gen_frame_mem (word_mode
,
11444 plus_constant (Pmode
, stack_pointer_rtx
,
11446 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11447 offset
-= UNITS_PER_WORD
;
11449 /* If we don't use shadow register set, we need to update SP. */
11450 if (!cfun
->machine
->use_shadow_register_set_p
)
11451 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11453 /* The choice of position is somewhat arbitrary in this case. */
11454 mips_epilogue_emit_cfa_restores ();
11456 /* Move to COP0 Status. */
11457 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11458 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11460 else if (TARGET_MICROMIPS
11461 && !crtl
->calls_eh_return
11464 && mips_unsigned_immediate_p (step2
, 5, 2))
11465 use_jraddiusp_p
= true;
11467 /* Deallocate the final bit of the frame. */
11468 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11471 if (!use_jraddiusp_p
)
11472 gcc_assert (!mips_epilogue
.cfa_restores
);
11474 /* Add in the __builtin_eh_return stack adjustment. We need to
11475 use a temporary in MIPS16 code. */
11476 if (crtl
->calls_eh_return
)
11480 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
11481 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
11482 MIPS_EPILOGUE_TEMP (Pmode
),
11483 EH_RETURN_STACKADJ_RTX
));
11484 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
11487 emit_insn (gen_add3_insn (stack_pointer_rtx
,
11489 EH_RETURN_STACKADJ_RTX
));
11494 mips_expand_before_return ();
11495 if (cfun
->machine
->interrupt_handler_p
)
11497 /* Interrupt handlers generate eret or deret. */
11498 if (cfun
->machine
->use_debug_exception_return_p
)
11499 emit_jump_insn (gen_mips_deret ());
11501 emit_jump_insn (gen_mips_eret ());
11507 /* When generating MIPS16 code, the normal
11508 mips_for_each_saved_gpr_and_fpr path will restore the return
11509 address into $7 rather than $31. */
11511 && !GENERATE_MIPS16E_SAVE_RESTORE
11512 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
11514 /* simple_returns cannot rely on values that are only available
11515 on paths through the epilogue (because return paths that do
11516 not pass through the epilogue may nevertheless reuse a
11517 simple_return that occurs at the end of the epilogue).
11518 Use a normal return here instead. */
11519 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
11520 pat
= gen_return_internal (reg
);
11522 else if (use_jraddiusp_p
)
11523 pat
= gen_jraddiusp (GEN_INT (step2
));
11526 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
11527 pat
= gen_simple_return_internal (reg
);
11529 emit_jump_insn (pat
);
11530 if (use_jraddiusp_p
)
11531 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
11535 /* Search from the beginning to the first use of K0 or K1. */
11536 if (cfun
->machine
->interrupt_handler_p
11537 && !cfun
->machine
->keep_interrupts_masked_p
)
11539 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11541 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
11543 gcc_assert (insn
!= NULL_RTX
);
11544 /* Insert disable interrupts before the first use of K0 or K1. */
11545 emit_insn_before (gen_mips_di (), insn
);
11546 emit_insn_before (gen_mips_ehb (), insn
);
11550 /* Return nonzero if this function is known to have a null epilogue.
11551 This allows the optimizer to omit jumps to jumps if no stack
11555 mips_can_use_return_insn (void)
11557 /* Interrupt handlers need to go through the epilogue. */
11558 if (cfun
->machine
->interrupt_handler_p
)
11561 if (!reload_completed
)
11567 /* In MIPS16 mode, a function that returns a floating-point value
11568 needs to arrange to copy the return value into the floating-point
11570 if (mips16_cfun_returns_in_fpr_p ())
11573 return cfun
->machine
->frame
.total_size
== 0;
11576 /* Return true if register REGNO can store a value of mode MODE.
11577 The result of this function is cached in mips_hard_regno_mode_ok. */
11580 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
11583 enum mode_class mclass
;
11585 if (mode
== CCV2mode
)
11586 return (ISA_HAS_8CC
11587 && ST_REG_P (regno
)
11588 && (regno
- ST_REG_FIRST
) % 2 == 0);
11590 if (mode
== CCV4mode
)
11591 return (ISA_HAS_8CC
11592 && ST_REG_P (regno
)
11593 && (regno
- ST_REG_FIRST
) % 4 == 0);
11595 if (mode
== CCmode
)
11596 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
11598 size
= GET_MODE_SIZE (mode
);
11599 mclass
= GET_MODE_CLASS (mode
);
11601 if (GP_REG_P (regno
))
11602 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
11604 if (FP_REG_P (regno
)
11605 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
11606 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
11608 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11609 if (TARGET_LOONGSON_VECTORS
11610 && (mode
== V2SImode
11611 || mode
== V4HImode
11612 || mode
== V8QImode
11613 || mode
== DImode
))
11616 if (mclass
== MODE_FLOAT
11617 || mclass
== MODE_COMPLEX_FLOAT
11618 || mclass
== MODE_VECTOR_FLOAT
)
11619 return size
<= UNITS_PER_FPVALUE
;
11621 /* Allow integer modes that fit into a single register. We need
11622 to put integers into FPRs when using instructions like CVT
11623 and TRUNC. There's no point allowing sizes smaller than a word,
11624 because the FPU has no appropriate load/store instructions. */
11625 if (mclass
== MODE_INT
)
11626 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
11629 if (ACC_REG_P (regno
)
11630 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
11632 if (MD_REG_P (regno
))
11634 /* After a multiplication or division, clobbering HI makes
11635 the value of LO unpredictable, and vice versa. This means
11636 that, for all interesting cases, HI and LO are effectively
11639 We model this by requiring that any value that uses HI
11641 if (size
<= UNITS_PER_WORD
* 2)
11642 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
11646 /* DSP accumulators do not have the same restrictions as
11647 HI and LO, so we can treat them as normal doubleword
11649 if (size
<= UNITS_PER_WORD
)
11652 if (size
<= UNITS_PER_WORD
* 2
11653 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
11658 if (ALL_COP_REG_P (regno
))
11659 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
11661 if (regno
== GOT_VERSION_REGNUM
)
11662 return mode
== SImode
;
11667 /* Implement HARD_REGNO_NREGS. */
11670 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
11672 if (ST_REG_P (regno
))
11673 /* The size of FP status registers is always 4, because they only hold
11674 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11675 return (GET_MODE_SIZE (mode
) + 3) / 4;
11677 if (FP_REG_P (regno
))
11678 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
11680 /* All other registers are word-sized. */
11681 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
11684 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11685 in mips_hard_regno_nregs. */
11688 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
11694 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
11695 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
11697 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
11698 size
= MIN (size
, 4);
11699 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
11701 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
11703 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
11704 size
= MIN (size
, UNITS_PER_FPREG
);
11705 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
11707 if (!hard_reg_set_empty_p (left
))
11708 size
= MIN (size
, UNITS_PER_WORD
);
11709 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
11712 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11715 mips_cannot_change_mode_class (enum machine_mode from
,
11716 enum machine_mode to
,
11717 enum reg_class rclass
)
11719 /* Allow conversions between different Loongson integer vectors,
11720 and between those vectors and DImode. */
11721 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
11722 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
11725 /* Otherwise, there are several problems with changing the modes of
11726 values in floating-point registers:
11728 - When a multi-word value is stored in paired floating-point
11729 registers, the first register always holds the low word. We
11730 therefore can't allow FPRs to change between single-word and
11731 multi-word modes on big-endian targets.
11733 - GCC assumes that each word of a multiword register can be
11734 accessed individually using SUBREGs. This is not true for
11735 floating-point registers if they are bigger than a word.
11737 - Loading a 32-bit value into a 64-bit floating-point register
11738 will not sign-extend the value, despite what LOAD_EXTEND_OP
11739 says. We can't allow FPRs to change from SImode to a wider
11740 mode on 64-bit targets.
11742 - If the FPU has already interpreted a value in one format, we
11743 must not ask it to treat the value as having a different
11746 We therefore disallow all mode changes involving FPRs. */
11748 return reg_classes_intersect_p (FP_REGS
, rclass
);
11751 /* Implement target hook small_register_classes_for_mode_p. */
11754 mips_small_register_classes_for_mode_p (enum machine_mode mode
11757 return TARGET_MIPS16
;
11760 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11763 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
11768 return TARGET_HARD_FLOAT
;
11771 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
11774 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
11781 /* Implement MODES_TIEABLE_P. */
11784 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
11786 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11787 prefer to put one of them in FPRs. */
11788 return (mode1
== mode2
11789 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
11790 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
11793 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11796 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
11798 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
11801 if (reg_class_subset_p (FP_REGS
, rclass
)
11802 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
11805 if (reg_class_subset_p (GR_REGS
, rclass
))
11808 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
11814 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11815 Return a "canonical" class to represent it in later calculations. */
11818 mips_canonicalize_move_class (reg_class_t rclass
)
11820 /* All moves involving accumulator registers have the same cost. */
11821 if (reg_class_subset_p (rclass
, ACC_REGS
))
11824 /* Likewise promote subclasses of general registers to the most
11825 interesting containing class. */
11826 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
11828 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
11829 rclass
= GENERAL_REGS
;
11834 /* Return the cost of moving a value of mode MODE from a register of
11835 class FROM to a GPR. Return 0 for classes that are unions of other
11836 classes handled by this function. */
11839 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
11845 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11849 /* MFLO and MFHI. */
11857 /* LUI followed by MOVF. */
11863 /* This choice of value is historical. */
11871 /* Return the cost of moving a value of mode MODE from a GPR to a
11872 register of class TO. Return 0 for classes that are unions of
11873 other classes handled by this function. */
11876 mips_move_from_gpr_cost (enum machine_mode mode
, reg_class_t to
)
11881 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11885 /* MTLO and MTHI. */
11893 /* A secondary reload through an FPR scratch. */
11894 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
11895 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
11900 /* This choice of value is historical. */
11908 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11909 maximum of the move costs for subclasses; regclass will work out
11910 the maximum for us. */
11913 mips_register_move_cost (enum machine_mode mode
,
11914 reg_class_t from
, reg_class_t to
)
11919 from
= mips_canonicalize_move_class (from
);
11920 to
= mips_canonicalize_move_class (to
);
11922 /* Handle moves that can be done without using general-purpose registers. */
11923 if (from
== FP_REGS
)
11925 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
11929 /* The sequence generated by mips_expand_fcc_reload. */
11933 /* Handle cases in which only one class deviates from the ideal. */
11934 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
11936 return mips_move_from_gpr_cost (mode
, to
);
11938 return mips_move_to_gpr_cost (mode
, from
);
11940 /* Handles cases that require a GPR temporary. */
11941 cost1
= mips_move_to_gpr_cost (mode
, from
);
11944 cost2
= mips_move_from_gpr_cost (mode
, to
);
11946 return cost1
+ cost2
;
11952 /* Implement TARGET_MEMORY_MOVE_COST. */
11955 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
11957 return (mips_cost
->memory_latency
11958 + memory_move_secondary_cost (mode
, rclass
, in
));
11961 /* Return the register class required for a secondary register when
11962 copying between one of the registers in RCLASS and value X, which
11963 has mode MODE. X is the source of the move if IN_P, otherwise it
11964 is the destination. Return NO_REGS if no secondary register is
11968 mips_secondary_reload_class (enum reg_class rclass
,
11969 enum machine_mode mode
, rtx x
, bool in_p
)
11973 /* If X is a constant that cannot be loaded into $25, it must be loaded
11974 into some other GPR. No other register class allows a direct move. */
11975 if (mips_dangerous_for_la25_p (x
))
11976 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
11978 regno
= true_regnum (x
);
11981 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11982 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
11988 /* Copying from accumulator registers to anywhere other than a general
11989 register requires a temporary general register. */
11990 if (reg_class_subset_p (rclass
, ACC_REGS
))
11991 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
11992 if (ACC_REG_P (regno
))
11993 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11995 /* We can only copy a value to a condition code register from a
11996 floating-point register, and even then we require a scratch
11997 floating-point register. We can only copy a value out of a
11998 condition-code register into a general register. */
11999 if (reg_class_subset_p (rclass
, ST_REGS
))
12003 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12005 if (ST_REG_P (regno
))
12009 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12012 if (reg_class_subset_p (rclass
, FP_REGS
))
12015 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
12016 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12017 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12020 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
12021 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12024 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
12025 /* We can force the constant to memory and use lwc1
12026 and ldc1. As above, we will use pairs of lwc1s if
12027 ldc1 is not supported. */
12030 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
12031 /* In this case we can use mov.fmt. */
12034 /* Otherwise, we need to reload through an integer register. */
12037 if (FP_REG_P (regno
))
12038 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12043 /* Implement TARGET_MODE_REP_EXTENDED. */
12046 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
12048 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12049 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
12050 return SIGN_EXTEND
;
12055 /* Implement TARGET_VALID_POINTER_MODE. */
12058 mips_valid_pointer_mode (enum machine_mode mode
)
12060 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
12063 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12066 mips_vector_mode_supported_p (enum machine_mode mode
)
12071 return TARGET_PAIRED_SINGLE_FLOAT
;
12086 return TARGET_LOONGSON_VECTORS
;
12093 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12096 mips_scalar_mode_supported_p (enum machine_mode mode
)
12098 if (ALL_FIXED_POINT_MODE_P (mode
)
12099 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
12102 return default_scalar_mode_supported_p (mode
);
12105 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12107 static enum machine_mode
12108 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED
)
12110 if (TARGET_PAIRED_SINGLE_FLOAT
12116 /* Implement TARGET_INIT_LIBFUNCS. */
12119 mips_init_libfuncs (void)
12121 if (TARGET_FIX_VR4120
)
12123 /* Register the special divsi3 and modsi3 functions needed to work
12124 around VR4120 division errata. */
12125 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
12126 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
12129 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
12131 /* Register the MIPS16 -mhard-float stubs. */
12132 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
12133 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
12134 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
12135 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
12137 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
12138 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
12139 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
12140 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
12141 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
12142 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
12143 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
12145 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
12146 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
12147 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
12149 if (TARGET_DOUBLE_FLOAT
)
12151 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
12152 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
12153 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
12154 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
12156 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
12157 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
12158 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
12159 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
12160 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
12161 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
12162 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
12164 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
12165 "__mips16_extendsfdf2");
12166 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
12167 "__mips16_truncdfsf2");
12168 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
12169 "__mips16_fix_truncdfsi");
12170 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
12171 "__mips16_floatsidf");
12172 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
12173 "__mips16_floatunsidf");
12177 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12178 on an external non-MIPS16 routine to implement __sync_synchronize.
12179 Similarly for the rest of the ll/sc libfuncs. */
12182 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
12183 init_sync_libfuncs (UNITS_PER_WORD
);
12187 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12190 mips_process_load_label (rtx target
)
12192 rtx base
, gp
, intop
;
12193 HOST_WIDE_INT offset
;
12195 mips_multi_start ();
12199 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
12200 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12204 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
12205 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12209 gp
= pic_offset_table_rtx
;
12210 if (mips_cfun_has_cprestore_slot_p ())
12212 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
12213 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12214 if (!SMALL_OPERAND (offset
))
12216 intop
= GEN_INT (CONST_HIGH_PART (offset
));
12217 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
12218 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
12221 offset
= CONST_LOW_PART (offset
);
12223 intop
= GEN_INT (offset
);
12224 if (ISA_HAS_LOAD_DELAY
)
12225 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
12227 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
12229 if (ISA_HAS_LOAD_DELAY
)
12230 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
12232 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
12233 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
12238 /* Return the number of instructions needed to load a label into $AT. */
12240 static unsigned int
12241 mips_load_label_num_insns (void)
12243 if (cfun
->machine
->load_label_num_insns
== 0)
12245 mips_process_load_label (pc_rtx
);
12246 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
12248 return cfun
->machine
->load_label_num_insns
;
12251 /* Emit an asm sequence to start a noat block and load the address
12252 of a label into $1. */
12255 mips_output_load_label (rtx target
)
12257 mips_push_asm_switch (&mips_noat
);
12258 if (TARGET_EXPLICIT_RELOCS
)
12260 mips_process_load_label (target
);
12261 mips_multi_write ();
12265 if (Pmode
== DImode
)
12266 output_asm_insn ("dla\t%@,%0", &target
);
12268 output_asm_insn ("la\t%@,%0", &target
);
12272 /* Return the length of INSN. LENGTH is the initial length computed by
12273 attributes in the machine-description file. */
12276 mips_adjust_insn_length (rtx insn
, int length
)
12278 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12279 of a PIC long-branch sequence. Substitute the correct value. */
12280 if (length
== MAX_PIC_BRANCH_LENGTH
12281 && INSN_CODE (insn
) >= 0
12282 && get_attr_type (insn
) == TYPE_BRANCH
)
12284 /* Add the branch-over instruction and its delay slot, if this
12285 is a conditional branch. */
12286 length
= simplejump_p (insn
) ? 0 : 8;
12288 /* Add the size of a load into $AT. */
12289 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
12291 /* Add the length of an indirect jump, ignoring the delay slot. */
12292 length
+= TARGET_COMPRESSION
? 2 : 4;
12295 /* A unconditional jump has an unfilled delay slot if it is not part
12296 of a sequence. A conditional jump normally has a delay slot, but
12297 does not on MIPS16. */
12298 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
12299 length
+= TARGET_MIPS16
? 2 : 4;
12301 /* See how many nops might be needed to avoid hardware hazards. */
12302 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
12303 switch (get_attr_hazard (insn
))
12309 length
+= NOP_INSN_LENGTH
;
12313 length
+= NOP_INSN_LENGTH
* 2;
12320 /* Return the assembly code for INSN, which has the operands given by
12321 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12322 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12323 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12324 version of BRANCH_IF_TRUE. */
12327 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
12328 const char *branch_if_true
,
12329 const char *branch_if_false
)
12331 unsigned int length
;
12332 rtx taken
, not_taken
;
12334 gcc_assert (LABEL_P (operands
[0]));
12336 length
= get_attr_length (insn
);
12339 /* Just a simple conditional branch. */
12340 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
12341 return branch_if_true
;
12344 /* Generate a reversed branch around a direct jump. This fallback does
12345 not use branch-likely instructions. */
12346 mips_branch_likely
= false;
12347 not_taken
= gen_label_rtx ();
12348 taken
= operands
[0];
12350 /* Generate the reversed branch to NOT_TAKEN. */
12351 operands
[0] = not_taken
;
12352 output_asm_insn (branch_if_false
, operands
);
12354 /* If INSN has a delay slot, we must provide delay slots for both the
12355 branch to NOT_TAKEN and the conditional jump. We must also ensure
12356 that INSN's delay slot is executed in the appropriate cases. */
12357 if (final_sequence
)
12359 /* This first delay slot will always be executed, so use INSN's
12360 delay slot if is not annulled. */
12361 if (!INSN_ANNULLED_BRANCH_P (insn
))
12363 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12364 asm_out_file
, optimize
, 1, NULL
);
12365 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12368 output_asm_insn ("nop", 0);
12369 fprintf (asm_out_file
, "\n");
12372 /* Output the unconditional branch to TAKEN. */
12373 if (TARGET_ABSOLUTE_JUMPS
)
12374 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
12377 mips_output_load_label (taken
);
12378 output_asm_insn ("jr\t%@%]%/", 0);
12381 /* Now deal with its delay slot; see above. */
12382 if (final_sequence
)
12384 /* This delay slot will only be executed if the branch is taken.
12385 Use INSN's delay slot if is annulled. */
12386 if (INSN_ANNULLED_BRANCH_P (insn
))
12388 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12389 asm_out_file
, optimize
, 1, NULL
);
12390 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12393 output_asm_insn ("nop", 0);
12394 fprintf (asm_out_file
, "\n");
12397 /* Output NOT_TAKEN. */
12398 targetm
.asm_out
.internal_label (asm_out_file
, "L",
12399 CODE_LABEL_NUMBER (not_taken
));
12403 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12404 if some ordering condition is true. The condition is given by
12405 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12406 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12407 its second is always zero. */
12410 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
12412 const char *branch
[2];
12414 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12415 Make BRANCH[0] branch on the inverse condition. */
12416 switch (GET_CODE (operands
[1]))
12418 /* These cases are equivalent to comparisons against zero. */
12420 inverted_p
= !inverted_p
;
12421 /* Fall through. */
12423 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
12424 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
12427 /* These cases are always true or always false. */
12429 inverted_p
= !inverted_p
;
12430 /* Fall through. */
12432 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
12433 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
12437 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
12438 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
12441 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
12444 /* Start a block of code that needs access to the LL, SC and SYNC
12448 mips_start_ll_sc_sync_block (void)
12450 if (!ISA_HAS_LL_SC
)
12452 output_asm_insn (".set\tpush", 0);
12453 output_asm_insn (".set\tmips2", 0);
12457 /* End a block started by mips_start_ll_sc_sync_block. */
12460 mips_end_ll_sc_sync_block (void)
12462 if (!ISA_HAS_LL_SC
)
12463 output_asm_insn (".set\tpop", 0);
12466 /* Output and/or return the asm template for a sync instruction. */
12469 mips_output_sync (void)
12471 mips_start_ll_sc_sync_block ();
12472 output_asm_insn ("sync", 0);
12473 mips_end_ll_sc_sync_block ();
12477 /* Return the asm template associated with sync_insn1 value TYPE.
12478 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12480 static const char *
12481 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
12485 case SYNC_INSN1_MOVE
:
12486 return "move\t%0,%z2";
12487 case SYNC_INSN1_LI
:
12488 return "li\t%0,%2";
12489 case SYNC_INSN1_ADDU
:
12490 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12491 case SYNC_INSN1_ADDIU
:
12492 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12493 case SYNC_INSN1_SUBU
:
12494 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12495 case SYNC_INSN1_AND
:
12496 return "and\t%0,%1,%z2";
12497 case SYNC_INSN1_ANDI
:
12498 return "andi\t%0,%1,%2";
12499 case SYNC_INSN1_OR
:
12500 return "or\t%0,%1,%z2";
12501 case SYNC_INSN1_ORI
:
12502 return "ori\t%0,%1,%2";
12503 case SYNC_INSN1_XOR
:
12504 return "xor\t%0,%1,%z2";
12505 case SYNC_INSN1_XORI
:
12506 return "xori\t%0,%1,%2";
12508 gcc_unreachable ();
12511 /* Return the asm template associated with sync_insn2 value TYPE. */
12513 static const char *
12514 mips_sync_insn2_template (enum attr_sync_insn2 type
)
12518 case SYNC_INSN2_NOP
:
12519 gcc_unreachable ();
12520 case SYNC_INSN2_AND
:
12521 return "and\t%0,%1,%z2";
12522 case SYNC_INSN2_XOR
:
12523 return "xor\t%0,%1,%z2";
12524 case SYNC_INSN2_NOT
:
12525 return "nor\t%0,%1,%.";
12527 gcc_unreachable ();
12530 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12531 the value of the one of the sync_* attributes. Return the operand
12532 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12533 have the associated attribute. */
12536 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
12539 default_value
= operands
[index
- 1];
12540 return default_value
;
12543 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12544 sequence for it. */
12547 mips_process_sync_loop (rtx insn
, rtx
*operands
)
12549 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
12550 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
12551 unsigned int tmp3_insn
;
12552 enum attr_sync_insn1 insn1
;
12553 enum attr_sync_insn2 insn2
;
12556 enum memmodel model
;
12558 /* Read an operand from the sync_WHAT attribute and store it in
12559 variable WHAT. DEFAULT is the default value if no attribute
12561 #define READ_OPERAND(WHAT, DEFAULT) \
12562 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12565 /* Read the memory. */
12566 READ_OPERAND (mem
, 0);
12568 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
12570 /* Read the other attributes. */
12571 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
12572 READ_OPERAND (oldval
, at
);
12573 READ_OPERAND (cmp
, 0);
12574 READ_OPERAND (newval
, at
);
12575 READ_OPERAND (inclusive_mask
, 0);
12576 READ_OPERAND (exclusive_mask
, 0);
12577 READ_OPERAND (required_oldval
, 0);
12578 READ_OPERAND (insn1_op2
, 0);
12579 insn1
= get_attr_sync_insn1 (insn
);
12580 insn2
= get_attr_sync_insn2 (insn
);
12582 /* Don't bother setting CMP result that is never used. */
12583 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
12586 memmodel_attr
= get_attr_sync_memmodel (insn
);
12587 switch (memmodel_attr
)
12590 model
= MEMMODEL_ACQ_REL
;
12593 model
= MEMMODEL_ACQUIRE
;
12596 model
= (enum memmodel
) INTVAL (operands
[memmodel_attr
]);
12599 mips_multi_start ();
12601 /* Output the release side of the memory barrier. */
12602 if (need_atomic_barrier_p (model
, true))
12604 if (required_oldval
== 0 && TARGET_OCTEON
)
12606 /* Octeon doesn't reorder reads, so a full barrier can be
12607 created by using SYNCW to order writes combined with the
12608 write from the following SC. When the SC successfully
12609 completes, we know that all preceding writes are also
12610 committed to the coherent memory system. It is possible
12611 for a single SYNCW to fail, but a pair of them will never
12612 fail, so we use two. */
12613 mips_multi_add_insn ("syncw", NULL
);
12614 mips_multi_add_insn ("syncw", NULL
);
12617 mips_multi_add_insn ("sync", NULL
);
12620 /* Output the branch-back label. */
12621 mips_multi_add_label ("1:");
12623 /* OLDVAL = *MEM. */
12624 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
12625 oldval
, mem
, NULL
);
12627 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12628 if (required_oldval
)
12630 if (inclusive_mask
== 0)
12634 gcc_assert (oldval
!= at
);
12635 mips_multi_add_insn ("and\t%0,%1,%2",
12636 at
, oldval
, inclusive_mask
, NULL
);
12639 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
12641 /* CMP = 0 [delay slot]. */
12643 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
12646 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12647 if (exclusive_mask
== 0)
12651 gcc_assert (oldval
!= at
);
12652 mips_multi_add_insn ("and\t%0,%1,%z2",
12653 at
, oldval
, exclusive_mask
, NULL
);
12657 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12659 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12660 at least one instruction in that case. */
12661 if (insn1
== SYNC_INSN1_MOVE
12662 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
12666 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
12667 newval
, oldval
, insn1_op2
, NULL
);
12671 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12672 if (insn2
== SYNC_INSN2_NOP
)
12676 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
12677 newval
, tmp2
, inclusive_mask
, NULL
);
12680 tmp3_insn
= mips_multi_last_index ();
12682 /* $AT = $TMP1 | $TMP3. */
12683 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
12685 mips_multi_set_operand (tmp3_insn
, 0, at
);
12690 gcc_assert (tmp1
!= tmp3
);
12691 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
12694 /* if (!commit (*MEM = $AT)) goto 1.
12696 This will sometimes be a delayed branch; see the write code below
12698 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
12699 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
12701 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12702 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
12704 mips_multi_copy_insn (tmp3_insn
);
12705 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
12707 else if (!(required_oldval
&& cmp
))
12708 mips_multi_add_insn ("nop", NULL
);
12710 /* CMP = 1 -- either standalone or in a delay slot. */
12711 if (required_oldval
&& cmp
)
12712 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
12714 /* Output the acquire side of the memory barrier. */
12715 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
12716 mips_multi_add_insn ("sync", NULL
);
12718 /* Output the exit label, if needed. */
12719 if (required_oldval
)
12720 mips_multi_add_label ("2:");
12722 #undef READ_OPERAND
12725 /* Output and/or return the asm template for sync loop INSN, which has
12726 the operands given by OPERANDS. */
12729 mips_output_sync_loop (rtx insn
, rtx
*operands
)
12731 mips_process_sync_loop (insn
, operands
);
12733 /* Use branch-likely instructions to work around the LL/SC R10000
12735 mips_branch_likely
= TARGET_FIX_R10000
;
12737 mips_push_asm_switch (&mips_noreorder
);
12738 mips_push_asm_switch (&mips_nomacro
);
12739 mips_push_asm_switch (&mips_noat
);
12740 mips_start_ll_sc_sync_block ();
12742 mips_multi_write ();
12744 mips_end_ll_sc_sync_block ();
12745 mips_pop_asm_switch (&mips_noat
);
12746 mips_pop_asm_switch (&mips_nomacro
);
12747 mips_pop_asm_switch (&mips_noreorder
);
12752 /* Return the number of individual instructions in sync loop INSN,
12753 which has the operands given by OPERANDS. */
12756 mips_sync_loop_insns (rtx insn
, rtx
*operands
)
12758 mips_process_sync_loop (insn
, operands
);
12759 return mips_multi_num_insns
;
12762 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12763 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12765 When working around R4000 and R4400 errata, we need to make sure that
12766 the division is not immediately followed by a shift[1][2]. We also
12767 need to stop the division from being put into a branch delay slot[3].
12768 The easiest way to avoid both problems is to add a nop after the
12769 division. When a divide-by-zero check is needed, this nop can be
12770 used to fill the branch delay slot.
12772 [1] If a double-word or a variable shift executes immediately
12773 after starting an integer division, the shift may give an
12774 incorrect result. See quotations of errata #16 and #28 from
12775 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12776 in mips.md for details.
12778 [2] A similar bug to [1] exists for all revisions of the
12779 R4000 and the R4400 when run in an MC configuration.
12780 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12782 "19. In this following sequence:
12784 ddiv (or ddivu or div or divu)
12785 dsll32 (or dsrl32, dsra32)
12787 if an MPT stall occurs, while the divide is slipping the cpu
12788 pipeline, then the following double shift would end up with an
12791 Workaround: The compiler needs to avoid generating any
12792 sequence with divide followed by extended double shift."
12794 This erratum is also present in "MIPS R4400MC Errata, Processor
12795 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12796 & 3.0" as errata #10 and #4, respectively.
12798 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12799 (also valid for MIPS R4000MC processors):
12801 "52. R4000SC: This bug does not apply for the R4000PC.
12803 There are two flavors of this bug:
12805 1) If the instruction just after divide takes an RF exception
12806 (tlb-refill, tlb-invalid) and gets an instruction cache
12807 miss (both primary and secondary) and the line which is
12808 currently in secondary cache at this index had the first
12809 data word, where the bits 5..2 are set, then R4000 would
12810 get a wrong result for the div.
12815 ------------------- # end-of page. -tlb-refill
12820 ------------------- # end-of page. -tlb-invalid
12823 2) If the divide is in the taken branch delay slot, where the
12824 target takes RF exception and gets an I-cache miss for the
12825 exception vector or where I-cache miss occurs for the
12826 target address, under the above mentioned scenarios, the
12827 div would get wrong results.
12830 j r2 # to next page mapped or unmapped
12831 div r8,r9 # this bug would be there as long
12832 # as there is an ICache miss and
12833 nop # the "data pattern" is present
12836 beq r0, r0, NextPage # to Next page
12840 This bug is present for div, divu, ddiv, and ddivu
12843 Workaround: For item 1), OS could make sure that the next page
12844 after the divide instruction is also mapped. For item 2), the
12845 compiler could make sure that the divide instruction is not in
12846 the branch delay slot."
12848 These processors have PRId values of 0x00004220 and 0x00004300 for
12849 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12852 mips_output_division (const char *division
, rtx
*operands
)
12857 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
12859 output_asm_insn (s
, operands
);
12862 if (TARGET_CHECK_ZERO_DIV
)
12866 output_asm_insn (s
, operands
);
12867 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
12869 else if (GENERATE_DIVIDE_TRAPS
)
12871 /* Avoid long replay penalty on load miss by putting the trap before
12874 output_asm_insn ("teq\t%2,%.,7", operands
);
12877 output_asm_insn (s
, operands
);
12878 s
= "teq\t%2,%.,7";
12883 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
12884 output_asm_insn (s
, operands
);
12885 s
= "break\t7%)\n1:";
12891 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12892 instruction and if OUT_INSN assigns to the accumulator operand. */
12895 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
12897 enum attr_accum_in accum_in
;
12898 int accum_in_opnum
;
12901 if (recog_memoized (in_insn
) < 0)
12904 accum_in
= get_attr_accum_in (in_insn
);
12905 if (accum_in
== ACCUM_IN_NONE
)
12908 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
12910 extract_insn (in_insn
);
12911 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
12912 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
12914 return reg_set_p (accum_in_op
, out_insn
);
12917 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12918 data rather than the address. We need this because the cprestore
12919 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12920 which causes the default routine to abort. We just return false
12924 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
12926 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
12929 return !store_data_bypass_p (out_insn
, in_insn
);
12933 /* Variables and flags used in scheduler hooks when tuning for
12937 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12940 /* If true, then next ALU1/2 instruction will go to ALU1. */
12943 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12946 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12947 int alu1_core_unit_code
;
12948 int alu2_core_unit_code
;
12949 int falu1_core_unit_code
;
12950 int falu2_core_unit_code
;
12952 /* True if current cycle has a multi instruction.
12953 This flag is used in mips_ls2_dfa_post_advance_cycle. */
12954 bool cycle_has_multi_p
;
12956 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
12957 These are used in mips_ls2_dfa_post_advance_cycle to initialize
12959 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
12960 instruction to go ALU1. */
12961 rtx alu1_turn_enabled_insn
;
12962 rtx alu2_turn_enabled_insn
;
12963 rtx falu1_turn_enabled_insn
;
12964 rtx falu2_turn_enabled_insn
;
12967 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12968 dependencies have no cost, except on the 20Kc where output-dependence
12969 is treated like input-dependence. */
12972 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
12973 rtx dep ATTRIBUTE_UNUSED
, int cost
)
12975 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
12978 if (REG_NOTE_KIND (link
) != 0)
12983 /* Return the number of instructions that can be issued per cycle. */
12986 mips_issue_rate (void)
12990 case PROCESSOR_74KC
:
12991 case PROCESSOR_74KF2_1
:
12992 case PROCESSOR_74KF1_1
:
12993 case PROCESSOR_74KF3_2
:
12994 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12995 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12996 but in reality only a maximum of 3 insns can be issued as
12997 floating-point loads and stores also require a slot in the
12999 case PROCESSOR_R10000
:
13000 /* All R10K Processors are quad-issue (being the first MIPS
13001 processors to support this feature). */
13004 case PROCESSOR_20KC
:
13005 case PROCESSOR_R4130
:
13006 case PROCESSOR_R5400
:
13007 case PROCESSOR_R5500
:
13008 case PROCESSOR_R7000
:
13009 case PROCESSOR_R9000
:
13010 case PROCESSOR_OCTEON
:
13011 case PROCESSOR_OCTEON2
:
13014 case PROCESSOR_SB1
:
13015 case PROCESSOR_SB1A
:
13016 /* This is actually 4, but we get better performance if we claim 3.
13017 This is partly because of unwanted speculative code motion with the
13018 larger number, and partly because in most common cases we can't
13019 reach the theoretical max of 4. */
13022 case PROCESSOR_LOONGSON_2E
:
13023 case PROCESSOR_LOONGSON_2F
:
13024 case PROCESSOR_LOONGSON_3A
:
13027 case PROCESSOR_XLP
:
13028 return (reload_completed
? 4 : 3);
13035 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13038 mips_ls2_init_dfa_post_cycle_insn (void)
13041 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13042 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
13046 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13047 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
13051 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13052 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
13056 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13057 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
13060 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
13061 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
13062 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
13063 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
13066 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13067 Init data used in mips_dfa_post_advance_cycle. */
13070 mips_init_dfa_post_cycle_insn (void)
13072 if (TUNE_LOONGSON_2EF
)
13073 mips_ls2_init_dfa_post_cycle_insn ();
13076 /* Initialize STATE when scheduling for Loongson 2E/2F.
13077 Support round-robin dispatch scheme by enabling only one of
13078 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13082 mips_ls2_dfa_post_advance_cycle (state_t state
)
13084 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
13086 /* Though there are no non-pipelined ALU1 insns,
13087 we can get an instruction of type 'multi' before reload. */
13088 gcc_assert (mips_ls2
.cycle_has_multi_p
);
13089 mips_ls2
.alu1_turn_p
= false;
13092 mips_ls2
.cycle_has_multi_p
= false;
13094 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
13095 /* We have a non-pipelined alu instruction in the core,
13096 adjust round-robin counter. */
13097 mips_ls2
.alu1_turn_p
= true;
13099 if (mips_ls2
.alu1_turn_p
)
13101 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
13102 gcc_unreachable ();
13106 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
13107 gcc_unreachable ();
13110 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
13112 /* There are no non-pipelined FALU1 insns. */
13113 gcc_unreachable ();
13114 mips_ls2
.falu1_turn_p
= false;
13117 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
13118 /* We have a non-pipelined falu instruction in the core,
13119 adjust round-robin counter. */
13120 mips_ls2
.falu1_turn_p
= true;
13122 if (mips_ls2
.falu1_turn_p
)
13124 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
13125 gcc_unreachable ();
13129 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
13130 gcc_unreachable ();
13134 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13135 This hook is being called at the start of each cycle. */
13138 mips_dfa_post_advance_cycle (void)
13140 if (TUNE_LOONGSON_2EF
)
13141 mips_ls2_dfa_post_advance_cycle (curr_state
);
13144 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13145 be as wide as the scheduling freedom in the DFA. */
13148 mips_multipass_dfa_lookahead (void)
13150 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13154 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
13163 /* Remove the instruction at index LOWER from ready queue READY and
13164 reinsert it in front of the instruction at index HIGHER. LOWER must
13168 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
13173 new_head
= ready
[lower
];
13174 for (i
= lower
; i
< higher
; i
++)
13175 ready
[i
] = ready
[i
+ 1];
13176 ready
[i
] = new_head
;
13179 /* If the priority of the instruction at POS2 in the ready queue READY
13180 is within LIMIT units of that of the instruction at POS1, swap the
13181 instructions if POS2 is not already less than POS1. */
13184 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
13187 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
13191 temp
= ready
[pos1
];
13192 ready
[pos1
] = ready
[pos2
];
13193 ready
[pos2
] = temp
;
13197 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13198 that may clobber hi or lo. */
13199 static rtx mips_macc_chains_last_hilo
;
13201 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13202 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13205 mips_macc_chains_record (rtx insn
)
13207 if (get_attr_may_clobber_hilo (insn
))
13208 mips_macc_chains_last_hilo
= insn
;
13211 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13212 has NREADY elements, looking for a multiply-add or multiply-subtract
13213 instruction that is cumulative with mips_macc_chains_last_hilo.
13214 If there is one, promote it ahead of anything else that might
13215 clobber hi or lo. */
13218 mips_macc_chains_reorder (rtx
*ready
, int nready
)
13222 if (mips_macc_chains_last_hilo
!= 0)
13223 for (i
= nready
- 1; i
>= 0; i
--)
13224 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
13226 for (j
= nready
- 1; j
> i
; j
--)
13227 if (recog_memoized (ready
[j
]) >= 0
13228 && get_attr_may_clobber_hilo (ready
[j
]))
13230 mips_promote_ready (ready
, i
, j
);
13237 /* The last instruction to be scheduled. */
13238 static rtx vr4130_last_insn
;
13240 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13241 points to an rtx that is initially an instruction. Nullify the rtx
13242 if the instruction uses the value of register X. */
13245 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13250 insn_ptr
= (rtx
*) data
;
13253 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
13257 /* Return true if there is true register dependence between vr4130_last_insn
13261 vr4130_true_reg_dependence_p (rtx insn
)
13263 note_stores (PATTERN (vr4130_last_insn
),
13264 vr4130_true_reg_dependence_p_1
, &insn
);
13268 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13269 the ready queue and that INSN2 is the instruction after it, return
13270 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13271 in which INSN1 and INSN2 can probably issue in parallel, but for
13272 which (INSN2, INSN1) should be less sensitive to instruction
13273 alignment than (INSN1, INSN2). See 4130.md for more details. */
13276 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
13278 sd_iterator_def sd_it
;
13281 /* Check for the following case:
13283 1) there is some other instruction X with an anti dependence on INSN1;
13284 2) X has a higher priority than INSN2; and
13285 3) X is an arithmetic instruction (and thus has no unit restrictions).
13287 If INSN1 is the last instruction blocking X, it would better to
13288 choose (INSN1, X) over (INSN2, INSN1). */
13289 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
13290 if (DEP_TYPE (dep
) == REG_DEP_ANTI
13291 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
13292 && recog_memoized (DEP_CON (dep
)) >= 0
13293 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
13296 if (vr4130_last_insn
!= 0
13297 && recog_memoized (insn1
) >= 0
13298 && recog_memoized (insn2
) >= 0)
13300 /* See whether INSN1 and INSN2 use different execution units,
13301 or if they are both ALU-type instructions. If so, they can
13302 probably execute in parallel. */
13303 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
13304 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
13305 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
13307 /* If only one of the instructions has a dependence on
13308 vr4130_last_insn, prefer to schedule the other one first. */
13309 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
13310 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
13311 if (dep1_p
!= dep2_p
)
13314 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13315 is not an ALU-type instruction and if INSN1 uses the same
13316 execution unit. (Note that if this condition holds, we already
13317 know that INSN2 uses a different execution unit.) */
13318 if (class1
!= VR4130_CLASS_ALU
13319 && recog_memoized (vr4130_last_insn
) >= 0
13320 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
13327 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13328 queue with at least two instructions. Swap the first two if
13329 vr4130_swap_insns_p says that it could be worthwhile. */
13332 vr4130_reorder (rtx
*ready
, int nready
)
13334 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
13335 mips_promote_ready (ready
, nready
- 2, nready
- 1);
13338 /* Record whether last 74k AGEN instruction was a load or store. */
13339 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13341 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13342 resets to TYPE_UNKNOWN state. */
13345 mips_74k_agen_init (rtx insn
)
13347 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
13348 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13351 enum attr_type type
= get_attr_type (insn
);
13352 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
13353 mips_last_74k_agen_insn
= type
;
13357 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13358 loads to be grouped together, and multiple stores to be grouped
13359 together. Swap things around in the ready queue to make this happen. */
13362 mips_74k_agen_reorder (rtx
*ready
, int nready
)
13365 int store_pos
, load_pos
;
13370 for (i
= nready
- 1; i
>= 0; i
--)
13372 rtx insn
= ready
[i
];
13373 if (USEFUL_INSN_P (insn
))
13374 switch (get_attr_type (insn
))
13377 if (store_pos
== -1)
13382 if (load_pos
== -1)
13391 if (load_pos
== -1 || store_pos
== -1)
13394 switch (mips_last_74k_agen_insn
)
13397 /* Prefer to schedule loads since they have a higher latency. */
13399 /* Swap loads to the front of the queue. */
13400 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
13403 /* Swap stores to the front of the queue. */
13404 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
13411 /* Implement TARGET_SCHED_INIT. */
13414 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13415 int max_ready ATTRIBUTE_UNUSED
)
13417 mips_macc_chains_last_hilo
= 0;
13418 vr4130_last_insn
= 0;
13419 mips_74k_agen_init (NULL_RTX
);
13421 /* When scheduling for Loongson2, branch instructions go to ALU1,
13422 therefore basic block is most likely to start with round-robin counter
13423 pointed to ALU2. */
13424 mips_ls2
.alu1_turn_p
= false;
13425 mips_ls2
.falu1_turn_p
= true;
13428 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13431 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13432 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13434 if (!reload_completed
13435 && TUNE_MACC_CHAINS
13437 mips_macc_chains_reorder (ready
, *nreadyp
);
13439 if (reload_completed
13441 && !TARGET_VR4130_ALIGN
13443 vr4130_reorder (ready
, *nreadyp
);
13446 mips_74k_agen_reorder (ready
, *nreadyp
);
13449 /* Implement TARGET_SCHED_REORDER. */
13452 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13453 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13455 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13456 return mips_issue_rate ();
13459 /* Implement TARGET_SCHED_REORDER2. */
13462 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13463 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13465 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13466 return cached_can_issue_more
;
13469 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13472 mips_ls2_variable_issue (rtx insn
)
13474 if (mips_ls2
.alu1_turn_p
)
13476 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
13477 mips_ls2
.alu1_turn_p
= false;
13481 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
13482 mips_ls2
.alu1_turn_p
= true;
13485 if (mips_ls2
.falu1_turn_p
)
13487 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
13488 mips_ls2
.falu1_turn_p
= false;
13492 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
13493 mips_ls2
.falu1_turn_p
= true;
13496 if (recog_memoized (insn
) >= 0)
13497 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
13500 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13503 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13504 rtx insn
, int more
)
13506 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13507 if (USEFUL_INSN_P (insn
))
13509 if (get_attr_type (insn
) != TYPE_GHOST
)
13511 if (!reload_completed
&& TUNE_MACC_CHAINS
)
13512 mips_macc_chains_record (insn
);
13513 vr4130_last_insn
= insn
;
13515 mips_74k_agen_init (insn
);
13516 else if (TUNE_LOONGSON_2EF
)
13517 mips_ls2_variable_issue (insn
);
13520 /* Instructions of type 'multi' should all be split before
13521 the second scheduling pass. */
13522 gcc_assert (!reload_completed
13523 || recog_memoized (insn
) < 0
13524 || get_attr_type (insn
) != TYPE_MULTI
);
13526 cached_can_issue_more
= more
;
13530 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13531 return the first operand of the associated PREF or PREFX insn. */
13534 mips_prefetch_cookie (rtx write
, rtx locality
)
13536 /* store_streamed / load_streamed. */
13537 if (INTVAL (locality
) <= 0)
13538 return GEN_INT (INTVAL (write
) + 4);
13540 /* store / load. */
13541 if (INTVAL (locality
) <= 2)
13544 /* store_retained / load_retained. */
13545 return GEN_INT (INTVAL (write
) + 6);
13548 /* Flags that indicate when a built-in function is available.
13550 BUILTIN_AVAIL_NON_MIPS16
13551 The function is available on the current target, but only
13552 in non-MIPS16 mode. */
13553 #define BUILTIN_AVAIL_NON_MIPS16 1
13555 /* Declare an availability predicate for built-in functions that
13556 require non-MIPS16 mode and also require COND to be true.
13557 NAME is the main part of the predicate's name. */
13558 #define AVAIL_NON_MIPS16(NAME, COND) \
13559 static unsigned int \
13560 mips_builtin_avail_##NAME (void) \
13562 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13565 /* This structure describes a single built-in function. */
13566 struct mips_builtin_description
{
13567 /* The code of the main .md file instruction. See mips_builtin_type
13568 for more information. */
13569 enum insn_code icode
;
13571 /* The floating-point comparison code to use with ICODE, if any. */
13572 enum mips_fp_condition cond
;
13574 /* The name of the built-in function. */
13577 /* Specifies how the function should be expanded. */
13578 enum mips_builtin_type builtin_type
;
13580 /* The function's prototype. */
13581 enum mips_function_type function_type
;
13583 /* Whether the function is available. */
13584 unsigned int (*avail
) (void);
13587 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
13588 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
13589 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
13590 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
13591 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
13592 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
13593 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
13594 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
13595 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
13596 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
13598 /* Construct a mips_builtin_description from the given arguments.
13600 INSN is the name of the associated instruction pattern, without the
13601 leading CODE_FOR_mips_.
13603 CODE is the floating-point condition code associated with the
13604 function. It can be 'f' if the field is not applicable.
13606 NAME is the name of the function itself, without the leading
13609 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13611 AVAIL is the name of the availability predicate, without the leading
13612 mips_builtin_avail_. */
13613 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13614 FUNCTION_TYPE, AVAIL) \
13615 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13616 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13617 mips_builtin_avail_ ## AVAIL }
13619 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13620 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13621 are as for MIPS_BUILTIN. */
13622 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13623 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13625 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13626 are subject to mips_builtin_avail_<AVAIL>. */
13627 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13628 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13629 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13630 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13631 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13633 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13634 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13635 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13636 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13637 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13638 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13640 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13641 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13643 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13644 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13646 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13647 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13650 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13651 are subject to mips_builtin_avail_mips3d. */
13652 #define CMP_4S_BUILTINS(INSN, COND) \
13653 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13654 MIPS_BUILTIN_CMP_ANY, \
13655 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13656 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13657 MIPS_BUILTIN_CMP_ALL, \
13658 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13660 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13661 instruction requires mips_builtin_avail_<AVAIL>. */
13662 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13663 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13664 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13666 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13667 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13670 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13671 #define CMP_BUILTINS(COND) \
13672 MOVTF_BUILTINS (c, COND, paired_single), \
13673 MOVTF_BUILTINS (cabs, COND, mips3d), \
13674 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13675 CMP_PS_BUILTINS (c, COND, paired_single), \
13676 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13677 CMP_4S_BUILTINS (c, COND), \
13678 CMP_4S_BUILTINS (cabs, COND)
13680 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13681 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13682 and AVAIL are as for MIPS_BUILTIN. */
13683 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13684 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13685 FUNCTION_TYPE, AVAIL)
13687 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13688 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13689 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13690 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13691 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13693 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13694 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13695 builtin_description field. */
13696 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13697 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13698 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13699 FUNCTION_TYPE, mips_builtin_avail_loongson }
13701 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13702 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13703 builtin_description field. */
13704 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13705 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13707 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13708 We use functions of this form when the same insn can be usefully applied
13709 to more than one datatype. */
13710 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13711 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13713 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13714 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13715 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13716 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13717 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13718 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13719 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13720 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13722 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13723 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13724 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13725 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13726 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13727 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13728 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13729 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13730 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13731 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13732 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13733 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13734 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13735 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13736 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13737 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13738 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13739 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13740 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13741 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13742 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13743 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13744 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13745 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13746 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13747 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13748 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13749 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13750 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13751 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13753 static const struct mips_builtin_description mips_builtins
[] = {
13754 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13755 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13756 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13757 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13758 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
13759 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13760 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13761 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
13763 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
13764 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13765 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13766 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13767 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13769 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13770 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13771 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13772 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13773 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13774 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13776 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13777 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13778 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13779 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13780 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13781 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13783 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
13785 /* Built-in functions for the SB-1 processor. */
13786 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
13788 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13789 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13790 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13791 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13792 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13793 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13794 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13795 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13796 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13797 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13798 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13799 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13800 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13801 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13802 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
13803 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
13804 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
13805 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13806 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13807 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13808 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13809 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
13810 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
13811 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13812 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13813 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13814 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13815 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13816 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13817 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13818 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13819 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13820 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13821 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13822 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13823 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13824 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13825 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13826 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13827 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13828 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13829 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13830 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13831 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13832 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
13833 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13834 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
13835 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
13836 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13837 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13838 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13839 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13840 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13841 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13842 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13843 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13844 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13845 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13846 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13847 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13848 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
13849 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
13850 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13851 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13852 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13853 BPOSGE_BUILTIN (32, dsp
),
13855 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13856 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
13857 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13858 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13859 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13860 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13861 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13862 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13863 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13864 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13865 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13866 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13867 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13868 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13869 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13870 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13871 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
13872 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13873 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13874 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13875 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13876 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13877 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
13878 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13879 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13880 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13881 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13882 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13883 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13884 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13885 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13886 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13887 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13888 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13889 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13891 /* Built-in functions for the DSP ASE (32-bit only). */
13892 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13893 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13894 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13895 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13896 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13897 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13898 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13899 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13900 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13901 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13902 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13903 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13904 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13905 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13906 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13907 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13908 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13909 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13910 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13911 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13912 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13913 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13914 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13915 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13916 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13917 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
13918 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
13920 /* Built-in functions for the DSP ASE (64-bit only). */
13921 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
13923 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13924 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13925 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13926 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13927 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13928 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13929 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13930 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13931 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13932 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13934 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13935 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
13936 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
13937 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
13938 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13939 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13940 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13941 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13942 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13943 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13944 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
13945 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
13946 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13947 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13948 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13949 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13950 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
13951 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13952 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13953 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13954 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
13955 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13956 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13957 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13958 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13959 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13960 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13961 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13962 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13963 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13964 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13965 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13966 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13967 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13968 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13969 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13970 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13971 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13972 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
13973 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
13974 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13975 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13976 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13977 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13978 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13979 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13980 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13981 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13982 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
13983 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13984 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13985 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13986 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13987 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
13988 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
13989 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13990 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13991 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13992 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
13993 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13994 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
13995 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
13996 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13997 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13998 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13999 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14000 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14001 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14002 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14003 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14004 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14005 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14006 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14007 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14008 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14009 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14010 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14011 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14012 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14013 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14014 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14015 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14016 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14017 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
14018 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14019 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14020 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14021 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14022 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14023 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14024 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14025 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14026 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14027 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14028 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14029 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14030 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14031 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14032 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14033 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14035 /* Sundry other built-in functions. */
14036 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
14039 /* Index I is the function declaration for mips_builtins[I], or null if the
14040 function isn't defined on this target. */
14041 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
14043 /* MODE is a vector mode whose elements have type TYPE. Return the type
14044 of the vector itself. */
14047 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
14049 static tree types
[2 * (int) MAX_MACHINE_MODE
];
14052 mode_index
= (int) mode
;
14054 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
14055 mode_index
+= MAX_MACHINE_MODE
;
14057 if (types
[mode_index
] == NULL_TREE
)
14058 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
14059 return types
[mode_index
];
14062 /* Return a type for 'const volatile void *'. */
14065 mips_build_cvpointer_type (void)
14069 if (cache
== NULL_TREE
)
14070 cache
= build_pointer_type (build_qualified_type
14072 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
14076 /* Source-level argument types. */
14077 #define MIPS_ATYPE_VOID void_type_node
14078 #define MIPS_ATYPE_INT integer_type_node
14079 #define MIPS_ATYPE_POINTER ptr_type_node
14080 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14082 /* Standard mode-based argument types. */
14083 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14084 #define MIPS_ATYPE_SI intSI_type_node
14085 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14086 #define MIPS_ATYPE_DI intDI_type_node
14087 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14088 #define MIPS_ATYPE_SF float_type_node
14089 #define MIPS_ATYPE_DF double_type_node
14091 /* Vector argument types. */
14092 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14093 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14094 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14095 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14096 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14097 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14098 #define MIPS_ATYPE_UV2SI \
14099 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14100 #define MIPS_ATYPE_UV4HI \
14101 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14102 #define MIPS_ATYPE_UV8QI \
14103 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14105 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14106 their associated MIPS_ATYPEs. */
14107 #define MIPS_FTYPE_ATYPES1(A, B) \
14108 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14110 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14111 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14113 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14114 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14116 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14117 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14120 /* Return the function type associated with function prototype TYPE. */
14123 mips_build_function_type (enum mips_function_type type
)
14125 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
14127 if (types
[(int) type
] == NULL_TREE
)
14130 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14131 case MIPS_FTYPE_NAME##NUM ARGS: \
14132 types[(int) type] \
14133 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14136 #include "config/mips/mips-ftypes.def"
14137 #undef DEF_MIPS_FTYPE
14139 gcc_unreachable ();
14142 return types
[(int) type
];
14145 /* Implement TARGET_INIT_BUILTINS. */
14148 mips_init_builtins (void)
14150 const struct mips_builtin_description
*d
;
14153 /* Iterate through all of the bdesc arrays, initializing all of the
14154 builtin functions. */
14155 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
14157 d
= &mips_builtins
[i
];
14159 mips_builtin_decls
[i
]
14160 = add_builtin_function (d
->name
,
14161 mips_build_function_type (d
->function_type
),
14162 i
, BUILT_IN_MD
, NULL
, NULL
);
14166 /* Implement TARGET_BUILTIN_DECL. */
14169 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
14171 if (code
>= ARRAY_SIZE (mips_builtins
))
14172 return error_mark_node
;
14173 return mips_builtin_decls
[code
];
14176 /* Take argument ARGNO from EXP's argument list and convert it into
14177 an expand operand. Store the operand in *OP. */
14180 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
14181 unsigned int argno
)
14186 arg
= CALL_EXPR_ARG (exp
, argno
);
14187 value
= expand_normal (arg
);
14188 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
14191 /* Expand instruction ICODE as part of a built-in function sequence.
14192 Use the first NOPS elements of OPS as the instruction's operands.
14193 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14194 instruction has no target.
14196 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14199 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
14200 struct expand_operand
*ops
, bool has_target_p
)
14202 if (!maybe_expand_insn (icode
, nops
, ops
))
14204 error ("invalid argument to built-in function");
14205 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
14207 return has_target_p
? ops
[0].value
: const0_rtx
;
14210 /* Expand a floating-point comparison for built-in function call EXP.
14211 The first NARGS arguments are the values to be compared. ICODE is
14212 the .md pattern that does the comparison and COND is the condition
14213 that is being tested. Return an rtx for the result. */
14216 mips_expand_builtin_compare_1 (enum insn_code icode
,
14217 enum mips_fp_condition cond
,
14218 tree exp
, int nargs
)
14220 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14224 /* The instruction should have a target operand, an operand for each
14225 argument, and an operand for COND. */
14226 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
14228 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
14230 create_fixed_operand (&ops
[opno
++], output
);
14231 for (argno
= 0; argno
< nargs
; argno
++)
14232 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14233 create_integer_operand (&ops
[opno
++], (int) cond
);
14234 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
14237 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14238 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14239 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14240 suggests a good place to put the result. */
14243 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
14246 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14249 /* Map any target to operand 0. */
14252 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
14254 /* Map the arguments to the other operands. */
14255 gcc_assert (opno
+ call_expr_nargs (exp
)
14256 == insn_data
[icode
].n_generator_args
);
14257 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
14258 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14260 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
14263 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14264 function; TYPE says which. EXP is the CALL_EXPR that calls the
14265 function, ICODE is the instruction that should be used to compare
14266 the first two arguments, and COND is the condition it should test.
14267 TARGET, if nonnull, suggests a good place to put the result. */
14270 mips_expand_builtin_movtf (enum mips_builtin_type type
,
14271 enum insn_code icode
, enum mips_fp_condition cond
,
14272 rtx target
, tree exp
)
14274 struct expand_operand ops
[4];
14277 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
14278 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
14279 if (type
== MIPS_BUILTIN_MOVT
)
14281 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
14282 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
14286 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
14287 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
14289 create_fixed_operand (&ops
[3], cmp_result
);
14290 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
14294 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14295 into TARGET otherwise. Return TARGET. */
14298 mips_builtin_branch_and_move (rtx condition
, rtx target
,
14299 rtx value_if_true
, rtx value_if_false
)
14301 rtx true_label
, done_label
;
14303 true_label
= gen_label_rtx ();
14304 done_label
= gen_label_rtx ();
14306 /* First assume that CONDITION is false. */
14307 mips_emit_move (target
, value_if_false
);
14309 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14310 emit_jump_insn (gen_condjump (condition
, true_label
));
14311 emit_jump_insn (gen_jump (done_label
));
14314 /* Fix TARGET if CONDITION is true. */
14315 emit_label (true_label
);
14316 mips_emit_move (target
, value_if_true
);
14318 emit_label (done_label
);
14322 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14323 the CALL_EXPR that calls the function, ICODE is the code of the
14324 comparison instruction, and COND is the condition it should test.
14325 TARGET, if nonnull, suggests a good place to put the boolean result. */
14328 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
14329 enum insn_code icode
, enum mips_fp_condition cond
,
14330 rtx target
, tree exp
)
14332 rtx offset
, condition
, cmp_result
;
14334 if (target
== 0 || GET_MODE (target
) != SImode
)
14335 target
= gen_reg_rtx (SImode
);
14336 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
14337 call_expr_nargs (exp
));
14339 /* If the comparison sets more than one register, we define the result
14340 to be 0 if all registers are false and -1 if all registers are true.
14341 The value of the complete result is indeterminate otherwise. */
14342 switch (builtin_type
)
14344 case MIPS_BUILTIN_CMP_ALL
:
14345 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
14346 return mips_builtin_branch_and_move (condition
, target
,
14347 const0_rtx
, const1_rtx
);
14349 case MIPS_BUILTIN_CMP_UPPER
:
14350 case MIPS_BUILTIN_CMP_LOWER
:
14351 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
14352 condition
= gen_single_cc (cmp_result
, offset
);
14353 return mips_builtin_branch_and_move (condition
, target
,
14354 const1_rtx
, const0_rtx
);
14357 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
14358 return mips_builtin_branch_and_move (condition
, target
,
14359 const1_rtx
, const0_rtx
);
14363 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14364 if nonnull, suggests a good place to put the boolean result. */
14367 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
14369 rtx condition
, cmp_result
;
14372 if (target
== 0 || GET_MODE (target
) != SImode
)
14373 target
= gen_reg_rtx (SImode
);
14375 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
14377 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
14382 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
14383 return mips_builtin_branch_and_move (condition
, target
,
14384 const1_rtx
, const0_rtx
);
14387 /* Implement TARGET_EXPAND_BUILTIN. */
14390 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14391 enum machine_mode mode
, int ignore
)
14394 unsigned int fcode
, avail
;
14395 const struct mips_builtin_description
*d
;
14397 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14398 fcode
= DECL_FUNCTION_CODE (fndecl
);
14399 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
14400 d
= &mips_builtins
[fcode
];
14401 avail
= d
->avail ();
14402 gcc_assert (avail
!= 0);
14405 error ("built-in function %qE not supported for MIPS16",
14406 DECL_NAME (fndecl
));
14407 return ignore
? const0_rtx
: CONST0_RTX (mode
);
14409 switch (d
->builtin_type
)
14411 case MIPS_BUILTIN_DIRECT
:
14412 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
14414 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
14415 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
14417 case MIPS_BUILTIN_MOVT
:
14418 case MIPS_BUILTIN_MOVF
:
14419 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
14420 d
->cond
, target
, exp
);
14422 case MIPS_BUILTIN_CMP_ANY
:
14423 case MIPS_BUILTIN_CMP_ALL
:
14424 case MIPS_BUILTIN_CMP_UPPER
:
14425 case MIPS_BUILTIN_CMP_LOWER
:
14426 case MIPS_BUILTIN_CMP_SINGLE
:
14427 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
14428 d
->cond
, target
, exp
);
14430 case MIPS_BUILTIN_BPOSGE32
:
14431 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
14433 gcc_unreachable ();
14436 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14437 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14438 struct mips16_constant
{
14439 struct mips16_constant
*next
;
14442 enum machine_mode mode
;
14445 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14446 first constant, HIGHEST_ADDRESS is the highest address that the first
14447 byte of the pool can have, and INSN_ADDRESS is the current instruction
14449 struct mips16_constant_pool
{
14450 struct mips16_constant
*first
;
14451 int highest_address
;
14455 /* Add constant VALUE to POOL and return its label. MODE is the
14456 value's mode (used for CONST_INTs, etc.). */
14459 mips16_add_constant (struct mips16_constant_pool
*pool
,
14460 rtx value
, enum machine_mode mode
)
14462 struct mips16_constant
**p
, *c
;
14463 bool first_of_size_p
;
14465 /* See whether the constant is already in the pool. If so, return the
14466 existing label, otherwise leave P pointing to the place where the
14467 constant should be added.
14469 Keep the pool sorted in increasing order of mode size so that we can
14470 reduce the number of alignments needed. */
14471 first_of_size_p
= true;
14472 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
14474 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
14475 return (*p
)->label
;
14476 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
14478 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
14479 first_of_size_p
= false;
14482 /* In the worst case, the constant needed by the earliest instruction
14483 will end up at the end of the pool. The entire pool must then be
14484 accessible from that instruction.
14486 When adding the first constant, set the pool's highest address to
14487 the address of the first out-of-range byte. Adjust this address
14488 downwards each time a new constant is added. */
14489 if (pool
->first
== 0)
14490 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14491 of the instruction with the lowest two bits clear. The base PC
14492 value for LDPC has the lowest three bits clear. Assume the worst
14493 case here; namely that the PC-relative instruction occupies the
14494 last 2 bytes in an aligned word. */
14495 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
14496 pool
->highest_address
-= GET_MODE_SIZE (mode
);
14497 if (first_of_size_p
)
14498 /* Take into account the worst possible padding due to alignment. */
14499 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
14501 /* Create a new entry. */
14502 c
= XNEW (struct mips16_constant
);
14505 c
->label
= gen_label_rtx ();
14512 /* Output constant VALUE after instruction INSN and return the last
14513 instruction emitted. MODE is the mode of the constant. */
14516 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
14518 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
14520 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
14521 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
14524 if (SCALAR_FLOAT_MODE_P (mode
))
14525 return emit_insn_after (gen_consttable_float (value
), insn
);
14527 if (VECTOR_MODE_P (mode
))
14531 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
14532 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
14533 CONST_VECTOR_ELT (value
, i
), insn
);
14537 gcc_unreachable ();
14540 /* Dump out the constants in CONSTANTS after INSN. */
14543 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
14545 struct mips16_constant
*c
, *next
;
14549 for (c
= constants
; c
!= NULL
; c
= next
)
14551 /* If necessary, increase the alignment of PC. */
14552 if (align
< GET_MODE_SIZE (c
->mode
))
14554 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
14555 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
14557 align
= GET_MODE_SIZE (c
->mode
);
14559 insn
= emit_label_after (c
->label
, insn
);
14560 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
14566 emit_barrier_after (insn
);
14569 /* Return the length of instruction INSN. */
14572 mips16_insn_length (rtx insn
)
14574 if (JUMP_TABLE_DATA_P (insn
))
14576 rtx body
= PATTERN (insn
);
14577 if (GET_CODE (body
) == ADDR_VEC
)
14578 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
14579 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
14580 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
14582 gcc_unreachable ();
14584 return get_attr_length (insn
);
14587 /* If *X is a symbolic constant that refers to the constant pool, add
14588 the constant to POOL and rewrite *X to use the constant's label. */
14591 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
14593 rtx base
, offset
, label
;
14595 split_const (*x
, &base
, &offset
);
14596 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
14598 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
14599 get_pool_mode (base
));
14600 base
= gen_rtx_LABEL_REF (Pmode
, label
);
14601 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
14605 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14606 INSN is the instruction we're rewriting and POOL points to the current
14608 struct mips16_rewrite_pool_refs_info
{
14610 struct mips16_constant_pool
*pool
;
14613 /* Rewrite *X so that constant pool references refer to the constant's
14614 label instead. DATA points to a mips16_rewrite_pool_refs_info
14618 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
14620 struct mips16_rewrite_pool_refs_info
*info
=
14621 (struct mips16_rewrite_pool_refs_info
*) data
;
14623 if (force_to_mem_operand (*x
, Pmode
))
14625 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
14626 validate_change (info
->insn
, x
, mem
, false);
14631 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
14635 /* Don't rewrite the __mips16_rdwr symbol. */
14636 if (GET_CODE (*x
) == UNSPEC
&& XINT (*x
, 1) == UNSPEC_TLS_GET_TP
)
14639 if (TARGET_MIPS16_TEXT_LOADS
)
14640 mips16_rewrite_pool_constant (info
->pool
, x
);
14642 return GET_CODE (*x
) == CONST
? -1 : 0;
14645 /* Return whether CFG is used in mips_reorg. */
14648 mips_cfg_in_reorg (void)
14650 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
14651 || TARGET_RELAX_PIC_CALLS
);
14654 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14655 otherwise assume that they are already split. */
14658 mips16_lay_out_constants (bool split_p
)
14660 struct mips16_constant_pool pool
;
14661 struct mips16_rewrite_pool_refs_info info
;
14664 if (!TARGET_MIPS16_PCREL_LOADS
)
14669 if (mips_cfg_in_reorg ())
14670 split_all_insns ();
14672 split_all_insns_noflow ();
14675 memset (&pool
, 0, sizeof (pool
));
14676 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14678 /* Rewrite constant pool references in INSN. */
14679 if (USEFUL_INSN_P (insn
))
14683 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
14686 pool
.insn_address
+= mips16_insn_length (insn
);
14688 if (pool
.first
!= NULL
)
14690 /* If there are no natural barriers between the first user of
14691 the pool and the highest acceptable address, we'll need to
14692 create a new instruction to jump around the constant pool.
14693 In the worst case, this instruction will be 4 bytes long.
14695 If it's too late to do this transformation after INSN,
14696 do it immediately before INSN. */
14697 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
14701 label
= gen_label_rtx ();
14703 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
14704 JUMP_LABEL (jump
) = label
;
14705 LABEL_NUSES (label
) = 1;
14706 barrier
= emit_barrier_after (jump
);
14708 emit_label_after (label
, barrier
);
14709 pool
.insn_address
+= 4;
14712 /* See whether the constant pool is now out of range of the first
14713 user. If so, output the constants after the previous barrier.
14714 Note that any instructions between BARRIER and INSN (inclusive)
14715 will use negative offsets to refer to the pool. */
14716 if (pool
.insn_address
> pool
.highest_address
)
14718 mips16_emit_constants (pool
.first
, barrier
);
14722 else if (BARRIER_P (insn
))
14726 mips16_emit_constants (pool
.first
, get_last_insn ());
14729 /* Return true if it is worth r10k_simplify_address's while replacing
14730 an address with X. We are looking for constants, and for addresses
14731 at a known offset from the incoming stack pointer. */
14734 r10k_simplified_address_p (rtx x
)
14736 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
14738 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
14741 /* X is an expression that appears in INSN. Try to use the UD chains
14742 to simplify it, returning the simplified form on success and the
14743 original form otherwise. Replace the incoming value of $sp with
14744 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14747 r10k_simplify_address (rtx x
, rtx insn
)
14749 rtx newx
, op0
, op1
, set
, def_insn
, note
;
14751 struct df_link
*defs
;
14756 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14757 if (op0
!= XEXP (x
, 0))
14758 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
14759 op0
, GET_MODE (XEXP (x
, 0)));
14761 else if (BINARY_P (x
))
14763 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14764 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
14765 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
14766 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
14768 else if (GET_CODE (x
) == LO_SUM
)
14770 /* LO_SUMs can be offset from HIGHs, if we know they won't
14771 overflow. See mips_classify_address for the rationale behind
14773 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14774 if (GET_CODE (op0
) == HIGH
)
14775 newx
= XEXP (x
, 1);
14777 else if (REG_P (x
))
14779 /* Uses are recorded by regno_reg_rtx, not X itself. */
14780 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
14782 defs
= DF_REF_CHAIN (use
);
14784 /* Require a single definition. */
14785 if (defs
&& defs
->next
== NULL
)
14788 if (DF_REF_IS_ARTIFICIAL (def
))
14790 /* Replace the incoming value of $sp with
14791 virtual_incoming_args_rtx. */
14792 if (x
== stack_pointer_rtx
14793 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR
)
14794 newx
= virtual_incoming_args_rtx
;
14796 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
14799 /* Make sure that DEF_INSN is a single set of REG. */
14800 def_insn
= DF_REF_INSN (def
);
14801 if (NONJUMP_INSN_P (def_insn
))
14803 set
= single_set (def_insn
);
14804 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
14806 /* Prefer to use notes, since the def-use chains
14807 are often shorter. */
14808 note
= find_reg_equal_equiv_note (def_insn
);
14810 newx
= XEXP (note
, 0);
14812 newx
= SET_SRC (set
);
14813 newx
= r10k_simplify_address (newx
, def_insn
);
14819 if (newx
&& r10k_simplified_address_p (newx
))
14824 /* Return true if ADDRESS is known to be an uncached address
14825 on R10K systems. */
14828 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
14830 unsigned HOST_WIDE_INT upper
;
14832 /* Check for KSEG1. */
14833 if (address
+ 0x60000000 < 0x20000000)
14836 /* Check for uncached XKPHYS addresses. */
14837 if (Pmode
== DImode
)
14839 upper
= (address
>> 40) & 0xf9ffff;
14840 if (upper
== 0x900000 || upper
== 0xb80000)
14846 /* Return true if we can prove that an access to address X in instruction
14847 INSN would be safe from R10K speculation. This X is a general
14848 expression; it might not be a legitimate address. */
14851 r10k_safe_address_p (rtx x
, rtx insn
)
14854 HOST_WIDE_INT offset_val
;
14856 x
= r10k_simplify_address (x
, insn
);
14858 /* Check for references to the stack frame. It doesn't really matter
14859 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14860 allows us to assume that accesses to any part of the eventual frame
14861 is safe from speculation at any point in the function. */
14862 mips_split_plus (x
, &base
, &offset_val
);
14863 if (base
== virtual_incoming_args_rtx
14864 && offset_val
>= -cfun
->machine
->frame
.total_size
14865 && offset_val
< cfun
->machine
->frame
.args_size
)
14868 /* Check for uncached addresses. */
14869 if (CONST_INT_P (x
))
14870 return r10k_uncached_address_p (INTVAL (x
));
14872 /* Check for accesses to a static object. */
14873 split_const (x
, &base
, &offset
);
14874 return offset_within_block_p (base
, INTVAL (offset
));
14877 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14878 an in-range access to an automatic variable, or to an object with
14879 a link-time-constant address. */
14882 r10k_safe_mem_expr_p (tree expr
, HOST_WIDE_INT offset
)
14884 HOST_WIDE_INT bitoffset
, bitsize
;
14885 tree inner
, var_offset
;
14886 enum machine_mode mode
;
14887 int unsigned_p
, volatile_p
;
14889 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
14890 &unsigned_p
, &volatile_p
, false);
14891 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
14894 offset
+= bitoffset
/ BITS_PER_UNIT
;
14895 return offset
>= 0 && offset
< tree_low_cst (DECL_SIZE_UNIT (inner
), 1);
14898 /* A for_each_rtx callback for which DATA points to the instruction
14899 containing *X. Stop the search if we find a MEM that is not safe
14900 from R10K speculation. */
14903 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
14912 && MEM_OFFSET_KNOWN_P (mem
)
14913 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
14916 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
14922 /* A note_stores callback for which DATA points to an instruction pointer.
14923 If *DATA is nonnull, make it null if it X contains a MEM that is not
14924 safe from R10K speculation. */
14927 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
14932 insn_ptr
= (rtx
*) data
;
14933 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
14934 *insn_ptr
= NULL_RTX
;
14937 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14938 Return nonzero if the call is not to a declared function. */
14941 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
14950 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
14956 /* Return true if instruction INSN needs to be protected by an R10K
14960 r10k_needs_protection_p (rtx insn
)
14963 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
14965 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
14967 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
14968 return insn
== NULL_RTX
;
14971 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
14974 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14975 edge is unconditional. */
14978 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
14983 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
14984 if (!single_succ_p (e
->src
)
14985 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
14986 || (e
->flags
& EDGE_COMPLEX
) != 0)
14991 /* Implement -mr10k-cache-barrier= for the current function. */
14994 r10k_insert_cache_barriers (void)
14996 int *rev_post_order
;
14999 sbitmap protected_bbs
;
15000 rtx insn
, end
, unprotected_region
;
15004 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15008 /* Calculate dominators. */
15009 calculate_dominance_info (CDI_DOMINATORS
);
15011 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15012 X is protected by a cache barrier. */
15013 protected_bbs
= sbitmap_alloc (last_basic_block
);
15014 bitmap_clear (protected_bbs
);
15016 /* Iterate over the basic blocks in reverse post-order. */
15017 rev_post_order
= XNEWVEC (int, last_basic_block
);
15018 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
15019 for (i
= 0; i
< n
; i
++)
15021 bb
= BASIC_BLOCK (rev_post_order
[i
]);
15023 /* If this block is only reached by unconditional edges, and if the
15024 source of every edge is protected, the beginning of the block is
15026 if (r10k_protected_bb_p (bb
, protected_bbs
))
15027 unprotected_region
= NULL_RTX
;
15029 unprotected_region
= pc_rtx
;
15030 end
= NEXT_INSN (BB_END (bb
));
15032 /* UNPROTECTED_REGION is:
15034 - null if we are processing a protected region,
15035 - pc_rtx if we are processing an unprotected region but have
15036 not yet found the first instruction in it
15037 - the first instruction in an unprotected region otherwise. */
15038 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
15040 if (unprotected_region
&& USEFUL_INSN_P (insn
))
15042 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
15043 /* This CACHE instruction protects the following code. */
15044 unprotected_region
= NULL_RTX
;
15047 /* See if INSN is the first instruction in this
15048 unprotected region. */
15049 if (unprotected_region
== pc_rtx
)
15050 unprotected_region
= insn
;
15052 /* See if INSN needs to be protected. If so,
15053 we must insert a cache barrier somewhere between
15054 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15055 clear which position is better performance-wise,
15056 but as a tie-breaker, we assume that it is better
15057 to allow delay slots to be back-filled where
15058 possible, and that it is better not to insert
15059 barriers in the middle of already-scheduled code.
15060 We therefore insert the barrier at the beginning
15062 if (r10k_needs_protection_p (insn
))
15064 emit_insn_before (gen_r10k_cache_barrier (),
15065 unprotected_region
);
15066 unprotected_region
= NULL_RTX
;
15072 /* The called function is not required to protect the exit path.
15073 The code that follows a call is therefore unprotected. */
15074 unprotected_region
= pc_rtx
;
15077 /* Record whether the end of this block is protected. */
15078 if (unprotected_region
== NULL_RTX
)
15079 bitmap_set_bit (protected_bbs
, bb
->index
);
15081 XDELETEVEC (rev_post_order
);
15083 sbitmap_free (protected_bbs
);
15085 free_dominance_info (CDI_DOMINATORS
);
15088 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15089 otherwise. If INSN has two call rtx, then store the second one in
15093 mips_call_expr_from_insn (rtx insn
, rtx
*second_call
)
15098 if (!CALL_P (insn
))
15101 x
= PATTERN (insn
);
15102 if (GET_CODE (x
) == PARALLEL
)
15104 /* Calls returning complex values have two CALL rtx. Look for the second
15105 one here, and return it via the SECOND_CALL arg. */
15106 x2
= XVECEXP (x
, 0, 1);
15107 if (GET_CODE (x2
) == SET
)
15109 if (GET_CODE (x2
) == CALL
)
15112 x
= XVECEXP (x
, 0, 0);
15114 if (GET_CODE (x
) == SET
)
15116 gcc_assert (GET_CODE (x
) == CALL
);
15121 /* REG is set in DEF. See if the definition is one of the ways we load a
15122 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15123 If it is, return the symbol reference of the function, otherwise return
15126 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15127 the values of source registers, otherwise treat such registers as
15128 having an unknown value. */
15131 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
15135 if (DF_REF_IS_ARTIFICIAL (def
))
15138 def_insn
= DF_REF_INSN (def
);
15139 set
= single_set (def_insn
);
15140 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
15142 rtx note
, src
, symbol
;
15144 /* First see whether the source is a plain symbol. This is used
15145 when calling symbols that are not lazily bound. */
15146 src
= SET_SRC (set
);
15147 if (GET_CODE (src
) == SYMBOL_REF
)
15150 /* Handle %call16 references. */
15151 symbol
= mips_strip_unspec_call (src
);
15154 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15158 /* If we have something more complicated, look for a
15159 REG_EQUAL or REG_EQUIV note. */
15160 note
= find_reg_equal_equiv_note (def_insn
);
15161 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
15162 return XEXP (note
, 0);
15164 /* Follow at most one simple register copy. Such copies are
15165 interesting in cases like:
15169 locally_binding_fn (...);
15174 locally_binding_fn (...);
15176 locally_binding_fn (...);
15178 where the load of locally_binding_fn can legitimately be
15179 hoisted or shared. However, we do not expect to see complex
15180 chains of copies, so a full worklist solution to the problem
15181 would probably be overkill. */
15182 if (recurse_p
&& REG_P (src
))
15183 return mips_find_pic_call_symbol (def_insn
, src
, false);
15189 /* Find the definition of the use of REG in INSN. See if the definition
15190 is one of the ways we load a register with a symbol address for a
15191 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15192 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15193 mips_pic_call_symbol_from_set. */
15196 mips_find_pic_call_symbol (rtx insn
, rtx reg
, bool recurse_p
)
15199 struct df_link
*defs
;
15202 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
15205 defs
= DF_REF_CHAIN (use
);
15208 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15212 /* If we have more than one definition, they need to be identical. */
15213 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
15217 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15218 if (!rtx_equal_p (symbol
, other
))
15225 /* Replace the args_size operand of the call expression CALL with the
15226 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15229 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
15233 args_size
= XEXP (call
, 1);
15234 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
15235 gen_rtvec (2, args_size
, symbol
),
15239 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15240 if instead of the arg_size argument it contains the call attributes. If
15241 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15242 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15246 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
15248 rtx args_size
, symbol
;
15250 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
15253 args_size
= operands
[args_size_opno
];
15254 if (GET_CODE (args_size
) != UNSPEC
)
15256 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
15258 symbol
= XVECEXP (args_size
, 0, 1);
15259 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15261 operands
[args_size_opno
] = symbol
;
15265 /* Use DF to annotate PIC indirect calls with the function symbol they
15269 mips_annotate_pic_calls (void)
15275 FOR_BB_INSNS (bb
, insn
)
15277 rtx call
, reg
, symbol
, second_call
;
15280 call
= mips_call_expr_from_insn (insn
, &second_call
);
15283 gcc_assert (MEM_P (XEXP (call
, 0)));
15284 reg
= XEXP (XEXP (call
, 0), 0);
15288 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
15291 mips_annotate_pic_call_expr (call
, symbol
);
15293 mips_annotate_pic_call_expr (second_call
, symbol
);
15298 /* A temporary variable used by for_each_rtx callbacks, etc. */
15299 static rtx mips_sim_insn
;
15301 /* A structure representing the state of the processor pipeline.
15302 Used by the mips_sim_* family of functions. */
15304 /* The maximum number of instructions that can be issued in a cycle.
15305 (Caches mips_issue_rate.) */
15306 unsigned int issue_rate
;
15308 /* The current simulation time. */
15311 /* How many more instructions can be issued in the current cycle. */
15312 unsigned int insns_left
;
15314 /* LAST_SET[X].INSN is the last instruction to set register X.
15315 LAST_SET[X].TIME is the time at which that instruction was issued.
15316 INSN is null if no instruction has yet set register X. */
15320 } last_set
[FIRST_PSEUDO_REGISTER
];
15322 /* The pipeline's current DFA state. */
15326 /* Reset STATE to the initial simulation state. */
15329 mips_sim_reset (struct mips_sim
*state
)
15331 curr_state
= state
->dfa_state
;
15334 state
->insns_left
= state
->issue_rate
;
15335 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
15336 state_reset (curr_state
);
15338 targetm
.sched
.init (0, false, 0);
15339 advance_state (curr_state
);
15342 /* Initialize STATE before its first use. DFA_STATE points to an
15343 allocated but uninitialized DFA state. */
15346 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
15348 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
15349 targetm
.sched
.init_dfa_pre_cycle_insn ();
15351 if (targetm
.sched
.init_dfa_post_cycle_insn
)
15352 targetm
.sched
.init_dfa_post_cycle_insn ();
15354 state
->issue_rate
= mips_issue_rate ();
15355 state
->dfa_state
= dfa_state
;
15356 mips_sim_reset (state
);
15359 /* Advance STATE by one clock cycle. */
15362 mips_sim_next_cycle (struct mips_sim
*state
)
15364 curr_state
= state
->dfa_state
;
15367 state
->insns_left
= state
->issue_rate
;
15368 advance_state (curr_state
);
15371 /* Advance simulation state STATE until instruction INSN can read
15375 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
15377 unsigned int regno
, end_regno
;
15379 end_regno
= END_REGNO (reg
);
15380 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
15381 if (state
->last_set
[regno
].insn
!= 0)
15385 t
= (state
->last_set
[regno
].time
15386 + insn_latency (state
->last_set
[regno
].insn
, insn
));
15387 while (state
->time
< t
)
15388 mips_sim_next_cycle (state
);
15392 /* A for_each_rtx callback. If *X is a register, advance simulation state
15393 DATA until mips_sim_insn can read the register's value. */
15396 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
15399 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
15403 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15406 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
15408 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
15411 /* Advance simulation state STATE until all of INSN's register
15412 dependencies are satisfied. */
15415 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
15417 mips_sim_insn
= insn
;
15418 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
15421 /* Advance simulation state STATE until the units required by
15422 instruction INSN are available. */
15425 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
15429 tmp_state
= alloca (state_size ());
15430 while (state
->insns_left
== 0
15431 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
15432 state_transition (tmp_state
, insn
) >= 0))
15433 mips_sim_next_cycle (state
);
15436 /* Advance simulation state STATE until INSN is ready to issue. */
15439 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
15441 mips_sim_wait_regs (state
, insn
);
15442 mips_sim_wait_units (state
, insn
);
15445 /* mips_sim_insn has just set X. Update the LAST_SET array
15446 in simulation state DATA. */
15449 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
15451 struct mips_sim
*state
;
15453 state
= (struct mips_sim
*) data
;
15456 unsigned int regno
, end_regno
;
15458 end_regno
= END_REGNO (x
);
15459 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
15461 state
->last_set
[regno
].insn
= mips_sim_insn
;
15462 state
->last_set
[regno
].time
= state
->time
;
15467 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15468 can issue immediately (i.e., that mips_sim_wait_insn has already
15472 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
15474 curr_state
= state
->dfa_state
;
15476 state_transition (curr_state
, insn
);
15477 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
15478 state
->insns_left
);
15480 mips_sim_insn
= insn
;
15481 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
15484 /* Simulate issuing a NOP in state STATE. */
15487 mips_sim_issue_nop (struct mips_sim
*state
)
15489 if (state
->insns_left
== 0)
15490 mips_sim_next_cycle (state
);
15491 state
->insns_left
--;
15494 /* Update simulation state STATE so that it's ready to accept the instruction
15495 after INSN. INSN should be part of the main rtl chain, not a member of a
15499 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
15501 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15503 mips_sim_issue_nop (state
);
15505 switch (GET_CODE (SEQ_BEGIN (insn
)))
15509 /* We can't predict the processor state after a call or label. */
15510 mips_sim_reset (state
);
15514 /* The delay slots of branch likely instructions are only executed
15515 when the branch is taken. Therefore, if the caller has simulated
15516 the delay slot instruction, STATE does not really reflect the state
15517 of the pipeline for the instruction after the delay slot. Also,
15518 branch likely instructions tend to incur a penalty when not taken,
15519 so there will probably be an extra delay between the branch and
15520 the instruction after the delay slot. */
15521 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
15522 mips_sim_reset (state
);
15530 /* Use simulator state STATE to calculate the execution time of
15531 instruction sequence SEQ. */
15533 static unsigned int
15534 mips_seq_time (struct mips_sim
*state
, rtx seq
)
15536 mips_sim_reset (state
);
15537 for (rtx insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
15539 mips_sim_wait_insn (state
, insn
);
15540 mips_sim_issue_insn (state
, insn
);
15542 return state
->time
;
15545 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15546 setting SETTING, using STATE to simulate instruction sequences. */
15548 static unsigned int
15549 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
15551 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
15554 enum machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
15555 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
15556 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
15558 /* If the target provides mulsidi3_32bit then that's the most likely
15559 consumer of the result. Test for bypasses. */
15560 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
15562 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
15563 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
15566 unsigned int time
= mips_seq_time (state
, get_insns ());
15571 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15572 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15573 Prefer MULT -- which is shorter -- in the event of a tie. */
15576 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
15579 /* No MTLO or MTHI available. */
15580 mips_tuning_info
.fast_mult_zero_zero_p
= true;
15583 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
15584 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
15585 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
15589 /* Set up costs based on the current architecture and tuning settings. */
15592 mips_set_tuning_info (void)
15594 if (mips_tuning_info
.initialized_p
15595 && mips_tuning_info
.arch
== mips_arch
15596 && mips_tuning_info
.tune
== mips_tune
15597 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
15600 mips_tuning_info
.arch
= mips_arch
;
15601 mips_tuning_info
.tune
= mips_tune
;
15602 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
15603 mips_tuning_info
.initialized_p
= true;
15607 struct mips_sim state
;
15608 mips_sim_init (&state
, alloca (state_size ()));
15610 mips_set_fast_mult_zero_zero_p (&state
);
15615 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15618 mips_expand_to_rtl_hook (void)
15620 /* We need to call this at a point where we can safely create sequences
15621 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15622 need to call it at a point where the DFA infrastructure is not
15623 already in use, so we can't just call it lazily on demand.
15625 At present, mips_tuning_info is only needed during post-expand
15626 RTL passes such as split_insns, so this hook should be early enough.
15627 We may need to move the call elsewhere if mips_tuning_info starts
15628 to be used for other things (such as rtx_costs, or expanders that
15629 could be called during gimple optimization). */
15630 mips_set_tuning_info ();
15633 /* The VR4130 pipeline issues aligned pairs of instructions together,
15634 but it stalls the second instruction if it depends on the first.
15635 In order to cut down the amount of logic required, this dependence
15636 check is not based on a full instruction decode. Instead, any non-SPECIAL
15637 instruction is assumed to modify the register specified by bits 20-16
15638 (which is usually the "rt" field).
15640 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15641 input, so we can end up with a false dependence between the branch
15642 and its delay slot. If this situation occurs in instruction INSN,
15643 try to avoid it by swapping rs and rt. */
15646 vr4130_avoid_branch_rt_conflict (rtx insn
)
15650 first
= SEQ_BEGIN (insn
);
15651 second
= SEQ_END (insn
);
15653 && NONJUMP_INSN_P (second
)
15654 && GET_CODE (PATTERN (first
)) == SET
15655 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
15656 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
15658 /* Check for the right kind of condition. */
15659 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
15660 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
15661 && REG_P (XEXP (cond
, 0))
15662 && REG_P (XEXP (cond
, 1))
15663 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
15664 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
15666 /* SECOND mentions the rt register but not the rs register. */
15667 rtx tmp
= XEXP (cond
, 0);
15668 XEXP (cond
, 0) = XEXP (cond
, 1);
15669 XEXP (cond
, 1) = tmp
;
15674 /* Implement -mvr4130-align. Go through each basic block and simulate the
15675 processor pipeline. If we find that a pair of instructions could execute
15676 in parallel, and the first of those instructions is not 8-byte aligned,
15677 insert a nop to make it aligned. */
15680 vr4130_align_insns (void)
15682 struct mips_sim state
;
15683 rtx insn
, subinsn
, last
, last2
, next
;
15688 /* LAST is the last instruction before INSN to have a nonzero length.
15689 LAST2 is the last such instruction before LAST. */
15693 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15696 mips_sim_init (&state
, alloca (state_size ()));
15697 for (insn
= get_insns (); insn
!= 0; insn
= next
)
15699 unsigned int length
;
15701 next
= NEXT_INSN (insn
);
15703 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15704 This isn't really related to the alignment pass, but we do it on
15705 the fly to avoid a separate instruction walk. */
15706 vr4130_avoid_branch_rt_conflict (insn
);
15708 length
= get_attr_length (insn
);
15709 if (length
> 0 && USEFUL_INSN_P (insn
))
15710 FOR_EACH_SUBINSN (subinsn
, insn
)
15712 mips_sim_wait_insn (&state
, subinsn
);
15714 /* If we want this instruction to issue in parallel with the
15715 previous one, make sure that the previous instruction is
15716 aligned. There are several reasons why this isn't worthwhile
15717 when the second instruction is a call:
15719 - Calls are less likely to be performance critical,
15720 - There's a good chance that the delay slot can execute
15721 in parallel with the call.
15722 - The return address would then be unaligned.
15724 In general, if we're going to insert a nop between instructions
15725 X and Y, it's better to insert it immediately after X. That
15726 way, if the nop makes Y aligned, it will also align any labels
15727 between X and Y. */
15728 if (state
.insns_left
!= state
.issue_rate
15729 && !CALL_P (subinsn
))
15731 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
15733 /* SUBINSN is the first instruction in INSN and INSN is
15734 aligned. We want to align the previous instruction
15735 instead, so insert a nop between LAST2 and LAST.
15737 Note that LAST could be either a single instruction
15738 or a branch with a delay slot. In the latter case,
15739 LAST, like INSN, is already aligned, but the delay
15740 slot must have some extra delay that stops it from
15741 issuing at the same time as the branch. We therefore
15742 insert a nop before the branch in order to align its
15744 gcc_assert (last2
);
15745 emit_insn_after (gen_nop (), last2
);
15748 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
15750 /* SUBINSN is the delay slot of INSN, but INSN is
15751 currently unaligned. Insert a nop between
15752 LAST and INSN to align it. */
15754 emit_insn_after (gen_nop (), last
);
15758 mips_sim_issue_insn (&state
, subinsn
);
15760 mips_sim_finish_insn (&state
, insn
);
15762 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15763 length
= get_attr_length (insn
);
15766 /* If the instruction is an asm statement or multi-instruction
15767 mips.md patern, the length is only an estimate. Insert an
15768 8 byte alignment after it so that the following instructions
15769 can be handled correctly. */
15770 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
15771 && (recog_memoized (insn
) < 0 || length
>= 8))
15773 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
15774 next
= NEXT_INSN (next
);
15775 mips_sim_next_cycle (&state
);
15778 else if (length
& 4)
15779 aligned_p
= !aligned_p
;
15784 /* See whether INSN is an aligned label. */
15785 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
15791 /* This structure records that the current function has a LO_SUM
15792 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15793 the largest offset applied to BASE by all such LO_SUMs. */
15794 struct mips_lo_sum_offset
{
15796 HOST_WIDE_INT offset
;
15799 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15802 mips_hash_base (rtx base
)
15804 int do_not_record_p
;
15806 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
15809 /* Hashtable helpers. */
15811 struct mips_lo_sum_offset_hasher
: typed_free_remove
<mips_lo_sum_offset
>
15813 typedef mips_lo_sum_offset value_type
;
15814 typedef rtx_def compare_type
;
15815 static inline hashval_t
hash (const value_type
*);
15816 static inline bool equal (const value_type
*, const compare_type
*);
15819 /* Hash-table callbacks for mips_lo_sum_offsets. */
15822 mips_lo_sum_offset_hasher::hash (const value_type
*entry
)
15824 return mips_hash_base (entry
->base
);
15828 mips_lo_sum_offset_hasher::equal (const value_type
*entry
,
15829 const compare_type
*value
)
15831 return rtx_equal_p (entry
->base
, value
);
15834 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
15836 /* Look up symbolic constant X in HTAB, which is a hash table of
15837 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15838 paired with a recorded LO_SUM, otherwise record X in the table. */
15841 mips_lo_sum_offset_lookup (mips_offset_table htab
, rtx x
,
15842 enum insert_option option
)
15845 mips_lo_sum_offset
**slot
;
15846 struct mips_lo_sum_offset
*entry
;
15848 /* Split X into a base and offset. */
15849 split_const (x
, &base
, &offset
);
15850 if (UNSPEC_ADDRESS_P (base
))
15851 base
= UNSPEC_ADDRESS (base
);
15853 /* Look up the base in the hash table. */
15854 slot
= htab
.find_slot_with_hash (base
, mips_hash_base (base
), option
);
15858 entry
= (struct mips_lo_sum_offset
*) *slot
;
15859 if (option
== INSERT
)
15863 entry
= XNEW (struct mips_lo_sum_offset
);
15864 entry
->base
= base
;
15865 entry
->offset
= INTVAL (offset
);
15870 if (INTVAL (offset
) > entry
->offset
)
15871 entry
->offset
= INTVAL (offset
);
15874 return INTVAL (offset
) <= entry
->offset
;
15877 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15878 Record every LO_SUM in *LOC. */
15881 mips_record_lo_sum (rtx
*loc
, void *data
)
15883 if (GET_CODE (*loc
) == LO_SUM
)
15884 mips_lo_sum_offset_lookup (*(mips_offset_table
*) data
,
15885 XEXP (*loc
, 1), INSERT
);
15889 /* Return true if INSN is a SET of an orphaned high-part relocation.
15890 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15891 LO_SUMs in the current function. */
15894 mips_orphaned_high_part_p (mips_offset_table htab
, rtx insn
)
15896 enum mips_symbol_type type
;
15899 set
= single_set (insn
);
15902 /* Check for %his. */
15904 if (GET_CODE (x
) == HIGH
15905 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
15906 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
15908 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15909 if (GET_CODE (x
) == UNSPEC
15910 && XINT (x
, 1) == UNSPEC_LOAD_GOT
15911 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
15912 SYMBOL_CONTEXT_LEA
, &type
)
15913 && type
== SYMBOL_GOTOFF_PAGE
)
15914 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
15919 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15920 INSN and a previous instruction, avoid it by inserting nops after
15923 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15924 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15925 before using the value of that register. *HILO_DELAY counts the
15926 number of instructions since the last hilo hazard (that is,
15927 the number of instructions since the last MFLO or MFHI).
15929 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15930 for the next instruction.
15932 LO_REG is an rtx for the LO register, used in dependence checking. */
15935 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
15936 rtx
*delayed_reg
, rtx lo_reg
)
15941 pattern
= PATTERN (insn
);
15943 /* Do not put the whole function in .set noreorder if it contains
15944 an asm statement. We don't know whether there will be hazards
15945 between the asm statement and the gcc-generated code. */
15946 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
15947 cfun
->machine
->all_noreorder_p
= false;
15949 /* Ignore zero-length instructions (barriers and the like). */
15950 ninsns
= get_attr_length (insn
) / 4;
15954 /* Work out how many nops are needed. Note that we only care about
15955 registers that are explicitly mentioned in the instruction's pattern.
15956 It doesn't matter that calls use the argument registers or that they
15957 clobber hi and lo. */
15958 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
15959 nops
= 2 - *hilo_delay
;
15960 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
15965 /* Insert the nops between this instruction and the previous one.
15966 Each new nop takes us further from the last hilo hazard. */
15967 *hilo_delay
+= nops
;
15969 emit_insn_after (gen_hazard_nop (), after
);
15971 /* Set up the state for the next instruction. */
15972 *hilo_delay
+= ninsns
;
15974 if (INSN_CODE (insn
) >= 0)
15975 switch (get_attr_hazard (insn
))
15985 set
= single_set (insn
);
15987 *delayed_reg
= SET_DEST (set
);
15992 /* Go through the instruction stream and insert nops where necessary.
15993 Also delete any high-part relocations whose partnering low parts
15994 are now all dead. See if the whole function can then be put into
15995 .set noreorder and .set nomacro. */
15998 mips_reorg_process_insns (void)
16000 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
16002 mips_offset_table htab
;
16004 /* Force all instructions to be split into their final form. */
16005 split_all_insns_noflow ();
16007 /* Recalculate instruction lengths without taking nops into account. */
16008 cfun
->machine
->ignore_hazard_length_p
= true;
16009 shorten_branches (get_insns ());
16011 cfun
->machine
->all_noreorder_p
= true;
16013 /* We don't track MIPS16 PC-relative offsets closely enough to make
16014 a good job of "set .noreorder" code in MIPS16 mode. */
16016 cfun
->machine
->all_noreorder_p
= false;
16018 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16019 if (!TARGET_EXPLICIT_RELOCS
)
16020 cfun
->machine
->all_noreorder_p
= false;
16022 /* Profiled functions can't be all noreorder because the profiler
16023 support uses assembler macros. */
16025 cfun
->machine
->all_noreorder_p
= false;
16027 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
16028 because we rely on the assembler to work around some errata. */
16029 if (TARGET_FIX_VR4120
|| TARGET_FIX_24K
)
16030 cfun
->machine
->all_noreorder_p
= false;
16032 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16033 MFHI instructions. Note that we avoid using MFLO and MFHI if
16034 the VR4130 MACC and DMACC instructions are available instead;
16035 see the *mfhilo_{si,di}_macc patterns. */
16036 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
16037 cfun
->machine
->all_noreorder_p
= false;
16041 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16042 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16043 FOR_EACH_SUBINSN (subinsn
, insn
)
16044 if (USEFUL_INSN_P (subinsn
))
16045 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, &htab
);
16050 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
16052 /* Make a second pass over the instructions. Delete orphaned
16053 high-part relocations or turn them into NOPs. Avoid hazards
16054 by inserting NOPs. */
16055 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
16057 next_insn
= NEXT_INSN (insn
);
16058 if (USEFUL_INSN_P (insn
))
16060 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
16062 /* If we find an orphaned high-part relocation in a delay
16063 slot, it's easier to turn that instruction into a NOP than
16064 to delete it. The delay slot will be a NOP either way. */
16065 FOR_EACH_SUBINSN (subinsn
, insn
)
16066 if (INSN_P (subinsn
))
16068 if (mips_orphaned_high_part_p (htab
, subinsn
))
16070 PATTERN (subinsn
) = gen_nop ();
16071 INSN_CODE (subinsn
) = CODE_FOR_nop
;
16073 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
16074 &delayed_reg
, lo_reg
);
16080 /* INSN is a single instruction. Delete it if it's an
16081 orphaned high-part relocation. */
16082 if (mips_orphaned_high_part_p (htab
, insn
))
16083 delete_insn (insn
);
16084 /* Also delete cache barriers if the last instruction
16085 was an annulled branch. INSN will not be speculatively
16087 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
16089 && JUMP_P (SEQ_BEGIN (last_insn
))
16090 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
16091 delete_insn (insn
);
16094 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
16095 &delayed_reg
, lo_reg
);
16105 /* Return true if the function has a long branch instruction. */
16108 mips_has_long_branch_p (void)
16113 /* We need up-to-date instruction lengths. */
16114 shorten_branches (get_insns ());
16116 /* Look for a branch that is longer than normal. The normal length for
16117 non-MIPS16 branches is 8, because the length includes the delay slot.
16118 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16119 but they have no delay slot. */
16120 normal_length
= (TARGET_MIPS16
? 4 : 8);
16121 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16122 FOR_EACH_SUBINSN (subinsn
, insn
)
16123 if (JUMP_P (subinsn
)
16124 && get_attr_length (subinsn
) > normal_length
16125 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
16131 /* If we are using a GOT, but have not decided to use a global pointer yet,
16132 see whether we need one to implement long branches. Convert the ghost
16133 global-pointer instructions into real ones if so. */
16136 mips_expand_ghost_gp_insns (void)
16138 /* Quick exit if we already know that we will or won't need a
16140 if (!TARGET_USE_GOT
16141 || cfun
->machine
->global_pointer
== INVALID_REGNUM
16142 || mips_must_initialize_gp_p ())
16145 /* Run a full check for long branches. */
16146 if (!mips_has_long_branch_p ())
16149 /* We've now established that we need $gp. */
16150 cfun
->machine
->must_initialize_gp_p
= true;
16151 split_all_insns_noflow ();
16156 /* Subroutine of mips_reorg to manage passes that require DF. */
16159 mips_df_reorg (void)
16161 /* Create def-use chains. */
16162 df_set_flags (DF_EQ_NOTES
);
16163 df_chain_add_problem (DF_UD_CHAIN
);
16166 if (TARGET_RELAX_PIC_CALLS
)
16167 mips_annotate_pic_calls ();
16169 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
16170 r10k_insert_cache_barriers ();
16172 df_finish_pass (false);
16175 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16176 called very late in mips_reorg, but the caller is required to run
16177 mips16_lay_out_constants on the result. */
16180 mips16_load_branch_target (rtx dest
, rtx src
)
16182 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
16186 if (mips_cfun_has_cprestore_slot_p ())
16187 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
16189 mips_emit_move (dest
, pic_offset_table_rtx
);
16190 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
16191 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
16192 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16193 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
16194 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16195 gen_rtx_LO_SUM (Pmode
, dest
, low
)));
16199 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
16200 mips_emit_move (dest
, src
);
16204 /* If we're compiling a MIPS16 function, look for and split any long branches.
16205 This must be called after all other instruction modifications in
16209 mips16_split_long_branches (void)
16211 bool something_changed
;
16213 if (!TARGET_MIPS16
)
16216 /* Loop until the alignments for all targets are sufficient. */
16221 shorten_branches (get_insns ());
16222 something_changed
= false;
16223 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16225 && get_attr_length (insn
) > 4
16226 && (any_condjump_p (insn
) || any_uncondjump_p (insn
)))
16228 rtx old_label
, new_label
, temp
, saved_temp
;
16229 rtx target
, jump
, jump_sequence
;
16233 /* Free up a MIPS16 register by saving it in $1. */
16234 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
16235 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
16236 emit_move_insn (saved_temp
, temp
);
16238 /* Load the branch target into TEMP. */
16239 old_label
= JUMP_LABEL (insn
);
16240 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
16241 mips16_load_branch_target (temp
, target
);
16243 /* Jump to the target and restore the register's
16245 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
16246 (temp
, temp
, saved_temp
)));
16247 JUMP_LABEL (jump
) = old_label
;
16248 LABEL_NUSES (old_label
)++;
16250 /* Rewrite any symbolic references that are supposed to use
16251 a PC-relative constant pool. */
16252 mips16_lay_out_constants (false);
16254 if (simplejump_p (insn
))
16255 /* We're going to replace INSN with a longer form. */
16256 new_label
= NULL_RTX
;
16259 /* Create a branch-around label for the original
16261 new_label
= gen_label_rtx ();
16262 emit_label (new_label
);
16265 jump_sequence
= get_insns ();
16268 emit_insn_after (jump_sequence
, insn
);
16270 invert_jump (insn
, new_label
, false);
16272 delete_insn (insn
);
16273 something_changed
= true;
16276 while (something_changed
);
16279 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16284 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16285 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16286 to date if the CFG is available. */
16287 if (mips_cfg_in_reorg ())
16288 compute_bb_for_insn ();
16289 mips16_lay_out_constants (true);
16290 if (mips_cfg_in_reorg ())
16293 free_bb_for_insn ();
16297 /* We use a machine specific pass to do a second machine dependent reorg
16298 pass after delay branch scheduling. */
16300 static unsigned int
16301 mips_machine_reorg2 (void)
16303 mips_reorg_process_insns ();
16305 && TARGET_EXPLICIT_RELOCS
16307 && TARGET_VR4130_ALIGN
)
16308 vr4130_align_insns ();
16309 if (mips_expand_ghost_gp_insns ())
16310 /* The expansion could invalidate some of the VR4130 alignment
16311 optimizations, but this should be an extremely rare case anyhow. */
16312 mips_reorg_process_insns ();
16313 mips16_split_long_branches ();
16317 struct rtl_opt_pass pass_mips_machine_reorg2
=
16321 "mach2", /* name */
16322 OPTGROUP_NONE
, /* optinfo_flags */
16324 mips_machine_reorg2
, /* execute */
16327 0, /* static_pass_number */
16328 TV_MACH_DEP
, /* tv_id */
16329 0, /* properties_required */
16330 0, /* properties_provided */
16331 0, /* properties_destroyed */
16332 0, /* todo_flags_start */
16333 TODO_verify_rtl_sharing
, /* todo_flags_finish */
16337 struct register_pass_info insert_pass_mips_machine_reorg2
=
16339 &pass_mips_machine_reorg2
.pass
, /* pass */
16340 "dbr", /* reference_pass_name */
16341 1, /* ref_pass_instance_number */
16342 PASS_POS_INSERT_AFTER
/* po_op */
16345 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16346 in order to avoid duplicating too much logic from elsewhere. */
16349 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
16350 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
16353 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
16354 bool use_sibcall_p
;
16356 /* Pretend to be a post-reload pass while generating rtl. */
16357 reload_completed
= 1;
16359 /* Mark the end of the (empty) prologue. */
16360 emit_note (NOTE_INSN_PROLOGUE_END
);
16362 /* Determine if we can use a sibcall to call FUNCTION directly. */
16363 fnaddr
= XEXP (DECL_RTL (function
), 0);
16364 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
16365 && const_call_insn_operand (fnaddr
, Pmode
));
16367 /* Determine if we need to load FNADDR from the GOT. */
16369 && (mips_got_symbol_type_p
16370 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
16372 /* Pick a global pointer. Use a call-clobbered register if
16373 TARGET_CALL_SAVED_GP. */
16374 cfun
->machine
->global_pointer
16375 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
16376 cfun
->machine
->must_initialize_gp_p
= true;
16377 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
16379 /* Set up the global pointer for n32 or n64 abicalls. */
16380 mips_emit_loadgp ();
16383 /* We need two temporary registers in some cases. */
16384 temp1
= gen_rtx_REG (Pmode
, 2);
16385 temp2
= gen_rtx_REG (Pmode
, 3);
16387 /* Find out which register contains the "this" pointer. */
16388 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
16389 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
16391 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
16393 /* Add DELTA to THIS_RTX. */
16396 rtx offset
= GEN_INT (delta
);
16397 if (!SMALL_OPERAND (delta
))
16399 mips_emit_move (temp1
, offset
);
16402 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
16405 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16406 if (vcall_offset
!= 0)
16410 /* Set TEMP1 to *THIS_RTX. */
16411 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
16413 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16414 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
16416 /* Load the offset and add it to THIS_RTX. */
16417 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
16418 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
16421 /* Jump to the target function. Use a sibcall if direct jumps are
16422 allowed, otherwise load the address into a register first. */
16425 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
16426 SIBLING_CALL_P (insn
) = 1;
16430 /* This is messy. GAS treats "la $25,foo" as part of a call
16431 sequence and may allow a global "foo" to be lazily bound.
16432 The general move patterns therefore reject this combination.
16434 In this context, lazy binding would actually be OK
16435 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16436 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16437 We must therefore load the address via a temporary
16438 register if mips_dangerous_for_la25_p.
16440 If we jump to the temporary register rather than $25,
16441 the assembler can use the move insn to fill the jump's
16444 We can use the same technique for MIPS16 code, where $25
16445 is not a valid JR register. */
16446 if (TARGET_USE_PIC_FN_ADDR_REG
16448 && !mips_dangerous_for_la25_p (fnaddr
))
16449 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
16450 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
16452 if (TARGET_USE_PIC_FN_ADDR_REG
16453 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
16454 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
16455 emit_jump_insn (gen_indirect_jump (temp1
));
16458 /* Run just enough of rest_of_compilation. This sequence was
16459 "borrowed" from alpha.c. */
16460 insn
= get_insns ();
16461 split_all_insns_noflow ();
16462 mips16_lay_out_constants (true);
16463 shorten_branches (insn
);
16464 final_start_function (insn
, file
, 1);
16465 final (insn
, file
, 1);
16466 final_end_function ();
16468 /* Clean up the vars set above. Note that final_end_function resets
16469 the global pointer for us. */
16470 reload_completed
= 0;
16474 /* The last argument passed to mips_set_compression_mode,
16475 or negative if the function hasn't been called yet. */
16476 static unsigned int old_compression_mode
= -1;
16478 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16479 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16482 mips_set_compression_mode (unsigned int compression_mode
)
16485 if (compression_mode
== old_compression_mode
)
16488 /* Restore base settings of various flags. */
16489 target_flags
= mips_base_target_flags
;
16490 flag_schedule_insns
= mips_base_schedule_insns
;
16491 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
16492 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
16493 align_loops
= mips_base_align_loops
;
16494 align_jumps
= mips_base_align_jumps
;
16495 align_functions
= mips_base_align_functions
;
16496 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
16497 target_flags
|= compression_mode
;
16499 if (compression_mode
& MASK_MIPS16
)
16501 /* Switch to MIPS16 mode. */
16502 target_flags
|= MASK_MIPS16
;
16504 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16505 target_flags
&= ~MASK_SYNCI
;
16507 /* Don't run the scheduler before reload, since it tends to
16508 increase register pressure. */
16509 flag_schedule_insns
= 0;
16511 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16512 the whole function to be in a single section. */
16513 flag_reorder_blocks_and_partition
= 0;
16515 /* Don't move loop invariants, because it tends to increase
16516 register pressure. It also introduces an extra move in cases
16517 where the constant is the first operand in a two-operand binary
16518 instruction, or when it forms a register argument to a functon
16520 flag_move_loop_invariants
= 0;
16522 target_flags
|= MASK_EXPLICIT_RELOCS
;
16524 /* Experiments suggest we get the best overall section-anchor
16525 results from using the range of an unextended LW or SW. Code
16526 that makes heavy use of byte or short accesses can do better
16527 with ranges of 0...31 and 0...63 respectively, but most code is
16528 sensitive to the range of LW and SW instead. */
16529 targetm
.min_anchor_offset
= 0;
16530 targetm
.max_anchor_offset
= 127;
16532 targetm
.const_anchor
= 0;
16534 /* MIPS16 has no BAL instruction. */
16535 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
16537 /* The R4000 errata don't apply to any known MIPS16 cores.
16538 It's simpler to make the R4000 fixes and MIPS16 mode
16539 mutually exclusive. */
16540 target_flags
&= ~MASK_FIX_R4000
;
16542 if (flag_pic
&& !TARGET_OLDABI
)
16543 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16546 sorry ("MIPS16 -mxgot code");
16548 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
16549 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16553 /* Switch to microMIPS or the standard encoding. */
16555 if (TARGET_MICROMIPS
)
16556 /* Avoid branch likely. */
16557 target_flags
&= ~MASK_BRANCHLIKELY
;
16559 /* Provide default values for align_* for 64-bit targets. */
16562 if (align_loops
== 0)
16564 if (align_jumps
== 0)
16566 if (align_functions
== 0)
16567 align_functions
= 8;
16570 targetm
.min_anchor_offset
= -32768;
16571 targetm
.max_anchor_offset
= 32767;
16573 targetm
.const_anchor
= 0x8000;
16576 /* (Re)initialize MIPS target internals for new ISA. */
16577 mips_init_relocs ();
16579 if (compression_mode
& MASK_MIPS16
)
16581 if (!mips16_globals
)
16582 mips16_globals
= save_target_globals_default_opts ();
16584 restore_target_globals (mips16_globals
);
16587 restore_target_globals (&default_target_globals
);
16589 old_compression_mode
= compression_mode
;
16592 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16593 function should use the MIPS16 or microMIPS ISA and switch modes
16597 mips_set_current_function (tree fndecl
)
16599 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
16602 /* Allocate a chunk of memory for per-function machine-dependent data. */
16604 static struct machine_function
*
16605 mips_init_machine_status (void)
16607 return ggc_alloc_cleared_machine_function ();
16610 /* Return the processor associated with the given ISA level, or null
16611 if the ISA isn't valid. */
16613 static const struct mips_cpu_info
*
16614 mips_cpu_info_from_isa (int isa
)
16618 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16619 if (mips_cpu_info_table
[i
].isa
== isa
)
16620 return mips_cpu_info_table
+ i
;
16625 /* Return a mips_cpu_info entry determined by an option valued
16628 static const struct mips_cpu_info
*
16629 mips_cpu_info_from_opt (int opt
)
16633 case MIPS_ARCH_OPTION_FROM_ABI
:
16634 /* 'from-abi' selects the most compatible architecture for the
16635 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16636 ABIs. For the EABIs, we have to decide whether we're using
16637 the 32-bit or 64-bit version. */
16638 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
16639 : ABI_NEEDS_64BIT_REGS
? 3
16640 : (TARGET_64BIT
? 3 : 1));
16642 case MIPS_ARCH_OPTION_NATIVE
:
16643 gcc_unreachable ();
16646 return &mips_cpu_info_table
[opt
];
16650 /* Return a default mips_cpu_info entry, given that no -march= option
16651 was explicitly specified. */
16653 static const struct mips_cpu_info
*
16654 mips_default_arch (void)
16656 #if defined (MIPS_CPU_STRING_DEFAULT)
16658 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16659 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
16660 return mips_cpu_info_table
+ i
;
16661 gcc_unreachable ();
16662 #elif defined (MIPS_ISA_DEFAULT)
16663 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
16665 /* 'from-abi' makes a good default: you get whatever the ABI
16667 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
16671 /* Set up globals to generate code for the ISA or processor
16672 described by INFO. */
16675 mips_set_architecture (const struct mips_cpu_info
*info
)
16679 mips_arch_info
= info
;
16680 mips_arch
= info
->cpu
;
16681 mips_isa
= info
->isa
;
16685 /* Likewise for tuning. */
16688 mips_set_tune (const struct mips_cpu_info
*info
)
16692 mips_tune_info
= info
;
16693 mips_tune
= info
->cpu
;
16697 /* Implement TARGET_OPTION_OVERRIDE. */
16700 mips_option_override (void)
16702 int i
, start
, regno
, mode
;
16704 if (global_options_set
.x_mips_isa_option
)
16705 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
16707 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16708 SUBTARGET_OVERRIDE_OPTIONS
;
16711 /* MIPS16 and microMIPS cannot coexist. */
16712 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
16713 error ("unsupported combination: %s", "-mips16 -mmicromips");
16715 /* Save the base compression state and process flags as though we
16716 were generating uncompressed code. */
16717 mips_base_compression_flags
= TARGET_COMPRESSION
;
16718 target_flags
&= ~TARGET_COMPRESSION
;
16720 /* -mno-float overrides -mhard-float and -msoft-float. */
16721 if (TARGET_NO_FLOAT
)
16723 target_flags
|= MASK_SOFT_FLOAT_ABI
;
16724 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
16727 if (TARGET_FLIP_MIPS16
)
16728 TARGET_INTERLINK_COMPRESSED
= 1;
16730 /* Set the small data limit. */
16731 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
16733 : MIPS_DEFAULT_GVALUE
);
16735 /* The following code determines the architecture and register size.
16736 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16737 The GAS and GCC code should be kept in sync as much as possible. */
16739 if (global_options_set
.x_mips_arch_option
)
16740 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
16742 if (mips_isa_option_info
!= 0)
16744 if (mips_arch_info
== 0)
16745 mips_set_architecture (mips_isa_option_info
);
16746 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
16747 error ("%<-%s%> conflicts with the other architecture options, "
16748 "which specify a %s processor",
16749 mips_isa_option_info
->name
,
16750 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
16753 if (mips_arch_info
== 0)
16754 mips_set_architecture (mips_default_arch ());
16756 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
16757 error ("%<-march=%s%> is not compatible with the selected ABI",
16758 mips_arch_info
->name
);
16760 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16761 if (global_options_set
.x_mips_tune_option
)
16762 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
16764 if (mips_tune_info
== 0)
16765 mips_set_tune (mips_arch_info
);
16767 if ((target_flags_explicit
& MASK_64BIT
) != 0)
16769 /* The user specified the size of the integer registers. Make sure
16770 it agrees with the ABI and ISA. */
16771 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
16772 error ("%<-mgp64%> used with a 32-bit processor");
16773 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
16774 error ("%<-mgp32%> used with a 64-bit ABI");
16775 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
16776 error ("%<-mgp64%> used with a 32-bit ABI");
16780 /* Infer the integer register size from the ABI and processor.
16781 Restrict ourselves to 32-bit registers if that's all the
16782 processor has, or if the ABI cannot handle 64-bit registers. */
16783 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
16784 target_flags
&= ~MASK_64BIT
;
16786 target_flags
|= MASK_64BIT
;
16789 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
16791 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
16792 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16793 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
16794 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16795 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
16797 if (!ISA_HAS_MXHC1
)
16798 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16799 " the target supports the mfhc1 and mthc1 instructions");
16800 else if (mips_abi
!= ABI_32
)
16801 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16807 /* -msingle-float selects 32-bit float registers. Otherwise the
16808 float registers should be the same size as the integer ones. */
16809 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
16810 target_flags
|= MASK_FLOAT64
;
16812 target_flags
&= ~MASK_FLOAT64
;
16815 /* End of code shared with GAS. */
16817 /* If a -mlong* option was given, check that it matches the ABI,
16818 otherwise infer the -mlong* setting from the other options. */
16819 if ((target_flags_explicit
& MASK_LONG64
) != 0)
16823 if (mips_abi
== ABI_N32
)
16824 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16825 else if (mips_abi
== ABI_32
)
16826 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16827 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
16828 /* We have traditionally allowed non-abicalls code to use
16829 an LP64 form of o64. However, it would take a bit more
16830 effort to support the combination of 32-bit GOT entries
16831 and 64-bit pointers, so we treat the abicalls case as
16833 error ("the combination of %qs and %qs is incompatible with %qs",
16834 "-mabi=o64", "-mabicalls", "-mlong64");
16838 if (mips_abi
== ABI_64
)
16839 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16844 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
16845 target_flags
|= MASK_LONG64
;
16847 target_flags
&= ~MASK_LONG64
;
16850 if (!TARGET_OLDABI
)
16851 flag_pcc_struct_return
= 0;
16853 /* Decide which rtx_costs structure to use. */
16855 mips_cost
= &mips_rtx_cost_optimize_size
;
16857 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
16859 /* If the user hasn't specified a branch cost, use the processor's
16861 if (mips_branch_cost
== 0)
16862 mips_branch_cost
= mips_cost
->branch_cost
;
16864 /* If neither -mbranch-likely nor -mno-branch-likely was given
16865 on the command line, set MASK_BRANCHLIKELY based on the target
16866 architecture and tuning flags. Annulled delay slots are a
16867 size win, so we only consider the processor-specific tuning
16868 for !optimize_size. */
16869 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
16871 if (ISA_HAS_BRANCHLIKELY
16873 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
16874 target_flags
|= MASK_BRANCHLIKELY
;
16876 target_flags
&= ~MASK_BRANCHLIKELY
;
16878 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
16879 warning (0, "the %qs architecture does not support branch-likely"
16880 " instructions", mips_arch_info
->name
);
16882 /* If the user hasn't specified -mimadd or -mno-imadd set
16883 MASK_IMADD based on the target architecture and tuning
16885 if ((target_flags_explicit
& MASK_IMADD
) == 0)
16887 if (ISA_HAS_MADD_MSUB
&&
16888 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
16889 target_flags
|= MASK_IMADD
;
16891 target_flags
&= ~MASK_IMADD
;
16893 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
16894 warning (0, "the %qs architecture does not support madd or msub"
16895 " instructions", mips_arch_info
->name
);
16897 /* The effect of -mabicalls isn't defined for the EABI. */
16898 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
16900 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16901 target_flags
&= ~MASK_ABICALLS
;
16904 /* PIC requires -mabicalls. */
16907 if (mips_abi
== ABI_EABI
)
16908 error ("cannot generate position-independent code for %qs",
16910 else if (!TARGET_ABICALLS
)
16911 error ("position-independent code requires %qs", "-mabicalls");
16914 if (TARGET_ABICALLS_PIC2
)
16915 /* We need to set flag_pic for executables as well as DSOs
16916 because we may reference symbols that are not defined in
16917 the final executable. (MIPS does not use things like
16918 copy relocs, for example.)
16920 There is a body of code that uses __PIC__ to distinguish
16921 between -mabicalls and -mno-abicalls code. The non-__PIC__
16922 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16923 long as any indirect jumps use $25. */
16926 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16927 faster code, but at the expense of more nops. Enable it at -O3 and
16929 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
16930 target_flags
|= MASK_VR4130_ALIGN
;
16932 /* Prefer a call to memcpy over inline code when optimizing for size,
16933 though see MOVE_RATIO in mips.h. */
16934 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
16935 target_flags
|= MASK_MEMCPY
;
16937 /* If we have a nonzero small-data limit, check that the -mgpopt
16938 setting is consistent with the other target flags. */
16939 if (mips_small_data_threshold
> 0)
16943 if (!TARGET_EXPLICIT_RELOCS
)
16944 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
16946 TARGET_LOCAL_SDATA
= false;
16947 TARGET_EXTERN_SDATA
= false;
16951 if (TARGET_VXWORKS_RTP
)
16952 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
16954 if (TARGET_ABICALLS
)
16955 warning (0, "cannot use small-data accesses for %qs",
16960 /* Make sure that the user didn't turn off paired single support when
16961 MIPS-3D support is requested. */
16963 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
16964 && !TARGET_PAIRED_SINGLE_FLOAT
)
16965 error ("%<-mips3d%> requires %<-mpaired-single%>");
16967 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
16969 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
16971 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
16972 and TARGET_HARD_FLOAT_ABI are both true. */
16973 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
16974 error ("%qs must be used with %qs",
16975 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
16976 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
16978 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
16980 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
16981 warning (0, "the %qs architecture does not support paired-single"
16982 " instructions", mips_arch_info
->name
);
16984 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
16985 && !TARGET_CACHE_BUILTIN
)
16987 error ("%qs requires a target that provides the %qs instruction",
16988 "-mr10k-cache-barrier", "cache");
16989 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
16992 /* If TARGET_DSPR2, enable MASK_DSP. */
16994 target_flags
|= MASK_DSP
;
16996 /* .eh_frame addresses should be the same width as a C pointer.
16997 Most MIPS ABIs support only one pointer size, so the assembler
16998 will usually know exactly how big an .eh_frame address is.
17000 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17001 originally defined to use 64-bit pointers (i.e. it is LP64), and
17002 this is still the default mode. However, we also support an n32-like
17003 ILP32 mode, which is selected by -mlong32. The problem is that the
17004 assembler has traditionally not had an -mlong option, so it has
17005 traditionally not known whether we're using the ILP32 or LP64 form.
17007 As it happens, gas versions up to and including 2.19 use _32-bit_
17008 addresses for EABI64 .cfi_* directives. This is wrong for the
17009 default LP64 mode, so we can't use the directives by default.
17010 Moreover, since gas's current behavior is at odds with gcc's
17011 default behavior, it seems unwise to rely on future versions
17012 of gas behaving the same way. We therefore avoid using .cfi
17013 directives for -mlong32 as well. */
17014 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
17015 flag_dwarf2_cfi_asm
= 0;
17017 /* .cfi_* directives generate a read-only section, so fall back on
17018 manual .eh_frame creation if we need the section to be writable. */
17019 if (TARGET_WRITABLE_EH_FRAME
)
17020 flag_dwarf2_cfi_asm
= 0;
17022 mips_init_print_operand_punct ();
17024 /* Set up array to map GCC register number to debug register number.
17025 Ignore the special purpose register numbers. */
17027 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17029 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
17030 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
17031 mips_dwarf_regno
[i
] = i
;
17033 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
17036 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
17037 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
17038 mips_dbx_regno
[i
] = i
+ start
;
17040 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
17041 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
17042 mips_dbx_regno
[i
] = i
+ start
;
17044 /* Accumulator debug registers use big-endian ordering. */
17045 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
17046 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
17047 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
17048 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
17049 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
17051 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
17052 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
17055 /* Set up mips_hard_regno_mode_ok. */
17056 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
17057 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
17058 mips_hard_regno_mode_ok
[mode
][regno
]
17059 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
17061 /* Function to allocate machine-dependent function status. */
17062 init_machine_status
= &mips_init_machine_status
;
17064 /* Default to working around R4000 errata only if the processor
17065 was selected explicitly. */
17066 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
17067 && strcmp (mips_arch_info
->name
, "r4000") == 0)
17068 target_flags
|= MASK_FIX_R4000
;
17070 /* Default to working around R4400 errata only if the processor
17071 was selected explicitly. */
17072 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
17073 && strcmp (mips_arch_info
->name
, "r4400") == 0)
17074 target_flags
|= MASK_FIX_R4400
;
17076 /* Default to working around R10000 errata only if the processor
17077 was selected explicitly. */
17078 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
17079 && strcmp (mips_arch_info
->name
, "r10000") == 0)
17080 target_flags
|= MASK_FIX_R10000
;
17082 /* Make sure that branch-likely instructions available when using
17083 -mfix-r10000. The instructions are not available if either:
17085 1. -mno-branch-likely was passed.
17086 2. The selected ISA does not support branch-likely and
17087 the command line does not include -mbranch-likely. */
17088 if (TARGET_FIX_R10000
17089 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
17090 ? !ISA_HAS_BRANCHLIKELY
17091 : !TARGET_BRANCHLIKELY
))
17092 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17094 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
17096 warning (0, "the %qs architecture does not support the synci "
17097 "instruction", mips_arch_info
->name
);
17098 target_flags
&= ~MASK_SYNCI
;
17101 /* Only optimize PIC indirect calls if they are actually required. */
17102 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
17103 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17105 /* Save base state of options. */
17106 mips_base_target_flags
= target_flags
;
17107 mips_base_schedule_insns
= flag_schedule_insns
;
17108 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
17109 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
17110 mips_base_align_loops
= align_loops
;
17111 mips_base_align_jumps
= align_jumps
;
17112 mips_base_align_functions
= align_functions
;
17114 /* Now select the ISA mode.
17116 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17117 later if required. */
17118 mips_set_compression_mode (0);
17120 /* We register a second machine specific reorg pass after delay slot
17121 filling. Registering the pass must be done at start up. It's
17122 convenient to do it here. */
17123 register_pass (&insert_pass_mips_machine_reorg2
);
17126 /* Swap the register information for registers I and I + 1, which
17127 currently have the wrong endianness. Note that the registers'
17128 fixedness and call-clobberedness might have been set on the
17132 mips_swap_registers (unsigned int i
)
17137 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17138 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17140 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
17141 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
17142 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
17143 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
17149 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17152 mips_conditional_register_usage (void)
17157 /* These DSP control register fields are global. */
17158 global_regs
[CCDSP_PO_REGNUM
] = 1;
17159 global_regs
[CCDSP_SC_REGNUM
] = 1;
17162 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17163 reg_class_contents
[(int) DSP_ACC_REGS
]);
17165 if (!TARGET_HARD_FLOAT
)
17167 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17168 reg_class_contents
[(int) FP_REGS
]);
17169 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17170 reg_class_contents
[(int) ST_REGS
]);
17172 else if (!ISA_HAS_8CC
)
17174 /* We only have a single condition-code register. We implement
17175 this by fixing all the condition-code registers and generating
17176 RTL that refers directly to ST_REG_FIRST. */
17177 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17178 reg_class_contents
[(int) ST_REGS
]);
17179 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
17180 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
17184 /* In MIPS16 mode, we permit the $t temporary registers to be used
17185 for reload. We prohibit the unused $s registers, since they
17186 are call-saved, and saving them via a MIPS16 register would
17187 probably waste more time than just reloading the value. */
17188 fixed_regs
[18] = call_used_regs
[18] = 1;
17189 fixed_regs
[19] = call_used_regs
[19] = 1;
17190 fixed_regs
[20] = call_used_regs
[20] = 1;
17191 fixed_regs
[21] = call_used_regs
[21] = 1;
17192 fixed_regs
[22] = call_used_regs
[22] = 1;
17193 fixed_regs
[23] = call_used_regs
[23] = 1;
17194 fixed_regs
[26] = call_used_regs
[26] = 1;
17195 fixed_regs
[27] = call_used_regs
[27] = 1;
17196 fixed_regs
[30] = call_used_regs
[30] = 1;
17198 /* Do not allow HI and LO to be treated as register operands.
17199 There are no MTHI or MTLO instructions (or any real need
17200 for them) and one-way registers cannot easily be reloaded. */
17201 AND_COMPL_HARD_REG_SET (operand_reg_set
,
17202 reg_class_contents
[(int) MD_REGS
]);
17204 /* $f20-$f23 are call-clobbered for n64. */
17205 if (mips_abi
== ABI_64
)
17208 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
17209 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17211 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17213 if (mips_abi
== ABI_N32
)
17216 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
17217 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17219 /* Make sure that double-register accumulator values are correctly
17220 ordered for the current endianness. */
17221 if (TARGET_LITTLE_ENDIAN
)
17223 unsigned int regno
;
17225 mips_swap_registers (MD_REG_FIRST
);
17226 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
17227 mips_swap_registers (regno
);
17231 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
17232 other registers for instructions for which it is possible. This
17233 encourages the compiler to use CMP in cases where an XOR would
17234 require some register shuffling. */
17237 mips_order_regs_for_local_alloc (void)
17241 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17242 reg_alloc_order
[i
] = i
;
17246 /* It really doesn't matter where we put register 0, since it is
17247 a fixed register anyhow. */
17248 reg_alloc_order
[0] = 24;
17249 reg_alloc_order
[24] = 0;
17253 /* Implement EH_USES. */
17256 mips_eh_uses (unsigned int regno
)
17258 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
17260 /* We need to force certain registers to be live in order to handle
17261 PIC long branches correctly. See mips_must_initialize_gp_p for
17263 if (mips_cfun_has_cprestore_slot_p ())
17265 if (regno
== CPRESTORE_SLOT_REGNUM
)
17270 if (cfun
->machine
->global_pointer
== regno
)
17278 /* Implement EPILOGUE_USES. */
17281 mips_epilogue_uses (unsigned int regno
)
17283 /* Say that the epilogue uses the return address register. Note that
17284 in the case of sibcalls, the values "used by the epilogue" are
17285 considered live at the start of the called function. */
17286 if (regno
== RETURN_ADDR_REGNUM
)
17289 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17290 See the comment above load_call<mode> for details. */
17291 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
17294 /* An interrupt handler must preserve some registers that are
17295 ordinarily call-clobbered. */
17296 if (cfun
->machine
->interrupt_handler_p
17297 && mips_interrupt_extra_call_saved_reg_p (regno
))
17303 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17306 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
17308 return REG_P (*x
) && REGNO (*x
) == AT_REGNUM
;
17311 /* Return true if INSN needs to be wrapped in ".set noat".
17312 INSN has NOPERANDS operands, stored in OPVEC. */
17315 mips_need_noat_wrapper_p (rtx insn
, rtx
*opvec
, int noperands
)
17319 if (recog_memoized (insn
) >= 0)
17320 for (i
= 0; i
< noperands
; i
++)
17321 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
17326 /* Implement FINAL_PRESCAN_INSN. */
17329 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
17331 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17332 mips_push_asm_switch (&mips_noat
);
17335 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17338 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx insn
,
17339 rtx
*opvec
, int noperands
)
17341 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17342 mips_pop_asm_switch (&mips_noat
);
17345 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17346 EXT_CODE is the code of the extension used. Return NULL if widening
17347 multiplication shouldn't be used. */
17350 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
17354 signed_p
= ext_code
== SIGN_EXTEND
;
17357 /* Don't use widening multiplication with MULT when we have DMUL. Even
17358 with the extension of its input operands DMUL is faster. Note that
17359 the extension is not needed for signed multiplication. In order to
17360 ensure that we always remove the redundant sign-extension in this
17361 case we still expand mulsidi3 for DMUL. */
17363 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
17366 ? gen_mulsidi3_64bit_mips16
17367 : gen_umulsidi3_64bit_mips16
);
17368 if (TARGET_FIX_R4000
)
17370 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
17376 ? gen_mulsidi3_32bit_mips16
17377 : gen_umulsidi3_32bit_mips16
);
17378 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
17379 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
17380 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
17384 /* Return true if PATTERN matches the kind of instruction generated by
17385 umips_build_save_restore. SAVE_P is true for store. */
17388 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
17392 HOST_WIDE_INT first_offset
= 0;
17393 rtx first_base
= 0;
17394 unsigned int regmask
= 0;
17396 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
17398 rtx set
, reg
, mem
, this_base
;
17399 HOST_WIDE_INT this_offset
;
17401 /* Check that we have a SET. */
17402 set
= XVECEXP (pattern
, 0, n
);
17403 if (GET_CODE (set
) != SET
)
17406 /* Check that the SET is a load (if restoring) or a store
17408 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17409 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
17412 /* Check that the address is the sum of base and a possibly-zero
17413 constant offset. Determine if the offset is in range. */
17414 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
17415 if (!REG_P (this_base
))
17420 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
17422 first_base
= this_base
;
17423 first_offset
= this_offset
;
17427 /* Check that the save slots are consecutive. */
17428 if (REGNO (this_base
) != REGNO (first_base
)
17429 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
17433 /* Check that SET's other operand is a register. */
17434 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
17438 regmask
|= 1 << REGNO (reg
);
17441 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
17442 if (regmask
== umips_swm_mask
[i
])
17448 /* Return the assembly instruction for microMIPS LWM or SWM.
17449 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17452 umips_output_save_restore (bool save_p
, rtx pattern
)
17454 static char buffer
[300];
17457 HOST_WIDE_INT offset
;
17458 rtx base
, mem
, set
, last_set
, last_reg
;
17460 /* Parse the pattern. */
17461 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
17463 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
17465 n
= XVECLEN (pattern
, 0);
17467 set
= XVECEXP (pattern
, 0, 0);
17468 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17469 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
17471 last_set
= XVECEXP (pattern
, 0, n
- 1);
17472 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
17474 if (REGNO (last_reg
) == 31)
17477 gcc_assert (n
<= 9);
17481 s
+= sprintf (s
, "%s,", reg_names
[16]);
17483 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
17485 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
17488 if (REGNO (last_reg
) == 31)
17489 s
+= sprintf (s
, "%s,", reg_names
[31]);
17491 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
17495 /* Return true if MEM1 and MEM2 use the same base register, and the
17496 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17497 register into (from) which the contents of MEM1 will be loaded
17498 (stored), depending on the value of LOAD_P.
17499 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17502 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
17503 rtx first_reg
, rtx mem1
, rtx mem2
)
17506 HOST_WIDE_INT offset1
, offset2
;
17508 if (!MEM_P (mem1
) || !MEM_P (mem2
))
17511 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
17512 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
17514 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
17517 /* Avoid invalid load pair instructions. */
17518 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
17521 /* We must avoid this case for anti-dependence.
17524 first_reg is $2, but the base is $3. */
17527 && REGNO (first_reg
) + 1 == REGNO (base1
))
17530 if (offset2
!= offset1
+ 4)
17533 if (!UMIPS_12BIT_OFFSET_P (offset1
))
17539 /* OPERANDS describes the operands to a pair of SETs, in the order
17540 dest1, src1, dest2, src2. Return true if the operands can be used
17541 in an LWP or SWP instruction; LOAD_P says which. */
17544 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
17546 rtx reg1
, reg2
, mem1
, mem2
;
17550 reg1
= operands
[0];
17551 reg2
= operands
[2];
17552 mem1
= operands
[1];
17553 mem2
= operands
[3];
17557 reg1
= operands
[1];
17558 reg2
= operands
[3];
17559 mem1
= operands
[0];
17560 mem2
= operands
[2];
17563 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17564 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
17566 if (REGNO (reg1
) == REGNO (reg2
) + 1)
17567 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
17572 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17573 the first register is REG and the first memory slot is MEM.
17574 LOAD_P is true for LWP. */
17577 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
17579 rtx ops
[] = {reg
, mem
};
17582 output_asm_insn ("lwp\t%0,%1", ops
);
17584 output_asm_insn ("swp\t%0,%1", ops
);
17587 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17588 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17591 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
17593 rtx reg1
, reg2
, mem1
, mem2
;
17596 reg1
= operands
[0];
17597 reg2
= operands
[2];
17598 mem1
= operands
[1];
17599 mem2
= operands
[3];
17603 reg1
= operands
[1];
17604 reg2
= operands
[3];
17605 mem1
= operands
[0];
17606 mem2
= operands
[2];
17609 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17611 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
17615 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
17616 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
17619 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17622 umips_movep_target_p (rtx reg1
, rtx reg2
)
17624 int regno1
, regno2
, pair
;
17626 static const int match
[8] = {
17627 0x00000060, /* 5, 6 */
17628 0x000000a0, /* 5, 7 */
17629 0x000000c0, /* 6, 7 */
17630 0x00200010, /* 4, 21 */
17631 0x00400010, /* 4, 22 */
17632 0x00000030, /* 4, 5 */
17633 0x00000050, /* 4, 6 */
17634 0x00000090 /* 4, 7 */
17637 if (!REG_P (reg1
) || !REG_P (reg2
))
17640 regno1
= REGNO (reg1
);
17641 regno2
= REGNO (reg2
);
17643 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
17646 pair
= (1 << regno1
) | (1 << regno2
);
17648 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
17649 if (pair
== match
[i
])
17655 /* Return the size in bytes of the trampoline code, padded to
17656 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17657 function address immediately follow. */
17660 mips_trampoline_code_size (void)
17662 if (TARGET_USE_PIC_FN_ADDR_REG
)
17664 else if (ptr_mode
== DImode
)
17666 else if (ISA_HAS_LOAD_DELAY
)
17672 /* Implement TARGET_TRAMPOLINE_INIT. */
17675 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
17677 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
17680 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
17682 /* Work out the offsets of the pointers from the start of the
17683 trampoline code. */
17684 end_addr_offset
= mips_trampoline_code_size ();
17685 static_chain_offset
= end_addr_offset
;
17686 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
17688 /* Get pointers to the beginning and end of the code block. */
17689 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
17690 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
17692 #define OP(X) gen_int_mode (X, SImode)
17694 /* Build up the code in TRAMPOLINE. */
17696 if (TARGET_USE_PIC_FN_ADDR_REG
)
17698 /* $25 contains the address of the trampoline. Emit code of the form:
17700 l[wd] $1, target_function_offset($25)
17701 l[wd] $static_chain, static_chain_offset($25)
17704 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
17705 target_function_offset
,
17706 PIC_FUNCTION_ADDR_REGNUM
));
17707 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17708 static_chain_offset
,
17709 PIC_FUNCTION_ADDR_REGNUM
));
17710 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
17711 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
17713 else if (ptr_mode
== DImode
)
17715 /* It's too cumbersome to create the full 64-bit address, so let's
17721 1: l[wd] $25, target_function_offset - 12($31)
17722 l[wd] $static_chain, static_chain_offset - 12($31)
17726 where 12 is the offset of "1:" from the start of the code block. */
17727 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
17728 trampoline
[i
++] = OP (MIPS_BAL (1));
17729 trampoline
[i
++] = OP (MIPS_NOP
);
17730 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
17731 target_function_offset
- 12,
17732 RETURN_ADDR_REGNUM
));
17733 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17734 static_chain_offset
- 12,
17735 RETURN_ADDR_REGNUM
));
17736 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17737 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
17741 /* If the target has load delays, emit:
17743 lui $1, %hi(end_addr)
17744 lw $25, %lo(end_addr + ...)($1)
17745 lw $static_chain, %lo(end_addr + ...)($1)
17751 lui $1, %hi(end_addr)
17752 lw $25, %lo(end_addr + ...)($1)
17754 lw $static_chain, %lo(end_addr + ...)($1). */
17756 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
17757 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
17758 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
17759 NULL
, false, OPTAB_WIDEN
);
17760 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
17761 NULL
, false, OPTAB_WIDEN
);
17762 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
17764 /* Emit the LUI. */
17765 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
17766 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
17767 NULL
, false, OPTAB_WIDEN
);
17769 /* Emit the load of the target function. */
17770 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
17771 target_function_offset
- end_addr_offset
,
17773 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
17774 NULL
, false, OPTAB_WIDEN
);
17776 /* Emit the JR here, if we can. */
17777 if (!ISA_HAS_LOAD_DELAY
)
17778 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17780 /* Emit the load of the static chain register. */
17781 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17782 static_chain_offset
- end_addr_offset
,
17784 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
17785 NULL
, false, OPTAB_WIDEN
);
17787 /* Emit the JR, if we couldn't above. */
17788 if (ISA_HAS_LOAD_DELAY
)
17790 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17791 trampoline
[i
++] = OP (MIPS_NOP
);
17797 /* Copy the trampoline code. Leave any padding uninitialized. */
17798 for (j
= 0; j
< i
; j
++)
17800 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
17801 mips_emit_move (mem
, trampoline
[j
]);
17804 /* Set up the static chain pointer field. */
17805 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
17806 mips_emit_move (mem
, chain_value
);
17808 /* Set up the target function field. */
17809 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
17810 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
17812 /* Flush the code part of the trampoline. */
17813 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
17814 emit_insn (gen_clear_cache (addr
, end_addr
));
17817 /* Implement FUNCTION_PROFILER. */
17819 void mips_function_profiler (FILE *file
)
17822 sorry ("mips16 function profiling");
17823 if (TARGET_LONG_CALLS
)
17825 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
17826 if (Pmode
== DImode
)
17827 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
17829 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
17831 mips_push_asm_switch (&mips_noat
);
17832 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
17833 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
17834 /* _mcount treats $2 as the static chain register. */
17835 if (cfun
->static_chain_decl
!= NULL
)
17836 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
17837 reg_names
[STATIC_CHAIN_REGNUM
]);
17838 if (TARGET_MCOUNT_RA_ADDRESS
)
17840 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
17841 ra save location. */
17842 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
17843 /* ra not saved, pass zero. */
17844 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
17846 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
17847 Pmode
== DImode
? "dla" : "la", reg_names
[12],
17848 cfun
->machine
->frame
.ra_fp_offset
,
17849 reg_names
[STACK_POINTER_REGNUM
]);
17851 if (!TARGET_NEWABI
)
17853 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
17854 TARGET_64BIT
? "dsubu" : "subu",
17855 reg_names
[STACK_POINTER_REGNUM
],
17856 reg_names
[STACK_POINTER_REGNUM
],
17857 Pmode
== DImode
? 16 : 8);
17859 if (TARGET_LONG_CALLS
)
17860 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
17862 fprintf (file
, "\tjal\t_mcount\n");
17863 mips_pop_asm_switch (&mips_noat
);
17864 /* _mcount treats $2 as the static chain register. */
17865 if (cfun
->static_chain_decl
!= NULL
)
17866 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
17870 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
17871 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
17872 when TARGET_LOONGSON_VECTORS is true. */
17874 static unsigned HOST_WIDE_INT
17875 mips_shift_truncation_mask (enum machine_mode mode
)
17877 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
17880 return GET_MODE_BITSIZE (mode
) - 1;
17883 /* Implement TARGET_PREPARE_PCH_SAVE. */
17886 mips_prepare_pch_save (void)
17888 /* We are called in a context where the current MIPS16 vs. non-MIPS16
17889 setting should be irrelevant. The question then is: which setting
17890 makes most sense at load time?
17892 The PCH is loaded before the first token is read. We should never
17893 have switched into MIPS16 mode by that point, and thus should not
17894 have populated mips16_globals. Nor can we load the entire contents
17895 of mips16_globals from the PCH file, because mips16_globals contains
17896 a combination of GGC and non-GGC data.
17898 There is therefore no point in trying save the GGC part of
17899 mips16_globals to the PCH file, or to preserve MIPS16ness across
17900 the PCH save and load. The loading compiler would not have access
17901 to the non-GGC parts of mips16_globals (either from the PCH file,
17902 or from a copy that the loading compiler generated itself) and would
17903 have to call target_reinit anyway.
17905 It therefore seems best to switch back to non-MIPS16 mode at
17906 save time, and to ensure that mips16_globals remains null after
17908 mips_set_compression_mode (0);
17909 mips16_globals
= 0;
17912 /* Generate or test for an insn that supports a constant permutation. */
17914 #define MAX_VECT_LEN 8
17916 struct expand_vec_perm_d
17918 rtx target
, op0
, op1
;
17919 unsigned char perm
[MAX_VECT_LEN
];
17920 enum machine_mode vmode
;
17921 unsigned char nelt
;
17926 /* Construct (set target (vec_select op0 (parallel perm))) and
17927 return true if that's a valid instruction in the active ISA. */
17930 mips_expand_vselect (rtx target
, rtx op0
,
17931 const unsigned char *perm
, unsigned nelt
)
17933 rtx rperm
[MAX_VECT_LEN
], x
;
17936 for (i
= 0; i
< nelt
; ++i
)
17937 rperm
[i
] = GEN_INT (perm
[i
]);
17939 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
17940 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
17941 x
= gen_rtx_SET (VOIDmode
, target
, x
);
17944 if (recog_memoized (x
) < 0)
17952 /* Similar, but generate a vec_concat from op0 and op1 as well. */
17955 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
17956 const unsigned char *perm
, unsigned nelt
)
17958 enum machine_mode v2mode
;
17961 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
17962 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
17963 return mips_expand_vselect (target
, x
, perm
, nelt
);
17966 /* Recognize patterns for even-odd extraction. */
17969 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
17971 unsigned i
, odd
, nelt
= d
->nelt
;
17972 rtx t0
, t1
, t2
, t3
;
17974 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
17976 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
17983 for (i
= 1; i
< nelt
; ++i
)
17984 if (d
->perm
[i
] != i
* 2 + odd
)
17990 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
17991 t0
= gen_reg_rtx (d
->vmode
);
17992 t1
= gen_reg_rtx (d
->vmode
);
17996 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
17997 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
17999 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
18001 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
18005 t2
= gen_reg_rtx (d
->vmode
);
18006 t3
= gen_reg_rtx (d
->vmode
);
18007 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
18008 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
18009 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
18010 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
18012 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
18014 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
18018 gcc_unreachable ();
18023 /* Recognize patterns for the Loongson PSHUFH instruction. */
18026 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
18031 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18033 if (d
->vmode
!= V4HImode
)
18038 /* Convert the selector into the packed 8-bit form for pshufh. */
18039 /* Recall that loongson is little-endian only. No big-endian
18040 adjustment required. */
18041 for (i
= mask
= 0; i
< 4; i
++)
18042 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
18043 rmask
= force_reg (SImode
, GEN_INT (mask
));
18045 if (d
->one_vector_p
)
18046 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
18049 rtx t0
, t1
, x
, merge
, rmerge
[4];
18051 t0
= gen_reg_rtx (V4HImode
);
18052 t1
= gen_reg_rtx (V4HImode
);
18053 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
18054 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
18056 for (i
= 0; i
< 4; ++i
)
18057 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
18058 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
18059 merge
= force_reg (V4HImode
, merge
);
18061 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
18062 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18064 x
= gen_rtx_NOT (V4HImode
, merge
);
18065 x
= gen_rtx_AND (V4HImode
, x
, t0
);
18066 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18068 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
18069 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
18075 /* Recognize broadcast patterns for the Loongson. */
18078 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
18083 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18085 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18086 if (d
->vmode
!= V8QImode
)
18088 if (!d
->one_vector_p
)
18092 for (i
= 1; i
< 8; ++i
)
18093 if (d
->perm
[i
] != elt
)
18099 /* With one interleave we put two of the desired element adjacent. */
18100 t0
= gen_reg_rtx (V8QImode
);
18102 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
18104 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
18106 /* Shuffle that one HImode element into all locations. */
18109 t1
= gen_reg_rtx (V4HImode
);
18110 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
18111 force_reg (SImode
, GEN_INT (elt
))));
18113 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
18118 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
18120 unsigned int i
, nelt
= d
->nelt
;
18121 unsigned char perm2
[MAX_VECT_LEN
];
18123 if (d
->one_vector_p
)
18125 /* Try interleave with alternating operands. */
18126 memcpy (perm2
, d
->perm
, sizeof(perm2
));
18127 for (i
= 1; i
< nelt
; i
+= 2)
18129 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
18134 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
18138 /* Try again with swapped operands. */
18139 for (i
= 0; i
< nelt
; ++i
)
18140 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
18141 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
18145 if (mips_expand_vpc_loongson_even_odd (d
))
18147 if (mips_expand_vpc_loongson_pshufh (d
))
18149 if (mips_expand_vpc_loongson_bcast (d
))
18154 /* Expand a vec_perm_const pattern. */
18157 mips_expand_vec_perm_const (rtx operands
[4])
18159 struct expand_vec_perm_d d
;
18160 int i
, nelt
, which
;
18161 unsigned char orig_perm
[MAX_VECT_LEN
];
18165 d
.target
= operands
[0];
18166 d
.op0
= operands
[1];
18167 d
.op1
= operands
[2];
18170 d
.vmode
= GET_MODE (d
.target
);
18171 gcc_assert (VECTOR_MODE_P (d
.vmode
));
18172 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18173 d
.testing_p
= false;
18175 for (i
= which
= 0; i
< nelt
; ++i
)
18177 rtx e
= XVECEXP (sel
, 0, i
);
18178 int ei
= INTVAL (e
) & (2 * nelt
- 1);
18179 which
|= (ei
< nelt
? 1 : 2);
18182 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18190 d
.one_vector_p
= false;
18191 if (!rtx_equal_p (d
.op0
, d
.op1
))
18196 for (i
= 0; i
< nelt
; ++i
)
18197 d
.perm
[i
] &= nelt
- 1;
18199 d
.one_vector_p
= true;
18204 d
.one_vector_p
= true;
18208 ok
= mips_expand_vec_perm_const_1 (&d
);
18210 /* If we were given a two-vector permutation which just happened to
18211 have both input vectors equal, we folded this into a one-vector
18212 permutation. There are several loongson patterns that are matched
18213 via direct vec_select+vec_concat expansion, but we do not have
18214 support in mips_expand_vec_perm_const_1 to guess the adjustment
18215 that should be made for a single operand. Just try again with
18216 the original permutation. */
18217 if (!ok
&& which
== 3)
18219 d
.op0
= operands
[1];
18220 d
.op1
= operands
[2];
18221 d
.one_vector_p
= false;
18222 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18223 ok
= mips_expand_vec_perm_const_1 (&d
);
18229 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18232 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
18233 const unsigned char *sel
)
18235 struct expand_vec_perm_d d
;
18236 unsigned int i
, nelt
, which
;
18240 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18241 d
.testing_p
= true;
18242 memcpy (d
.perm
, sel
, nelt
);
18244 /* Categorize the set of elements in the selector. */
18245 for (i
= which
= 0; i
< nelt
; ++i
)
18247 unsigned char e
= d
.perm
[i
];
18248 gcc_assert (e
< 2 * nelt
);
18249 which
|= (e
< nelt
? 1 : 2);
18252 /* For all elements from second vector, fold the elements to first. */
18254 for (i
= 0; i
< nelt
; ++i
)
18257 /* Check whether the mask can be applied to the vector type. */
18258 d
.one_vector_p
= (which
!= 3);
18260 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
18261 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
18262 if (!d
.one_vector_p
)
18263 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
18266 ret
= mips_expand_vec_perm_const_1 (&d
);
18272 /* Expand an integral vector unpack operation. */
18275 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
18277 enum machine_mode imode
= GET_MODE (operands
[1]);
18278 rtx (*unpack
) (rtx
, rtx
, rtx
);
18279 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
18280 rtx tmp
, dest
, zero
;
18286 unpack
= gen_loongson_punpckhbh
;
18288 unpack
= gen_loongson_punpcklbh
;
18289 cmpgt
= gen_loongson_pcmpgtb
;
18293 unpack
= gen_loongson_punpckhhw
;
18295 unpack
= gen_loongson_punpcklhw
;
18296 cmpgt
= gen_loongson_pcmpgth
;
18299 gcc_unreachable ();
18302 zero
= force_reg (imode
, CONST0_RTX (imode
));
18307 tmp
= gen_reg_rtx (imode
);
18308 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
18311 dest
= gen_reg_rtx (imode
);
18312 emit_insn (unpack (dest
, operands
[1], tmp
));
18314 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
18317 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18320 mips_constant_elt_p (rtx x
)
18322 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
18325 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18328 mips_expand_vi_broadcast (enum machine_mode vmode
, rtx target
, rtx elt
)
18330 struct expand_vec_perm_d d
;
18334 if (elt
!= const0_rtx
)
18335 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
18337 elt
= gen_lowpart (DImode
, elt
);
18339 t1
= gen_reg_rtx (vmode
);
18343 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
18346 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
18349 gcc_unreachable ();
18352 memset (&d
, 0, sizeof (d
));
18357 d
.nelt
= GET_MODE_NUNITS (vmode
);
18358 d
.one_vector_p
= true;
18360 ok
= mips_expand_vec_perm_const_1 (&d
);
18364 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18365 elements of VALS with zeros, copy the constant vector to TARGET. */
18368 mips_expand_vi_constant (enum machine_mode vmode
, unsigned nelt
,
18369 rtx target
, rtx vals
)
18371 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
18374 for (i
= 0; i
< nelt
; ++i
)
18376 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
18377 RTVEC_ELT (vec
, i
) = const0_rtx
;
18380 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
18384 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18387 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
18389 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
18391 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
18392 GEN_INT (one_var
)));
18395 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18398 mips_expand_vi_general (enum machine_mode vmode
, enum machine_mode imode
,
18399 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
18401 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
18402 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
18405 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
18407 for (i
= 0; i
< nelt
; ++i
)
18409 rtx x
= XVECEXP (vals
, 0, i
);
18410 if (!mips_constant_elt_p (x
))
18411 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
18414 emit_move_insn (target
, mem
);
18417 /* Expand a vector initialization. */
18420 mips_expand_vector_init (rtx target
, rtx vals
)
18422 enum machine_mode vmode
= GET_MODE (target
);
18423 enum machine_mode imode
= GET_MODE_INNER (vmode
);
18424 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
18425 unsigned nvar
= 0, one_var
= -1u;
18426 bool all_same
= true;
18429 for (i
= 0; i
< nelt
; ++i
)
18431 x
= XVECEXP (vals
, 0, i
);
18432 if (!mips_constant_elt_p (x
))
18433 nvar
++, one_var
= i
;
18434 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
18438 /* Load constants from the pool, or whatever's handy. */
18441 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
18445 /* For two-part initialization, always use CONCAT. */
18448 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
18449 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
18450 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
18451 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18455 /* Loongson is the only cpu with vectors with more elements. */
18456 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
18458 /* If all values are identical, broadcast the value. */
18461 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
18465 /* If we've only got one non-variable V4HImode, use PINSRH. */
18466 if (nvar
== 1 && vmode
== V4HImode
)
18468 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
18472 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
18475 /* Expand a vector reduction. */
18478 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
18480 enum machine_mode vmode
= GET_MODE (in
);
18481 unsigned char perm2
[2];
18482 rtx last
, next
, fold
, x
;
18486 fold
= gen_reg_rtx (vmode
);
18490 /* Use PUL/PLU to produce { L, H } op { H, L }.
18491 By reversing the pair order, rather than a pure interleave high,
18492 we avoid erroneous exceptional conditions that we might otherwise
18493 produce from the computation of H op H. */
18496 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
18501 /* Use interleave to produce { H, L } op { H, H }. */
18502 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
18506 /* Perform the first reduction with interleave,
18507 and subsequent reductions with shifts. */
18508 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
18510 next
= gen_reg_rtx (vmode
);
18511 emit_insn (gen (next
, last
, fold
));
18514 fold
= gen_reg_rtx (vmode
);
18515 x
= force_reg (SImode
, GEN_INT (16));
18516 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
18520 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
18522 next
= gen_reg_rtx (vmode
);
18523 emit_insn (gen (next
, last
, fold
));
18526 fold
= gen_reg_rtx (vmode
);
18527 x
= force_reg (SImode
, GEN_INT (16));
18528 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18530 next
= gen_reg_rtx (vmode
);
18531 emit_insn (gen (next
, last
, fold
));
18534 fold
= gen_reg_rtx (vmode
);
18535 x
= force_reg (SImode
, GEN_INT (8));
18536 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18540 gcc_unreachable ();
18543 emit_insn (gen (target
, last
, fold
));
18546 /* Expand a vector minimum/maximum. */
18549 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
18550 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
18552 enum machine_mode vmode
= GET_MODE (target
);
18555 tc
= gen_reg_rtx (vmode
);
18556 t0
= gen_reg_rtx (vmode
);
18557 t1
= gen_reg_rtx (vmode
);
18560 emit_insn (cmp (tc
, op0
, op1
));
18562 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
18563 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18565 x
= gen_rtx_NOT (vmode
, tc
);
18566 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
18567 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18569 x
= gen_rtx_IOR (vmode
, t0
, t1
);
18570 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18573 /* Initialize the GCC target structure. */
18574 #undef TARGET_ASM_ALIGNED_HI_OP
18575 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18576 #undef TARGET_ASM_ALIGNED_SI_OP
18577 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18578 #undef TARGET_ASM_ALIGNED_DI_OP
18579 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18581 #undef TARGET_OPTION_OVERRIDE
18582 #define TARGET_OPTION_OVERRIDE mips_option_override
18584 #undef TARGET_LEGITIMIZE_ADDRESS
18585 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18587 #undef TARGET_ASM_FUNCTION_PROLOGUE
18588 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18589 #undef TARGET_ASM_FUNCTION_EPILOGUE
18590 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18591 #undef TARGET_ASM_SELECT_RTX_SECTION
18592 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18593 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18594 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18596 #undef TARGET_SCHED_INIT
18597 #define TARGET_SCHED_INIT mips_sched_init
18598 #undef TARGET_SCHED_REORDER
18599 #define TARGET_SCHED_REORDER mips_sched_reorder
18600 #undef TARGET_SCHED_REORDER2
18601 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18602 #undef TARGET_SCHED_VARIABLE_ISSUE
18603 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18604 #undef TARGET_SCHED_ADJUST_COST
18605 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18606 #undef TARGET_SCHED_ISSUE_RATE
18607 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18608 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18609 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18610 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18611 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18612 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18613 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18614 mips_multipass_dfa_lookahead
18615 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18616 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18617 mips_small_register_classes_for_mode_p
18619 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18620 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18622 #undef TARGET_INSERT_ATTRIBUTES
18623 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18624 #undef TARGET_MERGE_DECL_ATTRIBUTES
18625 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18626 #undef TARGET_CAN_INLINE_P
18627 #define TARGET_CAN_INLINE_P mips_can_inline_p
18628 #undef TARGET_SET_CURRENT_FUNCTION
18629 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18631 #undef TARGET_VALID_POINTER_MODE
18632 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18633 #undef TARGET_REGISTER_MOVE_COST
18634 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18635 #undef TARGET_MEMORY_MOVE_COST
18636 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18637 #undef TARGET_RTX_COSTS
18638 #define TARGET_RTX_COSTS mips_rtx_costs
18639 #undef TARGET_ADDRESS_COST
18640 #define TARGET_ADDRESS_COST mips_address_cost
18642 #undef TARGET_IN_SMALL_DATA_P
18643 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18645 #undef TARGET_MACHINE_DEPENDENT_REORG
18646 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18648 #undef TARGET_PREFERRED_RELOAD_CLASS
18649 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18651 #undef TARGET_EXPAND_TO_RTL_HOOK
18652 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18653 #undef TARGET_ASM_FILE_START
18654 #define TARGET_ASM_FILE_START mips_file_start
18655 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18656 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18657 #undef TARGET_ASM_CODE_END
18658 #define TARGET_ASM_CODE_END mips_code_end
18660 #undef TARGET_INIT_LIBFUNCS
18661 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18663 #undef TARGET_BUILD_BUILTIN_VA_LIST
18664 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18665 #undef TARGET_EXPAND_BUILTIN_VA_START
18666 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18667 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18668 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18670 #undef TARGET_PROMOTE_FUNCTION_MODE
18671 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
18672 #undef TARGET_PROMOTE_PROTOTYPES
18673 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18675 #undef TARGET_FUNCTION_VALUE
18676 #define TARGET_FUNCTION_VALUE mips_function_value
18677 #undef TARGET_LIBCALL_VALUE
18678 #define TARGET_LIBCALL_VALUE mips_libcall_value
18679 #undef TARGET_FUNCTION_VALUE_REGNO_P
18680 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
18681 #undef TARGET_RETURN_IN_MEMORY
18682 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
18683 #undef TARGET_RETURN_IN_MSB
18684 #define TARGET_RETURN_IN_MSB mips_return_in_msb
18686 #undef TARGET_ASM_OUTPUT_MI_THUNK
18687 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
18688 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
18689 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
18691 #undef TARGET_PRINT_OPERAND
18692 #define TARGET_PRINT_OPERAND mips_print_operand
18693 #undef TARGET_PRINT_OPERAND_ADDRESS
18694 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
18695 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
18696 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
18698 #undef TARGET_SETUP_INCOMING_VARARGS
18699 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
18700 #undef TARGET_STRICT_ARGUMENT_NAMING
18701 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
18702 #undef TARGET_MUST_PASS_IN_STACK
18703 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
18704 #undef TARGET_PASS_BY_REFERENCE
18705 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
18706 #undef TARGET_CALLEE_COPIES
18707 #define TARGET_CALLEE_COPIES mips_callee_copies
18708 #undef TARGET_ARG_PARTIAL_BYTES
18709 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
18710 #undef TARGET_FUNCTION_ARG
18711 #define TARGET_FUNCTION_ARG mips_function_arg
18712 #undef TARGET_FUNCTION_ARG_ADVANCE
18713 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
18714 #undef TARGET_FUNCTION_ARG_BOUNDARY
18715 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
18717 #undef TARGET_MODE_REP_EXTENDED
18718 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
18720 #undef TARGET_VECTOR_MODE_SUPPORTED_P
18721 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
18723 #undef TARGET_SCALAR_MODE_SUPPORTED_P
18724 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
18726 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
18727 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
18729 #undef TARGET_INIT_BUILTINS
18730 #define TARGET_INIT_BUILTINS mips_init_builtins
18731 #undef TARGET_BUILTIN_DECL
18732 #define TARGET_BUILTIN_DECL mips_builtin_decl
18733 #undef TARGET_EXPAND_BUILTIN
18734 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
18736 #undef TARGET_HAVE_TLS
18737 #define TARGET_HAVE_TLS HAVE_AS_TLS
18739 #undef TARGET_CANNOT_FORCE_CONST_MEM
18740 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
18742 #undef TARGET_LEGITIMATE_CONSTANT_P
18743 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
18745 #undef TARGET_ENCODE_SECTION_INFO
18746 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
18748 #undef TARGET_ATTRIBUTE_TABLE
18749 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
18750 /* All our function attributes are related to how out-of-line copies should
18751 be compiled or called. They don't in themselves prevent inlining. */
18752 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
18753 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
18755 #undef TARGET_EXTRA_LIVE_ON_ENTRY
18756 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
18758 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
18759 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
18760 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
18761 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
18763 #undef TARGET_COMP_TYPE_ATTRIBUTES
18764 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
18766 #ifdef HAVE_AS_DTPRELWORD
18767 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
18768 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
18770 #undef TARGET_DWARF_REGISTER_SPAN
18771 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
18773 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
18774 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
18776 #undef TARGET_LEGITIMATE_ADDRESS_P
18777 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
18779 #undef TARGET_FRAME_POINTER_REQUIRED
18780 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
18782 #undef TARGET_CAN_ELIMINATE
18783 #define TARGET_CAN_ELIMINATE mips_can_eliminate
18785 #undef TARGET_CONDITIONAL_REGISTER_USAGE
18786 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
18788 #undef TARGET_TRAMPOLINE_INIT
18789 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
18791 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
18792 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
18794 #undef TARGET_SHIFT_TRUNCATION_MASK
18795 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
18797 #undef TARGET_PREPARE_PCH_SAVE
18798 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
18800 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
18801 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
18803 struct gcc_target targetm
= TARGET_INITIALIZER
;
18805 #include "gt-mips.h"