1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-95, 1996 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-flags.h"
37 #include "insn-attr.h"
38 #include "insn-codes.h"
42 #undef MAX /* sys/param.h may also define these */
47 #include <sys/types.h>
60 #if defined(USG) || defined(NO_STAB_H)
61 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
63 #include <stab.h> /* On BSD, use the system's stab.h. */
67 #define STAB_CODE_TYPE enum __stab_debug_code
69 #define STAB_CODE_TYPE int
74 extern char *getenv ();
75 extern char *mktemp ();
77 extern rtx
adj_offsettable_operand ();
78 extern rtx
copy_to_reg ();
81 extern tree
lookup_name ();
82 extern void pfatal_with_name ();
83 extern void warning ();
85 extern FILE *asm_out_file
;
87 /* Enumeration for all of the relational tests, so that we can build
88 arrays indexed by the test type, and not worry about the order
105 /* Global variables for machine-dependent things. */
107 /* Threshold for data being put into the small data/bss area, instead
108 of the normal data area (references to the small data/bss area take
109 1 instruction, and use the global pointer, references to the normal
110 data area takes 2 instructions). */
111 int mips_section_threshold
= -1;
113 /* Count the number of .file directives, so that .loc is up to date. */
114 int num_source_filenames
= 0;
116 /* Count the number of sdb related labels are generated (to find block
117 start and end boundaries). */
118 int sdb_label_count
= 0;
120 /* Next label # for each statement for Silicon Graphics IRIS systems. */
123 /* Non-zero if inside of a function, because the stupid MIPS asm can't
124 handle .files inside of functions. */
125 int inside_function
= 0;
127 /* Files to separate the text and the data output, so that all of the data
128 can be emitted before the text, which will mean that the assembler will
129 generate smaller code, based on the global pointer. */
130 FILE *asm_out_data_file
;
131 FILE *asm_out_text_file
;
133 /* Linked list of all externals that are to be emitted when optimizing
134 for the global pointer if they haven't been declared by the end of
135 the program with an appropriate .comm or initialization. */
138 struct extern_list
*next
; /* next external */
139 char *name
; /* name of the external */
140 int size
; /* size in bytes */
143 /* Name of the file containing the current function. */
144 char *current_function_file
= "";
146 /* Warning given that Mips ECOFF can't support changing files
147 within a function. */
148 int file_in_function_warning
= FALSE
;
150 /* Whether to suppress issuing .loc's because the user attempted
151 to change the filename within a function. */
152 int ignore_line_number
= FALSE
;
154 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
160 /* The next branch instruction is a branch likely, not branch normal. */
161 int mips_branch_likely
;
163 /* Count of delay slots and how many are filled. */
164 int dslots_load_total
;
165 int dslots_load_filled
;
166 int dslots_jump_total
;
167 int dslots_jump_filled
;
169 /* # of nops needed by previous insn */
170 int dslots_number_nops
;
172 /* Number of 1/2/3 word references to data items (ie, not jal's). */
175 /* registers to check for load delay */
176 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
178 /* Cached operands, and operator to compare for use in set/branch on
182 /* what type of branch to use */
183 enum cmp_type branch_type
;
185 /* Number of previously seen half-pic pointers and references. */
186 static int prev_half_pic_ptrs
= 0;
187 static int prev_half_pic_refs
= 0;
189 /* which cpu are we scheduling for */
190 enum processor_type mips_cpu
;
192 /* which instruction set architecture to use. */
195 #ifdef MIPS_ABI_DEFAULT
196 /* which ABI to use. This is defined to a constant in mips.h if the target
197 doesn't support multiple ABIs. */
198 enum mips_abi_type mips_abi
;
201 /* Strings to hold which cpu and instruction set architecture to use. */
202 char *mips_cpu_string
; /* for -mcpu=<xxx> */
203 char *mips_isa_string
; /* for -mips{1,2,3,4} */
204 char *mips_abi_string
; /* for -mabi={o32,32,n32,n64,64} */
206 /* If TRUE, we split addresses into their high and low parts in the RTL. */
207 int mips_split_addresses
;
209 /* Generating calls to position independent functions? */
210 enum mips_abicalls_type mips_abicalls
;
212 /* High and low marks for floating point values which we will accept
213 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
214 initialized in override_options. */
215 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
217 /* Array giving truth value on whether or not a given hard register
218 can support a given mode. */
219 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
221 /* Current frame information calculated by compute_frame_size. */
222 struct mips_frame_info current_frame_info
;
224 /* Zero structure to initialize current_frame_info. */
225 struct mips_frame_info zero_frame_info
;
227 /* Temporary filename used to buffer .text until end of program
229 static char *temp_filename
;
231 /* Pseudo-reg holding the address of the current function when
232 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
233 by mips_finalize_pic if it was created. */
234 rtx embedded_pic_fnaddr_rtx
;
236 /* List of all MIPS punctuation characters used by print_operand. */
237 char mips_print_operand_punct
[256];
239 /* Map GCC register number to debugger register number. */
240 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
242 /* Buffer to use to enclose a load/store operation with %{ %} to
243 turn on .set volatile. */
244 static char volatile_buffer
[60];
246 /* Hardware names for the registers. If -mrnames is used, this
247 will be overwritten with mips_sw_reg_names. */
249 char mips_reg_names
[][8] =
251 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
252 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
253 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
254 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
255 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
256 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
257 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
258 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
259 "hi", "lo", "accum","$fcr31","$rap"
262 /* Mips software names for the registers, used to overwrite the
263 mips_reg_names array. */
265 char mips_sw_reg_names
[][8] =
267 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
268 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
269 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
270 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
271 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
272 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
273 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
274 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
275 "hi", "lo", "accum","$fcr31","$rap"
278 /* Map hard register number to register class */
279 enum reg_class mips_regno_to_class
[] =
281 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
282 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
283 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
284 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
285 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
286 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
287 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
288 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
289 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
290 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
291 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
292 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
293 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
294 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
295 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
296 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
297 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
301 /* Map register constraint character to register class. */
302 enum reg_class mips_char_to_class
[256] =
304 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
305 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
306 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
307 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
308 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
309 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
310 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
311 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
312 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
313 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
314 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
315 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
316 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
317 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
318 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
319 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
320 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
321 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
322 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
323 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
324 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
325 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
326 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
327 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
328 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
329 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
330 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
331 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
332 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
333 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
334 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
335 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
336 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
337 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
338 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
339 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
340 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
341 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
342 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
343 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
344 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
345 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
346 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
347 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
348 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
349 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
350 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
351 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
352 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
353 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
354 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
355 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
356 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
357 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
358 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
359 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
360 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
361 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
362 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
363 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
364 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
365 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
366 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
367 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
371 /* Return truth value of whether OP can be used as an operands
372 where a register or 16 bit unsigned integer is needed. */
375 uns_arith_operand (op
, mode
)
377 enum machine_mode mode
;
379 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
382 return register_operand (op
, mode
);
385 /* Return truth value of whether OP can be used as an operands
386 where a 16 bit integer is needed */
389 arith_operand (op
, mode
)
391 enum machine_mode mode
;
393 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
396 return register_operand (op
, mode
);
399 /* Return truth value of whether OP can be used as an operand in a two
400 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
403 arith32_operand (op
, mode
)
405 enum machine_mode mode
;
407 if (GET_CODE (op
) == CONST_INT
)
410 return register_operand (op
, mode
);
413 /* Return truth value of whether OP is a integer which fits in 16 bits */
418 enum machine_mode mode
;
420 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
423 /* Return truth value of whether OP is a 32 bit integer which is too big to
424 be loaded with one instruction. */
429 enum machine_mode mode
;
433 if (GET_CODE (op
) != CONST_INT
)
437 if ((value
& ~0x0000ffff) == 0) /* ior reg,$r0,value */
440 if (((unsigned long)(value
+ 32768)) <= 32767) /* subu reg,$r0,value */
443 if ((value
& 0x0000ffff) == 0) /* lui reg,value>>16 */
449 /* Return truth value of whether OP is a register or the constant 0. */
452 reg_or_0_operand (op
, mode
)
454 enum machine_mode mode
;
456 switch (GET_CODE (op
))
462 return (INTVAL (op
) == 0);
465 if (op
!= CONST0_RTX (mode
))
472 return register_operand (op
, mode
);
478 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
481 mips_const_double_ok (op
, mode
)
483 enum machine_mode mode
;
487 if (GET_CODE (op
) != CONST_DOUBLE
)
490 if (mode
== VOIDmode
)
493 if (mode
!= SFmode
&& mode
!= DFmode
)
496 if (op
== CONST0_RTX (mode
))
499 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
500 if (mips_abi
!= ABI_32
)
503 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
505 if (REAL_VALUE_ISNAN (d
))
508 if (REAL_VALUE_NEGATIVE (d
))
509 d
= REAL_VALUE_NEGATE (d
);
513 if (REAL_VALUES_LESS (d
, dfhigh
)
514 && REAL_VALUES_LESS (dflow
, d
))
519 if (REAL_VALUES_LESS (d
, sfhigh
)
520 && REAL_VALUES_LESS (sflow
, d
))
527 /* Return truth value if a memory operand fits in a single instruction
528 (ie, register + small offset). */
531 simple_memory_operand (op
, mode
)
533 enum machine_mode mode
;
535 rtx addr
, plus0
, plus1
;
537 /* Eliminate non-memory operations */
538 if (GET_CODE (op
) != MEM
)
541 /* dword operations really put out 2 instructions, so eliminate them. */
542 /* ??? This isn't strictly correct. It is OK to accept multiword modes
543 here, since the length attributes are being set correctly, but only
544 if the address is offsettable. LO_SUM is not offsettable. */
545 if (GET_MODE_SIZE (GET_MODE (op
)) > UNITS_PER_WORD
)
548 /* Decode the address now. */
550 switch (GET_CODE (addr
))
560 return SMALL_INT (op
);
563 plus0
= XEXP (addr
, 0);
564 plus1
= XEXP (addr
, 1);
565 if (GET_CODE (plus0
) == REG
566 && GET_CODE (plus1
) == CONST_INT
567 && SMALL_INT (plus1
))
570 else if (GET_CODE (plus1
) == REG
571 && GET_CODE (plus0
) == CONST_INT
572 && SMALL_INT (plus0
))
579 /* We used to allow small symbol refs here (ie, stuff in .sdata
580 or .sbss), but this causes some bugs in G++. Also, it won't
581 interfere if the MIPS linker rewrites the store instruction
582 because the function is PIC. */
584 case LABEL_REF
: /* never gp relative */
588 /* If -G 0, we can never have a GP relative memory operation.
589 Also, save some time if not optimizing. */
594 rtx offset
= const0_rtx
;
595 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
596 if (GET_CODE (op
) != SYMBOL_REF
)
599 /* let's be paranoid.... */
600 if (! SMALL_INT (offset
))
606 return SYMBOL_REF_FLAG (addr
);
613 /* Return true if the code of this rtx pattern is EQ or NE. */
616 equality_op (op
, mode
)
618 enum machine_mode mode
;
620 if (mode
!= GET_MODE (op
))
623 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
626 /* Return true if the code is a relational operations (EQ, LE, etc.) */
631 enum machine_mode mode
;
633 if (mode
!= GET_MODE (op
))
636 return (GET_RTX_CLASS (GET_CODE (op
)) == '<');
639 /* Return true if the operand is either the PC or a label_ref. */
642 pc_or_label_operand (op
, mode
)
644 enum machine_mode mode
;
649 if (GET_CODE (op
) == LABEL_REF
)
655 /* Test for a valid operand for a call instruction.
656 Don't allow the arg pointer register or virtual regs
657 since they may change into reg + const, which the patterns
661 call_insn_operand (op
, mode
)
663 enum machine_mode mode
;
665 if (CONSTANT_ADDRESS_P (op
)
666 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
667 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
668 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)))
673 /* Return true if OPERAND is valid as a source operand for a move
677 move_operand (op
, mode
)
679 enum machine_mode mode
;
681 return (general_operand (op
, mode
)
682 && ! (mips_split_addresses
&& mips_check_split (op
, mode
)));
685 /* Return true if we split the address into high and low parts. */
687 /* ??? We should also handle reg+array somewhere. We get four
688 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
689 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
690 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
691 out of the address, then we have 4 instructions to combine. Perhaps
692 add a 3->2 define_split for combine. */
694 /* ??? We could also split a CONST_INT here if it is a large_int().
695 However, it doesn't seem to be very useful to have %hi(constant).
696 We would be better off by doing the masking ourselves and then putting
697 the explicit high part of the constant in the RTL. This will give better
698 optimization. Also, %hi(constant) needs assembler changes to work.
699 There is already a define_split that does this. */
702 mips_check_split (address
, mode
)
704 enum machine_mode mode
;
706 /* ??? This is the same check used in simple_memory_operand.
707 We use it here because LO_SUM is not offsettable. */
708 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
711 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
712 || (GET_CODE (address
) == CONST
713 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
714 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
715 || GET_CODE (address
) == LABEL_REF
)
721 /* Returns an operand string for the given instruction's delay slot,
722 after updating filled delay slot statistics.
724 We assume that operands[0] is the target register that is set.
726 In order to check the next insn, most of this functionality is moved
727 to FINAL_PRESCAN_INSN, and we just set the global variables that
730 /* ??? This function no longer does anything useful, because final_prescan_insn
731 now will never emit a nop. */
734 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
735 char *ret
; /* normal string to return */
736 enum delay_type type
; /* type of delay */
737 rtx operands
[]; /* operands to use */
738 rtx cur_insn
; /* current insn */
740 register rtx set_reg
;
741 register enum machine_mode mode
;
742 register rtx next_insn
= (cur_insn
) ? NEXT_INSN (cur_insn
) : (rtx
)0;
743 register int num_nops
;
745 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
748 else if (type
== DELAY_HILO
)
754 /* Make sure that we don't put nop's after labels. */
755 next_insn
= NEXT_INSN (cur_insn
);
756 while (next_insn
!= (rtx
)0 && GET_CODE (next_insn
) == NOTE
)
757 next_insn
= NEXT_INSN (next_insn
);
759 dslots_load_total
+= num_nops
;
760 if (TARGET_DEBUG_F_MODE
762 || type
== DELAY_NONE
763 || operands
== (rtx
*)0
764 || cur_insn
== (rtx
)0
765 || next_insn
== (rtx
)0
766 || GET_CODE (next_insn
) == CODE_LABEL
767 || (set_reg
= operands
[0]) == (rtx
)0)
769 dslots_number_nops
= 0;
770 mips_load_reg
= (rtx
)0;
771 mips_load_reg2
= (rtx
)0;
772 mips_load_reg3
= (rtx
)0;
773 mips_load_reg4
= (rtx
)0;
777 set_reg
= operands
[0];
778 if (set_reg
== (rtx
)0)
781 while (GET_CODE (set_reg
) == SUBREG
)
782 set_reg
= SUBREG_REG (set_reg
);
784 mode
= GET_MODE (set_reg
);
785 dslots_number_nops
= num_nops
;
786 mips_load_reg
= set_reg
;
787 if (GET_MODE_SIZE (mode
)
788 > (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
789 mips_load_reg2
= gen_rtx (REG
, SImode
, REGNO (set_reg
) + 1);
793 if (type
== DELAY_HILO
)
795 mips_load_reg3
= gen_rtx (REG
, SImode
, MD_REG_FIRST
);
796 mips_load_reg4
= gen_rtx (REG
, SImode
, MD_REG_FIRST
+1);
808 /* Determine whether a memory reference takes one (based off of the GP pointer),
809 two (normal), or three (label + reg) instructions, and bump the appropriate
810 counter for -mstats. */
813 mips_count_memory_refs (op
, num
)
819 rtx addr
, plus0
, plus1
;
820 enum rtx_code code0
, code1
;
823 if (TARGET_DEBUG_B_MODE
)
825 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
829 /* Skip MEM if passed, otherwise handle movsi of address. */
830 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
832 /* Loop, going through the address RTL */
836 switch (GET_CODE (addr
))
847 plus0
= XEXP (addr
, 0);
848 plus1
= XEXP (addr
, 1);
849 code0
= GET_CODE (plus0
);
850 code1
= GET_CODE (plus1
);
860 if (code0
== CONST_INT
)
875 if (code1
== CONST_INT
)
882 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
889 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
899 n_words
= 2; /* always 2 words */
903 addr
= XEXP (addr
, 0);
908 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
917 n_words
+= additional
;
921 num_refs
[n_words
-1] += num
;
925 /* Return RTL for the offset from the current function to the
929 embedded_pic_offset (x
)
932 if (embedded_pic_fnaddr_rtx
== NULL
)
936 embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
938 /* Output code at function start to initialize the pseudo-reg. */
939 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
940 inline functions, because it is called after RTL for the function
941 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
942 does not get copied, and ends up not matching the rest of the RTL.
943 This solution works, but means that we get unnecessary code to
944 initialize this value every time a function is inlined into another
947 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx
,
948 XEXP (DECL_RTL (current_function_decl
), 0)));
949 seq
= gen_sequence ();
951 push_topmost_sequence ();
952 emit_insn_after (seq
, get_insns ());
953 pop_topmost_sequence ();
956 return gen_rtx (CONST
, Pmode
,
957 gen_rtx (MINUS
, Pmode
, x
,
958 XEXP (DECL_RTL (current_function_decl
), 0)));
961 /* Return the appropriate instructions to move one operand to another. */
964 mips_move_1word (operands
, insn
, unsignedp
)
970 rtx op0
= operands
[0];
971 rtx op1
= operands
[1];
972 enum rtx_code code0
= GET_CODE (op0
);
973 enum rtx_code code1
= GET_CODE (op1
);
974 enum machine_mode mode
= GET_MODE (op0
);
975 int subreg_word0
= 0;
976 int subreg_word1
= 0;
977 enum delay_type delay
= DELAY_NONE
;
979 while (code0
== SUBREG
)
981 subreg_word0
+= SUBREG_WORD (op0
);
982 op0
= SUBREG_REG (op0
);
983 code0
= GET_CODE (op0
);
986 while (code1
== SUBREG
)
988 subreg_word1
+= SUBREG_WORD (op1
);
989 op1
= SUBREG_REG (op1
);
990 code1
= GET_CODE (op1
);
995 int regno0
= REGNO (op0
) + subreg_word0
;
999 int regno1
= REGNO (op1
) + subreg_word1
;
1001 /* Just in case, don't do anything for assigning a register
1002 to itself, unless we are filling a delay slot. */
1003 if (regno0
== regno1
&& set_nomacro
== 0)
1006 else if (GP_REG_P (regno0
))
1008 if (GP_REG_P (regno1
))
1009 ret
= "move\t%0,%1";
1011 else if (MD_REG_P (regno1
))
1014 if (regno1
!= HILO_REGNUM
)
1023 if (FP_REG_P (regno1
))
1024 ret
= "mfc1\t%0,%1";
1026 else if (regno1
== FPSW_REGNUM
)
1027 ret
= "cfc1\t%0,$31";
1031 else if (FP_REG_P (regno0
))
1033 if (GP_REG_P (regno1
))
1036 ret
= "mtc1\t%1,%0";
1039 if (FP_REG_P (regno1
))
1040 ret
= "mov.s\t%0,%1";
1043 else if (MD_REG_P (regno0
))
1045 if (GP_REG_P (regno1
))
1048 if (regno0
!= HILO_REGNUM
)
1053 else if (regno0
== FPSW_REGNUM
)
1055 if (GP_REG_P (regno1
))
1058 ret
= "ctc1\t%0,$31";
1063 else if (code1
== MEM
)
1068 mips_count_memory_refs (op1
, 1);
1070 if (GP_REG_P (regno0
))
1072 /* For loads, use the mode of the memory item, instead of the
1073 target, so zero/sign extend can use this code as well. */
1074 switch (GET_MODE (op1
))
1082 ret
= ((unsignedp
&& TARGET_64BIT
)
1087 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
1090 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
1095 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
1098 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1100 int i
= strlen (ret
);
1101 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1104 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1105 ret
= volatile_buffer
;
1109 else if (code1
== CONST_INT
1110 || (code1
== CONST_DOUBLE
1111 && GET_MODE (op1
) == VOIDmode
))
1113 if (code1
== CONST_DOUBLE
)
1115 /* This can happen when storing constants into long long
1116 bitfields. Just store the least significant word of
1118 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
1121 if (INTVAL (op1
) == 0)
1123 if (GP_REG_P (regno0
))
1124 ret
= "move\t%0,%z1";
1126 else if (FP_REG_P (regno0
))
1129 ret
= "mtc1\t%z1,%0";
1132 else if (MD_REG_P (regno0
))
1139 else if (GP_REG_P (regno0
))
1140 /* Don't use X format, because that will give out of range
1141 numbers for 64 bit host and 32 bit target. */
1142 ret
= "li\t%0,%1\t\t\t# %X1";
1145 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
1147 if (op1
== CONST0_RTX (SFmode
))
1149 if (GP_REG_P (regno0
))
1150 ret
= "move\t%0,%.";
1152 else if (FP_REG_P (regno0
))
1155 ret
= "mtc1\t%.,%0";
1162 ret
= "li.s\t%0,%1";
1166 else if (code1
== LABEL_REF
)
1169 mips_count_memory_refs (op1
, 1);
1174 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
1176 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
1178 rtx offset
= const0_rtx
;
1180 if (GET_CODE (op1
) == CONST
)
1181 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
1183 if (GET_CODE (op1
) == SYMBOL_REF
)
1185 operands
[2] = HALF_PIC_PTR (op1
);
1188 mips_count_memory_refs (operands
[2], 1);
1190 if (INTVAL (offset
) == 0)
1193 ret
= (unsignedp
&& TARGET_64BIT
1199 dslots_load_total
++;
1200 operands
[3] = offset
;
1201 if (unsignedp
&& TARGET_64BIT
)
1202 ret
= (SMALL_INT (offset
))
1203 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1204 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1206 ret
= (SMALL_INT (offset
))
1207 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1208 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1215 mips_count_memory_refs (op1
, 1);
1221 else if (code1
== PLUS
)
1223 rtx add_op0
= XEXP (op1
, 0);
1224 rtx add_op1
= XEXP (op1
, 1);
1226 if (GET_CODE (XEXP (op1
, 1)) == REG
&& GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
1228 add_op0
= XEXP (op1
, 1); /* reverse operands */
1229 add_op1
= XEXP (op1
, 0);
1232 operands
[2] = add_op0
;
1233 operands
[3] = add_op1
;
1234 ret
= "add%:\t%0,%2,%3";
1237 else if (code1
== HIGH
)
1239 operands
[1] = XEXP (op1
, 0);
1240 ret
= "lui\t%0,%%hi(%1)";
1244 else if (code0
== MEM
)
1247 mips_count_memory_refs (op0
, 1);
1251 int regno1
= REGNO (op1
) + subreg_word1
;
1253 if (GP_REG_P (regno1
))
1258 case SFmode
: ret
= "sw\t%1,%0"; break;
1259 case SImode
: ret
= "sw\t%1,%0"; break;
1260 case HImode
: ret
= "sh\t%1,%0"; break;
1261 case QImode
: ret
= "sb\t%1,%0"; break;
1265 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
1269 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1274 case SFmode
: ret
= "sw\t%z1,%0"; break;
1275 case SImode
: ret
= "sw\t%z1,%0"; break;
1276 case HImode
: ret
= "sh\t%z1,%0"; break;
1277 case QImode
: ret
= "sb\t%z1,%0"; break;
1281 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
1286 case SFmode
: ret
= "sw\t%.,%0"; break;
1287 case SImode
: ret
= "sw\t%.,%0"; break;
1288 case HImode
: ret
= "sh\t%.,%0"; break;
1289 case QImode
: ret
= "sb\t%.,%0"; break;
1293 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1295 int i
= strlen (ret
);
1296 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1299 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1300 ret
= volatile_buffer
;
1304 if (ret
== (char *)0)
1306 abort_with_insn (insn
, "Bad move");
1310 if (delay
!= DELAY_NONE
)
1311 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1317 /* Return the appropriate instructions to move 2 words */
1320 mips_move_2words (operands
, insn
)
1325 rtx op0
= operands
[0];
1326 rtx op1
= operands
[1];
1327 enum rtx_code code0
= GET_CODE (operands
[0]);
1328 enum rtx_code code1
= GET_CODE (operands
[1]);
1329 int subreg_word0
= 0;
1330 int subreg_word1
= 0;
1331 enum delay_type delay
= DELAY_NONE
;
1333 while (code0
== SUBREG
)
1335 subreg_word0
+= SUBREG_WORD (op0
);
1336 op0
= SUBREG_REG (op0
);
1337 code0
= GET_CODE (op0
);
1340 while (code1
== SUBREG
)
1342 subreg_word1
+= SUBREG_WORD (op1
);
1343 op1
= SUBREG_REG (op1
);
1344 code1
= GET_CODE (op1
);
1349 int regno0
= REGNO (op0
) + subreg_word0
;
1353 int regno1
= REGNO (op1
) + subreg_word1
;
1355 /* Just in case, don't do anything for assigning a register
1356 to itself, unless we are filling a delay slot. */
1357 if (regno0
== regno1
&& set_nomacro
== 0)
1360 else if (FP_REG_P (regno0
))
1362 if (FP_REG_P (regno1
))
1363 ret
= "mov.d\t%0,%1";
1371 abort_with_insn (insn
, "Bad move");
1372 #ifdef TARGET_FP_CALL_32
1373 if (FP_CALL_GP_REG_P (regno1
))
1374 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1377 ret
= "dmtc1\t%1,%0";
1380 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1384 else if (FP_REG_P (regno1
))
1390 abort_with_insn (insn
, "Bad move");
1391 #ifdef TARGET_FP_CALL_32
1392 if (FP_CALL_GP_REG_P (regno0
))
1393 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1396 ret
= "dmfc1\t%0,%1";
1399 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1402 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
))
1407 if (regno0
!= HILO_REGNUM
)
1409 else if (regno1
== 0)
1410 ret
= "mtlo\t%.\n\tmthi\t%.";
1413 ret
= "mthi\t%M1\n\tmtlo\t%L1";
1416 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
1421 if (regno1
!= HILO_REGNUM
)
1425 ret
= "mfhi\t%M0\n\tmflo\t%L0";
1428 else if (TARGET_64BIT
)
1429 ret
= "move\t%0,%1";
1431 else if (regno0
!= (regno1
+1))
1432 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
1435 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
1438 else if (code1
== CONST_DOUBLE
)
1440 /* Move zero from $0 unless !TARGET_64BIT and recipient
1441 is 64-bit fp reg, in which case generate a constant. */
1442 if (op1
!= CONST0_RTX (GET_MODE (op1
))
1443 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
1445 if (GET_MODE (op1
) == DFmode
)
1448 #ifdef TARGET_FP_CALL_32
1449 if (FP_CALL_GP_REG_P (regno0
))
1451 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
1453 split_double (op1
, operands
+ 2, operands
+ 3);
1454 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1457 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1461 ret
= "li.d\t%0,%1";
1464 else if (TARGET_64BIT
)
1469 split_double (op1
, operands
+ 2, operands
+ 3);
1470 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1476 if (GP_REG_P (regno0
))
1478 #ifdef TARGET_FP_CALL_32
1479 && ! FP_CALL_GP_REG_P (regno0
)
1483 : "move\t%0,%.\n\tmove\t%D0,%.";
1485 else if (FP_REG_P (regno0
))
1488 ret
= (TARGET_64BIT
)
1490 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1495 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1497 if (GP_REG_P (regno0
))
1498 ret
= (TARGET_64BIT
)
1500 : "move\t%0,%.\n\tmove\t%D0,%.";
1502 else if (FP_REG_P (regno0
))
1505 ret
= (TARGET_64BIT
)
1509 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1511 else if (MD_REG_P (regno0
))
1514 if (regno0
!= HILO_REGNUM
)
1517 ret
= "mtlo\t%.\n\tmthi\t%.";
1521 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
&& GP_REG_P (regno0
))
1525 if (HOST_BITS_PER_WIDE_INT
< 64)
1526 /* We can't use 'X' for negative numbers, because then we won't
1527 get the right value for the upper 32 bits. */
1528 ret
= ((INTVAL (op1
) < 0) ? "dli\t%0,%1\t\t\t# %X1"
1529 : "dli\t%0,%X1\t\t# %1");
1531 /* We must use 'X', because otherwise LONG_MIN will print as
1532 a number that the assembler won't accept. */
1533 ret
= "dli\t%0,%X1\t\t# %1";
1535 else if (HOST_BITS_PER_WIDE_INT
< 64)
1537 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
1538 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1542 /* We use multiple shifts here, to avoid warnings about out
1543 of range shifts on 32 bit hosts. */
1544 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
1545 operands
[1] = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
1546 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1550 else if (code1
== MEM
)
1555 mips_count_memory_refs (op1
, 2);
1557 if (FP_REG_P (regno0
))
1560 else if (TARGET_64BIT
)
1562 #ifdef TARGET_FP_CALL_32
1563 if (FP_CALL_GP_REG_P (regno0
))
1565 if (offsettable_address_p (FALSE
, SImode
, op1
))
1566 ret
= "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1568 ret
= "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1575 else if (offsettable_address_p (1, DFmode
, XEXP (op1
, 0)))
1577 operands
[2] = adj_offsettable_operand (op1
, 4);
1578 if (reg_mentioned_p (op0
, op1
))
1579 ret
= "lw\t%D0,%2\n\tlw\t%0,%1";
1581 ret
= "lw\t%0,%1\n\tlw\t%D0,%2";
1584 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1586 int i
= strlen (ret
);
1587 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1590 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1591 ret
= volatile_buffer
;
1595 else if (code1
== LABEL_REF
1596 || code1
== SYMBOL_REF
1600 mips_count_memory_refs (op1
, 2);
1602 ret
= "dla\t%0,%a1";
1606 else if (code0
== MEM
)
1610 int regno1
= REGNO (op1
) + subreg_word1
;
1612 if (FP_REG_P (regno1
))
1615 else if (TARGET_64BIT
)
1617 #ifdef TARGET_FP_CALL_32
1618 if (FP_CALL_GP_REG_P (regno1
))
1619 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1625 else if (offsettable_address_p (1, DFmode
, XEXP (op0
, 0)))
1627 operands
[2] = adj_offsettable_operand (op0
, 4);
1628 ret
= "sw\t%1,%0\n\tsw\t%D1,%2";
1632 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
1633 || (code1
== CONST_DOUBLE
1634 && op1
== CONST0_RTX (GET_MODE (op1
))))
1636 || offsettable_address_p (1, DFmode
, XEXP (op0
, 0))))
1642 operands
[2] = adj_offsettable_operand (op0
, 4);
1643 ret
= "sw\t%.,%0\n\tsw\t%.,%2";
1648 mips_count_memory_refs (op0
, 2);
1650 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1652 int i
= strlen (ret
);
1653 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1656 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1657 ret
= volatile_buffer
;
1661 if (ret
== (char *)0)
1663 abort_with_insn (insn
, "Bad move");
1667 if (delay
!= DELAY_NONE
)
1668 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1674 /* Provide the costs of an addressing mode that contains ADDR.
1675 If ADDR is not a valid address, its cost is irrelevant. */
1678 mips_address_cost (addr
)
1681 switch (GET_CODE (addr
))
1694 rtx offset
= const0_rtx
;
1695 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
1696 if (GET_CODE (addr
) == LABEL_REF
)
1699 if (GET_CODE (addr
) != SYMBOL_REF
)
1702 if (! SMALL_INT (offset
))
1708 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1712 register rtx plus0
= XEXP (addr
, 0);
1713 register rtx plus1
= XEXP (addr
, 1);
1715 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1717 plus0
= XEXP (addr
, 1);
1718 plus1
= XEXP (addr
, 0);
1721 if (GET_CODE (plus0
) != REG
)
1724 switch (GET_CODE (plus1
))
1730 return (SMALL_INT (plus1
) ? 1 : 2);
1737 return mips_address_cost (plus1
) + 1;
1745 /* Return true if X is an address which needs a temporary register when
1746 reloaded while generating PIC code. */
1749 pic_address_needs_scratch (x
)
1752 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1753 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1754 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1755 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1756 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1762 /* Make normal rtx_code into something we can index from an array */
1764 static enum internal_test
1765 map_test_to_internal_test (test_code
)
1766 enum rtx_code test_code
;
1768 enum internal_test test
= ITEST_MAX
;
1773 case EQ
: test
= ITEST_EQ
; break;
1774 case NE
: test
= ITEST_NE
; break;
1775 case GT
: test
= ITEST_GT
; break;
1776 case GE
: test
= ITEST_GE
; break;
1777 case LT
: test
= ITEST_LT
; break;
1778 case LE
: test
= ITEST_LE
; break;
1779 case GTU
: test
= ITEST_GTU
; break;
1780 case GEU
: test
= ITEST_GEU
; break;
1781 case LTU
: test
= ITEST_LTU
; break;
1782 case LEU
: test
= ITEST_LEU
; break;
1789 /* Generate the code to compare two integer values. The return value is:
1790 (reg:SI xx) The pseudo register the comparison is in
1791 (rtx)0 No register, generate a simple branch.
1793 ??? This is called with result nonzero by the Scond patterns in
1794 mips.md. These patterns are called with a target in the mode of
1795 the Scond instruction pattern. Since this must be a constant, we
1796 must use SImode. This means that if RESULT is non-zero, it will
1797 always be an SImode register, even if TARGET_64BIT is true. We
1798 cope with this by calling convert_move rather than emit_move_insn.
1799 This will sometimes lead to an unnecessary extension of the result;
1811 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
1812 enum rtx_code test_code
; /* relational test (EQ, etc) */
1813 rtx result
; /* result to store comp. or 0 if branch */
1814 rtx cmp0
; /* first operand to compare */
1815 rtx cmp1
; /* second operand to compare */
1816 int *p_invert
; /* NULL or ptr to hold whether branch needs */
1817 /* to reverse its test */
1820 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
1821 int const_low
; /* low bound of constant we can accept */
1822 int const_high
; /* high bound of constant we can accept */
1823 int const_add
; /* constant to add (convert LE -> LT) */
1824 int reverse_regs
; /* reverse registers in test */
1825 int invert_const
; /* != 0 if invert value if cmp1 is constant */
1826 int invert_reg
; /* != 0 if invert value if cmp1 is register */
1827 int unsignedp
; /* != 0 for unsigned comparisons. */
1830 static struct cmp_info info
[ (int)ITEST_MAX
] = {
1832 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
1833 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
1834 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
1835 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
1836 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
1837 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
1838 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
1839 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
1840 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
1841 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
1844 enum internal_test test
;
1845 enum machine_mode mode
;
1846 struct cmp_info
*p_info
;
1853 test
= map_test_to_internal_test (test_code
);
1854 if (test
== ITEST_MAX
)
1857 p_info
= &info
[ (int)test
];
1858 eqne_p
= (p_info
->test_code
== XOR
);
1860 mode
= GET_MODE (cmp0
);
1861 if (mode
== VOIDmode
)
1862 mode
= GET_MODE (cmp1
);
1864 /* Eliminate simple branches */
1865 branch_p
= (result
== (rtx
)0);
1868 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
1870 /* Comparisons against zero are simple branches */
1871 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
1874 /* Test for beq/bne. */
1879 /* allocate a pseudo to calculate the value in. */
1880 result
= gen_reg_rtx (mode
);
1883 /* Make sure we can handle any constants given to us. */
1884 if (GET_CODE (cmp0
) == CONST_INT
)
1885 cmp0
= force_reg (mode
, cmp0
);
1887 if (GET_CODE (cmp1
) == CONST_INT
)
1889 HOST_WIDE_INT value
= INTVAL (cmp1
);
1890 if (value
< p_info
->const_low
1891 || value
> p_info
->const_high
1892 /* ??? Why? And why wasn't the similar code below modified too? */
1894 && HOST_BITS_PER_WIDE_INT
< 64
1895 && p_info
->const_add
!= 0
1896 && ((p_info
->unsignedp
1897 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
1899 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
1900 != (p_info
->const_add
> 0))))
1901 cmp1
= force_reg (mode
, cmp1
);
1904 /* See if we need to invert the result. */
1905 invert
= (GET_CODE (cmp1
) == CONST_INT
)
1906 ? p_info
->invert_const
1907 : p_info
->invert_reg
;
1909 if (p_invert
!= (int *)0)
1915 /* Comparison to constants, may involve adding 1 to change a LT into LE.
1916 Comparison between two registers, may involve switching operands. */
1917 if (GET_CODE (cmp1
) == CONST_INT
)
1919 if (p_info
->const_add
!= 0)
1921 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
1922 /* If modification of cmp1 caused overflow,
1923 we would get the wrong answer if we follow the usual path;
1924 thus, x > 0xffffffffU would turn into x > 0U. */
1925 if ((p_info
->unsignedp
1926 ? (unsigned HOST_WIDE_INT
) new > INTVAL (cmp1
)
1927 : new > INTVAL (cmp1
))
1928 != (p_info
->const_add
> 0))
1930 /* This test is always true, but if INVERT is true then
1931 the result of the test needs to be inverted so 0 should
1932 be returned instead. */
1933 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
1937 cmp1
= GEN_INT (new);
1940 else if (p_info
->reverse_regs
)
1947 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
1951 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
1952 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
1955 if (test
== ITEST_NE
)
1957 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
1961 else if (test
== ITEST_EQ
)
1963 reg2
= (invert
) ? gen_reg_rtx (mode
) : result
;
1964 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
1969 convert_move (result
, gen_rtx (XOR
, mode
, reg
, const1_rtx
), 0);
1975 /* Emit the common code for doing conditional branches.
1976 operand[0] is the label to jump to.
1977 The comparison operands are saved away by cmp{si,di,sf,df}. */
1980 gen_conditional_branch (operands
, test_code
)
1982 enum rtx_code test_code
;
1984 static enum machine_mode mode_map
[(int)CMP_MAX
][(int)ITEST_MAX
] = {
2011 CC_REV_FPmode
, /* ne */
2023 CC_REV_FPmode
, /* ne */
2035 enum machine_mode mode
;
2036 enum cmp_type type
= branch_type
;
2037 rtx cmp0
= branch_cmp
[0];
2038 rtx cmp1
= branch_cmp
[1];
2039 rtx label1
= gen_rtx (LABEL_REF
, VOIDmode
, operands
[0]);
2040 rtx label2
= pc_rtx
;
2043 enum internal_test test
= map_test_to_internal_test (test_code
);
2045 if (test
== ITEST_MAX
)
2051 /* Get the machine mode to use (CCmode, CC_EQmode, CC_FPmode, or CC_REV_FPmode). */
2052 mode
= mode_map
[(int)type
][(int)test
];
2053 if (mode
== VOIDmode
)
2063 reg
= gen_int_relational (test_code
, (rtx
)0, cmp0
, cmp1
, &invert
);
2071 /* Make sure not non-zero constant if ==/!= */
2072 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
2073 cmp1
= force_reg (mode
, cmp1
);
2080 rtx reg
= gen_rtx (REG
, mode
, FPSW_REGNUM
);
2081 emit_insn (gen_rtx (SET
, VOIDmode
, reg
, gen_rtx (test_code
, mode
, cmp0
, cmp1
)));
2089 /* Generate the jump */
2096 emit_jump_insn (gen_rtx (SET
, VOIDmode
,
2098 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
2099 gen_rtx (test_code
, mode
, cmp0
, cmp1
),
2106 abort_with_insn (gen_rtx (test_code
, mode
, cmp0
, cmp1
), "bad test");
2111 /* Internal code to generate the load and store of one word/short/byte.
2112 The load is emitted directly, and the store insn is returned. */
2114 #define UNITS_PER_MIPS_DWORD 8
2115 #define UNITS_PER_MIPS_WORD 4
2116 #define UNITS_PER_MIPS_HWORD 2
2119 block_move_load_store (dest_reg
, src_reg
, p_bytes
, p_offset
, align
, orig_src
)
2120 rtx src_reg
; /* register holding source memory address */
2121 rtx dest_reg
; /* register holding dest. memory address */
2122 int *p_bytes
; /* pointer to # bytes remaining */
2123 int *p_offset
; /* pointer to current offset */
2124 int align
; /* alignment */
2125 rtx orig_src
; /* original source for making a reg note */
2127 int bytes
; /* # bytes remaining */
2128 int offset
; /* offset to use */
2129 int size
; /* size in bytes of load/store */
2130 enum machine_mode mode
; /* mode to use for load/store */
2131 rtx reg
; /* temporary register */
2132 rtx src_addr
; /* source address */
2133 rtx dest_addr
; /* destination address */
2134 rtx insn
; /* insn of the load */
2135 rtx orig_src_addr
; /* original source address */
2136 rtx (*load_func
)(); /* function to generate load insn */
2137 rtx (*store_func
)(); /* function to generate destination insn */
2140 if (bytes
<= 0 || align
<= 0)
2143 if (bytes
>= UNITS_PER_MIPS_DWORD
&& align
>= UNIS_PER_MIPS_DWORD
)
2146 size
= UNITS_PER_MIPS_DWORD
;
2147 load_func
= gen_movdi
;
2148 store_func
= gen_movdi
;
2150 else if (bytes
>= UNITS_PER_MIPS_WORD
&& align
>= UNITS_PER_MIPS_WORD
)
2153 size
= UNITS_PER_MIPS_WORD
;
2154 load_func
= gen_movsi
;
2155 store_func
= gen_movsi
;
2159 /* Don't generate unaligned moves here, rather defer those to the
2160 general movestrsi_internal pattern.
2161 If this gets commented back in, then should add the dword equivalent. */
2162 else if (bytes
>= UNITS_PER_MIPS_WORD
)
2165 size
= UNITS_PER_MIPS_WORD
;
2166 load_func
= gen_movsi_ulw
;
2167 store_func
= gen_movsi_usw
;
2171 else if (bytes
>= UNITS_PER_MIPS_SHORT
&& align
>= UNITS_PER_MIPS_SHORT
)
2174 size
= UNITS_PER_MIPS_SHORT
;
2175 load_func
= gen_movhi
;
2176 store_func
= gen_movhi
;
2183 load_func
= gen_movqi
;
2184 store_func
= gen_movqi
;
2188 *p_offset
= offset
+ size
;
2189 *p_bytes
= bytes
- size
;
2194 dest_addr
= dest_reg
;
2198 src_addr
= gen_rtx (PLUS
, Pmode
, src_reg
, GEN_INT (offset
));
2199 dest_addr
= gen_rtx (PLUS
, Pmode
, dest_reg
, GEN_INT (offset
));
2202 reg
= gen_reg_rtx (mode
);
2203 insn
= emit_insn ((*load_func
) (reg
, gen_rtx (MEM
, mode
, src_addr
)));
2204 orig_src_addr
= XEXP (orig_src
, 0);
2205 if (CONSTANT_P (orig_src_addr
))
2206 REG_NOTES (insn
) = gen_rtx (EXPR_LIST
, REG_EQUIV
,
2207 plus_constant (orig_src_addr
, offset
),
2210 return (*store_func
) (gen_rtx (MEM
, mode
, dest_addr
), reg
);
2215 /* Write a series of loads/stores to move some bytes. Generate load/stores as follows:
2227 This way, no NOP's are needed, except at the end, and only
2228 two temp registers are needed. Two delay slots are used
2229 in deference to the R4000. */
2233 block_move_sequence (dest_reg
, src_reg
, bytes
, align
, orig_src
)
2234 rtx dest_reg
; /* register holding destination address */
2235 rtx src_reg
; /* register holding source address */
2236 int bytes
; /* # bytes to move */
2237 int align
; /* max alignment to assume */
2238 rtx orig_src
; /* original source for making a reg note */
2241 rtx prev2_store
= (rtx
)0;
2242 rtx prev_store
= (rtx
)0;
2243 rtx cur_store
= (rtx
)0;
2247 /* Is there a store to do? */
2249 emit_insn (prev2_store
);
2251 prev2_store
= prev_store
;
2252 prev_store
= cur_store
;
2253 cur_store
= block_move_load_store (dest_reg
, src_reg
,
2258 /* Finish up last three stores. */
2260 emit_insn (prev2_store
);
2263 emit_insn (prev_store
);
2266 emit_insn (cur_store
);
2271 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2277 temp<last> = src[MAX_MOVE_REGS-1];
2281 dest[MAX_MOVE_REGS-1] = temp<last>;
2282 src += MAX_MOVE_REGS;
2283 dest += MAX_MOVE_REGS;
2284 } while (src != final);
2286 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2287 registers are needed.
2289 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2290 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2291 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2293 #define MAX_MOVE_REGS 4
2294 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2296 /* ??? Should add code to use DWORD load/stores. */
2299 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_src
)
2300 rtx dest_reg
; /* register holding destination address */
2301 rtx src_reg
; /* register holding source address */
2302 int bytes
; /* # bytes to move */
2303 int align
; /* alignment */
2304 rtx orig_src
; /* original source for making a reg note */
2306 rtx dest_mem
= gen_rtx (MEM
, BLKmode
, dest_reg
);
2307 rtx src_mem
= gen_rtx (MEM
, BLKmode
, src_reg
);
2308 rtx align_rtx
= GEN_INT (align
);
2314 if (bytes
< 2*MAX_MOVE_BYTES
)
2317 leftover
= bytes
% MAX_MOVE_BYTES
;
2320 label
= gen_label_rtx ();
2321 final_src
= gen_reg_rtx (Pmode
);
2322 bytes_rtx
= GEN_INT (bytes
);
2328 emit_insn (gen_movdi (final_src
, bytes_rtx
));
2329 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
2333 emit_insn (gen_movsi (final_src
, bytes_rtx
));
2334 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2340 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
2342 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
2347 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
2348 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
2351 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
2352 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
2353 emit_insn (gen_cmpdi (src_reg
, final_src
));
2357 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
2358 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
2359 emit_insn (gen_cmpsi (src_reg
, final_src
));
2361 emit_jump_insn (gen_bne (label
));
2364 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
,
2370 /* Use a library function to move some bytes. */
2373 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2378 /* We want to pass the size as Pmode, which will normally be SImode
2379 but will be DImode if we are using 64 bit longs and pointers. */
2380 if (GET_MODE (bytes_rtx
) != VOIDmode
2381 && GET_MODE (bytes_rtx
) != Pmode
)
2382 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, TRUE
);
2384 #ifdef TARGET_MEM_FUNCTIONS
2385 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0,
2389 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2390 TREE_UNSIGNED (sizetype
)),
2391 TYPE_MODE (sizetype
));
2393 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "bcopy"), 0,
2397 convert_to_mode (TYPE_MODE (integer_type_node
),
2399 TREE_UNSIGNED (integer_type_node
)),
2400 TYPE_MODE (integer_type_node
));
2405 /* Expand string/block move operations.
2407 operands[0] is the pointer to the destination.
2408 operands[1] is the pointer to the source.
2409 operands[2] is the number of bytes to move.
2410 operands[3] is the alignment. */
2413 expand_block_move (operands
)
2416 rtx bytes_rtx
= operands
[2];
2417 rtx align_rtx
= operands
[3];
2418 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2419 int bytes
= (constp
? INTVAL (bytes_rtx
) : 0);
2420 int align
= INTVAL (align_rtx
);
2421 rtx orig_src
= operands
[1];
2425 if (constp
&& bytes
<= 0)
2428 if (align
> UNITS_PER_WORD
)
2429 align
= UNITS_PER_WORD
;
2431 /* Move the address into scratch registers. */
2432 dest_reg
= copy_addr_to_reg (XEXP (operands
[0], 0));
2433 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2436 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2439 else if (constp
&& bytes
<= 3*align
)
2440 block_move_sequence (dest_reg
, src_reg
, bytes
, align
, orig_src
);
2443 else if (constp
&& bytes
<= 2*MAX_MOVE_BYTES
)
2444 emit_insn (gen_movstrsi_internal (change_address (operands
[0],
2446 change_address (orig_src
, BLKmode
,
2448 bytes_rtx
, align_rtx
));
2450 else if (constp
&& align
>= UNITS_PER_WORD
&& optimize
)
2451 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_src
);
2453 else if (constp
&& optimize
)
2455 /* If the alignment is not word aligned, generate a test at
2456 runtime, to see whether things wound up aligned, and we
2457 can use the faster lw/sw instead ulw/usw. */
2459 rtx temp
= gen_reg_rtx (Pmode
);
2460 rtx aligned_label
= gen_label_rtx ();
2461 rtx join_label
= gen_label_rtx ();
2462 int leftover
= bytes
% MAX_MOVE_BYTES
;
2468 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
2469 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2470 emit_insn (gen_cmpdi (temp
, const0_rtx
));
2474 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
2475 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2476 emit_insn (gen_cmpsi (temp
, const0_rtx
));
2478 emit_jump_insn (gen_beq (aligned_label
));
2480 /* Unaligned loop. */
2481 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_src
);
2482 emit_jump_insn (gen_jump (join_label
));
2486 emit_label (aligned_label
);
2487 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_src
);
2488 emit_label (join_label
);
2490 /* Bytes at the end of the loop. */
2494 if (leftover
<= 3*align
)
2495 block_move_sequence (dest_reg
, src_reg
, leftover
, align
, orig_src
);
2499 emit_insn (gen_movstrsi_internal (gen_rtx (MEM
, BLKmode
, dest_reg
),
2500 gen_rtx (MEM
, BLKmode
, src_reg
),
2507 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2511 /* Emit load/stores for a small constant block_move.
2513 operands[0] is the memory address of the destination.
2514 operands[1] is the memory address of the source.
2515 operands[2] is the number of bytes to move.
2516 operands[3] is the alignment.
2517 operands[4] is a temp register.
2518 operands[5] is a temp register.
2520 operands[3+num_regs] is the last temp register.
2522 The block move type can be one of the following:
2523 BLOCK_MOVE_NORMAL Do all of the block move.
2524 BLOCK_MOVE_NOT_LAST Do all but the last store.
2525 BLOCK_MOVE_LAST Do just the last store. */
2528 output_block_move (insn
, operands
, num_regs
, move_type
)
2532 enum block_move_type move_type
;
2534 rtx dest_reg
= XEXP (operands
[0], 0);
2535 rtx src_reg
= XEXP (operands
[1], 0);
2536 int bytes
= INTVAL (operands
[2]);
2537 int align
= INTVAL (operands
[3]);
2540 int use_lwl_lwr
= FALSE
;
2541 int last_operand
= num_regs
+4;
2547 char *load
; /* load insn without nop */
2548 char *load_nop
; /* load insn with trailing nop */
2549 char *store
; /* store insn */
2550 char *final
; /* if last_store used: NULL or swr */
2551 char *last_store
; /* last store instruction */
2552 int offset
; /* current offset */
2553 enum machine_mode mode
; /* mode to use on (MEM) */
2556 /* Detect a bug in GCC, where it can give us a register
2557 the same as one of the addressing registers and reduce
2558 the number of registers available. */
2560 i
< last_operand
&& safe_regs
< (sizeof(xoperands
) / sizeof(xoperands
[0]));
2563 if (!reg_mentioned_p (operands
[i
], operands
[0])
2564 && !reg_mentioned_p (operands
[i
], operands
[1]))
2566 xoperands
[safe_regs
++] = operands
[i
];
2569 if (safe_regs
< last_operand
)
2571 xoperands
[0] = operands
[0];
2572 xoperands
[1] = operands
[1];
2573 xoperands
[2] = operands
[2];
2574 xoperands
[3] = operands
[3];
2575 return output_block_move (insn
, xoperands
, safe_regs
-4, move_type
);
2578 /* If we are given global or static addresses, and we would be
2579 emitting a few instructions, try to save time by using a
2580 temporary register for the pointer. */
2581 if (num_regs
> 2 && (bytes
> 2*align
|| move_type
!= BLOCK_MOVE_NORMAL
))
2583 if (CONSTANT_P (src_reg
))
2586 mips_count_memory_refs (operands
[1], 1);
2588 src_reg
= operands
[ 3 + num_regs
-- ];
2589 if (move_type
!= BLOCK_MOVE_LAST
)
2591 xoperands
[1] = operands
[1];
2592 xoperands
[0] = src_reg
;
2593 if (Pmode
== DImode
)
2594 output_asm_insn ("dla\t%0,%1", xoperands
);
2596 output_asm_insn ("la\t%0,%1", xoperands
);
2600 if (CONSTANT_P (dest_reg
))
2603 mips_count_memory_refs (operands
[0], 1);
2605 dest_reg
= operands
[ 3 + num_regs
-- ];
2606 if (move_type
!= BLOCK_MOVE_LAST
)
2608 xoperands
[1] = operands
[0];
2609 xoperands
[0] = dest_reg
;
2610 if (Pmode
== DImode
)
2611 output_asm_insn ("dla\t%0,%1", xoperands
);
2613 output_asm_insn ("la\t%0,%1", xoperands
);
2618 /* ??? We really shouldn't get any LO_SUM addresses here, because they
2619 are not offsettable, however, offsettable_address_p says they are
2620 offsettable. I think this is a bug in offsettable_address_p.
2621 For expediency, we fix this by just loading the address into a register
2622 if we happen to get one. */
2624 if (GET_CODE (src_reg
) == LO_SUM
)
2626 src_reg
= operands
[ 3 + num_regs
-- ];
2627 if (move_type
!= BLOCK_MOVE_LAST
)
2629 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
2630 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2631 xoperands
[0] = src_reg
;
2632 if (Pmode
== DImode
)
2633 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2635 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2639 if (GET_CODE (dest_reg
) == LO_SUM
)
2641 dest_reg
= operands
[ 3 + num_regs
-- ];
2642 if (move_type
!= BLOCK_MOVE_LAST
)
2644 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
2645 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
2646 xoperands
[0] = dest_reg
;
2647 if (Pmode
== DImode
)
2648 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2650 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2654 if (num_regs
> (sizeof (load_store
) / sizeof (load_store
[0])))
2655 num_regs
= (sizeof (load_store
) / sizeof (load_store
[0]));
2657 else if (num_regs
< 1)
2658 abort_with_insn (insn
, "Cannot do block move, not enough scratch registers");
2662 load_store
[num
].offset
= offset
;
2664 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
2666 load_store
[num
].load
= "ld\t%0,%1";
2667 load_store
[num
].load_nop
= "ld\t%0,%1%#";
2668 load_store
[num
].store
= "sd\t%0,%1";
2669 load_store
[num
].last_store
= "sd\t%0,%1";
2670 load_store
[num
].final
= (char *)0;
2671 load_store
[num
].mode
= DImode
;
2676 /* ??? Fails because of a MIPS assembler bug? */
2677 else if (TARGET_64BIT
&& bytes
>= 8)
2679 if (BYTES_BIG_ENDIAN
)
2681 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
2682 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
2683 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
2684 load_store
[num
].last_store
= "sdr\t%0,%2";
2685 load_store
[num
].final
= "sdl\t%0,%1";
2689 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
2690 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
2691 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
2692 load_store
[num
].last_store
= "sdr\t%0,%1";
2693 load_store
[num
].final
= "sdl\t%0,%2";
2695 load_store
[num
].mode
= DImode
;
2701 else if (bytes
>= 4 && align
>= 4)
2703 load_store
[num
].load
= "lw\t%0,%1";
2704 load_store
[num
].load_nop
= "lw\t%0,%1%#";
2705 load_store
[num
].store
= "sw\t%0,%1";
2706 load_store
[num
].last_store
= "sw\t%0,%1";
2707 load_store
[num
].final
= (char *)0;
2708 load_store
[num
].mode
= SImode
;
2713 else if (bytes
>= 4)
2715 if (BYTES_BIG_ENDIAN
)
2717 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
2718 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2719 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
2720 load_store
[num
].last_store
= "swr\t%0,%2";
2721 load_store
[num
].final
= "swl\t%0,%1";
2725 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
2726 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2727 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
2728 load_store
[num
].last_store
= "swr\t%0,%1";
2729 load_store
[num
].final
= "swl\t%0,%2";
2731 load_store
[num
].mode
= SImode
;
2737 else if (bytes
>= 2 && align
>= 2)
2739 load_store
[num
].load
= "lh\t%0,%1";
2740 load_store
[num
].load_nop
= "lh\t%0,%1%#";
2741 load_store
[num
].store
= "sh\t%0,%1";
2742 load_store
[num
].last_store
= "sh\t%0,%1";
2743 load_store
[num
].final
= (char *)0;
2744 load_store
[num
].mode
= HImode
;
2751 load_store
[num
].load
= "lb\t%0,%1";
2752 load_store
[num
].load_nop
= "lb\t%0,%1%#";
2753 load_store
[num
].store
= "sb\t%0,%1";
2754 load_store
[num
].last_store
= "sb\t%0,%1";
2755 load_store
[num
].final
= (char *)0;
2756 load_store
[num
].mode
= QImode
;
2761 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2763 dslots_load_total
++;
2764 dslots_load_filled
++;
2766 if (CONSTANT_P (src_reg
))
2767 mips_count_memory_refs (src_reg
, 1);
2769 if (CONSTANT_P (dest_reg
))
2770 mips_count_memory_refs (dest_reg
, 1);
2773 /* Emit load/stores now if we have run out of registers or are
2774 at the end of the move. */
2776 if (++num
== num_regs
|| bytes
== 0)
2778 /* If only load/store, we need a NOP after the load. */
2781 load_store
[0].load
= load_store
[0].load_nop
;
2782 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2783 dslots_load_filled
--;
2786 if (move_type
!= BLOCK_MOVE_LAST
)
2788 for (i
= 0; i
< num
; i
++)
2795 if (GET_MODE (operands
[i
+4]) != load_store
[i
].mode
)
2796 operands
[i
+4] = gen_rtx (REG
, load_store
[i
].mode
, REGNO (operands
[i
+4]));
2798 offset
= load_store
[i
].offset
;
2799 xoperands
[0] = operands
[i
+4];
2800 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2801 plus_constant (src_reg
, offset
));
2806 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2807 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2808 plus_constant (src_reg
,
2813 output_asm_insn (load_store
[i
].load
, xoperands
);
2817 for (i
= 0; i
< num
; i
++)
2819 int last_p
= (i
== num
-1 && bytes
== 0);
2820 int offset
= load_store
[i
].offset
;
2822 xoperands
[0] = operands
[i
+4];
2823 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2824 plus_constant (dest_reg
, offset
));
2830 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2831 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2832 plus_constant (dest_reg
,
2837 if (move_type
== BLOCK_MOVE_NORMAL
)
2838 output_asm_insn (load_store
[i
].store
, xoperands
);
2840 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
2843 output_asm_insn (load_store
[i
].store
, xoperands
);
2845 else if (load_store
[i
].final
!= (char *)0)
2846 output_asm_insn (load_store
[i
].final
, xoperands
);
2850 output_asm_insn (load_store
[i
].last_store
, xoperands
);
2853 num
= 0; /* reset load_store */
2854 use_lwl_lwr
= FALSE
;
2862 /* Argument support functions. */
2864 /* Initialize CUMULATIVE_ARGS for a function. */
2867 init_cumulative_args (cum
, fntype
, libname
)
2868 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
2869 tree fntype
; /* tree ptr for function decl */
2870 rtx libname
; /* SYMBOL_REF of library name or 0 */
2872 static CUMULATIVE_ARGS zero_cum
;
2873 tree param
, next_param
;
2875 if (TARGET_DEBUG_E_MODE
)
2877 fprintf (stderr
, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
2879 fputc ('\n', stderr
);
2883 tree ret_type
= TREE_TYPE (fntype
);
2884 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
2885 tree_code_name
[ (int)TREE_CODE (fntype
) ],
2886 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
2892 /* Determine if this function has variable arguments. This is
2893 indicated by the last argument being 'void_type_mode' if there
2894 are no variable arguments. The standard MIPS calling sequence
2895 passes all arguments in the general purpose registers in this
2898 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
2902 next_param
= TREE_CHAIN (param
);
2903 if (next_param
== (tree
)0 && TREE_VALUE (param
) != void_type_node
)
2904 cum
->gp_reg_found
= 1;
2908 /* Advance the argument to the next argument position. */
2911 function_arg_advance (cum
, mode
, type
, named
)
2912 CUMULATIVE_ARGS
*cum
; /* current arg information */
2913 enum machine_mode mode
; /* current arg mode */
2914 tree type
; /* type of the argument or 0 if lib support */
2915 int named
; /* whether or not the argument was named */
2917 if (TARGET_DEBUG_E_MODE
)
2919 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
2920 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
2930 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
2931 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
2933 cum
->gp_reg_found
= 1;
2934 cum
->arg_words
+= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
2939 cum
->gp_reg_found
= 1;
2940 cum
->arg_words
+= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
2949 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
2953 cum
->gp_reg_found
= 1;
2954 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
2960 cum
->gp_reg_found
= 1;
2966 /* Return an RTL expression containing the register for the given mode,
2967 or 0 if the argument is to be passed on the stack. */
2970 function_arg (cum
, mode
, type
, named
)
2971 CUMULATIVE_ARGS
*cum
; /* current arg information */
2972 enum machine_mode mode
; /* current arg mode */
2973 tree type
; /* type of the argument or 0 if lib support */
2974 int named
; /* != 0 for normal args, == 0 for ... args */
2979 int struct_p
= ((type
!= (tree
)0)
2980 && (TREE_CODE (type
) == RECORD_TYPE
2981 || TREE_CODE (type
) == UNION_TYPE
));
2983 if (TARGET_DEBUG_E_MODE
)
2985 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
2986 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
2992 if (mips_abi
== ABI_32
)
2994 if (cum
->gp_reg_found
|| cum
->arg_number
>= 2 || TARGET_SOFT_FLOAT
)
2995 regbase
= GP_ARG_FIRST
;
2998 regbase
= FP_ARG_FIRST
;
2999 /* If the first arg was a float in a floating point register,
3000 then set bias to align this float arg properly. */
3001 if (cum
->arg_words
== 1)
3006 regbase
= (TARGET_SOFT_FLOAT
|| ! named
? GP_ARG_FIRST
: FP_ARG_FIRST
);
3011 cum
->arg_words
+= (cum
->arg_words
& 1);
3012 if (mips_abi
== ABI_32
)
3013 regbase
= ((cum
->gp_reg_found
3014 || TARGET_SOFT_FLOAT
3015 || TARGET_SINGLE_FLOAT
3016 || cum
->arg_number
>= 2)
3020 regbase
= (TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
|| ! named
3021 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
3025 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3026 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3029 /* Drops through. */
3031 if (type
!= (tree
)0 && TYPE_ALIGN (type
) > BITS_PER_WORD
3033 cum
->arg_words
+= (cum
->arg_words
& 1);
3035 regbase
= GP_ARG_FIRST
;
3042 regbase
= GP_ARG_FIRST
;
3047 cum
->arg_words
+= (cum
->arg_words
& 1);
3048 regbase
= GP_ARG_FIRST
;
3051 if (cum
->arg_words
>= MAX_ARGS_IN_REGISTERS
)
3053 if (TARGET_DEBUG_E_MODE
)
3054 fprintf (stderr
, "<stack>%s\n", struct_p
? ", [struct]" : "");
3063 if (! type
|| TREE_CODE (type
) != RECORD_TYPE
|| mips_abi
== ABI_32
3065 ret
= gen_rtx (REG
, mode
, regbase
+ cum
->arg_words
+ bias
);
3068 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3069 structure contains a double in its entirety, then that 64 bit
3070 chunk is passed in a floating point register. */
3073 /* First check to see if there is any such field. */
3074 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3075 if (TREE_CODE (field
) == FIELD_DECL
3076 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3077 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
3078 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3079 % BITS_PER_WORD
== 0))
3083 ret
= gen_rtx (REG
, mode
, regbase
+ cum
->arg_words
+ bias
);
3086 /* Now handle the special case by returning a PARALLEL
3087 indicating where each 64 bit chunk goes. */
3093 /* ??? If this is a packed structure, then the last hunk won't
3096 /* ??? If this is a structure with a single double field,
3097 it would be more convenient to return (REG:DI %fX) than
3098 a parallel. However, we would have to modify the mips
3099 backend to allow DImode values in fp registers. */
3101 chunks
= TREE_INT_CST_LOW (TYPE_SIZE (type
)) / BITS_PER_WORD
;
3102 if (chunks
+ cum
->arg_words
+ bias
> MAX_ARGS_IN_REGISTERS
)
3103 chunks
= MAX_ARGS_IN_REGISTERS
- cum
->arg_words
- bias
;
3105 /* assign_parms checks the mode of ENTRY_PARM, so we must
3106 use the actual mode here. */
3107 ret
= gen_rtx (PARALLEL
, mode
, rtvec_alloc (chunks
));
3110 regno
= regbase
+ cum
->arg_words
+ bias
;
3111 field
= TYPE_FIELDS (type
);
3112 for (i
= 0; i
< chunks
; i
++)
3116 for (; field
; field
= TREE_CHAIN (field
))
3117 if (TREE_CODE (field
) == FIELD_DECL
3118 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3123 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
)) == bitpos
3124 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3125 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
3126 reg
= gen_rtx (REG
, DFmode
,
3127 regno
+ FP_ARG_FIRST
- GP_ARG_FIRST
);
3129 reg
= gen_rtx (REG
, word_mode
, regno
);
3131 XVECEXP (ret
, 0, i
) = gen_rtx (EXPR_LIST
, VOIDmode
, reg
,
3132 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3140 if (TARGET_DEBUG_E_MODE
)
3141 fprintf (stderr
, "%s%s\n", reg_names
[regbase
+ cum
->arg_words
+ bias
],
3142 struct_p
? ", [struct]" : "");
3144 /* The following is a hack in order to pass 1 byte structures
3145 the same way that the MIPS compiler does (namely by passing
3146 the structure in the high byte or half word of the register).
3147 This also makes varargs work. If we have such a structure,
3148 we save the adjustment RTL, and the call define expands will
3149 emit them. For the VOIDmode argument (argument after the
3150 last real argument), pass back a parallel vector holding each
3151 of the adjustments. */
3153 /* ??? function_arg can be called more than once for each argument.
3154 As a result, we compute more adjustments than we need here.
3155 See the CUMULATIVE_ARGS definition in mips.h. */
3157 /* ??? This scheme requires everything smaller than the word size to
3158 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3159 that would mean every int needs to be shifted left, which is very
3160 inefficient. Let's not carry this compatibility to the 64 bit
3161 calling convention for now. */
3163 if (struct_p
&& int_size_in_bytes (type
) < UNITS_PER_WORD
3166 rtx amount
= GEN_INT (BITS_PER_WORD
3167 - int_size_in_bytes (type
) * BITS_PER_UNIT
);
3168 rtx reg
= gen_rtx (REG
, word_mode
, regbase
+ cum
->arg_words
+ bias
);
3170 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashldi3 (reg
, reg
, amount
);
3172 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashlsi3 (reg
, reg
, amount
);
3176 if (mode
== VOIDmode
&& cum
->num_adjusts
> 0)
3177 ret
= gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec_v (cum
->num_adjusts
, cum
->adjust
));
3184 function_arg_partial_nregs (cum
, mode
, type
, named
)
3185 CUMULATIVE_ARGS
*cum
; /* current arg information */
3186 enum machine_mode mode
; /* current arg mode */
3187 tree type
; /* type of the argument or 0 if lib support */
3188 int named
; /* != 0 for normal args, == 0 for ... args */
3190 if ((mode
== BLKmode
3191 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3192 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3193 && cum
->arg_words
< MAX_ARGS_IN_REGISTERS
)
3196 if (mode
== BLKmode
)
3197 words
= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3200 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3202 if (words
+ cum
->arg_words
<= MAX_ARGS_IN_REGISTERS
)
3203 return 0; /* structure fits in registers */
3205 if (TARGET_DEBUG_E_MODE
)
3206 fprintf (stderr
, "function_arg_partial_nregs = %d\n",
3207 MAX_ARGS_IN_REGISTERS
- cum
->arg_words
);
3209 return MAX_ARGS_IN_REGISTERS
- cum
->arg_words
;
3212 else if (mode
== DImode
&& cum
->arg_words
== MAX_ARGS_IN_REGISTERS
-1
3215 if (TARGET_DEBUG_E_MODE
)
3216 fprintf (stderr
, "function_arg_partial_nregs = 1\n");
3224 /* Abort after printing out a specific insn. */
3227 abort_with_insn (insn
, reason
)
3236 /* Write a message to stderr (for use in macros expanded in files that do not
3237 include stdio.h). */
3243 fprintf (stderr
, s
, s1
, s2
);
3253 fprintf (stderr
, "compiling '%s' in '%s'\n",
3254 (current_function_name
!= (char *)0) ? current_function_name
: "<toplevel>",
3255 (current_function_file
!= (char *)0) ? current_function_file
: "<no file>");
3258 #endif /* SIGINFO */
3261 /* Set up the threshold for data to go into the small data area, instead
3262 of the normal data area, and detect any conflicts in the switches. */
3267 register int i
, start
;
3269 register enum machine_mode mode
;
3271 mips_section_threshold
= (g_switch_set
) ? g_switch_value
: MIPS_DEFAULT_GVALUE
;
3273 if (mips_section_threshold
<= 0)
3274 target_flags
&= ~MASK_GPOPT
;
3276 target_flags
|= MASK_GPOPT
;
3278 /* Get the architectural level. */
3279 if (mips_isa_string
== (char *)0)
3281 #ifdef MIPS_ISA_DEFAULT
3282 mips_isa
= MIPS_ISA_DEFAULT
;
3288 else if (isdigit (*mips_isa_string
))
3290 mips_isa
= atoi (mips_isa_string
);
3291 if (mips_isa
< 1 || mips_isa
> 4)
3293 error ("-mips%d not supported", mips_isa
);
3300 error ("bad value (%s) for -mips switch", mips_isa_string
);
3304 #ifdef MIPS_ABI_DEFAULT
3305 /* Get the ABI to use. Currently this code is only used for Irix 6. */
3306 if (mips_abi_string
== (char *) 0)
3307 mips_abi
= MIPS_ABI_DEFAULT
;
3308 else if (! strcmp (mips_abi_string
, "32")
3309 || ! strcmp (mips_abi_string
, "o32"))
3311 else if (! strcmp (mips_abi_string
, "n32"))
3313 else if (! strcmp (mips_abi_string
, "64")
3314 || ! strcmp (mips_abi_string
, "n64"))
3317 error ("bad value (%s) for -mabi= switch", mips_abi_string
);
3319 /* A specified ISA defaults the ABI if it was not specified. */
3320 if (mips_abi_string
== 0 && mips_isa_string
)
3327 /* A specified ABI defaults the ISA if it was not specified. */
3328 else if (mips_isa_string
== 0 && mips_abi_string
)
3330 if (mips_abi
== ABI_32
)
3332 else if (mips_abi
== ABI_N32
)
3337 /* If both ABI and ISA were specified, check for conflicts. */
3338 else if (mips_isa_string
&& mips_abi_string
)
3340 if ((mips_isa
<= 2 && (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
3341 || (mips_isa
>= 3 && mips_abi
== ABI_32
))
3342 error ("-mabi=%s does not support -mips%d", mips_abi_string
, mips_isa
);
3345 /* Override TARGET_DEFAULT if necessary. */
3346 if (mips_abi
== ABI_32
)
3347 target_flags
&= ~ (MASK_FLOAT64
|MASK_64BIT
);
3349 /* ??? This doesn't work yet, so don't let people try to use it. */
3350 if (mips_abi
== ABI_32
)
3351 error ("The -mabi=32 support does not work yet.");
3353 if (mips_abi_string
)
3354 error ("This target does not support the -mabi switch.");
3357 #ifdef MIPS_CPU_STRING_DEFAULT
3358 /* ??? There is a minor inconsistency here. If the user specifies an ISA
3359 greater than that supported by the default processor, then the user gets
3360 an error. Normally, the compiler will just default to the base level cpu
3361 for the indicated isa. */
3362 if (mips_cpu_string
== (char *)0)
3363 mips_cpu_string
= MIPS_CPU_STRING_DEFAULT
;
3366 /* Identify the processor type */
3367 if (mips_cpu_string
== (char *)0
3368 || !strcmp (mips_cpu_string
, "default")
3369 || !strcmp (mips_cpu_string
, "DEFAULT"))
3374 mips_cpu_string
= "3000";
3375 mips_cpu
= PROCESSOR_R3000
;
3378 mips_cpu_string
= "6000";
3379 mips_cpu
= PROCESSOR_R6000
;
3382 mips_cpu_string
= "4000";
3383 mips_cpu
= PROCESSOR_R4000
;
3386 mips_cpu_string
= "8000";
3387 mips_cpu
= PROCESSOR_R8000
;
3394 char *p
= mips_cpu_string
;
3397 /* We need to cope with the various "vr" prefixes for the NEC 4300
3398 and 4100 processors. */
3399 if (*p
== 'v' || *p
== 'V')
3404 if (*p
== 'r' || *p
== 'R')
3407 /* Since there is no difference between a R2000 and R3000 in
3408 terms of the scheduler, we collapse them into just an R3000. */
3410 mips_cpu
= PROCESSOR_DEFAULT
;
3414 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
3415 mips_cpu
= PROCESSOR_R3000
;
3419 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
3420 mips_cpu
= PROCESSOR_R3000
;
3424 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
3425 mips_cpu
= PROCESSOR_R4000
;
3426 /* The vr4100 is a non-FP ISA III processor with some extra
3428 else if (!strcmp (p
, "4100")) {
3429 mips_cpu
= PROCESSOR_R4100
;
3430 target_flags
|= MASK_SOFT_FLOAT
;
3432 /* The vr4300 is a standard ISA III processor, but with a different
3434 else if (!strcmp (p
, "4300"))
3435 mips_cpu
= PROCESSOR_R4300
;
3436 /* The r4400 is exactly the same as the r4000 from the compiler's
3438 else if (!strcmp (p
, "4400"))
3439 mips_cpu
= PROCESSOR_R4000
;
3440 else if (!strcmp (p
, "4600"))
3441 mips_cpu
= PROCESSOR_R4600
;
3442 else if (!strcmp (p
, "4650"))
3443 mips_cpu
= PROCESSOR_R4650
;
3447 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
3448 mips_cpu
= PROCESSOR_R6000
;
3452 if (!strcmp (p
, "8000"))
3453 mips_cpu
= PROCESSOR_R8000
;
3457 if (!strcmp (p
, "orion"))
3458 mips_cpu
= PROCESSOR_R4600
;
3462 if (seen_v
&& mips_cpu
!= PROCESSOR_R4300
&& mips_cpu
!= PROCESSOR_R4100
)
3463 mips_cpu
= PROCESSOR_DEFAULT
;
3465 if (mips_cpu
== PROCESSOR_DEFAULT
)
3467 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
3468 mips_cpu_string
= "default";
3472 if ((mips_cpu
== PROCESSOR_R3000
&& mips_isa
> 1)
3473 || (mips_cpu
== PROCESSOR_R6000
&& mips_isa
> 2)
3474 || ((mips_cpu
== PROCESSOR_R4000
3475 || mips_cpu
== PROCESSOR_R4100
3476 || mips_cpu
== PROCESSOR_R4300
3477 || mips_cpu
== PROCESSOR_R4600
3478 || mips_cpu
== PROCESSOR_R4650
)
3480 error ("-mcpu=%s does not support -mips%d", mips_cpu_string
, mips_isa
);
3482 /* make sure sizes of ints/longs/etc. are ok */
3486 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3488 else if (TARGET_LONG64
)
3489 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3491 else if (TARGET_FLOAT64
)
3492 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3494 else if (TARGET_64BIT
)
3495 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3498 if (mips_abi
!= ABI_32
)
3499 flag_pcc_struct_return
= 0;
3501 /* Tell halfpic.c that we have half-pic code if we do. */
3502 if (TARGET_HALF_PIC
)
3505 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3506 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3507 /* ??? -non_shared turns off pic code generation, but this is not
3509 if (TARGET_ABICALLS
)
3511 mips_abicalls
= MIPS_ABICALLS_YES
;
3513 if (mips_section_threshold
> 0)
3514 warning ("-G is incompatible with PIC code which is the default");
3517 mips_abicalls
= MIPS_ABICALLS_NO
;
3519 /* -membedded-pic is a form of PIC code suitable for embedded
3520 systems. All calls are made using PC relative addressing, and
3521 all data is addressed using the $gp register. This requires gas,
3522 which does most of the work, and GNU ld, which automatically
3523 expands PC relative calls which are out of range into a longer
3524 instruction sequence. All gcc really does differently is
3525 generate a different sequence for a switch. */
3526 if (TARGET_EMBEDDED_PIC
)
3529 if (TARGET_ABICALLS
)
3530 warning ("-membedded-pic and -mabicalls are incompatible");
3532 warning ("-G and -membedded-pic are incompatible");
3533 /* Setting mips_section_threshold is not required, because gas
3534 will force everything to be GP addressable anyhow, but
3535 setting it will cause gcc to make better estimates of the
3536 number of instructions required to access a particular data
3538 mips_section_threshold
= 0x7fffffff;
3541 /* ??? This does not work when target addresses are DImode.
3542 This is because we are missing DImode high/lo_sum patterns. */
3544 if (TARGET_GAS
&& optimize
&& ! flag_pic
&& Pmode
== SImode
)
3545 mips_split_addresses
= 1;
3547 mips_split_addresses
= 0;
3549 /* -mrnames says to use the MIPS software convention for register
3550 names instead of the hardware names (ie, $a0 instead of $4).
3551 We do this by switching the names in mips_reg_names, which the
3552 reg_names points into via the REGISTER_NAMES macro. */
3554 if (TARGET_NAME_REGS
)
3555 bcopy ((char *) mips_sw_reg_names
, (char *) mips_reg_names
, sizeof (mips_reg_names
));
3557 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3558 is currently being compiled. */
3560 if (getenv ("GCC_SIGINFO") != (char *)0)
3562 struct sigaction action
;
3563 action
.sa_handler
= siginfo
;
3565 action
.sa_flags
= SA_RESTART
;
3566 sigaction (SIGINFO
, &action
, (struct sigaction
*)0);
3571 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3572 /* If -mstats and -quiet, make stderr line buffered. */
3573 if (quiet_flag
&& TARGET_STATS
)
3574 setvbuf (stderr
, (char *)0, _IOLBF
, BUFSIZ
);
3578 /* Initialize the high and low values for legitimate floating point
3579 constants. Rather than trying to get the accuracy down to the
3580 last bit, just use approximate ranges. */
3581 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
3582 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
3583 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
3584 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
3586 mips_print_operand_punct
['?'] = TRUE
;
3587 mips_print_operand_punct
['#'] = TRUE
;
3588 mips_print_operand_punct
['&'] = TRUE
;
3589 mips_print_operand_punct
['!'] = TRUE
;
3590 mips_print_operand_punct
['*'] = TRUE
;
3591 mips_print_operand_punct
['@'] = TRUE
;
3592 mips_print_operand_punct
['.'] = TRUE
;
3593 mips_print_operand_punct
['('] = TRUE
;
3594 mips_print_operand_punct
[')'] = TRUE
;
3595 mips_print_operand_punct
['['] = TRUE
;
3596 mips_print_operand_punct
[']'] = TRUE
;
3597 mips_print_operand_punct
['<'] = TRUE
;
3598 mips_print_operand_punct
['>'] = TRUE
;
3599 mips_print_operand_punct
['{'] = TRUE
;
3600 mips_print_operand_punct
['}'] = TRUE
;
3601 mips_print_operand_punct
['^'] = TRUE
;
3603 mips_char_to_class
['d'] = GR_REGS
;
3604 mips_char_to_class
['f'] = ((TARGET_HARD_FLOAT
) ? FP_REGS
: NO_REGS
);
3605 mips_char_to_class
['h'] = HI_REG
;
3606 mips_char_to_class
['l'] = LO_REG
;
3607 mips_char_to_class
['a'] = HILO_REG
;
3608 mips_char_to_class
['x'] = MD_REGS
;
3609 mips_char_to_class
['b'] = ALL_REGS
;
3610 mips_char_to_class
['y'] = GR_REGS
;
3611 mips_char_to_class
['z'] = ST_REGS
;
3613 /* Set up array to map GCC register number to debug register number.
3614 Ignore the special purpose register numbers. */
3616 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3617 mips_dbx_regno
[i
] = -1;
3619 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
3620 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
3621 mips_dbx_regno
[i
] = i
+ start
;
3623 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
3624 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
3625 mips_dbx_regno
[i
] = i
+ start
;
3627 /* Set up array giving whether a given register can hold a given mode.
3628 At present, restrict ints from being in FP registers, because reload
3629 is a little enthusiastic about storing extra values in FP registers,
3630 and this is not good for things like OS kernels. Also, due to the
3631 mandatory delay, it is as fast to load from cached memory as to move
3632 from the FP register. */
3634 for (mode
= VOIDmode
;
3635 mode
!= MAX_MACHINE_MODE
;
3636 mode
= (enum machine_mode
)((int)mode
+ 1))
3638 register int size
= GET_MODE_SIZE (mode
);
3639 register enum mode_class
class = GET_MODE_CLASS (mode
);
3641 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3645 if (mode
== CC_FPmode
|| mode
== CC_REV_FPmode
)
3646 temp
= (regno
== FPSW_REGNUM
);
3648 else if (GP_REG_P (regno
))
3649 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
3651 else if (FP_REG_P (regno
))
3652 temp
= ((TARGET_FLOAT64
|| ((regno
& 1) == 0))
3653 && (class == MODE_FLOAT
3654 || class == MODE_COMPLEX_FLOAT
3655 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
3656 && (! TARGET_SINGLE_FLOAT
|| size
<= 4));
3658 else if (MD_REG_P (regno
))
3659 temp
= (class == MODE_INT
3660 && (size
<= UNITS_PER_WORD
3661 || (regno
== MD_REG_FIRST
&& size
== 2 * UNITS_PER_WORD
)));
3666 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
3673 * The MIPS debug format wants all automatic variables and arguments
3674 * to be in terms of the virtual frame pointer (stack pointer before
3675 * any adjustment in the function), while the MIPS 3.0 linker wants
3676 * the frame pointer to be the stack pointer after the initial
3677 * adjustment. So, we do the adjustment here. The arg pointer (which
3678 * is eliminated) points to the virtual frame pointer, while the frame
3679 * pointer (which may be eliminated) points to the stack pointer after
3680 * the initial adjustments.
3684 mips_debugger_offset (addr
, offset
)
3688 rtx offset2
= const0_rtx
;
3689 rtx reg
= eliminate_constant_term (addr
, &offset2
);
3692 offset
= INTVAL (offset2
);
3694 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
)
3696 int frame_size
= (!current_frame_info
.initialized
)
3697 ? compute_frame_size (get_frame_size ())
3698 : current_frame_info
.total_size
;
3700 offset
= offset
- frame_size
;
3702 /* sdbout_parms does not want this to crash for unrecognized cases. */
3704 else if (reg
!= arg_pointer_rtx
)
3705 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer.");
3712 /* A C compound statement to output to stdio stream STREAM the
3713 assembler syntax for an instruction operand X. X is an RTL
3716 CODE is a value that can be used to specify one of several ways
3717 of printing the operand. It is used when identical operands
3718 must be printed differently depending on the context. CODE
3719 comes from the `%' specification that was used to request
3720 printing of the operand. If the specification was just `%DIGIT'
3721 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3722 is the ASCII code for LTR.
3724 If X is a register, this macro should print the register's name.
3725 The names can be found in an array `reg_names' whose type is
3726 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3728 When the machine description has a specification `%PUNCT' (a `%'
3729 followed by a punctuation character), this macro is called with
3730 a null pointer for X and the punctuation character for CODE.
3732 The MIPS specific codes are:
3734 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3735 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3736 'd' output integer constant in decimal,
3737 'z' if the operand is 0, use $0 instead of normal operand.
3738 'D' print second register of double-word register operand.
3739 'L' print low-order register of double-word register operand.
3740 'M' print high-order register of double-word register operand.
3741 'C' print part of opcode for a branch condition.
3742 'N' print part of opcode for a branch condition, inverted.
3743 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3744 'B' print 'z' for EQ, 'n' for NE
3745 'b' print 'n' for EQ, 'z' for NE
3746 'T' print 'f' for EQ, 't' for NE
3747 't' print 't' for EQ, 'f' for NE
3748 '(' Turn on .set noreorder
3749 ')' Turn on .set reorder
3750 '[' Turn on .set noat
3752 '<' Turn on .set nomacro
3753 '>' Turn on .set macro
3754 '{' Turn on .set volatile (not GAS)
3755 '}' Turn on .set novolatile (not GAS)
3756 '&' Turn on .set noreorder if filling delay slots
3757 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3758 '!' Turn on .set nomacro if filling delay slots
3759 '#' Print nop if in a .set noreorder section.
3760 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3761 '@' Print the name of the assembler temporary register (at or $1).
3762 '.' Print the name of the register with a hard-wired zero (zero or $0).
3763 '^' Print the name of the pic call-through register (t9 or $25). */
3766 print_operand (file
, op
, letter
)
3767 FILE *file
; /* file to write to */
3768 rtx op
; /* operand to print */
3769 int letter
; /* %<letter> or 0 */
3771 register enum rtx_code code
;
3773 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
3778 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter
);
3782 if (mips_branch_likely
)
3787 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
3791 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
3795 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
3799 if (final_sequence
!= 0 && set_noreorder
++ == 0)
3800 fputs (".set\tnoreorder\n\t", file
);
3804 if (final_sequence
!= 0)
3806 if (set_noreorder
++ == 0)
3807 fputs (".set\tnoreorder\n\t", file
);
3809 if (set_nomacro
++ == 0)
3810 fputs (".set\tnomacro\n\t", file
);
3815 if (final_sequence
!= 0 && set_nomacro
++ == 0)
3816 fputs ("\n\t.set\tnomacro", file
);
3820 if (set_noreorder
!= 0)
3821 fputs ("\n\tnop", file
);
3823 else if (TARGET_STATS
)
3824 fputs ("\n\t#nop", file
);
3829 if (set_noreorder
++ == 0)
3830 fputs (".set\tnoreorder\n\t", file
);
3834 if (set_noreorder
== 0)
3835 error ("internal error: %%) found without a %%( in assembler pattern");
3837 else if (--set_noreorder
== 0)
3838 fputs ("\n\t.set\treorder", file
);
3843 if (set_noat
++ == 0)
3844 fputs (".set\tnoat\n\t", file
);
3849 error ("internal error: %%] found without a %%[ in assembler pattern");
3851 else if (--set_noat
== 0)
3852 fputs ("\n\t.set\tat", file
);
3857 if (set_nomacro
++ == 0)
3858 fputs (".set\tnomacro\n\t", file
);
3862 if (set_nomacro
== 0)
3863 error ("internal error: %%> found without a %%< in assembler pattern");
3865 else if (--set_nomacro
== 0)
3866 fputs ("\n\t.set\tmacro", file
);
3871 if (set_volatile
++ == 0)
3872 fprintf (file
, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS
) ? "" : "#");
3876 if (set_volatile
== 0)
3877 error ("internal error: %%} found without a %%{ in assembler pattern");
3879 else if (--set_volatile
== 0)
3880 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
3889 error ("PRINT_OPERAND null pointer");
3893 code
= GET_CODE (op
);
3897 case EQ
: fputs ("eq", file
); break;
3898 case NE
: fputs ("ne", file
); break;
3899 case GT
: fputs ("gt", file
); break;
3900 case GE
: fputs ("ge", file
); break;
3901 case LT
: fputs ("lt", file
); break;
3902 case LE
: fputs ("le", file
); break;
3903 case GTU
: fputs ("gtu", file
); break;
3904 case GEU
: fputs ("geu", file
); break;
3905 case LTU
: fputs ("ltu", file
); break;
3906 case LEU
: fputs ("leu", file
); break;
3909 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
3912 else if (letter
== 'N')
3915 case EQ
: fputs ("ne", file
); break;
3916 case NE
: fputs ("eq", file
); break;
3917 case GT
: fputs ("le", file
); break;
3918 case GE
: fputs ("lt", file
); break;
3919 case LT
: fputs ("ge", file
); break;
3920 case LE
: fputs ("gt", file
); break;
3921 case GTU
: fputs ("leu", file
); break;
3922 case GEU
: fputs ("ltu", file
); break;
3923 case LTU
: fputs ("geu", file
); break;
3924 case LEU
: fputs ("gtu", file
); break;
3927 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
3930 else if (letter
== 'S')
3934 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
3935 assemble_name (file
, buffer
);
3938 else if (code
== REG
)
3940 register int regnum
= REGNO (op
);
3942 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
3943 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
3947 fprintf (file
, "%s", reg_names
[regnum
]);
3950 else if (code
== MEM
)
3951 output_address (XEXP (op
, 0));
3953 else if (code
== CONST_DOUBLE
3954 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
3959 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
3960 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
3964 else if ((letter
== 'x') && (GET_CODE(op
) == CONST_INT
))
3965 fprintf (file
, "0x%04x", 0xffff & (INTVAL(op
)));
3967 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
3968 && HOST_BITS_PER_WIDE_INT
== 32)
3969 fprintf (file
, "0x%08x", INTVAL(op
));
3971 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
3972 && HOST_BITS_PER_WIDE_INT
== 64)
3973 fprintf (file
, "0x%016lx", INTVAL(op
));
3975 else if ((letter
== 'd') && (GET_CODE(op
) == CONST_INT
))
3976 fprintf (file
, "%d", (INTVAL(op
)));
3978 else if (letter
== 'z'
3979 && (GET_CODE (op
) == CONST_INT
)
3980 && INTVAL (op
) == 0)
3981 fputs (reg_names
[GP_REG_FIRST
], file
);
3983 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
3984 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter
);
3986 else if (letter
== 'B')
3987 fputs (code
== EQ
? "z" : "n", file
);
3988 else if (letter
== 'b')
3989 fputs (code
== EQ
? "n" : "z", file
);
3990 else if (letter
== 'T')
3991 fputs (code
== EQ
? "f" : "t", file
);
3992 else if (letter
== 't')
3993 fputs (code
== EQ
? "t" : "f", file
);
3996 output_addr_const (file
, op
);
4000 /* A C compound statement to output to stdio stream STREAM the
4001 assembler syntax for an instruction operand that is a memory
4002 reference whose address is ADDR. ADDR is an RTL expression.
4004 On some machines, the syntax for a symbolic address depends on
4005 the section that the address refers to. On these machines,
4006 define the macro `ENCODE_SECTION_INFO' to store the information
4007 into the `symbol_ref', and then check for it here. */
4010 print_operand_address (file
, addr
)
4015 error ("PRINT_OPERAND_ADDRESS, null pointer");
4018 switch (GET_CODE (addr
))
4021 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
4025 if (REGNO (addr
) == ARG_POINTER_REGNUM
)
4026 abort_with_insn (addr
, "Arg pointer not eliminated.");
4028 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
4033 register rtx arg0
= XEXP (addr
, 0);
4034 register rtx arg1
= XEXP (addr
, 1);
4036 if (! mips_split_addresses
)
4037 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4039 if (GET_CODE (arg0
) != REG
)
4040 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4042 fprintf (file
, "%%lo(");
4043 print_operand_address (file
, arg1
);
4044 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
4050 register rtx reg
= (rtx
)0;
4051 register rtx offset
= (rtx
)0;
4052 register rtx arg0
= XEXP (addr
, 0);
4053 register rtx arg1
= XEXP (addr
, 1);
4055 if (GET_CODE (arg0
) == REG
)
4059 if (GET_CODE (offset
) == REG
)
4060 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
4062 else if (GET_CODE (arg1
) == REG
)
4067 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
4069 output_addr_const (file
, addr
);
4073 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
4075 if (!CONSTANT_P (offset
))
4076 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4078 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
4079 abort_with_insn (addr
, "Arg pointer not eliminated.");
4081 output_addr_const (file
, offset
);
4082 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
4090 output_addr_const (file
, addr
);
4096 /* If optimizing for the global pointer, keep track of all of
4097 the externs, so that at the end of the file, we can emit
4098 the appropriate .extern declaration for them, before writing
4099 out the text section. We assume that all names passed to
4100 us are in the permanent obstack, so that they will be valid
4101 at the end of the compilation.
4103 If we have -G 0, or the extern size is unknown, don't bother
4104 emitting the .externs. */
4107 mips_output_external (file
, decl
, name
)
4112 register struct extern_list
*p
;
4116 && ((TREE_CODE (decl
)) != FUNCTION_DECL
)
4117 && ((len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0))
4119 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4120 p
->next
= extern_head
;
4126 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4127 if (TREE_CODE (decl
) == FUNCTION_DECL
4128 /* ??? Don't include alloca, since gcc will always expand it
4129 inline. If we don't do this, libg++ fails to build. */
4130 && strcmp (name
, "alloca")
4131 /* ??? Don't include __builtin_next_arg, because then gcc will not
4132 bootstrap under Irix 5.1. */
4133 && strcmp (name
, "__builtin_next_arg"))
4135 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4136 p
->next
= extern_head
;
4146 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4148 mips_output_external_libcall (file
, name
)
4152 register struct extern_list
*p
;
4154 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4155 p
->next
= extern_head
;
4165 /* Compute a string to use as a temporary file name. */
4167 /* On MSDOS, write temp files in current dir
4168 because there's no place else we can expect to use. */
4171 #define P_tmpdir "./"
4179 char *base
= getenv ("TMPDIR");
4182 if (base
== (char *)0)
4185 if (access (P_tmpdir
, R_OK
| W_OK
) == 0)
4189 if (access ("/usr/tmp", R_OK
| W_OK
) == 0)
4195 len
= strlen (base
);
4196 /* temp_filename is global, so we must use malloc, not alloca. */
4197 temp_filename
= (char *) xmalloc (len
+ sizeof("/ctXXXXXX"));
4198 strcpy (temp_filename
, base
);
4199 if (len
> 0 && temp_filename
[len
-1] != '/')
4200 temp_filename
[len
++] = '/';
4202 strcpy (temp_filename
+ len
, "ctXXXXXX");
4203 mktemp (temp_filename
);
4205 stream
= fopen (temp_filename
, "w+");
4207 pfatal_with_name (temp_filename
);
4210 /* In MSDOS, we cannot unlink the temporary file until we are finished using
4211 it. Otherwise, we delete it now, so that it will be gone even if the
4212 compiler happens to crash. */
4213 unlink (temp_filename
);
4219 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
4220 for .file's that start within a function. If we are smuggling stabs, try to
4221 put out a MIPS ECOFF file and a stab. */
4224 mips_output_filename (stream
, name
)
4228 static int first_time
= TRUE
;
4229 char ltext_label_name
[100];
4235 current_function_file
= name
;
4236 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4237 /* This tells mips-tfile that stabs will follow. */
4238 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
4239 fprintf (stream
, "\t#@stabs\n");
4242 else if (write_symbols
== DBX_DEBUG
)
4244 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
4245 fprintf (stream
, "%s ", ASM_STABS_OP
);
4246 output_quoted_string (stream
, name
);
4247 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
4250 else if (name
!= current_function_file
4251 && strcmp (name
, current_function_file
) != 0)
4253 if (inside_function
&& !TARGET_GAS
)
4255 if (!file_in_function_warning
)
4257 file_in_function_warning
= TRUE
;
4258 ignore_line_number
= TRUE
;
4259 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
4265 current_function_file
= name
;
4266 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4272 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4273 as well as a .loc, since it is possible that MIPS ECOFF might not be
4274 able to represent the location for inlines that come from a different
4278 mips_output_lineno (stream
, line
)
4282 if (write_symbols
== DBX_DEBUG
)
4285 fprintf (stream
, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
4286 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
4287 LOCAL_LABEL_PREFIX
, sym_lineno
);
4292 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
4293 (ignore_line_number
) ? "#" : "",
4294 num_source_filenames
, line
);
4296 LABEL_AFTER_LOC (stream
);
4301 /* If defined, a C statement to be executed just prior to the
4302 output of assembler code for INSN, to modify the extracted
4303 operands so they will be output differently.
4305 Here the argument OPVEC is the vector containing the operands
4306 extracted from INSN, and NOPERANDS is the number of elements of
4307 the vector which contain meaningful data for this insn. The
4308 contents of this vector are what will be used to convert the
4309 insn template into assembler code, so you can change the
4310 assembler output by changing the contents of the vector.
4312 We use it to check if the current insn needs a nop in front of it
4313 because of load delays, and also to update the delay slot
4316 /* ??? There is no real need for this function, because it never actually
4317 emits a NOP anymore. */
4320 final_prescan_insn (insn
, opvec
, noperands
)
4325 if (dslots_number_nops
> 0)
4327 rtx pattern
= PATTERN (insn
);
4328 int length
= get_attr_length (insn
);
4330 /* Do we need to emit a NOP? */
4332 || (mips_load_reg
!= (rtx
)0 && reg_mentioned_p (mips_load_reg
, pattern
))
4333 || (mips_load_reg2
!= (rtx
)0 && reg_mentioned_p (mips_load_reg2
, pattern
))
4334 || (mips_load_reg3
!= (rtx
)0 && reg_mentioned_p (mips_load_reg3
, pattern
))
4335 || (mips_load_reg4
!= (rtx
)0 && reg_mentioned_p (mips_load_reg4
, pattern
)))
4336 fputs ("\t#nop\n", asm_out_file
);
4339 dslots_load_filled
++;
4341 while (--dslots_number_nops
> 0)
4342 fputs ("\t#nop\n", asm_out_file
);
4344 mips_load_reg
= (rtx
)0;
4345 mips_load_reg2
= (rtx
)0;
4346 mips_load_reg3
= (rtx
)0;
4347 mips_load_reg4
= (rtx
)0;
4352 enum rtx_code code
= GET_CODE (insn
);
4353 if (code
== JUMP_INSN
|| code
== CALL_INSN
)
4354 dslots_jump_total
++;
4359 /* Output at beginning of assembler file.
4360 If we are optimizing to use the global pointer, create a temporary
4361 file to hold all of the text stuff, and write it out to the end.
4362 This is needed because the MIPS assembler is evidently one pass,
4363 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4364 declaration when the code is processed, it generates a two
4365 instruction sequence. */
4368 mips_asm_file_start (stream
)
4371 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
4373 /* Versions of the MIPS assembler before 2.20 generate errors
4374 if a branch inside of a .set noreorder section jumps to a
4375 label outside of the .set noreorder section. Revision 2.20
4376 just set nobopt silently rather than fixing the bug. */
4378 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
4379 fprintf (stream
, "\t.set\tnobopt\n");
4381 /* Generate the pseudo ops that System V.4 wants. */
4382 #ifndef ABICALLS_ASM_OP
4383 #define ABICALLS_ASM_OP ".abicalls"
4385 if (TARGET_ABICALLS
)
4386 /* ??? but do not want this (or want pic0) if -non-shared? */
4387 fprintf (stream
, "\t%s\n", ABICALLS_ASM_OP
);
4389 /* Start a section, so that the first .popsection directive is guaranteed
4390 to have a previously defined section to pop back to. */
4391 if (mips_abi
!= ABI_32
)
4392 fprintf (stream
, "\t.section\t.text\n");
4394 /* This code exists so that we can put all externs before all symbol
4395 references. This is necessary for the assembler's global pointer
4396 optimizations to work. */
4397 /* ??? Current versions of gas do not require that externs occur before
4398 symbol references. This means that this code is unnecessary when
4399 gas is being used. This gas feature hasn't been well tested as yet
4403 asm_out_data_file
= stream
;
4404 asm_out_text_file
= make_temp_file ();
4407 asm_out_data_file
= asm_out_text_file
= stream
;
4409 if (flag_verbose_asm
)
4410 fprintf (stream
, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
4412 mips_section_threshold
, mips_cpu_string
, mips_isa
);
4416 /* If we are optimizing the global pointer, emit the text section now
4417 and any small externs which did not have .comm, etc that are
4418 needed. Also, give a warning if the data area is more than 32K and
4419 -pic because 3 instructions are needed to reference the data
4423 mips_asm_file_end (file
)
4428 struct extern_list
*p
;
4432 HALF_PIC_FINISH (file
);
4438 for (p
= extern_head
; p
!= 0; p
= p
->next
)
4440 name_tree
= get_identifier (p
->name
);
4442 /* Positively ensure only one .extern for any given symbol. */
4443 if (! TREE_ASM_WRITTEN (name_tree
))
4445 TREE_ASM_WRITTEN (name_tree
) = 1;
4446 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4448 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
4452 fputs ("\t.extern\t", file
);
4453 assemble_name (file
, p
->name
);
4454 fprintf (file
, ", %d\n", p
->size
);
4462 fprintf (file
, "\n\t.text\n");
4463 rewind (asm_out_text_file
);
4464 if (ferror (asm_out_text_file
))
4465 fatal_io_error (temp_filename
);
4467 while ((len
= fread (buffer
, 1, sizeof (buffer
), asm_out_text_file
)) > 0)
4468 if (fwrite (buffer
, 1, len
, file
) != len
)
4469 pfatal_with_name (asm_file_name
);
4472 pfatal_with_name (temp_filename
);
4474 if (fclose (asm_out_text_file
) != 0)
4475 pfatal_with_name (temp_filename
);
4478 unlink (temp_filename
);
4484 /* Emit either a label, .comm, or .lcomm directive, and mark
4485 that the symbol is used, so that we don't emit an .extern
4486 for it in mips_asm_file_end. */
4489 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
4496 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
4497 assemble_name (stream
, name
);
4498 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
4502 tree name_tree
= get_identifier (name
);
4503 TREE_ASM_WRITTEN (name_tree
) = 1;
4508 /* Output a double precision value to the assembler. If both the
4509 host and target are IEEE, emit the values in hex. */
4512 mips_output_double (stream
, value
)
4514 REAL_VALUE_TYPE value
;
4516 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4518 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
4520 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4521 value_long
[0], value
, value_long
[1]);
4523 fprintf (stream
, "\t.double\t%.20g\n", value
);
4528 /* Output a single precision value to the assembler. If both the
4529 host and target are IEEE, emit the values in hex. */
4532 mips_output_float (stream
, value
)
4534 REAL_VALUE_TYPE value
;
4536 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4538 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
4540 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
4542 fprintf (stream
, "\t.float\t%.12g\n", value
);
4547 /* Return TRUE if any register used in the epilogue is used. This to insure
4548 any insn put into the epilogue delay slots is safe. */
4551 epilogue_reg_mentioned_p (insn
)
4556 register enum rtx_code code
;
4562 if (GET_CODE (insn
) == LABEL_REF
)
4565 code
= GET_CODE (insn
);
4569 regno
= REGNO (insn
);
4570 if (regno
== STACK_POINTER_REGNUM
)
4573 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4576 if (!call_used_regs
[regno
])
4579 if (regno
!= MIPS_TEMP1_REGNUM
&& regno
!= MIPS_TEMP2_REGNUM
)
4582 if (!current_frame_info
.initialized
)
4583 compute_frame_size (get_frame_size ());
4585 return (current_frame_info
.total_size
>= 32768);
4595 fmt
= GET_RTX_FORMAT (code
);
4596 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4601 for (j
= XVECLEN (insn
, i
) - 1; j
>= 0; j
--)
4602 if (epilogue_reg_mentioned_p (XVECEXP (insn
, i
, j
)))
4605 else if (fmt
[i
] == 'e' && epilogue_reg_mentioned_p (XEXP (insn
, i
)))
4612 /* Return the bytes needed to compute the frame pointer from the current
4615 Mips stack frames look like:
4617 Before call After call
4618 +-----------------------+ +-----------------------+
4621 | caller's temps. | | caller's temps. |
4623 +-----------------------+ +-----------------------+
4625 | arguments on stack. | | arguments on stack. |
4627 +-----------------------+ +-----------------------+
4628 | 4 words to save | | 4 words to save |
4629 | arguments passed | | arguments passed |
4630 | in registers, even | | in registers, even |
4631 SP->| if not passed. | VFP->| if not passed. |
4632 +-----------------------+ +-----------------------+
4634 | fp register save |
4636 +-----------------------+
4638 | gp register save |
4640 +-----------------------+
4644 +-----------------------+
4646 | alloca allocations |
4648 +-----------------------+
4650 | GP save for V.4 abi |
4652 +-----------------------+
4654 | arguments on stack |
4656 +-----------------------+
4658 | arguments passed |
4659 | in registers, even |
4660 low SP->| if not passed. |
4661 memory +-----------------------+
4666 compute_frame_size (size
)
4667 int size
; /* # of var. bytes allocated */
4670 long total_size
; /* # bytes that the entire frame takes up */
4671 long var_size
; /* # bytes that variables take up */
4672 long args_size
; /* # bytes that outgoing arguments take up */
4673 long extra_size
; /* # extra bytes */
4674 long gp_reg_rounded
; /* # bytes needed to store gp after rounding */
4675 long gp_reg_size
; /* # bytes needed to store gp regs */
4676 long fp_reg_size
; /* # bytes needed to store fp regs */
4677 long mask
; /* mask of saved gp registers */
4678 long fmask
; /* mask of saved fp registers */
4679 int fp_inc
; /* 1 or 2 depending on the size of fp regs */
4680 long fp_bits
; /* bitmask to use for each fp register */
4686 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
4687 var_size
= MIPS_STACK_ALIGN (size
);
4688 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
4690 /* The MIPS 3.0 linker does not like functions that dynamically
4691 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4692 looks like we are trying to create a second frame pointer to the
4693 function, so allocate some stack space to make it happy. */
4695 if (args_size
== 0 && current_function_calls_alloca
)
4696 args_size
= 4*UNITS_PER_WORD
;
4698 total_size
= var_size
+ args_size
+ extra_size
;
4700 /* Calculate space needed for gp registers. */
4701 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4703 if (MUST_SAVE_REGISTER (regno
))
4705 gp_reg_size
+= UNITS_PER_WORD
;
4706 mask
|= 1L << (regno
- GP_REG_FIRST
);
4710 /* Calculate space needed for fp registers. */
4711 if (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
)
4722 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= fp_inc
)
4724 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
4726 fp_reg_size
+= fp_inc
* UNITS_PER_FPREG
;
4727 fmask
|= fp_bits
<< (regno
- FP_REG_FIRST
);
4731 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4732 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
4734 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4735 for leaf routines (total_size == extra_size) to save the gp reg.
4736 The gp reg is callee saved in the 64 bit ABI, so all routines must
4738 if (total_size
== extra_size
&& mips_abi
== ABI_32
)
4739 total_size
= extra_size
= 0;
4740 else if (TARGET_ABICALLS
)
4742 /* Add the context-pointer to the saved registers. */
4743 gp_reg_size
+= UNITS_PER_WORD
;
4744 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
4745 total_size
-= gp_reg_rounded
;
4746 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4747 total_size
+= gp_reg_rounded
;
4750 /* Add in space reserved on the stack by the callee for storing arguments
4751 passed in registers. */
4752 if (mips_abi
!= ABI_32
)
4753 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
4755 /* Save other computed information. */
4756 current_frame_info
.total_size
= total_size
;
4757 current_frame_info
.var_size
= var_size
;
4758 current_frame_info
.args_size
= args_size
;
4759 current_frame_info
.extra_size
= extra_size
;
4760 current_frame_info
.gp_reg_size
= gp_reg_size
;
4761 current_frame_info
.fp_reg_size
= fp_reg_size
;
4762 current_frame_info
.mask
= mask
;
4763 current_frame_info
.fmask
= fmask
;
4764 current_frame_info
.initialized
= reload_completed
;
4765 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
4766 current_frame_info
.num_fp
= fp_reg_size
/ (fp_inc
* UNITS_PER_FPREG
);
4770 unsigned long offset
= (args_size
+ extra_size
+ var_size
4771 + gp_reg_size
- UNITS_PER_WORD
);
4772 current_frame_info
.gp_sp_offset
= offset
;
4773 current_frame_info
.gp_save_offset
= offset
- total_size
;
4777 current_frame_info
.gp_sp_offset
= 0;
4778 current_frame_info
.gp_save_offset
= 0;
4784 unsigned long offset
= (args_size
+ extra_size
+ var_size
4785 + gp_reg_rounded
+ fp_reg_size
4786 - fp_inc
* UNITS_PER_FPREG
);
4787 current_frame_info
.fp_sp_offset
= offset
;
4788 current_frame_info
.fp_save_offset
= offset
- total_size
+ UNITS_PER_WORD
;
4792 current_frame_info
.fp_sp_offset
= 0;
4793 current_frame_info
.fp_save_offset
= 0;
4796 /* Ok, we're done. */
4801 /* Common code to emit the insns (or to write the instructions to a file)
4802 to save/restore registers.
4804 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4805 is not modified within save_restore_insns. */
4807 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4810 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
4811 int store_p
; /* true if this is prologue */
4812 rtx large_reg
; /* register holding large offset constant or NULL */
4813 long large_offset
; /* large constant offset value */
4814 FILE *file
; /* file to write instructions to instead of making RTL */
4816 long mask
= current_frame_info
.mask
;
4817 long fmask
= current_frame_info
.fmask
;
4825 if (frame_pointer_needed
&& !BITSET_P (mask
, FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
4828 if (mask
== 0 && fmask
== 0)
4831 /* Save registers starting from high to low. The debuggers prefer
4832 at least the return register be stored at func+4, and also it
4833 allows us not to need a nop in the epilog if at least one
4834 register is reloaded in addition to return address. */
4836 /* Save GP registers if needed. */
4839 /* Pick which pointer to use as a base register. For small
4840 frames, just use the stack pointer. Otherwise, use a
4841 temporary register. Save 2 cycles if the save area is near
4842 the end of a large frame, by reusing the constant created in
4843 the prologue/epilogue to adjust the stack frame. */
4845 gp_offset
= current_frame_info
.gp_sp_offset
;
4846 end_offset
= gp_offset
- (current_frame_info
.gp_reg_size
- UNITS_PER_WORD
);
4848 if (gp_offset
< 0 || end_offset
< 0)
4849 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
4850 gp_offset
, end_offset
);
4852 else if (gp_offset
< 32768)
4854 base_reg_rtx
= stack_pointer_rtx
;
4858 else if (large_reg
!= (rtx
)0
4859 && (((unsigned long)(large_offset
- gp_offset
)) < 32768)
4860 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
4862 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4863 base_offset
= large_offset
;
4864 if (file
== (FILE *)0)
4867 emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4869 emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4872 fprintf (file
, "\t%s\t%s,%s,%s\n",
4873 TARGET_LONG64
? "daddu" : "addu",
4874 reg_names
[MIPS_TEMP2_REGNUM
],
4875 reg_names
[REGNO (large_reg
)],
4876 reg_names
[STACK_POINTER_REGNUM
]);
4881 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4882 base_offset
= gp_offset
;
4883 if (file
== (FILE *)0)
4885 emit_move_insn (base_reg_rtx
, GEN_INT (gp_offset
));
4887 emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
4889 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
4892 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
4893 reg_names
[MIPS_TEMP2_REGNUM
],
4896 TARGET_LONG64
? "daddu" : "addu",
4897 reg_names
[MIPS_TEMP2_REGNUM
],
4898 reg_names
[MIPS_TEMP2_REGNUM
],
4899 reg_names
[STACK_POINTER_REGNUM
]);
4902 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
4904 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
4906 if (file
== (FILE *)0)
4908 rtx reg_rtx
= gen_rtx (REG
, word_mode
, regno
);
4909 rtx mem_rtx
= gen_rtx (MEM
, word_mode
,
4910 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
4911 GEN_INT (gp_offset
- base_offset
)));
4914 emit_move_insn (mem_rtx
, reg_rtx
);
4915 else if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
4916 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
4917 emit_move_insn (reg_rtx
, mem_rtx
);
4921 if (store_p
|| !TARGET_ABICALLS
|| mips_abi
!= ABI_32
4922 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
4923 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
4925 ? (store_p
) ? "sd" : "ld"
4926 : (store_p
) ? "sw" : "lw"),
4928 gp_offset
- base_offset
,
4929 reg_names
[REGNO(base_reg_rtx
)]);
4932 gp_offset
-= UNITS_PER_WORD
;
4938 base_reg_rtx
= (rtx
)0; /* Make sure these are initialized */
4942 /* Save floating point registers if needed. */
4945 int fp_inc
= (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
) ? 1 : 2;
4946 int fp_size
= fp_inc
* UNITS_PER_FPREG
;
4948 /* Pick which pointer to use as a base register. */
4949 fp_offset
= current_frame_info
.fp_sp_offset
;
4950 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
- fp_size
);
4952 if (fp_offset
< 0 || end_offset
< 0)
4953 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
4954 fp_offset
, end_offset
);
4956 else if (fp_offset
< 32768)
4958 base_reg_rtx
= stack_pointer_rtx
;
4962 else if (base_reg_rtx
!= (rtx
)0
4963 && (((unsigned long)(base_offset
- fp_offset
)) < 32768)
4964 && (((unsigned long)(base_offset
- end_offset
)) < 32768))
4966 ; /* already set up for gp registers above */
4969 else if (large_reg
!= (rtx
)0
4970 && (((unsigned long)(large_offset
- fp_offset
)) < 32768)
4971 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
4973 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4974 base_offset
= large_offset
;
4975 if (file
== (FILE *)0)
4978 emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4980 emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4983 fprintf (file
, "\t%s\t%s,%s,%s\n",
4984 TARGET_LONG64
? "daddu" : "addu",
4985 reg_names
[MIPS_TEMP2_REGNUM
],
4986 reg_names
[REGNO (large_reg
)],
4987 reg_names
[STACK_POINTER_REGNUM
]);
4992 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4993 base_offset
= fp_offset
;
4994 if (file
== (FILE *)0)
4996 emit_move_insn (base_reg_rtx
, GEN_INT (fp_offset
));
4998 emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5000 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5003 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5004 reg_names
[MIPS_TEMP2_REGNUM
],
5007 TARGET_LONG64
? "daddu" : "addu",
5008 reg_names
[MIPS_TEMP2_REGNUM
],
5009 reg_names
[MIPS_TEMP2_REGNUM
],
5010 reg_names
[STACK_POINTER_REGNUM
]);
5013 for (regno
= FP_REG_LAST
-1; regno
>= FP_REG_FIRST
; regno
-= fp_inc
)
5015 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
5017 if (file
== (FILE *)0)
5019 enum machine_mode sz
=
5020 TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5021 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
5022 rtx mem_rtx
= gen_rtx (MEM
, sz
,
5023 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5024 GEN_INT (fp_offset
- base_offset
)));
5027 emit_move_insn (mem_rtx
, reg_rtx
);
5029 emit_move_insn (reg_rtx
, mem_rtx
);
5032 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5033 (TARGET_SINGLE_FLOAT
5034 ? ((store_p
) ? "s.s" : "l.s")
5035 : ((store_p
) ? "s.d" : "l.d")),
5037 fp_offset
- base_offset
,
5038 reg_names
[REGNO(base_reg_rtx
)]);
5041 fp_offset
-= fp_size
;
5048 /* Set up the stack and frame (if desired) for the function. */
5051 function_prologue (file
, size
)
5056 long tsize
= current_frame_info
.total_size
;
5058 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
5060 #ifdef SDB_DEBUGGING_INFO
5061 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
5062 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
5065 inside_function
= 1;
5067 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5068 /* Get the function name the same way that toplev.c does before calling
5069 assemble_start_function. This is needed so that the name used here
5070 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5071 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5073 fputs ("\t.ent\t", file
);
5074 assemble_name (file
, fnname
);
5077 assemble_name (file
, fnname
);
5078 fputs (":\n", file
);
5081 fprintf (file
, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5082 reg_names
[ (frame_pointer_needed
) ? FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
],
5084 reg_names
[31 + GP_REG_FIRST
],
5085 current_frame_info
.var_size
,
5086 current_frame_info
.num_gp
,
5087 current_frame_info
.num_fp
,
5088 current_function_outgoing_args_size
,
5089 current_frame_info
.extra_size
);
5091 fprintf (file
, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
5092 current_frame_info
.mask
,
5093 current_frame_info
.gp_save_offset
,
5094 current_frame_info
.fmask
,
5095 current_frame_info
.fp_save_offset
);
5097 if (TARGET_ABICALLS
&& mips_abi
== ABI_32
)
5099 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5101 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
5102 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
5105 fprintf (file
, "\t%s\t%s,%s,%d\n",
5106 (TARGET_LONG64
? "dsubu" : "subu"),
5107 sp_str
, sp_str
, tsize
);
5108 fprintf (file
, "\t.cprestore %d\n", current_frame_info
.args_size
);
5114 /* Expand the prologue into a bunch of separate insns. */
5117 mips_expand_prologue ()
5121 rtx tmp_rtx
= (rtx
)0;
5122 char *arg_name
= (char *)0;
5123 tree fndecl
= current_function_decl
;
5124 tree fntype
= TREE_TYPE (fndecl
);
5125 tree fnargs
= DECL_ARGUMENTS (fndecl
);
5130 CUMULATIVE_ARGS args_so_far
;
5132 /* If struct value address is treated as the first argument, make it so. */
5133 if (aggregate_value_p (DECL_RESULT (fndecl
))
5134 && ! current_function_returns_pcc_struct
5135 && struct_value_incoming_rtx
== 0)
5137 tree type
= build_pointer_type (fntype
);
5138 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
5139 DECL_ARG_TYPE (function_result_decl
) = type
;
5140 TREE_CHAIN (function_result_decl
) = fnargs
;
5141 fnargs
= function_result_decl
;
5144 /* Determine the last argument, and get its name. */
5146 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, (rtx
)0, 0);
5147 regno
= GP_ARG_FIRST
;
5149 for (cur_arg
= fnargs
; cur_arg
!= (tree
)0; cur_arg
= next_arg
)
5151 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
5152 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
5155 if (TREE_ADDRESSABLE (passed_type
))
5157 passed_type
= build_pointer_type (passed_type
);
5158 passed_mode
= Pmode
;
5161 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
5167 /* passed in a register, so will get homed automatically */
5168 if (GET_MODE (entry_parm
) == BLKmode
)
5169 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
5171 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
5173 regno
= REGNO (entry_parm
) + words
- 1;
5177 regno
= GP_ARG_LAST
+1;
5181 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
5183 next_arg
= TREE_CHAIN (cur_arg
);
5184 if (next_arg
== (tree
)0)
5186 if (DECL_NAME (cur_arg
))
5187 arg_name
= IDENTIFIER_POINTER (DECL_NAME (cur_arg
));
5193 /* In order to pass small structures by value in registers
5194 compatibly with the MIPS compiler, we need to shift the value
5195 into the high part of the register. Function_arg has encoded a
5196 PARALLEL rtx, holding a vector of adjustments to be made as the
5197 next_arg_reg variable, so we split up the insns, and emit them
5200 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
5201 if (next_arg_reg
!= (rtx
)0 && GET_CODE (next_arg_reg
) == PARALLEL
)
5203 rtvec adjust
= XVEC (next_arg_reg
, 0);
5204 int num
= GET_NUM_ELEM (adjust
);
5206 for (i
= 0; i
< num
; i
++)
5208 rtx pattern
= RTVEC_ELT (adjust
, i
);
5209 if (GET_CODE (pattern
) != SET
5210 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
5211 abort_with_insn (pattern
, "Insn is not a shift");
5213 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
5214 emit_insn (pattern
);
5218 tsize
= compute_frame_size (get_frame_size ());
5220 /* If this function is a varargs function, store any registers that
5221 would normally hold arguments ($4 - $7) on the stack. */
5222 if (mips_abi
== ABI_32
5223 && ((TYPE_ARG_TYPES (fntype
) != 0
5224 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
))) != void_type_node
))
5225 || (arg_name
!= (char *)0
5226 && ((arg_name
[0] == '_' && strcmp (arg_name
, "__builtin_va_alist") == 0)
5227 || (arg_name
[0] == 'v' && strcmp (arg_name
, "va_alist") == 0)))))
5229 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
5230 rtx ptr
= stack_pointer_rtx
;
5232 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
5233 if (TARGET_ABICALLS
)
5236 for (; regno
<= GP_ARG_LAST
; regno
++)
5239 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
5240 emit_move_insn (gen_rtx (MEM
, word_mode
, ptr
),
5241 gen_rtx (REG
, word_mode
, regno
));
5242 offset
+= UNITS_PER_WORD
;
5248 rtx tsize_rtx
= GEN_INT (tsize
);
5250 /* If we are doing svr4-abi, sp move is done by function_prologue. */
5251 if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
)
5255 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5256 emit_move_insn (tmp_rtx
, tsize_rtx
);
5257 tsize_rtx
= tmp_rtx
;
5261 emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5264 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5268 save_restore_insns (TRUE
, tmp_rtx
, tsize
, (FILE *)0);
5270 if (frame_pointer_needed
)
5273 emit_insn (gen_movdi (frame_pointer_rtx
, stack_pointer_rtx
));
5275 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
5278 if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
)
5279 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0)));
5282 /* If we are profiling, make sure no instructions are scheduled before
5283 the call to mcount. */
5285 if (profile_flag
|| profile_block_flag
)
5286 emit_insn (gen_blockage ());
5290 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
5292 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5293 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5296 function_epilogue (file
, size
)
5302 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5303 char *t1_str
= reg_names
[MIPS_TEMP1_REGNUM
];
5304 rtx epilogue_delay
= current_function_epilogue_delay_list
;
5305 int noreorder
= (epilogue_delay
!= 0);
5306 int noepilogue
= FALSE
;
5307 int load_nop
= FALSE
;
5309 rtx tmp_rtx
= (rtx
)0;
5313 /* The epilogue does not depend on any registers, but the stack
5314 registers, so we assume that if we have 1 pending nop, it can be
5315 ignored, and 2 it must be filled (2 nops occur for integer
5316 multiply and divide). */
5318 if (dslots_number_nops
> 0)
5320 if (dslots_number_nops
== 1)
5322 dslots_number_nops
= 0;
5323 dslots_load_filled
++;
5327 while (--dslots_number_nops
> 0)
5328 fputs ("\t#nop\n", asm_out_file
);
5335 fputs ("\t.set\tat\n", file
);
5336 error ("internal gcc error: .set noat left on in epilogue");
5339 if (set_nomacro
!= 0)
5342 fputs ("\t.set\tmacro\n", file
);
5343 error ("internal gcc error: .set nomacro left on in epilogue");
5346 if (set_noreorder
!= 0)
5349 fputs ("\t.set\treorder\n", file
);
5350 error ("internal gcc error: .set noreorder left on in epilogue");
5353 if (set_volatile
!= 0)
5356 fprintf (file
, "\t%s.set\tnovolatile\n", (TARGET_MIPS_AS
) ? "" : "#");
5357 error ("internal gcc error: .set volatile left on in epilogue");
5360 size
= MIPS_STACK_ALIGN (size
);
5361 tsize
= (!current_frame_info
.initialized
)
5362 ? compute_frame_size (size
)
5363 : current_frame_info
.total_size
;
5365 if (tsize
== 0 && epilogue_delay
== 0)
5367 rtx insn
= get_last_insn ();
5369 /* If the last insn was a BARRIER, we don't have to write any code
5370 because a jump (aka return) was put there. */
5371 if (GET_CODE (insn
) == NOTE
)
5372 insn
= prev_nonnote_insn (insn
);
5373 if (insn
&& GET_CODE (insn
) == BARRIER
)
5381 /* In the reload sequence, we don't need to fill the load delay
5382 slots for most of the loads, also see if we can fill the final
5383 delay slot if not otherwise filled by the reload sequence. */
5386 fprintf (file
, "\t.set\tnoreorder\n");
5390 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n", t1_str
, (long)tsize
, (long)tsize
);
5391 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5394 if (frame_pointer_needed
)
5395 fprintf (file
, "\tmove\t%s,%s\t\t\t# sp not trusted here\n",
5396 sp_str
, reg_names
[FRAME_POINTER_REGNUM
]);
5398 save_restore_insns (FALSE
, tmp_rtx
, tsize
, file
);
5400 load_only_r31
= (((current_frame_info
.mask
5401 & ~ (TARGET_ABICALLS
&& mips_abi
== ABI_32
5402 ? PIC_OFFSET_TABLE_MASK
: 0))
5404 && current_frame_info
.fmask
== 0);
5408 /* If the only register saved is the return address, we need a
5409 nop, unless we have an instruction to put into it. Otherwise
5410 we don't since reloading multiple registers doesn't reference
5411 the register being loaded. */
5416 final_scan_insn (XEXP (epilogue_delay
, 0),
5420 1); /* nopeepholes */
5423 fprintf (file
, "\tnop\n");
5428 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5431 fprintf (file
, "\t%s\t%s,%s,%s\n",
5432 TARGET_LONG64
? "daddu" : "addu",
5433 sp_str
, sp_str
, t1_str
);
5436 fprintf (file
, "\t%s\t%s,%s,%d\n",
5437 TARGET_LONG64
? "daddu" : "addu",
5438 sp_str
, sp_str
, tsize
);
5440 else if (!load_only_r31
&& epilogue_delay
!= 0)
5441 final_scan_insn (XEXP (epilogue_delay
, 0),
5445 1); /* nopeepholes */
5447 fprintf (file
, "\t.set\treorder\n");
5453 fprintf (file
, "\t%s\t%s,%s,%s\n",
5454 TARGET_LONG64
? "daddu" : "addu",
5455 sp_str
, sp_str
, t1_str
);
5458 fprintf (file
, "\t%s\t%s,%s,%d\n",
5459 TARGET_LONG64
? "daddu" : "addu",
5460 sp_str
, sp_str
, tsize
);
5462 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5466 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5467 /* Get the function name the same way that toplev.c does before calling
5468 assemble_start_function. This is needed so that the name used here
5469 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5470 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5472 fputs ("\t.end\t", file
);
5473 assemble_name (file
, fnname
);
5479 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
5480 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
5481 int num_regs
= num_gp_regs
+ num_fp_regs
;
5482 char *name
= fnname
;
5487 dslots_load_total
+= num_regs
;
5490 dslots_jump_total
++;
5494 dslots_load_filled
+= num_regs
;
5496 /* If the only register saved is the return register, we
5497 can't fill this register's delay slot. */
5499 if (load_only_r31
&& epilogue_delay
== 0)
5500 dslots_load_filled
--;
5502 if (tsize
> 0 || (!load_only_r31
&& epilogue_delay
!= 0))
5503 dslots_jump_filled
++;
5507 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5509 (frame_pointer_needed
) ? 'y' : 'n',
5510 ((current_frame_info
.mask
& RA_MASK
) != 0) ? 'n' : 'y',
5511 (current_function_calls_alloca
) ? 'y' : 'n',
5512 (current_function_calls_setjmp
) ? 'y' : 'n',
5513 (long)current_frame_info
.total_size
,
5514 (long)current_function_outgoing_args_size
,
5515 num_gp_regs
, num_fp_regs
,
5516 dslots_load_total
, dslots_load_filled
,
5517 dslots_jump_total
, dslots_jump_filled
,
5518 num_refs
[0], num_refs
[1], num_refs
[2]);
5520 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
5522 fprintf (stderr
, " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
5523 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
5526 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
5528 fprintf (stderr
, " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
5529 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
5532 fputc ('\n', stderr
);
5535 /* Reset state info for each function. */
5536 inside_function
= FALSE
;
5537 ignore_line_number
= FALSE
;
5538 dslots_load_total
= 0;
5539 dslots_jump_total
= 0;
5540 dslots_load_filled
= 0;
5541 dslots_jump_filled
= 0;
5545 mips_load_reg
= (rtx
)0;
5546 mips_load_reg2
= (rtx
)0;
5547 current_frame_info
= zero_frame_info
;
5549 /* Restore the output file if optimizing the GP (optimizing the GP causes
5550 the text to be diverted to a tempfile, so that data decls come before
5551 references to the data). */
5554 asm_out_file
= asm_out_data_file
;
5558 /* Expand the epilogue into a bunch of separate insns. */
5561 mips_expand_epilogue ()
5563 long tsize
= current_frame_info
.total_size
;
5564 rtx tsize_rtx
= GEN_INT (tsize
);
5565 rtx tmp_rtx
= (rtx
)0;
5569 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5570 emit_move_insn (tmp_rtx
, tsize_rtx
);
5571 tsize_rtx
= tmp_rtx
;
5576 if (frame_pointer_needed
)
5579 emit_insn (gen_movdi (stack_pointer_rtx
, frame_pointer_rtx
));
5581 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
5584 save_restore_insns (FALSE
, tmp_rtx
, tsize
, (FILE *)0);
5587 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5590 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5594 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
, GP_REG_FIRST
+31)));
5598 /* Define the number of delay slots needed for the function epilogue.
5600 On the mips, we need a slot if either no stack has been allocated,
5601 or the only register saved is the return register. */
5604 mips_epilogue_delay_slots ()
5606 if (!current_frame_info
.initialized
)
5607 (void) compute_frame_size (get_frame_size ());
5609 if (current_frame_info
.total_size
== 0)
5612 if (current_frame_info
.mask
== RA_MASK
&& current_frame_info
.fmask
== 0)
5619 /* Return true if this function is known to have a null epilogue.
5620 This allows the optimizer to omit jumps to jumps if no stack
5624 simple_epilogue_p ()
5626 if (!reload_completed
)
5629 if (current_frame_info
.initialized
)
5630 return current_frame_info
.total_size
== 0;
5632 return (compute_frame_size (get_frame_size ())) == 0;
5635 /* Choose the section to use for the constant rtx expression X that has
5638 mips_select_rtx_section (mode
, x
)
5639 enum machine_mode mode
;
5642 if (TARGET_EMBEDDED_DATA
)
5644 /* For embedded applications, always put constants in read-only data,
5645 in order to reduce RAM usage. */
5646 READONLY_DATA_SECTION ();
5650 /* For hosted applications, always put constants in small data if
5651 possible, as this gives the best performance. */
5653 if (GET_MODE_SIZE (mode
) <= mips_section_threshold
5654 && mips_section_threshold
> 0)
5655 SMALL_DATA_SECTION ();
5657 READONLY_DATA_SECTION ();
5661 /* Choose the section to use for DECL. RELOC is true if its value contains
5662 any relocatable expression. */
5664 mips_select_section (decl
, reloc
)
5668 int size
= int_size_in_bytes (TREE_TYPE (decl
));
5670 if (TARGET_EMBEDDED_PIC
5671 && TREE_CODE (decl
) == STRING_CST
5672 && !flag_writable_strings
)
5674 /* For embedded position independent code, put constant strings
5675 in the text section, because the data section is limited to
5680 else if (TARGET_EMBEDDED_DATA
)
5682 /* For embedded applications, always put an object in read-only data
5683 if possible, in order to reduce RAM usage. */
5685 if (((TREE_CODE (decl
) == VAR_DECL
5686 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5687 && DECL_INITIAL (decl
)
5688 && (DECL_INITIAL (decl
) == error_mark_node
5689 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5690 /* Deal with calls from output_constant_def_contents. */
5691 || (TREE_CODE (decl
) != VAR_DECL
5692 && (TREE_CODE (decl
) != STRING_CST
5693 || !flag_writable_strings
)))
5694 && ! (flag_pic
&& reloc
))
5695 READONLY_DATA_SECTION ();
5696 else if (size
> 0 && size
<= mips_section_threshold
)
5697 SMALL_DATA_SECTION ();
5703 /* For hosted applications, always put an object in small data if
5704 possible, as this gives the best performance. */
5706 if (size
> 0 && size
<= mips_section_threshold
)
5707 SMALL_DATA_SECTION ();
5708 else if (((TREE_CODE (decl
) == VAR_DECL
5709 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5710 && DECL_INITIAL (decl
)
5711 && (DECL_INITIAL (decl
) == error_mark_node
5712 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5713 /* Deal with calls from output_constant_def_contents. */
5714 || (TREE_CODE (decl
) != VAR_DECL
5715 && (TREE_CODE (decl
) != STRING_CST
5716 || !flag_writable_strings
)))
5717 && ! (flag_pic
&& reloc
))
5718 READONLY_DATA_SECTION ();
5724 #ifdef MIPS_ABI_DEFAULT
5725 /* Support functions for the 64 bit ABI. */
5727 /* Return register to use for a function return value with VALTYPE for function
5731 mips_function_value (valtype
, func
)
5735 int reg
= GP_RETURN
;
5736 enum machine_mode mode
= TYPE_MODE (valtype
);
5737 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5739 /* ??? How should we return complex float? */
5740 if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5742 else if (TREE_CODE (valtype
) == RECORD_TYPE
&& mips_abi
!= ABI_32
)
5744 /* A struct with only one or two floating point fields is returned in
5745 the floating point registers. */
5746 tree field
, fields
[2];
5749 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
5750 field
= TREE_CHAIN (field
))
5752 if (TREE_CODE (field
) != FIELD_DECL
)
5754 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
5757 fields
[i
++] = field
;
5760 /* Must check i, so that we reject structures with no elements. */
5765 /* The structure has DImode, but we don't allow DImode values
5766 in FP registers, so we use a PARALLEL even though it isn't
5767 strictly necessary. */
5768 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
5770 return gen_rtx (PARALLEL
, mode
,
5772 gen_rtx (EXPR_LIST
, VOIDmode
,
5773 gen_rtx (REG
, field_mode
, FP_RETURN
),
5778 enum machine_mode first_mode
5779 = TYPE_MODE (TREE_TYPE (fields
[0]));
5780 enum machine_mode second_mode
5781 = TYPE_MODE (TREE_TYPE (fields
[1]));
5783 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[0]));
5785 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[1]));
5787 return gen_rtx (PARALLEL
, mode
,
5789 gen_rtx (EXPR_LIST
, VOIDmode
,
5790 gen_rtx (REG
, first_mode
, FP_RETURN
),
5791 GEN_INT (first_offset
/ BITS_PER_UNIT
)),
5792 gen_rtx (EXPR_LIST
, VOIDmode
,
5793 gen_rtx (REG
, second_mode
, FP_RETURN
+ 2),
5794 GEN_INT (second_offset
/ BITS_PER_UNIT
))));
5799 return gen_rtx (REG
, mode
, reg
);
5803 /* This function returns the register class required for a secondary
5804 register when copying between one of the registers in CLASS, and X,
5805 using MODE. If IN_P is nonzero, the copy is going from X to the
5806 register, otherwise the register is the source. A return value of
5807 NO_REGS means that no secondary register is required. */
5810 mips_secondary_reload_class (class, mode
, x
, in_p
)
5811 enum reg_class
class;
5812 enum machine_mode mode
;
5818 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
5819 regno
= true_regnum (x
);
5821 /* We always require a general register when copying anything to
5822 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
5823 to a general register, or when copying from register 0. */
5824 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
5828 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
5832 if (regno
== HILO_REGNUM
)
5836 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
5841 /* Copying from HI or LO to anywhere other than a general register
5842 requires a general register. */
5843 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
5845 if (GP_REG_P (regno
))
5849 if (MD_REG_P (regno
))
5851 if (class == GR_REGS
)