1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "stringpool.h"
39 #include "stor-layout.h"
55 #include "hash-table.h"
58 #include "target-def.h"
59 #include "common/common-target.h"
60 #include "langhooks.h"
61 #include "dominance.h"
67 #include "cfgcleanup.h"
69 #include "basic-block.h"
70 #include "sched-int.h"
71 #include "tree-ssa-alias.h"
72 #include "internal-fn.h"
73 #include "gimple-fold.h"
75 #include "gimple-expr.h"
80 #include "diagnostic.h"
81 #include "target-globals.h"
83 #include "tree-pass.h"
89 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
90 #define UNSPEC_ADDRESS_P(X) \
91 (GET_CODE (X) == UNSPEC \
92 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
93 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
95 /* Extract the symbol or label from UNSPEC wrapper X. */
96 #define UNSPEC_ADDRESS(X) \
99 /* Extract the symbol type from UNSPEC wrapper X. */
100 #define UNSPEC_ADDRESS_TYPE(X) \
101 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
103 /* The maximum distance between the top of the stack frame and the
104 value $sp has when we save and restore registers.
106 The value for normal-mode code must be a SMALL_OPERAND and must
107 preserve the maximum stack alignment. We therefore use a value
108 of 0x7ff0 in this case.
110 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
111 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
113 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
114 up to 0x7f8 bytes and can usually save or restore all the registers
115 that we need to save or restore. (Note that we can only use these
116 instructions for o32, for which the stack alignment is 8 bytes.)
118 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
119 RESTORE are not available. We can then use unextended instructions
120 to save and restore registers, and to allocate and deallocate the top
121 part of the frame. */
122 #define MIPS_MAX_FIRST_STACK_STEP \
123 (!TARGET_COMPRESSION ? 0x7ff0 \
124 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
125 : TARGET_64BIT ? 0x100 : 0x400)
127 /* True if INSN is a mips.md pattern or asm statement. */
128 /* ??? This test exists through the compiler, perhaps it should be
130 #define USEFUL_INSN_P(INSN) \
131 (NONDEBUG_INSN_P (INSN) \
132 && GET_CODE (PATTERN (INSN)) != USE \
133 && GET_CODE (PATTERN (INSN)) != CLOBBER)
135 /* If INSN is a delayed branch sequence, return the first instruction
136 in the sequence, otherwise return INSN itself. */
137 #define SEQ_BEGIN(INSN) \
138 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
139 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \
142 /* Likewise for the last instruction in a delayed branch sequence. */
143 #define SEQ_END(INSN) \
144 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
145 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \
147 XVECLEN (PATTERN (INSN), 0) - 1)) \
150 /* Execute the following loop body with SUBINSN set to each instruction
151 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
152 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
153 for ((SUBINSN) = SEQ_BEGIN (INSN); \
154 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
155 (SUBINSN) = NEXT_INSN (SUBINSN))
157 /* True if bit BIT is set in VALUE. */
158 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
160 /* Return the opcode for a ptr_mode load of the form:
162 l[wd] DEST, OFFSET(BASE). */
163 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
164 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
169 /* Return the opcode to move register SRC into register DEST. */
170 #define MIPS_MOVE(DEST, SRC) \
171 ((TARGET_64BIT ? 0x2d : 0x21) \
175 /* Return the opcode for:
178 #define MIPS_LUI(DEST, VALUE) \
179 ((0xf << 26) | ((DEST) << 16) | (VALUE))
181 /* Return the opcode to jump to register DEST. */
182 #define MIPS_JR(DEST) \
183 (((DEST) << 21) | 0x8)
185 /* Return the opcode for:
187 bal . + (1 + OFFSET) * 4. */
188 #define MIPS_BAL(OFFSET) \
189 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
191 /* Return the usual opcode for a nop. */
194 /* Classifies an address.
197 A natural register + offset address. The register satisfies
198 mips_valid_base_register_p and the offset is a const_arith_operand.
201 A LO_SUM rtx. The first operand is a valid base register and
202 the second operand is a symbolic address.
205 A signed 16-bit constant address.
208 A constant symbolic address. */
209 enum mips_address_type
{
216 /* Macros to create an enumeration identifier for a function prototype. */
217 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
218 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
219 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
220 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
222 /* Classifies the prototype of a built-in function. */
223 enum mips_function_type
{
224 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
225 #include "config/mips/mips-ftypes.def"
226 #undef DEF_MIPS_FTYPE
230 /* Specifies how a built-in function should be converted into rtl. */
231 enum mips_builtin_type
{
232 /* The function corresponds directly to an .md pattern. The return
233 value is mapped to operand 0 and the arguments are mapped to
234 operands 1 and above. */
237 /* The function corresponds directly to an .md pattern. There is no return
238 value and the arguments are mapped to operands 0 and above. */
239 MIPS_BUILTIN_DIRECT_NO_TARGET
,
241 /* The function corresponds to a comparison instruction followed by
242 a mips_cond_move_tf_ps pattern. The first two arguments are the
243 values to compare and the second two arguments are the vector
244 operands for the movt.ps or movf.ps instruction (in assembly order). */
248 /* The function corresponds to a V2SF comparison instruction. Operand 0
249 of this instruction is the result of the comparison, which has mode
250 CCV2 or CCV4. The function arguments are mapped to operands 1 and
251 above. The function's return value is an SImode boolean that is
252 true under the following conditions:
254 MIPS_BUILTIN_CMP_ANY: one of the registers is true
255 MIPS_BUILTIN_CMP_ALL: all of the registers are true
256 MIPS_BUILTIN_CMP_LOWER: the first register is true
257 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
258 MIPS_BUILTIN_CMP_ANY
,
259 MIPS_BUILTIN_CMP_ALL
,
260 MIPS_BUILTIN_CMP_UPPER
,
261 MIPS_BUILTIN_CMP_LOWER
,
263 /* As above, but the instruction only sets a single $fcc register. */
264 MIPS_BUILTIN_CMP_SINGLE
,
266 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
267 MIPS_BUILTIN_BPOSGE32
270 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
271 #define MIPS_FP_CONDITIONS(MACRO) \
289 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
290 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
291 enum mips_fp_condition
{
292 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
294 #undef DECLARE_MIPS_COND
296 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
297 #define STRINGIFY(X) #X
298 static const char *const mips_fp_conditions
[] = {
299 MIPS_FP_CONDITIONS (STRINGIFY
)
303 /* A class used to control a comdat-style stub that we output in each
304 translation unit that needs it. */
305 class mips_one_only_stub
{
307 virtual ~mips_one_only_stub () {}
309 /* Return the name of the stub. */
310 virtual const char *get_name () = 0;
312 /* Output the body of the function to asm_out_file. */
313 virtual void output_body () = 0;
316 /* Tuning information that is automatically derived from other sources
317 (such as the scheduler). */
319 /* The architecture and tuning settings that this structure describes. */
323 /* True if this structure describes MIPS16 settings. */
326 /* True if the structure has been initialized. */
329 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
330 when optimizing for speed. */
331 bool fast_mult_zero_zero_p
;
334 /* Information about a function's frame layout. */
335 struct GTY(()) mips_frame_info
{
336 /* The size of the frame in bytes. */
337 HOST_WIDE_INT total_size
;
339 /* The number of bytes allocated to variables. */
340 HOST_WIDE_INT var_size
;
342 /* The number of bytes allocated to outgoing function arguments. */
343 HOST_WIDE_INT args_size
;
345 /* The number of bytes allocated to the .cprestore slot, or 0 if there
347 HOST_WIDE_INT cprestore_size
;
349 /* Bit X is set if the function saves or restores GPR X. */
352 /* Likewise FPR X. */
355 /* Likewise doubleword accumulator X ($acX). */
356 unsigned int acc_mask
;
358 /* The number of GPRs, FPRs, doubleword accumulators and COP0
362 unsigned int num_acc
;
363 unsigned int num_cop0_regs
;
365 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
366 save slots from the top of the frame, or zero if no such slots are
368 HOST_WIDE_INT gp_save_offset
;
369 HOST_WIDE_INT fp_save_offset
;
370 HOST_WIDE_INT acc_save_offset
;
371 HOST_WIDE_INT cop0_save_offset
;
373 /* Likewise, but giving offsets from the bottom of the frame. */
374 HOST_WIDE_INT gp_sp_offset
;
375 HOST_WIDE_INT fp_sp_offset
;
376 HOST_WIDE_INT acc_sp_offset
;
377 HOST_WIDE_INT cop0_sp_offset
;
379 /* Similar, but the value passed to _mcount. */
380 HOST_WIDE_INT ra_fp_offset
;
382 /* The offset of arg_pointer_rtx from the bottom of the frame. */
383 HOST_WIDE_INT arg_pointer_offset
;
385 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
386 HOST_WIDE_INT hard_frame_pointer_offset
;
389 struct GTY(()) machine_function
{
390 /* The next floating-point condition-code register to allocate
391 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
392 unsigned int next_fcc
;
394 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
395 rtx mips16_gp_pseudo_rtx
;
397 /* The number of extra stack bytes taken up by register varargs.
398 This area is allocated by the callee at the very top of the frame. */
401 /* The current frame information, calculated by mips_compute_frame_info. */
402 struct mips_frame_info frame
;
404 /* The register to use as the function's global pointer, or INVALID_REGNUM
405 if the function doesn't need one. */
406 unsigned int global_pointer
;
408 /* How many instructions it takes to load a label into $AT, or 0 if
409 this property hasn't yet been calculated. */
410 unsigned int load_label_num_insns
;
412 /* True if mips_adjust_insn_length should ignore an instruction's
414 bool ignore_hazard_length_p
;
416 /* True if the whole function is suitable for .set noreorder and
418 bool all_noreorder_p
;
420 /* True if the function has "inflexible" and "flexible" references
421 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
422 and mips_cfun_has_flexible_gp_ref_p for details. */
423 bool has_inflexible_gp_insn_p
;
424 bool has_flexible_gp_insn_p
;
426 /* True if the function's prologue must load the global pointer
427 value into pic_offset_table_rtx and store the same value in
428 the function's cprestore slot (if any). Even if this value
429 is currently false, we may decide to set it to true later;
430 see mips_must_initialize_gp_p () for details. */
431 bool must_initialize_gp_p
;
433 /* True if the current function must restore $gp after any potential
434 clobber. This value is only meaningful during the first post-epilogue
435 split_insns pass; see mips_must_initialize_gp_p () for details. */
436 bool must_restore_gp_when_clobbered_p
;
438 /* True if this is an interrupt handler. */
439 bool interrupt_handler_p
;
441 /* True if this is an interrupt handler that uses shadow registers. */
442 bool use_shadow_register_set_p
;
444 /* True if this is an interrupt handler that should keep interrupts
446 bool keep_interrupts_masked_p
;
448 /* True if this is an interrupt handler that should use DERET
450 bool use_debug_exception_return_p
;
453 /* Information about a single argument. */
454 struct mips_arg_info
{
455 /* True if the argument is passed in a floating-point register, or
456 would have been if we hadn't run out of registers. */
459 /* The number of words passed in registers, rounded up. */
460 unsigned int reg_words
;
462 /* For EABI, the offset of the first register from GP_ARG_FIRST or
463 FP_ARG_FIRST. For other ABIs, the offset of the first register from
464 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
465 comment for details).
467 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
469 unsigned int reg_offset
;
471 /* The number of words that must be passed on the stack, rounded up. */
472 unsigned int stack_words
;
474 /* The offset from the start of the stack overflow area of the argument's
475 first stack word. Only meaningful when STACK_WORDS is nonzero. */
476 unsigned int stack_offset
;
479 /* Information about an address described by mips_address_type.
485 REG is the base register and OFFSET is the constant offset.
488 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
489 is the type of symbol it references.
492 SYMBOL_TYPE is the type of symbol that the address references. */
493 struct mips_address_info
{
494 enum mips_address_type type
;
497 enum mips_symbol_type symbol_type
;
500 /* One stage in a constant building sequence. These sequences have
504 A = A CODE[1] VALUE[1]
505 A = A CODE[2] VALUE[2]
508 where A is an accumulator, each CODE[i] is a binary rtl operation
509 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
510 struct mips_integer_op
{
512 unsigned HOST_WIDE_INT value
;
515 /* The largest number of operations needed to load an integer constant.
516 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
517 When the lowest bit is clear, we can try, but reject a sequence with
518 an extra SLL at the end. */
519 #define MIPS_MAX_INTEGER_OPS 7
521 /* Information about a MIPS16e SAVE or RESTORE instruction. */
522 struct mips16e_save_restore_info
{
523 /* The number of argument registers saved by a SAVE instruction.
524 0 for RESTORE instructions. */
527 /* Bit X is set if the instruction saves or restores GPR X. */
530 /* The total number of bytes to allocate. */
534 /* Costs of various operations on the different architectures. */
536 struct mips_rtx_cost_data
538 unsigned short fp_add
;
539 unsigned short fp_mult_sf
;
540 unsigned short fp_mult_df
;
541 unsigned short fp_div_sf
;
542 unsigned short fp_div_df
;
543 unsigned short int_mult_si
;
544 unsigned short int_mult_di
;
545 unsigned short int_div_si
;
546 unsigned short int_div_di
;
547 unsigned short branch_cost
;
548 unsigned short memory_latency
;
551 /* Global variables for machine-dependent things. */
553 /* The -G setting, or the configuration's default small-data limit if
554 no -G option is given. */
555 static unsigned int mips_small_data_threshold
;
557 /* The number of file directives written by mips_output_filename. */
558 int num_source_filenames
;
560 /* The name that appeared in the last .file directive written by
561 mips_output_filename, or "" if mips_output_filename hasn't
562 written anything yet. */
563 const char *current_function_file
= "";
565 /* Arrays that map GCC register numbers to debugger register numbers. */
566 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
567 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
569 /* Information about the current function's epilogue, used only while
572 /* A list of queued REG_CFA_RESTORE notes. */
575 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
577 HOST_WIDE_INT cfa_offset
;
579 /* The offset of the CFA from the stack pointer while restoring
581 HOST_WIDE_INT cfa_restore_sp_offset
;
584 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
585 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
586 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
587 struct mips_asm_switch mips_noat
= { "at", 0 };
589 /* True if we're writing out a branch-likely instruction rather than a
591 static bool mips_branch_likely
;
593 /* The current instruction-set architecture. */
594 enum processor mips_arch
;
595 const struct mips_cpu_info
*mips_arch_info
;
597 /* The processor that we should tune the code for. */
598 enum processor mips_tune
;
599 const struct mips_cpu_info
*mips_tune_info
;
601 /* The ISA level associated with mips_arch. */
604 /* The ISA revision level. This is 0 for MIPS I to V and N for
608 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
609 static const struct mips_cpu_info
*mips_isa_option_info
;
611 /* Which cost information to use. */
612 static const struct mips_rtx_cost_data
*mips_cost
;
614 /* The ambient target flags, excluding MASK_MIPS16. */
615 static int mips_base_target_flags
;
617 /* The default compression mode. */
618 unsigned int mips_base_compression_flags
;
620 /* The ambient values of other global variables. */
621 static int mips_base_schedule_insns
; /* flag_schedule_insns */
622 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
623 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
624 static int mips_base_align_loops
; /* align_loops */
625 static int mips_base_align_jumps
; /* align_jumps */
626 static int mips_base_align_functions
; /* align_functions */
628 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
629 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
631 /* Index C is true if character C is a valid PRINT_OPERAND punctation
633 static bool mips_print_operand_punct
[256];
635 static GTY (()) int mips_output_filename_first_time
= 1;
637 /* mips_split_p[X] is true if symbols of type X can be split by
638 mips_split_symbol. */
639 bool mips_split_p
[NUM_SYMBOL_TYPES
];
641 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
642 can be split by mips_split_symbol. */
643 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
645 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
646 forced into a PC-relative constant pool. */
647 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
649 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
650 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
651 if they are matched by a special .md file pattern. */
652 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
654 /* Likewise for HIGHs. */
655 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
657 /* Target state for MIPS16. */
658 struct target_globals
*mips16_globals
;
660 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
661 and returned from mips_sched_reorder2. */
662 static int cached_can_issue_more
;
664 /* The stubs for various MIPS16 support functions, if used. */
665 static mips_one_only_stub
*mips16_rdhwr_stub
;
666 static mips_one_only_stub
*mips16_get_fcsr_stub
;
667 static mips_one_only_stub
*mips16_set_fcsr_stub
;
669 /* Index R is the smallest register class that contains register R. */
670 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
671 LEA_REGS
, LEA_REGS
, M16_STORE_REGS
, V1_REG
,
672 M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
,
673 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
674 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
675 M16_REGS
, M16_STORE_REGS
, LEA_REGS
, LEA_REGS
,
676 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
677 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
678 LEA_REGS
, M16_SP_REGS
, LEA_REGS
, LEA_REGS
,
680 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
681 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
682 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
683 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
684 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
685 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
686 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
687 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
688 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
689 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
690 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
691 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
692 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
693 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
694 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
695 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
696 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
697 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
698 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
699 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
700 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
701 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
702 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
703 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
704 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
705 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
706 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
707 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
708 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
709 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
710 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
711 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
712 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
713 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
714 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
715 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
716 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
717 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
718 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
721 /* The value of TARGET_ATTRIBUTE_TABLE. */
722 static const struct attribute_spec mips_attribute_table
[] = {
723 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
725 { "long_call", 0, 0, false, true, true, NULL
, false },
726 { "far", 0, 0, false, true, true, NULL
, false },
727 { "near", 0, 0, false, true, true, NULL
, false },
728 /* We would really like to treat "mips16" and "nomips16" as type
729 attributes, but GCC doesn't provide the hooks we need to support
730 the right conversion rules. As declaration attributes, they affect
731 code generation but don't carry other semantics. */
732 { "mips16", 0, 0, true, false, false, NULL
, false },
733 { "nomips16", 0, 0, true, false, false, NULL
, false },
734 { "micromips", 0, 0, true, false, false, NULL
, false },
735 { "nomicromips", 0, 0, true, false, false, NULL
, false },
736 { "nocompression", 0, 0, true, false, false, NULL
, false },
737 /* Allow functions to be specified as interrupt handlers */
738 { "interrupt", 0, 0, false, true, true, NULL
, false },
739 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
740 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
741 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
742 { NULL
, 0, 0, false, false, false, NULL
, false }
745 /* A table describing all the processors GCC knows about; see
746 mips-cpus.def for details. */
747 static const struct mips_cpu_info mips_cpu_info_table
[] = {
748 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
749 { NAME, CPU, ISA, FLAGS },
750 #include "mips-cpus.def"
754 /* Default costs. If these are used for a processor we should look
755 up the actual costs. */
756 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
757 COSTS_N_INSNS (7), /* fp_mult_sf */ \
758 COSTS_N_INSNS (8), /* fp_mult_df */ \
759 COSTS_N_INSNS (23), /* fp_div_sf */ \
760 COSTS_N_INSNS (36), /* fp_div_df */ \
761 COSTS_N_INSNS (10), /* int_mult_si */ \
762 COSTS_N_INSNS (10), /* int_mult_di */ \
763 COSTS_N_INSNS (69), /* int_div_si */ \
764 COSTS_N_INSNS (69), /* int_div_di */ \
765 2, /* branch_cost */ \
766 4 /* memory_latency */
768 /* Floating-point costs for processors without an FPU. Just assume that
769 all floating-point libcalls are very expensive. */
770 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
771 COSTS_N_INSNS (256), /* fp_mult_sf */ \
772 COSTS_N_INSNS (256), /* fp_mult_df */ \
773 COSTS_N_INSNS (256), /* fp_div_sf */ \
774 COSTS_N_INSNS (256) /* fp_div_df */
776 /* Costs to use when optimizing for size. */
777 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
778 COSTS_N_INSNS (1), /* fp_add */
779 COSTS_N_INSNS (1), /* fp_mult_sf */
780 COSTS_N_INSNS (1), /* fp_mult_df */
781 COSTS_N_INSNS (1), /* fp_div_sf */
782 COSTS_N_INSNS (1), /* fp_div_df */
783 COSTS_N_INSNS (1), /* int_mult_si */
784 COSTS_N_INSNS (1), /* int_mult_di */
785 COSTS_N_INSNS (1), /* int_div_si */
786 COSTS_N_INSNS (1), /* int_div_di */
788 4 /* memory_latency */
791 /* Costs to use when optimizing for speed, indexed by processor. */
792 static const struct mips_rtx_cost_data
793 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
795 COSTS_N_INSNS (2), /* fp_add */
796 COSTS_N_INSNS (4), /* fp_mult_sf */
797 COSTS_N_INSNS (5), /* fp_mult_df */
798 COSTS_N_INSNS (12), /* fp_div_sf */
799 COSTS_N_INSNS (19), /* fp_div_df */
800 COSTS_N_INSNS (12), /* int_mult_si */
801 COSTS_N_INSNS (12), /* int_mult_di */
802 COSTS_N_INSNS (35), /* int_div_si */
803 COSTS_N_INSNS (35), /* int_div_di */
805 4 /* memory_latency */
809 COSTS_N_INSNS (6), /* int_mult_si */
810 COSTS_N_INSNS (6), /* int_mult_di */
811 COSTS_N_INSNS (36), /* int_div_si */
812 COSTS_N_INSNS (36), /* int_div_di */
814 4 /* memory_latency */
818 COSTS_N_INSNS (36), /* int_mult_si */
819 COSTS_N_INSNS (36), /* int_mult_di */
820 COSTS_N_INSNS (37), /* int_div_si */
821 COSTS_N_INSNS (37), /* int_div_di */
823 4 /* memory_latency */
827 COSTS_N_INSNS (4), /* int_mult_si */
828 COSTS_N_INSNS (11), /* int_mult_di */
829 COSTS_N_INSNS (36), /* int_div_si */
830 COSTS_N_INSNS (68), /* int_div_di */
832 4 /* memory_latency */
835 COSTS_N_INSNS (4), /* fp_add */
836 COSTS_N_INSNS (4), /* fp_mult_sf */
837 COSTS_N_INSNS (5), /* fp_mult_df */
838 COSTS_N_INSNS (17), /* fp_div_sf */
839 COSTS_N_INSNS (32), /* fp_div_df */
840 COSTS_N_INSNS (4), /* int_mult_si */
841 COSTS_N_INSNS (11), /* int_mult_di */
842 COSTS_N_INSNS (36), /* int_div_si */
843 COSTS_N_INSNS (68), /* int_div_di */
845 4 /* memory_latency */
848 COSTS_N_INSNS (4), /* fp_add */
849 COSTS_N_INSNS (4), /* fp_mult_sf */
850 COSTS_N_INSNS (5), /* fp_mult_df */
851 COSTS_N_INSNS (17), /* fp_div_sf */
852 COSTS_N_INSNS (32), /* fp_div_df */
853 COSTS_N_INSNS (4), /* int_mult_si */
854 COSTS_N_INSNS (7), /* int_mult_di */
855 COSTS_N_INSNS (42), /* int_div_si */
856 COSTS_N_INSNS (72), /* int_div_di */
858 4 /* memory_latency */
862 COSTS_N_INSNS (5), /* int_mult_si */
863 COSTS_N_INSNS (5), /* int_mult_di */
864 COSTS_N_INSNS (41), /* int_div_si */
865 COSTS_N_INSNS (41), /* int_div_di */
867 4 /* memory_latency */
870 COSTS_N_INSNS (8), /* fp_add */
871 COSTS_N_INSNS (8), /* fp_mult_sf */
872 COSTS_N_INSNS (10), /* fp_mult_df */
873 COSTS_N_INSNS (34), /* fp_div_sf */
874 COSTS_N_INSNS (64), /* fp_div_df */
875 COSTS_N_INSNS (5), /* int_mult_si */
876 COSTS_N_INSNS (5), /* int_mult_di */
877 COSTS_N_INSNS (41), /* int_div_si */
878 COSTS_N_INSNS (41), /* int_div_di */
880 4 /* memory_latency */
883 COSTS_N_INSNS (4), /* fp_add */
884 COSTS_N_INSNS (4), /* fp_mult_sf */
885 COSTS_N_INSNS (5), /* fp_mult_df */
886 COSTS_N_INSNS (17), /* fp_div_sf */
887 COSTS_N_INSNS (32), /* fp_div_df */
888 COSTS_N_INSNS (5), /* int_mult_si */
889 COSTS_N_INSNS (5), /* int_mult_di */
890 COSTS_N_INSNS (41), /* int_div_si */
891 COSTS_N_INSNS (41), /* int_div_di */
893 4 /* memory_latency */
897 COSTS_N_INSNS (5), /* int_mult_si */
898 COSTS_N_INSNS (5), /* int_mult_di */
899 COSTS_N_INSNS (41), /* int_div_si */
900 COSTS_N_INSNS (41), /* int_div_di */
902 4 /* memory_latency */
905 COSTS_N_INSNS (8), /* fp_add */
906 COSTS_N_INSNS (8), /* fp_mult_sf */
907 COSTS_N_INSNS (10), /* fp_mult_df */
908 COSTS_N_INSNS (34), /* fp_div_sf */
909 COSTS_N_INSNS (64), /* fp_div_df */
910 COSTS_N_INSNS (5), /* int_mult_si */
911 COSTS_N_INSNS (5), /* int_mult_di */
912 COSTS_N_INSNS (41), /* int_div_si */
913 COSTS_N_INSNS (41), /* int_div_di */
915 4 /* memory_latency */
918 COSTS_N_INSNS (4), /* fp_add */
919 COSTS_N_INSNS (4), /* fp_mult_sf */
920 COSTS_N_INSNS (5), /* fp_mult_df */
921 COSTS_N_INSNS (17), /* fp_div_sf */
922 COSTS_N_INSNS (32), /* fp_div_df */
923 COSTS_N_INSNS (5), /* int_mult_si */
924 COSTS_N_INSNS (5), /* int_mult_di */
925 COSTS_N_INSNS (41), /* int_div_si */
926 COSTS_N_INSNS (41), /* int_div_di */
928 4 /* memory_latency */
931 COSTS_N_INSNS (6), /* fp_add */
932 COSTS_N_INSNS (6), /* fp_mult_sf */
933 COSTS_N_INSNS (7), /* fp_mult_df */
934 COSTS_N_INSNS (25), /* fp_div_sf */
935 COSTS_N_INSNS (48), /* fp_div_df */
936 COSTS_N_INSNS (5), /* int_mult_si */
937 COSTS_N_INSNS (5), /* int_mult_di */
938 COSTS_N_INSNS (41), /* int_div_si */
939 COSTS_N_INSNS (41), /* int_div_di */
941 4 /* memory_latency */
958 COSTS_N_INSNS (5), /* int_mult_si */
959 COSTS_N_INSNS (5), /* int_mult_di */
960 COSTS_N_INSNS (72), /* int_div_si */
961 COSTS_N_INSNS (72), /* int_div_di */
963 4 /* memory_latency */
968 COSTS_N_INSNS (6), /* int_mult_si */
969 COSTS_N_INSNS (6), /* int_mult_di */
970 COSTS_N_INSNS (18), /* int_div_si */
971 COSTS_N_INSNS (35), /* int_div_di */
973 4 /* memory_latency */
976 COSTS_N_INSNS (2), /* fp_add */
977 COSTS_N_INSNS (4), /* fp_mult_sf */
978 COSTS_N_INSNS (5), /* fp_mult_df */
979 COSTS_N_INSNS (12), /* fp_div_sf */
980 COSTS_N_INSNS (19), /* fp_div_df */
981 COSTS_N_INSNS (2), /* int_mult_si */
982 COSTS_N_INSNS (2), /* int_mult_di */
983 COSTS_N_INSNS (35), /* int_div_si */
984 COSTS_N_INSNS (35), /* int_div_di */
986 4 /* memory_latency */
989 COSTS_N_INSNS (3), /* fp_add */
990 COSTS_N_INSNS (5), /* fp_mult_sf */
991 COSTS_N_INSNS (6), /* fp_mult_df */
992 COSTS_N_INSNS (15), /* fp_div_sf */
993 COSTS_N_INSNS (16), /* fp_div_df */
994 COSTS_N_INSNS (17), /* int_mult_si */
995 COSTS_N_INSNS (17), /* int_mult_di */
996 COSTS_N_INSNS (38), /* int_div_si */
997 COSTS_N_INSNS (38), /* int_div_di */
999 6 /* memory_latency */
1002 COSTS_N_INSNS (6), /* fp_add */
1003 COSTS_N_INSNS (7), /* fp_mult_sf */
1004 COSTS_N_INSNS (8), /* fp_mult_df */
1005 COSTS_N_INSNS (23), /* fp_div_sf */
1006 COSTS_N_INSNS (36), /* fp_div_df */
1007 COSTS_N_INSNS (10), /* int_mult_si */
1008 COSTS_N_INSNS (10), /* int_mult_di */
1009 COSTS_N_INSNS (69), /* int_div_si */
1010 COSTS_N_INSNS (69), /* int_div_di */
1011 2, /* branch_cost */
1012 6 /* memory_latency */
1024 /* The only costs that appear to be updated here are
1025 integer multiplication. */
1027 COSTS_N_INSNS (4), /* int_mult_si */
1028 COSTS_N_INSNS (6), /* int_mult_di */
1029 COSTS_N_INSNS (69), /* int_div_si */
1030 COSTS_N_INSNS (69), /* int_div_di */
1031 1, /* branch_cost */
1032 4 /* memory_latency */
1047 COSTS_N_INSNS (6), /* fp_add */
1048 COSTS_N_INSNS (4), /* fp_mult_sf */
1049 COSTS_N_INSNS (5), /* fp_mult_df */
1050 COSTS_N_INSNS (23), /* fp_div_sf */
1051 COSTS_N_INSNS (36), /* fp_div_df */
1052 COSTS_N_INSNS (5), /* int_mult_si */
1053 COSTS_N_INSNS (5), /* int_mult_di */
1054 COSTS_N_INSNS (36), /* int_div_si */
1055 COSTS_N_INSNS (36), /* int_div_di */
1056 1, /* branch_cost */
1057 4 /* memory_latency */
1060 COSTS_N_INSNS (6), /* fp_add */
1061 COSTS_N_INSNS (5), /* fp_mult_sf */
1062 COSTS_N_INSNS (6), /* fp_mult_df */
1063 COSTS_N_INSNS (30), /* fp_div_sf */
1064 COSTS_N_INSNS (59), /* fp_div_df */
1065 COSTS_N_INSNS (3), /* int_mult_si */
1066 COSTS_N_INSNS (4), /* int_mult_di */
1067 COSTS_N_INSNS (42), /* int_div_si */
1068 COSTS_N_INSNS (74), /* int_div_di */
1069 1, /* branch_cost */
1070 4 /* memory_latency */
1073 COSTS_N_INSNS (6), /* fp_add */
1074 COSTS_N_INSNS (5), /* fp_mult_sf */
1075 COSTS_N_INSNS (6), /* fp_mult_df */
1076 COSTS_N_INSNS (30), /* fp_div_sf */
1077 COSTS_N_INSNS (59), /* fp_div_df */
1078 COSTS_N_INSNS (5), /* int_mult_si */
1079 COSTS_N_INSNS (9), /* int_mult_di */
1080 COSTS_N_INSNS (42), /* int_div_si */
1081 COSTS_N_INSNS (74), /* int_div_di */
1082 1, /* branch_cost */
1083 4 /* memory_latency */
1086 COSTS_N_INSNS (4), /* fp_add */
1087 COSTS_N_INSNS (4), /* fp_mult_sf */
1088 COSTS_N_INSNS (256), /* fp_mult_df */
1089 COSTS_N_INSNS (8), /* fp_div_sf */
1090 COSTS_N_INSNS (256), /* fp_div_df */
1091 COSTS_N_INSNS (4), /* int_mult_si */
1092 COSTS_N_INSNS (256), /* int_mult_di */
1093 COSTS_N_INSNS (37), /* int_div_si */
1094 COSTS_N_INSNS (256), /* int_div_di */
1095 1, /* branch_cost */
1096 4 /* memory_latency */
1099 /* The only costs that are changed here are
1100 integer multiplication. */
1101 COSTS_N_INSNS (6), /* fp_add */
1102 COSTS_N_INSNS (7), /* fp_mult_sf */
1103 COSTS_N_INSNS (8), /* fp_mult_df */
1104 COSTS_N_INSNS (23), /* fp_div_sf */
1105 COSTS_N_INSNS (36), /* fp_div_df */
1106 COSTS_N_INSNS (5), /* int_mult_si */
1107 COSTS_N_INSNS (9), /* int_mult_di */
1108 COSTS_N_INSNS (69), /* int_div_si */
1109 COSTS_N_INSNS (69), /* int_div_di */
1110 1, /* branch_cost */
1111 4 /* memory_latency */
1117 /* The only costs that are changed here are
1118 integer multiplication. */
1119 COSTS_N_INSNS (6), /* fp_add */
1120 COSTS_N_INSNS (7), /* fp_mult_sf */
1121 COSTS_N_INSNS (8), /* fp_mult_df */
1122 COSTS_N_INSNS (23), /* fp_div_sf */
1123 COSTS_N_INSNS (36), /* fp_div_df */
1124 COSTS_N_INSNS (3), /* int_mult_si */
1125 COSTS_N_INSNS (8), /* int_mult_di */
1126 COSTS_N_INSNS (69), /* int_div_si */
1127 COSTS_N_INSNS (69), /* int_div_di */
1128 1, /* branch_cost */
1129 4 /* memory_latency */
1132 COSTS_N_INSNS (2), /* fp_add */
1133 COSTS_N_INSNS (2), /* fp_mult_sf */
1134 COSTS_N_INSNS (2), /* fp_mult_df */
1135 COSTS_N_INSNS (12), /* fp_div_sf */
1136 COSTS_N_INSNS (19), /* fp_div_df */
1137 COSTS_N_INSNS (5), /* int_mult_si */
1138 COSTS_N_INSNS (9), /* int_mult_di */
1139 COSTS_N_INSNS (34), /* int_div_si */
1140 COSTS_N_INSNS (66), /* int_div_di */
1141 1, /* branch_cost */
1142 4 /* memory_latency */
1145 /* These costs are the same as the SB-1A below. */
1146 COSTS_N_INSNS (4), /* fp_add */
1147 COSTS_N_INSNS (4), /* fp_mult_sf */
1148 COSTS_N_INSNS (4), /* fp_mult_df */
1149 COSTS_N_INSNS (24), /* fp_div_sf */
1150 COSTS_N_INSNS (32), /* fp_div_df */
1151 COSTS_N_INSNS (3), /* int_mult_si */
1152 COSTS_N_INSNS (4), /* int_mult_di */
1153 COSTS_N_INSNS (36), /* int_div_si */
1154 COSTS_N_INSNS (68), /* int_div_di */
1155 1, /* branch_cost */
1156 4 /* memory_latency */
1159 /* These costs are the same as the SB-1 above. */
1160 COSTS_N_INSNS (4), /* fp_add */
1161 COSTS_N_INSNS (4), /* fp_mult_sf */
1162 COSTS_N_INSNS (4), /* fp_mult_df */
1163 COSTS_N_INSNS (24), /* fp_div_sf */
1164 COSTS_N_INSNS (32), /* fp_div_df */
1165 COSTS_N_INSNS (3), /* int_mult_si */
1166 COSTS_N_INSNS (4), /* int_mult_di */
1167 COSTS_N_INSNS (36), /* int_div_si */
1168 COSTS_N_INSNS (68), /* int_div_di */
1169 1, /* branch_cost */
1170 4 /* memory_latency */
1177 COSTS_N_INSNS (8), /* int_mult_si */
1178 COSTS_N_INSNS (8), /* int_mult_di */
1179 COSTS_N_INSNS (72), /* int_div_si */
1180 COSTS_N_INSNS (72), /* int_div_di */
1181 1, /* branch_cost */
1182 4 /* memory_latency */
1185 /* These costs are the same as 5KF above. */
1186 COSTS_N_INSNS (4), /* fp_add */
1187 COSTS_N_INSNS (4), /* fp_mult_sf */
1188 COSTS_N_INSNS (5), /* fp_mult_df */
1189 COSTS_N_INSNS (17), /* fp_div_sf */
1190 COSTS_N_INSNS (32), /* fp_div_df */
1191 COSTS_N_INSNS (4), /* int_mult_si */
1192 COSTS_N_INSNS (11), /* int_mult_di */
1193 COSTS_N_INSNS (36), /* int_div_si */
1194 COSTS_N_INSNS (68), /* int_div_di */
1195 1, /* branch_cost */
1196 4 /* memory_latency */
1199 COSTS_N_INSNS (4), /* fp_add */
1200 COSTS_N_INSNS (5), /* fp_mult_sf */
1201 COSTS_N_INSNS (5), /* fp_mult_df */
1202 COSTS_N_INSNS (17), /* fp_div_sf */
1203 COSTS_N_INSNS (17), /* fp_div_df */
1204 COSTS_N_INSNS (5), /* int_mult_si */
1205 COSTS_N_INSNS (5), /* int_mult_di */
1206 COSTS_N_INSNS (8), /* int_div_si */
1207 COSTS_N_INSNS (8), /* int_div_di */
1208 2, /* branch_cost */
1209 10 /* memory_latency */
1213 static rtx
mips_find_pic_call_symbol (rtx_insn
*, rtx
, bool);
1214 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1216 static unsigned int mips_function_arg_boundary (enum machine_mode
, const_tree
);
1218 struct mips16_flip_traits
: default_hashmap_traits
1220 static hashval_t
hash (const char *s
) { return htab_hash_string (s
); }
1222 equal_keys (const char *a
, const char *b
)
1224 return !strcmp (a
, b
);
1228 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1229 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1230 static GTY (()) hash_map
<const char *, bool, mips16_flip_traits
> *
1233 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1234 mode, false if it should next add an attribute for the opposite mode. */
1235 static GTY(()) bool mips16_flipper
;
1237 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1238 for -mflip-mips16. Return true if it should use "mips16" and false if
1239 it should use "nomips16". */
1242 mflip_mips16_use_mips16_p (tree decl
)
1245 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1247 /* Use the opposite of the command-line setting for anonymous decls. */
1248 if (!DECL_NAME (decl
))
1249 return !base_is_mips16
;
1251 if (!mflip_mips16_htab
)
1253 = hash_map
<const char *, bool, mips16_flip_traits
>::create_ggc (37);
1255 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1258 bool *slot
= &mflip_mips16_htab
->get_or_insert (name
, &existed
);
1261 mips16_flipper
= !mips16_flipper
;
1262 *slot
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1267 /* Predicates to test for presence of "near" and "far"/"long_call"
1268 attributes on the given TYPE. */
1271 mips_near_type_p (const_tree type
)
1273 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1277 mips_far_type_p (const_tree type
)
1279 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1280 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1284 /* Check if the interrupt attribute is set for a function. */
1287 mips_interrupt_type_p (tree type
)
1289 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1292 /* Check if the attribute to use shadow register set is set for a function. */
1295 mips_use_shadow_register_set_p (tree type
)
1297 return lookup_attribute ("use_shadow_register_set",
1298 TYPE_ATTRIBUTES (type
)) != NULL
;
1301 /* Check if the attribute to keep interrupts masked is set for a function. */
1304 mips_keep_interrupts_masked_p (tree type
)
1306 return lookup_attribute ("keep_interrupts_masked",
1307 TYPE_ATTRIBUTES (type
)) != NULL
;
1310 /* Check if the attribute to use debug exception return is set for
1314 mips_use_debug_exception_return_p (tree type
)
1316 return lookup_attribute ("use_debug_exception_return",
1317 TYPE_ATTRIBUTES (type
)) != NULL
;
1320 /* Return the set of compression modes that are explicitly required
1321 by the attributes in ATTRIBUTES. */
1324 mips_get_compress_on_flags (tree attributes
)
1326 unsigned int flags
= 0;
1328 if (lookup_attribute ("mips16", attributes
) != NULL
)
1329 flags
|= MASK_MIPS16
;
1331 if (lookup_attribute ("micromips", attributes
) != NULL
)
1332 flags
|= MASK_MICROMIPS
;
1337 /* Return the set of compression modes that are explicitly forbidden
1338 by the attributes in ATTRIBUTES. */
1341 mips_get_compress_off_flags (tree attributes
)
1343 unsigned int flags
= 0;
1345 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1346 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1348 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1349 flags
|= MASK_MIPS16
;
1351 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1352 flags
|= MASK_MICROMIPS
;
1357 /* Return the compression mode that should be used for function DECL.
1358 Return the ambient setting if DECL is null. */
1361 mips_get_compress_mode (tree decl
)
1363 unsigned int flags
, force_on
;
1365 flags
= mips_base_compression_flags
;
1368 /* Nested functions must use the same frame pointer as their
1369 parent and must therefore use the same ISA mode. */
1370 tree parent
= decl_function_context (decl
);
1373 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1376 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1381 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1385 mips_get_compress_on_name (unsigned int flags
)
1387 if (flags
== MASK_MIPS16
)
1392 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1396 mips_get_compress_off_name (unsigned int flags
)
1398 if (flags
== MASK_MIPS16
)
1400 if (flags
== MASK_MICROMIPS
)
1401 return "nomicromips";
1402 return "nocompression";
1405 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1408 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1410 /* Disallow mixed near/far attributes. */
1411 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1413 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1418 /* Implement TARGET_INSERT_ATTRIBUTES. */
1421 mips_insert_attributes (tree decl
, tree
*attributes
)
1424 unsigned int compression_flags
, nocompression_flags
;
1426 /* Check for "mips16" and "nomips16" attributes. */
1427 compression_flags
= mips_get_compress_on_flags (*attributes
);
1428 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1430 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1432 if (nocompression_flags
)
1433 error ("%qs attribute only applies to functions",
1434 mips_get_compress_off_name (nocompression_flags
));
1436 if (compression_flags
)
1437 error ("%qs attribute only applies to functions",
1438 mips_get_compress_on_name (nocompression_flags
));
1442 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1443 nocompression_flags
|=
1444 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1446 if (compression_flags
&& nocompression_flags
)
1447 error ("%qE cannot have both %qs and %qs attributes",
1448 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1449 mips_get_compress_off_name (nocompression_flags
));
1451 if (compression_flags
& MASK_MIPS16
1452 && compression_flags
& MASK_MICROMIPS
)
1453 error ("%qE cannot have both %qs and %qs attributes",
1454 DECL_NAME (decl
), "mips16", "micromips");
1456 if (TARGET_FLIP_MIPS16
1457 && !DECL_ARTIFICIAL (decl
)
1458 && compression_flags
== 0
1459 && nocompression_flags
== 0)
1461 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1462 "mips16" attribute, arbitrarily pick one. We must pick the same
1463 setting for duplicate declarations of a function. */
1464 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1465 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1466 name
= "nomicromips";
1467 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1472 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1475 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1479 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1480 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1482 error ("%qE redeclared with conflicting %qs attributes",
1483 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1485 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1486 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1488 error ("%qE redeclared with conflicting %qs attributes",
1489 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1491 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1492 DECL_ATTRIBUTES (newdecl
));
1495 /* Implement TARGET_CAN_INLINE_P. */
1498 mips_can_inline_p (tree caller
, tree callee
)
1500 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1502 return default_target_can_inline_p (caller
, callee
);
1505 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1506 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1509 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1511 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1513 *base_ptr
= XEXP (x
, 0);
1514 *offset_ptr
= INTVAL (XEXP (x
, 1));
1523 static unsigned int mips_build_integer (struct mips_integer_op
*,
1524 unsigned HOST_WIDE_INT
);
1526 /* A subroutine of mips_build_integer, with the same interface.
1527 Assume that the final action in the sequence should be a left shift. */
1530 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1532 unsigned int i
, shift
;
1534 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1535 since signed numbers are easier to load than unsigned ones. */
1537 while ((value
& 1) == 0)
1538 value
/= 2, shift
++;
1540 i
= mips_build_integer (codes
, value
);
1541 codes
[i
].code
= ASHIFT
;
1542 codes
[i
].value
= shift
;
1546 /* As for mips_build_shift, but assume that the final action will be
1547 an IOR or PLUS operation. */
1550 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1552 unsigned HOST_WIDE_INT high
;
1555 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1556 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1558 /* The constant is too complex to load with a simple LUI/ORI pair,
1559 so we want to give the recursive call as many trailing zeros as
1560 possible. In this case, we know bit 16 is set and that the
1561 low 16 bits form a negative number. If we subtract that number
1562 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1563 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1564 codes
[i
].code
= PLUS
;
1565 codes
[i
].value
= CONST_LOW_PART (value
);
1569 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1570 bits gives a value with at least 17 trailing zeros. */
1571 i
= mips_build_integer (codes
, high
);
1572 codes
[i
].code
= IOR
;
1573 codes
[i
].value
= value
& 0xffff;
1578 /* Fill CODES with a sequence of rtl operations to load VALUE.
1579 Return the number of operations needed. */
1582 mips_build_integer (struct mips_integer_op
*codes
,
1583 unsigned HOST_WIDE_INT value
)
1585 if (SMALL_OPERAND (value
)
1586 || SMALL_OPERAND_UNSIGNED (value
)
1587 || LUI_OPERAND (value
))
1589 /* The value can be loaded with a single instruction. */
1590 codes
[0].code
= UNKNOWN
;
1591 codes
[0].value
= value
;
1594 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1596 /* Either the constant is a simple LUI/ORI combination or its
1597 lowest bit is set. We don't want to shift in this case. */
1598 return mips_build_lower (codes
, value
);
1600 else if ((value
& 0xffff) == 0)
1602 /* The constant will need at least three actions. The lowest
1603 16 bits are clear, so the final action will be a shift. */
1604 return mips_build_shift (codes
, value
);
1608 /* The final action could be a shift, add or inclusive OR.
1609 Rather than use a complex condition to select the best
1610 approach, try both mips_build_shift and mips_build_lower
1611 and pick the one that gives the shortest sequence.
1612 Note that this case is only used once per constant. */
1613 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1614 unsigned int cost
, alt_cost
;
1616 cost
= mips_build_shift (codes
, value
);
1617 alt_cost
= mips_build_lower (alt_codes
, value
);
1618 if (alt_cost
< cost
)
1620 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1627 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1630 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1632 return mips_const_insns (x
) > 0;
1635 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1638 mips16_stub_function (const char *name
)
1642 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1643 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1647 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1648 support function. */
1651 mips16_stub_call_address (mips_one_only_stub
*stub
)
1653 rtx fn
= mips16_stub_function (stub
->get_name ());
1654 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
1655 if (!call_insn_operand (fn
, VOIDmode
))
1656 fn
= force_reg (Pmode
, fn
);
1660 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1662 class mips16_rdhwr_one_only_stub
: public mips_one_only_stub
1664 virtual const char *get_name ();
1665 virtual void output_body ();
1669 mips16_rdhwr_one_only_stub::get_name ()
1671 return "__mips16_rdhwr";
1675 mips16_rdhwr_one_only_stub::output_body ()
1677 fprintf (asm_out_file
,
1679 "\t.set\tmips32r2\n"
1680 "\t.set\tnoreorder\n"
1686 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1687 class mips16_get_fcsr_one_only_stub
: public mips_one_only_stub
1689 virtual const char *get_name ();
1690 virtual void output_body ();
1694 mips16_get_fcsr_one_only_stub::get_name ()
1696 return "__mips16_get_fcsr";
1700 mips16_get_fcsr_one_only_stub::output_body ()
1702 fprintf (asm_out_file
,
1704 "\tj\t$31\n", reg_names
[GET_FCSR_REGNUM
]);
1707 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1708 class mips16_set_fcsr_one_only_stub
: public mips_one_only_stub
1710 virtual const char *get_name ();
1711 virtual void output_body ();
1715 mips16_set_fcsr_one_only_stub::get_name ()
1717 return "__mips16_set_fcsr";
1721 mips16_set_fcsr_one_only_stub::output_body ()
1723 fprintf (asm_out_file
,
1725 "\tj\t$31\n", reg_names
[SET_FCSR_REGNUM
]);
1728 /* Return true if symbols of type TYPE require a GOT access. */
1731 mips_got_symbol_type_p (enum mips_symbol_type type
)
1735 case SYMBOL_GOT_PAGE_OFST
:
1736 case SYMBOL_GOT_DISP
:
1744 /* Return true if X is a thread-local symbol. */
1747 mips_tls_symbol_p (rtx x
)
1749 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1752 /* Return true if SYMBOL_REF X is associated with a global symbol
1753 (in the STB_GLOBAL sense). */
1756 mips_global_symbol_p (const_rtx x
)
1758 const_tree decl
= SYMBOL_REF_DECL (x
);
1761 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1763 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1764 or weak symbols. Relocations in the object file will be against
1765 the target symbol, so it's that symbol's binding that matters here. */
1766 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1769 /* Return true if function X is a libgcc MIPS16 stub function. */
1772 mips16_stub_function_p (const_rtx x
)
1774 return (GET_CODE (x
) == SYMBOL_REF
1775 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1778 /* Return true if function X is a locally-defined and locally-binding
1782 mips16_local_function_p (const_rtx x
)
1784 return (GET_CODE (x
) == SYMBOL_REF
1785 && SYMBOL_REF_LOCAL_P (x
)
1786 && !SYMBOL_REF_EXTERNAL_P (x
)
1787 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1790 /* Return true if SYMBOL_REF X binds locally. */
1793 mips_symbol_binds_local_p (const_rtx x
)
1795 return (SYMBOL_REF_DECL (x
)
1796 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1797 : SYMBOL_REF_LOCAL_P (x
));
1800 /* Return true if rtx constants of mode MODE should be put into a small
1804 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1806 return (!TARGET_EMBEDDED_DATA
1807 && TARGET_LOCAL_SDATA
1808 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1811 /* Return true if X should not be moved directly into register $25.
1812 We need this because many versions of GAS will treat "la $25,foo" as
1813 part of a call sequence and so allow a global "foo" to be lazily bound. */
1816 mips_dangerous_for_la25_p (rtx x
)
1818 return (!TARGET_EXPLICIT_RELOCS
1820 && GET_CODE (x
) == SYMBOL_REF
1821 && mips_global_symbol_p (x
));
1824 /* Return true if calls to X might need $25 to be valid on entry. */
1827 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1829 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1832 /* MIPS16 stub functions are guaranteed not to use $25. */
1833 if (mips16_stub_function_p (x
))
1836 if (GET_CODE (x
) == SYMBOL_REF
)
1838 /* If PLTs and copy relocations are available, the static linker
1839 will make sure that $25 is valid on entry to the target function. */
1840 if (TARGET_ABICALLS_PIC0
)
1843 /* Locally-defined functions use absolute accesses to set up
1844 the global pointer. */
1845 if (TARGET_ABSOLUTE_ABICALLS
1846 && mips_symbol_binds_local_p (x
)
1847 && !SYMBOL_REF_EXTERNAL_P (x
))
1854 /* Return the method that should be used to access SYMBOL_REF or
1855 LABEL_REF X in context CONTEXT. */
1857 static enum mips_symbol_type
1858 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1861 return SYMBOL_GOT_DISP
;
1863 if (GET_CODE (x
) == LABEL_REF
)
1865 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1866 code and if we know that the label is in the current function's
1867 text section. LABEL_REFs are used for jump tables as well as
1868 text labels, so we must check whether jump tables live in the
1870 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1871 && !LABEL_REF_NONLOCAL_P (x
))
1872 return SYMBOL_PC_RELATIVE
;
1874 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1875 return SYMBOL_GOT_PAGE_OFST
;
1877 return SYMBOL_ABSOLUTE
;
1880 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1882 if (SYMBOL_REF_TLS_MODEL (x
))
1885 if (CONSTANT_POOL_ADDRESS_P (x
))
1887 if (TARGET_MIPS16_TEXT_LOADS
)
1888 return SYMBOL_PC_RELATIVE
;
1890 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1891 return SYMBOL_PC_RELATIVE
;
1893 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1894 return SYMBOL_GP_RELATIVE
;
1897 /* Do not use small-data accesses for weak symbols; they may end up
1899 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1900 return SYMBOL_GP_RELATIVE
;
1902 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1904 if (TARGET_ABICALLS_PIC2
1905 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1907 /* There are three cases to consider:
1909 - o32 PIC (either with or without explicit relocs)
1910 - n32/n64 PIC without explicit relocs
1911 - n32/n64 PIC with explicit relocs
1913 In the first case, both local and global accesses will use an
1914 R_MIPS_GOT16 relocation. We must correctly predict which of
1915 the two semantics (local or global) the assembler and linker
1916 will apply. The choice depends on the symbol's binding rather
1917 than its visibility.
1919 In the second case, the assembler will not use R_MIPS_GOT16
1920 relocations, but it chooses between local and global accesses
1921 in the same way as for o32 PIC.
1923 In the third case we have more freedom since both forms of
1924 access will work for any kind of symbol. However, there seems
1925 little point in doing things differently. */
1926 if (mips_global_symbol_p (x
))
1927 return SYMBOL_GOT_DISP
;
1929 return SYMBOL_GOT_PAGE_OFST
;
1932 return SYMBOL_ABSOLUTE
;
1935 /* Classify the base of symbolic expression X, given that X appears in
1938 static enum mips_symbol_type
1939 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1943 split_const (x
, &x
, &offset
);
1944 if (UNSPEC_ADDRESS_P (x
))
1945 return UNSPEC_ADDRESS_TYPE (x
);
1947 return mips_classify_symbol (x
, context
);
1950 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1951 is the alignment in bytes of SYMBOL_REF X. */
1954 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1956 HOST_WIDE_INT align
;
1958 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1959 return IN_RANGE (offset
, 0, align
- 1);
1962 /* Return true if X is a symbolic constant that can be used in context
1963 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1966 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1967 enum mips_symbol_type
*symbol_type
)
1971 split_const (x
, &x
, &offset
);
1972 if (UNSPEC_ADDRESS_P (x
))
1974 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1975 x
= UNSPEC_ADDRESS (x
);
1977 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1979 *symbol_type
= mips_classify_symbol (x
, context
);
1980 if (*symbol_type
== SYMBOL_TLS
)
1986 if (offset
== const0_rtx
)
1989 /* Check whether a nonzero offset is valid for the underlying
1991 switch (*symbol_type
)
1993 case SYMBOL_ABSOLUTE
:
1994 case SYMBOL_64_HIGH
:
1997 /* If the target has 64-bit pointers and the object file only
1998 supports 32-bit symbols, the values of those symbols will be
1999 sign-extended. In this case we can't allow an arbitrary offset
2000 in case the 32-bit value X + OFFSET has a different sign from X. */
2001 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
2002 return offset_within_block_p (x
, INTVAL (offset
));
2004 /* In other cases the relocations can handle any offset. */
2007 case SYMBOL_PC_RELATIVE
:
2008 /* Allow constant pool references to be converted to LABEL+CONSTANT.
2009 In this case, we no longer have access to the underlying constant,
2010 but the original symbol-based access was known to be valid. */
2011 if (GET_CODE (x
) == LABEL_REF
)
2016 case SYMBOL_GP_RELATIVE
:
2017 /* Make sure that the offset refers to something within the
2018 same object block. This should guarantee that the final
2019 PC- or GP-relative offset is within the 16-bit limit. */
2020 return offset_within_block_p (x
, INTVAL (offset
));
2022 case SYMBOL_GOT_PAGE_OFST
:
2023 case SYMBOL_GOTOFF_PAGE
:
2024 /* If the symbol is global, the GOT entry will contain the symbol's
2025 address, and we will apply a 16-bit offset after loading it.
2026 If the symbol is local, the linker should provide enough local
2027 GOT entries for a 16-bit offset, but larger offsets may lead
2029 return SMALL_INT (offset
);
2033 /* There is no carry between the HI and LO REL relocations, so the
2034 offset is only valid if we know it won't lead to such a carry. */
2035 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
2037 case SYMBOL_GOT_DISP
:
2038 case SYMBOL_GOTOFF_DISP
:
2039 case SYMBOL_GOTOFF_CALL
:
2040 case SYMBOL_GOTOFF_LOADGP
:
2043 case SYMBOL_GOTTPREL
:
2051 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2052 single instruction. We rely on the fact that, in the worst case,
2053 all instructions involved in a MIPS16 address calculation are usually
2057 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
2059 if (mips_use_pcrel_pool_p
[(int) type
])
2061 if (mode
== MAX_MACHINE_MODE
)
2062 /* LEAs will be converted into constant-pool references by
2064 type
= SYMBOL_PC_RELATIVE
;
2066 /* The constant must be loaded and then dereferenced. */
2072 case SYMBOL_ABSOLUTE
:
2073 /* When using 64-bit symbols, we need 5 preparatory instructions,
2076 lui $at,%highest(symbol)
2077 daddiu $at,$at,%higher(symbol)
2079 daddiu $at,$at,%hi(symbol)
2082 The final address is then $at + %lo(symbol). With 32-bit
2083 symbols we just need a preparatory LUI for normal mode and
2084 a preparatory LI and SLL for MIPS16. */
2085 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
2087 case SYMBOL_GP_RELATIVE
:
2088 /* Treat GP-relative accesses as taking a single instruction on
2089 MIPS16 too; the copy of $gp can often be shared. */
2092 case SYMBOL_PC_RELATIVE
:
2093 /* PC-relative constants can be only be used with ADDIUPC,
2094 DADDIUPC, LWPC and LDPC. */
2095 if (mode
== MAX_MACHINE_MODE
2096 || GET_MODE_SIZE (mode
) == 4
2097 || GET_MODE_SIZE (mode
) == 8)
2100 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2103 case SYMBOL_GOT_DISP
:
2104 /* The constant will have to be loaded from the GOT before it
2105 is used in an address. */
2106 if (mode
!= MAX_MACHINE_MODE
)
2111 case SYMBOL_GOT_PAGE_OFST
:
2112 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2113 local/global classification is accurate. The worst cases are:
2115 (1) For local symbols when generating o32 or o64 code. The assembler
2121 ...and the final address will be $at + %lo(symbol).
2123 (2) For global symbols when -mxgot. The assembler will use:
2125 lui $at,%got_hi(symbol)
2128 ...and the final address will be $at + %got_lo(symbol). */
2131 case SYMBOL_GOTOFF_PAGE
:
2132 case SYMBOL_GOTOFF_DISP
:
2133 case SYMBOL_GOTOFF_CALL
:
2134 case SYMBOL_GOTOFF_LOADGP
:
2135 case SYMBOL_64_HIGH
:
2141 case SYMBOL_GOTTPREL
:
2144 /* A 16-bit constant formed by a single relocation, or a 32-bit
2145 constant formed from a high 16-bit relocation and a low 16-bit
2146 relocation. Use mips_split_p to determine which. 32-bit
2147 constants need an "lui; addiu" sequence for normal mode and
2148 an "li; sll; addiu" sequence for MIPS16 mode. */
2149 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2152 /* We don't treat a bare TLS symbol as a constant. */
2158 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2159 to load symbols of type TYPE into a register. Return 0 if the given
2160 type of symbol cannot be used as an immediate operand.
2162 Otherwise, return the number of instructions needed to load or store
2163 values of mode MODE to or from addresses of type TYPE. Return 0 if
2164 the given type of symbol is not valid in addresses.
2166 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2169 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
2171 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2174 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2177 mips_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2179 enum mips_symbol_type type
;
2182 /* There is no assembler syntax for expressing an address-sized
2184 if (GET_CODE (x
) == HIGH
)
2187 /* As an optimization, reject constants that mips_legitimize_move
2190 Suppose we have a multi-instruction sequence that loads constant C
2191 into register R. If R does not get allocated a hard register, and
2192 R is used in an operand that allows both registers and memory
2193 references, reload will consider forcing C into memory and using
2194 one of the instruction's memory alternatives. Returning false
2195 here will force it to use an input reload instead. */
2196 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2199 split_const (x
, &base
, &offset
);
2200 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2202 /* See whether we explicitly want these symbols in the pool. */
2203 if (mips_use_pcrel_pool_p
[(int) type
])
2206 /* The same optimization as for CONST_INT. */
2207 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2210 /* If MIPS16 constant pools live in the text section, they should
2211 not refer to anything that might need run-time relocation. */
2212 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2216 /* TLS symbols must be computed by mips_legitimize_move. */
2217 if (tls_referenced_p (x
))
2223 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2224 constants when we're using a per-function constant pool. */
2227 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2228 const_rtx x ATTRIBUTE_UNUSED
)
2230 return !TARGET_MIPS16_PCREL_LOADS
;
2233 /* Return true if register REGNO is a valid base register for mode MODE.
2234 STRICT_P is true if REG_OK_STRICT is in effect. */
2237 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
2240 if (!HARD_REGISTER_NUM_P (regno
))
2244 regno
= reg_renumber
[regno
];
2247 /* These fake registers will be eliminated to either the stack or
2248 hard frame pointer, both of which are usually valid base registers.
2249 Reload deals with the cases where the eliminated form isn't valid. */
2250 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2253 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2254 values, nothing smaller. */
2255 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2256 return GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2258 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2261 /* Return true if X is a valid base register for mode MODE.
2262 STRICT_P is true if REG_OK_STRICT is in effect. */
2265 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2267 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2271 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2274 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2275 can address a value of mode MODE. */
2278 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2280 /* Check that X is a signed 16-bit number. */
2281 if (!const_arith_operand (x
, Pmode
))
2284 /* We may need to split multiword moves, so make sure that every word
2286 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2287 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2293 /* Return true if a LO_SUM can address a value of mode MODE when the
2294 LO_SUM symbol has type SYMBOL_TYPE. */
2297 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2299 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2301 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2304 /* Check that there is a known low-part relocation. */
2305 if (mips_lo_relocs
[symbol_type
] == NULL
)
2308 /* We may need to split multiword moves, so make sure that each word
2309 can be accessed without inducing a carry. This is mainly needed
2310 for o64, which has historically only guaranteed 64-bit alignment
2311 for 128-bit types. */
2312 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2313 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2319 /* Return true if X is a valid address for machine mode MODE. If it is,
2320 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2324 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2325 enum machine_mode mode
, bool strict_p
)
2327 switch (GET_CODE (x
))
2331 info
->type
= ADDRESS_REG
;
2333 info
->offset
= const0_rtx
;
2334 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2337 info
->type
= ADDRESS_REG
;
2338 info
->reg
= XEXP (x
, 0);
2339 info
->offset
= XEXP (x
, 1);
2340 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2341 && mips_valid_offset_p (info
->offset
, mode
));
2344 info
->type
= ADDRESS_LO_SUM
;
2345 info
->reg
= XEXP (x
, 0);
2346 info
->offset
= XEXP (x
, 1);
2347 /* We have to trust the creator of the LO_SUM to do something vaguely
2348 sane. Target-independent code that creates a LO_SUM should also
2349 create and verify the matching HIGH. Target-independent code that
2350 adds an offset to a LO_SUM must prove that the offset will not
2351 induce a carry. Failure to do either of these things would be
2352 a bug, and we are not required to check for it here. The MIPS
2353 backend itself should only create LO_SUMs for valid symbolic
2354 constants, with the high part being either a HIGH or a copy
2357 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2358 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2359 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2362 /* Small-integer addresses don't occur very often, but they
2363 are legitimate if $0 is a valid base register. */
2364 info
->type
= ADDRESS_CONST_INT
;
2365 return !TARGET_MIPS16
&& SMALL_INT (x
);
2370 info
->type
= ADDRESS_SYMBOLIC
;
2371 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2373 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2374 && !mips_split_p
[info
->symbol_type
]);
2381 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2384 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2386 struct mips_address_info addr
;
2388 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2391 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2394 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2396 struct mips_address_info addr
;
2398 return (mips_classify_address (&addr
, x
, mode
, false)
2399 && addr
.type
== ADDRESS_REG
2400 && addr
.reg
== stack_pointer_rtx
);
2403 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2404 address instruction. Note that such addresses are not considered
2405 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2406 is so restricted. */
2409 mips_lwxs_address_p (rtx addr
)
2412 && GET_CODE (addr
) == PLUS
2413 && REG_P (XEXP (addr
, 1)))
2415 rtx offset
= XEXP (addr
, 0);
2416 if (GET_CODE (offset
) == MULT
2417 && REG_P (XEXP (offset
, 0))
2418 && CONST_INT_P (XEXP (offset
, 1))
2419 && INTVAL (XEXP (offset
, 1)) == 4)
2425 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2426 indexed address instruction. Note that such addresses are
2427 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2428 sense, because their use is so restricted. */
2431 mips_lx_address_p (rtx addr
, enum machine_mode mode
)
2433 if (GET_CODE (addr
) != PLUS
2434 || !REG_P (XEXP (addr
, 0))
2435 || !REG_P (XEXP (addr
, 1)))
2437 if (ISA_HAS_LBX
&& mode
== QImode
)
2439 if (ISA_HAS_LHX
&& mode
== HImode
)
2441 if (ISA_HAS_LWX
&& mode
== SImode
)
2443 if (ISA_HAS_LDX
&& mode
== DImode
)
2448 /* Return true if a value at OFFSET bytes from base register BASE can be
2449 accessed using an unextended MIPS16 instruction. MODE is the mode of
2452 Usually the offset in an unextended instruction is a 5-bit field.
2453 The offset is unsigned and shifted left once for LH and SH, twice
2454 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2455 an 8-bit immediate field that's shifted left twice. */
2458 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2459 unsigned HOST_WIDE_INT offset
)
2461 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2463 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2464 return offset
< 256U * GET_MODE_SIZE (mode
);
2465 return offset
< 32U * GET_MODE_SIZE (mode
);
2470 /* Return the number of instructions needed to load or store a value
2471 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2472 length of one instruction. Return 0 if X isn't valid for MODE.
2473 Assume that multiword moves may need to be split into word moves
2474 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2478 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2480 struct mips_address_info addr
;
2483 /* BLKmode is used for single unaligned loads and stores and should
2484 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2485 meaningless, so we have to single it out as a special case one way
2487 if (mode
!= BLKmode
&& might_split_p
)
2488 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2492 if (mips_classify_address (&addr
, x
, mode
, false))
2497 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2498 UINTVAL (addr
.offset
)))
2502 case ADDRESS_LO_SUM
:
2503 return TARGET_MIPS16
? factor
* 2 : factor
;
2505 case ADDRESS_CONST_INT
:
2508 case ADDRESS_SYMBOLIC
:
2509 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2514 /* Return true if X fits within an unsigned field of BITS bits that is
2515 shifted left SHIFT bits before being used. */
2518 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2520 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2523 /* Return true if X fits within a signed field of BITS bits that is
2524 shifted left SHIFT bits before being used. */
2527 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2529 x
+= 1 << (bits
+ shift
- 1);
2530 return mips_unsigned_immediate_p (x
, bits
, shift
);
2533 /* Return true if X is legitimate for accessing values of mode MODE,
2534 if it is based on a MIPS16 register, and if the offset satisfies
2535 OFFSET_PREDICATE. */
2538 m16_based_address_p (rtx x
, enum machine_mode mode
,
2539 insn_operand_predicate_fn offset_predicate
)
2541 struct mips_address_info addr
;
2543 return (mips_classify_address (&addr
, x
, mode
, false)
2544 && addr
.type
== ADDRESS_REG
2545 && M16_REG_P (REGNO (addr
.reg
))
2546 && offset_predicate (addr
.offset
, mode
));
2549 /* Return true if X is a legitimate address that conforms to the requirements
2550 for a microMIPS LWSP or SWSP insn. */
2553 lwsp_swsp_address_p (rtx x
, enum machine_mode mode
)
2555 struct mips_address_info addr
;
2557 return (mips_classify_address (&addr
, x
, mode
, false)
2558 && addr
.type
== ADDRESS_REG
2559 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2560 && uw5_operand (addr
.offset
, mode
));
2563 /* Return true if X is a legitimate address with a 12-bit offset.
2564 MODE is the mode of the value being accessed. */
2567 umips_12bit_offset_address_p (rtx x
, enum machine_mode mode
)
2569 struct mips_address_info addr
;
2571 return (mips_classify_address (&addr
, x
, mode
, false)
2572 && addr
.type
== ADDRESS_REG
2573 && CONST_INT_P (addr
.offset
)
2574 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2577 /* Return the number of instructions needed to load constant X,
2578 assuming that BASE_INSN_LENGTH is the length of one instruction.
2579 Return 0 if X isn't a valid constant. */
2582 mips_const_insns (rtx x
)
2584 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2585 enum mips_symbol_type symbol_type
;
2588 switch (GET_CODE (x
))
2591 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2593 || !mips_split_p
[symbol_type
])
2596 /* This is simply an LUI for normal mode. It is an extended
2597 LI followed by an extended SLL for MIPS16. */
2598 return TARGET_MIPS16
? 4 : 1;
2602 /* Unsigned 8-bit constants can be loaded using an unextended
2603 LI instruction. Unsigned 16-bit constants can be loaded
2604 using an extended LI. Negative constants must be loaded
2605 using LI and then negated. */
2606 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2607 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2608 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2609 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2612 return mips_build_integer (codes
, INTVAL (x
));
2616 /* Allow zeros for normal mode, where we can use $0. */
2617 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2623 /* See if we can refer to X directly. */
2624 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2625 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2627 /* Otherwise try splitting the constant into a base and offset.
2628 If the offset is a 16-bit value, we can load the base address
2629 into a register and then use (D)ADDIU to add in the offset.
2630 If the offset is larger, we can load the base and offset
2631 into separate registers and add them together with (D)ADDU.
2632 However, the latter is only possible before reload; during
2633 and after reload, we must have the option of forcing the
2634 constant into the pool instead. */
2635 split_const (x
, &x
, &offset
);
2638 int n
= mips_const_insns (x
);
2641 if (SMALL_INT (offset
))
2643 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2644 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2651 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2659 /* X is a doubleword constant that can be handled by splitting it into
2660 two words and loading each word separately. Return the number of
2661 instructions required to do this, assuming that BASE_INSN_LENGTH
2662 is the length of one instruction. */
2665 mips_split_const_insns (rtx x
)
2667 unsigned int low
, high
;
2669 low
= mips_const_insns (mips_subword (x
, false));
2670 high
= mips_const_insns (mips_subword (x
, true));
2671 gcc_assert (low
> 0 && high
> 0);
2675 /* Return the number of instructions needed to implement INSN,
2676 given that it loads from or stores to MEM. Assume that
2677 BASE_INSN_LENGTH is the length of one instruction. */
2680 mips_load_store_insns (rtx mem
, rtx_insn
*insn
)
2682 enum machine_mode mode
;
2686 gcc_assert (MEM_P (mem
));
2687 mode
= GET_MODE (mem
);
2689 /* Try to prove that INSN does not need to be split. */
2690 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2693 set
= single_set (insn
);
2694 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2695 might_split_p
= false;
2698 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2701 /* Return the number of instructions needed for an integer division,
2702 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2705 mips_idiv_insns (void)
2710 if (TARGET_CHECK_ZERO_DIV
)
2712 if (GENERATE_DIVIDE_TRAPS
)
2718 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2723 /* Emit a move from SRC to DEST. Assume that the move expanders can
2724 handle all moves if !can_create_pseudo_p (). The distinction is
2725 important because, unlike emit_move_insn, the move expanders know
2726 how to force Pmode objects into the constant pool even when the
2727 constant pool address is not itself legitimate. */
2730 mips_emit_move (rtx dest
, rtx src
)
2732 return (can_create_pseudo_p ()
2733 ? emit_move_insn (dest
, src
)
2734 : emit_move_insn_1 (dest
, src
));
2737 /* Emit a move from SRC to DEST, splitting compound moves into individual
2738 instructions. SPLIT_TYPE is the type of split to perform. */
2741 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
2743 if (mips_split_move_p (dest
, src
, split_type
))
2744 mips_split_move (dest
, src
, split_type
);
2746 mips_emit_move (dest
, src
);
2749 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2752 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2754 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2755 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2758 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2759 Return that new register. */
2762 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2766 reg
= gen_reg_rtx (mode
);
2767 mips_emit_unary (code
, reg
, op0
);
2771 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2774 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2776 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2777 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2780 /* Compute (CODE OP0 OP1) and store the result in a new register
2781 of mode MODE. Return that new register. */
2784 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2788 reg
= gen_reg_rtx (mode
);
2789 mips_emit_binary (code
, reg
, op0
, op1
);
2793 /* Copy VALUE to a register and return that register. If new pseudos
2794 are allowed, copy it into a new register, otherwise use DEST. */
2797 mips_force_temporary (rtx dest
, rtx value
)
2799 if (can_create_pseudo_p ())
2800 return force_reg (Pmode
, value
);
2803 mips_emit_move (dest
, value
);
2808 /* Emit a call sequence with call pattern PATTERN and return the call
2809 instruction itself (which is not necessarily the last instruction
2810 emitted). ORIG_ADDR is the original, unlegitimized address,
2811 ADDR is the legitimized form, and LAZY_P is true if the call
2812 address is lazily-bound. */
2815 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2820 insn
= emit_call_insn (pattern
);
2822 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2824 /* MIPS16 JALRs only take MIPS16 registers. If the target
2825 function requires $25 to be valid on entry, we must copy it
2826 there separately. The move instruction can be put in the
2827 call's delay slot. */
2828 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2829 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2830 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2834 /* Lazy-binding stubs require $gp to be valid on entry. */
2835 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2839 /* See the comment above load_call<mode> for details. */
2840 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2841 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2842 emit_insn (gen_update_got_version ());
2846 && TARGET_EXPLICIT_RELOCS
2847 && TARGET_CALL_CLOBBERED_GP
)
2849 rtx post_call_tmp_reg
= gen_rtx_REG (word_mode
, POST_CALL_TMP_REG
);
2850 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn
), post_call_tmp_reg
);
2856 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2857 then add CONST_INT OFFSET to the result. */
2860 mips_unspec_address_offset (rtx base
, rtx offset
,
2861 enum mips_symbol_type symbol_type
)
2863 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2864 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2865 if (offset
!= const0_rtx
)
2866 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2867 return gen_rtx_CONST (Pmode
, base
);
2870 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2871 type SYMBOL_TYPE. */
2874 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2878 split_const (address
, &base
, &offset
);
2879 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2882 /* If OP is an UNSPEC address, return the address to which it refers,
2883 otherwise return OP itself. */
2886 mips_strip_unspec_address (rtx op
)
2890 split_const (op
, &base
, &offset
);
2891 if (UNSPEC_ADDRESS_P (base
))
2892 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2896 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2897 high part to BASE and return the result. Just return BASE otherwise.
2898 TEMP is as for mips_force_temporary.
2900 The returned expression can be used as the first operand to a LO_SUM. */
2903 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2904 enum mips_symbol_type symbol_type
)
2906 if (mips_split_p
[symbol_type
])
2908 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2909 addr
= mips_force_temporary (temp
, addr
);
2910 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2915 /* Return an instruction that copies $gp into register REG. We want
2916 GCC to treat the register's value as constant, so that its value
2917 can be rematerialized on demand. */
2920 gen_load_const_gp (rtx reg
)
2922 return PMODE_INSN (gen_load_const_gp
, (reg
));
2925 /* Return a pseudo register that contains the value of $gp throughout
2926 the current function. Such registers are needed by MIPS16 functions,
2927 for which $gp itself is not a valid base register or addition operand. */
2930 mips16_gp_pseudo_reg (void)
2932 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2936 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2938 push_topmost_sequence ();
2940 scan
= get_insns ();
2941 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2942 scan
= NEXT_INSN (scan
);
2944 rtx set
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2945 rtx_insn
*insn
= emit_insn_after (set
, scan
);
2946 INSN_LOCATION (insn
) = 0;
2948 pop_topmost_sequence ();
2951 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2954 /* Return a base register that holds pic_offset_table_rtx.
2955 TEMP, if nonnull, is a scratch Pmode base register. */
2958 mips_pic_base_register (rtx temp
)
2961 return pic_offset_table_rtx
;
2963 if (currently_expanding_to_rtl
)
2964 return mips16_gp_pseudo_reg ();
2966 if (can_create_pseudo_p ())
2967 temp
= gen_reg_rtx (Pmode
);
2970 /* The first post-reload split exposes all references to $gp
2971 (both uses and definitions). All references must remain
2972 explicit after that point.
2974 It is safe to introduce uses of $gp at any time, so for
2975 simplicity, we do that before the split too. */
2976 mips_emit_move (temp
, pic_offset_table_rtx
);
2978 emit_insn (gen_load_const_gp (temp
));
2982 /* Return the RHS of a load_call<mode> insn. */
2985 mips_unspec_call (rtx reg
, rtx symbol
)
2989 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
2990 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
2993 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2994 reference. Return NULL_RTX otherwise. */
2997 mips_strip_unspec_call (rtx src
)
2999 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
3000 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
3004 /* Create and return a GOT reference of type TYPE for address ADDR.
3005 TEMP, if nonnull, is a scratch Pmode base register. */
3008 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
3010 rtx base
, high
, lo_sum_symbol
;
3012 base
= mips_pic_base_register (temp
);
3014 /* If we used the temporary register to load $gp, we can't use
3015 it for the high part as well. */
3016 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
3019 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
3020 lo_sum_symbol
= mips_unspec_address (addr
, type
);
3022 if (type
== SYMBOL_GOTOFF_CALL
)
3023 return mips_unspec_call (high
, lo_sum_symbol
);
3025 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
3028 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3029 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3030 constant in that context and can be split into high and low parts.
3031 If so, and if LOW_OUT is nonnull, emit the high part and store the
3032 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3034 TEMP is as for mips_force_temporary and is used to load the high
3035 part into a register.
3037 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3038 a legitimize SET_SRC for an .md pattern, otherwise the low part
3039 is guaranteed to be a legitimate address for mode MODE. */
3042 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
3044 enum mips_symbol_context context
;
3045 enum mips_symbol_type symbol_type
;
3048 context
= (mode
== MAX_MACHINE_MODE
3049 ? SYMBOL_CONTEXT_LEA
3050 : SYMBOL_CONTEXT_MEM
);
3051 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
3053 addr
= XEXP (addr
, 0);
3054 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3055 && mips_symbol_insns (symbol_type
, mode
) > 0
3056 && mips_split_hi_p
[symbol_type
])
3059 switch (symbol_type
)
3061 case SYMBOL_GOT_PAGE_OFST
:
3062 /* The high part of a page/ofst pair is loaded from the GOT. */
3063 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
3074 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3075 && mips_symbol_insns (symbol_type
, mode
) > 0
3076 && mips_split_p
[symbol_type
])
3079 switch (symbol_type
)
3081 case SYMBOL_GOT_DISP
:
3082 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3083 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
3086 case SYMBOL_GP_RELATIVE
:
3087 high
= mips_pic_base_register (temp
);
3088 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3092 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
3093 high
= mips_force_temporary (temp
, high
);
3094 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3103 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3104 mips_force_temporary; it is only needed when OFFSET is not a
3108 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
3110 if (!SMALL_OPERAND (offset
))
3116 /* Load the full offset into a register so that we can use
3117 an unextended instruction for the address itself. */
3118 high
= GEN_INT (offset
);
3123 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3124 The addition inside the macro CONST_HIGH_PART may cause an
3125 overflow, so we need to force a sign-extension check. */
3126 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
3127 offset
= CONST_LOW_PART (offset
);
3129 high
= mips_force_temporary (temp
, high
);
3130 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
3132 return plus_constant (Pmode
, reg
, offset
);
3135 /* The __tls_get_attr symbol. */
3136 static GTY(()) rtx mips_tls_symbol
;
3138 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3139 the TLS symbol we are referencing and TYPE is the symbol type to use
3140 (either global dynamic or local dynamic). V0 is an RTX for the
3141 return value location. */
3144 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3148 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3150 if (!mips_tls_symbol
)
3151 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3153 loc
= mips_unspec_address (sym
, type
);
3157 emit_insn (gen_rtx_SET (Pmode
, a0
,
3158 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
3159 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3160 const0_rtx
, NULL_RTX
, false);
3161 RTL_CONST_CALL_P (insn
) = 1;
3162 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3163 insn
= get_insns ();
3170 /* Return a pseudo register that contains the current thread pointer. */
3173 mips_expand_thread_pointer (rtx tp
)
3179 if (!mips16_rdhwr_stub
)
3180 mips16_rdhwr_stub
= new mips16_rdhwr_one_only_stub ();
3181 fn
= mips16_stub_call_address (mips16_rdhwr_stub
);
3182 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3185 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3192 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3195 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3196 its address. The return value will be both a valid address and a valid
3197 SET_SRC (either a REG or a LO_SUM). */
3200 mips_legitimize_tls_address (rtx loc
)
3202 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3203 enum tls_model model
;
3205 model
= SYMBOL_REF_TLS_MODEL (loc
);
3206 /* Only TARGET_ABICALLS code can have more than one module; other
3207 code must be be static and should not use a GOT. All TLS models
3208 reduce to local exec in this situation. */
3209 if (!TARGET_ABICALLS
)
3210 model
= TLS_MODEL_LOCAL_EXEC
;
3214 case TLS_MODEL_GLOBAL_DYNAMIC
:
3215 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3216 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3217 dest
= gen_reg_rtx (Pmode
);
3218 emit_libcall_block (insn
, dest
, v0
, loc
);
3221 case TLS_MODEL_LOCAL_DYNAMIC
:
3222 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3223 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3224 tmp1
= gen_reg_rtx (Pmode
);
3226 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3227 share the LDM result with other LD model accesses. */
3228 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3230 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3232 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3233 if (mips_split_p
[SYMBOL_DTPREL
])
3235 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3236 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3239 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3240 0, 0, OPTAB_DIRECT
);
3243 case TLS_MODEL_INITIAL_EXEC
:
3244 tp
= mips_get_tp ();
3245 tmp1
= gen_reg_rtx (Pmode
);
3246 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3247 if (Pmode
== DImode
)
3248 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3250 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3251 dest
= gen_reg_rtx (Pmode
);
3252 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3255 case TLS_MODEL_LOCAL_EXEC
:
3256 tmp1
= mips_get_tp ();
3257 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3258 if (mips_split_p
[SYMBOL_TPREL
])
3260 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3261 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3264 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3265 0, 0, OPTAB_DIRECT
);
3274 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3278 mips16_expand_get_fcsr (rtx target
)
3280 if (!mips16_get_fcsr_stub
)
3281 mips16_get_fcsr_stub
= new mips16_get_fcsr_one_only_stub ();
3282 rtx fn
= mips16_stub_call_address (mips16_get_fcsr_stub
);
3283 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16
, (fn
)));
3284 emit_move_insn (target
, gen_rtx_REG (SImode
, GET_FCSR_REGNUM
));
3287 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3290 mips16_expand_set_fcsr (rtx newval
)
3292 if (!mips16_set_fcsr_stub
)
3293 mips16_set_fcsr_stub
= new mips16_set_fcsr_one_only_stub ();
3294 rtx fn
= mips16_stub_call_address (mips16_set_fcsr_stub
);
3295 emit_move_insn (gen_rtx_REG (SImode
, SET_FCSR_REGNUM
), newval
);
3296 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16
, (fn
)));
3299 /* If X is not a valid address for mode MODE, force it into a register. */
3302 mips_force_address (rtx x
, enum machine_mode mode
)
3304 if (!mips_legitimate_address_p (mode
, x
, false))
3305 x
= force_reg (Pmode
, x
);
3309 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3310 be legitimized in a way that the generic machinery might not expect,
3311 return a new address, otherwise return NULL. MODE is the mode of
3312 the memory being accessed. */
3315 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3316 enum machine_mode mode
)
3319 HOST_WIDE_INT offset
;
3321 if (mips_tls_symbol_p (x
))
3322 return mips_legitimize_tls_address (x
);
3324 /* See if the address can split into a high part and a LO_SUM. */
3325 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3326 return mips_force_address (addr
, mode
);
3328 /* Handle BASE + OFFSET using mips_add_offset. */
3329 mips_split_plus (x
, &base
, &offset
);
3332 if (!mips_valid_base_register_p (base
, mode
, false))
3333 base
= copy_to_mode_reg (Pmode
, base
);
3334 addr
= mips_add_offset (NULL
, base
, offset
);
3335 return mips_force_address (addr
, mode
);
3341 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3344 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3346 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3347 enum machine_mode mode
;
3348 unsigned int i
, num_ops
;
3351 mode
= GET_MODE (dest
);
3352 num_ops
= mips_build_integer (codes
, value
);
3354 /* Apply each binary operation to X. Invariant: X is a legitimate
3355 source operand for a SET pattern. */
3356 x
= GEN_INT (codes
[0].value
);
3357 for (i
= 1; i
< num_ops
; i
++)
3359 if (!can_create_pseudo_p ())
3361 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
3365 x
= force_reg (mode
, x
);
3366 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3369 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
3372 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3373 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3377 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
3381 /* Split moves of big integers into smaller pieces. */
3382 if (splittable_const_int_operand (src
, mode
))
3384 mips_move_integer (dest
, dest
, INTVAL (src
));
3388 /* Split moves of symbolic constants into high/low pairs. */
3389 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3391 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3395 /* Generate the appropriate access sequences for TLS symbols. */
3396 if (mips_tls_symbol_p (src
))
3398 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3402 /* If we have (const (plus symbol offset)), and that expression cannot
3403 be forced into memory, load the symbol first and add in the offset.
3404 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3405 forced into memory, as it usually produces better code. */
3406 split_const (src
, &base
, &offset
);
3407 if (offset
!= const0_rtx
3408 && (targetm
.cannot_force_const_mem (mode
, src
)
3409 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3411 base
= mips_force_temporary (dest
, base
);
3412 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3416 src
= force_const_mem (mode
, src
);
3418 /* When using explicit relocs, constant pool references are sometimes
3419 not legitimate addresses. */
3420 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3421 mips_emit_move (dest
, src
);
3424 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3425 sequence that is valid. */
3428 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
3430 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3432 mips_emit_move (dest
, force_reg (mode
, src
));
3436 /* We need to deal with constants that would be legitimate
3437 immediate_operands but aren't legitimate move_operands. */
3438 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3440 mips_legitimize_const_move (mode
, dest
, src
);
3441 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3447 /* Return true if value X in context CONTEXT is a small-data address
3448 that can be rewritten as a LO_SUM. */
3451 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3453 enum mips_symbol_type symbol_type
;
3455 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3456 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3457 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3458 && symbol_type
== SYMBOL_GP_RELATIVE
);
3461 /* Return true if OP refers to small data symbols directly, not through
3462 a LO_SUM. CONTEXT is the context in which X appears. */
3465 mips_small_data_pattern_1 (rtx x
, enum mips_symbol_context context
)
3467 subrtx_var_iterator::array_type array
;
3468 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
3472 /* Ignore things like "g" constraints in asms. We make no particular
3473 guarantee about which symbolic constants are acceptable as asm operands
3474 versus which must be forced into a GPR. */
3475 if (GET_CODE (x
) == LO_SUM
|| GET_CODE (x
) == ASM_OPERANDS
)
3476 iter
.skip_subrtxes ();
3479 if (mips_small_data_pattern_1 (XEXP (x
, 0), SYMBOL_CONTEXT_MEM
))
3481 iter
.skip_subrtxes ();
3483 else if (mips_rewrite_small_data_p (x
, context
))
3489 /* Return true if OP refers to small data symbols directly, not through
3493 mips_small_data_pattern_p (rtx op
)
3495 return mips_small_data_pattern_1 (op
, SYMBOL_CONTEXT_LEA
);
3498 /* Rewrite *LOC so that it refers to small data using explicit
3499 relocations. CONTEXT is the context in which *LOC appears. */
3502 mips_rewrite_small_data_1 (rtx
*loc
, enum mips_symbol_context context
)
3504 subrtx_ptr_iterator::array_type array
;
3505 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3510 mips_rewrite_small_data_1 (&XEXP (*loc
, 0), SYMBOL_CONTEXT_MEM
);
3511 iter
.skip_subrtxes ();
3513 else if (mips_rewrite_small_data_p (*loc
, context
))
3515 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3516 iter
.skip_subrtxes ();
3518 else if (GET_CODE (*loc
) == LO_SUM
)
3519 iter
.skip_subrtxes ();
3523 /* Rewrite instruction pattern PATTERN so that it refers to small data
3524 using explicit relocations. */
3527 mips_rewrite_small_data (rtx pattern
)
3529 pattern
= copy_insn (pattern
);
3530 mips_rewrite_small_data_1 (&pattern
, SYMBOL_CONTEXT_LEA
);
3534 /* The cost of loading values from the constant pool. It should be
3535 larger than the cost of any constant we want to synthesize inline. */
3536 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3538 /* Return the cost of X when used as an operand to the MIPS16 instruction
3539 that implements CODE. Return -1 if there is no such instruction, or if
3540 X is not a valid immediate operand for it. */
3543 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3550 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3551 other shifts are extended. The shift patterns truncate the shift
3552 count to the right size, so there are no out-of-range values. */
3553 if (IN_RANGE (x
, 1, 8))
3555 return COSTS_N_INSNS (1);
3558 if (IN_RANGE (x
, -128, 127))
3560 if (SMALL_OPERAND (x
))
3561 return COSTS_N_INSNS (1);
3565 /* Like LE, but reject the always-true case. */
3569 /* We add 1 to the immediate and use SLT. */
3572 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3575 if (IN_RANGE (x
, 0, 255))
3577 if (SMALL_OPERAND_UNSIGNED (x
))
3578 return COSTS_N_INSNS (1);
3583 /* Equality comparisons with 0 are cheap. */
3593 /* Return true if there is a non-MIPS16 instruction that implements CODE
3594 and if that instruction accepts X as an immediate operand. */
3597 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3604 /* All shift counts are truncated to a valid constant. */
3609 /* Likewise rotates, if the target supports rotates at all. */
3615 /* These instructions take 16-bit unsigned immediates. */
3616 return SMALL_OPERAND_UNSIGNED (x
);
3621 /* These instructions take 16-bit signed immediates. */
3622 return SMALL_OPERAND (x
);
3628 /* The "immediate" forms of these instructions are really
3629 implemented as comparisons with register 0. */
3634 /* Likewise, meaning that the only valid immediate operand is 1. */
3638 /* We add 1 to the immediate and use SLT. */
3639 return SMALL_OPERAND (x
+ 1);
3642 /* Likewise SLTU, but reject the always-true case. */
3643 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3647 /* The bit position and size are immediate operands. */
3648 return ISA_HAS_EXT_INS
;
3651 /* By default assume that $0 can be used for 0. */
3656 /* Return the cost of binary operation X, given that the instruction
3657 sequence for a word-sized or smaller operation has cost SINGLE_COST
3658 and that the sequence of a double-word operation has cost DOUBLE_COST.
3659 If SPEED is true, optimize for speed otherwise optimize for size. */
3662 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3666 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3671 + set_src_cost (XEXP (x
, 0), speed
)
3672 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3675 /* Return the cost of floating-point multiplications of mode MODE. */
3678 mips_fp_mult_cost (enum machine_mode mode
)
3680 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3683 /* Return the cost of floating-point divisions of mode MODE. */
3686 mips_fp_div_cost (enum machine_mode mode
)
3688 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3691 /* Return the cost of sign-extending OP to mode MODE, not including the
3692 cost of OP itself. */
3695 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3698 /* Extended loads are as cheap as unextended ones. */
3701 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3702 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3705 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3706 /* We can use SEB or SEH. */
3707 return COSTS_N_INSNS (1);
3709 /* We need to use a shift left and a shift right. */
3710 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3713 /* Return the cost of zero-extending OP to mode MODE, not including the
3714 cost of OP itself. */
3717 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3720 /* Extended loads are as cheap as unextended ones. */
3723 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3724 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3725 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3727 if (GENERATE_MIPS16E
)
3728 /* We can use ZEB or ZEH. */
3729 return COSTS_N_INSNS (1);
3732 /* We need to load 0xff or 0xffff into a register and use AND. */
3733 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3735 /* We can use ANDI. */
3736 return COSTS_N_INSNS (1);
3739 /* Return the cost of moving between two registers of mode MODE,
3740 assuming that the move will be in pieces of at most UNITS bytes. */
3743 mips_set_reg_reg_piece_cost (enum machine_mode mode
, unsigned int units
)
3745 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3748 /* Return the cost of moving between two registers of mode MODE. */
3751 mips_set_reg_reg_cost (enum machine_mode mode
)
3753 switch (GET_MODE_CLASS (mode
))
3756 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3759 case MODE_COMPLEX_FLOAT
:
3760 case MODE_VECTOR_FLOAT
:
3761 if (TARGET_HARD_FLOAT
)
3762 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3766 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3770 /* Implement TARGET_RTX_COSTS. */
3773 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3774 int *total
, bool speed
)
3776 enum machine_mode mode
= GET_MODE (x
);
3777 bool float_mode_p
= FLOAT_MODE_P (mode
);
3781 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3782 appear in the instruction stream, and the cost of a comparison is
3783 really the cost of the branch or scc condition. At the time of
3784 writing, GCC only uses an explicit outer COMPARE code when optabs
3785 is testing whether a constant is expensive enough to force into a
3786 register. We want optabs to pass such constants through the MIPS
3787 expanders instead, so make all constants very cheap here. */
3788 if (outer_code
== COMPARE
)
3790 gcc_assert (CONSTANT_P (x
));
3798 /* Treat *clear_upper32-style ANDs as having zero cost in the
3799 second operand. The cost is entirely in the first operand.
3801 ??? This is needed because we would otherwise try to CSE
3802 the constant operand. Although that's the right thing for
3803 instructions that continue to be a register operation throughout
3804 compilation, it is disastrous for instructions that could
3805 later be converted into a memory operation. */
3807 && outer_code
== AND
3808 && UINTVAL (x
) == 0xffffffff)
3816 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3825 /* When not optimizing for size, we care more about the cost
3826 of hot code, and hot code is often in a loop. If a constant
3827 operand needs to be forced into a register, we will often be
3828 able to hoist the constant load out of the loop, so the load
3829 should not contribute to the cost. */
3830 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3842 if (force_to_mem_operand (x
, VOIDmode
))
3844 *total
= COSTS_N_INSNS (1);
3847 cost
= mips_const_insns (x
);
3850 /* If the constant is likely to be stored in a GPR, SETs of
3851 single-insn constants are as cheap as register sets; we
3852 never want to CSE them.
3854 Don't reduce the cost of storing a floating-point zero in
3855 FPRs. If we have a zero in an FPR for other reasons, we
3856 can get better cfg-cleanup and delayed-branch results by
3857 using it consistently, rather than using $0 sometimes and
3858 an FPR at other times. Also, moves between floating-point
3859 registers are sometimes cheaper than (D)MTC1 $0. */
3861 && outer_code
== SET
3862 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3864 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3865 want to CSE the constant itself. It is usually better to
3866 have N copies of the last operation in the sequence and one
3867 shared copy of the other operations. (Note that this is
3868 not true for MIPS16 code, where the final operation in the
3869 sequence is often an extended instruction.)
3871 Also, if we have a CONST_INT, we don't know whether it is
3872 for a word or doubleword operation, so we cannot rely on
3873 the result of mips_build_integer. */
3874 else if (!TARGET_MIPS16
3875 && (outer_code
== SET
|| mode
== VOIDmode
))
3877 *total
= COSTS_N_INSNS (cost
);
3880 /* The value will need to be fetched from the constant pool. */
3881 *total
= CONSTANT_POOL_COST
;
3885 /* If the address is legitimate, return the number of
3886 instructions it needs. */
3888 cost
= mips_address_insns (addr
, mode
, true);
3891 *total
= COSTS_N_INSNS (cost
+ 1);
3894 /* Check for a scaled indexed address. */
3895 if (mips_lwxs_address_p (addr
)
3896 || mips_lx_address_p (addr
, mode
))
3898 *total
= COSTS_N_INSNS (2);
3901 /* Otherwise use the default handling. */
3905 *total
= COSTS_N_INSNS (6);
3909 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3913 /* Check for a *clear_upper32 pattern and treat it like a zero
3914 extension. See the pattern's comment for details. */
3917 && CONST_INT_P (XEXP (x
, 1))
3918 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3920 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3921 + set_src_cost (XEXP (x
, 0), speed
));
3924 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
3926 rtx op
= XEXP (x
, 0);
3927 if (GET_CODE (op
) == ASHIFT
3928 && CONST_INT_P (XEXP (op
, 1))
3929 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
3931 *total
= COSTS_N_INSNS (1) + set_src_cost (XEXP (op
, 0), speed
);
3935 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3936 a single instruction. */
3938 && GET_CODE (XEXP (x
, 0)) == NOT
3939 && GET_CODE (XEXP (x
, 1)) == NOT
)
3941 cost
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1;
3942 *total
= (COSTS_N_INSNS (cost
)
3943 + set_src_cost (XEXP (XEXP (x
, 0), 0), speed
)
3944 + set_src_cost (XEXP (XEXP (x
, 1), 0), speed
));
3952 /* Double-word operations use two single-word operations. */
3953 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3962 if (CONSTANT_P (XEXP (x
, 1)))
3963 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3966 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3972 *total
= mips_cost
->fp_add
;
3974 *total
= COSTS_N_INSNS (4);
3978 /* Low-part immediates need an extended MIPS16 instruction. */
3979 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3980 + set_src_cost (XEXP (x
, 0), speed
));
3995 /* Branch comparisons have VOIDmode, so use the first operand's
3997 mode
= GET_MODE (XEXP (x
, 0));
3998 if (FLOAT_MODE_P (mode
))
4000 *total
= mips_cost
->fp_add
;
4003 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4009 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
4010 && TARGET_FUSED_MADD
4011 && !HONOR_NANS (mode
)
4012 && !HONOR_SIGNED_ZEROS (mode
))
4014 /* See if we can use NMADD or NMSUB. See mips.md for the
4015 associated patterns. */
4016 rtx op0
= XEXP (x
, 0);
4017 rtx op1
= XEXP (x
, 1);
4018 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
4020 *total
= (mips_fp_mult_cost (mode
)
4021 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
4022 + set_src_cost (XEXP (op0
, 1), speed
)
4023 + set_src_cost (op1
, speed
));
4026 if (GET_CODE (op1
) == MULT
)
4028 *total
= (mips_fp_mult_cost (mode
)
4029 + set_src_cost (op0
, speed
)
4030 + set_src_cost (XEXP (op1
, 0), speed
)
4031 + set_src_cost (XEXP (op1
, 1), speed
));
4040 /* If this is part of a MADD or MSUB, treat the PLUS as
4042 if ((ISA_HAS_FP_MADD4_MSUB4
|| ISA_HAS_FP_MADD3_MSUB3
)
4043 && TARGET_FUSED_MADD
4044 && GET_CODE (XEXP (x
, 0)) == MULT
)
4047 *total
= mips_cost
->fp_add
;
4051 /* Double-word operations require three single-word operations and
4052 an SLTU. The MIPS16 version then needs to move the result of
4053 the SLTU from $24 to a MIPS16 register. */
4054 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
4055 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
4061 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
4062 && TARGET_FUSED_MADD
4063 && !HONOR_NANS (mode
)
4064 && HONOR_SIGNED_ZEROS (mode
))
4066 /* See if we can use NMADD or NMSUB. See mips.md for the
4067 associated patterns. */
4068 rtx op
= XEXP (x
, 0);
4069 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
4070 && GET_CODE (XEXP (op
, 0)) == MULT
)
4072 *total
= (mips_fp_mult_cost (mode
)
4073 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
4074 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
4075 + set_src_cost (XEXP (op
, 1), speed
));
4081 *total
= mips_cost
->fp_add
;
4083 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
4088 *total
= mips_fp_mult_cost (mode
);
4089 else if (mode
== DImode
&& !TARGET_64BIT
)
4090 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4091 where the mulsidi3 always includes an MFHI and an MFLO. */
4093 ? mips_cost
->int_mult_si
* 3 + 6
4094 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
4096 *total
= COSTS_N_INSNS (ISA_HAS_MUL3
? 1 : 2) + 1;
4097 else if (mode
== DImode
)
4098 *total
= mips_cost
->int_mult_di
;
4100 *total
= mips_cost
->int_mult_si
;
4104 /* Check for a reciprocal. */
4106 && ISA_HAS_FP_RECIP_RSQRT (mode
)
4107 && flag_unsafe_math_optimizations
4108 && XEXP (x
, 0) == CONST1_RTX (mode
))
4110 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
4111 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4112 division as being free. */
4113 *total
= set_src_cost (XEXP (x
, 1), speed
);
4115 *total
= (mips_fp_div_cost (mode
)
4116 + set_src_cost (XEXP (x
, 1), speed
));
4125 *total
= mips_fp_div_cost (mode
);
4134 /* It is our responsibility to make division by a power of 2
4135 as cheap as 2 register additions if we want the division
4136 expanders to be used for such operations; see the setting
4137 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4138 should always produce shorter code than using
4139 expand_sdiv2_pow2. */
4141 && CONST_INT_P (XEXP (x
, 1))
4142 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
4144 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
4147 *total
= COSTS_N_INSNS (mips_idiv_insns ());
4149 else if (mode
== DImode
)
4150 *total
= mips_cost
->int_div_di
;
4152 *total
= mips_cost
->int_div_si
;
4156 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
4160 if (outer_code
== SET
4162 && (GET_CODE (XEXP (x
, 0)) == TRUNCATE
4163 || GET_CODE (XEXP (x
, 0)) == SUBREG
)
4164 && GET_MODE (XEXP (x
, 0)) == QImode
4165 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4167 *total
= set_src_cost (XEXP (XEXP (x
, 0), 0), speed
);
4170 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4174 case UNSIGNED_FLOAT
:
4177 case FLOAT_TRUNCATE
:
4178 *total
= mips_cost
->fp_add
;
4182 if (register_operand (SET_DEST (x
), VOIDmode
)
4183 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4185 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4195 /* Implement TARGET_ADDRESS_COST. */
4198 mips_address_cost (rtx addr
, enum machine_mode mode
,
4199 addr_space_t as ATTRIBUTE_UNUSED
,
4200 bool speed ATTRIBUTE_UNUSED
)
4202 return mips_address_insns (addr
, mode
, false);
4205 /* Information about a single instruction in a multi-instruction
4207 struct mips_multi_member
{
4208 /* True if this is a label, false if it is code. */
4211 /* The output_asm_insn format of the instruction. */
4214 /* The operands to the instruction. */
4215 rtx operands
[MAX_RECOG_OPERANDS
];
4217 typedef struct mips_multi_member mips_multi_member
;
4219 /* The instructions that make up the current multi-insn sequence. */
4220 static vec
<mips_multi_member
> mips_multi_members
;
4222 /* How many instructions (as opposed to labels) are in the current
4223 multi-insn sequence. */
4224 static unsigned int mips_multi_num_insns
;
4226 /* Start a new multi-insn sequence. */
4229 mips_multi_start (void)
4231 mips_multi_members
.truncate (0);
4232 mips_multi_num_insns
= 0;
4235 /* Add a new, uninitialized member to the current multi-insn sequence. */
4237 static struct mips_multi_member
*
4238 mips_multi_add (void)
4240 mips_multi_member empty
;
4241 return mips_multi_members
.safe_push (empty
);
4244 /* Add a normal insn with the given asm format to the current multi-insn
4245 sequence. The other arguments are a null-terminated list of operands. */
4248 mips_multi_add_insn (const char *format
, ...)
4250 struct mips_multi_member
*member
;
4255 member
= mips_multi_add ();
4256 member
->is_label_p
= false;
4257 member
->format
= format
;
4258 va_start (ap
, format
);
4260 while ((op
= va_arg (ap
, rtx
)))
4261 member
->operands
[i
++] = op
;
4263 mips_multi_num_insns
++;
4266 /* Add the given label definition to the current multi-insn sequence.
4267 The definition should include the colon. */
4270 mips_multi_add_label (const char *label
)
4272 struct mips_multi_member
*member
;
4274 member
= mips_multi_add ();
4275 member
->is_label_p
= true;
4276 member
->format
= label
;
4279 /* Return the index of the last member of the current multi-insn sequence. */
4282 mips_multi_last_index (void)
4284 return mips_multi_members
.length () - 1;
4287 /* Add a copy of an existing instruction to the current multi-insn
4288 sequence. I is the index of the instruction that should be copied. */
4291 mips_multi_copy_insn (unsigned int i
)
4293 struct mips_multi_member
*member
;
4295 member
= mips_multi_add ();
4296 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4297 gcc_assert (!member
->is_label_p
);
4300 /* Change the operand of an existing instruction in the current
4301 multi-insn sequence. I is the index of the instruction,
4302 OP is the index of the operand, and X is the new value. */
4305 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4307 mips_multi_members
[i
].operands
[op
] = x
;
4310 /* Write out the asm code for the current multi-insn sequence. */
4313 mips_multi_write (void)
4315 struct mips_multi_member
*member
;
4318 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4319 if (member
->is_label_p
)
4320 fprintf (asm_out_file
, "%s\n", member
->format
);
4322 output_asm_insn (member
->format
, member
->operands
);
4325 /* Return one word of double-word value OP, taking into account the fixed
4326 endianness of certain registers. HIGH_P is true to select the high part,
4327 false to select the low part. */
4330 mips_subword (rtx op
, bool high_p
)
4332 unsigned int byte
, offset
;
4333 enum machine_mode mode
;
4335 mode
= GET_MODE (op
);
4336 if (mode
== VOIDmode
)
4337 mode
= TARGET_64BIT
? TImode
: DImode
;
4339 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4340 byte
= UNITS_PER_WORD
;
4344 if (FP_REG_RTX_P (op
))
4346 /* Paired FPRs are always ordered little-endian. */
4347 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4348 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4352 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4354 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4357 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4358 SPLIT_TYPE is the condition under which moves should be split. */
4361 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4363 return ((split_type
!= SPLIT_FOR_SPEED
4364 || mips_tuning_info
.fast_mult_zero_zero_p
)
4365 && src
== const0_rtx
4367 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4368 && (ISA_HAS_DSP_MULT
4369 ? ACC_REG_P (REGNO (dest
))
4370 : MD_REG_P (REGNO (dest
))));
4373 /* Return true if a move from SRC to DEST should be split into two.
4374 SPLIT_TYPE describes the split condition. */
4377 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4379 /* Check whether the move can be done using some variant of MULT $0,$0. */
4380 if (mips_mult_move_p (dest
, src
, split_type
))
4383 /* FPR-to-FPR moves can be done in a single instruction, if they're
4385 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4386 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4389 /* Check for floating-point loads and stores. */
4390 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4392 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4394 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4398 /* Otherwise split all multiword moves. */
4399 return size
> UNITS_PER_WORD
;
4402 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4403 SPLIT_TYPE describes the split condition. */
4406 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4410 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4411 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4413 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4414 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4415 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4416 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4417 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4418 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4419 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4420 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4421 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4422 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4423 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4424 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4425 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4426 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4430 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4432 low_dest
= mips_subword (dest
, false);
4433 mips_emit_move (low_dest
, mips_subword (src
, false));
4435 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4437 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4439 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4441 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4443 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4445 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4449 /* The operation can be split into two normal moves. Decide in
4450 which order to do them. */
4451 low_dest
= mips_subword (dest
, false);
4452 if (REG_P (low_dest
)
4453 && reg_overlap_mentioned_p (low_dest
, src
))
4455 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4456 mips_emit_move (low_dest
, mips_subword (src
, false));
4460 mips_emit_move (low_dest
, mips_subword (src
, false));
4461 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4466 /* Return the split type for instruction INSN. */
4468 static enum mips_split_type
4469 mips_insn_split_type (rtx insn
)
4471 basic_block bb
= BLOCK_FOR_INSN (insn
);
4474 if (optimize_bb_for_speed_p (bb
))
4475 return SPLIT_FOR_SPEED
;
4477 return SPLIT_FOR_SIZE
;
4479 /* Once CFG information has been removed, we should trust the optimization
4480 decisions made by previous passes and only split where necessary. */
4481 return SPLIT_IF_NECESSARY
;
4484 /* Return true if a move from SRC to DEST in INSN should be split. */
4487 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
4489 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
4492 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4496 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
4498 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
4501 /* Return the appropriate instructions to move SRC into DEST. Assume
4502 that SRC is operand 1 and DEST is operand 0. */
4505 mips_output_move (rtx dest
, rtx src
)
4507 enum rtx_code dest_code
, src_code
;
4508 enum machine_mode mode
;
4509 enum mips_symbol_type symbol_type
;
4512 dest_code
= GET_CODE (dest
);
4513 src_code
= GET_CODE (src
);
4514 mode
= GET_MODE (dest
);
4515 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4517 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4520 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4521 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4523 if (dest_code
== REG
)
4525 if (GP_REG_P (REGNO (dest
)))
4526 return "move\t%0,%z1";
4528 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4530 if (ISA_HAS_DSP_MULT
)
4531 return "mult\t%q0,%.,%.";
4533 return "mult\t%.,%.";
4536 /* Moves to HI are handled by special .md insns. */
4537 if (REGNO (dest
) == LO_REGNUM
)
4540 if (DSP_ACC_REG_P (REGNO (dest
)))
4542 static char retval
[] = "mt__\t%z1,%q0";
4544 retval
[2] = reg_names
[REGNO (dest
)][4];
4545 retval
[3] = reg_names
[REGNO (dest
)][5];
4549 if (FP_REG_P (REGNO (dest
)))
4550 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4552 if (ALL_COP_REG_P (REGNO (dest
)))
4554 static char retval
[] = "dmtc_\t%z1,%0";
4556 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4557 return dbl_p
? retval
: retval
+ 1;
4560 if (dest_code
== MEM
)
4561 switch (GET_MODE_SIZE (mode
))
4563 case 1: return "sb\t%z1,%0";
4564 case 2: return "sh\t%z1,%0";
4565 case 4: return "sw\t%z1,%0";
4566 case 8: return "sd\t%z1,%0";
4569 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4571 if (src_code
== REG
)
4573 /* Moves from HI are handled by special .md insns. */
4574 if (REGNO (src
) == LO_REGNUM
)
4576 /* When generating VR4120 or VR4130 code, we use MACC and
4577 DMACC instead of MFLO. This avoids both the normal
4578 MIPS III HI/LO hazards and the errata related to
4581 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4585 if (DSP_ACC_REG_P (REGNO (src
)))
4587 static char retval
[] = "mf__\t%0,%q1";
4589 retval
[2] = reg_names
[REGNO (src
)][4];
4590 retval
[3] = reg_names
[REGNO (src
)][5];
4594 if (FP_REG_P (REGNO (src
)))
4595 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4597 if (ALL_COP_REG_P (REGNO (src
)))
4599 static char retval
[] = "dmfc_\t%0,%1";
4601 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4602 return dbl_p
? retval
: retval
+ 1;
4606 if (src_code
== MEM
)
4607 switch (GET_MODE_SIZE (mode
))
4609 case 1: return "lbu\t%0,%1";
4610 case 2: return "lhu\t%0,%1";
4611 case 4: return "lw\t%0,%1";
4612 case 8: return "ld\t%0,%1";
4615 if (src_code
== CONST_INT
)
4617 /* Don't use the X format for the operand itself, because that
4618 will give out-of-range numbers for 64-bit hosts and 32-bit
4621 return "li\t%0,%1\t\t\t# %X1";
4623 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4626 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4630 if (src_code
== HIGH
)
4631 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4633 if (CONST_GP_P (src
))
4634 return "move\t%0,%1";
4636 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4637 && mips_lo_relocs
[symbol_type
] != 0)
4639 /* A signed 16-bit constant formed by applying a relocation
4640 operator to a symbolic address. */
4641 gcc_assert (!mips_split_p
[symbol_type
]);
4642 return "li\t%0,%R1";
4645 if (symbolic_operand (src
, VOIDmode
))
4647 gcc_assert (TARGET_MIPS16
4648 ? TARGET_MIPS16_TEXT_LOADS
4649 : !TARGET_EXPLICIT_RELOCS
);
4650 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4653 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4655 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4657 if (GET_MODE (dest
) == V2SFmode
)
4658 return "mov.ps\t%0,%1";
4660 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4663 if (dest_code
== MEM
)
4664 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4666 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4668 if (src_code
== MEM
)
4669 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4671 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4673 static char retval
[] = "l_c_\t%0,%1";
4675 retval
[1] = (dbl_p
? 'd' : 'w');
4676 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4679 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4681 static char retval
[] = "s_c_\t%1,%0";
4683 retval
[1] = (dbl_p
? 'd' : 'w');
4684 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4690 /* Return true if CMP1 is a suitable second operand for integer ordering
4691 test CODE. See also the *sCC patterns in mips.md. */
4694 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4700 return reg_or_0_operand (cmp1
, VOIDmode
);
4704 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4708 return arith_operand (cmp1
, VOIDmode
);
4711 return sle_operand (cmp1
, VOIDmode
);
4714 return sleu_operand (cmp1
, VOIDmode
);
4721 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4722 integer ordering test *CODE, or if an equivalent combination can
4723 be formed by adjusting *CODE and *CMP1. When returning true, update
4724 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4728 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4729 enum machine_mode mode
)
4731 HOST_WIDE_INT plus_one
;
4733 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4736 if (CONST_INT_P (*cmp1
))
4740 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4741 if (INTVAL (*cmp1
) < plus_one
)
4744 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4750 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4754 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4765 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4766 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4767 is nonnull, it's OK to set TARGET to the inverse of the result and
4768 flip *INVERT_PTR instead. */
4771 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4772 rtx target
, rtx cmp0
, rtx cmp1
)
4774 enum machine_mode mode
;
4776 /* First see if there is a MIPS instruction that can do this operation.
4777 If not, try doing the same for the inverse operation. If that also
4778 fails, force CMP1 into a register and try again. */
4779 mode
= GET_MODE (cmp0
);
4780 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4781 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4784 enum rtx_code inv_code
= reverse_condition (code
);
4785 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4787 cmp1
= force_reg (mode
, cmp1
);
4788 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4790 else if (invert_ptr
== 0)
4794 inv_target
= mips_force_binary (GET_MODE (target
),
4795 inv_code
, cmp0
, cmp1
);
4796 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4800 *invert_ptr
= !*invert_ptr
;
4801 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4806 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4807 The register will have the same mode as CMP0. */
4810 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4812 if (cmp1
== const0_rtx
)
4815 if (uns_arith_operand (cmp1
, VOIDmode
))
4816 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4817 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4819 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4820 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4823 /* Convert *CODE into a code that can be used in a floating-point
4824 scc instruction (C.cond.fmt). Return true if the values of
4825 the condition code registers will be inverted, with 0 indicating
4826 that the condition holds. */
4829 mips_reversed_fp_cond (enum rtx_code
*code
)
4836 *code
= reverse_condition_maybe_unordered (*code
);
4844 /* Allocate a floating-point condition-code register of mode MODE.
4846 These condition code registers are used for certain kinds
4847 of compound operation, such as compare and branches, vconds,
4848 and built-in functions. At expand time, their use is entirely
4849 controlled by MIPS-specific code and is entirely internal
4850 to these compound operations.
4852 We could (and did in the past) expose condition-code values
4853 as pseudo registers and leave the register allocator to pick
4854 appropriate registers. The problem is that it is not practically
4855 possible for the rtl optimizers to guarantee that no spills will
4856 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4857 therefore need spill and reload sequences to handle the worst case.
4859 Although such sequences do exist, they are very expensive and are
4860 not something we'd want to use. This is especially true of CCV2 and
4861 CCV4, where all the shuffling would greatly outweigh whatever benefit
4862 the vectorization itself provides.
4864 The main benefit of having more than one condition-code register
4865 is to allow the pipelining of operations, especially those involving
4866 comparisons and conditional moves. We don't really expect the
4867 registers to be live for long periods, and certainly never want
4868 them to be live across calls.
4870 Also, there should be no penalty attached to using all the available
4871 registers. They are simply bits in the same underlying FPU control
4874 We therefore expose the hardware registers from the outset and use
4875 a simple round-robin allocation scheme. */
4878 mips_allocate_fcc (enum machine_mode mode
)
4880 unsigned int regno
, count
;
4882 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
4886 else if (mode
== CCV2mode
)
4888 else if (mode
== CCV4mode
)
4893 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
4894 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
4895 cfun
->machine
->next_fcc
= 0;
4896 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
4897 cfun
->machine
->next_fcc
+= count
;
4898 return gen_rtx_REG (mode
, regno
);
4901 /* Convert a comparison into something that can be used in a branch or
4902 conditional move. On entry, *OP0 and *OP1 are the values being
4903 compared and *CODE is the code used to compare them.
4905 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4906 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4907 otherwise any standard branch condition can be used. The standard branch
4910 - EQ or NE between two registers.
4911 - any comparison between a register and zero. */
4914 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4919 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4921 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4923 else if (*code
== EQ
|| *code
== NE
)
4927 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4931 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4935 /* The comparison needs a separate scc instruction. Store the
4936 result of the scc in *OP0 and compare it against zero. */
4937 bool invert
= false;
4938 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4939 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4940 *code
= (invert
? EQ
: NE
);
4944 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4946 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4947 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4953 enum rtx_code cmp_code
;
4955 /* Floating-point tests use a separate C.cond.fmt comparison to
4956 set a condition code register. The branch or conditional move
4957 will then compare that register against zero.
4959 Set CMP_CODE to the code of the comparison instruction and
4960 *CODE to the code that the branch or move should use. */
4962 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4964 ? mips_allocate_fcc (CCmode
)
4965 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4967 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4971 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4972 and OPERAND[3]. Store the result in OPERANDS[0].
4974 On 64-bit targets, the mode of the comparison and target will always be
4975 SImode, thus possibly narrower than that of the comparison's operands. */
4978 mips_expand_scc (rtx operands
[])
4980 rtx target
= operands
[0];
4981 enum rtx_code code
= GET_CODE (operands
[1]);
4982 rtx op0
= operands
[2];
4983 rtx op1
= operands
[3];
4985 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
4987 if (code
== EQ
|| code
== NE
)
4990 && reg_imm10_operand (op1
, GET_MODE (op1
)))
4991 mips_emit_binary (code
, target
, op0
, op1
);
4994 rtx zie
= mips_zero_if_equal (op0
, op1
);
4995 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4999 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
5002 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
5003 CODE and jump to OPERANDS[3] if the condition holds. */
5006 mips_expand_conditional_branch (rtx
*operands
)
5008 enum rtx_code code
= GET_CODE (operands
[0]);
5009 rtx op0
= operands
[1];
5010 rtx op1
= operands
[2];
5013 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
5014 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5015 emit_jump_insn (gen_condjump (condition
, operands
[3]));
5020 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5021 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5024 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
5025 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
5030 reversed_p
= mips_reversed_fp_cond (&cond
);
5031 cmp_result
= mips_allocate_fcc (CCV2mode
);
5032 emit_insn (gen_scc_ps (cmp_result
,
5033 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
5035 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
5038 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
5042 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5043 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5046 mips_expand_conditional_move (rtx
*operands
)
5049 enum rtx_code code
= GET_CODE (operands
[1]);
5050 rtx op0
= XEXP (operands
[1], 0);
5051 rtx op1
= XEXP (operands
[1], 1);
5053 mips_emit_compare (&code
, &op0
, &op1
, true);
5054 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
5055 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
5056 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
5057 operands
[2], operands
[3])));
5060 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5063 mips_expand_conditional_trap (rtx comparison
)
5066 enum machine_mode mode
;
5069 /* MIPS conditional trap instructions don't have GT or LE flavors,
5070 so we must swap the operands and convert to LT and GE respectively. */
5071 code
= GET_CODE (comparison
);
5078 code
= swap_condition (code
);
5079 op0
= XEXP (comparison
, 1);
5080 op1
= XEXP (comparison
, 0);
5084 op0
= XEXP (comparison
, 0);
5085 op1
= XEXP (comparison
, 1);
5089 mode
= GET_MODE (XEXP (comparison
, 0));
5090 op0
= force_reg (mode
, op0
);
5091 if (!arith_operand (op1
, mode
))
5092 op1
= force_reg (mode
, op1
);
5094 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
5095 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
5099 /* Initialize *CUM for a call to a function of type FNTYPE. */
5102 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
5104 memset (cum
, 0, sizeof (*cum
));
5105 cum
->prototype
= (fntype
&& prototype_p (fntype
));
5106 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
5109 /* Fill INFO with information about a single argument. CUM is the
5110 cumulative state for earlier arguments. MODE is the mode of this
5111 argument and TYPE is its type (if known). NAMED is true if this
5112 is a named (fixed) argument rather than a variable one. */
5115 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
5116 enum machine_mode mode
, const_tree type
, bool named
)
5118 bool doubleword_aligned_p
;
5119 unsigned int num_bytes
, num_words
, max_regs
;
5121 /* Work out the size of the argument. */
5122 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5123 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5125 /* Decide whether it should go in a floating-point register, assuming
5126 one is free. Later code checks for availability.
5128 The checks against UNITS_PER_FPVALUE handle the soft-float and
5129 single-float cases. */
5133 /* The EABI conventions have traditionally been defined in terms
5134 of TYPE_MODE, regardless of the actual type. */
5135 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5136 || mode
== V2SFmode
)
5137 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5142 /* Only leading floating-point scalars are passed in
5143 floating-point registers. We also handle vector floats the same
5144 say, which is OK because they are not covered by the standard ABI. */
5145 info
->fpr_p
= (!cum
->gp_reg_found
5146 && cum
->arg_number
< 2
5148 || SCALAR_FLOAT_TYPE_P (type
)
5149 || VECTOR_FLOAT_TYPE_P (type
))
5150 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5151 || mode
== V2SFmode
)
5152 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5157 /* Scalar, complex and vector floating-point types are passed in
5158 floating-point registers, as long as this is a named rather
5159 than a variable argument. */
5160 info
->fpr_p
= (named
5161 && (type
== 0 || FLOAT_TYPE_P (type
))
5162 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5163 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5164 || mode
== V2SFmode
)
5165 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5167 /* ??? According to the ABI documentation, the real and imaginary
5168 parts of complex floats should be passed in individual registers.
5169 The real and imaginary parts of stack arguments are supposed
5170 to be contiguous and there should be an extra word of padding
5173 This has two problems. First, it makes it impossible to use a
5174 single "void *" va_list type, since register and stack arguments
5175 are passed differently. (At the time of writing, MIPSpro cannot
5176 handle complex float varargs correctly.) Second, it's unclear
5177 what should happen when there is only one register free.
5179 For now, we assume that named complex floats should go into FPRs
5180 if there are two FPRs free, otherwise they should be passed in the
5181 same way as a struct containing two floats. */
5183 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5184 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5186 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5187 info
->fpr_p
= false;
5197 /* See whether the argument has doubleword alignment. */
5198 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5201 /* Set REG_OFFSET to the register count we're interested in.
5202 The EABI allocates the floating-point registers separately,
5203 but the other ABIs allocate them like integer registers. */
5204 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5208 /* Advance to an even register if the argument is doubleword-aligned. */
5209 if (doubleword_aligned_p
)
5210 info
->reg_offset
+= info
->reg_offset
& 1;
5212 /* Work out the offset of a stack argument. */
5213 info
->stack_offset
= cum
->stack_words
;
5214 if (doubleword_aligned_p
)
5215 info
->stack_offset
+= info
->stack_offset
& 1;
5217 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5219 /* Partition the argument between registers and stack. */
5220 info
->reg_words
= MIN (num_words
, max_regs
);
5221 info
->stack_words
= num_words
- info
->reg_words
;
5224 /* INFO describes a register argument that has the normal format for the
5225 argument's mode. Return the register it uses, assuming that FPRs are
5226 available if HARD_FLOAT_P. */
5229 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5231 if (!info
->fpr_p
|| !hard_float_p
)
5232 return GP_ARG_FIRST
+ info
->reg_offset
;
5233 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5234 /* In o32, the second argument is always passed in $f14
5235 for TARGET_DOUBLE_FLOAT, regardless of whether the
5236 first argument was a word or doubleword. */
5237 return FP_ARG_FIRST
+ 2;
5239 return FP_ARG_FIRST
+ info
->reg_offset
;
5242 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5245 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5247 return !TARGET_OLDABI
;
5250 /* Implement TARGET_FUNCTION_ARG. */
5253 mips_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
5254 const_tree type
, bool named
)
5256 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5257 struct mips_arg_info info
;
5259 /* We will be called with a mode of VOIDmode after the last argument
5260 has been seen. Whatever we return will be passed to the call expander.
5261 If we need a MIPS16 fp_code, return a REG with the code stored as
5263 if (mode
== VOIDmode
)
5265 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5266 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
5271 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5273 /* Return straight away if the whole argument is passed on the stack. */
5274 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5277 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5278 contains a double in its entirety, then that 64-bit chunk is passed
5279 in a floating-point register. */
5281 && TARGET_HARD_FLOAT
5284 && TREE_CODE (type
) == RECORD_TYPE
5285 && TYPE_SIZE_UNIT (type
)
5286 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
5290 /* First check to see if there is any such field. */
5291 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5292 if (TREE_CODE (field
) == FIELD_DECL
5293 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5294 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5295 && tree_fits_shwi_p (bit_position (field
))
5296 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5301 /* Now handle the special case by returning a PARALLEL
5302 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5303 chunks are passed in registers. */
5305 HOST_WIDE_INT bitpos
;
5308 /* assign_parms checks the mode of ENTRY_PARM, so we must
5309 use the actual mode here. */
5310 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5313 field
= TYPE_FIELDS (type
);
5314 for (i
= 0; i
< info
.reg_words
; i
++)
5318 for (; field
; field
= DECL_CHAIN (field
))
5319 if (TREE_CODE (field
) == FIELD_DECL
5320 && int_bit_position (field
) >= bitpos
)
5324 && int_bit_position (field
) == bitpos
5325 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5326 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5327 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5329 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
5332 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5333 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5335 bitpos
+= BITS_PER_WORD
;
5341 /* Handle the n32/n64 conventions for passing complex floating-point
5342 arguments in FPR pairs. The real part goes in the lower register
5343 and the imaginary part goes in the upper register. */
5346 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5349 enum machine_mode inner
;
5352 inner
= GET_MODE_INNER (mode
);
5353 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
5354 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
5356 /* Real part in registers, imaginary part on stack. */
5357 gcc_assert (info
.stack_words
== info
.reg_words
);
5358 return gen_rtx_REG (inner
, regno
);
5362 gcc_assert (info
.stack_words
== 0);
5363 real
= gen_rtx_EXPR_LIST (VOIDmode
,
5364 gen_rtx_REG (inner
, regno
),
5366 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
5368 regno
+ info
.reg_words
/ 2),
5369 GEN_INT (GET_MODE_SIZE (inner
)));
5370 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
5374 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
5377 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5380 mips_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
5381 const_tree type
, bool named
)
5383 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5384 struct mips_arg_info info
;
5386 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5389 cum
->gp_reg_found
= true;
5391 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5392 an explanation of what this code does. It assumes that we're using
5393 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5395 if (cum
->arg_number
< 2 && info
.fpr_p
)
5396 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5398 /* Advance the register count. This has the effect of setting
5399 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5400 argument required us to skip the final GPR and pass the whole
5401 argument on the stack. */
5402 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5403 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5404 else if (info
.reg_words
> 0)
5405 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5407 /* Advance the stack word count. */
5408 if (info
.stack_words
> 0)
5409 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5414 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5417 mips_arg_partial_bytes (cumulative_args_t cum
,
5418 enum machine_mode mode
, tree type
, bool named
)
5420 struct mips_arg_info info
;
5422 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5423 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5426 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5427 least PARM_BOUNDARY bits of alignment, but will be given anything up
5428 to STACK_BOUNDARY bits if the type requires it. */
5431 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5433 unsigned int alignment
;
5435 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5436 if (alignment
< PARM_BOUNDARY
)
5437 alignment
= PARM_BOUNDARY
;
5438 if (alignment
> STACK_BOUNDARY
)
5439 alignment
= STACK_BOUNDARY
;
5443 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5444 upward rather than downward. In other words, return true if the
5445 first byte of the stack slot has useful data, false if the last
5449 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
5451 /* On little-endian targets, the first byte of every stack argument
5452 is passed in the first byte of the stack slot. */
5453 if (!BYTES_BIG_ENDIAN
)
5456 /* Otherwise, integral types are padded downward: the last byte of a
5457 stack argument is passed in the last byte of the stack slot. */
5459 ? (INTEGRAL_TYPE_P (type
)
5460 || POINTER_TYPE_P (type
)
5461 || FIXED_POINT_TYPE_P (type
))
5462 : (SCALAR_INT_MODE_P (mode
)
5463 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5466 /* Big-endian o64 pads floating-point arguments downward. */
5467 if (mips_abi
== ABI_O64
)
5468 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5471 /* Other types are padded upward for o32, o64, n32 and n64. */
5472 if (mips_abi
!= ABI_EABI
)
5475 /* Arguments smaller than a stack slot are padded downward. */
5476 if (mode
!= BLKmode
)
5477 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5479 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5482 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5483 if the least significant byte of the register has useful data. Return
5484 the opposite if the most significant byte does. */
5487 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
5489 /* No shifting is required for floating-point arguments. */
5490 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5491 return !BYTES_BIG_ENDIAN
;
5493 /* Otherwise, apply the same padding to register arguments as we do
5494 to stack arguments. */
5495 return mips_pad_arg_upward (mode
, type
);
5498 /* Return nonzero when an argument must be passed by reference. */
5501 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5502 enum machine_mode mode
, const_tree type
,
5503 bool named ATTRIBUTE_UNUSED
)
5505 if (mips_abi
== ABI_EABI
)
5509 /* ??? How should SCmode be handled? */
5510 if (mode
== DImode
|| mode
== DFmode
5511 || mode
== DQmode
|| mode
== UDQmode
5512 || mode
== DAmode
|| mode
== UDAmode
)
5515 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5516 return size
== -1 || size
> UNITS_PER_WORD
;
5520 /* If we have a variable-sized parameter, we have no choice. */
5521 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5525 /* Implement TARGET_CALLEE_COPIES. */
5528 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5529 enum machine_mode mode ATTRIBUTE_UNUSED
,
5530 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5532 return mips_abi
== ABI_EABI
&& named
;
5535 /* See whether VALTYPE is a record whose fields should be returned in
5536 floating-point registers. If so, return the number of fields and
5537 list them in FIELDS (which should have two elements). Return 0
5540 For n32 & n64, a structure with one or two fields is returned in
5541 floating-point registers as long as every field has a floating-point
5545 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5553 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5557 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5559 if (TREE_CODE (field
) != FIELD_DECL
)
5562 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5568 fields
[i
++] = field
;
5573 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5574 a value in the most significant part of $2/$3 if:
5576 - the target is big-endian;
5578 - the value has a structure or union type (we generalize this to
5579 cover aggregates from other languages too); and
5581 - the structure is not returned in floating-point registers. */
5584 mips_return_in_msb (const_tree valtype
)
5588 return (TARGET_NEWABI
5589 && TARGET_BIG_ENDIAN
5590 && AGGREGATE_TYPE_P (valtype
)
5591 && mips_fpr_return_fields (valtype
, fields
) == 0);
5594 /* Return true if the function return value MODE will get returned in a
5595 floating-point register. */
5598 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5600 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5602 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5603 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5606 /* Return the representation of an FPR return register when the
5607 value being returned in FP_RETURN has mode VALUE_MODE and the
5608 return type itself has mode TYPE_MODE. On NewABI targets,
5609 the two modes may be different for structures like:
5611 struct __attribute__((packed)) foo { float f; }
5613 where we return the SFmode value of "f" in FP_RETURN, but where
5614 the structure itself has mode BLKmode. */
5617 mips_return_fpr_single (enum machine_mode type_mode
,
5618 enum machine_mode value_mode
)
5622 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5623 if (type_mode
!= value_mode
)
5625 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5626 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5631 /* Return a composite value in a pair of floating-point registers.
5632 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5633 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5636 For n32 & n64, $f0 always holds the first value and $f2 the second.
5637 Otherwise the values are packed together as closely as possible. */
5640 mips_return_fpr_pair (enum machine_mode mode
,
5641 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5642 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5646 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5647 return gen_rtx_PARALLEL
5650 gen_rtx_EXPR_LIST (VOIDmode
,
5651 gen_rtx_REG (mode1
, FP_RETURN
),
5653 gen_rtx_EXPR_LIST (VOIDmode
,
5654 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5655 GEN_INT (offset2
))));
5659 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5660 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5661 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5664 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5665 enum machine_mode mode
)
5673 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5674 func
= fn_decl_or_type
;
5678 mode
= TYPE_MODE (valtype
);
5679 unsigned_p
= TYPE_UNSIGNED (valtype
);
5681 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5682 return values, promote the mode here too. */
5683 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5685 /* Handle structures whose fields are returned in $f0/$f2. */
5686 switch (mips_fpr_return_fields (valtype
, fields
))
5689 return mips_return_fpr_single (mode
,
5690 TYPE_MODE (TREE_TYPE (fields
[0])));
5693 return mips_return_fpr_pair (mode
,
5694 TYPE_MODE (TREE_TYPE (fields
[0])),
5695 int_byte_position (fields
[0]),
5696 TYPE_MODE (TREE_TYPE (fields
[1])),
5697 int_byte_position (fields
[1]));
5700 /* If a value is passed in the most significant part of a register, see
5701 whether we have to round the mode up to a whole number of words. */
5702 if (mips_return_in_msb (valtype
))
5704 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5705 if (size
% UNITS_PER_WORD
!= 0)
5707 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5708 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5712 /* For EABI, the class of return register depends entirely on MODE.
5713 For example, "struct { some_type x; }" and "union { some_type x; }"
5714 are returned in the same way as a bare "some_type" would be.
5715 Other ABIs only use FPRs for scalar, complex or vector types. */
5716 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5717 return gen_rtx_REG (mode
, GP_RETURN
);
5722 /* Handle long doubles for n32 & n64. */
5724 return mips_return_fpr_pair (mode
,
5726 DImode
, GET_MODE_SIZE (mode
) / 2);
5728 if (mips_return_mode_in_fpr_p (mode
))
5730 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5731 return mips_return_fpr_pair (mode
,
5732 GET_MODE_INNER (mode
), 0,
5733 GET_MODE_INNER (mode
),
5734 GET_MODE_SIZE (mode
) / 2);
5736 return gen_rtx_REG (mode
, FP_RETURN
);
5740 return gen_rtx_REG (mode
, GP_RETURN
);
5743 /* Implement TARGET_FUNCTION_VALUE. */
5746 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5747 bool outgoing ATTRIBUTE_UNUSED
)
5749 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5752 /* Implement TARGET_LIBCALL_VALUE. */
5755 mips_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5757 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5760 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5762 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5763 Currently, R2 and F0 are only implemented here (C has no complex type). */
5766 mips_function_value_regno_p (const unsigned int regno
)
5768 if (regno
== GP_RETURN
5769 || regno
== FP_RETURN
5770 || (LONG_DOUBLE_TYPE_SIZE
== 128
5771 && FP_RETURN
!= GP_RETURN
5772 && regno
== FP_RETURN
+ 2))
5778 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5779 all BLKmode objects are returned in memory. Under the n32, n64
5780 and embedded ABIs, small structures are returned in a register.
5781 Objects with varying size must still be returned in memory, of
5785 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5787 return (TARGET_OLDABI
5788 ? TYPE_MODE (type
) == BLKmode
5789 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5792 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5795 mips_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
5796 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5799 CUMULATIVE_ARGS local_cum
;
5800 int gp_saved
, fp_saved
;
5802 /* The caller has advanced CUM up to, but not beyond, the last named
5803 argument. Advance a local copy of CUM past the last "real" named
5804 argument, to find out how many registers are left over. */
5805 local_cum
= *get_cumulative_args (cum
);
5806 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5809 /* Found out how many registers we need to save. */
5810 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5811 fp_saved
= (EABI_FLOAT_VARARGS_P
5812 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5821 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
5822 REG_PARM_STACK_SPACE (cfun
->decl
)
5823 - gp_saved
* UNITS_PER_WORD
);
5824 mem
= gen_frame_mem (BLKmode
, ptr
);
5825 set_mem_alias_set (mem
, get_varargs_alias_set ());
5827 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5832 /* We can't use move_block_from_reg, because it will use
5834 enum machine_mode mode
;
5837 /* Set OFF to the offset from virtual_incoming_args_rtx of
5838 the first float register. The FP save area lies below
5839 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5840 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5841 off
-= fp_saved
* UNITS_PER_FPREG
;
5843 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5845 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5846 i
+= MAX_FPRS_PER_FMT
)
5850 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
5851 mem
= gen_frame_mem (mode
, ptr
);
5852 set_mem_alias_set (mem
, get_varargs_alias_set ());
5853 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5854 off
+= UNITS_PER_HWFPVALUE
;
5858 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5859 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5860 + fp_saved
* UNITS_PER_FPREG
);
5863 /* Implement TARGET_BUILTIN_VA_LIST. */
5866 mips_build_builtin_va_list (void)
5868 if (EABI_FLOAT_VARARGS_P
)
5870 /* We keep 3 pointers, and two offsets.
5872 Two pointers are to the overflow area, which starts at the CFA.
5873 One of these is constant, for addressing into the GPR save area
5874 below it. The other is advanced up the stack through the
5877 The third pointer is to the bottom of the GPR save area.
5878 Since the FPR save area is just below it, we can address
5879 FPR slots off this pointer.
5881 We also keep two one-byte offsets, which are to be subtracted
5882 from the constant pointers to yield addresses in the GPR and
5883 FPR save areas. These are downcounted as float or non-float
5884 arguments are used, and when they get to zero, the argument
5885 must be obtained from the overflow region. */
5886 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5889 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5891 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5892 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5894 f_gtop
= build_decl (BUILTINS_LOCATION
,
5895 FIELD_DECL
, get_identifier ("__gpr_top"),
5897 f_ftop
= build_decl (BUILTINS_LOCATION
,
5898 FIELD_DECL
, get_identifier ("__fpr_top"),
5900 f_goff
= build_decl (BUILTINS_LOCATION
,
5901 FIELD_DECL
, get_identifier ("__gpr_offset"),
5902 unsigned_char_type_node
);
5903 f_foff
= build_decl (BUILTINS_LOCATION
,
5904 FIELD_DECL
, get_identifier ("__fpr_offset"),
5905 unsigned_char_type_node
);
5906 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5907 warn on every user file. */
5908 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5909 array
= build_array_type (unsigned_char_type_node
,
5910 build_index_type (index
));
5911 f_res
= build_decl (BUILTINS_LOCATION
,
5912 FIELD_DECL
, get_identifier ("__reserved"), array
);
5914 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5915 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5916 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5917 DECL_FIELD_CONTEXT (f_goff
) = record
;
5918 DECL_FIELD_CONTEXT (f_foff
) = record
;
5919 DECL_FIELD_CONTEXT (f_res
) = record
;
5921 TYPE_FIELDS (record
) = f_ovfl
;
5922 DECL_CHAIN (f_ovfl
) = f_gtop
;
5923 DECL_CHAIN (f_gtop
) = f_ftop
;
5924 DECL_CHAIN (f_ftop
) = f_goff
;
5925 DECL_CHAIN (f_goff
) = f_foff
;
5926 DECL_CHAIN (f_foff
) = f_res
;
5928 layout_type (record
);
5932 /* Otherwise, we use 'void *'. */
5933 return ptr_type_node
;
5936 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5939 mips_va_start (tree valist
, rtx nextarg
)
5941 if (EABI_FLOAT_VARARGS_P
)
5943 const CUMULATIVE_ARGS
*cum
;
5944 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5945 tree ovfl
, gtop
, ftop
, goff
, foff
;
5947 int gpr_save_area_size
;
5948 int fpr_save_area_size
;
5951 cum
= &crtl
->args
.info
;
5953 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5955 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5957 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5958 f_gtop
= DECL_CHAIN (f_ovfl
);
5959 f_ftop
= DECL_CHAIN (f_gtop
);
5960 f_goff
= DECL_CHAIN (f_ftop
);
5961 f_foff
= DECL_CHAIN (f_goff
);
5963 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5965 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5967 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5969 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5971 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5974 /* Emit code to initialize OVFL, which points to the next varargs
5975 stack argument. CUM->STACK_WORDS gives the number of stack
5976 words used by named arguments. */
5977 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5978 if (cum
->stack_words
> 0)
5979 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
5980 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5981 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5983 /* Emit code to initialize GTOP, the top of the GPR save area. */
5984 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5985 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5986 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5988 /* Emit code to initialize FTOP, the top of the FPR save area.
5989 This address is gpr_save_area_bytes below GTOP, rounded
5990 down to the next fp-aligned boundary. */
5991 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5992 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5993 fpr_offset
&= -UNITS_PER_FPVALUE
;
5995 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
5996 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5997 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5999 /* Emit code to initialize GOFF, the offset from GTOP of the
6000 next GPR argument. */
6001 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
6002 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
6003 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6005 /* Likewise emit code to initialize FOFF, the offset from FTOP
6006 of the next FPR argument. */
6007 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
6008 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
6009 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6013 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
6014 std_expand_builtin_va_start (valist
, nextarg
);
6018 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6022 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6025 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
6026 unsigned HOST_WIDE_INT align
, boundary
;
6029 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6031 type
= build_pointer_type (type
);
6033 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
6034 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
6036 /* When we align parameter on stack for caller, if the parameter
6037 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6038 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6039 here with caller. */
6040 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
6041 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
6043 boundary
/= BITS_PER_UNIT
;
6045 /* Hoist the valist value into a temporary for the moment. */
6046 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
6048 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6049 requires greater alignment, we must perform dynamic alignment. */
6050 if (boundary
> align
)
6052 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6053 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
6054 gimplify_and_add (t
, pre_p
);
6056 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6057 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
6059 build_int_cst (TREE_TYPE (valist
), -boundary
)));
6060 gimplify_and_add (t
, pre_p
);
6065 /* If the actual alignment is less than the alignment of the type,
6066 adjust the type accordingly so that we don't assume strict alignment
6067 when dereferencing the pointer. */
6068 boundary
*= BITS_PER_UNIT
;
6069 if (boundary
< TYPE_ALIGN (type
))
6071 type
= build_variant_type_copy (type
);
6072 TYPE_ALIGN (type
) = boundary
;
6075 /* Compute the rounded size of the type. */
6076 type_size
= size_in_bytes (type
);
6077 rounded_size
= round_up (type_size
, align
);
6079 /* Reduce rounded_size so it's sharable with the postqueue. */
6080 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6084 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
6086 /* Small args are padded downward. */
6087 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
6088 rounded_size
, size_int (align
));
6089 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
6090 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
6091 addr
= fold_build_pointer_plus (addr
, t
);
6094 /* Compute new value for AP. */
6095 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
6096 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
6097 gimplify_and_add (t
, pre_p
);
6099 addr
= fold_convert (build_pointer_type (type
), addr
);
6102 addr
= build_va_arg_indirect_ref (addr
);
6104 return build_va_arg_indirect_ref (addr
);
6107 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6110 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6116 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
6118 type
= build_pointer_type (type
);
6120 if (!EABI_FLOAT_VARARGS_P
)
6121 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6124 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6125 tree ovfl
, top
, off
, align
;
6126 HOST_WIDE_INT size
, rsize
, osize
;
6129 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6130 f_gtop
= DECL_CHAIN (f_ovfl
);
6131 f_ftop
= DECL_CHAIN (f_gtop
);
6132 f_goff
= DECL_CHAIN (f_ftop
);
6133 f_foff
= DECL_CHAIN (f_goff
);
6137 TOP be the top of the GPR or FPR save area;
6138 OFF be the offset from TOP of the next register;
6139 ADDR_RTX be the address of the argument;
6140 SIZE be the number of bytes in the argument type;
6141 RSIZE be the number of bytes used to store the argument
6142 when it's in the register save area; and
6143 OSIZE be the number of bytes used to store it when it's
6144 in the stack overflow area.
6146 The code we want is:
6148 1: off &= -rsize; // round down
6151 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6156 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6157 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6161 [1] and [9] can sometimes be optimized away. */
6163 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6165 size
= int_size_in_bytes (type
);
6167 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6168 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6170 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6171 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6172 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6173 unshare_expr (valist
), f_foff
, NULL_TREE
);
6175 /* When va_start saves FPR arguments to the stack, each slot
6176 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6177 argument's precision. */
6178 rsize
= UNITS_PER_HWFPVALUE
;
6180 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6181 (= PARM_BOUNDARY bits). This can be different from RSIZE
6184 (1) On 32-bit targets when TYPE is a structure such as:
6186 struct s { float f; };
6188 Such structures are passed in paired FPRs, so RSIZE
6189 will be 8 bytes. However, the structure only takes
6190 up 4 bytes of memory, so OSIZE will only be 4.
6192 (2) In combinations such as -mgp64 -msingle-float
6193 -fshort-double. Doubles passed in registers will then take
6194 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6195 stack take up UNITS_PER_WORD bytes. */
6196 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6200 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6201 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6202 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6203 unshare_expr (valist
), f_goff
, NULL_TREE
);
6204 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6205 if (rsize
> UNITS_PER_WORD
)
6207 /* [1] Emit code for: off &= -rsize. */
6208 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6209 build_int_cst (TREE_TYPE (off
), -rsize
));
6210 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6215 /* [2] Emit code to branch if off == 0. */
6216 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6217 build_int_cst (TREE_TYPE (off
), 0));
6218 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6220 /* [5] Emit code for: off -= rsize. We do this as a form of
6221 post-decrement not available to C. */
6222 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6223 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6225 /* [4] Emit code for:
6226 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6227 t
= fold_convert (sizetype
, t
);
6228 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6229 t
= fold_build_pointer_plus (top
, t
);
6230 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6231 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6232 COND_EXPR_THEN (addr
) = t
;
6234 if (osize
> UNITS_PER_WORD
)
6236 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6237 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6238 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6239 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6240 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6241 unshare_expr (ovfl
), t
);
6246 /* [10, 11] Emit code for:
6247 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6249 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6250 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6251 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6252 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6254 /* String [9] and [10, 11] together. */
6256 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6257 COND_EXPR_ELSE (addr
) = t
;
6259 addr
= fold_convert (build_pointer_type (type
), addr
);
6260 addr
= build_va_arg_indirect_ref (addr
);
6264 addr
= build_va_arg_indirect_ref (addr
);
6269 /* Declare a unique, locally-binding function called NAME, then start
6273 mips_start_unique_function (const char *name
)
6277 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6278 get_identifier (name
),
6279 build_function_type_list (void_type_node
, NULL_TREE
));
6280 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6281 NULL_TREE
, void_type_node
);
6282 TREE_PUBLIC (decl
) = 1;
6283 TREE_STATIC (decl
) = 1;
6285 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
6287 targetm
.asm_out
.unique_section (decl
, 0);
6288 switch_to_section (get_named_section (decl
, NULL
, 0));
6290 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6291 fputs ("\t.hidden\t", asm_out_file
);
6292 assemble_name (asm_out_file
, name
);
6293 putc ('\n', asm_out_file
);
6296 /* Start a definition of function NAME. MIPS16_P indicates whether the
6297 function contains MIPS16 code. */
6300 mips_start_function_definition (const char *name
, bool mips16_p
)
6303 fprintf (asm_out_file
, "\t.set\tmips16\n");
6305 fprintf (asm_out_file
, "\t.set\tnomips16\n");
6307 if (TARGET_MICROMIPS
)
6308 fprintf (asm_out_file
, "\t.set\tmicromips\n");
6309 #ifdef HAVE_GAS_MICROMIPS
6311 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
6314 if (!flag_inhibit_size_directive
)
6316 fputs ("\t.ent\t", asm_out_file
);
6317 assemble_name (asm_out_file
, name
);
6318 fputs ("\n", asm_out_file
);
6321 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
6323 /* Start the definition proper. */
6324 assemble_name (asm_out_file
, name
);
6325 fputs (":\n", asm_out_file
);
6328 /* End a function definition started by mips_start_function_definition. */
6331 mips_end_function_definition (const char *name
)
6333 if (!flag_inhibit_size_directive
)
6335 fputs ("\t.end\t", asm_out_file
);
6336 assemble_name (asm_out_file
, name
);
6337 fputs ("\n", asm_out_file
);
6341 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
6342 then free *STUB_PTR. */
6345 mips_finish_stub (mips_one_only_stub
**stub_ptr
)
6347 mips_one_only_stub
*stub
= *stub_ptr
;
6351 const char *name
= stub
->get_name ();
6352 mips_start_unique_function (name
);
6353 mips_start_function_definition (name
, false);
6354 stub
->output_body ();
6355 mips_end_function_definition (name
);
6360 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6363 mips_ok_for_lazy_binding_p (rtx x
)
6365 return (TARGET_USE_GOT
6366 && GET_CODE (x
) == SYMBOL_REF
6367 && !SYMBOL_REF_BIND_NOW_P (x
)
6368 && !mips_symbol_binds_local_p (x
));
6371 /* Load function address ADDR into register DEST. TYPE is as for
6372 mips_expand_call. Return true if we used an explicit lazy-binding
6376 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
6378 /* If we're generating PIC, and this call is to a global function,
6379 try to allow its address to be resolved lazily. This isn't
6380 possible for sibcalls when $gp is call-saved because the value
6381 of $gp on entry to the stub would be our caller's gp, not ours. */
6382 if (TARGET_EXPLICIT_RELOCS
6383 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
6384 && mips_ok_for_lazy_binding_p (addr
))
6386 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
6387 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
6392 mips_emit_move (dest
, addr
);
6397 struct local_alias_traits
: default_hashmap_traits
6399 static hashval_t
hash (rtx
);
6400 static bool equal_keys (rtx
, rtx
);
6403 /* Each locally-defined hard-float MIPS16 function has a local symbol
6404 associated with it. This hash table maps the function symbol (FUNC)
6405 to the local symbol (LOCAL). */
6406 static GTY (()) hash_map
<rtx
, rtx
, local_alias_traits
> *mips16_local_aliases
;
6408 /* Hash table callbacks for mips16_local_aliases. */
6411 local_alias_traits::hash (rtx func
)
6413 return htab_hash_string (XSTR (func
, 0));
6417 local_alias_traits::equal_keys (rtx func1
, rtx func2
)
6419 return rtx_equal_p (func1
, func2
);
6422 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6423 Return a local alias for it, creating a new one if necessary. */
6426 mips16_local_alias (rtx func
)
6428 /* Create the hash table if this is the first call. */
6429 if (mips16_local_aliases
== NULL
)
6430 mips16_local_aliases
6431 = hash_map
<rtx
, rtx
, local_alias_traits
>::create_ggc (37);
6433 /* Look up the function symbol, creating a new entry if need be. */
6435 rtx
*slot
= &mips16_local_aliases
->get_or_insert (func
, &existed
);
6436 gcc_assert (slot
!= NULL
);
6440 const char *func_name
, *local_name
;
6443 /* Create a new SYMBOL_REF for the local symbol. The choice of
6444 __fn_local_* is based on the __fn_stub_* names that we've
6445 traditionally used for the non-MIPS16 stub. */
6446 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6447 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6448 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6449 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6451 /* Create a new structure to represent the mapping. */
6457 /* A chained list of functions for which mips16_build_call_stub has already
6458 generated a stub. NAME is the name of the function and FP_RET_P is true
6459 if the function returns a value in floating-point registers. */
6460 struct mips16_stub
{
6461 struct mips16_stub
*next
;
6465 static struct mips16_stub
*mips16_stubs
;
6467 /* Return the two-character string that identifies floating-point
6468 return mode MODE in the name of a MIPS16 function stub. */
6471 mips16_call_stub_mode_suffix (enum machine_mode mode
)
6475 else if (mode
== DFmode
)
6477 else if (mode
== SCmode
)
6479 else if (mode
== DCmode
)
6481 else if (mode
== V2SFmode
)
6487 /* Write instructions to move a 32-bit value between general register
6488 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6489 from GPREG to FPREG and 'f' to move in the opposite direction. */
6492 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6494 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6495 reg_names
[gpreg
], reg_names
[fpreg
]);
6498 /* Likewise for 64-bit values. */
6501 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6504 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6505 reg_names
[gpreg
], reg_names
[fpreg
]);
6506 else if (TARGET_FLOAT64
)
6508 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6509 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6510 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6511 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6515 /* Move the least-significant word. */
6516 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6517 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6518 /* ...then the most significant word. */
6519 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6520 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6524 /* Write out code to move floating-point arguments into or out of
6525 general registers. FP_CODE is the code describing which arguments
6526 are present (see the comment above the definition of CUMULATIVE_ARGS
6527 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6530 mips_output_args_xfer (int fp_code
, char direction
)
6532 unsigned int gparg
, fparg
, f
;
6533 CUMULATIVE_ARGS cum
;
6535 /* This code only works for o32 and o64. */
6536 gcc_assert (TARGET_OLDABI
);
6538 mips_init_cumulative_args (&cum
, NULL
);
6540 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6542 enum machine_mode mode
;
6543 struct mips_arg_info info
;
6547 else if ((f
& 3) == 2)
6552 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6553 gparg
= mips_arg_regno (&info
, false);
6554 fparg
= mips_arg_regno (&info
, true);
6557 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6559 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6561 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6565 /* Write a MIPS16 stub for the current function. This stub is used
6566 for functions which take arguments in the floating-point registers.
6567 It is normal-mode code that moves the floating-point arguments
6568 into the general registers and then jumps to the MIPS16 code. */
6571 mips16_build_function_stub (void)
6573 const char *fnname
, *alias_name
, *separator
;
6574 char *secname
, *stubname
;
6579 /* Create the name of the stub, and its unique section. */
6580 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6581 alias
= mips16_local_alias (symbol
);
6583 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6584 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6585 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6586 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6588 /* Build a decl for the stub. */
6589 stubdecl
= build_decl (BUILTINS_LOCATION
,
6590 FUNCTION_DECL
, get_identifier (stubname
),
6591 build_function_type_list (void_type_node
, NULL_TREE
));
6592 set_decl_section_name (stubdecl
, secname
);
6593 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6594 RESULT_DECL
, NULL_TREE
, void_type_node
);
6596 /* Output a comment. */
6597 fprintf (asm_out_file
, "\t# Stub function for %s (",
6598 current_function_name ());
6600 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6602 fprintf (asm_out_file
, "%s%s", separator
,
6603 (f
& 3) == 1 ? "float" : "double");
6606 fprintf (asm_out_file
, ")\n");
6608 /* Start the function definition. */
6609 assemble_start_function (stubdecl
, stubname
);
6610 mips_start_function_definition (stubname
, false);
6612 /* If generating pic2 code, either set up the global pointer or
6614 if (TARGET_ABICALLS_PIC2
)
6616 if (TARGET_ABSOLUTE_ABICALLS
)
6617 fprintf (asm_out_file
, "\t.option\tpic0\n");
6620 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6621 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6622 target function is. Use a local GOT access when loading the
6623 symbol, to cut down on the number of unnecessary GOT entries
6624 for stubs that aren't needed. */
6625 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6630 /* Load the address of the MIPS16 function into $25. Do this first so
6631 that targets with coprocessor interlocks can use an MFC1 to fill the
6633 output_asm_insn ("la\t%^,%0", &symbol
);
6635 /* Move the arguments from floating-point registers to general registers. */
6636 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6638 /* Jump to the MIPS16 function. */
6639 output_asm_insn ("jr\t%^", NULL
);
6641 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6642 fprintf (asm_out_file
, "\t.option\tpic2\n");
6644 mips_end_function_definition (stubname
);
6646 /* If the linker needs to create a dynamic symbol for the target
6647 function, it will associate the symbol with the stub (which,
6648 unlike the target function, follows the proper calling conventions).
6649 It is therefore useful to have a local alias for the target function,
6650 so that it can still be identified as MIPS16 code. As an optimization,
6651 this symbol can also be used for indirect MIPS16 references from
6652 within this file. */
6653 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6655 switch_to_section (function_section (current_function_decl
));
6658 /* The current function is a MIPS16 function that returns a value in an FPR.
6659 Copy the return value from its soft-float to its hard-float location.
6660 libgcc2 has special non-MIPS16 helper functions for each case. */
6663 mips16_copy_fpr_return_value (void)
6665 rtx fn
, insn
, retval
;
6667 enum machine_mode return_mode
;
6670 return_type
= DECL_RESULT (current_function_decl
);
6671 return_mode
= DECL_MODE (return_type
);
6673 name
= ACONCAT (("__mips16_ret_",
6674 mips16_call_stub_mode_suffix (return_mode
),
6676 fn
= mips16_stub_function (name
);
6678 /* The function takes arguments in $2 (and possibly $3), so calls
6679 to it cannot be lazily bound. */
6680 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6682 /* Model the call as something that takes the GPR return value as
6683 argument and returns an "updated" value. */
6684 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6685 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6686 const0_rtx
, NULL_RTX
, false);
6687 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6690 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6691 RETVAL is the location of the return value, or null if this is
6692 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6693 arguments and FP_CODE is the code built by mips_function_arg;
6694 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6696 There are three alternatives:
6698 - If a stub was needed, emit the call and return the call insn itself.
6700 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6701 to the new target and return null.
6703 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6706 A stub is needed for calls to functions that, in normal mode,
6707 receive arguments in FPRs or return values in FPRs. The stub
6708 copies the arguments from their soft-float positions to their
6709 hard-float positions, calls the real function, then copies the
6710 return value from its hard-float position to its soft-float
6713 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6714 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6715 automatically redirects the JAL to the stub, otherwise the JAL
6716 continues to call FN directly. */
6719 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6723 struct mips16_stub
*l
;
6727 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6728 we were invoked with the -msoft-float option. */
6729 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6732 /* Figure out whether the value might come back in a floating-point
6734 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6736 /* We don't need to do anything if there were no floating-point
6737 arguments and the value will not be returned in a floating-point
6739 if (fp_code
== 0 && !fp_ret_p
)
6742 /* We don't need to do anything if this is a call to a special
6743 MIPS16 support function. */
6745 if (mips16_stub_function_p (fn
))
6748 /* If we're calling a locally-defined MIPS16 function, we know that
6749 it will return values in both the "soft-float" and "hard-float"
6750 registers. There is no need to use a stub to move the latter
6752 if (fp_code
== 0 && mips16_local_function_p (fn
))
6755 /* This code will only work for o32 and o64 abis. The other ABI's
6756 require more sophisticated support. */
6757 gcc_assert (TARGET_OLDABI
);
6759 /* If we're calling via a function pointer, use one of the magic
6760 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6761 Each stub expects the function address to arrive in register $2. */
6762 if (GET_CODE (fn
) != SYMBOL_REF
6763 || !call_insn_operand (fn
, VOIDmode
))
6770 /* If this is a locally-defined and locally-binding function,
6771 avoid the stub by calling the local alias directly. */
6772 if (mips16_local_function_p (fn
))
6774 *fn_ptr
= mips16_local_alias (fn
);
6778 /* Create a SYMBOL_REF for the libgcc.a function. */
6780 sprintf (buf
, "__mips16_call_stub_%s_%d",
6781 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6784 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6785 stub_fn
= mips16_stub_function (buf
);
6787 /* The function uses $2 as an argument, so calls to it
6788 cannot be lazily bound. */
6789 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6791 /* Load the target function into $2. */
6792 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6793 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6795 /* Emit the call. */
6796 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6797 args_size
, NULL_RTX
, lazy_p
);
6799 /* Tell GCC that this call does indeed use the value of $2. */
6800 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6802 /* If we are handling a floating-point return value, we need to
6803 save $18 in the function prologue. Putting a note on the
6804 call will mean that df_regs_ever_live_p ($18) will be true if the
6805 call is not eliminated, and we can check that in the prologue
6808 CALL_INSN_FUNCTION_USAGE (insn
) =
6809 gen_rtx_EXPR_LIST (VOIDmode
,
6810 gen_rtx_CLOBBER (VOIDmode
,
6811 gen_rtx_REG (word_mode
, 18)),
6812 CALL_INSN_FUNCTION_USAGE (insn
));
6817 /* We know the function we are going to call. If we have already
6818 built a stub, we don't need to do anything further. */
6819 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6820 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6821 if (strcmp (l
->name
, fnname
) == 0)
6826 const char *separator
;
6827 char *secname
, *stubname
;
6828 tree stubid
, stubdecl
;
6831 /* If the function does not return in FPRs, the special stub
6835 If the function does return in FPRs, the stub section is named
6836 .mips16.call.fp.FNNAME
6838 Build a decl for the stub. */
6839 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6841 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6843 stubid
= get_identifier (stubname
);
6844 stubdecl
= build_decl (BUILTINS_LOCATION
,
6845 FUNCTION_DECL
, stubid
,
6846 build_function_type_list (void_type_node
,
6848 set_decl_section_name (stubdecl
, secname
);
6849 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6850 RESULT_DECL
, NULL_TREE
,
6853 /* Output a comment. */
6854 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6856 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6860 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6862 fprintf (asm_out_file
, "%s%s", separator
,
6863 (f
& 3) == 1 ? "float" : "double");
6866 fprintf (asm_out_file
, ")\n");
6868 /* Start the function definition. */
6869 assemble_start_function (stubdecl
, stubname
);
6870 mips_start_function_definition (stubname
, false);
6874 fprintf (asm_out_file
, "\t.cfi_startproc\n");
6876 /* Create a fake CFA 4 bytes below the stack pointer.
6877 This works around unwinders (like libgcc's) that expect
6878 the CFA for non-signal frames to be unique. */
6879 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
6881 /* "Save" $sp in itself so we don't use the fake CFA.
6882 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6883 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
6887 /* Load the address of the MIPS16 function into $25. Do this
6888 first so that targets with coprocessor interlocks can use
6889 an MFC1 to fill the delay slot. */
6890 if (TARGET_EXPLICIT_RELOCS
)
6892 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6893 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6896 output_asm_insn ("la\t%^,%0", &fn
);
6899 /* Move the arguments from general registers to floating-point
6901 mips_output_args_xfer (fp_code
, 't');
6905 /* Save the return address in $18 and call the non-MIPS16 function.
6906 The stub's caller knows that $18 might be clobbered, even though
6907 $18 is usually a call-saved register. */
6908 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6909 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6910 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6911 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
6913 /* Move the result from floating-point registers to
6914 general registers. */
6915 switch (GET_MODE (retval
))
6918 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6920 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6922 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6923 TARGET_LITTLE_ENDIAN
6924 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6926 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6928 /* On 64-bit targets, complex floats are returned in
6929 a single GPR, such that "sd" on a suitably-aligned
6930 target would store the value correctly. */
6931 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6932 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6933 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6934 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6935 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6936 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6937 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6938 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6939 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6940 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6941 reg_names
[GP_RETURN
],
6942 reg_names
[GP_RETURN
],
6943 reg_names
[GP_RETURN
+ 1]);
6948 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6952 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6953 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6957 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6963 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6964 fprintf (asm_out_file
, "\t.cfi_endproc\n");
6968 /* Jump to the previously-loaded address. */
6969 output_asm_insn ("jr\t%^", NULL
);
6972 #ifdef ASM_DECLARE_FUNCTION_SIZE
6973 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6976 mips_end_function_definition (stubname
);
6978 /* Record this stub. */
6979 l
= XNEW (struct mips16_stub
);
6980 l
->name
= xstrdup (fnname
);
6981 l
->fp_ret_p
= fp_ret_p
;
6982 l
->next
= mips16_stubs
;
6986 /* If we expect a floating-point return value, but we've built a
6987 stub which does not expect one, then we're in trouble. We can't
6988 use the existing stub, because it won't handle the floating-point
6989 value. We can't build a new stub, because the linker won't know
6990 which stub to use for the various calls in this object file.
6991 Fortunately, this case is illegal, since it means that a function
6992 was declared in two different ways in a single compilation. */
6993 if (fp_ret_p
&& !l
->fp_ret_p
)
6994 error ("cannot handle inconsistent calls to %qs", fnname
);
6996 if (retval
== NULL_RTX
)
6997 pattern
= gen_call_internal_direct (fn
, args_size
);
6999 pattern
= gen_call_value_internal_direct (retval
, fn
, args_size
);
7000 insn
= mips_emit_call_insn (pattern
, fn
, fn
, false);
7002 /* If we are calling a stub which handles a floating-point return
7003 value, we need to arrange to save $18 in the prologue. We do this
7004 by marking the function call as using the register. The prologue
7005 will later see that it is used, and emit code to save it. */
7007 CALL_INSN_FUNCTION_USAGE (insn
) =
7008 gen_rtx_EXPR_LIST (VOIDmode
,
7009 gen_rtx_CLOBBER (VOIDmode
,
7010 gen_rtx_REG (word_mode
, 18)),
7011 CALL_INSN_FUNCTION_USAGE (insn
));
7016 /* Expand a call of type TYPE. RESULT is where the result will go (null
7017 for "call"s and "sibcall"s), ADDR is the address of the function,
7018 ARGS_SIZE is the size of the arguments and AUX is the value passed
7019 to us by mips_function_arg. LAZY_P is true if this call already
7020 involves a lazily-bound function address (such as when calling
7021 functions through a MIPS16 hard-float stub).
7023 Return the call itself. */
7026 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
7027 rtx args_size
, rtx aux
, bool lazy_p
)
7029 rtx orig_addr
, pattern
;
7033 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
7034 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
7037 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
7042 if (!call_insn_operand (addr
, VOIDmode
))
7044 if (type
== MIPS_CALL_EPILOGUE
)
7045 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
7047 addr
= gen_reg_rtx (Pmode
);
7048 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
7053 rtx (*fn
) (rtx
, rtx
);
7055 if (type
== MIPS_CALL_SIBCALL
)
7056 fn
= gen_sibcall_internal
;
7058 fn
= gen_call_internal
;
7060 pattern
= fn (addr
, args_size
);
7062 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
7064 /* Handle return values created by mips_return_fpr_pair. */
7065 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
7068 if (type
== MIPS_CALL_SIBCALL
)
7069 fn
= gen_sibcall_value_multiple_internal
;
7071 fn
= gen_call_value_multiple_internal
;
7073 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
7074 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
7075 pattern
= fn (reg1
, addr
, args_size
, reg2
);
7079 rtx (*fn
) (rtx
, rtx
, rtx
);
7081 if (type
== MIPS_CALL_SIBCALL
)
7082 fn
= gen_sibcall_value_internal
;
7084 fn
= gen_call_value_internal
;
7086 /* Handle return values created by mips_return_fpr_single. */
7087 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
7088 result
= XEXP (XVECEXP (result
, 0, 0), 0);
7089 pattern
= fn (result
, addr
, args_size
);
7092 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
7095 /* Split call instruction INSN into a $gp-clobbering call and
7096 (where necessary) an instruction to restore $gp from its save slot.
7097 CALL_PATTERN is the pattern of the new call. */
7100 mips_split_call (rtx insn
, rtx call_pattern
)
7102 emit_call_insn (call_pattern
);
7103 if (!find_reg_note (insn
, REG_NORETURN
, 0))
7104 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
,
7105 POST_CALL_TMP_REG
));
7108 /* Return true if a call to DECL may need to use JALX. */
7111 mips_call_may_need_jalx_p (tree decl
)
7113 /* If the current translation unit would use a different mode for DECL,
7114 assume that the call needs JALX. */
7115 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
7118 /* mips_get_compress_mode is always accurate for locally-binding
7119 functions in the current translation unit. */
7120 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
7123 /* When -minterlink-compressed is in effect, assume that functions
7124 could use a different encoding mode unless an attribute explicitly
7125 tells us otherwise. */
7126 if (TARGET_INTERLINK_COMPRESSED
)
7128 if (!TARGET_COMPRESSION
7129 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
7131 if (TARGET_COMPRESSION
7132 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
7139 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7142 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7144 if (!TARGET_SIBCALLS
)
7147 /* Interrupt handlers need special epilogue code and therefore can't
7149 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7152 /* Direct Js are only possible to functions that use the same ISA encoding.
7153 There is no JX counterpoart of JALX. */
7155 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7156 && mips_call_may_need_jalx_p (decl
))
7159 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7160 require $gp to be valid on entry, so sibcalls can only use stubs
7161 if $gp is call-clobbered. */
7163 && TARGET_CALL_SAVED_GP
7164 && !TARGET_ABICALLS_PIC0
7165 && !targetm
.binds_local_p (decl
))
7172 /* Implement MOVE_BY_PIECES_P. */
7175 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7179 /* movmemsi is meant to generate code that is at least as good as
7180 move_by_pieces. However, movmemsi effectively uses a by-pieces
7181 implementation both for moves smaller than a word and for
7182 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7183 bytes. We should allow the tree-level optimisers to do such
7184 moves by pieces, as it often exposes other optimization
7185 opportunities. We might as well continue to use movmemsi at
7186 the rtl level though, as it produces better code when
7187 scheduling is disabled (such as at -O). */
7188 if (currently_expanding_to_rtl
)
7190 if (align
< BITS_PER_WORD
)
7191 return size
< UNITS_PER_WORD
;
7192 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7194 /* The default value. If this becomes a target hook, we should
7195 call the default definition instead. */
7196 return (move_by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1)
7197 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7200 /* Implement STORE_BY_PIECES_P. */
7203 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7205 /* Storing by pieces involves moving constants into registers
7206 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7207 We need to decide whether it is cheaper to load the address of
7208 constant data into a register and use a block move instead. */
7210 /* If the data is only byte aligned, then:
7212 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7213 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7216 (a2) A block move of 4 bytes from aligned source data can use an
7217 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7218 4 SBs that we would generate when storing by pieces. */
7219 if (align
<= BITS_PER_UNIT
)
7222 /* If the data is 2-byte aligned, then:
7224 (b1) A block move of less than 4 bytes would use a combination of LBs,
7225 LHs, SBs and SHs. We get better code by using single-instruction
7226 LIs, SBs and SHs instead.
7228 (b2) A block move of 4 bytes from aligned source data would again use
7229 an LW/SWL/SWR sequence. In most cases, loading the address of
7230 the source data would require at least one extra instruction.
7231 It is often more efficient to use 2 single-instruction LIs and
7234 (b3) A block move of up to 3 additional bytes would be like (b1).
7236 (b4) A block move of 8 bytes from aligned source data can use two
7237 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7238 sequences are better than the 4 LIs and 4 SHs that we'd generate
7239 when storing by pieces.
7241 The reasoning for higher alignments is similar:
7243 (c1) A block move of less than 4 bytes would be the same as (b1).
7245 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7246 loading the address of the source data would typically require
7247 at least one extra instruction. It is generally better to use
7250 (c3) A block move of up to 3 additional bytes would be like (b1).
7252 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7253 LD/SD sequence, and in these cases we've traditionally preferred
7254 the memory copy over the more bulky constant moves. */
7258 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7259 Assume that the areas do not overlap. */
7262 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7264 HOST_WIDE_INT offset
, delta
;
7265 unsigned HOST_WIDE_INT bits
;
7267 enum machine_mode mode
;
7270 /* Work out how many bits to move at a time. If both operands have
7271 half-word alignment, it is usually better to move in half words.
7272 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7273 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7274 Otherwise move word-sized chunks. */
7275 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7276 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7277 bits
= BITS_PER_WORD
/ 2;
7279 bits
= BITS_PER_WORD
;
7281 mode
= mode_for_size (bits
, MODE_INT
, 0);
7282 delta
= bits
/ BITS_PER_UNIT
;
7284 /* Allocate a buffer for the temporary registers. */
7285 regs
= XALLOCAVEC (rtx
, length
/ delta
);
7287 /* Load as many BITS-sized chunks as possible. Use a normal load if
7288 the source has enough alignment, otherwise use left/right pairs. */
7289 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7291 regs
[i
] = gen_reg_rtx (mode
);
7292 if (MEM_ALIGN (src
) >= bits
)
7293 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
7296 rtx part
= adjust_address (src
, BLKmode
, offset
);
7297 set_mem_size (part
, delta
);
7298 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
7303 /* Copy the chunks to the destination. */
7304 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7305 if (MEM_ALIGN (dest
) >= bits
)
7306 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
7309 rtx part
= adjust_address (dest
, BLKmode
, offset
);
7310 set_mem_size (part
, delta
);
7311 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
7315 /* Mop up any left-over bytes. */
7316 if (offset
< length
)
7318 src
= adjust_address (src
, BLKmode
, offset
);
7319 dest
= adjust_address (dest
, BLKmode
, offset
);
7320 move_by_pieces (dest
, src
, length
- offset
,
7321 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
7325 /* Helper function for doing a loop-based block operation on memory
7326 reference MEM. Each iteration of the loop will operate on LENGTH
7329 Create a new base register for use within the loop and point it to
7330 the start of MEM. Create a new memory reference that uses this
7331 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7334 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
7335 rtx
*loop_reg
, rtx
*loop_mem
)
7337 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
7339 /* Although the new mem does not refer to a known location,
7340 it does keep up to LENGTH bytes of alignment. */
7341 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
7342 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
7345 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7346 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7347 the memory regions do not overlap. */
7350 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
7351 HOST_WIDE_INT bytes_per_iter
)
7353 rtx_code_label
*label
;
7354 rtx src_reg
, dest_reg
, final_src
, test
;
7355 HOST_WIDE_INT leftover
;
7357 leftover
= length
% bytes_per_iter
;
7360 /* Create registers and memory references for use within the loop. */
7361 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
7362 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
7364 /* Calculate the value that SRC_REG should have after the last iteration
7366 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
7369 /* Emit the start of the loop. */
7370 label
= gen_label_rtx ();
7373 /* Emit the loop body. */
7374 mips_block_move_straight (dest
, src
, bytes_per_iter
);
7376 /* Move on to the next block. */
7377 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
7378 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
7380 /* Emit the loop condition. */
7381 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7382 if (Pmode
== DImode
)
7383 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7385 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7387 /* Mop up any left-over bytes. */
7389 mips_block_move_straight (dest
, src
, leftover
);
7392 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7393 memory reference SRC to memory reference DEST. */
7396 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7398 if (CONST_INT_P (length
))
7400 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7402 mips_block_move_straight (dest
, src
, INTVAL (length
));
7407 mips_block_move_loop (dest
, src
, INTVAL (length
),
7408 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7415 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7418 mips_expand_synci_loop (rtx begin
, rtx end
)
7420 rtx inc
, cmp_result
, mask
, length
;
7421 rtx_code_label
*label
, *end_label
;
7423 /* Create end_label. */
7424 end_label
= gen_label_rtx ();
7426 /* Check if begin equals end. */
7427 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7428 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7430 /* Load INC with the cache line size (rdhwr INC,$1). */
7431 inc
= gen_reg_rtx (Pmode
);
7432 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7434 /* Check if inc is 0. */
7435 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7436 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7438 /* Calculate mask. */
7439 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7441 /* Mask out begin by mask. */
7442 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7444 /* Calculate length. */
7445 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7447 /* Loop back to here. */
7448 label
= gen_label_rtx ();
7451 emit_insn (gen_synci (begin
));
7453 /* Update length. */
7454 mips_emit_binary (MINUS
, length
, length
, inc
);
7457 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7459 /* Check if length is greater than 0. */
7460 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7461 emit_jump_insn (gen_condjump (cmp_result
, label
));
7463 emit_label (end_label
);
7466 /* Expand a QI or HI mode atomic memory operation.
7468 GENERATOR contains a pointer to the gen_* function that generates
7469 the SI mode underlying atomic operation using masks that we
7472 RESULT is the return register for the operation. Its value is NULL
7475 MEM is the location of the atomic access.
7477 OLDVAL is the first operand for the operation.
7479 NEWVAL is the optional second operand for the operation. Its value
7480 is NULL if unused. */
7483 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7484 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7486 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7487 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7489 enum machine_mode mode
;
7491 mode
= GET_MODE (mem
);
7493 /* Compute the address of the containing SImode value. */
7494 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7495 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7496 force_reg (Pmode
, GEN_INT (-4)));
7498 /* Create a memory reference for it. */
7499 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7500 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7501 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7503 /* Work out the byte offset of the QImode or HImode value,
7504 counting from the least significant byte. */
7505 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7506 if (TARGET_BIG_ENDIAN
)
7507 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7509 /* Multiply by eight to convert the shift value from bytes to bits. */
7510 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7512 /* Make the final shift an SImode value, so that it can be used in
7513 SImode operations. */
7514 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7516 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7517 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7518 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7519 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7521 /* Compute the equivalent exclusive mask. */
7522 inverted_mask
= gen_reg_rtx (SImode
);
7523 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
7524 gen_rtx_NOT (SImode
, mask
)));
7526 /* Shift the old value into place. */
7527 if (oldval
!= const0_rtx
)
7529 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7530 oldval
= force_reg (SImode
, oldval
);
7531 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7534 /* Do the same for the new value. */
7535 if (newval
&& newval
!= const0_rtx
)
7537 newval
= convert_modes (SImode
, mode
, newval
, true);
7538 newval
= force_reg (SImode
, newval
);
7539 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7542 /* Do the SImode atomic access. */
7544 res
= gen_reg_rtx (SImode
);
7546 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7548 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7550 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7556 /* Shift and convert the result. */
7557 mips_emit_binary (AND
, res
, res
, mask
);
7558 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7559 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7563 /* Return true if it is possible to use left/right accesses for a
7564 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7565 When returning true, update *LEFT and *RIGHT as follows:
7567 *LEFT is a QImode reference to the first byte if big endian or
7568 the last byte if little endian. This address can be used in the
7569 left-side instructions (LWL, SWL, LDL, SDL).
7571 *RIGHT is a QImode reference to the opposite end of the field and
7572 can be used in the patterning right-side instruction. */
7575 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7576 rtx
*left
, rtx
*right
)
7580 /* Check that the size is valid. */
7581 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7584 /* We can only access byte-aligned values. Since we are always passed
7585 a reference to the first byte of the field, it is not necessary to
7586 do anything with BITPOS after this check. */
7587 if (bitpos
% BITS_PER_UNIT
!= 0)
7590 /* Reject aligned bitfields: we want to use a normal load or store
7591 instead of a left/right pair. */
7592 if (MEM_ALIGN (op
) >= width
)
7595 /* Get references to both ends of the field. */
7596 first
= adjust_address (op
, QImode
, 0);
7597 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7599 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7600 correspond to the MSB and RIGHT to the LSB. */
7601 if (TARGET_BIG_ENDIAN
)
7602 *left
= first
, *right
= last
;
7604 *left
= last
, *right
= first
;
7609 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7610 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7611 the operation is the equivalent of:
7613 (set DEST (*_extract SRC WIDTH BITPOS))
7615 Return true on success. */
7618 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7619 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7621 rtx left
, right
, temp
;
7622 rtx dest1
= NULL_RTX
;
7624 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7625 be a DImode, create a new temp and emit a zero extend at the end. */
7626 if (GET_MODE (dest
) == DImode
7628 && GET_MODE_BITSIZE (SImode
) == width
)
7631 dest
= gen_reg_rtx (SImode
);
7634 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
7637 temp
= gen_reg_rtx (GET_MODE (dest
));
7638 if (GET_MODE (dest
) == DImode
)
7640 emit_insn (gen_mov_ldl (temp
, src
, left
));
7641 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7645 emit_insn (gen_mov_lwl (temp
, src
, left
));
7646 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7649 /* If we were loading 32bits and the original register was DI then
7650 sign/zero extend into the orignal dest. */
7654 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7656 emit_insn (gen_extendsidi2 (dest1
, dest
));
7661 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7662 BITPOS and SRC are the operands passed to the expander; the operation
7663 is the equivalent of:
7665 (set (zero_extract DEST WIDTH BITPOS) SRC)
7667 Return true on success. */
7670 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7671 HOST_WIDE_INT bitpos
)
7674 enum machine_mode mode
;
7676 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
7679 mode
= mode_for_size (width
, MODE_INT
, 0);
7680 src
= gen_lowpart (mode
, src
);
7683 emit_insn (gen_mov_sdl (dest
, src
, left
));
7684 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7688 emit_insn (gen_mov_swl (dest
, src
, left
));
7689 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7694 /* Return true if X is a MEM with the same size as MODE. */
7697 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
7700 && MEM_SIZE_KNOWN_P (x
)
7701 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7704 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7705 source of an "ext" instruction or the destination of an "ins"
7706 instruction. OP must be a register operand and the following
7707 conditions must hold:
7709 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7710 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7711 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7713 Also reject lengths equal to a word as they are better handled
7714 by the move patterns. */
7717 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7719 if (!ISA_HAS_EXT_INS
7720 || !register_operand (op
, VOIDmode
)
7721 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7724 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7727 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7733 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7734 operation if MAXLEN is the maxium length of consecutive bits that
7735 can make up MASK. MODE is the mode of the operation. See
7736 mask_low_and_shift_len for the actual definition. */
7739 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7741 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7744 /* Return true iff OP1 and OP2 are valid operands together for the
7745 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7746 see the table in the comment before the pattern. */
7749 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7751 return (memory_operand (op1
, mode
)
7752 ? and_load_operand (op2
, mode
)
7753 : and_reg_operand (op2
, mode
));
7756 /* The canonical form of a mask-low-and-shift-left operation is
7757 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7758 cleared. Thus we need to shift MASK to the right before checking if it
7759 is a valid mask value. MODE is the mode of the operation. If true
7760 return the length of the mask, otherwise return -1. */
7763 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7765 HOST_WIDE_INT shval
;
7767 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7768 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7771 /* Return true if -msplit-addresses is selected and should be honored.
7773 -msplit-addresses is a half-way house between explicit relocations
7774 and the traditional assembler macros. It can split absolute 32-bit
7775 symbolic constants into a high/lo_sum pair but uses macros for other
7778 Like explicit relocation support for REL targets, it relies
7779 on GNU extensions in the assembler and the linker.
7781 Although this code should work for -O0, it has traditionally
7782 been treated as an optimization. */
7785 mips_split_addresses_p (void)
7787 return (TARGET_SPLIT_ADDRESSES
7791 && !ABI_HAS_64BIT_SYMBOLS
);
7794 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7797 mips_init_relocs (void)
7799 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7800 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7801 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
7802 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7803 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7805 if (TARGET_MIPS16_PCREL_LOADS
)
7806 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
7809 if (ABI_HAS_64BIT_SYMBOLS
)
7811 if (TARGET_EXPLICIT_RELOCS
)
7813 mips_split_p
[SYMBOL_64_HIGH
] = true;
7814 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7815 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7817 mips_split_p
[SYMBOL_64_MID
] = true;
7818 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7819 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7821 mips_split_p
[SYMBOL_64_LOW
] = true;
7822 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7823 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7825 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7826 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7831 if (TARGET_EXPLICIT_RELOCS
7832 || mips_split_addresses_p ()
7835 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7836 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7837 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7844 /* The high part is provided by a pseudo copy of $gp. */
7845 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7846 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7848 else if (TARGET_EXPLICIT_RELOCS
)
7849 /* Small data constants are kept whole until after reload,
7850 then lowered by mips_rewrite_small_data. */
7851 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7853 if (TARGET_EXPLICIT_RELOCS
)
7855 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7858 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7859 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7863 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7864 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7867 /* Expose the use of $28 as soon as possible. */
7868 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7872 /* The HIGH and LO_SUM are matched by special .md patterns. */
7873 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7875 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7876 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7877 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7879 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7880 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7881 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7886 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7888 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7889 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7891 /* Expose the use of $28 as soon as possible. */
7892 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7898 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7899 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7900 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7903 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7904 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7906 if (TARGET_MIPS16_PCREL_LOADS
)
7908 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
7909 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
7913 mips_split_p
[SYMBOL_DTPREL
] = true;
7914 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7915 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7917 mips_split_p
[SYMBOL_TPREL
] = true;
7918 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7919 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7922 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7923 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7926 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7927 in context CONTEXT. RELOCS is the array of relocations to use. */
7930 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7931 const char **relocs
)
7933 enum mips_symbol_type symbol_type
;
7936 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7937 gcc_assert (relocs
[symbol_type
]);
7939 fputs (relocs
[symbol_type
], file
);
7940 output_addr_const (file
, mips_strip_unspec_address (op
));
7941 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7946 /* Start a new block with the given asm switch enabled. If we need
7947 to print a directive, emit PREFIX before it and SUFFIX after it. */
7950 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7951 const char *prefix
, const char *suffix
)
7953 if (asm_switch
->nesting_level
== 0)
7954 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
7955 asm_switch
->nesting_level
++;
7958 /* Likewise, but end a block. */
7961 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7962 const char *prefix
, const char *suffix
)
7964 gcc_assert (asm_switch
->nesting_level
);
7965 asm_switch
->nesting_level
--;
7966 if (asm_switch
->nesting_level
== 0)
7967 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
7970 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7971 that either print a complete line or print nothing. */
7974 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
7976 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
7980 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
7982 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
7985 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7986 The punctuation characters are:
7988 '(' Start a nested ".set noreorder" block.
7989 ')' End a nested ".set noreorder" block.
7990 '[' Start a nested ".set noat" block.
7991 ']' End a nested ".set noat" block.
7992 '<' Start a nested ".set nomacro" block.
7993 '>' End a nested ".set nomacro" block.
7994 '*' Behave like %(%< if generating a delayed-branch sequence.
7995 '#' Print a nop if in a ".set noreorder" block.
7996 '/' Like '#', but do nothing within a delayed-branch sequence.
7997 '?' Print "l" if mips_branch_likely is true
7998 '~' Print a nop if mips_branch_likely is true
7999 '.' Print the name of the register with a hard-wired zero (zero or $0).
8000 '@' Print the name of the assembler temporary register (at or $1).
8001 '^' Print the name of the pic call-through register (t9 or $25).
8002 '+' Print the name of the gp register (usually gp or $28).
8003 '$' Print the name of the stack pointer register (sp or $29).
8004 ':' Print "c" to use the compact version if the delay slot is a nop.
8005 '!' Print "s" to use the short version if the delay slot contains a
8008 See also mips_init_print_operand_pucnt. */
8011 mips_print_operand_punctuation (FILE *file
, int ch
)
8016 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
8020 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
8024 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
8028 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
8032 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
8036 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
8040 if (final_sequence
!= 0)
8042 mips_print_operand_punctuation (file
, '(');
8043 mips_print_operand_punctuation (file
, '<');
8048 if (mips_noreorder
.nesting_level
> 0)
8049 fputs ("\n\tnop", file
);
8053 /* Print an extra newline so that the delayed insn is separated
8054 from the following ones. This looks neater and is consistent
8055 with non-nop delayed sequences. */
8056 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
8057 fputs ("\n\tnop\n", file
);
8061 if (mips_branch_likely
)
8066 if (mips_branch_likely
)
8067 fputs ("\n\tnop", file
);
8071 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
8075 fputs (reg_names
[AT_REGNUM
], file
);
8079 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
8083 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
8087 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
8091 /* When final_sequence is 0, the delay slot will be a nop. We can
8092 use the compact version for microMIPS. */
8093 if (final_sequence
== 0)
8098 /* If the delay slot instruction is short, then use the
8100 if (final_sequence
== 0
8101 || get_attr_length (final_sequence
->insn (1)) == 2)
8111 /* Initialize mips_print_operand_punct. */
8114 mips_init_print_operand_punct (void)
8118 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
8119 mips_print_operand_punct
[(unsigned char) *p
] = true;
8122 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8123 associated with condition CODE. Print the condition part of the
8127 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8141 /* Conveniently, the MIPS names for these conditions are the same
8142 as their RTL equivalents. */
8143 fputs (GET_RTX_NAME (code
), file
);
8147 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8152 /* Likewise floating-point branches. */
8155 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8160 fputs ("c1f", file
);
8164 fputs ("c1t", file
);
8168 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8173 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8176 mips_print_operand_punct_valid_p (unsigned char code
)
8178 return mips_print_operand_punct
[code
];
8181 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8183 'X' Print CONST_INT OP in hexadecimal format.
8184 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8185 'd' Print CONST_INT OP in decimal.
8186 'm' Print one less than CONST_INT OP in decimal.
8187 'h' Print the high-part relocation associated with OP, after stripping
8189 'R' Print the low-part relocation associated with OP.
8190 'C' Print the integer branch condition for comparison OP.
8191 'N' Print the inverse of the integer branch condition for comparison OP.
8192 'F' Print the FPU branch condition for comparison OP.
8193 'W' Print the inverse of the FPU branch condition for comparison OP.
8194 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8195 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8196 't' Like 'T', but with the EQ/NE cases reversed
8197 'Y' Print mips_fp_conditions[INTVAL (OP)]
8198 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8199 'q' Print a DSP accumulator register.
8200 'D' Print the second part of a double-word register or memory operand.
8201 'L' Print the low-order register in a double-word register operand.
8202 'M' Print high-order register in a double-word register operand.
8203 'z' Print $0 if OP is zero, otherwise print OP normally.
8204 'b' Print the address of a memory operand, without offset. */
8207 mips_print_operand (FILE *file
, rtx op
, int letter
)
8211 if (mips_print_operand_punct_valid_p (letter
))
8213 mips_print_operand_punctuation (file
, letter
);
8218 code
= GET_CODE (op
);
8223 if (CONST_INT_P (op
))
8224 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8226 output_operand_lossage ("invalid use of '%%%c'", letter
);
8230 if (CONST_INT_P (op
))
8231 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8233 output_operand_lossage ("invalid use of '%%%c'", letter
);
8237 if (CONST_INT_P (op
))
8238 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8240 output_operand_lossage ("invalid use of '%%%c'", letter
);
8244 if (CONST_INT_P (op
))
8245 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
8247 output_operand_lossage ("invalid use of '%%%c'", letter
);
8253 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
8257 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
8261 mips_print_int_branch_condition (file
, code
, letter
);
8265 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
8269 mips_print_float_branch_condition (file
, code
, letter
);
8273 mips_print_float_branch_condition (file
, reverse_condition (code
),
8280 int truth
= (code
== NE
) == (letter
== 'T');
8281 fputc ("zfnt"[truth
* 2 + ST_REG_P (REGNO (XEXP (op
, 0)))], file
);
8286 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
8287 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
8289 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8296 mips_print_operand (file
, op
, 0);
8302 if (code
== REG
&& MD_REG_P (REGNO (op
)))
8303 fprintf (file
, "$ac0");
8304 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
8305 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
8307 output_operand_lossage ("invalid use of '%%%c'", letter
);
8315 unsigned int regno
= REGNO (op
);
8316 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
8317 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
8320 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
8321 output_operand_lossage ("invalid use of '%%%c'", letter
);
8322 /* We need to print $0 .. $31 for COP0 registers. */
8323 if (COP0_REG_P (regno
))
8324 fprintf (file
, "$%s", ®_names
[regno
][4]);
8326 fprintf (file
, "%s", reg_names
[regno
]);
8332 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
8333 else if (letter
== 'b')
8335 gcc_assert (REG_P (XEXP (op
, 0)));
8336 mips_print_operand (file
, XEXP (op
, 0), 0);
8338 else if (letter
&& letter
!= 'z')
8339 output_operand_lossage ("invalid use of '%%%c'", letter
);
8341 output_address (XEXP (op
, 0));
8345 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
8346 fputs (reg_names
[GP_REG_FIRST
], file
);
8347 else if (letter
&& letter
!= 'z')
8348 output_operand_lossage ("invalid use of '%%%c'", letter
);
8349 else if (CONST_GP_P (op
))
8350 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
8352 output_addr_const (file
, mips_strip_unspec_address (op
));
8358 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8361 mips_print_operand_address (FILE *file
, rtx x
)
8363 struct mips_address_info addr
;
8365 if (mips_classify_address (&addr
, x
, word_mode
, true))
8369 mips_print_operand (file
, addr
.offset
, 0);
8370 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8373 case ADDRESS_LO_SUM
:
8374 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8376 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8379 case ADDRESS_CONST_INT
:
8380 output_addr_const (file
, x
);
8381 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8384 case ADDRESS_SYMBOLIC
:
8385 output_addr_const (file
, mips_strip_unspec_address (x
));
8391 /* Implement TARGET_ENCODE_SECTION_INFO. */
8394 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8396 default_encode_section_info (decl
, rtl
, first
);
8398 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8400 rtx symbol
= XEXP (rtl
, 0);
8401 tree type
= TREE_TYPE (decl
);
8403 /* Encode whether the symbol is short or long. */
8404 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8405 || mips_far_type_p (type
))
8406 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8410 /* Implement TARGET_SELECT_RTX_SECTION. */
8413 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
8414 unsigned HOST_WIDE_INT align
)
8416 /* ??? Consider using mergeable small data sections. */
8417 if (mips_rtx_constant_in_small_data_p (mode
))
8418 return get_named_section (NULL
, ".sdata", 0);
8420 return default_elf_select_rtx_section (mode
, x
, align
);
8423 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8425 The complication here is that, with the combination TARGET_ABICALLS
8426 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8427 absolute addresses, and should therefore not be included in the
8428 read-only part of a DSO. Handle such cases by selecting a normal
8429 data section instead of a read-only one. The logic apes that in
8430 default_function_rodata_section. */
8433 mips_function_rodata_section (tree decl
)
8435 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8436 return default_function_rodata_section (decl
);
8438 if (decl
&& DECL_SECTION_NAME (decl
))
8440 const char *name
= DECL_SECTION_NAME (decl
);
8441 if (DECL_COMDAT_GROUP (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8443 char *rname
= ASTRDUP (name
);
8445 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8447 else if (flag_function_sections
8448 && flag_data_sections
8449 && strncmp (name
, ".text.", 6) == 0)
8451 char *rname
= ASTRDUP (name
);
8452 memcpy (rname
+ 1, "data", 4);
8453 return get_section (rname
, SECTION_WRITE
, decl
);
8456 return data_section
;
8459 /* Implement TARGET_IN_SMALL_DATA_P. */
8462 mips_in_small_data_p (const_tree decl
)
8464 unsigned HOST_WIDE_INT size
;
8466 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8469 /* We don't yet generate small-data references for -mabicalls
8470 or VxWorks RTP code. See the related -G handling in
8471 mips_option_override. */
8472 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8475 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8479 /* Reject anything that isn't in a known small-data section. */
8480 name
= DECL_SECTION_NAME (decl
);
8481 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8484 /* If a symbol is defined externally, the assembler will use the
8485 usual -G rules when deciding how to implement macros. */
8486 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8489 else if (TARGET_EMBEDDED_DATA
)
8491 /* Don't put constants into the small data section: we want them
8492 to be in ROM rather than RAM. */
8493 if (TREE_CODE (decl
) != VAR_DECL
)
8496 if (TREE_READONLY (decl
)
8497 && !TREE_SIDE_EFFECTS (decl
)
8498 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8502 /* Enforce -mlocal-sdata. */
8503 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8506 /* Enforce -mextern-sdata. */
8507 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8509 if (DECL_EXTERNAL (decl
))
8511 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8515 /* We have traditionally not treated zero-sized objects as small data,
8516 so this is now effectively part of the ABI. */
8517 size
= int_size_in_bytes (TREE_TYPE (decl
));
8518 return size
> 0 && size
<= mips_small_data_threshold
;
8521 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8522 anchors for small data: the GP register acts as an anchor in that
8523 case. We also don't want to use them for PC-relative accesses,
8524 where the PC acts as an anchor. */
8527 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8529 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8531 case SYMBOL_PC_RELATIVE
:
8532 case SYMBOL_GP_RELATIVE
:
8536 return default_use_anchors_for_symbol_p (symbol
);
8540 /* The MIPS debug format wants all automatic variables and arguments
8541 to be in terms of the virtual frame pointer (stack pointer before
8542 any adjustment in the function), while the MIPS 3.0 linker wants
8543 the frame pointer to be the stack pointer after the initial
8544 adjustment. So, we do the adjustment here. The arg pointer (which
8545 is eliminated) points to the virtual frame pointer, while the frame
8546 pointer (which may be eliminated) points to the stack pointer after
8547 the initial adjustments. */
8550 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8552 rtx offset2
= const0_rtx
;
8553 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8556 offset
= INTVAL (offset2
);
8558 if (reg
== stack_pointer_rtx
8559 || reg
== frame_pointer_rtx
8560 || reg
== hard_frame_pointer_rtx
)
8562 offset
-= cfun
->machine
->frame
.total_size
;
8563 if (reg
== hard_frame_pointer_rtx
)
8564 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8570 /* Implement ASM_OUTPUT_EXTERNAL. */
8573 mips_output_external (FILE *file
, tree decl
, const char *name
)
8575 default_elf_asm_output_external (file
, decl
, name
);
8577 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8578 set in order to avoid putting out names that are never really
8580 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8582 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8584 /* When using assembler macros, emit .extern directives for
8585 all small-data externs so that the assembler knows how
8588 In most cases it would be safe (though pointless) to emit
8589 .externs for other symbols too. One exception is when an
8590 object is within the -G limit but declared by the user to
8591 be in a section other than .sbss or .sdata. */
8592 fputs ("\t.extern\t", file
);
8593 assemble_name (file
, name
);
8594 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8595 int_size_in_bytes (TREE_TYPE (decl
)));
8600 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8603 mips_output_filename (FILE *stream
, const char *name
)
8605 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8607 if (write_symbols
== DWARF2_DEBUG
)
8609 else if (mips_output_filename_first_time
)
8611 mips_output_filename_first_time
= 0;
8612 num_source_filenames
+= 1;
8613 current_function_file
= name
;
8614 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8615 output_quoted_string (stream
, name
);
8616 putc ('\n', stream
);
8618 /* If we are emitting stabs, let dbxout.c handle this (except for
8619 the mips_output_filename_first_time case). */
8620 else if (write_symbols
== DBX_DEBUG
)
8622 else if (name
!= current_function_file
8623 && strcmp (name
, current_function_file
) != 0)
8625 num_source_filenames
+= 1;
8626 current_function_file
= name
;
8627 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8628 output_quoted_string (stream
, name
);
8629 putc ('\n', stream
);
8633 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8635 static void ATTRIBUTE_UNUSED
8636 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8641 fputs ("\t.dtprelword\t", file
);
8645 fputs ("\t.dtpreldword\t", file
);
8651 output_addr_const (file
, x
);
8652 fputs ("+0x8000", file
);
8655 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8658 mips_dwarf_register_span (rtx reg
)
8661 enum machine_mode mode
;
8663 /* By default, GCC maps increasing register numbers to increasing
8664 memory locations, but paired FPRs are always little-endian,
8665 regardless of the prevailing endianness. */
8666 mode
= GET_MODE (reg
);
8667 if (FP_REG_P (REGNO (reg
))
8668 && TARGET_BIG_ENDIAN
8669 && MAX_FPRS_PER_FMT
> 1
8670 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8672 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8673 high
= mips_subword (reg
, true);
8674 low
= mips_subword (reg
, false);
8675 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8681 /* DSP ALU can bypass data with no delays for the following pairs. */
8682 enum insn_code dspalu_bypass_table
[][2] =
8684 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
8685 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
8686 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
8687 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
8688 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
8689 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
8690 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
8691 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
8695 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
8698 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
8699 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
8700 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
8702 for (i
= 0; i
< num_bypass
; i
++)
8704 if (out_icode
== dspalu_bypass_table
[i
][0]
8705 && in_icode
== dspalu_bypass_table
[i
][1])
8711 /* Implement ASM_OUTPUT_ASCII. */
8714 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8720 fprintf (stream
, "\t.ascii\t\"");
8721 for (i
= 0; i
< len
; i
++)
8725 c
= (unsigned char) string
[i
];
8728 if (c
== '\\' || c
== '\"')
8730 putc ('\\', stream
);
8738 fprintf (stream
, "\\%03o", c
);
8742 if (cur_pos
> 72 && i
+1 < len
)
8745 fprintf (stream
, "\"\n\t.ascii\t\"");
8748 fprintf (stream
, "\"\n");
8751 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8752 Update *ADDR with the operand that should be printed. */
8755 mips_output_tls_reloc_directive (rtx
*addr
)
8757 enum mips_symbol_type type
;
8759 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
8760 *addr
= mips_strip_unspec_address (*addr
);
8764 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
8767 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
8774 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8775 macros, mark the symbol as written so that mips_asm_output_external
8776 won't emit an .extern for it. STREAM is the output file, NAME is the
8777 name of the symbol, INIT_STRING is the string that should be written
8778 before the symbol and FINAL_STRING is the string that should be
8779 written after it. FINAL_STRING is a printf format that consumes the
8780 remaining arguments. */
8783 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
8784 const char *final_string
, ...)
8788 fputs (init_string
, stream
);
8789 assemble_name (stream
, name
);
8790 va_start (ap
, final_string
);
8791 vfprintf (stream
, final_string
, ap
);
8794 if (!TARGET_EXPLICIT_RELOCS
)
8796 tree name_tree
= get_identifier (name
);
8797 TREE_ASM_WRITTEN (name_tree
) = 1;
8801 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8802 NAME is the name of the object and ALIGN is the required alignment
8803 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8804 alignment argument. */
8807 mips_declare_common_object (FILE *stream
, const char *name
,
8808 const char *init_string
,
8809 unsigned HOST_WIDE_INT size
,
8810 unsigned int align
, bool takes_alignment_p
)
8812 if (!takes_alignment_p
)
8814 size
+= (align
/ BITS_PER_UNIT
) - 1;
8815 size
-= size
% (align
/ BITS_PER_UNIT
);
8816 mips_declare_object (stream
, name
, init_string
,
8817 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8820 mips_declare_object (stream
, name
, init_string
,
8821 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
8822 size
, align
/ BITS_PER_UNIT
);
8825 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8826 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8829 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8830 unsigned HOST_WIDE_INT size
,
8833 /* If the target wants uninitialized const declarations in
8834 .rdata then don't put them in .comm. */
8835 if (TARGET_EMBEDDED_DATA
8836 && TARGET_UNINIT_CONST_IN_RODATA
8837 && TREE_CODE (decl
) == VAR_DECL
8838 && TREE_READONLY (decl
)
8839 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8841 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8842 targetm
.asm_out
.globalize_label (stream
, name
);
8844 switch_to_section (readonly_data_section
);
8845 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8846 mips_declare_object (stream
, name
, "",
8847 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8851 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8855 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8856 extern int size_directive_output
;
8858 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8859 definitions except that it uses mips_declare_object to emit the label. */
8862 mips_declare_object_name (FILE *stream
, const char *name
,
8863 tree decl ATTRIBUTE_UNUSED
)
8865 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8866 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8869 size_directive_output
= 0;
8870 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8874 size_directive_output
= 1;
8875 size
= int_size_in_bytes (TREE_TYPE (decl
));
8876 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8879 mips_declare_object (stream
, name
, "", ":\n");
8882 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8885 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8889 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8890 if (!flag_inhibit_size_directive
8891 && DECL_SIZE (decl
) != 0
8894 && DECL_INITIAL (decl
) == error_mark_node
8895 && !size_directive_output
)
8899 size_directive_output
= 1;
8900 size
= int_size_in_bytes (TREE_TYPE (decl
));
8901 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8906 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8907 with the current ABI. */
8910 mips_mdebug_abi_name (void)
8923 return TARGET_64BIT
? "eabi64" : "eabi32";
8929 /* Implement TARGET_ASM_FILE_START. */
8932 mips_file_start (void)
8934 default_file_start ();
8936 /* Generate a special section to describe the ABI switches used to
8937 produce the resultant binary. */
8939 /* Record the ABI itself. Modern versions of binutils encode
8940 this information in the ELF header flags, but GDB needs the
8941 information in order to correctly debug binaries produced by
8942 older binutils. See the function mips_gdbarch_init in
8944 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8945 mips_mdebug_abi_name ());
8947 /* There is no ELF header flag to distinguish long32 forms of the
8948 EABI from long64 forms. Emit a special section to help tools
8949 such as GDB. Do the same for o64, which is sometimes used with
8951 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
8952 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
8953 "\t.previous\n", TARGET_LONG64
? 64 : 32);
8955 /* Record the NaN encoding. */
8956 if (HAVE_AS_NAN
|| mips_nan
!= MIPS_IEEE_754_DEFAULT
)
8957 fprintf (asm_out_file
, "\t.nan\t%s\n",
8958 mips_nan
== MIPS_IEEE_754_2008
? "2008" : "legacy");
8960 #ifdef HAVE_AS_GNU_ATTRIBUTE
8964 /* No floating-point operations, -mno-float. */
8965 if (TARGET_NO_FLOAT
)
8967 /* Soft-float code, -msoft-float. */
8968 else if (!TARGET_HARD_FLOAT_ABI
)
8970 /* Single-float code, -msingle-float. */
8971 else if (!TARGET_DOUBLE_FLOAT
)
8973 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8974 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
8976 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8980 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
8984 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8985 if (TARGET_ABICALLS
)
8987 fprintf (asm_out_file
, "\t.abicalls\n");
8988 if (TARGET_ABICALLS_PIC0
)
8989 fprintf (asm_out_file
, "\t.option\tpic0\n");
8992 if (flag_verbose_asm
)
8993 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8995 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
8998 /* Implement TARGET_ASM_CODE_END. */
9001 mips_code_end (void)
9003 mips_finish_stub (&mips16_rdhwr_stub
);
9004 mips_finish_stub (&mips16_get_fcsr_stub
);
9005 mips_finish_stub (&mips16_set_fcsr_stub
);
9008 /* Make the last instruction frame-related and note that it performs
9009 the operation described by FRAME_PATTERN. */
9012 mips_set_frame_expr (rtx frame_pattern
)
9016 insn
= get_last_insn ();
9017 RTX_FRAME_RELATED_P (insn
) = 1;
9018 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
9023 /* Return a frame-related rtx that stores REG at MEM.
9024 REG must be a single register. */
9027 mips_frame_set (rtx mem
, rtx reg
)
9031 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
9032 RTX_FRAME_RELATED_P (set
) = 1;
9037 /* Record that the epilogue has restored call-saved register REG. */
9040 mips_add_cfa_restore (rtx reg
)
9042 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
9043 mips_epilogue
.cfa_restores
);
9046 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9047 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9048 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9049 static const unsigned char mips16e_s2_s8_regs
[] = {
9050 30, 23, 22, 21, 20, 19, 18
9052 static const unsigned char mips16e_a0_a3_regs
[] = {
9056 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9057 ordered from the uppermost in memory to the lowest in memory. */
9058 static const unsigned char mips16e_save_restore_regs
[] = {
9059 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9062 /* Return the index of the lowest X in the range [0, SIZE) for which
9063 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9066 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
9071 for (i
= 0; i
< size
; i
++)
9072 if (BITSET_P (mask
, regs
[i
]))
9078 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9079 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9080 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9081 is true for all indexes (X, SIZE). */
9084 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
9085 unsigned int size
, unsigned int *num_regs_ptr
)
9089 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
9090 for (i
++; i
< size
; i
++)
9091 if (!BITSET_P (*mask_ptr
, regs
[i
]))
9094 *mask_ptr
|= 1 << regs
[i
];
9098 /* Return a simplified form of X using the register values in REG_VALUES.
9099 REG_VALUES[R] is the last value assigned to hard register R, or null
9100 if R has not been modified.
9102 This function is rather limited, but is good enough for our purposes. */
9105 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
9107 x
= avoid_constant_pool_reference (x
);
9111 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9112 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
9113 x0
, GET_MODE (XEXP (x
, 0)));
9116 if (ARITHMETIC_P (x
))
9118 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9119 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
9120 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
9124 && reg_values
[REGNO (x
)]
9125 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
9126 return reg_values
[REGNO (x
)];
9131 /* Return true if (set DEST SRC) stores an argument register into its
9132 caller-allocated save slot, storing the number of that argument
9133 register in *REGNO_PTR if so. REG_VALUES is as for
9134 mips16e_collect_propagate_value. */
9137 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
9138 unsigned int *regno_ptr
)
9140 unsigned int argno
, regno
;
9141 HOST_WIDE_INT offset
, required_offset
;
9144 /* Check that this is a word-mode store. */
9145 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
9148 /* Check that the register being saved is an unmodified argument
9150 regno
= REGNO (src
);
9151 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
9153 argno
= regno
- GP_ARG_FIRST
;
9155 /* Check whether the address is an appropriate stack-pointer or
9156 frame-pointer access. */
9157 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
9158 mips_split_plus (addr
, &base
, &offset
);
9159 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
9160 if (base
== hard_frame_pointer_rtx
)
9161 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9162 else if (base
!= stack_pointer_rtx
)
9164 if (offset
!= required_offset
)
9171 /* A subroutine of mips_expand_prologue, called only when generating
9172 MIPS16e SAVE instructions. Search the start of the function for any
9173 instructions that save argument registers into their caller-allocated
9174 save slots. Delete such instructions and return a value N such that
9175 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9176 instructions redundant. */
9179 mips16e_collect_argument_saves (void)
9181 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
9182 rtx_insn
*insn
, *next
;
9184 unsigned int nargs
, regno
;
9186 push_topmost_sequence ();
9188 memset (reg_values
, 0, sizeof (reg_values
));
9189 for (insn
= get_insns (); insn
; insn
= next
)
9191 next
= NEXT_INSN (insn
);
9192 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
9198 set
= PATTERN (insn
);
9199 if (GET_CODE (set
) != SET
)
9202 dest
= SET_DEST (set
);
9203 src
= SET_SRC (set
);
9204 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
9206 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
9209 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
9212 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
9213 reg_values
[REGNO (dest
)]
9214 = mips16e_collect_propagate_value (src
, reg_values
);
9218 pop_topmost_sequence ();
9223 /* Return a move between register REGNO and memory location SP + OFFSET.
9224 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9225 Make the move a load if RESTORE_P, otherwise make it a store. */
9228 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
9229 HOST_WIDE_INT offset
, unsigned int regno
)
9233 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
9235 reg
= gen_rtx_REG (SImode
, regno
);
9238 mips_add_cfa_restore (reg
);
9239 return gen_rtx_SET (VOIDmode
, reg
, mem
);
9242 return gen_rtx_SET (VOIDmode
, mem
, reg
);
9243 return mips_frame_set (mem
, reg
);
9246 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9247 The instruction must:
9249 - Allocate or deallocate SIZE bytes in total; SIZE is known
9252 - Save or restore as many registers in *MASK_PTR as possible.
9253 The instruction saves the first registers at the top of the
9254 allocated area, with the other registers below it.
9256 - Save NARGS argument registers above the allocated area.
9258 (NARGS is always zero if RESTORE_P.)
9260 The SAVE and RESTORE instructions cannot save and restore all general
9261 registers, so there may be some registers left over for the caller to
9262 handle. Destructively modify *MASK_PTR so that it contains the registers
9263 that still need to be saved or restored. The caller can save these
9264 registers in the memory immediately below *OFFSET_PTR, which is a
9265 byte offset from the bottom of the allocated stack area. */
9268 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
9269 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
9273 HOST_WIDE_INT offset
, top_offset
;
9274 unsigned int i
, regno
;
9277 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
9279 /* Calculate the number of elements in the PARALLEL. We need one element
9280 for the stack adjustment, one for each argument register save, and one
9281 for each additional register move. */
9283 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9284 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
9287 /* Create the final PARALLEL. */
9288 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
9291 /* Add the stack pointer adjustment. */
9292 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9293 plus_constant (Pmode
, stack_pointer_rtx
,
9294 restore_p
? size
: -size
));
9295 RTX_FRAME_RELATED_P (set
) = 1;
9296 XVECEXP (pattern
, 0, n
++) = set
;
9298 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9299 top_offset
= restore_p
? size
: 0;
9301 /* Save the arguments. */
9302 for (i
= 0; i
< nargs
; i
++)
9304 offset
= top_offset
+ i
* UNITS_PER_WORD
;
9305 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
9307 XVECEXP (pattern
, 0, n
++) = set
;
9310 /* Then fill in the other register moves. */
9311 offset
= top_offset
;
9312 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9314 regno
= mips16e_save_restore_regs
[i
];
9315 if (BITSET_P (*mask_ptr
, regno
))
9317 offset
-= UNITS_PER_WORD
;
9318 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
9319 XVECEXP (pattern
, 0, n
++) = set
;
9320 *mask_ptr
&= ~(1 << regno
);
9324 /* Tell the caller what offset it should use for the remaining registers. */
9325 *offset_ptr
= size
+ (offset
- top_offset
);
9327 gcc_assert (n
== XVECLEN (pattern
, 0));
9332 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9333 pointer. Return true if PATTERN matches the kind of instruction
9334 generated by mips16e_build_save_restore. If INFO is nonnull,
9335 initialize it when returning true. */
9338 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
9339 struct mips16e_save_restore_info
*info
)
9341 unsigned int i
, nargs
, mask
, extra
;
9342 HOST_WIDE_INT top_offset
, save_offset
, offset
;
9343 rtx set
, reg
, mem
, base
;
9346 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
9349 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9350 top_offset
= adjust
> 0 ? adjust
: 0;
9352 /* Interpret all other members of the PARALLEL. */
9353 save_offset
= top_offset
- UNITS_PER_WORD
;
9357 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
9359 /* Check that we have a SET. */
9360 set
= XVECEXP (pattern
, 0, n
);
9361 if (GET_CODE (set
) != SET
)
9364 /* Check that the SET is a load (if restoring) or a store
9366 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
9370 /* Check that the address is the sum of the stack pointer and a
9371 possibly-zero constant offset. */
9372 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
9373 if (base
!= stack_pointer_rtx
)
9376 /* Check that SET's other operand is a register. */
9377 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
9381 /* Check for argument saves. */
9382 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
9383 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
9385 else if (offset
== save_offset
)
9387 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
9388 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
9391 mask
|= 1 << REGNO (reg
);
9392 save_offset
-= UNITS_PER_WORD
;
9398 /* Check that the restrictions on register ranges are met. */
9400 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
9401 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
9402 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
9403 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
9407 /* Make sure that the topmost argument register is not saved twice.
9408 The checks above ensure that the same is then true for the other
9409 argument registers. */
9410 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9413 /* Pass back information, if requested. */
9416 info
->nargs
= nargs
;
9418 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9424 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9425 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9426 the null terminator. */
9429 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9430 unsigned int max_reg
)
9432 if (min_reg
!= max_reg
)
9433 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9435 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9439 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9440 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9443 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9445 static char buffer
[300];
9447 struct mips16e_save_restore_info info
;
9448 unsigned int i
, end
;
9451 /* Parse the pattern. */
9452 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9455 /* Add the mnemonic. */
9456 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9459 /* Save the arguments. */
9461 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9462 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9463 else if (info
.nargs
== 1)
9464 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9466 /* Emit the amount of stack space to allocate or deallocate. */
9467 s
+= sprintf (s
, "%d", (int) info
.size
);
9469 /* Save or restore $16. */
9470 if (BITSET_P (info
.mask
, 16))
9471 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9473 /* Save or restore $17. */
9474 if (BITSET_P (info
.mask
, 17))
9475 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9477 /* Save or restore registers in the range $s2...$s8, which
9478 mips16e_s2_s8_regs lists in decreasing order. Note that this
9479 is a software register range; the hardware registers are not
9480 numbered consecutively. */
9481 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9482 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9484 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9485 mips16e_s2_s8_regs
[i
]);
9487 /* Save or restore registers in the range $a0...$a3. */
9488 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9489 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9491 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9492 mips16e_a0_a3_regs
[end
- 1]);
9494 /* Save or restore $31. */
9495 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9496 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9501 /* Return true if the current function returns its value in a floating-point
9502 register in MIPS16 mode. */
9505 mips16_cfun_returns_in_fpr_p (void)
9507 tree return_type
= DECL_RESULT (current_function_decl
);
9508 return (TARGET_MIPS16
9509 && TARGET_HARD_FLOAT_ABI
9510 && !aggregate_value_p (return_type
, current_function_decl
)
9511 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9514 /* Return true if predicate PRED is true for at least one instruction.
9515 Cache the result in *CACHE, and assume that the result is true
9516 if *CACHE is already true. */
9519 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx_insn
*))
9525 push_topmost_sequence ();
9526 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9527 if (USEFUL_INSN_P (insn
) && pred (insn
))
9532 pop_topmost_sequence ();
9537 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9538 See mips_cfun_has_inflexible_gp_ref_p for details. */
9541 mips_insn_has_inflexible_gp_ref_p (rtx_insn
*insn
)
9543 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9544 indicate that the target could be a traditional MIPS
9545 lazily-binding stub. */
9546 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9549 /* Return true if the current function refers to the global pointer
9550 in a way that forces $28 to be valid. This means that we can't
9551 change the choice of global pointer, even for NewABI code.
9553 One example of this (and one which needs several checks) is that
9554 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9555 (This restriction does not apply to PLTs.) */
9558 mips_cfun_has_inflexible_gp_ref_p (void)
9560 /* If the function has a nonlocal goto, $28 must hold the correct
9561 global pointer for the target function. That is, the target
9562 of the goto implicitly uses $28. */
9563 if (crtl
->has_nonlocal_goto
)
9566 if (TARGET_ABICALLS_PIC2
)
9568 /* Symbolic accesses implicitly use the global pointer unless
9569 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9570 might go to traditional MIPS lazy-binding stubs. */
9571 if (!TARGET_EXPLICIT_RELOCS
)
9574 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9575 can be lazily-bound. */
9579 /* MIPS16 functions that return in FPRs need to call an
9580 external libgcc routine. This call is only made explict
9581 during mips_expand_epilogue, and it too might be lazily bound. */
9582 if (mips16_cfun_returns_in_fpr_p ())
9586 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9587 mips_insn_has_inflexible_gp_ref_p
);
9590 /* Return true if INSN refers to the global pointer in a "flexible" way.
9591 See mips_cfun_has_flexible_gp_ref_p for details. */
9594 mips_insn_has_flexible_gp_ref_p (rtx_insn
*insn
)
9596 return (get_attr_got (insn
) != GOT_UNSET
9597 || mips_small_data_pattern_p (PATTERN (insn
))
9598 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9601 /* Return true if the current function references the global pointer,
9602 but if those references do not inherently require the global pointer
9603 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9606 mips_cfun_has_flexible_gp_ref_p (void)
9608 /* Reload can sometimes introduce constant pool references
9609 into a function that otherwise didn't need them. For example,
9610 suppose we have an instruction like:
9612 (set (reg:DF R1) (float:DF (reg:SI R2)))
9614 If R2 turns out to be a constant such as 1, the instruction may
9615 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9616 the option of using this constant if R2 doesn't get allocated
9619 In cases like these, reload will have added the constant to the
9620 pool but no instruction will yet refer to it. */
9621 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9624 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9625 mips_insn_has_flexible_gp_ref_p
);
9628 /* Return the register that should be used as the global pointer
9629 within this function. Return INVALID_REGNUM if the function
9630 doesn't need a global pointer. */
9633 mips_global_pointer (void)
9637 /* $gp is always available unless we're using a GOT. */
9638 if (!TARGET_USE_GOT
)
9639 return GLOBAL_POINTER_REGNUM
;
9641 /* If there are inflexible references to $gp, we must use the
9642 standard register. */
9643 if (mips_cfun_has_inflexible_gp_ref_p ())
9644 return GLOBAL_POINTER_REGNUM
;
9646 /* If there are no current references to $gp, then the only uses
9647 we can introduce later are those involved in long branches. */
9648 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9649 return INVALID_REGNUM
;
9651 /* If the global pointer is call-saved, try to use a call-clobbered
9653 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9654 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9655 if (!df_regs_ever_live_p (regno
)
9656 && call_really_used_regs
[regno
]
9657 && !fixed_regs
[regno
]
9658 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9661 return GLOBAL_POINTER_REGNUM
;
9664 /* Return true if the current function's prologue must load the global
9665 pointer value into pic_offset_table_rtx and store the same value in
9666 the function's cprestore slot (if any).
9668 One problem we have to deal with is that, when emitting GOT-based
9669 position independent code, long-branch sequences will need to load
9670 the address of the branch target from the GOT. We don't know until
9671 the very end of compilation whether (and where) the function needs
9672 long branches, so we must ensure that _any_ branch can access the
9673 global pointer in some form. However, we do not want to pessimize
9674 the usual case in which all branches are short.
9676 We handle this as follows:
9678 (1) During reload, we set cfun->machine->global_pointer to
9679 INVALID_REGNUM if we _know_ that the current function
9680 doesn't need a global pointer. This is only valid if
9681 long branches don't need the GOT.
9683 Otherwise, we assume that we might need a global pointer
9684 and pick an appropriate register.
9686 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9687 we ensure that the global pointer is available at every
9688 block boundary bar entry and exit. We do this in one of two ways:
9690 - If the function has a cprestore slot, we ensure that this
9691 slot is valid at every branch. However, as explained in
9692 point (6) below, there is no guarantee that pic_offset_table_rtx
9693 itself is valid if new uses of the global pointer are introduced
9694 after the first post-epilogue split.
9696 We guarantee that the cprestore slot is valid by loading it
9697 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9698 this register live at every block boundary bar function entry
9699 and exit. It is then invalid to move the load (and thus the
9700 preceding store) across a block boundary.
9702 - If the function has no cprestore slot, we guarantee that
9703 pic_offset_table_rtx itself is valid at every branch.
9705 See mips_eh_uses for the handling of the register liveness.
9707 (3) During prologue and epilogue generation, we emit "ghost"
9708 placeholder instructions to manipulate the global pointer.
9710 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9711 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9712 that the function needs a global pointer. (There is no need to set
9713 them earlier than this, and doing it as late as possible leads to
9714 fewer false positives.)
9716 (5) If cfun->machine->must_initialize_gp_p is true during a
9717 split_insns pass, we split the ghost instructions into real
9718 instructions. These split instructions can then be optimized in
9719 the usual way. Otherwise, we keep the ghost instructions intact,
9720 and optimize for the case where they aren't needed. We still
9721 have the option of splitting them later, if we need to introduce
9722 new uses of the global pointer.
9724 For example, the scheduler ignores a ghost instruction that
9725 stores $28 to the stack, but it handles the split form of
9726 the ghost instruction as an ordinary store.
9728 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9729 is true during the first post-epilogue split_insns pass, we split
9730 calls and restore_gp patterns into instructions that explicitly
9731 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9732 we split these patterns into instructions that _don't_ load from
9735 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9736 time of the split, then any instructions that exist at that time
9737 can make free use of pic_offset_table_rtx. However, if we want
9738 to introduce new uses of the global pointer after the split,
9739 we must explicitly load the value from the cprestore slot, since
9740 pic_offset_table_rtx itself might not be valid at a given point
9743 The idea is that we want to be able to delete redundant
9744 loads from the cprestore slot in the usual case where no
9745 long branches are needed.
9747 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9748 of md_reorg, we decide whether the global pointer is needed for
9749 long branches. If so, we set cfun->machine->must_initialize_gp_p
9750 to true and split the ghost instructions into real instructions
9753 Note that the ghost instructions must have a zero length for three reasons:
9755 - Giving the length of the underlying $gp sequence might cause
9756 us to use long branches in cases where they aren't really needed.
9758 - They would perturb things like alignment calculations.
9760 - More importantly, the hazard detection in md_reorg relies on
9761 empty instructions having a zero length.
9763 If we find a long branch and split the ghost instructions at the
9764 end of md_reorg, the split could introduce more long branches.
9765 That isn't a problem though, because we still do the split before
9766 the final shorten_branches pass.
9768 This is extremely ugly, but it seems like the best compromise between
9769 correctness and efficiency. */
9772 mips_must_initialize_gp_p (void)
9774 return cfun
->machine
->must_initialize_gp_p
;
9777 /* Return true if REGNO is a register that is ordinarily call-clobbered
9778 but must nevertheless be preserved by an interrupt handler. */
9781 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
9783 if (MD_REG_P (regno
))
9786 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
9789 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
9791 /* $0 is hard-wired. */
9792 if (regno
== GP_REG_FIRST
)
9795 /* The interrupt handler can treat kernel registers as
9796 scratch registers. */
9797 if (KERNEL_REG_P (regno
))
9800 /* The function will return the stack pointer to its original value
9802 if (regno
== STACK_POINTER_REGNUM
)
9805 /* Otherwise, return true for registers that aren't ordinarily
9807 return call_really_used_regs
[regno
];
9813 /* Return true if the current function should treat register REGNO
9817 mips_cfun_call_saved_reg_p (unsigned int regno
)
9819 /* If the user makes an ordinarily-call-saved register global,
9820 that register is no longer call-saved. */
9821 if (global_regs
[regno
])
9824 /* Interrupt handlers need to save extra registers. */
9825 if (cfun
->machine
->interrupt_handler_p
9826 && mips_interrupt_extra_call_saved_reg_p (regno
))
9829 /* call_insns preserve $28 unless they explicitly say otherwise,
9830 so call_really_used_regs[] treats $28 as call-saved. However,
9831 we want the ABI property rather than the default call_insn
9833 return (regno
== GLOBAL_POINTER_REGNUM
9834 ? TARGET_CALL_SAVED_GP
9835 : !call_really_used_regs
[regno
]);
9838 /* Return true if the function body might clobber register REGNO.
9839 We know that REGNO is call-saved. */
9842 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
9844 /* Some functions should be treated as clobbering all call-saved
9846 if (crtl
->saves_all_registers
)
9849 /* DF handles cases where a register is explicitly referenced in
9850 the rtl. Incoming values are passed in call-clobbered registers,
9851 so we can assume that any live call-saved register is set within
9853 if (df_regs_ever_live_p (regno
))
9856 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9857 These clobbers are not explicit in the rtl. */
9858 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9861 /* If we're using a call-saved global pointer, the function's
9862 prologue will need to set it up. */
9863 if (cfun
->machine
->global_pointer
== regno
)
9866 /* The function's prologue will need to set the frame pointer if
9867 frame_pointer_needed. */
9868 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9871 /* If a MIPS16 function returns a value in FPRs, its epilogue
9872 will need to call an external libgcc routine. This yet-to-be
9873 generated call_insn will clobber $31. */
9874 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9877 /* If REGNO is ordinarily call-clobbered, we must assume that any
9878 called function could modify it. */
9879 if (cfun
->machine
->interrupt_handler_p
9881 && mips_interrupt_extra_call_saved_reg_p (regno
))
9887 /* Return true if the current function must save register REGNO. */
9890 mips_save_reg_p (unsigned int regno
)
9892 if (mips_cfun_call_saved_reg_p (regno
))
9894 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9897 /* Save both registers in an FPR pair if either one is used. This is
9898 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9899 register to be used without the even register. */
9900 if (FP_REG_P (regno
)
9901 && MAX_FPRS_PER_FMT
== 2
9902 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9906 /* We need to save the incoming return address if __builtin_eh_return
9907 is being used to set a different return address. */
9908 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9914 /* Populate the current function's mips_frame_info structure.
9916 MIPS stack frames look like:
9918 +-------------------------------+
9920 | incoming stack arguments |
9922 +-------------------------------+
9924 | caller-allocated save area |
9925 A | for register arguments |
9927 +-------------------------------+ <-- incoming stack pointer
9929 | callee-allocated save area |
9930 B | for arguments that are |
9931 | split between registers and |
9934 +-------------------------------+ <-- arg_pointer_rtx
9936 C | callee-allocated save area |
9937 | for register varargs |
9939 +-------------------------------+ <-- frame_pointer_rtx
9940 | | + cop0_sp_offset
9941 | COP0 reg save area | + UNITS_PER_WORD
9943 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9944 | | + UNITS_PER_WORD
9945 | accumulator save area |
9947 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9948 | | + UNITS_PER_HWFPVALUE
9951 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9952 | | + UNITS_PER_WORD
9955 +-------------------------------+ <-- frame_pointer_rtx with
9956 | | \ -fstack-protector
9957 | local variables | | var_size
9959 +-------------------------------+
9961 | $gp save area | | cprestore_size
9963 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9965 | outgoing stack arguments | |
9967 +-------------------------------+ | args_size
9969 | caller-allocated save area | |
9970 | for register arguments | |
9972 +-------------------------------+ <-- stack_pointer_rtx
9973 frame_pointer_rtx without
9975 hard_frame_pointer_rtx for
9978 At least two of A, B and C will be empty.
9980 Dynamic stack allocations such as alloca insert data at point P.
9981 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9982 hard_frame_pointer_rtx unchanged. */
9985 mips_compute_frame_info (void)
9987 struct mips_frame_info
*frame
;
9988 HOST_WIDE_INT offset
, size
;
9989 unsigned int regno
, i
;
9991 /* Set this function's interrupt properties. */
9992 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
9994 if (mips_isa_rev
< 2)
9995 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
9996 else if (TARGET_HARD_FLOAT
)
9997 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9998 else if (TARGET_MIPS16
)
9999 error ("interrupt handlers cannot be MIPS16 functions");
10002 cfun
->machine
->interrupt_handler_p
= true;
10003 cfun
->machine
->use_shadow_register_set_p
=
10004 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
10005 cfun
->machine
->keep_interrupts_masked_p
=
10006 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
10007 cfun
->machine
->use_debug_exception_return_p
=
10008 mips_use_debug_exception_return_p (TREE_TYPE
10009 (current_function_decl
));
10013 frame
= &cfun
->machine
->frame
;
10014 memset (frame
, 0, sizeof (*frame
));
10015 size
= get_frame_size ();
10017 cfun
->machine
->global_pointer
= mips_global_pointer ();
10019 /* The first two blocks contain the outgoing argument area and the $gp save
10020 slot. This area isn't needed in leaf functions, but if the
10021 target-independent frame size is nonzero, we have already committed to
10022 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
10023 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
10025 /* The MIPS 3.0 linker does not like functions that dynamically
10026 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10027 looks like we are trying to create a second frame pointer to the
10028 function, so allocate some stack space to make it happy. */
10029 if (cfun
->calls_alloca
)
10030 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
10032 frame
->args_size
= 0;
10033 frame
->cprestore_size
= 0;
10037 frame
->args_size
= crtl
->outgoing_args_size
;
10038 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
10040 offset
= frame
->args_size
+ frame
->cprestore_size
;
10042 /* Move above the local variables. */
10043 frame
->var_size
= MIPS_STACK_ALIGN (size
);
10044 offset
+= frame
->var_size
;
10046 /* Find out which GPRs we need to save. */
10047 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
10048 if (mips_save_reg_p (regno
))
10051 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
10054 /* If this function calls eh_return, we must also save and restore the
10055 EH data registers. */
10056 if (crtl
->calls_eh_return
)
10057 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
10060 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
10063 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10064 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10065 save all later registers too. */
10066 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10068 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
10069 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
10070 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
10071 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
10074 /* Move above the GPR save area. */
10075 if (frame
->num_gp
> 0)
10077 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
10078 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
10081 /* Find out which FPRs we need to save. This loop must iterate over
10082 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10083 if (TARGET_HARD_FLOAT
)
10084 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
10085 if (mips_save_reg_p (regno
))
10087 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
10088 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
10091 /* Move above the FPR save area. */
10092 if (frame
->num_fp
> 0)
10094 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
10095 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
10098 /* Add in space for the interrupt context information. */
10099 if (cfun
->machine
->interrupt_handler_p
)
10102 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
10105 frame
->acc_mask
|= (1 << 0);
10108 /* Check accumulators 1, 2, 3. */
10109 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
10110 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
10113 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
10116 /* All interrupt context functions need space to preserve STATUS. */
10117 frame
->num_cop0_regs
++;
10119 /* If we don't keep interrupts masked, we need to save EPC. */
10120 if (!cfun
->machine
->keep_interrupts_masked_p
)
10121 frame
->num_cop0_regs
++;
10124 /* Move above the accumulator save area. */
10125 if (frame
->num_acc
> 0)
10127 /* Each accumulator needs 2 words. */
10128 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
10129 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
10132 /* Move above the COP0 register save area. */
10133 if (frame
->num_cop0_regs
> 0)
10135 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
10136 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
10139 /* Move above the callee-allocated varargs save area. */
10140 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
10141 frame
->arg_pointer_offset
= offset
;
10143 /* Move above the callee-allocated area for pretend stack arguments. */
10144 offset
+= crtl
->args
.pretend_args_size
;
10145 frame
->total_size
= offset
;
10147 /* Work out the offsets of the save areas from the top of the frame. */
10148 if (frame
->gp_sp_offset
> 0)
10149 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
10150 if (frame
->fp_sp_offset
> 0)
10151 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
10152 if (frame
->acc_sp_offset
> 0)
10153 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
10154 if (frame
->num_cop0_regs
> 0)
10155 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
10157 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10158 arguments. This tends to increase the chances of using unextended
10159 instructions for local variables and incoming arguments. */
10161 frame
->hard_frame_pointer_offset
= frame
->args_size
;
10164 /* Return the style of GP load sequence that is being used for the
10165 current function. */
10167 enum mips_loadgp_style
10168 mips_current_loadgp_style (void)
10170 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
10171 return LOADGP_NONE
;
10173 if (TARGET_RTP_PIC
)
10176 if (TARGET_ABSOLUTE_ABICALLS
)
10177 return LOADGP_ABSOLUTE
;
10179 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
10182 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10185 mips_frame_pointer_required (void)
10187 /* If the function contains dynamic stack allocations, we need to
10188 use the frame pointer to access the static parts of the frame. */
10189 if (cfun
->calls_alloca
)
10192 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10193 reload may be unable to compute the address of a local variable,
10194 since there is no way to add a large constant to the stack pointer
10195 without using a second temporary register. */
10198 mips_compute_frame_info ();
10199 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
10206 /* Make sure that we're not trying to eliminate to the wrong hard frame
10210 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10212 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
10215 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10216 or argument pointer. TO is either the stack pointer or hard frame
10220 mips_initial_elimination_offset (int from
, int to
)
10222 HOST_WIDE_INT offset
;
10224 mips_compute_frame_info ();
10226 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10229 case FRAME_POINTER_REGNUM
:
10230 if (FRAME_GROWS_DOWNWARD
)
10231 offset
= (cfun
->machine
->frame
.args_size
10232 + cfun
->machine
->frame
.cprestore_size
10233 + cfun
->machine
->frame
.var_size
);
10238 case ARG_POINTER_REGNUM
:
10239 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
10243 gcc_unreachable ();
10246 if (to
== HARD_FRAME_POINTER_REGNUM
)
10247 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10252 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10255 mips_extra_live_on_entry (bitmap regs
)
10257 if (TARGET_USE_GOT
)
10259 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10260 the global pointer. */
10261 if (!TARGET_ABSOLUTE_ABICALLS
)
10262 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10264 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10265 the global pointer. */
10267 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
10269 /* See the comment above load_call<mode> for details. */
10270 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
10274 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10278 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
10283 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
10286 /* Emit code to change the current function's return address to
10287 ADDRESS. SCRATCH is available as a scratch register, if needed.
10288 ADDRESS and SCRATCH are both word-mode GPRs. */
10291 mips_set_return_address (rtx address
, rtx scratch
)
10295 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
10296 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
10297 cfun
->machine
->frame
.gp_sp_offset
);
10298 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
10301 /* Return true if the current function has a cprestore slot. */
10304 mips_cfun_has_cprestore_slot_p (void)
10306 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
10307 && cfun
->machine
->frame
.cprestore_size
> 0);
10310 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10311 cprestore slot. LOAD_P is true if the caller wants to load from
10312 the cprestore slot; it is false if the caller wants to store to
10316 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
10319 const struct mips_frame_info
*frame
;
10321 frame
= &cfun
->machine
->frame
;
10322 /* .cprestore always uses the stack pointer instead of the frame pointer.
10323 We have a free choice for direct stores for non-MIPS16 functions,
10324 and for MIPS16 functions whose cprestore slot is in range of the
10325 stack pointer. Using the stack pointer would sometimes give more
10326 (early) scheduling freedom, but using the frame pointer would
10327 sometimes give more (late) scheduling freedom. It's hard to
10328 predict which applies to a given function, so let's keep things
10331 Loads must always use the frame pointer in functions that call
10332 alloca, and there's little benefit to using the stack pointer
10334 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
10336 *base
= hard_frame_pointer_rtx
;
10337 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
10341 *base
= stack_pointer_rtx
;
10342 *offset
= frame
->args_size
;
10346 /* Return true if X is the load or store address of the cprestore slot;
10347 LOAD_P says which. */
10350 mips_cprestore_address_p (rtx x
, bool load_p
)
10352 rtx given_base
, required_base
;
10353 HOST_WIDE_INT given_offset
, required_offset
;
10355 mips_split_plus (x
, &given_base
, &given_offset
);
10356 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
10357 return given_base
== required_base
&& given_offset
== required_offset
;
10360 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10361 going to load from it, false if we are going to store to it.
10362 Use TEMP as a temporary register if need be. */
10365 mips_cprestore_slot (rtx temp
, bool load_p
)
10368 HOST_WIDE_INT offset
;
10370 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
10371 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
10374 /* Emit instructions to save global pointer value GP into cprestore
10375 slot MEM. OFFSET is the offset that MEM applies to the base register.
10377 MEM may not be a legitimate address. If it isn't, TEMP is a
10378 temporary register that can be used, otherwise it is a SCRATCH. */
10381 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
10383 if (TARGET_CPRESTORE_DIRECTIVE
)
10385 gcc_assert (gp
== pic_offset_table_rtx
);
10386 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
10389 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
10392 /* Restore $gp from its save slot, using TEMP as a temporary base register
10393 if need be. This function is for o32 and o64 abicalls only.
10395 See mips_must_initialize_gp_p for details about how we manage the
10399 mips_restore_gp_from_cprestore_slot (rtx temp
)
10401 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
10403 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
10405 emit_note (NOTE_INSN_DELETED
);
10411 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10412 mips_emit_move (pic_offset_table_rtx
, temp
);
10415 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10416 if (!TARGET_EXPLICIT_RELOCS
)
10417 emit_insn (gen_blockage ());
10420 /* A function to save or store a register. The first argument is the
10421 register and the second is the stack slot. */
10422 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10424 /* Use FN to save or restore register REGNO. MODE is the register's
10425 mode and OFFSET is the offset of its save slot from the current
10429 mips_save_restore_reg (enum machine_mode mode
, int regno
,
10430 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10434 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10436 fn (gen_rtx_REG (mode
, regno
), mem
);
10439 /* Call FN for each accumlator that is saved by the current function.
10440 SP_OFFSET is the offset of the current stack pointer from the start
10444 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10446 HOST_WIDE_INT offset
;
10449 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10450 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10452 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10453 offset
-= UNITS_PER_WORD
;
10454 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10455 offset
-= UNITS_PER_WORD
;
10458 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10459 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10460 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10462 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10463 offset
-= UNITS_PER_WORD
;
10467 /* Save register REG to MEM. Make the instruction frame-related. */
10470 mips_save_reg (rtx reg
, rtx mem
)
10472 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
10476 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
10478 x1
= mips_frame_set (mips_subword (mem
, false),
10479 mips_subword (reg
, false));
10480 x2
= mips_frame_set (mips_subword (mem
, true),
10481 mips_subword (reg
, true));
10482 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10485 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10488 /* Capture the register combinations that are allowed in a SWM or LWM
10489 instruction. The entries are ordered by number of registers set in
10490 the mask. We also ignore the single register encodings because a
10491 normal SW/LW is preferred. */
10493 static const unsigned int umips_swm_mask
[17] = {
10494 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10495 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10496 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10497 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10501 static const unsigned int umips_swm_encoding
[17] = {
10502 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10505 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10506 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10507 stack pointer of the topmost save slot.
10509 Remove from *MASK all registers that were handled using LWM and SWM.
10510 Update *OFFSET so that it points to the first unused save slot. */
10513 umips_build_save_restore (mips_save_restore_fn fn
,
10514 unsigned *mask
, HOST_WIDE_INT
*offset
)
10518 rtx pattern
, set
, reg
, mem
;
10519 HOST_WIDE_INT this_offset
;
10522 /* Try matching $16 to $31 (s0 to ra). */
10523 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
10524 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
10527 if (i
== ARRAY_SIZE (umips_swm_mask
))
10530 /* Get the offset of the lowest save slot. */
10531 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
10532 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
10534 /* LWM/SWM can only support offsets from -2048 to 2047. */
10535 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
10538 /* Create the final PARALLEL. */
10539 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
10540 this_base
= stack_pointer_rtx
;
10542 /* For registers $16-$23 and $30. */
10543 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
10545 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10546 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10547 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
10548 *mask
&= ~(1 << regno
);
10549 reg
= gen_rtx_REG (SImode
, regno
);
10550 if (fn
== mips_save_reg
)
10551 set
= mips_frame_set (mem
, reg
);
10554 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10555 mips_add_cfa_restore (reg
);
10557 XVECEXP (pattern
, 0, j
) = set
;
10560 /* For register $31. */
10561 if (umips_swm_encoding
[i
] >> 4)
10563 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10564 *mask
&= ~(1 << 31);
10565 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10566 reg
= gen_rtx_REG (SImode
, 31);
10567 if (fn
== mips_save_reg
)
10568 set
= mips_frame_set (mem
, reg
);
10571 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10572 mips_add_cfa_restore (reg
);
10574 XVECEXP (pattern
, 0, j
) = set
;
10577 pattern
= emit_insn (pattern
);
10578 if (fn
== mips_save_reg
)
10579 RTX_FRAME_RELATED_P (pattern
) = 1;
10581 /* Adjust the last offset. */
10582 *offset
-= UNITS_PER_WORD
* nregs
;
10587 /* Call FN for each register that is saved by the current function.
10588 SP_OFFSET is the offset of the current stack pointer from the start
10592 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10593 mips_save_restore_fn fn
)
10595 enum machine_mode fpr_mode
;
10597 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
10598 HOST_WIDE_INT offset
;
10601 /* Save registers starting from high to low. The debuggers prefer at least
10602 the return register be stored at func+4, and also it allows us not to
10603 need a nop in the epilogue if at least one register is reloaded in
10604 addition to return address. */
10605 offset
= frame
->gp_sp_offset
- sp_offset
;
10606 mask
= frame
->mask
;
10608 if (TARGET_MICROMIPS
)
10609 umips_build_save_restore (fn
, &mask
, &offset
);
10611 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10612 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10614 /* Record the ra offset for use by mips_function_profiler. */
10615 if (regno
== RETURN_ADDR_REGNUM
)
10616 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10617 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10618 offset
-= UNITS_PER_WORD
;
10621 /* This loop must iterate over the same space as its companion in
10622 mips_compute_frame_info. */
10623 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10624 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10625 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10626 regno
>= FP_REG_FIRST
;
10627 regno
-= MAX_FPRS_PER_FMT
)
10628 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10630 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10631 offset
-= GET_MODE_SIZE (fpr_mode
);
10635 /* Return true if a move between register REGNO and its save slot (MEM)
10636 can be done in a single move. LOAD_P is true if we are loading
10637 from the slot, false if we are storing to it. */
10640 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10642 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10643 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10646 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10647 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10650 /* Emit a move from SRC to DEST, given that one of them is a register
10651 save slot and that the other is a register. TEMP is a temporary
10652 GPR of the same mode that is available if need be. */
10655 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10657 unsigned int regno
;
10662 regno
= REGNO (src
);
10667 regno
= REGNO (dest
);
10671 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
10673 /* We don't yet know whether we'll need this instruction or not.
10674 Postpone the decision by emitting a ghost move. This move
10675 is specifically not frame-related; only the split version is. */
10677 emit_insn (gen_move_gpdi (dest
, src
));
10679 emit_insn (gen_move_gpsi (dest
, src
));
10683 if (regno
== HI_REGNUM
)
10687 mips_emit_move (temp
, src
);
10689 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
10690 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
10692 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
10693 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
10698 emit_insn (gen_mfhidi_ti (temp
,
10699 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
10701 emit_insn (gen_mfhisi_di (temp
,
10702 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
10703 mips_emit_move (dest
, temp
);
10706 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
10707 mips_emit_move (dest
, src
);
10710 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
10711 mips_emit_move (temp
, src
);
10712 mips_emit_move (dest
, temp
);
10715 mips_set_frame_expr (mips_frame_set (dest
, src
));
10718 /* If we're generating n32 or n64 abicalls, and the current function
10719 does not use $28 as its global pointer, emit a cplocal directive.
10720 Use pic_offset_table_rtx as the argument to the directive. */
10723 mips_output_cplocal (void)
10725 if (!TARGET_EXPLICIT_RELOCS
10726 && mips_must_initialize_gp_p ()
10727 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
10728 output_asm_insn (".cplocal %+", 0);
10731 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10734 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10736 const char *fnname
;
10738 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10739 floating-point arguments. */
10741 && TARGET_HARD_FLOAT_ABI
10742 && crtl
->args
.info
.fp_code
!= 0)
10743 mips16_build_function_stub ();
10745 /* Get the function name the same way that toplev.c does before calling
10746 assemble_start_function. This is needed so that the name used here
10747 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10748 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10749 mips_start_function_definition (fnname
, TARGET_MIPS16
);
10751 /* Output MIPS-specific frame information. */
10752 if (!flag_inhibit_size_directive
)
10754 const struct mips_frame_info
*frame
;
10756 frame
= &cfun
->machine
->frame
;
10758 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10760 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
10761 "# vars= " HOST_WIDE_INT_PRINT_DEC
10763 ", args= " HOST_WIDE_INT_PRINT_DEC
10764 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
10765 reg_names
[frame_pointer_needed
10766 ? HARD_FRAME_POINTER_REGNUM
10767 : STACK_POINTER_REGNUM
],
10768 (frame_pointer_needed
10769 ? frame
->total_size
- frame
->hard_frame_pointer_offset
10770 : frame
->total_size
),
10771 reg_names
[RETURN_ADDR_REGNUM
],
10773 frame
->num_gp
, frame
->num_fp
,
10775 frame
->cprestore_size
);
10777 /* .mask MASK, OFFSET. */
10778 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10779 frame
->mask
, frame
->gp_save_offset
);
10781 /* .fmask MASK, OFFSET. */
10782 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10783 frame
->fmask
, frame
->fp_save_offset
);
10786 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10787 Also emit the ".set noreorder; .set nomacro" sequence for functions
10789 if (mips_must_initialize_gp_p ()
10790 && mips_current_loadgp_style () == LOADGP_OLDABI
)
10794 /* This is a fixed-form sequence. The position of the
10795 first two instructions is important because of the
10796 way _gp_disp is defined. */
10797 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10798 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10799 output_asm_insn ("sll\t$2,16", 0);
10800 output_asm_insn ("addu\t$2,$3", 0);
10804 /* .cpload must be in a .set noreorder but not a
10805 .set nomacro block. */
10806 mips_push_asm_switch (&mips_noreorder
);
10807 output_asm_insn (".cpload\t%^", 0);
10808 if (!cfun
->machine
->all_noreorder_p
)
10809 mips_pop_asm_switch (&mips_noreorder
);
10811 mips_push_asm_switch (&mips_nomacro
);
10814 else if (cfun
->machine
->all_noreorder_p
)
10816 mips_push_asm_switch (&mips_noreorder
);
10817 mips_push_asm_switch (&mips_nomacro
);
10820 /* Tell the assembler which register we're using as the global
10821 pointer. This is needed for thunks, since they can use either
10822 explicit relocs or assembler macros. */
10823 mips_output_cplocal ();
10826 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10829 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10830 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10832 const char *fnname
;
10834 /* Reinstate the normal $gp. */
10835 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
10836 mips_output_cplocal ();
10838 if (cfun
->machine
->all_noreorder_p
)
10840 mips_pop_asm_switch (&mips_nomacro
);
10841 mips_pop_asm_switch (&mips_noreorder
);
10844 /* Get the function name the same way that toplev.c does before calling
10845 assemble_start_function. This is needed so that the name used here
10846 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10847 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10848 mips_end_function_definition (fnname
);
10851 /* Emit an optimisation barrier for accesses to the current frame. */
10854 mips_frame_barrier (void)
10856 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
10860 /* The __gnu_local_gp symbol. */
10862 static GTY(()) rtx mips_gnu_local_gp
;
10864 /* If we're generating n32 or n64 abicalls, emit instructions
10865 to set up the global pointer. */
10868 mips_emit_loadgp (void)
10870 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
10872 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10873 switch (mips_current_loadgp_style ())
10875 case LOADGP_ABSOLUTE
:
10876 if (mips_gnu_local_gp
== NULL
)
10878 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
10879 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
10881 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
10882 (pic_reg
, mips_gnu_local_gp
)));
10885 case LOADGP_OLDABI
:
10886 /* Added by mips_output_function_prologue. */
10889 case LOADGP_NEWABI
:
10890 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
10891 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
10892 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
10893 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
10894 (pic_reg
, offset
, incoming_address
)));
10898 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
10899 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
10900 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
10908 emit_insn (PMODE_INSN (gen_copygp_mips16
,
10909 (pic_offset_table_rtx
, pic_reg
)));
10911 /* Emit a blockage if there are implicit uses of the GP register.
10912 This includes profiled functions, because FUNCTION_PROFILE uses
10914 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
10915 emit_insn (gen_loadgp_blockage ());
10918 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10920 #if PROBE_INTERVAL > 32768
10921 #error Cannot use indexed addressing mode for stack probing
10924 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10925 inclusive. These are offsets from the current stack pointer. */
10928 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
10931 sorry ("-fstack-check=specific not implemented for MIPS16");
10933 /* See if we have a constant small number of probes to generate. If so,
10934 that's the easy case. */
10935 if (first
+ size
<= 32768)
10939 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10940 it exceeds SIZE. If only one probe is needed, this will not
10941 generate any code. Then probe at FIRST + SIZE. */
10942 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
10943 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10946 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10950 /* Otherwise, do the same as above, but in a loop. Note that we must be
10951 extra careful with variables wrapping around because we might be at
10952 the very top (or the very bottom) of the address space and we have
10953 to be able to handle this case properly; in particular, we use an
10954 equality test for the loop condition. */
10957 HOST_WIDE_INT rounded_size
;
10958 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
10959 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
10961 /* Sanity check for the addressing mode we're going to use. */
10962 gcc_assert (first
<= 32768);
10965 /* Step 1: round SIZE to the previous multiple of the interval. */
10967 rounded_size
= size
& -PROBE_INTERVAL
;
10970 /* Step 2: compute initial and final value of the loop counter. */
10972 /* TEST_ADDR = SP + FIRST. */
10973 emit_insn (gen_rtx_SET (VOIDmode
, r3
,
10974 plus_constant (Pmode
, stack_pointer_rtx
,
10977 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10978 if (rounded_size
> 32768)
10980 emit_move_insn (r12
, GEN_INT (rounded_size
));
10981 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10982 gen_rtx_MINUS (Pmode
, r3
, r12
)));
10985 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10986 plus_constant (Pmode
, r3
, -rounded_size
)));
10989 /* Step 3: the loop
10991 while (TEST_ADDR != LAST_ADDR)
10993 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10997 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10998 until it is equal to ROUNDED_SIZE. */
11000 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
11003 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11004 that SIZE is equal to ROUNDED_SIZE. */
11006 if (size
!= rounded_size
)
11007 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
11010 /* Make sure nothing is scheduled before we are done. */
11011 emit_insn (gen_blockage ());
11014 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
11015 absolute addresses. */
11018 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
11020 static int labelno
= 0;
11021 char loop_lab
[32], end_lab
[32], tmp
[64];
11024 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
11025 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
11027 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
11029 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11032 strcpy (tmp
, "%(%<beq\t%0,%1,");
11033 output_asm_insn (strcat (tmp
, &end_lab
[1]), xops
);
11035 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11036 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
11037 if (TARGET_64BIT
&& TARGET_LONG64
)
11038 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
11040 output_asm_insn ("addiu\t%0,%0,%1", xops
);
11042 /* Probe at TEST_ADDR and branch. */
11043 fprintf (asm_out_file
, "\tb\t");
11044 assemble_name_raw (asm_out_file
, loop_lab
);
11045 fputc ('\n', asm_out_file
);
11047 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
11049 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
11051 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
11056 /* Return true if X contains a kernel register. */
11059 mips_refers_to_kernel_reg_p (const_rtx x
)
11061 subrtx_iterator::array_type array
;
11062 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
11063 if (REG_P (*iter
) && KERNEL_REG_P (REGNO (*iter
)))
11068 /* Expand the "prologue" pattern. */
11071 mips_expand_prologue (void)
11073 const struct mips_frame_info
*frame
;
11074 HOST_WIDE_INT size
;
11075 unsigned int nargs
;
11077 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
11079 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11080 or implicitly. If so, we can commit to using a global pointer
11081 straight away, otherwise we need to defer the decision. */
11082 if (mips_cfun_has_inflexible_gp_ref_p ()
11083 || mips_cfun_has_flexible_gp_ref_p ())
11085 cfun
->machine
->must_initialize_gp_p
= true;
11086 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
11089 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
11092 frame
= &cfun
->machine
->frame
;
11093 size
= frame
->total_size
;
11095 if (flag_stack_usage_info
)
11096 current_function_static_stack_size
= size
;
11098 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
11100 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
11102 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
11103 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
,
11104 size
- STACK_CHECK_PROTECT
);
11107 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
11110 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11111 bytes beforehand; this is enough to cover the register save area
11112 without going out of range. */
11113 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
11114 || frame
->num_cop0_regs
> 0)
11116 HOST_WIDE_INT step1
;
11118 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
11119 if (GENERATE_MIPS16E_SAVE_RESTORE
)
11121 HOST_WIDE_INT offset
;
11122 unsigned int mask
, regno
;
11124 /* Try to merge argument stores into the save instruction. */
11125 nargs
= mips16e_collect_argument_saves ();
11127 /* Build the save instruction. */
11128 mask
= frame
->mask
;
11129 rtx insn
= mips16e_build_save_restore (false, &mask
, &offset
,
11131 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11132 mips_frame_barrier ();
11135 /* Check if we need to save other registers. */
11136 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11137 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11139 offset
-= UNITS_PER_WORD
;
11140 mips_save_restore_reg (word_mode
, regno
,
11141 offset
, mips_save_reg
);
11146 if (cfun
->machine
->interrupt_handler_p
)
11148 HOST_WIDE_INT offset
;
11151 /* If this interrupt is using a shadow register set, we need to
11152 get the stack pointer from the previous register set. */
11153 if (cfun
->machine
->use_shadow_register_set_p
)
11154 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
11155 stack_pointer_rtx
));
11157 if (!cfun
->machine
->keep_interrupts_masked_p
)
11159 /* Move from COP0 Cause to K0. */
11160 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
11161 gen_rtx_REG (SImode
,
11162 COP0_CAUSE_REG_NUM
)));
11163 /* Move from COP0 EPC to K1. */
11164 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11165 gen_rtx_REG (SImode
,
11166 COP0_EPC_REG_NUM
)));
11169 /* Allocate the first part of the frame. */
11170 rtx insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
11172 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11173 mips_frame_barrier ();
11176 /* Start at the uppermost location for saving. */
11177 offset
= frame
->cop0_sp_offset
- size
;
11178 if (!cfun
->machine
->keep_interrupts_masked_p
)
11180 /* Push EPC into its stack slot. */
11181 mem
= gen_frame_mem (word_mode
,
11182 plus_constant (Pmode
, stack_pointer_rtx
,
11184 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11185 offset
-= UNITS_PER_WORD
;
11188 /* Move from COP0 Status to K1. */
11189 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11190 gen_rtx_REG (SImode
,
11191 COP0_STATUS_REG_NUM
)));
11193 /* Right justify the RIPL in k0. */
11194 if (!cfun
->machine
->keep_interrupts_masked_p
)
11195 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
11196 gen_rtx_REG (SImode
, K0_REG_NUM
),
11197 GEN_INT (CAUSE_IPL
)));
11199 /* Push Status into its stack slot. */
11200 mem
= gen_frame_mem (word_mode
,
11201 plus_constant (Pmode
, stack_pointer_rtx
,
11203 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11204 offset
-= UNITS_PER_WORD
;
11206 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11207 if (!cfun
->machine
->keep_interrupts_masked_p
)
11208 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11211 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11213 if (!cfun
->machine
->keep_interrupts_masked_p
)
11214 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11215 IE is already the correct value, so we don't have to do
11216 anything explicit. */
11217 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11220 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11222 /* Disable interrupts by clearing the KSU, ERL, EXL,
11224 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11227 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11231 rtx insn
= gen_add3_insn (stack_pointer_rtx
,
11234 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11235 mips_frame_barrier ();
11238 mips_for_each_saved_acc (size
, mips_save_reg
);
11239 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
11243 /* Allocate the rest of the frame. */
11246 if (SMALL_OPERAND (-size
))
11247 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
11249 GEN_INT (-size
)))) = 1;
11252 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
11255 /* There are no instructions to add or subtract registers
11256 from the stack pointer, so use the frame pointer as a
11257 temporary. We should always be using a frame pointer
11258 in this case anyway. */
11259 gcc_assert (frame_pointer_needed
);
11260 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11261 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
11262 hard_frame_pointer_rtx
,
11263 MIPS_PROLOGUE_TEMP (Pmode
)));
11264 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
11267 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
11269 MIPS_PROLOGUE_TEMP (Pmode
)));
11271 /* Describe the combined effect of the previous instructions. */
11272 mips_set_frame_expr
11273 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
11274 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
11276 mips_frame_barrier ();
11279 /* Set up the frame pointer, if we're using one. */
11280 if (frame_pointer_needed
)
11282 HOST_WIDE_INT offset
;
11284 offset
= frame
->hard_frame_pointer_offset
;
11287 rtx insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11288 RTX_FRAME_RELATED_P (insn
) = 1;
11290 else if (SMALL_OPERAND (offset
))
11292 rtx insn
= gen_add3_insn (hard_frame_pointer_rtx
,
11293 stack_pointer_rtx
, GEN_INT (offset
));
11294 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11298 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
11299 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11300 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
11301 hard_frame_pointer_rtx
,
11302 MIPS_PROLOGUE_TEMP (Pmode
)));
11303 mips_set_frame_expr
11304 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
11305 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
11309 mips_emit_loadgp ();
11311 /* Initialize the $gp save slot. */
11312 if (mips_cfun_has_cprestore_slot_p ())
11314 rtx base
, mem
, gp
, temp
;
11315 HOST_WIDE_INT offset
;
11317 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
11318 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11319 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11320 temp
= (SMALL_OPERAND (offset
)
11321 ? gen_rtx_SCRATCH (Pmode
)
11322 : MIPS_PROLOGUE_TEMP (Pmode
));
11323 emit_insn (PMODE_INSN (gen_potential_cprestore
,
11324 (mem
, GEN_INT (offset
), gp
, temp
)));
11326 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11327 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11328 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
11331 /* We need to search back to the last use of K0 or K1. */
11332 if (cfun
->machine
->interrupt_handler_p
)
11335 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
11337 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
11339 /* Emit a move from K1 to COP0 Status after insn. */
11340 gcc_assert (insn
!= NULL_RTX
);
11341 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11342 gen_rtx_REG (SImode
, K1_REG_NUM
)),
11346 /* If we are profiling, make sure no instructions are scheduled before
11347 the call to mcount. */
11349 emit_insn (gen_blockage ());
11352 /* Attach all pending register saves to the previous instruction.
11353 Return that instruction. */
11356 mips_epilogue_emit_cfa_restores (void)
11360 insn
= get_last_insn ();
11361 gcc_assert (insn
&& !REG_NOTES (insn
));
11362 if (mips_epilogue
.cfa_restores
)
11364 RTX_FRAME_RELATED_P (insn
) = 1;
11365 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
11366 mips_epilogue
.cfa_restores
= 0;
11371 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11372 now at REG + OFFSET. */
11375 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
11379 insn
= mips_epilogue_emit_cfa_restores ();
11380 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
11382 RTX_FRAME_RELATED_P (insn
) = 1;
11383 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
11384 plus_constant (Pmode
, reg
, offset
),
11386 mips_epilogue
.cfa_reg
= reg
;
11387 mips_epilogue
.cfa_offset
= offset
;
11391 /* Emit instructions to restore register REG from slot MEM. Also update
11392 the cfa_restores list. */
11395 mips_restore_reg (rtx reg
, rtx mem
)
11397 /* There's no MIPS16 instruction to load $31 directly. Load into
11398 $7 instead and adjust the return insn appropriately. */
11399 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
11400 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
11401 else if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
11403 mips_add_cfa_restore (mips_subword (reg
, true));
11404 mips_add_cfa_restore (mips_subword (reg
, false));
11407 mips_add_cfa_restore (reg
);
11409 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
11410 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
11411 /* The CFA is currently defined in terms of the register whose
11412 value we have just restored. Redefine the CFA in terms of
11413 the stack pointer. */
11414 mips_epilogue_set_cfa (stack_pointer_rtx
,
11415 mips_epilogue
.cfa_restore_sp_offset
);
11418 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11419 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11420 BASE, if not the stack pointer, is available as a temporary. */
11423 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
11425 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
11428 mips_frame_barrier ();
11429 if (offset
== const0_rtx
)
11431 emit_move_insn (stack_pointer_rtx
, base
);
11432 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11434 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
11436 emit_insn (gen_add3_insn (base
, base
, offset
));
11437 mips_epilogue_set_cfa (base
, new_frame_size
);
11438 emit_move_insn (stack_pointer_rtx
, base
);
11442 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
11443 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11447 /* Emit any instructions needed before a return. */
11450 mips_expand_before_return (void)
11452 /* When using a call-clobbered gp, we start out with unified call
11453 insns that include instructions to restore the gp. We then split
11454 these unified calls after reload. These split calls explicitly
11455 clobber gp, so there is no need to define
11456 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11458 For consistency, we should also insert an explicit clobber of $28
11459 before return insns, so that the post-reload optimizers know that
11460 the register is not live on exit. */
11461 if (TARGET_CALL_CLOBBERED_GP
)
11462 emit_clobber (pic_offset_table_rtx
);
11465 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11469 mips_expand_epilogue (bool sibcall_p
)
11471 const struct mips_frame_info
*frame
;
11472 HOST_WIDE_INT step1
, step2
;
11475 bool use_jraddiusp_p
= false;
11477 if (!sibcall_p
&& mips_can_use_return_insn ())
11479 emit_jump_insn (gen_return ());
11483 /* In MIPS16 mode, if the return value should go into a floating-point
11484 register, we need to call a helper routine to copy it over. */
11485 if (mips16_cfun_returns_in_fpr_p ())
11486 mips16_copy_fpr_return_value ();
11488 /* Split the frame into two. STEP1 is the amount of stack we should
11489 deallocate before restoring the registers. STEP2 is the amount we
11490 should deallocate afterwards.
11492 Start off by assuming that no registers need to be restored. */
11493 frame
= &cfun
->machine
->frame
;
11494 step1
= frame
->total_size
;
11497 /* Work out which register holds the frame address. */
11498 if (!frame_pointer_needed
)
11499 base
= stack_pointer_rtx
;
11502 base
= hard_frame_pointer_rtx
;
11503 step1
-= frame
->hard_frame_pointer_offset
;
11505 mips_epilogue
.cfa_reg
= base
;
11506 mips_epilogue
.cfa_offset
= step1
;
11507 mips_epilogue
.cfa_restores
= NULL_RTX
;
11509 /* If we need to restore registers, deallocate as much stack as
11510 possible in the second step without going out of range. */
11511 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
11512 || frame
->num_cop0_regs
> 0)
11514 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
11518 /* Get an rtx for STEP1 that we can add to BASE. */
11519 adjust
= GEN_INT (step1
);
11520 if (!SMALL_OPERAND (step1
))
11522 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
11523 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
11525 mips_deallocate_stack (base
, adjust
, step2
);
11527 /* If we're using addressing macros, $gp is implicitly used by all
11528 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11530 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
11531 emit_insn (gen_blockage ());
11533 mips_epilogue
.cfa_restore_sp_offset
= step2
;
11534 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
11536 unsigned int regno
, mask
;
11537 HOST_WIDE_INT offset
;
11540 /* Generate the restore instruction. */
11541 mask
= frame
->mask
;
11542 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
11544 /* Restore any other registers manually. */
11545 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11546 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11548 offset
-= UNITS_PER_WORD
;
11549 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
11552 /* Restore the remaining registers and deallocate the final bit
11554 mips_frame_barrier ();
11555 emit_insn (restore
);
11556 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
11560 /* Restore the registers. */
11561 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
11562 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
11565 if (cfun
->machine
->interrupt_handler_p
)
11567 HOST_WIDE_INT offset
;
11570 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
11571 if (!cfun
->machine
->keep_interrupts_masked_p
)
11573 /* Restore the original EPC. */
11574 mem
= gen_frame_mem (word_mode
,
11575 plus_constant (Pmode
, stack_pointer_rtx
,
11577 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11578 offset
-= UNITS_PER_WORD
;
11580 /* Move to COP0 EPC. */
11581 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
11582 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11585 /* Restore the original Status. */
11586 mem
= gen_frame_mem (word_mode
,
11587 plus_constant (Pmode
, stack_pointer_rtx
,
11589 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11590 offset
-= UNITS_PER_WORD
;
11592 /* If we don't use shadow register set, we need to update SP. */
11593 if (!cfun
->machine
->use_shadow_register_set_p
)
11594 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11596 /* The choice of position is somewhat arbitrary in this case. */
11597 mips_epilogue_emit_cfa_restores ();
11599 /* Move to COP0 Status. */
11600 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11601 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11603 else if (TARGET_MICROMIPS
11604 && !crtl
->calls_eh_return
11607 && mips_unsigned_immediate_p (step2
, 5, 2))
11608 use_jraddiusp_p
= true;
11610 /* Deallocate the final bit of the frame. */
11611 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11614 if (!use_jraddiusp_p
)
11615 gcc_assert (!mips_epilogue
.cfa_restores
);
11617 /* Add in the __builtin_eh_return stack adjustment. We need to
11618 use a temporary in MIPS16 code. */
11619 if (crtl
->calls_eh_return
)
11623 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
11624 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
11625 MIPS_EPILOGUE_TEMP (Pmode
),
11626 EH_RETURN_STACKADJ_RTX
));
11627 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
11630 emit_insn (gen_add3_insn (stack_pointer_rtx
,
11632 EH_RETURN_STACKADJ_RTX
));
11637 mips_expand_before_return ();
11638 if (cfun
->machine
->interrupt_handler_p
)
11640 /* Interrupt handlers generate eret or deret. */
11641 if (cfun
->machine
->use_debug_exception_return_p
)
11642 emit_jump_insn (gen_mips_deret ());
11644 emit_jump_insn (gen_mips_eret ());
11650 /* When generating MIPS16 code, the normal
11651 mips_for_each_saved_gpr_and_fpr path will restore the return
11652 address into $7 rather than $31. */
11654 && !GENERATE_MIPS16E_SAVE_RESTORE
11655 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
11657 /* simple_returns cannot rely on values that are only available
11658 on paths through the epilogue (because return paths that do
11659 not pass through the epilogue may nevertheless reuse a
11660 simple_return that occurs at the end of the epilogue).
11661 Use a normal return here instead. */
11662 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
11663 pat
= gen_return_internal (reg
);
11665 else if (use_jraddiusp_p
)
11666 pat
= gen_jraddiusp (GEN_INT (step2
));
11669 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
11670 pat
= gen_simple_return_internal (reg
);
11672 emit_jump_insn (pat
);
11673 if (use_jraddiusp_p
)
11674 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
11678 /* Search from the beginning to the first use of K0 or K1. */
11679 if (cfun
->machine
->interrupt_handler_p
11680 && !cfun
->machine
->keep_interrupts_masked_p
)
11682 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11684 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
11686 gcc_assert (insn
!= NULL_RTX
);
11687 /* Insert disable interrupts before the first use of K0 or K1. */
11688 emit_insn_before (gen_mips_di (), insn
);
11689 emit_insn_before (gen_mips_ehb (), insn
);
11693 /* Return nonzero if this function is known to have a null epilogue.
11694 This allows the optimizer to omit jumps to jumps if no stack
11698 mips_can_use_return_insn (void)
11700 /* Interrupt handlers need to go through the epilogue. */
11701 if (cfun
->machine
->interrupt_handler_p
)
11704 if (!reload_completed
)
11710 /* In MIPS16 mode, a function that returns a floating-point value
11711 needs to arrange to copy the return value into the floating-point
11713 if (mips16_cfun_returns_in_fpr_p ())
11716 return cfun
->machine
->frame
.total_size
== 0;
11719 /* Return true if register REGNO can store a value of mode MODE.
11720 The result of this function is cached in mips_hard_regno_mode_ok. */
11723 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
11726 enum mode_class mclass
;
11728 if (mode
== CCV2mode
)
11729 return (ISA_HAS_8CC
11730 && ST_REG_P (regno
)
11731 && (regno
- ST_REG_FIRST
) % 2 == 0);
11733 if (mode
== CCV4mode
)
11734 return (ISA_HAS_8CC
11735 && ST_REG_P (regno
)
11736 && (regno
- ST_REG_FIRST
) % 4 == 0);
11738 if (mode
== CCmode
)
11739 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
11741 size
= GET_MODE_SIZE (mode
);
11742 mclass
= GET_MODE_CLASS (mode
);
11744 if (GP_REG_P (regno
))
11745 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
11747 if (FP_REG_P (regno
)
11748 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
11749 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
11751 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11752 if (TARGET_LOONGSON_VECTORS
11753 && (mode
== V2SImode
11754 || mode
== V4HImode
11755 || mode
== V8QImode
11756 || mode
== DImode
))
11759 if (mclass
== MODE_FLOAT
11760 || mclass
== MODE_COMPLEX_FLOAT
11761 || mclass
== MODE_VECTOR_FLOAT
)
11762 return size
<= UNITS_PER_FPVALUE
;
11764 /* Allow integer modes that fit into a single register. We need
11765 to put integers into FPRs when using instructions like CVT
11766 and TRUNC. There's no point allowing sizes smaller than a word,
11767 because the FPU has no appropriate load/store instructions. */
11768 if (mclass
== MODE_INT
)
11769 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
11772 if (ACC_REG_P (regno
)
11773 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
11775 if (MD_REG_P (regno
))
11777 /* After a multiplication or division, clobbering HI makes
11778 the value of LO unpredictable, and vice versa. This means
11779 that, for all interesting cases, HI and LO are effectively
11782 We model this by requiring that any value that uses HI
11784 if (size
<= UNITS_PER_WORD
* 2)
11785 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
11789 /* DSP accumulators do not have the same restrictions as
11790 HI and LO, so we can treat them as normal doubleword
11792 if (size
<= UNITS_PER_WORD
)
11795 if (size
<= UNITS_PER_WORD
* 2
11796 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
11801 if (ALL_COP_REG_P (regno
))
11802 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
11804 if (regno
== GOT_VERSION_REGNUM
)
11805 return mode
== SImode
;
11810 /* Implement HARD_REGNO_NREGS. */
11813 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
11815 if (ST_REG_P (regno
))
11816 /* The size of FP status registers is always 4, because they only hold
11817 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11818 return (GET_MODE_SIZE (mode
) + 3) / 4;
11820 if (FP_REG_P (regno
))
11821 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
11823 /* All other registers are word-sized. */
11824 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
11827 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11828 in mips_hard_regno_nregs. */
11831 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
11837 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
11838 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
11840 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
11841 size
= MIN (size
, 4);
11842 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
11844 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
11846 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
11847 size
= MIN (size
, UNITS_PER_FPREG
);
11848 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
11850 if (!hard_reg_set_empty_p (left
))
11851 size
= MIN (size
, UNITS_PER_WORD
);
11852 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
11855 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11858 mips_cannot_change_mode_class (enum machine_mode from
,
11859 enum machine_mode to
,
11860 enum reg_class rclass
)
11862 /* Allow conversions between different Loongson integer vectors,
11863 and between those vectors and DImode. */
11864 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
11865 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
11868 /* Otherwise, there are several problems with changing the modes of
11869 values in floating-point registers:
11871 - When a multi-word value is stored in paired floating-point
11872 registers, the first register always holds the low word. We
11873 therefore can't allow FPRs to change between single-word and
11874 multi-word modes on big-endian targets.
11876 - GCC assumes that each word of a multiword register can be
11877 accessed individually using SUBREGs. This is not true for
11878 floating-point registers if they are bigger than a word.
11880 - Loading a 32-bit value into a 64-bit floating-point register
11881 will not sign-extend the value, despite what LOAD_EXTEND_OP
11882 says. We can't allow FPRs to change from SImode to a wider
11883 mode on 64-bit targets.
11885 - If the FPU has already interpreted a value in one format, we
11886 must not ask it to treat the value as having a different
11889 We therefore disallow all mode changes involving FPRs. */
11891 return reg_classes_intersect_p (FP_REGS
, rclass
);
11894 /* Implement target hook small_register_classes_for_mode_p. */
11897 mips_small_register_classes_for_mode_p (enum machine_mode mode
11900 return TARGET_MIPS16
;
11903 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11906 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
11911 return TARGET_HARD_FLOAT
;
11914 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
11917 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
11924 /* Implement MODES_TIEABLE_P. */
11927 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
11929 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11930 prefer to put one of them in FPRs. */
11931 return (mode1
== mode2
11932 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
11933 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
11936 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11939 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
11941 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
11944 if (reg_class_subset_p (FP_REGS
, rclass
)
11945 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
11948 if (reg_class_subset_p (GR_REGS
, rclass
))
11951 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
11957 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11958 Return a "canonical" class to represent it in later calculations. */
11961 mips_canonicalize_move_class (reg_class_t rclass
)
11963 /* All moves involving accumulator registers have the same cost. */
11964 if (reg_class_subset_p (rclass
, ACC_REGS
))
11967 /* Likewise promote subclasses of general registers to the most
11968 interesting containing class. */
11969 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
11971 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
11972 rclass
= GENERAL_REGS
;
11977 /* Return the cost of moving a value from a register of class FROM to a GPR.
11978 Return 0 for classes that are unions of other classes handled by this
11982 mips_move_to_gpr_cost (reg_class_t from
)
11988 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11992 /* MFLO and MFHI. */
12002 /* This choice of value is historical. */
12010 /* Return the cost of moving a value from a GPR to a register of class TO.
12011 Return 0 for classes that are unions of other classes handled by this
12015 mips_move_from_gpr_cost (reg_class_t to
)
12021 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12025 /* MTLO and MTHI. */
12035 /* This choice of value is historical. */
12043 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
12044 maximum of the move costs for subclasses; regclass will work out
12045 the maximum for us. */
12048 mips_register_move_cost (enum machine_mode mode
,
12049 reg_class_t from
, reg_class_t to
)
12054 from
= mips_canonicalize_move_class (from
);
12055 to
= mips_canonicalize_move_class (to
);
12057 /* Handle moves that can be done without using general-purpose registers. */
12058 if (from
== FP_REGS
)
12060 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
12065 /* Handle cases in which only one class deviates from the ideal. */
12066 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
12068 return mips_move_from_gpr_cost (to
);
12070 return mips_move_to_gpr_cost (from
);
12072 /* Handles cases that require a GPR temporary. */
12073 cost1
= mips_move_to_gpr_cost (from
);
12076 cost2
= mips_move_from_gpr_cost (to
);
12078 return cost1
+ cost2
;
12084 /* Implement TARGET_REGISTER_PRIORITY. */
12087 mips_register_priority (int hard_regno
)
12089 /* Treat MIPS16 registers with higher priority than other regs. */
12091 && TEST_HARD_REG_BIT (reg_class_contents
[M16_REGS
], hard_regno
))
12096 /* Implement TARGET_MEMORY_MOVE_COST. */
12099 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
12101 return (mips_cost
->memory_latency
12102 + memory_move_secondary_cost (mode
, rclass
, in
));
12105 /* Return the register class required for a secondary register when
12106 copying between one of the registers in RCLASS and value X, which
12107 has mode MODE. X is the source of the move if IN_P, otherwise it
12108 is the destination. Return NO_REGS if no secondary register is
12112 mips_secondary_reload_class (enum reg_class rclass
,
12113 enum machine_mode mode
, rtx x
, bool)
12117 /* If X is a constant that cannot be loaded into $25, it must be loaded
12118 into some other GPR. No other register class allows a direct move. */
12119 if (mips_dangerous_for_la25_p (x
))
12120 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
12122 regno
= true_regnum (x
);
12125 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12126 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
12132 /* Copying from accumulator registers to anywhere other than a general
12133 register requires a temporary general register. */
12134 if (reg_class_subset_p (rclass
, ACC_REGS
))
12135 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12136 if (ACC_REG_P (regno
))
12137 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12139 if (reg_class_subset_p (rclass
, FP_REGS
))
12143 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)))
12144 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12145 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12148 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
12149 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12152 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
12153 /* We can force the constant to memory and use lwc1
12154 and ldc1. As above, we will use pairs of lwc1s if
12155 ldc1 is not supported. */
12158 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
12159 /* In this case we can use mov.fmt. */
12162 /* Otherwise, we need to reload through an integer register. */
12165 if (FP_REG_P (regno
))
12166 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12171 /* Implement TARGET_MODE_REP_EXTENDED. */
12174 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
12176 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12177 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
12178 return SIGN_EXTEND
;
12183 /* Implement TARGET_VALID_POINTER_MODE. */
12186 mips_valid_pointer_mode (enum machine_mode mode
)
12188 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
12191 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12194 mips_vector_mode_supported_p (enum machine_mode mode
)
12199 return TARGET_PAIRED_SINGLE_FLOAT
;
12214 return TARGET_LOONGSON_VECTORS
;
12221 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12224 mips_scalar_mode_supported_p (enum machine_mode mode
)
12226 if (ALL_FIXED_POINT_MODE_P (mode
)
12227 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
12230 return default_scalar_mode_supported_p (mode
);
12233 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12235 static enum machine_mode
12236 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED
)
12238 if (TARGET_PAIRED_SINGLE_FLOAT
12244 /* Implement TARGET_INIT_LIBFUNCS. */
12247 mips_init_libfuncs (void)
12249 if (TARGET_FIX_VR4120
)
12251 /* Register the special divsi3 and modsi3 functions needed to work
12252 around VR4120 division errata. */
12253 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
12254 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
12257 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
12259 /* Register the MIPS16 -mhard-float stubs. */
12260 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
12261 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
12262 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
12263 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
12265 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
12266 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
12267 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
12268 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
12269 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
12270 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
12271 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
12273 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
12274 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
12275 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
12277 if (TARGET_DOUBLE_FLOAT
)
12279 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
12280 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
12281 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
12282 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
12284 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
12285 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
12286 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
12287 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
12288 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
12289 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
12290 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
12292 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
12293 "__mips16_extendsfdf2");
12294 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
12295 "__mips16_truncdfsf2");
12296 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
12297 "__mips16_fix_truncdfsi");
12298 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
12299 "__mips16_floatsidf");
12300 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
12301 "__mips16_floatunsidf");
12305 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12306 on an external non-MIPS16 routine to implement __sync_synchronize.
12307 Similarly for the rest of the ll/sc libfuncs. */
12310 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
12311 init_sync_libfuncs (UNITS_PER_WORD
);
12315 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12318 mips_process_load_label (rtx target
)
12320 rtx base
, gp
, intop
;
12321 HOST_WIDE_INT offset
;
12323 mips_multi_start ();
12327 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
12328 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12332 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
12333 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12337 gp
= pic_offset_table_rtx
;
12338 if (mips_cfun_has_cprestore_slot_p ())
12340 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
12341 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12342 if (!SMALL_OPERAND (offset
))
12344 intop
= GEN_INT (CONST_HIGH_PART (offset
));
12345 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
12346 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
12349 offset
= CONST_LOW_PART (offset
);
12351 intop
= GEN_INT (offset
);
12352 if (ISA_HAS_LOAD_DELAY
)
12353 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
12355 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
12357 if (ISA_HAS_LOAD_DELAY
)
12358 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
12360 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
12361 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
12366 /* Return the number of instructions needed to load a label into $AT. */
12368 static unsigned int
12369 mips_load_label_num_insns (void)
12371 if (cfun
->machine
->load_label_num_insns
== 0)
12373 mips_process_load_label (pc_rtx
);
12374 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
12376 return cfun
->machine
->load_label_num_insns
;
12379 /* Emit an asm sequence to start a noat block and load the address
12380 of a label into $1. */
12383 mips_output_load_label (rtx target
)
12385 mips_push_asm_switch (&mips_noat
);
12386 if (TARGET_EXPLICIT_RELOCS
)
12388 mips_process_load_label (target
);
12389 mips_multi_write ();
12393 if (Pmode
== DImode
)
12394 output_asm_insn ("dla\t%@,%0", &target
);
12396 output_asm_insn ("la\t%@,%0", &target
);
12400 /* Return the length of INSN. LENGTH is the initial length computed by
12401 attributes in the machine-description file. */
12404 mips_adjust_insn_length (rtx_insn
*insn
, int length
)
12406 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12407 of a PIC long-branch sequence. Substitute the correct value. */
12408 if (length
== MAX_PIC_BRANCH_LENGTH
12410 && INSN_CODE (insn
) >= 0
12411 && get_attr_type (insn
) == TYPE_BRANCH
)
12413 /* Add the branch-over instruction and its delay slot, if this
12414 is a conditional branch. */
12415 length
= simplejump_p (insn
) ? 0 : 8;
12417 /* Add the size of a load into $AT. */
12418 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
12420 /* Add the length of an indirect jump, ignoring the delay slot. */
12421 length
+= TARGET_COMPRESSION
? 2 : 4;
12424 /* A unconditional jump has an unfilled delay slot if it is not part
12425 of a sequence. A conditional jump normally has a delay slot, but
12426 does not on MIPS16. */
12427 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
12428 length
+= TARGET_MIPS16
? 2 : 4;
12430 /* See how many nops might be needed to avoid hardware hazards. */
12431 if (!cfun
->machine
->ignore_hazard_length_p
12433 && INSN_CODE (insn
) >= 0)
12434 switch (get_attr_hazard (insn
))
12440 length
+= NOP_INSN_LENGTH
;
12444 length
+= NOP_INSN_LENGTH
* 2;
12451 /* Return the assembly code for INSN, which has the operands given by
12452 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12453 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12454 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12455 version of BRANCH_IF_TRUE. */
12458 mips_output_conditional_branch (rtx_insn
*insn
, rtx
*operands
,
12459 const char *branch_if_true
,
12460 const char *branch_if_false
)
12462 unsigned int length
;
12465 gcc_assert (LABEL_P (operands
[0]));
12467 length
= get_attr_length (insn
);
12470 /* Just a simple conditional branch. */
12471 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
12472 return branch_if_true
;
12475 /* Generate a reversed branch around a direct jump. This fallback does
12476 not use branch-likely instructions. */
12477 mips_branch_likely
= false;
12478 rtx_code_label
*not_taken
= gen_label_rtx ();
12479 taken
= operands
[0];
12481 /* Generate the reversed branch to NOT_TAKEN. */
12482 operands
[0] = not_taken
;
12483 output_asm_insn (branch_if_false
, operands
);
12485 /* If INSN has a delay slot, we must provide delay slots for both the
12486 branch to NOT_TAKEN and the conditional jump. We must also ensure
12487 that INSN's delay slot is executed in the appropriate cases. */
12488 if (final_sequence
)
12490 /* This first delay slot will always be executed, so use INSN's
12491 delay slot if is not annulled. */
12492 if (!INSN_ANNULLED_BRANCH_P (insn
))
12494 final_scan_insn (final_sequence
->insn (1),
12495 asm_out_file
, optimize
, 1, NULL
);
12496 final_sequence
->insn (1)->set_deleted ();
12499 output_asm_insn ("nop", 0);
12500 fprintf (asm_out_file
, "\n");
12503 /* Output the unconditional branch to TAKEN. */
12504 if (TARGET_ABSOLUTE_JUMPS
)
12505 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
12508 mips_output_load_label (taken
);
12509 output_asm_insn ("jr\t%@%]%/", 0);
12512 /* Now deal with its delay slot; see above. */
12513 if (final_sequence
)
12515 /* This delay slot will only be executed if the branch is taken.
12516 Use INSN's delay slot if is annulled. */
12517 if (INSN_ANNULLED_BRANCH_P (insn
))
12519 final_scan_insn (final_sequence
->insn (1),
12520 asm_out_file
, optimize
, 1, NULL
);
12521 final_sequence
->insn (1)->set_deleted ();
12524 output_asm_insn ("nop", 0);
12525 fprintf (asm_out_file
, "\n");
12528 /* Output NOT_TAKEN. */
12529 targetm
.asm_out
.internal_label (asm_out_file
, "L",
12530 CODE_LABEL_NUMBER (not_taken
));
12534 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12535 if some ordering condition is true. The condition is given by
12536 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12537 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12538 its second is always zero. */
12541 mips_output_order_conditional_branch (rtx_insn
*insn
, rtx
*operands
, bool inverted_p
)
12543 const char *branch
[2];
12545 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12546 Make BRANCH[0] branch on the inverse condition. */
12547 switch (GET_CODE (operands
[1]))
12549 /* These cases are equivalent to comparisons against zero. */
12551 inverted_p
= !inverted_p
;
12552 /* Fall through. */
12554 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
12555 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
12558 /* These cases are always true or always false. */
12560 inverted_p
= !inverted_p
;
12561 /* Fall through. */
12563 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
12564 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
12568 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
12569 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
12572 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
12575 /* Start a block of code that needs access to the LL, SC and SYNC
12579 mips_start_ll_sc_sync_block (void)
12581 if (!ISA_HAS_LL_SC
)
12583 output_asm_insn (".set\tpush", 0);
12585 output_asm_insn (".set\tmips3", 0);
12587 output_asm_insn (".set\tmips2", 0);
12591 /* End a block started by mips_start_ll_sc_sync_block. */
12594 mips_end_ll_sc_sync_block (void)
12596 if (!ISA_HAS_LL_SC
)
12597 output_asm_insn (".set\tpop", 0);
12600 /* Output and/or return the asm template for a sync instruction. */
12603 mips_output_sync (void)
12605 mips_start_ll_sc_sync_block ();
12606 output_asm_insn ("sync", 0);
12607 mips_end_ll_sc_sync_block ();
12611 /* Return the asm template associated with sync_insn1 value TYPE.
12612 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12614 static const char *
12615 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
12619 case SYNC_INSN1_MOVE
:
12620 return "move\t%0,%z2";
12621 case SYNC_INSN1_LI
:
12622 return "li\t%0,%2";
12623 case SYNC_INSN1_ADDU
:
12624 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12625 case SYNC_INSN1_ADDIU
:
12626 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12627 case SYNC_INSN1_SUBU
:
12628 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12629 case SYNC_INSN1_AND
:
12630 return "and\t%0,%1,%z2";
12631 case SYNC_INSN1_ANDI
:
12632 return "andi\t%0,%1,%2";
12633 case SYNC_INSN1_OR
:
12634 return "or\t%0,%1,%z2";
12635 case SYNC_INSN1_ORI
:
12636 return "ori\t%0,%1,%2";
12637 case SYNC_INSN1_XOR
:
12638 return "xor\t%0,%1,%z2";
12639 case SYNC_INSN1_XORI
:
12640 return "xori\t%0,%1,%2";
12642 gcc_unreachable ();
12645 /* Return the asm template associated with sync_insn2 value TYPE. */
12647 static const char *
12648 mips_sync_insn2_template (enum attr_sync_insn2 type
)
12652 case SYNC_INSN2_NOP
:
12653 gcc_unreachable ();
12654 case SYNC_INSN2_AND
:
12655 return "and\t%0,%1,%z2";
12656 case SYNC_INSN2_XOR
:
12657 return "xor\t%0,%1,%z2";
12658 case SYNC_INSN2_NOT
:
12659 return "nor\t%0,%1,%.";
12661 gcc_unreachable ();
12664 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12665 the value of the one of the sync_* attributes. Return the operand
12666 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12667 have the associated attribute. */
12670 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
12673 default_value
= operands
[index
- 1];
12674 return default_value
;
12677 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12678 sequence for it. */
12681 mips_process_sync_loop (rtx_insn
*insn
, rtx
*operands
)
12683 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
12684 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
12685 unsigned int tmp3_insn
;
12686 enum attr_sync_insn1 insn1
;
12687 enum attr_sync_insn2 insn2
;
12690 enum memmodel model
;
12692 /* Read an operand from the sync_WHAT attribute and store it in
12693 variable WHAT. DEFAULT is the default value if no attribute
12695 #define READ_OPERAND(WHAT, DEFAULT) \
12696 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12699 /* Read the memory. */
12700 READ_OPERAND (mem
, 0);
12702 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
12704 /* Read the other attributes. */
12705 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
12706 READ_OPERAND (oldval
, at
);
12707 READ_OPERAND (cmp
, 0);
12708 READ_OPERAND (newval
, at
);
12709 READ_OPERAND (inclusive_mask
, 0);
12710 READ_OPERAND (exclusive_mask
, 0);
12711 READ_OPERAND (required_oldval
, 0);
12712 READ_OPERAND (insn1_op2
, 0);
12713 insn1
= get_attr_sync_insn1 (insn
);
12714 insn2
= get_attr_sync_insn2 (insn
);
12716 /* Don't bother setting CMP result that is never used. */
12717 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
12720 memmodel_attr
= get_attr_sync_memmodel (insn
);
12721 switch (memmodel_attr
)
12724 model
= MEMMODEL_ACQ_REL
;
12727 model
= MEMMODEL_ACQUIRE
;
12730 model
= (enum memmodel
) INTVAL (operands
[memmodel_attr
]);
12733 mips_multi_start ();
12735 /* Output the release side of the memory barrier. */
12736 if (need_atomic_barrier_p (model
, true))
12738 if (required_oldval
== 0 && TARGET_OCTEON
)
12740 /* Octeon doesn't reorder reads, so a full barrier can be
12741 created by using SYNCW to order writes combined with the
12742 write from the following SC. When the SC successfully
12743 completes, we know that all preceding writes are also
12744 committed to the coherent memory system. It is possible
12745 for a single SYNCW to fail, but a pair of them will never
12746 fail, so we use two. */
12747 mips_multi_add_insn ("syncw", NULL
);
12748 mips_multi_add_insn ("syncw", NULL
);
12751 mips_multi_add_insn ("sync", NULL
);
12754 /* Output the branch-back label. */
12755 mips_multi_add_label ("1:");
12757 /* OLDVAL = *MEM. */
12758 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
12759 oldval
, mem
, NULL
);
12761 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12762 if (required_oldval
)
12764 if (inclusive_mask
== 0)
12768 gcc_assert (oldval
!= at
);
12769 mips_multi_add_insn ("and\t%0,%1,%2",
12770 at
, oldval
, inclusive_mask
, NULL
);
12773 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
12775 /* CMP = 0 [delay slot]. */
12777 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
12780 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12781 if (exclusive_mask
== 0)
12785 gcc_assert (oldval
!= at
);
12786 mips_multi_add_insn ("and\t%0,%1,%z2",
12787 at
, oldval
, exclusive_mask
, NULL
);
12791 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12793 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12794 at least one instruction in that case. */
12795 if (insn1
== SYNC_INSN1_MOVE
12796 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
12800 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
12801 newval
, oldval
, insn1_op2
, NULL
);
12805 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12806 if (insn2
== SYNC_INSN2_NOP
)
12810 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
12811 newval
, tmp2
, inclusive_mask
, NULL
);
12814 tmp3_insn
= mips_multi_last_index ();
12816 /* $AT = $TMP1 | $TMP3. */
12817 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
12819 mips_multi_set_operand (tmp3_insn
, 0, at
);
12824 gcc_assert (tmp1
!= tmp3
);
12825 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
12828 /* if (!commit (*MEM = $AT)) goto 1.
12830 This will sometimes be a delayed branch; see the write code below
12832 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
12833 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
12835 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12836 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
12838 mips_multi_copy_insn (tmp3_insn
);
12839 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
12841 else if (!(required_oldval
&& cmp
))
12842 mips_multi_add_insn ("nop", NULL
);
12844 /* CMP = 1 -- either standalone or in a delay slot. */
12845 if (required_oldval
&& cmp
)
12846 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
12848 /* Output the acquire side of the memory barrier. */
12849 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
12850 mips_multi_add_insn ("sync", NULL
);
12852 /* Output the exit label, if needed. */
12853 if (required_oldval
)
12854 mips_multi_add_label ("2:");
12856 #undef READ_OPERAND
12859 /* Output and/or return the asm template for sync loop INSN, which has
12860 the operands given by OPERANDS. */
12863 mips_output_sync_loop (rtx_insn
*insn
, rtx
*operands
)
12865 mips_process_sync_loop (insn
, operands
);
12867 /* Use branch-likely instructions to work around the LL/SC R10000
12869 mips_branch_likely
= TARGET_FIX_R10000
;
12871 mips_push_asm_switch (&mips_noreorder
);
12872 mips_push_asm_switch (&mips_nomacro
);
12873 mips_push_asm_switch (&mips_noat
);
12874 mips_start_ll_sc_sync_block ();
12876 mips_multi_write ();
12878 mips_end_ll_sc_sync_block ();
12879 mips_pop_asm_switch (&mips_noat
);
12880 mips_pop_asm_switch (&mips_nomacro
);
12881 mips_pop_asm_switch (&mips_noreorder
);
12886 /* Return the number of individual instructions in sync loop INSN,
12887 which has the operands given by OPERANDS. */
12890 mips_sync_loop_insns (rtx_insn
*insn
, rtx
*operands
)
12892 mips_process_sync_loop (insn
, operands
);
12893 return mips_multi_num_insns
;
12896 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12897 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12899 When working around R4000 and R4400 errata, we need to make sure that
12900 the division is not immediately followed by a shift[1][2]. We also
12901 need to stop the division from being put into a branch delay slot[3].
12902 The easiest way to avoid both problems is to add a nop after the
12903 division. When a divide-by-zero check is needed, this nop can be
12904 used to fill the branch delay slot.
12906 [1] If a double-word or a variable shift executes immediately
12907 after starting an integer division, the shift may give an
12908 incorrect result. See quotations of errata #16 and #28 from
12909 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12910 in mips.md for details.
12912 [2] A similar bug to [1] exists for all revisions of the
12913 R4000 and the R4400 when run in an MC configuration.
12914 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12916 "19. In this following sequence:
12918 ddiv (or ddivu or div or divu)
12919 dsll32 (or dsrl32, dsra32)
12921 if an MPT stall occurs, while the divide is slipping the cpu
12922 pipeline, then the following double shift would end up with an
12925 Workaround: The compiler needs to avoid generating any
12926 sequence with divide followed by extended double shift."
12928 This erratum is also present in "MIPS R4400MC Errata, Processor
12929 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12930 & 3.0" as errata #10 and #4, respectively.
12932 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12933 (also valid for MIPS R4000MC processors):
12935 "52. R4000SC: This bug does not apply for the R4000PC.
12937 There are two flavors of this bug:
12939 1) If the instruction just after divide takes an RF exception
12940 (tlb-refill, tlb-invalid) and gets an instruction cache
12941 miss (both primary and secondary) and the line which is
12942 currently in secondary cache at this index had the first
12943 data word, where the bits 5..2 are set, then R4000 would
12944 get a wrong result for the div.
12949 ------------------- # end-of page. -tlb-refill
12954 ------------------- # end-of page. -tlb-invalid
12957 2) If the divide is in the taken branch delay slot, where the
12958 target takes RF exception and gets an I-cache miss for the
12959 exception vector or where I-cache miss occurs for the
12960 target address, under the above mentioned scenarios, the
12961 div would get wrong results.
12964 j r2 # to next page mapped or unmapped
12965 div r8,r9 # this bug would be there as long
12966 # as there is an ICache miss and
12967 nop # the "data pattern" is present
12970 beq r0, r0, NextPage # to Next page
12974 This bug is present for div, divu, ddiv, and ddivu
12977 Workaround: For item 1), OS could make sure that the next page
12978 after the divide instruction is also mapped. For item 2), the
12979 compiler could make sure that the divide instruction is not in
12980 the branch delay slot."
12982 These processors have PRId values of 0x00004220 and 0x00004300 for
12983 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12986 mips_output_division (const char *division
, rtx
*operands
)
12991 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
12993 output_asm_insn (s
, operands
);
12996 if (TARGET_CHECK_ZERO_DIV
)
13000 output_asm_insn (s
, operands
);
13001 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
13003 else if (GENERATE_DIVIDE_TRAPS
)
13005 /* Avoid long replay penalty on load miss by putting the trap before
13008 output_asm_insn ("teq\t%2,%.,7", operands
);
13011 output_asm_insn (s
, operands
);
13012 s
= "teq\t%2,%.,7";
13017 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
13018 output_asm_insn (s
, operands
);
13019 s
= "break\t7%)\n1:";
13025 /* Return true if destination of IN_INSN is used as add source in
13026 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
13027 madd.s dst, x, y, z
13028 madd.s a, dst, b, c */
13031 mips_fmadd_bypass (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
13033 int dst_reg
, src_reg
;
13035 gcc_assert (get_attr_type (in_insn
) == TYPE_FMADD
);
13036 gcc_assert (get_attr_type (out_insn
) == TYPE_FMADD
);
13038 extract_insn (in_insn
);
13039 dst_reg
= REG_P (recog_data
.operand
[0]);
13041 extract_insn (out_insn
);
13042 src_reg
= REG_P (recog_data
.operand
[1]);
13044 if (dst_reg
== src_reg
)
13050 /* Return true if IN_INSN is a multiply-add or multiply-subtract
13051 instruction and if OUT_INSN assigns to the accumulator operand. */
13054 mips_linked_madd_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
13056 enum attr_accum_in accum_in
;
13057 int accum_in_opnum
;
13060 if (recog_memoized (in_insn
) < 0)
13063 accum_in
= get_attr_accum_in (in_insn
);
13064 if (accum_in
== ACCUM_IN_NONE
)
13067 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
13069 extract_insn (in_insn
);
13070 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
13071 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
13073 return reg_set_p (accum_in_op
, out_insn
);
13076 /* True if the dependency between OUT_INSN and IN_INSN is on the store
13077 data rather than the address. We need this because the cprestore
13078 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
13079 which causes the default routine to abort. We just return false
13083 mips_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
13085 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
13088 return !store_data_bypass_p (out_insn
, in_insn
);
13092 /* Variables and flags used in scheduler hooks when tuning for
13096 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13099 /* If true, then next ALU1/2 instruction will go to ALU1. */
13102 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13105 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13106 int alu1_core_unit_code
;
13107 int alu2_core_unit_code
;
13108 int falu1_core_unit_code
;
13109 int falu2_core_unit_code
;
13111 /* True if current cycle has a multi instruction.
13112 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13113 bool cycle_has_multi_p
;
13115 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13116 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13118 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13119 instruction to go ALU1. */
13120 rtx_insn
*alu1_turn_enabled_insn
;
13121 rtx_insn
*alu2_turn_enabled_insn
;
13122 rtx_insn
*falu1_turn_enabled_insn
;
13123 rtx_insn
*falu2_turn_enabled_insn
;
13126 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13127 dependencies have no cost, except on the 20Kc where output-dependence
13128 is treated like input-dependence. */
13131 mips_adjust_cost (rtx_insn
*insn ATTRIBUTE_UNUSED
, rtx link
,
13132 rtx_insn
*dep ATTRIBUTE_UNUSED
, int cost
)
13134 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
13137 if (REG_NOTE_KIND (link
) != 0)
13142 /* Return the number of instructions that can be issued per cycle. */
13145 mips_issue_rate (void)
13149 case PROCESSOR_74KC
:
13150 case PROCESSOR_74KF2_1
:
13151 case PROCESSOR_74KF1_1
:
13152 case PROCESSOR_74KF3_2
:
13153 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13154 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13155 but in reality only a maximum of 3 insns can be issued as
13156 floating-point loads and stores also require a slot in the
13158 case PROCESSOR_R10000
:
13159 /* All R10K Processors are quad-issue (being the first MIPS
13160 processors to support this feature). */
13163 case PROCESSOR_20KC
:
13164 case PROCESSOR_R4130
:
13165 case PROCESSOR_R5400
:
13166 case PROCESSOR_R5500
:
13167 case PROCESSOR_R5900
:
13168 case PROCESSOR_R7000
:
13169 case PROCESSOR_R9000
:
13170 case PROCESSOR_OCTEON
:
13171 case PROCESSOR_OCTEON2
:
13174 case PROCESSOR_SB1
:
13175 case PROCESSOR_SB1A
:
13176 /* This is actually 4, but we get better performance if we claim 3.
13177 This is partly because of unwanted speculative code motion with the
13178 larger number, and partly because in most common cases we can't
13179 reach the theoretical max of 4. */
13182 case PROCESSOR_LOONGSON_2E
:
13183 case PROCESSOR_LOONGSON_2F
:
13184 case PROCESSOR_LOONGSON_3A
:
13185 case PROCESSOR_P5600
:
13188 case PROCESSOR_XLP
:
13189 return (reload_completed
? 4 : 3);
13196 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13199 mips_ls2_init_dfa_post_cycle_insn (void)
13202 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13203 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
13207 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13208 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
13212 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13213 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
13217 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13218 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
13221 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
13222 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
13223 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
13224 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
13227 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13228 Init data used in mips_dfa_post_advance_cycle. */
13231 mips_init_dfa_post_cycle_insn (void)
13233 if (TUNE_LOONGSON_2EF
)
13234 mips_ls2_init_dfa_post_cycle_insn ();
13237 /* Initialize STATE when scheduling for Loongson 2E/2F.
13238 Support round-robin dispatch scheme by enabling only one of
13239 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13243 mips_ls2_dfa_post_advance_cycle (state_t state
)
13245 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
13247 /* Though there are no non-pipelined ALU1 insns,
13248 we can get an instruction of type 'multi' before reload. */
13249 gcc_assert (mips_ls2
.cycle_has_multi_p
);
13250 mips_ls2
.alu1_turn_p
= false;
13253 mips_ls2
.cycle_has_multi_p
= false;
13255 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
13256 /* We have a non-pipelined alu instruction in the core,
13257 adjust round-robin counter. */
13258 mips_ls2
.alu1_turn_p
= true;
13260 if (mips_ls2
.alu1_turn_p
)
13262 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
13263 gcc_unreachable ();
13267 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
13268 gcc_unreachable ();
13271 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
13273 /* There are no non-pipelined FALU1 insns. */
13274 gcc_unreachable ();
13275 mips_ls2
.falu1_turn_p
= false;
13278 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
13279 /* We have a non-pipelined falu instruction in the core,
13280 adjust round-robin counter. */
13281 mips_ls2
.falu1_turn_p
= true;
13283 if (mips_ls2
.falu1_turn_p
)
13285 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
13286 gcc_unreachable ();
13290 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
13291 gcc_unreachable ();
13295 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13296 This hook is being called at the start of each cycle. */
13299 mips_dfa_post_advance_cycle (void)
13301 if (TUNE_LOONGSON_2EF
)
13302 mips_ls2_dfa_post_advance_cycle (curr_state
);
13305 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13306 be as wide as the scheduling freedom in the DFA. */
13309 mips_multipass_dfa_lookahead (void)
13311 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13315 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
13327 /* Remove the instruction at index LOWER from ready queue READY and
13328 reinsert it in front of the instruction at index HIGHER. LOWER must
13332 mips_promote_ready (rtx_insn
**ready
, int lower
, int higher
)
13334 rtx_insn
*new_head
;
13337 new_head
= ready
[lower
];
13338 for (i
= lower
; i
< higher
; i
++)
13339 ready
[i
] = ready
[i
+ 1];
13340 ready
[i
] = new_head
;
13343 /* If the priority of the instruction at POS2 in the ready queue READY
13344 is within LIMIT units of that of the instruction at POS1, swap the
13345 instructions if POS2 is not already less than POS1. */
13348 mips_maybe_swap_ready (rtx_insn
**ready
, int pos1
, int pos2
, int limit
)
13351 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
13355 temp
= ready
[pos1
];
13356 ready
[pos1
] = ready
[pos2
];
13357 ready
[pos2
] = temp
;
13361 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13362 that may clobber hi or lo. */
13363 static rtx_insn
*mips_macc_chains_last_hilo
;
13365 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13366 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13369 mips_macc_chains_record (rtx_insn
*insn
)
13371 if (get_attr_may_clobber_hilo (insn
))
13372 mips_macc_chains_last_hilo
= insn
;
13375 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13376 has NREADY elements, looking for a multiply-add or multiply-subtract
13377 instruction that is cumulative with mips_macc_chains_last_hilo.
13378 If there is one, promote it ahead of anything else that might
13379 clobber hi or lo. */
13382 mips_macc_chains_reorder (rtx_insn
**ready
, int nready
)
13386 if (mips_macc_chains_last_hilo
!= 0)
13387 for (i
= nready
- 1; i
>= 0; i
--)
13388 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
13390 for (j
= nready
- 1; j
> i
; j
--)
13391 if (recog_memoized (ready
[j
]) >= 0
13392 && get_attr_may_clobber_hilo (ready
[j
]))
13394 mips_promote_ready (ready
, i
, j
);
13401 /* The last instruction to be scheduled. */
13402 static rtx_insn
*vr4130_last_insn
;
13404 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13405 points to an rtx that is initially an instruction. Nullify the rtx
13406 if the instruction uses the value of register X. */
13409 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13414 insn_ptr
= (rtx
*) data
;
13417 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
13421 /* Return true if there is true register dependence between vr4130_last_insn
13425 vr4130_true_reg_dependence_p (rtx insn
)
13427 note_stores (PATTERN (vr4130_last_insn
),
13428 vr4130_true_reg_dependence_p_1
, &insn
);
13432 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13433 the ready queue and that INSN2 is the instruction after it, return
13434 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13435 in which INSN1 and INSN2 can probably issue in parallel, but for
13436 which (INSN2, INSN1) should be less sensitive to instruction
13437 alignment than (INSN1, INSN2). See 4130.md for more details. */
13440 vr4130_swap_insns_p (rtx_insn
*insn1
, rtx_insn
*insn2
)
13442 sd_iterator_def sd_it
;
13445 /* Check for the following case:
13447 1) there is some other instruction X with an anti dependence on INSN1;
13448 2) X has a higher priority than INSN2; and
13449 3) X is an arithmetic instruction (and thus has no unit restrictions).
13451 If INSN1 is the last instruction blocking X, it would better to
13452 choose (INSN1, X) over (INSN2, INSN1). */
13453 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
13454 if (DEP_TYPE (dep
) == REG_DEP_ANTI
13455 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
13456 && recog_memoized (DEP_CON (dep
)) >= 0
13457 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
13460 if (vr4130_last_insn
!= 0
13461 && recog_memoized (insn1
) >= 0
13462 && recog_memoized (insn2
) >= 0)
13464 /* See whether INSN1 and INSN2 use different execution units,
13465 or if they are both ALU-type instructions. If so, they can
13466 probably execute in parallel. */
13467 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
13468 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
13469 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
13471 /* If only one of the instructions has a dependence on
13472 vr4130_last_insn, prefer to schedule the other one first. */
13473 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
13474 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
13475 if (dep1_p
!= dep2_p
)
13478 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13479 is not an ALU-type instruction and if INSN1 uses the same
13480 execution unit. (Note that if this condition holds, we already
13481 know that INSN2 uses a different execution unit.) */
13482 if (class1
!= VR4130_CLASS_ALU
13483 && recog_memoized (vr4130_last_insn
) >= 0
13484 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
13491 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13492 queue with at least two instructions. Swap the first two if
13493 vr4130_swap_insns_p says that it could be worthwhile. */
13496 vr4130_reorder (rtx_insn
**ready
, int nready
)
13498 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
13499 mips_promote_ready (ready
, nready
- 2, nready
- 1);
13502 /* Record whether last 74k AGEN instruction was a load or store. */
13503 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13505 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13506 resets to TYPE_UNKNOWN state. */
13509 mips_74k_agen_init (rtx_insn
*insn
)
13511 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
13512 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13515 enum attr_type type
= get_attr_type (insn
);
13516 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
13517 mips_last_74k_agen_insn
= type
;
13521 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13522 loads to be grouped together, and multiple stores to be grouped
13523 together. Swap things around in the ready queue to make this happen. */
13526 mips_74k_agen_reorder (rtx_insn
**ready
, int nready
)
13529 int store_pos
, load_pos
;
13534 for (i
= nready
- 1; i
>= 0; i
--)
13536 rtx_insn
*insn
= ready
[i
];
13537 if (USEFUL_INSN_P (insn
))
13538 switch (get_attr_type (insn
))
13541 if (store_pos
== -1)
13546 if (load_pos
== -1)
13555 if (load_pos
== -1 || store_pos
== -1)
13558 switch (mips_last_74k_agen_insn
)
13561 /* Prefer to schedule loads since they have a higher latency. */
13563 /* Swap loads to the front of the queue. */
13564 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
13567 /* Swap stores to the front of the queue. */
13568 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
13575 /* Implement TARGET_SCHED_INIT. */
13578 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13579 int max_ready ATTRIBUTE_UNUSED
)
13581 mips_macc_chains_last_hilo
= 0;
13582 vr4130_last_insn
= 0;
13583 mips_74k_agen_init (NULL
);
13585 /* When scheduling for Loongson2, branch instructions go to ALU1,
13586 therefore basic block is most likely to start with round-robin counter
13587 pointed to ALU2. */
13588 mips_ls2
.alu1_turn_p
= false;
13589 mips_ls2
.falu1_turn_p
= true;
13592 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13595 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13596 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13598 if (!reload_completed
13599 && TUNE_MACC_CHAINS
13601 mips_macc_chains_reorder (ready
, *nreadyp
);
13603 if (reload_completed
13605 && !TARGET_VR4130_ALIGN
13607 vr4130_reorder (ready
, *nreadyp
);
13610 mips_74k_agen_reorder (ready
, *nreadyp
);
13613 /* Implement TARGET_SCHED_REORDER. */
13616 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13617 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13619 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13620 return mips_issue_rate ();
13623 /* Implement TARGET_SCHED_REORDER2. */
13626 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13627 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13629 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13630 return cached_can_issue_more
;
13633 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13636 mips_ls2_variable_issue (rtx_insn
*insn
)
13638 if (mips_ls2
.alu1_turn_p
)
13640 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
13641 mips_ls2
.alu1_turn_p
= false;
13645 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
13646 mips_ls2
.alu1_turn_p
= true;
13649 if (mips_ls2
.falu1_turn_p
)
13651 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
13652 mips_ls2
.falu1_turn_p
= false;
13656 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
13657 mips_ls2
.falu1_turn_p
= true;
13660 if (recog_memoized (insn
) >= 0)
13661 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
13664 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13667 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13668 rtx_insn
*insn
, int more
)
13670 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13671 if (USEFUL_INSN_P (insn
))
13673 if (get_attr_type (insn
) != TYPE_GHOST
)
13675 if (!reload_completed
&& TUNE_MACC_CHAINS
)
13676 mips_macc_chains_record (insn
);
13677 vr4130_last_insn
= insn
;
13679 mips_74k_agen_init (insn
);
13680 else if (TUNE_LOONGSON_2EF
)
13681 mips_ls2_variable_issue (insn
);
13684 /* Instructions of type 'multi' should all be split before
13685 the second scheduling pass. */
13686 gcc_assert (!reload_completed
13687 || recog_memoized (insn
) < 0
13688 || get_attr_type (insn
) != TYPE_MULTI
);
13690 cached_can_issue_more
= more
;
13694 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13695 return the first operand of the associated PREF or PREFX insn. */
13698 mips_prefetch_cookie (rtx write
, rtx locality
)
13700 /* store_streamed / load_streamed. */
13701 if (INTVAL (locality
) <= 0)
13702 return GEN_INT (INTVAL (write
) + 4);
13704 /* store / load. */
13705 if (INTVAL (locality
) <= 2)
13708 /* store_retained / load_retained. */
13709 return GEN_INT (INTVAL (write
) + 6);
13712 /* Flags that indicate when a built-in function is available.
13714 BUILTIN_AVAIL_NON_MIPS16
13715 The function is available on the current target if !TARGET_MIPS16.
13717 BUILTIN_AVAIL_MIPS16
13718 The function is available on the current target if TARGET_MIPS16. */
13719 #define BUILTIN_AVAIL_NON_MIPS16 1
13720 #define BUILTIN_AVAIL_MIPS16 2
13722 /* Declare an availability predicate for built-in functions that
13723 require non-MIPS16 mode and also require COND to be true.
13724 NAME is the main part of the predicate's name. */
13725 #define AVAIL_NON_MIPS16(NAME, COND) \
13726 static unsigned int \
13727 mips_builtin_avail_##NAME (void) \
13729 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13732 /* Declare an availability predicate for built-in functions that
13733 support both MIPS16 and non-MIPS16 code and also require COND
13734 to be true. NAME is the main part of the predicate's name. */
13735 #define AVAIL_ALL(NAME, COND) \
13736 static unsigned int \
13737 mips_builtin_avail_##NAME (void) \
13739 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
13742 /* This structure describes a single built-in function. */
13743 struct mips_builtin_description
{
13744 /* The code of the main .md file instruction. See mips_builtin_type
13745 for more information. */
13746 enum insn_code icode
;
13748 /* The floating-point comparison code to use with ICODE, if any. */
13749 enum mips_fp_condition cond
;
13751 /* The name of the built-in function. */
13754 /* Specifies how the function should be expanded. */
13755 enum mips_builtin_type builtin_type
;
13757 /* The function's prototype. */
13758 enum mips_function_type function_type
;
13760 /* Whether the function is available. */
13761 unsigned int (*avail
) (void);
13764 AVAIL_ALL (hard_float
, TARGET_HARD_FLOAT_ABI
)
13765 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
13766 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
13767 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
13768 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
13769 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
13770 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
13771 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
13772 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
13773 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
13774 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
13776 /* Construct a mips_builtin_description from the given arguments.
13778 INSN is the name of the associated instruction pattern, without the
13779 leading CODE_FOR_mips_.
13781 CODE is the floating-point condition code associated with the
13782 function. It can be 'f' if the field is not applicable.
13784 NAME is the name of the function itself, without the leading
13787 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13789 AVAIL is the name of the availability predicate, without the leading
13790 mips_builtin_avail_. */
13791 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13792 FUNCTION_TYPE, AVAIL) \
13793 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13794 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13795 mips_builtin_avail_ ## AVAIL }
13797 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13798 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13799 are as for MIPS_BUILTIN. */
13800 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13801 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13803 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13804 are subject to mips_builtin_avail_<AVAIL>. */
13805 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13806 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13807 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13808 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13809 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13811 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13812 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13813 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13814 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13815 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13816 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13818 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13819 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13821 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13822 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13824 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13825 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13828 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13829 are subject to mips_builtin_avail_mips3d. */
13830 #define CMP_4S_BUILTINS(INSN, COND) \
13831 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13832 MIPS_BUILTIN_CMP_ANY, \
13833 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13834 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13835 MIPS_BUILTIN_CMP_ALL, \
13836 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13838 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13839 instruction requires mips_builtin_avail_<AVAIL>. */
13840 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13841 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13842 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13844 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13845 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13848 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13849 #define CMP_BUILTINS(COND) \
13850 MOVTF_BUILTINS (c, COND, paired_single), \
13851 MOVTF_BUILTINS (cabs, COND, mips3d), \
13852 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13853 CMP_PS_BUILTINS (c, COND, paired_single), \
13854 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13855 CMP_4S_BUILTINS (c, COND), \
13856 CMP_4S_BUILTINS (cabs, COND)
13858 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13859 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13860 and AVAIL are as for MIPS_BUILTIN. */
13861 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13862 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13863 FUNCTION_TYPE, AVAIL)
13865 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13866 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13867 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13868 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13869 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13871 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13872 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13873 builtin_description field. */
13874 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13875 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13876 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13877 FUNCTION_TYPE, mips_builtin_avail_loongson }
13879 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13880 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13881 builtin_description field. */
13882 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13883 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13885 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13886 We use functions of this form when the same insn can be usefully applied
13887 to more than one datatype. */
13888 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13889 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13891 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13892 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13893 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13894 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13895 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13896 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13897 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13898 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13900 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13901 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13902 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13903 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13904 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13905 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13906 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13907 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13908 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13909 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13910 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13911 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13912 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13913 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13914 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13915 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13916 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13917 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13918 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13919 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13920 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13921 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13922 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13923 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13924 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13925 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13926 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13927 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13928 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13929 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13931 static const struct mips_builtin_description mips_builtins
[] = {
13932 #define MIPS_GET_FCSR 0
13933 DIRECT_BUILTIN (get_fcsr
, MIPS_USI_FTYPE_VOID
, hard_float
),
13934 #define MIPS_SET_FCSR 1
13935 DIRECT_NO_TARGET_BUILTIN (set_fcsr
, MIPS_VOID_FTYPE_USI
, hard_float
),
13937 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13938 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13939 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13940 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13941 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
13942 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13943 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13944 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
13946 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
13947 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13948 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13949 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13950 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13952 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13953 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13954 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13955 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13956 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13957 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13959 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13960 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13961 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13962 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13963 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13964 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13966 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
13968 /* Built-in functions for the SB-1 processor. */
13969 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
13971 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13972 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13973 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13974 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13975 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13976 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13977 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13978 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13979 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13980 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13981 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13982 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13983 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13984 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13985 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
13986 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
13987 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
13988 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13989 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13990 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13991 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13992 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
13993 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
13994 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13995 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13996 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13997 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13998 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13999 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14000 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14001 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14002 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
14003 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14004 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14005 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14006 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
14007 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14008 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14009 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14010 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
14011 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
14012 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14013 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
14014 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
14015 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
14016 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14017 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
14018 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
14019 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14020 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14021 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14022 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14023 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14024 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14025 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14026 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14027 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14028 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14029 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14030 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14031 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
14032 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
14033 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14034 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14035 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14036 BPOSGE_BUILTIN (32, dsp
),
14038 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
14039 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
14040 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14041 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14042 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14043 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14044 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14045 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14046 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14047 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14048 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14049 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14050 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14051 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14052 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14053 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14054 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
14055 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
14056 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
14057 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14058 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
14059 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
14060 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
14061 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14062 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14063 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14064 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14065 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14066 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14067 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14068 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14069 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14070 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14071 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14072 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14074 /* Built-in functions for the DSP ASE (32-bit only). */
14075 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14076 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14077 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14078 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14079 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14080 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14081 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14082 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14083 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14084 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14085 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14086 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14087 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14088 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14089 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14090 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14091 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14092 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14093 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14094 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14095 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14096 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14097 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14098 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14099 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14100 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
14101 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
14103 /* Built-in functions for the DSP ASE (64-bit only). */
14104 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
14106 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14107 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14108 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14109 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14110 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14111 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14112 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14113 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14114 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14115 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14117 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14118 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
14119 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
14120 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
14121 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14122 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14123 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14124 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14125 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14126 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14127 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14128 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
14129 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14130 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14131 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14132 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14133 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
14134 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14135 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14136 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14137 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
14138 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14139 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14140 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14141 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14142 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14143 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14144 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14145 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14146 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14147 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14148 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14149 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14150 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14151 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14152 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14153 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14154 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14155 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
14156 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
14157 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14158 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14159 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14160 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14161 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14162 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14163 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14164 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14165 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
14166 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14167 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14168 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14169 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14170 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
14171 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
14172 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14173 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14174 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14175 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
14176 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14177 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
14178 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
14179 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14180 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14181 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14182 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14183 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14184 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14185 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14186 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14187 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14188 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14189 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14190 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14191 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14192 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14193 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14194 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14195 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14196 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14197 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14198 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14199 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14200 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
14201 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14202 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14203 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14204 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14205 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14206 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14207 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14208 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14209 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14210 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14211 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14212 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14213 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14214 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14215 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14216 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14218 /* Sundry other built-in functions. */
14219 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
14222 /* Index I is the function declaration for mips_builtins[I], or null if the
14223 function isn't defined on this target. */
14224 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
14226 /* MODE is a vector mode whose elements have type TYPE. Return the type
14227 of the vector itself. */
14230 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
14232 static tree types
[2 * (int) MAX_MACHINE_MODE
];
14235 mode_index
= (int) mode
;
14237 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
14238 mode_index
+= MAX_MACHINE_MODE
;
14240 if (types
[mode_index
] == NULL_TREE
)
14241 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
14242 return types
[mode_index
];
14245 /* Return a type for 'const volatile void *'. */
14248 mips_build_cvpointer_type (void)
14252 if (cache
== NULL_TREE
)
14253 cache
= build_pointer_type (build_qualified_type
14255 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
14259 /* Source-level argument types. */
14260 #define MIPS_ATYPE_VOID void_type_node
14261 #define MIPS_ATYPE_INT integer_type_node
14262 #define MIPS_ATYPE_POINTER ptr_type_node
14263 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14265 /* Standard mode-based argument types. */
14266 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14267 #define MIPS_ATYPE_SI intSI_type_node
14268 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14269 #define MIPS_ATYPE_DI intDI_type_node
14270 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14271 #define MIPS_ATYPE_SF float_type_node
14272 #define MIPS_ATYPE_DF double_type_node
14274 /* Vector argument types. */
14275 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14276 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14277 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14278 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14279 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14280 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14281 #define MIPS_ATYPE_UV2SI \
14282 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14283 #define MIPS_ATYPE_UV4HI \
14284 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14285 #define MIPS_ATYPE_UV8QI \
14286 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14288 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14289 their associated MIPS_ATYPEs. */
14290 #define MIPS_FTYPE_ATYPES1(A, B) \
14291 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14293 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14294 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14296 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14297 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14299 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14300 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14303 /* Return the function type associated with function prototype TYPE. */
14306 mips_build_function_type (enum mips_function_type type
)
14308 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
14310 if (types
[(int) type
] == NULL_TREE
)
14313 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14314 case MIPS_FTYPE_NAME##NUM ARGS: \
14315 types[(int) type] \
14316 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14319 #include "config/mips/mips-ftypes.def"
14320 #undef DEF_MIPS_FTYPE
14322 gcc_unreachable ();
14325 return types
[(int) type
];
14328 /* Implement TARGET_INIT_BUILTINS. */
14331 mips_init_builtins (void)
14333 const struct mips_builtin_description
*d
;
14336 /* Iterate through all of the bdesc arrays, initializing all of the
14337 builtin functions. */
14338 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
14340 d
= &mips_builtins
[i
];
14342 mips_builtin_decls
[i
]
14343 = add_builtin_function (d
->name
,
14344 mips_build_function_type (d
->function_type
),
14345 i
, BUILT_IN_MD
, NULL
, NULL
);
14349 /* Implement TARGET_BUILTIN_DECL. */
14352 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
14354 if (code
>= ARRAY_SIZE (mips_builtins
))
14355 return error_mark_node
;
14356 return mips_builtin_decls
[code
];
14359 /* Take argument ARGNO from EXP's argument list and convert it into
14360 an expand operand. Store the operand in *OP. */
14363 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
14364 unsigned int argno
)
14369 arg
= CALL_EXPR_ARG (exp
, argno
);
14370 value
= expand_normal (arg
);
14371 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
14374 /* Expand instruction ICODE as part of a built-in function sequence.
14375 Use the first NOPS elements of OPS as the instruction's operands.
14376 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14377 instruction has no target.
14379 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14382 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
14383 struct expand_operand
*ops
, bool has_target_p
)
14385 if (!maybe_expand_insn (icode
, nops
, ops
))
14387 error ("invalid argument to built-in function");
14388 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
14390 return has_target_p
? ops
[0].value
: const0_rtx
;
14393 /* Expand a floating-point comparison for built-in function call EXP.
14394 The first NARGS arguments are the values to be compared. ICODE is
14395 the .md pattern that does the comparison and COND is the condition
14396 that is being tested. Return an rtx for the result. */
14399 mips_expand_builtin_compare_1 (enum insn_code icode
,
14400 enum mips_fp_condition cond
,
14401 tree exp
, int nargs
)
14403 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14407 /* The instruction should have a target operand, an operand for each
14408 argument, and an operand for COND. */
14409 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
14411 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
14413 create_fixed_operand (&ops
[opno
++], output
);
14414 for (argno
= 0; argno
< nargs
; argno
++)
14415 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14416 create_integer_operand (&ops
[opno
++], (int) cond
);
14417 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
14420 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14421 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14422 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14423 suggests a good place to put the result. */
14426 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
14429 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14432 /* Map any target to operand 0. */
14435 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
14437 /* Map the arguments to the other operands. */
14438 gcc_assert (opno
+ call_expr_nargs (exp
)
14439 == insn_data
[icode
].n_generator_args
);
14440 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
14441 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14443 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
14446 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14447 function; TYPE says which. EXP is the CALL_EXPR that calls the
14448 function, ICODE is the instruction that should be used to compare
14449 the first two arguments, and COND is the condition it should test.
14450 TARGET, if nonnull, suggests a good place to put the result. */
14453 mips_expand_builtin_movtf (enum mips_builtin_type type
,
14454 enum insn_code icode
, enum mips_fp_condition cond
,
14455 rtx target
, tree exp
)
14457 struct expand_operand ops
[4];
14460 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
14461 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
14462 if (type
== MIPS_BUILTIN_MOVT
)
14464 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
14465 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
14469 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
14470 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
14472 create_fixed_operand (&ops
[3], cmp_result
);
14473 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
14477 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14478 into TARGET otherwise. Return TARGET. */
14481 mips_builtin_branch_and_move (rtx condition
, rtx target
,
14482 rtx value_if_true
, rtx value_if_false
)
14484 rtx_code_label
*true_label
, *done_label
;
14486 true_label
= gen_label_rtx ();
14487 done_label
= gen_label_rtx ();
14489 /* First assume that CONDITION is false. */
14490 mips_emit_move (target
, value_if_false
);
14492 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14493 emit_jump_insn (gen_condjump (condition
, true_label
));
14494 emit_jump_insn (gen_jump (done_label
));
14497 /* Fix TARGET if CONDITION is true. */
14498 emit_label (true_label
);
14499 mips_emit_move (target
, value_if_true
);
14501 emit_label (done_label
);
14505 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14506 the CALL_EXPR that calls the function, ICODE is the code of the
14507 comparison instruction, and COND is the condition it should test.
14508 TARGET, if nonnull, suggests a good place to put the boolean result. */
14511 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
14512 enum insn_code icode
, enum mips_fp_condition cond
,
14513 rtx target
, tree exp
)
14515 rtx offset
, condition
, cmp_result
;
14517 if (target
== 0 || GET_MODE (target
) != SImode
)
14518 target
= gen_reg_rtx (SImode
);
14519 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
14520 call_expr_nargs (exp
));
14522 /* If the comparison sets more than one register, we define the result
14523 to be 0 if all registers are false and -1 if all registers are true.
14524 The value of the complete result is indeterminate otherwise. */
14525 switch (builtin_type
)
14527 case MIPS_BUILTIN_CMP_ALL
:
14528 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
14529 return mips_builtin_branch_and_move (condition
, target
,
14530 const0_rtx
, const1_rtx
);
14532 case MIPS_BUILTIN_CMP_UPPER
:
14533 case MIPS_BUILTIN_CMP_LOWER
:
14534 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
14535 condition
= gen_single_cc (cmp_result
, offset
);
14536 return mips_builtin_branch_and_move (condition
, target
,
14537 const1_rtx
, const0_rtx
);
14540 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
14541 return mips_builtin_branch_and_move (condition
, target
,
14542 const1_rtx
, const0_rtx
);
14546 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14547 if nonnull, suggests a good place to put the boolean result. */
14550 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
14552 rtx condition
, cmp_result
;
14555 if (target
== 0 || GET_MODE (target
) != SImode
)
14556 target
= gen_reg_rtx (SImode
);
14558 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
14560 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
14565 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
14566 return mips_builtin_branch_and_move (condition
, target
,
14567 const1_rtx
, const0_rtx
);
14570 /* Implement TARGET_EXPAND_BUILTIN. */
14573 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14574 enum machine_mode mode
, int ignore
)
14577 unsigned int fcode
, avail
;
14578 const struct mips_builtin_description
*d
;
14580 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14581 fcode
= DECL_FUNCTION_CODE (fndecl
);
14582 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
14583 d
= &mips_builtins
[fcode
];
14584 avail
= d
->avail ();
14585 gcc_assert (avail
!= 0);
14586 if (TARGET_MIPS16
&& !(avail
& BUILTIN_AVAIL_MIPS16
))
14588 error ("built-in function %qE not supported for MIPS16",
14589 DECL_NAME (fndecl
));
14590 return ignore
? const0_rtx
: CONST0_RTX (mode
);
14592 switch (d
->builtin_type
)
14594 case MIPS_BUILTIN_DIRECT
:
14595 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
14597 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
14598 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
14600 case MIPS_BUILTIN_MOVT
:
14601 case MIPS_BUILTIN_MOVF
:
14602 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
14603 d
->cond
, target
, exp
);
14605 case MIPS_BUILTIN_CMP_ANY
:
14606 case MIPS_BUILTIN_CMP_ALL
:
14607 case MIPS_BUILTIN_CMP_UPPER
:
14608 case MIPS_BUILTIN_CMP_LOWER
:
14609 case MIPS_BUILTIN_CMP_SINGLE
:
14610 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
14611 d
->cond
, target
, exp
);
14613 case MIPS_BUILTIN_BPOSGE32
:
14614 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
14616 gcc_unreachable ();
14619 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14620 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14621 struct mips16_constant
{
14622 struct mips16_constant
*next
;
14624 rtx_code_label
*label
;
14625 enum machine_mode mode
;
14628 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14629 first constant, HIGHEST_ADDRESS is the highest address that the first
14630 byte of the pool can have, and INSN_ADDRESS is the current instruction
14632 struct mips16_constant_pool
{
14633 struct mips16_constant
*first
;
14634 int highest_address
;
14638 /* Add constant VALUE to POOL and return its label. MODE is the
14639 value's mode (used for CONST_INTs, etc.). */
14641 static rtx_code_label
*
14642 mips16_add_constant (struct mips16_constant_pool
*pool
,
14643 rtx value
, enum machine_mode mode
)
14645 struct mips16_constant
**p
, *c
;
14646 bool first_of_size_p
;
14648 /* See whether the constant is already in the pool. If so, return the
14649 existing label, otherwise leave P pointing to the place where the
14650 constant should be added.
14652 Keep the pool sorted in increasing order of mode size so that we can
14653 reduce the number of alignments needed. */
14654 first_of_size_p
= true;
14655 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
14657 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
14658 return (*p
)->label
;
14659 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
14661 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
14662 first_of_size_p
= false;
14665 /* In the worst case, the constant needed by the earliest instruction
14666 will end up at the end of the pool. The entire pool must then be
14667 accessible from that instruction.
14669 When adding the first constant, set the pool's highest address to
14670 the address of the first out-of-range byte. Adjust this address
14671 downwards each time a new constant is added. */
14672 if (pool
->first
== 0)
14673 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14674 of the instruction with the lowest two bits clear. The base PC
14675 value for LDPC has the lowest three bits clear. Assume the worst
14676 case here; namely that the PC-relative instruction occupies the
14677 last 2 bytes in an aligned word. */
14678 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
14679 pool
->highest_address
-= GET_MODE_SIZE (mode
);
14680 if (first_of_size_p
)
14681 /* Take into account the worst possible padding due to alignment. */
14682 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
14684 /* Create a new entry. */
14685 c
= XNEW (struct mips16_constant
);
14688 c
->label
= gen_label_rtx ();
14695 /* Output constant VALUE after instruction INSN and return the last
14696 instruction emitted. MODE is the mode of the constant. */
14699 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx_insn
*insn
)
14701 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
14703 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
14704 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
14707 if (SCALAR_FLOAT_MODE_P (mode
))
14708 return emit_insn_after (gen_consttable_float (value
), insn
);
14710 if (VECTOR_MODE_P (mode
))
14714 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
14715 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
14716 CONST_VECTOR_ELT (value
, i
), insn
);
14720 gcc_unreachable ();
14723 /* Dump out the constants in CONSTANTS after INSN. */
14726 mips16_emit_constants (struct mips16_constant
*constants
, rtx_insn
*insn
)
14728 struct mips16_constant
*c
, *next
;
14732 for (c
= constants
; c
!= NULL
; c
= next
)
14734 /* If necessary, increase the alignment of PC. */
14735 if (align
< GET_MODE_SIZE (c
->mode
))
14737 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
14738 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
14740 align
= GET_MODE_SIZE (c
->mode
);
14742 insn
= emit_label_after (c
->label
, insn
);
14743 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
14749 emit_barrier_after (insn
);
14752 /* Return the length of instruction INSN. */
14755 mips16_insn_length (rtx_insn
*insn
)
14757 if (JUMP_TABLE_DATA_P (insn
))
14759 rtx body
= PATTERN (insn
);
14760 if (GET_CODE (body
) == ADDR_VEC
)
14761 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
14762 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
14763 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
14765 gcc_unreachable ();
14767 return get_attr_length (insn
);
14770 /* If *X is a symbolic constant that refers to the constant pool, add
14771 the constant to POOL and rewrite *X to use the constant's label. */
14774 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
14777 rtx_code_label
*label
;
14779 split_const (*x
, &base
, &offset
);
14780 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
14782 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
14783 get_pool_mode (base
));
14784 base
= gen_rtx_LABEL_REF (Pmode
, label
);
14785 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
14789 /* Rewrite INSN so that constant pool references refer to the constant's
14793 mips16_rewrite_pool_refs (rtx_insn
*insn
, struct mips16_constant_pool
*pool
)
14795 subrtx_ptr_iterator::array_type array
;
14796 FOR_EACH_SUBRTX_PTR (iter
, array
, &PATTERN (insn
), ALL
)
14800 if (force_to_mem_operand (*loc
, Pmode
))
14802 rtx mem
= force_const_mem (GET_MODE (*loc
), *loc
);
14803 validate_change (insn
, loc
, mem
, false);
14808 mips16_rewrite_pool_constant (pool
, &XEXP (*loc
, 0));
14809 iter
.skip_subrtxes ();
14813 if (TARGET_MIPS16_TEXT_LOADS
)
14814 mips16_rewrite_pool_constant (pool
, loc
);
14815 if (GET_CODE (*loc
) == CONST
14816 /* Don't rewrite the __mips16_rdwr symbol. */
14817 || (GET_CODE (*loc
) == UNSPEC
14818 && XINT (*loc
, 1) == UNSPEC_TLS_GET_TP
))
14819 iter
.skip_subrtxes ();
14824 /* Return whether CFG is used in mips_reorg. */
14827 mips_cfg_in_reorg (void)
14829 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
14830 || TARGET_RELAX_PIC_CALLS
);
14833 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14834 otherwise assume that they are already split. */
14837 mips16_lay_out_constants (bool split_p
)
14839 struct mips16_constant_pool pool
;
14840 rtx_insn
*insn
, *barrier
;
14842 if (!TARGET_MIPS16_PCREL_LOADS
)
14847 if (mips_cfg_in_reorg ())
14848 split_all_insns ();
14850 split_all_insns_noflow ();
14853 memset (&pool
, 0, sizeof (pool
));
14854 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14856 /* Rewrite constant pool references in INSN. */
14857 if (USEFUL_INSN_P (insn
))
14858 mips16_rewrite_pool_refs (insn
, &pool
);
14860 pool
.insn_address
+= mips16_insn_length (insn
);
14862 if (pool
.first
!= NULL
)
14864 /* If there are no natural barriers between the first user of
14865 the pool and the highest acceptable address, we'll need to
14866 create a new instruction to jump around the constant pool.
14867 In the worst case, this instruction will be 4 bytes long.
14869 If it's too late to do this transformation after INSN,
14870 do it immediately before INSN. */
14871 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
14873 rtx_code_label
*label
;
14876 label
= gen_label_rtx ();
14878 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
14879 JUMP_LABEL (jump
) = label
;
14880 LABEL_NUSES (label
) = 1;
14881 barrier
= emit_barrier_after (jump
);
14883 emit_label_after (label
, barrier
);
14884 pool
.insn_address
+= 4;
14887 /* See whether the constant pool is now out of range of the first
14888 user. If so, output the constants after the previous barrier.
14889 Note that any instructions between BARRIER and INSN (inclusive)
14890 will use negative offsets to refer to the pool. */
14891 if (pool
.insn_address
> pool
.highest_address
)
14893 mips16_emit_constants (pool
.first
, barrier
);
14897 else if (BARRIER_P (insn
))
14901 mips16_emit_constants (pool
.first
, get_last_insn ());
14904 /* Return true if it is worth r10k_simplify_address's while replacing
14905 an address with X. We are looking for constants, and for addresses
14906 at a known offset from the incoming stack pointer. */
14909 r10k_simplified_address_p (rtx x
)
14911 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
14913 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
14916 /* X is an expression that appears in INSN. Try to use the UD chains
14917 to simplify it, returning the simplified form on success and the
14918 original form otherwise. Replace the incoming value of $sp with
14919 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14922 r10k_simplify_address (rtx x
, rtx_insn
*insn
)
14924 rtx newx
, op0
, op1
, set
, note
;
14925 rtx_insn
*def_insn
;
14927 struct df_link
*defs
;
14932 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14933 if (op0
!= XEXP (x
, 0))
14934 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
14935 op0
, GET_MODE (XEXP (x
, 0)));
14937 else if (BINARY_P (x
))
14939 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14940 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
14941 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
14942 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
14944 else if (GET_CODE (x
) == LO_SUM
)
14946 /* LO_SUMs can be offset from HIGHs, if we know they won't
14947 overflow. See mips_classify_address for the rationale behind
14949 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14950 if (GET_CODE (op0
) == HIGH
)
14951 newx
= XEXP (x
, 1);
14953 else if (REG_P (x
))
14955 /* Uses are recorded by regno_reg_rtx, not X itself. */
14956 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
14958 defs
= DF_REF_CHAIN (use
);
14960 /* Require a single definition. */
14961 if (defs
&& defs
->next
== NULL
)
14964 if (DF_REF_IS_ARTIFICIAL (def
))
14966 /* Replace the incoming value of $sp with
14967 virtual_incoming_args_rtx. */
14968 if (x
== stack_pointer_rtx
14969 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR_FOR_FN (cfun
))
14970 newx
= virtual_incoming_args_rtx
;
14972 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
14975 /* Make sure that DEF_INSN is a single set of REG. */
14976 def_insn
= DF_REF_INSN (def
);
14977 if (NONJUMP_INSN_P (def_insn
))
14979 set
= single_set (def_insn
);
14980 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
14982 /* Prefer to use notes, since the def-use chains
14983 are often shorter. */
14984 note
= find_reg_equal_equiv_note (def_insn
);
14986 newx
= XEXP (note
, 0);
14988 newx
= SET_SRC (set
);
14989 newx
= r10k_simplify_address (newx
, def_insn
);
14995 if (newx
&& r10k_simplified_address_p (newx
))
15000 /* Return true if ADDRESS is known to be an uncached address
15001 on R10K systems. */
15004 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
15006 unsigned HOST_WIDE_INT upper
;
15008 /* Check for KSEG1. */
15009 if (address
+ 0x60000000 < 0x20000000)
15012 /* Check for uncached XKPHYS addresses. */
15013 if (Pmode
== DImode
)
15015 upper
= (address
>> 40) & 0xf9ffff;
15016 if (upper
== 0x900000 || upper
== 0xb80000)
15022 /* Return true if we can prove that an access to address X in instruction
15023 INSN would be safe from R10K speculation. This X is a general
15024 expression; it might not be a legitimate address. */
15027 r10k_safe_address_p (rtx x
, rtx_insn
*insn
)
15030 HOST_WIDE_INT offset_val
;
15032 x
= r10k_simplify_address (x
, insn
);
15034 /* Check for references to the stack frame. It doesn't really matter
15035 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
15036 allows us to assume that accesses to any part of the eventual frame
15037 is safe from speculation at any point in the function. */
15038 mips_split_plus (x
, &base
, &offset_val
);
15039 if (base
== virtual_incoming_args_rtx
15040 && offset_val
>= -cfun
->machine
->frame
.total_size
15041 && offset_val
< cfun
->machine
->frame
.args_size
)
15044 /* Check for uncached addresses. */
15045 if (CONST_INT_P (x
))
15046 return r10k_uncached_address_p (INTVAL (x
));
15048 /* Check for accesses to a static object. */
15049 split_const (x
, &base
, &offset
);
15050 return offset_within_block_p (base
, INTVAL (offset
));
15053 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
15054 an in-range access to an automatic variable, or to an object with
15055 a link-time-constant address. */
15058 r10k_safe_mem_expr_p (tree expr
, unsigned HOST_WIDE_INT offset
)
15060 HOST_WIDE_INT bitoffset
, bitsize
;
15061 tree inner
, var_offset
;
15062 enum machine_mode mode
;
15063 int unsigned_p
, volatile_p
;
15065 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
15066 &unsigned_p
, &volatile_p
, false);
15067 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
15070 offset
+= bitoffset
/ BITS_PER_UNIT
;
15071 return offset
< tree_to_uhwi (DECL_SIZE_UNIT (inner
));
15074 /* Return true if X contains a MEM that is not safe from R10K speculation.
15075 INSN is the instruction that contains X. */
15078 r10k_needs_protection_p_1 (rtx x
, rtx_insn
*insn
)
15080 subrtx_var_iterator::array_type array
;
15081 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
15086 if ((MEM_EXPR (mem
)
15087 && MEM_OFFSET_KNOWN_P (mem
)
15088 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
15089 || r10k_safe_address_p (XEXP (mem
, 0), insn
))
15090 iter
.skip_subrtxes ();
15098 /* A note_stores callback for which DATA points to an instruction pointer.
15099 If *DATA is nonnull, make it null if it X contains a MEM that is not
15100 safe from R10K speculation. */
15103 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
15106 rtx_insn
**insn_ptr
;
15108 insn_ptr
= (rtx_insn
**) data
;
15109 if (*insn_ptr
&& r10k_needs_protection_p_1 (x
, *insn_ptr
))
15113 /* X is the pattern of a call instruction. Return true if the call is
15114 not to a declared function. */
15117 r10k_needs_protection_p_call (const_rtx x
)
15119 subrtx_iterator::array_type array
;
15120 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
15122 const_rtx mem
= *iter
;
15125 const_rtx addr
= XEXP (mem
, 0);
15126 if (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_DECL (addr
))
15127 iter
.skip_subrtxes ();
15135 /* Return true if instruction INSN needs to be protected by an R10K
15139 r10k_needs_protection_p (rtx_insn
*insn
)
15142 return r10k_needs_protection_p_call (PATTERN (insn
));
15144 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
15146 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
15147 return insn
== NULL_RTX
;
15150 return r10k_needs_protection_p_1 (PATTERN (insn
), insn
);
15153 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15154 edge is unconditional. */
15157 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
15162 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
15163 if (!single_succ_p (e
->src
)
15164 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
15165 || (e
->flags
& EDGE_COMPLEX
) != 0)
15170 /* Implement -mr10k-cache-barrier= for the current function. */
15173 r10k_insert_cache_barriers (void)
15175 int *rev_post_order
;
15178 sbitmap protected_bbs
;
15179 rtx_insn
*insn
, *end
;
15180 rtx unprotected_region
;
15184 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15188 /* Calculate dominators. */
15189 calculate_dominance_info (CDI_DOMINATORS
);
15191 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15192 X is protected by a cache barrier. */
15193 protected_bbs
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
15194 bitmap_clear (protected_bbs
);
15196 /* Iterate over the basic blocks in reverse post-order. */
15197 rev_post_order
= XNEWVEC (int, last_basic_block_for_fn (cfun
));
15198 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
15199 for (i
= 0; i
< n
; i
++)
15201 bb
= BASIC_BLOCK_FOR_FN (cfun
, rev_post_order
[i
]);
15203 /* If this block is only reached by unconditional edges, and if the
15204 source of every edge is protected, the beginning of the block is
15206 if (r10k_protected_bb_p (bb
, protected_bbs
))
15207 unprotected_region
= NULL_RTX
;
15209 unprotected_region
= pc_rtx
;
15210 end
= NEXT_INSN (BB_END (bb
));
15212 /* UNPROTECTED_REGION is:
15214 - null if we are processing a protected region,
15215 - pc_rtx if we are processing an unprotected region but have
15216 not yet found the first instruction in it
15217 - the first instruction in an unprotected region otherwise. */
15218 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
15220 if (unprotected_region
&& USEFUL_INSN_P (insn
))
15222 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
15223 /* This CACHE instruction protects the following code. */
15224 unprotected_region
= NULL_RTX
;
15227 /* See if INSN is the first instruction in this
15228 unprotected region. */
15229 if (unprotected_region
== pc_rtx
)
15230 unprotected_region
= insn
;
15232 /* See if INSN needs to be protected. If so,
15233 we must insert a cache barrier somewhere between
15234 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15235 clear which position is better performance-wise,
15236 but as a tie-breaker, we assume that it is better
15237 to allow delay slots to be back-filled where
15238 possible, and that it is better not to insert
15239 barriers in the middle of already-scheduled code.
15240 We therefore insert the barrier at the beginning
15242 if (r10k_needs_protection_p (insn
))
15244 emit_insn_before (gen_r10k_cache_barrier (),
15245 unprotected_region
);
15246 unprotected_region
= NULL_RTX
;
15252 /* The called function is not required to protect the exit path.
15253 The code that follows a call is therefore unprotected. */
15254 unprotected_region
= pc_rtx
;
15257 /* Record whether the end of this block is protected. */
15258 if (unprotected_region
== NULL_RTX
)
15259 bitmap_set_bit (protected_bbs
, bb
->index
);
15261 XDELETEVEC (rev_post_order
);
15263 sbitmap_free (protected_bbs
);
15265 free_dominance_info (CDI_DOMINATORS
);
15268 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15269 otherwise. If INSN has two call rtx, then store the second one in
15273 mips_call_expr_from_insn (rtx_insn
*insn
, rtx
*second_call
)
15278 if (!CALL_P (insn
))
15281 x
= PATTERN (insn
);
15282 if (GET_CODE (x
) == PARALLEL
)
15284 /* Calls returning complex values have two CALL rtx. Look for the second
15285 one here, and return it via the SECOND_CALL arg. */
15286 x2
= XVECEXP (x
, 0, 1);
15287 if (GET_CODE (x2
) == SET
)
15289 if (GET_CODE (x2
) == CALL
)
15292 x
= XVECEXP (x
, 0, 0);
15294 if (GET_CODE (x
) == SET
)
15296 gcc_assert (GET_CODE (x
) == CALL
);
15301 /* REG is set in DEF. See if the definition is one of the ways we load a
15302 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15303 If it is, return the symbol reference of the function, otherwise return
15306 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15307 the values of source registers, otherwise treat such registers as
15308 having an unknown value. */
15311 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
15313 rtx_insn
*def_insn
;
15316 if (DF_REF_IS_ARTIFICIAL (def
))
15319 def_insn
= DF_REF_INSN (def
);
15320 set
= single_set (def_insn
);
15321 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
15323 rtx note
, src
, symbol
;
15325 /* First see whether the source is a plain symbol. This is used
15326 when calling symbols that are not lazily bound. */
15327 src
= SET_SRC (set
);
15328 if (GET_CODE (src
) == SYMBOL_REF
)
15331 /* Handle %call16 references. */
15332 symbol
= mips_strip_unspec_call (src
);
15335 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15339 /* If we have something more complicated, look for a
15340 REG_EQUAL or REG_EQUIV note. */
15341 note
= find_reg_equal_equiv_note (def_insn
);
15342 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
15343 return XEXP (note
, 0);
15345 /* Follow at most one simple register copy. Such copies are
15346 interesting in cases like:
15350 locally_binding_fn (...);
15355 locally_binding_fn (...);
15357 locally_binding_fn (...);
15359 where the load of locally_binding_fn can legitimately be
15360 hoisted or shared. However, we do not expect to see complex
15361 chains of copies, so a full worklist solution to the problem
15362 would probably be overkill. */
15363 if (recurse_p
&& REG_P (src
))
15364 return mips_find_pic_call_symbol (def_insn
, src
, false);
15370 /* Find the definition of the use of REG in INSN. See if the definition
15371 is one of the ways we load a register with a symbol address for a
15372 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15373 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15374 mips_pic_call_symbol_from_set. */
15377 mips_find_pic_call_symbol (rtx_insn
*insn
, rtx reg
, bool recurse_p
)
15380 struct df_link
*defs
;
15383 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
15386 defs
= DF_REF_CHAIN (use
);
15389 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15393 /* If we have more than one definition, they need to be identical. */
15394 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
15398 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15399 if (!rtx_equal_p (symbol
, other
))
15406 /* Replace the args_size operand of the call expression CALL with the
15407 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15410 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
15414 args_size
= XEXP (call
, 1);
15415 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
15416 gen_rtvec (2, args_size
, symbol
),
15420 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15421 if instead of the arg_size argument it contains the call attributes. If
15422 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15423 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15427 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
15429 rtx args_size
, symbol
;
15431 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
15434 args_size
= operands
[args_size_opno
];
15435 if (GET_CODE (args_size
) != UNSPEC
)
15437 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
15439 symbol
= XVECEXP (args_size
, 0, 1);
15440 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15442 operands
[args_size_opno
] = symbol
;
15446 /* Use DF to annotate PIC indirect calls with the function symbol they
15450 mips_annotate_pic_calls (void)
15455 FOR_EACH_BB_FN (bb
, cfun
)
15456 FOR_BB_INSNS (bb
, insn
)
15458 rtx call
, reg
, symbol
, second_call
;
15461 call
= mips_call_expr_from_insn (insn
, &second_call
);
15464 gcc_assert (MEM_P (XEXP (call
, 0)));
15465 reg
= XEXP (XEXP (call
, 0), 0);
15469 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
15472 mips_annotate_pic_call_expr (call
, symbol
);
15474 mips_annotate_pic_call_expr (second_call
, symbol
);
15479 /* A temporary variable used by note_uses callbacks, etc. */
15480 static rtx_insn
*mips_sim_insn
;
15482 /* A structure representing the state of the processor pipeline.
15483 Used by the mips_sim_* family of functions. */
15485 /* The maximum number of instructions that can be issued in a cycle.
15486 (Caches mips_issue_rate.) */
15487 unsigned int issue_rate
;
15489 /* The current simulation time. */
15492 /* How many more instructions can be issued in the current cycle. */
15493 unsigned int insns_left
;
15495 /* LAST_SET[X].INSN is the last instruction to set register X.
15496 LAST_SET[X].TIME is the time at which that instruction was issued.
15497 INSN is null if no instruction has yet set register X. */
15501 } last_set
[FIRST_PSEUDO_REGISTER
];
15503 /* The pipeline's current DFA state. */
15507 /* Reset STATE to the initial simulation state. */
15510 mips_sim_reset (struct mips_sim
*state
)
15512 curr_state
= state
->dfa_state
;
15515 state
->insns_left
= state
->issue_rate
;
15516 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
15517 state_reset (curr_state
);
15519 targetm
.sched
.init (0, false, 0);
15520 advance_state (curr_state
);
15523 /* Initialize STATE before its first use. DFA_STATE points to an
15524 allocated but uninitialized DFA state. */
15527 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
15529 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
15530 targetm
.sched
.init_dfa_pre_cycle_insn ();
15532 if (targetm
.sched
.init_dfa_post_cycle_insn
)
15533 targetm
.sched
.init_dfa_post_cycle_insn ();
15535 state
->issue_rate
= mips_issue_rate ();
15536 state
->dfa_state
= dfa_state
;
15537 mips_sim_reset (state
);
15540 /* Advance STATE by one clock cycle. */
15543 mips_sim_next_cycle (struct mips_sim
*state
)
15545 curr_state
= state
->dfa_state
;
15548 state
->insns_left
= state
->issue_rate
;
15549 advance_state (curr_state
);
15552 /* Advance simulation state STATE until instruction INSN can read
15556 mips_sim_wait_reg (struct mips_sim
*state
, rtx_insn
*insn
, rtx reg
)
15558 unsigned int regno
, end_regno
;
15560 end_regno
= END_REGNO (reg
);
15561 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
15562 if (state
->last_set
[regno
].insn
!= 0)
15566 t
= (state
->last_set
[regno
].time
15567 + insn_latency (state
->last_set
[regno
].insn
, insn
));
15568 while (state
->time
< t
)
15569 mips_sim_next_cycle (state
);
15573 /* A note_uses callback. For each register in *X, advance simulation
15574 state DATA until mips_sim_insn can read the register's value. */
15577 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
15579 subrtx_var_iterator::array_type array
;
15580 FOR_EACH_SUBRTX_VAR (iter
, array
, *x
, NONCONST
)
15582 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *iter
);
15585 /* Advance simulation state STATE until all of INSN's register
15586 dependencies are satisfied. */
15589 mips_sim_wait_regs (struct mips_sim
*state
, rtx_insn
*insn
)
15591 mips_sim_insn
= insn
;
15592 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
15595 /* Advance simulation state STATE until the units required by
15596 instruction INSN are available. */
15599 mips_sim_wait_units (struct mips_sim
*state
, rtx_insn
*insn
)
15603 tmp_state
= alloca (state_size ());
15604 while (state
->insns_left
== 0
15605 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
15606 state_transition (tmp_state
, insn
) >= 0))
15607 mips_sim_next_cycle (state
);
15610 /* Advance simulation state STATE until INSN is ready to issue. */
15613 mips_sim_wait_insn (struct mips_sim
*state
, rtx_insn
*insn
)
15615 mips_sim_wait_regs (state
, insn
);
15616 mips_sim_wait_units (state
, insn
);
15619 /* mips_sim_insn has just set X. Update the LAST_SET array
15620 in simulation state DATA. */
15623 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
15625 struct mips_sim
*state
;
15627 state
= (struct mips_sim
*) data
;
15630 unsigned int regno
, end_regno
;
15632 end_regno
= END_REGNO (x
);
15633 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
15635 state
->last_set
[regno
].insn
= mips_sim_insn
;
15636 state
->last_set
[regno
].time
= state
->time
;
15641 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15642 can issue immediately (i.e., that mips_sim_wait_insn has already
15646 mips_sim_issue_insn (struct mips_sim
*state
, rtx_insn
*insn
)
15648 curr_state
= state
->dfa_state
;
15650 state_transition (curr_state
, insn
);
15651 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
15652 state
->insns_left
);
15654 mips_sim_insn
= insn
;
15655 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
15658 /* Simulate issuing a NOP in state STATE. */
15661 mips_sim_issue_nop (struct mips_sim
*state
)
15663 if (state
->insns_left
== 0)
15664 mips_sim_next_cycle (state
);
15665 state
->insns_left
--;
15668 /* Update simulation state STATE so that it's ready to accept the instruction
15669 after INSN. INSN should be part of the main rtl chain, not a member of a
15673 mips_sim_finish_insn (struct mips_sim
*state
, rtx_insn
*insn
)
15675 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15677 mips_sim_issue_nop (state
);
15679 switch (GET_CODE (SEQ_BEGIN (insn
)))
15683 /* We can't predict the processor state after a call or label. */
15684 mips_sim_reset (state
);
15688 /* The delay slots of branch likely instructions are only executed
15689 when the branch is taken. Therefore, if the caller has simulated
15690 the delay slot instruction, STATE does not really reflect the state
15691 of the pipeline for the instruction after the delay slot. Also,
15692 branch likely instructions tend to incur a penalty when not taken,
15693 so there will probably be an extra delay between the branch and
15694 the instruction after the delay slot. */
15695 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
15696 mips_sim_reset (state
);
15704 /* Use simulator state STATE to calculate the execution time of
15705 instruction sequence SEQ. */
15707 static unsigned int
15708 mips_seq_time (struct mips_sim
*state
, rtx_insn
*seq
)
15710 mips_sim_reset (state
);
15711 for (rtx_insn
*insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
15713 mips_sim_wait_insn (state
, insn
);
15714 mips_sim_issue_insn (state
, insn
);
15716 return state
->time
;
15719 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15720 setting SETTING, using STATE to simulate instruction sequences. */
15722 static unsigned int
15723 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
15725 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
15728 enum machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
15729 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
15730 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
15732 /* If the target provides mulsidi3_32bit then that's the most likely
15733 consumer of the result. Test for bypasses. */
15734 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
15736 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
15737 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
15740 unsigned int time
= mips_seq_time (state
, get_insns ());
15745 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15746 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15747 Prefer MULT -- which is shorter -- in the event of a tie. */
15750 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
15753 /* No MTLO or MTHI available. */
15754 mips_tuning_info
.fast_mult_zero_zero_p
= true;
15757 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
15758 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
15759 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
15763 /* Set up costs based on the current architecture and tuning settings. */
15766 mips_set_tuning_info (void)
15768 if (mips_tuning_info
.initialized_p
15769 && mips_tuning_info
.arch
== mips_arch
15770 && mips_tuning_info
.tune
== mips_tune
15771 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
15774 mips_tuning_info
.arch
= mips_arch
;
15775 mips_tuning_info
.tune
= mips_tune
;
15776 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
15777 mips_tuning_info
.initialized_p
= true;
15781 struct mips_sim state
;
15782 mips_sim_init (&state
, alloca (state_size ()));
15784 mips_set_fast_mult_zero_zero_p (&state
);
15789 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15792 mips_expand_to_rtl_hook (void)
15794 /* We need to call this at a point where we can safely create sequences
15795 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15796 need to call it at a point where the DFA infrastructure is not
15797 already in use, so we can't just call it lazily on demand.
15799 At present, mips_tuning_info is only needed during post-expand
15800 RTL passes such as split_insns, so this hook should be early enough.
15801 We may need to move the call elsewhere if mips_tuning_info starts
15802 to be used for other things (such as rtx_costs, or expanders that
15803 could be called during gimple optimization). */
15804 mips_set_tuning_info ();
15807 /* The VR4130 pipeline issues aligned pairs of instructions together,
15808 but it stalls the second instruction if it depends on the first.
15809 In order to cut down the amount of logic required, this dependence
15810 check is not based on a full instruction decode. Instead, any non-SPECIAL
15811 instruction is assumed to modify the register specified by bits 20-16
15812 (which is usually the "rt" field).
15814 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15815 input, so we can end up with a false dependence between the branch
15816 and its delay slot. If this situation occurs in instruction INSN,
15817 try to avoid it by swapping rs and rt. */
15820 vr4130_avoid_branch_rt_conflict (rtx_insn
*insn
)
15822 rtx_insn
*first
, *second
;
15824 first
= SEQ_BEGIN (insn
);
15825 second
= SEQ_END (insn
);
15827 && NONJUMP_INSN_P (second
)
15828 && GET_CODE (PATTERN (first
)) == SET
15829 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
15830 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
15832 /* Check for the right kind of condition. */
15833 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
15834 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
15835 && REG_P (XEXP (cond
, 0))
15836 && REG_P (XEXP (cond
, 1))
15837 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
15838 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
15840 /* SECOND mentions the rt register but not the rs register. */
15841 rtx tmp
= XEXP (cond
, 0);
15842 XEXP (cond
, 0) = XEXP (cond
, 1);
15843 XEXP (cond
, 1) = tmp
;
15848 /* Implement -mvr4130-align. Go through each basic block and simulate the
15849 processor pipeline. If we find that a pair of instructions could execute
15850 in parallel, and the first of those instructions is not 8-byte aligned,
15851 insert a nop to make it aligned. */
15854 vr4130_align_insns (void)
15856 struct mips_sim state
;
15857 rtx_insn
*insn
, *subinsn
, *last
, *last2
, *next
;
15862 /* LAST is the last instruction before INSN to have a nonzero length.
15863 LAST2 is the last such instruction before LAST. */
15867 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15870 mips_sim_init (&state
, alloca (state_size ()));
15871 for (insn
= get_insns (); insn
!= 0; insn
= next
)
15873 unsigned int length
;
15875 next
= NEXT_INSN (insn
);
15877 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15878 This isn't really related to the alignment pass, but we do it on
15879 the fly to avoid a separate instruction walk. */
15880 vr4130_avoid_branch_rt_conflict (insn
);
15882 length
= get_attr_length (insn
);
15883 if (length
> 0 && USEFUL_INSN_P (insn
))
15884 FOR_EACH_SUBINSN (subinsn
, insn
)
15886 mips_sim_wait_insn (&state
, subinsn
);
15888 /* If we want this instruction to issue in parallel with the
15889 previous one, make sure that the previous instruction is
15890 aligned. There are several reasons why this isn't worthwhile
15891 when the second instruction is a call:
15893 - Calls are less likely to be performance critical,
15894 - There's a good chance that the delay slot can execute
15895 in parallel with the call.
15896 - The return address would then be unaligned.
15898 In general, if we're going to insert a nop between instructions
15899 X and Y, it's better to insert it immediately after X. That
15900 way, if the nop makes Y aligned, it will also align any labels
15901 between X and Y. */
15902 if (state
.insns_left
!= state
.issue_rate
15903 && !CALL_P (subinsn
))
15905 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
15907 /* SUBINSN is the first instruction in INSN and INSN is
15908 aligned. We want to align the previous instruction
15909 instead, so insert a nop between LAST2 and LAST.
15911 Note that LAST could be either a single instruction
15912 or a branch with a delay slot. In the latter case,
15913 LAST, like INSN, is already aligned, but the delay
15914 slot must have some extra delay that stops it from
15915 issuing at the same time as the branch. We therefore
15916 insert a nop before the branch in order to align its
15918 gcc_assert (last2
);
15919 emit_insn_after (gen_nop (), last2
);
15922 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
15924 /* SUBINSN is the delay slot of INSN, but INSN is
15925 currently unaligned. Insert a nop between
15926 LAST and INSN to align it. */
15928 emit_insn_after (gen_nop (), last
);
15932 mips_sim_issue_insn (&state
, subinsn
);
15934 mips_sim_finish_insn (&state
, insn
);
15936 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15937 length
= get_attr_length (insn
);
15940 /* If the instruction is an asm statement or multi-instruction
15941 mips.md patern, the length is only an estimate. Insert an
15942 8 byte alignment after it so that the following instructions
15943 can be handled correctly. */
15944 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
15945 && (recog_memoized (insn
) < 0 || length
>= 8))
15947 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
15948 next
= NEXT_INSN (next
);
15949 mips_sim_next_cycle (&state
);
15952 else if (length
& 4)
15953 aligned_p
= !aligned_p
;
15958 /* See whether INSN is an aligned label. */
15959 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
15965 /* This structure records that the current function has a LO_SUM
15966 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15967 the largest offset applied to BASE by all such LO_SUMs. */
15968 struct mips_lo_sum_offset
{
15970 HOST_WIDE_INT offset
;
15973 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15976 mips_hash_base (rtx base
)
15978 int do_not_record_p
;
15980 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
15983 /* Hashtable helpers. */
15985 struct mips_lo_sum_offset_hasher
: typed_free_remove
<mips_lo_sum_offset
>
15987 typedef mips_lo_sum_offset value_type
;
15988 typedef rtx_def compare_type
;
15989 static inline hashval_t
hash (const value_type
*);
15990 static inline bool equal (const value_type
*, const compare_type
*);
15993 /* Hash-table callbacks for mips_lo_sum_offsets. */
15996 mips_lo_sum_offset_hasher::hash (const value_type
*entry
)
15998 return mips_hash_base (entry
->base
);
16002 mips_lo_sum_offset_hasher::equal (const value_type
*entry
,
16003 const compare_type
*value
)
16005 return rtx_equal_p (entry
->base
, value
);
16008 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
16010 /* Look up symbolic constant X in HTAB, which is a hash table of
16011 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
16012 paired with a recorded LO_SUM, otherwise record X in the table. */
16015 mips_lo_sum_offset_lookup (mips_offset_table
*htab
, rtx x
,
16016 enum insert_option option
)
16019 mips_lo_sum_offset
**slot
;
16020 struct mips_lo_sum_offset
*entry
;
16022 /* Split X into a base and offset. */
16023 split_const (x
, &base
, &offset
);
16024 if (UNSPEC_ADDRESS_P (base
))
16025 base
= UNSPEC_ADDRESS (base
);
16027 /* Look up the base in the hash table. */
16028 slot
= htab
->find_slot_with_hash (base
, mips_hash_base (base
), option
);
16032 entry
= (struct mips_lo_sum_offset
*) *slot
;
16033 if (option
== INSERT
)
16037 entry
= XNEW (struct mips_lo_sum_offset
);
16038 entry
->base
= base
;
16039 entry
->offset
= INTVAL (offset
);
16044 if (INTVAL (offset
) > entry
->offset
)
16045 entry
->offset
= INTVAL (offset
);
16048 return INTVAL (offset
) <= entry
->offset
;
16051 /* Search X for LO_SUMs and record them in HTAB. */
16054 mips_record_lo_sums (const_rtx x
, mips_offset_table
*htab
)
16056 subrtx_iterator::array_type array
;
16057 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
16058 if (GET_CODE (*iter
) == LO_SUM
)
16059 mips_lo_sum_offset_lookup (htab
, XEXP (*iter
, 1), INSERT
);
16062 /* Return true if INSN is a SET of an orphaned high-part relocation.
16063 HTAB is a hash table of mips_lo_sum_offsets that describes all the
16064 LO_SUMs in the current function. */
16067 mips_orphaned_high_part_p (mips_offset_table
*htab
, rtx_insn
*insn
)
16069 enum mips_symbol_type type
;
16072 set
= single_set (insn
);
16075 /* Check for %his. */
16077 if (GET_CODE (x
) == HIGH
16078 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
16079 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
16081 /* Check for local %gots (and %got_pages, which is redundant but OK). */
16082 if (GET_CODE (x
) == UNSPEC
16083 && XINT (x
, 1) == UNSPEC_LOAD_GOT
16084 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
16085 SYMBOL_CONTEXT_LEA
, &type
)
16086 && type
== SYMBOL_GOTOFF_PAGE
)
16087 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
16092 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
16093 INSN and a previous instruction, avoid it by inserting nops after
16096 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
16097 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
16098 before using the value of that register. *HILO_DELAY counts the
16099 number of instructions since the last hilo hazard (that is,
16100 the number of instructions since the last MFLO or MFHI).
16102 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
16103 for the next instruction.
16105 LO_REG is an rtx for the LO register, used in dependence checking. */
16108 mips_avoid_hazard (rtx_insn
*after
, rtx_insn
*insn
, int *hilo_delay
,
16109 rtx
*delayed_reg
, rtx lo_reg
)
16114 pattern
= PATTERN (insn
);
16116 /* Do not put the whole function in .set noreorder if it contains
16117 an asm statement. We don't know whether there will be hazards
16118 between the asm statement and the gcc-generated code. */
16119 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
16120 cfun
->machine
->all_noreorder_p
= false;
16122 /* Ignore zero-length instructions (barriers and the like). */
16123 ninsns
= get_attr_length (insn
) / 4;
16127 /* Work out how many nops are needed. Note that we only care about
16128 registers that are explicitly mentioned in the instruction's pattern.
16129 It doesn't matter that calls use the argument registers or that they
16130 clobber hi and lo. */
16131 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
16132 nops
= 2 - *hilo_delay
;
16133 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
16138 /* Insert the nops between this instruction and the previous one.
16139 Each new nop takes us further from the last hilo hazard. */
16140 *hilo_delay
+= nops
;
16142 emit_insn_after (gen_hazard_nop (), after
);
16144 /* Set up the state for the next instruction. */
16145 *hilo_delay
+= ninsns
;
16147 if (INSN_CODE (insn
) >= 0)
16148 switch (get_attr_hazard (insn
))
16158 set
= single_set (insn
);
16160 *delayed_reg
= SET_DEST (set
);
16165 /* Go through the instruction stream and insert nops where necessary.
16166 Also delete any high-part relocations whose partnering low parts
16167 are now all dead. See if the whole function can then be put into
16168 .set noreorder and .set nomacro. */
16171 mips_reorg_process_insns (void)
16173 rtx_insn
*insn
, *last_insn
, *subinsn
, *next_insn
;
16174 rtx lo_reg
, delayed_reg
;
16177 /* Force all instructions to be split into their final form. */
16178 split_all_insns_noflow ();
16180 /* Recalculate instruction lengths without taking nops into account. */
16181 cfun
->machine
->ignore_hazard_length_p
= true;
16182 shorten_branches (get_insns ());
16184 cfun
->machine
->all_noreorder_p
= true;
16186 /* We don't track MIPS16 PC-relative offsets closely enough to make
16187 a good job of "set .noreorder" code in MIPS16 mode. */
16189 cfun
->machine
->all_noreorder_p
= false;
16191 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16192 if (!TARGET_EXPLICIT_RELOCS
)
16193 cfun
->machine
->all_noreorder_p
= false;
16195 /* Profiled functions can't be all noreorder because the profiler
16196 support uses assembler macros. */
16198 cfun
->machine
->all_noreorder_p
= false;
16200 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16201 all noreorder because we rely on the assembler to work around some
16202 errata. The R5900 too has several bugs. */
16203 if (TARGET_FIX_VR4120
16204 || TARGET_FIX_RM7000
16206 || TARGET_MIPS5900
)
16207 cfun
->machine
->all_noreorder_p
= false;
16209 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16210 MFHI instructions. Note that we avoid using MFLO and MFHI if
16211 the VR4130 MACC and DMACC instructions are available instead;
16212 see the *mfhilo_{si,di}_macc patterns. */
16213 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
16214 cfun
->machine
->all_noreorder_p
= false;
16216 mips_offset_table
htab (37);
16218 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16219 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16220 FOR_EACH_SUBINSN (subinsn
, insn
)
16221 if (USEFUL_INSN_P (subinsn
))
16223 rtx body
= PATTERN (insn
);
16224 int noperands
= asm_noperands (body
);
16225 if (noperands
>= 0)
16227 rtx
*ops
= XALLOCAVEC (rtx
, noperands
);
16228 bool *used
= XALLOCAVEC (bool, noperands
);
16229 const char *string
= decode_asm_operands (body
, ops
, NULL
, NULL
,
16231 get_referenced_operands (string
, used
, noperands
);
16232 for (int i
= 0; i
< noperands
; ++i
)
16234 mips_record_lo_sums (ops
[i
], &htab
);
16237 mips_record_lo_sums (PATTERN (subinsn
), &htab
);
16243 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
16245 /* Make a second pass over the instructions. Delete orphaned
16246 high-part relocations or turn them into NOPs. Avoid hazards
16247 by inserting NOPs. */
16248 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
16250 next_insn
= NEXT_INSN (insn
);
16251 if (USEFUL_INSN_P (insn
))
16253 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
16255 /* If we find an orphaned high-part relocation in a delay
16256 slot, it's easier to turn that instruction into a NOP than
16257 to delete it. The delay slot will be a NOP either way. */
16258 FOR_EACH_SUBINSN (subinsn
, insn
)
16259 if (INSN_P (subinsn
))
16261 if (mips_orphaned_high_part_p (&htab
, subinsn
))
16263 PATTERN (subinsn
) = gen_nop ();
16264 INSN_CODE (subinsn
) = CODE_FOR_nop
;
16266 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
16267 &delayed_reg
, lo_reg
);
16273 /* INSN is a single instruction. Delete it if it's an
16274 orphaned high-part relocation. */
16275 if (mips_orphaned_high_part_p (&htab
, insn
))
16276 delete_insn (insn
);
16277 /* Also delete cache barriers if the last instruction
16278 was an annulled branch. INSN will not be speculatively
16280 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
16282 && JUMP_P (SEQ_BEGIN (last_insn
))
16283 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
16284 delete_insn (insn
);
16287 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
16288 &delayed_reg
, lo_reg
);
16296 /* Return true if the function has a long branch instruction. */
16299 mips_has_long_branch_p (void)
16301 rtx_insn
*insn
, *subinsn
;
16304 /* We need up-to-date instruction lengths. */
16305 shorten_branches (get_insns ());
16307 /* Look for a branch that is longer than normal. The normal length for
16308 non-MIPS16 branches is 8, because the length includes the delay slot.
16309 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16310 but they have no delay slot. */
16311 normal_length
= (TARGET_MIPS16
? 4 : 8);
16312 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16313 FOR_EACH_SUBINSN (subinsn
, insn
)
16314 if (JUMP_P (subinsn
)
16315 && get_attr_length (subinsn
) > normal_length
16316 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
16322 /* If we are using a GOT, but have not decided to use a global pointer yet,
16323 see whether we need one to implement long branches. Convert the ghost
16324 global-pointer instructions into real ones if so. */
16327 mips_expand_ghost_gp_insns (void)
16329 /* Quick exit if we already know that we will or won't need a
16331 if (!TARGET_USE_GOT
16332 || cfun
->machine
->global_pointer
== INVALID_REGNUM
16333 || mips_must_initialize_gp_p ())
16336 /* Run a full check for long branches. */
16337 if (!mips_has_long_branch_p ())
16340 /* We've now established that we need $gp. */
16341 cfun
->machine
->must_initialize_gp_p
= true;
16342 split_all_insns_noflow ();
16347 /* Subroutine of mips_reorg to manage passes that require DF. */
16350 mips_df_reorg (void)
16352 /* Create def-use chains. */
16353 df_set_flags (DF_EQ_NOTES
);
16354 df_chain_add_problem (DF_UD_CHAIN
);
16357 if (TARGET_RELAX_PIC_CALLS
)
16358 mips_annotate_pic_calls ();
16360 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
16361 r10k_insert_cache_barriers ();
16363 df_finish_pass (false);
16366 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16367 called very late in mips_reorg, but the caller is required to run
16368 mips16_lay_out_constants on the result. */
16371 mips16_load_branch_target (rtx dest
, rtx src
)
16373 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
16377 if (mips_cfun_has_cprestore_slot_p ())
16378 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
16380 mips_emit_move (dest
, pic_offset_table_rtx
);
16381 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
16382 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
16383 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16384 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
16385 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16386 gen_rtx_LO_SUM (Pmode
, dest
, low
)));
16390 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
16391 mips_emit_move (dest
, src
);
16395 /* If we're compiling a MIPS16 function, look for and split any long branches.
16396 This must be called after all other instruction modifications in
16400 mips16_split_long_branches (void)
16402 bool something_changed
;
16404 if (!TARGET_MIPS16
)
16407 /* Loop until the alignments for all targets are sufficient. */
16412 shorten_branches (get_insns ());
16413 something_changed
= false;
16414 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16416 && get_attr_length (insn
) > 4
16417 && (any_condjump_p (insn
) || any_uncondjump_p (insn
)))
16419 rtx old_label
, temp
, saved_temp
;
16420 rtx_code_label
*new_label
;
16422 rtx_insn
*jump
, *jump_sequence
;
16426 /* Free up a MIPS16 register by saving it in $1. */
16427 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
16428 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
16429 emit_move_insn (saved_temp
, temp
);
16431 /* Load the branch target into TEMP. */
16432 old_label
= JUMP_LABEL (insn
);
16433 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
16434 mips16_load_branch_target (temp
, target
);
16436 /* Jump to the target and restore the register's
16438 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
16439 (temp
, temp
, saved_temp
)));
16440 JUMP_LABEL (jump
) = old_label
;
16441 LABEL_NUSES (old_label
)++;
16443 /* Rewrite any symbolic references that are supposed to use
16444 a PC-relative constant pool. */
16445 mips16_lay_out_constants (false);
16447 if (simplejump_p (insn
))
16448 /* We're going to replace INSN with a longer form. */
16452 /* Create a branch-around label for the original
16454 new_label
= gen_label_rtx ();
16455 emit_label (new_label
);
16458 jump_sequence
= get_insns ();
16461 emit_insn_after (jump_sequence
, insn
);
16463 invert_jump (insn
, new_label
, false);
16465 delete_insn (insn
);
16466 something_changed
= true;
16469 while (something_changed
);
16472 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16477 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16478 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16479 to date if the CFG is available. */
16480 if (mips_cfg_in_reorg ())
16481 compute_bb_for_insn ();
16482 mips16_lay_out_constants (true);
16483 if (mips_cfg_in_reorg ())
16486 free_bb_for_insn ();
16490 /* We use a machine specific pass to do a second machine dependent reorg
16491 pass after delay branch scheduling. */
16493 static unsigned int
16494 mips_machine_reorg2 (void)
16496 mips_reorg_process_insns ();
16498 && TARGET_EXPLICIT_RELOCS
16500 && TARGET_VR4130_ALIGN
)
16501 vr4130_align_insns ();
16502 if (mips_expand_ghost_gp_insns ())
16503 /* The expansion could invalidate some of the VR4130 alignment
16504 optimizations, but this should be an extremely rare case anyhow. */
16505 mips_reorg_process_insns ();
16506 mips16_split_long_branches ();
16512 const pass_data pass_data_mips_machine_reorg2
=
16514 RTL_PASS
, /* type */
16515 "mach2", /* name */
16516 OPTGROUP_NONE
, /* optinfo_flags */
16517 TV_MACH_DEP
, /* tv_id */
16518 0, /* properties_required */
16519 0, /* properties_provided */
16520 0, /* properties_destroyed */
16521 0, /* todo_flags_start */
16522 0, /* todo_flags_finish */
16525 class pass_mips_machine_reorg2
: public rtl_opt_pass
16528 pass_mips_machine_reorg2(gcc::context
*ctxt
)
16529 : rtl_opt_pass(pass_data_mips_machine_reorg2
, ctxt
)
16532 /* opt_pass methods: */
16533 virtual unsigned int execute (function
*) { return mips_machine_reorg2 (); }
16535 }; // class pass_mips_machine_reorg2
16537 } // anon namespace
16540 make_pass_mips_machine_reorg2 (gcc::context
*ctxt
)
16542 return new pass_mips_machine_reorg2 (ctxt
);
16546 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16547 in order to avoid duplicating too much logic from elsewhere. */
16550 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
16551 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
16554 rtx this_rtx
, temp1
, temp2
, fnaddr
;
16556 bool use_sibcall_p
;
16558 /* Pretend to be a post-reload pass while generating rtl. */
16559 reload_completed
= 1;
16561 /* Mark the end of the (empty) prologue. */
16562 emit_note (NOTE_INSN_PROLOGUE_END
);
16564 /* Determine if we can use a sibcall to call FUNCTION directly. */
16565 fnaddr
= XEXP (DECL_RTL (function
), 0);
16566 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
16567 && const_call_insn_operand (fnaddr
, Pmode
));
16569 /* Determine if we need to load FNADDR from the GOT. */
16571 && (mips_got_symbol_type_p
16572 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
16574 /* Pick a global pointer. Use a call-clobbered register if
16575 TARGET_CALL_SAVED_GP. */
16576 cfun
->machine
->global_pointer
16577 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
16578 cfun
->machine
->must_initialize_gp_p
= true;
16579 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
16581 /* Set up the global pointer for n32 or n64 abicalls. */
16582 mips_emit_loadgp ();
16585 /* We need two temporary registers in some cases. */
16586 temp1
= gen_rtx_REG (Pmode
, 2);
16587 temp2
= gen_rtx_REG (Pmode
, 3);
16589 /* Find out which register contains the "this" pointer. */
16590 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
16591 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
16593 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
16595 /* Add DELTA to THIS_RTX. */
16598 rtx offset
= GEN_INT (delta
);
16599 if (!SMALL_OPERAND (delta
))
16601 mips_emit_move (temp1
, offset
);
16604 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
16607 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16608 if (vcall_offset
!= 0)
16612 /* Set TEMP1 to *THIS_RTX. */
16613 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
16615 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16616 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
16618 /* Load the offset and add it to THIS_RTX. */
16619 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
16620 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
16623 /* Jump to the target function. Use a sibcall if direct jumps are
16624 allowed, otherwise load the address into a register first. */
16627 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
16628 SIBLING_CALL_P (insn
) = 1;
16632 /* This is messy. GAS treats "la $25,foo" as part of a call
16633 sequence and may allow a global "foo" to be lazily bound.
16634 The general move patterns therefore reject this combination.
16636 In this context, lazy binding would actually be OK
16637 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16638 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16639 We must therefore load the address via a temporary
16640 register if mips_dangerous_for_la25_p.
16642 If we jump to the temporary register rather than $25,
16643 the assembler can use the move insn to fill the jump's
16646 We can use the same technique for MIPS16 code, where $25
16647 is not a valid JR register. */
16648 if (TARGET_USE_PIC_FN_ADDR_REG
16650 && !mips_dangerous_for_la25_p (fnaddr
))
16651 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
16652 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
16654 if (TARGET_USE_PIC_FN_ADDR_REG
16655 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
16656 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
16657 emit_jump_insn (gen_indirect_jump (temp1
));
16660 /* Run just enough of rest_of_compilation. This sequence was
16661 "borrowed" from alpha.c. */
16662 insn
= get_insns ();
16663 split_all_insns_noflow ();
16664 mips16_lay_out_constants (true);
16665 shorten_branches (insn
);
16666 final_start_function (insn
, file
, 1);
16667 final (insn
, file
, 1);
16668 final_end_function ();
16670 /* Clean up the vars set above. Note that final_end_function resets
16671 the global pointer for us. */
16672 reload_completed
= 0;
16676 /* The last argument passed to mips_set_compression_mode,
16677 or negative if the function hasn't been called yet. */
16678 static unsigned int old_compression_mode
= -1;
16680 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16681 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16684 mips_set_compression_mode (unsigned int compression_mode
)
16687 if (compression_mode
== old_compression_mode
)
16690 /* Restore base settings of various flags. */
16691 target_flags
= mips_base_target_flags
;
16692 flag_schedule_insns
= mips_base_schedule_insns
;
16693 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
16694 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
16695 align_loops
= mips_base_align_loops
;
16696 align_jumps
= mips_base_align_jumps
;
16697 align_functions
= mips_base_align_functions
;
16698 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
16699 target_flags
|= compression_mode
;
16701 if (compression_mode
& MASK_MIPS16
)
16703 /* Switch to MIPS16 mode. */
16704 target_flags
|= MASK_MIPS16
;
16706 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16707 target_flags
&= ~MASK_SYNCI
;
16709 /* Don't run the scheduler before reload, since it tends to
16710 increase register pressure. */
16711 flag_schedule_insns
= 0;
16713 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16714 the whole function to be in a single section. */
16715 flag_reorder_blocks_and_partition
= 0;
16717 /* Don't move loop invariants, because it tends to increase
16718 register pressure. It also introduces an extra move in cases
16719 where the constant is the first operand in a two-operand binary
16720 instruction, or when it forms a register argument to a functon
16722 flag_move_loop_invariants
= 0;
16724 target_flags
|= MASK_EXPLICIT_RELOCS
;
16726 /* Experiments suggest we get the best overall section-anchor
16727 results from using the range of an unextended LW or SW. Code
16728 that makes heavy use of byte or short accesses can do better
16729 with ranges of 0...31 and 0...63 respectively, but most code is
16730 sensitive to the range of LW and SW instead. */
16731 targetm
.min_anchor_offset
= 0;
16732 targetm
.max_anchor_offset
= 127;
16734 targetm
.const_anchor
= 0;
16736 /* MIPS16 has no BAL instruction. */
16737 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
16739 /* The R4000 errata don't apply to any known MIPS16 cores.
16740 It's simpler to make the R4000 fixes and MIPS16 mode
16741 mutually exclusive. */
16742 target_flags
&= ~MASK_FIX_R4000
;
16744 if (flag_pic
&& !TARGET_OLDABI
)
16745 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16748 sorry ("MIPS16 -mxgot code");
16750 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
16751 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16755 /* Switch to microMIPS or the standard encoding. */
16757 if (TARGET_MICROMIPS
)
16758 /* Avoid branch likely. */
16759 target_flags
&= ~MASK_BRANCHLIKELY
;
16761 /* Provide default values for align_* for 64-bit targets. */
16764 if (align_loops
== 0)
16766 if (align_jumps
== 0)
16768 if (align_functions
== 0)
16769 align_functions
= 8;
16772 targetm
.min_anchor_offset
= -32768;
16773 targetm
.max_anchor_offset
= 32767;
16775 targetm
.const_anchor
= 0x8000;
16778 /* (Re)initialize MIPS target internals for new ISA. */
16779 mips_init_relocs ();
16781 if (compression_mode
& MASK_MIPS16
)
16783 if (!mips16_globals
)
16784 mips16_globals
= save_target_globals_default_opts ();
16786 restore_target_globals (mips16_globals
);
16789 restore_target_globals (&default_target_globals
);
16791 old_compression_mode
= compression_mode
;
16794 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16795 function should use the MIPS16 or microMIPS ISA and switch modes
16799 mips_set_current_function (tree fndecl
)
16801 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
16804 /* Allocate a chunk of memory for per-function machine-dependent data. */
16806 static struct machine_function
*
16807 mips_init_machine_status (void)
16809 return ggc_cleared_alloc
<machine_function
> ();
16812 /* Return the processor associated with the given ISA level, or null
16813 if the ISA isn't valid. */
16815 static const struct mips_cpu_info
*
16816 mips_cpu_info_from_isa (int isa
)
16820 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16821 if (mips_cpu_info_table
[i
].isa
== isa
)
16822 return mips_cpu_info_table
+ i
;
16827 /* Return a mips_cpu_info entry determined by an option valued
16830 static const struct mips_cpu_info
*
16831 mips_cpu_info_from_opt (int opt
)
16835 case MIPS_ARCH_OPTION_FROM_ABI
:
16836 /* 'from-abi' selects the most compatible architecture for the
16837 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16838 ABIs. For the EABIs, we have to decide whether we're using
16839 the 32-bit or 64-bit version. */
16840 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
16841 : ABI_NEEDS_64BIT_REGS
? 3
16842 : (TARGET_64BIT
? 3 : 1));
16844 case MIPS_ARCH_OPTION_NATIVE
:
16845 gcc_unreachable ();
16848 return &mips_cpu_info_table
[opt
];
16852 /* Return a default mips_cpu_info entry, given that no -march= option
16853 was explicitly specified. */
16855 static const struct mips_cpu_info
*
16856 mips_default_arch (void)
16858 #if defined (MIPS_CPU_STRING_DEFAULT)
16860 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16861 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
16862 return mips_cpu_info_table
+ i
;
16863 gcc_unreachable ();
16864 #elif defined (MIPS_ISA_DEFAULT)
16865 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
16867 /* 'from-abi' makes a good default: you get whatever the ABI
16869 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
16873 /* Set up globals to generate code for the ISA or processor
16874 described by INFO. */
16877 mips_set_architecture (const struct mips_cpu_info
*info
)
16881 mips_arch_info
= info
;
16882 mips_arch
= info
->cpu
;
16883 mips_isa
= info
->isa
;
16887 mips_isa_rev
= (mips_isa
& 31) + 1;
16891 /* Likewise for tuning. */
16894 mips_set_tune (const struct mips_cpu_info
*info
)
16898 mips_tune_info
= info
;
16899 mips_tune
= info
->cpu
;
16903 /* Implement TARGET_OPTION_OVERRIDE. */
16906 mips_option_override (void)
16908 int i
, start
, regno
, mode
;
16910 if (global_options_set
.x_mips_isa_option
)
16911 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
16913 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16914 SUBTARGET_OVERRIDE_OPTIONS
;
16917 /* MIPS16 and microMIPS cannot coexist. */
16918 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
16919 error ("unsupported combination: %s", "-mips16 -mmicromips");
16921 /* Save the base compression state and process flags as though we
16922 were generating uncompressed code. */
16923 mips_base_compression_flags
= TARGET_COMPRESSION
;
16924 target_flags
&= ~TARGET_COMPRESSION
;
16926 /* -mno-float overrides -mhard-float and -msoft-float. */
16927 if (TARGET_NO_FLOAT
)
16929 target_flags
|= MASK_SOFT_FLOAT_ABI
;
16930 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
16933 if (TARGET_FLIP_MIPS16
)
16934 TARGET_INTERLINK_COMPRESSED
= 1;
16936 /* Set the small data limit. */
16937 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
16939 : MIPS_DEFAULT_GVALUE
);
16941 /* The following code determines the architecture and register size.
16942 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16943 The GAS and GCC code should be kept in sync as much as possible. */
16945 if (global_options_set
.x_mips_arch_option
)
16946 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
16948 if (mips_isa_option_info
!= 0)
16950 if (mips_arch_info
== 0)
16951 mips_set_architecture (mips_isa_option_info
);
16952 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
16953 error ("%<-%s%> conflicts with the other architecture options, "
16954 "which specify a %s processor",
16955 mips_isa_option_info
->name
,
16956 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
16959 if (mips_arch_info
== 0)
16960 mips_set_architecture (mips_default_arch ());
16962 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
16963 error ("%<-march=%s%> is not compatible with the selected ABI",
16964 mips_arch_info
->name
);
16966 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16967 if (global_options_set
.x_mips_tune_option
)
16968 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
16970 if (mips_tune_info
== 0)
16971 mips_set_tune (mips_arch_info
);
16973 if ((target_flags_explicit
& MASK_64BIT
) != 0)
16975 /* The user specified the size of the integer registers. Make sure
16976 it agrees with the ABI and ISA. */
16977 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
16978 error ("%<-mgp64%> used with a 32-bit processor");
16979 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
16980 error ("%<-mgp32%> used with a 64-bit ABI");
16981 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
16982 error ("%<-mgp64%> used with a 32-bit ABI");
16986 /* Infer the integer register size from the ABI and processor.
16987 Restrict ourselves to 32-bit registers if that's all the
16988 processor has, or if the ABI cannot handle 64-bit registers. */
16989 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
16990 target_flags
&= ~MASK_64BIT
;
16992 target_flags
|= MASK_64BIT
;
16995 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
16997 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
16998 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16999 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
17000 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
17001 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
17003 if (!ISA_HAS_MXHC1
)
17004 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
17005 " the target supports the mfhc1 and mthc1 instructions");
17006 else if (mips_abi
!= ABI_32
)
17007 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
17013 /* -msingle-float selects 32-bit float registers. Otherwise the
17014 float registers should be the same size as the integer ones. */
17015 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
17016 target_flags
|= MASK_FLOAT64
;
17018 target_flags
&= ~MASK_FLOAT64
;
17021 /* End of code shared with GAS. */
17023 /* The R5900 FPU only supports single precision. */
17024 if (TARGET_MIPS5900
&& TARGET_HARD_FLOAT_ABI
&& TARGET_DOUBLE_FLOAT
)
17025 error ("unsupported combination: %s",
17026 "-march=r5900 -mhard-float -mdouble-float");
17028 /* If a -mlong* option was given, check that it matches the ABI,
17029 otherwise infer the -mlong* setting from the other options. */
17030 if ((target_flags_explicit
& MASK_LONG64
) != 0)
17034 if (mips_abi
== ABI_N32
)
17035 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
17036 else if (mips_abi
== ABI_32
)
17037 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
17038 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
17039 /* We have traditionally allowed non-abicalls code to use
17040 an LP64 form of o64. However, it would take a bit more
17041 effort to support the combination of 32-bit GOT entries
17042 and 64-bit pointers, so we treat the abicalls case as
17044 error ("the combination of %qs and %qs is incompatible with %qs",
17045 "-mabi=o64", "-mabicalls", "-mlong64");
17049 if (mips_abi
== ABI_64
)
17050 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
17055 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
17056 target_flags
|= MASK_LONG64
;
17058 target_flags
&= ~MASK_LONG64
;
17061 if (!TARGET_OLDABI
)
17062 flag_pcc_struct_return
= 0;
17064 /* Decide which rtx_costs structure to use. */
17066 mips_cost
= &mips_rtx_cost_optimize_size
;
17068 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
17070 /* If the user hasn't specified a branch cost, use the processor's
17072 if (mips_branch_cost
== 0)
17073 mips_branch_cost
= mips_cost
->branch_cost
;
17075 /* If neither -mbranch-likely nor -mno-branch-likely was given
17076 on the command line, set MASK_BRANCHLIKELY based on the target
17077 architecture and tuning flags. Annulled delay slots are a
17078 size win, so we only consider the processor-specific tuning
17079 for !optimize_size. */
17080 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
17082 if (ISA_HAS_BRANCHLIKELY
17084 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
17085 target_flags
|= MASK_BRANCHLIKELY
;
17087 target_flags
&= ~MASK_BRANCHLIKELY
;
17089 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
17090 warning (0, "the %qs architecture does not support branch-likely"
17091 " instructions", mips_arch_info
->name
);
17093 /* If the user hasn't specified -mimadd or -mno-imadd set
17094 MASK_IMADD based on the target architecture and tuning
17096 if ((target_flags_explicit
& MASK_IMADD
) == 0)
17098 if (ISA_HAS_MADD_MSUB
&&
17099 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
17100 target_flags
|= MASK_IMADD
;
17102 target_flags
&= ~MASK_IMADD
;
17104 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
17105 warning (0, "the %qs architecture does not support madd or msub"
17106 " instructions", mips_arch_info
->name
);
17108 /* The effect of -mabicalls isn't defined for the EABI. */
17109 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
17111 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
17112 target_flags
&= ~MASK_ABICALLS
;
17115 /* PIC requires -mabicalls. */
17118 if (mips_abi
== ABI_EABI
)
17119 error ("cannot generate position-independent code for %qs",
17121 else if (!TARGET_ABICALLS
)
17122 error ("position-independent code requires %qs", "-mabicalls");
17125 if (TARGET_ABICALLS_PIC2
)
17126 /* We need to set flag_pic for executables as well as DSOs
17127 because we may reference symbols that are not defined in
17128 the final executable. (MIPS does not use things like
17129 copy relocs, for example.)
17131 There is a body of code that uses __PIC__ to distinguish
17132 between -mabicalls and -mno-abicalls code. The non-__PIC__
17133 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
17134 long as any indirect jumps use $25. */
17137 /* -mvr4130-align is a "speed over size" optimization: it usually produces
17138 faster code, but at the expense of more nops. Enable it at -O3 and
17140 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
17141 target_flags
|= MASK_VR4130_ALIGN
;
17143 /* Prefer a call to memcpy over inline code when optimizing for size,
17144 though see MOVE_RATIO in mips.h. */
17145 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
17146 target_flags
|= MASK_MEMCPY
;
17148 /* If we have a nonzero small-data limit, check that the -mgpopt
17149 setting is consistent with the other target flags. */
17150 if (mips_small_data_threshold
> 0)
17154 if (!TARGET_EXPLICIT_RELOCS
)
17155 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17157 TARGET_LOCAL_SDATA
= false;
17158 TARGET_EXTERN_SDATA
= false;
17162 if (TARGET_VXWORKS_RTP
)
17163 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17165 if (TARGET_ABICALLS
)
17166 warning (0, "cannot use small-data accesses for %qs",
17171 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17172 for all its floating point. */
17173 if (mips_nan
!= MIPS_IEEE_754_2008
)
17175 REAL_MODE_FORMAT (SFmode
) = &mips_single_format
;
17176 REAL_MODE_FORMAT (DFmode
) = &mips_double_format
;
17177 REAL_MODE_FORMAT (TFmode
) = &mips_quad_format
;
17180 /* Make sure that the user didn't turn off paired single support when
17181 MIPS-3D support is requested. */
17183 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
17184 && !TARGET_PAIRED_SINGLE_FLOAT
)
17185 error ("%<-mips3d%> requires %<-mpaired-single%>");
17187 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17189 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
17191 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17192 and TARGET_HARD_FLOAT_ABI are both true. */
17193 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
17195 error ("%qs must be used with %qs",
17196 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
17197 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
17198 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
17202 /* Make sure that -mpaired-single is only used on ISAs that support it.
17203 We must disable it otherwise since it relies on other ISA properties
17204 like ISA_HAS_8CC having their normal values. */
17205 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
17207 error ("the %qs architecture does not support paired-single"
17208 " instructions", mips_arch_info
->name
);
17209 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
17213 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
17214 && !TARGET_CACHE_BUILTIN
)
17216 error ("%qs requires a target that provides the %qs instruction",
17217 "-mr10k-cache-barrier", "cache");
17218 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
17221 /* If TARGET_DSPR2, enable TARGET_DSP. */
17225 /* .eh_frame addresses should be the same width as a C pointer.
17226 Most MIPS ABIs support only one pointer size, so the assembler
17227 will usually know exactly how big an .eh_frame address is.
17229 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17230 originally defined to use 64-bit pointers (i.e. it is LP64), and
17231 this is still the default mode. However, we also support an n32-like
17232 ILP32 mode, which is selected by -mlong32. The problem is that the
17233 assembler has traditionally not had an -mlong option, so it has
17234 traditionally not known whether we're using the ILP32 or LP64 form.
17236 As it happens, gas versions up to and including 2.19 use _32-bit_
17237 addresses for EABI64 .cfi_* directives. This is wrong for the
17238 default LP64 mode, so we can't use the directives by default.
17239 Moreover, since gas's current behavior is at odds with gcc's
17240 default behavior, it seems unwise to rely on future versions
17241 of gas behaving the same way. We therefore avoid using .cfi
17242 directives for -mlong32 as well. */
17243 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
17244 flag_dwarf2_cfi_asm
= 0;
17246 /* .cfi_* directives generate a read-only section, so fall back on
17247 manual .eh_frame creation if we need the section to be writable. */
17248 if (TARGET_WRITABLE_EH_FRAME
)
17249 flag_dwarf2_cfi_asm
= 0;
17251 mips_init_print_operand_punct ();
17253 /* Set up array to map GCC register number to debug register number.
17254 Ignore the special purpose register numbers. */
17256 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17258 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
17259 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
17260 mips_dwarf_regno
[i
] = i
;
17262 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
17265 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
17266 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
17267 mips_dbx_regno
[i
] = i
+ start
;
17269 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
17270 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
17271 mips_dbx_regno
[i
] = i
+ start
;
17273 /* Accumulator debug registers use big-endian ordering. */
17274 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
17275 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
17276 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
17277 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
17278 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
17280 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
17281 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
17284 /* Set up mips_hard_regno_mode_ok. */
17285 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
17286 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
17287 mips_hard_regno_mode_ok
[mode
][regno
]
17288 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
17290 /* Function to allocate machine-dependent function status. */
17291 init_machine_status
= &mips_init_machine_status
;
17293 /* Default to working around R4000 errata only if the processor
17294 was selected explicitly. */
17295 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
17296 && strcmp (mips_arch_info
->name
, "r4000") == 0)
17297 target_flags
|= MASK_FIX_R4000
;
17299 /* Default to working around R4400 errata only if the processor
17300 was selected explicitly. */
17301 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
17302 && strcmp (mips_arch_info
->name
, "r4400") == 0)
17303 target_flags
|= MASK_FIX_R4400
;
17305 /* Default to working around R10000 errata only if the processor
17306 was selected explicitly. */
17307 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
17308 && strcmp (mips_arch_info
->name
, "r10000") == 0)
17309 target_flags
|= MASK_FIX_R10000
;
17311 /* Make sure that branch-likely instructions available when using
17312 -mfix-r10000. The instructions are not available if either:
17314 1. -mno-branch-likely was passed.
17315 2. The selected ISA does not support branch-likely and
17316 the command line does not include -mbranch-likely. */
17317 if (TARGET_FIX_R10000
17318 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
17319 ? !ISA_HAS_BRANCHLIKELY
17320 : !TARGET_BRANCHLIKELY
))
17321 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17323 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
17325 warning (0, "the %qs architecture does not support the synci "
17326 "instruction", mips_arch_info
->name
);
17327 target_flags
&= ~MASK_SYNCI
;
17330 /* Only optimize PIC indirect calls if they are actually required. */
17331 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
17332 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17334 /* Save base state of options. */
17335 mips_base_target_flags
= target_flags
;
17336 mips_base_schedule_insns
= flag_schedule_insns
;
17337 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
17338 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
17339 mips_base_align_loops
= align_loops
;
17340 mips_base_align_jumps
= align_jumps
;
17341 mips_base_align_functions
= align_functions
;
17343 /* Now select the ISA mode.
17345 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17346 later if required. */
17347 mips_set_compression_mode (0);
17349 /* We register a second machine specific reorg pass after delay slot
17350 filling. Registering the pass must be done at start up. It's
17351 convenient to do it here. */
17352 opt_pass
*new_pass
= make_pass_mips_machine_reorg2 (g
);
17353 struct register_pass_info insert_pass_mips_machine_reorg2
=
17355 new_pass
, /* pass */
17356 "dbr", /* reference_pass_name */
17357 1, /* ref_pass_instance_number */
17358 PASS_POS_INSERT_AFTER
/* po_op */
17360 register_pass (&insert_pass_mips_machine_reorg2
);
17362 if (TARGET_HARD_FLOAT_ABI
&& TARGET_MIPS5900
)
17363 REAL_MODE_FORMAT (SFmode
) = &spu_single_format
;
17366 /* Swap the register information for registers I and I + 1, which
17367 currently have the wrong endianness. Note that the registers'
17368 fixedness and call-clobberedness might have been set on the
17372 mips_swap_registers (unsigned int i
)
17377 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17378 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17380 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
17381 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
17382 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
17383 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
17389 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17392 mips_conditional_register_usage (void)
17397 /* These DSP control register fields are global. */
17398 global_regs
[CCDSP_PO_REGNUM
] = 1;
17399 global_regs
[CCDSP_SC_REGNUM
] = 1;
17402 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17403 reg_class_contents
[(int) DSP_ACC_REGS
]);
17405 if (!TARGET_HARD_FLOAT
)
17407 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17408 reg_class_contents
[(int) FP_REGS
]);
17409 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17410 reg_class_contents
[(int) ST_REGS
]);
17412 else if (!ISA_HAS_8CC
)
17414 /* We only have a single condition-code register. We implement
17415 this by fixing all the condition-code registers and generating
17416 RTL that refers directly to ST_REG_FIRST. */
17417 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17418 reg_class_contents
[(int) ST_REGS
]);
17419 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
17420 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
17424 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17425 are call-saved, and saving them via a MIPS16 register would
17426 probably waste more time than just reloading the value.
17428 We permit the $t temporary registers when optimizing for speed
17429 but not when optimizing for space because using them results in
17430 code that is larger (but faster) then not using them. We do
17431 allow $24 (t8) because it is used in CMP and CMPI instructions
17432 and $25 (t9) because it is used as the function call address in
17435 fixed_regs
[18] = call_used_regs
[18] = 1;
17436 fixed_regs
[19] = call_used_regs
[19] = 1;
17437 fixed_regs
[20] = call_used_regs
[20] = 1;
17438 fixed_regs
[21] = call_used_regs
[21] = 1;
17439 fixed_regs
[22] = call_used_regs
[22] = 1;
17440 fixed_regs
[23] = call_used_regs
[23] = 1;
17441 fixed_regs
[26] = call_used_regs
[26] = 1;
17442 fixed_regs
[27] = call_used_regs
[27] = 1;
17443 fixed_regs
[30] = call_used_regs
[30] = 1;
17446 fixed_regs
[8] = call_used_regs
[8] = 1;
17447 fixed_regs
[9] = call_used_regs
[9] = 1;
17448 fixed_regs
[10] = call_used_regs
[10] = 1;
17449 fixed_regs
[11] = call_used_regs
[11] = 1;
17450 fixed_regs
[12] = call_used_regs
[12] = 1;
17451 fixed_regs
[13] = call_used_regs
[13] = 1;
17452 fixed_regs
[14] = call_used_regs
[14] = 1;
17453 fixed_regs
[15] = call_used_regs
[15] = 1;
17456 /* Do not allow HI and LO to be treated as register operands.
17457 There are no MTHI or MTLO instructions (or any real need
17458 for them) and one-way registers cannot easily be reloaded. */
17459 AND_COMPL_HARD_REG_SET (operand_reg_set
,
17460 reg_class_contents
[(int) MD_REGS
]);
17462 /* $f20-$f23 are call-clobbered for n64. */
17463 if (mips_abi
== ABI_64
)
17466 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
17467 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17469 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17471 if (mips_abi
== ABI_N32
)
17474 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
17475 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17477 /* Make sure that double-register accumulator values are correctly
17478 ordered for the current endianness. */
17479 if (TARGET_LITTLE_ENDIAN
)
17481 unsigned int regno
;
17483 mips_swap_registers (MD_REG_FIRST
);
17484 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
17485 mips_swap_registers (regno
);
17489 /* Implement EH_USES. */
17492 mips_eh_uses (unsigned int regno
)
17494 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
17496 /* We need to force certain registers to be live in order to handle
17497 PIC long branches correctly. See mips_must_initialize_gp_p for
17499 if (mips_cfun_has_cprestore_slot_p ())
17501 if (regno
== CPRESTORE_SLOT_REGNUM
)
17506 if (cfun
->machine
->global_pointer
== regno
)
17514 /* Implement EPILOGUE_USES. */
17517 mips_epilogue_uses (unsigned int regno
)
17519 /* Say that the epilogue uses the return address register. Note that
17520 in the case of sibcalls, the values "used by the epilogue" are
17521 considered live at the start of the called function. */
17522 if (regno
== RETURN_ADDR_REGNUM
)
17525 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17526 See the comment above load_call<mode> for details. */
17527 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
17530 /* An interrupt handler must preserve some registers that are
17531 ordinarily call-clobbered. */
17532 if (cfun
->machine
->interrupt_handler_p
17533 && mips_interrupt_extra_call_saved_reg_p (regno
))
17539 /* Return true if INSN needs to be wrapped in ".set noat".
17540 INSN has NOPERANDS operands, stored in OPVEC. */
17543 mips_need_noat_wrapper_p (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
17545 if (recog_memoized (insn
) >= 0)
17547 subrtx_iterator::array_type array
;
17548 for (int i
= 0; i
< noperands
; i
++)
17549 FOR_EACH_SUBRTX (iter
, array
, opvec
[i
], NONCONST
)
17550 if (REG_P (*iter
) && REGNO (*iter
) == AT_REGNUM
)
17556 /* Implement FINAL_PRESCAN_INSN. */
17559 mips_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
17561 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17562 mips_push_asm_switch (&mips_noat
);
17565 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17568 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx_insn
*insn
,
17569 rtx
*opvec
, int noperands
)
17571 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17572 mips_pop_asm_switch (&mips_noat
);
17575 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17576 EXT_CODE is the code of the extension used. Return NULL if widening
17577 multiplication shouldn't be used. */
17580 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
17584 signed_p
= ext_code
== SIGN_EXTEND
;
17587 /* Don't use widening multiplication with MULT when we have DMUL. Even
17588 with the extension of its input operands DMUL is faster. Note that
17589 the extension is not needed for signed multiplication. In order to
17590 ensure that we always remove the redundant sign-extension in this
17591 case we still expand mulsidi3 for DMUL. */
17593 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
17596 ? gen_mulsidi3_64bit_mips16
17597 : gen_umulsidi3_64bit_mips16
);
17598 if (TARGET_FIX_R4000
)
17600 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
17606 ? gen_mulsidi3_32bit_mips16
17607 : gen_umulsidi3_32bit_mips16
);
17608 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
17609 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
17610 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
17614 /* Return true if PATTERN matches the kind of instruction generated by
17615 umips_build_save_restore. SAVE_P is true for store. */
17618 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
17622 HOST_WIDE_INT first_offset
= 0;
17623 rtx first_base
= 0;
17624 unsigned int regmask
= 0;
17626 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
17628 rtx set
, reg
, mem
, this_base
;
17629 HOST_WIDE_INT this_offset
;
17631 /* Check that we have a SET. */
17632 set
= XVECEXP (pattern
, 0, n
);
17633 if (GET_CODE (set
) != SET
)
17636 /* Check that the SET is a load (if restoring) or a store
17638 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17639 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
17642 /* Check that the address is the sum of base and a possibly-zero
17643 constant offset. Determine if the offset is in range. */
17644 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
17645 if (!REG_P (this_base
))
17650 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
17652 first_base
= this_base
;
17653 first_offset
= this_offset
;
17657 /* Check that the save slots are consecutive. */
17658 if (REGNO (this_base
) != REGNO (first_base
)
17659 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
17663 /* Check that SET's other operand is a register. */
17664 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
17668 regmask
|= 1 << REGNO (reg
);
17671 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
17672 if (regmask
== umips_swm_mask
[i
])
17678 /* Return the assembly instruction for microMIPS LWM or SWM.
17679 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17682 umips_output_save_restore (bool save_p
, rtx pattern
)
17684 static char buffer
[300];
17687 HOST_WIDE_INT offset
;
17688 rtx base
, mem
, set
, last_set
, last_reg
;
17690 /* Parse the pattern. */
17691 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
17693 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
17695 n
= XVECLEN (pattern
, 0);
17697 set
= XVECEXP (pattern
, 0, 0);
17698 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17699 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
17701 last_set
= XVECEXP (pattern
, 0, n
- 1);
17702 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
17704 if (REGNO (last_reg
) == 31)
17707 gcc_assert (n
<= 9);
17711 s
+= sprintf (s
, "%s,", reg_names
[16]);
17713 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
17715 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
17718 if (REGNO (last_reg
) == 31)
17719 s
+= sprintf (s
, "%s,", reg_names
[31]);
17721 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
17725 /* Return true if MEM1 and MEM2 use the same base register, and the
17726 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17727 register into (from) which the contents of MEM1 will be loaded
17728 (stored), depending on the value of LOAD_P.
17729 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17732 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
17733 rtx first_reg
, rtx mem1
, rtx mem2
)
17736 HOST_WIDE_INT offset1
, offset2
;
17738 if (!MEM_P (mem1
) || !MEM_P (mem2
))
17741 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
17742 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
17744 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
17747 /* Avoid invalid load pair instructions. */
17748 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
17751 /* We must avoid this case for anti-dependence.
17754 first_reg is $2, but the base is $3. */
17757 && REGNO (first_reg
) + 1 == REGNO (base1
))
17760 if (offset2
!= offset1
+ 4)
17763 if (!UMIPS_12BIT_OFFSET_P (offset1
))
17769 /* OPERANDS describes the operands to a pair of SETs, in the order
17770 dest1, src1, dest2, src2. Return true if the operands can be used
17771 in an LWP or SWP instruction; LOAD_P says which. */
17774 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
17776 rtx reg1
, reg2
, mem1
, mem2
;
17780 reg1
= operands
[0];
17781 reg2
= operands
[2];
17782 mem1
= operands
[1];
17783 mem2
= operands
[3];
17787 reg1
= operands
[1];
17788 reg2
= operands
[3];
17789 mem1
= operands
[0];
17790 mem2
= operands
[2];
17793 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17794 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
17796 if (REGNO (reg1
) == REGNO (reg2
) + 1)
17797 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
17802 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17803 the first register is REG and the first memory slot is MEM.
17804 LOAD_P is true for LWP. */
17807 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
17809 rtx ops
[] = {reg
, mem
};
17812 output_asm_insn ("lwp\t%0,%1", ops
);
17814 output_asm_insn ("swp\t%0,%1", ops
);
17817 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17818 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17821 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
17823 rtx reg1
, reg2
, mem1
, mem2
;
17826 reg1
= operands
[0];
17827 reg2
= operands
[2];
17828 mem1
= operands
[1];
17829 mem2
= operands
[3];
17833 reg1
= operands
[1];
17834 reg2
= operands
[3];
17835 mem1
= operands
[0];
17836 mem2
= operands
[2];
17839 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17841 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
17845 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
17846 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
17849 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17852 umips_movep_target_p (rtx reg1
, rtx reg2
)
17854 int regno1
, regno2
, pair
;
17856 static const int match
[8] = {
17857 0x00000060, /* 5, 6 */
17858 0x000000a0, /* 5, 7 */
17859 0x000000c0, /* 6, 7 */
17860 0x00200010, /* 4, 21 */
17861 0x00400010, /* 4, 22 */
17862 0x00000030, /* 4, 5 */
17863 0x00000050, /* 4, 6 */
17864 0x00000090 /* 4, 7 */
17867 if (!REG_P (reg1
) || !REG_P (reg2
))
17870 regno1
= REGNO (reg1
);
17871 regno2
= REGNO (reg2
);
17873 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
17876 pair
= (1 << regno1
) | (1 << regno2
);
17878 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
17879 if (pair
== match
[i
])
17885 /* Return the size in bytes of the trampoline code, padded to
17886 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17887 function address immediately follow. */
17890 mips_trampoline_code_size (void)
17892 if (TARGET_USE_PIC_FN_ADDR_REG
)
17894 else if (ptr_mode
== DImode
)
17896 else if (ISA_HAS_LOAD_DELAY
)
17902 /* Implement TARGET_TRAMPOLINE_INIT. */
17905 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
17907 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
17910 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
17912 /* Work out the offsets of the pointers from the start of the
17913 trampoline code. */
17914 end_addr_offset
= mips_trampoline_code_size ();
17915 static_chain_offset
= end_addr_offset
;
17916 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
17918 /* Get pointers to the beginning and end of the code block. */
17919 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
17920 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
17922 #define OP(X) gen_int_mode (X, SImode)
17924 /* Build up the code in TRAMPOLINE. */
17926 if (TARGET_USE_PIC_FN_ADDR_REG
)
17928 /* $25 contains the address of the trampoline. Emit code of the form:
17930 l[wd] $1, target_function_offset($25)
17931 l[wd] $static_chain, static_chain_offset($25)
17934 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
17935 target_function_offset
,
17936 PIC_FUNCTION_ADDR_REGNUM
));
17937 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17938 static_chain_offset
,
17939 PIC_FUNCTION_ADDR_REGNUM
));
17940 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
17941 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
17943 else if (ptr_mode
== DImode
)
17945 /* It's too cumbersome to create the full 64-bit address, so let's
17951 1: l[wd] $25, target_function_offset - 12($31)
17952 l[wd] $static_chain, static_chain_offset - 12($31)
17956 where 12 is the offset of "1:" from the start of the code block. */
17957 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
17958 trampoline
[i
++] = OP (MIPS_BAL (1));
17959 trampoline
[i
++] = OP (MIPS_NOP
);
17960 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
17961 target_function_offset
- 12,
17962 RETURN_ADDR_REGNUM
));
17963 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17964 static_chain_offset
- 12,
17965 RETURN_ADDR_REGNUM
));
17966 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17967 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
17971 /* If the target has load delays, emit:
17973 lui $1, %hi(end_addr)
17974 lw $25, %lo(end_addr + ...)($1)
17975 lw $static_chain, %lo(end_addr + ...)($1)
17981 lui $1, %hi(end_addr)
17982 lw $25, %lo(end_addr + ...)($1)
17984 lw $static_chain, %lo(end_addr + ...)($1). */
17986 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
17987 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
17988 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
17989 NULL
, false, OPTAB_WIDEN
);
17990 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
17991 NULL
, false, OPTAB_WIDEN
);
17992 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
17994 /* Emit the LUI. */
17995 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
17996 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
17997 NULL
, false, OPTAB_WIDEN
);
17999 /* Emit the load of the target function. */
18000 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
18001 target_function_offset
- end_addr_offset
,
18003 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
18004 NULL
, false, OPTAB_WIDEN
);
18006 /* Emit the JR here, if we can. */
18007 if (!ISA_HAS_LOAD_DELAY
)
18008 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18010 /* Emit the load of the static chain register. */
18011 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18012 static_chain_offset
- end_addr_offset
,
18014 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
18015 NULL
, false, OPTAB_WIDEN
);
18017 /* Emit the JR, if we couldn't above. */
18018 if (ISA_HAS_LOAD_DELAY
)
18020 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18021 trampoline
[i
++] = OP (MIPS_NOP
);
18027 /* Copy the trampoline code. Leave any padding uninitialized. */
18028 for (j
= 0; j
< i
; j
++)
18030 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
18031 mips_emit_move (mem
, trampoline
[j
]);
18034 /* Set up the static chain pointer field. */
18035 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
18036 mips_emit_move (mem
, chain_value
);
18038 /* Set up the target function field. */
18039 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
18040 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
18042 /* Flush the code part of the trampoline. */
18043 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
18044 emit_insn (gen_clear_cache (addr
, end_addr
));
18047 /* Implement FUNCTION_PROFILER. */
18049 void mips_function_profiler (FILE *file
)
18052 sorry ("mips16 function profiling");
18053 if (TARGET_LONG_CALLS
)
18055 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
18056 if (Pmode
== DImode
)
18057 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
18059 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
18061 mips_push_asm_switch (&mips_noat
);
18062 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
18063 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
18064 /* _mcount treats $2 as the static chain register. */
18065 if (cfun
->static_chain_decl
!= NULL
)
18066 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
18067 reg_names
[STATIC_CHAIN_REGNUM
]);
18068 if (TARGET_MCOUNT_RA_ADDRESS
)
18070 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
18071 ra save location. */
18072 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
18073 /* ra not saved, pass zero. */
18074 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
18076 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
18077 Pmode
== DImode
? "dla" : "la", reg_names
[12],
18078 cfun
->machine
->frame
.ra_fp_offset
,
18079 reg_names
[STACK_POINTER_REGNUM
]);
18081 if (!TARGET_NEWABI
)
18083 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
18084 TARGET_64BIT
? "dsubu" : "subu",
18085 reg_names
[STACK_POINTER_REGNUM
],
18086 reg_names
[STACK_POINTER_REGNUM
],
18087 Pmode
== DImode
? 16 : 8);
18089 if (TARGET_LONG_CALLS
)
18090 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
18092 fprintf (file
, "\tjal\t_mcount\n");
18093 mips_pop_asm_switch (&mips_noat
);
18094 /* _mcount treats $2 as the static chain register. */
18095 if (cfun
->static_chain_decl
!= NULL
)
18096 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
18100 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
18101 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
18102 when TARGET_LOONGSON_VECTORS is true. */
18104 static unsigned HOST_WIDE_INT
18105 mips_shift_truncation_mask (enum machine_mode mode
)
18107 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
18110 return GET_MODE_BITSIZE (mode
) - 1;
18113 /* Implement TARGET_PREPARE_PCH_SAVE. */
18116 mips_prepare_pch_save (void)
18118 /* We are called in a context where the current MIPS16 vs. non-MIPS16
18119 setting should be irrelevant. The question then is: which setting
18120 makes most sense at load time?
18122 The PCH is loaded before the first token is read. We should never
18123 have switched into MIPS16 mode by that point, and thus should not
18124 have populated mips16_globals. Nor can we load the entire contents
18125 of mips16_globals from the PCH file, because mips16_globals contains
18126 a combination of GGC and non-GGC data.
18128 There is therefore no point in trying save the GGC part of
18129 mips16_globals to the PCH file, or to preserve MIPS16ness across
18130 the PCH save and load. The loading compiler would not have access
18131 to the non-GGC parts of mips16_globals (either from the PCH file,
18132 or from a copy that the loading compiler generated itself) and would
18133 have to call target_reinit anyway.
18135 It therefore seems best to switch back to non-MIPS16 mode at
18136 save time, and to ensure that mips16_globals remains null after
18138 mips_set_compression_mode (0);
18139 mips16_globals
= 0;
18142 /* Generate or test for an insn that supports a constant permutation. */
18144 #define MAX_VECT_LEN 8
18146 struct expand_vec_perm_d
18148 rtx target
, op0
, op1
;
18149 unsigned char perm
[MAX_VECT_LEN
];
18150 enum machine_mode vmode
;
18151 unsigned char nelt
;
18156 /* Construct (set target (vec_select op0 (parallel perm))) and
18157 return true if that's a valid instruction in the active ISA. */
18160 mips_expand_vselect (rtx target
, rtx op0
,
18161 const unsigned char *perm
, unsigned nelt
)
18163 rtx rperm
[MAX_VECT_LEN
], x
;
18167 for (i
= 0; i
< nelt
; ++i
)
18168 rperm
[i
] = GEN_INT (perm
[i
]);
18170 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
18171 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
18172 x
= gen_rtx_SET (VOIDmode
, target
, x
);
18174 insn
= emit_insn (x
);
18175 if (recog_memoized (insn
) < 0)
18177 remove_insn (insn
);
18183 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18186 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
18187 const unsigned char *perm
, unsigned nelt
)
18189 enum machine_mode v2mode
;
18192 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
18193 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
18194 return mips_expand_vselect (target
, x
, perm
, nelt
);
18197 /* Recognize patterns for even-odd extraction. */
18200 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
18202 unsigned i
, odd
, nelt
= d
->nelt
;
18203 rtx t0
, t1
, t2
, t3
;
18205 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18207 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18214 for (i
= 1; i
< nelt
; ++i
)
18215 if (d
->perm
[i
] != i
* 2 + odd
)
18221 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18222 t0
= gen_reg_rtx (d
->vmode
);
18223 t1
= gen_reg_rtx (d
->vmode
);
18227 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
18228 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
18230 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
18232 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
18236 t2
= gen_reg_rtx (d
->vmode
);
18237 t3
= gen_reg_rtx (d
->vmode
);
18238 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
18239 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
18240 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
18241 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
18243 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
18245 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
18249 gcc_unreachable ();
18254 /* Recognize patterns for the Loongson PSHUFH instruction. */
18257 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
18262 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18264 if (d
->vmode
!= V4HImode
)
18269 /* Convert the selector into the packed 8-bit form for pshufh. */
18270 /* Recall that loongson is little-endian only. No big-endian
18271 adjustment required. */
18272 for (i
= mask
= 0; i
< 4; i
++)
18273 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
18274 rmask
= force_reg (SImode
, GEN_INT (mask
));
18276 if (d
->one_vector_p
)
18277 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
18280 rtx t0
, t1
, x
, merge
, rmerge
[4];
18282 t0
= gen_reg_rtx (V4HImode
);
18283 t1
= gen_reg_rtx (V4HImode
);
18284 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
18285 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
18287 for (i
= 0; i
< 4; ++i
)
18288 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
18289 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
18290 merge
= force_reg (V4HImode
, merge
);
18292 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
18293 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18295 x
= gen_rtx_NOT (V4HImode
, merge
);
18296 x
= gen_rtx_AND (V4HImode
, x
, t0
);
18297 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18299 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
18300 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
18306 /* Recognize broadcast patterns for the Loongson. */
18309 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
18314 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18316 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18317 if (d
->vmode
!= V8QImode
)
18319 if (!d
->one_vector_p
)
18323 for (i
= 1; i
< 8; ++i
)
18324 if (d
->perm
[i
] != elt
)
18330 /* With one interleave we put two of the desired element adjacent. */
18331 t0
= gen_reg_rtx (V8QImode
);
18333 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
18335 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
18337 /* Shuffle that one HImode element into all locations. */
18340 t1
= gen_reg_rtx (V4HImode
);
18341 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
18342 force_reg (SImode
, GEN_INT (elt
))));
18344 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
18349 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
18351 unsigned int i
, nelt
= d
->nelt
;
18352 unsigned char perm2
[MAX_VECT_LEN
];
18354 if (d
->one_vector_p
)
18356 /* Try interleave with alternating operands. */
18357 memcpy (perm2
, d
->perm
, sizeof(perm2
));
18358 for (i
= 1; i
< nelt
; i
+= 2)
18360 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
18365 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
18369 /* Try again with swapped operands. */
18370 for (i
= 0; i
< nelt
; ++i
)
18371 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
18372 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
18376 if (mips_expand_vpc_loongson_even_odd (d
))
18378 if (mips_expand_vpc_loongson_pshufh (d
))
18380 if (mips_expand_vpc_loongson_bcast (d
))
18385 /* Expand a vec_perm_const pattern. */
18388 mips_expand_vec_perm_const (rtx operands
[4])
18390 struct expand_vec_perm_d d
;
18391 int i
, nelt
, which
;
18392 unsigned char orig_perm
[MAX_VECT_LEN
];
18396 d
.target
= operands
[0];
18397 d
.op0
= operands
[1];
18398 d
.op1
= operands
[2];
18401 d
.vmode
= GET_MODE (d
.target
);
18402 gcc_assert (VECTOR_MODE_P (d
.vmode
));
18403 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18404 d
.testing_p
= false;
18406 for (i
= which
= 0; i
< nelt
; ++i
)
18408 rtx e
= XVECEXP (sel
, 0, i
);
18409 int ei
= INTVAL (e
) & (2 * nelt
- 1);
18410 which
|= (ei
< nelt
? 1 : 2);
18413 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18421 d
.one_vector_p
= false;
18422 if (!rtx_equal_p (d
.op0
, d
.op1
))
18427 for (i
= 0; i
< nelt
; ++i
)
18428 d
.perm
[i
] &= nelt
- 1;
18430 d
.one_vector_p
= true;
18435 d
.one_vector_p
= true;
18439 ok
= mips_expand_vec_perm_const_1 (&d
);
18441 /* If we were given a two-vector permutation which just happened to
18442 have both input vectors equal, we folded this into a one-vector
18443 permutation. There are several loongson patterns that are matched
18444 via direct vec_select+vec_concat expansion, but we do not have
18445 support in mips_expand_vec_perm_const_1 to guess the adjustment
18446 that should be made for a single operand. Just try again with
18447 the original permutation. */
18448 if (!ok
&& which
== 3)
18450 d
.op0
= operands
[1];
18451 d
.op1
= operands
[2];
18452 d
.one_vector_p
= false;
18453 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18454 ok
= mips_expand_vec_perm_const_1 (&d
);
18460 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18463 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
18464 const unsigned char *sel
)
18466 struct expand_vec_perm_d d
;
18467 unsigned int i
, nelt
, which
;
18471 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18472 d
.testing_p
= true;
18473 memcpy (d
.perm
, sel
, nelt
);
18475 /* Categorize the set of elements in the selector. */
18476 for (i
= which
= 0; i
< nelt
; ++i
)
18478 unsigned char e
= d
.perm
[i
];
18479 gcc_assert (e
< 2 * nelt
);
18480 which
|= (e
< nelt
? 1 : 2);
18483 /* For all elements from second vector, fold the elements to first. */
18485 for (i
= 0; i
< nelt
; ++i
)
18488 /* Check whether the mask can be applied to the vector type. */
18489 d
.one_vector_p
= (which
!= 3);
18491 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
18492 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
18493 if (!d
.one_vector_p
)
18494 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
18497 ret
= mips_expand_vec_perm_const_1 (&d
);
18503 /* Expand an integral vector unpack operation. */
18506 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
18508 enum machine_mode imode
= GET_MODE (operands
[1]);
18509 rtx (*unpack
) (rtx
, rtx
, rtx
);
18510 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
18511 rtx tmp
, dest
, zero
;
18517 unpack
= gen_loongson_punpckhbh
;
18519 unpack
= gen_loongson_punpcklbh
;
18520 cmpgt
= gen_loongson_pcmpgtb
;
18524 unpack
= gen_loongson_punpckhhw
;
18526 unpack
= gen_loongson_punpcklhw
;
18527 cmpgt
= gen_loongson_pcmpgth
;
18530 gcc_unreachable ();
18533 zero
= force_reg (imode
, CONST0_RTX (imode
));
18538 tmp
= gen_reg_rtx (imode
);
18539 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
18542 dest
= gen_reg_rtx (imode
);
18543 emit_insn (unpack (dest
, operands
[1], tmp
));
18545 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
18548 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18551 mips_constant_elt_p (rtx x
)
18553 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
18556 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18559 mips_expand_vi_broadcast (enum machine_mode vmode
, rtx target
, rtx elt
)
18561 struct expand_vec_perm_d d
;
18565 if (elt
!= const0_rtx
)
18566 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
18568 elt
= gen_lowpart (DImode
, elt
);
18570 t1
= gen_reg_rtx (vmode
);
18574 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
18577 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
18580 gcc_unreachable ();
18583 memset (&d
, 0, sizeof (d
));
18588 d
.nelt
= GET_MODE_NUNITS (vmode
);
18589 d
.one_vector_p
= true;
18591 ok
= mips_expand_vec_perm_const_1 (&d
);
18595 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18596 elements of VALS with zeros, copy the constant vector to TARGET. */
18599 mips_expand_vi_constant (enum machine_mode vmode
, unsigned nelt
,
18600 rtx target
, rtx vals
)
18602 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
18605 for (i
= 0; i
< nelt
; ++i
)
18607 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
18608 RTVEC_ELT (vec
, i
) = const0_rtx
;
18611 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
18615 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18618 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
18620 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
18622 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
18623 GEN_INT (one_var
)));
18626 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18629 mips_expand_vi_general (enum machine_mode vmode
, enum machine_mode imode
,
18630 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
18632 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
18633 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
18636 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
18638 for (i
= 0; i
< nelt
; ++i
)
18640 rtx x
= XVECEXP (vals
, 0, i
);
18641 if (!mips_constant_elt_p (x
))
18642 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
18645 emit_move_insn (target
, mem
);
18648 /* Expand a vector initialization. */
18651 mips_expand_vector_init (rtx target
, rtx vals
)
18653 enum machine_mode vmode
= GET_MODE (target
);
18654 enum machine_mode imode
= GET_MODE_INNER (vmode
);
18655 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
18656 unsigned nvar
= 0, one_var
= -1u;
18657 bool all_same
= true;
18660 for (i
= 0; i
< nelt
; ++i
)
18662 x
= XVECEXP (vals
, 0, i
);
18663 if (!mips_constant_elt_p (x
))
18664 nvar
++, one_var
= i
;
18665 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
18669 /* Load constants from the pool, or whatever's handy. */
18672 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
18676 /* For two-part initialization, always use CONCAT. */
18679 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
18680 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
18681 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
18682 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18686 /* Loongson is the only cpu with vectors with more elements. */
18687 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
18689 /* If all values are identical, broadcast the value. */
18692 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
18696 /* If we've only got one non-variable V4HImode, use PINSRH. */
18697 if (nvar
== 1 && vmode
== V4HImode
)
18699 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
18703 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
18706 /* Expand a vector reduction. */
18709 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
18711 enum machine_mode vmode
= GET_MODE (in
);
18712 unsigned char perm2
[2];
18713 rtx last
, next
, fold
, x
;
18717 fold
= gen_reg_rtx (vmode
);
18721 /* Use PUL/PLU to produce { L, H } op { H, L }.
18722 By reversing the pair order, rather than a pure interleave high,
18723 we avoid erroneous exceptional conditions that we might otherwise
18724 produce from the computation of H op H. */
18727 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
18732 /* Use interleave to produce { H, L } op { H, H }. */
18733 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
18737 /* Perform the first reduction with interleave,
18738 and subsequent reductions with shifts. */
18739 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
18741 next
= gen_reg_rtx (vmode
);
18742 emit_insn (gen (next
, last
, fold
));
18745 fold
= gen_reg_rtx (vmode
);
18746 x
= force_reg (SImode
, GEN_INT (16));
18747 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
18751 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
18753 next
= gen_reg_rtx (vmode
);
18754 emit_insn (gen (next
, last
, fold
));
18757 fold
= gen_reg_rtx (vmode
);
18758 x
= force_reg (SImode
, GEN_INT (16));
18759 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18761 next
= gen_reg_rtx (vmode
);
18762 emit_insn (gen (next
, last
, fold
));
18765 fold
= gen_reg_rtx (vmode
);
18766 x
= force_reg (SImode
, GEN_INT (8));
18767 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18771 gcc_unreachable ();
18774 emit_insn (gen (target
, last
, fold
));
18777 /* Expand a vector minimum/maximum. */
18780 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
18781 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
18783 enum machine_mode vmode
= GET_MODE (target
);
18786 tc
= gen_reg_rtx (vmode
);
18787 t0
= gen_reg_rtx (vmode
);
18788 t1
= gen_reg_rtx (vmode
);
18791 emit_insn (cmp (tc
, op0
, op1
));
18793 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
18794 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18796 x
= gen_rtx_NOT (vmode
, tc
);
18797 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
18798 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18800 x
= gen_rtx_IOR (vmode
, t0
, t1
);
18801 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18804 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
18807 mips_case_values_threshold (void)
18809 /* In MIPS16 mode using a larger case threshold generates smaller code. */
18810 if (TARGET_MIPS16
&& optimize_size
)
18813 return default_case_values_threshold ();
18816 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
18819 mips_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
18821 if (!TARGET_HARD_FLOAT_ABI
)
18823 tree exceptions_var
= create_tmp_var (MIPS_ATYPE_USI
, NULL
);
18824 tree fcsr_orig_var
= create_tmp_var (MIPS_ATYPE_USI
, NULL
);
18825 tree fcsr_mod_var
= create_tmp_var (MIPS_ATYPE_USI
, NULL
);
18826 tree get_fcsr
= mips_builtin_decls
[MIPS_GET_FCSR
];
18827 tree set_fcsr
= mips_builtin_decls
[MIPS_SET_FCSR
];
18828 tree get_fcsr_hold_call
= build_call_expr (get_fcsr
, 0);
18829 tree hold_assign_orig
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
18830 fcsr_orig_var
, get_fcsr_hold_call
);
18831 tree hold_mod_val
= build2 (BIT_AND_EXPR
, MIPS_ATYPE_USI
, fcsr_orig_var
,
18832 build_int_cst (MIPS_ATYPE_USI
, 0xfffff003));
18833 tree hold_assign_mod
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
18834 fcsr_mod_var
, hold_mod_val
);
18835 tree set_fcsr_hold_call
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
18836 tree hold_all
= build2 (COMPOUND_EXPR
, MIPS_ATYPE_USI
,
18837 hold_assign_orig
, hold_assign_mod
);
18838 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_all
,
18839 set_fcsr_hold_call
);
18841 *clear
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
18843 tree get_fcsr_update_call
= build_call_expr (get_fcsr
, 0);
18844 *update
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
18845 exceptions_var
, get_fcsr_update_call
);
18846 tree set_fcsr_update_call
= build_call_expr (set_fcsr
, 1, fcsr_orig_var
);
18847 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
18848 set_fcsr_update_call
);
18849 tree atomic_feraiseexcept
18850 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
18851 tree int_exceptions_var
= fold_convert (integer_type_node
,
18853 tree atomic_feraiseexcept_call
= build_call_expr (atomic_feraiseexcept
,
18854 1, int_exceptions_var
);
18855 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
18856 atomic_feraiseexcept_call
);
18859 /* Implement TARGET_SPILL_CLASS. */
18862 mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED
,
18863 enum machine_mode mode ATTRIBUTE_UNUSED
)
18870 /* Implement TARGET_LRA_P. */
18875 return mips_lra_flag
;
18878 /* Initialize the GCC target structure. */
18879 #undef TARGET_ASM_ALIGNED_HI_OP
18880 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18881 #undef TARGET_ASM_ALIGNED_SI_OP
18882 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18883 #undef TARGET_ASM_ALIGNED_DI_OP
18884 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18886 #undef TARGET_OPTION_OVERRIDE
18887 #define TARGET_OPTION_OVERRIDE mips_option_override
18889 #undef TARGET_LEGITIMIZE_ADDRESS
18890 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18892 #undef TARGET_ASM_FUNCTION_PROLOGUE
18893 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18894 #undef TARGET_ASM_FUNCTION_EPILOGUE
18895 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18896 #undef TARGET_ASM_SELECT_RTX_SECTION
18897 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18898 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18899 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18901 #undef TARGET_SCHED_INIT
18902 #define TARGET_SCHED_INIT mips_sched_init
18903 #undef TARGET_SCHED_REORDER
18904 #define TARGET_SCHED_REORDER mips_sched_reorder
18905 #undef TARGET_SCHED_REORDER2
18906 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18907 #undef TARGET_SCHED_VARIABLE_ISSUE
18908 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18909 #undef TARGET_SCHED_ADJUST_COST
18910 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18911 #undef TARGET_SCHED_ISSUE_RATE
18912 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18913 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18914 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18915 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18916 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18917 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18918 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18919 mips_multipass_dfa_lookahead
18920 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18921 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18922 mips_small_register_classes_for_mode_p
18924 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18925 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18927 #undef TARGET_INSERT_ATTRIBUTES
18928 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18929 #undef TARGET_MERGE_DECL_ATTRIBUTES
18930 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18931 #undef TARGET_CAN_INLINE_P
18932 #define TARGET_CAN_INLINE_P mips_can_inline_p
18933 #undef TARGET_SET_CURRENT_FUNCTION
18934 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18936 #undef TARGET_VALID_POINTER_MODE
18937 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18938 #undef TARGET_REGISTER_MOVE_COST
18939 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18940 #undef TARGET_REGISTER_PRIORITY
18941 #define TARGET_REGISTER_PRIORITY mips_register_priority
18942 #undef TARGET_MEMORY_MOVE_COST
18943 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18944 #undef TARGET_RTX_COSTS
18945 #define TARGET_RTX_COSTS mips_rtx_costs
18946 #undef TARGET_ADDRESS_COST
18947 #define TARGET_ADDRESS_COST mips_address_cost
18949 #undef TARGET_IN_SMALL_DATA_P
18950 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18952 #undef TARGET_MACHINE_DEPENDENT_REORG
18953 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18955 #undef TARGET_PREFERRED_RELOAD_CLASS
18956 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18958 #undef TARGET_EXPAND_TO_RTL_HOOK
18959 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18960 #undef TARGET_ASM_FILE_START
18961 #define TARGET_ASM_FILE_START mips_file_start
18962 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18963 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18964 #undef TARGET_ASM_CODE_END
18965 #define TARGET_ASM_CODE_END mips_code_end
18967 #undef TARGET_INIT_LIBFUNCS
18968 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18970 #undef TARGET_BUILD_BUILTIN_VA_LIST
18971 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18972 #undef TARGET_EXPAND_BUILTIN_VA_START
18973 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18974 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18975 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18977 #undef TARGET_PROMOTE_FUNCTION_MODE
18978 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
18979 #undef TARGET_PROMOTE_PROTOTYPES
18980 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18982 #undef TARGET_FUNCTION_VALUE
18983 #define TARGET_FUNCTION_VALUE mips_function_value
18984 #undef TARGET_LIBCALL_VALUE
18985 #define TARGET_LIBCALL_VALUE mips_libcall_value
18986 #undef TARGET_FUNCTION_VALUE_REGNO_P
18987 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
18988 #undef TARGET_RETURN_IN_MEMORY
18989 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
18990 #undef TARGET_RETURN_IN_MSB
18991 #define TARGET_RETURN_IN_MSB mips_return_in_msb
18993 #undef TARGET_ASM_OUTPUT_MI_THUNK
18994 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
18995 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
18996 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
18998 #undef TARGET_PRINT_OPERAND
18999 #define TARGET_PRINT_OPERAND mips_print_operand
19000 #undef TARGET_PRINT_OPERAND_ADDRESS
19001 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
19002 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
19003 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
19005 #undef TARGET_SETUP_INCOMING_VARARGS
19006 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
19007 #undef TARGET_STRICT_ARGUMENT_NAMING
19008 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
19009 #undef TARGET_MUST_PASS_IN_STACK
19010 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
19011 #undef TARGET_PASS_BY_REFERENCE
19012 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
19013 #undef TARGET_CALLEE_COPIES
19014 #define TARGET_CALLEE_COPIES mips_callee_copies
19015 #undef TARGET_ARG_PARTIAL_BYTES
19016 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
19017 #undef TARGET_FUNCTION_ARG
19018 #define TARGET_FUNCTION_ARG mips_function_arg
19019 #undef TARGET_FUNCTION_ARG_ADVANCE
19020 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
19021 #undef TARGET_FUNCTION_ARG_BOUNDARY
19022 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
19024 #undef TARGET_MODE_REP_EXTENDED
19025 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
19027 #undef TARGET_VECTOR_MODE_SUPPORTED_P
19028 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
19030 #undef TARGET_SCALAR_MODE_SUPPORTED_P
19031 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
19033 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
19034 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
19036 #undef TARGET_INIT_BUILTINS
19037 #define TARGET_INIT_BUILTINS mips_init_builtins
19038 #undef TARGET_BUILTIN_DECL
19039 #define TARGET_BUILTIN_DECL mips_builtin_decl
19040 #undef TARGET_EXPAND_BUILTIN
19041 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
19043 #undef TARGET_HAVE_TLS
19044 #define TARGET_HAVE_TLS HAVE_AS_TLS
19046 #undef TARGET_CANNOT_FORCE_CONST_MEM
19047 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
19049 #undef TARGET_LEGITIMATE_CONSTANT_P
19050 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
19052 #undef TARGET_ENCODE_SECTION_INFO
19053 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
19055 #undef TARGET_ATTRIBUTE_TABLE
19056 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
19057 /* All our function attributes are related to how out-of-line copies should
19058 be compiled or called. They don't in themselves prevent inlining. */
19059 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
19060 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
19062 #undef TARGET_EXTRA_LIVE_ON_ENTRY
19063 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
19065 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
19066 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
19067 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
19068 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
19070 #undef TARGET_COMP_TYPE_ATTRIBUTES
19071 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
19073 #ifdef HAVE_AS_DTPRELWORD
19074 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
19075 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
19077 #undef TARGET_DWARF_REGISTER_SPAN
19078 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
19080 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
19081 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
19083 #undef TARGET_LEGITIMATE_ADDRESS_P
19084 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
19086 #undef TARGET_FRAME_POINTER_REQUIRED
19087 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
19089 #undef TARGET_CAN_ELIMINATE
19090 #define TARGET_CAN_ELIMINATE mips_can_eliminate
19092 #undef TARGET_CONDITIONAL_REGISTER_USAGE
19093 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
19095 #undef TARGET_TRAMPOLINE_INIT
19096 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
19098 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
19099 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
19101 #undef TARGET_SHIFT_TRUNCATION_MASK
19102 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
19104 #undef TARGET_PREPARE_PCH_SAVE
19105 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
19107 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
19108 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
19110 #undef TARGET_CASE_VALUES_THRESHOLD
19111 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
19113 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
19114 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
19116 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
19117 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
19119 #undef TARGET_SPILL_CLASS
19120 #define TARGET_SPILL_CLASS mips_spill_class
19121 #undef TARGET_LRA_P
19122 #define TARGET_LRA_P mips_lra_p
19124 struct gcc_target targetm
= TARGET_INITIALIZER
;
19126 #include "gt-mips.h"