1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "stringpool.h"
39 #include "stor-layout.h"
50 #include "hash-table.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
56 #include "sched-int.h"
57 #include "pointer-set.h"
59 #include "basic-block.h"
60 #include "tree-ssa-alias.h"
61 #include "internal-fn.h"
62 #include "gimple-fold.h"
64 #include "gimple-expr.h"
69 #include "diagnostic.h"
70 #include "target-globals.h"
72 #include "tree-pass.h"
75 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
76 #define UNSPEC_ADDRESS_P(X) \
77 (GET_CODE (X) == UNSPEC \
78 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
79 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
81 /* Extract the symbol or label from UNSPEC wrapper X. */
82 #define UNSPEC_ADDRESS(X) \
85 /* Extract the symbol type from UNSPEC wrapper X. */
86 #define UNSPEC_ADDRESS_TYPE(X) \
87 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
89 /* The maximum distance between the top of the stack frame and the
90 value $sp has when we save and restore registers.
92 The value for normal-mode code must be a SMALL_OPERAND and must
93 preserve the maximum stack alignment. We therefore use a value
94 of 0x7ff0 in this case.
96 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
97 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
99 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
100 up to 0x7f8 bytes and can usually save or restore all the registers
101 that we need to save or restore. (Note that we can only use these
102 instructions for o32, for which the stack alignment is 8 bytes.)
104 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
105 RESTORE are not available. We can then use unextended instructions
106 to save and restore registers, and to allocate and deallocate the top
107 part of the frame. */
108 #define MIPS_MAX_FIRST_STACK_STEP \
109 (!TARGET_COMPRESSION ? 0x7ff0 \
110 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
111 : TARGET_64BIT ? 0x100 : 0x400)
113 /* True if INSN is a mips.md pattern or asm statement. */
114 /* ??? This test exists through the compiler, perhaps it should be
116 #define USEFUL_INSN_P(INSN) \
117 (NONDEBUG_INSN_P (INSN) \
118 && GET_CODE (PATTERN (INSN)) != USE \
119 && GET_CODE (PATTERN (INSN)) != CLOBBER)
121 /* If INSN is a delayed branch sequence, return the first instruction
122 in the sequence, otherwise return INSN itself. */
123 #define SEQ_BEGIN(INSN) \
124 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
125 ? XVECEXP (PATTERN (INSN), 0, 0) \
128 /* Likewise for the last instruction in a delayed branch sequence. */
129 #define SEQ_END(INSN) \
130 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
131 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
134 /* Execute the following loop body with SUBINSN set to each instruction
135 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
136 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
137 for ((SUBINSN) = SEQ_BEGIN (INSN); \
138 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
139 (SUBINSN) = NEXT_INSN (SUBINSN))
141 /* True if bit BIT is set in VALUE. */
142 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
144 /* Return the opcode for a ptr_mode load of the form:
146 l[wd] DEST, OFFSET(BASE). */
147 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
148 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
153 /* Return the opcode to move register SRC into register DEST. */
154 #define MIPS_MOVE(DEST, SRC) \
155 ((TARGET_64BIT ? 0x2d : 0x21) \
159 /* Return the opcode for:
162 #define MIPS_LUI(DEST, VALUE) \
163 ((0xf << 26) | ((DEST) << 16) | (VALUE))
165 /* Return the opcode to jump to register DEST. */
166 #define MIPS_JR(DEST) \
167 (((DEST) << 21) | 0x8)
169 /* Return the opcode for:
171 bal . + (1 + OFFSET) * 4. */
172 #define MIPS_BAL(OFFSET) \
173 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
175 /* Return the usual opcode for a nop. */
178 /* Classifies an address.
181 A natural register + offset address. The register satisfies
182 mips_valid_base_register_p and the offset is a const_arith_operand.
185 A LO_SUM rtx. The first operand is a valid base register and
186 the second operand is a symbolic address.
189 A signed 16-bit constant address.
192 A constant symbolic address. */
193 enum mips_address_type
{
200 /* Macros to create an enumeration identifier for a function prototype. */
201 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
202 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
203 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
204 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
206 /* Classifies the prototype of a built-in function. */
207 enum mips_function_type
{
208 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
209 #include "config/mips/mips-ftypes.def"
210 #undef DEF_MIPS_FTYPE
214 /* Specifies how a built-in function should be converted into rtl. */
215 enum mips_builtin_type
{
216 /* The function corresponds directly to an .md pattern. The return
217 value is mapped to operand 0 and the arguments are mapped to
218 operands 1 and above. */
221 /* The function corresponds directly to an .md pattern. There is no return
222 value and the arguments are mapped to operands 0 and above. */
223 MIPS_BUILTIN_DIRECT_NO_TARGET
,
225 /* The function corresponds to a comparison instruction followed by
226 a mips_cond_move_tf_ps pattern. The first two arguments are the
227 values to compare and the second two arguments are the vector
228 operands for the movt.ps or movf.ps instruction (in assembly order). */
232 /* The function corresponds to a V2SF comparison instruction. Operand 0
233 of this instruction is the result of the comparison, which has mode
234 CCV2 or CCV4. The function arguments are mapped to operands 1 and
235 above. The function's return value is an SImode boolean that is
236 true under the following conditions:
238 MIPS_BUILTIN_CMP_ANY: one of the registers is true
239 MIPS_BUILTIN_CMP_ALL: all of the registers are true
240 MIPS_BUILTIN_CMP_LOWER: the first register is true
241 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
242 MIPS_BUILTIN_CMP_ANY
,
243 MIPS_BUILTIN_CMP_ALL
,
244 MIPS_BUILTIN_CMP_UPPER
,
245 MIPS_BUILTIN_CMP_LOWER
,
247 /* As above, but the instruction only sets a single $fcc register. */
248 MIPS_BUILTIN_CMP_SINGLE
,
250 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
251 MIPS_BUILTIN_BPOSGE32
254 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
255 #define MIPS_FP_CONDITIONS(MACRO) \
273 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
274 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
275 enum mips_fp_condition
{
276 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
278 #undef DECLARE_MIPS_COND
280 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
281 #define STRINGIFY(X) #X
282 static const char *const mips_fp_conditions
[] = {
283 MIPS_FP_CONDITIONS (STRINGIFY
)
287 /* A class used to control a comdat-style stub that we output in each
288 translation unit that needs it. */
289 class mips_one_only_stub
{
291 virtual ~mips_one_only_stub () {}
293 /* Return the name of the stub. */
294 virtual const char *get_name () = 0;
296 /* Output the body of the function to asm_out_file. */
297 virtual void output_body () = 0;
300 /* Tuning information that is automatically derived from other sources
301 (such as the scheduler). */
303 /* The architecture and tuning settings that this structure describes. */
307 /* True if this structure describes MIPS16 settings. */
310 /* True if the structure has been initialized. */
313 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
314 when optimizing for speed. */
315 bool fast_mult_zero_zero_p
;
318 /* Information about a function's frame layout. */
319 struct GTY(()) mips_frame_info
{
320 /* The size of the frame in bytes. */
321 HOST_WIDE_INT total_size
;
323 /* The number of bytes allocated to variables. */
324 HOST_WIDE_INT var_size
;
326 /* The number of bytes allocated to outgoing function arguments. */
327 HOST_WIDE_INT args_size
;
329 /* The number of bytes allocated to the .cprestore slot, or 0 if there
331 HOST_WIDE_INT cprestore_size
;
333 /* Bit X is set if the function saves or restores GPR X. */
336 /* Likewise FPR X. */
339 /* Likewise doubleword accumulator X ($acX). */
340 unsigned int acc_mask
;
342 /* The number of GPRs, FPRs, doubleword accumulators and COP0
346 unsigned int num_acc
;
347 unsigned int num_cop0_regs
;
349 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
350 save slots from the top of the frame, or zero if no such slots are
352 HOST_WIDE_INT gp_save_offset
;
353 HOST_WIDE_INT fp_save_offset
;
354 HOST_WIDE_INT acc_save_offset
;
355 HOST_WIDE_INT cop0_save_offset
;
357 /* Likewise, but giving offsets from the bottom of the frame. */
358 HOST_WIDE_INT gp_sp_offset
;
359 HOST_WIDE_INT fp_sp_offset
;
360 HOST_WIDE_INT acc_sp_offset
;
361 HOST_WIDE_INT cop0_sp_offset
;
363 /* Similar, but the value passed to _mcount. */
364 HOST_WIDE_INT ra_fp_offset
;
366 /* The offset of arg_pointer_rtx from the bottom of the frame. */
367 HOST_WIDE_INT arg_pointer_offset
;
369 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
370 HOST_WIDE_INT hard_frame_pointer_offset
;
373 struct GTY(()) machine_function
{
374 /* The next floating-point condition-code register to allocate
375 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
376 unsigned int next_fcc
;
378 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
379 rtx mips16_gp_pseudo_rtx
;
381 /* The number of extra stack bytes taken up by register varargs.
382 This area is allocated by the callee at the very top of the frame. */
385 /* The current frame information, calculated by mips_compute_frame_info. */
386 struct mips_frame_info frame
;
388 /* The register to use as the function's global pointer, or INVALID_REGNUM
389 if the function doesn't need one. */
390 unsigned int global_pointer
;
392 /* How many instructions it takes to load a label into $AT, or 0 if
393 this property hasn't yet been calculated. */
394 unsigned int load_label_num_insns
;
396 /* True if mips_adjust_insn_length should ignore an instruction's
398 bool ignore_hazard_length_p
;
400 /* True if the whole function is suitable for .set noreorder and
402 bool all_noreorder_p
;
404 /* True if the function has "inflexible" and "flexible" references
405 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
406 and mips_cfun_has_flexible_gp_ref_p for details. */
407 bool has_inflexible_gp_insn_p
;
408 bool has_flexible_gp_insn_p
;
410 /* True if the function's prologue must load the global pointer
411 value into pic_offset_table_rtx and store the same value in
412 the function's cprestore slot (if any). Even if this value
413 is currently false, we may decide to set it to true later;
414 see mips_must_initialize_gp_p () for details. */
415 bool must_initialize_gp_p
;
417 /* True if the current function must restore $gp after any potential
418 clobber. This value is only meaningful during the first post-epilogue
419 split_insns pass; see mips_must_initialize_gp_p () for details. */
420 bool must_restore_gp_when_clobbered_p
;
422 /* True if this is an interrupt handler. */
423 bool interrupt_handler_p
;
425 /* True if this is an interrupt handler that uses shadow registers. */
426 bool use_shadow_register_set_p
;
428 /* True if this is an interrupt handler that should keep interrupts
430 bool keep_interrupts_masked_p
;
432 /* True if this is an interrupt handler that should use DERET
434 bool use_debug_exception_return_p
;
437 /* Information about a single argument. */
438 struct mips_arg_info
{
439 /* True if the argument is passed in a floating-point register, or
440 would have been if we hadn't run out of registers. */
443 /* The number of words passed in registers, rounded up. */
444 unsigned int reg_words
;
446 /* For EABI, the offset of the first register from GP_ARG_FIRST or
447 FP_ARG_FIRST. For other ABIs, the offset of the first register from
448 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
449 comment for details).
451 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
453 unsigned int reg_offset
;
455 /* The number of words that must be passed on the stack, rounded up. */
456 unsigned int stack_words
;
458 /* The offset from the start of the stack overflow area of the argument's
459 first stack word. Only meaningful when STACK_WORDS is nonzero. */
460 unsigned int stack_offset
;
463 /* Information about an address described by mips_address_type.
469 REG is the base register and OFFSET is the constant offset.
472 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
473 is the type of symbol it references.
476 SYMBOL_TYPE is the type of symbol that the address references. */
477 struct mips_address_info
{
478 enum mips_address_type type
;
481 enum mips_symbol_type symbol_type
;
484 /* One stage in a constant building sequence. These sequences have
488 A = A CODE[1] VALUE[1]
489 A = A CODE[2] VALUE[2]
492 where A is an accumulator, each CODE[i] is a binary rtl operation
493 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
494 struct mips_integer_op
{
496 unsigned HOST_WIDE_INT value
;
499 /* The largest number of operations needed to load an integer constant.
500 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
501 When the lowest bit is clear, we can try, but reject a sequence with
502 an extra SLL at the end. */
503 #define MIPS_MAX_INTEGER_OPS 7
505 /* Information about a MIPS16e SAVE or RESTORE instruction. */
506 struct mips16e_save_restore_info
{
507 /* The number of argument registers saved by a SAVE instruction.
508 0 for RESTORE instructions. */
511 /* Bit X is set if the instruction saves or restores GPR X. */
514 /* The total number of bytes to allocate. */
518 /* Costs of various operations on the different architectures. */
520 struct mips_rtx_cost_data
522 unsigned short fp_add
;
523 unsigned short fp_mult_sf
;
524 unsigned short fp_mult_df
;
525 unsigned short fp_div_sf
;
526 unsigned short fp_div_df
;
527 unsigned short int_mult_si
;
528 unsigned short int_mult_di
;
529 unsigned short int_div_si
;
530 unsigned short int_div_di
;
531 unsigned short branch_cost
;
532 unsigned short memory_latency
;
535 /* Global variables for machine-dependent things. */
537 /* The -G setting, or the configuration's default small-data limit if
538 no -G option is given. */
539 static unsigned int mips_small_data_threshold
;
541 /* The number of file directives written by mips_output_filename. */
542 int num_source_filenames
;
544 /* The name that appeared in the last .file directive written by
545 mips_output_filename, or "" if mips_output_filename hasn't
546 written anything yet. */
547 const char *current_function_file
= "";
549 /* Arrays that map GCC register numbers to debugger register numbers. */
550 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
551 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
553 /* Information about the current function's epilogue, used only while
556 /* A list of queued REG_CFA_RESTORE notes. */
559 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
561 HOST_WIDE_INT cfa_offset
;
563 /* The offset of the CFA from the stack pointer while restoring
565 HOST_WIDE_INT cfa_restore_sp_offset
;
568 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
569 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
570 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
571 struct mips_asm_switch mips_noat
= { "at", 0 };
573 /* True if we're writing out a branch-likely instruction rather than a
575 static bool mips_branch_likely
;
577 /* The current instruction-set architecture. */
578 enum processor mips_arch
;
579 const struct mips_cpu_info
*mips_arch_info
;
581 /* The processor that we should tune the code for. */
582 enum processor mips_tune
;
583 const struct mips_cpu_info
*mips_tune_info
;
585 /* The ISA level associated with mips_arch. */
588 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
589 static const struct mips_cpu_info
*mips_isa_option_info
;
591 /* Which cost information to use. */
592 static const struct mips_rtx_cost_data
*mips_cost
;
594 /* The ambient target flags, excluding MASK_MIPS16. */
595 static int mips_base_target_flags
;
597 /* The default compression mode. */
598 unsigned int mips_base_compression_flags
;
600 /* The ambient values of other global variables. */
601 static int mips_base_schedule_insns
; /* flag_schedule_insns */
602 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
603 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
604 static int mips_base_align_loops
; /* align_loops */
605 static int mips_base_align_jumps
; /* align_jumps */
606 static int mips_base_align_functions
; /* align_functions */
608 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
609 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
611 /* Index C is true if character C is a valid PRINT_OPERAND punctation
613 static bool mips_print_operand_punct
[256];
615 static GTY (()) int mips_output_filename_first_time
= 1;
617 /* mips_split_p[X] is true if symbols of type X can be split by
618 mips_split_symbol. */
619 bool mips_split_p
[NUM_SYMBOL_TYPES
];
621 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
622 can be split by mips_split_symbol. */
623 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
625 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
626 forced into a PC-relative constant pool. */
627 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
629 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
630 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
631 if they are matched by a special .md file pattern. */
632 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
634 /* Likewise for HIGHs. */
635 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
637 /* Target state for MIPS16. */
638 struct target_globals
*mips16_globals
;
640 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
641 and returned from mips_sched_reorder2. */
642 static int cached_can_issue_more
;
644 /* The stub for __mips16_rdhwr, if used. */
645 static mips_one_only_stub
*mips16_rdhwr_stub
;
647 /* Index R is the smallest register class that contains register R. */
648 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
649 LEA_REGS
, LEA_REGS
, M16_REGS
, V1_REG
,
650 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
651 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
652 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
653 M16_REGS
, M16_REGS
, LEA_REGS
, LEA_REGS
,
654 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
655 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
656 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
657 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
658 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
659 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
660 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
661 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
662 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
663 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
664 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
665 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
666 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
667 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
668 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
669 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
670 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
671 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
672 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
673 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
674 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
675 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
676 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
677 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
678 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
679 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
680 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
681 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
682 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
683 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
684 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
685 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
686 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
687 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
688 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
689 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
690 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
691 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
692 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
693 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
694 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
695 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
698 /* The value of TARGET_ATTRIBUTE_TABLE. */
699 static const struct attribute_spec mips_attribute_table
[] = {
700 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
702 { "long_call", 0, 0, false, true, true, NULL
, false },
703 { "far", 0, 0, false, true, true, NULL
, false },
704 { "near", 0, 0, false, true, true, NULL
, false },
705 /* We would really like to treat "mips16" and "nomips16" as type
706 attributes, but GCC doesn't provide the hooks we need to support
707 the right conversion rules. As declaration attributes, they affect
708 code generation but don't carry other semantics. */
709 { "mips16", 0, 0, true, false, false, NULL
, false },
710 { "nomips16", 0, 0, true, false, false, NULL
, false },
711 { "micromips", 0, 0, true, false, false, NULL
, false },
712 { "nomicromips", 0, 0, true, false, false, NULL
, false },
713 { "nocompression", 0, 0, true, false, false, NULL
, false },
714 /* Allow functions to be specified as interrupt handlers */
715 { "interrupt", 0, 0, false, true, true, NULL
, false },
716 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
717 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
718 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
719 { NULL
, 0, 0, false, false, false, NULL
, false }
722 /* A table describing all the processors GCC knows about; see
723 mips-cpus.def for details. */
724 static const struct mips_cpu_info mips_cpu_info_table
[] = {
725 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
726 { NAME, CPU, ISA, FLAGS },
727 #include "mips-cpus.def"
731 /* Default costs. If these are used for a processor we should look
732 up the actual costs. */
733 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
734 COSTS_N_INSNS (7), /* fp_mult_sf */ \
735 COSTS_N_INSNS (8), /* fp_mult_df */ \
736 COSTS_N_INSNS (23), /* fp_div_sf */ \
737 COSTS_N_INSNS (36), /* fp_div_df */ \
738 COSTS_N_INSNS (10), /* int_mult_si */ \
739 COSTS_N_INSNS (10), /* int_mult_di */ \
740 COSTS_N_INSNS (69), /* int_div_si */ \
741 COSTS_N_INSNS (69), /* int_div_di */ \
742 2, /* branch_cost */ \
743 4 /* memory_latency */
745 /* Floating-point costs for processors without an FPU. Just assume that
746 all floating-point libcalls are very expensive. */
747 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
748 COSTS_N_INSNS (256), /* fp_mult_sf */ \
749 COSTS_N_INSNS (256), /* fp_mult_df */ \
750 COSTS_N_INSNS (256), /* fp_div_sf */ \
751 COSTS_N_INSNS (256) /* fp_div_df */
753 /* Costs to use when optimizing for size. */
754 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
755 COSTS_N_INSNS (1), /* fp_add */
756 COSTS_N_INSNS (1), /* fp_mult_sf */
757 COSTS_N_INSNS (1), /* fp_mult_df */
758 COSTS_N_INSNS (1), /* fp_div_sf */
759 COSTS_N_INSNS (1), /* fp_div_df */
760 COSTS_N_INSNS (1), /* int_mult_si */
761 COSTS_N_INSNS (1), /* int_mult_di */
762 COSTS_N_INSNS (1), /* int_div_si */
763 COSTS_N_INSNS (1), /* int_div_di */
765 4 /* memory_latency */
768 /* Costs to use when optimizing for speed, indexed by processor. */
769 static const struct mips_rtx_cost_data
770 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
772 COSTS_N_INSNS (2), /* fp_add */
773 COSTS_N_INSNS (4), /* fp_mult_sf */
774 COSTS_N_INSNS (5), /* fp_mult_df */
775 COSTS_N_INSNS (12), /* fp_div_sf */
776 COSTS_N_INSNS (19), /* fp_div_df */
777 COSTS_N_INSNS (12), /* int_mult_si */
778 COSTS_N_INSNS (12), /* int_mult_di */
779 COSTS_N_INSNS (35), /* int_div_si */
780 COSTS_N_INSNS (35), /* int_div_di */
782 4 /* memory_latency */
786 COSTS_N_INSNS (6), /* int_mult_si */
787 COSTS_N_INSNS (6), /* int_mult_di */
788 COSTS_N_INSNS (36), /* int_div_si */
789 COSTS_N_INSNS (36), /* int_div_di */
791 4 /* memory_latency */
795 COSTS_N_INSNS (36), /* int_mult_si */
796 COSTS_N_INSNS (36), /* int_mult_di */
797 COSTS_N_INSNS (37), /* int_div_si */
798 COSTS_N_INSNS (37), /* int_div_di */
800 4 /* memory_latency */
804 COSTS_N_INSNS (4), /* int_mult_si */
805 COSTS_N_INSNS (11), /* int_mult_di */
806 COSTS_N_INSNS (36), /* int_div_si */
807 COSTS_N_INSNS (68), /* int_div_di */
809 4 /* memory_latency */
812 COSTS_N_INSNS (4), /* fp_add */
813 COSTS_N_INSNS (4), /* fp_mult_sf */
814 COSTS_N_INSNS (5), /* fp_mult_df */
815 COSTS_N_INSNS (17), /* fp_div_sf */
816 COSTS_N_INSNS (32), /* fp_div_df */
817 COSTS_N_INSNS (4), /* int_mult_si */
818 COSTS_N_INSNS (11), /* int_mult_di */
819 COSTS_N_INSNS (36), /* int_div_si */
820 COSTS_N_INSNS (68), /* int_div_di */
822 4 /* memory_latency */
825 COSTS_N_INSNS (4), /* fp_add */
826 COSTS_N_INSNS (4), /* fp_mult_sf */
827 COSTS_N_INSNS (5), /* fp_mult_df */
828 COSTS_N_INSNS (17), /* fp_div_sf */
829 COSTS_N_INSNS (32), /* fp_div_df */
830 COSTS_N_INSNS (4), /* int_mult_si */
831 COSTS_N_INSNS (7), /* int_mult_di */
832 COSTS_N_INSNS (42), /* int_div_si */
833 COSTS_N_INSNS (72), /* int_div_di */
835 4 /* memory_latency */
839 COSTS_N_INSNS (5), /* int_mult_si */
840 COSTS_N_INSNS (5), /* int_mult_di */
841 COSTS_N_INSNS (41), /* int_div_si */
842 COSTS_N_INSNS (41), /* int_div_di */
844 4 /* memory_latency */
847 COSTS_N_INSNS (8), /* fp_add */
848 COSTS_N_INSNS (8), /* fp_mult_sf */
849 COSTS_N_INSNS (10), /* fp_mult_df */
850 COSTS_N_INSNS (34), /* fp_div_sf */
851 COSTS_N_INSNS (64), /* fp_div_df */
852 COSTS_N_INSNS (5), /* int_mult_si */
853 COSTS_N_INSNS (5), /* int_mult_di */
854 COSTS_N_INSNS (41), /* int_div_si */
855 COSTS_N_INSNS (41), /* int_div_di */
857 4 /* memory_latency */
860 COSTS_N_INSNS (4), /* fp_add */
861 COSTS_N_INSNS (4), /* fp_mult_sf */
862 COSTS_N_INSNS (5), /* fp_mult_df */
863 COSTS_N_INSNS (17), /* fp_div_sf */
864 COSTS_N_INSNS (32), /* fp_div_df */
865 COSTS_N_INSNS (5), /* int_mult_si */
866 COSTS_N_INSNS (5), /* int_mult_di */
867 COSTS_N_INSNS (41), /* int_div_si */
868 COSTS_N_INSNS (41), /* int_div_di */
870 4 /* memory_latency */
874 COSTS_N_INSNS (5), /* int_mult_si */
875 COSTS_N_INSNS (5), /* int_mult_di */
876 COSTS_N_INSNS (41), /* int_div_si */
877 COSTS_N_INSNS (41), /* int_div_di */
879 4 /* memory_latency */
882 COSTS_N_INSNS (8), /* fp_add */
883 COSTS_N_INSNS (8), /* fp_mult_sf */
884 COSTS_N_INSNS (10), /* fp_mult_df */
885 COSTS_N_INSNS (34), /* fp_div_sf */
886 COSTS_N_INSNS (64), /* fp_div_df */
887 COSTS_N_INSNS (5), /* int_mult_si */
888 COSTS_N_INSNS (5), /* int_mult_di */
889 COSTS_N_INSNS (41), /* int_div_si */
890 COSTS_N_INSNS (41), /* int_div_di */
892 4 /* memory_latency */
895 COSTS_N_INSNS (4), /* fp_add */
896 COSTS_N_INSNS (4), /* fp_mult_sf */
897 COSTS_N_INSNS (5), /* fp_mult_df */
898 COSTS_N_INSNS (17), /* fp_div_sf */
899 COSTS_N_INSNS (32), /* fp_div_df */
900 COSTS_N_INSNS (5), /* int_mult_si */
901 COSTS_N_INSNS (5), /* int_mult_di */
902 COSTS_N_INSNS (41), /* int_div_si */
903 COSTS_N_INSNS (41), /* int_div_di */
905 4 /* memory_latency */
908 COSTS_N_INSNS (6), /* fp_add */
909 COSTS_N_INSNS (6), /* fp_mult_sf */
910 COSTS_N_INSNS (7), /* fp_mult_df */
911 COSTS_N_INSNS (25), /* fp_div_sf */
912 COSTS_N_INSNS (48), /* fp_div_df */
913 COSTS_N_INSNS (5), /* int_mult_si */
914 COSTS_N_INSNS (5), /* int_mult_di */
915 COSTS_N_INSNS (41), /* int_div_si */
916 COSTS_N_INSNS (41), /* int_div_di */
918 4 /* memory_latency */
935 COSTS_N_INSNS (5), /* int_mult_si */
936 COSTS_N_INSNS (5), /* int_mult_di */
937 COSTS_N_INSNS (72), /* int_div_si */
938 COSTS_N_INSNS (72), /* int_div_di */
940 4 /* memory_latency */
945 COSTS_N_INSNS (6), /* int_mult_si */
946 COSTS_N_INSNS (6), /* int_mult_di */
947 COSTS_N_INSNS (18), /* int_div_si */
948 COSTS_N_INSNS (35), /* int_div_di */
950 4 /* memory_latency */
953 COSTS_N_INSNS (2), /* fp_add */
954 COSTS_N_INSNS (4), /* fp_mult_sf */
955 COSTS_N_INSNS (5), /* fp_mult_df */
956 COSTS_N_INSNS (12), /* fp_div_sf */
957 COSTS_N_INSNS (19), /* fp_div_df */
958 COSTS_N_INSNS (2), /* int_mult_si */
959 COSTS_N_INSNS (2), /* int_mult_di */
960 COSTS_N_INSNS (35), /* int_div_si */
961 COSTS_N_INSNS (35), /* int_div_di */
963 4 /* memory_latency */
966 COSTS_N_INSNS (3), /* fp_add */
967 COSTS_N_INSNS (5), /* fp_mult_sf */
968 COSTS_N_INSNS (6), /* fp_mult_df */
969 COSTS_N_INSNS (15), /* fp_div_sf */
970 COSTS_N_INSNS (16), /* fp_div_df */
971 COSTS_N_INSNS (17), /* int_mult_si */
972 COSTS_N_INSNS (17), /* int_mult_di */
973 COSTS_N_INSNS (38), /* int_div_si */
974 COSTS_N_INSNS (38), /* int_div_di */
976 6 /* memory_latency */
979 COSTS_N_INSNS (6), /* fp_add */
980 COSTS_N_INSNS (7), /* fp_mult_sf */
981 COSTS_N_INSNS (8), /* fp_mult_df */
982 COSTS_N_INSNS (23), /* fp_div_sf */
983 COSTS_N_INSNS (36), /* fp_div_df */
984 COSTS_N_INSNS (10), /* int_mult_si */
985 COSTS_N_INSNS (10), /* int_mult_di */
986 COSTS_N_INSNS (69), /* int_div_si */
987 COSTS_N_INSNS (69), /* int_div_di */
989 6 /* memory_latency */
1001 /* The only costs that appear to be updated here are
1002 integer multiplication. */
1004 COSTS_N_INSNS (4), /* int_mult_si */
1005 COSTS_N_INSNS (6), /* int_mult_di */
1006 COSTS_N_INSNS (69), /* int_div_si */
1007 COSTS_N_INSNS (69), /* int_div_di */
1008 1, /* branch_cost */
1009 4 /* memory_latency */
1024 COSTS_N_INSNS (6), /* fp_add */
1025 COSTS_N_INSNS (4), /* fp_mult_sf */
1026 COSTS_N_INSNS (5), /* fp_mult_df */
1027 COSTS_N_INSNS (23), /* fp_div_sf */
1028 COSTS_N_INSNS (36), /* fp_div_df */
1029 COSTS_N_INSNS (5), /* int_mult_si */
1030 COSTS_N_INSNS (5), /* int_mult_di */
1031 COSTS_N_INSNS (36), /* int_div_si */
1032 COSTS_N_INSNS (36), /* int_div_di */
1033 1, /* branch_cost */
1034 4 /* memory_latency */
1037 COSTS_N_INSNS (6), /* fp_add */
1038 COSTS_N_INSNS (5), /* fp_mult_sf */
1039 COSTS_N_INSNS (6), /* fp_mult_df */
1040 COSTS_N_INSNS (30), /* fp_div_sf */
1041 COSTS_N_INSNS (59), /* fp_div_df */
1042 COSTS_N_INSNS (3), /* int_mult_si */
1043 COSTS_N_INSNS (4), /* int_mult_di */
1044 COSTS_N_INSNS (42), /* int_div_si */
1045 COSTS_N_INSNS (74), /* int_div_di */
1046 1, /* branch_cost */
1047 4 /* memory_latency */
1050 COSTS_N_INSNS (6), /* fp_add */
1051 COSTS_N_INSNS (5), /* fp_mult_sf */
1052 COSTS_N_INSNS (6), /* fp_mult_df */
1053 COSTS_N_INSNS (30), /* fp_div_sf */
1054 COSTS_N_INSNS (59), /* fp_div_df */
1055 COSTS_N_INSNS (5), /* int_mult_si */
1056 COSTS_N_INSNS (9), /* int_mult_di */
1057 COSTS_N_INSNS (42), /* int_div_si */
1058 COSTS_N_INSNS (74), /* int_div_di */
1059 1, /* branch_cost */
1060 4 /* memory_latency */
1063 COSTS_N_INSNS (4), /* fp_add */
1064 COSTS_N_INSNS (4), /* fp_mult_sf */
1065 COSTS_N_INSNS (256), /* fp_mult_df */
1066 COSTS_N_INSNS (8), /* fp_div_sf */
1067 COSTS_N_INSNS (256), /* fp_div_df */
1068 COSTS_N_INSNS (4), /* int_mult_si */
1069 COSTS_N_INSNS (256), /* int_mult_di */
1070 COSTS_N_INSNS (37), /* int_div_si */
1071 COSTS_N_INSNS (256), /* int_div_di */
1072 1, /* branch_cost */
1073 4 /* memory_latency */
1076 /* The only costs that are changed here are
1077 integer multiplication. */
1078 COSTS_N_INSNS (6), /* fp_add */
1079 COSTS_N_INSNS (7), /* fp_mult_sf */
1080 COSTS_N_INSNS (8), /* fp_mult_df */
1081 COSTS_N_INSNS (23), /* fp_div_sf */
1082 COSTS_N_INSNS (36), /* fp_div_df */
1083 COSTS_N_INSNS (5), /* int_mult_si */
1084 COSTS_N_INSNS (9), /* int_mult_di */
1085 COSTS_N_INSNS (69), /* int_div_si */
1086 COSTS_N_INSNS (69), /* int_div_di */
1087 1, /* branch_cost */
1088 4 /* memory_latency */
1094 /* The only costs that are changed here are
1095 integer multiplication. */
1096 COSTS_N_INSNS (6), /* fp_add */
1097 COSTS_N_INSNS (7), /* fp_mult_sf */
1098 COSTS_N_INSNS (8), /* fp_mult_df */
1099 COSTS_N_INSNS (23), /* fp_div_sf */
1100 COSTS_N_INSNS (36), /* fp_div_df */
1101 COSTS_N_INSNS (3), /* int_mult_si */
1102 COSTS_N_INSNS (8), /* int_mult_di */
1103 COSTS_N_INSNS (69), /* int_div_si */
1104 COSTS_N_INSNS (69), /* int_div_di */
1105 1, /* branch_cost */
1106 4 /* memory_latency */
1109 COSTS_N_INSNS (2), /* fp_add */
1110 COSTS_N_INSNS (2), /* fp_mult_sf */
1111 COSTS_N_INSNS (2), /* fp_mult_df */
1112 COSTS_N_INSNS (12), /* fp_div_sf */
1113 COSTS_N_INSNS (19), /* fp_div_df */
1114 COSTS_N_INSNS (5), /* int_mult_si */
1115 COSTS_N_INSNS (9), /* int_mult_di */
1116 COSTS_N_INSNS (34), /* int_div_si */
1117 COSTS_N_INSNS (66), /* int_div_di */
1118 1, /* branch_cost */
1119 4 /* memory_latency */
1122 /* These costs are the same as the SB-1A below. */
1123 COSTS_N_INSNS (4), /* fp_add */
1124 COSTS_N_INSNS (4), /* fp_mult_sf */
1125 COSTS_N_INSNS (4), /* fp_mult_df */
1126 COSTS_N_INSNS (24), /* fp_div_sf */
1127 COSTS_N_INSNS (32), /* fp_div_df */
1128 COSTS_N_INSNS (3), /* int_mult_si */
1129 COSTS_N_INSNS (4), /* int_mult_di */
1130 COSTS_N_INSNS (36), /* int_div_si */
1131 COSTS_N_INSNS (68), /* int_div_di */
1132 1, /* branch_cost */
1133 4 /* memory_latency */
1136 /* These costs are the same as the SB-1 above. */
1137 COSTS_N_INSNS (4), /* fp_add */
1138 COSTS_N_INSNS (4), /* fp_mult_sf */
1139 COSTS_N_INSNS (4), /* fp_mult_df */
1140 COSTS_N_INSNS (24), /* fp_div_sf */
1141 COSTS_N_INSNS (32), /* fp_div_df */
1142 COSTS_N_INSNS (3), /* int_mult_si */
1143 COSTS_N_INSNS (4), /* int_mult_di */
1144 COSTS_N_INSNS (36), /* int_div_si */
1145 COSTS_N_INSNS (68), /* int_div_di */
1146 1, /* branch_cost */
1147 4 /* memory_latency */
1154 COSTS_N_INSNS (8), /* int_mult_si */
1155 COSTS_N_INSNS (8), /* int_mult_di */
1156 COSTS_N_INSNS (72), /* int_div_si */
1157 COSTS_N_INSNS (72), /* int_div_di */
1158 1, /* branch_cost */
1159 4 /* memory_latency */
1162 /* These costs are the same as 5KF above. */
1163 COSTS_N_INSNS (4), /* fp_add */
1164 COSTS_N_INSNS (4), /* fp_mult_sf */
1165 COSTS_N_INSNS (5), /* fp_mult_df */
1166 COSTS_N_INSNS (17), /* fp_div_sf */
1167 COSTS_N_INSNS (32), /* fp_div_df */
1168 COSTS_N_INSNS (4), /* int_mult_si */
1169 COSTS_N_INSNS (11), /* int_mult_di */
1170 COSTS_N_INSNS (36), /* int_div_si */
1171 COSTS_N_INSNS (68), /* int_div_di */
1172 1, /* branch_cost */
1173 4 /* memory_latency */
1177 static rtx
mips_find_pic_call_symbol (rtx
, rtx
, bool);
1178 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1180 static unsigned int mips_function_arg_boundary (enum machine_mode
, const_tree
);
1182 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1183 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1184 struct GTY (()) mflip_mips16_entry
{
1188 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1190 /* Hash table callbacks for mflip_mips16_htab. */
1193 mflip_mips16_htab_hash (const void *entry
)
1195 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1199 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1201 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1202 (const char *) name
) == 0;
1205 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1206 mode, false if it should next add an attribute for the opposite mode. */
1207 static GTY(()) bool mips16_flipper
;
1209 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1210 for -mflip-mips16. Return true if it should use "mips16" and false if
1211 it should use "nomips16". */
1214 mflip_mips16_use_mips16_p (tree decl
)
1216 struct mflip_mips16_entry
*entry
;
1220 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1222 /* Use the opposite of the command-line setting for anonymous decls. */
1223 if (!DECL_NAME (decl
))
1224 return !base_is_mips16
;
1226 if (!mflip_mips16_htab
)
1227 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1228 mflip_mips16_htab_eq
, NULL
);
1230 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1231 hash
= htab_hash_string (name
);
1232 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1233 entry
= (struct mflip_mips16_entry
*) *slot
;
1236 mips16_flipper
= !mips16_flipper
;
1237 entry
= ggc_alloc_mflip_mips16_entry ();
1239 entry
->mips16_p
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1242 return entry
->mips16_p
;
1245 /* Predicates to test for presence of "near" and "far"/"long_call"
1246 attributes on the given TYPE. */
1249 mips_near_type_p (const_tree type
)
1251 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1255 mips_far_type_p (const_tree type
)
1257 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1258 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1262 /* Check if the interrupt attribute is set for a function. */
1265 mips_interrupt_type_p (tree type
)
1267 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1270 /* Check if the attribute to use shadow register set is set for a function. */
1273 mips_use_shadow_register_set_p (tree type
)
1275 return lookup_attribute ("use_shadow_register_set",
1276 TYPE_ATTRIBUTES (type
)) != NULL
;
1279 /* Check if the attribute to keep interrupts masked is set for a function. */
1282 mips_keep_interrupts_masked_p (tree type
)
1284 return lookup_attribute ("keep_interrupts_masked",
1285 TYPE_ATTRIBUTES (type
)) != NULL
;
1288 /* Check if the attribute to use debug exception return is set for
1292 mips_use_debug_exception_return_p (tree type
)
1294 return lookup_attribute ("use_debug_exception_return",
1295 TYPE_ATTRIBUTES (type
)) != NULL
;
1298 /* Return the set of compression modes that are explicitly required
1299 by the attributes in ATTRIBUTES. */
1302 mips_get_compress_on_flags (tree attributes
)
1304 unsigned int flags
= 0;
1306 if (lookup_attribute ("mips16", attributes
) != NULL
)
1307 flags
|= MASK_MIPS16
;
1309 if (lookup_attribute ("micromips", attributes
) != NULL
)
1310 flags
|= MASK_MICROMIPS
;
1315 /* Return the set of compression modes that are explicitly forbidden
1316 by the attributes in ATTRIBUTES. */
1319 mips_get_compress_off_flags (tree attributes
)
1321 unsigned int flags
= 0;
1323 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1324 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1326 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1327 flags
|= MASK_MIPS16
;
1329 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1330 flags
|= MASK_MICROMIPS
;
1335 /* Return the compression mode that should be used for function DECL.
1336 Return the ambient setting if DECL is null. */
1339 mips_get_compress_mode (tree decl
)
1341 unsigned int flags
, force_on
;
1343 flags
= mips_base_compression_flags
;
1346 /* Nested functions must use the same frame pointer as their
1347 parent and must therefore use the same ISA mode. */
1348 tree parent
= decl_function_context (decl
);
1351 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1354 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1359 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1363 mips_get_compress_on_name (unsigned int flags
)
1365 if (flags
== MASK_MIPS16
)
1370 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1374 mips_get_compress_off_name (unsigned int flags
)
1376 if (flags
== MASK_MIPS16
)
1378 if (flags
== MASK_MICROMIPS
)
1379 return "nomicromips";
1380 return "nocompression";
1383 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1386 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1388 /* Disallow mixed near/far attributes. */
1389 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1391 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1396 /* Implement TARGET_INSERT_ATTRIBUTES. */
1399 mips_insert_attributes (tree decl
, tree
*attributes
)
1402 unsigned int compression_flags
, nocompression_flags
;
1404 /* Check for "mips16" and "nomips16" attributes. */
1405 compression_flags
= mips_get_compress_on_flags (*attributes
);
1406 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1408 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1410 if (nocompression_flags
)
1411 error ("%qs attribute only applies to functions",
1412 mips_get_compress_off_name (nocompression_flags
));
1414 if (compression_flags
)
1415 error ("%qs attribute only applies to functions",
1416 mips_get_compress_on_name (nocompression_flags
));
1420 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1421 nocompression_flags
|=
1422 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1424 if (compression_flags
&& nocompression_flags
)
1425 error ("%qE cannot have both %qs and %qs attributes",
1426 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1427 mips_get_compress_off_name (nocompression_flags
));
1429 if (compression_flags
& MASK_MIPS16
1430 && compression_flags
& MASK_MICROMIPS
)
1431 error ("%qE cannot have both %qs and %qs attributes",
1432 DECL_NAME (decl
), "mips16", "micromips");
1434 if (TARGET_FLIP_MIPS16
1435 && !DECL_ARTIFICIAL (decl
)
1436 && compression_flags
== 0
1437 && nocompression_flags
== 0)
1439 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1440 "mips16" attribute, arbitrarily pick one. We must pick the same
1441 setting for duplicate declarations of a function. */
1442 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1443 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1444 name
= "nomicromips";
1445 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1450 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1453 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1457 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1458 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1460 error ("%qE redeclared with conflicting %qs attributes",
1461 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1463 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1464 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1466 error ("%qE redeclared with conflicting %qs attributes",
1467 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1469 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1470 DECL_ATTRIBUTES (newdecl
));
1473 /* Implement TARGET_CAN_INLINE_P. */
1476 mips_can_inline_p (tree caller
, tree callee
)
1478 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1480 return default_target_can_inline_p (caller
, callee
);
1483 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1484 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1487 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1489 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1491 *base_ptr
= XEXP (x
, 0);
1492 *offset_ptr
= INTVAL (XEXP (x
, 1));
1501 static unsigned int mips_build_integer (struct mips_integer_op
*,
1502 unsigned HOST_WIDE_INT
);
1504 /* A subroutine of mips_build_integer, with the same interface.
1505 Assume that the final action in the sequence should be a left shift. */
1508 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1510 unsigned int i
, shift
;
1512 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1513 since signed numbers are easier to load than unsigned ones. */
1515 while ((value
& 1) == 0)
1516 value
/= 2, shift
++;
1518 i
= mips_build_integer (codes
, value
);
1519 codes
[i
].code
= ASHIFT
;
1520 codes
[i
].value
= shift
;
1524 /* As for mips_build_shift, but assume that the final action will be
1525 an IOR or PLUS operation. */
1528 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1530 unsigned HOST_WIDE_INT high
;
1533 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1534 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1536 /* The constant is too complex to load with a simple LUI/ORI pair,
1537 so we want to give the recursive call as many trailing zeros as
1538 possible. In this case, we know bit 16 is set and that the
1539 low 16 bits form a negative number. If we subtract that number
1540 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1541 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1542 codes
[i
].code
= PLUS
;
1543 codes
[i
].value
= CONST_LOW_PART (value
);
1547 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1548 bits gives a value with at least 17 trailing zeros. */
1549 i
= mips_build_integer (codes
, high
);
1550 codes
[i
].code
= IOR
;
1551 codes
[i
].value
= value
& 0xffff;
1556 /* Fill CODES with a sequence of rtl operations to load VALUE.
1557 Return the number of operations needed. */
1560 mips_build_integer (struct mips_integer_op
*codes
,
1561 unsigned HOST_WIDE_INT value
)
1563 if (SMALL_OPERAND (value
)
1564 || SMALL_OPERAND_UNSIGNED (value
)
1565 || LUI_OPERAND (value
))
1567 /* The value can be loaded with a single instruction. */
1568 codes
[0].code
= UNKNOWN
;
1569 codes
[0].value
= value
;
1572 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1574 /* Either the constant is a simple LUI/ORI combination or its
1575 lowest bit is set. We don't want to shift in this case. */
1576 return mips_build_lower (codes
, value
);
1578 else if ((value
& 0xffff) == 0)
1580 /* The constant will need at least three actions. The lowest
1581 16 bits are clear, so the final action will be a shift. */
1582 return mips_build_shift (codes
, value
);
1586 /* The final action could be a shift, add or inclusive OR.
1587 Rather than use a complex condition to select the best
1588 approach, try both mips_build_shift and mips_build_lower
1589 and pick the one that gives the shortest sequence.
1590 Note that this case is only used once per constant. */
1591 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1592 unsigned int cost
, alt_cost
;
1594 cost
= mips_build_shift (codes
, value
);
1595 alt_cost
= mips_build_lower (alt_codes
, value
);
1596 if (alt_cost
< cost
)
1598 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1605 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1608 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1610 return mips_const_insns (x
) > 0;
1613 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1616 mips16_stub_function (const char *name
)
1620 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1621 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1625 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1626 support function. */
1629 mips16_stub_call_address (mips_one_only_stub
*stub
)
1631 rtx fn
= mips16_stub_function (stub
->get_name ());
1632 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
1633 if (!call_insn_operand (fn
, VOIDmode
))
1634 fn
= force_reg (Pmode
, fn
);
1638 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1640 class mips16_rdhwr_one_only_stub
: public mips_one_only_stub
1642 virtual const char *get_name ();
1643 virtual void output_body ();
1647 mips16_rdhwr_one_only_stub::get_name ()
1649 return "__mips16_rdhwr";
1653 mips16_rdhwr_one_only_stub::output_body ()
1655 fprintf (asm_out_file
,
1657 "\t.set\tmips32r2\n"
1658 "\t.set\tnoreorder\n"
1664 /* Return true if symbols of type TYPE require a GOT access. */
1667 mips_got_symbol_type_p (enum mips_symbol_type type
)
1671 case SYMBOL_GOT_PAGE_OFST
:
1672 case SYMBOL_GOT_DISP
:
1680 /* Return true if X is a thread-local symbol. */
1683 mips_tls_symbol_p (rtx x
)
1685 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1688 /* Return true if SYMBOL_REF X is associated with a global symbol
1689 (in the STB_GLOBAL sense). */
1692 mips_global_symbol_p (const_rtx x
)
1694 const_tree decl
= SYMBOL_REF_DECL (x
);
1697 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1699 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1700 or weak symbols. Relocations in the object file will be against
1701 the target symbol, so it's that symbol's binding that matters here. */
1702 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1705 /* Return true if function X is a libgcc MIPS16 stub function. */
1708 mips16_stub_function_p (const_rtx x
)
1710 return (GET_CODE (x
) == SYMBOL_REF
1711 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1714 /* Return true if function X is a locally-defined and locally-binding
1718 mips16_local_function_p (const_rtx x
)
1720 return (GET_CODE (x
) == SYMBOL_REF
1721 && SYMBOL_REF_LOCAL_P (x
)
1722 && !SYMBOL_REF_EXTERNAL_P (x
)
1723 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1726 /* Return true if SYMBOL_REF X binds locally. */
1729 mips_symbol_binds_local_p (const_rtx x
)
1731 return (SYMBOL_REF_DECL (x
)
1732 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1733 : SYMBOL_REF_LOCAL_P (x
));
1736 /* Return true if rtx constants of mode MODE should be put into a small
1740 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1742 return (!TARGET_EMBEDDED_DATA
1743 && TARGET_LOCAL_SDATA
1744 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1747 /* Return true if X should not be moved directly into register $25.
1748 We need this because many versions of GAS will treat "la $25,foo" as
1749 part of a call sequence and so allow a global "foo" to be lazily bound. */
1752 mips_dangerous_for_la25_p (rtx x
)
1754 return (!TARGET_EXPLICIT_RELOCS
1756 && GET_CODE (x
) == SYMBOL_REF
1757 && mips_global_symbol_p (x
));
1760 /* Return true if calls to X might need $25 to be valid on entry. */
1763 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1765 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1768 /* MIPS16 stub functions are guaranteed not to use $25. */
1769 if (mips16_stub_function_p (x
))
1772 if (GET_CODE (x
) == SYMBOL_REF
)
1774 /* If PLTs and copy relocations are available, the static linker
1775 will make sure that $25 is valid on entry to the target function. */
1776 if (TARGET_ABICALLS_PIC0
)
1779 /* Locally-defined functions use absolute accesses to set up
1780 the global pointer. */
1781 if (TARGET_ABSOLUTE_ABICALLS
1782 && mips_symbol_binds_local_p (x
)
1783 && !SYMBOL_REF_EXTERNAL_P (x
))
1790 /* Return the method that should be used to access SYMBOL_REF or
1791 LABEL_REF X in context CONTEXT. */
1793 static enum mips_symbol_type
1794 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1797 return SYMBOL_GOT_DISP
;
1799 if (GET_CODE (x
) == LABEL_REF
)
1801 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1802 code and if we know that the label is in the current function's
1803 text section. LABEL_REFs are used for jump tables as well as
1804 text labels, so we must check whether jump tables live in the
1806 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1807 && !LABEL_REF_NONLOCAL_P (x
))
1808 return SYMBOL_PC_RELATIVE
;
1810 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1811 return SYMBOL_GOT_PAGE_OFST
;
1813 return SYMBOL_ABSOLUTE
;
1816 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1818 if (SYMBOL_REF_TLS_MODEL (x
))
1821 if (CONSTANT_POOL_ADDRESS_P (x
))
1823 if (TARGET_MIPS16_TEXT_LOADS
)
1824 return SYMBOL_PC_RELATIVE
;
1826 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1827 return SYMBOL_PC_RELATIVE
;
1829 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1830 return SYMBOL_GP_RELATIVE
;
1833 /* Do not use small-data accesses for weak symbols; they may end up
1835 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1836 return SYMBOL_GP_RELATIVE
;
1838 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1840 if (TARGET_ABICALLS_PIC2
1841 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1843 /* There are three cases to consider:
1845 - o32 PIC (either with or without explicit relocs)
1846 - n32/n64 PIC without explicit relocs
1847 - n32/n64 PIC with explicit relocs
1849 In the first case, both local and global accesses will use an
1850 R_MIPS_GOT16 relocation. We must correctly predict which of
1851 the two semantics (local or global) the assembler and linker
1852 will apply. The choice depends on the symbol's binding rather
1853 than its visibility.
1855 In the second case, the assembler will not use R_MIPS_GOT16
1856 relocations, but it chooses between local and global accesses
1857 in the same way as for o32 PIC.
1859 In the third case we have more freedom since both forms of
1860 access will work for any kind of symbol. However, there seems
1861 little point in doing things differently. */
1862 if (mips_global_symbol_p (x
))
1863 return SYMBOL_GOT_DISP
;
1865 return SYMBOL_GOT_PAGE_OFST
;
1868 return SYMBOL_ABSOLUTE
;
1871 /* Classify the base of symbolic expression X, given that X appears in
1874 static enum mips_symbol_type
1875 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1879 split_const (x
, &x
, &offset
);
1880 if (UNSPEC_ADDRESS_P (x
))
1881 return UNSPEC_ADDRESS_TYPE (x
);
1883 return mips_classify_symbol (x
, context
);
1886 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1887 is the alignment in bytes of SYMBOL_REF X. */
1890 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1892 HOST_WIDE_INT align
;
1894 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1895 return IN_RANGE (offset
, 0, align
- 1);
1898 /* Return true if X is a symbolic constant that can be used in context
1899 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1902 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1903 enum mips_symbol_type
*symbol_type
)
1907 split_const (x
, &x
, &offset
);
1908 if (UNSPEC_ADDRESS_P (x
))
1910 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1911 x
= UNSPEC_ADDRESS (x
);
1913 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1915 *symbol_type
= mips_classify_symbol (x
, context
);
1916 if (*symbol_type
== SYMBOL_TLS
)
1922 if (offset
== const0_rtx
)
1925 /* Check whether a nonzero offset is valid for the underlying
1927 switch (*symbol_type
)
1929 case SYMBOL_ABSOLUTE
:
1930 case SYMBOL_64_HIGH
:
1933 /* If the target has 64-bit pointers and the object file only
1934 supports 32-bit symbols, the values of those symbols will be
1935 sign-extended. In this case we can't allow an arbitrary offset
1936 in case the 32-bit value X + OFFSET has a different sign from X. */
1937 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1938 return offset_within_block_p (x
, INTVAL (offset
));
1940 /* In other cases the relocations can handle any offset. */
1943 case SYMBOL_PC_RELATIVE
:
1944 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1945 In this case, we no longer have access to the underlying constant,
1946 but the original symbol-based access was known to be valid. */
1947 if (GET_CODE (x
) == LABEL_REF
)
1952 case SYMBOL_GP_RELATIVE
:
1953 /* Make sure that the offset refers to something within the
1954 same object block. This should guarantee that the final
1955 PC- or GP-relative offset is within the 16-bit limit. */
1956 return offset_within_block_p (x
, INTVAL (offset
));
1958 case SYMBOL_GOT_PAGE_OFST
:
1959 case SYMBOL_GOTOFF_PAGE
:
1960 /* If the symbol is global, the GOT entry will contain the symbol's
1961 address, and we will apply a 16-bit offset after loading it.
1962 If the symbol is local, the linker should provide enough local
1963 GOT entries for a 16-bit offset, but larger offsets may lead
1965 return SMALL_INT (offset
);
1969 /* There is no carry between the HI and LO REL relocations, so the
1970 offset is only valid if we know it won't lead to such a carry. */
1971 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1973 case SYMBOL_GOT_DISP
:
1974 case SYMBOL_GOTOFF_DISP
:
1975 case SYMBOL_GOTOFF_CALL
:
1976 case SYMBOL_GOTOFF_LOADGP
:
1979 case SYMBOL_GOTTPREL
:
1987 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1988 single instruction. We rely on the fact that, in the worst case,
1989 all instructions involved in a MIPS16 address calculation are usually
1993 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1995 if (mips_use_pcrel_pool_p
[(int) type
])
1997 if (mode
== MAX_MACHINE_MODE
)
1998 /* LEAs will be converted into constant-pool references by
2000 type
= SYMBOL_PC_RELATIVE
;
2002 /* The constant must be loaded and then dereferenced. */
2008 case SYMBOL_ABSOLUTE
:
2009 /* When using 64-bit symbols, we need 5 preparatory instructions,
2012 lui $at,%highest(symbol)
2013 daddiu $at,$at,%higher(symbol)
2015 daddiu $at,$at,%hi(symbol)
2018 The final address is then $at + %lo(symbol). With 32-bit
2019 symbols we just need a preparatory LUI for normal mode and
2020 a preparatory LI and SLL for MIPS16. */
2021 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
2023 case SYMBOL_GP_RELATIVE
:
2024 /* Treat GP-relative accesses as taking a single instruction on
2025 MIPS16 too; the copy of $gp can often be shared. */
2028 case SYMBOL_PC_RELATIVE
:
2029 /* PC-relative constants can be only be used with ADDIUPC,
2030 DADDIUPC, LWPC and LDPC. */
2031 if (mode
== MAX_MACHINE_MODE
2032 || GET_MODE_SIZE (mode
) == 4
2033 || GET_MODE_SIZE (mode
) == 8)
2036 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2039 case SYMBOL_GOT_DISP
:
2040 /* The constant will have to be loaded from the GOT before it
2041 is used in an address. */
2042 if (mode
!= MAX_MACHINE_MODE
)
2047 case SYMBOL_GOT_PAGE_OFST
:
2048 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2049 local/global classification is accurate. The worst cases are:
2051 (1) For local symbols when generating o32 or o64 code. The assembler
2057 ...and the final address will be $at + %lo(symbol).
2059 (2) For global symbols when -mxgot. The assembler will use:
2061 lui $at,%got_hi(symbol)
2064 ...and the final address will be $at + %got_lo(symbol). */
2067 case SYMBOL_GOTOFF_PAGE
:
2068 case SYMBOL_GOTOFF_DISP
:
2069 case SYMBOL_GOTOFF_CALL
:
2070 case SYMBOL_GOTOFF_LOADGP
:
2071 case SYMBOL_64_HIGH
:
2077 case SYMBOL_GOTTPREL
:
2080 /* A 16-bit constant formed by a single relocation, or a 32-bit
2081 constant formed from a high 16-bit relocation and a low 16-bit
2082 relocation. Use mips_split_p to determine which. 32-bit
2083 constants need an "lui; addiu" sequence for normal mode and
2084 an "li; sll; addiu" sequence for MIPS16 mode. */
2085 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2088 /* We don't treat a bare TLS symbol as a constant. */
2094 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2095 to load symbols of type TYPE into a register. Return 0 if the given
2096 type of symbol cannot be used as an immediate operand.
2098 Otherwise, return the number of instructions needed to load or store
2099 values of mode MODE to or from addresses of type TYPE. Return 0 if
2100 the given type of symbol is not valid in addresses.
2102 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2105 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
2107 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2110 /* A for_each_rtx callback. Stop the search if *X references a
2111 thread-local symbol. */
2114 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
2116 return mips_tls_symbol_p (*x
);
2119 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2122 mips_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2124 enum mips_symbol_type type
;
2127 /* There is no assembler syntax for expressing an address-sized
2129 if (GET_CODE (x
) == HIGH
)
2132 /* As an optimization, reject constants that mips_legitimize_move
2135 Suppose we have a multi-instruction sequence that loads constant C
2136 into register R. If R does not get allocated a hard register, and
2137 R is used in an operand that allows both registers and memory
2138 references, reload will consider forcing C into memory and using
2139 one of the instruction's memory alternatives. Returning false
2140 here will force it to use an input reload instead. */
2141 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2144 split_const (x
, &base
, &offset
);
2145 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2147 /* See whether we explicitly want these symbols in the pool. */
2148 if (mips_use_pcrel_pool_p
[(int) type
])
2151 /* The same optimization as for CONST_INT. */
2152 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2155 /* If MIPS16 constant pools live in the text section, they should
2156 not refer to anything that might need run-time relocation. */
2157 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2161 /* TLS symbols must be computed by mips_legitimize_move. */
2162 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
2168 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2169 constants when we're using a per-function constant pool. */
2172 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2173 const_rtx x ATTRIBUTE_UNUSED
)
2175 return !TARGET_MIPS16_PCREL_LOADS
;
2178 /* Return true if register REGNO is a valid base register for mode MODE.
2179 STRICT_P is true if REG_OK_STRICT is in effect. */
2182 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
2185 if (!HARD_REGISTER_NUM_P (regno
))
2189 regno
= reg_renumber
[regno
];
2192 /* These fake registers will be eliminated to either the stack or
2193 hard frame pointer, both of which are usually valid base registers.
2194 Reload deals with the cases where the eliminated form isn't valid. */
2195 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2198 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2199 values, nothing smaller. There are two problems here:
2201 (a) Instantiating virtual registers can introduce new uses of the
2202 stack pointer. If these virtual registers are valid addresses,
2203 the stack pointer should be too.
2205 (b) Most uses of the stack pointer are not made explicit until
2206 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2207 We don't know until that stage whether we'll be eliminating to the
2208 stack pointer (which needs the restriction) or the hard frame
2209 pointer (which doesn't).
2211 All in all, it seems more consistent to only enforce this restriction
2212 during and after reload. */
2213 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2214 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2216 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2219 /* Return true if X is a valid base register for mode MODE.
2220 STRICT_P is true if REG_OK_STRICT is in effect. */
2223 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2225 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2229 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2232 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2233 can address a value of mode MODE. */
2236 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2238 /* Check that X is a signed 16-bit number. */
2239 if (!const_arith_operand (x
, Pmode
))
2242 /* We may need to split multiword moves, so make sure that every word
2244 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2245 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2251 /* Return true if a LO_SUM can address a value of mode MODE when the
2252 LO_SUM symbol has type SYMBOL_TYPE. */
2255 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2257 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2259 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2262 /* Check that there is a known low-part relocation. */
2263 if (mips_lo_relocs
[symbol_type
] == NULL
)
2266 /* We may need to split multiword moves, so make sure that each word
2267 can be accessed without inducing a carry. This is mainly needed
2268 for o64, which has historically only guaranteed 64-bit alignment
2269 for 128-bit types. */
2270 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2271 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2277 /* Return true if X is a valid address for machine mode MODE. If it is,
2278 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2282 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2283 enum machine_mode mode
, bool strict_p
)
2285 switch (GET_CODE (x
))
2289 info
->type
= ADDRESS_REG
;
2291 info
->offset
= const0_rtx
;
2292 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2295 info
->type
= ADDRESS_REG
;
2296 info
->reg
= XEXP (x
, 0);
2297 info
->offset
= XEXP (x
, 1);
2298 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2299 && mips_valid_offset_p (info
->offset
, mode
));
2302 info
->type
= ADDRESS_LO_SUM
;
2303 info
->reg
= XEXP (x
, 0);
2304 info
->offset
= XEXP (x
, 1);
2305 /* We have to trust the creator of the LO_SUM to do something vaguely
2306 sane. Target-independent code that creates a LO_SUM should also
2307 create and verify the matching HIGH. Target-independent code that
2308 adds an offset to a LO_SUM must prove that the offset will not
2309 induce a carry. Failure to do either of these things would be
2310 a bug, and we are not required to check for it here. The MIPS
2311 backend itself should only create LO_SUMs for valid symbolic
2312 constants, with the high part being either a HIGH or a copy
2315 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2316 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2317 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2320 /* Small-integer addresses don't occur very often, but they
2321 are legitimate if $0 is a valid base register. */
2322 info
->type
= ADDRESS_CONST_INT
;
2323 return !TARGET_MIPS16
&& SMALL_INT (x
);
2328 info
->type
= ADDRESS_SYMBOLIC
;
2329 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2331 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2332 && !mips_split_p
[info
->symbol_type
]);
2339 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2342 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2344 struct mips_address_info addr
;
2346 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2349 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2352 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2354 struct mips_address_info addr
;
2356 return (mips_classify_address (&addr
, x
, mode
, false)
2357 && addr
.type
== ADDRESS_REG
2358 && addr
.reg
== stack_pointer_rtx
);
2361 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2362 address instruction. Note that such addresses are not considered
2363 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2364 is so restricted. */
2367 mips_lwxs_address_p (rtx addr
)
2370 && GET_CODE (addr
) == PLUS
2371 && REG_P (XEXP (addr
, 1)))
2373 rtx offset
= XEXP (addr
, 0);
2374 if (GET_CODE (offset
) == MULT
2375 && REG_P (XEXP (offset
, 0))
2376 && CONST_INT_P (XEXP (offset
, 1))
2377 && INTVAL (XEXP (offset
, 1)) == 4)
2383 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2384 indexed address instruction. Note that such addresses are
2385 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2386 sense, because their use is so restricted. */
2389 mips_lx_address_p (rtx addr
, enum machine_mode mode
)
2391 if (GET_CODE (addr
) != PLUS
2392 || !REG_P (XEXP (addr
, 0))
2393 || !REG_P (XEXP (addr
, 1)))
2395 if (ISA_HAS_LBX
&& mode
== QImode
)
2397 if (ISA_HAS_LHX
&& mode
== HImode
)
2399 if (ISA_HAS_LWX
&& mode
== SImode
)
2401 if (ISA_HAS_LDX
&& mode
== DImode
)
2406 /* Return true if a value at OFFSET bytes from base register BASE can be
2407 accessed using an unextended MIPS16 instruction. MODE is the mode of
2410 Usually the offset in an unextended instruction is a 5-bit field.
2411 The offset is unsigned and shifted left once for LH and SH, twice
2412 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2413 an 8-bit immediate field that's shifted left twice. */
2416 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2417 unsigned HOST_WIDE_INT offset
)
2419 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2421 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2422 return offset
< 256U * GET_MODE_SIZE (mode
);
2423 return offset
< 32U * GET_MODE_SIZE (mode
);
2428 /* Return the number of instructions needed to load or store a value
2429 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2430 length of one instruction. Return 0 if X isn't valid for MODE.
2431 Assume that multiword moves may need to be split into word moves
2432 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2436 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2438 struct mips_address_info addr
;
2441 /* BLKmode is used for single unaligned loads and stores and should
2442 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2443 meaningless, so we have to single it out as a special case one way
2445 if (mode
!= BLKmode
&& might_split_p
)
2446 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2450 if (mips_classify_address (&addr
, x
, mode
, false))
2455 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2456 UINTVAL (addr
.offset
)))
2460 case ADDRESS_LO_SUM
:
2461 return TARGET_MIPS16
? factor
* 2 : factor
;
2463 case ADDRESS_CONST_INT
:
2466 case ADDRESS_SYMBOLIC
:
2467 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2472 /* Return true if X fits within an unsigned field of BITS bits that is
2473 shifted left SHIFT bits before being used. */
2476 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2478 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2481 /* Return true if X fits within a signed field of BITS bits that is
2482 shifted left SHIFT bits before being used. */
2485 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2487 x
+= 1 << (bits
+ shift
- 1);
2488 return mips_unsigned_immediate_p (x
, bits
, shift
);
2491 /* Return true if X is legitimate for accessing values of mode MODE,
2492 if it is based on a MIPS16 register, and if the offset satisfies
2493 OFFSET_PREDICATE. */
2496 m16_based_address_p (rtx x
, enum machine_mode mode
,
2497 insn_operand_predicate_fn offset_predicate
)
2499 struct mips_address_info addr
;
2501 return (mips_classify_address (&addr
, x
, mode
, false)
2502 && addr
.type
== ADDRESS_REG
2503 && M16_REG_P (REGNO (addr
.reg
))
2504 && offset_predicate (addr
.offset
, mode
));
2507 /* Return true if X is a legitimate address that conforms to the requirements
2508 for a microMIPS LWSP or SWSP insn. */
2511 lwsp_swsp_address_p (rtx x
, enum machine_mode mode
)
2513 struct mips_address_info addr
;
2515 return (mips_classify_address (&addr
, x
, mode
, false)
2516 && addr
.type
== ADDRESS_REG
2517 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2518 && uw5_operand (addr
.offset
, mode
));
2521 /* Return true if X is a legitimate address with a 12-bit offset.
2522 MODE is the mode of the value being accessed. */
2525 umips_12bit_offset_address_p (rtx x
, enum machine_mode mode
)
2527 struct mips_address_info addr
;
2529 return (mips_classify_address (&addr
, x
, mode
, false)
2530 && addr
.type
== ADDRESS_REG
2531 && CONST_INT_P (addr
.offset
)
2532 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2535 /* Return the number of instructions needed to load constant X,
2536 assuming that BASE_INSN_LENGTH is the length of one instruction.
2537 Return 0 if X isn't a valid constant. */
2540 mips_const_insns (rtx x
)
2542 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2543 enum mips_symbol_type symbol_type
;
2546 switch (GET_CODE (x
))
2549 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2551 || !mips_split_p
[symbol_type
])
2554 /* This is simply an LUI for normal mode. It is an extended
2555 LI followed by an extended SLL for MIPS16. */
2556 return TARGET_MIPS16
? 4 : 1;
2560 /* Unsigned 8-bit constants can be loaded using an unextended
2561 LI instruction. Unsigned 16-bit constants can be loaded
2562 using an extended LI. Negative constants must be loaded
2563 using LI and then negated. */
2564 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2565 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2566 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2567 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2570 return mips_build_integer (codes
, INTVAL (x
));
2574 /* Allow zeros for normal mode, where we can use $0. */
2575 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2581 /* See if we can refer to X directly. */
2582 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2583 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2585 /* Otherwise try splitting the constant into a base and offset.
2586 If the offset is a 16-bit value, we can load the base address
2587 into a register and then use (D)ADDIU to add in the offset.
2588 If the offset is larger, we can load the base and offset
2589 into separate registers and add them together with (D)ADDU.
2590 However, the latter is only possible before reload; during
2591 and after reload, we must have the option of forcing the
2592 constant into the pool instead. */
2593 split_const (x
, &x
, &offset
);
2596 int n
= mips_const_insns (x
);
2599 if (SMALL_INT (offset
))
2601 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2602 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2609 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2617 /* X is a doubleword constant that can be handled by splitting it into
2618 two words and loading each word separately. Return the number of
2619 instructions required to do this, assuming that BASE_INSN_LENGTH
2620 is the length of one instruction. */
2623 mips_split_const_insns (rtx x
)
2625 unsigned int low
, high
;
2627 low
= mips_const_insns (mips_subword (x
, false));
2628 high
= mips_const_insns (mips_subword (x
, true));
2629 gcc_assert (low
> 0 && high
> 0);
2633 /* Return the number of instructions needed to implement INSN,
2634 given that it loads from or stores to MEM. Assume that
2635 BASE_INSN_LENGTH is the length of one instruction. */
2638 mips_load_store_insns (rtx mem
, rtx insn
)
2640 enum machine_mode mode
;
2644 gcc_assert (MEM_P (mem
));
2645 mode
= GET_MODE (mem
);
2647 /* Try to prove that INSN does not need to be split. */
2648 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2651 set
= single_set (insn
);
2652 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2653 might_split_p
= false;
2656 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2659 /* Return the number of instructions needed for an integer division,
2660 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2663 mips_idiv_insns (void)
2668 if (TARGET_CHECK_ZERO_DIV
)
2670 if (GENERATE_DIVIDE_TRAPS
)
2676 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2681 /* Emit a move from SRC to DEST. Assume that the move expanders can
2682 handle all moves if !can_create_pseudo_p (). The distinction is
2683 important because, unlike emit_move_insn, the move expanders know
2684 how to force Pmode objects into the constant pool even when the
2685 constant pool address is not itself legitimate. */
2688 mips_emit_move (rtx dest
, rtx src
)
2690 return (can_create_pseudo_p ()
2691 ? emit_move_insn (dest
, src
)
2692 : emit_move_insn_1 (dest
, src
));
2695 /* Emit a move from SRC to DEST, splitting compound moves into individual
2696 instructions. SPLIT_TYPE is the type of split to perform. */
2699 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
2701 if (mips_split_move_p (dest
, src
, split_type
))
2702 mips_split_move (dest
, src
, split_type
);
2704 mips_emit_move (dest
, src
);
2707 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2710 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2712 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2713 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2716 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2717 Return that new register. */
2720 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2724 reg
= gen_reg_rtx (mode
);
2725 mips_emit_unary (code
, reg
, op0
);
2729 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2732 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2734 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2735 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2738 /* Compute (CODE OP0 OP1) and store the result in a new register
2739 of mode MODE. Return that new register. */
2742 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2746 reg
= gen_reg_rtx (mode
);
2747 mips_emit_binary (code
, reg
, op0
, op1
);
2751 /* Copy VALUE to a register and return that register. If new pseudos
2752 are allowed, copy it into a new register, otherwise use DEST. */
2755 mips_force_temporary (rtx dest
, rtx value
)
2757 if (can_create_pseudo_p ())
2758 return force_reg (Pmode
, value
);
2761 mips_emit_move (dest
, value
);
2766 /* Emit a call sequence with call pattern PATTERN and return the call
2767 instruction itself (which is not necessarily the last instruction
2768 emitted). ORIG_ADDR is the original, unlegitimized address,
2769 ADDR is the legitimized form, and LAZY_P is true if the call
2770 address is lazily-bound. */
2773 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2777 insn
= emit_call_insn (pattern
);
2779 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2781 /* MIPS16 JALRs only take MIPS16 registers. If the target
2782 function requires $25 to be valid on entry, we must copy it
2783 there separately. The move instruction can be put in the
2784 call's delay slot. */
2785 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2786 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2787 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2791 /* Lazy-binding stubs require $gp to be valid on entry. */
2792 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2796 /* See the comment above load_call<mode> for details. */
2797 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2798 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2799 emit_insn (gen_update_got_version ());
2804 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2805 then add CONST_INT OFFSET to the result. */
2808 mips_unspec_address_offset (rtx base
, rtx offset
,
2809 enum mips_symbol_type symbol_type
)
2811 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2812 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2813 if (offset
!= const0_rtx
)
2814 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2815 return gen_rtx_CONST (Pmode
, base
);
2818 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2819 type SYMBOL_TYPE. */
2822 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2826 split_const (address
, &base
, &offset
);
2827 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2830 /* If OP is an UNSPEC address, return the address to which it refers,
2831 otherwise return OP itself. */
2834 mips_strip_unspec_address (rtx op
)
2838 split_const (op
, &base
, &offset
);
2839 if (UNSPEC_ADDRESS_P (base
))
2840 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2844 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2845 high part to BASE and return the result. Just return BASE otherwise.
2846 TEMP is as for mips_force_temporary.
2848 The returned expression can be used as the first operand to a LO_SUM. */
2851 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2852 enum mips_symbol_type symbol_type
)
2854 if (mips_split_p
[symbol_type
])
2856 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2857 addr
= mips_force_temporary (temp
, addr
);
2858 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2863 /* Return an instruction that copies $gp into register REG. We want
2864 GCC to treat the register's value as constant, so that its value
2865 can be rematerialized on demand. */
2868 gen_load_const_gp (rtx reg
)
2870 return PMODE_INSN (gen_load_const_gp
, (reg
));
2873 /* Return a pseudo register that contains the value of $gp throughout
2874 the current function. Such registers are needed by MIPS16 functions,
2875 for which $gp itself is not a valid base register or addition operand. */
2878 mips16_gp_pseudo_reg (void)
2880 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2884 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2886 push_topmost_sequence ();
2888 scan
= get_insns ();
2889 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2890 scan
= NEXT_INSN (scan
);
2892 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2893 insn
= emit_insn_after (insn
, scan
);
2894 INSN_LOCATION (insn
) = 0;
2896 pop_topmost_sequence ();
2899 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2902 /* Return a base register that holds pic_offset_table_rtx.
2903 TEMP, if nonnull, is a scratch Pmode base register. */
2906 mips_pic_base_register (rtx temp
)
2909 return pic_offset_table_rtx
;
2911 if (currently_expanding_to_rtl
)
2912 return mips16_gp_pseudo_reg ();
2914 if (can_create_pseudo_p ())
2915 temp
= gen_reg_rtx (Pmode
);
2918 /* The first post-reload split exposes all references to $gp
2919 (both uses and definitions). All references must remain
2920 explicit after that point.
2922 It is safe to introduce uses of $gp at any time, so for
2923 simplicity, we do that before the split too. */
2924 mips_emit_move (temp
, pic_offset_table_rtx
);
2926 emit_insn (gen_load_const_gp (temp
));
2930 /* Return the RHS of a load_call<mode> insn. */
2933 mips_unspec_call (rtx reg
, rtx symbol
)
2937 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
2938 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
2941 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2942 reference. Return NULL_RTX otherwise. */
2945 mips_strip_unspec_call (rtx src
)
2947 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
2948 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
2952 /* Create and return a GOT reference of type TYPE for address ADDR.
2953 TEMP, if nonnull, is a scratch Pmode base register. */
2956 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
2958 rtx base
, high
, lo_sum_symbol
;
2960 base
= mips_pic_base_register (temp
);
2962 /* If we used the temporary register to load $gp, we can't use
2963 it for the high part as well. */
2964 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
2967 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
2968 lo_sum_symbol
= mips_unspec_address (addr
, type
);
2970 if (type
== SYMBOL_GOTOFF_CALL
)
2971 return mips_unspec_call (high
, lo_sum_symbol
);
2973 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
2976 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2977 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2978 constant in that context and can be split into high and low parts.
2979 If so, and if LOW_OUT is nonnull, emit the high part and store the
2980 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2982 TEMP is as for mips_force_temporary and is used to load the high
2983 part into a register.
2985 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2986 a legitimize SET_SRC for an .md pattern, otherwise the low part
2987 is guaranteed to be a legitimate address for mode MODE. */
2990 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
2992 enum mips_symbol_context context
;
2993 enum mips_symbol_type symbol_type
;
2996 context
= (mode
== MAX_MACHINE_MODE
2997 ? SYMBOL_CONTEXT_LEA
2998 : SYMBOL_CONTEXT_MEM
);
2999 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
3001 addr
= XEXP (addr
, 0);
3002 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3003 && mips_symbol_insns (symbol_type
, mode
) > 0
3004 && mips_split_hi_p
[symbol_type
])
3007 switch (symbol_type
)
3009 case SYMBOL_GOT_PAGE_OFST
:
3010 /* The high part of a page/ofst pair is loaded from the GOT. */
3011 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
3022 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3023 && mips_symbol_insns (symbol_type
, mode
) > 0
3024 && mips_split_p
[symbol_type
])
3027 switch (symbol_type
)
3029 case SYMBOL_GOT_DISP
:
3030 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3031 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
3034 case SYMBOL_GP_RELATIVE
:
3035 high
= mips_pic_base_register (temp
);
3036 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3040 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
3041 high
= mips_force_temporary (temp
, high
);
3042 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3051 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3052 mips_force_temporary; it is only needed when OFFSET is not a
3056 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
3058 if (!SMALL_OPERAND (offset
))
3064 /* Load the full offset into a register so that we can use
3065 an unextended instruction for the address itself. */
3066 high
= GEN_INT (offset
);
3071 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3072 The addition inside the macro CONST_HIGH_PART may cause an
3073 overflow, so we need to force a sign-extension check. */
3074 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
3075 offset
= CONST_LOW_PART (offset
);
3077 high
= mips_force_temporary (temp
, high
);
3078 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
3080 return plus_constant (Pmode
, reg
, offset
);
3083 /* The __tls_get_attr symbol. */
3084 static GTY(()) rtx mips_tls_symbol
;
3086 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3087 the TLS symbol we are referencing and TYPE is the symbol type to use
3088 (either global dynamic or local dynamic). V0 is an RTX for the
3089 return value location. */
3092 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3096 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3098 if (!mips_tls_symbol
)
3099 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3101 loc
= mips_unspec_address (sym
, type
);
3105 emit_insn (gen_rtx_SET (Pmode
, a0
,
3106 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
3107 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3108 const0_rtx
, NULL_RTX
, false);
3109 RTL_CONST_CALL_P (insn
) = 1;
3110 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3111 insn
= get_insns ();
3118 /* Return a pseudo register that contains the current thread pointer. */
3121 mips_expand_thread_pointer (rtx tp
)
3127 if (!mips16_rdhwr_stub
)
3128 mips16_rdhwr_stub
= new mips16_rdhwr_one_only_stub ();
3129 fn
= mips16_stub_call_address (mips16_rdhwr_stub
);
3130 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3133 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3140 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3143 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3144 its address. The return value will be both a valid address and a valid
3145 SET_SRC (either a REG or a LO_SUM). */
3148 mips_legitimize_tls_address (rtx loc
)
3150 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3151 enum tls_model model
;
3153 model
= SYMBOL_REF_TLS_MODEL (loc
);
3154 /* Only TARGET_ABICALLS code can have more than one module; other
3155 code must be be static and should not use a GOT. All TLS models
3156 reduce to local exec in this situation. */
3157 if (!TARGET_ABICALLS
)
3158 model
= TLS_MODEL_LOCAL_EXEC
;
3162 case TLS_MODEL_GLOBAL_DYNAMIC
:
3163 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3164 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3165 dest
= gen_reg_rtx (Pmode
);
3166 emit_libcall_block (insn
, dest
, v0
, loc
);
3169 case TLS_MODEL_LOCAL_DYNAMIC
:
3170 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3171 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3172 tmp1
= gen_reg_rtx (Pmode
);
3174 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3175 share the LDM result with other LD model accesses. */
3176 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3178 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3180 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3181 if (mips_split_p
[SYMBOL_DTPREL
])
3183 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3184 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3187 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3188 0, 0, OPTAB_DIRECT
);
3191 case TLS_MODEL_INITIAL_EXEC
:
3192 tp
= mips_get_tp ();
3193 tmp1
= gen_reg_rtx (Pmode
);
3194 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3195 if (Pmode
== DImode
)
3196 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3198 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3199 dest
= gen_reg_rtx (Pmode
);
3200 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3203 case TLS_MODEL_LOCAL_EXEC
:
3204 tmp1
= mips_get_tp ();
3205 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3206 if (mips_split_p
[SYMBOL_TPREL
])
3208 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3209 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3212 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3213 0, 0, OPTAB_DIRECT
);
3222 /* If X is not a valid address for mode MODE, force it into a register. */
3225 mips_force_address (rtx x
, enum machine_mode mode
)
3227 if (!mips_legitimate_address_p (mode
, x
, false))
3228 x
= force_reg (Pmode
, x
);
3232 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3233 be legitimized in a way that the generic machinery might not expect,
3234 return a new address, otherwise return NULL. MODE is the mode of
3235 the memory being accessed. */
3238 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3239 enum machine_mode mode
)
3242 HOST_WIDE_INT offset
;
3244 if (mips_tls_symbol_p (x
))
3245 return mips_legitimize_tls_address (x
);
3247 /* See if the address can split into a high part and a LO_SUM. */
3248 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3249 return mips_force_address (addr
, mode
);
3251 /* Handle BASE + OFFSET using mips_add_offset. */
3252 mips_split_plus (x
, &base
, &offset
);
3255 if (!mips_valid_base_register_p (base
, mode
, false))
3256 base
= copy_to_mode_reg (Pmode
, base
);
3257 addr
= mips_add_offset (NULL
, base
, offset
);
3258 return mips_force_address (addr
, mode
);
3264 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3267 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3269 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3270 enum machine_mode mode
;
3271 unsigned int i
, num_ops
;
3274 mode
= GET_MODE (dest
);
3275 num_ops
= mips_build_integer (codes
, value
);
3277 /* Apply each binary operation to X. Invariant: X is a legitimate
3278 source operand for a SET pattern. */
3279 x
= GEN_INT (codes
[0].value
);
3280 for (i
= 1; i
< num_ops
; i
++)
3282 if (!can_create_pseudo_p ())
3284 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
3288 x
= force_reg (mode
, x
);
3289 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3292 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
3295 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3296 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3300 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
3304 /* Split moves of big integers into smaller pieces. */
3305 if (splittable_const_int_operand (src
, mode
))
3307 mips_move_integer (dest
, dest
, INTVAL (src
));
3311 /* Split moves of symbolic constants into high/low pairs. */
3312 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3314 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3318 /* Generate the appropriate access sequences for TLS symbols. */
3319 if (mips_tls_symbol_p (src
))
3321 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3325 /* If we have (const (plus symbol offset)), and that expression cannot
3326 be forced into memory, load the symbol first and add in the offset.
3327 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3328 forced into memory, as it usually produces better code. */
3329 split_const (src
, &base
, &offset
);
3330 if (offset
!= const0_rtx
3331 && (targetm
.cannot_force_const_mem (mode
, src
)
3332 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3334 base
= mips_force_temporary (dest
, base
);
3335 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3339 src
= force_const_mem (mode
, src
);
3341 /* When using explicit relocs, constant pool references are sometimes
3342 not legitimate addresses. */
3343 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3344 mips_emit_move (dest
, src
);
3347 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3348 sequence that is valid. */
3351 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
3353 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3355 mips_emit_move (dest
, force_reg (mode
, src
));
3359 /* We need to deal with constants that would be legitimate
3360 immediate_operands but aren't legitimate move_operands. */
3361 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3363 mips_legitimize_const_move (mode
, dest
, src
);
3364 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3370 /* Return true if value X in context CONTEXT is a small-data address
3371 that can be rewritten as a LO_SUM. */
3374 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3376 enum mips_symbol_type symbol_type
;
3378 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3379 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3380 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3381 && symbol_type
== SYMBOL_GP_RELATIVE
);
3384 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3385 containing MEM, or null if none. */
3388 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3390 enum mips_symbol_context context
;
3392 /* Ignore things like "g" constraints in asms. We make no particular
3393 guarantee about which symbolic constants are acceptable as asm operands
3394 versus which must be forced into a GPR. */
3395 if (GET_CODE (*loc
) == LO_SUM
|| GET_CODE (*loc
) == ASM_OPERANDS
)
3400 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3405 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3406 return mips_rewrite_small_data_p (*loc
, context
);
3409 /* Return true if OP refers to small data symbols directly, not through
3413 mips_small_data_pattern_p (rtx op
)
3415 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3418 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3419 DATA is the containing MEM, or null if none. */
3422 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3424 enum mips_symbol_context context
;
3428 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3432 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3433 if (mips_rewrite_small_data_p (*loc
, context
))
3434 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3436 if (GET_CODE (*loc
) == LO_SUM
)
3442 /* Rewrite instruction pattern PATTERN so that it refers to small data
3443 using explicit relocations. */
3446 mips_rewrite_small_data (rtx pattern
)
3448 pattern
= copy_insn (pattern
);
3449 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3453 /* The cost of loading values from the constant pool. It should be
3454 larger than the cost of any constant we want to synthesize inline. */
3455 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3457 /* Return the cost of X when used as an operand to the MIPS16 instruction
3458 that implements CODE. Return -1 if there is no such instruction, or if
3459 X is not a valid immediate operand for it. */
3462 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3469 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3470 other shifts are extended. The shift patterns truncate the shift
3471 count to the right size, so there are no out-of-range values. */
3472 if (IN_RANGE (x
, 1, 8))
3474 return COSTS_N_INSNS (1);
3477 if (IN_RANGE (x
, -128, 127))
3479 if (SMALL_OPERAND (x
))
3480 return COSTS_N_INSNS (1);
3484 /* Like LE, but reject the always-true case. */
3488 /* We add 1 to the immediate and use SLT. */
3491 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3494 if (IN_RANGE (x
, 0, 255))
3496 if (SMALL_OPERAND_UNSIGNED (x
))
3497 return COSTS_N_INSNS (1);
3502 /* Equality comparisons with 0 are cheap. */
3512 /* Return true if there is a non-MIPS16 instruction that implements CODE
3513 and if that instruction accepts X as an immediate operand. */
3516 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3523 /* All shift counts are truncated to a valid constant. */
3528 /* Likewise rotates, if the target supports rotates at all. */
3534 /* These instructions take 16-bit unsigned immediates. */
3535 return SMALL_OPERAND_UNSIGNED (x
);
3540 /* These instructions take 16-bit signed immediates. */
3541 return SMALL_OPERAND (x
);
3547 /* The "immediate" forms of these instructions are really
3548 implemented as comparisons with register 0. */
3553 /* Likewise, meaning that the only valid immediate operand is 1. */
3557 /* We add 1 to the immediate and use SLT. */
3558 return SMALL_OPERAND (x
+ 1);
3561 /* Likewise SLTU, but reject the always-true case. */
3562 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3566 /* The bit position and size are immediate operands. */
3567 return ISA_HAS_EXT_INS
;
3570 /* By default assume that $0 can be used for 0. */
3575 /* Return the cost of binary operation X, given that the instruction
3576 sequence for a word-sized or smaller operation has cost SINGLE_COST
3577 and that the sequence of a double-word operation has cost DOUBLE_COST.
3578 If SPEED is true, optimize for speed otherwise optimize for size. */
3581 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3585 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3590 + set_src_cost (XEXP (x
, 0), speed
)
3591 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3594 /* Return the cost of floating-point multiplications of mode MODE. */
3597 mips_fp_mult_cost (enum machine_mode mode
)
3599 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3602 /* Return the cost of floating-point divisions of mode MODE. */
3605 mips_fp_div_cost (enum machine_mode mode
)
3607 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3610 /* Return the cost of sign-extending OP to mode MODE, not including the
3611 cost of OP itself. */
3614 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3617 /* Extended loads are as cheap as unextended ones. */
3620 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3621 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3624 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3625 /* We can use SEB or SEH. */
3626 return COSTS_N_INSNS (1);
3628 /* We need to use a shift left and a shift right. */
3629 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3632 /* Return the cost of zero-extending OP to mode MODE, not including the
3633 cost of OP itself. */
3636 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3639 /* Extended loads are as cheap as unextended ones. */
3642 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3643 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3644 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3646 if (GENERATE_MIPS16E
)
3647 /* We can use ZEB or ZEH. */
3648 return COSTS_N_INSNS (1);
3651 /* We need to load 0xff or 0xffff into a register and use AND. */
3652 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3654 /* We can use ANDI. */
3655 return COSTS_N_INSNS (1);
3658 /* Return the cost of moving between two registers of mode MODE,
3659 assuming that the move will be in pieces of at most UNITS bytes. */
3662 mips_set_reg_reg_piece_cost (enum machine_mode mode
, unsigned int units
)
3664 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3667 /* Return the cost of moving between two registers of mode MODE. */
3670 mips_set_reg_reg_cost (enum machine_mode mode
)
3672 switch (GET_MODE_CLASS (mode
))
3675 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3678 case MODE_COMPLEX_FLOAT
:
3679 case MODE_VECTOR_FLOAT
:
3680 if (TARGET_HARD_FLOAT
)
3681 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3685 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3689 /* Implement TARGET_RTX_COSTS. */
3692 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3693 int *total
, bool speed
)
3695 enum machine_mode mode
= GET_MODE (x
);
3696 bool float_mode_p
= FLOAT_MODE_P (mode
);
3700 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3701 appear in the instruction stream, and the cost of a comparison is
3702 really the cost of the branch or scc condition. At the time of
3703 writing, GCC only uses an explicit outer COMPARE code when optabs
3704 is testing whether a constant is expensive enough to force into a
3705 register. We want optabs to pass such constants through the MIPS
3706 expanders instead, so make all constants very cheap here. */
3707 if (outer_code
== COMPARE
)
3709 gcc_assert (CONSTANT_P (x
));
3717 /* Treat *clear_upper32-style ANDs as having zero cost in the
3718 second operand. The cost is entirely in the first operand.
3720 ??? This is needed because we would otherwise try to CSE
3721 the constant operand. Although that's the right thing for
3722 instructions that continue to be a register operation throughout
3723 compilation, it is disastrous for instructions that could
3724 later be converted into a memory operation. */
3726 && outer_code
== AND
3727 && UINTVAL (x
) == 0xffffffff)
3735 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3744 /* When not optimizing for size, we care more about the cost
3745 of hot code, and hot code is often in a loop. If a constant
3746 operand needs to be forced into a register, we will often be
3747 able to hoist the constant load out of the loop, so the load
3748 should not contribute to the cost. */
3749 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3761 if (force_to_mem_operand (x
, VOIDmode
))
3763 *total
= COSTS_N_INSNS (1);
3766 cost
= mips_const_insns (x
);
3769 /* If the constant is likely to be stored in a GPR, SETs of
3770 single-insn constants are as cheap as register sets; we
3771 never want to CSE them.
3773 Don't reduce the cost of storing a floating-point zero in
3774 FPRs. If we have a zero in an FPR for other reasons, we
3775 can get better cfg-cleanup and delayed-branch results by
3776 using it consistently, rather than using $0 sometimes and
3777 an FPR at other times. Also, moves between floating-point
3778 registers are sometimes cheaper than (D)MTC1 $0. */
3780 && outer_code
== SET
3781 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3783 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3784 want to CSE the constant itself. It is usually better to
3785 have N copies of the last operation in the sequence and one
3786 shared copy of the other operations. (Note that this is
3787 not true for MIPS16 code, where the final operation in the
3788 sequence is often an extended instruction.)
3790 Also, if we have a CONST_INT, we don't know whether it is
3791 for a word or doubleword operation, so we cannot rely on
3792 the result of mips_build_integer. */
3793 else if (!TARGET_MIPS16
3794 && (outer_code
== SET
|| mode
== VOIDmode
))
3796 *total
= COSTS_N_INSNS (cost
);
3799 /* The value will need to be fetched from the constant pool. */
3800 *total
= CONSTANT_POOL_COST
;
3804 /* If the address is legitimate, return the number of
3805 instructions it needs. */
3807 cost
= mips_address_insns (addr
, mode
, true);
3810 *total
= COSTS_N_INSNS (cost
+ 1);
3813 /* Check for a scaled indexed address. */
3814 if (mips_lwxs_address_p (addr
)
3815 || mips_lx_address_p (addr
, mode
))
3817 *total
= COSTS_N_INSNS (2);
3820 /* Otherwise use the default handling. */
3824 *total
= COSTS_N_INSNS (6);
3828 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3832 /* Check for a *clear_upper32 pattern and treat it like a zero
3833 extension. See the pattern's comment for details. */
3836 && CONST_INT_P (XEXP (x
, 1))
3837 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3839 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3840 + set_src_cost (XEXP (x
, 0), speed
));
3843 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
3845 rtx op
= XEXP (x
, 0);
3846 if (GET_CODE (op
) == ASHIFT
3847 && CONST_INT_P (XEXP (op
, 1))
3848 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
3850 *total
= COSTS_N_INSNS (1) + set_src_cost (XEXP (op
, 0), speed
);
3854 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3855 a single instruction. */
3857 && GET_CODE (XEXP (x
, 0)) == NOT
3858 && GET_CODE (XEXP (x
, 1)) == NOT
)
3860 cost
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1;
3861 *total
= (COSTS_N_INSNS (cost
)
3862 + set_src_cost (XEXP (XEXP (x
, 0), 0), speed
)
3863 + set_src_cost (XEXP (XEXP (x
, 1), 0), speed
));
3871 /* Double-word operations use two single-word operations. */
3872 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3881 if (CONSTANT_P (XEXP (x
, 1)))
3882 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3885 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3891 *total
= mips_cost
->fp_add
;
3893 *total
= COSTS_N_INSNS (4);
3897 /* Low-part immediates need an extended MIPS16 instruction. */
3898 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3899 + set_src_cost (XEXP (x
, 0), speed
));
3914 /* Branch comparisons have VOIDmode, so use the first operand's
3916 mode
= GET_MODE (XEXP (x
, 0));
3917 if (FLOAT_MODE_P (mode
))
3919 *total
= mips_cost
->fp_add
;
3922 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3928 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
3929 && TARGET_FUSED_MADD
3930 && !HONOR_NANS (mode
)
3931 && !HONOR_SIGNED_ZEROS (mode
))
3933 /* See if we can use NMADD or NMSUB. See mips.md for the
3934 associated patterns. */
3935 rtx op0
= XEXP (x
, 0);
3936 rtx op1
= XEXP (x
, 1);
3937 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3939 *total
= (mips_fp_mult_cost (mode
)
3940 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
3941 + set_src_cost (XEXP (op0
, 1), speed
)
3942 + set_src_cost (op1
, speed
));
3945 if (GET_CODE (op1
) == MULT
)
3947 *total
= (mips_fp_mult_cost (mode
)
3948 + set_src_cost (op0
, speed
)
3949 + set_src_cost (XEXP (op1
, 0), speed
)
3950 + set_src_cost (XEXP (op1
, 1), speed
));
3959 /* If this is part of a MADD or MSUB, treat the PLUS as
3961 if ((ISA_HAS_FP_MADD4_MSUB4
|| ISA_HAS_FP_MADD3_MSUB3
)
3962 && TARGET_FUSED_MADD
3963 && GET_CODE (XEXP (x
, 0)) == MULT
)
3966 *total
= mips_cost
->fp_add
;
3970 /* Double-word operations require three single-word operations and
3971 an SLTU. The MIPS16 version then needs to move the result of
3972 the SLTU from $24 to a MIPS16 register. */
3973 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3974 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
3980 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
3981 && TARGET_FUSED_MADD
3982 && !HONOR_NANS (mode
)
3983 && HONOR_SIGNED_ZEROS (mode
))
3985 /* See if we can use NMADD or NMSUB. See mips.md for the
3986 associated patterns. */
3987 rtx op
= XEXP (x
, 0);
3988 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3989 && GET_CODE (XEXP (op
, 0)) == MULT
)
3991 *total
= (mips_fp_mult_cost (mode
)
3992 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
3993 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
3994 + set_src_cost (XEXP (op
, 1), speed
));
4000 *total
= mips_cost
->fp_add
;
4002 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
4007 *total
= mips_fp_mult_cost (mode
);
4008 else if (mode
== DImode
&& !TARGET_64BIT
)
4009 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4010 where the mulsidi3 always includes an MFHI and an MFLO. */
4012 ? mips_cost
->int_mult_si
* 3 + 6
4013 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
4015 *total
= COSTS_N_INSNS (ISA_HAS_MUL3
? 1 : 2) + 1;
4016 else if (mode
== DImode
)
4017 *total
= mips_cost
->int_mult_di
;
4019 *total
= mips_cost
->int_mult_si
;
4023 /* Check for a reciprocal. */
4025 && ISA_HAS_FP_RECIP_RSQRT (mode
)
4026 && flag_unsafe_math_optimizations
4027 && XEXP (x
, 0) == CONST1_RTX (mode
))
4029 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
4030 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4031 division as being free. */
4032 *total
= set_src_cost (XEXP (x
, 1), speed
);
4034 *total
= (mips_fp_div_cost (mode
)
4035 + set_src_cost (XEXP (x
, 1), speed
));
4044 *total
= mips_fp_div_cost (mode
);
4053 /* It is our responsibility to make division by a power of 2
4054 as cheap as 2 register additions if we want the division
4055 expanders to be used for such operations; see the setting
4056 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4057 should always produce shorter code than using
4058 expand_sdiv2_pow2. */
4060 && CONST_INT_P (XEXP (x
, 1))
4061 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
4063 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
4066 *total
= COSTS_N_INSNS (mips_idiv_insns ());
4068 else if (mode
== DImode
)
4069 *total
= mips_cost
->int_div_di
;
4071 *total
= mips_cost
->int_div_si
;
4075 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
4079 if (outer_code
== SET
4081 && (GET_CODE (XEXP (x
, 0)) == TRUNCATE
4082 || GET_CODE (XEXP (x
, 0)) == SUBREG
)
4083 && GET_MODE (XEXP (x
, 0)) == QImode
4084 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4086 *total
= set_src_cost (XEXP (XEXP (x
, 0), 0), speed
);
4089 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4093 case UNSIGNED_FLOAT
:
4096 case FLOAT_TRUNCATE
:
4097 *total
= mips_cost
->fp_add
;
4101 if (register_operand (SET_DEST (x
), VOIDmode
)
4102 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4104 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4114 /* Implement TARGET_ADDRESS_COST. */
4117 mips_address_cost (rtx addr
, enum machine_mode mode
,
4118 addr_space_t as ATTRIBUTE_UNUSED
,
4119 bool speed ATTRIBUTE_UNUSED
)
4121 return mips_address_insns (addr
, mode
, false);
4124 /* Information about a single instruction in a multi-instruction
4126 struct mips_multi_member
{
4127 /* True if this is a label, false if it is code. */
4130 /* The output_asm_insn format of the instruction. */
4133 /* The operands to the instruction. */
4134 rtx operands
[MAX_RECOG_OPERANDS
];
4136 typedef struct mips_multi_member mips_multi_member
;
4138 /* The instructions that make up the current multi-insn sequence. */
4139 static vec
<mips_multi_member
> mips_multi_members
;
4141 /* How many instructions (as opposed to labels) are in the current
4142 multi-insn sequence. */
4143 static unsigned int mips_multi_num_insns
;
4145 /* Start a new multi-insn sequence. */
4148 mips_multi_start (void)
4150 mips_multi_members
.truncate (0);
4151 mips_multi_num_insns
= 0;
4154 /* Add a new, uninitialized member to the current multi-insn sequence. */
4156 static struct mips_multi_member
*
4157 mips_multi_add (void)
4159 mips_multi_member empty
;
4160 return mips_multi_members
.safe_push (empty
);
4163 /* Add a normal insn with the given asm format to the current multi-insn
4164 sequence. The other arguments are a null-terminated list of operands. */
4167 mips_multi_add_insn (const char *format
, ...)
4169 struct mips_multi_member
*member
;
4174 member
= mips_multi_add ();
4175 member
->is_label_p
= false;
4176 member
->format
= format
;
4177 va_start (ap
, format
);
4179 while ((op
= va_arg (ap
, rtx
)))
4180 member
->operands
[i
++] = op
;
4182 mips_multi_num_insns
++;
4185 /* Add the given label definition to the current multi-insn sequence.
4186 The definition should include the colon. */
4189 mips_multi_add_label (const char *label
)
4191 struct mips_multi_member
*member
;
4193 member
= mips_multi_add ();
4194 member
->is_label_p
= true;
4195 member
->format
= label
;
4198 /* Return the index of the last member of the current multi-insn sequence. */
4201 mips_multi_last_index (void)
4203 return mips_multi_members
.length () - 1;
4206 /* Add a copy of an existing instruction to the current multi-insn
4207 sequence. I is the index of the instruction that should be copied. */
4210 mips_multi_copy_insn (unsigned int i
)
4212 struct mips_multi_member
*member
;
4214 member
= mips_multi_add ();
4215 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4216 gcc_assert (!member
->is_label_p
);
4219 /* Change the operand of an existing instruction in the current
4220 multi-insn sequence. I is the index of the instruction,
4221 OP is the index of the operand, and X is the new value. */
4224 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4226 mips_multi_members
[i
].operands
[op
] = x
;
4229 /* Write out the asm code for the current multi-insn sequence. */
4232 mips_multi_write (void)
4234 struct mips_multi_member
*member
;
4237 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4238 if (member
->is_label_p
)
4239 fprintf (asm_out_file
, "%s\n", member
->format
);
4241 output_asm_insn (member
->format
, member
->operands
);
4244 /* Return one word of double-word value OP, taking into account the fixed
4245 endianness of certain registers. HIGH_P is true to select the high part,
4246 false to select the low part. */
4249 mips_subword (rtx op
, bool high_p
)
4251 unsigned int byte
, offset
;
4252 enum machine_mode mode
;
4254 mode
= GET_MODE (op
);
4255 if (mode
== VOIDmode
)
4256 mode
= TARGET_64BIT
? TImode
: DImode
;
4258 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4259 byte
= UNITS_PER_WORD
;
4263 if (FP_REG_RTX_P (op
))
4265 /* Paired FPRs are always ordered little-endian. */
4266 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4267 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4271 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4273 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4276 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4277 SPLIT_TYPE is the condition under which moves should be split. */
4280 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4282 return ((split_type
!= SPLIT_FOR_SPEED
4283 || mips_tuning_info
.fast_mult_zero_zero_p
)
4284 && src
== const0_rtx
4286 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4287 && (ISA_HAS_DSP_MULT
4288 ? ACC_REG_P (REGNO (dest
))
4289 : MD_REG_P (REGNO (dest
))));
4292 /* Return true if a move from SRC to DEST should be split into two.
4293 SPLIT_TYPE describes the split condition. */
4296 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4298 /* Check whether the move can be done using some variant of MULT $0,$0. */
4299 if (mips_mult_move_p (dest
, src
, split_type
))
4302 /* FPR-to-FPR moves can be done in a single instruction, if they're
4304 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4305 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4308 /* Check for floating-point loads and stores. */
4309 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4311 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4313 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4317 /* Otherwise split all multiword moves. */
4318 return size
> UNITS_PER_WORD
;
4321 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4322 SPLIT_TYPE describes the split condition. */
4325 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4329 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4330 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4332 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4333 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4334 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4335 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4336 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4337 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4338 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4339 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4340 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4341 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4342 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4343 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4344 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4345 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4349 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4351 low_dest
= mips_subword (dest
, false);
4352 mips_emit_move (low_dest
, mips_subword (src
, false));
4354 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4356 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4358 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4360 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4362 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4364 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4368 /* The operation can be split into two normal moves. Decide in
4369 which order to do them. */
4370 low_dest
= mips_subword (dest
, false);
4371 if (REG_P (low_dest
)
4372 && reg_overlap_mentioned_p (low_dest
, src
))
4374 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4375 mips_emit_move (low_dest
, mips_subword (src
, false));
4379 mips_emit_move (low_dest
, mips_subword (src
, false));
4380 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4385 /* Return the split type for instruction INSN. */
4387 static enum mips_split_type
4388 mips_insn_split_type (rtx insn
)
4390 basic_block bb
= BLOCK_FOR_INSN (insn
);
4393 if (optimize_bb_for_speed_p (bb
))
4394 return SPLIT_FOR_SPEED
;
4396 return SPLIT_FOR_SIZE
;
4398 /* Once CFG information has been removed, we should trust the optimization
4399 decisions made by previous passes and only split where necessary. */
4400 return SPLIT_IF_NECESSARY
;
4403 /* Return true if a move from SRC to DEST in INSN should be split. */
4406 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
4408 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
4411 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4415 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
4417 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
4420 /* Return the appropriate instructions to move SRC into DEST. Assume
4421 that SRC is operand 1 and DEST is operand 0. */
4424 mips_output_move (rtx dest
, rtx src
)
4426 enum rtx_code dest_code
, src_code
;
4427 enum machine_mode mode
;
4428 enum mips_symbol_type symbol_type
;
4431 dest_code
= GET_CODE (dest
);
4432 src_code
= GET_CODE (src
);
4433 mode
= GET_MODE (dest
);
4434 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4436 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4439 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4440 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4442 if (dest_code
== REG
)
4444 if (GP_REG_P (REGNO (dest
)))
4445 return "move\t%0,%z1";
4447 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4449 if (ISA_HAS_DSP_MULT
)
4450 return "mult\t%q0,%.,%.";
4452 return "mult\t%.,%.";
4455 /* Moves to HI are handled by special .md insns. */
4456 if (REGNO (dest
) == LO_REGNUM
)
4459 if (DSP_ACC_REG_P (REGNO (dest
)))
4461 static char retval
[] = "mt__\t%z1,%q0";
4463 retval
[2] = reg_names
[REGNO (dest
)][4];
4464 retval
[3] = reg_names
[REGNO (dest
)][5];
4468 if (FP_REG_P (REGNO (dest
)))
4469 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4471 if (ALL_COP_REG_P (REGNO (dest
)))
4473 static char retval
[] = "dmtc_\t%z1,%0";
4475 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4476 return dbl_p
? retval
: retval
+ 1;
4479 if (dest_code
== MEM
)
4480 switch (GET_MODE_SIZE (mode
))
4482 case 1: return "sb\t%z1,%0";
4483 case 2: return "sh\t%z1,%0";
4484 case 4: return "sw\t%z1,%0";
4485 case 8: return "sd\t%z1,%0";
4488 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4490 if (src_code
== REG
)
4492 /* Moves from HI are handled by special .md insns. */
4493 if (REGNO (src
) == LO_REGNUM
)
4495 /* When generating VR4120 or VR4130 code, we use MACC and
4496 DMACC instead of MFLO. This avoids both the normal
4497 MIPS III HI/LO hazards and the errata related to
4500 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4504 if (DSP_ACC_REG_P (REGNO (src
)))
4506 static char retval
[] = "mf__\t%0,%q1";
4508 retval
[2] = reg_names
[REGNO (src
)][4];
4509 retval
[3] = reg_names
[REGNO (src
)][5];
4513 if (FP_REG_P (REGNO (src
)))
4514 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4516 if (ALL_COP_REG_P (REGNO (src
)))
4518 static char retval
[] = "dmfc_\t%0,%1";
4520 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4521 return dbl_p
? retval
: retval
+ 1;
4525 if (src_code
== MEM
)
4526 switch (GET_MODE_SIZE (mode
))
4528 case 1: return "lbu\t%0,%1";
4529 case 2: return "lhu\t%0,%1";
4530 case 4: return "lw\t%0,%1";
4531 case 8: return "ld\t%0,%1";
4534 if (src_code
== CONST_INT
)
4536 /* Don't use the X format for the operand itself, because that
4537 will give out-of-range numbers for 64-bit hosts and 32-bit
4540 return "li\t%0,%1\t\t\t# %X1";
4542 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4545 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4549 if (src_code
== HIGH
)
4550 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4552 if (CONST_GP_P (src
))
4553 return "move\t%0,%1";
4555 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4556 && mips_lo_relocs
[symbol_type
] != 0)
4558 /* A signed 16-bit constant formed by applying a relocation
4559 operator to a symbolic address. */
4560 gcc_assert (!mips_split_p
[symbol_type
]);
4561 return "li\t%0,%R1";
4564 if (symbolic_operand (src
, VOIDmode
))
4566 gcc_assert (TARGET_MIPS16
4567 ? TARGET_MIPS16_TEXT_LOADS
4568 : !TARGET_EXPLICIT_RELOCS
);
4569 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4572 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4574 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4576 if (GET_MODE (dest
) == V2SFmode
)
4577 return "mov.ps\t%0,%1";
4579 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4582 if (dest_code
== MEM
)
4583 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4585 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4587 if (src_code
== MEM
)
4588 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4590 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4592 static char retval
[] = "l_c_\t%0,%1";
4594 retval
[1] = (dbl_p
? 'd' : 'w');
4595 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4598 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4600 static char retval
[] = "s_c_\t%1,%0";
4602 retval
[1] = (dbl_p
? 'd' : 'w');
4603 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4609 /* Return true if CMP1 is a suitable second operand for integer ordering
4610 test CODE. See also the *sCC patterns in mips.md. */
4613 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4619 return reg_or_0_operand (cmp1
, VOIDmode
);
4623 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4627 return arith_operand (cmp1
, VOIDmode
);
4630 return sle_operand (cmp1
, VOIDmode
);
4633 return sleu_operand (cmp1
, VOIDmode
);
4640 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4641 integer ordering test *CODE, or if an equivalent combination can
4642 be formed by adjusting *CODE and *CMP1. When returning true, update
4643 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4647 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4648 enum machine_mode mode
)
4650 HOST_WIDE_INT plus_one
;
4652 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4655 if (CONST_INT_P (*cmp1
))
4659 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4660 if (INTVAL (*cmp1
) < plus_one
)
4663 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4669 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4673 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4684 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4685 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4686 is nonnull, it's OK to set TARGET to the inverse of the result and
4687 flip *INVERT_PTR instead. */
4690 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4691 rtx target
, rtx cmp0
, rtx cmp1
)
4693 enum machine_mode mode
;
4695 /* First see if there is a MIPS instruction that can do this operation.
4696 If not, try doing the same for the inverse operation. If that also
4697 fails, force CMP1 into a register and try again. */
4698 mode
= GET_MODE (cmp0
);
4699 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4700 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4703 enum rtx_code inv_code
= reverse_condition (code
);
4704 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4706 cmp1
= force_reg (mode
, cmp1
);
4707 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4709 else if (invert_ptr
== 0)
4713 inv_target
= mips_force_binary (GET_MODE (target
),
4714 inv_code
, cmp0
, cmp1
);
4715 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4719 *invert_ptr
= !*invert_ptr
;
4720 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4725 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4726 The register will have the same mode as CMP0. */
4729 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4731 if (cmp1
== const0_rtx
)
4734 if (uns_arith_operand (cmp1
, VOIDmode
))
4735 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4736 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4738 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4739 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4742 /* Convert *CODE into a code that can be used in a floating-point
4743 scc instruction (C.cond.fmt). Return true if the values of
4744 the condition code registers will be inverted, with 0 indicating
4745 that the condition holds. */
4748 mips_reversed_fp_cond (enum rtx_code
*code
)
4755 *code
= reverse_condition_maybe_unordered (*code
);
4763 /* Allocate a floating-point condition-code register of mode MODE.
4765 These condition code registers are used for certain kinds
4766 of compound operation, such as compare and branches, vconds,
4767 and built-in functions. At expand time, their use is entirely
4768 controlled by MIPS-specific code and is entirely internal
4769 to these compound operations.
4771 We could (and did in the past) expose condition-code values
4772 as pseudo registers and leave the register allocator to pick
4773 appropriate registers. The problem is that it is not practically
4774 possible for the rtl optimizers to guarantee that no spills will
4775 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4776 therefore need spill and reload sequences to handle the worst case.
4778 Although such sequences do exist, they are very expensive and are
4779 not something we'd want to use. This is especially true of CCV2 and
4780 CCV4, where all the shuffling would greatly outweigh whatever benefit
4781 the vectorization itself provides.
4783 The main benefit of having more than one condition-code register
4784 is to allow the pipelining of operations, especially those involving
4785 comparisons and conditional moves. We don't really expect the
4786 registers to be live for long periods, and certainly never want
4787 them to be live across calls.
4789 Also, there should be no penalty attached to using all the available
4790 registers. They are simply bits in the same underlying FPU control
4793 We therefore expose the hardware registers from the outset and use
4794 a simple round-robin allocation scheme. */
4797 mips_allocate_fcc (enum machine_mode mode
)
4799 unsigned int regno
, count
;
4801 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
4805 else if (mode
== CCV2mode
)
4807 else if (mode
== CCV4mode
)
4812 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
4813 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
4814 cfun
->machine
->next_fcc
= 0;
4815 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
4816 cfun
->machine
->next_fcc
+= count
;
4817 return gen_rtx_REG (mode
, regno
);
4820 /* Convert a comparison into something that can be used in a branch or
4821 conditional move. On entry, *OP0 and *OP1 are the values being
4822 compared and *CODE is the code used to compare them.
4824 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4825 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4826 otherwise any standard branch condition can be used. The standard branch
4829 - EQ or NE between two registers.
4830 - any comparison between a register and zero. */
4833 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4838 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4840 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4842 else if (*code
== EQ
|| *code
== NE
)
4846 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4850 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4854 /* The comparison needs a separate scc instruction. Store the
4855 result of the scc in *OP0 and compare it against zero. */
4856 bool invert
= false;
4857 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4858 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4859 *code
= (invert
? EQ
: NE
);
4863 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4865 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4866 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4872 enum rtx_code cmp_code
;
4874 /* Floating-point tests use a separate C.cond.fmt comparison to
4875 set a condition code register. The branch or conditional move
4876 will then compare that register against zero.
4878 Set CMP_CODE to the code of the comparison instruction and
4879 *CODE to the code that the branch or move should use. */
4881 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4883 ? mips_allocate_fcc (CCmode
)
4884 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4886 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4890 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4891 and OPERAND[3]. Store the result in OPERANDS[0].
4893 On 64-bit targets, the mode of the comparison and target will always be
4894 SImode, thus possibly narrower than that of the comparison's operands. */
4897 mips_expand_scc (rtx operands
[])
4899 rtx target
= operands
[0];
4900 enum rtx_code code
= GET_CODE (operands
[1]);
4901 rtx op0
= operands
[2];
4902 rtx op1
= operands
[3];
4904 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
4906 if (code
== EQ
|| code
== NE
)
4909 && reg_imm10_operand (op1
, GET_MODE (op1
)))
4910 mips_emit_binary (code
, target
, op0
, op1
);
4913 rtx zie
= mips_zero_if_equal (op0
, op1
);
4914 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4918 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
4921 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4922 CODE and jump to OPERANDS[3] if the condition holds. */
4925 mips_expand_conditional_branch (rtx
*operands
)
4927 enum rtx_code code
= GET_CODE (operands
[0]);
4928 rtx op0
= operands
[1];
4929 rtx op1
= operands
[2];
4932 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
4933 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
4934 emit_jump_insn (gen_condjump (condition
, operands
[3]));
4939 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4940 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4943 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
4944 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
4949 reversed_p
= mips_reversed_fp_cond (&cond
);
4950 cmp_result
= mips_allocate_fcc (CCV2mode
);
4951 emit_insn (gen_scc_ps (cmp_result
,
4952 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
4954 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
4957 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
4961 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4962 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4965 mips_expand_conditional_move (rtx
*operands
)
4968 enum rtx_code code
= GET_CODE (operands
[1]);
4969 rtx op0
= XEXP (operands
[1], 0);
4970 rtx op1
= XEXP (operands
[1], 1);
4972 mips_emit_compare (&code
, &op0
, &op1
, true);
4973 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
4974 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
4975 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
4976 operands
[2], operands
[3])));
4979 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4982 mips_expand_conditional_trap (rtx comparison
)
4985 enum machine_mode mode
;
4988 /* MIPS conditional trap instructions don't have GT or LE flavors,
4989 so we must swap the operands and convert to LT and GE respectively. */
4990 code
= GET_CODE (comparison
);
4997 code
= swap_condition (code
);
4998 op0
= XEXP (comparison
, 1);
4999 op1
= XEXP (comparison
, 0);
5003 op0
= XEXP (comparison
, 0);
5004 op1
= XEXP (comparison
, 1);
5008 mode
= GET_MODE (XEXP (comparison
, 0));
5009 op0
= force_reg (mode
, op0
);
5010 if (!arith_operand (op1
, mode
))
5011 op1
= force_reg (mode
, op1
);
5013 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
5014 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
5018 /* Initialize *CUM for a call to a function of type FNTYPE. */
5021 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
5023 memset (cum
, 0, sizeof (*cum
));
5024 cum
->prototype
= (fntype
&& prototype_p (fntype
));
5025 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
5028 /* Fill INFO with information about a single argument. CUM is the
5029 cumulative state for earlier arguments. MODE is the mode of this
5030 argument and TYPE is its type (if known). NAMED is true if this
5031 is a named (fixed) argument rather than a variable one. */
5034 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
5035 enum machine_mode mode
, const_tree type
, bool named
)
5037 bool doubleword_aligned_p
;
5038 unsigned int num_bytes
, num_words
, max_regs
;
5040 /* Work out the size of the argument. */
5041 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5042 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5044 /* Decide whether it should go in a floating-point register, assuming
5045 one is free. Later code checks for availability.
5047 The checks against UNITS_PER_FPVALUE handle the soft-float and
5048 single-float cases. */
5052 /* The EABI conventions have traditionally been defined in terms
5053 of TYPE_MODE, regardless of the actual type. */
5054 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5055 || mode
== V2SFmode
)
5056 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5061 /* Only leading floating-point scalars are passed in
5062 floating-point registers. We also handle vector floats the same
5063 say, which is OK because they are not covered by the standard ABI. */
5064 info
->fpr_p
= (!cum
->gp_reg_found
5065 && cum
->arg_number
< 2
5067 || SCALAR_FLOAT_TYPE_P (type
)
5068 || VECTOR_FLOAT_TYPE_P (type
))
5069 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5070 || mode
== V2SFmode
)
5071 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5076 /* Scalar, complex and vector floating-point types are passed in
5077 floating-point registers, as long as this is a named rather
5078 than a variable argument. */
5079 info
->fpr_p
= (named
5080 && (type
== 0 || FLOAT_TYPE_P (type
))
5081 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5082 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5083 || mode
== V2SFmode
)
5084 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5086 /* ??? According to the ABI documentation, the real and imaginary
5087 parts of complex floats should be passed in individual registers.
5088 The real and imaginary parts of stack arguments are supposed
5089 to be contiguous and there should be an extra word of padding
5092 This has two problems. First, it makes it impossible to use a
5093 single "void *" va_list type, since register and stack arguments
5094 are passed differently. (At the time of writing, MIPSpro cannot
5095 handle complex float varargs correctly.) Second, it's unclear
5096 what should happen when there is only one register free.
5098 For now, we assume that named complex floats should go into FPRs
5099 if there are two FPRs free, otherwise they should be passed in the
5100 same way as a struct containing two floats. */
5102 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5103 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5105 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5106 info
->fpr_p
= false;
5116 /* See whether the argument has doubleword alignment. */
5117 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5120 /* Set REG_OFFSET to the register count we're interested in.
5121 The EABI allocates the floating-point registers separately,
5122 but the other ABIs allocate them like integer registers. */
5123 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5127 /* Advance to an even register if the argument is doubleword-aligned. */
5128 if (doubleword_aligned_p
)
5129 info
->reg_offset
+= info
->reg_offset
& 1;
5131 /* Work out the offset of a stack argument. */
5132 info
->stack_offset
= cum
->stack_words
;
5133 if (doubleword_aligned_p
)
5134 info
->stack_offset
+= info
->stack_offset
& 1;
5136 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5138 /* Partition the argument between registers and stack. */
5139 info
->reg_words
= MIN (num_words
, max_regs
);
5140 info
->stack_words
= num_words
- info
->reg_words
;
5143 /* INFO describes a register argument that has the normal format for the
5144 argument's mode. Return the register it uses, assuming that FPRs are
5145 available if HARD_FLOAT_P. */
5148 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5150 if (!info
->fpr_p
|| !hard_float_p
)
5151 return GP_ARG_FIRST
+ info
->reg_offset
;
5152 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5153 /* In o32, the second argument is always passed in $f14
5154 for TARGET_DOUBLE_FLOAT, regardless of whether the
5155 first argument was a word or doubleword. */
5156 return FP_ARG_FIRST
+ 2;
5158 return FP_ARG_FIRST
+ info
->reg_offset
;
5161 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5164 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5166 return !TARGET_OLDABI
;
5169 /* Implement TARGET_FUNCTION_ARG. */
5172 mips_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
5173 const_tree type
, bool named
)
5175 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5176 struct mips_arg_info info
;
5178 /* We will be called with a mode of VOIDmode after the last argument
5179 has been seen. Whatever we return will be passed to the call expander.
5180 If we need a MIPS16 fp_code, return a REG with the code stored as
5182 if (mode
== VOIDmode
)
5184 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5185 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
5190 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5192 /* Return straight away if the whole argument is passed on the stack. */
5193 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5196 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5197 contains a double in its entirety, then that 64-bit chunk is passed
5198 in a floating-point register. */
5200 && TARGET_HARD_FLOAT
5203 && TREE_CODE (type
) == RECORD_TYPE
5204 && TYPE_SIZE_UNIT (type
)
5205 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
5209 /* First check to see if there is any such field. */
5210 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5211 if (TREE_CODE (field
) == FIELD_DECL
5212 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5213 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5214 && tree_fits_shwi_p (bit_position (field
))
5215 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5220 /* Now handle the special case by returning a PARALLEL
5221 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5222 chunks are passed in registers. */
5224 HOST_WIDE_INT bitpos
;
5227 /* assign_parms checks the mode of ENTRY_PARM, so we must
5228 use the actual mode here. */
5229 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5232 field
= TYPE_FIELDS (type
);
5233 for (i
= 0; i
< info
.reg_words
; i
++)
5237 for (; field
; field
= DECL_CHAIN (field
))
5238 if (TREE_CODE (field
) == FIELD_DECL
5239 && int_bit_position (field
) >= bitpos
)
5243 && int_bit_position (field
) == bitpos
5244 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5245 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5246 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5248 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
5251 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5252 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5254 bitpos
+= BITS_PER_WORD
;
5260 /* Handle the n32/n64 conventions for passing complex floating-point
5261 arguments in FPR pairs. The real part goes in the lower register
5262 and the imaginary part goes in the upper register. */
5265 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5268 enum machine_mode inner
;
5271 inner
= GET_MODE_INNER (mode
);
5272 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
5273 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
5275 /* Real part in registers, imaginary part on stack. */
5276 gcc_assert (info
.stack_words
== info
.reg_words
);
5277 return gen_rtx_REG (inner
, regno
);
5281 gcc_assert (info
.stack_words
== 0);
5282 real
= gen_rtx_EXPR_LIST (VOIDmode
,
5283 gen_rtx_REG (inner
, regno
),
5285 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
5287 regno
+ info
.reg_words
/ 2),
5288 GEN_INT (GET_MODE_SIZE (inner
)));
5289 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
5293 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
5296 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5299 mips_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
5300 const_tree type
, bool named
)
5302 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5303 struct mips_arg_info info
;
5305 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5308 cum
->gp_reg_found
= true;
5310 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5311 an explanation of what this code does. It assumes that we're using
5312 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5314 if (cum
->arg_number
< 2 && info
.fpr_p
)
5315 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5317 /* Advance the register count. This has the effect of setting
5318 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5319 argument required us to skip the final GPR and pass the whole
5320 argument on the stack. */
5321 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5322 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5323 else if (info
.reg_words
> 0)
5324 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5326 /* Advance the stack word count. */
5327 if (info
.stack_words
> 0)
5328 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5333 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5336 mips_arg_partial_bytes (cumulative_args_t cum
,
5337 enum machine_mode mode
, tree type
, bool named
)
5339 struct mips_arg_info info
;
5341 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5342 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5345 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5346 least PARM_BOUNDARY bits of alignment, but will be given anything up
5347 to STACK_BOUNDARY bits if the type requires it. */
5350 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5352 unsigned int alignment
;
5354 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5355 if (alignment
< PARM_BOUNDARY
)
5356 alignment
= PARM_BOUNDARY
;
5357 if (alignment
> STACK_BOUNDARY
)
5358 alignment
= STACK_BOUNDARY
;
5362 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5363 upward rather than downward. In other words, return true if the
5364 first byte of the stack slot has useful data, false if the last
5368 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
5370 /* On little-endian targets, the first byte of every stack argument
5371 is passed in the first byte of the stack slot. */
5372 if (!BYTES_BIG_ENDIAN
)
5375 /* Otherwise, integral types are padded downward: the last byte of a
5376 stack argument is passed in the last byte of the stack slot. */
5378 ? (INTEGRAL_TYPE_P (type
)
5379 || POINTER_TYPE_P (type
)
5380 || FIXED_POINT_TYPE_P (type
))
5381 : (SCALAR_INT_MODE_P (mode
)
5382 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5385 /* Big-endian o64 pads floating-point arguments downward. */
5386 if (mips_abi
== ABI_O64
)
5387 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5390 /* Other types are padded upward for o32, o64, n32 and n64. */
5391 if (mips_abi
!= ABI_EABI
)
5394 /* Arguments smaller than a stack slot are padded downward. */
5395 if (mode
!= BLKmode
)
5396 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5398 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5401 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5402 if the least significant byte of the register has useful data. Return
5403 the opposite if the most significant byte does. */
5406 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
5408 /* No shifting is required for floating-point arguments. */
5409 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5410 return !BYTES_BIG_ENDIAN
;
5412 /* Otherwise, apply the same padding to register arguments as we do
5413 to stack arguments. */
5414 return mips_pad_arg_upward (mode
, type
);
5417 /* Return nonzero when an argument must be passed by reference. */
5420 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5421 enum machine_mode mode
, const_tree type
,
5422 bool named ATTRIBUTE_UNUSED
)
5424 if (mips_abi
== ABI_EABI
)
5428 /* ??? How should SCmode be handled? */
5429 if (mode
== DImode
|| mode
== DFmode
5430 || mode
== DQmode
|| mode
== UDQmode
5431 || mode
== DAmode
|| mode
== UDAmode
)
5434 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5435 return size
== -1 || size
> UNITS_PER_WORD
;
5439 /* If we have a variable-sized parameter, we have no choice. */
5440 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5444 /* Implement TARGET_CALLEE_COPIES. */
5447 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5448 enum machine_mode mode ATTRIBUTE_UNUSED
,
5449 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5451 return mips_abi
== ABI_EABI
&& named
;
5454 /* See whether VALTYPE is a record whose fields should be returned in
5455 floating-point registers. If so, return the number of fields and
5456 list them in FIELDS (which should have two elements). Return 0
5459 For n32 & n64, a structure with one or two fields is returned in
5460 floating-point registers as long as every field has a floating-point
5464 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5472 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5476 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5478 if (TREE_CODE (field
) != FIELD_DECL
)
5481 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5487 fields
[i
++] = field
;
5492 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5493 a value in the most significant part of $2/$3 if:
5495 - the target is big-endian;
5497 - the value has a structure or union type (we generalize this to
5498 cover aggregates from other languages too); and
5500 - the structure is not returned in floating-point registers. */
5503 mips_return_in_msb (const_tree valtype
)
5507 return (TARGET_NEWABI
5508 && TARGET_BIG_ENDIAN
5509 && AGGREGATE_TYPE_P (valtype
)
5510 && mips_fpr_return_fields (valtype
, fields
) == 0);
5513 /* Return true if the function return value MODE will get returned in a
5514 floating-point register. */
5517 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5519 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5521 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5522 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5525 /* Return the representation of an FPR return register when the
5526 value being returned in FP_RETURN has mode VALUE_MODE and the
5527 return type itself has mode TYPE_MODE. On NewABI targets,
5528 the two modes may be different for structures like:
5530 struct __attribute__((packed)) foo { float f; }
5532 where we return the SFmode value of "f" in FP_RETURN, but where
5533 the structure itself has mode BLKmode. */
5536 mips_return_fpr_single (enum machine_mode type_mode
,
5537 enum machine_mode value_mode
)
5541 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5542 if (type_mode
!= value_mode
)
5544 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5545 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5550 /* Return a composite value in a pair of floating-point registers.
5551 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5552 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5555 For n32 & n64, $f0 always holds the first value and $f2 the second.
5556 Otherwise the values are packed together as closely as possible. */
5559 mips_return_fpr_pair (enum machine_mode mode
,
5560 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5561 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5565 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5566 return gen_rtx_PARALLEL
5569 gen_rtx_EXPR_LIST (VOIDmode
,
5570 gen_rtx_REG (mode1
, FP_RETURN
),
5572 gen_rtx_EXPR_LIST (VOIDmode
,
5573 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5574 GEN_INT (offset2
))));
5578 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5579 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5580 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5583 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5584 enum machine_mode mode
)
5592 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5593 func
= fn_decl_or_type
;
5597 mode
= TYPE_MODE (valtype
);
5598 unsigned_p
= TYPE_UNSIGNED (valtype
);
5600 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5601 return values, promote the mode here too. */
5602 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5604 /* Handle structures whose fields are returned in $f0/$f2. */
5605 switch (mips_fpr_return_fields (valtype
, fields
))
5608 return mips_return_fpr_single (mode
,
5609 TYPE_MODE (TREE_TYPE (fields
[0])));
5612 return mips_return_fpr_pair (mode
,
5613 TYPE_MODE (TREE_TYPE (fields
[0])),
5614 int_byte_position (fields
[0]),
5615 TYPE_MODE (TREE_TYPE (fields
[1])),
5616 int_byte_position (fields
[1]));
5619 /* If a value is passed in the most significant part of a register, see
5620 whether we have to round the mode up to a whole number of words. */
5621 if (mips_return_in_msb (valtype
))
5623 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5624 if (size
% UNITS_PER_WORD
!= 0)
5626 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5627 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5631 /* For EABI, the class of return register depends entirely on MODE.
5632 For example, "struct { some_type x; }" and "union { some_type x; }"
5633 are returned in the same way as a bare "some_type" would be.
5634 Other ABIs only use FPRs for scalar, complex or vector types. */
5635 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5636 return gen_rtx_REG (mode
, GP_RETURN
);
5641 /* Handle long doubles for n32 & n64. */
5643 return mips_return_fpr_pair (mode
,
5645 DImode
, GET_MODE_SIZE (mode
) / 2);
5647 if (mips_return_mode_in_fpr_p (mode
))
5649 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5650 return mips_return_fpr_pair (mode
,
5651 GET_MODE_INNER (mode
), 0,
5652 GET_MODE_INNER (mode
),
5653 GET_MODE_SIZE (mode
) / 2);
5655 return gen_rtx_REG (mode
, FP_RETURN
);
5659 return gen_rtx_REG (mode
, GP_RETURN
);
5662 /* Implement TARGET_FUNCTION_VALUE. */
5665 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5666 bool outgoing ATTRIBUTE_UNUSED
)
5668 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5671 /* Implement TARGET_LIBCALL_VALUE. */
5674 mips_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5676 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5679 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5681 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5682 Currently, R2 and F0 are only implemented here (C has no complex type). */
5685 mips_function_value_regno_p (const unsigned int regno
)
5687 if (regno
== GP_RETURN
5688 || regno
== FP_RETURN
5689 || (LONG_DOUBLE_TYPE_SIZE
== 128
5690 && FP_RETURN
!= GP_RETURN
5691 && regno
== FP_RETURN
+ 2))
5697 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5698 all BLKmode objects are returned in memory. Under the n32, n64
5699 and embedded ABIs, small structures are returned in a register.
5700 Objects with varying size must still be returned in memory, of
5704 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5706 return (TARGET_OLDABI
5707 ? TYPE_MODE (type
) == BLKmode
5708 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5711 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5714 mips_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
5715 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5718 CUMULATIVE_ARGS local_cum
;
5719 int gp_saved
, fp_saved
;
5721 /* The caller has advanced CUM up to, but not beyond, the last named
5722 argument. Advance a local copy of CUM past the last "real" named
5723 argument, to find out how many registers are left over. */
5724 local_cum
= *get_cumulative_args (cum
);
5725 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5728 /* Found out how many registers we need to save. */
5729 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5730 fp_saved
= (EABI_FLOAT_VARARGS_P
5731 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5740 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
5741 REG_PARM_STACK_SPACE (cfun
->decl
)
5742 - gp_saved
* UNITS_PER_WORD
);
5743 mem
= gen_frame_mem (BLKmode
, ptr
);
5744 set_mem_alias_set (mem
, get_varargs_alias_set ());
5746 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5751 /* We can't use move_block_from_reg, because it will use
5753 enum machine_mode mode
;
5756 /* Set OFF to the offset from virtual_incoming_args_rtx of
5757 the first float register. The FP save area lies below
5758 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5759 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5760 off
-= fp_saved
* UNITS_PER_FPREG
;
5762 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5764 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5765 i
+= MAX_FPRS_PER_FMT
)
5769 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
5770 mem
= gen_frame_mem (mode
, ptr
);
5771 set_mem_alias_set (mem
, get_varargs_alias_set ());
5772 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5773 off
+= UNITS_PER_HWFPVALUE
;
5777 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5778 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5779 + fp_saved
* UNITS_PER_FPREG
);
5782 /* Implement TARGET_BUILTIN_VA_LIST. */
5785 mips_build_builtin_va_list (void)
5787 if (EABI_FLOAT_VARARGS_P
)
5789 /* We keep 3 pointers, and two offsets.
5791 Two pointers are to the overflow area, which starts at the CFA.
5792 One of these is constant, for addressing into the GPR save area
5793 below it. The other is advanced up the stack through the
5796 The third pointer is to the bottom of the GPR save area.
5797 Since the FPR save area is just below it, we can address
5798 FPR slots off this pointer.
5800 We also keep two one-byte offsets, which are to be subtracted
5801 from the constant pointers to yield addresses in the GPR and
5802 FPR save areas. These are downcounted as float or non-float
5803 arguments are used, and when they get to zero, the argument
5804 must be obtained from the overflow region. */
5805 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5808 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5810 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5811 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5813 f_gtop
= build_decl (BUILTINS_LOCATION
,
5814 FIELD_DECL
, get_identifier ("__gpr_top"),
5816 f_ftop
= build_decl (BUILTINS_LOCATION
,
5817 FIELD_DECL
, get_identifier ("__fpr_top"),
5819 f_goff
= build_decl (BUILTINS_LOCATION
,
5820 FIELD_DECL
, get_identifier ("__gpr_offset"),
5821 unsigned_char_type_node
);
5822 f_foff
= build_decl (BUILTINS_LOCATION
,
5823 FIELD_DECL
, get_identifier ("__fpr_offset"),
5824 unsigned_char_type_node
);
5825 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5826 warn on every user file. */
5827 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5828 array
= build_array_type (unsigned_char_type_node
,
5829 build_index_type (index
));
5830 f_res
= build_decl (BUILTINS_LOCATION
,
5831 FIELD_DECL
, get_identifier ("__reserved"), array
);
5833 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5834 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5835 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5836 DECL_FIELD_CONTEXT (f_goff
) = record
;
5837 DECL_FIELD_CONTEXT (f_foff
) = record
;
5838 DECL_FIELD_CONTEXT (f_res
) = record
;
5840 TYPE_FIELDS (record
) = f_ovfl
;
5841 DECL_CHAIN (f_ovfl
) = f_gtop
;
5842 DECL_CHAIN (f_gtop
) = f_ftop
;
5843 DECL_CHAIN (f_ftop
) = f_goff
;
5844 DECL_CHAIN (f_goff
) = f_foff
;
5845 DECL_CHAIN (f_foff
) = f_res
;
5847 layout_type (record
);
5851 /* Otherwise, we use 'void *'. */
5852 return ptr_type_node
;
5855 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5858 mips_va_start (tree valist
, rtx nextarg
)
5860 if (EABI_FLOAT_VARARGS_P
)
5862 const CUMULATIVE_ARGS
*cum
;
5863 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5864 tree ovfl
, gtop
, ftop
, goff
, foff
;
5866 int gpr_save_area_size
;
5867 int fpr_save_area_size
;
5870 cum
= &crtl
->args
.info
;
5872 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5874 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5876 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5877 f_gtop
= DECL_CHAIN (f_ovfl
);
5878 f_ftop
= DECL_CHAIN (f_gtop
);
5879 f_goff
= DECL_CHAIN (f_ftop
);
5880 f_foff
= DECL_CHAIN (f_goff
);
5882 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5884 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5886 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5888 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5890 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5893 /* Emit code to initialize OVFL, which points to the next varargs
5894 stack argument. CUM->STACK_WORDS gives the number of stack
5895 words used by named arguments. */
5896 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5897 if (cum
->stack_words
> 0)
5898 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
5899 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5900 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5902 /* Emit code to initialize GTOP, the top of the GPR save area. */
5903 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5904 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5905 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5907 /* Emit code to initialize FTOP, the top of the FPR save area.
5908 This address is gpr_save_area_bytes below GTOP, rounded
5909 down to the next fp-aligned boundary. */
5910 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5911 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5912 fpr_offset
&= -UNITS_PER_FPVALUE
;
5914 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
5915 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5916 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5918 /* Emit code to initialize GOFF, the offset from GTOP of the
5919 next GPR argument. */
5920 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5921 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
5922 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5924 /* Likewise emit code to initialize FOFF, the offset from FTOP
5925 of the next FPR argument. */
5926 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5927 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
5928 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5932 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
5933 std_expand_builtin_va_start (valist
, nextarg
);
5937 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5941 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5944 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
5945 unsigned HOST_WIDE_INT align
, boundary
;
5948 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
5950 type
= build_pointer_type (type
);
5952 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
5953 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
5955 /* When we align parameter on stack for caller, if the parameter
5956 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5957 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5958 here with caller. */
5959 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
5960 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
5962 boundary
/= BITS_PER_UNIT
;
5964 /* Hoist the valist value into a temporary for the moment. */
5965 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
5967 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5968 requires greater alignment, we must perform dynamic alignment. */
5969 if (boundary
> align
)
5971 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5972 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
5973 gimplify_and_add (t
, pre_p
);
5975 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5976 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
5978 build_int_cst (TREE_TYPE (valist
), -boundary
)));
5979 gimplify_and_add (t
, pre_p
);
5984 /* If the actual alignment is less than the alignment of the type,
5985 adjust the type accordingly so that we don't assume strict alignment
5986 when dereferencing the pointer. */
5987 boundary
*= BITS_PER_UNIT
;
5988 if (boundary
< TYPE_ALIGN (type
))
5990 type
= build_variant_type_copy (type
);
5991 TYPE_ALIGN (type
) = boundary
;
5994 /* Compute the rounded size of the type. */
5995 type_size
= size_in_bytes (type
);
5996 rounded_size
= round_up (type_size
, align
);
5998 /* Reduce rounded_size so it's sharable with the postqueue. */
5999 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6003 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
6005 /* Small args are padded downward. */
6006 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
6007 rounded_size
, size_int (align
));
6008 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
6009 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
6010 addr
= fold_build_pointer_plus (addr
, t
);
6013 /* Compute new value for AP. */
6014 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
6015 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
6016 gimplify_and_add (t
, pre_p
);
6018 addr
= fold_convert (build_pointer_type (type
), addr
);
6021 addr
= build_va_arg_indirect_ref (addr
);
6023 return build_va_arg_indirect_ref (addr
);
6026 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6029 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6035 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
6037 type
= build_pointer_type (type
);
6039 if (!EABI_FLOAT_VARARGS_P
)
6040 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6043 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6044 tree ovfl
, top
, off
, align
;
6045 HOST_WIDE_INT size
, rsize
, osize
;
6048 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6049 f_gtop
= DECL_CHAIN (f_ovfl
);
6050 f_ftop
= DECL_CHAIN (f_gtop
);
6051 f_goff
= DECL_CHAIN (f_ftop
);
6052 f_foff
= DECL_CHAIN (f_goff
);
6056 TOP be the top of the GPR or FPR save area;
6057 OFF be the offset from TOP of the next register;
6058 ADDR_RTX be the address of the argument;
6059 SIZE be the number of bytes in the argument type;
6060 RSIZE be the number of bytes used to store the argument
6061 when it's in the register save area; and
6062 OSIZE be the number of bytes used to store it when it's
6063 in the stack overflow area.
6065 The code we want is:
6067 1: off &= -rsize; // round down
6070 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6075 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6076 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6080 [1] and [9] can sometimes be optimized away. */
6082 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6084 size
= int_size_in_bytes (type
);
6086 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6087 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6089 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6090 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6091 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6092 unshare_expr (valist
), f_foff
, NULL_TREE
);
6094 /* When va_start saves FPR arguments to the stack, each slot
6095 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6096 argument's precision. */
6097 rsize
= UNITS_PER_HWFPVALUE
;
6099 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6100 (= PARM_BOUNDARY bits). This can be different from RSIZE
6103 (1) On 32-bit targets when TYPE is a structure such as:
6105 struct s { float f; };
6107 Such structures are passed in paired FPRs, so RSIZE
6108 will be 8 bytes. However, the structure only takes
6109 up 4 bytes of memory, so OSIZE will only be 4.
6111 (2) In combinations such as -mgp64 -msingle-float
6112 -fshort-double. Doubles passed in registers will then take
6113 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6114 stack take up UNITS_PER_WORD bytes. */
6115 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6119 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6120 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6121 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6122 unshare_expr (valist
), f_goff
, NULL_TREE
);
6123 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6124 if (rsize
> UNITS_PER_WORD
)
6126 /* [1] Emit code for: off &= -rsize. */
6127 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6128 build_int_cst (TREE_TYPE (off
), -rsize
));
6129 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6134 /* [2] Emit code to branch if off == 0. */
6135 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6136 build_int_cst (TREE_TYPE (off
), 0));
6137 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6139 /* [5] Emit code for: off -= rsize. We do this as a form of
6140 post-decrement not available to C. */
6141 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6142 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6144 /* [4] Emit code for:
6145 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6146 t
= fold_convert (sizetype
, t
);
6147 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6148 t
= fold_build_pointer_plus (top
, t
);
6149 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6150 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6151 COND_EXPR_THEN (addr
) = t
;
6153 if (osize
> UNITS_PER_WORD
)
6155 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6156 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6157 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6158 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6159 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6160 unshare_expr (ovfl
), t
);
6165 /* [10, 11] Emit code for:
6166 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6168 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6169 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6170 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6171 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6173 /* String [9] and [10, 11] together. */
6175 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6176 COND_EXPR_ELSE (addr
) = t
;
6178 addr
= fold_convert (build_pointer_type (type
), addr
);
6179 addr
= build_va_arg_indirect_ref (addr
);
6183 addr
= build_va_arg_indirect_ref (addr
);
6188 /* Declare a unique, locally-binding function called NAME, then start
6192 mips_start_unique_function (const char *name
)
6196 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6197 get_identifier (name
),
6198 build_function_type_list (void_type_node
, NULL_TREE
));
6199 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6200 NULL_TREE
, void_type_node
);
6201 TREE_PUBLIC (decl
) = 1;
6202 TREE_STATIC (decl
) = 1;
6204 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
6206 targetm
.asm_out
.unique_section (decl
, 0);
6207 switch_to_section (get_named_section (decl
, NULL
, 0));
6209 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6210 fputs ("\t.hidden\t", asm_out_file
);
6211 assemble_name (asm_out_file
, name
);
6212 putc ('\n', asm_out_file
);
6215 /* Start a definition of function NAME. MIPS16_P indicates whether the
6216 function contains MIPS16 code. */
6219 mips_start_function_definition (const char *name
, bool mips16_p
)
6222 fprintf (asm_out_file
, "\t.set\tmips16\n");
6224 fprintf (asm_out_file
, "\t.set\tnomips16\n");
6226 if (TARGET_MICROMIPS
)
6227 fprintf (asm_out_file
, "\t.set\tmicromips\n");
6228 #ifdef HAVE_GAS_MICROMIPS
6230 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
6233 if (!flag_inhibit_size_directive
)
6235 fputs ("\t.ent\t", asm_out_file
);
6236 assemble_name (asm_out_file
, name
);
6237 fputs ("\n", asm_out_file
);
6240 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
6242 /* Start the definition proper. */
6243 assemble_name (asm_out_file
, name
);
6244 fputs (":\n", asm_out_file
);
6247 /* End a function definition started by mips_start_function_definition. */
6250 mips_end_function_definition (const char *name
)
6252 if (!flag_inhibit_size_directive
)
6254 fputs ("\t.end\t", asm_out_file
);
6255 assemble_name (asm_out_file
, name
);
6256 fputs ("\n", asm_out_file
);
6260 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
6261 then free *STUB_PTR. */
6264 mips_finish_stub (mips_one_only_stub
**stub_ptr
)
6266 mips_one_only_stub
*stub
= *stub_ptr
;
6270 const char *name
= stub
->get_name ();
6271 mips_start_unique_function (name
);
6272 mips_start_function_definition (name
, false);
6273 stub
->output_body ();
6274 mips_end_function_definition (name
);
6279 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6282 mips_ok_for_lazy_binding_p (rtx x
)
6284 return (TARGET_USE_GOT
6285 && GET_CODE (x
) == SYMBOL_REF
6286 && !SYMBOL_REF_BIND_NOW_P (x
)
6287 && !mips_symbol_binds_local_p (x
));
6290 /* Load function address ADDR into register DEST. TYPE is as for
6291 mips_expand_call. Return true if we used an explicit lazy-binding
6295 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
6297 /* If we're generating PIC, and this call is to a global function,
6298 try to allow its address to be resolved lazily. This isn't
6299 possible for sibcalls when $gp is call-saved because the value
6300 of $gp on entry to the stub would be our caller's gp, not ours. */
6301 if (TARGET_EXPLICIT_RELOCS
6302 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
6303 && mips_ok_for_lazy_binding_p (addr
))
6305 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
6306 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
6311 mips_emit_move (dest
, addr
);
6316 /* Each locally-defined hard-float MIPS16 function has a local symbol
6317 associated with it. This hash table maps the function symbol (FUNC)
6318 to the local symbol (LOCAL). */
6319 struct GTY(()) mips16_local_alias
{
6323 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
6325 /* Hash table callbacks for mips16_local_aliases. */
6328 mips16_local_aliases_hash (const void *entry
)
6330 const struct mips16_local_alias
*alias
;
6332 alias
= (const struct mips16_local_alias
*) entry
;
6333 return htab_hash_string (XSTR (alias
->func
, 0));
6337 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
6339 const struct mips16_local_alias
*alias1
, *alias2
;
6341 alias1
= (const struct mips16_local_alias
*) entry1
;
6342 alias2
= (const struct mips16_local_alias
*) entry2
;
6343 return rtx_equal_p (alias1
->func
, alias2
->func
);
6346 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6347 Return a local alias for it, creating a new one if necessary. */
6350 mips16_local_alias (rtx func
)
6352 struct mips16_local_alias
*alias
, tmp_alias
;
6355 /* Create the hash table if this is the first call. */
6356 if (mips16_local_aliases
== NULL
)
6357 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
6358 mips16_local_aliases_eq
, NULL
);
6360 /* Look up the function symbol, creating a new entry if need be. */
6361 tmp_alias
.func
= func
;
6362 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
6363 gcc_assert (slot
!= NULL
);
6365 alias
= (struct mips16_local_alias
*) *slot
;
6368 const char *func_name
, *local_name
;
6371 /* Create a new SYMBOL_REF for the local symbol. The choice of
6372 __fn_local_* is based on the __fn_stub_* names that we've
6373 traditionally used for the non-MIPS16 stub. */
6374 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6375 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6376 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6377 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6379 /* Create a new structure to represent the mapping. */
6380 alias
= ggc_alloc_mips16_local_alias ();
6382 alias
->local
= local
;
6385 return alias
->local
;
6388 /* A chained list of functions for which mips16_build_call_stub has already
6389 generated a stub. NAME is the name of the function and FP_RET_P is true
6390 if the function returns a value in floating-point registers. */
6391 struct mips16_stub
{
6392 struct mips16_stub
*next
;
6396 static struct mips16_stub
*mips16_stubs
;
6398 /* Return the two-character string that identifies floating-point
6399 return mode MODE in the name of a MIPS16 function stub. */
6402 mips16_call_stub_mode_suffix (enum machine_mode mode
)
6406 else if (mode
== DFmode
)
6408 else if (mode
== SCmode
)
6410 else if (mode
== DCmode
)
6412 else if (mode
== V2SFmode
)
6418 /* Write instructions to move a 32-bit value between general register
6419 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6420 from GPREG to FPREG and 'f' to move in the opposite direction. */
6423 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6425 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6426 reg_names
[gpreg
], reg_names
[fpreg
]);
6429 /* Likewise for 64-bit values. */
6432 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6435 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6436 reg_names
[gpreg
], reg_names
[fpreg
]);
6437 else if (TARGET_FLOAT64
)
6439 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6440 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6441 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6442 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6446 /* Move the least-significant word. */
6447 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6448 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6449 /* ...then the most significant word. */
6450 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6451 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6455 /* Write out code to move floating-point arguments into or out of
6456 general registers. FP_CODE is the code describing which arguments
6457 are present (see the comment above the definition of CUMULATIVE_ARGS
6458 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6461 mips_output_args_xfer (int fp_code
, char direction
)
6463 unsigned int gparg
, fparg
, f
;
6464 CUMULATIVE_ARGS cum
;
6466 /* This code only works for o32 and o64. */
6467 gcc_assert (TARGET_OLDABI
);
6469 mips_init_cumulative_args (&cum
, NULL
);
6471 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6473 enum machine_mode mode
;
6474 struct mips_arg_info info
;
6478 else if ((f
& 3) == 2)
6483 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6484 gparg
= mips_arg_regno (&info
, false);
6485 fparg
= mips_arg_regno (&info
, true);
6488 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6490 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6492 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6496 /* Write a MIPS16 stub for the current function. This stub is used
6497 for functions which take arguments in the floating-point registers.
6498 It is normal-mode code that moves the floating-point arguments
6499 into the general registers and then jumps to the MIPS16 code. */
6502 mips16_build_function_stub (void)
6504 const char *fnname
, *alias_name
, *separator
;
6505 char *secname
, *stubname
;
6510 /* Create the name of the stub, and its unique section. */
6511 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6512 alias
= mips16_local_alias (symbol
);
6514 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6515 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6516 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6517 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6519 /* Build a decl for the stub. */
6520 stubdecl
= build_decl (BUILTINS_LOCATION
,
6521 FUNCTION_DECL
, get_identifier (stubname
),
6522 build_function_type_list (void_type_node
, NULL_TREE
));
6523 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6524 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6525 RESULT_DECL
, NULL_TREE
, void_type_node
);
6527 /* Output a comment. */
6528 fprintf (asm_out_file
, "\t# Stub function for %s (",
6529 current_function_name ());
6531 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6533 fprintf (asm_out_file
, "%s%s", separator
,
6534 (f
& 3) == 1 ? "float" : "double");
6537 fprintf (asm_out_file
, ")\n");
6539 /* Start the function definition. */
6540 assemble_start_function (stubdecl
, stubname
);
6541 mips_start_function_definition (stubname
, false);
6543 /* If generating pic2 code, either set up the global pointer or
6545 if (TARGET_ABICALLS_PIC2
)
6547 if (TARGET_ABSOLUTE_ABICALLS
)
6548 fprintf (asm_out_file
, "\t.option\tpic0\n");
6551 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6552 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6553 target function is. Use a local GOT access when loading the
6554 symbol, to cut down on the number of unnecessary GOT entries
6555 for stubs that aren't needed. */
6556 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6561 /* Load the address of the MIPS16 function into $25. Do this first so
6562 that targets with coprocessor interlocks can use an MFC1 to fill the
6564 output_asm_insn ("la\t%^,%0", &symbol
);
6566 /* Move the arguments from floating-point registers to general registers. */
6567 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6569 /* Jump to the MIPS16 function. */
6570 output_asm_insn ("jr\t%^", NULL
);
6572 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6573 fprintf (asm_out_file
, "\t.option\tpic2\n");
6575 mips_end_function_definition (stubname
);
6577 /* If the linker needs to create a dynamic symbol for the target
6578 function, it will associate the symbol with the stub (which,
6579 unlike the target function, follows the proper calling conventions).
6580 It is therefore useful to have a local alias for the target function,
6581 so that it can still be identified as MIPS16 code. As an optimization,
6582 this symbol can also be used for indirect MIPS16 references from
6583 within this file. */
6584 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6586 switch_to_section (function_section (current_function_decl
));
6589 /* The current function is a MIPS16 function that returns a value in an FPR.
6590 Copy the return value from its soft-float to its hard-float location.
6591 libgcc2 has special non-MIPS16 helper functions for each case. */
6594 mips16_copy_fpr_return_value (void)
6596 rtx fn
, insn
, retval
;
6598 enum machine_mode return_mode
;
6601 return_type
= DECL_RESULT (current_function_decl
);
6602 return_mode
= DECL_MODE (return_type
);
6604 name
= ACONCAT (("__mips16_ret_",
6605 mips16_call_stub_mode_suffix (return_mode
),
6607 fn
= mips16_stub_function (name
);
6609 /* The function takes arguments in $2 (and possibly $3), so calls
6610 to it cannot be lazily bound. */
6611 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6613 /* Model the call as something that takes the GPR return value as
6614 argument and returns an "updated" value. */
6615 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6616 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6617 const0_rtx
, NULL_RTX
, false);
6618 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6621 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6622 RETVAL is the location of the return value, or null if this is
6623 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6624 arguments and FP_CODE is the code built by mips_function_arg;
6625 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6627 There are three alternatives:
6629 - If a stub was needed, emit the call and return the call insn itself.
6631 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6632 to the new target and return null.
6634 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6637 A stub is needed for calls to functions that, in normal mode,
6638 receive arguments in FPRs or return values in FPRs. The stub
6639 copies the arguments from their soft-float positions to their
6640 hard-float positions, calls the real function, then copies the
6641 return value from its hard-float position to its soft-float
6644 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6645 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6646 automatically redirects the JAL to the stub, otherwise the JAL
6647 continues to call FN directly. */
6650 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6654 struct mips16_stub
*l
;
6657 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6658 we were invoked with the -msoft-float option. */
6659 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6662 /* Figure out whether the value might come back in a floating-point
6664 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6666 /* We don't need to do anything if there were no floating-point
6667 arguments and the value will not be returned in a floating-point
6669 if (fp_code
== 0 && !fp_ret_p
)
6672 /* We don't need to do anything if this is a call to a special
6673 MIPS16 support function. */
6675 if (mips16_stub_function_p (fn
))
6678 /* If we're calling a locally-defined MIPS16 function, we know that
6679 it will return values in both the "soft-float" and "hard-float"
6680 registers. There is no need to use a stub to move the latter
6682 if (fp_code
== 0 && mips16_local_function_p (fn
))
6685 /* This code will only work for o32 and o64 abis. The other ABI's
6686 require more sophisticated support. */
6687 gcc_assert (TARGET_OLDABI
);
6689 /* If we're calling via a function pointer, use one of the magic
6690 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6691 Each stub expects the function address to arrive in register $2. */
6692 if (GET_CODE (fn
) != SYMBOL_REF
6693 || !call_insn_operand (fn
, VOIDmode
))
6696 rtx stub_fn
, insn
, addr
;
6699 /* If this is a locally-defined and locally-binding function,
6700 avoid the stub by calling the local alias directly. */
6701 if (mips16_local_function_p (fn
))
6703 *fn_ptr
= mips16_local_alias (fn
);
6707 /* Create a SYMBOL_REF for the libgcc.a function. */
6709 sprintf (buf
, "__mips16_call_stub_%s_%d",
6710 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6713 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6714 stub_fn
= mips16_stub_function (buf
);
6716 /* The function uses $2 as an argument, so calls to it
6717 cannot be lazily bound. */
6718 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6720 /* Load the target function into $2. */
6721 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6722 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6724 /* Emit the call. */
6725 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6726 args_size
, NULL_RTX
, lazy_p
);
6728 /* Tell GCC that this call does indeed use the value of $2. */
6729 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6731 /* If we are handling a floating-point return value, we need to
6732 save $18 in the function prologue. Putting a note on the
6733 call will mean that df_regs_ever_live_p ($18) will be true if the
6734 call is not eliminated, and we can check that in the prologue
6737 CALL_INSN_FUNCTION_USAGE (insn
) =
6738 gen_rtx_EXPR_LIST (VOIDmode
,
6739 gen_rtx_CLOBBER (VOIDmode
,
6740 gen_rtx_REG (word_mode
, 18)),
6741 CALL_INSN_FUNCTION_USAGE (insn
));
6746 /* We know the function we are going to call. If we have already
6747 built a stub, we don't need to do anything further. */
6748 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6749 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6750 if (strcmp (l
->name
, fnname
) == 0)
6755 const char *separator
;
6756 char *secname
, *stubname
;
6757 tree stubid
, stubdecl
;
6760 /* If the function does not return in FPRs, the special stub
6764 If the function does return in FPRs, the stub section is named
6765 .mips16.call.fp.FNNAME
6767 Build a decl for the stub. */
6768 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6770 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6772 stubid
= get_identifier (stubname
);
6773 stubdecl
= build_decl (BUILTINS_LOCATION
,
6774 FUNCTION_DECL
, stubid
,
6775 build_function_type_list (void_type_node
,
6777 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6778 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6779 RESULT_DECL
, NULL_TREE
,
6782 /* Output a comment. */
6783 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6785 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6789 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6791 fprintf (asm_out_file
, "%s%s", separator
,
6792 (f
& 3) == 1 ? "float" : "double");
6795 fprintf (asm_out_file
, ")\n");
6797 /* Start the function definition. */
6798 assemble_start_function (stubdecl
, stubname
);
6799 mips_start_function_definition (stubname
, false);
6803 fprintf (asm_out_file
, "\t.cfi_startproc\n");
6805 /* Create a fake CFA 4 bytes below the stack pointer.
6806 This works around unwinders (like libgcc's) that expect
6807 the CFA for non-signal frames to be unique. */
6808 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
6810 /* "Save" $sp in itself so we don't use the fake CFA.
6811 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6812 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
6816 /* Load the address of the MIPS16 function into $25. Do this
6817 first so that targets with coprocessor interlocks can use
6818 an MFC1 to fill the delay slot. */
6819 if (TARGET_EXPLICIT_RELOCS
)
6821 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6822 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6825 output_asm_insn ("la\t%^,%0", &fn
);
6828 /* Move the arguments from general registers to floating-point
6830 mips_output_args_xfer (fp_code
, 't');
6834 /* Save the return address in $18 and call the non-MIPS16 function.
6835 The stub's caller knows that $18 might be clobbered, even though
6836 $18 is usually a call-saved register. */
6837 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6838 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6839 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6840 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
6842 /* Move the result from floating-point registers to
6843 general registers. */
6844 switch (GET_MODE (retval
))
6847 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6849 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6851 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6852 TARGET_LITTLE_ENDIAN
6853 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6855 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6857 /* On 64-bit targets, complex floats are returned in
6858 a single GPR, such that "sd" on a suitably-aligned
6859 target would store the value correctly. */
6860 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6861 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6862 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6863 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6864 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6865 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6866 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6867 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6868 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6869 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6870 reg_names
[GP_RETURN
],
6871 reg_names
[GP_RETURN
],
6872 reg_names
[GP_RETURN
+ 1]);
6877 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6881 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6882 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6886 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6892 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6893 fprintf (asm_out_file
, "\t.cfi_endproc\n");
6897 /* Jump to the previously-loaded address. */
6898 output_asm_insn ("jr\t%^", NULL
);
6901 #ifdef ASM_DECLARE_FUNCTION_SIZE
6902 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6905 mips_end_function_definition (stubname
);
6907 /* Record this stub. */
6908 l
= XNEW (struct mips16_stub
);
6909 l
->name
= xstrdup (fnname
);
6910 l
->fp_ret_p
= fp_ret_p
;
6911 l
->next
= mips16_stubs
;
6915 /* If we expect a floating-point return value, but we've built a
6916 stub which does not expect one, then we're in trouble. We can't
6917 use the existing stub, because it won't handle the floating-point
6918 value. We can't build a new stub, because the linker won't know
6919 which stub to use for the various calls in this object file.
6920 Fortunately, this case is illegal, since it means that a function
6921 was declared in two different ways in a single compilation. */
6922 if (fp_ret_p
&& !l
->fp_ret_p
)
6923 error ("cannot handle inconsistent calls to %qs", fnname
);
6925 if (retval
== NULL_RTX
)
6926 insn
= gen_call_internal_direct (fn
, args_size
);
6928 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
6929 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
6931 /* If we are calling a stub which handles a floating-point return
6932 value, we need to arrange to save $18 in the prologue. We do this
6933 by marking the function call as using the register. The prologue
6934 will later see that it is used, and emit code to save it. */
6936 CALL_INSN_FUNCTION_USAGE (insn
) =
6937 gen_rtx_EXPR_LIST (VOIDmode
,
6938 gen_rtx_CLOBBER (VOIDmode
,
6939 gen_rtx_REG (word_mode
, 18)),
6940 CALL_INSN_FUNCTION_USAGE (insn
));
6945 /* Expand a call of type TYPE. RESULT is where the result will go (null
6946 for "call"s and "sibcall"s), ADDR is the address of the function,
6947 ARGS_SIZE is the size of the arguments and AUX is the value passed
6948 to us by mips_function_arg. LAZY_P is true if this call already
6949 involves a lazily-bound function address (such as when calling
6950 functions through a MIPS16 hard-float stub).
6952 Return the call itself. */
6955 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
6956 rtx args_size
, rtx aux
, bool lazy_p
)
6958 rtx orig_addr
, pattern
, insn
;
6961 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
6962 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
6965 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
6970 if (!call_insn_operand (addr
, VOIDmode
))
6972 if (type
== MIPS_CALL_EPILOGUE
)
6973 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
6975 addr
= gen_reg_rtx (Pmode
);
6976 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
6981 rtx (*fn
) (rtx
, rtx
);
6983 if (type
== MIPS_CALL_SIBCALL
)
6984 fn
= gen_sibcall_internal
;
6986 fn
= gen_call_internal
;
6988 pattern
= fn (addr
, args_size
);
6990 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
6992 /* Handle return values created by mips_return_fpr_pair. */
6993 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
6996 if (type
== MIPS_CALL_SIBCALL
)
6997 fn
= gen_sibcall_value_multiple_internal
;
6999 fn
= gen_call_value_multiple_internal
;
7001 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
7002 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
7003 pattern
= fn (reg1
, addr
, args_size
, reg2
);
7007 rtx (*fn
) (rtx
, rtx
, rtx
);
7009 if (type
== MIPS_CALL_SIBCALL
)
7010 fn
= gen_sibcall_value_internal
;
7012 fn
= gen_call_value_internal
;
7014 /* Handle return values created by mips_return_fpr_single. */
7015 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
7016 result
= XEXP (XVECEXP (result
, 0, 0), 0);
7017 pattern
= fn (result
, addr
, args_size
);
7020 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
7023 /* Split call instruction INSN into a $gp-clobbering call and
7024 (where necessary) an instruction to restore $gp from its save slot.
7025 CALL_PATTERN is the pattern of the new call. */
7028 mips_split_call (rtx insn
, rtx call_pattern
)
7030 emit_call_insn (call_pattern
);
7031 if (!find_reg_note (insn
, REG_NORETURN
, 0))
7032 /* Pick a temporary register that is suitable for both MIPS16 and
7033 non-MIPS16 code. $4 and $5 are used for returning complex double
7034 values in soft-float code, so $6 is the first suitable candidate. */
7035 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 2));
7038 /* Return true if a call to DECL may need to use JALX. */
7041 mips_call_may_need_jalx_p (tree decl
)
7043 /* If the current translation unit would use a different mode for DECL,
7044 assume that the call needs JALX. */
7045 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
7048 /* mips_get_compress_mode is always accurate for locally-binding
7049 functions in the current translation unit. */
7050 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
7053 /* When -minterlink-compressed is in effect, assume that functions
7054 could use a different encoding mode unless an attribute explicitly
7055 tells us otherwise. */
7056 if (TARGET_INTERLINK_COMPRESSED
)
7058 if (!TARGET_COMPRESSION
7059 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
7061 if (TARGET_COMPRESSION
7062 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
7069 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7072 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7074 if (!TARGET_SIBCALLS
)
7077 /* Interrupt handlers need special epilogue code and therefore can't
7079 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7082 /* Direct Js are only possible to functions that use the same ISA encoding.
7083 There is no JX counterpoart of JALX. */
7085 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7086 && mips_call_may_need_jalx_p (decl
))
7089 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7090 require $gp to be valid on entry, so sibcalls can only use stubs
7091 if $gp is call-clobbered. */
7093 && TARGET_CALL_SAVED_GP
7094 && !TARGET_ABICALLS_PIC0
7095 && !targetm
.binds_local_p (decl
))
7102 /* Emit code to move general operand SRC into condition-code
7103 register DEST given that SCRATCH is a scratch TFmode FPR.
7110 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
7113 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
7117 /* Change the source to SFmode. */
7119 src
= adjust_address (src
, SFmode
, 0);
7120 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
7121 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
7123 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
7124 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
7126 mips_emit_move (copy_rtx (fp1
), src
);
7127 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
7128 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
7131 /* Implement MOVE_BY_PIECES_P. */
7134 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7138 /* movmemsi is meant to generate code that is at least as good as
7139 move_by_pieces. However, movmemsi effectively uses a by-pieces
7140 implementation both for moves smaller than a word and for
7141 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7142 bytes. We should allow the tree-level optimisers to do such
7143 moves by pieces, as it often exposes other optimization
7144 opportunities. We might as well continue to use movmemsi at
7145 the rtl level though, as it produces better code when
7146 scheduling is disabled (such as at -O). */
7147 if (currently_expanding_to_rtl
)
7149 if (align
< BITS_PER_WORD
)
7150 return size
< UNITS_PER_WORD
;
7151 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7153 /* The default value. If this becomes a target hook, we should
7154 call the default definition instead. */
7155 return (move_by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1)
7156 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7159 /* Implement STORE_BY_PIECES_P. */
7162 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7164 /* Storing by pieces involves moving constants into registers
7165 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7166 We need to decide whether it is cheaper to load the address of
7167 constant data into a register and use a block move instead. */
7169 /* If the data is only byte aligned, then:
7171 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7172 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7175 (a2) A block move of 4 bytes from aligned source data can use an
7176 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7177 4 SBs that we would generate when storing by pieces. */
7178 if (align
<= BITS_PER_UNIT
)
7181 /* If the data is 2-byte aligned, then:
7183 (b1) A block move of less than 4 bytes would use a combination of LBs,
7184 LHs, SBs and SHs. We get better code by using single-instruction
7185 LIs, SBs and SHs instead.
7187 (b2) A block move of 4 bytes from aligned source data would again use
7188 an LW/SWL/SWR sequence. In most cases, loading the address of
7189 the source data would require at least one extra instruction.
7190 It is often more efficient to use 2 single-instruction LIs and
7193 (b3) A block move of up to 3 additional bytes would be like (b1).
7195 (b4) A block move of 8 bytes from aligned source data can use two
7196 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7197 sequences are better than the 4 LIs and 4 SHs that we'd generate
7198 when storing by pieces.
7200 The reasoning for higher alignments is similar:
7202 (c1) A block move of less than 4 bytes would be the same as (b1).
7204 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7205 loading the address of the source data would typically require
7206 at least one extra instruction. It is generally better to use
7209 (c3) A block move of up to 3 additional bytes would be like (b1).
7211 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7212 LD/SD sequence, and in these cases we've traditionally preferred
7213 the memory copy over the more bulky constant moves. */
7217 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7218 Assume that the areas do not overlap. */
7221 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7223 HOST_WIDE_INT offset
, delta
;
7224 unsigned HOST_WIDE_INT bits
;
7226 enum machine_mode mode
;
7229 /* Work out how many bits to move at a time. If both operands have
7230 half-word alignment, it is usually better to move in half words.
7231 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7232 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7233 Otherwise move word-sized chunks. */
7234 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7235 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7236 bits
= BITS_PER_WORD
/ 2;
7238 bits
= BITS_PER_WORD
;
7240 mode
= mode_for_size (bits
, MODE_INT
, 0);
7241 delta
= bits
/ BITS_PER_UNIT
;
7243 /* Allocate a buffer for the temporary registers. */
7244 regs
= XALLOCAVEC (rtx
, length
/ delta
);
7246 /* Load as many BITS-sized chunks as possible. Use a normal load if
7247 the source has enough alignment, otherwise use left/right pairs. */
7248 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7250 regs
[i
] = gen_reg_rtx (mode
);
7251 if (MEM_ALIGN (src
) >= bits
)
7252 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
7255 rtx part
= adjust_address (src
, BLKmode
, offset
);
7256 set_mem_size (part
, delta
);
7257 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
7262 /* Copy the chunks to the destination. */
7263 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7264 if (MEM_ALIGN (dest
) >= bits
)
7265 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
7268 rtx part
= adjust_address (dest
, BLKmode
, offset
);
7269 set_mem_size (part
, delta
);
7270 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
7274 /* Mop up any left-over bytes. */
7275 if (offset
< length
)
7277 src
= adjust_address (src
, BLKmode
, offset
);
7278 dest
= adjust_address (dest
, BLKmode
, offset
);
7279 move_by_pieces (dest
, src
, length
- offset
,
7280 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
7284 /* Helper function for doing a loop-based block operation on memory
7285 reference MEM. Each iteration of the loop will operate on LENGTH
7288 Create a new base register for use within the loop and point it to
7289 the start of MEM. Create a new memory reference that uses this
7290 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7293 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
7294 rtx
*loop_reg
, rtx
*loop_mem
)
7296 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
7298 /* Although the new mem does not refer to a known location,
7299 it does keep up to LENGTH bytes of alignment. */
7300 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
7301 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
7304 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7305 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7306 the memory regions do not overlap. */
7309 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
7310 HOST_WIDE_INT bytes_per_iter
)
7312 rtx label
, src_reg
, dest_reg
, final_src
, test
;
7313 HOST_WIDE_INT leftover
;
7315 leftover
= length
% bytes_per_iter
;
7318 /* Create registers and memory references for use within the loop. */
7319 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
7320 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
7322 /* Calculate the value that SRC_REG should have after the last iteration
7324 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
7327 /* Emit the start of the loop. */
7328 label
= gen_label_rtx ();
7331 /* Emit the loop body. */
7332 mips_block_move_straight (dest
, src
, bytes_per_iter
);
7334 /* Move on to the next block. */
7335 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
7336 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
7338 /* Emit the loop condition. */
7339 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7340 if (Pmode
== DImode
)
7341 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7343 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7345 /* Mop up any left-over bytes. */
7347 mips_block_move_straight (dest
, src
, leftover
);
7350 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7351 memory reference SRC to memory reference DEST. */
7354 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7356 if (CONST_INT_P (length
))
7358 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7360 mips_block_move_straight (dest
, src
, INTVAL (length
));
7365 mips_block_move_loop (dest
, src
, INTVAL (length
),
7366 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7373 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7376 mips_expand_synci_loop (rtx begin
, rtx end
)
7378 rtx inc
, label
, end_label
, cmp_result
, mask
, length
;
7380 /* Create end_label. */
7381 end_label
= gen_label_rtx ();
7383 /* Check if begin equals end. */
7384 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7385 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7387 /* Load INC with the cache line size (rdhwr INC,$1). */
7388 inc
= gen_reg_rtx (Pmode
);
7389 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7391 /* Check if inc is 0. */
7392 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7393 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7395 /* Calculate mask. */
7396 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7398 /* Mask out begin by mask. */
7399 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7401 /* Calculate length. */
7402 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7404 /* Loop back to here. */
7405 label
= gen_label_rtx ();
7408 emit_insn (gen_synci (begin
));
7410 /* Update length. */
7411 mips_emit_binary (MINUS
, length
, length
, inc
);
7414 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7416 /* Check if length is greater than 0. */
7417 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7418 emit_jump_insn (gen_condjump (cmp_result
, label
));
7420 emit_label (end_label
);
7423 /* Expand a QI or HI mode atomic memory operation.
7425 GENERATOR contains a pointer to the gen_* function that generates
7426 the SI mode underlying atomic operation using masks that we
7429 RESULT is the return register for the operation. Its value is NULL
7432 MEM is the location of the atomic access.
7434 OLDVAL is the first operand for the operation.
7436 NEWVAL is the optional second operand for the operation. Its value
7437 is NULL if unused. */
7440 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7441 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7443 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7444 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7446 enum machine_mode mode
;
7448 mode
= GET_MODE (mem
);
7450 /* Compute the address of the containing SImode value. */
7451 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7452 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7453 force_reg (Pmode
, GEN_INT (-4)));
7455 /* Create a memory reference for it. */
7456 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7457 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7458 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7460 /* Work out the byte offset of the QImode or HImode value,
7461 counting from the least significant byte. */
7462 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7463 if (TARGET_BIG_ENDIAN
)
7464 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7466 /* Multiply by eight to convert the shift value from bytes to bits. */
7467 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7469 /* Make the final shift an SImode value, so that it can be used in
7470 SImode operations. */
7471 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7473 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7474 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7475 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7476 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7478 /* Compute the equivalent exclusive mask. */
7479 inverted_mask
= gen_reg_rtx (SImode
);
7480 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
7481 gen_rtx_NOT (SImode
, mask
)));
7483 /* Shift the old value into place. */
7484 if (oldval
!= const0_rtx
)
7486 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7487 oldval
= force_reg (SImode
, oldval
);
7488 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7491 /* Do the same for the new value. */
7492 if (newval
&& newval
!= const0_rtx
)
7494 newval
= convert_modes (SImode
, mode
, newval
, true);
7495 newval
= force_reg (SImode
, newval
);
7496 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7499 /* Do the SImode atomic access. */
7501 res
= gen_reg_rtx (SImode
);
7503 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7505 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7507 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7513 /* Shift and convert the result. */
7514 mips_emit_binary (AND
, res
, res
, mask
);
7515 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7516 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7520 /* Return true if it is possible to use left/right accesses for a
7521 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7522 When returning true, update *LEFT and *RIGHT as follows:
7524 *LEFT is a QImode reference to the first byte if big endian or
7525 the last byte if little endian. This address can be used in the
7526 left-side instructions (LWL, SWL, LDL, SDL).
7528 *RIGHT is a QImode reference to the opposite end of the field and
7529 can be used in the patterning right-side instruction. */
7532 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7533 rtx
*left
, rtx
*right
)
7537 /* Check that the size is valid. */
7538 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7541 /* We can only access byte-aligned values. Since we are always passed
7542 a reference to the first byte of the field, it is not necessary to
7543 do anything with BITPOS after this check. */
7544 if (bitpos
% BITS_PER_UNIT
!= 0)
7547 /* Reject aligned bitfields: we want to use a normal load or store
7548 instead of a left/right pair. */
7549 if (MEM_ALIGN (op
) >= width
)
7552 /* Get references to both ends of the field. */
7553 first
= adjust_address (op
, QImode
, 0);
7554 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7556 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7557 correspond to the MSB and RIGHT to the LSB. */
7558 if (TARGET_BIG_ENDIAN
)
7559 *left
= first
, *right
= last
;
7561 *left
= last
, *right
= first
;
7566 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7567 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7568 the operation is the equivalent of:
7570 (set DEST (*_extract SRC WIDTH BITPOS))
7572 Return true on success. */
7575 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7576 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7578 rtx left
, right
, temp
;
7579 rtx dest1
= NULL_RTX
;
7581 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7582 be a DImode, create a new temp and emit a zero extend at the end. */
7583 if (GET_MODE (dest
) == DImode
7585 && GET_MODE_BITSIZE (SImode
) == width
)
7588 dest
= gen_reg_rtx (SImode
);
7591 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
7594 temp
= gen_reg_rtx (GET_MODE (dest
));
7595 if (GET_MODE (dest
) == DImode
)
7597 emit_insn (gen_mov_ldl (temp
, src
, left
));
7598 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7602 emit_insn (gen_mov_lwl (temp
, src
, left
));
7603 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7606 /* If we were loading 32bits and the original register was DI then
7607 sign/zero extend into the orignal dest. */
7611 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7613 emit_insn (gen_extendsidi2 (dest1
, dest
));
7618 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7619 BITPOS and SRC are the operands passed to the expander; the operation
7620 is the equivalent of:
7622 (set (zero_extract DEST WIDTH BITPOS) SRC)
7624 Return true on success. */
7627 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7628 HOST_WIDE_INT bitpos
)
7631 enum machine_mode mode
;
7633 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
7636 mode
= mode_for_size (width
, MODE_INT
, 0);
7637 src
= gen_lowpart (mode
, src
);
7640 emit_insn (gen_mov_sdl (dest
, src
, left
));
7641 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7645 emit_insn (gen_mov_swl (dest
, src
, left
));
7646 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7651 /* Return true if X is a MEM with the same size as MODE. */
7654 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
7657 && MEM_SIZE_KNOWN_P (x
)
7658 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7661 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7662 source of an "ext" instruction or the destination of an "ins"
7663 instruction. OP must be a register operand and the following
7664 conditions must hold:
7666 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7667 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7668 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7670 Also reject lengths equal to a word as they are better handled
7671 by the move patterns. */
7674 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7676 if (!ISA_HAS_EXT_INS
7677 || !register_operand (op
, VOIDmode
)
7678 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7681 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7684 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7690 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7691 operation if MAXLEN is the maxium length of consecutive bits that
7692 can make up MASK. MODE is the mode of the operation. See
7693 mask_low_and_shift_len for the actual definition. */
7696 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7698 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7701 /* Return true iff OP1 and OP2 are valid operands together for the
7702 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7703 see the table in the comment before the pattern. */
7706 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7708 return (memory_operand (op1
, mode
)
7709 ? and_load_operand (op2
, mode
)
7710 : and_reg_operand (op2
, mode
));
7713 /* The canonical form of a mask-low-and-shift-left operation is
7714 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7715 cleared. Thus we need to shift MASK to the right before checking if it
7716 is a valid mask value. MODE is the mode of the operation. If true
7717 return the length of the mask, otherwise return -1. */
7720 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7722 HOST_WIDE_INT shval
;
7724 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7725 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7728 /* Return true if -msplit-addresses is selected and should be honored.
7730 -msplit-addresses is a half-way house between explicit relocations
7731 and the traditional assembler macros. It can split absolute 32-bit
7732 symbolic constants into a high/lo_sum pair but uses macros for other
7735 Like explicit relocation support for REL targets, it relies
7736 on GNU extensions in the assembler and the linker.
7738 Although this code should work for -O0, it has traditionally
7739 been treated as an optimization. */
7742 mips_split_addresses_p (void)
7744 return (TARGET_SPLIT_ADDRESSES
7748 && !ABI_HAS_64BIT_SYMBOLS
);
7751 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7754 mips_init_relocs (void)
7756 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7757 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7758 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
7759 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7760 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7762 if (TARGET_MIPS16_PCREL_LOADS
)
7763 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
7766 if (ABI_HAS_64BIT_SYMBOLS
)
7768 if (TARGET_EXPLICIT_RELOCS
)
7770 mips_split_p
[SYMBOL_64_HIGH
] = true;
7771 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7772 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7774 mips_split_p
[SYMBOL_64_MID
] = true;
7775 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7776 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7778 mips_split_p
[SYMBOL_64_LOW
] = true;
7779 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7780 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7782 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7783 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7788 if (TARGET_EXPLICIT_RELOCS
7789 || mips_split_addresses_p ()
7792 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7793 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7794 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7801 /* The high part is provided by a pseudo copy of $gp. */
7802 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7803 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7805 else if (TARGET_EXPLICIT_RELOCS
)
7806 /* Small data constants are kept whole until after reload,
7807 then lowered by mips_rewrite_small_data. */
7808 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7810 if (TARGET_EXPLICIT_RELOCS
)
7812 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7815 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7816 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7820 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7821 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7824 /* Expose the use of $28 as soon as possible. */
7825 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7829 /* The HIGH and LO_SUM are matched by special .md patterns. */
7830 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7832 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7833 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7834 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7836 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7837 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7838 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7843 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7845 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7846 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7848 /* Expose the use of $28 as soon as possible. */
7849 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7855 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7856 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7857 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7860 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7861 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7863 if (TARGET_MIPS16_PCREL_LOADS
)
7865 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
7866 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
7870 mips_split_p
[SYMBOL_DTPREL
] = true;
7871 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7872 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7874 mips_split_p
[SYMBOL_TPREL
] = true;
7875 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7876 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7879 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7880 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7883 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7884 in context CONTEXT. RELOCS is the array of relocations to use. */
7887 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7888 const char **relocs
)
7890 enum mips_symbol_type symbol_type
;
7893 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7894 gcc_assert (relocs
[symbol_type
]);
7896 fputs (relocs
[symbol_type
], file
);
7897 output_addr_const (file
, mips_strip_unspec_address (op
));
7898 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7903 /* Start a new block with the given asm switch enabled. If we need
7904 to print a directive, emit PREFIX before it and SUFFIX after it. */
7907 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7908 const char *prefix
, const char *suffix
)
7910 if (asm_switch
->nesting_level
== 0)
7911 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
7912 asm_switch
->nesting_level
++;
7915 /* Likewise, but end a block. */
7918 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7919 const char *prefix
, const char *suffix
)
7921 gcc_assert (asm_switch
->nesting_level
);
7922 asm_switch
->nesting_level
--;
7923 if (asm_switch
->nesting_level
== 0)
7924 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
7927 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7928 that either print a complete line or print nothing. */
7931 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
7933 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
7937 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
7939 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
7942 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7943 The punctuation characters are:
7945 '(' Start a nested ".set noreorder" block.
7946 ')' End a nested ".set noreorder" block.
7947 '[' Start a nested ".set noat" block.
7948 ']' End a nested ".set noat" block.
7949 '<' Start a nested ".set nomacro" block.
7950 '>' End a nested ".set nomacro" block.
7951 '*' Behave like %(%< if generating a delayed-branch sequence.
7952 '#' Print a nop if in a ".set noreorder" block.
7953 '/' Like '#', but do nothing within a delayed-branch sequence.
7954 '?' Print "l" if mips_branch_likely is true
7955 '~' Print a nop if mips_branch_likely is true
7956 '.' Print the name of the register with a hard-wired zero (zero or $0).
7957 '@' Print the name of the assembler temporary register (at or $1).
7958 '^' Print the name of the pic call-through register (t9 or $25).
7959 '+' Print the name of the gp register (usually gp or $28).
7960 '$' Print the name of the stack pointer register (sp or $29).
7961 ':' Print "c" to use the compact version if the delay slot is a nop.
7962 '!' Print "s" to use the short version if the delay slot contains a
7965 See also mips_init_print_operand_pucnt. */
7968 mips_print_operand_punctuation (FILE *file
, int ch
)
7973 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
7977 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
7981 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
7985 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
7989 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
7993 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
7997 if (final_sequence
!= 0)
7999 mips_print_operand_punctuation (file
, '(');
8000 mips_print_operand_punctuation (file
, '<');
8005 if (mips_noreorder
.nesting_level
> 0)
8006 fputs ("\n\tnop", file
);
8010 /* Print an extra newline so that the delayed insn is separated
8011 from the following ones. This looks neater and is consistent
8012 with non-nop delayed sequences. */
8013 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
8014 fputs ("\n\tnop\n", file
);
8018 if (mips_branch_likely
)
8023 if (mips_branch_likely
)
8024 fputs ("\n\tnop", file
);
8028 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
8032 fputs (reg_names
[AT_REGNUM
], file
);
8036 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
8040 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
8044 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
8048 /* When final_sequence is 0, the delay slot will be a nop. We can
8049 use the compact version for microMIPS. */
8050 if (final_sequence
== 0)
8055 /* If the delay slot instruction is short, then use the
8057 if (final_sequence
== 0
8058 || get_attr_length (XVECEXP (final_sequence
, 0, 1)) == 2)
8068 /* Initialize mips_print_operand_punct. */
8071 mips_init_print_operand_punct (void)
8075 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
8076 mips_print_operand_punct
[(unsigned char) *p
] = true;
8079 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8080 associated with condition CODE. Print the condition part of the
8084 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8098 /* Conveniently, the MIPS names for these conditions are the same
8099 as their RTL equivalents. */
8100 fputs (GET_RTX_NAME (code
), file
);
8104 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8109 /* Likewise floating-point branches. */
8112 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8117 fputs ("c1f", file
);
8121 fputs ("c1t", file
);
8125 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8130 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8133 mips_print_operand_punct_valid_p (unsigned char code
)
8135 return mips_print_operand_punct
[code
];
8138 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8140 'X' Print CONST_INT OP in hexadecimal format.
8141 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8142 'd' Print CONST_INT OP in decimal.
8143 'm' Print one less than CONST_INT OP in decimal.
8144 'h' Print the high-part relocation associated with OP, after stripping
8146 'R' Print the low-part relocation associated with OP.
8147 'C' Print the integer branch condition for comparison OP.
8148 'N' Print the inverse of the integer branch condition for comparison OP.
8149 'F' Print the FPU branch condition for comparison OP.
8150 'W' Print the inverse of the FPU branch condition for comparison OP.
8151 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8152 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8153 't' Like 'T', but with the EQ/NE cases reversed
8154 'Y' Print mips_fp_conditions[INTVAL (OP)]
8155 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8156 'q' Print a DSP accumulator register.
8157 'D' Print the second part of a double-word register or memory operand.
8158 'L' Print the low-order register in a double-word register operand.
8159 'M' Print high-order register in a double-word register operand.
8160 'z' Print $0 if OP is zero, otherwise print OP normally.
8161 'b' Print the address of a memory operand, without offset. */
8164 mips_print_operand (FILE *file
, rtx op
, int letter
)
8168 if (mips_print_operand_punct_valid_p (letter
))
8170 mips_print_operand_punctuation (file
, letter
);
8175 code
= GET_CODE (op
);
8180 if (CONST_INT_P (op
))
8181 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8183 output_operand_lossage ("invalid use of '%%%c'", letter
);
8187 if (CONST_INT_P (op
))
8188 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8190 output_operand_lossage ("invalid use of '%%%c'", letter
);
8194 if (CONST_INT_P (op
))
8195 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8197 output_operand_lossage ("invalid use of '%%%c'", letter
);
8201 if (CONST_INT_P (op
))
8202 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
8204 output_operand_lossage ("invalid use of '%%%c'", letter
);
8210 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
8214 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
8218 mips_print_int_branch_condition (file
, code
, letter
);
8222 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
8226 mips_print_float_branch_condition (file
, code
, letter
);
8230 mips_print_float_branch_condition (file
, reverse_condition (code
),
8237 int truth
= (code
== NE
) == (letter
== 'T');
8238 fputc ("zfnt"[truth
* 2 + ST_REG_P (REGNO (XEXP (op
, 0)))], file
);
8243 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
8244 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
8246 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8253 mips_print_operand (file
, op
, 0);
8259 if (code
== REG
&& MD_REG_P (REGNO (op
)))
8260 fprintf (file
, "$ac0");
8261 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
8262 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
8264 output_operand_lossage ("invalid use of '%%%c'", letter
);
8272 unsigned int regno
= REGNO (op
);
8273 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
8274 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
8277 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
8278 output_operand_lossage ("invalid use of '%%%c'", letter
);
8279 /* We need to print $0 .. $31 for COP0 registers. */
8280 if (COP0_REG_P (regno
))
8281 fprintf (file
, "$%s", ®_names
[regno
][4]);
8283 fprintf (file
, "%s", reg_names
[regno
]);
8289 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
8290 else if (letter
== 'b')
8292 gcc_assert (REG_P (XEXP (op
, 0)));
8293 mips_print_operand (file
, XEXP (op
, 0), 0);
8295 else if (letter
&& letter
!= 'z')
8296 output_operand_lossage ("invalid use of '%%%c'", letter
);
8298 output_address (XEXP (op
, 0));
8302 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
8303 fputs (reg_names
[GP_REG_FIRST
], file
);
8304 else if (letter
&& letter
!= 'z')
8305 output_operand_lossage ("invalid use of '%%%c'", letter
);
8306 else if (CONST_GP_P (op
))
8307 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
8309 output_addr_const (file
, mips_strip_unspec_address (op
));
8315 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8318 mips_print_operand_address (FILE *file
, rtx x
)
8320 struct mips_address_info addr
;
8322 if (mips_classify_address (&addr
, x
, word_mode
, true))
8326 mips_print_operand (file
, addr
.offset
, 0);
8327 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8330 case ADDRESS_LO_SUM
:
8331 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8333 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8336 case ADDRESS_CONST_INT
:
8337 output_addr_const (file
, x
);
8338 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8341 case ADDRESS_SYMBOLIC
:
8342 output_addr_const (file
, mips_strip_unspec_address (x
));
8348 /* Implement TARGET_ENCODE_SECTION_INFO. */
8351 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8353 default_encode_section_info (decl
, rtl
, first
);
8355 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8357 rtx symbol
= XEXP (rtl
, 0);
8358 tree type
= TREE_TYPE (decl
);
8360 /* Encode whether the symbol is short or long. */
8361 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8362 || mips_far_type_p (type
))
8363 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8367 /* Implement TARGET_SELECT_RTX_SECTION. */
8370 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
8371 unsigned HOST_WIDE_INT align
)
8373 /* ??? Consider using mergeable small data sections. */
8374 if (mips_rtx_constant_in_small_data_p (mode
))
8375 return get_named_section (NULL
, ".sdata", 0);
8377 return default_elf_select_rtx_section (mode
, x
, align
);
8380 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8382 The complication here is that, with the combination TARGET_ABICALLS
8383 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8384 absolute addresses, and should therefore not be included in the
8385 read-only part of a DSO. Handle such cases by selecting a normal
8386 data section instead of a read-only one. The logic apes that in
8387 default_function_rodata_section. */
8390 mips_function_rodata_section (tree decl
)
8392 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8393 return default_function_rodata_section (decl
);
8395 if (decl
&& DECL_SECTION_NAME (decl
))
8397 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8398 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8400 char *rname
= ASTRDUP (name
);
8402 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8404 else if (flag_function_sections
8405 && flag_data_sections
8406 && strncmp (name
, ".text.", 6) == 0)
8408 char *rname
= ASTRDUP (name
);
8409 memcpy (rname
+ 1, "data", 4);
8410 return get_section (rname
, SECTION_WRITE
, decl
);
8413 return data_section
;
8416 /* Implement TARGET_IN_SMALL_DATA_P. */
8419 mips_in_small_data_p (const_tree decl
)
8421 unsigned HOST_WIDE_INT size
;
8423 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8426 /* We don't yet generate small-data references for -mabicalls
8427 or VxWorks RTP code. See the related -G handling in
8428 mips_option_override. */
8429 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8432 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8436 /* Reject anything that isn't in a known small-data section. */
8437 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8438 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8441 /* If a symbol is defined externally, the assembler will use the
8442 usual -G rules when deciding how to implement macros. */
8443 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8446 else if (TARGET_EMBEDDED_DATA
)
8448 /* Don't put constants into the small data section: we want them
8449 to be in ROM rather than RAM. */
8450 if (TREE_CODE (decl
) != VAR_DECL
)
8453 if (TREE_READONLY (decl
)
8454 && !TREE_SIDE_EFFECTS (decl
)
8455 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8459 /* Enforce -mlocal-sdata. */
8460 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8463 /* Enforce -mextern-sdata. */
8464 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8466 if (DECL_EXTERNAL (decl
))
8468 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8472 /* We have traditionally not treated zero-sized objects as small data,
8473 so this is now effectively part of the ABI. */
8474 size
= int_size_in_bytes (TREE_TYPE (decl
));
8475 return size
> 0 && size
<= mips_small_data_threshold
;
8478 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8479 anchors for small data: the GP register acts as an anchor in that
8480 case. We also don't want to use them for PC-relative accesses,
8481 where the PC acts as an anchor. */
8484 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8486 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8488 case SYMBOL_PC_RELATIVE
:
8489 case SYMBOL_GP_RELATIVE
:
8493 return default_use_anchors_for_symbol_p (symbol
);
8497 /* The MIPS debug format wants all automatic variables and arguments
8498 to be in terms of the virtual frame pointer (stack pointer before
8499 any adjustment in the function), while the MIPS 3.0 linker wants
8500 the frame pointer to be the stack pointer after the initial
8501 adjustment. So, we do the adjustment here. The arg pointer (which
8502 is eliminated) points to the virtual frame pointer, while the frame
8503 pointer (which may be eliminated) points to the stack pointer after
8504 the initial adjustments. */
8507 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8509 rtx offset2
= const0_rtx
;
8510 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8513 offset
= INTVAL (offset2
);
8515 if (reg
== stack_pointer_rtx
8516 || reg
== frame_pointer_rtx
8517 || reg
== hard_frame_pointer_rtx
)
8519 offset
-= cfun
->machine
->frame
.total_size
;
8520 if (reg
== hard_frame_pointer_rtx
)
8521 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8527 /* Implement ASM_OUTPUT_EXTERNAL. */
8530 mips_output_external (FILE *file
, tree decl
, const char *name
)
8532 default_elf_asm_output_external (file
, decl
, name
);
8534 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8535 set in order to avoid putting out names that are never really
8537 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8539 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8541 /* When using assembler macros, emit .extern directives for
8542 all small-data externs so that the assembler knows how
8545 In most cases it would be safe (though pointless) to emit
8546 .externs for other symbols too. One exception is when an
8547 object is within the -G limit but declared by the user to
8548 be in a section other than .sbss or .sdata. */
8549 fputs ("\t.extern\t", file
);
8550 assemble_name (file
, name
);
8551 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8552 int_size_in_bytes (TREE_TYPE (decl
)));
8557 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8560 mips_output_filename (FILE *stream
, const char *name
)
8562 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8564 if (write_symbols
== DWARF2_DEBUG
)
8566 else if (mips_output_filename_first_time
)
8568 mips_output_filename_first_time
= 0;
8569 num_source_filenames
+= 1;
8570 current_function_file
= name
;
8571 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8572 output_quoted_string (stream
, name
);
8573 putc ('\n', stream
);
8575 /* If we are emitting stabs, let dbxout.c handle this (except for
8576 the mips_output_filename_first_time case). */
8577 else if (write_symbols
== DBX_DEBUG
)
8579 else if (name
!= current_function_file
8580 && strcmp (name
, current_function_file
) != 0)
8582 num_source_filenames
+= 1;
8583 current_function_file
= name
;
8584 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8585 output_quoted_string (stream
, name
);
8586 putc ('\n', stream
);
8590 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8592 static void ATTRIBUTE_UNUSED
8593 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8598 fputs ("\t.dtprelword\t", file
);
8602 fputs ("\t.dtpreldword\t", file
);
8608 output_addr_const (file
, x
);
8609 fputs ("+0x8000", file
);
8612 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8615 mips_dwarf_register_span (rtx reg
)
8618 enum machine_mode mode
;
8620 /* By default, GCC maps increasing register numbers to increasing
8621 memory locations, but paired FPRs are always little-endian,
8622 regardless of the prevailing endianness. */
8623 mode
= GET_MODE (reg
);
8624 if (FP_REG_P (REGNO (reg
))
8625 && TARGET_BIG_ENDIAN
8626 && MAX_FPRS_PER_FMT
> 1
8627 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8629 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8630 high
= mips_subword (reg
, true);
8631 low
= mips_subword (reg
, false);
8632 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8638 /* DSP ALU can bypass data with no delays for the following pairs. */
8639 enum insn_code dspalu_bypass_table
[][2] =
8641 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
8642 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
8643 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
8644 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
8645 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
8646 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
8647 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
8648 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
8652 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
8655 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
8656 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
8657 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
8659 for (i
= 0; i
< num_bypass
; i
++)
8661 if (out_icode
== dspalu_bypass_table
[i
][0]
8662 && in_icode
== dspalu_bypass_table
[i
][1])
8668 /* Implement ASM_OUTPUT_ASCII. */
8671 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8677 fprintf (stream
, "\t.ascii\t\"");
8678 for (i
= 0; i
< len
; i
++)
8682 c
= (unsigned char) string
[i
];
8685 if (c
== '\\' || c
== '\"')
8687 putc ('\\', stream
);
8695 fprintf (stream
, "\\%03o", c
);
8699 if (cur_pos
> 72 && i
+1 < len
)
8702 fprintf (stream
, "\"\n\t.ascii\t\"");
8705 fprintf (stream
, "\"\n");
8708 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8709 Update *ADDR with the operand that should be printed. */
8712 mips_output_tls_reloc_directive (rtx
*addr
)
8714 enum mips_symbol_type type
;
8716 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
8717 *addr
= mips_strip_unspec_address (*addr
);
8721 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
8724 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
8731 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8732 macros, mark the symbol as written so that mips_asm_output_external
8733 won't emit an .extern for it. STREAM is the output file, NAME is the
8734 name of the symbol, INIT_STRING is the string that should be written
8735 before the symbol and FINAL_STRING is the string that should be
8736 written after it. FINAL_STRING is a printf format that consumes the
8737 remaining arguments. */
8740 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
8741 const char *final_string
, ...)
8745 fputs (init_string
, stream
);
8746 assemble_name (stream
, name
);
8747 va_start (ap
, final_string
);
8748 vfprintf (stream
, final_string
, ap
);
8751 if (!TARGET_EXPLICIT_RELOCS
)
8753 tree name_tree
= get_identifier (name
);
8754 TREE_ASM_WRITTEN (name_tree
) = 1;
8758 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8759 NAME is the name of the object and ALIGN is the required alignment
8760 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8761 alignment argument. */
8764 mips_declare_common_object (FILE *stream
, const char *name
,
8765 const char *init_string
,
8766 unsigned HOST_WIDE_INT size
,
8767 unsigned int align
, bool takes_alignment_p
)
8769 if (!takes_alignment_p
)
8771 size
+= (align
/ BITS_PER_UNIT
) - 1;
8772 size
-= size
% (align
/ BITS_PER_UNIT
);
8773 mips_declare_object (stream
, name
, init_string
,
8774 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8777 mips_declare_object (stream
, name
, init_string
,
8778 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
8779 size
, align
/ BITS_PER_UNIT
);
8782 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8783 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8786 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8787 unsigned HOST_WIDE_INT size
,
8790 /* If the target wants uninitialized const declarations in
8791 .rdata then don't put them in .comm. */
8792 if (TARGET_EMBEDDED_DATA
8793 && TARGET_UNINIT_CONST_IN_RODATA
8794 && TREE_CODE (decl
) == VAR_DECL
8795 && TREE_READONLY (decl
)
8796 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8798 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8799 targetm
.asm_out
.globalize_label (stream
, name
);
8801 switch_to_section (readonly_data_section
);
8802 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8803 mips_declare_object (stream
, name
, "",
8804 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8808 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8812 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8813 extern int size_directive_output
;
8815 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8816 definitions except that it uses mips_declare_object to emit the label. */
8819 mips_declare_object_name (FILE *stream
, const char *name
,
8820 tree decl ATTRIBUTE_UNUSED
)
8822 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8823 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8826 size_directive_output
= 0;
8827 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8831 size_directive_output
= 1;
8832 size
= int_size_in_bytes (TREE_TYPE (decl
));
8833 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8836 mips_declare_object (stream
, name
, "", ":\n");
8839 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8842 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8846 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8847 if (!flag_inhibit_size_directive
8848 && DECL_SIZE (decl
) != 0
8851 && DECL_INITIAL (decl
) == error_mark_node
8852 && !size_directive_output
)
8856 size_directive_output
= 1;
8857 size
= int_size_in_bytes (TREE_TYPE (decl
));
8858 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8863 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8864 with the current ABI. */
8867 mips_mdebug_abi_name (void)
8880 return TARGET_64BIT
? "eabi64" : "eabi32";
8886 /* Implement TARGET_ASM_FILE_START. */
8889 mips_file_start (void)
8891 default_file_start ();
8893 /* Generate a special section to describe the ABI switches used to
8894 produce the resultant binary. */
8896 /* Record the ABI itself. Modern versions of binutils encode
8897 this information in the ELF header flags, but GDB needs the
8898 information in order to correctly debug binaries produced by
8899 older binutils. See the function mips_gdbarch_init in
8901 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8902 mips_mdebug_abi_name ());
8904 /* There is no ELF header flag to distinguish long32 forms of the
8905 EABI from long64 forms. Emit a special section to help tools
8906 such as GDB. Do the same for o64, which is sometimes used with
8908 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
8909 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
8910 "\t.previous\n", TARGET_LONG64
? 64 : 32);
8912 /* Record the NaN encoding. */
8913 if (HAVE_AS_NAN
|| mips_nan
!= MIPS_IEEE_754_DEFAULT
)
8914 fprintf (asm_out_file
, "\t.nan\t%s\n",
8915 mips_nan
== MIPS_IEEE_754_2008
? "2008" : "legacy");
8917 #ifdef HAVE_AS_GNU_ATTRIBUTE
8921 /* No floating-point operations, -mno-float. */
8922 if (TARGET_NO_FLOAT
)
8924 /* Soft-float code, -msoft-float. */
8925 else if (!TARGET_HARD_FLOAT_ABI
)
8927 /* Single-float code, -msingle-float. */
8928 else if (!TARGET_DOUBLE_FLOAT
)
8930 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8931 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
8933 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8937 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
8941 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8942 if (TARGET_ABICALLS
)
8944 fprintf (asm_out_file
, "\t.abicalls\n");
8945 if (TARGET_ABICALLS_PIC0
)
8946 fprintf (asm_out_file
, "\t.option\tpic0\n");
8949 if (flag_verbose_asm
)
8950 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8952 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
8955 /* Implement TARGET_ASM_CODE_END. */
8958 mips_code_end (void)
8960 mips_finish_stub (&mips16_rdhwr_stub
);
8963 /* Make the last instruction frame-related and note that it performs
8964 the operation described by FRAME_PATTERN. */
8967 mips_set_frame_expr (rtx frame_pattern
)
8971 insn
= get_last_insn ();
8972 RTX_FRAME_RELATED_P (insn
) = 1;
8973 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8978 /* Return a frame-related rtx that stores REG at MEM.
8979 REG must be a single register. */
8982 mips_frame_set (rtx mem
, rtx reg
)
8986 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
8987 RTX_FRAME_RELATED_P (set
) = 1;
8992 /* Record that the epilogue has restored call-saved register REG. */
8995 mips_add_cfa_restore (rtx reg
)
8997 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
8998 mips_epilogue
.cfa_restores
);
9001 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9002 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9003 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9004 static const unsigned char mips16e_s2_s8_regs
[] = {
9005 30, 23, 22, 21, 20, 19, 18
9007 static const unsigned char mips16e_a0_a3_regs
[] = {
9011 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9012 ordered from the uppermost in memory to the lowest in memory. */
9013 static const unsigned char mips16e_save_restore_regs
[] = {
9014 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9017 /* Return the index of the lowest X in the range [0, SIZE) for which
9018 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9021 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
9026 for (i
= 0; i
< size
; i
++)
9027 if (BITSET_P (mask
, regs
[i
]))
9033 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9034 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9035 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9036 is true for all indexes (X, SIZE). */
9039 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
9040 unsigned int size
, unsigned int *num_regs_ptr
)
9044 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
9045 for (i
++; i
< size
; i
++)
9046 if (!BITSET_P (*mask_ptr
, regs
[i
]))
9049 *mask_ptr
|= 1 << regs
[i
];
9053 /* Return a simplified form of X using the register values in REG_VALUES.
9054 REG_VALUES[R] is the last value assigned to hard register R, or null
9055 if R has not been modified.
9057 This function is rather limited, but is good enough for our purposes. */
9060 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
9062 x
= avoid_constant_pool_reference (x
);
9066 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9067 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
9068 x0
, GET_MODE (XEXP (x
, 0)));
9071 if (ARITHMETIC_P (x
))
9073 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9074 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
9075 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
9079 && reg_values
[REGNO (x
)]
9080 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
9081 return reg_values
[REGNO (x
)];
9086 /* Return true if (set DEST SRC) stores an argument register into its
9087 caller-allocated save slot, storing the number of that argument
9088 register in *REGNO_PTR if so. REG_VALUES is as for
9089 mips16e_collect_propagate_value. */
9092 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
9093 unsigned int *regno_ptr
)
9095 unsigned int argno
, regno
;
9096 HOST_WIDE_INT offset
, required_offset
;
9099 /* Check that this is a word-mode store. */
9100 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
9103 /* Check that the register being saved is an unmodified argument
9105 regno
= REGNO (src
);
9106 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
9108 argno
= regno
- GP_ARG_FIRST
;
9110 /* Check whether the address is an appropriate stack-pointer or
9111 frame-pointer access. */
9112 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
9113 mips_split_plus (addr
, &base
, &offset
);
9114 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
9115 if (base
== hard_frame_pointer_rtx
)
9116 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9117 else if (base
!= stack_pointer_rtx
)
9119 if (offset
!= required_offset
)
9126 /* A subroutine of mips_expand_prologue, called only when generating
9127 MIPS16e SAVE instructions. Search the start of the function for any
9128 instructions that save argument registers into their caller-allocated
9129 save slots. Delete such instructions and return a value N such that
9130 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9131 instructions redundant. */
9134 mips16e_collect_argument_saves (void)
9136 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
9137 rtx insn
, next
, set
, dest
, src
;
9138 unsigned int nargs
, regno
;
9140 push_topmost_sequence ();
9142 memset (reg_values
, 0, sizeof (reg_values
));
9143 for (insn
= get_insns (); insn
; insn
= next
)
9145 next
= NEXT_INSN (insn
);
9146 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
9152 set
= PATTERN (insn
);
9153 if (GET_CODE (set
) != SET
)
9156 dest
= SET_DEST (set
);
9157 src
= SET_SRC (set
);
9158 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
9160 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
9163 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
9166 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
9167 reg_values
[REGNO (dest
)]
9168 = mips16e_collect_propagate_value (src
, reg_values
);
9172 pop_topmost_sequence ();
9177 /* Return a move between register REGNO and memory location SP + OFFSET.
9178 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9179 Make the move a load if RESTORE_P, otherwise make it a store. */
9182 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
9183 HOST_WIDE_INT offset
, unsigned int regno
)
9187 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
9189 reg
= gen_rtx_REG (SImode
, regno
);
9192 mips_add_cfa_restore (reg
);
9193 return gen_rtx_SET (VOIDmode
, reg
, mem
);
9196 return gen_rtx_SET (VOIDmode
, mem
, reg
);
9197 return mips_frame_set (mem
, reg
);
9200 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9201 The instruction must:
9203 - Allocate or deallocate SIZE bytes in total; SIZE is known
9206 - Save or restore as many registers in *MASK_PTR as possible.
9207 The instruction saves the first registers at the top of the
9208 allocated area, with the other registers below it.
9210 - Save NARGS argument registers above the allocated area.
9212 (NARGS is always zero if RESTORE_P.)
9214 The SAVE and RESTORE instructions cannot save and restore all general
9215 registers, so there may be some registers left over for the caller to
9216 handle. Destructively modify *MASK_PTR so that it contains the registers
9217 that still need to be saved or restored. The caller can save these
9218 registers in the memory immediately below *OFFSET_PTR, which is a
9219 byte offset from the bottom of the allocated stack area. */
9222 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
9223 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
9227 HOST_WIDE_INT offset
, top_offset
;
9228 unsigned int i
, regno
;
9231 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
9233 /* Calculate the number of elements in the PARALLEL. We need one element
9234 for the stack adjustment, one for each argument register save, and one
9235 for each additional register move. */
9237 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9238 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
9241 /* Create the final PARALLEL. */
9242 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
9245 /* Add the stack pointer adjustment. */
9246 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9247 plus_constant (Pmode
, stack_pointer_rtx
,
9248 restore_p
? size
: -size
));
9249 RTX_FRAME_RELATED_P (set
) = 1;
9250 XVECEXP (pattern
, 0, n
++) = set
;
9252 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9253 top_offset
= restore_p
? size
: 0;
9255 /* Save the arguments. */
9256 for (i
= 0; i
< nargs
; i
++)
9258 offset
= top_offset
+ i
* UNITS_PER_WORD
;
9259 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
9261 XVECEXP (pattern
, 0, n
++) = set
;
9264 /* Then fill in the other register moves. */
9265 offset
= top_offset
;
9266 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9268 regno
= mips16e_save_restore_regs
[i
];
9269 if (BITSET_P (*mask_ptr
, regno
))
9271 offset
-= UNITS_PER_WORD
;
9272 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
9273 XVECEXP (pattern
, 0, n
++) = set
;
9274 *mask_ptr
&= ~(1 << regno
);
9278 /* Tell the caller what offset it should use for the remaining registers. */
9279 *offset_ptr
= size
+ (offset
- top_offset
);
9281 gcc_assert (n
== XVECLEN (pattern
, 0));
9286 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9287 pointer. Return true if PATTERN matches the kind of instruction
9288 generated by mips16e_build_save_restore. If INFO is nonnull,
9289 initialize it when returning true. */
9292 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
9293 struct mips16e_save_restore_info
*info
)
9295 unsigned int i
, nargs
, mask
, extra
;
9296 HOST_WIDE_INT top_offset
, save_offset
, offset
;
9297 rtx set
, reg
, mem
, base
;
9300 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
9303 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9304 top_offset
= adjust
> 0 ? adjust
: 0;
9306 /* Interpret all other members of the PARALLEL. */
9307 save_offset
= top_offset
- UNITS_PER_WORD
;
9311 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
9313 /* Check that we have a SET. */
9314 set
= XVECEXP (pattern
, 0, n
);
9315 if (GET_CODE (set
) != SET
)
9318 /* Check that the SET is a load (if restoring) or a store
9320 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
9324 /* Check that the address is the sum of the stack pointer and a
9325 possibly-zero constant offset. */
9326 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
9327 if (base
!= stack_pointer_rtx
)
9330 /* Check that SET's other operand is a register. */
9331 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
9335 /* Check for argument saves. */
9336 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
9337 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
9339 else if (offset
== save_offset
)
9341 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
9342 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
9345 mask
|= 1 << REGNO (reg
);
9346 save_offset
-= UNITS_PER_WORD
;
9352 /* Check that the restrictions on register ranges are met. */
9354 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
9355 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
9356 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
9357 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
9361 /* Make sure that the topmost argument register is not saved twice.
9362 The checks above ensure that the same is then true for the other
9363 argument registers. */
9364 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9367 /* Pass back information, if requested. */
9370 info
->nargs
= nargs
;
9372 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9378 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9379 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9380 the null terminator. */
9383 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9384 unsigned int max_reg
)
9386 if (min_reg
!= max_reg
)
9387 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9389 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9393 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9394 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9397 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9399 static char buffer
[300];
9401 struct mips16e_save_restore_info info
;
9402 unsigned int i
, end
;
9405 /* Parse the pattern. */
9406 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9409 /* Add the mnemonic. */
9410 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9413 /* Save the arguments. */
9415 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9416 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9417 else if (info
.nargs
== 1)
9418 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9420 /* Emit the amount of stack space to allocate or deallocate. */
9421 s
+= sprintf (s
, "%d", (int) info
.size
);
9423 /* Save or restore $16. */
9424 if (BITSET_P (info
.mask
, 16))
9425 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9427 /* Save or restore $17. */
9428 if (BITSET_P (info
.mask
, 17))
9429 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9431 /* Save or restore registers in the range $s2...$s8, which
9432 mips16e_s2_s8_regs lists in decreasing order. Note that this
9433 is a software register range; the hardware registers are not
9434 numbered consecutively. */
9435 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9436 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9438 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9439 mips16e_s2_s8_regs
[i
]);
9441 /* Save or restore registers in the range $a0...$a3. */
9442 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9443 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9445 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9446 mips16e_a0_a3_regs
[end
- 1]);
9448 /* Save or restore $31. */
9449 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9450 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9455 /* Return true if the current function returns its value in a floating-point
9456 register in MIPS16 mode. */
9459 mips16_cfun_returns_in_fpr_p (void)
9461 tree return_type
= DECL_RESULT (current_function_decl
);
9462 return (TARGET_MIPS16
9463 && TARGET_HARD_FLOAT_ABI
9464 && !aggregate_value_p (return_type
, current_function_decl
)
9465 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9468 /* Return true if predicate PRED is true for at least one instruction.
9469 Cache the result in *CACHE, and assume that the result is true
9470 if *CACHE is already true. */
9473 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx
))
9479 push_topmost_sequence ();
9480 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9481 if (USEFUL_INSN_P (insn
) && pred (insn
))
9486 pop_topmost_sequence ();
9491 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9492 See mips_cfun_has_inflexible_gp_ref_p for details. */
9495 mips_insn_has_inflexible_gp_ref_p (rtx insn
)
9497 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9498 indicate that the target could be a traditional MIPS
9499 lazily-binding stub. */
9500 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9503 /* Return true if the current function refers to the global pointer
9504 in a way that forces $28 to be valid. This means that we can't
9505 change the choice of global pointer, even for NewABI code.
9507 One example of this (and one which needs several checks) is that
9508 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9509 (This restriction does not apply to PLTs.) */
9512 mips_cfun_has_inflexible_gp_ref_p (void)
9514 /* If the function has a nonlocal goto, $28 must hold the correct
9515 global pointer for the target function. That is, the target
9516 of the goto implicitly uses $28. */
9517 if (crtl
->has_nonlocal_goto
)
9520 if (TARGET_ABICALLS_PIC2
)
9522 /* Symbolic accesses implicitly use the global pointer unless
9523 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9524 might go to traditional MIPS lazy-binding stubs. */
9525 if (!TARGET_EXPLICIT_RELOCS
)
9528 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9529 can be lazily-bound. */
9533 /* MIPS16 functions that return in FPRs need to call an
9534 external libgcc routine. This call is only made explict
9535 during mips_expand_epilogue, and it too might be lazily bound. */
9536 if (mips16_cfun_returns_in_fpr_p ())
9540 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9541 mips_insn_has_inflexible_gp_ref_p
);
9544 /* Return true if INSN refers to the global pointer in a "flexible" way.
9545 See mips_cfun_has_flexible_gp_ref_p for details. */
9548 mips_insn_has_flexible_gp_ref_p (rtx insn
)
9550 return (get_attr_got (insn
) != GOT_UNSET
9551 || mips_small_data_pattern_p (PATTERN (insn
))
9552 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9555 /* Return true if the current function references the global pointer,
9556 but if those references do not inherently require the global pointer
9557 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9560 mips_cfun_has_flexible_gp_ref_p (void)
9562 /* Reload can sometimes introduce constant pool references
9563 into a function that otherwise didn't need them. For example,
9564 suppose we have an instruction like:
9566 (set (reg:DF R1) (float:DF (reg:SI R2)))
9568 If R2 turns out to be a constant such as 1, the instruction may
9569 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9570 the option of using this constant if R2 doesn't get allocated
9573 In cases like these, reload will have added the constant to the
9574 pool but no instruction will yet refer to it. */
9575 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9578 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9579 mips_insn_has_flexible_gp_ref_p
);
9582 /* Return the register that should be used as the global pointer
9583 within this function. Return INVALID_REGNUM if the function
9584 doesn't need a global pointer. */
9587 mips_global_pointer (void)
9591 /* $gp is always available unless we're using a GOT. */
9592 if (!TARGET_USE_GOT
)
9593 return GLOBAL_POINTER_REGNUM
;
9595 /* If there are inflexible references to $gp, we must use the
9596 standard register. */
9597 if (mips_cfun_has_inflexible_gp_ref_p ())
9598 return GLOBAL_POINTER_REGNUM
;
9600 /* If there are no current references to $gp, then the only uses
9601 we can introduce later are those involved in long branches. */
9602 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9603 return INVALID_REGNUM
;
9605 /* If the global pointer is call-saved, try to use a call-clobbered
9607 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9608 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9609 if (!df_regs_ever_live_p (regno
)
9610 && call_really_used_regs
[regno
]
9611 && !fixed_regs
[regno
]
9612 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9615 return GLOBAL_POINTER_REGNUM
;
9618 /* Return true if the current function's prologue must load the global
9619 pointer value into pic_offset_table_rtx and store the same value in
9620 the function's cprestore slot (if any).
9622 One problem we have to deal with is that, when emitting GOT-based
9623 position independent code, long-branch sequences will need to load
9624 the address of the branch target from the GOT. We don't know until
9625 the very end of compilation whether (and where) the function needs
9626 long branches, so we must ensure that _any_ branch can access the
9627 global pointer in some form. However, we do not want to pessimize
9628 the usual case in which all branches are short.
9630 We handle this as follows:
9632 (1) During reload, we set cfun->machine->global_pointer to
9633 INVALID_REGNUM if we _know_ that the current function
9634 doesn't need a global pointer. This is only valid if
9635 long branches don't need the GOT.
9637 Otherwise, we assume that we might need a global pointer
9638 and pick an appropriate register.
9640 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9641 we ensure that the global pointer is available at every
9642 block boundary bar entry and exit. We do this in one of two ways:
9644 - If the function has a cprestore slot, we ensure that this
9645 slot is valid at every branch. However, as explained in
9646 point (6) below, there is no guarantee that pic_offset_table_rtx
9647 itself is valid if new uses of the global pointer are introduced
9648 after the first post-epilogue split.
9650 We guarantee that the cprestore slot is valid by loading it
9651 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9652 this register live at every block boundary bar function entry
9653 and exit. It is then invalid to move the load (and thus the
9654 preceding store) across a block boundary.
9656 - If the function has no cprestore slot, we guarantee that
9657 pic_offset_table_rtx itself is valid at every branch.
9659 See mips_eh_uses for the handling of the register liveness.
9661 (3) During prologue and epilogue generation, we emit "ghost"
9662 placeholder instructions to manipulate the global pointer.
9664 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9665 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9666 that the function needs a global pointer. (There is no need to set
9667 them earlier than this, and doing it as late as possible leads to
9668 fewer false positives.)
9670 (5) If cfun->machine->must_initialize_gp_p is true during a
9671 split_insns pass, we split the ghost instructions into real
9672 instructions. These split instructions can then be optimized in
9673 the usual way. Otherwise, we keep the ghost instructions intact,
9674 and optimize for the case where they aren't needed. We still
9675 have the option of splitting them later, if we need to introduce
9676 new uses of the global pointer.
9678 For example, the scheduler ignores a ghost instruction that
9679 stores $28 to the stack, but it handles the split form of
9680 the ghost instruction as an ordinary store.
9682 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9683 is true during the first post-epilogue split_insns pass, we split
9684 calls and restore_gp patterns into instructions that explicitly
9685 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9686 we split these patterns into instructions that _don't_ load from
9689 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9690 time of the split, then any instructions that exist at that time
9691 can make free use of pic_offset_table_rtx. However, if we want
9692 to introduce new uses of the global pointer after the split,
9693 we must explicitly load the value from the cprestore slot, since
9694 pic_offset_table_rtx itself might not be valid at a given point
9697 The idea is that we want to be able to delete redundant
9698 loads from the cprestore slot in the usual case where no
9699 long branches are needed.
9701 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9702 of md_reorg, we decide whether the global pointer is needed for
9703 long branches. If so, we set cfun->machine->must_initialize_gp_p
9704 to true and split the ghost instructions into real instructions
9707 Note that the ghost instructions must have a zero length for three reasons:
9709 - Giving the length of the underlying $gp sequence might cause
9710 us to use long branches in cases where they aren't really needed.
9712 - They would perturb things like alignment calculations.
9714 - More importantly, the hazard detection in md_reorg relies on
9715 empty instructions having a zero length.
9717 If we find a long branch and split the ghost instructions at the
9718 end of md_reorg, the split could introduce more long branches.
9719 That isn't a problem though, because we still do the split before
9720 the final shorten_branches pass.
9722 This is extremely ugly, but it seems like the best compromise between
9723 correctness and efficiency. */
9726 mips_must_initialize_gp_p (void)
9728 return cfun
->machine
->must_initialize_gp_p
;
9731 /* Return true if REGNO is a register that is ordinarily call-clobbered
9732 but must nevertheless be preserved by an interrupt handler. */
9735 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
9737 if (MD_REG_P (regno
))
9740 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
9743 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
9745 /* $0 is hard-wired. */
9746 if (regno
== GP_REG_FIRST
)
9749 /* The interrupt handler can treat kernel registers as
9750 scratch registers. */
9751 if (KERNEL_REG_P (regno
))
9754 /* The function will return the stack pointer to its original value
9756 if (regno
== STACK_POINTER_REGNUM
)
9759 /* Otherwise, return true for registers that aren't ordinarily
9761 return call_really_used_regs
[regno
];
9767 /* Return true if the current function should treat register REGNO
9771 mips_cfun_call_saved_reg_p (unsigned int regno
)
9773 /* If the user makes an ordinarily-call-saved register global,
9774 that register is no longer call-saved. */
9775 if (global_regs
[regno
])
9778 /* Interrupt handlers need to save extra registers. */
9779 if (cfun
->machine
->interrupt_handler_p
9780 && mips_interrupt_extra_call_saved_reg_p (regno
))
9783 /* call_insns preserve $28 unless they explicitly say otherwise,
9784 so call_really_used_regs[] treats $28 as call-saved. However,
9785 we want the ABI property rather than the default call_insn
9787 return (regno
== GLOBAL_POINTER_REGNUM
9788 ? TARGET_CALL_SAVED_GP
9789 : !call_really_used_regs
[regno
]);
9792 /* Return true if the function body might clobber register REGNO.
9793 We know that REGNO is call-saved. */
9796 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
9798 /* Some functions should be treated as clobbering all call-saved
9800 if (crtl
->saves_all_registers
)
9803 /* DF handles cases where a register is explicitly referenced in
9804 the rtl. Incoming values are passed in call-clobbered registers,
9805 so we can assume that any live call-saved register is set within
9807 if (df_regs_ever_live_p (regno
))
9810 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9811 These clobbers are not explicit in the rtl. */
9812 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9815 /* If we're using a call-saved global pointer, the function's
9816 prologue will need to set it up. */
9817 if (cfun
->machine
->global_pointer
== regno
)
9820 /* The function's prologue will need to set the frame pointer if
9821 frame_pointer_needed. */
9822 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9825 /* If a MIPS16 function returns a value in FPRs, its epilogue
9826 will need to call an external libgcc routine. This yet-to-be
9827 generated call_insn will clobber $31. */
9828 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9831 /* If REGNO is ordinarily call-clobbered, we must assume that any
9832 called function could modify it. */
9833 if (cfun
->machine
->interrupt_handler_p
9835 && mips_interrupt_extra_call_saved_reg_p (regno
))
9841 /* Return true if the current function must save register REGNO. */
9844 mips_save_reg_p (unsigned int regno
)
9846 if (mips_cfun_call_saved_reg_p (regno
))
9848 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9851 /* Save both registers in an FPR pair if either one is used. This is
9852 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9853 register to be used without the even register. */
9854 if (FP_REG_P (regno
)
9855 && MAX_FPRS_PER_FMT
== 2
9856 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9860 /* We need to save the incoming return address if __builtin_eh_return
9861 is being used to set a different return address. */
9862 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9868 /* Populate the current function's mips_frame_info structure.
9870 MIPS stack frames look like:
9872 +-------------------------------+
9874 | incoming stack arguments |
9876 +-------------------------------+
9878 | caller-allocated save area |
9879 A | for register arguments |
9881 +-------------------------------+ <-- incoming stack pointer
9883 | callee-allocated save area |
9884 B | for arguments that are |
9885 | split between registers and |
9888 +-------------------------------+ <-- arg_pointer_rtx
9890 C | callee-allocated save area |
9891 | for register varargs |
9893 +-------------------------------+ <-- frame_pointer_rtx
9894 | | + cop0_sp_offset
9895 | COP0 reg save area | + UNITS_PER_WORD
9897 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9898 | | + UNITS_PER_WORD
9899 | accumulator save area |
9901 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9902 | | + UNITS_PER_HWFPVALUE
9905 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9906 | | + UNITS_PER_WORD
9909 +-------------------------------+ <-- frame_pointer_rtx with
9910 | | \ -fstack-protector
9911 | local variables | | var_size
9913 +-------------------------------+
9915 | $gp save area | | cprestore_size
9917 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9919 | outgoing stack arguments | |
9921 +-------------------------------+ | args_size
9923 | caller-allocated save area | |
9924 | for register arguments | |
9926 +-------------------------------+ <-- stack_pointer_rtx
9927 frame_pointer_rtx without
9929 hard_frame_pointer_rtx for
9932 At least two of A, B and C will be empty.
9934 Dynamic stack allocations such as alloca insert data at point P.
9935 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9936 hard_frame_pointer_rtx unchanged. */
9939 mips_compute_frame_info (void)
9941 struct mips_frame_info
*frame
;
9942 HOST_WIDE_INT offset
, size
;
9943 unsigned int regno
, i
;
9945 /* Set this function's interrupt properties. */
9946 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
9949 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9950 else if (TARGET_HARD_FLOAT
)
9951 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9952 else if (TARGET_MIPS16
)
9953 error ("interrupt handlers cannot be MIPS16 functions");
9956 cfun
->machine
->interrupt_handler_p
= true;
9957 cfun
->machine
->use_shadow_register_set_p
=
9958 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
9959 cfun
->machine
->keep_interrupts_masked_p
=
9960 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
9961 cfun
->machine
->use_debug_exception_return_p
=
9962 mips_use_debug_exception_return_p (TREE_TYPE
9963 (current_function_decl
));
9967 frame
= &cfun
->machine
->frame
;
9968 memset (frame
, 0, sizeof (*frame
));
9969 size
= get_frame_size ();
9971 cfun
->machine
->global_pointer
= mips_global_pointer ();
9973 /* The first two blocks contain the outgoing argument area and the $gp save
9974 slot. This area isn't needed in leaf functions, but if the
9975 target-independent frame size is nonzero, we have already committed to
9976 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9977 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
9979 /* The MIPS 3.0 linker does not like functions that dynamically
9980 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9981 looks like we are trying to create a second frame pointer to the
9982 function, so allocate some stack space to make it happy. */
9983 if (cfun
->calls_alloca
)
9984 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
9986 frame
->args_size
= 0;
9987 frame
->cprestore_size
= 0;
9991 frame
->args_size
= crtl
->outgoing_args_size
;
9992 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
9994 offset
= frame
->args_size
+ frame
->cprestore_size
;
9996 /* Move above the local variables. */
9997 frame
->var_size
= MIPS_STACK_ALIGN (size
);
9998 offset
+= frame
->var_size
;
10000 /* Find out which GPRs we need to save. */
10001 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
10002 if (mips_save_reg_p (regno
))
10005 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
10008 /* If this function calls eh_return, we must also save and restore the
10009 EH data registers. */
10010 if (crtl
->calls_eh_return
)
10011 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
10014 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
10017 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10018 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10019 save all later registers too. */
10020 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10022 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
10023 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
10024 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
10025 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
10028 /* Move above the GPR save area. */
10029 if (frame
->num_gp
> 0)
10031 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
10032 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
10035 /* Find out which FPRs we need to save. This loop must iterate over
10036 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10037 if (TARGET_HARD_FLOAT
)
10038 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
10039 if (mips_save_reg_p (regno
))
10041 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
10042 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
10045 /* Move above the FPR save area. */
10046 if (frame
->num_fp
> 0)
10048 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
10049 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
10052 /* Add in space for the interrupt context information. */
10053 if (cfun
->machine
->interrupt_handler_p
)
10056 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
10059 frame
->acc_mask
|= (1 << 0);
10062 /* Check accumulators 1, 2, 3. */
10063 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
10064 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
10067 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
10070 /* All interrupt context functions need space to preserve STATUS. */
10071 frame
->num_cop0_regs
++;
10073 /* If we don't keep interrupts masked, we need to save EPC. */
10074 if (!cfun
->machine
->keep_interrupts_masked_p
)
10075 frame
->num_cop0_regs
++;
10078 /* Move above the accumulator save area. */
10079 if (frame
->num_acc
> 0)
10081 /* Each accumulator needs 2 words. */
10082 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
10083 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
10086 /* Move above the COP0 register save area. */
10087 if (frame
->num_cop0_regs
> 0)
10089 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
10090 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
10093 /* Move above the callee-allocated varargs save area. */
10094 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
10095 frame
->arg_pointer_offset
= offset
;
10097 /* Move above the callee-allocated area for pretend stack arguments. */
10098 offset
+= crtl
->args
.pretend_args_size
;
10099 frame
->total_size
= offset
;
10101 /* Work out the offsets of the save areas from the top of the frame. */
10102 if (frame
->gp_sp_offset
> 0)
10103 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
10104 if (frame
->fp_sp_offset
> 0)
10105 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
10106 if (frame
->acc_sp_offset
> 0)
10107 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
10108 if (frame
->num_cop0_regs
> 0)
10109 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
10111 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10112 arguments. This tends to increase the chances of using unextended
10113 instructions for local variables and incoming arguments. */
10115 frame
->hard_frame_pointer_offset
= frame
->args_size
;
10118 /* Return the style of GP load sequence that is being used for the
10119 current function. */
10121 enum mips_loadgp_style
10122 mips_current_loadgp_style (void)
10124 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
10125 return LOADGP_NONE
;
10127 if (TARGET_RTP_PIC
)
10130 if (TARGET_ABSOLUTE_ABICALLS
)
10131 return LOADGP_ABSOLUTE
;
10133 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
10136 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10139 mips_frame_pointer_required (void)
10141 /* If the function contains dynamic stack allocations, we need to
10142 use the frame pointer to access the static parts of the frame. */
10143 if (cfun
->calls_alloca
)
10146 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10147 reload may be unable to compute the address of a local variable,
10148 since there is no way to add a large constant to the stack pointer
10149 without using a second temporary register. */
10152 mips_compute_frame_info ();
10153 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
10160 /* Make sure that we're not trying to eliminate to the wrong hard frame
10164 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10166 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
10169 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10170 or argument pointer. TO is either the stack pointer or hard frame
10174 mips_initial_elimination_offset (int from
, int to
)
10176 HOST_WIDE_INT offset
;
10178 mips_compute_frame_info ();
10180 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10183 case FRAME_POINTER_REGNUM
:
10184 if (FRAME_GROWS_DOWNWARD
)
10185 offset
= (cfun
->machine
->frame
.args_size
10186 + cfun
->machine
->frame
.cprestore_size
10187 + cfun
->machine
->frame
.var_size
);
10192 case ARG_POINTER_REGNUM
:
10193 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
10197 gcc_unreachable ();
10200 if (to
== HARD_FRAME_POINTER_REGNUM
)
10201 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10206 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10209 mips_extra_live_on_entry (bitmap regs
)
10211 if (TARGET_USE_GOT
)
10213 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10214 the global pointer. */
10215 if (!TARGET_ABSOLUTE_ABICALLS
)
10216 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10218 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10219 the global pointer. */
10221 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
10223 /* See the comment above load_call<mode> for details. */
10224 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
10228 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10232 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
10237 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
10240 /* Emit code to change the current function's return address to
10241 ADDRESS. SCRATCH is available as a scratch register, if needed.
10242 ADDRESS and SCRATCH are both word-mode GPRs. */
10245 mips_set_return_address (rtx address
, rtx scratch
)
10249 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
10250 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
10251 cfun
->machine
->frame
.gp_sp_offset
);
10252 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
10255 /* Return true if the current function has a cprestore slot. */
10258 mips_cfun_has_cprestore_slot_p (void)
10260 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
10261 && cfun
->machine
->frame
.cprestore_size
> 0);
10264 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10265 cprestore slot. LOAD_P is true if the caller wants to load from
10266 the cprestore slot; it is false if the caller wants to store to
10270 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
10273 const struct mips_frame_info
*frame
;
10275 frame
= &cfun
->machine
->frame
;
10276 /* .cprestore always uses the stack pointer instead of the frame pointer.
10277 We have a free choice for direct stores for non-MIPS16 functions,
10278 and for MIPS16 functions whose cprestore slot is in range of the
10279 stack pointer. Using the stack pointer would sometimes give more
10280 (early) scheduling freedom, but using the frame pointer would
10281 sometimes give more (late) scheduling freedom. It's hard to
10282 predict which applies to a given function, so let's keep things
10285 Loads must always use the frame pointer in functions that call
10286 alloca, and there's little benefit to using the stack pointer
10288 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
10290 *base
= hard_frame_pointer_rtx
;
10291 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
10295 *base
= stack_pointer_rtx
;
10296 *offset
= frame
->args_size
;
10300 /* Return true if X is the load or store address of the cprestore slot;
10301 LOAD_P says which. */
10304 mips_cprestore_address_p (rtx x
, bool load_p
)
10306 rtx given_base
, required_base
;
10307 HOST_WIDE_INT given_offset
, required_offset
;
10309 mips_split_plus (x
, &given_base
, &given_offset
);
10310 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
10311 return given_base
== required_base
&& given_offset
== required_offset
;
10314 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10315 going to load from it, false if we are going to store to it.
10316 Use TEMP as a temporary register if need be. */
10319 mips_cprestore_slot (rtx temp
, bool load_p
)
10322 HOST_WIDE_INT offset
;
10324 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
10325 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
10328 /* Emit instructions to save global pointer value GP into cprestore
10329 slot MEM. OFFSET is the offset that MEM applies to the base register.
10331 MEM may not be a legitimate address. If it isn't, TEMP is a
10332 temporary register that can be used, otherwise it is a SCRATCH. */
10335 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
10337 if (TARGET_CPRESTORE_DIRECTIVE
)
10339 gcc_assert (gp
== pic_offset_table_rtx
);
10340 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
10343 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
10346 /* Restore $gp from its save slot, using TEMP as a temporary base register
10347 if need be. This function is for o32 and o64 abicalls only.
10349 See mips_must_initialize_gp_p for details about how we manage the
10353 mips_restore_gp_from_cprestore_slot (rtx temp
)
10355 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
10357 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
10359 emit_note (NOTE_INSN_DELETED
);
10365 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10366 mips_emit_move (pic_offset_table_rtx
, temp
);
10369 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10370 if (!TARGET_EXPLICIT_RELOCS
)
10371 emit_insn (gen_blockage ());
10374 /* A function to save or store a register. The first argument is the
10375 register and the second is the stack slot. */
10376 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10378 /* Use FN to save or restore register REGNO. MODE is the register's
10379 mode and OFFSET is the offset of its save slot from the current
10383 mips_save_restore_reg (enum machine_mode mode
, int regno
,
10384 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10388 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10390 fn (gen_rtx_REG (mode
, regno
), mem
);
10393 /* Call FN for each accumlator that is saved by the current function.
10394 SP_OFFSET is the offset of the current stack pointer from the start
10398 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10400 HOST_WIDE_INT offset
;
10403 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10404 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10406 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10407 offset
-= UNITS_PER_WORD
;
10408 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10409 offset
-= UNITS_PER_WORD
;
10412 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10413 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10414 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10416 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10417 offset
-= UNITS_PER_WORD
;
10421 /* Save register REG to MEM. Make the instruction frame-related. */
10424 mips_save_reg (rtx reg
, rtx mem
)
10426 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
10430 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
10432 x1
= mips_frame_set (mips_subword (mem
, false),
10433 mips_subword (reg
, false));
10434 x2
= mips_frame_set (mips_subword (mem
, true),
10435 mips_subword (reg
, true));
10436 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10439 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10442 /* Capture the register combinations that are allowed in a SWM or LWM
10443 instruction. The entries are ordered by number of registers set in
10444 the mask. We also ignore the single register encodings because a
10445 normal SW/LW is preferred. */
10447 static const unsigned int umips_swm_mask
[17] = {
10448 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10449 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10450 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10451 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10455 static const unsigned int umips_swm_encoding
[17] = {
10456 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10459 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10460 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10461 stack pointer of the topmost save slot.
10463 Remove from *MASK all registers that were handled using LWM and SWM.
10464 Update *OFFSET so that it points to the first unused save slot. */
10467 umips_build_save_restore (mips_save_restore_fn fn
,
10468 unsigned *mask
, HOST_WIDE_INT
*offset
)
10472 rtx pattern
, set
, reg
, mem
;
10473 HOST_WIDE_INT this_offset
;
10476 /* Try matching $16 to $31 (s0 to ra). */
10477 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
10478 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
10481 if (i
== ARRAY_SIZE (umips_swm_mask
))
10484 /* Get the offset of the lowest save slot. */
10485 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
10486 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
10488 /* LWM/SWM can only support offsets from -2048 to 2047. */
10489 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
10492 /* Create the final PARALLEL. */
10493 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
10494 this_base
= stack_pointer_rtx
;
10496 /* For registers $16-$23 and $30. */
10497 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
10499 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10500 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10501 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
10502 *mask
&= ~(1 << regno
);
10503 reg
= gen_rtx_REG (SImode
, regno
);
10504 if (fn
== mips_save_reg
)
10505 set
= mips_frame_set (mem
, reg
);
10508 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10509 mips_add_cfa_restore (reg
);
10511 XVECEXP (pattern
, 0, j
) = set
;
10514 /* For register $31. */
10515 if (umips_swm_encoding
[i
] >> 4)
10517 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10518 *mask
&= ~(1 << 31);
10519 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10520 reg
= gen_rtx_REG (SImode
, 31);
10521 if (fn
== mips_save_reg
)
10522 set
= mips_frame_set (mem
, reg
);
10525 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10526 mips_add_cfa_restore (reg
);
10528 XVECEXP (pattern
, 0, j
) = set
;
10531 pattern
= emit_insn (pattern
);
10532 if (fn
== mips_save_reg
)
10533 RTX_FRAME_RELATED_P (pattern
) = 1;
10535 /* Adjust the last offset. */
10536 *offset
-= UNITS_PER_WORD
* nregs
;
10541 /* Call FN for each register that is saved by the current function.
10542 SP_OFFSET is the offset of the current stack pointer from the start
10546 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10547 mips_save_restore_fn fn
)
10549 enum machine_mode fpr_mode
;
10551 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
10552 HOST_WIDE_INT offset
;
10555 /* Save registers starting from high to low. The debuggers prefer at least
10556 the return register be stored at func+4, and also it allows us not to
10557 need a nop in the epilogue if at least one register is reloaded in
10558 addition to return address. */
10559 offset
= frame
->gp_sp_offset
- sp_offset
;
10560 mask
= frame
->mask
;
10562 if (TARGET_MICROMIPS
)
10563 umips_build_save_restore (fn
, &mask
, &offset
);
10565 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10566 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10568 /* Record the ra offset for use by mips_function_profiler. */
10569 if (regno
== RETURN_ADDR_REGNUM
)
10570 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10571 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10572 offset
-= UNITS_PER_WORD
;
10575 /* This loop must iterate over the same space as its companion in
10576 mips_compute_frame_info. */
10577 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10578 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10579 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10580 regno
>= FP_REG_FIRST
;
10581 regno
-= MAX_FPRS_PER_FMT
)
10582 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10584 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10585 offset
-= GET_MODE_SIZE (fpr_mode
);
10589 /* Return true if a move between register REGNO and its save slot (MEM)
10590 can be done in a single move. LOAD_P is true if we are loading
10591 from the slot, false if we are storing to it. */
10594 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10596 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10597 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10600 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10601 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10604 /* Emit a move from SRC to DEST, given that one of them is a register
10605 save slot and that the other is a register. TEMP is a temporary
10606 GPR of the same mode that is available if need be. */
10609 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10611 unsigned int regno
;
10616 regno
= REGNO (src
);
10621 regno
= REGNO (dest
);
10625 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
10627 /* We don't yet know whether we'll need this instruction or not.
10628 Postpone the decision by emitting a ghost move. This move
10629 is specifically not frame-related; only the split version is. */
10631 emit_insn (gen_move_gpdi (dest
, src
));
10633 emit_insn (gen_move_gpsi (dest
, src
));
10637 if (regno
== HI_REGNUM
)
10641 mips_emit_move (temp
, src
);
10643 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
10644 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
10646 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
10647 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
10652 emit_insn (gen_mfhidi_ti (temp
,
10653 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
10655 emit_insn (gen_mfhisi_di (temp
,
10656 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
10657 mips_emit_move (dest
, temp
);
10660 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
10661 mips_emit_move (dest
, src
);
10664 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
10665 mips_emit_move (temp
, src
);
10666 mips_emit_move (dest
, temp
);
10669 mips_set_frame_expr (mips_frame_set (dest
, src
));
10672 /* If we're generating n32 or n64 abicalls, and the current function
10673 does not use $28 as its global pointer, emit a cplocal directive.
10674 Use pic_offset_table_rtx as the argument to the directive. */
10677 mips_output_cplocal (void)
10679 if (!TARGET_EXPLICIT_RELOCS
10680 && mips_must_initialize_gp_p ()
10681 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
10682 output_asm_insn (".cplocal %+", 0);
10685 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10688 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10690 const char *fnname
;
10692 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10693 floating-point arguments. */
10695 && TARGET_HARD_FLOAT_ABI
10696 && crtl
->args
.info
.fp_code
!= 0)
10697 mips16_build_function_stub ();
10699 /* Get the function name the same way that toplev.c does before calling
10700 assemble_start_function. This is needed so that the name used here
10701 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10702 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10703 mips_start_function_definition (fnname
, TARGET_MIPS16
);
10705 /* Output MIPS-specific frame information. */
10706 if (!flag_inhibit_size_directive
)
10708 const struct mips_frame_info
*frame
;
10710 frame
= &cfun
->machine
->frame
;
10712 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10714 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
10715 "# vars= " HOST_WIDE_INT_PRINT_DEC
10717 ", args= " HOST_WIDE_INT_PRINT_DEC
10718 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
10719 reg_names
[frame_pointer_needed
10720 ? HARD_FRAME_POINTER_REGNUM
10721 : STACK_POINTER_REGNUM
],
10722 (frame_pointer_needed
10723 ? frame
->total_size
- frame
->hard_frame_pointer_offset
10724 : frame
->total_size
),
10725 reg_names
[RETURN_ADDR_REGNUM
],
10727 frame
->num_gp
, frame
->num_fp
,
10729 frame
->cprestore_size
);
10731 /* .mask MASK, OFFSET. */
10732 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10733 frame
->mask
, frame
->gp_save_offset
);
10735 /* .fmask MASK, OFFSET. */
10736 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10737 frame
->fmask
, frame
->fp_save_offset
);
10740 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10741 Also emit the ".set noreorder; .set nomacro" sequence for functions
10743 if (mips_must_initialize_gp_p ()
10744 && mips_current_loadgp_style () == LOADGP_OLDABI
)
10748 /* This is a fixed-form sequence. The position of the
10749 first two instructions is important because of the
10750 way _gp_disp is defined. */
10751 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10752 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10753 output_asm_insn ("sll\t$2,16", 0);
10754 output_asm_insn ("addu\t$2,$3", 0);
10758 /* .cpload must be in a .set noreorder but not a
10759 .set nomacro block. */
10760 mips_push_asm_switch (&mips_noreorder
);
10761 output_asm_insn (".cpload\t%^", 0);
10762 if (!cfun
->machine
->all_noreorder_p
)
10763 mips_pop_asm_switch (&mips_noreorder
);
10765 mips_push_asm_switch (&mips_nomacro
);
10768 else if (cfun
->machine
->all_noreorder_p
)
10770 mips_push_asm_switch (&mips_noreorder
);
10771 mips_push_asm_switch (&mips_nomacro
);
10774 /* Tell the assembler which register we're using as the global
10775 pointer. This is needed for thunks, since they can use either
10776 explicit relocs or assembler macros. */
10777 mips_output_cplocal ();
10780 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10783 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10784 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10786 const char *fnname
;
10788 /* Reinstate the normal $gp. */
10789 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
10790 mips_output_cplocal ();
10792 if (cfun
->machine
->all_noreorder_p
)
10794 mips_pop_asm_switch (&mips_nomacro
);
10795 mips_pop_asm_switch (&mips_noreorder
);
10798 /* Get the function name the same way that toplev.c does before calling
10799 assemble_start_function. This is needed so that the name used here
10800 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10801 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10802 mips_end_function_definition (fnname
);
10805 /* Emit an optimisation barrier for accesses to the current frame. */
10808 mips_frame_barrier (void)
10810 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
10814 /* The __gnu_local_gp symbol. */
10816 static GTY(()) rtx mips_gnu_local_gp
;
10818 /* If we're generating n32 or n64 abicalls, emit instructions
10819 to set up the global pointer. */
10822 mips_emit_loadgp (void)
10824 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
10826 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10827 switch (mips_current_loadgp_style ())
10829 case LOADGP_ABSOLUTE
:
10830 if (mips_gnu_local_gp
== NULL
)
10832 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
10833 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
10835 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
10836 (pic_reg
, mips_gnu_local_gp
)));
10839 case LOADGP_OLDABI
:
10840 /* Added by mips_output_function_prologue. */
10843 case LOADGP_NEWABI
:
10844 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
10845 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
10846 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
10847 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
10848 (pic_reg
, offset
, incoming_address
)));
10852 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
10853 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
10854 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
10862 emit_insn (PMODE_INSN (gen_copygp_mips16
,
10863 (pic_offset_table_rtx
, pic_reg
)));
10865 /* Emit a blockage if there are implicit uses of the GP register.
10866 This includes profiled functions, because FUNCTION_PROFILE uses
10868 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
10869 emit_insn (gen_loadgp_blockage ());
10872 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10874 #if PROBE_INTERVAL > 32768
10875 #error Cannot use indexed addressing mode for stack probing
10878 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10879 inclusive. These are offsets from the current stack pointer. */
10882 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
10885 sorry ("-fstack-check=specific not implemented for MIPS16");
10887 /* See if we have a constant small number of probes to generate. If so,
10888 that's the easy case. */
10889 if (first
+ size
<= 32768)
10893 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10894 it exceeds SIZE. If only one probe is needed, this will not
10895 generate any code. Then probe at FIRST + SIZE. */
10896 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
10897 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10900 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10904 /* Otherwise, do the same as above, but in a loop. Note that we must be
10905 extra careful with variables wrapping around because we might be at
10906 the very top (or the very bottom) of the address space and we have
10907 to be able to handle this case properly; in particular, we use an
10908 equality test for the loop condition. */
10911 HOST_WIDE_INT rounded_size
;
10912 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
10913 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
10915 /* Sanity check for the addressing mode we're going to use. */
10916 gcc_assert (first
<= 32768);
10919 /* Step 1: round SIZE to the previous multiple of the interval. */
10921 rounded_size
= size
& -PROBE_INTERVAL
;
10924 /* Step 2: compute initial and final value of the loop counter. */
10926 /* TEST_ADDR = SP + FIRST. */
10927 emit_insn (gen_rtx_SET (VOIDmode
, r3
,
10928 plus_constant (Pmode
, stack_pointer_rtx
,
10931 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10932 if (rounded_size
> 32768)
10934 emit_move_insn (r12
, GEN_INT (rounded_size
));
10935 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10936 gen_rtx_MINUS (Pmode
, r3
, r12
)));
10939 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10940 plus_constant (Pmode
, r3
, -rounded_size
)));
10943 /* Step 3: the loop
10945 while (TEST_ADDR != LAST_ADDR)
10947 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10951 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10952 until it is equal to ROUNDED_SIZE. */
10954 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
10957 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10958 that SIZE is equal to ROUNDED_SIZE. */
10960 if (size
!= rounded_size
)
10961 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
10964 /* Make sure nothing is scheduled before we are done. */
10965 emit_insn (gen_blockage ());
10968 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
10969 absolute addresses. */
10972 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
10974 static int labelno
= 0;
10975 char loop_lab
[32], end_lab
[32], tmp
[64];
10978 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
10979 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
10981 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
10983 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10986 strcpy (tmp
, "%(%<beq\t%0,%1,");
10987 output_asm_insn (strcat (tmp
, &end_lab
[1]), xops
);
10989 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10990 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
10991 if (TARGET_64BIT
&& TARGET_LONG64
)
10992 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
10994 output_asm_insn ("addiu\t%0,%0,%1", xops
);
10996 /* Probe at TEST_ADDR and branch. */
10997 fprintf (asm_out_file
, "\tb\t");
10998 assemble_name_raw (asm_out_file
, loop_lab
);
10999 fputc ('\n', asm_out_file
);
11001 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
11003 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
11005 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
11010 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
11013 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
11015 return REG_P (*x
) && KERNEL_REG_P (REGNO (*x
));
11018 /* Expand the "prologue" pattern. */
11021 mips_expand_prologue (void)
11023 const struct mips_frame_info
*frame
;
11024 HOST_WIDE_INT size
;
11025 unsigned int nargs
;
11028 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
11030 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11031 or implicitly. If so, we can commit to using a global pointer
11032 straight away, otherwise we need to defer the decision. */
11033 if (mips_cfun_has_inflexible_gp_ref_p ()
11034 || mips_cfun_has_flexible_gp_ref_p ())
11036 cfun
->machine
->must_initialize_gp_p
= true;
11037 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
11040 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
11043 frame
= &cfun
->machine
->frame
;
11044 size
= frame
->total_size
;
11046 if (flag_stack_usage_info
)
11047 current_function_static_stack_size
= size
;
11049 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
11051 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
11053 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
11054 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
,
11055 size
- STACK_CHECK_PROTECT
);
11058 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
11061 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11062 bytes beforehand; this is enough to cover the register save area
11063 without going out of range. */
11064 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
11065 || frame
->num_cop0_regs
> 0)
11067 HOST_WIDE_INT step1
;
11069 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
11070 if (GENERATE_MIPS16E_SAVE_RESTORE
)
11072 HOST_WIDE_INT offset
;
11073 unsigned int mask
, regno
;
11075 /* Try to merge argument stores into the save instruction. */
11076 nargs
= mips16e_collect_argument_saves ();
11078 /* Build the save instruction. */
11079 mask
= frame
->mask
;
11080 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
11082 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11083 mips_frame_barrier ();
11086 /* Check if we need to save other registers. */
11087 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11088 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11090 offset
-= UNITS_PER_WORD
;
11091 mips_save_restore_reg (word_mode
, regno
,
11092 offset
, mips_save_reg
);
11097 if (cfun
->machine
->interrupt_handler_p
)
11099 HOST_WIDE_INT offset
;
11102 /* If this interrupt is using a shadow register set, we need to
11103 get the stack pointer from the previous register set. */
11104 if (cfun
->machine
->use_shadow_register_set_p
)
11105 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
11106 stack_pointer_rtx
));
11108 if (!cfun
->machine
->keep_interrupts_masked_p
)
11110 /* Move from COP0 Cause to K0. */
11111 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
11112 gen_rtx_REG (SImode
,
11113 COP0_CAUSE_REG_NUM
)));
11114 /* Move from COP0 EPC to K1. */
11115 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11116 gen_rtx_REG (SImode
,
11117 COP0_EPC_REG_NUM
)));
11120 /* Allocate the first part of the frame. */
11121 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
11123 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11124 mips_frame_barrier ();
11127 /* Start at the uppermost location for saving. */
11128 offset
= frame
->cop0_sp_offset
- size
;
11129 if (!cfun
->machine
->keep_interrupts_masked_p
)
11131 /* Push EPC into its stack slot. */
11132 mem
= gen_frame_mem (word_mode
,
11133 plus_constant (Pmode
, stack_pointer_rtx
,
11135 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11136 offset
-= UNITS_PER_WORD
;
11139 /* Move from COP0 Status to K1. */
11140 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11141 gen_rtx_REG (SImode
,
11142 COP0_STATUS_REG_NUM
)));
11144 /* Right justify the RIPL in k0. */
11145 if (!cfun
->machine
->keep_interrupts_masked_p
)
11146 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
11147 gen_rtx_REG (SImode
, K0_REG_NUM
),
11148 GEN_INT (CAUSE_IPL
)));
11150 /* Push Status into its stack slot. */
11151 mem
= gen_frame_mem (word_mode
,
11152 plus_constant (Pmode
, stack_pointer_rtx
,
11154 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11155 offset
-= UNITS_PER_WORD
;
11157 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11158 if (!cfun
->machine
->keep_interrupts_masked_p
)
11159 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11162 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11164 if (!cfun
->machine
->keep_interrupts_masked_p
)
11165 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11166 IE is already the correct value, so we don't have to do
11167 anything explicit. */
11168 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11171 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11173 /* Disable interrupts by clearing the KSU, ERL, EXL,
11175 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11178 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11182 insn
= gen_add3_insn (stack_pointer_rtx
,
11185 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11186 mips_frame_barrier ();
11189 mips_for_each_saved_acc (size
, mips_save_reg
);
11190 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
11194 /* Allocate the rest of the frame. */
11197 if (SMALL_OPERAND (-size
))
11198 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
11200 GEN_INT (-size
)))) = 1;
11203 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
11206 /* There are no instructions to add or subtract registers
11207 from the stack pointer, so use the frame pointer as a
11208 temporary. We should always be using a frame pointer
11209 in this case anyway. */
11210 gcc_assert (frame_pointer_needed
);
11211 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11212 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
11213 hard_frame_pointer_rtx
,
11214 MIPS_PROLOGUE_TEMP (Pmode
)));
11215 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
11218 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
11220 MIPS_PROLOGUE_TEMP (Pmode
)));
11222 /* Describe the combined effect of the previous instructions. */
11223 mips_set_frame_expr
11224 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
11225 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
11227 mips_frame_barrier ();
11230 /* Set up the frame pointer, if we're using one. */
11231 if (frame_pointer_needed
)
11233 HOST_WIDE_INT offset
;
11235 offset
= frame
->hard_frame_pointer_offset
;
11238 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11239 RTX_FRAME_RELATED_P (insn
) = 1;
11241 else if (SMALL_OPERAND (offset
))
11243 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
11244 stack_pointer_rtx
, GEN_INT (offset
));
11245 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11249 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
11250 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11251 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
11252 hard_frame_pointer_rtx
,
11253 MIPS_PROLOGUE_TEMP (Pmode
)));
11254 mips_set_frame_expr
11255 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
11256 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
11260 mips_emit_loadgp ();
11262 /* Initialize the $gp save slot. */
11263 if (mips_cfun_has_cprestore_slot_p ())
11265 rtx base
, mem
, gp
, temp
;
11266 HOST_WIDE_INT offset
;
11268 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
11269 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11270 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11271 temp
= (SMALL_OPERAND (offset
)
11272 ? gen_rtx_SCRATCH (Pmode
)
11273 : MIPS_PROLOGUE_TEMP (Pmode
));
11274 emit_insn (PMODE_INSN (gen_potential_cprestore
,
11275 (mem
, GEN_INT (offset
), gp
, temp
)));
11277 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11278 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11279 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
11282 /* We need to search back to the last use of K0 or K1. */
11283 if (cfun
->machine
->interrupt_handler_p
)
11285 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
11287 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
11289 /* Emit a move from K1 to COP0 Status after insn. */
11290 gcc_assert (insn
!= NULL_RTX
);
11291 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11292 gen_rtx_REG (SImode
, K1_REG_NUM
)),
11296 /* If we are profiling, make sure no instructions are scheduled before
11297 the call to mcount. */
11299 emit_insn (gen_blockage ());
11302 /* Attach all pending register saves to the previous instruction.
11303 Return that instruction. */
11306 mips_epilogue_emit_cfa_restores (void)
11310 insn
= get_last_insn ();
11311 gcc_assert (insn
&& !REG_NOTES (insn
));
11312 if (mips_epilogue
.cfa_restores
)
11314 RTX_FRAME_RELATED_P (insn
) = 1;
11315 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
11316 mips_epilogue
.cfa_restores
= 0;
11321 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11322 now at REG + OFFSET. */
11325 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
11329 insn
= mips_epilogue_emit_cfa_restores ();
11330 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
11332 RTX_FRAME_RELATED_P (insn
) = 1;
11333 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
11334 plus_constant (Pmode
, reg
, offset
),
11336 mips_epilogue
.cfa_reg
= reg
;
11337 mips_epilogue
.cfa_offset
= offset
;
11341 /* Emit instructions to restore register REG from slot MEM. Also update
11342 the cfa_restores list. */
11345 mips_restore_reg (rtx reg
, rtx mem
)
11347 /* There's no MIPS16 instruction to load $31 directly. Load into
11348 $7 instead and adjust the return insn appropriately. */
11349 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
11350 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
11351 else if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
11353 mips_add_cfa_restore (mips_subword (reg
, true));
11354 mips_add_cfa_restore (mips_subword (reg
, false));
11357 mips_add_cfa_restore (reg
);
11359 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
11360 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
11361 /* The CFA is currently defined in terms of the register whose
11362 value we have just restored. Redefine the CFA in terms of
11363 the stack pointer. */
11364 mips_epilogue_set_cfa (stack_pointer_rtx
,
11365 mips_epilogue
.cfa_restore_sp_offset
);
11368 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11369 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11370 BASE, if not the stack pointer, is available as a temporary. */
11373 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
11375 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
11378 mips_frame_barrier ();
11379 if (offset
== const0_rtx
)
11381 emit_move_insn (stack_pointer_rtx
, base
);
11382 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11384 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
11386 emit_insn (gen_add3_insn (base
, base
, offset
));
11387 mips_epilogue_set_cfa (base
, new_frame_size
);
11388 emit_move_insn (stack_pointer_rtx
, base
);
11392 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
11393 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11397 /* Emit any instructions needed before a return. */
11400 mips_expand_before_return (void)
11402 /* When using a call-clobbered gp, we start out with unified call
11403 insns that include instructions to restore the gp. We then split
11404 these unified calls after reload. These split calls explicitly
11405 clobber gp, so there is no need to define
11406 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11408 For consistency, we should also insert an explicit clobber of $28
11409 before return insns, so that the post-reload optimizers know that
11410 the register is not live on exit. */
11411 if (TARGET_CALL_CLOBBERED_GP
)
11412 emit_clobber (pic_offset_table_rtx
);
11415 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11419 mips_expand_epilogue (bool sibcall_p
)
11421 const struct mips_frame_info
*frame
;
11422 HOST_WIDE_INT step1
, step2
;
11423 rtx base
, adjust
, insn
;
11424 bool use_jraddiusp_p
= false;
11426 if (!sibcall_p
&& mips_can_use_return_insn ())
11428 emit_jump_insn (gen_return ());
11432 /* In MIPS16 mode, if the return value should go into a floating-point
11433 register, we need to call a helper routine to copy it over. */
11434 if (mips16_cfun_returns_in_fpr_p ())
11435 mips16_copy_fpr_return_value ();
11437 /* Split the frame into two. STEP1 is the amount of stack we should
11438 deallocate before restoring the registers. STEP2 is the amount we
11439 should deallocate afterwards.
11441 Start off by assuming that no registers need to be restored. */
11442 frame
= &cfun
->machine
->frame
;
11443 step1
= frame
->total_size
;
11446 /* Work out which register holds the frame address. */
11447 if (!frame_pointer_needed
)
11448 base
= stack_pointer_rtx
;
11451 base
= hard_frame_pointer_rtx
;
11452 step1
-= frame
->hard_frame_pointer_offset
;
11454 mips_epilogue
.cfa_reg
= base
;
11455 mips_epilogue
.cfa_offset
= step1
;
11456 mips_epilogue
.cfa_restores
= NULL_RTX
;
11458 /* If we need to restore registers, deallocate as much stack as
11459 possible in the second step without going out of range. */
11460 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
11461 || frame
->num_cop0_regs
> 0)
11463 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
11467 /* Get an rtx for STEP1 that we can add to BASE. */
11468 adjust
= GEN_INT (step1
);
11469 if (!SMALL_OPERAND (step1
))
11471 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
11472 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
11474 mips_deallocate_stack (base
, adjust
, step2
);
11476 /* If we're using addressing macros, $gp is implicitly used by all
11477 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11479 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
11480 emit_insn (gen_blockage ());
11482 mips_epilogue
.cfa_restore_sp_offset
= step2
;
11483 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
11485 unsigned int regno
, mask
;
11486 HOST_WIDE_INT offset
;
11489 /* Generate the restore instruction. */
11490 mask
= frame
->mask
;
11491 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
11493 /* Restore any other registers manually. */
11494 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11495 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11497 offset
-= UNITS_PER_WORD
;
11498 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
11501 /* Restore the remaining registers and deallocate the final bit
11503 mips_frame_barrier ();
11504 emit_insn (restore
);
11505 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
11509 /* Restore the registers. */
11510 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
11511 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
11514 if (cfun
->machine
->interrupt_handler_p
)
11516 HOST_WIDE_INT offset
;
11519 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
11520 if (!cfun
->machine
->keep_interrupts_masked_p
)
11522 /* Restore the original EPC. */
11523 mem
= gen_frame_mem (word_mode
,
11524 plus_constant (Pmode
, stack_pointer_rtx
,
11526 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11527 offset
-= UNITS_PER_WORD
;
11529 /* Move to COP0 EPC. */
11530 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
11531 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11534 /* Restore the original Status. */
11535 mem
= gen_frame_mem (word_mode
,
11536 plus_constant (Pmode
, stack_pointer_rtx
,
11538 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11539 offset
-= UNITS_PER_WORD
;
11541 /* If we don't use shadow register set, we need to update SP. */
11542 if (!cfun
->machine
->use_shadow_register_set_p
)
11543 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11545 /* The choice of position is somewhat arbitrary in this case. */
11546 mips_epilogue_emit_cfa_restores ();
11548 /* Move to COP0 Status. */
11549 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11550 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11552 else if (TARGET_MICROMIPS
11553 && !crtl
->calls_eh_return
11556 && mips_unsigned_immediate_p (step2
, 5, 2))
11557 use_jraddiusp_p
= true;
11559 /* Deallocate the final bit of the frame. */
11560 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11563 if (!use_jraddiusp_p
)
11564 gcc_assert (!mips_epilogue
.cfa_restores
);
11566 /* Add in the __builtin_eh_return stack adjustment. We need to
11567 use a temporary in MIPS16 code. */
11568 if (crtl
->calls_eh_return
)
11572 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
11573 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
11574 MIPS_EPILOGUE_TEMP (Pmode
),
11575 EH_RETURN_STACKADJ_RTX
));
11576 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
11579 emit_insn (gen_add3_insn (stack_pointer_rtx
,
11581 EH_RETURN_STACKADJ_RTX
));
11586 mips_expand_before_return ();
11587 if (cfun
->machine
->interrupt_handler_p
)
11589 /* Interrupt handlers generate eret or deret. */
11590 if (cfun
->machine
->use_debug_exception_return_p
)
11591 emit_jump_insn (gen_mips_deret ());
11593 emit_jump_insn (gen_mips_eret ());
11599 /* When generating MIPS16 code, the normal
11600 mips_for_each_saved_gpr_and_fpr path will restore the return
11601 address into $7 rather than $31. */
11603 && !GENERATE_MIPS16E_SAVE_RESTORE
11604 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
11606 /* simple_returns cannot rely on values that are only available
11607 on paths through the epilogue (because return paths that do
11608 not pass through the epilogue may nevertheless reuse a
11609 simple_return that occurs at the end of the epilogue).
11610 Use a normal return here instead. */
11611 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
11612 pat
= gen_return_internal (reg
);
11614 else if (use_jraddiusp_p
)
11615 pat
= gen_jraddiusp (GEN_INT (step2
));
11618 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
11619 pat
= gen_simple_return_internal (reg
);
11621 emit_jump_insn (pat
);
11622 if (use_jraddiusp_p
)
11623 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
11627 /* Search from the beginning to the first use of K0 or K1. */
11628 if (cfun
->machine
->interrupt_handler_p
11629 && !cfun
->machine
->keep_interrupts_masked_p
)
11631 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11633 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
11635 gcc_assert (insn
!= NULL_RTX
);
11636 /* Insert disable interrupts before the first use of K0 or K1. */
11637 emit_insn_before (gen_mips_di (), insn
);
11638 emit_insn_before (gen_mips_ehb (), insn
);
11642 /* Return nonzero if this function is known to have a null epilogue.
11643 This allows the optimizer to omit jumps to jumps if no stack
11647 mips_can_use_return_insn (void)
11649 /* Interrupt handlers need to go through the epilogue. */
11650 if (cfun
->machine
->interrupt_handler_p
)
11653 if (!reload_completed
)
11659 /* In MIPS16 mode, a function that returns a floating-point value
11660 needs to arrange to copy the return value into the floating-point
11662 if (mips16_cfun_returns_in_fpr_p ())
11665 return cfun
->machine
->frame
.total_size
== 0;
11668 /* Return true if register REGNO can store a value of mode MODE.
11669 The result of this function is cached in mips_hard_regno_mode_ok. */
11672 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
11675 enum mode_class mclass
;
11677 if (mode
== CCV2mode
)
11678 return (ISA_HAS_8CC
11679 && ST_REG_P (regno
)
11680 && (regno
- ST_REG_FIRST
) % 2 == 0);
11682 if (mode
== CCV4mode
)
11683 return (ISA_HAS_8CC
11684 && ST_REG_P (regno
)
11685 && (regno
- ST_REG_FIRST
) % 4 == 0);
11687 if (mode
== CCmode
)
11688 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
11690 size
= GET_MODE_SIZE (mode
);
11691 mclass
= GET_MODE_CLASS (mode
);
11693 if (GP_REG_P (regno
))
11694 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
11696 if (FP_REG_P (regno
)
11697 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
11698 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
11700 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11701 if (TARGET_LOONGSON_VECTORS
11702 && (mode
== V2SImode
11703 || mode
== V4HImode
11704 || mode
== V8QImode
11705 || mode
== DImode
))
11708 if (mclass
== MODE_FLOAT
11709 || mclass
== MODE_COMPLEX_FLOAT
11710 || mclass
== MODE_VECTOR_FLOAT
)
11711 return size
<= UNITS_PER_FPVALUE
;
11713 /* Allow integer modes that fit into a single register. We need
11714 to put integers into FPRs when using instructions like CVT
11715 and TRUNC. There's no point allowing sizes smaller than a word,
11716 because the FPU has no appropriate load/store instructions. */
11717 if (mclass
== MODE_INT
)
11718 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
11721 if (ACC_REG_P (regno
)
11722 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
11724 if (MD_REG_P (regno
))
11726 /* After a multiplication or division, clobbering HI makes
11727 the value of LO unpredictable, and vice versa. This means
11728 that, for all interesting cases, HI and LO are effectively
11731 We model this by requiring that any value that uses HI
11733 if (size
<= UNITS_PER_WORD
* 2)
11734 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
11738 /* DSP accumulators do not have the same restrictions as
11739 HI and LO, so we can treat them as normal doubleword
11741 if (size
<= UNITS_PER_WORD
)
11744 if (size
<= UNITS_PER_WORD
* 2
11745 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
11750 if (ALL_COP_REG_P (regno
))
11751 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
11753 if (regno
== GOT_VERSION_REGNUM
)
11754 return mode
== SImode
;
11759 /* Implement HARD_REGNO_NREGS. */
11762 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
11764 if (ST_REG_P (regno
))
11765 /* The size of FP status registers is always 4, because they only hold
11766 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11767 return (GET_MODE_SIZE (mode
) + 3) / 4;
11769 if (FP_REG_P (regno
))
11770 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
11772 /* All other registers are word-sized. */
11773 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
11776 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11777 in mips_hard_regno_nregs. */
11780 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
11786 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
11787 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
11789 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
11790 size
= MIN (size
, 4);
11791 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
11793 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
11795 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
11796 size
= MIN (size
, UNITS_PER_FPREG
);
11797 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
11799 if (!hard_reg_set_empty_p (left
))
11800 size
= MIN (size
, UNITS_PER_WORD
);
11801 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
11804 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11807 mips_cannot_change_mode_class (enum machine_mode from
,
11808 enum machine_mode to
,
11809 enum reg_class rclass
)
11811 /* Allow conversions between different Loongson integer vectors,
11812 and between those vectors and DImode. */
11813 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
11814 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
11817 /* Otherwise, there are several problems with changing the modes of
11818 values in floating-point registers:
11820 - When a multi-word value is stored in paired floating-point
11821 registers, the first register always holds the low word. We
11822 therefore can't allow FPRs to change between single-word and
11823 multi-word modes on big-endian targets.
11825 - GCC assumes that each word of a multiword register can be
11826 accessed individually using SUBREGs. This is not true for
11827 floating-point registers if they are bigger than a word.
11829 - Loading a 32-bit value into a 64-bit floating-point register
11830 will not sign-extend the value, despite what LOAD_EXTEND_OP
11831 says. We can't allow FPRs to change from SImode to a wider
11832 mode on 64-bit targets.
11834 - If the FPU has already interpreted a value in one format, we
11835 must not ask it to treat the value as having a different
11838 We therefore disallow all mode changes involving FPRs. */
11840 return reg_classes_intersect_p (FP_REGS
, rclass
);
11843 /* Implement target hook small_register_classes_for_mode_p. */
11846 mips_small_register_classes_for_mode_p (enum machine_mode mode
11849 return TARGET_MIPS16
;
11852 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11855 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
11860 return TARGET_HARD_FLOAT
;
11863 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
11866 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
11873 /* Implement MODES_TIEABLE_P. */
11876 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
11878 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11879 prefer to put one of them in FPRs. */
11880 return (mode1
== mode2
11881 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
11882 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
11885 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11888 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
11890 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
11893 if (reg_class_subset_p (FP_REGS
, rclass
)
11894 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
11897 if (reg_class_subset_p (GR_REGS
, rclass
))
11900 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
11906 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11907 Return a "canonical" class to represent it in later calculations. */
11910 mips_canonicalize_move_class (reg_class_t rclass
)
11912 /* All moves involving accumulator registers have the same cost. */
11913 if (reg_class_subset_p (rclass
, ACC_REGS
))
11916 /* Likewise promote subclasses of general registers to the most
11917 interesting containing class. */
11918 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
11920 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
11921 rclass
= GENERAL_REGS
;
11926 /* Return the cost of moving a value of mode MODE from a register of
11927 class FROM to a GPR. Return 0 for classes that are unions of other
11928 classes handled by this function. */
11931 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
11938 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11942 /* MFLO and MFHI. */
11950 /* LUI followed by MOVF. */
11956 /* This choice of value is historical. */
11964 /* Return the cost of moving a value of mode MODE from a GPR to a
11965 register of class TO. Return 0 for classes that are unions of
11966 other classes handled by this function. */
11969 mips_move_from_gpr_cost (enum machine_mode mode
, reg_class_t to
)
11975 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11979 /* MTLO and MTHI. */
11987 /* A secondary reload through an FPR scratch. */
11988 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
11989 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
11994 /* This choice of value is historical. */
12002 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
12003 maximum of the move costs for subclasses; regclass will work out
12004 the maximum for us. */
12007 mips_register_move_cost (enum machine_mode mode
,
12008 reg_class_t from
, reg_class_t to
)
12013 from
= mips_canonicalize_move_class (from
);
12014 to
= mips_canonicalize_move_class (to
);
12016 /* Handle moves that can be done without using general-purpose registers. */
12017 if (from
== FP_REGS
)
12019 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
12023 /* The sequence generated by mips_expand_fcc_reload. */
12027 /* Handle cases in which only one class deviates from the ideal. */
12028 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
12030 return mips_move_from_gpr_cost (mode
, to
);
12032 return mips_move_to_gpr_cost (mode
, from
);
12034 /* Handles cases that require a GPR temporary. */
12035 cost1
= mips_move_to_gpr_cost (mode
, from
);
12038 cost2
= mips_move_from_gpr_cost (mode
, to
);
12040 return cost1
+ cost2
;
12046 /* Implement TARGET_MEMORY_MOVE_COST. */
12049 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
12051 return (mips_cost
->memory_latency
12052 + memory_move_secondary_cost (mode
, rclass
, in
));
12055 /* Return the register class required for a secondary register when
12056 copying between one of the registers in RCLASS and value X, which
12057 has mode MODE. X is the source of the move if IN_P, otherwise it
12058 is the destination. Return NO_REGS if no secondary register is
12062 mips_secondary_reload_class (enum reg_class rclass
,
12063 enum machine_mode mode
, rtx x
, bool in_p
)
12067 /* If X is a constant that cannot be loaded into $25, it must be loaded
12068 into some other GPR. No other register class allows a direct move. */
12069 if (mips_dangerous_for_la25_p (x
))
12070 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
12072 regno
= true_regnum (x
);
12075 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12076 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
12082 /* Copying from accumulator registers to anywhere other than a general
12083 register requires a temporary general register. */
12084 if (reg_class_subset_p (rclass
, ACC_REGS
))
12085 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12086 if (ACC_REG_P (regno
))
12087 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12089 /* We can only copy a value to a condition code register from a
12090 floating-point register, and even then we require a scratch
12091 floating-point register. We can only copy a value out of a
12092 condition-code register into a general register. */
12093 if (reg_class_subset_p (rclass
, ST_REGS
))
12097 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12099 if (ST_REG_P (regno
))
12103 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12106 if (reg_class_subset_p (rclass
, FP_REGS
))
12109 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
12110 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12111 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12114 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
12115 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12118 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
12119 /* We can force the constant to memory and use lwc1
12120 and ldc1. As above, we will use pairs of lwc1s if
12121 ldc1 is not supported. */
12124 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
12125 /* In this case we can use mov.fmt. */
12128 /* Otherwise, we need to reload through an integer register. */
12131 if (FP_REG_P (regno
))
12132 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12137 /* Implement TARGET_MODE_REP_EXTENDED. */
12140 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
12142 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12143 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
12144 return SIGN_EXTEND
;
12149 /* Implement TARGET_VALID_POINTER_MODE. */
12152 mips_valid_pointer_mode (enum machine_mode mode
)
12154 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
12157 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12160 mips_vector_mode_supported_p (enum machine_mode mode
)
12165 return TARGET_PAIRED_SINGLE_FLOAT
;
12180 return TARGET_LOONGSON_VECTORS
;
12187 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12190 mips_scalar_mode_supported_p (enum machine_mode mode
)
12192 if (ALL_FIXED_POINT_MODE_P (mode
)
12193 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
12196 return default_scalar_mode_supported_p (mode
);
12199 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12201 static enum machine_mode
12202 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED
)
12204 if (TARGET_PAIRED_SINGLE_FLOAT
12210 /* Implement TARGET_INIT_LIBFUNCS. */
12213 mips_init_libfuncs (void)
12215 if (TARGET_FIX_VR4120
)
12217 /* Register the special divsi3 and modsi3 functions needed to work
12218 around VR4120 division errata. */
12219 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
12220 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
12223 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
12225 /* Register the MIPS16 -mhard-float stubs. */
12226 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
12227 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
12228 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
12229 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
12231 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
12232 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
12233 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
12234 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
12235 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
12236 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
12237 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
12239 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
12240 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
12241 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
12243 if (TARGET_DOUBLE_FLOAT
)
12245 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
12246 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
12247 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
12248 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
12250 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
12251 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
12252 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
12253 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
12254 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
12255 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
12256 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
12258 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
12259 "__mips16_extendsfdf2");
12260 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
12261 "__mips16_truncdfsf2");
12262 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
12263 "__mips16_fix_truncdfsi");
12264 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
12265 "__mips16_floatsidf");
12266 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
12267 "__mips16_floatunsidf");
12271 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12272 on an external non-MIPS16 routine to implement __sync_synchronize.
12273 Similarly for the rest of the ll/sc libfuncs. */
12276 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
12277 init_sync_libfuncs (UNITS_PER_WORD
);
12281 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12284 mips_process_load_label (rtx target
)
12286 rtx base
, gp
, intop
;
12287 HOST_WIDE_INT offset
;
12289 mips_multi_start ();
12293 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
12294 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12298 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
12299 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12303 gp
= pic_offset_table_rtx
;
12304 if (mips_cfun_has_cprestore_slot_p ())
12306 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
12307 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12308 if (!SMALL_OPERAND (offset
))
12310 intop
= GEN_INT (CONST_HIGH_PART (offset
));
12311 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
12312 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
12315 offset
= CONST_LOW_PART (offset
);
12317 intop
= GEN_INT (offset
);
12318 if (ISA_HAS_LOAD_DELAY
)
12319 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
12321 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
12323 if (ISA_HAS_LOAD_DELAY
)
12324 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
12326 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
12327 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
12332 /* Return the number of instructions needed to load a label into $AT. */
12334 static unsigned int
12335 mips_load_label_num_insns (void)
12337 if (cfun
->machine
->load_label_num_insns
== 0)
12339 mips_process_load_label (pc_rtx
);
12340 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
12342 return cfun
->machine
->load_label_num_insns
;
12345 /* Emit an asm sequence to start a noat block and load the address
12346 of a label into $1. */
12349 mips_output_load_label (rtx target
)
12351 mips_push_asm_switch (&mips_noat
);
12352 if (TARGET_EXPLICIT_RELOCS
)
12354 mips_process_load_label (target
);
12355 mips_multi_write ();
12359 if (Pmode
== DImode
)
12360 output_asm_insn ("dla\t%@,%0", &target
);
12362 output_asm_insn ("la\t%@,%0", &target
);
12366 /* Return the length of INSN. LENGTH is the initial length computed by
12367 attributes in the machine-description file. */
12370 mips_adjust_insn_length (rtx insn
, int length
)
12372 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12373 of a PIC long-branch sequence. Substitute the correct value. */
12374 if (length
== MAX_PIC_BRANCH_LENGTH
12376 && INSN_CODE (insn
) >= 0
12377 && get_attr_type (insn
) == TYPE_BRANCH
)
12379 /* Add the branch-over instruction and its delay slot, if this
12380 is a conditional branch. */
12381 length
= simplejump_p (insn
) ? 0 : 8;
12383 /* Add the size of a load into $AT. */
12384 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
12386 /* Add the length of an indirect jump, ignoring the delay slot. */
12387 length
+= TARGET_COMPRESSION
? 2 : 4;
12390 /* A unconditional jump has an unfilled delay slot if it is not part
12391 of a sequence. A conditional jump normally has a delay slot, but
12392 does not on MIPS16. */
12393 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
12394 length
+= TARGET_MIPS16
? 2 : 4;
12396 /* See how many nops might be needed to avoid hardware hazards. */
12397 if (!cfun
->machine
->ignore_hazard_length_p
12399 && INSN_CODE (insn
) >= 0)
12400 switch (get_attr_hazard (insn
))
12406 length
+= NOP_INSN_LENGTH
;
12410 length
+= NOP_INSN_LENGTH
* 2;
12417 /* Return the assembly code for INSN, which has the operands given by
12418 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12419 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12420 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12421 version of BRANCH_IF_TRUE. */
12424 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
12425 const char *branch_if_true
,
12426 const char *branch_if_false
)
12428 unsigned int length
;
12429 rtx taken
, not_taken
;
12431 gcc_assert (LABEL_P (operands
[0]));
12433 length
= get_attr_length (insn
);
12436 /* Just a simple conditional branch. */
12437 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
12438 return branch_if_true
;
12441 /* Generate a reversed branch around a direct jump. This fallback does
12442 not use branch-likely instructions. */
12443 mips_branch_likely
= false;
12444 not_taken
= gen_label_rtx ();
12445 taken
= operands
[0];
12447 /* Generate the reversed branch to NOT_TAKEN. */
12448 operands
[0] = not_taken
;
12449 output_asm_insn (branch_if_false
, operands
);
12451 /* If INSN has a delay slot, we must provide delay slots for both the
12452 branch to NOT_TAKEN and the conditional jump. We must also ensure
12453 that INSN's delay slot is executed in the appropriate cases. */
12454 if (final_sequence
)
12456 /* This first delay slot will always be executed, so use INSN's
12457 delay slot if is not annulled. */
12458 if (!INSN_ANNULLED_BRANCH_P (insn
))
12460 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12461 asm_out_file
, optimize
, 1, NULL
);
12462 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12465 output_asm_insn ("nop", 0);
12466 fprintf (asm_out_file
, "\n");
12469 /* Output the unconditional branch to TAKEN. */
12470 if (TARGET_ABSOLUTE_JUMPS
)
12471 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
12474 mips_output_load_label (taken
);
12475 output_asm_insn ("jr\t%@%]%/", 0);
12478 /* Now deal with its delay slot; see above. */
12479 if (final_sequence
)
12481 /* This delay slot will only be executed if the branch is taken.
12482 Use INSN's delay slot if is annulled. */
12483 if (INSN_ANNULLED_BRANCH_P (insn
))
12485 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12486 asm_out_file
, optimize
, 1, NULL
);
12487 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12490 output_asm_insn ("nop", 0);
12491 fprintf (asm_out_file
, "\n");
12494 /* Output NOT_TAKEN. */
12495 targetm
.asm_out
.internal_label (asm_out_file
, "L",
12496 CODE_LABEL_NUMBER (not_taken
));
12500 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12501 if some ordering condition is true. The condition is given by
12502 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12503 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12504 its second is always zero. */
12507 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
12509 const char *branch
[2];
12511 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12512 Make BRANCH[0] branch on the inverse condition. */
12513 switch (GET_CODE (operands
[1]))
12515 /* These cases are equivalent to comparisons against zero. */
12517 inverted_p
= !inverted_p
;
12518 /* Fall through. */
12520 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
12521 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
12524 /* These cases are always true or always false. */
12526 inverted_p
= !inverted_p
;
12527 /* Fall through. */
12529 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
12530 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
12534 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
12535 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
12538 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
12541 /* Start a block of code that needs access to the LL, SC and SYNC
12545 mips_start_ll_sc_sync_block (void)
12547 if (!ISA_HAS_LL_SC
)
12549 output_asm_insn (".set\tpush", 0);
12551 output_asm_insn (".set\tmips3", 0);
12553 output_asm_insn (".set\tmips2", 0);
12557 /* End a block started by mips_start_ll_sc_sync_block. */
12560 mips_end_ll_sc_sync_block (void)
12562 if (!ISA_HAS_LL_SC
)
12563 output_asm_insn (".set\tpop", 0);
12566 /* Output and/or return the asm template for a sync instruction. */
12569 mips_output_sync (void)
12571 mips_start_ll_sc_sync_block ();
12572 output_asm_insn ("sync", 0);
12573 mips_end_ll_sc_sync_block ();
12577 /* Return the asm template associated with sync_insn1 value TYPE.
12578 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12580 static const char *
12581 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
12585 case SYNC_INSN1_MOVE
:
12586 return "move\t%0,%z2";
12587 case SYNC_INSN1_LI
:
12588 return "li\t%0,%2";
12589 case SYNC_INSN1_ADDU
:
12590 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12591 case SYNC_INSN1_ADDIU
:
12592 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12593 case SYNC_INSN1_SUBU
:
12594 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12595 case SYNC_INSN1_AND
:
12596 return "and\t%0,%1,%z2";
12597 case SYNC_INSN1_ANDI
:
12598 return "andi\t%0,%1,%2";
12599 case SYNC_INSN1_OR
:
12600 return "or\t%0,%1,%z2";
12601 case SYNC_INSN1_ORI
:
12602 return "ori\t%0,%1,%2";
12603 case SYNC_INSN1_XOR
:
12604 return "xor\t%0,%1,%z2";
12605 case SYNC_INSN1_XORI
:
12606 return "xori\t%0,%1,%2";
12608 gcc_unreachable ();
12611 /* Return the asm template associated with sync_insn2 value TYPE. */
12613 static const char *
12614 mips_sync_insn2_template (enum attr_sync_insn2 type
)
12618 case SYNC_INSN2_NOP
:
12619 gcc_unreachable ();
12620 case SYNC_INSN2_AND
:
12621 return "and\t%0,%1,%z2";
12622 case SYNC_INSN2_XOR
:
12623 return "xor\t%0,%1,%z2";
12624 case SYNC_INSN2_NOT
:
12625 return "nor\t%0,%1,%.";
12627 gcc_unreachable ();
12630 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12631 the value of the one of the sync_* attributes. Return the operand
12632 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12633 have the associated attribute. */
12636 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
12639 default_value
= operands
[index
- 1];
12640 return default_value
;
12643 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12644 sequence for it. */
12647 mips_process_sync_loop (rtx insn
, rtx
*operands
)
12649 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
12650 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
12651 unsigned int tmp3_insn
;
12652 enum attr_sync_insn1 insn1
;
12653 enum attr_sync_insn2 insn2
;
12656 enum memmodel model
;
12658 /* Read an operand from the sync_WHAT attribute and store it in
12659 variable WHAT. DEFAULT is the default value if no attribute
12661 #define READ_OPERAND(WHAT, DEFAULT) \
12662 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12665 /* Read the memory. */
12666 READ_OPERAND (mem
, 0);
12668 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
12670 /* Read the other attributes. */
12671 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
12672 READ_OPERAND (oldval
, at
);
12673 READ_OPERAND (cmp
, 0);
12674 READ_OPERAND (newval
, at
);
12675 READ_OPERAND (inclusive_mask
, 0);
12676 READ_OPERAND (exclusive_mask
, 0);
12677 READ_OPERAND (required_oldval
, 0);
12678 READ_OPERAND (insn1_op2
, 0);
12679 insn1
= get_attr_sync_insn1 (insn
);
12680 insn2
= get_attr_sync_insn2 (insn
);
12682 /* Don't bother setting CMP result that is never used. */
12683 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
12686 memmodel_attr
= get_attr_sync_memmodel (insn
);
12687 switch (memmodel_attr
)
12690 model
= MEMMODEL_ACQ_REL
;
12693 model
= MEMMODEL_ACQUIRE
;
12696 model
= (enum memmodel
) INTVAL (operands
[memmodel_attr
]);
12699 mips_multi_start ();
12701 /* Output the release side of the memory barrier. */
12702 if (need_atomic_barrier_p (model
, true))
12704 if (required_oldval
== 0 && TARGET_OCTEON
)
12706 /* Octeon doesn't reorder reads, so a full barrier can be
12707 created by using SYNCW to order writes combined with the
12708 write from the following SC. When the SC successfully
12709 completes, we know that all preceding writes are also
12710 committed to the coherent memory system. It is possible
12711 for a single SYNCW to fail, but a pair of them will never
12712 fail, so we use two. */
12713 mips_multi_add_insn ("syncw", NULL
);
12714 mips_multi_add_insn ("syncw", NULL
);
12717 mips_multi_add_insn ("sync", NULL
);
12720 /* Output the branch-back label. */
12721 mips_multi_add_label ("1:");
12723 /* OLDVAL = *MEM. */
12724 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
12725 oldval
, mem
, NULL
);
12727 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12728 if (required_oldval
)
12730 if (inclusive_mask
== 0)
12734 gcc_assert (oldval
!= at
);
12735 mips_multi_add_insn ("and\t%0,%1,%2",
12736 at
, oldval
, inclusive_mask
, NULL
);
12739 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
12741 /* CMP = 0 [delay slot]. */
12743 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
12746 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12747 if (exclusive_mask
== 0)
12751 gcc_assert (oldval
!= at
);
12752 mips_multi_add_insn ("and\t%0,%1,%z2",
12753 at
, oldval
, exclusive_mask
, NULL
);
12757 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12759 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12760 at least one instruction in that case. */
12761 if (insn1
== SYNC_INSN1_MOVE
12762 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
12766 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
12767 newval
, oldval
, insn1_op2
, NULL
);
12771 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12772 if (insn2
== SYNC_INSN2_NOP
)
12776 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
12777 newval
, tmp2
, inclusive_mask
, NULL
);
12780 tmp3_insn
= mips_multi_last_index ();
12782 /* $AT = $TMP1 | $TMP3. */
12783 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
12785 mips_multi_set_operand (tmp3_insn
, 0, at
);
12790 gcc_assert (tmp1
!= tmp3
);
12791 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
12794 /* if (!commit (*MEM = $AT)) goto 1.
12796 This will sometimes be a delayed branch; see the write code below
12798 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
12799 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
12801 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12802 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
12804 mips_multi_copy_insn (tmp3_insn
);
12805 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
12807 else if (!(required_oldval
&& cmp
))
12808 mips_multi_add_insn ("nop", NULL
);
12810 /* CMP = 1 -- either standalone or in a delay slot. */
12811 if (required_oldval
&& cmp
)
12812 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
12814 /* Output the acquire side of the memory barrier. */
12815 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
12816 mips_multi_add_insn ("sync", NULL
);
12818 /* Output the exit label, if needed. */
12819 if (required_oldval
)
12820 mips_multi_add_label ("2:");
12822 #undef READ_OPERAND
12825 /* Output and/or return the asm template for sync loop INSN, which has
12826 the operands given by OPERANDS. */
12829 mips_output_sync_loop (rtx insn
, rtx
*operands
)
12831 mips_process_sync_loop (insn
, operands
);
12833 /* Use branch-likely instructions to work around the LL/SC R10000
12835 mips_branch_likely
= TARGET_FIX_R10000
;
12837 mips_push_asm_switch (&mips_noreorder
);
12838 mips_push_asm_switch (&mips_nomacro
);
12839 mips_push_asm_switch (&mips_noat
);
12840 mips_start_ll_sc_sync_block ();
12842 mips_multi_write ();
12844 mips_end_ll_sc_sync_block ();
12845 mips_pop_asm_switch (&mips_noat
);
12846 mips_pop_asm_switch (&mips_nomacro
);
12847 mips_pop_asm_switch (&mips_noreorder
);
12852 /* Return the number of individual instructions in sync loop INSN,
12853 which has the operands given by OPERANDS. */
12856 mips_sync_loop_insns (rtx insn
, rtx
*operands
)
12858 mips_process_sync_loop (insn
, operands
);
12859 return mips_multi_num_insns
;
12862 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12863 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12865 When working around R4000 and R4400 errata, we need to make sure that
12866 the division is not immediately followed by a shift[1][2]. We also
12867 need to stop the division from being put into a branch delay slot[3].
12868 The easiest way to avoid both problems is to add a nop after the
12869 division. When a divide-by-zero check is needed, this nop can be
12870 used to fill the branch delay slot.
12872 [1] If a double-word or a variable shift executes immediately
12873 after starting an integer division, the shift may give an
12874 incorrect result. See quotations of errata #16 and #28 from
12875 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12876 in mips.md for details.
12878 [2] A similar bug to [1] exists for all revisions of the
12879 R4000 and the R4400 when run in an MC configuration.
12880 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12882 "19. In this following sequence:
12884 ddiv (or ddivu or div or divu)
12885 dsll32 (or dsrl32, dsra32)
12887 if an MPT stall occurs, while the divide is slipping the cpu
12888 pipeline, then the following double shift would end up with an
12891 Workaround: The compiler needs to avoid generating any
12892 sequence with divide followed by extended double shift."
12894 This erratum is also present in "MIPS R4400MC Errata, Processor
12895 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12896 & 3.0" as errata #10 and #4, respectively.
12898 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12899 (also valid for MIPS R4000MC processors):
12901 "52. R4000SC: This bug does not apply for the R4000PC.
12903 There are two flavors of this bug:
12905 1) If the instruction just after divide takes an RF exception
12906 (tlb-refill, tlb-invalid) and gets an instruction cache
12907 miss (both primary and secondary) and the line which is
12908 currently in secondary cache at this index had the first
12909 data word, where the bits 5..2 are set, then R4000 would
12910 get a wrong result for the div.
12915 ------------------- # end-of page. -tlb-refill
12920 ------------------- # end-of page. -tlb-invalid
12923 2) If the divide is in the taken branch delay slot, where the
12924 target takes RF exception and gets an I-cache miss for the
12925 exception vector or where I-cache miss occurs for the
12926 target address, under the above mentioned scenarios, the
12927 div would get wrong results.
12930 j r2 # to next page mapped or unmapped
12931 div r8,r9 # this bug would be there as long
12932 # as there is an ICache miss and
12933 nop # the "data pattern" is present
12936 beq r0, r0, NextPage # to Next page
12940 This bug is present for div, divu, ddiv, and ddivu
12943 Workaround: For item 1), OS could make sure that the next page
12944 after the divide instruction is also mapped. For item 2), the
12945 compiler could make sure that the divide instruction is not in
12946 the branch delay slot."
12948 These processors have PRId values of 0x00004220 and 0x00004300 for
12949 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12952 mips_output_division (const char *division
, rtx
*operands
)
12957 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
12959 output_asm_insn (s
, operands
);
12962 if (TARGET_CHECK_ZERO_DIV
)
12966 output_asm_insn (s
, operands
);
12967 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
12969 else if (GENERATE_DIVIDE_TRAPS
)
12971 /* Avoid long replay penalty on load miss by putting the trap before
12974 output_asm_insn ("teq\t%2,%.,7", operands
);
12977 output_asm_insn (s
, operands
);
12978 s
= "teq\t%2,%.,7";
12983 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
12984 output_asm_insn (s
, operands
);
12985 s
= "break\t7%)\n1:";
12991 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12992 instruction and if OUT_INSN assigns to the accumulator operand. */
12995 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
12997 enum attr_accum_in accum_in
;
12998 int accum_in_opnum
;
13001 if (recog_memoized (in_insn
) < 0)
13004 accum_in
= get_attr_accum_in (in_insn
);
13005 if (accum_in
== ACCUM_IN_NONE
)
13008 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
13010 extract_insn (in_insn
);
13011 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
13012 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
13014 return reg_set_p (accum_in_op
, out_insn
);
13017 /* True if the dependency between OUT_INSN and IN_INSN is on the store
13018 data rather than the address. We need this because the cprestore
13019 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
13020 which causes the default routine to abort. We just return false
13024 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
13026 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
13029 return !store_data_bypass_p (out_insn
, in_insn
);
13033 /* Variables and flags used in scheduler hooks when tuning for
13037 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13040 /* If true, then next ALU1/2 instruction will go to ALU1. */
13043 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13046 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13047 int alu1_core_unit_code
;
13048 int alu2_core_unit_code
;
13049 int falu1_core_unit_code
;
13050 int falu2_core_unit_code
;
13052 /* True if current cycle has a multi instruction.
13053 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13054 bool cycle_has_multi_p
;
13056 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13057 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13059 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13060 instruction to go ALU1. */
13061 rtx alu1_turn_enabled_insn
;
13062 rtx alu2_turn_enabled_insn
;
13063 rtx falu1_turn_enabled_insn
;
13064 rtx falu2_turn_enabled_insn
;
13067 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13068 dependencies have no cost, except on the 20Kc where output-dependence
13069 is treated like input-dependence. */
13072 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
13073 rtx dep ATTRIBUTE_UNUSED
, int cost
)
13075 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
13078 if (REG_NOTE_KIND (link
) != 0)
13083 /* Return the number of instructions that can be issued per cycle. */
13086 mips_issue_rate (void)
13090 case PROCESSOR_74KC
:
13091 case PROCESSOR_74KF2_1
:
13092 case PROCESSOR_74KF1_1
:
13093 case PROCESSOR_74KF3_2
:
13094 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13095 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13096 but in reality only a maximum of 3 insns can be issued as
13097 floating-point loads and stores also require a slot in the
13099 case PROCESSOR_R10000
:
13100 /* All R10K Processors are quad-issue (being the first MIPS
13101 processors to support this feature). */
13104 case PROCESSOR_20KC
:
13105 case PROCESSOR_R4130
:
13106 case PROCESSOR_R5400
:
13107 case PROCESSOR_R5500
:
13108 case PROCESSOR_R5900
:
13109 case PROCESSOR_R7000
:
13110 case PROCESSOR_R9000
:
13111 case PROCESSOR_OCTEON
:
13112 case PROCESSOR_OCTEON2
:
13115 case PROCESSOR_SB1
:
13116 case PROCESSOR_SB1A
:
13117 /* This is actually 4, but we get better performance if we claim 3.
13118 This is partly because of unwanted speculative code motion with the
13119 larger number, and partly because in most common cases we can't
13120 reach the theoretical max of 4. */
13123 case PROCESSOR_LOONGSON_2E
:
13124 case PROCESSOR_LOONGSON_2F
:
13125 case PROCESSOR_LOONGSON_3A
:
13128 case PROCESSOR_XLP
:
13129 return (reload_completed
? 4 : 3);
13136 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13139 mips_ls2_init_dfa_post_cycle_insn (void)
13142 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13143 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
13147 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13148 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
13152 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13153 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
13157 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13158 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
13161 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
13162 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
13163 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
13164 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
13167 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13168 Init data used in mips_dfa_post_advance_cycle. */
13171 mips_init_dfa_post_cycle_insn (void)
13173 if (TUNE_LOONGSON_2EF
)
13174 mips_ls2_init_dfa_post_cycle_insn ();
13177 /* Initialize STATE when scheduling for Loongson 2E/2F.
13178 Support round-robin dispatch scheme by enabling only one of
13179 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13183 mips_ls2_dfa_post_advance_cycle (state_t state
)
13185 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
13187 /* Though there are no non-pipelined ALU1 insns,
13188 we can get an instruction of type 'multi' before reload. */
13189 gcc_assert (mips_ls2
.cycle_has_multi_p
);
13190 mips_ls2
.alu1_turn_p
= false;
13193 mips_ls2
.cycle_has_multi_p
= false;
13195 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
13196 /* We have a non-pipelined alu instruction in the core,
13197 adjust round-robin counter. */
13198 mips_ls2
.alu1_turn_p
= true;
13200 if (mips_ls2
.alu1_turn_p
)
13202 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
13203 gcc_unreachable ();
13207 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
13208 gcc_unreachable ();
13211 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
13213 /* There are no non-pipelined FALU1 insns. */
13214 gcc_unreachable ();
13215 mips_ls2
.falu1_turn_p
= false;
13218 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
13219 /* We have a non-pipelined falu instruction in the core,
13220 adjust round-robin counter. */
13221 mips_ls2
.falu1_turn_p
= true;
13223 if (mips_ls2
.falu1_turn_p
)
13225 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
13226 gcc_unreachable ();
13230 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
13231 gcc_unreachable ();
13235 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13236 This hook is being called at the start of each cycle. */
13239 mips_dfa_post_advance_cycle (void)
13241 if (TUNE_LOONGSON_2EF
)
13242 mips_ls2_dfa_post_advance_cycle (curr_state
);
13245 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13246 be as wide as the scheduling freedom in the DFA. */
13249 mips_multipass_dfa_lookahead (void)
13251 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13255 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
13264 /* Remove the instruction at index LOWER from ready queue READY and
13265 reinsert it in front of the instruction at index HIGHER. LOWER must
13269 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
13274 new_head
= ready
[lower
];
13275 for (i
= lower
; i
< higher
; i
++)
13276 ready
[i
] = ready
[i
+ 1];
13277 ready
[i
] = new_head
;
13280 /* If the priority of the instruction at POS2 in the ready queue READY
13281 is within LIMIT units of that of the instruction at POS1, swap the
13282 instructions if POS2 is not already less than POS1. */
13285 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
13288 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
13292 temp
= ready
[pos1
];
13293 ready
[pos1
] = ready
[pos2
];
13294 ready
[pos2
] = temp
;
13298 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13299 that may clobber hi or lo. */
13300 static rtx mips_macc_chains_last_hilo
;
13302 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13303 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13306 mips_macc_chains_record (rtx insn
)
13308 if (get_attr_may_clobber_hilo (insn
))
13309 mips_macc_chains_last_hilo
= insn
;
13312 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13313 has NREADY elements, looking for a multiply-add or multiply-subtract
13314 instruction that is cumulative with mips_macc_chains_last_hilo.
13315 If there is one, promote it ahead of anything else that might
13316 clobber hi or lo. */
13319 mips_macc_chains_reorder (rtx
*ready
, int nready
)
13323 if (mips_macc_chains_last_hilo
!= 0)
13324 for (i
= nready
- 1; i
>= 0; i
--)
13325 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
13327 for (j
= nready
- 1; j
> i
; j
--)
13328 if (recog_memoized (ready
[j
]) >= 0
13329 && get_attr_may_clobber_hilo (ready
[j
]))
13331 mips_promote_ready (ready
, i
, j
);
13338 /* The last instruction to be scheduled. */
13339 static rtx vr4130_last_insn
;
13341 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13342 points to an rtx that is initially an instruction. Nullify the rtx
13343 if the instruction uses the value of register X. */
13346 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13351 insn_ptr
= (rtx
*) data
;
13354 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
13358 /* Return true if there is true register dependence between vr4130_last_insn
13362 vr4130_true_reg_dependence_p (rtx insn
)
13364 note_stores (PATTERN (vr4130_last_insn
),
13365 vr4130_true_reg_dependence_p_1
, &insn
);
13369 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13370 the ready queue and that INSN2 is the instruction after it, return
13371 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13372 in which INSN1 and INSN2 can probably issue in parallel, but for
13373 which (INSN2, INSN1) should be less sensitive to instruction
13374 alignment than (INSN1, INSN2). See 4130.md for more details. */
13377 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
13379 sd_iterator_def sd_it
;
13382 /* Check for the following case:
13384 1) there is some other instruction X with an anti dependence on INSN1;
13385 2) X has a higher priority than INSN2; and
13386 3) X is an arithmetic instruction (and thus has no unit restrictions).
13388 If INSN1 is the last instruction blocking X, it would better to
13389 choose (INSN1, X) over (INSN2, INSN1). */
13390 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
13391 if (DEP_TYPE (dep
) == REG_DEP_ANTI
13392 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
13393 && recog_memoized (DEP_CON (dep
)) >= 0
13394 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
13397 if (vr4130_last_insn
!= 0
13398 && recog_memoized (insn1
) >= 0
13399 && recog_memoized (insn2
) >= 0)
13401 /* See whether INSN1 and INSN2 use different execution units,
13402 or if they are both ALU-type instructions. If so, they can
13403 probably execute in parallel. */
13404 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
13405 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
13406 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
13408 /* If only one of the instructions has a dependence on
13409 vr4130_last_insn, prefer to schedule the other one first. */
13410 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
13411 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
13412 if (dep1_p
!= dep2_p
)
13415 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13416 is not an ALU-type instruction and if INSN1 uses the same
13417 execution unit. (Note that if this condition holds, we already
13418 know that INSN2 uses a different execution unit.) */
13419 if (class1
!= VR4130_CLASS_ALU
13420 && recog_memoized (vr4130_last_insn
) >= 0
13421 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
13428 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13429 queue with at least two instructions. Swap the first two if
13430 vr4130_swap_insns_p says that it could be worthwhile. */
13433 vr4130_reorder (rtx
*ready
, int nready
)
13435 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
13436 mips_promote_ready (ready
, nready
- 2, nready
- 1);
13439 /* Record whether last 74k AGEN instruction was a load or store. */
13440 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13442 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13443 resets to TYPE_UNKNOWN state. */
13446 mips_74k_agen_init (rtx insn
)
13448 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
13449 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13452 enum attr_type type
= get_attr_type (insn
);
13453 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
13454 mips_last_74k_agen_insn
= type
;
13458 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13459 loads to be grouped together, and multiple stores to be grouped
13460 together. Swap things around in the ready queue to make this happen. */
13463 mips_74k_agen_reorder (rtx
*ready
, int nready
)
13466 int store_pos
, load_pos
;
13471 for (i
= nready
- 1; i
>= 0; i
--)
13473 rtx insn
= ready
[i
];
13474 if (USEFUL_INSN_P (insn
))
13475 switch (get_attr_type (insn
))
13478 if (store_pos
== -1)
13483 if (load_pos
== -1)
13492 if (load_pos
== -1 || store_pos
== -1)
13495 switch (mips_last_74k_agen_insn
)
13498 /* Prefer to schedule loads since they have a higher latency. */
13500 /* Swap loads to the front of the queue. */
13501 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
13504 /* Swap stores to the front of the queue. */
13505 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
13512 /* Implement TARGET_SCHED_INIT. */
13515 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13516 int max_ready ATTRIBUTE_UNUSED
)
13518 mips_macc_chains_last_hilo
= 0;
13519 vr4130_last_insn
= 0;
13520 mips_74k_agen_init (NULL_RTX
);
13522 /* When scheduling for Loongson2, branch instructions go to ALU1,
13523 therefore basic block is most likely to start with round-robin counter
13524 pointed to ALU2. */
13525 mips_ls2
.alu1_turn_p
= false;
13526 mips_ls2
.falu1_turn_p
= true;
13529 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13532 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13533 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13535 if (!reload_completed
13536 && TUNE_MACC_CHAINS
13538 mips_macc_chains_reorder (ready
, *nreadyp
);
13540 if (reload_completed
13542 && !TARGET_VR4130_ALIGN
13544 vr4130_reorder (ready
, *nreadyp
);
13547 mips_74k_agen_reorder (ready
, *nreadyp
);
13550 /* Implement TARGET_SCHED_REORDER. */
13553 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13554 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13556 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13557 return mips_issue_rate ();
13560 /* Implement TARGET_SCHED_REORDER2. */
13563 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13564 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13566 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13567 return cached_can_issue_more
;
13570 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13573 mips_ls2_variable_issue (rtx insn
)
13575 if (mips_ls2
.alu1_turn_p
)
13577 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
13578 mips_ls2
.alu1_turn_p
= false;
13582 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
13583 mips_ls2
.alu1_turn_p
= true;
13586 if (mips_ls2
.falu1_turn_p
)
13588 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
13589 mips_ls2
.falu1_turn_p
= false;
13593 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
13594 mips_ls2
.falu1_turn_p
= true;
13597 if (recog_memoized (insn
) >= 0)
13598 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
13601 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13604 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13605 rtx insn
, int more
)
13607 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13608 if (USEFUL_INSN_P (insn
))
13610 if (get_attr_type (insn
) != TYPE_GHOST
)
13612 if (!reload_completed
&& TUNE_MACC_CHAINS
)
13613 mips_macc_chains_record (insn
);
13614 vr4130_last_insn
= insn
;
13616 mips_74k_agen_init (insn
);
13617 else if (TUNE_LOONGSON_2EF
)
13618 mips_ls2_variable_issue (insn
);
13621 /* Instructions of type 'multi' should all be split before
13622 the second scheduling pass. */
13623 gcc_assert (!reload_completed
13624 || recog_memoized (insn
) < 0
13625 || get_attr_type (insn
) != TYPE_MULTI
);
13627 cached_can_issue_more
= more
;
13631 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13632 return the first operand of the associated PREF or PREFX insn. */
13635 mips_prefetch_cookie (rtx write
, rtx locality
)
13637 /* store_streamed / load_streamed. */
13638 if (INTVAL (locality
) <= 0)
13639 return GEN_INT (INTVAL (write
) + 4);
13641 /* store / load. */
13642 if (INTVAL (locality
) <= 2)
13645 /* store_retained / load_retained. */
13646 return GEN_INT (INTVAL (write
) + 6);
13649 /* Flags that indicate when a built-in function is available.
13651 BUILTIN_AVAIL_NON_MIPS16
13652 The function is available on the current target, but only
13653 in non-MIPS16 mode. */
13654 #define BUILTIN_AVAIL_NON_MIPS16 1
13656 /* Declare an availability predicate for built-in functions that
13657 require non-MIPS16 mode and also require COND to be true.
13658 NAME is the main part of the predicate's name. */
13659 #define AVAIL_NON_MIPS16(NAME, COND) \
13660 static unsigned int \
13661 mips_builtin_avail_##NAME (void) \
13663 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13666 /* This structure describes a single built-in function. */
13667 struct mips_builtin_description
{
13668 /* The code of the main .md file instruction. See mips_builtin_type
13669 for more information. */
13670 enum insn_code icode
;
13672 /* The floating-point comparison code to use with ICODE, if any. */
13673 enum mips_fp_condition cond
;
13675 /* The name of the built-in function. */
13678 /* Specifies how the function should be expanded. */
13679 enum mips_builtin_type builtin_type
;
13681 /* The function's prototype. */
13682 enum mips_function_type function_type
;
13684 /* Whether the function is available. */
13685 unsigned int (*avail
) (void);
13688 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
13689 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
13690 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
13691 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
13692 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
13693 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
13694 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
13695 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
13696 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
13697 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
13699 /* Construct a mips_builtin_description from the given arguments.
13701 INSN is the name of the associated instruction pattern, without the
13702 leading CODE_FOR_mips_.
13704 CODE is the floating-point condition code associated with the
13705 function. It can be 'f' if the field is not applicable.
13707 NAME is the name of the function itself, without the leading
13710 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13712 AVAIL is the name of the availability predicate, without the leading
13713 mips_builtin_avail_. */
13714 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13715 FUNCTION_TYPE, AVAIL) \
13716 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13717 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13718 mips_builtin_avail_ ## AVAIL }
13720 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13721 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13722 are as for MIPS_BUILTIN. */
13723 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13724 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13726 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13727 are subject to mips_builtin_avail_<AVAIL>. */
13728 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13729 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13730 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13731 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13732 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13734 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13735 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13736 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13737 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13738 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13739 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13741 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13742 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13744 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13745 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13747 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13748 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13751 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13752 are subject to mips_builtin_avail_mips3d. */
13753 #define CMP_4S_BUILTINS(INSN, COND) \
13754 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13755 MIPS_BUILTIN_CMP_ANY, \
13756 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13757 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13758 MIPS_BUILTIN_CMP_ALL, \
13759 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13761 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13762 instruction requires mips_builtin_avail_<AVAIL>. */
13763 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13764 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13765 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13767 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13768 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13771 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13772 #define CMP_BUILTINS(COND) \
13773 MOVTF_BUILTINS (c, COND, paired_single), \
13774 MOVTF_BUILTINS (cabs, COND, mips3d), \
13775 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13776 CMP_PS_BUILTINS (c, COND, paired_single), \
13777 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13778 CMP_4S_BUILTINS (c, COND), \
13779 CMP_4S_BUILTINS (cabs, COND)
13781 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13782 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13783 and AVAIL are as for MIPS_BUILTIN. */
13784 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13785 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13786 FUNCTION_TYPE, AVAIL)
13788 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13789 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13790 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13791 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13792 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13794 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13795 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13796 builtin_description field. */
13797 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13798 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13799 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13800 FUNCTION_TYPE, mips_builtin_avail_loongson }
13802 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13803 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13804 builtin_description field. */
13805 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13806 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13808 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13809 We use functions of this form when the same insn can be usefully applied
13810 to more than one datatype. */
13811 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13812 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13814 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13815 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13816 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13817 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13818 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13819 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13820 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13821 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13823 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13824 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13825 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13826 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13827 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13828 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13829 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13830 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13831 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13832 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13833 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13834 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13835 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13836 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13837 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13838 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13839 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13840 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13841 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13842 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13843 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13844 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13845 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13846 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13847 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13848 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13849 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13850 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13851 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13852 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13854 static const struct mips_builtin_description mips_builtins
[] = {
13855 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13856 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13857 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13858 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13859 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
13860 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13861 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13862 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
13864 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
13865 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13866 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13867 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13868 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13870 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13871 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13872 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13873 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13874 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13875 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13877 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13878 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13879 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13880 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13881 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13882 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13884 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
13886 /* Built-in functions for the SB-1 processor. */
13887 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
13889 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13890 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13891 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13892 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13893 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13894 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13895 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13896 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13897 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13898 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13899 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13900 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13901 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13902 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13903 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
13904 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
13905 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
13906 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13907 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13908 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13909 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13910 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
13911 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
13912 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13913 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13914 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13915 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13916 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13917 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13918 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13919 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13920 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13921 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13922 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13923 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13924 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13925 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13926 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13927 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13928 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13929 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13930 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13931 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13932 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13933 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
13934 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13935 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
13936 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
13937 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13938 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13939 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13940 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13941 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13942 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13943 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13944 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13945 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13946 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13947 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13948 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13949 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
13950 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
13951 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13952 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13953 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13954 BPOSGE_BUILTIN (32, dsp
),
13956 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13957 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
13958 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13959 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13960 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13961 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13962 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13963 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13964 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13965 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13966 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13967 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13968 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13969 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13970 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13971 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13972 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
13973 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13974 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13975 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13976 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13977 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13978 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
13979 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13980 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13981 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13982 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13983 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13984 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13985 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13986 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13987 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13988 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13989 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13990 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13992 /* Built-in functions for the DSP ASE (32-bit only). */
13993 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13994 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13995 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13996 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13997 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13998 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13999 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14000 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14001 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14002 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14003 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14004 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14005 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14006 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14007 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14008 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14009 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14010 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14011 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14012 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14013 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14014 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14015 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14016 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14017 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14018 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
14019 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
14021 /* Built-in functions for the DSP ASE (64-bit only). */
14022 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
14024 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14025 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14026 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14027 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14028 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14029 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14030 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14031 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14032 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14033 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14035 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14036 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
14037 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
14038 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
14039 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14040 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14041 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14042 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14043 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14044 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14045 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14046 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
14047 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14048 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14049 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14050 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14051 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
14052 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14053 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14054 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14055 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
14056 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14057 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14058 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14059 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14060 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14061 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14062 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14063 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14064 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14065 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14066 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14067 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14068 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14069 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14070 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14071 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14072 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14073 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
14074 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
14075 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14076 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14077 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14078 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14079 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14080 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14081 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14082 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14083 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
14084 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14085 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14086 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14087 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14088 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
14089 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
14090 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14091 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14092 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14093 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
14094 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14095 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
14096 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
14097 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14098 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14099 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14100 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14101 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14102 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14103 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14104 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14105 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14106 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14107 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14108 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14109 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14110 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14111 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14112 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14113 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14114 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14115 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14116 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14117 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14118 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
14119 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14120 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14121 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14122 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14123 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14124 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14125 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14126 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14127 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14128 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14129 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14130 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14131 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14132 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14133 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14134 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14136 /* Sundry other built-in functions. */
14137 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
14140 /* Index I is the function declaration for mips_builtins[I], or null if the
14141 function isn't defined on this target. */
14142 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
14144 /* MODE is a vector mode whose elements have type TYPE. Return the type
14145 of the vector itself. */
14148 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
14150 static tree types
[2 * (int) MAX_MACHINE_MODE
];
14153 mode_index
= (int) mode
;
14155 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
14156 mode_index
+= MAX_MACHINE_MODE
;
14158 if (types
[mode_index
] == NULL_TREE
)
14159 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
14160 return types
[mode_index
];
14163 /* Return a type for 'const volatile void *'. */
14166 mips_build_cvpointer_type (void)
14170 if (cache
== NULL_TREE
)
14171 cache
= build_pointer_type (build_qualified_type
14173 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
14177 /* Source-level argument types. */
14178 #define MIPS_ATYPE_VOID void_type_node
14179 #define MIPS_ATYPE_INT integer_type_node
14180 #define MIPS_ATYPE_POINTER ptr_type_node
14181 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14183 /* Standard mode-based argument types. */
14184 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14185 #define MIPS_ATYPE_SI intSI_type_node
14186 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14187 #define MIPS_ATYPE_DI intDI_type_node
14188 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14189 #define MIPS_ATYPE_SF float_type_node
14190 #define MIPS_ATYPE_DF double_type_node
14192 /* Vector argument types. */
14193 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14194 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14195 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14196 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14197 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14198 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14199 #define MIPS_ATYPE_UV2SI \
14200 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14201 #define MIPS_ATYPE_UV4HI \
14202 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14203 #define MIPS_ATYPE_UV8QI \
14204 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14206 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14207 their associated MIPS_ATYPEs. */
14208 #define MIPS_FTYPE_ATYPES1(A, B) \
14209 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14211 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14212 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14214 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14215 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14217 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14218 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14221 /* Return the function type associated with function prototype TYPE. */
14224 mips_build_function_type (enum mips_function_type type
)
14226 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
14228 if (types
[(int) type
] == NULL_TREE
)
14231 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14232 case MIPS_FTYPE_NAME##NUM ARGS: \
14233 types[(int) type] \
14234 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14237 #include "config/mips/mips-ftypes.def"
14238 #undef DEF_MIPS_FTYPE
14240 gcc_unreachable ();
14243 return types
[(int) type
];
14246 /* Implement TARGET_INIT_BUILTINS. */
14249 mips_init_builtins (void)
14251 const struct mips_builtin_description
*d
;
14254 /* Iterate through all of the bdesc arrays, initializing all of the
14255 builtin functions. */
14256 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
14258 d
= &mips_builtins
[i
];
14260 mips_builtin_decls
[i
]
14261 = add_builtin_function (d
->name
,
14262 mips_build_function_type (d
->function_type
),
14263 i
, BUILT_IN_MD
, NULL
, NULL
);
14267 /* Implement TARGET_BUILTIN_DECL. */
14270 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
14272 if (code
>= ARRAY_SIZE (mips_builtins
))
14273 return error_mark_node
;
14274 return mips_builtin_decls
[code
];
14277 /* Take argument ARGNO from EXP's argument list and convert it into
14278 an expand operand. Store the operand in *OP. */
14281 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
14282 unsigned int argno
)
14287 arg
= CALL_EXPR_ARG (exp
, argno
);
14288 value
= expand_normal (arg
);
14289 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
14292 /* Expand instruction ICODE as part of a built-in function sequence.
14293 Use the first NOPS elements of OPS as the instruction's operands.
14294 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14295 instruction has no target.
14297 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14300 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
14301 struct expand_operand
*ops
, bool has_target_p
)
14303 if (!maybe_expand_insn (icode
, nops
, ops
))
14305 error ("invalid argument to built-in function");
14306 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
14308 return has_target_p
? ops
[0].value
: const0_rtx
;
14311 /* Expand a floating-point comparison for built-in function call EXP.
14312 The first NARGS arguments are the values to be compared. ICODE is
14313 the .md pattern that does the comparison and COND is the condition
14314 that is being tested. Return an rtx for the result. */
14317 mips_expand_builtin_compare_1 (enum insn_code icode
,
14318 enum mips_fp_condition cond
,
14319 tree exp
, int nargs
)
14321 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14325 /* The instruction should have a target operand, an operand for each
14326 argument, and an operand for COND. */
14327 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
14329 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
14331 create_fixed_operand (&ops
[opno
++], output
);
14332 for (argno
= 0; argno
< nargs
; argno
++)
14333 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14334 create_integer_operand (&ops
[opno
++], (int) cond
);
14335 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
14338 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14339 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14340 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14341 suggests a good place to put the result. */
14344 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
14347 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14350 /* Map any target to operand 0. */
14353 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
14355 /* Map the arguments to the other operands. */
14356 gcc_assert (opno
+ call_expr_nargs (exp
)
14357 == insn_data
[icode
].n_generator_args
);
14358 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
14359 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14361 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
14364 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14365 function; TYPE says which. EXP is the CALL_EXPR that calls the
14366 function, ICODE is the instruction that should be used to compare
14367 the first two arguments, and COND is the condition it should test.
14368 TARGET, if nonnull, suggests a good place to put the result. */
14371 mips_expand_builtin_movtf (enum mips_builtin_type type
,
14372 enum insn_code icode
, enum mips_fp_condition cond
,
14373 rtx target
, tree exp
)
14375 struct expand_operand ops
[4];
14378 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
14379 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
14380 if (type
== MIPS_BUILTIN_MOVT
)
14382 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
14383 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
14387 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
14388 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
14390 create_fixed_operand (&ops
[3], cmp_result
);
14391 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
14395 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14396 into TARGET otherwise. Return TARGET. */
14399 mips_builtin_branch_and_move (rtx condition
, rtx target
,
14400 rtx value_if_true
, rtx value_if_false
)
14402 rtx true_label
, done_label
;
14404 true_label
= gen_label_rtx ();
14405 done_label
= gen_label_rtx ();
14407 /* First assume that CONDITION is false. */
14408 mips_emit_move (target
, value_if_false
);
14410 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14411 emit_jump_insn (gen_condjump (condition
, true_label
));
14412 emit_jump_insn (gen_jump (done_label
));
14415 /* Fix TARGET if CONDITION is true. */
14416 emit_label (true_label
);
14417 mips_emit_move (target
, value_if_true
);
14419 emit_label (done_label
);
14423 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14424 the CALL_EXPR that calls the function, ICODE is the code of the
14425 comparison instruction, and COND is the condition it should test.
14426 TARGET, if nonnull, suggests a good place to put the boolean result. */
14429 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
14430 enum insn_code icode
, enum mips_fp_condition cond
,
14431 rtx target
, tree exp
)
14433 rtx offset
, condition
, cmp_result
;
14435 if (target
== 0 || GET_MODE (target
) != SImode
)
14436 target
= gen_reg_rtx (SImode
);
14437 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
14438 call_expr_nargs (exp
));
14440 /* If the comparison sets more than one register, we define the result
14441 to be 0 if all registers are false and -1 if all registers are true.
14442 The value of the complete result is indeterminate otherwise. */
14443 switch (builtin_type
)
14445 case MIPS_BUILTIN_CMP_ALL
:
14446 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
14447 return mips_builtin_branch_and_move (condition
, target
,
14448 const0_rtx
, const1_rtx
);
14450 case MIPS_BUILTIN_CMP_UPPER
:
14451 case MIPS_BUILTIN_CMP_LOWER
:
14452 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
14453 condition
= gen_single_cc (cmp_result
, offset
);
14454 return mips_builtin_branch_and_move (condition
, target
,
14455 const1_rtx
, const0_rtx
);
14458 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
14459 return mips_builtin_branch_and_move (condition
, target
,
14460 const1_rtx
, const0_rtx
);
14464 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14465 if nonnull, suggests a good place to put the boolean result. */
14468 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
14470 rtx condition
, cmp_result
;
14473 if (target
== 0 || GET_MODE (target
) != SImode
)
14474 target
= gen_reg_rtx (SImode
);
14476 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
14478 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
14483 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
14484 return mips_builtin_branch_and_move (condition
, target
,
14485 const1_rtx
, const0_rtx
);
14488 /* Implement TARGET_EXPAND_BUILTIN. */
14491 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14492 enum machine_mode mode
, int ignore
)
14495 unsigned int fcode
, avail
;
14496 const struct mips_builtin_description
*d
;
14498 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14499 fcode
= DECL_FUNCTION_CODE (fndecl
);
14500 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
14501 d
= &mips_builtins
[fcode
];
14502 avail
= d
->avail ();
14503 gcc_assert (avail
!= 0);
14506 error ("built-in function %qE not supported for MIPS16",
14507 DECL_NAME (fndecl
));
14508 return ignore
? const0_rtx
: CONST0_RTX (mode
);
14510 switch (d
->builtin_type
)
14512 case MIPS_BUILTIN_DIRECT
:
14513 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
14515 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
14516 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
14518 case MIPS_BUILTIN_MOVT
:
14519 case MIPS_BUILTIN_MOVF
:
14520 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
14521 d
->cond
, target
, exp
);
14523 case MIPS_BUILTIN_CMP_ANY
:
14524 case MIPS_BUILTIN_CMP_ALL
:
14525 case MIPS_BUILTIN_CMP_UPPER
:
14526 case MIPS_BUILTIN_CMP_LOWER
:
14527 case MIPS_BUILTIN_CMP_SINGLE
:
14528 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
14529 d
->cond
, target
, exp
);
14531 case MIPS_BUILTIN_BPOSGE32
:
14532 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
14534 gcc_unreachable ();
14537 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14538 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14539 struct mips16_constant
{
14540 struct mips16_constant
*next
;
14543 enum machine_mode mode
;
14546 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14547 first constant, HIGHEST_ADDRESS is the highest address that the first
14548 byte of the pool can have, and INSN_ADDRESS is the current instruction
14550 struct mips16_constant_pool
{
14551 struct mips16_constant
*first
;
14552 int highest_address
;
14556 /* Add constant VALUE to POOL and return its label. MODE is the
14557 value's mode (used for CONST_INTs, etc.). */
14560 mips16_add_constant (struct mips16_constant_pool
*pool
,
14561 rtx value
, enum machine_mode mode
)
14563 struct mips16_constant
**p
, *c
;
14564 bool first_of_size_p
;
14566 /* See whether the constant is already in the pool. If so, return the
14567 existing label, otherwise leave P pointing to the place where the
14568 constant should be added.
14570 Keep the pool sorted in increasing order of mode size so that we can
14571 reduce the number of alignments needed. */
14572 first_of_size_p
= true;
14573 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
14575 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
14576 return (*p
)->label
;
14577 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
14579 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
14580 first_of_size_p
= false;
14583 /* In the worst case, the constant needed by the earliest instruction
14584 will end up at the end of the pool. The entire pool must then be
14585 accessible from that instruction.
14587 When adding the first constant, set the pool's highest address to
14588 the address of the first out-of-range byte. Adjust this address
14589 downwards each time a new constant is added. */
14590 if (pool
->first
== 0)
14591 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14592 of the instruction with the lowest two bits clear. The base PC
14593 value for LDPC has the lowest three bits clear. Assume the worst
14594 case here; namely that the PC-relative instruction occupies the
14595 last 2 bytes in an aligned word. */
14596 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
14597 pool
->highest_address
-= GET_MODE_SIZE (mode
);
14598 if (first_of_size_p
)
14599 /* Take into account the worst possible padding due to alignment. */
14600 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
14602 /* Create a new entry. */
14603 c
= XNEW (struct mips16_constant
);
14606 c
->label
= gen_label_rtx ();
14613 /* Output constant VALUE after instruction INSN and return the last
14614 instruction emitted. MODE is the mode of the constant. */
14617 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
14619 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
14621 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
14622 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
14625 if (SCALAR_FLOAT_MODE_P (mode
))
14626 return emit_insn_after (gen_consttable_float (value
), insn
);
14628 if (VECTOR_MODE_P (mode
))
14632 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
14633 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
14634 CONST_VECTOR_ELT (value
, i
), insn
);
14638 gcc_unreachable ();
14641 /* Dump out the constants in CONSTANTS after INSN. */
14644 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
14646 struct mips16_constant
*c
, *next
;
14650 for (c
= constants
; c
!= NULL
; c
= next
)
14652 /* If necessary, increase the alignment of PC. */
14653 if (align
< GET_MODE_SIZE (c
->mode
))
14655 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
14656 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
14658 align
= GET_MODE_SIZE (c
->mode
);
14660 insn
= emit_label_after (c
->label
, insn
);
14661 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
14667 emit_barrier_after (insn
);
14670 /* Return the length of instruction INSN. */
14673 mips16_insn_length (rtx insn
)
14675 if (JUMP_TABLE_DATA_P (insn
))
14677 rtx body
= PATTERN (insn
);
14678 if (GET_CODE (body
) == ADDR_VEC
)
14679 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
14680 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
14681 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
14683 gcc_unreachable ();
14685 return get_attr_length (insn
);
14688 /* If *X is a symbolic constant that refers to the constant pool, add
14689 the constant to POOL and rewrite *X to use the constant's label. */
14692 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
14694 rtx base
, offset
, label
;
14696 split_const (*x
, &base
, &offset
);
14697 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
14699 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
14700 get_pool_mode (base
));
14701 base
= gen_rtx_LABEL_REF (Pmode
, label
);
14702 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
14706 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14707 INSN is the instruction we're rewriting and POOL points to the current
14709 struct mips16_rewrite_pool_refs_info
{
14711 struct mips16_constant_pool
*pool
;
14714 /* Rewrite *X so that constant pool references refer to the constant's
14715 label instead. DATA points to a mips16_rewrite_pool_refs_info
14719 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
14721 struct mips16_rewrite_pool_refs_info
*info
=
14722 (struct mips16_rewrite_pool_refs_info
*) data
;
14724 if (force_to_mem_operand (*x
, Pmode
))
14726 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
14727 validate_change (info
->insn
, x
, mem
, false);
14732 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
14736 /* Don't rewrite the __mips16_rdwr symbol. */
14737 if (GET_CODE (*x
) == UNSPEC
&& XINT (*x
, 1) == UNSPEC_TLS_GET_TP
)
14740 if (TARGET_MIPS16_TEXT_LOADS
)
14741 mips16_rewrite_pool_constant (info
->pool
, x
);
14743 return GET_CODE (*x
) == CONST
? -1 : 0;
14746 /* Return whether CFG is used in mips_reorg. */
14749 mips_cfg_in_reorg (void)
14751 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
14752 || TARGET_RELAX_PIC_CALLS
);
14755 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14756 otherwise assume that they are already split. */
14759 mips16_lay_out_constants (bool split_p
)
14761 struct mips16_constant_pool pool
;
14762 struct mips16_rewrite_pool_refs_info info
;
14765 if (!TARGET_MIPS16_PCREL_LOADS
)
14770 if (mips_cfg_in_reorg ())
14771 split_all_insns ();
14773 split_all_insns_noflow ();
14776 memset (&pool
, 0, sizeof (pool
));
14777 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14779 /* Rewrite constant pool references in INSN. */
14780 if (USEFUL_INSN_P (insn
))
14784 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
14787 pool
.insn_address
+= mips16_insn_length (insn
);
14789 if (pool
.first
!= NULL
)
14791 /* If there are no natural barriers between the first user of
14792 the pool and the highest acceptable address, we'll need to
14793 create a new instruction to jump around the constant pool.
14794 In the worst case, this instruction will be 4 bytes long.
14796 If it's too late to do this transformation after INSN,
14797 do it immediately before INSN. */
14798 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
14802 label
= gen_label_rtx ();
14804 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
14805 JUMP_LABEL (jump
) = label
;
14806 LABEL_NUSES (label
) = 1;
14807 barrier
= emit_barrier_after (jump
);
14809 emit_label_after (label
, barrier
);
14810 pool
.insn_address
+= 4;
14813 /* See whether the constant pool is now out of range of the first
14814 user. If so, output the constants after the previous barrier.
14815 Note that any instructions between BARRIER and INSN (inclusive)
14816 will use negative offsets to refer to the pool. */
14817 if (pool
.insn_address
> pool
.highest_address
)
14819 mips16_emit_constants (pool
.first
, barrier
);
14823 else if (BARRIER_P (insn
))
14827 mips16_emit_constants (pool
.first
, get_last_insn ());
14830 /* Return true if it is worth r10k_simplify_address's while replacing
14831 an address with X. We are looking for constants, and for addresses
14832 at a known offset from the incoming stack pointer. */
14835 r10k_simplified_address_p (rtx x
)
14837 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
14839 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
14842 /* X is an expression that appears in INSN. Try to use the UD chains
14843 to simplify it, returning the simplified form on success and the
14844 original form otherwise. Replace the incoming value of $sp with
14845 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14848 r10k_simplify_address (rtx x
, rtx insn
)
14850 rtx newx
, op0
, op1
, set
, def_insn
, note
;
14852 struct df_link
*defs
;
14857 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14858 if (op0
!= XEXP (x
, 0))
14859 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
14860 op0
, GET_MODE (XEXP (x
, 0)));
14862 else if (BINARY_P (x
))
14864 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14865 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
14866 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
14867 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
14869 else if (GET_CODE (x
) == LO_SUM
)
14871 /* LO_SUMs can be offset from HIGHs, if we know they won't
14872 overflow. See mips_classify_address for the rationale behind
14874 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14875 if (GET_CODE (op0
) == HIGH
)
14876 newx
= XEXP (x
, 1);
14878 else if (REG_P (x
))
14880 /* Uses are recorded by regno_reg_rtx, not X itself. */
14881 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
14883 defs
= DF_REF_CHAIN (use
);
14885 /* Require a single definition. */
14886 if (defs
&& defs
->next
== NULL
)
14889 if (DF_REF_IS_ARTIFICIAL (def
))
14891 /* Replace the incoming value of $sp with
14892 virtual_incoming_args_rtx. */
14893 if (x
== stack_pointer_rtx
14894 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR_FOR_FN (cfun
))
14895 newx
= virtual_incoming_args_rtx
;
14897 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
14900 /* Make sure that DEF_INSN is a single set of REG. */
14901 def_insn
= DF_REF_INSN (def
);
14902 if (NONJUMP_INSN_P (def_insn
))
14904 set
= single_set (def_insn
);
14905 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
14907 /* Prefer to use notes, since the def-use chains
14908 are often shorter. */
14909 note
= find_reg_equal_equiv_note (def_insn
);
14911 newx
= XEXP (note
, 0);
14913 newx
= SET_SRC (set
);
14914 newx
= r10k_simplify_address (newx
, def_insn
);
14920 if (newx
&& r10k_simplified_address_p (newx
))
14925 /* Return true if ADDRESS is known to be an uncached address
14926 on R10K systems. */
14929 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
14931 unsigned HOST_WIDE_INT upper
;
14933 /* Check for KSEG1. */
14934 if (address
+ 0x60000000 < 0x20000000)
14937 /* Check for uncached XKPHYS addresses. */
14938 if (Pmode
== DImode
)
14940 upper
= (address
>> 40) & 0xf9ffff;
14941 if (upper
== 0x900000 || upper
== 0xb80000)
14947 /* Return true if we can prove that an access to address X in instruction
14948 INSN would be safe from R10K speculation. This X is a general
14949 expression; it might not be a legitimate address. */
14952 r10k_safe_address_p (rtx x
, rtx insn
)
14955 HOST_WIDE_INT offset_val
;
14957 x
= r10k_simplify_address (x
, insn
);
14959 /* Check for references to the stack frame. It doesn't really matter
14960 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14961 allows us to assume that accesses to any part of the eventual frame
14962 is safe from speculation at any point in the function. */
14963 mips_split_plus (x
, &base
, &offset_val
);
14964 if (base
== virtual_incoming_args_rtx
14965 && offset_val
>= -cfun
->machine
->frame
.total_size
14966 && offset_val
< cfun
->machine
->frame
.args_size
)
14969 /* Check for uncached addresses. */
14970 if (CONST_INT_P (x
))
14971 return r10k_uncached_address_p (INTVAL (x
));
14973 /* Check for accesses to a static object. */
14974 split_const (x
, &base
, &offset
);
14975 return offset_within_block_p (base
, INTVAL (offset
));
14978 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14979 an in-range access to an automatic variable, or to an object with
14980 a link-time-constant address. */
14983 r10k_safe_mem_expr_p (tree expr
, unsigned HOST_WIDE_INT offset
)
14985 HOST_WIDE_INT bitoffset
, bitsize
;
14986 tree inner
, var_offset
;
14987 enum machine_mode mode
;
14988 int unsigned_p
, volatile_p
;
14990 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
14991 &unsigned_p
, &volatile_p
, false);
14992 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
14995 offset
+= bitoffset
/ BITS_PER_UNIT
;
14996 return offset
< tree_to_uhwi (DECL_SIZE_UNIT (inner
));
14999 /* A for_each_rtx callback for which DATA points to the instruction
15000 containing *X. Stop the search if we find a MEM that is not safe
15001 from R10K speculation. */
15004 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
15013 && MEM_OFFSET_KNOWN_P (mem
)
15014 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
15017 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
15023 /* A note_stores callback for which DATA points to an instruction pointer.
15024 If *DATA is nonnull, make it null if it X contains a MEM that is not
15025 safe from R10K speculation. */
15028 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
15033 insn_ptr
= (rtx
*) data
;
15034 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
15035 *insn_ptr
= NULL_RTX
;
15038 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
15039 Return nonzero if the call is not to a declared function. */
15042 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
15051 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
15057 /* Return true if instruction INSN needs to be protected by an R10K
15061 r10k_needs_protection_p (rtx insn
)
15064 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
15066 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
15068 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
15069 return insn
== NULL_RTX
;
15072 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
15075 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15076 edge is unconditional. */
15079 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
15084 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
15085 if (!single_succ_p (e
->src
)
15086 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
15087 || (e
->flags
& EDGE_COMPLEX
) != 0)
15092 /* Implement -mr10k-cache-barrier= for the current function. */
15095 r10k_insert_cache_barriers (void)
15097 int *rev_post_order
;
15100 sbitmap protected_bbs
;
15101 rtx insn
, end
, unprotected_region
;
15105 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15109 /* Calculate dominators. */
15110 calculate_dominance_info (CDI_DOMINATORS
);
15112 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15113 X is protected by a cache barrier. */
15114 protected_bbs
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
15115 bitmap_clear (protected_bbs
);
15117 /* Iterate over the basic blocks in reverse post-order. */
15118 rev_post_order
= XNEWVEC (int, last_basic_block_for_fn (cfun
));
15119 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
15120 for (i
= 0; i
< n
; i
++)
15122 bb
= BASIC_BLOCK_FOR_FN (cfun
, rev_post_order
[i
]);
15124 /* If this block is only reached by unconditional edges, and if the
15125 source of every edge is protected, the beginning of the block is
15127 if (r10k_protected_bb_p (bb
, protected_bbs
))
15128 unprotected_region
= NULL_RTX
;
15130 unprotected_region
= pc_rtx
;
15131 end
= NEXT_INSN (BB_END (bb
));
15133 /* UNPROTECTED_REGION is:
15135 - null if we are processing a protected region,
15136 - pc_rtx if we are processing an unprotected region but have
15137 not yet found the first instruction in it
15138 - the first instruction in an unprotected region otherwise. */
15139 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
15141 if (unprotected_region
&& USEFUL_INSN_P (insn
))
15143 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
15144 /* This CACHE instruction protects the following code. */
15145 unprotected_region
= NULL_RTX
;
15148 /* See if INSN is the first instruction in this
15149 unprotected region. */
15150 if (unprotected_region
== pc_rtx
)
15151 unprotected_region
= insn
;
15153 /* See if INSN needs to be protected. If so,
15154 we must insert a cache barrier somewhere between
15155 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15156 clear which position is better performance-wise,
15157 but as a tie-breaker, we assume that it is better
15158 to allow delay slots to be back-filled where
15159 possible, and that it is better not to insert
15160 barriers in the middle of already-scheduled code.
15161 We therefore insert the barrier at the beginning
15163 if (r10k_needs_protection_p (insn
))
15165 emit_insn_before (gen_r10k_cache_barrier (),
15166 unprotected_region
);
15167 unprotected_region
= NULL_RTX
;
15173 /* The called function is not required to protect the exit path.
15174 The code that follows a call is therefore unprotected. */
15175 unprotected_region
= pc_rtx
;
15178 /* Record whether the end of this block is protected. */
15179 if (unprotected_region
== NULL_RTX
)
15180 bitmap_set_bit (protected_bbs
, bb
->index
);
15182 XDELETEVEC (rev_post_order
);
15184 sbitmap_free (protected_bbs
);
15186 free_dominance_info (CDI_DOMINATORS
);
15189 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15190 otherwise. If INSN has two call rtx, then store the second one in
15194 mips_call_expr_from_insn (rtx insn
, rtx
*second_call
)
15199 if (!CALL_P (insn
))
15202 x
= PATTERN (insn
);
15203 if (GET_CODE (x
) == PARALLEL
)
15205 /* Calls returning complex values have two CALL rtx. Look for the second
15206 one here, and return it via the SECOND_CALL arg. */
15207 x2
= XVECEXP (x
, 0, 1);
15208 if (GET_CODE (x2
) == SET
)
15210 if (GET_CODE (x2
) == CALL
)
15213 x
= XVECEXP (x
, 0, 0);
15215 if (GET_CODE (x
) == SET
)
15217 gcc_assert (GET_CODE (x
) == CALL
);
15222 /* REG is set in DEF. See if the definition is one of the ways we load a
15223 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15224 If it is, return the symbol reference of the function, otherwise return
15227 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15228 the values of source registers, otherwise treat such registers as
15229 having an unknown value. */
15232 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
15236 if (DF_REF_IS_ARTIFICIAL (def
))
15239 def_insn
= DF_REF_INSN (def
);
15240 set
= single_set (def_insn
);
15241 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
15243 rtx note
, src
, symbol
;
15245 /* First see whether the source is a plain symbol. This is used
15246 when calling symbols that are not lazily bound. */
15247 src
= SET_SRC (set
);
15248 if (GET_CODE (src
) == SYMBOL_REF
)
15251 /* Handle %call16 references. */
15252 symbol
= mips_strip_unspec_call (src
);
15255 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15259 /* If we have something more complicated, look for a
15260 REG_EQUAL or REG_EQUIV note. */
15261 note
= find_reg_equal_equiv_note (def_insn
);
15262 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
15263 return XEXP (note
, 0);
15265 /* Follow at most one simple register copy. Such copies are
15266 interesting in cases like:
15270 locally_binding_fn (...);
15275 locally_binding_fn (...);
15277 locally_binding_fn (...);
15279 where the load of locally_binding_fn can legitimately be
15280 hoisted or shared. However, we do not expect to see complex
15281 chains of copies, so a full worklist solution to the problem
15282 would probably be overkill. */
15283 if (recurse_p
&& REG_P (src
))
15284 return mips_find_pic_call_symbol (def_insn
, src
, false);
15290 /* Find the definition of the use of REG in INSN. See if the definition
15291 is one of the ways we load a register with a symbol address for a
15292 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15293 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15294 mips_pic_call_symbol_from_set. */
15297 mips_find_pic_call_symbol (rtx insn
, rtx reg
, bool recurse_p
)
15300 struct df_link
*defs
;
15303 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
15306 defs
= DF_REF_CHAIN (use
);
15309 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15313 /* If we have more than one definition, they need to be identical. */
15314 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
15318 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15319 if (!rtx_equal_p (symbol
, other
))
15326 /* Replace the args_size operand of the call expression CALL with the
15327 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15330 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
15334 args_size
= XEXP (call
, 1);
15335 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
15336 gen_rtvec (2, args_size
, symbol
),
15340 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15341 if instead of the arg_size argument it contains the call attributes. If
15342 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15343 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15347 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
15349 rtx args_size
, symbol
;
15351 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
15354 args_size
= operands
[args_size_opno
];
15355 if (GET_CODE (args_size
) != UNSPEC
)
15357 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
15359 symbol
= XVECEXP (args_size
, 0, 1);
15360 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15362 operands
[args_size_opno
] = symbol
;
15366 /* Use DF to annotate PIC indirect calls with the function symbol they
15370 mips_annotate_pic_calls (void)
15375 FOR_EACH_BB_FN (bb
, cfun
)
15376 FOR_BB_INSNS (bb
, insn
)
15378 rtx call
, reg
, symbol
, second_call
;
15381 call
= mips_call_expr_from_insn (insn
, &second_call
);
15384 gcc_assert (MEM_P (XEXP (call
, 0)));
15385 reg
= XEXP (XEXP (call
, 0), 0);
15389 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
15392 mips_annotate_pic_call_expr (call
, symbol
);
15394 mips_annotate_pic_call_expr (second_call
, symbol
);
15399 /* A temporary variable used by for_each_rtx callbacks, etc. */
15400 static rtx mips_sim_insn
;
15402 /* A structure representing the state of the processor pipeline.
15403 Used by the mips_sim_* family of functions. */
15405 /* The maximum number of instructions that can be issued in a cycle.
15406 (Caches mips_issue_rate.) */
15407 unsigned int issue_rate
;
15409 /* The current simulation time. */
15412 /* How many more instructions can be issued in the current cycle. */
15413 unsigned int insns_left
;
15415 /* LAST_SET[X].INSN is the last instruction to set register X.
15416 LAST_SET[X].TIME is the time at which that instruction was issued.
15417 INSN is null if no instruction has yet set register X. */
15421 } last_set
[FIRST_PSEUDO_REGISTER
];
15423 /* The pipeline's current DFA state. */
15427 /* Reset STATE to the initial simulation state. */
15430 mips_sim_reset (struct mips_sim
*state
)
15432 curr_state
= state
->dfa_state
;
15435 state
->insns_left
= state
->issue_rate
;
15436 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
15437 state_reset (curr_state
);
15439 targetm
.sched
.init (0, false, 0);
15440 advance_state (curr_state
);
15443 /* Initialize STATE before its first use. DFA_STATE points to an
15444 allocated but uninitialized DFA state. */
15447 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
15449 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
15450 targetm
.sched
.init_dfa_pre_cycle_insn ();
15452 if (targetm
.sched
.init_dfa_post_cycle_insn
)
15453 targetm
.sched
.init_dfa_post_cycle_insn ();
15455 state
->issue_rate
= mips_issue_rate ();
15456 state
->dfa_state
= dfa_state
;
15457 mips_sim_reset (state
);
15460 /* Advance STATE by one clock cycle. */
15463 mips_sim_next_cycle (struct mips_sim
*state
)
15465 curr_state
= state
->dfa_state
;
15468 state
->insns_left
= state
->issue_rate
;
15469 advance_state (curr_state
);
15472 /* Advance simulation state STATE until instruction INSN can read
15476 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
15478 unsigned int regno
, end_regno
;
15480 end_regno
= END_REGNO (reg
);
15481 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
15482 if (state
->last_set
[regno
].insn
!= 0)
15486 t
= (state
->last_set
[regno
].time
15487 + insn_latency (state
->last_set
[regno
].insn
, insn
));
15488 while (state
->time
< t
)
15489 mips_sim_next_cycle (state
);
15493 /* A for_each_rtx callback. If *X is a register, advance simulation state
15494 DATA until mips_sim_insn can read the register's value. */
15497 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
15500 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
15504 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15507 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
15509 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
15512 /* Advance simulation state STATE until all of INSN's register
15513 dependencies are satisfied. */
15516 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
15518 mips_sim_insn
= insn
;
15519 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
15522 /* Advance simulation state STATE until the units required by
15523 instruction INSN are available. */
15526 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
15530 tmp_state
= alloca (state_size ());
15531 while (state
->insns_left
== 0
15532 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
15533 state_transition (tmp_state
, insn
) >= 0))
15534 mips_sim_next_cycle (state
);
15537 /* Advance simulation state STATE until INSN is ready to issue. */
15540 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
15542 mips_sim_wait_regs (state
, insn
);
15543 mips_sim_wait_units (state
, insn
);
15546 /* mips_sim_insn has just set X. Update the LAST_SET array
15547 in simulation state DATA. */
15550 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
15552 struct mips_sim
*state
;
15554 state
= (struct mips_sim
*) data
;
15557 unsigned int regno
, end_regno
;
15559 end_regno
= END_REGNO (x
);
15560 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
15562 state
->last_set
[regno
].insn
= mips_sim_insn
;
15563 state
->last_set
[regno
].time
= state
->time
;
15568 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15569 can issue immediately (i.e., that mips_sim_wait_insn has already
15573 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
15575 curr_state
= state
->dfa_state
;
15577 state_transition (curr_state
, insn
);
15578 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
15579 state
->insns_left
);
15581 mips_sim_insn
= insn
;
15582 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
15585 /* Simulate issuing a NOP in state STATE. */
15588 mips_sim_issue_nop (struct mips_sim
*state
)
15590 if (state
->insns_left
== 0)
15591 mips_sim_next_cycle (state
);
15592 state
->insns_left
--;
15595 /* Update simulation state STATE so that it's ready to accept the instruction
15596 after INSN. INSN should be part of the main rtl chain, not a member of a
15600 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
15602 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15604 mips_sim_issue_nop (state
);
15606 switch (GET_CODE (SEQ_BEGIN (insn
)))
15610 /* We can't predict the processor state after a call or label. */
15611 mips_sim_reset (state
);
15615 /* The delay slots of branch likely instructions are only executed
15616 when the branch is taken. Therefore, if the caller has simulated
15617 the delay slot instruction, STATE does not really reflect the state
15618 of the pipeline for the instruction after the delay slot. Also,
15619 branch likely instructions tend to incur a penalty when not taken,
15620 so there will probably be an extra delay between the branch and
15621 the instruction after the delay slot. */
15622 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
15623 mips_sim_reset (state
);
15631 /* Use simulator state STATE to calculate the execution time of
15632 instruction sequence SEQ. */
15634 static unsigned int
15635 mips_seq_time (struct mips_sim
*state
, rtx seq
)
15637 mips_sim_reset (state
);
15638 for (rtx insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
15640 mips_sim_wait_insn (state
, insn
);
15641 mips_sim_issue_insn (state
, insn
);
15643 return state
->time
;
15646 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15647 setting SETTING, using STATE to simulate instruction sequences. */
15649 static unsigned int
15650 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
15652 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
15655 enum machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
15656 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
15657 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
15659 /* If the target provides mulsidi3_32bit then that's the most likely
15660 consumer of the result. Test for bypasses. */
15661 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
15663 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
15664 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
15667 unsigned int time
= mips_seq_time (state
, get_insns ());
15672 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15673 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15674 Prefer MULT -- which is shorter -- in the event of a tie. */
15677 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
15680 /* No MTLO or MTHI available. */
15681 mips_tuning_info
.fast_mult_zero_zero_p
= true;
15684 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
15685 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
15686 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
15690 /* Set up costs based on the current architecture and tuning settings. */
15693 mips_set_tuning_info (void)
15695 if (mips_tuning_info
.initialized_p
15696 && mips_tuning_info
.arch
== mips_arch
15697 && mips_tuning_info
.tune
== mips_tune
15698 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
15701 mips_tuning_info
.arch
= mips_arch
;
15702 mips_tuning_info
.tune
= mips_tune
;
15703 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
15704 mips_tuning_info
.initialized_p
= true;
15708 struct mips_sim state
;
15709 mips_sim_init (&state
, alloca (state_size ()));
15711 mips_set_fast_mult_zero_zero_p (&state
);
15716 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15719 mips_expand_to_rtl_hook (void)
15721 /* We need to call this at a point where we can safely create sequences
15722 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15723 need to call it at a point where the DFA infrastructure is not
15724 already in use, so we can't just call it lazily on demand.
15726 At present, mips_tuning_info is only needed during post-expand
15727 RTL passes such as split_insns, so this hook should be early enough.
15728 We may need to move the call elsewhere if mips_tuning_info starts
15729 to be used for other things (such as rtx_costs, or expanders that
15730 could be called during gimple optimization). */
15731 mips_set_tuning_info ();
15734 /* The VR4130 pipeline issues aligned pairs of instructions together,
15735 but it stalls the second instruction if it depends on the first.
15736 In order to cut down the amount of logic required, this dependence
15737 check is not based on a full instruction decode. Instead, any non-SPECIAL
15738 instruction is assumed to modify the register specified by bits 20-16
15739 (which is usually the "rt" field).
15741 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15742 input, so we can end up with a false dependence between the branch
15743 and its delay slot. If this situation occurs in instruction INSN,
15744 try to avoid it by swapping rs and rt. */
15747 vr4130_avoid_branch_rt_conflict (rtx insn
)
15751 first
= SEQ_BEGIN (insn
);
15752 second
= SEQ_END (insn
);
15754 && NONJUMP_INSN_P (second
)
15755 && GET_CODE (PATTERN (first
)) == SET
15756 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
15757 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
15759 /* Check for the right kind of condition. */
15760 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
15761 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
15762 && REG_P (XEXP (cond
, 0))
15763 && REG_P (XEXP (cond
, 1))
15764 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
15765 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
15767 /* SECOND mentions the rt register but not the rs register. */
15768 rtx tmp
= XEXP (cond
, 0);
15769 XEXP (cond
, 0) = XEXP (cond
, 1);
15770 XEXP (cond
, 1) = tmp
;
15775 /* Implement -mvr4130-align. Go through each basic block and simulate the
15776 processor pipeline. If we find that a pair of instructions could execute
15777 in parallel, and the first of those instructions is not 8-byte aligned,
15778 insert a nop to make it aligned. */
15781 vr4130_align_insns (void)
15783 struct mips_sim state
;
15784 rtx insn
, subinsn
, last
, last2
, next
;
15789 /* LAST is the last instruction before INSN to have a nonzero length.
15790 LAST2 is the last such instruction before LAST. */
15794 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15797 mips_sim_init (&state
, alloca (state_size ()));
15798 for (insn
= get_insns (); insn
!= 0; insn
= next
)
15800 unsigned int length
;
15802 next
= NEXT_INSN (insn
);
15804 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15805 This isn't really related to the alignment pass, but we do it on
15806 the fly to avoid a separate instruction walk. */
15807 vr4130_avoid_branch_rt_conflict (insn
);
15809 length
= get_attr_length (insn
);
15810 if (length
> 0 && USEFUL_INSN_P (insn
))
15811 FOR_EACH_SUBINSN (subinsn
, insn
)
15813 mips_sim_wait_insn (&state
, subinsn
);
15815 /* If we want this instruction to issue in parallel with the
15816 previous one, make sure that the previous instruction is
15817 aligned. There are several reasons why this isn't worthwhile
15818 when the second instruction is a call:
15820 - Calls are less likely to be performance critical,
15821 - There's a good chance that the delay slot can execute
15822 in parallel with the call.
15823 - The return address would then be unaligned.
15825 In general, if we're going to insert a nop between instructions
15826 X and Y, it's better to insert it immediately after X. That
15827 way, if the nop makes Y aligned, it will also align any labels
15828 between X and Y. */
15829 if (state
.insns_left
!= state
.issue_rate
15830 && !CALL_P (subinsn
))
15832 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
15834 /* SUBINSN is the first instruction in INSN and INSN is
15835 aligned. We want to align the previous instruction
15836 instead, so insert a nop between LAST2 and LAST.
15838 Note that LAST could be either a single instruction
15839 or a branch with a delay slot. In the latter case,
15840 LAST, like INSN, is already aligned, but the delay
15841 slot must have some extra delay that stops it from
15842 issuing at the same time as the branch. We therefore
15843 insert a nop before the branch in order to align its
15845 gcc_assert (last2
);
15846 emit_insn_after (gen_nop (), last2
);
15849 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
15851 /* SUBINSN is the delay slot of INSN, but INSN is
15852 currently unaligned. Insert a nop between
15853 LAST and INSN to align it. */
15855 emit_insn_after (gen_nop (), last
);
15859 mips_sim_issue_insn (&state
, subinsn
);
15861 mips_sim_finish_insn (&state
, insn
);
15863 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15864 length
= get_attr_length (insn
);
15867 /* If the instruction is an asm statement or multi-instruction
15868 mips.md patern, the length is only an estimate. Insert an
15869 8 byte alignment after it so that the following instructions
15870 can be handled correctly. */
15871 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
15872 && (recog_memoized (insn
) < 0 || length
>= 8))
15874 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
15875 next
= NEXT_INSN (next
);
15876 mips_sim_next_cycle (&state
);
15879 else if (length
& 4)
15880 aligned_p
= !aligned_p
;
15885 /* See whether INSN is an aligned label. */
15886 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
15892 /* This structure records that the current function has a LO_SUM
15893 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15894 the largest offset applied to BASE by all such LO_SUMs. */
15895 struct mips_lo_sum_offset
{
15897 HOST_WIDE_INT offset
;
15900 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15903 mips_hash_base (rtx base
)
15905 int do_not_record_p
;
15907 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
15910 /* Hashtable helpers. */
15912 struct mips_lo_sum_offset_hasher
: typed_free_remove
<mips_lo_sum_offset
>
15914 typedef mips_lo_sum_offset value_type
;
15915 typedef rtx_def compare_type
;
15916 static inline hashval_t
hash (const value_type
*);
15917 static inline bool equal (const value_type
*, const compare_type
*);
15920 /* Hash-table callbacks for mips_lo_sum_offsets. */
15923 mips_lo_sum_offset_hasher::hash (const value_type
*entry
)
15925 return mips_hash_base (entry
->base
);
15929 mips_lo_sum_offset_hasher::equal (const value_type
*entry
,
15930 const compare_type
*value
)
15932 return rtx_equal_p (entry
->base
, value
);
15935 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
15937 /* Look up symbolic constant X in HTAB, which is a hash table of
15938 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15939 paired with a recorded LO_SUM, otherwise record X in the table. */
15942 mips_lo_sum_offset_lookup (mips_offset_table htab
, rtx x
,
15943 enum insert_option option
)
15946 mips_lo_sum_offset
**slot
;
15947 struct mips_lo_sum_offset
*entry
;
15949 /* Split X into a base and offset. */
15950 split_const (x
, &base
, &offset
);
15951 if (UNSPEC_ADDRESS_P (base
))
15952 base
= UNSPEC_ADDRESS (base
);
15954 /* Look up the base in the hash table. */
15955 slot
= htab
.find_slot_with_hash (base
, mips_hash_base (base
), option
);
15959 entry
= (struct mips_lo_sum_offset
*) *slot
;
15960 if (option
== INSERT
)
15964 entry
= XNEW (struct mips_lo_sum_offset
);
15965 entry
->base
= base
;
15966 entry
->offset
= INTVAL (offset
);
15971 if (INTVAL (offset
) > entry
->offset
)
15972 entry
->offset
= INTVAL (offset
);
15975 return INTVAL (offset
) <= entry
->offset
;
15978 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15979 Record every LO_SUM in *LOC. */
15982 mips_record_lo_sum (rtx
*loc
, void *data
)
15984 if (GET_CODE (*loc
) == LO_SUM
)
15985 mips_lo_sum_offset_lookup (*(mips_offset_table
*) data
,
15986 XEXP (*loc
, 1), INSERT
);
15990 /* Return true if INSN is a SET of an orphaned high-part relocation.
15991 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15992 LO_SUMs in the current function. */
15995 mips_orphaned_high_part_p (mips_offset_table htab
, rtx insn
)
15997 enum mips_symbol_type type
;
16000 set
= single_set (insn
);
16003 /* Check for %his. */
16005 if (GET_CODE (x
) == HIGH
16006 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
16007 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
16009 /* Check for local %gots (and %got_pages, which is redundant but OK). */
16010 if (GET_CODE (x
) == UNSPEC
16011 && XINT (x
, 1) == UNSPEC_LOAD_GOT
16012 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
16013 SYMBOL_CONTEXT_LEA
, &type
)
16014 && type
== SYMBOL_GOTOFF_PAGE
)
16015 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
16020 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
16021 INSN and a previous instruction, avoid it by inserting nops after
16024 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
16025 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
16026 before using the value of that register. *HILO_DELAY counts the
16027 number of instructions since the last hilo hazard (that is,
16028 the number of instructions since the last MFLO or MFHI).
16030 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
16031 for the next instruction.
16033 LO_REG is an rtx for the LO register, used in dependence checking. */
16036 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
16037 rtx
*delayed_reg
, rtx lo_reg
)
16042 pattern
= PATTERN (insn
);
16044 /* Do not put the whole function in .set noreorder if it contains
16045 an asm statement. We don't know whether there will be hazards
16046 between the asm statement and the gcc-generated code. */
16047 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
16048 cfun
->machine
->all_noreorder_p
= false;
16050 /* Ignore zero-length instructions (barriers and the like). */
16051 ninsns
= get_attr_length (insn
) / 4;
16055 /* Work out how many nops are needed. Note that we only care about
16056 registers that are explicitly mentioned in the instruction's pattern.
16057 It doesn't matter that calls use the argument registers or that they
16058 clobber hi and lo. */
16059 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
16060 nops
= 2 - *hilo_delay
;
16061 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
16066 /* Insert the nops between this instruction and the previous one.
16067 Each new nop takes us further from the last hilo hazard. */
16068 *hilo_delay
+= nops
;
16070 emit_insn_after (gen_hazard_nop (), after
);
16072 /* Set up the state for the next instruction. */
16073 *hilo_delay
+= ninsns
;
16075 if (INSN_CODE (insn
) >= 0)
16076 switch (get_attr_hazard (insn
))
16086 set
= single_set (insn
);
16088 *delayed_reg
= SET_DEST (set
);
16093 /* Go through the instruction stream and insert nops where necessary.
16094 Also delete any high-part relocations whose partnering low parts
16095 are now all dead. See if the whole function can then be put into
16096 .set noreorder and .set nomacro. */
16099 mips_reorg_process_insns (void)
16101 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
16103 mips_offset_table htab
;
16105 /* Force all instructions to be split into their final form. */
16106 split_all_insns_noflow ();
16108 /* Recalculate instruction lengths without taking nops into account. */
16109 cfun
->machine
->ignore_hazard_length_p
= true;
16110 shorten_branches (get_insns ());
16112 cfun
->machine
->all_noreorder_p
= true;
16114 /* We don't track MIPS16 PC-relative offsets closely enough to make
16115 a good job of "set .noreorder" code in MIPS16 mode. */
16117 cfun
->machine
->all_noreorder_p
= false;
16119 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16120 if (!TARGET_EXPLICIT_RELOCS
)
16121 cfun
->machine
->all_noreorder_p
= false;
16123 /* Profiled functions can't be all noreorder because the profiler
16124 support uses assembler macros. */
16126 cfun
->machine
->all_noreorder_p
= false;
16128 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16129 all noreorder because we rely on the assembler to work around some
16130 errata. The R5900 too has several bugs. */
16131 if (TARGET_FIX_VR4120
16132 || TARGET_FIX_RM7000
16134 || TARGET_MIPS5900
)
16135 cfun
->machine
->all_noreorder_p
= false;
16137 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16138 MFHI instructions. Note that we avoid using MFLO and MFHI if
16139 the VR4130 MACC and DMACC instructions are available instead;
16140 see the *mfhilo_{si,di}_macc patterns. */
16141 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
16142 cfun
->machine
->all_noreorder_p
= false;
16146 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16147 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16148 FOR_EACH_SUBINSN (subinsn
, insn
)
16149 if (USEFUL_INSN_P (subinsn
))
16151 rtx body
= PATTERN (insn
);
16152 int noperands
= asm_noperands (body
);
16153 if (noperands
>= 0)
16155 rtx
*ops
= XALLOCAVEC (rtx
, noperands
);
16156 bool *used
= XALLOCAVEC (bool, noperands
);
16157 const char *string
= decode_asm_operands (body
, ops
, NULL
, NULL
,
16159 get_referenced_operands (string
, used
, noperands
);
16160 for (int i
= 0; i
< noperands
; ++i
)
16162 for_each_rtx (&ops
[i
], mips_record_lo_sum
, &htab
);
16165 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, &htab
);
16171 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
16173 /* Make a second pass over the instructions. Delete orphaned
16174 high-part relocations or turn them into NOPs. Avoid hazards
16175 by inserting NOPs. */
16176 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
16178 next_insn
= NEXT_INSN (insn
);
16179 if (USEFUL_INSN_P (insn
))
16181 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
16183 /* If we find an orphaned high-part relocation in a delay
16184 slot, it's easier to turn that instruction into a NOP than
16185 to delete it. The delay slot will be a NOP either way. */
16186 FOR_EACH_SUBINSN (subinsn
, insn
)
16187 if (INSN_P (subinsn
))
16189 if (mips_orphaned_high_part_p (htab
, subinsn
))
16191 PATTERN (subinsn
) = gen_nop ();
16192 INSN_CODE (subinsn
) = CODE_FOR_nop
;
16194 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
16195 &delayed_reg
, lo_reg
);
16201 /* INSN is a single instruction. Delete it if it's an
16202 orphaned high-part relocation. */
16203 if (mips_orphaned_high_part_p (htab
, insn
))
16204 delete_insn (insn
);
16205 /* Also delete cache barriers if the last instruction
16206 was an annulled branch. INSN will not be speculatively
16208 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
16210 && JUMP_P (SEQ_BEGIN (last_insn
))
16211 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
16212 delete_insn (insn
);
16215 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
16216 &delayed_reg
, lo_reg
);
16226 /* Return true if the function has a long branch instruction. */
16229 mips_has_long_branch_p (void)
16234 /* We need up-to-date instruction lengths. */
16235 shorten_branches (get_insns ());
16237 /* Look for a branch that is longer than normal. The normal length for
16238 non-MIPS16 branches is 8, because the length includes the delay slot.
16239 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16240 but they have no delay slot. */
16241 normal_length
= (TARGET_MIPS16
? 4 : 8);
16242 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16243 FOR_EACH_SUBINSN (subinsn
, insn
)
16244 if (JUMP_P (subinsn
)
16245 && get_attr_length (subinsn
) > normal_length
16246 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
16252 /* If we are using a GOT, but have not decided to use a global pointer yet,
16253 see whether we need one to implement long branches. Convert the ghost
16254 global-pointer instructions into real ones if so. */
16257 mips_expand_ghost_gp_insns (void)
16259 /* Quick exit if we already know that we will or won't need a
16261 if (!TARGET_USE_GOT
16262 || cfun
->machine
->global_pointer
== INVALID_REGNUM
16263 || mips_must_initialize_gp_p ())
16266 /* Run a full check for long branches. */
16267 if (!mips_has_long_branch_p ())
16270 /* We've now established that we need $gp. */
16271 cfun
->machine
->must_initialize_gp_p
= true;
16272 split_all_insns_noflow ();
16277 /* Subroutine of mips_reorg to manage passes that require DF. */
16280 mips_df_reorg (void)
16282 /* Create def-use chains. */
16283 df_set_flags (DF_EQ_NOTES
);
16284 df_chain_add_problem (DF_UD_CHAIN
);
16287 if (TARGET_RELAX_PIC_CALLS
)
16288 mips_annotate_pic_calls ();
16290 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
16291 r10k_insert_cache_barriers ();
16293 df_finish_pass (false);
16296 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16297 called very late in mips_reorg, but the caller is required to run
16298 mips16_lay_out_constants on the result. */
16301 mips16_load_branch_target (rtx dest
, rtx src
)
16303 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
16307 if (mips_cfun_has_cprestore_slot_p ())
16308 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
16310 mips_emit_move (dest
, pic_offset_table_rtx
);
16311 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
16312 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
16313 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16314 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
16315 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16316 gen_rtx_LO_SUM (Pmode
, dest
, low
)));
16320 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
16321 mips_emit_move (dest
, src
);
16325 /* If we're compiling a MIPS16 function, look for and split any long branches.
16326 This must be called after all other instruction modifications in
16330 mips16_split_long_branches (void)
16332 bool something_changed
;
16334 if (!TARGET_MIPS16
)
16337 /* Loop until the alignments for all targets are sufficient. */
16342 shorten_branches (get_insns ());
16343 something_changed
= false;
16344 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16346 && get_attr_length (insn
) > 4
16347 && (any_condjump_p (insn
) || any_uncondjump_p (insn
)))
16349 rtx old_label
, new_label
, temp
, saved_temp
;
16350 rtx target
, jump
, jump_sequence
;
16354 /* Free up a MIPS16 register by saving it in $1. */
16355 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
16356 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
16357 emit_move_insn (saved_temp
, temp
);
16359 /* Load the branch target into TEMP. */
16360 old_label
= JUMP_LABEL (insn
);
16361 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
16362 mips16_load_branch_target (temp
, target
);
16364 /* Jump to the target and restore the register's
16366 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
16367 (temp
, temp
, saved_temp
)));
16368 JUMP_LABEL (jump
) = old_label
;
16369 LABEL_NUSES (old_label
)++;
16371 /* Rewrite any symbolic references that are supposed to use
16372 a PC-relative constant pool. */
16373 mips16_lay_out_constants (false);
16375 if (simplejump_p (insn
))
16376 /* We're going to replace INSN with a longer form. */
16377 new_label
= NULL_RTX
;
16380 /* Create a branch-around label for the original
16382 new_label
= gen_label_rtx ();
16383 emit_label (new_label
);
16386 jump_sequence
= get_insns ();
16389 emit_insn_after (jump_sequence
, insn
);
16391 invert_jump (insn
, new_label
, false);
16393 delete_insn (insn
);
16394 something_changed
= true;
16397 while (something_changed
);
16400 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16405 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16406 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16407 to date if the CFG is available. */
16408 if (mips_cfg_in_reorg ())
16409 compute_bb_for_insn ();
16410 mips16_lay_out_constants (true);
16411 if (mips_cfg_in_reorg ())
16414 free_bb_for_insn ();
16418 /* We use a machine specific pass to do a second machine dependent reorg
16419 pass after delay branch scheduling. */
16421 static unsigned int
16422 mips_machine_reorg2 (void)
16424 mips_reorg_process_insns ();
16426 && TARGET_EXPLICIT_RELOCS
16428 && TARGET_VR4130_ALIGN
)
16429 vr4130_align_insns ();
16430 if (mips_expand_ghost_gp_insns ())
16431 /* The expansion could invalidate some of the VR4130 alignment
16432 optimizations, but this should be an extremely rare case anyhow. */
16433 mips_reorg_process_insns ();
16434 mips16_split_long_branches ();
16440 const pass_data pass_data_mips_machine_reorg2
=
16442 RTL_PASS
, /* type */
16443 "mach2", /* name */
16444 OPTGROUP_NONE
, /* optinfo_flags */
16445 false, /* has_gate */
16446 true, /* has_execute */
16447 TV_MACH_DEP
, /* tv_id */
16448 0, /* properties_required */
16449 0, /* properties_provided */
16450 0, /* properties_destroyed */
16451 0, /* todo_flags_start */
16452 TODO_verify_rtl_sharing
, /* todo_flags_finish */
16455 class pass_mips_machine_reorg2
: public rtl_opt_pass
16458 pass_mips_machine_reorg2(gcc::context
*ctxt
)
16459 : rtl_opt_pass(pass_data_mips_machine_reorg2
, ctxt
)
16462 /* opt_pass methods: */
16463 unsigned int execute () { return mips_machine_reorg2 (); }
16465 }; // class pass_mips_machine_reorg2
16467 } // anon namespace
16470 make_pass_mips_machine_reorg2 (gcc::context
*ctxt
)
16472 return new pass_mips_machine_reorg2 (ctxt
);
16476 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16477 in order to avoid duplicating too much logic from elsewhere. */
16480 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
16481 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
16484 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
16485 bool use_sibcall_p
;
16487 /* Pretend to be a post-reload pass while generating rtl. */
16488 reload_completed
= 1;
16490 /* Mark the end of the (empty) prologue. */
16491 emit_note (NOTE_INSN_PROLOGUE_END
);
16493 /* Determine if we can use a sibcall to call FUNCTION directly. */
16494 fnaddr
= XEXP (DECL_RTL (function
), 0);
16495 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
16496 && const_call_insn_operand (fnaddr
, Pmode
));
16498 /* Determine if we need to load FNADDR from the GOT. */
16500 && (mips_got_symbol_type_p
16501 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
16503 /* Pick a global pointer. Use a call-clobbered register if
16504 TARGET_CALL_SAVED_GP. */
16505 cfun
->machine
->global_pointer
16506 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
16507 cfun
->machine
->must_initialize_gp_p
= true;
16508 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
16510 /* Set up the global pointer for n32 or n64 abicalls. */
16511 mips_emit_loadgp ();
16514 /* We need two temporary registers in some cases. */
16515 temp1
= gen_rtx_REG (Pmode
, 2);
16516 temp2
= gen_rtx_REG (Pmode
, 3);
16518 /* Find out which register contains the "this" pointer. */
16519 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
16520 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
16522 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
16524 /* Add DELTA to THIS_RTX. */
16527 rtx offset
= GEN_INT (delta
);
16528 if (!SMALL_OPERAND (delta
))
16530 mips_emit_move (temp1
, offset
);
16533 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
16536 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16537 if (vcall_offset
!= 0)
16541 /* Set TEMP1 to *THIS_RTX. */
16542 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
16544 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16545 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
16547 /* Load the offset and add it to THIS_RTX. */
16548 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
16549 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
16552 /* Jump to the target function. Use a sibcall if direct jumps are
16553 allowed, otherwise load the address into a register first. */
16556 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
16557 SIBLING_CALL_P (insn
) = 1;
16561 /* This is messy. GAS treats "la $25,foo" as part of a call
16562 sequence and may allow a global "foo" to be lazily bound.
16563 The general move patterns therefore reject this combination.
16565 In this context, lazy binding would actually be OK
16566 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16567 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16568 We must therefore load the address via a temporary
16569 register if mips_dangerous_for_la25_p.
16571 If we jump to the temporary register rather than $25,
16572 the assembler can use the move insn to fill the jump's
16575 We can use the same technique for MIPS16 code, where $25
16576 is not a valid JR register. */
16577 if (TARGET_USE_PIC_FN_ADDR_REG
16579 && !mips_dangerous_for_la25_p (fnaddr
))
16580 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
16581 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
16583 if (TARGET_USE_PIC_FN_ADDR_REG
16584 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
16585 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
16586 emit_jump_insn (gen_indirect_jump (temp1
));
16589 /* Run just enough of rest_of_compilation. This sequence was
16590 "borrowed" from alpha.c. */
16591 insn
= get_insns ();
16592 split_all_insns_noflow ();
16593 mips16_lay_out_constants (true);
16594 shorten_branches (insn
);
16595 final_start_function (insn
, file
, 1);
16596 final (insn
, file
, 1);
16597 final_end_function ();
16599 /* Clean up the vars set above. Note that final_end_function resets
16600 the global pointer for us. */
16601 reload_completed
= 0;
16605 /* The last argument passed to mips_set_compression_mode,
16606 or negative if the function hasn't been called yet. */
16607 static unsigned int old_compression_mode
= -1;
16609 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16610 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16613 mips_set_compression_mode (unsigned int compression_mode
)
16616 if (compression_mode
== old_compression_mode
)
16619 /* Restore base settings of various flags. */
16620 target_flags
= mips_base_target_flags
;
16621 flag_schedule_insns
= mips_base_schedule_insns
;
16622 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
16623 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
16624 align_loops
= mips_base_align_loops
;
16625 align_jumps
= mips_base_align_jumps
;
16626 align_functions
= mips_base_align_functions
;
16627 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
16628 target_flags
|= compression_mode
;
16630 if (compression_mode
& MASK_MIPS16
)
16632 /* Switch to MIPS16 mode. */
16633 target_flags
|= MASK_MIPS16
;
16635 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16636 target_flags
&= ~MASK_SYNCI
;
16638 /* Don't run the scheduler before reload, since it tends to
16639 increase register pressure. */
16640 flag_schedule_insns
= 0;
16642 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16643 the whole function to be in a single section. */
16644 flag_reorder_blocks_and_partition
= 0;
16646 /* Don't move loop invariants, because it tends to increase
16647 register pressure. It also introduces an extra move in cases
16648 where the constant is the first operand in a two-operand binary
16649 instruction, or when it forms a register argument to a functon
16651 flag_move_loop_invariants
= 0;
16653 target_flags
|= MASK_EXPLICIT_RELOCS
;
16655 /* Experiments suggest we get the best overall section-anchor
16656 results from using the range of an unextended LW or SW. Code
16657 that makes heavy use of byte or short accesses can do better
16658 with ranges of 0...31 and 0...63 respectively, but most code is
16659 sensitive to the range of LW and SW instead. */
16660 targetm
.min_anchor_offset
= 0;
16661 targetm
.max_anchor_offset
= 127;
16663 targetm
.const_anchor
= 0;
16665 /* MIPS16 has no BAL instruction. */
16666 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
16668 /* The R4000 errata don't apply to any known MIPS16 cores.
16669 It's simpler to make the R4000 fixes and MIPS16 mode
16670 mutually exclusive. */
16671 target_flags
&= ~MASK_FIX_R4000
;
16673 if (flag_pic
&& !TARGET_OLDABI
)
16674 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16677 sorry ("MIPS16 -mxgot code");
16679 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
16680 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16684 /* Switch to microMIPS or the standard encoding. */
16686 if (TARGET_MICROMIPS
)
16687 /* Avoid branch likely. */
16688 target_flags
&= ~MASK_BRANCHLIKELY
;
16690 /* Provide default values for align_* for 64-bit targets. */
16693 if (align_loops
== 0)
16695 if (align_jumps
== 0)
16697 if (align_functions
== 0)
16698 align_functions
= 8;
16701 targetm
.min_anchor_offset
= -32768;
16702 targetm
.max_anchor_offset
= 32767;
16704 targetm
.const_anchor
= 0x8000;
16707 /* (Re)initialize MIPS target internals for new ISA. */
16708 mips_init_relocs ();
16710 if (compression_mode
& MASK_MIPS16
)
16712 if (!mips16_globals
)
16713 mips16_globals
= save_target_globals_default_opts ();
16715 restore_target_globals (mips16_globals
);
16718 restore_target_globals (&default_target_globals
);
16720 old_compression_mode
= compression_mode
;
16723 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16724 function should use the MIPS16 or microMIPS ISA and switch modes
16728 mips_set_current_function (tree fndecl
)
16730 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
16733 /* Allocate a chunk of memory for per-function machine-dependent data. */
16735 static struct machine_function
*
16736 mips_init_machine_status (void)
16738 return ggc_alloc_cleared_machine_function ();
16741 /* Return the processor associated with the given ISA level, or null
16742 if the ISA isn't valid. */
16744 static const struct mips_cpu_info
*
16745 mips_cpu_info_from_isa (int isa
)
16749 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16750 if (mips_cpu_info_table
[i
].isa
== isa
)
16751 return mips_cpu_info_table
+ i
;
16756 /* Return a mips_cpu_info entry determined by an option valued
16759 static const struct mips_cpu_info
*
16760 mips_cpu_info_from_opt (int opt
)
16764 case MIPS_ARCH_OPTION_FROM_ABI
:
16765 /* 'from-abi' selects the most compatible architecture for the
16766 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16767 ABIs. For the EABIs, we have to decide whether we're using
16768 the 32-bit or 64-bit version. */
16769 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
16770 : ABI_NEEDS_64BIT_REGS
? 3
16771 : (TARGET_64BIT
? 3 : 1));
16773 case MIPS_ARCH_OPTION_NATIVE
:
16774 gcc_unreachable ();
16777 return &mips_cpu_info_table
[opt
];
16781 /* Return a default mips_cpu_info entry, given that no -march= option
16782 was explicitly specified. */
16784 static const struct mips_cpu_info
*
16785 mips_default_arch (void)
16787 #if defined (MIPS_CPU_STRING_DEFAULT)
16789 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16790 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
16791 return mips_cpu_info_table
+ i
;
16792 gcc_unreachable ();
16793 #elif defined (MIPS_ISA_DEFAULT)
16794 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
16796 /* 'from-abi' makes a good default: you get whatever the ABI
16798 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
16802 /* Set up globals to generate code for the ISA or processor
16803 described by INFO. */
16806 mips_set_architecture (const struct mips_cpu_info
*info
)
16810 mips_arch_info
= info
;
16811 mips_arch
= info
->cpu
;
16812 mips_isa
= info
->isa
;
16816 /* Likewise for tuning. */
16819 mips_set_tune (const struct mips_cpu_info
*info
)
16823 mips_tune_info
= info
;
16824 mips_tune
= info
->cpu
;
16828 /* Implement TARGET_OPTION_OVERRIDE. */
16831 mips_option_override (void)
16833 int i
, start
, regno
, mode
;
16835 if (global_options_set
.x_mips_isa_option
)
16836 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
16838 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16839 SUBTARGET_OVERRIDE_OPTIONS
;
16842 /* MIPS16 and microMIPS cannot coexist. */
16843 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
16844 error ("unsupported combination: %s", "-mips16 -mmicromips");
16846 /* Save the base compression state and process flags as though we
16847 were generating uncompressed code. */
16848 mips_base_compression_flags
= TARGET_COMPRESSION
;
16849 target_flags
&= ~TARGET_COMPRESSION
;
16851 /* -mno-float overrides -mhard-float and -msoft-float. */
16852 if (TARGET_NO_FLOAT
)
16854 target_flags
|= MASK_SOFT_FLOAT_ABI
;
16855 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
16858 if (TARGET_FLIP_MIPS16
)
16859 TARGET_INTERLINK_COMPRESSED
= 1;
16861 /* Set the small data limit. */
16862 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
16864 : MIPS_DEFAULT_GVALUE
);
16866 /* The following code determines the architecture and register size.
16867 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16868 The GAS and GCC code should be kept in sync as much as possible. */
16870 if (global_options_set
.x_mips_arch_option
)
16871 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
16873 if (mips_isa_option_info
!= 0)
16875 if (mips_arch_info
== 0)
16876 mips_set_architecture (mips_isa_option_info
);
16877 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
16878 error ("%<-%s%> conflicts with the other architecture options, "
16879 "which specify a %s processor",
16880 mips_isa_option_info
->name
,
16881 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
16884 if (mips_arch_info
== 0)
16885 mips_set_architecture (mips_default_arch ());
16887 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
16888 error ("%<-march=%s%> is not compatible with the selected ABI",
16889 mips_arch_info
->name
);
16891 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16892 if (global_options_set
.x_mips_tune_option
)
16893 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
16895 if (mips_tune_info
== 0)
16896 mips_set_tune (mips_arch_info
);
16898 if ((target_flags_explicit
& MASK_64BIT
) != 0)
16900 /* The user specified the size of the integer registers. Make sure
16901 it agrees with the ABI and ISA. */
16902 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
16903 error ("%<-mgp64%> used with a 32-bit processor");
16904 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
16905 error ("%<-mgp32%> used with a 64-bit ABI");
16906 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
16907 error ("%<-mgp64%> used with a 32-bit ABI");
16911 /* Infer the integer register size from the ABI and processor.
16912 Restrict ourselves to 32-bit registers if that's all the
16913 processor has, or if the ABI cannot handle 64-bit registers. */
16914 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
16915 target_flags
&= ~MASK_64BIT
;
16917 target_flags
|= MASK_64BIT
;
16920 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
16922 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
16923 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16924 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
16925 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16926 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
16928 if (!ISA_HAS_MXHC1
)
16929 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16930 " the target supports the mfhc1 and mthc1 instructions");
16931 else if (mips_abi
!= ABI_32
)
16932 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16938 /* -msingle-float selects 32-bit float registers. Otherwise the
16939 float registers should be the same size as the integer ones. */
16940 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
16941 target_flags
|= MASK_FLOAT64
;
16943 target_flags
&= ~MASK_FLOAT64
;
16946 /* End of code shared with GAS. */
16948 /* The R5900 FPU only supports single precision. */
16949 if (TARGET_MIPS5900
&& TARGET_HARD_FLOAT_ABI
&& TARGET_DOUBLE_FLOAT
)
16950 error ("unsupported combination: %s",
16951 "-march=r5900 -mhard-float -mdouble-float");
16953 /* If a -mlong* option was given, check that it matches the ABI,
16954 otherwise infer the -mlong* setting from the other options. */
16955 if ((target_flags_explicit
& MASK_LONG64
) != 0)
16959 if (mips_abi
== ABI_N32
)
16960 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16961 else if (mips_abi
== ABI_32
)
16962 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16963 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
16964 /* We have traditionally allowed non-abicalls code to use
16965 an LP64 form of o64. However, it would take a bit more
16966 effort to support the combination of 32-bit GOT entries
16967 and 64-bit pointers, so we treat the abicalls case as
16969 error ("the combination of %qs and %qs is incompatible with %qs",
16970 "-mabi=o64", "-mabicalls", "-mlong64");
16974 if (mips_abi
== ABI_64
)
16975 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16980 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
16981 target_flags
|= MASK_LONG64
;
16983 target_flags
&= ~MASK_LONG64
;
16986 if (!TARGET_OLDABI
)
16987 flag_pcc_struct_return
= 0;
16989 /* Decide which rtx_costs structure to use. */
16991 mips_cost
= &mips_rtx_cost_optimize_size
;
16993 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
16995 /* If the user hasn't specified a branch cost, use the processor's
16997 if (mips_branch_cost
== 0)
16998 mips_branch_cost
= mips_cost
->branch_cost
;
17000 /* If neither -mbranch-likely nor -mno-branch-likely was given
17001 on the command line, set MASK_BRANCHLIKELY based on the target
17002 architecture and tuning flags. Annulled delay slots are a
17003 size win, so we only consider the processor-specific tuning
17004 for !optimize_size. */
17005 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
17007 if (ISA_HAS_BRANCHLIKELY
17009 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
17010 target_flags
|= MASK_BRANCHLIKELY
;
17012 target_flags
&= ~MASK_BRANCHLIKELY
;
17014 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
17015 warning (0, "the %qs architecture does not support branch-likely"
17016 " instructions", mips_arch_info
->name
);
17018 /* If the user hasn't specified -mimadd or -mno-imadd set
17019 MASK_IMADD based on the target architecture and tuning
17021 if ((target_flags_explicit
& MASK_IMADD
) == 0)
17023 if (ISA_HAS_MADD_MSUB
&&
17024 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
17025 target_flags
|= MASK_IMADD
;
17027 target_flags
&= ~MASK_IMADD
;
17029 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
17030 warning (0, "the %qs architecture does not support madd or msub"
17031 " instructions", mips_arch_info
->name
);
17033 /* The effect of -mabicalls isn't defined for the EABI. */
17034 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
17036 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
17037 target_flags
&= ~MASK_ABICALLS
;
17040 /* PIC requires -mabicalls. */
17043 if (mips_abi
== ABI_EABI
)
17044 error ("cannot generate position-independent code for %qs",
17046 else if (!TARGET_ABICALLS
)
17047 error ("position-independent code requires %qs", "-mabicalls");
17050 if (TARGET_ABICALLS_PIC2
)
17051 /* We need to set flag_pic for executables as well as DSOs
17052 because we may reference symbols that are not defined in
17053 the final executable. (MIPS does not use things like
17054 copy relocs, for example.)
17056 There is a body of code that uses __PIC__ to distinguish
17057 between -mabicalls and -mno-abicalls code. The non-__PIC__
17058 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
17059 long as any indirect jumps use $25. */
17062 /* -mvr4130-align is a "speed over size" optimization: it usually produces
17063 faster code, but at the expense of more nops. Enable it at -O3 and
17065 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
17066 target_flags
|= MASK_VR4130_ALIGN
;
17068 /* Prefer a call to memcpy over inline code when optimizing for size,
17069 though see MOVE_RATIO in mips.h. */
17070 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
17071 target_flags
|= MASK_MEMCPY
;
17073 /* If we have a nonzero small-data limit, check that the -mgpopt
17074 setting is consistent with the other target flags. */
17075 if (mips_small_data_threshold
> 0)
17079 if (!TARGET_EXPLICIT_RELOCS
)
17080 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17082 TARGET_LOCAL_SDATA
= false;
17083 TARGET_EXTERN_SDATA
= false;
17087 if (TARGET_VXWORKS_RTP
)
17088 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17090 if (TARGET_ABICALLS
)
17091 warning (0, "cannot use small-data accesses for %qs",
17096 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17097 for all its floating point. */
17098 if (mips_nan
!= MIPS_IEEE_754_2008
)
17100 REAL_MODE_FORMAT (SFmode
) = &mips_single_format
;
17101 REAL_MODE_FORMAT (DFmode
) = &mips_double_format
;
17102 REAL_MODE_FORMAT (TFmode
) = &mips_quad_format
;
17105 /* Make sure that the user didn't turn off paired single support when
17106 MIPS-3D support is requested. */
17108 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
17109 && !TARGET_PAIRED_SINGLE_FLOAT
)
17110 error ("%<-mips3d%> requires %<-mpaired-single%>");
17112 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17114 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
17116 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17117 and TARGET_HARD_FLOAT_ABI are both true. */
17118 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
17119 error ("%qs must be used with %qs",
17120 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
17121 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
17123 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
17125 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
17126 warning (0, "the %qs architecture does not support paired-single"
17127 " instructions", mips_arch_info
->name
);
17129 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
17130 && !TARGET_CACHE_BUILTIN
)
17132 error ("%qs requires a target that provides the %qs instruction",
17133 "-mr10k-cache-barrier", "cache");
17134 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
17137 /* If TARGET_DSPR2, enable TARGET_DSP. */
17141 /* .eh_frame addresses should be the same width as a C pointer.
17142 Most MIPS ABIs support only one pointer size, so the assembler
17143 will usually know exactly how big an .eh_frame address is.
17145 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17146 originally defined to use 64-bit pointers (i.e. it is LP64), and
17147 this is still the default mode. However, we also support an n32-like
17148 ILP32 mode, which is selected by -mlong32. The problem is that the
17149 assembler has traditionally not had an -mlong option, so it has
17150 traditionally not known whether we're using the ILP32 or LP64 form.
17152 As it happens, gas versions up to and including 2.19 use _32-bit_
17153 addresses for EABI64 .cfi_* directives. This is wrong for the
17154 default LP64 mode, so we can't use the directives by default.
17155 Moreover, since gas's current behavior is at odds with gcc's
17156 default behavior, it seems unwise to rely on future versions
17157 of gas behaving the same way. We therefore avoid using .cfi
17158 directives for -mlong32 as well. */
17159 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
17160 flag_dwarf2_cfi_asm
= 0;
17162 /* .cfi_* directives generate a read-only section, so fall back on
17163 manual .eh_frame creation if we need the section to be writable. */
17164 if (TARGET_WRITABLE_EH_FRAME
)
17165 flag_dwarf2_cfi_asm
= 0;
17167 mips_init_print_operand_punct ();
17169 /* Set up array to map GCC register number to debug register number.
17170 Ignore the special purpose register numbers. */
17172 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17174 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
17175 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
17176 mips_dwarf_regno
[i
] = i
;
17178 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
17181 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
17182 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
17183 mips_dbx_regno
[i
] = i
+ start
;
17185 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
17186 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
17187 mips_dbx_regno
[i
] = i
+ start
;
17189 /* Accumulator debug registers use big-endian ordering. */
17190 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
17191 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
17192 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
17193 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
17194 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
17196 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
17197 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
17200 /* Set up mips_hard_regno_mode_ok. */
17201 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
17202 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
17203 mips_hard_regno_mode_ok
[mode
][regno
]
17204 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
17206 /* Function to allocate machine-dependent function status. */
17207 init_machine_status
= &mips_init_machine_status
;
17209 /* Default to working around R4000 errata only if the processor
17210 was selected explicitly. */
17211 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
17212 && strcmp (mips_arch_info
->name
, "r4000") == 0)
17213 target_flags
|= MASK_FIX_R4000
;
17215 /* Default to working around R4400 errata only if the processor
17216 was selected explicitly. */
17217 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
17218 && strcmp (mips_arch_info
->name
, "r4400") == 0)
17219 target_flags
|= MASK_FIX_R4400
;
17221 /* Default to working around R10000 errata only if the processor
17222 was selected explicitly. */
17223 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
17224 && strcmp (mips_arch_info
->name
, "r10000") == 0)
17225 target_flags
|= MASK_FIX_R10000
;
17227 /* Make sure that branch-likely instructions available when using
17228 -mfix-r10000. The instructions are not available if either:
17230 1. -mno-branch-likely was passed.
17231 2. The selected ISA does not support branch-likely and
17232 the command line does not include -mbranch-likely. */
17233 if (TARGET_FIX_R10000
17234 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
17235 ? !ISA_HAS_BRANCHLIKELY
17236 : !TARGET_BRANCHLIKELY
))
17237 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17239 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
17241 warning (0, "the %qs architecture does not support the synci "
17242 "instruction", mips_arch_info
->name
);
17243 target_flags
&= ~MASK_SYNCI
;
17246 /* Only optimize PIC indirect calls if they are actually required. */
17247 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
17248 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17250 /* Save base state of options. */
17251 mips_base_target_flags
= target_flags
;
17252 mips_base_schedule_insns
= flag_schedule_insns
;
17253 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
17254 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
17255 mips_base_align_loops
= align_loops
;
17256 mips_base_align_jumps
= align_jumps
;
17257 mips_base_align_functions
= align_functions
;
17259 /* Now select the ISA mode.
17261 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17262 later if required. */
17263 mips_set_compression_mode (0);
17265 /* We register a second machine specific reorg pass after delay slot
17266 filling. Registering the pass must be done at start up. It's
17267 convenient to do it here. */
17268 opt_pass
*new_pass
= make_pass_mips_machine_reorg2 (g
);
17269 struct register_pass_info insert_pass_mips_machine_reorg2
=
17271 new_pass
, /* pass */
17272 "dbr", /* reference_pass_name */
17273 1, /* ref_pass_instance_number */
17274 PASS_POS_INSERT_AFTER
/* po_op */
17276 register_pass (&insert_pass_mips_machine_reorg2
);
17278 if (TARGET_HARD_FLOAT_ABI
&& TARGET_MIPS5900
)
17279 REAL_MODE_FORMAT (SFmode
) = &spu_single_format
;
17282 /* Swap the register information for registers I and I + 1, which
17283 currently have the wrong endianness. Note that the registers'
17284 fixedness and call-clobberedness might have been set on the
17288 mips_swap_registers (unsigned int i
)
17293 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17294 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17296 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
17297 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
17298 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
17299 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
17305 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17308 mips_conditional_register_usage (void)
17313 /* These DSP control register fields are global. */
17314 global_regs
[CCDSP_PO_REGNUM
] = 1;
17315 global_regs
[CCDSP_SC_REGNUM
] = 1;
17318 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17319 reg_class_contents
[(int) DSP_ACC_REGS
]);
17321 if (!TARGET_HARD_FLOAT
)
17323 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17324 reg_class_contents
[(int) FP_REGS
]);
17325 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17326 reg_class_contents
[(int) ST_REGS
]);
17328 else if (!ISA_HAS_8CC
)
17330 /* We only have a single condition-code register. We implement
17331 this by fixing all the condition-code registers and generating
17332 RTL that refers directly to ST_REG_FIRST. */
17333 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17334 reg_class_contents
[(int) ST_REGS
]);
17335 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
17336 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
17340 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17341 are call-saved, and saving them via a MIPS16 register would
17342 probably waste more time than just reloading the value.
17344 We permit the $t temporary registers when optimizing for speed
17345 but not when optimizing for space because using them results in
17346 code that is larger (but faster) then not using them. We do
17347 allow $24 (t8) because it is used in CMP and CMPI instructions
17348 and $25 (t9) because it is used as the function call address in
17351 fixed_regs
[18] = call_used_regs
[18] = 1;
17352 fixed_regs
[19] = call_used_regs
[19] = 1;
17353 fixed_regs
[20] = call_used_regs
[20] = 1;
17354 fixed_regs
[21] = call_used_regs
[21] = 1;
17355 fixed_regs
[22] = call_used_regs
[22] = 1;
17356 fixed_regs
[23] = call_used_regs
[23] = 1;
17357 fixed_regs
[26] = call_used_regs
[26] = 1;
17358 fixed_regs
[27] = call_used_regs
[27] = 1;
17359 fixed_regs
[30] = call_used_regs
[30] = 1;
17362 fixed_regs
[8] = call_used_regs
[8] = 1;
17363 fixed_regs
[9] = call_used_regs
[9] = 1;
17364 fixed_regs
[10] = call_used_regs
[10] = 1;
17365 fixed_regs
[11] = call_used_regs
[11] = 1;
17366 fixed_regs
[12] = call_used_regs
[12] = 1;
17367 fixed_regs
[13] = call_used_regs
[13] = 1;
17368 fixed_regs
[14] = call_used_regs
[14] = 1;
17369 fixed_regs
[15] = call_used_regs
[15] = 1;
17372 /* Do not allow HI and LO to be treated as register operands.
17373 There are no MTHI or MTLO instructions (or any real need
17374 for them) and one-way registers cannot easily be reloaded. */
17375 AND_COMPL_HARD_REG_SET (operand_reg_set
,
17376 reg_class_contents
[(int) MD_REGS
]);
17378 /* $f20-$f23 are call-clobbered for n64. */
17379 if (mips_abi
== ABI_64
)
17382 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
17383 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17385 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17387 if (mips_abi
== ABI_N32
)
17390 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
17391 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17393 /* Make sure that double-register accumulator values are correctly
17394 ordered for the current endianness. */
17395 if (TARGET_LITTLE_ENDIAN
)
17397 unsigned int regno
;
17399 mips_swap_registers (MD_REG_FIRST
);
17400 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
17401 mips_swap_registers (regno
);
17405 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
17406 other registers for instructions for which it is possible. This
17407 encourages the compiler to use CMP in cases where an XOR would
17408 require some register shuffling. */
17411 mips_order_regs_for_local_alloc (void)
17415 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17416 reg_alloc_order
[i
] = i
;
17420 /* It really doesn't matter where we put register 0, since it is
17421 a fixed register anyhow. */
17422 reg_alloc_order
[0] = 24;
17423 reg_alloc_order
[24] = 0;
17427 /* Implement EH_USES. */
17430 mips_eh_uses (unsigned int regno
)
17432 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
17434 /* We need to force certain registers to be live in order to handle
17435 PIC long branches correctly. See mips_must_initialize_gp_p for
17437 if (mips_cfun_has_cprestore_slot_p ())
17439 if (regno
== CPRESTORE_SLOT_REGNUM
)
17444 if (cfun
->machine
->global_pointer
== regno
)
17452 /* Implement EPILOGUE_USES. */
17455 mips_epilogue_uses (unsigned int regno
)
17457 /* Say that the epilogue uses the return address register. Note that
17458 in the case of sibcalls, the values "used by the epilogue" are
17459 considered live at the start of the called function. */
17460 if (regno
== RETURN_ADDR_REGNUM
)
17463 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17464 See the comment above load_call<mode> for details. */
17465 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
17468 /* An interrupt handler must preserve some registers that are
17469 ordinarily call-clobbered. */
17470 if (cfun
->machine
->interrupt_handler_p
17471 && mips_interrupt_extra_call_saved_reg_p (regno
))
17477 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17480 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
17482 return REG_P (*x
) && REGNO (*x
) == AT_REGNUM
;
17485 /* Return true if INSN needs to be wrapped in ".set noat".
17486 INSN has NOPERANDS operands, stored in OPVEC. */
17489 mips_need_noat_wrapper_p (rtx insn
, rtx
*opvec
, int noperands
)
17493 if (recog_memoized (insn
) >= 0)
17494 for (i
= 0; i
< noperands
; i
++)
17495 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
17500 /* Implement FINAL_PRESCAN_INSN. */
17503 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
17505 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17506 mips_push_asm_switch (&mips_noat
);
17509 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17512 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx insn
,
17513 rtx
*opvec
, int noperands
)
17515 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17516 mips_pop_asm_switch (&mips_noat
);
17519 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17520 EXT_CODE is the code of the extension used. Return NULL if widening
17521 multiplication shouldn't be used. */
17524 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
17528 signed_p
= ext_code
== SIGN_EXTEND
;
17531 /* Don't use widening multiplication with MULT when we have DMUL. Even
17532 with the extension of its input operands DMUL is faster. Note that
17533 the extension is not needed for signed multiplication. In order to
17534 ensure that we always remove the redundant sign-extension in this
17535 case we still expand mulsidi3 for DMUL. */
17537 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
17540 ? gen_mulsidi3_64bit_mips16
17541 : gen_umulsidi3_64bit_mips16
);
17542 if (TARGET_FIX_R4000
)
17544 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
17550 ? gen_mulsidi3_32bit_mips16
17551 : gen_umulsidi3_32bit_mips16
);
17552 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
17553 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
17554 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
17558 /* Return true if PATTERN matches the kind of instruction generated by
17559 umips_build_save_restore. SAVE_P is true for store. */
17562 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
17566 HOST_WIDE_INT first_offset
= 0;
17567 rtx first_base
= 0;
17568 unsigned int regmask
= 0;
17570 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
17572 rtx set
, reg
, mem
, this_base
;
17573 HOST_WIDE_INT this_offset
;
17575 /* Check that we have a SET. */
17576 set
= XVECEXP (pattern
, 0, n
);
17577 if (GET_CODE (set
) != SET
)
17580 /* Check that the SET is a load (if restoring) or a store
17582 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17583 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
17586 /* Check that the address is the sum of base and a possibly-zero
17587 constant offset. Determine if the offset is in range. */
17588 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
17589 if (!REG_P (this_base
))
17594 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
17596 first_base
= this_base
;
17597 first_offset
= this_offset
;
17601 /* Check that the save slots are consecutive. */
17602 if (REGNO (this_base
) != REGNO (first_base
)
17603 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
17607 /* Check that SET's other operand is a register. */
17608 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
17612 regmask
|= 1 << REGNO (reg
);
17615 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
17616 if (regmask
== umips_swm_mask
[i
])
17622 /* Return the assembly instruction for microMIPS LWM or SWM.
17623 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17626 umips_output_save_restore (bool save_p
, rtx pattern
)
17628 static char buffer
[300];
17631 HOST_WIDE_INT offset
;
17632 rtx base
, mem
, set
, last_set
, last_reg
;
17634 /* Parse the pattern. */
17635 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
17637 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
17639 n
= XVECLEN (pattern
, 0);
17641 set
= XVECEXP (pattern
, 0, 0);
17642 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17643 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
17645 last_set
= XVECEXP (pattern
, 0, n
- 1);
17646 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
17648 if (REGNO (last_reg
) == 31)
17651 gcc_assert (n
<= 9);
17655 s
+= sprintf (s
, "%s,", reg_names
[16]);
17657 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
17659 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
17662 if (REGNO (last_reg
) == 31)
17663 s
+= sprintf (s
, "%s,", reg_names
[31]);
17665 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
17669 /* Return true if MEM1 and MEM2 use the same base register, and the
17670 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17671 register into (from) which the contents of MEM1 will be loaded
17672 (stored), depending on the value of LOAD_P.
17673 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17676 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
17677 rtx first_reg
, rtx mem1
, rtx mem2
)
17680 HOST_WIDE_INT offset1
, offset2
;
17682 if (!MEM_P (mem1
) || !MEM_P (mem2
))
17685 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
17686 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
17688 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
17691 /* Avoid invalid load pair instructions. */
17692 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
17695 /* We must avoid this case for anti-dependence.
17698 first_reg is $2, but the base is $3. */
17701 && REGNO (first_reg
) + 1 == REGNO (base1
))
17704 if (offset2
!= offset1
+ 4)
17707 if (!UMIPS_12BIT_OFFSET_P (offset1
))
17713 /* OPERANDS describes the operands to a pair of SETs, in the order
17714 dest1, src1, dest2, src2. Return true if the operands can be used
17715 in an LWP or SWP instruction; LOAD_P says which. */
17718 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
17720 rtx reg1
, reg2
, mem1
, mem2
;
17724 reg1
= operands
[0];
17725 reg2
= operands
[2];
17726 mem1
= operands
[1];
17727 mem2
= operands
[3];
17731 reg1
= operands
[1];
17732 reg2
= operands
[3];
17733 mem1
= operands
[0];
17734 mem2
= operands
[2];
17737 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17738 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
17740 if (REGNO (reg1
) == REGNO (reg2
) + 1)
17741 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
17746 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17747 the first register is REG and the first memory slot is MEM.
17748 LOAD_P is true for LWP. */
17751 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
17753 rtx ops
[] = {reg
, mem
};
17756 output_asm_insn ("lwp\t%0,%1", ops
);
17758 output_asm_insn ("swp\t%0,%1", ops
);
17761 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17762 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17765 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
17767 rtx reg1
, reg2
, mem1
, mem2
;
17770 reg1
= operands
[0];
17771 reg2
= operands
[2];
17772 mem1
= operands
[1];
17773 mem2
= operands
[3];
17777 reg1
= operands
[1];
17778 reg2
= operands
[3];
17779 mem1
= operands
[0];
17780 mem2
= operands
[2];
17783 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17785 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
17789 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
17790 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
17793 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17796 umips_movep_target_p (rtx reg1
, rtx reg2
)
17798 int regno1
, regno2
, pair
;
17800 static const int match
[8] = {
17801 0x00000060, /* 5, 6 */
17802 0x000000a0, /* 5, 7 */
17803 0x000000c0, /* 6, 7 */
17804 0x00200010, /* 4, 21 */
17805 0x00400010, /* 4, 22 */
17806 0x00000030, /* 4, 5 */
17807 0x00000050, /* 4, 6 */
17808 0x00000090 /* 4, 7 */
17811 if (!REG_P (reg1
) || !REG_P (reg2
))
17814 regno1
= REGNO (reg1
);
17815 regno2
= REGNO (reg2
);
17817 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
17820 pair
= (1 << regno1
) | (1 << regno2
);
17822 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
17823 if (pair
== match
[i
])
17829 /* Return the size in bytes of the trampoline code, padded to
17830 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17831 function address immediately follow. */
17834 mips_trampoline_code_size (void)
17836 if (TARGET_USE_PIC_FN_ADDR_REG
)
17838 else if (ptr_mode
== DImode
)
17840 else if (ISA_HAS_LOAD_DELAY
)
17846 /* Implement TARGET_TRAMPOLINE_INIT. */
17849 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
17851 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
17854 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
17856 /* Work out the offsets of the pointers from the start of the
17857 trampoline code. */
17858 end_addr_offset
= mips_trampoline_code_size ();
17859 static_chain_offset
= end_addr_offset
;
17860 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
17862 /* Get pointers to the beginning and end of the code block. */
17863 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
17864 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
17866 #define OP(X) gen_int_mode (X, SImode)
17868 /* Build up the code in TRAMPOLINE. */
17870 if (TARGET_USE_PIC_FN_ADDR_REG
)
17872 /* $25 contains the address of the trampoline. Emit code of the form:
17874 l[wd] $1, target_function_offset($25)
17875 l[wd] $static_chain, static_chain_offset($25)
17878 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
17879 target_function_offset
,
17880 PIC_FUNCTION_ADDR_REGNUM
));
17881 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17882 static_chain_offset
,
17883 PIC_FUNCTION_ADDR_REGNUM
));
17884 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
17885 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
17887 else if (ptr_mode
== DImode
)
17889 /* It's too cumbersome to create the full 64-bit address, so let's
17895 1: l[wd] $25, target_function_offset - 12($31)
17896 l[wd] $static_chain, static_chain_offset - 12($31)
17900 where 12 is the offset of "1:" from the start of the code block. */
17901 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
17902 trampoline
[i
++] = OP (MIPS_BAL (1));
17903 trampoline
[i
++] = OP (MIPS_NOP
);
17904 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
17905 target_function_offset
- 12,
17906 RETURN_ADDR_REGNUM
));
17907 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17908 static_chain_offset
- 12,
17909 RETURN_ADDR_REGNUM
));
17910 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17911 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
17915 /* If the target has load delays, emit:
17917 lui $1, %hi(end_addr)
17918 lw $25, %lo(end_addr + ...)($1)
17919 lw $static_chain, %lo(end_addr + ...)($1)
17925 lui $1, %hi(end_addr)
17926 lw $25, %lo(end_addr + ...)($1)
17928 lw $static_chain, %lo(end_addr + ...)($1). */
17930 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
17931 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
17932 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
17933 NULL
, false, OPTAB_WIDEN
);
17934 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
17935 NULL
, false, OPTAB_WIDEN
);
17936 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
17938 /* Emit the LUI. */
17939 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
17940 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
17941 NULL
, false, OPTAB_WIDEN
);
17943 /* Emit the load of the target function. */
17944 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
17945 target_function_offset
- end_addr_offset
,
17947 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
17948 NULL
, false, OPTAB_WIDEN
);
17950 /* Emit the JR here, if we can. */
17951 if (!ISA_HAS_LOAD_DELAY
)
17952 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17954 /* Emit the load of the static chain register. */
17955 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17956 static_chain_offset
- end_addr_offset
,
17958 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
17959 NULL
, false, OPTAB_WIDEN
);
17961 /* Emit the JR, if we couldn't above. */
17962 if (ISA_HAS_LOAD_DELAY
)
17964 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17965 trampoline
[i
++] = OP (MIPS_NOP
);
17971 /* Copy the trampoline code. Leave any padding uninitialized. */
17972 for (j
= 0; j
< i
; j
++)
17974 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
17975 mips_emit_move (mem
, trampoline
[j
]);
17978 /* Set up the static chain pointer field. */
17979 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
17980 mips_emit_move (mem
, chain_value
);
17982 /* Set up the target function field. */
17983 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
17984 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
17986 /* Flush the code part of the trampoline. */
17987 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
17988 emit_insn (gen_clear_cache (addr
, end_addr
));
17991 /* Implement FUNCTION_PROFILER. */
17993 void mips_function_profiler (FILE *file
)
17996 sorry ("mips16 function profiling");
17997 if (TARGET_LONG_CALLS
)
17999 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
18000 if (Pmode
== DImode
)
18001 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
18003 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
18005 mips_push_asm_switch (&mips_noat
);
18006 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
18007 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
18008 /* _mcount treats $2 as the static chain register. */
18009 if (cfun
->static_chain_decl
!= NULL
)
18010 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
18011 reg_names
[STATIC_CHAIN_REGNUM
]);
18012 if (TARGET_MCOUNT_RA_ADDRESS
)
18014 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
18015 ra save location. */
18016 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
18017 /* ra not saved, pass zero. */
18018 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
18020 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
18021 Pmode
== DImode
? "dla" : "la", reg_names
[12],
18022 cfun
->machine
->frame
.ra_fp_offset
,
18023 reg_names
[STACK_POINTER_REGNUM
]);
18025 if (!TARGET_NEWABI
)
18027 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
18028 TARGET_64BIT
? "dsubu" : "subu",
18029 reg_names
[STACK_POINTER_REGNUM
],
18030 reg_names
[STACK_POINTER_REGNUM
],
18031 Pmode
== DImode
? 16 : 8);
18033 if (TARGET_LONG_CALLS
)
18034 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
18036 fprintf (file
, "\tjal\t_mcount\n");
18037 mips_pop_asm_switch (&mips_noat
);
18038 /* _mcount treats $2 as the static chain register. */
18039 if (cfun
->static_chain_decl
!= NULL
)
18040 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
18044 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
18045 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
18046 when TARGET_LOONGSON_VECTORS is true. */
18048 static unsigned HOST_WIDE_INT
18049 mips_shift_truncation_mask (enum machine_mode mode
)
18051 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
18054 return GET_MODE_BITSIZE (mode
) - 1;
18057 /* Implement TARGET_PREPARE_PCH_SAVE. */
18060 mips_prepare_pch_save (void)
18062 /* We are called in a context where the current MIPS16 vs. non-MIPS16
18063 setting should be irrelevant. The question then is: which setting
18064 makes most sense at load time?
18066 The PCH is loaded before the first token is read. We should never
18067 have switched into MIPS16 mode by that point, and thus should not
18068 have populated mips16_globals. Nor can we load the entire contents
18069 of mips16_globals from the PCH file, because mips16_globals contains
18070 a combination of GGC and non-GGC data.
18072 There is therefore no point in trying save the GGC part of
18073 mips16_globals to the PCH file, or to preserve MIPS16ness across
18074 the PCH save and load. The loading compiler would not have access
18075 to the non-GGC parts of mips16_globals (either from the PCH file,
18076 or from a copy that the loading compiler generated itself) and would
18077 have to call target_reinit anyway.
18079 It therefore seems best to switch back to non-MIPS16 mode at
18080 save time, and to ensure that mips16_globals remains null after
18082 mips_set_compression_mode (0);
18083 mips16_globals
= 0;
18086 /* Generate or test for an insn that supports a constant permutation. */
18088 #define MAX_VECT_LEN 8
18090 struct expand_vec_perm_d
18092 rtx target
, op0
, op1
;
18093 unsigned char perm
[MAX_VECT_LEN
];
18094 enum machine_mode vmode
;
18095 unsigned char nelt
;
18100 /* Construct (set target (vec_select op0 (parallel perm))) and
18101 return true if that's a valid instruction in the active ISA. */
18104 mips_expand_vselect (rtx target
, rtx op0
,
18105 const unsigned char *perm
, unsigned nelt
)
18107 rtx rperm
[MAX_VECT_LEN
], x
;
18110 for (i
= 0; i
< nelt
; ++i
)
18111 rperm
[i
] = GEN_INT (perm
[i
]);
18113 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
18114 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
18115 x
= gen_rtx_SET (VOIDmode
, target
, x
);
18118 if (recog_memoized (x
) < 0)
18126 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18129 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
18130 const unsigned char *perm
, unsigned nelt
)
18132 enum machine_mode v2mode
;
18135 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
18136 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
18137 return mips_expand_vselect (target
, x
, perm
, nelt
);
18140 /* Recognize patterns for even-odd extraction. */
18143 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
18145 unsigned i
, odd
, nelt
= d
->nelt
;
18146 rtx t0
, t1
, t2
, t3
;
18148 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18150 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18157 for (i
= 1; i
< nelt
; ++i
)
18158 if (d
->perm
[i
] != i
* 2 + odd
)
18164 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18165 t0
= gen_reg_rtx (d
->vmode
);
18166 t1
= gen_reg_rtx (d
->vmode
);
18170 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
18171 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
18173 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
18175 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
18179 t2
= gen_reg_rtx (d
->vmode
);
18180 t3
= gen_reg_rtx (d
->vmode
);
18181 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
18182 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
18183 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
18184 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
18186 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
18188 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
18192 gcc_unreachable ();
18197 /* Recognize patterns for the Loongson PSHUFH instruction. */
18200 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
18205 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18207 if (d
->vmode
!= V4HImode
)
18212 /* Convert the selector into the packed 8-bit form for pshufh. */
18213 /* Recall that loongson is little-endian only. No big-endian
18214 adjustment required. */
18215 for (i
= mask
= 0; i
< 4; i
++)
18216 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
18217 rmask
= force_reg (SImode
, GEN_INT (mask
));
18219 if (d
->one_vector_p
)
18220 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
18223 rtx t0
, t1
, x
, merge
, rmerge
[4];
18225 t0
= gen_reg_rtx (V4HImode
);
18226 t1
= gen_reg_rtx (V4HImode
);
18227 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
18228 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
18230 for (i
= 0; i
< 4; ++i
)
18231 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
18232 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
18233 merge
= force_reg (V4HImode
, merge
);
18235 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
18236 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18238 x
= gen_rtx_NOT (V4HImode
, merge
);
18239 x
= gen_rtx_AND (V4HImode
, x
, t0
);
18240 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18242 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
18243 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
18249 /* Recognize broadcast patterns for the Loongson. */
18252 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
18257 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18259 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18260 if (d
->vmode
!= V8QImode
)
18262 if (!d
->one_vector_p
)
18266 for (i
= 1; i
< 8; ++i
)
18267 if (d
->perm
[i
] != elt
)
18273 /* With one interleave we put two of the desired element adjacent. */
18274 t0
= gen_reg_rtx (V8QImode
);
18276 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
18278 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
18280 /* Shuffle that one HImode element into all locations. */
18283 t1
= gen_reg_rtx (V4HImode
);
18284 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
18285 force_reg (SImode
, GEN_INT (elt
))));
18287 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
18292 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
18294 unsigned int i
, nelt
= d
->nelt
;
18295 unsigned char perm2
[MAX_VECT_LEN
];
18297 if (d
->one_vector_p
)
18299 /* Try interleave with alternating operands. */
18300 memcpy (perm2
, d
->perm
, sizeof(perm2
));
18301 for (i
= 1; i
< nelt
; i
+= 2)
18303 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
18308 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
18312 /* Try again with swapped operands. */
18313 for (i
= 0; i
< nelt
; ++i
)
18314 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
18315 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
18319 if (mips_expand_vpc_loongson_even_odd (d
))
18321 if (mips_expand_vpc_loongson_pshufh (d
))
18323 if (mips_expand_vpc_loongson_bcast (d
))
18328 /* Expand a vec_perm_const pattern. */
18331 mips_expand_vec_perm_const (rtx operands
[4])
18333 struct expand_vec_perm_d d
;
18334 int i
, nelt
, which
;
18335 unsigned char orig_perm
[MAX_VECT_LEN
];
18339 d
.target
= operands
[0];
18340 d
.op0
= operands
[1];
18341 d
.op1
= operands
[2];
18344 d
.vmode
= GET_MODE (d
.target
);
18345 gcc_assert (VECTOR_MODE_P (d
.vmode
));
18346 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18347 d
.testing_p
= false;
18349 for (i
= which
= 0; i
< nelt
; ++i
)
18351 rtx e
= XVECEXP (sel
, 0, i
);
18352 int ei
= INTVAL (e
) & (2 * nelt
- 1);
18353 which
|= (ei
< nelt
? 1 : 2);
18356 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18364 d
.one_vector_p
= false;
18365 if (!rtx_equal_p (d
.op0
, d
.op1
))
18370 for (i
= 0; i
< nelt
; ++i
)
18371 d
.perm
[i
] &= nelt
- 1;
18373 d
.one_vector_p
= true;
18378 d
.one_vector_p
= true;
18382 ok
= mips_expand_vec_perm_const_1 (&d
);
18384 /* If we were given a two-vector permutation which just happened to
18385 have both input vectors equal, we folded this into a one-vector
18386 permutation. There are several loongson patterns that are matched
18387 via direct vec_select+vec_concat expansion, but we do not have
18388 support in mips_expand_vec_perm_const_1 to guess the adjustment
18389 that should be made for a single operand. Just try again with
18390 the original permutation. */
18391 if (!ok
&& which
== 3)
18393 d
.op0
= operands
[1];
18394 d
.op1
= operands
[2];
18395 d
.one_vector_p
= false;
18396 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18397 ok
= mips_expand_vec_perm_const_1 (&d
);
18403 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18406 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
18407 const unsigned char *sel
)
18409 struct expand_vec_perm_d d
;
18410 unsigned int i
, nelt
, which
;
18414 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18415 d
.testing_p
= true;
18416 memcpy (d
.perm
, sel
, nelt
);
18418 /* Categorize the set of elements in the selector. */
18419 for (i
= which
= 0; i
< nelt
; ++i
)
18421 unsigned char e
= d
.perm
[i
];
18422 gcc_assert (e
< 2 * nelt
);
18423 which
|= (e
< nelt
? 1 : 2);
18426 /* For all elements from second vector, fold the elements to first. */
18428 for (i
= 0; i
< nelt
; ++i
)
18431 /* Check whether the mask can be applied to the vector type. */
18432 d
.one_vector_p
= (which
!= 3);
18434 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
18435 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
18436 if (!d
.one_vector_p
)
18437 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
18440 ret
= mips_expand_vec_perm_const_1 (&d
);
18446 /* Expand an integral vector unpack operation. */
18449 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
18451 enum machine_mode imode
= GET_MODE (operands
[1]);
18452 rtx (*unpack
) (rtx
, rtx
, rtx
);
18453 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
18454 rtx tmp
, dest
, zero
;
18460 unpack
= gen_loongson_punpckhbh
;
18462 unpack
= gen_loongson_punpcklbh
;
18463 cmpgt
= gen_loongson_pcmpgtb
;
18467 unpack
= gen_loongson_punpckhhw
;
18469 unpack
= gen_loongson_punpcklhw
;
18470 cmpgt
= gen_loongson_pcmpgth
;
18473 gcc_unreachable ();
18476 zero
= force_reg (imode
, CONST0_RTX (imode
));
18481 tmp
= gen_reg_rtx (imode
);
18482 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
18485 dest
= gen_reg_rtx (imode
);
18486 emit_insn (unpack (dest
, operands
[1], tmp
));
18488 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
18491 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18494 mips_constant_elt_p (rtx x
)
18496 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
18499 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18502 mips_expand_vi_broadcast (enum machine_mode vmode
, rtx target
, rtx elt
)
18504 struct expand_vec_perm_d d
;
18508 if (elt
!= const0_rtx
)
18509 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
18511 elt
= gen_lowpart (DImode
, elt
);
18513 t1
= gen_reg_rtx (vmode
);
18517 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
18520 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
18523 gcc_unreachable ();
18526 memset (&d
, 0, sizeof (d
));
18531 d
.nelt
= GET_MODE_NUNITS (vmode
);
18532 d
.one_vector_p
= true;
18534 ok
= mips_expand_vec_perm_const_1 (&d
);
18538 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18539 elements of VALS with zeros, copy the constant vector to TARGET. */
18542 mips_expand_vi_constant (enum machine_mode vmode
, unsigned nelt
,
18543 rtx target
, rtx vals
)
18545 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
18548 for (i
= 0; i
< nelt
; ++i
)
18550 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
18551 RTVEC_ELT (vec
, i
) = const0_rtx
;
18554 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
18558 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18561 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
18563 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
18565 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
18566 GEN_INT (one_var
)));
18569 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18572 mips_expand_vi_general (enum machine_mode vmode
, enum machine_mode imode
,
18573 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
18575 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
18576 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
18579 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
18581 for (i
= 0; i
< nelt
; ++i
)
18583 rtx x
= XVECEXP (vals
, 0, i
);
18584 if (!mips_constant_elt_p (x
))
18585 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
18588 emit_move_insn (target
, mem
);
18591 /* Expand a vector initialization. */
18594 mips_expand_vector_init (rtx target
, rtx vals
)
18596 enum machine_mode vmode
= GET_MODE (target
);
18597 enum machine_mode imode
= GET_MODE_INNER (vmode
);
18598 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
18599 unsigned nvar
= 0, one_var
= -1u;
18600 bool all_same
= true;
18603 for (i
= 0; i
< nelt
; ++i
)
18605 x
= XVECEXP (vals
, 0, i
);
18606 if (!mips_constant_elt_p (x
))
18607 nvar
++, one_var
= i
;
18608 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
18612 /* Load constants from the pool, or whatever's handy. */
18615 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
18619 /* For two-part initialization, always use CONCAT. */
18622 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
18623 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
18624 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
18625 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18629 /* Loongson is the only cpu with vectors with more elements. */
18630 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
18632 /* If all values are identical, broadcast the value. */
18635 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
18639 /* If we've only got one non-variable V4HImode, use PINSRH. */
18640 if (nvar
== 1 && vmode
== V4HImode
)
18642 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
18646 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
18649 /* Expand a vector reduction. */
18652 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
18654 enum machine_mode vmode
= GET_MODE (in
);
18655 unsigned char perm2
[2];
18656 rtx last
, next
, fold
, x
;
18660 fold
= gen_reg_rtx (vmode
);
18664 /* Use PUL/PLU to produce { L, H } op { H, L }.
18665 By reversing the pair order, rather than a pure interleave high,
18666 we avoid erroneous exceptional conditions that we might otherwise
18667 produce from the computation of H op H. */
18670 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
18675 /* Use interleave to produce { H, L } op { H, H }. */
18676 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
18680 /* Perform the first reduction with interleave,
18681 and subsequent reductions with shifts. */
18682 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
18684 next
= gen_reg_rtx (vmode
);
18685 emit_insn (gen (next
, last
, fold
));
18688 fold
= gen_reg_rtx (vmode
);
18689 x
= force_reg (SImode
, GEN_INT (16));
18690 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
18694 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
18696 next
= gen_reg_rtx (vmode
);
18697 emit_insn (gen (next
, last
, fold
));
18700 fold
= gen_reg_rtx (vmode
);
18701 x
= force_reg (SImode
, GEN_INT (16));
18702 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18704 next
= gen_reg_rtx (vmode
);
18705 emit_insn (gen (next
, last
, fold
));
18708 fold
= gen_reg_rtx (vmode
);
18709 x
= force_reg (SImode
, GEN_INT (8));
18710 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18714 gcc_unreachable ();
18717 emit_insn (gen (target
, last
, fold
));
18720 /* Expand a vector minimum/maximum. */
18723 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
18724 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
18726 enum machine_mode vmode
= GET_MODE (target
);
18729 tc
= gen_reg_rtx (vmode
);
18730 t0
= gen_reg_rtx (vmode
);
18731 t1
= gen_reg_rtx (vmode
);
18734 emit_insn (cmp (tc
, op0
, op1
));
18736 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
18737 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18739 x
= gen_rtx_NOT (vmode
, tc
);
18740 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
18741 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18743 x
= gen_rtx_IOR (vmode
, t0
, t1
);
18744 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18747 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
18750 mips_case_values_threshold (void)
18752 /* In MIPS16 mode using a larger case threshold generates smaller code. */
18753 if (TARGET_MIPS16
&& optimize_size
)
18756 return default_case_values_threshold ();
18759 /* Initialize the GCC target structure. */
18760 #undef TARGET_ASM_ALIGNED_HI_OP
18761 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18762 #undef TARGET_ASM_ALIGNED_SI_OP
18763 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18764 #undef TARGET_ASM_ALIGNED_DI_OP
18765 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18767 #undef TARGET_OPTION_OVERRIDE
18768 #define TARGET_OPTION_OVERRIDE mips_option_override
18770 #undef TARGET_LEGITIMIZE_ADDRESS
18771 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18773 #undef TARGET_ASM_FUNCTION_PROLOGUE
18774 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18775 #undef TARGET_ASM_FUNCTION_EPILOGUE
18776 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18777 #undef TARGET_ASM_SELECT_RTX_SECTION
18778 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18779 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18780 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18782 #undef TARGET_SCHED_INIT
18783 #define TARGET_SCHED_INIT mips_sched_init
18784 #undef TARGET_SCHED_REORDER
18785 #define TARGET_SCHED_REORDER mips_sched_reorder
18786 #undef TARGET_SCHED_REORDER2
18787 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18788 #undef TARGET_SCHED_VARIABLE_ISSUE
18789 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18790 #undef TARGET_SCHED_ADJUST_COST
18791 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18792 #undef TARGET_SCHED_ISSUE_RATE
18793 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18794 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18795 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18796 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18797 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18798 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18799 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18800 mips_multipass_dfa_lookahead
18801 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18802 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18803 mips_small_register_classes_for_mode_p
18805 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18806 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18808 #undef TARGET_INSERT_ATTRIBUTES
18809 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18810 #undef TARGET_MERGE_DECL_ATTRIBUTES
18811 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18812 #undef TARGET_CAN_INLINE_P
18813 #define TARGET_CAN_INLINE_P mips_can_inline_p
18814 #undef TARGET_SET_CURRENT_FUNCTION
18815 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18817 #undef TARGET_VALID_POINTER_MODE
18818 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18819 #undef TARGET_REGISTER_MOVE_COST
18820 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18821 #undef TARGET_MEMORY_MOVE_COST
18822 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18823 #undef TARGET_RTX_COSTS
18824 #define TARGET_RTX_COSTS mips_rtx_costs
18825 #undef TARGET_ADDRESS_COST
18826 #define TARGET_ADDRESS_COST mips_address_cost
18828 #undef TARGET_IN_SMALL_DATA_P
18829 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18831 #undef TARGET_MACHINE_DEPENDENT_REORG
18832 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18834 #undef TARGET_PREFERRED_RELOAD_CLASS
18835 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18837 #undef TARGET_EXPAND_TO_RTL_HOOK
18838 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18839 #undef TARGET_ASM_FILE_START
18840 #define TARGET_ASM_FILE_START mips_file_start
18841 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18842 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18843 #undef TARGET_ASM_CODE_END
18844 #define TARGET_ASM_CODE_END mips_code_end
18846 #undef TARGET_INIT_LIBFUNCS
18847 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18849 #undef TARGET_BUILD_BUILTIN_VA_LIST
18850 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18851 #undef TARGET_EXPAND_BUILTIN_VA_START
18852 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18853 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18854 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18856 #undef TARGET_PROMOTE_FUNCTION_MODE
18857 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
18858 #undef TARGET_PROMOTE_PROTOTYPES
18859 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18861 #undef TARGET_FUNCTION_VALUE
18862 #define TARGET_FUNCTION_VALUE mips_function_value
18863 #undef TARGET_LIBCALL_VALUE
18864 #define TARGET_LIBCALL_VALUE mips_libcall_value
18865 #undef TARGET_FUNCTION_VALUE_REGNO_P
18866 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
18867 #undef TARGET_RETURN_IN_MEMORY
18868 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
18869 #undef TARGET_RETURN_IN_MSB
18870 #define TARGET_RETURN_IN_MSB mips_return_in_msb
18872 #undef TARGET_ASM_OUTPUT_MI_THUNK
18873 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
18874 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
18875 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
18877 #undef TARGET_PRINT_OPERAND
18878 #define TARGET_PRINT_OPERAND mips_print_operand
18879 #undef TARGET_PRINT_OPERAND_ADDRESS
18880 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
18881 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
18882 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
18884 #undef TARGET_SETUP_INCOMING_VARARGS
18885 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
18886 #undef TARGET_STRICT_ARGUMENT_NAMING
18887 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
18888 #undef TARGET_MUST_PASS_IN_STACK
18889 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
18890 #undef TARGET_PASS_BY_REFERENCE
18891 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
18892 #undef TARGET_CALLEE_COPIES
18893 #define TARGET_CALLEE_COPIES mips_callee_copies
18894 #undef TARGET_ARG_PARTIAL_BYTES
18895 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
18896 #undef TARGET_FUNCTION_ARG
18897 #define TARGET_FUNCTION_ARG mips_function_arg
18898 #undef TARGET_FUNCTION_ARG_ADVANCE
18899 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
18900 #undef TARGET_FUNCTION_ARG_BOUNDARY
18901 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
18903 #undef TARGET_MODE_REP_EXTENDED
18904 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
18906 #undef TARGET_VECTOR_MODE_SUPPORTED_P
18907 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
18909 #undef TARGET_SCALAR_MODE_SUPPORTED_P
18910 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
18912 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
18913 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
18915 #undef TARGET_INIT_BUILTINS
18916 #define TARGET_INIT_BUILTINS mips_init_builtins
18917 #undef TARGET_BUILTIN_DECL
18918 #define TARGET_BUILTIN_DECL mips_builtin_decl
18919 #undef TARGET_EXPAND_BUILTIN
18920 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
18922 #undef TARGET_HAVE_TLS
18923 #define TARGET_HAVE_TLS HAVE_AS_TLS
18925 #undef TARGET_CANNOT_FORCE_CONST_MEM
18926 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
18928 #undef TARGET_LEGITIMATE_CONSTANT_P
18929 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
18931 #undef TARGET_ENCODE_SECTION_INFO
18932 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
18934 #undef TARGET_ATTRIBUTE_TABLE
18935 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
18936 /* All our function attributes are related to how out-of-line copies should
18937 be compiled or called. They don't in themselves prevent inlining. */
18938 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
18939 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
18941 #undef TARGET_EXTRA_LIVE_ON_ENTRY
18942 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
18944 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
18945 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
18946 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
18947 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
18949 #undef TARGET_COMP_TYPE_ATTRIBUTES
18950 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
18952 #ifdef HAVE_AS_DTPRELWORD
18953 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
18954 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
18956 #undef TARGET_DWARF_REGISTER_SPAN
18957 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
18959 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
18960 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
18962 #undef TARGET_LEGITIMATE_ADDRESS_P
18963 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
18965 #undef TARGET_FRAME_POINTER_REQUIRED
18966 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
18968 #undef TARGET_CAN_ELIMINATE
18969 #define TARGET_CAN_ELIMINATE mips_can_eliminate
18971 #undef TARGET_CONDITIONAL_REGISTER_USAGE
18972 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
18974 #undef TARGET_TRAMPOLINE_INIT
18975 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
18977 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
18978 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
18980 #undef TARGET_SHIFT_TRUNCATION_MASK
18981 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
18983 #undef TARGET_PREPARE_PCH_SAVE
18984 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
18986 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
18987 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
18989 #undef TARGET_CASE_VALUES_THRESHOLD
18990 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
18992 struct gcc_target targetm
= TARGET_INITIALIZER
;
18994 #include "gt-mips.h"