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(override_options): Set mips_split_addresses only if
[gcc.git] / gcc / config / mips / mips.c
1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-95, 1996 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
28
29 #include "config.h"
30 #include "rtl.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-flags.h"
37 #include "insn-attr.h"
38 #include "insn-codes.h"
39 #include "recog.h"
40 #include "output.h"
41
42 #undef MAX /* sys/param.h may also define these */
43 #undef MIN
44
45 #include <stdio.h>
46 #include <signal.h>
47 #include <sys/types.h>
48 #include <sys/file.h>
49 #include <ctype.h>
50 #include "tree.h"
51 #include "expr.h"
52 #include "flags.h"
53
54 #ifndef R_OK
55 #define R_OK 4
56 #define W_OK 2
57 #define X_OK 1
58 #endif
59
60 #if defined(USG) || defined(NO_STAB_H)
61 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
62 #else
63 #include <stab.h> /* On BSD, use the system's stab.h. */
64 #endif /* not USG */
65
66 #ifdef __GNU_STAB__
67 #define STAB_CODE_TYPE enum __stab_debug_code
68 #else
69 #define STAB_CODE_TYPE int
70 #endif
71
72 extern void abort ();
73 extern int atoi ();
74 extern char *getenv ();
75 extern char *mktemp ();
76
77 extern rtx adj_offsettable_operand ();
78 extern rtx copy_to_reg ();
79 extern void error ();
80 extern void fatal ();
81 extern tree lookup_name ();
82 extern void pfatal_with_name ();
83 extern void warning ();
84
85 extern FILE *asm_out_file;
86
87 /* Enumeration for all of the relational tests, so that we can build
88 arrays indexed by the test type, and not worry about the order
89 of EQ, NE, etc. */
90
91 enum internal_test {
92 ITEST_EQ,
93 ITEST_NE,
94 ITEST_GT,
95 ITEST_GE,
96 ITEST_LT,
97 ITEST_LE,
98 ITEST_GTU,
99 ITEST_GEU,
100 ITEST_LTU,
101 ITEST_LEU,
102 ITEST_MAX
103 };
104
105 /* Global variables for machine-dependent things. */
106
107 /* Threshold for data being put into the small data/bss area, instead
108 of the normal data area (references to the small data/bss area take
109 1 instruction, and use the global pointer, references to the normal
110 data area takes 2 instructions). */
111 int mips_section_threshold = -1;
112
113 /* Count the number of .file directives, so that .loc is up to date. */
114 int num_source_filenames = 0;
115
116 /* Count the number of sdb related labels are generated (to find block
117 start and end boundaries). */
118 int sdb_label_count = 0;
119
120 /* Next label # for each statement for Silicon Graphics IRIS systems. */
121 int sym_lineno = 0;
122
123 /* Non-zero if inside of a function, because the stupid MIPS asm can't
124 handle .files inside of functions. */
125 int inside_function = 0;
126
127 /* Files to separate the text and the data output, so that all of the data
128 can be emitted before the text, which will mean that the assembler will
129 generate smaller code, based on the global pointer. */
130 FILE *asm_out_data_file;
131 FILE *asm_out_text_file;
132
133 /* Linked list of all externals that are to be emitted when optimizing
134 for the global pointer if they haven't been declared by the end of
135 the program with an appropriate .comm or initialization. */
136
137 struct extern_list {
138 struct extern_list *next; /* next external */
139 char *name; /* name of the external */
140 int size; /* size in bytes */
141 } *extern_head = 0;
142
143 /* Name of the file containing the current function. */
144 char *current_function_file = "";
145
146 /* Warning given that Mips ECOFF can't support changing files
147 within a function. */
148 int file_in_function_warning = FALSE;
149
150 /* Whether to suppress issuing .loc's because the user attempted
151 to change the filename within a function. */
152 int ignore_line_number = FALSE;
153
154 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
155 int set_noreorder;
156 int set_noat;
157 int set_nomacro;
158 int set_volatile;
159
160 /* The next branch instruction is a branch likely, not branch normal. */
161 int mips_branch_likely;
162
163 /* Count of delay slots and how many are filled. */
164 int dslots_load_total;
165 int dslots_load_filled;
166 int dslots_jump_total;
167 int dslots_jump_filled;
168
169 /* # of nops needed by previous insn */
170 int dslots_number_nops;
171
172 /* Number of 1/2/3 word references to data items (ie, not jal's). */
173 int num_refs[3];
174
175 /* registers to check for load delay */
176 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
177
178 /* Cached operands, and operator to compare for use in set/branch on
179 condition codes. */
180 rtx branch_cmp[2];
181
182 /* what type of branch to use */
183 enum cmp_type branch_type;
184
185 /* Number of previously seen half-pic pointers and references. */
186 static int prev_half_pic_ptrs = 0;
187 static int prev_half_pic_refs = 0;
188
189 /* which cpu are we scheduling for */
190 enum processor_type mips_cpu;
191
192 /* which instruction set architecture to use. */
193 int mips_isa;
194
195 #ifdef MIPS_ABI_DEFAULT
196 /* which ABI to use. This is defined to a constant in mips.h if the target
197 doesn't support multiple ABIs. */
198 enum mips_abi_type mips_abi;
199 #endif
200
201 /* Strings to hold which cpu and instruction set architecture to use. */
202 char *mips_cpu_string; /* for -mcpu=<xxx> */
203 char *mips_isa_string; /* for -mips{1,2,3,4} */
204 char *mips_abi_string; /* for -mabi={o32,32,n32,n64,64,eabi} */
205
206 /* If TRUE, we split addresses into their high and low parts in the RTL. */
207 int mips_split_addresses;
208
209 /* Generating calls to position independent functions? */
210 enum mips_abicalls_type mips_abicalls;
211
212 /* High and low marks for floating point values which we will accept
213 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
214 initialized in override_options. */
215 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
216
217 /* Array giving truth value on whether or not a given hard register
218 can support a given mode. */
219 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
220
221 /* Current frame information calculated by compute_frame_size. */
222 struct mips_frame_info current_frame_info;
223
224 /* Zero structure to initialize current_frame_info. */
225 struct mips_frame_info zero_frame_info;
226
227 /* Temporary filename used to buffer .text until end of program
228 for -mgpopt. */
229 static char *temp_filename;
230
231 /* Pseudo-reg holding the address of the current function when
232 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
233 by mips_finalize_pic if it was created. */
234 rtx embedded_pic_fnaddr_rtx;
235
236 /* List of all MIPS punctuation characters used by print_operand. */
237 char mips_print_operand_punct[256];
238
239 /* Map GCC register number to debugger register number. */
240 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
241
242 /* Buffer to use to enclose a load/store operation with %{ %} to
243 turn on .set volatile. */
244 static char volatile_buffer[60];
245
246 /* Hardware names for the registers. If -mrnames is used, this
247 will be overwritten with mips_sw_reg_names. */
248
249 char mips_reg_names[][8] =
250 {
251 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
252 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
253 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
254 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
255 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
256 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
257 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
258 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
259 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
260 "$fcc5","$fcc6","$fcc7","$rap"
261 };
262
263 /* Mips software names for the registers, used to overwrite the
264 mips_reg_names array. */
265
266 char mips_sw_reg_names[][8] =
267 {
268 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
269 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
270 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
271 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
272 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
273 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
274 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
275 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
276 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
277 "$fcc5","$fcc6","$fcc7","$rap"
278 };
279
280 /* Map hard register number to register class */
281 enum reg_class mips_regno_to_class[] =
282 {
283 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
284 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
285 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
286 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
287 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
288 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
289 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
290 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
291 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
292 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
293 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
294 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
295 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
296 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
297 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
298 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
299 HI_REG, LO_REG, HILO_REG, ST_REGS,
300 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
301 ST_REGS, ST_REGS, ST_REGS, GR_REGS
302 };
303
304 /* Map register constraint character to register class. */
305 enum reg_class mips_char_to_class[256] =
306 {
307 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
308 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
309 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
310 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
311 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
312 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
313 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
314 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
315 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
316 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
317 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
318 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
319 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
320 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
321 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
322 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
323 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
324 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
325 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
326 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
327 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
328 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
329 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
330 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
331 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
332 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
333 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
334 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
335 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
336 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
337 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
338 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
339 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
340 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
341 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
342 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
343 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
344 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
345 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
346 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
347 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
348 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
349 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
350 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
351 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
352 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
353 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
354 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
355 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
356 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
357 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
358 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
359 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
360 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
361 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
362 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
363 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
364 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
365 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
366 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
367 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
368 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
369 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
370 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
371 };
372
373 \f
374 /* Return truth value of whether OP can be used as an operands
375 where a register or 16 bit unsigned integer is needed. */
376
377 int
378 uns_arith_operand (op, mode)
379 rtx op;
380 enum machine_mode mode;
381 {
382 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
383 return TRUE;
384
385 return register_operand (op, mode);
386 }
387
388 /* Return truth value of whether OP can be used as an operands
389 where a 16 bit integer is needed */
390
391 int
392 arith_operand (op, mode)
393 rtx op;
394 enum machine_mode mode;
395 {
396 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
397 return TRUE;
398
399 return register_operand (op, mode);
400 }
401
402 /* Return truth value of whether OP can be used as an operand in a two
403 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
404
405 int
406 arith32_operand (op, mode)
407 rtx op;
408 enum machine_mode mode;
409 {
410 if (GET_CODE (op) == CONST_INT)
411 return TRUE;
412
413 return register_operand (op, mode);
414 }
415
416 /* Return truth value of whether OP is a integer which fits in 16 bits */
417
418 int
419 small_int (op, mode)
420 rtx op;
421 enum machine_mode mode;
422 {
423 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
424 }
425
426 /* Return truth value of whether OP is a 32 bit integer which is too big to
427 be loaded with one instruction. */
428
429 int
430 large_int (op, mode)
431 rtx op;
432 enum machine_mode mode;
433 {
434 HOST_WIDE_INT value;
435
436 if (GET_CODE (op) != CONST_INT)
437 return FALSE;
438
439 value = INTVAL (op);
440 if ((value & ~0x0000ffff) == 0) /* ior reg,$r0,value */
441 return FALSE;
442
443 if (((unsigned long)(value + 32768)) <= 32767) /* subu reg,$r0,value */
444 return FALSE;
445
446 if ((value & 0x0000ffff) == 0) /* lui reg,value>>16 */
447 return FALSE;
448
449 return TRUE;
450 }
451
452 /* Return truth value of whether OP is a register or the constant 0. */
453
454 int
455 reg_or_0_operand (op, mode)
456 rtx op;
457 enum machine_mode mode;
458 {
459 switch (GET_CODE (op))
460 {
461 default:
462 break;
463
464 case CONST_INT:
465 return (INTVAL (op) == 0);
466
467 case CONST_DOUBLE:
468 if (op != CONST0_RTX (mode))
469 return FALSE;
470
471 return TRUE;
472
473 case REG:
474 case SUBREG:
475 return register_operand (op, mode);
476 }
477
478 return FALSE;
479 }
480
481 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
482
483 int
484 mips_const_double_ok (op, mode)
485 rtx op;
486 enum machine_mode mode;
487 {
488 REAL_VALUE_TYPE d;
489
490 if (GET_CODE (op) != CONST_DOUBLE)
491 return FALSE;
492
493 if (mode == VOIDmode)
494 return TRUE;
495
496 if (mode != SFmode && mode != DFmode)
497 return FALSE;
498
499 if (op == CONST0_RTX (mode))
500 return TRUE;
501
502 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
503 if (mips_abi != ABI_32 && mips_abi != ABI_EABI)
504 return FALSE;
505
506 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
507
508 if (REAL_VALUE_ISNAN (d))
509 return FALSE;
510
511 if (REAL_VALUE_NEGATIVE (d))
512 d = REAL_VALUE_NEGATE (d);
513
514 if (mode == DFmode)
515 {
516 if (REAL_VALUES_LESS (d, dfhigh)
517 && REAL_VALUES_LESS (dflow, d))
518 return TRUE;
519 }
520 else
521 {
522 if (REAL_VALUES_LESS (d, sfhigh)
523 && REAL_VALUES_LESS (sflow, d))
524 return TRUE;
525 }
526
527 return FALSE;
528 }
529
530 /* Accept the floating point constant 1 in the appropriate mode. */
531
532 int
533 const_float_1_operand (op, mode)
534 rtx op;
535 enum machine_mode mode;
536 {
537 REAL_VALUE_TYPE d;
538 static REAL_VALUE_TYPE onedf;
539 static REAL_VALUE_TYPE onesf;
540 static int one_initialized;
541
542 if (GET_CODE (op) != CONST_DOUBLE
543 || mode != GET_MODE (op)
544 || (mode != DFmode && mode != SFmode))
545 return FALSE;
546
547 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
548
549 /* We only initialize these values if we need them, since we will
550 never get called unless mips_isa >= 4. */
551 if (! one_initialized)
552 {
553 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
554 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
555 one_initialized = TRUE;
556 }
557
558 if (mode == DFmode)
559 return REAL_VALUES_EQUAL (d, onedf);
560 else
561 return REAL_VALUES_EQUAL (d, onesf);
562 }
563
564 /* Return truth value if a memory operand fits in a single instruction
565 (ie, register + small offset). */
566
567 int
568 simple_memory_operand (op, mode)
569 rtx op;
570 enum machine_mode mode;
571 {
572 rtx addr, plus0, plus1;
573
574 /* Eliminate non-memory operations */
575 if (GET_CODE (op) != MEM)
576 return FALSE;
577
578 /* dword operations really put out 2 instructions, so eliminate them. */
579 /* ??? This isn't strictly correct. It is OK to accept multiword modes
580 here, since the length attributes are being set correctly, but only
581 if the address is offsettable. LO_SUM is not offsettable. */
582 if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD)
583 return FALSE;
584
585 /* Decode the address now. */
586 addr = XEXP (op, 0);
587 switch (GET_CODE (addr))
588 {
589 default:
590 break;
591
592 case REG:
593 case LO_SUM:
594 return TRUE;
595
596 case CONST_INT:
597 return SMALL_INT (op);
598
599 case PLUS:
600 plus0 = XEXP (addr, 0);
601 plus1 = XEXP (addr, 1);
602 if (GET_CODE (plus0) == REG
603 && GET_CODE (plus1) == CONST_INT
604 && SMALL_INT (plus1))
605 return TRUE;
606
607 else if (GET_CODE (plus1) == REG
608 && GET_CODE (plus0) == CONST_INT
609 && SMALL_INT (plus0))
610 return TRUE;
611
612 else
613 return FALSE;
614
615 #if 0
616 /* We used to allow small symbol refs here (ie, stuff in .sdata
617 or .sbss), but this causes some bugs in G++. Also, it won't
618 interfere if the MIPS linker rewrites the store instruction
619 because the function is PIC. */
620
621 case LABEL_REF: /* never gp relative */
622 break;
623
624 case CONST:
625 /* If -G 0, we can never have a GP relative memory operation.
626 Also, save some time if not optimizing. */
627 if (!TARGET_GP_OPT)
628 return FALSE;
629
630 {
631 rtx offset = const0_rtx;
632 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
633 if (GET_CODE (op) != SYMBOL_REF)
634 return FALSE;
635
636 /* let's be paranoid.... */
637 if (! SMALL_INT (offset))
638 return FALSE;
639 }
640 /* fall through */
641
642 case SYMBOL_REF:
643 return SYMBOL_REF_FLAG (addr);
644 #endif
645 }
646
647 return FALSE;
648 }
649
650 /* Return true if the code of this rtx pattern is EQ or NE. */
651
652 int
653 equality_op (op, mode)
654 rtx op;
655 enum machine_mode mode;
656 {
657 if (mode != GET_MODE (op))
658 return FALSE;
659
660 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
661 }
662
663 /* Return true if the code is a relational operations (EQ, LE, etc.) */
664
665 int
666 cmp_op (op, mode)
667 rtx op;
668 enum machine_mode mode;
669 {
670 if (mode != GET_MODE (op))
671 return FALSE;
672
673 return (GET_RTX_CLASS (GET_CODE (op)) == '<');
674 }
675
676 /* Return true if the operand is either the PC or a label_ref. */
677
678 int
679 pc_or_label_operand (op, mode)
680 rtx op;
681 enum machine_mode mode;
682 {
683 if (op == pc_rtx)
684 return TRUE;
685
686 if (GET_CODE (op) == LABEL_REF)
687 return TRUE;
688
689 return FALSE;
690 }
691
692 /* Test for a valid operand for a call instruction.
693 Don't allow the arg pointer register or virtual regs
694 since they may change into reg + const, which the patterns
695 can't handle yet. */
696
697 int
698 call_insn_operand (op, mode)
699 rtx op;
700 enum machine_mode mode;
701 {
702 if (CONSTANT_ADDRESS_P (op)
703 || (GET_CODE (op) == REG && op != arg_pointer_rtx
704 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
705 && REGNO (op) <= LAST_VIRTUAL_REGISTER)))
706 return 1;
707 return 0;
708 }
709
710 /* Return true if OPERAND is valid as a source operand for a move
711 instruction. */
712
713 int
714 move_operand (op, mode)
715 rtx op;
716 enum machine_mode mode;
717 {
718 return (general_operand (op, mode)
719 && ! (mips_split_addresses && mips_check_split (op, mode)));
720 }
721
722 /* Return true if OPERAND is valid as a source operand for movdi.
723 This accepts not only general_operand, but also sign extended
724 constants and registers. We need to accept sign extended constants
725 in case a sign extended register which is used in an expression,
726 and is equivalent to a constant, is spilled. */
727
728 int
729 movdi_operand (op, mode)
730 rtx op;
731 enum machine_mode mode;
732 {
733 if (TARGET_64BIT
734 && mode == DImode
735 && GET_CODE (op) == SIGN_EXTEND
736 && GET_MODE (op) == DImode
737 && (GET_MODE (XEXP (op, 0)) == SImode
738 || (GET_CODE (XEXP (op, 0)) == CONST_INT
739 && GET_MODE (XEXP (op, 0)) == VOIDmode))
740 && (register_operand (XEXP (op, 0), SImode)
741 || immediate_operand (XEXP (op, 0), SImode)))
742 return 1;
743
744 return general_operand (op, mode);
745 }
746
747 /* Like register_operand, but when in 64 bit mode also accept a sign
748 extend of a 32 bit register, since the value is known to be already
749 sign extended. */
750
751 int
752 se_register_operand (op, mode)
753 rtx op;
754 enum machine_mode mode;
755 {
756 if (TARGET_64BIT
757 && mode == DImode
758 && GET_CODE (op) == SIGN_EXTEND
759 && GET_MODE (op) == DImode
760 && GET_MODE (XEXP (op, 0)) == SImode
761 && register_operand (XEXP (op, 0), SImode))
762 return 1;
763
764 return register_operand (op, mode);
765 }
766
767 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
768 extend of a 32 bit register, since the value is known to be already
769 sign extended. */
770
771 int
772 se_reg_or_0_operand (op, mode)
773 rtx op;
774 enum machine_mode mode;
775 {
776 if (TARGET_64BIT
777 && mode == DImode
778 && GET_CODE (op) == SIGN_EXTEND
779 && GET_MODE (op) == DImode
780 && GET_MODE (XEXP (op, 0)) == SImode
781 && register_operand (XEXP (op, 0), SImode))
782 return 1;
783
784 return reg_or_0_operand (op, mode);
785 }
786
787 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
788 extend of a 32 bit register, since the value is known to be already
789 sign extended. */
790
791 int
792 se_uns_arith_operand (op, mode)
793 rtx op;
794 enum machine_mode mode;
795 {
796 if (TARGET_64BIT
797 && mode == DImode
798 && GET_CODE (op) == SIGN_EXTEND
799 && GET_MODE (op) == DImode
800 && GET_MODE (XEXP (op, 0)) == SImode
801 && register_operand (XEXP (op, 0), SImode))
802 return 1;
803
804 return uns_arith_operand (op, mode);
805 }
806
807 /* Like arith_operand, but when in 64 bit mode also accept a sign
808 extend of a 32 bit register, since the value is known to be already
809 sign extended. */
810
811 int
812 se_arith_operand (op, mode)
813 rtx op;
814 enum machine_mode mode;
815 {
816 if (TARGET_64BIT
817 && mode == DImode
818 && GET_CODE (op) == SIGN_EXTEND
819 && GET_MODE (op) == DImode
820 && GET_MODE (XEXP (op, 0)) == SImode
821 && register_operand (XEXP (op, 0), SImode))
822 return 1;
823
824 return arith_operand (op, mode);
825 }
826
827 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
828 extend of a 32 bit register, since the value is known to be already
829 sign extended. */
830
831 int
832 se_nonmemory_operand (op, mode)
833 rtx op;
834 enum machine_mode mode;
835 {
836 if (TARGET_64BIT
837 && mode == DImode
838 && GET_CODE (op) == SIGN_EXTEND
839 && GET_MODE (op) == DImode
840 && GET_MODE (XEXP (op, 0)) == SImode
841 && register_operand (XEXP (op, 0), SImode))
842 return 1;
843
844 return nonmemory_operand (op, mode);
845 }
846
847 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
848 sign extend of a 32 bit register, since the value is known to be
849 already sign extended. */
850
851 int
852 se_nonimmediate_operand (op, mode)
853 rtx op;
854 enum machine_mode mode;
855 {
856 if (TARGET_64BIT
857 && mode == DImode
858 && GET_CODE (op) == SIGN_EXTEND
859 && GET_MODE (op) == DImode
860 && GET_MODE (XEXP (op, 0)) == SImode
861 && register_operand (XEXP (op, 0), SImode))
862 return 1;
863
864 return nonimmediate_operand (op, mode);
865 }
866
867 /* Return true if we split the address into high and low parts. */
868
869 /* ??? We should also handle reg+array somewhere. We get four
870 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
871 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
872 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
873 out of the address, then we have 4 instructions to combine. Perhaps
874 add a 3->2 define_split for combine. */
875
876 /* ??? We could also split a CONST_INT here if it is a large_int().
877 However, it doesn't seem to be very useful to have %hi(constant).
878 We would be better off by doing the masking ourselves and then putting
879 the explicit high part of the constant in the RTL. This will give better
880 optimization. Also, %hi(constant) needs assembler changes to work.
881 There is already a define_split that does this. */
882
883 int
884 mips_check_split (address, mode)
885 rtx address;
886 enum machine_mode mode;
887 {
888 /* ??? This is the same check used in simple_memory_operand.
889 We use it here because LO_SUM is not offsettable. */
890 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
891 return 0;
892
893 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
894 || (GET_CODE (address) == CONST
895 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
896 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
897 || GET_CODE (address) == LABEL_REF)
898 return 1;
899
900 return 0;
901 }
902 \f
903 /* Returns an operand string for the given instruction's delay slot,
904 after updating filled delay slot statistics.
905
906 We assume that operands[0] is the target register that is set.
907
908 In order to check the next insn, most of this functionality is moved
909 to FINAL_PRESCAN_INSN, and we just set the global variables that
910 it needs. */
911
912 /* ??? This function no longer does anything useful, because final_prescan_insn
913 now will never emit a nop. */
914
915 char *
916 mips_fill_delay_slot (ret, type, operands, cur_insn)
917 char *ret; /* normal string to return */
918 enum delay_type type; /* type of delay */
919 rtx operands[]; /* operands to use */
920 rtx cur_insn; /* current insn */
921 {
922 register rtx set_reg;
923 register enum machine_mode mode;
924 register rtx next_insn = (cur_insn) ? NEXT_INSN (cur_insn) : (rtx)0;
925 register int num_nops;
926
927 if (type == DELAY_LOAD || type == DELAY_FCMP)
928 num_nops = 1;
929
930 else if (type == DELAY_HILO)
931 num_nops = 2;
932
933 else
934 num_nops = 0;
935
936 /* Make sure that we don't put nop's after labels. */
937 next_insn = NEXT_INSN (cur_insn);
938 while (next_insn != (rtx)0 && GET_CODE (next_insn) == NOTE)
939 next_insn = NEXT_INSN (next_insn);
940
941 dslots_load_total += num_nops;
942 if (TARGET_DEBUG_F_MODE
943 || !optimize
944 || type == DELAY_NONE
945 || operands == (rtx *)0
946 || cur_insn == (rtx)0
947 || next_insn == (rtx)0
948 || GET_CODE (next_insn) == CODE_LABEL
949 || (set_reg = operands[0]) == (rtx)0)
950 {
951 dslots_number_nops = 0;
952 mips_load_reg = (rtx)0;
953 mips_load_reg2 = (rtx)0;
954 mips_load_reg3 = (rtx)0;
955 mips_load_reg4 = (rtx)0;
956 return ret;
957 }
958
959 set_reg = operands[0];
960 if (set_reg == (rtx)0)
961 return ret;
962
963 while (GET_CODE (set_reg) == SUBREG)
964 set_reg = SUBREG_REG (set_reg);
965
966 mode = GET_MODE (set_reg);
967 dslots_number_nops = num_nops;
968 mips_load_reg = set_reg;
969 if (GET_MODE_SIZE (mode)
970 > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
971 mips_load_reg2 = gen_rtx (REG, SImode, REGNO (set_reg) + 1);
972 else
973 mips_load_reg2 = 0;
974
975 if (type == DELAY_HILO)
976 {
977 mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST);
978 mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1);
979 }
980 else
981 {
982 mips_load_reg3 = 0;
983 mips_load_reg4 = 0;
984 }
985
986 return ret;
987 }
988
989 \f
990 /* Determine whether a memory reference takes one (based off of the GP pointer),
991 two (normal), or three (label + reg) instructions, and bump the appropriate
992 counter for -mstats. */
993
994 void
995 mips_count_memory_refs (op, num)
996 rtx op;
997 int num;
998 {
999 int additional = 0;
1000 int n_words = 0;
1001 rtx addr, plus0, plus1;
1002 enum rtx_code code0, code1;
1003 int looping;
1004
1005 if (TARGET_DEBUG_B_MODE)
1006 {
1007 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1008 debug_rtx (op);
1009 }
1010
1011 /* Skip MEM if passed, otherwise handle movsi of address. */
1012 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1013
1014 /* Loop, going through the address RTL */
1015 do
1016 {
1017 looping = FALSE;
1018 switch (GET_CODE (addr))
1019 {
1020 default:
1021 break;
1022
1023 case REG:
1024 case CONST_INT:
1025 case LO_SUM:
1026 break;
1027
1028 case PLUS:
1029 plus0 = XEXP (addr, 0);
1030 plus1 = XEXP (addr, 1);
1031 code0 = GET_CODE (plus0);
1032 code1 = GET_CODE (plus1);
1033
1034 if (code0 == REG)
1035 {
1036 additional++;
1037 addr = plus1;
1038 looping = TRUE;
1039 continue;
1040 }
1041
1042 if (code0 == CONST_INT)
1043 {
1044 addr = plus1;
1045 looping = TRUE;
1046 continue;
1047 }
1048
1049 if (code1 == REG)
1050 {
1051 additional++;
1052 addr = plus0;
1053 looping = TRUE;
1054 continue;
1055 }
1056
1057 if (code1 == CONST_INT)
1058 {
1059 addr = plus0;
1060 looping = TRUE;
1061 continue;
1062 }
1063
1064 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1065 {
1066 addr = plus0;
1067 looping = TRUE;
1068 continue;
1069 }
1070
1071 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1072 {
1073 addr = plus1;
1074 looping = TRUE;
1075 continue;
1076 }
1077
1078 break;
1079
1080 case LABEL_REF:
1081 n_words = 2; /* always 2 words */
1082 break;
1083
1084 case CONST:
1085 addr = XEXP (addr, 0);
1086 looping = TRUE;
1087 continue;
1088
1089 case SYMBOL_REF:
1090 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1091 break;
1092 }
1093 }
1094 while (looping);
1095
1096 if (n_words == 0)
1097 return;
1098
1099 n_words += additional;
1100 if (n_words > 3)
1101 n_words = 3;
1102
1103 num_refs[n_words-1] += num;
1104 }
1105
1106 \f
1107 /* Return RTL for the offset from the current function to the
1108 argument. */
1109
1110 rtx
1111 embedded_pic_offset (x)
1112 rtx x;
1113 {
1114 if (embedded_pic_fnaddr_rtx == NULL)
1115 {
1116 rtx seq;
1117
1118 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1119
1120 /* Output code at function start to initialize the pseudo-reg. */
1121 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1122 inline functions, because it is called after RTL for the function
1123 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1124 does not get copied, and ends up not matching the rest of the RTL.
1125 This solution works, but means that we get unnecessary code to
1126 initialize this value every time a function is inlined into another
1127 function. */
1128 start_sequence ();
1129 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1130 XEXP (DECL_RTL (current_function_decl), 0)));
1131 seq = gen_sequence ();
1132 end_sequence ();
1133 push_topmost_sequence ();
1134 emit_insn_after (seq, get_insns ());
1135 pop_topmost_sequence ();
1136 }
1137
1138 return gen_rtx (CONST, Pmode,
1139 gen_rtx (MINUS, Pmode, x,
1140 XEXP (DECL_RTL (current_function_decl), 0)));
1141 }
1142
1143 /* Return the appropriate instructions to move one operand to another. */
1144
1145 char *
1146 mips_move_1word (operands, insn, unsignedp)
1147 rtx operands[];
1148 rtx insn;
1149 int unsignedp;
1150 {
1151 char *ret = 0;
1152 rtx op0 = operands[0];
1153 rtx op1 = operands[1];
1154 enum rtx_code code0 = GET_CODE (op0);
1155 enum rtx_code code1 = GET_CODE (op1);
1156 enum machine_mode mode = GET_MODE (op0);
1157 int subreg_word0 = 0;
1158 int subreg_word1 = 0;
1159 enum delay_type delay = DELAY_NONE;
1160
1161 while (code0 == SUBREG)
1162 {
1163 subreg_word0 += SUBREG_WORD (op0);
1164 op0 = SUBREG_REG (op0);
1165 code0 = GET_CODE (op0);
1166 }
1167
1168 while (code1 == SUBREG)
1169 {
1170 subreg_word1 += SUBREG_WORD (op1);
1171 op1 = SUBREG_REG (op1);
1172 code1 = GET_CODE (op1);
1173 }
1174
1175 /* For our purposes, a condition code mode is the same as SImode. */
1176 if (mode == CCmode)
1177 mode = SImode;
1178
1179 if (code0 == REG)
1180 {
1181 int regno0 = REGNO (op0) + subreg_word0;
1182
1183 if (code1 == REG)
1184 {
1185 int regno1 = REGNO (op1) + subreg_word1;
1186
1187 /* Just in case, don't do anything for assigning a register
1188 to itself, unless we are filling a delay slot. */
1189 if (regno0 == regno1 && set_nomacro == 0)
1190 ret = "";
1191
1192 else if (GP_REG_P (regno0))
1193 {
1194 if (GP_REG_P (regno1))
1195 ret = "move\t%0,%1";
1196
1197 else if (MD_REG_P (regno1))
1198 {
1199 delay = DELAY_HILO;
1200 if (regno1 != HILO_REGNUM)
1201 ret = "mf%1\t%0";
1202 else
1203 ret = "mflo\t%0";
1204 }
1205
1206 else if (ST_REG_P (regno1) && mips_isa >= 4)
1207 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1208
1209 else
1210 {
1211 delay = DELAY_LOAD;
1212 if (FP_REG_P (regno1))
1213 ret = "mfc1\t%0,%1";
1214
1215 else if (regno1 == FPSW_REGNUM && mips_isa < 4)
1216 ret = "cfc1\t%0,$31";
1217 }
1218 }
1219
1220 else if (FP_REG_P (regno0))
1221 {
1222 if (GP_REG_P (regno1))
1223 {
1224 delay = DELAY_LOAD;
1225 ret = "mtc1\t%1,%0";
1226 }
1227
1228 if (FP_REG_P (regno1))
1229 ret = "mov.s\t%0,%1";
1230 }
1231
1232 else if (MD_REG_P (regno0))
1233 {
1234 if (GP_REG_P (regno1))
1235 {
1236 delay = DELAY_HILO;
1237 if (regno0 != HILO_REGNUM)
1238 ret = "mt%0\t%1";
1239 }
1240 }
1241
1242 else if (regno0 == FPSW_REGNUM && mips_isa < 4)
1243 {
1244 if (GP_REG_P (regno1))
1245 {
1246 delay = DELAY_LOAD;
1247 ret = "ctc1\t%0,$31";
1248 }
1249 }
1250 }
1251
1252 else if (code1 == MEM)
1253 {
1254 delay = DELAY_LOAD;
1255
1256 if (TARGET_STATS)
1257 mips_count_memory_refs (op1, 1);
1258
1259 if (GP_REG_P (regno0))
1260 {
1261 /* For loads, use the mode of the memory item, instead of the
1262 target, so zero/sign extend can use this code as well. */
1263 switch (GET_MODE (op1))
1264 {
1265 default:
1266 break;
1267 case SFmode:
1268 ret = "lw\t%0,%1";
1269 break;
1270 case SImode:
1271 case CCmode:
1272 ret = ((unsignedp && TARGET_64BIT)
1273 ? "lwu\t%0,%1"
1274 : "lw\t%0,%1");
1275 break;
1276 case HImode:
1277 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1278 break;
1279 case QImode:
1280 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1281 break;
1282 }
1283 }
1284
1285 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1286 ret = "l.s\t%0,%1";
1287
1288 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1289 {
1290 int i = strlen (ret);
1291 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1292 abort ();
1293
1294 sprintf (volatile_buffer, "%%{%s%%}", ret);
1295 ret = volatile_buffer;
1296 }
1297 }
1298
1299 else if (code1 == CONST_INT
1300 || (code1 == CONST_DOUBLE
1301 && GET_MODE (op1) == VOIDmode))
1302 {
1303 if (code1 == CONST_DOUBLE)
1304 {
1305 /* This can happen when storing constants into long long
1306 bitfields. Just store the least significant word of
1307 the value. */
1308 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1309 }
1310
1311 if (INTVAL (op1) == 0)
1312 {
1313 if (GP_REG_P (regno0))
1314 ret = "move\t%0,%z1";
1315
1316 else if (FP_REG_P (regno0))
1317 {
1318 delay = DELAY_LOAD;
1319 ret = "mtc1\t%z1,%0";
1320 }
1321
1322 else if (MD_REG_P (regno0))
1323 {
1324 delay = DELAY_HILO;
1325 ret = "mt%0\t%.";
1326 }
1327 }
1328
1329 else if (GP_REG_P (regno0))
1330 /* Don't use X format, because that will give out of range
1331 numbers for 64 bit host and 32 bit target. */
1332 ret = "li\t%0,%1\t\t\t# %X1";
1333 }
1334
1335 else if (code1 == CONST_DOUBLE && mode == SFmode)
1336 {
1337 if (op1 == CONST0_RTX (SFmode))
1338 {
1339 if (GP_REG_P (regno0))
1340 ret = "move\t%0,%.";
1341
1342 else if (FP_REG_P (regno0))
1343 {
1344 delay = DELAY_LOAD;
1345 ret = "mtc1\t%.,%0";
1346 }
1347 }
1348
1349 else
1350 {
1351 delay = DELAY_LOAD;
1352 ret = "li.s\t%0,%1";
1353 }
1354 }
1355
1356 else if (code1 == LABEL_REF)
1357 {
1358 if (TARGET_STATS)
1359 mips_count_memory_refs (op1, 1);
1360
1361 ret = "la\t%0,%a1";
1362 }
1363
1364 else if (code1 == SYMBOL_REF || code1 == CONST)
1365 {
1366 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
1367 {
1368 rtx offset = const0_rtx;
1369
1370 if (GET_CODE (op1) == CONST)
1371 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
1372
1373 if (GET_CODE (op1) == SYMBOL_REF)
1374 {
1375 operands[2] = HALF_PIC_PTR (op1);
1376
1377 if (TARGET_STATS)
1378 mips_count_memory_refs (operands[2], 1);
1379
1380 if (INTVAL (offset) == 0)
1381 {
1382 delay = DELAY_LOAD;
1383 ret = (unsignedp && TARGET_64BIT
1384 ? "lwu\t%0,%2"
1385 : "lw\t%0,%2");
1386 }
1387 else
1388 {
1389 dslots_load_total++;
1390 operands[3] = offset;
1391 if (unsignedp && TARGET_64BIT)
1392 ret = (SMALL_INT (offset))
1393 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1394 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1395 else
1396 ret = (SMALL_INT (offset))
1397 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1398 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1399 }
1400 }
1401 }
1402 else
1403 {
1404 if (TARGET_STATS)
1405 mips_count_memory_refs (op1, 1);
1406
1407 ret = "la\t%0,%a1";
1408 }
1409 }
1410
1411 else if (code1 == PLUS)
1412 {
1413 rtx add_op0 = XEXP (op1, 0);
1414 rtx add_op1 = XEXP (op1, 1);
1415
1416 if (GET_CODE (XEXP (op1, 1)) == REG && GET_CODE (XEXP (op1, 0)) == CONST_INT)
1417 {
1418 add_op0 = XEXP (op1, 1); /* reverse operands */
1419 add_op1 = XEXP (op1, 0);
1420 }
1421
1422 operands[2] = add_op0;
1423 operands[3] = add_op1;
1424 ret = "add%:\t%0,%2,%3";
1425 }
1426
1427 else if (code1 == HIGH)
1428 {
1429 operands[1] = XEXP (op1, 0);
1430 ret = "lui\t%0,%%hi(%1)";
1431 }
1432 }
1433
1434 else if (code0 == MEM)
1435 {
1436 if (TARGET_STATS)
1437 mips_count_memory_refs (op0, 1);
1438
1439 if (code1 == REG)
1440 {
1441 int regno1 = REGNO (op1) + subreg_word1;
1442
1443 if (GP_REG_P (regno1))
1444 {
1445 switch (mode)
1446 {
1447 default: break;
1448 case SFmode: ret = "sw\t%1,%0"; break;
1449 case SImode: ret = "sw\t%1,%0"; break;
1450 case HImode: ret = "sh\t%1,%0"; break;
1451 case QImode: ret = "sb\t%1,%0"; break;
1452 }
1453 }
1454
1455 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
1456 ret = "s.s\t%1,%0";
1457 }
1458
1459 else if (code1 == CONST_INT && INTVAL (op1) == 0)
1460 {
1461 switch (mode)
1462 {
1463 default: break;
1464 case SFmode: ret = "sw\t%z1,%0"; break;
1465 case SImode: ret = "sw\t%z1,%0"; break;
1466 case HImode: ret = "sh\t%z1,%0"; break;
1467 case QImode: ret = "sb\t%z1,%0"; break;
1468 }
1469 }
1470
1471 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
1472 {
1473 switch (mode)
1474 {
1475 default: break;
1476 case SFmode: ret = "sw\t%.,%0"; break;
1477 case SImode: ret = "sw\t%.,%0"; break;
1478 case HImode: ret = "sh\t%.,%0"; break;
1479 case QImode: ret = "sb\t%.,%0"; break;
1480 }
1481 }
1482
1483 if (ret != (char *)0 && MEM_VOLATILE_P (op0))
1484 {
1485 int i = strlen (ret);
1486 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1487 abort ();
1488
1489 sprintf (volatile_buffer, "%%{%s%%}", ret);
1490 ret = volatile_buffer;
1491 }
1492 }
1493
1494 if (ret == (char *)0)
1495 {
1496 abort_with_insn (insn, "Bad move");
1497 return 0;
1498 }
1499
1500 if (delay != DELAY_NONE)
1501 return mips_fill_delay_slot (ret, delay, operands, insn);
1502
1503 return ret;
1504 }
1505
1506 \f
1507 /* Return the appropriate instructions to move 2 words */
1508
1509 char *
1510 mips_move_2words (operands, insn)
1511 rtx operands[];
1512 rtx insn;
1513 {
1514 char *ret = 0;
1515 rtx op0 = operands[0];
1516 rtx op1 = operands[1];
1517 enum rtx_code code0 = GET_CODE (operands[0]);
1518 enum rtx_code code1 = GET_CODE (operands[1]);
1519 int subreg_word0 = 0;
1520 int subreg_word1 = 0;
1521 enum delay_type delay = DELAY_NONE;
1522
1523 while (code0 == SUBREG)
1524 {
1525 subreg_word0 += SUBREG_WORD (op0);
1526 op0 = SUBREG_REG (op0);
1527 code0 = GET_CODE (op0);
1528 }
1529
1530 if (code1 == SIGN_EXTEND)
1531 {
1532 op1 = XEXP (op1, 0);
1533 code1 = GET_CODE (op1);
1534 }
1535
1536 while (code1 == SUBREG)
1537 {
1538 subreg_word1 += SUBREG_WORD (op1);
1539 op1 = SUBREG_REG (op1);
1540 code1 = GET_CODE (op1);
1541 }
1542
1543 /* Sanity check. */
1544 if (GET_CODE (operands[1]) == SIGN_EXTEND
1545 && code1 != REG
1546 && code1 != CONST_INT
1547 /* The following three can happen as the result of a questionable
1548 cast. */
1549 && code1 != LABEL_REF
1550 && code1 != SYMBOL_REF
1551 && code1 != CONST)
1552 abort ();
1553
1554 if (code0 == REG)
1555 {
1556 int regno0 = REGNO (op0) + subreg_word0;
1557
1558 if (code1 == REG)
1559 {
1560 int regno1 = REGNO (op1) + subreg_word1;
1561
1562 /* Just in case, don't do anything for assigning a register
1563 to itself, unless we are filling a delay slot. */
1564 if (regno0 == regno1 && set_nomacro == 0)
1565 ret = "";
1566
1567 else if (FP_REG_P (regno0))
1568 {
1569 if (FP_REG_P (regno1))
1570 ret = "mov.d\t%0,%1";
1571
1572 else
1573 {
1574 delay = DELAY_LOAD;
1575 if (TARGET_FLOAT64)
1576 {
1577 if (!TARGET_64BIT)
1578 abort_with_insn (insn, "Bad move");
1579 #ifdef TARGET_FP_CALL_32
1580 if (FP_CALL_GP_REG_P (regno1))
1581 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1582 else
1583 #endif
1584 ret = "dmtc1\t%1,%0";
1585 }
1586 else
1587 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1588 }
1589 }
1590
1591 else if (FP_REG_P (regno1))
1592 {
1593 delay = DELAY_LOAD;
1594 if (TARGET_FLOAT64)
1595 {
1596 if (!TARGET_64BIT)
1597 abort_with_insn (insn, "Bad move");
1598 #ifdef TARGET_FP_CALL_32
1599 if (FP_CALL_GP_REG_P (regno0))
1600 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1601 else
1602 #endif
1603 ret = "dmfc1\t%0,%1";
1604 }
1605 else
1606 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1607 }
1608
1609 else if (MD_REG_P (regno0) && GP_REG_P (regno1))
1610 {
1611 delay = DELAY_HILO;
1612 if (TARGET_64BIT)
1613 {
1614 if (regno0 != HILO_REGNUM)
1615 ret = "mt%0\t%1";
1616 else if (regno1 == 0)
1617 ret = "mtlo\t%.\n\tmthi\t%.";
1618 }
1619 else
1620 ret = "mthi\t%M1\n\tmtlo\t%L1";
1621 }
1622
1623 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
1624 {
1625 delay = DELAY_HILO;
1626 if (TARGET_64BIT)
1627 {
1628 if (regno1 != HILO_REGNUM)
1629 ret = "mf%1\t%0";
1630 }
1631 else
1632 ret = "mfhi\t%M0\n\tmflo\t%L0";
1633 }
1634
1635 else if (TARGET_64BIT)
1636 ret = "move\t%0,%1";
1637
1638 else if (regno0 != (regno1+1))
1639 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
1640
1641 else
1642 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
1643 }
1644
1645 else if (code1 == CONST_DOUBLE)
1646 {
1647 /* Move zero from $0 unless !TARGET_64BIT and recipient
1648 is 64-bit fp reg, in which case generate a constant. */
1649 if (op1 != CONST0_RTX (GET_MODE (op1))
1650 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
1651 {
1652 if (GET_MODE (op1) == DFmode)
1653 {
1654 delay = DELAY_LOAD;
1655 #ifdef TARGET_FP_CALL_32
1656 if (FP_CALL_GP_REG_P (regno0))
1657 {
1658 if (TARGET_FLOAT64 && !TARGET_64BIT)
1659 {
1660 split_double (op1, operands + 2, operands + 3);
1661 ret = "li\t%0,%2\n\tli\t%D0,%3";
1662 }
1663 else
1664 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1665 }
1666 else
1667 #endif
1668 ret = "li.d\t%0,%1";
1669 }
1670
1671 else if (TARGET_64BIT)
1672 ret = "dli\t%0,%1";
1673
1674 else
1675 {
1676 split_double (op1, operands + 2, operands + 3);
1677 ret = "li\t%0,%2\n\tli\t%D0,%3";
1678 }
1679 }
1680
1681 else
1682 {
1683 if (GP_REG_P (regno0))
1684 ret = (TARGET_64BIT
1685 #ifdef TARGET_FP_CALL_32
1686 && ! FP_CALL_GP_REG_P (regno0)
1687 #endif
1688 )
1689 ? "move\t%0,%."
1690 : "move\t%0,%.\n\tmove\t%D0,%.";
1691
1692 else if (FP_REG_P (regno0))
1693 {
1694 delay = DELAY_LOAD;
1695 ret = (TARGET_64BIT)
1696 ? "dmtc1\t%.,%0"
1697 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1698 }
1699 }
1700 }
1701
1702 else if (code1 == CONST_INT && INTVAL (op1) == 0)
1703 {
1704 if (GP_REG_P (regno0))
1705 ret = (TARGET_64BIT)
1706 ? "move\t%0,%."
1707 : "move\t%0,%.\n\tmove\t%D0,%.";
1708
1709 else if (FP_REG_P (regno0))
1710 {
1711 delay = DELAY_LOAD;
1712 ret = (TARGET_64BIT)
1713 ? "dmtc1\t%.,%0"
1714 : (TARGET_FLOAT64
1715 ? "li.d\t%0,%1"
1716 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1717 }
1718 else if (MD_REG_P (regno0))
1719 {
1720 delay = DELAY_HILO;
1721 if (regno0 != HILO_REGNUM)
1722 ret = "mt%0\t%.\n";
1723 else
1724 ret = "mtlo\t%.\n\tmthi\t%.";
1725 }
1726 }
1727
1728 else if (code1 == CONST_INT && GET_MODE (op0) == DImode && GP_REG_P (regno0))
1729 {
1730 if (TARGET_64BIT)
1731 {
1732 if (GET_CODE (operands[1]) == SIGN_EXTEND)
1733 ret = "li\t%0,%1\t\t# %X1";
1734 else if (HOST_BITS_PER_WIDE_INT < 64)
1735 /* We can't use 'X' for negative numbers, because then we won't
1736 get the right value for the upper 32 bits. */
1737 ret = ((INTVAL (op1) < 0) ? "dli\t%0,%1\t\t\t# %X1"
1738 : "dli\t%0,%X1\t\t# %1");
1739 else
1740 /* We must use 'X', because otherwise LONG_MIN will print as
1741 a number that the assembler won't accept. */
1742 ret = "dli\t%0,%X1\t\t# %1";
1743 }
1744 else if (HOST_BITS_PER_WIDE_INT < 64)
1745 {
1746 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
1747 ret = "li\t%M0,%2\n\tli\t%L0,%1";
1748 }
1749 else
1750 {
1751 /* We use multiple shifts here, to avoid warnings about out
1752 of range shifts on 32 bit hosts. */
1753 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
1754 operands[1] = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
1755 ret = "li\t%M0,%2\n\tli\t%L0,%1";
1756 }
1757 }
1758
1759 else if (code1 == MEM)
1760 {
1761 delay = DELAY_LOAD;
1762
1763 if (TARGET_STATS)
1764 mips_count_memory_refs (op1, 2);
1765
1766 if (FP_REG_P (regno0))
1767 ret = "l.d\t%0,%1";
1768
1769 else if (TARGET_64BIT)
1770 {
1771 #ifdef TARGET_FP_CALL_32
1772 if (FP_CALL_GP_REG_P (regno0))
1773 {
1774 if (offsettable_address_p (FALSE, SImode, op1))
1775 ret = "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1776 else
1777 ret = "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1778 }
1779 else
1780 #endif
1781 ret = "ld\t%0,%1";
1782 }
1783
1784 else if (offsettable_address_p (1, DFmode, XEXP (op1, 0)))
1785 {
1786 operands[2] = adj_offsettable_operand (op1, 4);
1787 if (reg_mentioned_p (op0, op1))
1788 ret = "lw\t%D0,%2\n\tlw\t%0,%1";
1789 else
1790 ret = "lw\t%0,%1\n\tlw\t%D0,%2";
1791 }
1792
1793 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1794 {
1795 int i = strlen (ret);
1796 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1797 abort ();
1798
1799 sprintf (volatile_buffer, "%%{%s%%}", ret);
1800 ret = volatile_buffer;
1801 }
1802 }
1803
1804 else if (code1 == LABEL_REF
1805 || code1 == SYMBOL_REF
1806 || code1 == CONST)
1807 {
1808 if (TARGET_STATS)
1809 mips_count_memory_refs (op1, 2);
1810
1811 if (GET_CODE (operands[1]) == SIGN_EXTEND)
1812 /* We deliberately remove the 'a' from '%1', so that we don't
1813 have to add SIGN_EXTEND support to print_operand_address.
1814 print_operand will just call print_operand_address in this
1815 case, so there is no problem. */
1816 ret = "la\t%0,%1";
1817 else
1818 ret = "dla\t%0,%a1";
1819 }
1820 }
1821
1822 else if (code0 == MEM)
1823 {
1824 if (code1 == REG)
1825 {
1826 int regno1 = REGNO (op1) + subreg_word1;
1827
1828 if (FP_REG_P (regno1))
1829 ret = "s.d\t%1,%0";
1830
1831 else if (TARGET_64BIT)
1832 {
1833 #ifdef TARGET_FP_CALL_32
1834 if (FP_CALL_GP_REG_P (regno1))
1835 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1836 else
1837 #endif
1838 ret = "sd\t%1,%0";
1839 }
1840
1841 else if (offsettable_address_p (1, DFmode, XEXP (op0, 0)))
1842 {
1843 operands[2] = adj_offsettable_operand (op0, 4);
1844 ret = "sw\t%1,%0\n\tsw\t%D1,%2";
1845 }
1846 }
1847
1848 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
1849 || (code1 == CONST_DOUBLE
1850 && op1 == CONST0_RTX (GET_MODE (op1))))
1851 && (TARGET_64BIT
1852 || offsettable_address_p (1, DFmode, XEXP (op0, 0))))
1853 {
1854 if (TARGET_64BIT)
1855 ret = "sd\t%.,%0";
1856 else
1857 {
1858 operands[2] = adj_offsettable_operand (op0, 4);
1859 ret = "sw\t%.,%0\n\tsw\t%.,%2";
1860 }
1861 }
1862
1863 if (TARGET_STATS)
1864 mips_count_memory_refs (op0, 2);
1865
1866 if (ret != (char *)0 && MEM_VOLATILE_P (op0))
1867 {
1868 int i = strlen (ret);
1869 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1870 abort ();
1871
1872 sprintf (volatile_buffer, "%%{%s%%}", ret);
1873 ret = volatile_buffer;
1874 }
1875 }
1876
1877 if (ret == (char *)0)
1878 {
1879 abort_with_insn (insn, "Bad move");
1880 return 0;
1881 }
1882
1883 if (delay != DELAY_NONE)
1884 return mips_fill_delay_slot (ret, delay, operands, insn);
1885
1886 return ret;
1887 }
1888
1889 \f
1890 /* Provide the costs of an addressing mode that contains ADDR.
1891 If ADDR is not a valid address, its cost is irrelevant. */
1892
1893 int
1894 mips_address_cost (addr)
1895 rtx addr;
1896 {
1897 switch (GET_CODE (addr))
1898 {
1899 default:
1900 break;
1901
1902 case LO_SUM:
1903 return 1;
1904
1905 case LABEL_REF:
1906 return 2;
1907
1908 case CONST:
1909 {
1910 rtx offset = const0_rtx;
1911 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
1912 if (GET_CODE (addr) == LABEL_REF)
1913 return 2;
1914
1915 if (GET_CODE (addr) != SYMBOL_REF)
1916 return 4;
1917
1918 if (! SMALL_INT (offset))
1919 return 2;
1920 }
1921 /* fall through */
1922
1923 case SYMBOL_REF:
1924 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
1925
1926 case PLUS:
1927 {
1928 register rtx plus0 = XEXP (addr, 0);
1929 register rtx plus1 = XEXP (addr, 1);
1930
1931 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1932 {
1933 plus0 = XEXP (addr, 1);
1934 plus1 = XEXP (addr, 0);
1935 }
1936
1937 if (GET_CODE (plus0) != REG)
1938 break;
1939
1940 switch (GET_CODE (plus1))
1941 {
1942 default:
1943 break;
1944
1945 case CONST_INT:
1946 return (SMALL_INT (plus1) ? 1 : 2);
1947
1948 case CONST:
1949 case SYMBOL_REF:
1950 case LABEL_REF:
1951 case HIGH:
1952 case LO_SUM:
1953 return mips_address_cost (plus1) + 1;
1954 }
1955 }
1956 }
1957
1958 return 4;
1959 }
1960
1961 /* Return true if X is an address which needs a temporary register when
1962 reloaded while generating PIC code. */
1963
1964 int
1965 pic_address_needs_scratch (x)
1966 rtx x;
1967 {
1968 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1969 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
1970 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1971 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1972 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
1973 return 1;
1974
1975 return 0;
1976 }
1977 \f
1978 /* Make normal rtx_code into something we can index from an array */
1979
1980 static enum internal_test
1981 map_test_to_internal_test (test_code)
1982 enum rtx_code test_code;
1983 {
1984 enum internal_test test = ITEST_MAX;
1985
1986 switch (test_code)
1987 {
1988 default: break;
1989 case EQ: test = ITEST_EQ; break;
1990 case NE: test = ITEST_NE; break;
1991 case GT: test = ITEST_GT; break;
1992 case GE: test = ITEST_GE; break;
1993 case LT: test = ITEST_LT; break;
1994 case LE: test = ITEST_LE; break;
1995 case GTU: test = ITEST_GTU; break;
1996 case GEU: test = ITEST_GEU; break;
1997 case LTU: test = ITEST_LTU; break;
1998 case LEU: test = ITEST_LEU; break;
1999 }
2000
2001 return test;
2002 }
2003
2004 \f
2005 /* Generate the code to compare two integer values. The return value is:
2006 (reg:SI xx) The pseudo register the comparison is in
2007 (rtx)0 No register, generate a simple branch.
2008
2009 ??? This is called with result nonzero by the Scond patterns in
2010 mips.md. These patterns are called with a target in the mode of
2011 the Scond instruction pattern. Since this must be a constant, we
2012 must use SImode. This means that if RESULT is non-zero, it will
2013 always be an SImode register, even if TARGET_64BIT is true. We
2014 cope with this by calling convert_move rather than emit_move_insn.
2015 This will sometimes lead to an unnecessary extension of the result;
2016 for example:
2017
2018 long long
2019 foo (long long i)
2020 {
2021 return i < 5;
2022 }
2023
2024 */
2025
2026 rtx
2027 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2028 enum rtx_code test_code; /* relational test (EQ, etc) */
2029 rtx result; /* result to store comp. or 0 if branch */
2030 rtx cmp0; /* first operand to compare */
2031 rtx cmp1; /* second operand to compare */
2032 int *p_invert; /* NULL or ptr to hold whether branch needs */
2033 /* to reverse its test */
2034 {
2035 struct cmp_info {
2036 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2037 int const_low; /* low bound of constant we can accept */
2038 int const_high; /* high bound of constant we can accept */
2039 int const_add; /* constant to add (convert LE -> LT) */
2040 int reverse_regs; /* reverse registers in test */
2041 int invert_const; /* != 0 if invert value if cmp1 is constant */
2042 int invert_reg; /* != 0 if invert value if cmp1 is register */
2043 int unsignedp; /* != 0 for unsigned comparisons. */
2044 };
2045
2046 static struct cmp_info info[ (int)ITEST_MAX ] = {
2047
2048 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2049 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2050 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2051 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2052 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2053 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2054 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2055 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2056 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2057 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2058 };
2059
2060 enum internal_test test;
2061 enum machine_mode mode;
2062 struct cmp_info *p_info;
2063 int branch_p;
2064 int eqne_p;
2065 int invert;
2066 rtx reg;
2067 rtx reg2;
2068
2069 test = map_test_to_internal_test (test_code);
2070 if (test == ITEST_MAX)
2071 abort ();
2072
2073 p_info = &info[ (int)test ];
2074 eqne_p = (p_info->test_code == XOR);
2075
2076 mode = GET_MODE (cmp0);
2077 if (mode == VOIDmode)
2078 mode = GET_MODE (cmp1);
2079
2080 /* Eliminate simple branches */
2081 branch_p = (result == (rtx)0);
2082 if (branch_p)
2083 {
2084 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2085 {
2086 /* Comparisons against zero are simple branches */
2087 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2088 return (rtx)0;
2089
2090 /* Test for beq/bne. */
2091 if (eqne_p)
2092 return (rtx)0;
2093 }
2094
2095 /* allocate a pseudo to calculate the value in. */
2096 result = gen_reg_rtx (mode);
2097 }
2098
2099 /* Make sure we can handle any constants given to us. */
2100 if (GET_CODE (cmp0) == CONST_INT)
2101 cmp0 = force_reg (mode, cmp0);
2102
2103 if (GET_CODE (cmp1) == CONST_INT)
2104 {
2105 HOST_WIDE_INT value = INTVAL (cmp1);
2106 if (value < p_info->const_low
2107 || value > p_info->const_high
2108 /* ??? Why? And why wasn't the similar code below modified too? */
2109 || (TARGET_64BIT
2110 && HOST_BITS_PER_WIDE_INT < 64
2111 && p_info->const_add != 0
2112 && ((p_info->unsignedp
2113 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2114 > INTVAL (cmp1))
2115 : (value + p_info->const_add) > INTVAL (cmp1))
2116 != (p_info->const_add > 0))))
2117 cmp1 = force_reg (mode, cmp1);
2118 }
2119
2120 /* See if we need to invert the result. */
2121 invert = (GET_CODE (cmp1) == CONST_INT)
2122 ? p_info->invert_const
2123 : p_info->invert_reg;
2124
2125 if (p_invert != (int *)0)
2126 {
2127 *p_invert = invert;
2128 invert = FALSE;
2129 }
2130
2131 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2132 Comparison between two registers, may involve switching operands. */
2133 if (GET_CODE (cmp1) == CONST_INT)
2134 {
2135 if (p_info->const_add != 0)
2136 {
2137 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2138 /* If modification of cmp1 caused overflow,
2139 we would get the wrong answer if we follow the usual path;
2140 thus, x > 0xffffffffU would turn into x > 0U. */
2141 if ((p_info->unsignedp
2142 ? (unsigned HOST_WIDE_INT) new > INTVAL (cmp1)
2143 : new > INTVAL (cmp1))
2144 != (p_info->const_add > 0))
2145 {
2146 /* This test is always true, but if INVERT is true then
2147 the result of the test needs to be inverted so 0 should
2148 be returned instead. */
2149 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2150 return result;
2151 }
2152 else
2153 cmp1 = GEN_INT (new);
2154 }
2155 }
2156 else if (p_info->reverse_regs)
2157 {
2158 rtx temp = cmp0;
2159 cmp0 = cmp1;
2160 cmp1 = temp;
2161 }
2162
2163 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2164 reg = cmp0;
2165 else
2166 {
2167 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2168 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
2169 }
2170
2171 if (test == ITEST_NE)
2172 {
2173 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
2174 invert = FALSE;
2175 }
2176
2177 else if (test == ITEST_EQ)
2178 {
2179 reg2 = (invert) ? gen_reg_rtx (mode) : result;
2180 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2181 reg = reg2;
2182 }
2183
2184 if (invert)
2185 convert_move (result, gen_rtx (XOR, mode, reg, const1_rtx), 0);
2186
2187 return result;
2188 }
2189
2190 \f
2191 /* Emit the common code for doing conditional branches.
2192 operand[0] is the label to jump to.
2193 The comparison operands are saved away by cmp{si,di,sf,df}. */
2194
2195 void
2196 gen_conditional_branch (operands, test_code)
2197 rtx operands[];
2198 enum rtx_code test_code;
2199 {
2200 enum cmp_type type = branch_type;
2201 rtx cmp0 = branch_cmp[0];
2202 rtx cmp1 = branch_cmp[1];
2203 enum machine_mode mode;
2204 rtx reg;
2205 int invert;
2206 rtx label1, label2;
2207
2208 switch (type)
2209 {
2210 default:
2211 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
2212
2213 case CMP_SI:
2214 case CMP_DI:
2215 mode = type == CMP_SI ? SImode : DImode;
2216 invert = FALSE;
2217 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
2218 if (reg)
2219 {
2220 cmp0 = reg;
2221 cmp1 = const0_rtx;
2222 test_code = NE;
2223 }
2224 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
2225 {
2226 /* We don't want to build a comparison against a non-zero
2227 constant. */
2228 cmp1 = force_reg (mode, cmp1);
2229 }
2230 break;
2231
2232 case CMP_SF:
2233 case CMP_DF:
2234 if (mips_isa < 4)
2235 reg = gen_rtx (REG, CCmode, FPSW_REGNUM);
2236 else
2237 reg = gen_reg_rtx (CCmode);
2238
2239 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2240 0 in the instruction built below. The MIPS FPU handles
2241 inequality testing by testing for equality and looking for a
2242 false result. */
2243 emit_insn (gen_rtx (SET, VOIDmode,
2244 reg,
2245 gen_rtx (test_code == NE ? EQ : test_code,
2246 CCmode, cmp0, cmp1)));
2247
2248 test_code = test_code == NE ? EQ : NE;
2249 mode = CCmode;
2250 cmp0 = reg;
2251 cmp1 = const0_rtx;
2252 invert = FALSE;
2253 break;
2254 }
2255
2256 /* Generate the branch. */
2257
2258 label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]);
2259 label2 = pc_rtx;
2260
2261 if (invert)
2262 {
2263 label2 = label1;
2264 label1 = pc_rtx;
2265 }
2266
2267 emit_jump_insn (gen_rtx (SET, VOIDmode,
2268 pc_rtx,
2269 gen_rtx (IF_THEN_ELSE, VOIDmode,
2270 gen_rtx (test_code, mode, cmp0, cmp1),
2271 label1,
2272 label2)));
2273 }
2274
2275 /* Emit the common code for conditional moves. OPERANDS is the array
2276 of operands passed to the conditional move defined_expand. */
2277
2278 void
2279 gen_conditional_move (operands)
2280 rtx *operands;
2281 {
2282 rtx op0 = branch_cmp[0];
2283 rtx op1 = branch_cmp[1];
2284 enum machine_mode mode = GET_MODE (branch_cmp[0]);
2285 enum rtx_code cmp_code = GET_CODE (operands[1]);
2286 enum rtx_code move_code = NE;
2287 enum machine_mode op_mode = GET_MODE (operands[0]);
2288 enum machine_mode cmp_mode;
2289 rtx cmp_reg;
2290
2291 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
2292 {
2293 switch (cmp_code)
2294 {
2295 case EQ:
2296 cmp_code = XOR;
2297 move_code = EQ;
2298 break;
2299 case NE:
2300 cmp_code = XOR;
2301 break;
2302 case LT:
2303 break;
2304 case GE:
2305 cmp_code = LT;
2306 move_code = EQ;
2307 break;
2308 case GT:
2309 cmp_code = LT;
2310 op0 = force_reg (mode, branch_cmp[1]);
2311 op1 = branch_cmp[0];
2312 break;
2313 case LE:
2314 cmp_code = LT;
2315 op0 = force_reg (mode, branch_cmp[1]);
2316 op1 = branch_cmp[0];
2317 move_code = EQ;
2318 break;
2319 case LTU:
2320 break;
2321 case GEU:
2322 cmp_code = LTU;
2323 move_code = EQ;
2324 break;
2325 case GTU:
2326 cmp_code = LTU;
2327 op0 = force_reg (mode, branch_cmp[1]);
2328 op1 = branch_cmp[0];
2329 break;
2330 case LEU:
2331 cmp_code = LTU;
2332 op0 = force_reg (mode, branch_cmp[1]);
2333 op1 = branch_cmp[0];
2334 move_code = EQ;
2335 break;
2336 default:
2337 abort ();
2338 }
2339 }
2340 else
2341 {
2342 if (cmp_code == NE)
2343 {
2344 cmp_code = EQ;
2345 move_code = EQ;
2346 }
2347 }
2348
2349 if (mode == SImode || mode == DImode)
2350 cmp_mode = mode;
2351 else if (mode == SFmode || mode == DFmode)
2352 cmp_mode = CCmode;
2353 else
2354 abort ();
2355
2356 cmp_reg = gen_reg_rtx (cmp_mode);
2357 emit_insn (gen_rtx (SET, cmp_mode,
2358 cmp_reg,
2359 gen_rtx (cmp_code, cmp_mode, op0, op1)));
2360 emit_insn (gen_rtx (SET, op_mode,
2361 operands[0],
2362 gen_rtx (IF_THEN_ELSE, op_mode,
2363 gen_rtx (move_code, VOIDmode,
2364 cmp_reg,
2365 CONST0_RTX (SImode)),
2366 operands[2],
2367 operands[3])));
2368 }
2369 \f
2370 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2371
2372 do {
2373 temp1 = src[0];
2374 temp2 = src[1];
2375 ...
2376 temp<last> = src[MAX_MOVE_REGS-1];
2377 dest[0] = temp1;
2378 dest[1] = temp2;
2379 ...
2380 dest[MAX_MOVE_REGS-1] = temp<last>;
2381 src += MAX_MOVE_REGS;
2382 dest += MAX_MOVE_REGS;
2383 } while (src != final);
2384
2385 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2386 registers are needed.
2387
2388 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2389 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2390 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2391
2392 #define MAX_MOVE_REGS 4
2393 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2394
2395 static void
2396 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
2397 rtx dest_reg; /* register holding destination address */
2398 rtx src_reg; /* register holding source address */
2399 int bytes; /* # bytes to move */
2400 int align; /* alignment */
2401 rtx orig_dest; /* original dest for change_address */
2402 rtx orig_src; /* original source for making a reg note */
2403 {
2404 rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg);
2405 rtx src_mem = change_address (orig_src, BLKmode, src_reg);
2406 rtx align_rtx = GEN_INT (align);
2407 rtx label;
2408 rtx final_src;
2409 rtx bytes_rtx;
2410 int leftover;
2411
2412 if (bytes < 2*MAX_MOVE_BYTES)
2413 abort ();
2414
2415 leftover = bytes % MAX_MOVE_BYTES;
2416 bytes -= leftover;
2417
2418 label = gen_label_rtx ();
2419 final_src = gen_reg_rtx (Pmode);
2420 bytes_rtx = GEN_INT (bytes);
2421
2422 if (bytes > 0x7fff)
2423 {
2424 if (TARGET_LONG64)
2425 {
2426 emit_insn (gen_movdi (final_src, bytes_rtx));
2427 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
2428 }
2429 else
2430 {
2431 emit_insn (gen_movsi (final_src, bytes_rtx));
2432 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2433 }
2434 }
2435 else
2436 {
2437 if (TARGET_LONG64)
2438 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
2439 else
2440 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
2441 }
2442
2443 emit_label (label);
2444
2445 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
2446 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
2447 if (TARGET_LONG64)
2448 {
2449 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
2450 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
2451 emit_insn (gen_cmpdi (src_reg, final_src));
2452 }
2453 else
2454 {
2455 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
2456 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
2457 emit_insn (gen_cmpsi (src_reg, final_src));
2458 }
2459 emit_jump_insn (gen_bne (label));
2460
2461 if (leftover)
2462 emit_insn (gen_movstrsi_internal (dest_mem, src_mem,
2463 GEN_INT (leftover),
2464 align_rtx));
2465 }
2466 \f
2467 /* Use a library function to move some bytes. */
2468
2469 static void
2470 block_move_call (dest_reg, src_reg, bytes_rtx)
2471 rtx dest_reg;
2472 rtx src_reg;
2473 rtx bytes_rtx;
2474 {
2475 /* We want to pass the size as Pmode, which will normally be SImode
2476 but will be DImode if we are using 64 bit longs and pointers. */
2477 if (GET_MODE (bytes_rtx) != VOIDmode
2478 && GET_MODE (bytes_rtx) != Pmode)
2479 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, TRUE);
2480
2481 #ifdef TARGET_MEM_FUNCTIONS
2482 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2483 VOIDmode, 3,
2484 dest_reg, Pmode,
2485 src_reg, Pmode,
2486 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2487 TREE_UNSIGNED (sizetype)),
2488 TYPE_MODE (sizetype));
2489 #else
2490 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2491 VOIDmode, 3,
2492 src_reg, Pmode,
2493 dest_reg, Pmode,
2494 convert_to_mode (TYPE_MODE (integer_type_node),
2495 bytes_rtx,
2496 TREE_UNSIGNED (integer_type_node)),
2497 TYPE_MODE (integer_type_node));
2498 #endif
2499 }
2500
2501 \f
2502 /* Expand string/block move operations.
2503
2504 operands[0] is the pointer to the destination.
2505 operands[1] is the pointer to the source.
2506 operands[2] is the number of bytes to move.
2507 operands[3] is the alignment. */
2508
2509 void
2510 expand_block_move (operands)
2511 rtx operands[];
2512 {
2513 rtx bytes_rtx = operands[2];
2514 rtx align_rtx = operands[3];
2515 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2516 int bytes = (constp ? INTVAL (bytes_rtx) : 0);
2517 int align = INTVAL (align_rtx);
2518 rtx orig_src = operands[1];
2519 rtx orig_dest = operands[0];
2520 rtx src_reg;
2521 rtx dest_reg;
2522
2523 if (constp && bytes <= 0)
2524 return;
2525
2526 if (align > UNITS_PER_WORD)
2527 align = UNITS_PER_WORD;
2528
2529 /* Move the address into scratch registers. */
2530 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2531 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2532
2533 if (TARGET_MEMCPY)
2534 block_move_call (dest_reg, src_reg, bytes_rtx);
2535
2536 else if (constp && bytes <= 2*MAX_MOVE_BYTES)
2537 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
2538 dest_reg),
2539 change_address (orig_src, BLKmode,
2540 src_reg),
2541 bytes_rtx, align_rtx));
2542
2543 else if (constp && align >= UNITS_PER_WORD && optimize)
2544 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
2545
2546 else if (constp && optimize)
2547 {
2548 /* If the alignment is not word aligned, generate a test at
2549 runtime, to see whether things wound up aligned, and we
2550 can use the faster lw/sw instead ulw/usw. */
2551
2552 rtx temp = gen_reg_rtx (Pmode);
2553 rtx aligned_label = gen_label_rtx ();
2554 rtx join_label = gen_label_rtx ();
2555 int leftover = bytes % MAX_MOVE_BYTES;
2556
2557 bytes -= leftover;
2558
2559 if (TARGET_LONG64)
2560 {
2561 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
2562 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD-1)));
2563 emit_insn (gen_cmpdi (temp, const0_rtx));
2564 }
2565 else
2566 {
2567 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
2568 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD-1)));
2569 emit_insn (gen_cmpsi (temp, const0_rtx));
2570 }
2571 emit_jump_insn (gen_beq (aligned_label));
2572
2573 /* Unaligned loop. */
2574 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
2575 emit_jump_insn (gen_jump (join_label));
2576 emit_barrier ();
2577
2578 /* Aligned loop. */
2579 emit_label (aligned_label);
2580 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
2581 orig_src);
2582 emit_label (join_label);
2583
2584 /* Bytes at the end of the loop. */
2585 if (leftover)
2586 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
2587 dest_reg),
2588 change_address (orig_src, BLKmode,
2589 src_reg),
2590 GEN_INT (leftover),
2591 GEN_INT (align)));
2592 }
2593
2594 else
2595 block_move_call (dest_reg, src_reg, bytes_rtx);
2596 }
2597
2598 \f
2599 /* Emit load/stores for a small constant block_move.
2600
2601 operands[0] is the memory address of the destination.
2602 operands[1] is the memory address of the source.
2603 operands[2] is the number of bytes to move.
2604 operands[3] is the alignment.
2605 operands[4] is a temp register.
2606 operands[5] is a temp register.
2607 ...
2608 operands[3+num_regs] is the last temp register.
2609
2610 The block move type can be one of the following:
2611 BLOCK_MOVE_NORMAL Do all of the block move.
2612 BLOCK_MOVE_NOT_LAST Do all but the last store.
2613 BLOCK_MOVE_LAST Do just the last store. */
2614
2615 char *
2616 output_block_move (insn, operands, num_regs, move_type)
2617 rtx insn;
2618 rtx operands[];
2619 int num_regs;
2620 enum block_move_type move_type;
2621 {
2622 rtx dest_reg = XEXP (operands[0], 0);
2623 rtx src_reg = XEXP (operands[1], 0);
2624 int bytes = INTVAL (operands[2]);
2625 int align = INTVAL (operands[3]);
2626 int num = 0;
2627 int offset = 0;
2628 int use_lwl_lwr = FALSE;
2629 int last_operand = num_regs+4;
2630 int safe_regs = 4;
2631 int i;
2632 rtx xoperands[10];
2633
2634 struct {
2635 char *load; /* load insn without nop */
2636 char *load_nop; /* load insn with trailing nop */
2637 char *store; /* store insn */
2638 char *final; /* if last_store used: NULL or swr */
2639 char *last_store; /* last store instruction */
2640 int offset; /* current offset */
2641 enum machine_mode mode; /* mode to use on (MEM) */
2642 } load_store[4];
2643
2644 /* Detect a bug in GCC, where it can give us a register
2645 the same as one of the addressing registers and reduce
2646 the number of registers available. */
2647 for (i = 4;
2648 i < last_operand && safe_regs < (sizeof(xoperands) / sizeof(xoperands[0]));
2649 i++)
2650 {
2651 if (!reg_mentioned_p (operands[i], operands[0])
2652 && !reg_mentioned_p (operands[i], operands[1]))
2653
2654 xoperands[safe_regs++] = operands[i];
2655 }
2656
2657 if (safe_regs < last_operand)
2658 {
2659 xoperands[0] = operands[0];
2660 xoperands[1] = operands[1];
2661 xoperands[2] = operands[2];
2662 xoperands[3] = operands[3];
2663 return output_block_move (insn, xoperands, safe_regs-4, move_type);
2664 }
2665
2666 /* If we are given global or static addresses, and we would be
2667 emitting a few instructions, try to save time by using a
2668 temporary register for the pointer. */
2669 if (num_regs > 2 && (bytes > 2*align || move_type != BLOCK_MOVE_NORMAL))
2670 {
2671 if (CONSTANT_P (src_reg))
2672 {
2673 if (TARGET_STATS)
2674 mips_count_memory_refs (operands[1], 1);
2675
2676 src_reg = operands[ 3 + num_regs-- ];
2677 if (move_type != BLOCK_MOVE_LAST)
2678 {
2679 xoperands[1] = operands[1];
2680 xoperands[0] = src_reg;
2681 if (Pmode == DImode)
2682 output_asm_insn ("dla\t%0,%1", xoperands);
2683 else
2684 output_asm_insn ("la\t%0,%1", xoperands);
2685 }
2686 }
2687
2688 if (CONSTANT_P (dest_reg))
2689 {
2690 if (TARGET_STATS)
2691 mips_count_memory_refs (operands[0], 1);
2692
2693 dest_reg = operands[ 3 + num_regs-- ];
2694 if (move_type != BLOCK_MOVE_LAST)
2695 {
2696 xoperands[1] = operands[0];
2697 xoperands[0] = dest_reg;
2698 if (Pmode == DImode)
2699 output_asm_insn ("dla\t%0,%1", xoperands);
2700 else
2701 output_asm_insn ("la\t%0,%1", xoperands);
2702 }
2703 }
2704 }
2705
2706 /* ??? We really shouldn't get any LO_SUM addresses here, because they
2707 are not offsettable, however, offsettable_address_p says they are
2708 offsettable. I think this is a bug in offsettable_address_p.
2709 For expediency, we fix this by just loading the address into a register
2710 if we happen to get one. */
2711
2712 if (GET_CODE (src_reg) == LO_SUM)
2713 {
2714 src_reg = operands[ 3 + num_regs-- ];
2715 if (move_type != BLOCK_MOVE_LAST)
2716 {
2717 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
2718 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
2719 xoperands[0] = src_reg;
2720 if (Pmode == DImode)
2721 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
2722 else
2723 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
2724 }
2725 }
2726
2727 if (GET_CODE (dest_reg) == LO_SUM)
2728 {
2729 dest_reg = operands[ 3 + num_regs-- ];
2730 if (move_type != BLOCK_MOVE_LAST)
2731 {
2732 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
2733 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
2734 xoperands[0] = dest_reg;
2735 if (Pmode == DImode)
2736 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
2737 else
2738 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
2739 }
2740 }
2741
2742 if (num_regs > (sizeof (load_store) / sizeof (load_store[0])))
2743 num_regs = (sizeof (load_store) / sizeof (load_store[0]));
2744
2745 else if (num_regs < 1)
2746 abort_with_insn (insn, "Cannot do block move, not enough scratch registers");
2747
2748 while (bytes > 0)
2749 {
2750 load_store[num].offset = offset;
2751
2752 if (TARGET_64BIT && bytes >= 8 && align >= 8)
2753 {
2754 load_store[num].load = "ld\t%0,%1";
2755 load_store[num].load_nop = "ld\t%0,%1%#";
2756 load_store[num].store = "sd\t%0,%1";
2757 load_store[num].last_store = "sd\t%0,%1";
2758 load_store[num].final = (char *)0;
2759 load_store[num].mode = DImode;
2760 offset += 8;
2761 bytes -= 8;
2762 }
2763
2764 /* ??? Fails because of a MIPS assembler bug? */
2765 else if (TARGET_64BIT && bytes >= 8)
2766 {
2767 if (BYTES_BIG_ENDIAN)
2768 {
2769 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
2770 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
2771 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
2772 load_store[num].last_store = "sdr\t%0,%2";
2773 load_store[num].final = "sdl\t%0,%1";
2774 }
2775 else
2776 {
2777 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
2778 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
2779 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
2780 load_store[num].last_store = "sdr\t%0,%1";
2781 load_store[num].final = "sdl\t%0,%2";
2782 }
2783 load_store[num].mode = DImode;
2784 offset += 8;
2785 bytes -= 8;
2786 use_lwl_lwr = TRUE;
2787 }
2788
2789 else if (bytes >= 4 && align >= 4)
2790 {
2791 load_store[num].load = "lw\t%0,%1";
2792 load_store[num].load_nop = "lw\t%0,%1%#";
2793 load_store[num].store = "sw\t%0,%1";
2794 load_store[num].last_store = "sw\t%0,%1";
2795 load_store[num].final = (char *)0;
2796 load_store[num].mode = SImode;
2797 offset += 4;
2798 bytes -= 4;
2799 }
2800
2801 else if (bytes >= 4)
2802 {
2803 if (BYTES_BIG_ENDIAN)
2804 {
2805 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
2806 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2807 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
2808 load_store[num].last_store = "swr\t%0,%2";
2809 load_store[num].final = "swl\t%0,%1";
2810 }
2811 else
2812 {
2813 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
2814 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2815 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
2816 load_store[num].last_store = "swr\t%0,%1";
2817 load_store[num].final = "swl\t%0,%2";
2818 }
2819 load_store[num].mode = SImode;
2820 offset += 4;
2821 bytes -= 4;
2822 use_lwl_lwr = TRUE;
2823 }
2824
2825 else if (bytes >= 2 && align >= 2)
2826 {
2827 load_store[num].load = "lh\t%0,%1";
2828 load_store[num].load_nop = "lh\t%0,%1%#";
2829 load_store[num].store = "sh\t%0,%1";
2830 load_store[num].last_store = "sh\t%0,%1";
2831 load_store[num].final = (char *)0;
2832 load_store[num].mode = HImode;
2833 offset += 2;
2834 bytes -= 2;
2835 }
2836
2837 else
2838 {
2839 load_store[num].load = "lb\t%0,%1";
2840 load_store[num].load_nop = "lb\t%0,%1%#";
2841 load_store[num].store = "sb\t%0,%1";
2842 load_store[num].last_store = "sb\t%0,%1";
2843 load_store[num].final = (char *)0;
2844 load_store[num].mode = QImode;
2845 offset++;
2846 bytes--;
2847 }
2848
2849 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
2850 {
2851 dslots_load_total++;
2852 dslots_load_filled++;
2853
2854 if (CONSTANT_P (src_reg))
2855 mips_count_memory_refs (src_reg, 1);
2856
2857 if (CONSTANT_P (dest_reg))
2858 mips_count_memory_refs (dest_reg, 1);
2859 }
2860
2861 /* Emit load/stores now if we have run out of registers or are
2862 at the end of the move. */
2863
2864 if (++num == num_regs || bytes == 0)
2865 {
2866 /* If only load/store, we need a NOP after the load. */
2867 if (num == 1)
2868 {
2869 load_store[0].load = load_store[0].load_nop;
2870 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
2871 dslots_load_filled--;
2872 }
2873
2874 if (move_type != BLOCK_MOVE_LAST)
2875 {
2876 for (i = 0; i < num; i++)
2877 {
2878 int offset;
2879
2880 if (!operands[i+4])
2881 abort ();
2882
2883 if (GET_MODE (operands[i+4]) != load_store[i].mode)
2884 operands[i+4] = gen_rtx (REG, load_store[i].mode, REGNO (operands[i+4]));
2885
2886 offset = load_store[i].offset;
2887 xoperands[0] = operands[i+4];
2888 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
2889 plus_constant (src_reg, offset));
2890
2891 if (use_lwl_lwr)
2892 {
2893 int extra_offset;
2894 extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
2895 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
2896 plus_constant (src_reg,
2897 extra_offset
2898 + offset));
2899 }
2900
2901 output_asm_insn (load_store[i].load, xoperands);
2902 }
2903 }
2904
2905 for (i = 0; i < num; i++)
2906 {
2907 int last_p = (i == num-1 && bytes == 0);
2908 int offset = load_store[i].offset;
2909
2910 xoperands[0] = operands[i+4];
2911 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
2912 plus_constant (dest_reg, offset));
2913
2914
2915 if (use_lwl_lwr)
2916 {
2917 int extra_offset;
2918 extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
2919 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
2920 plus_constant (dest_reg,
2921 extra_offset
2922 + offset));
2923 }
2924
2925 if (move_type == BLOCK_MOVE_NORMAL)
2926 output_asm_insn (load_store[i].store, xoperands);
2927
2928 else if (move_type == BLOCK_MOVE_NOT_LAST)
2929 {
2930 if (!last_p)
2931 output_asm_insn (load_store[i].store, xoperands);
2932
2933 else if (load_store[i].final != (char *)0)
2934 output_asm_insn (load_store[i].final, xoperands);
2935 }
2936
2937 else if (last_p)
2938 output_asm_insn (load_store[i].last_store, xoperands);
2939 }
2940
2941 num = 0; /* reset load_store */
2942 use_lwl_lwr = FALSE;
2943 }
2944 }
2945
2946 return "";
2947 }
2948
2949 \f
2950 /* Argument support functions. */
2951
2952 /* Initialize CUMULATIVE_ARGS for a function. */
2953
2954 void
2955 init_cumulative_args (cum, fntype, libname)
2956 CUMULATIVE_ARGS *cum; /* argument info to initialize */
2957 tree fntype; /* tree ptr for function decl */
2958 rtx libname; /* SYMBOL_REF of library name or 0 */
2959 {
2960 static CUMULATIVE_ARGS zero_cum;
2961 tree param, next_param;
2962
2963 if (TARGET_DEBUG_E_MODE)
2964 {
2965 fprintf (stderr, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
2966 if (!fntype)
2967 fputc ('\n', stderr);
2968
2969 else
2970 {
2971 tree ret_type = TREE_TYPE (fntype);
2972 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
2973 tree_code_name[ (int)TREE_CODE (fntype) ],
2974 tree_code_name[ (int)TREE_CODE (ret_type) ]);
2975 }
2976 }
2977
2978 *cum = zero_cum;
2979
2980 /* Determine if this function has variable arguments. This is
2981 indicated by the last argument being 'void_type_mode' if there
2982 are no variable arguments. The standard MIPS calling sequence
2983 passes all arguments in the general purpose registers in this
2984 case. */
2985
2986 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
2987 param != (tree)0;
2988 param = next_param)
2989 {
2990 next_param = TREE_CHAIN (param);
2991 if (next_param == (tree)0 && TREE_VALUE (param) != void_type_node)
2992 cum->gp_reg_found = 1;
2993 }
2994 }
2995
2996 /* Advance the argument to the next argument position. */
2997
2998 void
2999 function_arg_advance (cum, mode, type, named)
3000 CUMULATIVE_ARGS *cum; /* current arg information */
3001 enum machine_mode mode; /* current arg mode */
3002 tree type; /* type of the argument or 0 if lib support */
3003 int named; /* whether or not the argument was named */
3004 {
3005 if (TARGET_DEBUG_E_MODE)
3006 fprintf (stderr,
3007 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
3008 cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode),
3009 type, named);
3010
3011 cum->arg_number++;
3012 switch (mode)
3013 {
3014 case VOIDmode:
3015 break;
3016
3017 default:
3018 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3019 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3020 abort ();
3021 cum->gp_reg_found = 1;
3022 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3023 / UNITS_PER_WORD);
3024 break;
3025
3026 case BLKmode:
3027 cum->gp_reg_found = 1;
3028 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3029 / UNITS_PER_WORD);
3030 break;
3031
3032 case SFmode:
3033 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3034 cum->fp_arg_words++;
3035 else
3036 cum->arg_words++;
3037 break;
3038
3039 case DFmode:
3040 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3041 cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3042 else
3043 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3044 break;
3045
3046 case DImode:
3047 cum->gp_reg_found = 1;
3048 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3049 break;
3050
3051 case QImode:
3052 case HImode:
3053 case SImode:
3054 cum->gp_reg_found = 1;
3055 cum->arg_words++;
3056 break;
3057 }
3058 }
3059
3060 /* Return an RTL expression containing the register for the given mode,
3061 or 0 if the argument is to be passed on the stack. */
3062
3063 struct rtx_def *
3064 function_arg (cum, mode, type, named)
3065 CUMULATIVE_ARGS *cum; /* current arg information */
3066 enum machine_mode mode; /* current arg mode */
3067 tree type; /* type of the argument or 0 if lib support */
3068 int named; /* != 0 for normal args, == 0 for ... args */
3069 {
3070 rtx ret;
3071 int regbase = -1;
3072 int bias = 0;
3073 int *arg_words = &cum->arg_words;
3074 int struct_p = ((type != (tree)0)
3075 && (TREE_CODE (type) == RECORD_TYPE
3076 || TREE_CODE (type) == UNION_TYPE));
3077
3078 if (TARGET_DEBUG_E_MODE)
3079 fprintf (stderr,
3080 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
3081 cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode),
3082 type, named);
3083
3084 cum->last_arg_fp = 0;
3085 switch (mode)
3086 {
3087 case SFmode:
3088 if (mips_abi == ABI_32)
3089 {
3090 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
3091 regbase = GP_ARG_FIRST;
3092 else
3093 {
3094 regbase = FP_ARG_FIRST;
3095 /* If the first arg was a float in a floating point register,
3096 then set bias to align this float arg properly. */
3097 if (cum->arg_words == 1)
3098 bias = 1;
3099 }
3100 }
3101 else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3102 {
3103 if (! TARGET_64BIT)
3104 cum->fp_arg_words += cum->fp_arg_words & 1;
3105 cum->last_arg_fp = 1;
3106 arg_words = &cum->fp_arg_words;
3107 regbase = FP_ARG_FIRST;
3108 }
3109 else
3110 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
3111 break;
3112
3113 case DFmode:
3114 if (! TARGET_64BIT)
3115 {
3116 if (mips_abi == ABI_EABI
3117 && ! TARGET_SOFT_FLOAT
3118 && ! TARGET_SINGLE_FLOAT)
3119 cum->fp_arg_words += cum->fp_arg_words & 1;
3120 else
3121 cum->arg_words += cum->arg_words & 1;
3122 }
3123 if (mips_abi == ABI_32)
3124 regbase = ((cum->gp_reg_found
3125 || TARGET_SOFT_FLOAT
3126 || TARGET_SINGLE_FLOAT
3127 || cum->arg_number >= 2)
3128 ? GP_ARG_FIRST
3129 : FP_ARG_FIRST);
3130 else if (mips_abi == ABI_EABI
3131 && ! TARGET_SOFT_FLOAT
3132 && ! TARGET_SINGLE_FLOAT)
3133 {
3134 cum->last_arg_fp = 1;
3135 arg_words = &cum->fp_arg_words;
3136 regbase = FP_ARG_FIRST;
3137 }
3138 else
3139 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
3140 ? GP_ARG_FIRST : FP_ARG_FIRST);
3141 break;
3142
3143 default:
3144 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3145 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3146 abort ();
3147
3148 /* Drops through. */
3149 case BLKmode:
3150 if (type != (tree)0 && TYPE_ALIGN (type) > BITS_PER_WORD
3151 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3152 cum->arg_words += (cum->arg_words & 1);
3153 regbase = GP_ARG_FIRST;
3154 break;
3155
3156 case VOIDmode:
3157 case QImode:
3158 case HImode:
3159 case SImode:
3160 regbase = GP_ARG_FIRST;
3161 break;
3162
3163 case DImode:
3164 if (! TARGET_64BIT)
3165 cum->arg_words += (cum->arg_words & 1);
3166 regbase = GP_ARG_FIRST;
3167 }
3168
3169 if (*arg_words >= MAX_ARGS_IN_REGISTERS)
3170 {
3171 if (TARGET_DEBUG_E_MODE)
3172 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
3173
3174 ret = (rtx)0;
3175 }
3176 else
3177 {
3178 if (regbase == -1)
3179 abort ();
3180
3181 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
3182 || mips_abi == ABI_EABI || ! named)
3183 ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
3184 else
3185 {
3186 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3187 structure contains a double in its entirety, then that 64 bit
3188 chunk is passed in a floating point register. */
3189 tree field;
3190
3191 /* First check to see if there is any such field. */
3192 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3193 if (TREE_CODE (field) == FIELD_DECL
3194 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3195 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3196 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3197 % BITS_PER_WORD == 0))
3198 break;
3199
3200 if (! field)
3201 ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
3202 else
3203 {
3204 /* Now handle the special case by returning a PARALLEL
3205 indicating where each 64 bit chunk goes. */
3206 int chunks;
3207 int bitpos;
3208 int regno;
3209 int i;
3210
3211 /* ??? If this is a packed structure, then the last hunk won't
3212 be 64 bits. */
3213
3214 /* ??? If this is a structure with a single double field,
3215 it would be more convenient to return (REG:DI %fX) than
3216 a parallel. However, we would have to modify the mips
3217 backend to allow DImode values in fp registers. */
3218
3219 chunks = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_WORD;
3220 if (chunks + *arg_words + bias > MAX_ARGS_IN_REGISTERS)
3221 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
3222
3223 /* assign_parms checks the mode of ENTRY_PARM, so we must
3224 use the actual mode here. */
3225 ret = gen_rtx (PARALLEL, mode, rtvec_alloc (chunks));
3226
3227 bitpos = 0;
3228 regno = regbase + *arg_words + bias;
3229 field = TYPE_FIELDS (type);
3230 for (i = 0; i < chunks; i++)
3231 {
3232 rtx reg;
3233
3234 for (; field; field = TREE_CHAIN (field))
3235 if (TREE_CODE (field) == FIELD_DECL
3236 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3237 >= bitpos))
3238 break;
3239
3240 if (field
3241 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) == bitpos
3242 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3243 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3244 reg = gen_rtx (REG, DFmode,
3245 regno + FP_ARG_FIRST - GP_ARG_FIRST);
3246 else
3247 reg = gen_rtx (REG, word_mode, regno);
3248
3249 XVECEXP (ret, 0, i) = gen_rtx (EXPR_LIST, VOIDmode, reg,
3250 GEN_INT (bitpos / BITS_PER_UNIT));
3251
3252 bitpos += 64;
3253 regno++;
3254 }
3255 }
3256 }
3257
3258 if (TARGET_DEBUG_E_MODE)
3259 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
3260 struct_p ? ", [struct]" : "");
3261
3262 /* The following is a hack in order to pass 1 byte structures
3263 the same way that the MIPS compiler does (namely by passing
3264 the structure in the high byte or half word of the register).
3265 This also makes varargs work. If we have such a structure,
3266 we save the adjustment RTL, and the call define expands will
3267 emit them. For the VOIDmode argument (argument after the
3268 last real argument), pass back a parallel vector holding each
3269 of the adjustments. */
3270
3271 /* ??? function_arg can be called more than once for each argument.
3272 As a result, we compute more adjustments than we need here.
3273 See the CUMULATIVE_ARGS definition in mips.h. */
3274
3275 /* ??? This scheme requires everything smaller than the word size to
3276 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3277 that would mean every int needs to be shifted left, which is very
3278 inefficient. Let's not carry this compatibility to the 64 bit
3279 calling convention for now. */
3280
3281 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
3282 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3283 {
3284 rtx amount = GEN_INT (BITS_PER_WORD
3285 - int_size_in_bytes (type) * BITS_PER_UNIT);
3286 rtx reg = gen_rtx (REG, word_mode, regbase + *arg_words + bias);
3287 if (TARGET_64BIT)
3288 cum->adjust[ cum->num_adjusts++ ] = gen_ashldi3 (reg, reg, amount);
3289 else
3290 cum->adjust[ cum->num_adjusts++ ] = gen_ashlsi3 (reg, reg, amount);
3291 }
3292 }
3293
3294 if (mode == VOIDmode && cum->num_adjusts > 0)
3295 ret = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (cum->num_adjusts, cum->adjust));
3296
3297 return ret;
3298 }
3299
3300
3301 int
3302 function_arg_partial_nregs (cum, mode, type, named)
3303 CUMULATIVE_ARGS *cum; /* current arg information */
3304 enum machine_mode mode; /* current arg mode */
3305 tree type; /* type of the argument or 0 if lib support */
3306 int named; /* != 0 for normal args, == 0 for ... args */
3307 {
3308 if ((mode == BLKmode
3309 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3310 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3311 && cum->arg_words < MAX_ARGS_IN_REGISTERS
3312 && mips_abi != ABI_EABI)
3313 {
3314 int words;
3315 if (mode == BLKmode)
3316 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3317 / UNITS_PER_WORD);
3318 else
3319 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3320
3321 if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS)
3322 return 0; /* structure fits in registers */
3323
3324 if (TARGET_DEBUG_E_MODE)
3325 fprintf (stderr, "function_arg_partial_nregs = %d\n",
3326 MAX_ARGS_IN_REGISTERS - cum->arg_words);
3327
3328 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
3329 }
3330
3331 else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1
3332 && ! TARGET_64BIT
3333 && mips_abi != ABI_EABI)
3334 {
3335 if (TARGET_DEBUG_E_MODE)
3336 fprintf (stderr, "function_arg_partial_nregs = 1\n");
3337
3338 return 1;
3339 }
3340
3341 return 0;
3342 }
3343 \f
3344 /* Abort after printing out a specific insn. */
3345
3346 void
3347 abort_with_insn (insn, reason)
3348 rtx insn;
3349 char *reason;
3350 {
3351 error (reason);
3352 debug_rtx (insn);
3353 abort ();
3354 }
3355
3356 /* Write a message to stderr (for use in macros expanded in files that do not
3357 include stdio.h). */
3358
3359 void
3360 trace (s, s1, s2)
3361 char *s, *s1, *s2;
3362 {
3363 fprintf (stderr, s, s1, s2);
3364 }
3365
3366 \f
3367 #ifdef SIGINFO
3368
3369 static void
3370 siginfo (signo)
3371 int signo;
3372 {
3373 fprintf (stderr, "compiling '%s' in '%s'\n",
3374 (current_function_name != (char *)0) ? current_function_name : "<toplevel>",
3375 (current_function_file != (char *)0) ? current_function_file : "<no file>");
3376 fflush (stderr);
3377 }
3378 #endif /* SIGINFO */
3379
3380 \f
3381 /* Set up the threshold for data to go into the small data area, instead
3382 of the normal data area, and detect any conflicts in the switches. */
3383
3384 void
3385 override_options ()
3386 {
3387 register int i, start;
3388 register int regno;
3389 register enum machine_mode mode;
3390
3391 mips_section_threshold = (g_switch_set) ? g_switch_value : MIPS_DEFAULT_GVALUE;
3392
3393 if (mips_section_threshold <= 0)
3394 target_flags &= ~MASK_GPOPT;
3395 else if (optimize)
3396 target_flags |= MASK_GPOPT;
3397
3398 /* Get the architectural level. */
3399 if (mips_isa_string == (char *)0)
3400 {
3401 #ifdef MIPS_ISA_DEFAULT
3402 mips_isa = MIPS_ISA_DEFAULT;
3403 #else
3404 mips_isa = 1;
3405 #endif
3406 }
3407
3408 else if (isdigit (*mips_isa_string))
3409 {
3410 mips_isa = atoi (mips_isa_string);
3411 if (mips_isa < 1 || mips_isa > 4)
3412 {
3413 error ("-mips%d not supported", mips_isa);
3414 mips_isa = 1;
3415 }
3416 }
3417
3418 else
3419 {
3420 error ("bad value (%s) for -mips switch", mips_isa_string);
3421 mips_isa = 1;
3422 }
3423
3424 #ifdef MIPS_ABI_DEFAULT
3425 /* Get the ABI to use. Currently this code is only used for Irix 6. */
3426 if (mips_abi_string == (char *) 0)
3427 mips_abi = MIPS_ABI_DEFAULT;
3428 else if (! strcmp (mips_abi_string, "32")
3429 || ! strcmp (mips_abi_string, "o32"))
3430 mips_abi = ABI_32;
3431 else if (! strcmp (mips_abi_string, "n32"))
3432 mips_abi = ABI_N32;
3433 else if (! strcmp (mips_abi_string, "64")
3434 || ! strcmp (mips_abi_string, "n64"))
3435 mips_abi = ABI_64;
3436 else if (! strcmp (mips_abi_string, "eabi"))
3437 mips_abi = ABI_EABI;
3438 else
3439 error ("bad value (%s) for -mabi= switch", mips_abi_string);
3440
3441 /* A specified ISA defaults the ABI if it was not specified. */
3442 if (mips_abi_string == 0 && mips_isa_string && mips_abi != ABI_EABI)
3443 {
3444 if (mips_isa <= 2)
3445 mips_abi = ABI_32;
3446 else
3447 mips_abi = ABI_64;
3448 }
3449 /* A specified ABI defaults the ISA if it was not specified. */
3450 else if (mips_isa_string == 0 && mips_abi_string && mips_abi != ABI_EABI)
3451 {
3452 if (mips_abi == ABI_32)
3453 mips_isa = 1;
3454 else if (mips_abi == ABI_N32)
3455 mips_isa = 3;
3456 else
3457 mips_isa = 4;
3458 }
3459 /* If both ABI and ISA were specified, check for conflicts. */
3460 else if (mips_isa_string && mips_abi_string)
3461 {
3462 if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64))
3463 || (mips_isa >= 3 && mips_abi == ABI_32))
3464 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
3465 }
3466
3467 /* Override TARGET_DEFAULT if necessary. */
3468 if (mips_abi == ABI_32)
3469 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
3470
3471 /* In the EABI in 64 bit mode, longs and pointers are 64 bits. */
3472 if (mips_abi == ABI_EABI && TARGET_64BIT)
3473 target_flags |= MASK_LONG64;
3474
3475 /* ??? This doesn't work yet, so don't let people try to use it. */
3476 if (mips_abi == ABI_32)
3477 error ("The -mabi=32 support does not work yet.");
3478 #else
3479 if (mips_abi_string)
3480 error ("This target does not support the -mabi switch.");
3481 #endif
3482
3483 #ifdef MIPS_CPU_STRING_DEFAULT
3484 /* ??? There is a minor inconsistency here. If the user specifies an ISA
3485 greater than that supported by the default processor, then the user gets
3486 an error. Normally, the compiler will just default to the base level cpu
3487 for the indicated isa. */
3488 if (mips_cpu_string == (char *)0)
3489 mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
3490 #endif
3491
3492 /* Identify the processor type */
3493 if (mips_cpu_string == (char *)0
3494 || !strcmp (mips_cpu_string, "default")
3495 || !strcmp (mips_cpu_string, "DEFAULT"))
3496 {
3497 switch (mips_isa)
3498 {
3499 default:
3500 mips_cpu_string = "3000";
3501 mips_cpu = PROCESSOR_R3000;
3502 break;
3503 case 2:
3504 mips_cpu_string = "6000";
3505 mips_cpu = PROCESSOR_R6000;
3506 break;
3507 case 3:
3508 mips_cpu_string = "4000";
3509 mips_cpu = PROCESSOR_R4000;
3510 break;
3511 case 4:
3512 mips_cpu_string = "8000";
3513 mips_cpu = PROCESSOR_R8000;
3514 break;
3515 }
3516 }
3517
3518 else
3519 {
3520 char *p = mips_cpu_string;
3521 int seen_v = FALSE;
3522
3523 /* We need to cope with the various "vr" prefixes for the NEC 4300
3524 and 4100 processors. */
3525 if (*p == 'v' || *p == 'V')
3526 {
3527 seen_v = TRUE;
3528 p++;
3529 }
3530 if (*p == 'r' || *p == 'R')
3531 p++;
3532
3533 /* Since there is no difference between a R2000 and R3000 in
3534 terms of the scheduler, we collapse them into just an R3000. */
3535
3536 mips_cpu = PROCESSOR_DEFAULT;
3537 switch (*p)
3538 {
3539 case '2':
3540 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
3541 mips_cpu = PROCESSOR_R3000;
3542 break;
3543
3544 case '3':
3545 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
3546 mips_cpu = PROCESSOR_R3000;
3547 break;
3548
3549 case '4':
3550 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
3551 mips_cpu = PROCESSOR_R4000;
3552 /* The vr4100 is a non-FP ISA III processor with some extra
3553 instructions. */
3554 else if (!strcmp (p, "4100")) {
3555 mips_cpu = PROCESSOR_R4100;
3556 target_flags |= MASK_SOFT_FLOAT ;
3557 }
3558 /* The vr4300 is a standard ISA III processor, but with a different
3559 pipeline. */
3560 else if (!strcmp (p, "4300"))
3561 mips_cpu = PROCESSOR_R4300;
3562 /* The r4400 is exactly the same as the r4000 from the compiler's
3563 viewpoint. */
3564 else if (!strcmp (p, "4400"))
3565 mips_cpu = PROCESSOR_R4000;
3566 else if (!strcmp (p, "4600"))
3567 mips_cpu = PROCESSOR_R4600;
3568 else if (!strcmp (p, "4650"))
3569 mips_cpu = PROCESSOR_R4650;
3570 break;
3571
3572 case '5':
3573 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
3574 mips_cpu = PROCESSOR_R5000;
3575 break;
3576
3577 case '6':
3578 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
3579 mips_cpu = PROCESSOR_R6000;
3580 break;
3581
3582 case '8':
3583 if (!strcmp (p, "8000"))
3584 mips_cpu = PROCESSOR_R8000;
3585 break;
3586
3587 case 'o':
3588 if (!strcmp (p, "orion"))
3589 mips_cpu = PROCESSOR_R4600;
3590 break;
3591 }
3592
3593 if (seen_v
3594 && mips_cpu != PROCESSOR_R4300
3595 && mips_cpu != PROCESSOR_R4100
3596 && mips_cpu != PROCESSOR_R5000)
3597 mips_cpu = PROCESSOR_DEFAULT;
3598
3599 if (mips_cpu == PROCESSOR_DEFAULT)
3600 {
3601 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
3602 mips_cpu_string = "default";
3603 }
3604 }
3605
3606 if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
3607 || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
3608 || ((mips_cpu == PROCESSOR_R4000
3609 || mips_cpu == PROCESSOR_R4100
3610 || mips_cpu == PROCESSOR_R4300
3611 || mips_cpu == PROCESSOR_R4600
3612 || mips_cpu == PROCESSOR_R4650)
3613 && mips_isa > 3))
3614 error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
3615
3616 /* make sure sizes of ints/longs/etc. are ok */
3617 if (mips_isa < 3)
3618 {
3619 if (TARGET_INT64)
3620 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3621
3622 else if (TARGET_LONG64)
3623 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3624
3625 else if (TARGET_FLOAT64)
3626 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3627
3628 else if (TARGET_64BIT)
3629 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3630 }
3631
3632 if (mips_abi != ABI_32)
3633 flag_pcc_struct_return = 0;
3634
3635 /* Tell halfpic.c that we have half-pic code if we do. */
3636 if (TARGET_HALF_PIC)
3637 HALF_PIC_INIT ();
3638
3639 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3640 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3641 /* ??? -non_shared turns off pic code generation, but this is not
3642 implemented. */
3643 if (TARGET_ABICALLS)
3644 {
3645 mips_abicalls = MIPS_ABICALLS_YES;
3646 flag_pic = 1;
3647 if (mips_section_threshold > 0)
3648 warning ("-G is incompatible with PIC code which is the default");
3649 }
3650 else
3651 mips_abicalls = MIPS_ABICALLS_NO;
3652
3653 /* -membedded-pic is a form of PIC code suitable for embedded
3654 systems. All calls are made using PC relative addressing, and
3655 all data is addressed using the $gp register. This requires gas,
3656 which does most of the work, and GNU ld, which automatically
3657 expands PC relative calls which are out of range into a longer
3658 instruction sequence. All gcc really does differently is
3659 generate a different sequence for a switch. */
3660 if (TARGET_EMBEDDED_PIC)
3661 {
3662 flag_pic = 1;
3663 if (TARGET_ABICALLS)
3664 warning ("-membedded-pic and -mabicalls are incompatible");
3665 if (g_switch_set)
3666 warning ("-G and -membedded-pic are incompatible");
3667 /* Setting mips_section_threshold is not required, because gas
3668 will force everything to be GP addressable anyhow, but
3669 setting it will cause gcc to make better estimates of the
3670 number of instructions required to access a particular data
3671 item. */
3672 mips_section_threshold = 0x7fffffff;
3673 }
3674
3675 /* This optimization requires a linker that can support a R_MIPS_LO16
3676 relocation which is not immediately preceeded by a R_MIPS_HI16 relocation.
3677 GNU ld has this support, but not all other MIPS linkers do, so we enable
3678 this optimization only if the user requests it, or if GNU ld is the
3679 standard linker for this configuration. */
3680 /* ??? This does not work when target addresses are DImode.
3681 This is because we are missing DImode high/lo_sum patterns. */
3682 if (TARGET_GAS && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
3683 && Pmode == SImode)
3684 mips_split_addresses = 1;
3685 else
3686 mips_split_addresses = 0;
3687
3688 /* -mrnames says to use the MIPS software convention for register
3689 names instead of the hardware names (ie, $a0 instead of $4).
3690 We do this by switching the names in mips_reg_names, which the
3691 reg_names points into via the REGISTER_NAMES macro. */
3692
3693 if (TARGET_NAME_REGS)
3694 bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names, sizeof (mips_reg_names));
3695
3696 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3697 is currently being compiled. */
3698 #ifdef SIGINFO
3699 if (getenv ("GCC_SIGINFO") != (char *)0)
3700 {
3701 struct sigaction action;
3702 action.sa_handler = siginfo;
3703 action.sa_mask = 0;
3704 action.sa_flags = SA_RESTART;
3705 sigaction (SIGINFO, &action, (struct sigaction *)0);
3706 }
3707 #endif
3708
3709 #if defined(_IOLBF)
3710 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3711 /* If -mstats and -quiet, make stderr line buffered. */
3712 if (quiet_flag && TARGET_STATS)
3713 setvbuf (stderr, (char *)0, _IOLBF, BUFSIZ);
3714 #endif
3715 #endif
3716
3717 /* Initialize the high and low values for legitimate floating point
3718 constants. Rather than trying to get the accuracy down to the
3719 last bit, just use approximate ranges. */
3720 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
3721 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
3722 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
3723 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
3724
3725 mips_print_operand_punct['?'] = TRUE;
3726 mips_print_operand_punct['#'] = TRUE;
3727 mips_print_operand_punct['&'] = TRUE;
3728 mips_print_operand_punct['!'] = TRUE;
3729 mips_print_operand_punct['*'] = TRUE;
3730 mips_print_operand_punct['@'] = TRUE;
3731 mips_print_operand_punct['.'] = TRUE;
3732 mips_print_operand_punct['('] = TRUE;
3733 mips_print_operand_punct[')'] = TRUE;
3734 mips_print_operand_punct['['] = TRUE;
3735 mips_print_operand_punct[']'] = TRUE;
3736 mips_print_operand_punct['<'] = TRUE;
3737 mips_print_operand_punct['>'] = TRUE;
3738 mips_print_operand_punct['{'] = TRUE;
3739 mips_print_operand_punct['}'] = TRUE;
3740 mips_print_operand_punct['^'] = TRUE;
3741
3742 mips_char_to_class['d'] = GR_REGS;
3743 mips_char_to_class['f'] = ((TARGET_HARD_FLOAT) ? FP_REGS : NO_REGS);
3744 mips_char_to_class['h'] = HI_REG;
3745 mips_char_to_class['l'] = LO_REG;
3746 mips_char_to_class['a'] = HILO_REG;
3747 mips_char_to_class['x'] = MD_REGS;
3748 mips_char_to_class['b'] = ALL_REGS;
3749 mips_char_to_class['y'] = GR_REGS;
3750 mips_char_to_class['z'] = ST_REGS;
3751
3752 /* Set up array to map GCC register number to debug register number.
3753 Ignore the special purpose register numbers. */
3754
3755 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3756 mips_dbx_regno[i] = -1;
3757
3758 start = GP_DBX_FIRST - GP_REG_FIRST;
3759 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
3760 mips_dbx_regno[i] = i + start;
3761
3762 start = FP_DBX_FIRST - FP_REG_FIRST;
3763 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
3764 mips_dbx_regno[i] = i + start;
3765
3766 /* Set up array giving whether a given register can hold a given mode.
3767 At present, restrict ints from being in FP registers, because reload
3768 is a little enthusiastic about storing extra values in FP registers,
3769 and this is not good for things like OS kernels. Also, due to the
3770 mandatory delay, it is as fast to load from cached memory as to move
3771 from the FP register. */
3772
3773 for (mode = VOIDmode;
3774 mode != MAX_MACHINE_MODE;
3775 mode = (enum machine_mode)((int)mode + 1))
3776 {
3777 register int size = GET_MODE_SIZE (mode);
3778 register enum mode_class class = GET_MODE_CLASS (mode);
3779
3780 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
3781 {
3782 register int temp;
3783
3784 if (mode == CCmode)
3785 {
3786 if (mips_isa < 4)
3787 temp = (regno == FPSW_REGNUM);
3788 else
3789 temp = (ST_REG_P (regno)
3790 || GP_REG_P (regno)
3791 || FP_REG_P (regno));
3792 }
3793
3794 else if (GP_REG_P (regno))
3795 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
3796
3797 else if (FP_REG_P (regno))
3798 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
3799 && (class == MODE_FLOAT
3800 || class == MODE_COMPLEX_FLOAT
3801 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
3802 && (! TARGET_SINGLE_FLOAT || size <= 4));
3803
3804 else if (MD_REG_P (regno))
3805 temp = (class == MODE_INT
3806 && (size <= UNITS_PER_WORD
3807 || (regno == MD_REG_FIRST && size == 2 * UNITS_PER_WORD)));
3808
3809 else
3810 temp = FALSE;
3811
3812 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
3813 }
3814 }
3815 }
3816
3817 \f
3818 /*
3819 * The MIPS debug format wants all automatic variables and arguments
3820 * to be in terms of the virtual frame pointer (stack pointer before
3821 * any adjustment in the function), while the MIPS 3.0 linker wants
3822 * the frame pointer to be the stack pointer after the initial
3823 * adjustment. So, we do the adjustment here. The arg pointer (which
3824 * is eliminated) points to the virtual frame pointer, while the frame
3825 * pointer (which may be eliminated) points to the stack pointer after
3826 * the initial adjustments.
3827 */
3828
3829 int
3830 mips_debugger_offset (addr, offset)
3831 rtx addr;
3832 int offset;
3833 {
3834 rtx offset2 = const0_rtx;
3835 rtx reg = eliminate_constant_term (addr, &offset2);
3836
3837 if (!offset)
3838 offset = INTVAL (offset2);
3839
3840 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx)
3841 {
3842 int frame_size = (!current_frame_info.initialized)
3843 ? compute_frame_size (get_frame_size ())
3844 : current_frame_info.total_size;
3845
3846 offset = offset - frame_size;
3847 }
3848 /* sdbout_parms does not want this to crash for unrecognized cases. */
3849 #if 0
3850 else if (reg != arg_pointer_rtx)
3851 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
3852 #endif
3853
3854 return offset;
3855 }
3856
3857 \f
3858 /* A C compound statement to output to stdio stream STREAM the
3859 assembler syntax for an instruction operand X. X is an RTL
3860 expression.
3861
3862 CODE is a value that can be used to specify one of several ways
3863 of printing the operand. It is used when identical operands
3864 must be printed differently depending on the context. CODE
3865 comes from the `%' specification that was used to request
3866 printing of the operand. If the specification was just `%DIGIT'
3867 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3868 is the ASCII code for LTR.
3869
3870 If X is a register, this macro should print the register's name.
3871 The names can be found in an array `reg_names' whose type is
3872 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3873
3874 When the machine description has a specification `%PUNCT' (a `%'
3875 followed by a punctuation character), this macro is called with
3876 a null pointer for X and the punctuation character for CODE.
3877
3878 The MIPS specific codes are:
3879
3880 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3881 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3882 'd' output integer constant in decimal,
3883 'z' if the operand is 0, use $0 instead of normal operand.
3884 'D' print second register of double-word register operand.
3885 'L' print low-order register of double-word register operand.
3886 'M' print high-order register of double-word register operand.
3887 'C' print part of opcode for a branch condition.
3888 'N' print part of opcode for a branch condition, inverted.
3889 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3890 'B' print 'z' for EQ, 'n' for NE
3891 'b' print 'n' for EQ, 'z' for NE
3892 'T' print 'f' for EQ, 't' for NE
3893 't' print 't' for EQ, 'f' for NE
3894 'Z' print register and a comma, but print nothing for $fcc0
3895 '(' Turn on .set noreorder
3896 ')' Turn on .set reorder
3897 '[' Turn on .set noat
3898 ']' Turn on .set at
3899 '<' Turn on .set nomacro
3900 '>' Turn on .set macro
3901 '{' Turn on .set volatile (not GAS)
3902 '}' Turn on .set novolatile (not GAS)
3903 '&' Turn on .set noreorder if filling delay slots
3904 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3905 '!' Turn on .set nomacro if filling delay slots
3906 '#' Print nop if in a .set noreorder section.
3907 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3908 '@' Print the name of the assembler temporary register (at or $1).
3909 '.' Print the name of the register with a hard-wired zero (zero or $0).
3910 '^' Print the name of the pic call-through register (t9 or $25). */
3911
3912 void
3913 print_operand (file, op, letter)
3914 FILE *file; /* file to write to */
3915 rtx op; /* operand to print */
3916 int letter; /* %<letter> or 0 */
3917 {
3918 register enum rtx_code code;
3919
3920 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
3921 {
3922 switch (letter)
3923 {
3924 default:
3925 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
3926 break;
3927
3928 case '?':
3929 if (mips_branch_likely)
3930 putc ('l', file);
3931 break;
3932
3933 case '@':
3934 fputs (reg_names [GP_REG_FIRST + 1], file);
3935 break;
3936
3937 case '^':
3938 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
3939 break;
3940
3941 case '.':
3942 fputs (reg_names [GP_REG_FIRST + 0], file);
3943 break;
3944
3945 case '&':
3946 if (final_sequence != 0 && set_noreorder++ == 0)
3947 fputs (".set\tnoreorder\n\t", file);
3948 break;
3949
3950 case '*':
3951 if (final_sequence != 0)
3952 {
3953 if (set_noreorder++ == 0)
3954 fputs (".set\tnoreorder\n\t", file);
3955
3956 if (set_nomacro++ == 0)
3957 fputs (".set\tnomacro\n\t", file);
3958 }
3959 break;
3960
3961 case '!':
3962 if (final_sequence != 0 && set_nomacro++ == 0)
3963 fputs ("\n\t.set\tnomacro", file);
3964 break;
3965
3966 case '#':
3967 if (set_noreorder != 0)
3968 fputs ("\n\tnop", file);
3969
3970 else if (TARGET_STATS)
3971 fputs ("\n\t#nop", file);
3972
3973 break;
3974
3975 case '(':
3976 if (set_noreorder++ == 0)
3977 fputs (".set\tnoreorder\n\t", file);
3978 break;
3979
3980 case ')':
3981 if (set_noreorder == 0)
3982 error ("internal error: %%) found without a %%( in assembler pattern");
3983
3984 else if (--set_noreorder == 0)
3985 fputs ("\n\t.set\treorder", file);
3986
3987 break;
3988
3989 case '[':
3990 if (set_noat++ == 0)
3991 fputs (".set\tnoat\n\t", file);
3992 break;
3993
3994 case ']':
3995 if (set_noat == 0)
3996 error ("internal error: %%] found without a %%[ in assembler pattern");
3997
3998 else if (--set_noat == 0)
3999 fputs ("\n\t.set\tat", file);
4000
4001 break;
4002
4003 case '<':
4004 if (set_nomacro++ == 0)
4005 fputs (".set\tnomacro\n\t", file);
4006 break;
4007
4008 case '>':
4009 if (set_nomacro == 0)
4010 error ("internal error: %%> found without a %%< in assembler pattern");
4011
4012 else if (--set_nomacro == 0)
4013 fputs ("\n\t.set\tmacro", file);
4014
4015 break;
4016
4017 case '{':
4018 if (set_volatile++ == 0)
4019 fprintf (file, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS) ? "" : "#");
4020 break;
4021
4022 case '}':
4023 if (set_volatile == 0)
4024 error ("internal error: %%} found without a %%{ in assembler pattern");
4025
4026 else if (--set_volatile == 0)
4027 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
4028
4029 break;
4030 }
4031 return;
4032 }
4033
4034 if (! op)
4035 {
4036 error ("PRINT_OPERAND null pointer");
4037 return;
4038 }
4039
4040 code = GET_CODE (op);
4041
4042 if (code == SIGN_EXTEND)
4043 {
4044 op = XEXP (op, 0);
4045 code = GET_CODE (op);
4046 }
4047
4048 if (letter == 'C')
4049 switch (code)
4050 {
4051 case EQ: fputs ("eq", file); break;
4052 case NE: fputs ("ne", file); break;
4053 case GT: fputs ("gt", file); break;
4054 case GE: fputs ("ge", file); break;
4055 case LT: fputs ("lt", file); break;
4056 case LE: fputs ("le", file); break;
4057 case GTU: fputs ("gtu", file); break;
4058 case GEU: fputs ("geu", file); break;
4059 case LTU: fputs ("ltu", file); break;
4060 case LEU: fputs ("leu", file); break;
4061
4062 default:
4063 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
4064 }
4065
4066 else if (letter == 'N')
4067 switch (code)
4068 {
4069 case EQ: fputs ("ne", file); break;
4070 case NE: fputs ("eq", file); break;
4071 case GT: fputs ("le", file); break;
4072 case GE: fputs ("lt", file); break;
4073 case LT: fputs ("ge", file); break;
4074 case LE: fputs ("gt", file); break;
4075 case GTU: fputs ("leu", file); break;
4076 case GEU: fputs ("ltu", file); break;
4077 case LTU: fputs ("geu", file); break;
4078 case LEU: fputs ("gtu", file); break;
4079
4080 default:
4081 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
4082 }
4083
4084 else if (letter == 'S')
4085 {
4086 char buffer[100];
4087
4088 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
4089 assemble_name (file, buffer);
4090 }
4091
4092 else if (letter == 'Z')
4093 {
4094 register int regnum;
4095
4096 if (code != REG)
4097 abort ();
4098 regnum = REGNO (op);
4099 if (! ST_REG_P (regnum))
4100 abort ();
4101 if (regnum != ST_REG_FIRST)
4102 fprintf (file, "%s,", reg_names[regnum]);
4103 }
4104
4105 else if (code == REG || code == SUBREG)
4106 {
4107 register int regnum;
4108
4109 if (code == REG)
4110 regnum = REGNO (op);
4111 else
4112 regnum = true_regnum (op);
4113
4114 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
4115 || (letter == 'L' && WORDS_BIG_ENDIAN)
4116 || letter == 'D')
4117 regnum++;
4118
4119 fprintf (file, "%s", reg_names[regnum]);
4120 }
4121
4122 else if (code == MEM)
4123 output_address (XEXP (op, 0));
4124
4125 else if (code == CONST_DOUBLE
4126 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
4127 {
4128 REAL_VALUE_TYPE d;
4129 char s[30];
4130
4131 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
4132 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
4133 fprintf (file, s);
4134 }
4135
4136 else if ((letter == 'x') && (GET_CODE(op) == CONST_INT))
4137 fprintf (file, "0x%04x", 0xffff & (INTVAL(op)));
4138
4139 else if ((letter == 'X') && (GET_CODE(op) == CONST_INT)
4140 && HOST_BITS_PER_WIDE_INT == 32)
4141 fprintf (file, "0x%08x", INTVAL(op));
4142
4143 else if ((letter == 'X') && (GET_CODE(op) == CONST_INT)
4144 && HOST_BITS_PER_WIDE_INT == 64)
4145 fprintf (file, "0x%016lx", INTVAL(op));
4146
4147 else if ((letter == 'd') && (GET_CODE(op) == CONST_INT))
4148 fprintf (file, "%d", (INTVAL(op)));
4149
4150 else if (letter == 'z'
4151 && (GET_CODE (op) == CONST_INT)
4152 && INTVAL (op) == 0)
4153 fputs (reg_names[GP_REG_FIRST], file);
4154
4155 else if (letter == 'd' || letter == 'x' || letter == 'X')
4156 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter);
4157
4158 else if (letter == 'B')
4159 fputs (code == EQ ? "z" : "n", file);
4160 else if (letter == 'b')
4161 fputs (code == EQ ? "n" : "z", file);
4162 else if (letter == 'T')
4163 fputs (code == EQ ? "f" : "t", file);
4164 else if (letter == 't')
4165 fputs (code == EQ ? "t" : "f", file);
4166
4167 else
4168 output_addr_const (file, op);
4169 }
4170
4171 \f
4172 /* A C compound statement to output to stdio stream STREAM the
4173 assembler syntax for an instruction operand that is a memory
4174 reference whose address is ADDR. ADDR is an RTL expression.
4175
4176 On some machines, the syntax for a symbolic address depends on
4177 the section that the address refers to. On these machines,
4178 define the macro `ENCODE_SECTION_INFO' to store the information
4179 into the `symbol_ref', and then check for it here. */
4180
4181 void
4182 print_operand_address (file, addr)
4183 FILE *file;
4184 rtx addr;
4185 {
4186 if (!addr)
4187 error ("PRINT_OPERAND_ADDRESS, null pointer");
4188
4189 else
4190 switch (GET_CODE (addr))
4191 {
4192 default:
4193 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
4194 break;
4195
4196 case REG:
4197 if (REGNO (addr) == ARG_POINTER_REGNUM)
4198 abort_with_insn (addr, "Arg pointer not eliminated.");
4199
4200 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
4201 break;
4202
4203 case LO_SUM:
4204 {
4205 register rtx arg0 = XEXP (addr, 0);
4206 register rtx arg1 = XEXP (addr, 1);
4207
4208 if (! mips_split_addresses)
4209 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4210
4211 if (GET_CODE (arg0) != REG)
4212 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4213
4214 fprintf (file, "%%lo(");
4215 print_operand_address (file, arg1);
4216 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
4217 }
4218 break;
4219
4220 case PLUS:
4221 {
4222 register rtx reg = (rtx)0;
4223 register rtx offset = (rtx)0;
4224 register rtx arg0 = XEXP (addr, 0);
4225 register rtx arg1 = XEXP (addr, 1);
4226
4227 if (GET_CODE (arg0) == REG)
4228 {
4229 reg = arg0;
4230 offset = arg1;
4231 if (GET_CODE (offset) == REG)
4232 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
4233 }
4234 else if (GET_CODE (arg1) == REG)
4235 {
4236 reg = arg1;
4237 offset = arg0;
4238 }
4239 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
4240 {
4241 output_addr_const (file, addr);
4242 break;
4243 }
4244 else
4245 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
4246
4247 if (!CONSTANT_P (offset))
4248 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4249
4250 if (REGNO (reg) == ARG_POINTER_REGNUM)
4251 abort_with_insn (addr, "Arg pointer not eliminated.");
4252
4253 output_addr_const (file, offset);
4254 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
4255 }
4256 break;
4257
4258 case LABEL_REF:
4259 case SYMBOL_REF:
4260 case CONST_INT:
4261 case CONST:
4262 output_addr_const (file, addr);
4263 break;
4264 }
4265 }
4266
4267 \f
4268 /* If optimizing for the global pointer, keep track of all of
4269 the externs, so that at the end of the file, we can emit
4270 the appropriate .extern declaration for them, before writing
4271 out the text section. We assume that all names passed to
4272 us are in the permanent obstack, so that they will be valid
4273 at the end of the compilation.
4274
4275 If we have -G 0, or the extern size is unknown, don't bother
4276 emitting the .externs. */
4277
4278 int
4279 mips_output_external (file, decl, name)
4280 FILE *file;
4281 tree decl;
4282 char *name;
4283 {
4284 register struct extern_list *p;
4285 int len;
4286
4287 if (TARGET_GP_OPT
4288 && ((TREE_CODE (decl)) != FUNCTION_DECL)
4289 && ((len = int_size_in_bytes (TREE_TYPE (decl))) > 0))
4290 {
4291 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
4292 p->next = extern_head;
4293 p->name = name;
4294 p->size = len;
4295 extern_head = p;
4296 }
4297
4298 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4299 if (TREE_CODE (decl) == FUNCTION_DECL
4300 /* ??? Don't include alloca, since gcc will always expand it
4301 inline. If we don't do this, libg++ fails to build. */
4302 && strcmp (name, "alloca")
4303 /* ??? Don't include __builtin_next_arg, because then gcc will not
4304 bootstrap under Irix 5.1. */
4305 && strcmp (name, "__builtin_next_arg"))
4306 {
4307 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
4308 p->next = extern_head;
4309 p->name = name;
4310 p->size = -1;
4311 extern_head = p;
4312 }
4313 #endif
4314
4315 return 0;
4316 }
4317
4318 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4319 int
4320 mips_output_external_libcall (file, name)
4321 FILE *file;
4322 char *name;
4323 {
4324 register struct extern_list *p;
4325
4326 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
4327 p->next = extern_head;
4328 p->name = name;
4329 p->size = -1;
4330 extern_head = p;
4331
4332 return 0;
4333 }
4334 #endif
4335
4336 \f
4337 /* Compute a string to use as a temporary file name. */
4338
4339 /* On MSDOS, write temp files in current dir
4340 because there's no place else we can expect to use. */
4341 #if __MSDOS__
4342 #ifndef P_tmpdir
4343 #define P_tmpdir "./"
4344 #endif
4345 #endif
4346
4347 static FILE *
4348 make_temp_file ()
4349 {
4350 FILE *stream;
4351 char *base = getenv ("TMPDIR");
4352 int len;
4353
4354 if (base == (char *)0)
4355 {
4356 #ifdef P_tmpdir
4357 if (access (P_tmpdir, R_OK | W_OK) == 0)
4358 base = P_tmpdir;
4359 else
4360 #endif
4361 if (access ("/usr/tmp", R_OK | W_OK) == 0)
4362 base = "/usr/tmp/";
4363 else
4364 base = "/tmp/";
4365 }
4366
4367 len = strlen (base);
4368 /* temp_filename is global, so we must use malloc, not alloca. */
4369 temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX"));
4370 strcpy (temp_filename, base);
4371 if (len > 0 && temp_filename[len-1] != '/')
4372 temp_filename[len++] = '/';
4373
4374 strcpy (temp_filename + len, "ctXXXXXX");
4375 mktemp (temp_filename);
4376
4377 stream = fopen (temp_filename, "w+");
4378 if (!stream)
4379 pfatal_with_name (temp_filename);
4380
4381 #ifndef __MSDOS__
4382 /* In MSDOS, we cannot unlink the temporary file until we are finished using
4383 it. Otherwise, we delete it now, so that it will be gone even if the
4384 compiler happens to crash. */
4385 unlink (temp_filename);
4386 #endif
4387 return stream;
4388 }
4389
4390 \f
4391 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
4392 for .file's that start within a function. If we are smuggling stabs, try to
4393 put out a MIPS ECOFF file and a stab. */
4394
4395 void
4396 mips_output_filename (stream, name)
4397 FILE *stream;
4398 char *name;
4399 {
4400 static int first_time = TRUE;
4401 char ltext_label_name[100];
4402
4403 if (first_time)
4404 {
4405 first_time = FALSE;
4406 SET_FILE_NUMBER ();
4407 current_function_file = name;
4408 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
4409 /* This tells mips-tfile that stabs will follow. */
4410 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
4411 fprintf (stream, "\t#@stabs\n");
4412 }
4413
4414 else if (write_symbols == DBX_DEBUG)
4415 {
4416 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
4417 fprintf (stream, "%s ", ASM_STABS_OP);
4418 output_quoted_string (stream, name);
4419 fprintf (stream, ",%d,0,0,%s\n", N_SOL, &ltext_label_name[1]);
4420 }
4421
4422 else if (name != current_function_file
4423 && strcmp (name, current_function_file) != 0)
4424 {
4425 if (inside_function && !TARGET_GAS)
4426 {
4427 if (!file_in_function_warning)
4428 {
4429 file_in_function_warning = TRUE;
4430 ignore_line_number = TRUE;
4431 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
4432 }
4433 }
4434 else
4435 {
4436 SET_FILE_NUMBER ();
4437 current_function_file = name;
4438 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
4439 }
4440 }
4441 }
4442
4443 \f
4444 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4445 as well as a .loc, since it is possible that MIPS ECOFF might not be
4446 able to represent the location for inlines that come from a different
4447 file. */
4448
4449 void
4450 mips_output_lineno (stream, line)
4451 FILE *stream;
4452 int line;
4453 {
4454 if (write_symbols == DBX_DEBUG)
4455 {
4456 ++sym_lineno;
4457 fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
4458 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
4459 LOCAL_LABEL_PREFIX, sym_lineno);
4460 }
4461
4462 else
4463 {
4464 fprintf (stream, "\n\t%s.loc\t%d %d\n",
4465 (ignore_line_number) ? "#" : "",
4466 num_source_filenames, line);
4467
4468 LABEL_AFTER_LOC (stream);
4469 }
4470 }
4471
4472 \f
4473 /* If defined, a C statement to be executed just prior to the
4474 output of assembler code for INSN, to modify the extracted
4475 operands so they will be output differently.
4476
4477 Here the argument OPVEC is the vector containing the operands
4478 extracted from INSN, and NOPERANDS is the number of elements of
4479 the vector which contain meaningful data for this insn. The
4480 contents of this vector are what will be used to convert the
4481 insn template into assembler code, so you can change the
4482 assembler output by changing the contents of the vector.
4483
4484 We use it to check if the current insn needs a nop in front of it
4485 because of load delays, and also to update the delay slot
4486 statistics. */
4487
4488 /* ??? There is no real need for this function, because it never actually
4489 emits a NOP anymore. */
4490
4491 void
4492 final_prescan_insn (insn, opvec, noperands)
4493 rtx insn;
4494 rtx opvec[];
4495 int noperands;
4496 {
4497 if (dslots_number_nops > 0)
4498 {
4499 rtx pattern = PATTERN (insn);
4500 int length = get_attr_length (insn);
4501
4502 /* Do we need to emit a NOP? */
4503 if (length == 0
4504 || (mips_load_reg != (rtx)0 && reg_mentioned_p (mips_load_reg, pattern))
4505 || (mips_load_reg2 != (rtx)0 && reg_mentioned_p (mips_load_reg2, pattern))
4506 || (mips_load_reg3 != (rtx)0 && reg_mentioned_p (mips_load_reg3, pattern))
4507 || (mips_load_reg4 != (rtx)0 && reg_mentioned_p (mips_load_reg4, pattern)))
4508 fputs ("\t#nop\n", asm_out_file);
4509
4510 else
4511 dslots_load_filled++;
4512
4513 while (--dslots_number_nops > 0)
4514 fputs ("\t#nop\n", asm_out_file);
4515
4516 mips_load_reg = (rtx)0;
4517 mips_load_reg2 = (rtx)0;
4518 mips_load_reg3 = (rtx)0;
4519 mips_load_reg4 = (rtx)0;
4520 }
4521
4522 if (TARGET_STATS)
4523 {
4524 enum rtx_code code = GET_CODE (insn);
4525 if (code == JUMP_INSN || code == CALL_INSN)
4526 dslots_jump_total++;
4527 }
4528 }
4529
4530 \f
4531 /* Output at beginning of assembler file.
4532 If we are optimizing to use the global pointer, create a temporary
4533 file to hold all of the text stuff, and write it out to the end.
4534 This is needed because the MIPS assembler is evidently one pass,
4535 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4536 declaration when the code is processed, it generates a two
4537 instruction sequence. */
4538
4539 void
4540 mips_asm_file_start (stream)
4541 FILE *stream;
4542 {
4543 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
4544
4545 /* Versions of the MIPS assembler before 2.20 generate errors
4546 if a branch inside of a .set noreorder section jumps to a
4547 label outside of the .set noreorder section. Revision 2.20
4548 just set nobopt silently rather than fixing the bug. */
4549
4550 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
4551 fprintf (stream, "\t.set\tnobopt\n");
4552
4553 /* Generate the pseudo ops that System V.4 wants. */
4554 #ifndef ABICALLS_ASM_OP
4555 #define ABICALLS_ASM_OP ".abicalls"
4556 #endif
4557 if (TARGET_ABICALLS)
4558 /* ??? but do not want this (or want pic0) if -non-shared? */
4559 fprintf (stream, "\t%s\n", ABICALLS_ASM_OP);
4560
4561 /* Start a section, so that the first .popsection directive is guaranteed
4562 to have a previously defined section to pop back to. */
4563 if (mips_abi != ABI_32 && mips_abi != ABI_EABI)
4564 fprintf (stream, "\t.section\t.text\n");
4565
4566 /* This code exists so that we can put all externs before all symbol
4567 references. This is necessary for the assembler's global pointer
4568 optimizations to work. */
4569 /* ??? Current versions of gas do not require that externs occur before
4570 symbol references. This means that this code is unnecessary when
4571 gas is being used. This gas feature hasn't been well tested as yet
4572 though. */
4573 if (TARGET_GP_OPT)
4574 {
4575 asm_out_data_file = stream;
4576 asm_out_text_file = make_temp_file ();
4577 }
4578 else
4579 asm_out_data_file = asm_out_text_file = stream;
4580
4581 if (flag_verbose_asm)
4582 fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
4583 ASM_COMMENT_START,
4584 mips_section_threshold, mips_cpu_string, mips_isa);
4585 }
4586
4587 \f
4588 /* If we are optimizing the global pointer, emit the text section now
4589 and any small externs which did not have .comm, etc that are
4590 needed. Also, give a warning if the data area is more than 32K and
4591 -pic because 3 instructions are needed to reference the data
4592 pointers. */
4593
4594 void
4595 mips_asm_file_end (file)
4596 FILE *file;
4597 {
4598 char buffer[8192];
4599 tree name_tree;
4600 struct extern_list *p;
4601 int len;
4602
4603 if (HALF_PIC_P ())
4604 HALF_PIC_FINISH (file);
4605
4606 if (extern_head)
4607 {
4608 fputs ("\n", file);
4609
4610 for (p = extern_head; p != 0; p = p->next)
4611 {
4612 name_tree = get_identifier (p->name);
4613
4614 /* Positively ensure only one .extern for any given symbol. */
4615 if (! TREE_ASM_WRITTEN (name_tree))
4616 {
4617 TREE_ASM_WRITTEN (name_tree) = 1;
4618 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4619 if (p->size == -1)
4620 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
4621 else
4622 #endif
4623 {
4624 fputs ("\t.extern\t", file);
4625 assemble_name (file, p->name);
4626 fprintf (file, ", %d\n", p->size);
4627 }
4628 }
4629 }
4630 }
4631
4632 if (TARGET_GP_OPT)
4633 {
4634 fprintf (file, "\n\t.text\n");
4635 rewind (asm_out_text_file);
4636 if (ferror (asm_out_text_file))
4637 fatal_io_error (temp_filename);
4638
4639 while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
4640 if (fwrite (buffer, 1, len, file) != len)
4641 pfatal_with_name (asm_file_name);
4642
4643 if (len < 0)
4644 pfatal_with_name (temp_filename);
4645
4646 if (fclose (asm_out_text_file) != 0)
4647 pfatal_with_name (temp_filename);
4648
4649 #ifdef __MSDOS__
4650 unlink (temp_filename);
4651 #endif
4652 }
4653 }
4654
4655 \f
4656 /* Emit either a label, .comm, or .lcomm directive, and mark
4657 that the symbol is used, so that we don't emit an .extern
4658 for it in mips_asm_file_end. */
4659
4660 void
4661 mips_declare_object (stream, name, init_string, final_string, size)
4662 FILE *stream;
4663 char *name;
4664 char *init_string;
4665 char *final_string;
4666 int size;
4667 {
4668 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
4669 assemble_name (stream, name);
4670 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
4671
4672 if (TARGET_GP_OPT)
4673 {
4674 tree name_tree = get_identifier (name);
4675 TREE_ASM_WRITTEN (name_tree) = 1;
4676 }
4677 }
4678
4679 \f
4680 /* Output a double precision value to the assembler. If both the
4681 host and target are IEEE, emit the values in hex. */
4682
4683 void
4684 mips_output_double (stream, value)
4685 FILE *stream;
4686 REAL_VALUE_TYPE value;
4687 {
4688 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4689 long value_long[2];
4690 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
4691
4692 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4693 value_long[0], value, value_long[1]);
4694 #else
4695 fprintf (stream, "\t.double\t%.20g\n", value);
4696 #endif
4697 }
4698
4699
4700 /* Output a single precision value to the assembler. If both the
4701 host and target are IEEE, emit the values in hex. */
4702
4703 void
4704 mips_output_float (stream, value)
4705 FILE *stream;
4706 REAL_VALUE_TYPE value;
4707 {
4708 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4709 long value_long;
4710 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
4711
4712 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
4713 #else
4714 fprintf (stream, "\t.float\t%.12g\n", value);
4715 #endif
4716 }
4717
4718 \f
4719 /* Return TRUE if any register used in the epilogue is used. This to insure
4720 any insn put into the epilogue delay slots is safe. */
4721
4722 int
4723 epilogue_reg_mentioned_p (insn)
4724 rtx insn;
4725 {
4726 register char *fmt;
4727 register int i;
4728 register enum rtx_code code;
4729 register int regno;
4730
4731 if (insn == (rtx)0)
4732 return 0;
4733
4734 if (GET_CODE (insn) == LABEL_REF)
4735 return 0;
4736
4737 code = GET_CODE (insn);
4738 switch (code)
4739 {
4740 case REG:
4741 regno = REGNO (insn);
4742 if (regno == STACK_POINTER_REGNUM)
4743 return 1;
4744
4745 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
4746 return 1;
4747
4748 if (!call_used_regs[regno])
4749 return 1;
4750
4751 if (regno != MIPS_TEMP1_REGNUM && regno != MIPS_TEMP2_REGNUM)
4752 return 0;
4753
4754 if (!current_frame_info.initialized)
4755 compute_frame_size (get_frame_size ());
4756
4757 return (current_frame_info.total_size >= 32768);
4758
4759 case SCRATCH:
4760 case CC0:
4761 case PC:
4762 case CONST_INT:
4763 case CONST_DOUBLE:
4764 return 0;
4765 }
4766
4767 fmt = GET_RTX_FORMAT (code);
4768 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4769 {
4770 if (fmt[i] == 'E')
4771 {
4772 register int j;
4773 for (j = XVECLEN (insn, i) - 1; j >= 0; j--)
4774 if (epilogue_reg_mentioned_p (XVECEXP (insn, i, j)))
4775 return 1;
4776 }
4777 else if (fmt[i] == 'e' && epilogue_reg_mentioned_p (XEXP (insn, i)))
4778 return 1;
4779 }
4780
4781 return 0;
4782 }
4783 \f
4784 /* Return the bytes needed to compute the frame pointer from the current
4785 stack pointer.
4786
4787 Mips stack frames look like:
4788
4789 Before call After call
4790 +-----------------------+ +-----------------------+
4791 high | | | |
4792 mem. | | | |
4793 | caller's temps. | | caller's temps. |
4794 | | | |
4795 +-----------------------+ +-----------------------+
4796 | | | |
4797 | arguments on stack. | | arguments on stack. |
4798 | | | |
4799 +-----------------------+ +-----------------------+
4800 | 4 words to save | | 4 words to save |
4801 | arguments passed | | arguments passed |
4802 | in registers, even | | in registers, even |
4803 SP->| if not passed. | VFP->| if not passed. |
4804 +-----------------------+ +-----------------------+
4805 | |
4806 | fp register save |
4807 | |
4808 +-----------------------+
4809 | |
4810 | gp register save |
4811 | |
4812 +-----------------------+
4813 | |
4814 | local variables |
4815 | |
4816 +-----------------------+
4817 | |
4818 | alloca allocations |
4819 | |
4820 +-----------------------+
4821 | |
4822 | GP save for V.4 abi |
4823 | |
4824 +-----------------------+
4825 | |
4826 | arguments on stack |
4827 | |
4828 +-----------------------+
4829 | 4 words to save |
4830 | arguments passed |
4831 | in registers, even |
4832 low SP->| if not passed. |
4833 memory +-----------------------+
4834
4835 */
4836
4837 long
4838 compute_frame_size (size)
4839 int size; /* # of var. bytes allocated */
4840 {
4841 int regno;
4842 long total_size; /* # bytes that the entire frame takes up */
4843 long var_size; /* # bytes that variables take up */
4844 long args_size; /* # bytes that outgoing arguments take up */
4845 long extra_size; /* # extra bytes */
4846 long gp_reg_rounded; /* # bytes needed to store gp after rounding */
4847 long gp_reg_size; /* # bytes needed to store gp regs */
4848 long fp_reg_size; /* # bytes needed to store fp regs */
4849 long mask; /* mask of saved gp registers */
4850 long fmask; /* mask of saved fp registers */
4851 int fp_inc; /* 1 or 2 depending on the size of fp regs */
4852 long fp_bits; /* bitmask to use for each fp register */
4853
4854 gp_reg_size = 0;
4855 fp_reg_size = 0;
4856 mask = 0;
4857 fmask = 0;
4858 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
4859 var_size = MIPS_STACK_ALIGN (size);
4860 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
4861
4862 /* The MIPS 3.0 linker does not like functions that dynamically
4863 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4864 looks like we are trying to create a second frame pointer to the
4865 function, so allocate some stack space to make it happy. */
4866
4867 if (args_size == 0 && current_function_calls_alloca)
4868 args_size = 4*UNITS_PER_WORD;
4869
4870 total_size = var_size + args_size + extra_size;
4871
4872 /* Calculate space needed for gp registers. */
4873 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
4874 {
4875 if (MUST_SAVE_REGISTER (regno))
4876 {
4877 gp_reg_size += UNITS_PER_WORD;
4878 mask |= 1L << (regno - GP_REG_FIRST);
4879 }
4880 }
4881
4882 /* Calculate space needed for fp registers. */
4883 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
4884 {
4885 fp_inc = 1;
4886 fp_bits = 1;
4887 }
4888 else
4889 {
4890 fp_inc = 2;
4891 fp_bits = 3;
4892 }
4893
4894 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += fp_inc)
4895 {
4896 if (regs_ever_live[regno] && !call_used_regs[regno])
4897 {
4898 fp_reg_size += fp_inc * UNITS_PER_FPREG;
4899 fmask |= fp_bits << (regno - FP_REG_FIRST);
4900 }
4901 }
4902
4903 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
4904 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
4905
4906 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4907 for leaf routines (total_size == extra_size) to save the gp reg.
4908 The gp reg is callee saved in the 64 bit ABI, so all routines must
4909 save the gp reg. */
4910 if (total_size == extra_size && (mips_abi == ABI_32 || mips_abi == ABI_EABI))
4911 total_size = extra_size = 0;
4912 else if (TARGET_ABICALLS)
4913 {
4914 /* Add the context-pointer to the saved registers. */
4915 gp_reg_size += UNITS_PER_WORD;
4916 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
4917 total_size -= gp_reg_rounded;
4918 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
4919 total_size += gp_reg_rounded;
4920 }
4921
4922 /* Add in space reserved on the stack by the callee for storing arguments
4923 passed in registers. */
4924 if (mips_abi != ABI_32)
4925 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
4926
4927 /* Save other computed information. */
4928 current_frame_info.total_size = total_size;
4929 current_frame_info.var_size = var_size;
4930 current_frame_info.args_size = args_size;
4931 current_frame_info.extra_size = extra_size;
4932 current_frame_info.gp_reg_size = gp_reg_size;
4933 current_frame_info.fp_reg_size = fp_reg_size;
4934 current_frame_info.mask = mask;
4935 current_frame_info.fmask = fmask;
4936 current_frame_info.initialized = reload_completed;
4937 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
4938 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
4939
4940 if (mask)
4941 {
4942 unsigned long offset = (args_size + extra_size + var_size
4943 + gp_reg_size - UNITS_PER_WORD);
4944 current_frame_info.gp_sp_offset = offset;
4945 current_frame_info.gp_save_offset = offset - total_size;
4946 }
4947 else
4948 {
4949 current_frame_info.gp_sp_offset = 0;
4950 current_frame_info.gp_save_offset = 0;
4951 }
4952
4953
4954 if (fmask)
4955 {
4956 unsigned long offset = (args_size + extra_size + var_size
4957 + gp_reg_rounded + fp_reg_size
4958 - fp_inc * UNITS_PER_FPREG);
4959 current_frame_info.fp_sp_offset = offset;
4960 current_frame_info.fp_save_offset = offset - total_size;
4961 }
4962 else
4963 {
4964 current_frame_info.fp_sp_offset = 0;
4965 current_frame_info.fp_save_offset = 0;
4966 }
4967
4968 /* Ok, we're done. */
4969 return total_size;
4970 }
4971
4972 \f
4973 /* Common code to emit the insns (or to write the instructions to a file)
4974 to save/restore registers.
4975
4976 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4977 is not modified within save_restore_insns. */
4978
4979 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4980
4981 static void
4982 save_restore_insns (store_p, large_reg, large_offset, file)
4983 int store_p; /* true if this is prologue */
4984 rtx large_reg; /* register holding large offset constant or NULL */
4985 long large_offset; /* large constant offset value */
4986 FILE *file; /* file to write instructions to instead of making RTL */
4987 {
4988 long mask = current_frame_info.mask;
4989 long fmask = current_frame_info.fmask;
4990 int regno;
4991 rtx base_reg_rtx;
4992 long base_offset;
4993 long gp_offset;
4994 long fp_offset;
4995 long end_offset;
4996 rtx insn;
4997
4998 if (frame_pointer_needed && !BITSET_P (mask, FRAME_POINTER_REGNUM - GP_REG_FIRST))
4999 abort ();
5000
5001 if (mask == 0 && fmask == 0)
5002 return;
5003
5004 /* Save registers starting from high to low. The debuggers prefer
5005 at least the return register be stored at func+4, and also it
5006 allows us not to need a nop in the epilog if at least one
5007 register is reloaded in addition to return address. */
5008
5009 /* Save GP registers if needed. */
5010 if (mask)
5011 {
5012 /* Pick which pointer to use as a base register. For small
5013 frames, just use the stack pointer. Otherwise, use a
5014 temporary register. Save 2 cycles if the save area is near
5015 the end of a large frame, by reusing the constant created in
5016 the prologue/epilogue to adjust the stack frame. */
5017
5018 gp_offset = current_frame_info.gp_sp_offset;
5019 end_offset = gp_offset - (current_frame_info.gp_reg_size - UNITS_PER_WORD);
5020
5021 if (gp_offset < 0 || end_offset < 0)
5022 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
5023 gp_offset, end_offset);
5024
5025 else if (gp_offset < 32768)
5026 {
5027 base_reg_rtx = stack_pointer_rtx;
5028 base_offset = 0;
5029 }
5030
5031 else if (large_reg != (rtx)0
5032 && (((unsigned long)(large_offset - gp_offset)) < 32768)
5033 && (((unsigned long)(large_offset - end_offset)) < 32768))
5034 {
5035 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5036 base_offset = large_offset;
5037 if (file == (FILE *)0)
5038 {
5039 if (TARGET_LONG64)
5040 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
5041 else
5042 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
5043 RTX_FRAME_RELATED_P (insn) = 1;
5044 }
5045 else
5046 fprintf (file, "\t%s\t%s,%s,%s\n",
5047 TARGET_LONG64 ? "daddu" : "addu",
5048 reg_names[MIPS_TEMP2_REGNUM],
5049 reg_names[REGNO (large_reg)],
5050 reg_names[STACK_POINTER_REGNUM]);
5051 }
5052
5053 else
5054 {
5055 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5056 base_offset = gp_offset;
5057 if (file == (FILE *)0)
5058 {
5059 insn = emit_move_insn (base_reg_rtx, GEN_INT (gp_offset));
5060 RTX_FRAME_RELATED_P (insn) = 1;
5061 if (TARGET_LONG64)
5062 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
5063 else
5064 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
5065 RTX_FRAME_RELATED_P (insn) = 1;
5066 }
5067 else
5068 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5069 reg_names[MIPS_TEMP2_REGNUM],
5070 (long)base_offset,
5071 (long)base_offset,
5072 TARGET_LONG64 ? "daddu" : "addu",
5073 reg_names[MIPS_TEMP2_REGNUM],
5074 reg_names[MIPS_TEMP2_REGNUM],
5075 reg_names[STACK_POINTER_REGNUM]);
5076 }
5077
5078 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
5079 {
5080 if (BITSET_P (mask, regno - GP_REG_FIRST))
5081 {
5082 if (file == (FILE *)0)
5083 {
5084 rtx reg_rtx = gen_rtx (REG, word_mode, regno);
5085 rtx mem_rtx = gen_rtx (MEM, word_mode,
5086 gen_rtx (PLUS, Pmode, base_reg_rtx,
5087 GEN_INT (gp_offset - base_offset)));
5088
5089 if (store_p)
5090 {
5091 insn = emit_move_insn (mem_rtx, reg_rtx);
5092 RTX_FRAME_RELATED_P (insn) = 1;
5093 }
5094 else if (!TARGET_ABICALLS || mips_abi != ABI_32
5095 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5096 emit_move_insn (reg_rtx, mem_rtx);
5097 }
5098 else
5099 {
5100 if (store_p || !TARGET_ABICALLS || mips_abi != ABI_32
5101 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5102 fprintf (file, "\t%s\t%s,%ld(%s)\n",
5103 (TARGET_64BIT
5104 ? (store_p) ? "sd" : "ld"
5105 : (store_p) ? "sw" : "lw"),
5106 reg_names[regno],
5107 gp_offset - base_offset,
5108 reg_names[REGNO(base_reg_rtx)]);
5109
5110 }
5111 gp_offset -= UNITS_PER_WORD;
5112 }
5113 }
5114 }
5115 else
5116 {
5117 base_reg_rtx = (rtx)0; /* Make sure these are initialized */
5118 base_offset = 0;
5119 }
5120
5121 /* Save floating point registers if needed. */
5122 if (fmask)
5123 {
5124 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
5125 int fp_size = fp_inc * UNITS_PER_FPREG;
5126
5127 /* Pick which pointer to use as a base register. */
5128 fp_offset = current_frame_info.fp_sp_offset;
5129 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
5130
5131 if (fp_offset < 0 || end_offset < 0)
5132 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
5133 fp_offset, end_offset);
5134
5135 else if (fp_offset < 32768)
5136 {
5137 base_reg_rtx = stack_pointer_rtx;
5138 base_offset = 0;
5139 }
5140
5141 else if (base_reg_rtx != (rtx)0
5142 && (((unsigned long)(base_offset - fp_offset)) < 32768)
5143 && (((unsigned long)(base_offset - end_offset)) < 32768))
5144 {
5145 ; /* already set up for gp registers above */
5146 }
5147
5148 else if (large_reg != (rtx)0
5149 && (((unsigned long)(large_offset - fp_offset)) < 32768)
5150 && (((unsigned long)(large_offset - end_offset)) < 32768))
5151 {
5152 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5153 base_offset = large_offset;
5154 if (file == (FILE *)0)
5155 {
5156 if (TARGET_LONG64)
5157 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
5158 else
5159 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
5160 RTX_FRAME_RELATED_P (insn) = 1;
5161 }
5162 else
5163 fprintf (file, "\t%s\t%s,%s,%s\n",
5164 TARGET_LONG64 ? "daddu" : "addu",
5165 reg_names[MIPS_TEMP2_REGNUM],
5166 reg_names[REGNO (large_reg)],
5167 reg_names[STACK_POINTER_REGNUM]);
5168 }
5169
5170 else
5171 {
5172 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5173 base_offset = fp_offset;
5174 if (file == (FILE *)0)
5175 {
5176 insn = emit_move_insn (base_reg_rtx, GEN_INT (fp_offset));
5177 RTX_FRAME_RELATED_P (insn) = 1;
5178 if (TARGET_LONG64)
5179 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
5180 else
5181 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
5182 RTX_FRAME_RELATED_P (insn) = 1;
5183 }
5184 else
5185 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5186 reg_names[MIPS_TEMP2_REGNUM],
5187 (long)base_offset,
5188 (long)base_offset,
5189 TARGET_LONG64 ? "daddu" : "addu",
5190 reg_names[MIPS_TEMP2_REGNUM],
5191 reg_names[MIPS_TEMP2_REGNUM],
5192 reg_names[STACK_POINTER_REGNUM]);
5193 }
5194
5195 for (regno = FP_REG_LAST-1; regno >= FP_REG_FIRST; regno -= fp_inc)
5196 {
5197 if (BITSET_P (fmask, regno - FP_REG_FIRST))
5198 {
5199 if (file == (FILE *)0)
5200 {
5201 enum machine_mode sz =
5202 TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5203 rtx reg_rtx = gen_rtx (REG, sz, regno);
5204 rtx mem_rtx = gen_rtx (MEM, sz,
5205 gen_rtx (PLUS, Pmode, base_reg_rtx,
5206 GEN_INT (fp_offset - base_offset)));
5207
5208 if (store_p)
5209 {
5210 insn = emit_move_insn (mem_rtx, reg_rtx);
5211 RTX_FRAME_RELATED_P (insn) = 1;
5212 }
5213 else
5214 emit_move_insn (reg_rtx, mem_rtx);
5215 }
5216 else
5217 fprintf (file, "\t%s\t%s,%ld(%s)\n",
5218 (TARGET_SINGLE_FLOAT
5219 ? ((store_p) ? "s.s" : "l.s")
5220 : ((store_p) ? "s.d" : "l.d")),
5221 reg_names[regno],
5222 fp_offset - base_offset,
5223 reg_names[REGNO(base_reg_rtx)]);
5224
5225
5226 fp_offset -= fp_size;
5227 }
5228 }
5229 }
5230 }
5231
5232 \f
5233 /* Set up the stack and frame (if desired) for the function. */
5234
5235 void
5236 function_prologue (file, size)
5237 FILE *file;
5238 int size;
5239 {
5240 char *fnname;
5241 long tsize = current_frame_info.total_size;
5242
5243 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
5244
5245 #ifdef SDB_DEBUGGING_INFO
5246 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
5247 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
5248 #endif
5249
5250 inside_function = 1;
5251
5252 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5253 /* Get the function name the same way that toplev.c does before calling
5254 assemble_start_function. This is needed so that the name used here
5255 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5256 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
5257
5258 fputs ("\t.ent\t", file);
5259 assemble_name (file, fnname);
5260 fputs ("\n", file);
5261
5262 assemble_name (file, fnname);
5263 fputs (":\n", file);
5264 #endif
5265
5266 fprintf (file, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5267 reg_names[ (frame_pointer_needed) ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ],
5268 tsize,
5269 reg_names[31 + GP_REG_FIRST],
5270 current_frame_info.var_size,
5271 current_frame_info.num_gp,
5272 current_frame_info.num_fp,
5273 current_function_outgoing_args_size,
5274 current_frame_info.extra_size);
5275
5276 fprintf (file, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
5277 current_frame_info.mask,
5278 current_frame_info.gp_save_offset,
5279 current_frame_info.fmask,
5280 current_frame_info.fp_save_offset);
5281
5282 if (TARGET_ABICALLS && mips_abi == ABI_32)
5283 {
5284 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5285
5286 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
5287 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
5288 if (tsize > 0)
5289 {
5290 fprintf (file, "\t%s\t%s,%s,%d\n",
5291 (TARGET_LONG64 ? "dsubu" : "subu"),
5292 sp_str, sp_str, tsize);
5293 fprintf (file, "\t.cprestore %d\n", current_frame_info.args_size);
5294 }
5295 }
5296 }
5297
5298 \f
5299 /* Expand the prologue into a bunch of separate insns. */
5300
5301 void
5302 mips_expand_prologue ()
5303 {
5304 int regno;
5305 long tsize;
5306 rtx tmp_rtx = (rtx)0;
5307 char *arg_name = (char *)0;
5308 tree fndecl = current_function_decl;
5309 tree fntype = TREE_TYPE (fndecl);
5310 tree fnargs = DECL_ARGUMENTS (fndecl);
5311 rtx next_arg_reg;
5312 int i;
5313 tree next_arg;
5314 tree cur_arg;
5315 CUMULATIVE_ARGS args_so_far;
5316
5317 /* If struct value address is treated as the first argument, make it so. */
5318 if (aggregate_value_p (DECL_RESULT (fndecl))
5319 && ! current_function_returns_pcc_struct
5320 && struct_value_incoming_rtx == 0)
5321 {
5322 tree type = build_pointer_type (fntype);
5323 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
5324 DECL_ARG_TYPE (function_result_decl) = type;
5325 TREE_CHAIN (function_result_decl) = fnargs;
5326 fnargs = function_result_decl;
5327 }
5328
5329 /* Determine the last argument, and get its name. */
5330
5331 INIT_CUMULATIVE_ARGS (args_so_far, fntype, (rtx)0, 0);
5332 regno = GP_ARG_FIRST;
5333
5334 for (cur_arg = fnargs; cur_arg != (tree)0; cur_arg = next_arg)
5335 {
5336 tree passed_type = DECL_ARG_TYPE (cur_arg);
5337 enum machine_mode passed_mode = TYPE_MODE (passed_type);
5338 rtx entry_parm;
5339
5340 if (TREE_ADDRESSABLE (passed_type))
5341 {
5342 passed_type = build_pointer_type (passed_type);
5343 passed_mode = Pmode;
5344 }
5345
5346 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
5347
5348 if (entry_parm)
5349 {
5350 int words;
5351
5352 /* passed in a register, so will get homed automatically */
5353 if (GET_MODE (entry_parm) == BLKmode)
5354 words = (int_size_in_bytes (passed_type) + 3) / 4;
5355 else
5356 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
5357
5358 regno = REGNO (entry_parm) + words - 1;
5359 }
5360 else
5361 {
5362 regno = GP_ARG_LAST+1;
5363 break;
5364 }
5365
5366 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
5367
5368 next_arg = TREE_CHAIN (cur_arg);
5369 if (next_arg == (tree)0)
5370 {
5371 if (DECL_NAME (cur_arg))
5372 arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg));
5373
5374 break;
5375 }
5376 }
5377
5378 /* In order to pass small structures by value in registers
5379 compatibly with the MIPS compiler, we need to shift the value
5380 into the high part of the register. Function_arg has encoded a
5381 PARALLEL rtx, holding a vector of adjustments to be made as the
5382 next_arg_reg variable, so we split up the insns, and emit them
5383 separately. */
5384
5385 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
5386 if (next_arg_reg != (rtx)0 && GET_CODE (next_arg_reg) == PARALLEL)
5387 {
5388 rtvec adjust = XVEC (next_arg_reg, 0);
5389 int num = GET_NUM_ELEM (adjust);
5390
5391 for (i = 0; i < num; i++)
5392 {
5393 rtx pattern = RTVEC_ELT (adjust, i);
5394 if (GET_CODE (pattern) != SET
5395 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
5396 abort_with_insn (pattern, "Insn is not a shift");
5397
5398 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
5399 emit_insn (pattern);
5400 }
5401 }
5402
5403 tsize = compute_frame_size (get_frame_size ());
5404
5405 /* If this function is a varargs function, store any registers that
5406 would normally hold arguments ($4 - $7) on the stack. */
5407 if (mips_abi == ABI_32
5408 && ((TYPE_ARG_TYPES (fntype) != 0
5409 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
5410 || (arg_name != (char *)0
5411 && ((arg_name[0] == '_' && strcmp (arg_name, "__builtin_va_alist") == 0)
5412 || (arg_name[0] == 'v' && strcmp (arg_name, "va_alist") == 0)))))
5413 {
5414 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
5415 rtx ptr = stack_pointer_rtx;
5416
5417 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
5418 if (TARGET_ABICALLS)
5419 offset += tsize;
5420
5421 for (; regno <= GP_ARG_LAST; regno++)
5422 {
5423 if (offset != 0)
5424 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
5425 emit_move_insn (gen_rtx (MEM, word_mode, ptr),
5426 gen_rtx (REG, word_mode, regno));
5427 offset += UNITS_PER_WORD;
5428 }
5429 }
5430
5431 if (tsize > 0)
5432 {
5433 rtx tsize_rtx = GEN_INT (tsize);
5434
5435 /* If we are doing svr4-abi, sp move is done by function_prologue. */
5436 if (!TARGET_ABICALLS || mips_abi != ABI_32)
5437 {
5438 rtx insn;
5439
5440 if (tsize > 32767)
5441 {
5442 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
5443 insn = emit_move_insn (tmp_rtx, tsize_rtx);
5444 RTX_FRAME_RELATED_P (insn) = 1;
5445 tsize_rtx = tmp_rtx;
5446 }
5447
5448 if (TARGET_LONG64)
5449 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
5450 tsize_rtx));
5451 else
5452 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
5453 tsize_rtx));
5454
5455 RTX_FRAME_RELATED_P (insn) = 1;
5456 }
5457
5458 save_restore_insns (TRUE, tmp_rtx, tsize, (FILE *)0);
5459
5460 if (frame_pointer_needed)
5461 {
5462 rtx insn;
5463
5464 if (TARGET_64BIT)
5465 insn= emit_insn (gen_movdi (frame_pointer_rtx, stack_pointer_rtx));
5466 else
5467 insn= emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
5468
5469 RTX_FRAME_RELATED_P (insn) = 1;
5470 }
5471
5472 if (TARGET_ABICALLS && mips_abi != ABI_32)
5473 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0)));
5474 }
5475
5476 /* If we are profiling, make sure no instructions are scheduled before
5477 the call to mcount. */
5478
5479 if (profile_flag || profile_block_flag)
5480 emit_insn (gen_blockage ());
5481 }
5482
5483 \f
5484 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
5485
5486 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5487 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5488
5489 void
5490 function_epilogue (file, size)
5491 FILE *file;
5492 int size;
5493 {
5494 char *fnname;
5495 long tsize;
5496 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5497 char *t1_str = reg_names[MIPS_TEMP1_REGNUM];
5498 rtx epilogue_delay = current_function_epilogue_delay_list;
5499 int noreorder = (epilogue_delay != 0);
5500 int noepilogue = FALSE;
5501 int load_nop = FALSE;
5502 int load_only_r31;
5503 rtx tmp_rtx = (rtx)0;
5504 rtx restore_rtx;
5505 int i;
5506
5507 /* The epilogue does not depend on any registers, but the stack
5508 registers, so we assume that if we have 1 pending nop, it can be
5509 ignored, and 2 it must be filled (2 nops occur for integer
5510 multiply and divide). */
5511
5512 if (dslots_number_nops > 0)
5513 {
5514 if (dslots_number_nops == 1)
5515 {
5516 dslots_number_nops = 0;
5517 dslots_load_filled++;
5518 }
5519 else
5520 {
5521 while (--dslots_number_nops > 0)
5522 fputs ("\t#nop\n", asm_out_file);
5523 }
5524 }
5525
5526 if (set_noat != 0)
5527 {
5528 set_noat = 0;
5529 fputs ("\t.set\tat\n", file);
5530 error ("internal gcc error: .set noat left on in epilogue");
5531 }
5532
5533 if (set_nomacro != 0)
5534 {
5535 set_nomacro = 0;
5536 fputs ("\t.set\tmacro\n", file);
5537 error ("internal gcc error: .set nomacro left on in epilogue");
5538 }
5539
5540 if (set_noreorder != 0)
5541 {
5542 set_noreorder = 0;
5543 fputs ("\t.set\treorder\n", file);
5544 error ("internal gcc error: .set noreorder left on in epilogue");
5545 }
5546
5547 if (set_volatile != 0)
5548 {
5549 set_volatile = 0;
5550 fprintf (file, "\t%s.set\tnovolatile\n", (TARGET_MIPS_AS) ? "" : "#");
5551 error ("internal gcc error: .set volatile left on in epilogue");
5552 }
5553
5554 size = MIPS_STACK_ALIGN (size);
5555 tsize = (!current_frame_info.initialized)
5556 ? compute_frame_size (size)
5557 : current_frame_info.total_size;
5558
5559 if (tsize == 0 && epilogue_delay == 0)
5560 {
5561 rtx insn = get_last_insn ();
5562
5563 /* If the last insn was a BARRIER, we don't have to write any code
5564 because a jump (aka return) was put there. */
5565 if (GET_CODE (insn) == NOTE)
5566 insn = prev_nonnote_insn (insn);
5567 if (insn && GET_CODE (insn) == BARRIER)
5568 noepilogue = TRUE;
5569
5570 noreorder = FALSE;
5571 }
5572
5573 if (!noepilogue)
5574 {
5575 /* In the reload sequence, we don't need to fill the load delay
5576 slots for most of the loads, also see if we can fill the final
5577 delay slot if not otherwise filled by the reload sequence. */
5578
5579 if (noreorder)
5580 fprintf (file, "\t.set\tnoreorder\n");
5581
5582 if (tsize > 32767)
5583 {
5584 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n", t1_str, (long)tsize, (long)tsize);
5585 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
5586 }
5587
5588 if (frame_pointer_needed)
5589 fprintf (file, "\tmove\t%s,%s\t\t\t# sp not trusted here\n",
5590 sp_str, reg_names[FRAME_POINTER_REGNUM]);
5591
5592 save_restore_insns (FALSE, tmp_rtx, tsize, file);
5593
5594 load_only_r31 = (((current_frame_info.mask
5595 & ~ (TARGET_ABICALLS && mips_abi == ABI_32
5596 ? PIC_OFFSET_TABLE_MASK : 0))
5597 == RA_MASK)
5598 && current_frame_info.fmask == 0);
5599
5600 if (noreorder)
5601 {
5602 /* If the only register saved is the return address, we need a
5603 nop, unless we have an instruction to put into it. Otherwise
5604 we don't since reloading multiple registers doesn't reference
5605 the register being loaded. */
5606
5607 if (load_only_r31)
5608 {
5609 if (epilogue_delay)
5610 final_scan_insn (XEXP (epilogue_delay, 0),
5611 file,
5612 1, /* optimize */
5613 -2, /* prescan */
5614 1); /* nopeepholes */
5615 else
5616 {
5617 fprintf (file, "\tnop\n");
5618 load_nop = TRUE;
5619 }
5620 }
5621
5622 fprintf (file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 31]);
5623
5624 if (tsize > 32767)
5625 fprintf (file, "\t%s\t%s,%s,%s\n",
5626 TARGET_LONG64 ? "daddu" : "addu",
5627 sp_str, sp_str, t1_str);
5628
5629 else if (tsize > 0)
5630 fprintf (file, "\t%s\t%s,%s,%d\n",
5631 TARGET_LONG64 ? "daddu" : "addu",
5632 sp_str, sp_str, tsize);
5633
5634 else if (!load_only_r31 && epilogue_delay != 0)
5635 final_scan_insn (XEXP (epilogue_delay, 0),
5636 file,
5637 1, /* optimize */
5638 -2, /* prescan */
5639 1); /* nopeepholes */
5640
5641 fprintf (file, "\t.set\treorder\n");
5642 }
5643
5644 else
5645 {
5646 if (tsize > 32767)
5647 fprintf (file, "\t%s\t%s,%s,%s\n",
5648 TARGET_LONG64 ? "daddu" : "addu",
5649 sp_str, sp_str, t1_str);
5650
5651 else if (tsize > 0)
5652 fprintf (file, "\t%s\t%s,%s,%d\n",
5653 TARGET_LONG64 ? "daddu" : "addu",
5654 sp_str, sp_str, tsize);
5655
5656 fprintf (file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 31]);
5657 }
5658 }
5659
5660 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5661 /* Get the function name the same way that toplev.c does before calling
5662 assemble_start_function. This is needed so that the name used here
5663 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5664 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
5665
5666 fputs ("\t.end\t", file);
5667 assemble_name (file, fnname);
5668 fputs ("\n", file);
5669 #endif
5670
5671 if (TARGET_STATS)
5672 {
5673 int num_gp_regs = current_frame_info.gp_reg_size / 4;
5674 int num_fp_regs = current_frame_info.fp_reg_size / 8;
5675 int num_regs = num_gp_regs + num_fp_regs;
5676 char *name = fnname;
5677
5678 if (name[0] == '*')
5679 name++;
5680
5681 dslots_load_total += num_regs;
5682
5683 if (!noepilogue)
5684 dslots_jump_total++;
5685
5686 if (noreorder)
5687 {
5688 dslots_load_filled += num_regs;
5689
5690 /* If the only register saved is the return register, we
5691 can't fill this register's delay slot. */
5692
5693 if (load_only_r31 && epilogue_delay == 0)
5694 dslots_load_filled--;
5695
5696 if (tsize > 0 || (!load_only_r31 && epilogue_delay != 0))
5697 dslots_jump_filled++;
5698 }
5699
5700 fprintf (stderr,
5701 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5702 name,
5703 (frame_pointer_needed) ? 'y' : 'n',
5704 ((current_frame_info.mask & RA_MASK) != 0) ? 'n' : 'y',
5705 (current_function_calls_alloca) ? 'y' : 'n',
5706 (current_function_calls_setjmp) ? 'y' : 'n',
5707 (long)current_frame_info.total_size,
5708 (long)current_function_outgoing_args_size,
5709 num_gp_regs, num_fp_regs,
5710 dslots_load_total, dslots_load_filled,
5711 dslots_jump_total, dslots_jump_filled,
5712 num_refs[0], num_refs[1], num_refs[2]);
5713
5714 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
5715 {
5716 fprintf (stderr, " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
5717 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
5718 }
5719
5720 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
5721 {
5722 fprintf (stderr, " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
5723 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
5724 }
5725
5726 fputc ('\n', stderr);
5727 }
5728
5729 /* Reset state info for each function. */
5730 inside_function = FALSE;
5731 ignore_line_number = FALSE;
5732 dslots_load_total = 0;
5733 dslots_jump_total = 0;
5734 dslots_load_filled = 0;
5735 dslots_jump_filled = 0;
5736 num_refs[0] = 0;
5737 num_refs[1] = 0;
5738 num_refs[2] = 0;
5739 mips_load_reg = (rtx)0;
5740 mips_load_reg2 = (rtx)0;
5741 current_frame_info = zero_frame_info;
5742
5743 /* Restore the output file if optimizing the GP (optimizing the GP causes
5744 the text to be diverted to a tempfile, so that data decls come before
5745 references to the data). */
5746
5747 if (TARGET_GP_OPT)
5748 asm_out_file = asm_out_data_file;
5749 }
5750
5751 \f
5752 /* Expand the epilogue into a bunch of separate insns. */
5753
5754 void
5755 mips_expand_epilogue ()
5756 {
5757 long tsize = current_frame_info.total_size;
5758 rtx tsize_rtx = GEN_INT (tsize);
5759 rtx tmp_rtx = (rtx)0;
5760
5761 if (tsize > 32767)
5762 {
5763 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
5764 emit_move_insn (tmp_rtx, tsize_rtx);
5765 tsize_rtx = tmp_rtx;
5766 }
5767
5768 if (tsize > 0)
5769 {
5770 if (frame_pointer_needed)
5771 {
5772 if (TARGET_LONG64)
5773 emit_insn (gen_movdi (stack_pointer_rtx, frame_pointer_rtx));
5774 else
5775 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
5776 }
5777
5778 save_restore_insns (FALSE, tmp_rtx, tsize, (FILE *)0);
5779
5780 if (TARGET_LONG64)
5781 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
5782 tsize_rtx));
5783 else
5784 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
5785 tsize_rtx));
5786 }
5787
5788 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode, GP_REG_FIRST+31)));
5789 }
5790
5791 \f
5792 /* Define the number of delay slots needed for the function epilogue.
5793
5794 On the mips, we need a slot if either no stack has been allocated,
5795 or the only register saved is the return register. */
5796
5797 int
5798 mips_epilogue_delay_slots ()
5799 {
5800 if (!current_frame_info.initialized)
5801 (void) compute_frame_size (get_frame_size ());
5802
5803 if (current_frame_info.total_size == 0)
5804 return 1;
5805
5806 if (current_frame_info.mask == RA_MASK && current_frame_info.fmask == 0)
5807 return 1;
5808
5809 return 0;
5810 }
5811
5812 \f
5813 /* Return true if this function is known to have a null epilogue.
5814 This allows the optimizer to omit jumps to jumps if no stack
5815 was created. */
5816
5817 int
5818 simple_epilogue_p ()
5819 {
5820 if (!reload_completed)
5821 return 0;
5822
5823 if (current_frame_info.initialized)
5824 return current_frame_info.total_size == 0;
5825
5826 return (compute_frame_size (get_frame_size ())) == 0;
5827 }
5828 \f
5829 /* Choose the section to use for the constant rtx expression X that has
5830 mode MODE. */
5831
5832 mips_select_rtx_section (mode, x)
5833 enum machine_mode mode;
5834 rtx x;
5835 {
5836 if (TARGET_EMBEDDED_DATA)
5837 {
5838 /* For embedded applications, always put constants in read-only data,
5839 in order to reduce RAM usage. */
5840 READONLY_DATA_SECTION ();
5841 }
5842 else
5843 {
5844 /* For hosted applications, always put constants in small data if
5845 possible, as this gives the best performance. */
5846
5847 if (GET_MODE_SIZE (mode) <= mips_section_threshold
5848 && mips_section_threshold > 0)
5849 SMALL_DATA_SECTION ();
5850 else
5851 READONLY_DATA_SECTION ();
5852 }
5853 }
5854
5855 /* Choose the section to use for DECL. RELOC is true if its value contains
5856 any relocatable expression. */
5857
5858 mips_select_section (decl, reloc)
5859 tree decl;
5860 int reloc;
5861 {
5862 int size = int_size_in_bytes (TREE_TYPE (decl));
5863
5864 if (TARGET_EMBEDDED_PIC
5865 && TREE_CODE (decl) == STRING_CST
5866 && !flag_writable_strings)
5867 {
5868 /* For embedded position independent code, put constant strings
5869 in the text section, because the data section is limited to
5870 64K in size. */
5871
5872 text_section ();
5873 }
5874 else if (TARGET_EMBEDDED_DATA)
5875 {
5876 /* For embedded applications, always put an object in read-only data
5877 if possible, in order to reduce RAM usage. */
5878
5879 if (((TREE_CODE (decl) == VAR_DECL
5880 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
5881 && DECL_INITIAL (decl)
5882 && (DECL_INITIAL (decl) == error_mark_node
5883 || TREE_CONSTANT (DECL_INITIAL (decl))))
5884 /* Deal with calls from output_constant_def_contents. */
5885 || (TREE_CODE (decl) != VAR_DECL
5886 && (TREE_CODE (decl) != STRING_CST
5887 || !flag_writable_strings)))
5888 && ! (flag_pic && reloc))
5889 READONLY_DATA_SECTION ();
5890 else if (size > 0 && size <= mips_section_threshold)
5891 SMALL_DATA_SECTION ();
5892 else
5893 data_section ();
5894 }
5895 else
5896 {
5897 /* For hosted applications, always put an object in small data if
5898 possible, as this gives the best performance. */
5899
5900 if (size > 0 && size <= mips_section_threshold)
5901 SMALL_DATA_SECTION ();
5902 else if (((TREE_CODE (decl) == VAR_DECL
5903 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
5904 && DECL_INITIAL (decl)
5905 && (DECL_INITIAL (decl) == error_mark_node
5906 || TREE_CONSTANT (DECL_INITIAL (decl))))
5907 /* Deal with calls from output_constant_def_contents. */
5908 || (TREE_CODE (decl) != VAR_DECL
5909 && (TREE_CODE (decl) != STRING_CST
5910 || !flag_writable_strings)))
5911 && ! (flag_pic && reloc))
5912 READONLY_DATA_SECTION ();
5913 else
5914 data_section ();
5915 }
5916 }
5917 \f
5918 #ifdef MIPS_ABI_DEFAULT
5919 /* Support functions for the 64 bit ABI. */
5920
5921 /* Return register to use for a function return value with VALTYPE for function
5922 FUNC. */
5923
5924 rtx
5925 mips_function_value (valtype, func)
5926 tree valtype;
5927 tree func;
5928 {
5929 int reg = GP_RETURN;
5930 enum machine_mode mode = TYPE_MODE (valtype);
5931 enum mode_class mclass = GET_MODE_CLASS (mode);
5932
5933 /* ??? How should we return complex float? */
5934 if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
5935 {
5936 if (TARGET_SINGLE_FLOAT
5937 && (mclass == MODE_FLOAT
5938 ? GET_MODE_SIZE (mode) > 4
5939 : GET_MODE_SIZE (mode) / 2 > 4))
5940 reg = GP_RETURN;
5941 else
5942 reg = FP_RETURN;
5943 }
5944 else if (TREE_CODE (valtype) == RECORD_TYPE
5945 && mips_abi != ABI_32 && mips_abi != ABI_EABI)
5946 {
5947 /* A struct with only one or two floating point fields is returned in
5948 the floating point registers. */
5949 tree field, fields[2];
5950 int i;
5951
5952 for (i = 0, field = TYPE_FIELDS (valtype); field;
5953 field = TREE_CHAIN (field))
5954 {
5955 if (TREE_CODE (field) != FIELD_DECL)
5956 continue;
5957 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
5958 break;
5959
5960 fields[i++] = field;
5961 }
5962
5963 /* Must check i, so that we reject structures with no elements. */
5964 if (! field)
5965 {
5966 if (i == 1)
5967 {
5968 /* The structure has DImode, but we don't allow DImode values
5969 in FP registers, so we use a PARALLEL even though it isn't
5970 strictly necessary. */
5971 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
5972
5973 return gen_rtx (PARALLEL, mode,
5974 gen_rtvec (1,
5975 gen_rtx (EXPR_LIST, VOIDmode,
5976 gen_rtx (REG, field_mode, FP_RETURN),
5977 const0_rtx)));
5978 }
5979 else if (i == 2)
5980 {
5981 enum machine_mode first_mode
5982 = TYPE_MODE (TREE_TYPE (fields[0]));
5983 enum machine_mode second_mode
5984 = TYPE_MODE (TREE_TYPE (fields[1]));
5985 int first_offset
5986 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[0]));
5987 int second_offset
5988 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[1]));
5989
5990 return gen_rtx (PARALLEL, mode,
5991 gen_rtvec (2,
5992 gen_rtx (EXPR_LIST, VOIDmode,
5993 gen_rtx (REG, first_mode, FP_RETURN),
5994 GEN_INT (first_offset / BITS_PER_UNIT)),
5995 gen_rtx (EXPR_LIST, VOIDmode,
5996 gen_rtx (REG, second_mode, FP_RETURN + 2),
5997 GEN_INT (second_offset / BITS_PER_UNIT))));
5998 }
5999 }
6000 }
6001
6002 return gen_rtx (REG, mode, reg);
6003 }
6004
6005 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
6006 nonzero when an argument must be passed by reference. */
6007
6008 int
6009 function_arg_pass_by_reference (cum, mode, type, named)
6010 CUMULATIVE_ARGS *cum;
6011 enum machine_mode mode;
6012 tree type;
6013 int named;
6014 {
6015 int size;
6016
6017 if (mips_abi != ABI_EABI)
6018 return 0;
6019
6020 /* ??? How should SCmode be handled? */
6021 if (type == NULL_TREE || mode == DImode || mode == DFmode)
6022 return 0;
6023
6024 size = int_size_in_bytes (type);
6025 return size == -1 || size > UNITS_PER_WORD;
6026 }
6027
6028 #endif
6029
6030 /* This function returns the register class required for a secondary
6031 register when copying between one of the registers in CLASS, and X,
6032 using MODE. If IN_P is nonzero, the copy is going from X to the
6033 register, otherwise the register is the source. A return value of
6034 NO_REGS means that no secondary register is required. */
6035
6036 enum reg_class
6037 mips_secondary_reload_class (class, mode, x, in_p)
6038 enum reg_class class;
6039 enum machine_mode mode;
6040 rtx x;
6041 int in_p;
6042 {
6043 int regno = -1;
6044
6045 if (GET_CODE (x) == SIGN_EXTEND)
6046 {
6047 int off = 0;
6048
6049 x = XEXP (x, 0);
6050
6051 /* We may be called with reg_renumber NULL from regclass.
6052 ??? This is probably a bug. */
6053 if (reg_renumber)
6054 regno = true_regnum (x);
6055 else
6056 {
6057 while (GET_CODE (x) == SUBREG)
6058 {
6059 off += SUBREG_WORD (x);
6060 x = SUBREG_REG (x);
6061 }
6062 if (GET_CODE (x) == REG)
6063 regno = REGNO (x) + off;
6064 }
6065 }
6066 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
6067 regno = true_regnum (x);
6068
6069 /* We always require a general register when copying anything to
6070 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
6071 to a general register, or when copying from register 0. */
6072 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
6073 {
6074 if (! in_p
6075 && GP_REG_P (regno)
6076 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
6077 return NO_REGS;
6078 return GR_REGS;
6079 }
6080 if (regno == HILO_REGNUM)
6081 {
6082 if (in_p
6083 && class == GR_REGS
6084 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
6085 return NO_REGS;
6086 return GR_REGS;
6087 }
6088
6089 /* Copying from HI or LO to anywhere other than a general register
6090 requires a general register. */
6091 if (class == HI_REG || class == LO_REG || class == MD_REGS)
6092 {
6093 if (GP_REG_P (regno))
6094 return NO_REGS;
6095 return GR_REGS;
6096 }
6097 if (MD_REG_P (regno))
6098 {
6099 if (class == GR_REGS)
6100 return NO_REGS;
6101 return GR_REGS;
6102 }
6103
6104 /* We can only copy a value to a condition code register from a
6105 floating point register, and even then we require a scratch
6106 floating point register. We can only copy a value out of a
6107 condition code register into a general register. */
6108 if (class == ST_REGS)
6109 {
6110 if (in_p)
6111 return FP_REGS;
6112 if (GP_REG_P (regno))
6113 return NO_REGS;
6114 return GR_REGS;
6115 }
6116 if (ST_REG_P (regno))
6117 {
6118 if (! in_p)
6119 return FP_REGS;
6120 if (class == GR_REGS)
6121 return NO_REGS;
6122 return GR_REGS;
6123 }
6124
6125 return NO_REGS;
6126 }