1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
46 #include "hash-table.h"
49 #include "target-def.h"
50 #include "common/common-target.h"
51 #include "langhooks.h"
52 #include "sched-int.h"
55 #include "diagnostic.h"
56 #include "target-globals.h"
58 #include "tree-pass.h"
61 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save and restore registers.
78 The value for normal-mode code must be a SMALL_OPERAND and must
79 preserve the maximum stack alignment. We therefore use a value
80 of 0x7ff0 in this case.
82 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
83 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
85 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
86 up to 0x7f8 bytes and can usually save or restore all the registers
87 that we need to save or restore. (Note that we can only use these
88 instructions for o32, for which the stack alignment is 8 bytes.)
90 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
91 RESTORE are not available. We can then use unextended instructions
92 to save and restore registers, and to allocate and deallocate the top
94 #define MIPS_MAX_FIRST_STACK_STEP \
95 (!TARGET_COMPRESSION ? 0x7ff0 \
96 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
97 : TARGET_64BIT ? 0x100 : 0x400)
99 /* True if INSN is a mips.md pattern or asm statement. */
100 /* ??? This test exists through the compiler, perhaps it should be
102 #define USEFUL_INSN_P(INSN) \
103 (NONDEBUG_INSN_P (INSN) \
104 && GET_CODE (PATTERN (INSN)) != USE \
105 && GET_CODE (PATTERN (INSN)) != CLOBBER)
107 /* If INSN is a delayed branch sequence, return the first instruction
108 in the sequence, otherwise return INSN itself. */
109 #define SEQ_BEGIN(INSN) \
110 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
111 ? XVECEXP (PATTERN (INSN), 0, 0) \
114 /* Likewise for the last instruction in a delayed branch sequence. */
115 #define SEQ_END(INSN) \
116 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
117 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
120 /* Execute the following loop body with SUBINSN set to each instruction
121 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
122 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
123 for ((SUBINSN) = SEQ_BEGIN (INSN); \
124 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
125 (SUBINSN) = NEXT_INSN (SUBINSN))
127 /* True if bit BIT is set in VALUE. */
128 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
130 /* Return the opcode for a ptr_mode load of the form:
132 l[wd] DEST, OFFSET(BASE). */
133 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
134 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
139 /* Return the opcode to move register SRC into register DEST. */
140 #define MIPS_MOVE(DEST, SRC) \
141 ((TARGET_64BIT ? 0x2d : 0x21) \
145 /* Return the opcode for:
148 #define MIPS_LUI(DEST, VALUE) \
149 ((0xf << 26) | ((DEST) << 16) | (VALUE))
151 /* Return the opcode to jump to register DEST. */
152 #define MIPS_JR(DEST) \
153 (((DEST) << 21) | 0x8)
155 /* Return the opcode for:
157 bal . + (1 + OFFSET) * 4. */
158 #define MIPS_BAL(OFFSET) \
159 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
161 /* Return the usual opcode for a nop. */
164 /* Classifies an address.
167 A natural register + offset address. The register satisfies
168 mips_valid_base_register_p and the offset is a const_arith_operand.
171 A LO_SUM rtx. The first operand is a valid base register and
172 the second operand is a symbolic address.
175 A signed 16-bit constant address.
178 A constant symbolic address. */
179 enum mips_address_type
{
186 /* Macros to create an enumeration identifier for a function prototype. */
187 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
188 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
189 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
190 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
192 /* Classifies the prototype of a built-in function. */
193 enum mips_function_type
{
194 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
195 #include "config/mips/mips-ftypes.def"
196 #undef DEF_MIPS_FTYPE
200 /* Specifies how a built-in function should be converted into rtl. */
201 enum mips_builtin_type
{
202 /* The function corresponds directly to an .md pattern. The return
203 value is mapped to operand 0 and the arguments are mapped to
204 operands 1 and above. */
207 /* The function corresponds directly to an .md pattern. There is no return
208 value and the arguments are mapped to operands 0 and above. */
209 MIPS_BUILTIN_DIRECT_NO_TARGET
,
211 /* The function corresponds to a comparison instruction followed by
212 a mips_cond_move_tf_ps pattern. The first two arguments are the
213 values to compare and the second two arguments are the vector
214 operands for the movt.ps or movf.ps instruction (in assembly order). */
218 /* The function corresponds to a V2SF comparison instruction. Operand 0
219 of this instruction is the result of the comparison, which has mode
220 CCV2 or CCV4. The function arguments are mapped to operands 1 and
221 above. The function's return value is an SImode boolean that is
222 true under the following conditions:
224 MIPS_BUILTIN_CMP_ANY: one of the registers is true
225 MIPS_BUILTIN_CMP_ALL: all of the registers are true
226 MIPS_BUILTIN_CMP_LOWER: the first register is true
227 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
228 MIPS_BUILTIN_CMP_ANY
,
229 MIPS_BUILTIN_CMP_ALL
,
230 MIPS_BUILTIN_CMP_UPPER
,
231 MIPS_BUILTIN_CMP_LOWER
,
233 /* As above, but the instruction only sets a single $fcc register. */
234 MIPS_BUILTIN_CMP_SINGLE
,
236 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
237 MIPS_BUILTIN_BPOSGE32
240 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
241 #define MIPS_FP_CONDITIONS(MACRO) \
259 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
260 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
261 enum mips_fp_condition
{
262 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
265 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
266 #define STRINGIFY(X) #X
267 static const char *const mips_fp_conditions
[] = {
268 MIPS_FP_CONDITIONS (STRINGIFY
)
271 /* Tuning information that is automatically derived from other sources
272 (such as the scheduler). */
274 /* The architecture and tuning settings that this structure describes. */
278 /* True if this structure describes MIPS16 settings. */
281 /* True if the structure has been initialized. */
284 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
285 when optimizing for speed. */
286 bool fast_mult_zero_zero_p
;
289 /* Information about a function's frame layout. */
290 struct GTY(()) mips_frame_info
{
291 /* The size of the frame in bytes. */
292 HOST_WIDE_INT total_size
;
294 /* The number of bytes allocated to variables. */
295 HOST_WIDE_INT var_size
;
297 /* The number of bytes allocated to outgoing function arguments. */
298 HOST_WIDE_INT args_size
;
300 /* The number of bytes allocated to the .cprestore slot, or 0 if there
302 HOST_WIDE_INT cprestore_size
;
304 /* Bit X is set if the function saves or restores GPR X. */
307 /* Likewise FPR X. */
310 /* Likewise doubleword accumulator X ($acX). */
311 unsigned int acc_mask
;
313 /* The number of GPRs, FPRs, doubleword accumulators and COP0
317 unsigned int num_acc
;
318 unsigned int num_cop0_regs
;
320 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
321 save slots from the top of the frame, or zero if no such slots are
323 HOST_WIDE_INT gp_save_offset
;
324 HOST_WIDE_INT fp_save_offset
;
325 HOST_WIDE_INT acc_save_offset
;
326 HOST_WIDE_INT cop0_save_offset
;
328 /* Likewise, but giving offsets from the bottom of the frame. */
329 HOST_WIDE_INT gp_sp_offset
;
330 HOST_WIDE_INT fp_sp_offset
;
331 HOST_WIDE_INT acc_sp_offset
;
332 HOST_WIDE_INT cop0_sp_offset
;
334 /* Similar, but the value passed to _mcount. */
335 HOST_WIDE_INT ra_fp_offset
;
337 /* The offset of arg_pointer_rtx from the bottom of the frame. */
338 HOST_WIDE_INT arg_pointer_offset
;
340 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
341 HOST_WIDE_INT hard_frame_pointer_offset
;
344 struct GTY(()) machine_function
{
345 /* The next floating-point condition-code register to allocate
346 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
347 unsigned int next_fcc
;
349 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
350 rtx mips16_gp_pseudo_rtx
;
352 /* The number of extra stack bytes taken up by register varargs.
353 This area is allocated by the callee at the very top of the frame. */
356 /* The current frame information, calculated by mips_compute_frame_info. */
357 struct mips_frame_info frame
;
359 /* The register to use as the function's global pointer, or INVALID_REGNUM
360 if the function doesn't need one. */
361 unsigned int global_pointer
;
363 /* How many instructions it takes to load a label into $AT, or 0 if
364 this property hasn't yet been calculated. */
365 unsigned int load_label_num_insns
;
367 /* True if mips_adjust_insn_length should ignore an instruction's
369 bool ignore_hazard_length_p
;
371 /* True if the whole function is suitable for .set noreorder and
373 bool all_noreorder_p
;
375 /* True if the function has "inflexible" and "flexible" references
376 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
377 and mips_cfun_has_flexible_gp_ref_p for details. */
378 bool has_inflexible_gp_insn_p
;
379 bool has_flexible_gp_insn_p
;
381 /* True if the function's prologue must load the global pointer
382 value into pic_offset_table_rtx and store the same value in
383 the function's cprestore slot (if any). Even if this value
384 is currently false, we may decide to set it to true later;
385 see mips_must_initialize_gp_p () for details. */
386 bool must_initialize_gp_p
;
388 /* True if the current function must restore $gp after any potential
389 clobber. This value is only meaningful during the first post-epilogue
390 split_insns pass; see mips_must_initialize_gp_p () for details. */
391 bool must_restore_gp_when_clobbered_p
;
393 /* True if this is an interrupt handler. */
394 bool interrupt_handler_p
;
396 /* True if this is an interrupt handler that uses shadow registers. */
397 bool use_shadow_register_set_p
;
399 /* True if this is an interrupt handler that should keep interrupts
401 bool keep_interrupts_masked_p
;
403 /* True if this is an interrupt handler that should use DERET
405 bool use_debug_exception_return_p
;
408 /* Information about a single argument. */
409 struct mips_arg_info
{
410 /* True if the argument is passed in a floating-point register, or
411 would have been if we hadn't run out of registers. */
414 /* The number of words passed in registers, rounded up. */
415 unsigned int reg_words
;
417 /* For EABI, the offset of the first register from GP_ARG_FIRST or
418 FP_ARG_FIRST. For other ABIs, the offset of the first register from
419 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
420 comment for details).
422 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
424 unsigned int reg_offset
;
426 /* The number of words that must be passed on the stack, rounded up. */
427 unsigned int stack_words
;
429 /* The offset from the start of the stack overflow area of the argument's
430 first stack word. Only meaningful when STACK_WORDS is nonzero. */
431 unsigned int stack_offset
;
434 /* Information about an address described by mips_address_type.
440 REG is the base register and OFFSET is the constant offset.
443 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
444 is the type of symbol it references.
447 SYMBOL_TYPE is the type of symbol that the address references. */
448 struct mips_address_info
{
449 enum mips_address_type type
;
452 enum mips_symbol_type symbol_type
;
455 /* One stage in a constant building sequence. These sequences have
459 A = A CODE[1] VALUE[1]
460 A = A CODE[2] VALUE[2]
463 where A is an accumulator, each CODE[i] is a binary rtl operation
464 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
465 struct mips_integer_op
{
467 unsigned HOST_WIDE_INT value
;
470 /* The largest number of operations needed to load an integer constant.
471 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
472 When the lowest bit is clear, we can try, but reject a sequence with
473 an extra SLL at the end. */
474 #define MIPS_MAX_INTEGER_OPS 7
476 /* Information about a MIPS16e SAVE or RESTORE instruction. */
477 struct mips16e_save_restore_info
{
478 /* The number of argument registers saved by a SAVE instruction.
479 0 for RESTORE instructions. */
482 /* Bit X is set if the instruction saves or restores GPR X. */
485 /* The total number of bytes to allocate. */
489 /* Costs of various operations on the different architectures. */
491 struct mips_rtx_cost_data
493 unsigned short fp_add
;
494 unsigned short fp_mult_sf
;
495 unsigned short fp_mult_df
;
496 unsigned short fp_div_sf
;
497 unsigned short fp_div_df
;
498 unsigned short int_mult_si
;
499 unsigned short int_mult_di
;
500 unsigned short int_div_si
;
501 unsigned short int_div_di
;
502 unsigned short branch_cost
;
503 unsigned short memory_latency
;
506 /* Global variables for machine-dependent things. */
508 /* The -G setting, or the configuration's default small-data limit if
509 no -G option is given. */
510 static unsigned int mips_small_data_threshold
;
512 /* The number of file directives written by mips_output_filename. */
513 int num_source_filenames
;
515 /* The name that appeared in the last .file directive written by
516 mips_output_filename, or "" if mips_output_filename hasn't
517 written anything yet. */
518 const char *current_function_file
= "";
520 /* Arrays that map GCC register numbers to debugger register numbers. */
521 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
522 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
524 /* Information about the current function's epilogue, used only while
527 /* A list of queued REG_CFA_RESTORE notes. */
530 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
532 HOST_WIDE_INT cfa_offset
;
534 /* The offset of the CFA from the stack pointer while restoring
536 HOST_WIDE_INT cfa_restore_sp_offset
;
539 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
540 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
541 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
542 struct mips_asm_switch mips_noat
= { "at", 0 };
544 /* True if we're writing out a branch-likely instruction rather than a
546 static bool mips_branch_likely
;
548 /* The current instruction-set architecture. */
549 enum processor mips_arch
;
550 const struct mips_cpu_info
*mips_arch_info
;
552 /* The processor that we should tune the code for. */
553 enum processor mips_tune
;
554 const struct mips_cpu_info
*mips_tune_info
;
556 /* The ISA level associated with mips_arch. */
559 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
560 static const struct mips_cpu_info
*mips_isa_option_info
;
562 /* Which cost information to use. */
563 static const struct mips_rtx_cost_data
*mips_cost
;
565 /* The ambient target flags, excluding MASK_MIPS16. */
566 static int mips_base_target_flags
;
568 /* The default compression mode. */
569 unsigned int mips_base_compression_flags
;
571 /* The ambient values of other global variables. */
572 static int mips_base_schedule_insns
; /* flag_schedule_insns */
573 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
574 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
575 static int mips_base_align_loops
; /* align_loops */
576 static int mips_base_align_jumps
; /* align_jumps */
577 static int mips_base_align_functions
; /* align_functions */
579 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
580 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
582 /* Index C is true if character C is a valid PRINT_OPERAND punctation
584 static bool mips_print_operand_punct
[256];
586 static GTY (()) int mips_output_filename_first_time
= 1;
588 /* mips_split_p[X] is true if symbols of type X can be split by
589 mips_split_symbol. */
590 bool mips_split_p
[NUM_SYMBOL_TYPES
];
592 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
593 can be split by mips_split_symbol. */
594 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
596 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
597 forced into a PC-relative constant pool. */
598 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
600 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
601 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
602 if they are matched by a special .md file pattern. */
603 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
605 /* Likewise for HIGHs. */
606 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
608 /* Target state for MIPS16. */
609 struct target_globals
*mips16_globals
;
611 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
612 and returned from mips_sched_reorder2. */
613 static int cached_can_issue_more
;
615 /* True if the output uses __mips16_rdhwr. */
616 static bool mips_need_mips16_rdhwr_p
;
618 /* Index R is the smallest register class that contains register R. */
619 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
620 LEA_REGS
, LEA_REGS
, M16_REGS
, V1_REG
,
621 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
622 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
623 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
624 M16_REGS
, M16_REGS
, LEA_REGS
, LEA_REGS
,
625 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
626 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
627 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
628 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
629 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
630 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
631 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
632 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
633 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
634 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
635 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
636 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
637 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
638 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
639 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
640 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
641 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
642 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
643 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
644 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
645 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
646 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
647 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
648 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
649 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
650 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
651 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
652 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
653 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
654 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
655 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
656 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
657 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
658 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
659 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
660 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
661 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
662 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
663 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
664 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
665 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
666 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
669 /* The value of TARGET_ATTRIBUTE_TABLE. */
670 static const struct attribute_spec mips_attribute_table
[] = {
671 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
673 { "long_call", 0, 0, false, true, true, NULL
, false },
674 { "far", 0, 0, false, true, true, NULL
, false },
675 { "near", 0, 0, false, true, true, NULL
, false },
676 /* We would really like to treat "mips16" and "nomips16" as type
677 attributes, but GCC doesn't provide the hooks we need to support
678 the right conversion rules. As declaration attributes, they affect
679 code generation but don't carry other semantics. */
680 { "mips16", 0, 0, true, false, false, NULL
, false },
681 { "nomips16", 0, 0, true, false, false, NULL
, false },
682 { "micromips", 0, 0, true, false, false, NULL
, false },
683 { "nomicromips", 0, 0, true, false, false, NULL
, false },
684 { "nocompression", 0, 0, true, false, false, NULL
, false },
685 /* Allow functions to be specified as interrupt handlers */
686 { "interrupt", 0, 0, false, true, true, NULL
, false },
687 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
688 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
689 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
690 { NULL
, 0, 0, false, false, false, NULL
, false }
693 /* A table describing all the processors GCC knows about; see
694 mips-cpus.def for details. */
695 static const struct mips_cpu_info mips_cpu_info_table
[] = {
696 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
697 { NAME, CPU, ISA, FLAGS },
698 #include "mips-cpus.def"
702 /* Default costs. If these are used for a processor we should look
703 up the actual costs. */
704 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
705 COSTS_N_INSNS (7), /* fp_mult_sf */ \
706 COSTS_N_INSNS (8), /* fp_mult_df */ \
707 COSTS_N_INSNS (23), /* fp_div_sf */ \
708 COSTS_N_INSNS (36), /* fp_div_df */ \
709 COSTS_N_INSNS (10), /* int_mult_si */ \
710 COSTS_N_INSNS (10), /* int_mult_di */ \
711 COSTS_N_INSNS (69), /* int_div_si */ \
712 COSTS_N_INSNS (69), /* int_div_di */ \
713 2, /* branch_cost */ \
714 4 /* memory_latency */
716 /* Floating-point costs for processors without an FPU. Just assume that
717 all floating-point libcalls are very expensive. */
718 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
719 COSTS_N_INSNS (256), /* fp_mult_sf */ \
720 COSTS_N_INSNS (256), /* fp_mult_df */ \
721 COSTS_N_INSNS (256), /* fp_div_sf */ \
722 COSTS_N_INSNS (256) /* fp_div_df */
724 /* Costs to use when optimizing for size. */
725 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
726 COSTS_N_INSNS (1), /* fp_add */
727 COSTS_N_INSNS (1), /* fp_mult_sf */
728 COSTS_N_INSNS (1), /* fp_mult_df */
729 COSTS_N_INSNS (1), /* fp_div_sf */
730 COSTS_N_INSNS (1), /* fp_div_df */
731 COSTS_N_INSNS (1), /* int_mult_si */
732 COSTS_N_INSNS (1), /* int_mult_di */
733 COSTS_N_INSNS (1), /* int_div_si */
734 COSTS_N_INSNS (1), /* int_div_di */
736 4 /* memory_latency */
739 /* Costs to use when optimizing for speed, indexed by processor. */
740 static const struct mips_rtx_cost_data
741 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
743 COSTS_N_INSNS (2), /* fp_add */
744 COSTS_N_INSNS (4), /* fp_mult_sf */
745 COSTS_N_INSNS (5), /* fp_mult_df */
746 COSTS_N_INSNS (12), /* fp_div_sf */
747 COSTS_N_INSNS (19), /* fp_div_df */
748 COSTS_N_INSNS (12), /* int_mult_si */
749 COSTS_N_INSNS (12), /* int_mult_di */
750 COSTS_N_INSNS (35), /* int_div_si */
751 COSTS_N_INSNS (35), /* int_div_di */
753 4 /* memory_latency */
757 COSTS_N_INSNS (6), /* int_mult_si */
758 COSTS_N_INSNS (6), /* int_mult_di */
759 COSTS_N_INSNS (36), /* int_div_si */
760 COSTS_N_INSNS (36), /* int_div_di */
762 4 /* memory_latency */
766 COSTS_N_INSNS (36), /* int_mult_si */
767 COSTS_N_INSNS (36), /* int_mult_di */
768 COSTS_N_INSNS (37), /* int_div_si */
769 COSTS_N_INSNS (37), /* int_div_di */
771 4 /* memory_latency */
775 COSTS_N_INSNS (4), /* int_mult_si */
776 COSTS_N_INSNS (11), /* int_mult_di */
777 COSTS_N_INSNS (36), /* int_div_si */
778 COSTS_N_INSNS (68), /* int_div_di */
780 4 /* memory_latency */
783 COSTS_N_INSNS (4), /* fp_add */
784 COSTS_N_INSNS (4), /* fp_mult_sf */
785 COSTS_N_INSNS (5), /* fp_mult_df */
786 COSTS_N_INSNS (17), /* fp_div_sf */
787 COSTS_N_INSNS (32), /* fp_div_df */
788 COSTS_N_INSNS (4), /* int_mult_si */
789 COSTS_N_INSNS (11), /* int_mult_di */
790 COSTS_N_INSNS (36), /* int_div_si */
791 COSTS_N_INSNS (68), /* int_div_di */
793 4 /* memory_latency */
796 COSTS_N_INSNS (4), /* fp_add */
797 COSTS_N_INSNS (4), /* fp_mult_sf */
798 COSTS_N_INSNS (5), /* fp_mult_df */
799 COSTS_N_INSNS (17), /* fp_div_sf */
800 COSTS_N_INSNS (32), /* fp_div_df */
801 COSTS_N_INSNS (4), /* int_mult_si */
802 COSTS_N_INSNS (7), /* int_mult_di */
803 COSTS_N_INSNS (42), /* int_div_si */
804 COSTS_N_INSNS (72), /* int_div_di */
806 4 /* memory_latency */
810 COSTS_N_INSNS (5), /* int_mult_si */
811 COSTS_N_INSNS (5), /* int_mult_di */
812 COSTS_N_INSNS (41), /* int_div_si */
813 COSTS_N_INSNS (41), /* int_div_di */
815 4 /* memory_latency */
818 COSTS_N_INSNS (8), /* fp_add */
819 COSTS_N_INSNS (8), /* fp_mult_sf */
820 COSTS_N_INSNS (10), /* fp_mult_df */
821 COSTS_N_INSNS (34), /* fp_div_sf */
822 COSTS_N_INSNS (64), /* fp_div_df */
823 COSTS_N_INSNS (5), /* int_mult_si */
824 COSTS_N_INSNS (5), /* int_mult_di */
825 COSTS_N_INSNS (41), /* int_div_si */
826 COSTS_N_INSNS (41), /* int_div_di */
828 4 /* memory_latency */
831 COSTS_N_INSNS (4), /* fp_add */
832 COSTS_N_INSNS (4), /* fp_mult_sf */
833 COSTS_N_INSNS (5), /* fp_mult_df */
834 COSTS_N_INSNS (17), /* fp_div_sf */
835 COSTS_N_INSNS (32), /* fp_div_df */
836 COSTS_N_INSNS (5), /* int_mult_si */
837 COSTS_N_INSNS (5), /* int_mult_di */
838 COSTS_N_INSNS (41), /* int_div_si */
839 COSTS_N_INSNS (41), /* int_div_di */
841 4 /* memory_latency */
845 COSTS_N_INSNS (5), /* int_mult_si */
846 COSTS_N_INSNS (5), /* int_mult_di */
847 COSTS_N_INSNS (41), /* int_div_si */
848 COSTS_N_INSNS (41), /* int_div_di */
850 4 /* memory_latency */
853 COSTS_N_INSNS (8), /* fp_add */
854 COSTS_N_INSNS (8), /* fp_mult_sf */
855 COSTS_N_INSNS (10), /* fp_mult_df */
856 COSTS_N_INSNS (34), /* fp_div_sf */
857 COSTS_N_INSNS (64), /* fp_div_df */
858 COSTS_N_INSNS (5), /* int_mult_si */
859 COSTS_N_INSNS (5), /* int_mult_di */
860 COSTS_N_INSNS (41), /* int_div_si */
861 COSTS_N_INSNS (41), /* int_div_di */
863 4 /* memory_latency */
866 COSTS_N_INSNS (4), /* fp_add */
867 COSTS_N_INSNS (4), /* fp_mult_sf */
868 COSTS_N_INSNS (5), /* fp_mult_df */
869 COSTS_N_INSNS (17), /* fp_div_sf */
870 COSTS_N_INSNS (32), /* fp_div_df */
871 COSTS_N_INSNS (5), /* int_mult_si */
872 COSTS_N_INSNS (5), /* int_mult_di */
873 COSTS_N_INSNS (41), /* int_div_si */
874 COSTS_N_INSNS (41), /* int_div_di */
876 4 /* memory_latency */
879 COSTS_N_INSNS (6), /* fp_add */
880 COSTS_N_INSNS (6), /* fp_mult_sf */
881 COSTS_N_INSNS (7), /* fp_mult_df */
882 COSTS_N_INSNS (25), /* fp_div_sf */
883 COSTS_N_INSNS (48), /* fp_div_df */
884 COSTS_N_INSNS (5), /* int_mult_si */
885 COSTS_N_INSNS (5), /* int_mult_di */
886 COSTS_N_INSNS (41), /* int_div_si */
887 COSTS_N_INSNS (41), /* int_div_di */
889 4 /* memory_latency */
906 COSTS_N_INSNS (5), /* int_mult_si */
907 COSTS_N_INSNS (5), /* int_mult_di */
908 COSTS_N_INSNS (72), /* int_div_si */
909 COSTS_N_INSNS (72), /* int_div_di */
911 4 /* memory_latency */
916 COSTS_N_INSNS (6), /* int_mult_si */
917 COSTS_N_INSNS (6), /* int_mult_di */
918 COSTS_N_INSNS (18), /* int_div_si */
919 COSTS_N_INSNS (35), /* int_div_di */
921 4 /* memory_latency */
924 COSTS_N_INSNS (2), /* fp_add */
925 COSTS_N_INSNS (4), /* fp_mult_sf */
926 COSTS_N_INSNS (5), /* fp_mult_df */
927 COSTS_N_INSNS (12), /* fp_div_sf */
928 COSTS_N_INSNS (19), /* fp_div_df */
929 COSTS_N_INSNS (2), /* int_mult_si */
930 COSTS_N_INSNS (2), /* int_mult_di */
931 COSTS_N_INSNS (35), /* int_div_si */
932 COSTS_N_INSNS (35), /* int_div_di */
934 4 /* memory_latency */
937 COSTS_N_INSNS (3), /* fp_add */
938 COSTS_N_INSNS (5), /* fp_mult_sf */
939 COSTS_N_INSNS (6), /* fp_mult_df */
940 COSTS_N_INSNS (15), /* fp_div_sf */
941 COSTS_N_INSNS (16), /* fp_div_df */
942 COSTS_N_INSNS (17), /* int_mult_si */
943 COSTS_N_INSNS (17), /* int_mult_di */
944 COSTS_N_INSNS (38), /* int_div_si */
945 COSTS_N_INSNS (38), /* int_div_di */
947 6 /* memory_latency */
950 COSTS_N_INSNS (6), /* fp_add */
951 COSTS_N_INSNS (7), /* fp_mult_sf */
952 COSTS_N_INSNS (8), /* fp_mult_df */
953 COSTS_N_INSNS (23), /* fp_div_sf */
954 COSTS_N_INSNS (36), /* fp_div_df */
955 COSTS_N_INSNS (10), /* int_mult_si */
956 COSTS_N_INSNS (10), /* int_mult_di */
957 COSTS_N_INSNS (69), /* int_div_si */
958 COSTS_N_INSNS (69), /* int_div_di */
960 6 /* memory_latency */
972 /* The only costs that appear to be updated here are
973 integer multiplication. */
975 COSTS_N_INSNS (4), /* int_mult_si */
976 COSTS_N_INSNS (6), /* int_mult_di */
977 COSTS_N_INSNS (69), /* int_div_si */
978 COSTS_N_INSNS (69), /* int_div_di */
980 4 /* memory_latency */
995 COSTS_N_INSNS (6), /* fp_add */
996 COSTS_N_INSNS (4), /* fp_mult_sf */
997 COSTS_N_INSNS (5), /* fp_mult_df */
998 COSTS_N_INSNS (23), /* fp_div_sf */
999 COSTS_N_INSNS (36), /* fp_div_df */
1000 COSTS_N_INSNS (5), /* int_mult_si */
1001 COSTS_N_INSNS (5), /* int_mult_di */
1002 COSTS_N_INSNS (36), /* int_div_si */
1003 COSTS_N_INSNS (36), /* int_div_di */
1004 1, /* branch_cost */
1005 4 /* memory_latency */
1008 COSTS_N_INSNS (6), /* fp_add */
1009 COSTS_N_INSNS (5), /* fp_mult_sf */
1010 COSTS_N_INSNS (6), /* fp_mult_df */
1011 COSTS_N_INSNS (30), /* fp_div_sf */
1012 COSTS_N_INSNS (59), /* fp_div_df */
1013 COSTS_N_INSNS (3), /* int_mult_si */
1014 COSTS_N_INSNS (4), /* int_mult_di */
1015 COSTS_N_INSNS (42), /* int_div_si */
1016 COSTS_N_INSNS (74), /* int_div_di */
1017 1, /* branch_cost */
1018 4 /* memory_latency */
1021 COSTS_N_INSNS (6), /* fp_add */
1022 COSTS_N_INSNS (5), /* fp_mult_sf */
1023 COSTS_N_INSNS (6), /* fp_mult_df */
1024 COSTS_N_INSNS (30), /* fp_div_sf */
1025 COSTS_N_INSNS (59), /* fp_div_df */
1026 COSTS_N_INSNS (5), /* int_mult_si */
1027 COSTS_N_INSNS (9), /* int_mult_di */
1028 COSTS_N_INSNS (42), /* int_div_si */
1029 COSTS_N_INSNS (74), /* int_div_di */
1030 1, /* branch_cost */
1031 4 /* memory_latency */
1034 COSTS_N_INSNS (4), /* fp_add */
1035 COSTS_N_INSNS (4), /* fp_mult_sf */
1036 COSTS_N_INSNS (256), /* fp_mult_df */
1037 COSTS_N_INSNS (8), /* fp_div_sf */
1038 COSTS_N_INSNS (256), /* fp_div_df */
1039 COSTS_N_INSNS (4), /* int_mult_si */
1040 COSTS_N_INSNS (256), /* int_mult_di */
1041 COSTS_N_INSNS (37), /* int_div_si */
1042 COSTS_N_INSNS (256), /* int_div_di */
1043 1, /* branch_cost */
1044 4 /* memory_latency */
1047 /* The only costs that are changed here are
1048 integer multiplication. */
1049 COSTS_N_INSNS (6), /* fp_add */
1050 COSTS_N_INSNS (7), /* fp_mult_sf */
1051 COSTS_N_INSNS (8), /* fp_mult_df */
1052 COSTS_N_INSNS (23), /* fp_div_sf */
1053 COSTS_N_INSNS (36), /* fp_div_df */
1054 COSTS_N_INSNS (5), /* int_mult_si */
1055 COSTS_N_INSNS (9), /* int_mult_di */
1056 COSTS_N_INSNS (69), /* int_div_si */
1057 COSTS_N_INSNS (69), /* int_div_di */
1058 1, /* branch_cost */
1059 4 /* memory_latency */
1065 /* The only costs that are changed here are
1066 integer multiplication. */
1067 COSTS_N_INSNS (6), /* fp_add */
1068 COSTS_N_INSNS (7), /* fp_mult_sf */
1069 COSTS_N_INSNS (8), /* fp_mult_df */
1070 COSTS_N_INSNS (23), /* fp_div_sf */
1071 COSTS_N_INSNS (36), /* fp_div_df */
1072 COSTS_N_INSNS (3), /* int_mult_si */
1073 COSTS_N_INSNS (8), /* int_mult_di */
1074 COSTS_N_INSNS (69), /* int_div_si */
1075 COSTS_N_INSNS (69), /* int_div_di */
1076 1, /* branch_cost */
1077 4 /* memory_latency */
1080 COSTS_N_INSNS (2), /* fp_add */
1081 COSTS_N_INSNS (2), /* fp_mult_sf */
1082 COSTS_N_INSNS (2), /* fp_mult_df */
1083 COSTS_N_INSNS (12), /* fp_div_sf */
1084 COSTS_N_INSNS (19), /* fp_div_df */
1085 COSTS_N_INSNS (5), /* int_mult_si */
1086 COSTS_N_INSNS (9), /* int_mult_di */
1087 COSTS_N_INSNS (34), /* int_div_si */
1088 COSTS_N_INSNS (66), /* int_div_di */
1089 1, /* branch_cost */
1090 4 /* memory_latency */
1093 /* These costs are the same as the SB-1A below. */
1094 COSTS_N_INSNS (4), /* fp_add */
1095 COSTS_N_INSNS (4), /* fp_mult_sf */
1096 COSTS_N_INSNS (4), /* fp_mult_df */
1097 COSTS_N_INSNS (24), /* fp_div_sf */
1098 COSTS_N_INSNS (32), /* fp_div_df */
1099 COSTS_N_INSNS (3), /* int_mult_si */
1100 COSTS_N_INSNS (4), /* int_mult_di */
1101 COSTS_N_INSNS (36), /* int_div_si */
1102 COSTS_N_INSNS (68), /* int_div_di */
1103 1, /* branch_cost */
1104 4 /* memory_latency */
1107 /* These costs are the same as the SB-1 above. */
1108 COSTS_N_INSNS (4), /* fp_add */
1109 COSTS_N_INSNS (4), /* fp_mult_sf */
1110 COSTS_N_INSNS (4), /* fp_mult_df */
1111 COSTS_N_INSNS (24), /* fp_div_sf */
1112 COSTS_N_INSNS (32), /* fp_div_df */
1113 COSTS_N_INSNS (3), /* int_mult_si */
1114 COSTS_N_INSNS (4), /* int_mult_di */
1115 COSTS_N_INSNS (36), /* int_div_si */
1116 COSTS_N_INSNS (68), /* int_div_di */
1117 1, /* branch_cost */
1118 4 /* memory_latency */
1125 COSTS_N_INSNS (8), /* int_mult_si */
1126 COSTS_N_INSNS (8), /* int_mult_di */
1127 COSTS_N_INSNS (72), /* int_div_si */
1128 COSTS_N_INSNS (72), /* int_div_di */
1129 1, /* branch_cost */
1130 4 /* memory_latency */
1133 /* These costs are the same as 5KF above. */
1134 COSTS_N_INSNS (4), /* fp_add */
1135 COSTS_N_INSNS (4), /* fp_mult_sf */
1136 COSTS_N_INSNS (5), /* fp_mult_df */
1137 COSTS_N_INSNS (17), /* fp_div_sf */
1138 COSTS_N_INSNS (32), /* fp_div_df */
1139 COSTS_N_INSNS (4), /* int_mult_si */
1140 COSTS_N_INSNS (11), /* int_mult_di */
1141 COSTS_N_INSNS (36), /* int_div_si */
1142 COSTS_N_INSNS (68), /* int_div_di */
1143 1, /* branch_cost */
1144 4 /* memory_latency */
1148 static rtx
mips_find_pic_call_symbol (rtx
, rtx
, bool);
1149 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1151 static unsigned int mips_function_arg_boundary (enum machine_mode
, const_tree
);
1153 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1154 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1155 struct GTY (()) mflip_mips16_entry
{
1159 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1161 /* Hash table callbacks for mflip_mips16_htab. */
1164 mflip_mips16_htab_hash (const void *entry
)
1166 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1170 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1172 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1173 (const char *) name
) == 0;
1176 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1177 mode, false if it should next add an attribute for the opposite mode. */
1178 static GTY(()) bool mips16_flipper
;
1180 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1181 for -mflip-mips16. Return true if it should use "mips16" and false if
1182 it should use "nomips16". */
1185 mflip_mips16_use_mips16_p (tree decl
)
1187 struct mflip_mips16_entry
*entry
;
1191 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1193 /* Use the opposite of the command-line setting for anonymous decls. */
1194 if (!DECL_NAME (decl
))
1195 return !base_is_mips16
;
1197 if (!mflip_mips16_htab
)
1198 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1199 mflip_mips16_htab_eq
, NULL
);
1201 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1202 hash
= htab_hash_string (name
);
1203 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1204 entry
= (struct mflip_mips16_entry
*) *slot
;
1207 mips16_flipper
= !mips16_flipper
;
1208 entry
= ggc_alloc_mflip_mips16_entry ();
1210 entry
->mips16_p
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1213 return entry
->mips16_p
;
1216 /* Predicates to test for presence of "near" and "far"/"long_call"
1217 attributes on the given TYPE. */
1220 mips_near_type_p (const_tree type
)
1222 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1226 mips_far_type_p (const_tree type
)
1228 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1229 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1233 /* Check if the interrupt attribute is set for a function. */
1236 mips_interrupt_type_p (tree type
)
1238 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1241 /* Check if the attribute to use shadow register set is set for a function. */
1244 mips_use_shadow_register_set_p (tree type
)
1246 return lookup_attribute ("use_shadow_register_set",
1247 TYPE_ATTRIBUTES (type
)) != NULL
;
1250 /* Check if the attribute to keep interrupts masked is set for a function. */
1253 mips_keep_interrupts_masked_p (tree type
)
1255 return lookup_attribute ("keep_interrupts_masked",
1256 TYPE_ATTRIBUTES (type
)) != NULL
;
1259 /* Check if the attribute to use debug exception return is set for
1263 mips_use_debug_exception_return_p (tree type
)
1265 return lookup_attribute ("use_debug_exception_return",
1266 TYPE_ATTRIBUTES (type
)) != NULL
;
1269 /* Return the set of compression modes that are explicitly required
1270 by the attributes in ATTRIBUTES. */
1273 mips_get_compress_on_flags (tree attributes
)
1275 unsigned int flags
= 0;
1277 if (lookup_attribute ("mips16", attributes
) != NULL
)
1278 flags
|= MASK_MIPS16
;
1280 if (lookup_attribute ("micromips", attributes
) != NULL
)
1281 flags
|= MASK_MICROMIPS
;
1286 /* Return the set of compression modes that are explicitly forbidden
1287 by the attributes in ATTRIBUTES. */
1290 mips_get_compress_off_flags (tree attributes
)
1292 unsigned int flags
= 0;
1294 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1295 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1297 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1298 flags
|= MASK_MIPS16
;
1300 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1301 flags
|= MASK_MICROMIPS
;
1306 /* Return the compression mode that should be used for function DECL.
1307 Return the ambient setting if DECL is null. */
1310 mips_get_compress_mode (tree decl
)
1312 unsigned int flags
, force_on
;
1314 flags
= mips_base_compression_flags
;
1317 /* Nested functions must use the same frame pointer as their
1318 parent and must therefore use the same ISA mode. */
1319 tree parent
= decl_function_context (decl
);
1322 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1325 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1330 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1334 mips_get_compress_on_name (unsigned int flags
)
1336 if (flags
== MASK_MIPS16
)
1341 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1345 mips_get_compress_off_name (unsigned int flags
)
1347 if (flags
== MASK_MIPS16
)
1349 if (flags
== MASK_MICROMIPS
)
1350 return "nomicromips";
1351 return "nocompression";
1354 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1357 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1359 /* Disallow mixed near/far attributes. */
1360 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1362 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1367 /* Implement TARGET_INSERT_ATTRIBUTES. */
1370 mips_insert_attributes (tree decl
, tree
*attributes
)
1373 unsigned int compression_flags
, nocompression_flags
;
1375 /* Check for "mips16" and "nomips16" attributes. */
1376 compression_flags
= mips_get_compress_on_flags (*attributes
);
1377 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1379 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1381 if (nocompression_flags
)
1382 error ("%qs attribute only applies to functions",
1383 mips_get_compress_off_name (nocompression_flags
));
1385 if (compression_flags
)
1386 error ("%qs attribute only applies to functions",
1387 mips_get_compress_on_name (nocompression_flags
));
1391 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1392 nocompression_flags
|=
1393 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1395 if (compression_flags
&& nocompression_flags
)
1396 error ("%qE cannot have both %qs and %qs attributes",
1397 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1398 mips_get_compress_off_name (nocompression_flags
));
1400 if (compression_flags
& MASK_MIPS16
1401 && compression_flags
& MASK_MICROMIPS
)
1402 error ("%qE cannot have both %qs and %qs attributes",
1403 DECL_NAME (decl
), "mips16", "micromips");
1405 if (TARGET_FLIP_MIPS16
1406 && !DECL_ARTIFICIAL (decl
)
1407 && compression_flags
== 0
1408 && nocompression_flags
== 0)
1410 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1411 "mips16" attribute, arbitrarily pick one. We must pick the same
1412 setting for duplicate declarations of a function. */
1413 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1414 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1415 name
= "nomicromips";
1416 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1421 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1424 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1428 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1429 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1431 error ("%qE redeclared with conflicting %qs attributes",
1432 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1434 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1435 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1437 error ("%qE redeclared with conflicting %qs attributes",
1438 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1440 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1441 DECL_ATTRIBUTES (newdecl
));
1444 /* Implement TARGET_CAN_INLINE_P. */
1447 mips_can_inline_p (tree caller
, tree callee
)
1449 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1451 return default_target_can_inline_p (caller
, callee
);
1454 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1455 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1458 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1460 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1462 *base_ptr
= XEXP (x
, 0);
1463 *offset_ptr
= INTVAL (XEXP (x
, 1));
1472 static unsigned int mips_build_integer (struct mips_integer_op
*,
1473 unsigned HOST_WIDE_INT
);
1475 /* A subroutine of mips_build_integer, with the same interface.
1476 Assume that the final action in the sequence should be a left shift. */
1479 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1481 unsigned int i
, shift
;
1483 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1484 since signed numbers are easier to load than unsigned ones. */
1486 while ((value
& 1) == 0)
1487 value
/= 2, shift
++;
1489 i
= mips_build_integer (codes
, value
);
1490 codes
[i
].code
= ASHIFT
;
1491 codes
[i
].value
= shift
;
1495 /* As for mips_build_shift, but assume that the final action will be
1496 an IOR or PLUS operation. */
1499 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1501 unsigned HOST_WIDE_INT high
;
1504 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1505 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1507 /* The constant is too complex to load with a simple LUI/ORI pair,
1508 so we want to give the recursive call as many trailing zeros as
1509 possible. In this case, we know bit 16 is set and that the
1510 low 16 bits form a negative number. If we subtract that number
1511 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1512 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1513 codes
[i
].code
= PLUS
;
1514 codes
[i
].value
= CONST_LOW_PART (value
);
1518 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1519 bits gives a value with at least 17 trailing zeros. */
1520 i
= mips_build_integer (codes
, high
);
1521 codes
[i
].code
= IOR
;
1522 codes
[i
].value
= value
& 0xffff;
1527 /* Fill CODES with a sequence of rtl operations to load VALUE.
1528 Return the number of operations needed. */
1531 mips_build_integer (struct mips_integer_op
*codes
,
1532 unsigned HOST_WIDE_INT value
)
1534 if (SMALL_OPERAND (value
)
1535 || SMALL_OPERAND_UNSIGNED (value
)
1536 || LUI_OPERAND (value
))
1538 /* The value can be loaded with a single instruction. */
1539 codes
[0].code
= UNKNOWN
;
1540 codes
[0].value
= value
;
1543 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1545 /* Either the constant is a simple LUI/ORI combination or its
1546 lowest bit is set. We don't want to shift in this case. */
1547 return mips_build_lower (codes
, value
);
1549 else if ((value
& 0xffff) == 0)
1551 /* The constant will need at least three actions. The lowest
1552 16 bits are clear, so the final action will be a shift. */
1553 return mips_build_shift (codes
, value
);
1557 /* The final action could be a shift, add or inclusive OR.
1558 Rather than use a complex condition to select the best
1559 approach, try both mips_build_shift and mips_build_lower
1560 and pick the one that gives the shortest sequence.
1561 Note that this case is only used once per constant. */
1562 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1563 unsigned int cost
, alt_cost
;
1565 cost
= mips_build_shift (codes
, value
);
1566 alt_cost
= mips_build_lower (alt_codes
, value
);
1567 if (alt_cost
< cost
)
1569 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1576 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1579 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1581 return mips_const_insns (x
) > 0;
1584 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1587 mips16_stub_function (const char *name
)
1591 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1592 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1596 /* Return true if symbols of type TYPE require a GOT access. */
1599 mips_got_symbol_type_p (enum mips_symbol_type type
)
1603 case SYMBOL_GOT_PAGE_OFST
:
1604 case SYMBOL_GOT_DISP
:
1612 /* Return true if X is a thread-local symbol. */
1615 mips_tls_symbol_p (rtx x
)
1617 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1620 /* Return true if SYMBOL_REF X is associated with a global symbol
1621 (in the STB_GLOBAL sense). */
1624 mips_global_symbol_p (const_rtx x
)
1626 const_tree decl
= SYMBOL_REF_DECL (x
);
1629 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1631 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1632 or weak symbols. Relocations in the object file will be against
1633 the target symbol, so it's that symbol's binding that matters here. */
1634 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1637 /* Return true if function X is a libgcc MIPS16 stub function. */
1640 mips16_stub_function_p (const_rtx x
)
1642 return (GET_CODE (x
) == SYMBOL_REF
1643 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1646 /* Return true if function X is a locally-defined and locally-binding
1650 mips16_local_function_p (const_rtx x
)
1652 return (GET_CODE (x
) == SYMBOL_REF
1653 && SYMBOL_REF_LOCAL_P (x
)
1654 && !SYMBOL_REF_EXTERNAL_P (x
)
1655 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1658 /* Return true if SYMBOL_REF X binds locally. */
1661 mips_symbol_binds_local_p (const_rtx x
)
1663 return (SYMBOL_REF_DECL (x
)
1664 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1665 : SYMBOL_REF_LOCAL_P (x
));
1668 /* Return true if rtx constants of mode MODE should be put into a small
1672 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1674 return (!TARGET_EMBEDDED_DATA
1675 && TARGET_LOCAL_SDATA
1676 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1679 /* Return true if X should not be moved directly into register $25.
1680 We need this because many versions of GAS will treat "la $25,foo" as
1681 part of a call sequence and so allow a global "foo" to be lazily bound. */
1684 mips_dangerous_for_la25_p (rtx x
)
1686 return (!TARGET_EXPLICIT_RELOCS
1688 && GET_CODE (x
) == SYMBOL_REF
1689 && mips_global_symbol_p (x
));
1692 /* Return true if calls to X might need $25 to be valid on entry. */
1695 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1697 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1700 /* MIPS16 stub functions are guaranteed not to use $25. */
1701 if (mips16_stub_function_p (x
))
1704 if (GET_CODE (x
) == SYMBOL_REF
)
1706 /* If PLTs and copy relocations are available, the static linker
1707 will make sure that $25 is valid on entry to the target function. */
1708 if (TARGET_ABICALLS_PIC0
)
1711 /* Locally-defined functions use absolute accesses to set up
1712 the global pointer. */
1713 if (TARGET_ABSOLUTE_ABICALLS
1714 && mips_symbol_binds_local_p (x
)
1715 && !SYMBOL_REF_EXTERNAL_P (x
))
1722 /* Return the method that should be used to access SYMBOL_REF or
1723 LABEL_REF X in context CONTEXT. */
1725 static enum mips_symbol_type
1726 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1729 return SYMBOL_GOT_DISP
;
1731 if (GET_CODE (x
) == LABEL_REF
)
1733 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1734 code and if we know that the label is in the current function's
1735 text section. LABEL_REFs are used for jump tables as well as
1736 text labels, so we must check whether jump tables live in the
1738 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1739 && !LABEL_REF_NONLOCAL_P (x
))
1740 return SYMBOL_PC_RELATIVE
;
1742 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1743 return SYMBOL_GOT_PAGE_OFST
;
1745 return SYMBOL_ABSOLUTE
;
1748 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1750 if (SYMBOL_REF_TLS_MODEL (x
))
1753 if (CONSTANT_POOL_ADDRESS_P (x
))
1755 if (TARGET_MIPS16_TEXT_LOADS
)
1756 return SYMBOL_PC_RELATIVE
;
1758 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1759 return SYMBOL_PC_RELATIVE
;
1761 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1762 return SYMBOL_GP_RELATIVE
;
1765 /* Do not use small-data accesses for weak symbols; they may end up
1767 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1768 return SYMBOL_GP_RELATIVE
;
1770 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1772 if (TARGET_ABICALLS_PIC2
1773 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1775 /* There are three cases to consider:
1777 - o32 PIC (either with or without explicit relocs)
1778 - n32/n64 PIC without explicit relocs
1779 - n32/n64 PIC with explicit relocs
1781 In the first case, both local and global accesses will use an
1782 R_MIPS_GOT16 relocation. We must correctly predict which of
1783 the two semantics (local or global) the assembler and linker
1784 will apply. The choice depends on the symbol's binding rather
1785 than its visibility.
1787 In the second case, the assembler will not use R_MIPS_GOT16
1788 relocations, but it chooses between local and global accesses
1789 in the same way as for o32 PIC.
1791 In the third case we have more freedom since both forms of
1792 access will work for any kind of symbol. However, there seems
1793 little point in doing things differently. */
1794 if (mips_global_symbol_p (x
))
1795 return SYMBOL_GOT_DISP
;
1797 return SYMBOL_GOT_PAGE_OFST
;
1800 return SYMBOL_ABSOLUTE
;
1803 /* Classify the base of symbolic expression X, given that X appears in
1806 static enum mips_symbol_type
1807 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1811 split_const (x
, &x
, &offset
);
1812 if (UNSPEC_ADDRESS_P (x
))
1813 return UNSPEC_ADDRESS_TYPE (x
);
1815 return mips_classify_symbol (x
, context
);
1818 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1819 is the alignment in bytes of SYMBOL_REF X. */
1822 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1824 HOST_WIDE_INT align
;
1826 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1827 return IN_RANGE (offset
, 0, align
- 1);
1830 /* Return true if X is a symbolic constant that can be used in context
1831 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1834 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1835 enum mips_symbol_type
*symbol_type
)
1839 split_const (x
, &x
, &offset
);
1840 if (UNSPEC_ADDRESS_P (x
))
1842 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1843 x
= UNSPEC_ADDRESS (x
);
1845 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1847 *symbol_type
= mips_classify_symbol (x
, context
);
1848 if (*symbol_type
== SYMBOL_TLS
)
1854 if (offset
== const0_rtx
)
1857 /* Check whether a nonzero offset is valid for the underlying
1859 switch (*symbol_type
)
1861 case SYMBOL_ABSOLUTE
:
1862 case SYMBOL_64_HIGH
:
1865 /* If the target has 64-bit pointers and the object file only
1866 supports 32-bit symbols, the values of those symbols will be
1867 sign-extended. In this case we can't allow an arbitrary offset
1868 in case the 32-bit value X + OFFSET has a different sign from X. */
1869 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1870 return offset_within_block_p (x
, INTVAL (offset
));
1872 /* In other cases the relocations can handle any offset. */
1875 case SYMBOL_PC_RELATIVE
:
1876 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1877 In this case, we no longer have access to the underlying constant,
1878 but the original symbol-based access was known to be valid. */
1879 if (GET_CODE (x
) == LABEL_REF
)
1884 case SYMBOL_GP_RELATIVE
:
1885 /* Make sure that the offset refers to something within the
1886 same object block. This should guarantee that the final
1887 PC- or GP-relative offset is within the 16-bit limit. */
1888 return offset_within_block_p (x
, INTVAL (offset
));
1890 case SYMBOL_GOT_PAGE_OFST
:
1891 case SYMBOL_GOTOFF_PAGE
:
1892 /* If the symbol is global, the GOT entry will contain the symbol's
1893 address, and we will apply a 16-bit offset after loading it.
1894 If the symbol is local, the linker should provide enough local
1895 GOT entries for a 16-bit offset, but larger offsets may lead
1897 return SMALL_INT (offset
);
1901 /* There is no carry between the HI and LO REL relocations, so the
1902 offset is only valid if we know it won't lead to such a carry. */
1903 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1905 case SYMBOL_GOT_DISP
:
1906 case SYMBOL_GOTOFF_DISP
:
1907 case SYMBOL_GOTOFF_CALL
:
1908 case SYMBOL_GOTOFF_LOADGP
:
1911 case SYMBOL_GOTTPREL
:
1919 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1920 single instruction. We rely on the fact that, in the worst case,
1921 all instructions involved in a MIPS16 address calculation are usually
1925 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1927 if (mips_use_pcrel_pool_p
[(int) type
])
1929 if (mode
== MAX_MACHINE_MODE
)
1930 /* LEAs will be converted into constant-pool references by
1932 type
= SYMBOL_PC_RELATIVE
;
1934 /* The constant must be loaded and then dereferenced. */
1940 case SYMBOL_ABSOLUTE
:
1941 /* When using 64-bit symbols, we need 5 preparatory instructions,
1944 lui $at,%highest(symbol)
1945 daddiu $at,$at,%higher(symbol)
1947 daddiu $at,$at,%hi(symbol)
1950 The final address is then $at + %lo(symbol). With 32-bit
1951 symbols we just need a preparatory LUI for normal mode and
1952 a preparatory LI and SLL for MIPS16. */
1953 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1955 case SYMBOL_GP_RELATIVE
:
1956 /* Treat GP-relative accesses as taking a single instruction on
1957 MIPS16 too; the copy of $gp can often be shared. */
1960 case SYMBOL_PC_RELATIVE
:
1961 /* PC-relative constants can be only be used with ADDIUPC,
1962 DADDIUPC, LWPC and LDPC. */
1963 if (mode
== MAX_MACHINE_MODE
1964 || GET_MODE_SIZE (mode
) == 4
1965 || GET_MODE_SIZE (mode
) == 8)
1968 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1971 case SYMBOL_GOT_DISP
:
1972 /* The constant will have to be loaded from the GOT before it
1973 is used in an address. */
1974 if (mode
!= MAX_MACHINE_MODE
)
1979 case SYMBOL_GOT_PAGE_OFST
:
1980 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1981 local/global classification is accurate. The worst cases are:
1983 (1) For local symbols when generating o32 or o64 code. The assembler
1989 ...and the final address will be $at + %lo(symbol).
1991 (2) For global symbols when -mxgot. The assembler will use:
1993 lui $at,%got_hi(symbol)
1996 ...and the final address will be $at + %got_lo(symbol). */
1999 case SYMBOL_GOTOFF_PAGE
:
2000 case SYMBOL_GOTOFF_DISP
:
2001 case SYMBOL_GOTOFF_CALL
:
2002 case SYMBOL_GOTOFF_LOADGP
:
2003 case SYMBOL_64_HIGH
:
2009 case SYMBOL_GOTTPREL
:
2012 /* A 16-bit constant formed by a single relocation, or a 32-bit
2013 constant formed from a high 16-bit relocation and a low 16-bit
2014 relocation. Use mips_split_p to determine which. 32-bit
2015 constants need an "lui; addiu" sequence for normal mode and
2016 an "li; sll; addiu" sequence for MIPS16 mode. */
2017 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2020 /* We don't treat a bare TLS symbol as a constant. */
2026 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2027 to load symbols of type TYPE into a register. Return 0 if the given
2028 type of symbol cannot be used as an immediate operand.
2030 Otherwise, return the number of instructions needed to load or store
2031 values of mode MODE to or from addresses of type TYPE. Return 0 if
2032 the given type of symbol is not valid in addresses.
2034 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2037 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
2039 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2042 /* A for_each_rtx callback. Stop the search if *X references a
2043 thread-local symbol. */
2046 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
2048 return mips_tls_symbol_p (*x
);
2051 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2054 mips_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2056 enum mips_symbol_type type
;
2059 /* There is no assembler syntax for expressing an address-sized
2061 if (GET_CODE (x
) == HIGH
)
2064 /* As an optimization, reject constants that mips_legitimize_move
2067 Suppose we have a multi-instruction sequence that loads constant C
2068 into register R. If R does not get allocated a hard register, and
2069 R is used in an operand that allows both registers and memory
2070 references, reload will consider forcing C into memory and using
2071 one of the instruction's memory alternatives. Returning false
2072 here will force it to use an input reload instead. */
2073 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2076 split_const (x
, &base
, &offset
);
2077 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2079 /* See whether we explicitly want these symbols in the pool. */
2080 if (mips_use_pcrel_pool_p
[(int) type
])
2083 /* The same optimization as for CONST_INT. */
2084 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2087 /* If MIPS16 constant pools live in the text section, they should
2088 not refer to anything that might need run-time relocation. */
2089 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2093 /* TLS symbols must be computed by mips_legitimize_move. */
2094 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
2100 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2101 constants when we're using a per-function constant pool. */
2104 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2105 const_rtx x ATTRIBUTE_UNUSED
)
2107 return !TARGET_MIPS16_PCREL_LOADS
;
2110 /* Return true if register REGNO is a valid base register for mode MODE.
2111 STRICT_P is true if REG_OK_STRICT is in effect. */
2114 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
2117 if (!HARD_REGISTER_NUM_P (regno
))
2121 regno
= reg_renumber
[regno
];
2124 /* These fake registers will be eliminated to either the stack or
2125 hard frame pointer, both of which are usually valid base registers.
2126 Reload deals with the cases where the eliminated form isn't valid. */
2127 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2130 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2131 values, nothing smaller. There are two problems here:
2133 (a) Instantiating virtual registers can introduce new uses of the
2134 stack pointer. If these virtual registers are valid addresses,
2135 the stack pointer should be too.
2137 (b) Most uses of the stack pointer are not made explicit until
2138 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2139 We don't know until that stage whether we'll be eliminating to the
2140 stack pointer (which needs the restriction) or the hard frame
2141 pointer (which doesn't).
2143 All in all, it seems more consistent to only enforce this restriction
2144 during and after reload. */
2145 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2146 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2148 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2151 /* Return true if X is a valid base register for mode MODE.
2152 STRICT_P is true if REG_OK_STRICT is in effect. */
2155 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2157 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2161 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2164 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2165 can address a value of mode MODE. */
2168 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2170 /* Check that X is a signed 16-bit number. */
2171 if (!const_arith_operand (x
, Pmode
))
2174 /* We may need to split multiword moves, so make sure that every word
2176 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2177 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2183 /* Return true if a LO_SUM can address a value of mode MODE when the
2184 LO_SUM symbol has type SYMBOL_TYPE. */
2187 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2189 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2191 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2194 /* Check that there is a known low-part relocation. */
2195 if (mips_lo_relocs
[symbol_type
] == NULL
)
2198 /* We may need to split multiword moves, so make sure that each word
2199 can be accessed without inducing a carry. This is mainly needed
2200 for o64, which has historically only guaranteed 64-bit alignment
2201 for 128-bit types. */
2202 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2203 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2209 /* Return true if X is a valid address for machine mode MODE. If it is,
2210 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2214 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2215 enum machine_mode mode
, bool strict_p
)
2217 switch (GET_CODE (x
))
2221 info
->type
= ADDRESS_REG
;
2223 info
->offset
= const0_rtx
;
2224 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2227 info
->type
= ADDRESS_REG
;
2228 info
->reg
= XEXP (x
, 0);
2229 info
->offset
= XEXP (x
, 1);
2230 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2231 && mips_valid_offset_p (info
->offset
, mode
));
2234 info
->type
= ADDRESS_LO_SUM
;
2235 info
->reg
= XEXP (x
, 0);
2236 info
->offset
= XEXP (x
, 1);
2237 /* We have to trust the creator of the LO_SUM to do something vaguely
2238 sane. Target-independent code that creates a LO_SUM should also
2239 create and verify the matching HIGH. Target-independent code that
2240 adds an offset to a LO_SUM must prove that the offset will not
2241 induce a carry. Failure to do either of these things would be
2242 a bug, and we are not required to check for it here. The MIPS
2243 backend itself should only create LO_SUMs for valid symbolic
2244 constants, with the high part being either a HIGH or a copy
2247 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2248 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2249 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2252 /* Small-integer addresses don't occur very often, but they
2253 are legitimate if $0 is a valid base register. */
2254 info
->type
= ADDRESS_CONST_INT
;
2255 return !TARGET_MIPS16
&& SMALL_INT (x
);
2260 info
->type
= ADDRESS_SYMBOLIC
;
2261 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2263 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2264 && !mips_split_p
[info
->symbol_type
]);
2271 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2274 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2276 struct mips_address_info addr
;
2278 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2281 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2284 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2286 struct mips_address_info addr
;
2288 return (mips_classify_address (&addr
, x
, mode
, false)
2289 && addr
.type
== ADDRESS_REG
2290 && addr
.reg
== stack_pointer_rtx
);
2293 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2294 address instruction. Note that such addresses are not considered
2295 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2296 is so restricted. */
2299 mips_lwxs_address_p (rtx addr
)
2302 && GET_CODE (addr
) == PLUS
2303 && REG_P (XEXP (addr
, 1)))
2305 rtx offset
= XEXP (addr
, 0);
2306 if (GET_CODE (offset
) == MULT
2307 && REG_P (XEXP (offset
, 0))
2308 && CONST_INT_P (XEXP (offset
, 1))
2309 && INTVAL (XEXP (offset
, 1)) == 4)
2315 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2316 indexed address instruction. Note that such addresses are
2317 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2318 sense, because their use is so restricted. */
2321 mips_lx_address_p (rtx addr
, enum machine_mode mode
)
2323 if (GET_CODE (addr
) != PLUS
2324 || !REG_P (XEXP (addr
, 0))
2325 || !REG_P (XEXP (addr
, 1)))
2327 if (ISA_HAS_LBX
&& mode
== QImode
)
2329 if (ISA_HAS_LHX
&& mode
== HImode
)
2331 if (ISA_HAS_LWX
&& mode
== SImode
)
2333 if (ISA_HAS_LDX
&& mode
== DImode
)
2338 /* Return true if a value at OFFSET bytes from base register BASE can be
2339 accessed using an unextended MIPS16 instruction. MODE is the mode of
2342 Usually the offset in an unextended instruction is a 5-bit field.
2343 The offset is unsigned and shifted left once for LH and SH, twice
2344 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2345 an 8-bit immediate field that's shifted left twice. */
2348 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2349 unsigned HOST_WIDE_INT offset
)
2351 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2353 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2354 return offset
< 256U * GET_MODE_SIZE (mode
);
2355 return offset
< 32U * GET_MODE_SIZE (mode
);
2360 /* Return the number of instructions needed to load or store a value
2361 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2362 length of one instruction. Return 0 if X isn't valid for MODE.
2363 Assume that multiword moves may need to be split into word moves
2364 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2368 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2370 struct mips_address_info addr
;
2373 /* BLKmode is used for single unaligned loads and stores and should
2374 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2375 meaningless, so we have to single it out as a special case one way
2377 if (mode
!= BLKmode
&& might_split_p
)
2378 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2382 if (mips_classify_address (&addr
, x
, mode
, false))
2387 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2388 UINTVAL (addr
.offset
)))
2392 case ADDRESS_LO_SUM
:
2393 return TARGET_MIPS16
? factor
* 2 : factor
;
2395 case ADDRESS_CONST_INT
:
2398 case ADDRESS_SYMBOLIC
:
2399 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2404 /* Return true if X fits within an unsigned field of BITS bits that is
2405 shifted left SHIFT bits before being used. */
2408 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2410 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2413 /* Return true if X fits within a signed field of BITS bits that is
2414 shifted left SHIFT bits before being used. */
2417 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2419 x
+= 1 << (bits
+ shift
- 1);
2420 return mips_unsigned_immediate_p (x
, bits
, shift
);
2423 /* Return true if X is legitimate for accessing values of mode MODE,
2424 if it is based on a MIPS16 register, and if the offset satisfies
2425 OFFSET_PREDICATE. */
2428 m16_based_address_p (rtx x
, enum machine_mode mode
,
2429 insn_operand_predicate_fn offset_predicate
)
2431 struct mips_address_info addr
;
2433 return (mips_classify_address (&addr
, x
, mode
, false)
2434 && addr
.type
== ADDRESS_REG
2435 && M16_REG_P (REGNO (addr
.reg
))
2436 && offset_predicate (addr
.offset
, mode
));
2439 /* Return true if X is a legitimate address that conforms to the requirements
2440 for a microMIPS LWSP or SWSP insn. */
2443 lwsp_swsp_address_p (rtx x
, enum machine_mode mode
)
2445 struct mips_address_info addr
;
2447 return (mips_classify_address (&addr
, x
, mode
, false)
2448 && addr
.type
== ADDRESS_REG
2449 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2450 && uw5_operand (addr
.offset
, mode
));
2453 /* Return true if X is a legitimate address with a 12-bit offset.
2454 MODE is the mode of the value being accessed. */
2457 umips_12bit_offset_address_p (rtx x
, enum machine_mode mode
)
2459 struct mips_address_info addr
;
2461 return (mips_classify_address (&addr
, x
, mode
, false)
2462 && addr
.type
== ADDRESS_REG
2463 && CONST_INT_P (addr
.offset
)
2464 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2467 /* Return the number of instructions needed to load constant X,
2468 assuming that BASE_INSN_LENGTH is the length of one instruction.
2469 Return 0 if X isn't a valid constant. */
2472 mips_const_insns (rtx x
)
2474 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2475 enum mips_symbol_type symbol_type
;
2478 switch (GET_CODE (x
))
2481 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2483 || !mips_split_p
[symbol_type
])
2486 /* This is simply an LUI for normal mode. It is an extended
2487 LI followed by an extended SLL for MIPS16. */
2488 return TARGET_MIPS16
? 4 : 1;
2492 /* Unsigned 8-bit constants can be loaded using an unextended
2493 LI instruction. Unsigned 16-bit constants can be loaded
2494 using an extended LI. Negative constants must be loaded
2495 using LI and then negated. */
2496 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2497 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2498 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2499 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2502 return mips_build_integer (codes
, INTVAL (x
));
2506 /* Allow zeros for normal mode, where we can use $0. */
2507 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2513 /* See if we can refer to X directly. */
2514 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2515 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2517 /* Otherwise try splitting the constant into a base and offset.
2518 If the offset is a 16-bit value, we can load the base address
2519 into a register and then use (D)ADDIU to add in the offset.
2520 If the offset is larger, we can load the base and offset
2521 into separate registers and add them together with (D)ADDU.
2522 However, the latter is only possible before reload; during
2523 and after reload, we must have the option of forcing the
2524 constant into the pool instead. */
2525 split_const (x
, &x
, &offset
);
2528 int n
= mips_const_insns (x
);
2531 if (SMALL_INT (offset
))
2533 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2534 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2541 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2549 /* X is a doubleword constant that can be handled by splitting it into
2550 two words and loading each word separately. Return the number of
2551 instructions required to do this, assuming that BASE_INSN_LENGTH
2552 is the length of one instruction. */
2555 mips_split_const_insns (rtx x
)
2557 unsigned int low
, high
;
2559 low
= mips_const_insns (mips_subword (x
, false));
2560 high
= mips_const_insns (mips_subword (x
, true));
2561 gcc_assert (low
> 0 && high
> 0);
2565 /* Return the number of instructions needed to implement INSN,
2566 given that it loads from or stores to MEM. Assume that
2567 BASE_INSN_LENGTH is the length of one instruction. */
2570 mips_load_store_insns (rtx mem
, rtx insn
)
2572 enum machine_mode mode
;
2576 gcc_assert (MEM_P (mem
));
2577 mode
= GET_MODE (mem
);
2579 /* Try to prove that INSN does not need to be split. */
2580 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2583 set
= single_set (insn
);
2584 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2585 might_split_p
= false;
2588 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2591 /* Return the number of instructions needed for an integer division,
2592 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2595 mips_idiv_insns (void)
2600 if (TARGET_CHECK_ZERO_DIV
)
2602 if (GENERATE_DIVIDE_TRAPS
)
2608 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2613 /* Emit a move from SRC to DEST. Assume that the move expanders can
2614 handle all moves if !can_create_pseudo_p (). The distinction is
2615 important because, unlike emit_move_insn, the move expanders know
2616 how to force Pmode objects into the constant pool even when the
2617 constant pool address is not itself legitimate. */
2620 mips_emit_move (rtx dest
, rtx src
)
2622 return (can_create_pseudo_p ()
2623 ? emit_move_insn (dest
, src
)
2624 : emit_move_insn_1 (dest
, src
));
2627 /* Emit a move from SRC to DEST, splitting compound moves into individual
2628 instructions. SPLIT_TYPE is the type of split to perform. */
2631 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
2633 if (mips_split_move_p (dest
, src
, split_type
))
2634 mips_split_move (dest
, src
, split_type
);
2636 mips_emit_move (dest
, src
);
2639 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2642 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2644 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2645 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2648 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2649 Return that new register. */
2652 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2656 reg
= gen_reg_rtx (mode
);
2657 mips_emit_unary (code
, reg
, op0
);
2661 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2664 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2666 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2667 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2670 /* Compute (CODE OP0 OP1) and store the result in a new register
2671 of mode MODE. Return that new register. */
2674 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2678 reg
= gen_reg_rtx (mode
);
2679 mips_emit_binary (code
, reg
, op0
, op1
);
2683 /* Copy VALUE to a register and return that register. If new pseudos
2684 are allowed, copy it into a new register, otherwise use DEST. */
2687 mips_force_temporary (rtx dest
, rtx value
)
2689 if (can_create_pseudo_p ())
2690 return force_reg (Pmode
, value
);
2693 mips_emit_move (dest
, value
);
2698 /* Emit a call sequence with call pattern PATTERN and return the call
2699 instruction itself (which is not necessarily the last instruction
2700 emitted). ORIG_ADDR is the original, unlegitimized address,
2701 ADDR is the legitimized form, and LAZY_P is true if the call
2702 address is lazily-bound. */
2705 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2709 insn
= emit_call_insn (pattern
);
2711 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2713 /* MIPS16 JALRs only take MIPS16 registers. If the target
2714 function requires $25 to be valid on entry, we must copy it
2715 there separately. The move instruction can be put in the
2716 call's delay slot. */
2717 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2718 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2719 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2723 /* Lazy-binding stubs require $gp to be valid on entry. */
2724 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2728 /* See the comment above load_call<mode> for details. */
2729 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2730 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2731 emit_insn (gen_update_got_version ());
2736 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2737 then add CONST_INT OFFSET to the result. */
2740 mips_unspec_address_offset (rtx base
, rtx offset
,
2741 enum mips_symbol_type symbol_type
)
2743 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2744 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2745 if (offset
!= const0_rtx
)
2746 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2747 return gen_rtx_CONST (Pmode
, base
);
2750 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2751 type SYMBOL_TYPE. */
2754 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2758 split_const (address
, &base
, &offset
);
2759 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2762 /* If OP is an UNSPEC address, return the address to which it refers,
2763 otherwise return OP itself. */
2766 mips_strip_unspec_address (rtx op
)
2770 split_const (op
, &base
, &offset
);
2771 if (UNSPEC_ADDRESS_P (base
))
2772 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2776 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2777 high part to BASE and return the result. Just return BASE otherwise.
2778 TEMP is as for mips_force_temporary.
2780 The returned expression can be used as the first operand to a LO_SUM. */
2783 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2784 enum mips_symbol_type symbol_type
)
2786 if (mips_split_p
[symbol_type
])
2788 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2789 addr
= mips_force_temporary (temp
, addr
);
2790 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2795 /* Return an instruction that copies $gp into register REG. We want
2796 GCC to treat the register's value as constant, so that its value
2797 can be rematerialized on demand. */
2800 gen_load_const_gp (rtx reg
)
2802 return PMODE_INSN (gen_load_const_gp
, (reg
));
2805 /* Return a pseudo register that contains the value of $gp throughout
2806 the current function. Such registers are needed by MIPS16 functions,
2807 for which $gp itself is not a valid base register or addition operand. */
2810 mips16_gp_pseudo_reg (void)
2812 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2816 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2818 push_topmost_sequence ();
2820 scan
= get_insns ();
2821 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2822 scan
= NEXT_INSN (scan
);
2824 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2825 insn
= emit_insn_after (insn
, scan
);
2826 INSN_LOCATION (insn
) = 0;
2828 pop_topmost_sequence ();
2831 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2834 /* Return a base register that holds pic_offset_table_rtx.
2835 TEMP, if nonnull, is a scratch Pmode base register. */
2838 mips_pic_base_register (rtx temp
)
2841 return pic_offset_table_rtx
;
2843 if (currently_expanding_to_rtl
)
2844 return mips16_gp_pseudo_reg ();
2846 if (can_create_pseudo_p ())
2847 temp
= gen_reg_rtx (Pmode
);
2850 /* The first post-reload split exposes all references to $gp
2851 (both uses and definitions). All references must remain
2852 explicit after that point.
2854 It is safe to introduce uses of $gp at any time, so for
2855 simplicity, we do that before the split too. */
2856 mips_emit_move (temp
, pic_offset_table_rtx
);
2858 emit_insn (gen_load_const_gp (temp
));
2862 /* Return the RHS of a load_call<mode> insn. */
2865 mips_unspec_call (rtx reg
, rtx symbol
)
2869 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
2870 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
2873 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2874 reference. Return NULL_RTX otherwise. */
2877 mips_strip_unspec_call (rtx src
)
2879 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
2880 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
2884 /* Create and return a GOT reference of type TYPE for address ADDR.
2885 TEMP, if nonnull, is a scratch Pmode base register. */
2888 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
2890 rtx base
, high
, lo_sum_symbol
;
2892 base
= mips_pic_base_register (temp
);
2894 /* If we used the temporary register to load $gp, we can't use
2895 it for the high part as well. */
2896 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
2899 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
2900 lo_sum_symbol
= mips_unspec_address (addr
, type
);
2902 if (type
== SYMBOL_GOTOFF_CALL
)
2903 return mips_unspec_call (high
, lo_sum_symbol
);
2905 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
2908 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2909 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2910 constant in that context and can be split into high and low parts.
2911 If so, and if LOW_OUT is nonnull, emit the high part and store the
2912 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2914 TEMP is as for mips_force_temporary and is used to load the high
2915 part into a register.
2917 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2918 a legitimize SET_SRC for an .md pattern, otherwise the low part
2919 is guaranteed to be a legitimate address for mode MODE. */
2922 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
2924 enum mips_symbol_context context
;
2925 enum mips_symbol_type symbol_type
;
2928 context
= (mode
== MAX_MACHINE_MODE
2929 ? SYMBOL_CONTEXT_LEA
2930 : SYMBOL_CONTEXT_MEM
);
2931 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
2933 addr
= XEXP (addr
, 0);
2934 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2935 && mips_symbol_insns (symbol_type
, mode
) > 0
2936 && mips_split_hi_p
[symbol_type
])
2939 switch (symbol_type
)
2941 case SYMBOL_GOT_PAGE_OFST
:
2942 /* The high part of a page/ofst pair is loaded from the GOT. */
2943 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
2954 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2955 && mips_symbol_insns (symbol_type
, mode
) > 0
2956 && mips_split_p
[symbol_type
])
2959 switch (symbol_type
)
2961 case SYMBOL_GOT_DISP
:
2962 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2963 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
2966 case SYMBOL_GP_RELATIVE
:
2967 high
= mips_pic_base_register (temp
);
2968 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2972 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2973 high
= mips_force_temporary (temp
, high
);
2974 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2983 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2984 mips_force_temporary; it is only needed when OFFSET is not a
2988 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2990 if (!SMALL_OPERAND (offset
))
2996 /* Load the full offset into a register so that we can use
2997 an unextended instruction for the address itself. */
2998 high
= GEN_INT (offset
);
3003 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3004 The addition inside the macro CONST_HIGH_PART may cause an
3005 overflow, so we need to force a sign-extension check. */
3006 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
3007 offset
= CONST_LOW_PART (offset
);
3009 high
= mips_force_temporary (temp
, high
);
3010 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
3012 return plus_constant (Pmode
, reg
, offset
);
3015 /* The __tls_get_attr symbol. */
3016 static GTY(()) rtx mips_tls_symbol
;
3018 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3019 the TLS symbol we are referencing and TYPE is the symbol type to use
3020 (either global dynamic or local dynamic). V0 is an RTX for the
3021 return value location. */
3024 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3028 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3030 if (!mips_tls_symbol
)
3031 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3033 loc
= mips_unspec_address (sym
, type
);
3037 emit_insn (gen_rtx_SET (Pmode
, a0
,
3038 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
3039 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3040 const0_rtx
, NULL_RTX
, false);
3041 RTL_CONST_CALL_P (insn
) = 1;
3042 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3043 insn
= get_insns ();
3050 /* Return a pseudo register that contains the current thread pointer. */
3053 mips_expand_thread_pointer (rtx tp
)
3059 mips_need_mips16_rdhwr_p
= true;
3060 fn
= mips16_stub_function ("__mips16_rdhwr");
3061 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
3062 if (!call_insn_operand (fn
, VOIDmode
))
3063 fn
= force_reg (Pmode
, fn
);
3064 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3067 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3074 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3077 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3078 its address. The return value will be both a valid address and a valid
3079 SET_SRC (either a REG or a LO_SUM). */
3082 mips_legitimize_tls_address (rtx loc
)
3084 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3085 enum tls_model model
;
3087 model
= SYMBOL_REF_TLS_MODEL (loc
);
3088 /* Only TARGET_ABICALLS code can have more than one module; other
3089 code must be be static and should not use a GOT. All TLS models
3090 reduce to local exec in this situation. */
3091 if (!TARGET_ABICALLS
)
3092 model
= TLS_MODEL_LOCAL_EXEC
;
3096 case TLS_MODEL_GLOBAL_DYNAMIC
:
3097 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3098 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3099 dest
= gen_reg_rtx (Pmode
);
3100 emit_libcall_block (insn
, dest
, v0
, loc
);
3103 case TLS_MODEL_LOCAL_DYNAMIC
:
3104 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3105 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3106 tmp1
= gen_reg_rtx (Pmode
);
3108 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3109 share the LDM result with other LD model accesses. */
3110 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3112 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3114 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3115 if (mips_split_p
[SYMBOL_DTPREL
])
3117 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3118 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3121 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3122 0, 0, OPTAB_DIRECT
);
3125 case TLS_MODEL_INITIAL_EXEC
:
3126 tp
= mips_get_tp ();
3127 tmp1
= gen_reg_rtx (Pmode
);
3128 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3129 if (Pmode
== DImode
)
3130 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3132 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3133 dest
= gen_reg_rtx (Pmode
);
3134 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3137 case TLS_MODEL_LOCAL_EXEC
:
3138 tmp1
= mips_get_tp ();
3139 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3140 if (mips_split_p
[SYMBOL_TPREL
])
3142 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3143 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3146 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3147 0, 0, OPTAB_DIRECT
);
3156 /* If X is not a valid address for mode MODE, force it into a register. */
3159 mips_force_address (rtx x
, enum machine_mode mode
)
3161 if (!mips_legitimate_address_p (mode
, x
, false))
3162 x
= force_reg (Pmode
, x
);
3166 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3167 be legitimized in a way that the generic machinery might not expect,
3168 return a new address, otherwise return NULL. MODE is the mode of
3169 the memory being accessed. */
3172 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3173 enum machine_mode mode
)
3176 HOST_WIDE_INT offset
;
3178 if (mips_tls_symbol_p (x
))
3179 return mips_legitimize_tls_address (x
);
3181 /* See if the address can split into a high part and a LO_SUM. */
3182 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3183 return mips_force_address (addr
, mode
);
3185 /* Handle BASE + OFFSET using mips_add_offset. */
3186 mips_split_plus (x
, &base
, &offset
);
3189 if (!mips_valid_base_register_p (base
, mode
, false))
3190 base
= copy_to_mode_reg (Pmode
, base
);
3191 addr
= mips_add_offset (NULL
, base
, offset
);
3192 return mips_force_address (addr
, mode
);
3198 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3201 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3203 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3204 enum machine_mode mode
;
3205 unsigned int i
, num_ops
;
3208 mode
= GET_MODE (dest
);
3209 num_ops
= mips_build_integer (codes
, value
);
3211 /* Apply each binary operation to X. Invariant: X is a legitimate
3212 source operand for a SET pattern. */
3213 x
= GEN_INT (codes
[0].value
);
3214 for (i
= 1; i
< num_ops
; i
++)
3216 if (!can_create_pseudo_p ())
3218 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
3222 x
= force_reg (mode
, x
);
3223 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3226 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
3229 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3230 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3234 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
3238 /* Split moves of big integers into smaller pieces. */
3239 if (splittable_const_int_operand (src
, mode
))
3241 mips_move_integer (dest
, dest
, INTVAL (src
));
3245 /* Split moves of symbolic constants into high/low pairs. */
3246 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3248 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3252 /* Generate the appropriate access sequences for TLS symbols. */
3253 if (mips_tls_symbol_p (src
))
3255 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3259 /* If we have (const (plus symbol offset)), and that expression cannot
3260 be forced into memory, load the symbol first and add in the offset.
3261 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3262 forced into memory, as it usually produces better code. */
3263 split_const (src
, &base
, &offset
);
3264 if (offset
!= const0_rtx
3265 && (targetm
.cannot_force_const_mem (mode
, src
)
3266 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3268 base
= mips_force_temporary (dest
, base
);
3269 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3273 src
= force_const_mem (mode
, src
);
3275 /* When using explicit relocs, constant pool references are sometimes
3276 not legitimate addresses. */
3277 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3278 mips_emit_move (dest
, src
);
3281 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3282 sequence that is valid. */
3285 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
3287 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3289 mips_emit_move (dest
, force_reg (mode
, src
));
3293 /* We need to deal with constants that would be legitimate
3294 immediate_operands but aren't legitimate move_operands. */
3295 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3297 mips_legitimize_const_move (mode
, dest
, src
);
3298 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3304 /* Return true if value X in context CONTEXT is a small-data address
3305 that can be rewritten as a LO_SUM. */
3308 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3310 enum mips_symbol_type symbol_type
;
3312 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3313 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3314 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3315 && symbol_type
== SYMBOL_GP_RELATIVE
);
3318 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3319 containing MEM, or null if none. */
3322 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3324 enum mips_symbol_context context
;
3326 /* Ignore things like "g" constraints in asms. We make no particular
3327 guarantee about which symbolic constants are acceptable as asm operands
3328 versus which must be forced into a GPR. */
3329 if (GET_CODE (*loc
) == LO_SUM
|| GET_CODE (*loc
) == ASM_OPERANDS
)
3334 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3339 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3340 return mips_rewrite_small_data_p (*loc
, context
);
3343 /* Return true if OP refers to small data symbols directly, not through
3347 mips_small_data_pattern_p (rtx op
)
3349 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3352 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3353 DATA is the containing MEM, or null if none. */
3356 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3358 enum mips_symbol_context context
;
3362 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3366 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3367 if (mips_rewrite_small_data_p (*loc
, context
))
3368 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3370 if (GET_CODE (*loc
) == LO_SUM
)
3376 /* Rewrite instruction pattern PATTERN so that it refers to small data
3377 using explicit relocations. */
3380 mips_rewrite_small_data (rtx pattern
)
3382 pattern
= copy_insn (pattern
);
3383 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3387 /* The cost of loading values from the constant pool. It should be
3388 larger than the cost of any constant we want to synthesize inline. */
3389 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3391 /* Return the cost of X when used as an operand to the MIPS16 instruction
3392 that implements CODE. Return -1 if there is no such instruction, or if
3393 X is not a valid immediate operand for it. */
3396 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3403 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3404 other shifts are extended. The shift patterns truncate the shift
3405 count to the right size, so there are no out-of-range values. */
3406 if (IN_RANGE (x
, 1, 8))
3408 return COSTS_N_INSNS (1);
3411 if (IN_RANGE (x
, -128, 127))
3413 if (SMALL_OPERAND (x
))
3414 return COSTS_N_INSNS (1);
3418 /* Like LE, but reject the always-true case. */
3422 /* We add 1 to the immediate and use SLT. */
3425 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3428 if (IN_RANGE (x
, 0, 255))
3430 if (SMALL_OPERAND_UNSIGNED (x
))
3431 return COSTS_N_INSNS (1);
3436 /* Equality comparisons with 0 are cheap. */
3446 /* Return true if there is a non-MIPS16 instruction that implements CODE
3447 and if that instruction accepts X as an immediate operand. */
3450 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3457 /* All shift counts are truncated to a valid constant. */
3462 /* Likewise rotates, if the target supports rotates at all. */
3468 /* These instructions take 16-bit unsigned immediates. */
3469 return SMALL_OPERAND_UNSIGNED (x
);
3474 /* These instructions take 16-bit signed immediates. */
3475 return SMALL_OPERAND (x
);
3481 /* The "immediate" forms of these instructions are really
3482 implemented as comparisons with register 0. */
3487 /* Likewise, meaning that the only valid immediate operand is 1. */
3491 /* We add 1 to the immediate and use SLT. */
3492 return SMALL_OPERAND (x
+ 1);
3495 /* Likewise SLTU, but reject the always-true case. */
3496 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3500 /* The bit position and size are immediate operands. */
3501 return ISA_HAS_EXT_INS
;
3504 /* By default assume that $0 can be used for 0. */
3509 /* Return the cost of binary operation X, given that the instruction
3510 sequence for a word-sized or smaller operation has cost SINGLE_COST
3511 and that the sequence of a double-word operation has cost DOUBLE_COST.
3512 If SPEED is true, optimize for speed otherwise optimize for size. */
3515 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3519 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3524 + set_src_cost (XEXP (x
, 0), speed
)
3525 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3528 /* Return the cost of floating-point multiplications of mode MODE. */
3531 mips_fp_mult_cost (enum machine_mode mode
)
3533 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3536 /* Return the cost of floating-point divisions of mode MODE. */
3539 mips_fp_div_cost (enum machine_mode mode
)
3541 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3544 /* Return the cost of sign-extending OP to mode MODE, not including the
3545 cost of OP itself. */
3548 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3551 /* Extended loads are as cheap as unextended ones. */
3554 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3555 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3558 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3559 /* We can use SEB or SEH. */
3560 return COSTS_N_INSNS (1);
3562 /* We need to use a shift left and a shift right. */
3563 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3566 /* Return the cost of zero-extending OP to mode MODE, not including the
3567 cost of OP itself. */
3570 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3573 /* Extended loads are as cheap as unextended ones. */
3576 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3577 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3578 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3580 if (GENERATE_MIPS16E
)
3581 /* We can use ZEB or ZEH. */
3582 return COSTS_N_INSNS (1);
3585 /* We need to load 0xff or 0xffff into a register and use AND. */
3586 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3588 /* We can use ANDI. */
3589 return COSTS_N_INSNS (1);
3592 /* Return the cost of moving between two registers of mode MODE,
3593 assuming that the move will be in pieces of at most UNITS bytes. */
3596 mips_set_reg_reg_piece_cost (enum machine_mode mode
, unsigned int units
)
3598 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3601 /* Return the cost of moving between two registers of mode MODE. */
3604 mips_set_reg_reg_cost (enum machine_mode mode
)
3606 switch (GET_MODE_CLASS (mode
))
3609 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3612 case MODE_COMPLEX_FLOAT
:
3613 case MODE_VECTOR_FLOAT
:
3614 if (TARGET_HARD_FLOAT
)
3615 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3619 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3623 /* Return the cost of an operand X that can be trucated for free.
3624 SPEED says whether we're optimizing for size or speed. */
3627 mips_truncated_op_cost (rtx x
, bool speed
)
3629 if (GET_CODE (x
) == TRUNCATE
)
3631 return set_src_cost (x
, speed
);
3634 /* Implement TARGET_RTX_COSTS. */
3637 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3638 int *total
, bool speed
)
3640 enum machine_mode mode
= GET_MODE (x
);
3641 bool float_mode_p
= FLOAT_MODE_P (mode
);
3645 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3646 appear in the instruction stream, and the cost of a comparison is
3647 really the cost of the branch or scc condition. At the time of
3648 writing, GCC only uses an explicit outer COMPARE code when optabs
3649 is testing whether a constant is expensive enough to force into a
3650 register. We want optabs to pass such constants through the MIPS
3651 expanders instead, so make all constants very cheap here. */
3652 if (outer_code
== COMPARE
)
3654 gcc_assert (CONSTANT_P (x
));
3662 /* Treat *clear_upper32-style ANDs as having zero cost in the
3663 second operand. The cost is entirely in the first operand.
3665 ??? This is needed because we would otherwise try to CSE
3666 the constant operand. Although that's the right thing for
3667 instructions that continue to be a register operation throughout
3668 compilation, it is disastrous for instructions that could
3669 later be converted into a memory operation. */
3671 && outer_code
== AND
3672 && UINTVAL (x
) == 0xffffffff)
3680 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3689 /* When not optimizing for size, we care more about the cost
3690 of hot code, and hot code is often in a loop. If a constant
3691 operand needs to be forced into a register, we will often be
3692 able to hoist the constant load out of the loop, so the load
3693 should not contribute to the cost. */
3694 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3706 if (force_to_mem_operand (x
, VOIDmode
))
3708 *total
= COSTS_N_INSNS (1);
3711 cost
= mips_const_insns (x
);
3714 /* If the constant is likely to be stored in a GPR, SETs of
3715 single-insn constants are as cheap as register sets; we
3716 never want to CSE them.
3718 Don't reduce the cost of storing a floating-point zero in
3719 FPRs. If we have a zero in an FPR for other reasons, we
3720 can get better cfg-cleanup and delayed-branch results by
3721 using it consistently, rather than using $0 sometimes and
3722 an FPR at other times. Also, moves between floating-point
3723 registers are sometimes cheaper than (D)MTC1 $0. */
3725 && outer_code
== SET
3726 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3728 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3729 want to CSE the constant itself. It is usually better to
3730 have N copies of the last operation in the sequence and one
3731 shared copy of the other operations. (Note that this is
3732 not true for MIPS16 code, where the final operation in the
3733 sequence is often an extended instruction.)
3735 Also, if we have a CONST_INT, we don't know whether it is
3736 for a word or doubleword operation, so we cannot rely on
3737 the result of mips_build_integer. */
3738 else if (!TARGET_MIPS16
3739 && (outer_code
== SET
|| mode
== VOIDmode
))
3741 *total
= COSTS_N_INSNS (cost
);
3744 /* The value will need to be fetched from the constant pool. */
3745 *total
= CONSTANT_POOL_COST
;
3749 /* If the address is legitimate, return the number of
3750 instructions it needs. */
3752 cost
= mips_address_insns (addr
, mode
, true);
3755 *total
= COSTS_N_INSNS (cost
+ 1);
3758 /* Check for a scaled indexed address. */
3759 if (mips_lwxs_address_p (addr
)
3760 || mips_lx_address_p (addr
, mode
))
3762 *total
= COSTS_N_INSNS (2);
3765 /* Otherwise use the default handling. */
3769 *total
= COSTS_N_INSNS (6);
3773 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3777 /* Check for a *clear_upper32 pattern and treat it like a zero
3778 extension. See the pattern's comment for details. */
3781 && CONST_INT_P (XEXP (x
, 1))
3782 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3784 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3785 + set_src_cost (XEXP (x
, 0), speed
));
3788 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
3790 rtx op
= XEXP (x
, 0);
3791 if (GET_CODE (op
) == ASHIFT
3792 && CONST_INT_P (XEXP (op
, 1))
3793 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
3795 *total
= COSTS_N_INSNS (1) + set_src_cost (XEXP (op
, 0), speed
);
3804 /* Double-word operations use two single-word operations. */
3805 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3814 if (CONSTANT_P (XEXP (x
, 1)))
3815 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3818 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3824 *total
= mips_cost
->fp_add
;
3826 *total
= COSTS_N_INSNS (4);
3830 /* Low-part immediates need an extended MIPS16 instruction. */
3831 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3832 + set_src_cost (XEXP (x
, 0), speed
));
3847 /* Branch comparisons have VOIDmode, so use the first operand's
3849 mode
= GET_MODE (XEXP (x
, 0));
3850 if (FLOAT_MODE_P (mode
))
3852 *total
= mips_cost
->fp_add
;
3855 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3861 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
3862 && TARGET_FUSED_MADD
3863 && !HONOR_NANS (mode
)
3864 && !HONOR_SIGNED_ZEROS (mode
))
3866 /* See if we can use NMADD or NMSUB. See mips.md for the
3867 associated patterns. */
3868 rtx op0
= XEXP (x
, 0);
3869 rtx op1
= XEXP (x
, 1);
3870 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3872 *total
= (mips_fp_mult_cost (mode
)
3873 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
3874 + set_src_cost (XEXP (op0
, 1), speed
)
3875 + set_src_cost (op1
, speed
));
3878 if (GET_CODE (op1
) == MULT
)
3880 *total
= (mips_fp_mult_cost (mode
)
3881 + set_src_cost (op0
, speed
)
3882 + set_src_cost (XEXP (op1
, 0), speed
)
3883 + set_src_cost (XEXP (op1
, 1), speed
));
3892 /* If this is part of a MADD or MSUB, treat the PLUS as
3894 if ((ISA_HAS_FP_MADD4_MSUB4
|| ISA_HAS_FP_MADD3_MSUB3
)
3895 && TARGET_FUSED_MADD
3896 && GET_CODE (XEXP (x
, 0)) == MULT
)
3899 *total
= mips_cost
->fp_add
;
3903 /* Double-word operations require three single-word operations and
3904 an SLTU. The MIPS16 version then needs to move the result of
3905 the SLTU from $24 to a MIPS16 register. */
3906 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3907 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
3913 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
3914 && TARGET_FUSED_MADD
3915 && !HONOR_NANS (mode
)
3916 && HONOR_SIGNED_ZEROS (mode
))
3918 /* See if we can use NMADD or NMSUB. See mips.md for the
3919 associated patterns. */
3920 rtx op
= XEXP (x
, 0);
3921 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3922 && GET_CODE (XEXP (op
, 0)) == MULT
)
3924 *total
= (mips_fp_mult_cost (mode
)
3925 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
3926 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
3927 + set_src_cost (XEXP (op
, 1), speed
));
3933 *total
= mips_cost
->fp_add
;
3935 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3940 *total
= mips_fp_mult_cost (mode
);
3941 else if (mode
== DImode
&& !TARGET_64BIT
)
3942 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3943 where the mulsidi3 always includes an MFHI and an MFLO. */
3945 ? mips_cost
->int_mult_si
* 3 + 6
3946 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
3948 *total
= COSTS_N_INSNS (ISA_HAS_MUL3
? 1 : 2) + 1;
3949 else if (mode
== DImode
)
3950 *total
= mips_cost
->int_mult_di
;
3952 *total
= mips_cost
->int_mult_si
;
3956 /* Check for a reciprocal. */
3959 && flag_unsafe_math_optimizations
3960 && XEXP (x
, 0) == CONST1_RTX (mode
))
3962 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
3963 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3964 division as being free. */
3965 *total
= set_src_cost (XEXP (x
, 1), speed
);
3967 *total
= (mips_fp_div_cost (mode
)
3968 + set_src_cost (XEXP (x
, 1), speed
));
3977 *total
= mips_fp_div_cost (mode
);
3986 /* It is our responsibility to make division by a power of 2
3987 as cheap as 2 register additions if we want the division
3988 expanders to be used for such operations; see the setting
3989 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3990 should always produce shorter code than using
3991 expand_sdiv2_pow2. */
3993 && CONST_INT_P (XEXP (x
, 1))
3994 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
3996 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
3999 *total
= COSTS_N_INSNS (mips_idiv_insns ());
4001 else if (mode
== DImode
)
4002 *total
= mips_cost
->int_div_di
;
4004 *total
= mips_cost
->int_div_si
;
4008 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
4012 if (outer_code
== SET
4014 && GET_MODE (XEXP (x
, 0)) == QImode
4015 && GET_CODE (XEXP (x
, 0)) == PLUS
)
4017 rtx plus
= XEXP (x
, 0);
4018 *total
= (COSTS_N_INSNS (1)
4019 + mips_truncated_op_cost (XEXP (plus
, 0), speed
)
4020 + mips_truncated_op_cost (XEXP (plus
, 1), speed
));
4023 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4027 case UNSIGNED_FLOAT
:
4030 case FLOAT_TRUNCATE
:
4031 *total
= mips_cost
->fp_add
;
4035 if (register_operand (SET_DEST (x
), VOIDmode
)
4036 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4038 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4048 /* Implement TARGET_ADDRESS_COST. */
4051 mips_address_cost (rtx addr
, enum machine_mode mode
,
4052 addr_space_t as ATTRIBUTE_UNUSED
,
4053 bool speed ATTRIBUTE_UNUSED
)
4055 return mips_address_insns (addr
, mode
, false);
4058 /* Information about a single instruction in a multi-instruction
4060 struct mips_multi_member
{
4061 /* True if this is a label, false if it is code. */
4064 /* The output_asm_insn format of the instruction. */
4067 /* The operands to the instruction. */
4068 rtx operands
[MAX_RECOG_OPERANDS
];
4070 typedef struct mips_multi_member mips_multi_member
;
4072 /* The instructions that make up the current multi-insn sequence. */
4073 static vec
<mips_multi_member
> mips_multi_members
;
4075 /* How many instructions (as opposed to labels) are in the current
4076 multi-insn sequence. */
4077 static unsigned int mips_multi_num_insns
;
4079 /* Start a new multi-insn sequence. */
4082 mips_multi_start (void)
4084 mips_multi_members
.truncate (0);
4085 mips_multi_num_insns
= 0;
4088 /* Add a new, uninitialized member to the current multi-insn sequence. */
4090 static struct mips_multi_member
*
4091 mips_multi_add (void)
4093 mips_multi_member empty
;
4094 return mips_multi_members
.safe_push (empty
);
4097 /* Add a normal insn with the given asm format to the current multi-insn
4098 sequence. The other arguments are a null-terminated list of operands. */
4101 mips_multi_add_insn (const char *format
, ...)
4103 struct mips_multi_member
*member
;
4108 member
= mips_multi_add ();
4109 member
->is_label_p
= false;
4110 member
->format
= format
;
4111 va_start (ap
, format
);
4113 while ((op
= va_arg (ap
, rtx
)))
4114 member
->operands
[i
++] = op
;
4116 mips_multi_num_insns
++;
4119 /* Add the given label definition to the current multi-insn sequence.
4120 The definition should include the colon. */
4123 mips_multi_add_label (const char *label
)
4125 struct mips_multi_member
*member
;
4127 member
= mips_multi_add ();
4128 member
->is_label_p
= true;
4129 member
->format
= label
;
4132 /* Return the index of the last member of the current multi-insn sequence. */
4135 mips_multi_last_index (void)
4137 return mips_multi_members
.length () - 1;
4140 /* Add a copy of an existing instruction to the current multi-insn
4141 sequence. I is the index of the instruction that should be copied. */
4144 mips_multi_copy_insn (unsigned int i
)
4146 struct mips_multi_member
*member
;
4148 member
= mips_multi_add ();
4149 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4150 gcc_assert (!member
->is_label_p
);
4153 /* Change the operand of an existing instruction in the current
4154 multi-insn sequence. I is the index of the instruction,
4155 OP is the index of the operand, and X is the new value. */
4158 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4160 mips_multi_members
[i
].operands
[op
] = x
;
4163 /* Write out the asm code for the current multi-insn sequence. */
4166 mips_multi_write (void)
4168 struct mips_multi_member
*member
;
4171 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4172 if (member
->is_label_p
)
4173 fprintf (asm_out_file
, "%s\n", member
->format
);
4175 output_asm_insn (member
->format
, member
->operands
);
4178 /* Return one word of double-word value OP, taking into account the fixed
4179 endianness of certain registers. HIGH_P is true to select the high part,
4180 false to select the low part. */
4183 mips_subword (rtx op
, bool high_p
)
4185 unsigned int byte
, offset
;
4186 enum machine_mode mode
;
4188 mode
= GET_MODE (op
);
4189 if (mode
== VOIDmode
)
4190 mode
= TARGET_64BIT
? TImode
: DImode
;
4192 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4193 byte
= UNITS_PER_WORD
;
4197 if (FP_REG_RTX_P (op
))
4199 /* Paired FPRs are always ordered little-endian. */
4200 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4201 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4205 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4207 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4210 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4211 SPLIT_TYPE is the condition under which moves should be split. */
4214 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4216 return ((split_type
!= SPLIT_FOR_SPEED
4217 || mips_tuning_info
.fast_mult_zero_zero_p
)
4218 && src
== const0_rtx
4220 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4221 && (ISA_HAS_DSP_MULT
4222 ? ACC_REG_P (REGNO (dest
))
4223 : MD_REG_P (REGNO (dest
))));
4226 /* Return true if a move from SRC to DEST should be split into two.
4227 SPLIT_TYPE describes the split condition. */
4230 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4232 /* Check whether the move can be done using some variant of MULT $0,$0. */
4233 if (mips_mult_move_p (dest
, src
, split_type
))
4236 /* FPR-to-FPR moves can be done in a single instruction, if they're
4238 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4239 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4242 /* Check for floating-point loads and stores. */
4243 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4245 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4247 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4251 /* Otherwise split all multiword moves. */
4252 return size
> UNITS_PER_WORD
;
4255 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4256 SPLIT_TYPE describes the split condition. */
4259 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4263 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4264 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4266 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4267 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4268 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4269 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4270 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4271 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4272 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4273 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4274 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4275 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4276 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4277 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4278 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4279 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4283 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4285 low_dest
= mips_subword (dest
, false);
4286 mips_emit_move (low_dest
, mips_subword (src
, false));
4288 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4290 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4292 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4294 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4296 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4298 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4302 /* The operation can be split into two normal moves. Decide in
4303 which order to do them. */
4304 low_dest
= mips_subword (dest
, false);
4305 if (REG_P (low_dest
)
4306 && reg_overlap_mentioned_p (low_dest
, src
))
4308 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4309 mips_emit_move (low_dest
, mips_subword (src
, false));
4313 mips_emit_move (low_dest
, mips_subword (src
, false));
4314 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4319 /* Return the split type for instruction INSN. */
4321 static enum mips_split_type
4322 mips_insn_split_type (rtx insn
)
4324 basic_block bb
= BLOCK_FOR_INSN (insn
);
4327 if (optimize_bb_for_speed_p (bb
))
4328 return SPLIT_FOR_SPEED
;
4330 return SPLIT_FOR_SIZE
;
4332 /* Once CFG information has been removed, we should trust the optimization
4333 decisions made by previous passes and only split where necessary. */
4334 return SPLIT_IF_NECESSARY
;
4337 /* Return true if a move from SRC to DEST in INSN should be split. */
4340 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
4342 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
4345 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4349 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
4351 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
4354 /* Return the appropriate instructions to move SRC into DEST. Assume
4355 that SRC is operand 1 and DEST is operand 0. */
4358 mips_output_move (rtx dest
, rtx src
)
4360 enum rtx_code dest_code
, src_code
;
4361 enum machine_mode mode
;
4362 enum mips_symbol_type symbol_type
;
4365 dest_code
= GET_CODE (dest
);
4366 src_code
= GET_CODE (src
);
4367 mode
= GET_MODE (dest
);
4368 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4370 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4373 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4374 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4376 if (dest_code
== REG
)
4378 if (GP_REG_P (REGNO (dest
)))
4379 return "move\t%0,%z1";
4381 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4383 if (ISA_HAS_DSP_MULT
)
4384 return "mult\t%q0,%.,%.";
4386 return "mult\t%.,%.";
4389 /* Moves to HI are handled by special .md insns. */
4390 if (REGNO (dest
) == LO_REGNUM
)
4393 if (DSP_ACC_REG_P (REGNO (dest
)))
4395 static char retval
[] = "mt__\t%z1,%q0";
4397 retval
[2] = reg_names
[REGNO (dest
)][4];
4398 retval
[3] = reg_names
[REGNO (dest
)][5];
4402 if (FP_REG_P (REGNO (dest
)))
4403 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4405 if (ALL_COP_REG_P (REGNO (dest
)))
4407 static char retval
[] = "dmtc_\t%z1,%0";
4409 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4410 return dbl_p
? retval
: retval
+ 1;
4413 if (dest_code
== MEM
)
4414 switch (GET_MODE_SIZE (mode
))
4416 case 1: return "sb\t%z1,%0";
4417 case 2: return "sh\t%z1,%0";
4418 case 4: return "sw\t%z1,%0";
4419 case 8: return "sd\t%z1,%0";
4422 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4424 if (src_code
== REG
)
4426 /* Moves from HI are handled by special .md insns. */
4427 if (REGNO (src
) == LO_REGNUM
)
4429 /* When generating VR4120 or VR4130 code, we use MACC and
4430 DMACC instead of MFLO. This avoids both the normal
4431 MIPS III HI/LO hazards and the errata related to
4434 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4438 if (DSP_ACC_REG_P (REGNO (src
)))
4440 static char retval
[] = "mf__\t%0,%q1";
4442 retval
[2] = reg_names
[REGNO (src
)][4];
4443 retval
[3] = reg_names
[REGNO (src
)][5];
4447 if (FP_REG_P (REGNO (src
)))
4448 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4450 if (ALL_COP_REG_P (REGNO (src
)))
4452 static char retval
[] = "dmfc_\t%0,%1";
4454 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4455 return dbl_p
? retval
: retval
+ 1;
4459 if (src_code
== MEM
)
4460 switch (GET_MODE_SIZE (mode
))
4462 case 1: return "lbu\t%0,%1";
4463 case 2: return "lhu\t%0,%1";
4464 case 4: return "lw\t%0,%1";
4465 case 8: return "ld\t%0,%1";
4468 if (src_code
== CONST_INT
)
4470 /* Don't use the X format for the operand itself, because that
4471 will give out-of-range numbers for 64-bit hosts and 32-bit
4474 return "li\t%0,%1\t\t\t# %X1";
4476 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4479 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4483 if (src_code
== HIGH
)
4484 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4486 if (CONST_GP_P (src
))
4487 return "move\t%0,%1";
4489 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4490 && mips_lo_relocs
[symbol_type
] != 0)
4492 /* A signed 16-bit constant formed by applying a relocation
4493 operator to a symbolic address. */
4494 gcc_assert (!mips_split_p
[symbol_type
]);
4495 return "li\t%0,%R1";
4498 if (symbolic_operand (src
, VOIDmode
))
4500 gcc_assert (TARGET_MIPS16
4501 ? TARGET_MIPS16_TEXT_LOADS
4502 : !TARGET_EXPLICIT_RELOCS
);
4503 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4506 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4508 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4510 if (GET_MODE (dest
) == V2SFmode
)
4511 return "mov.ps\t%0,%1";
4513 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4516 if (dest_code
== MEM
)
4517 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4519 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4521 if (src_code
== MEM
)
4522 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4524 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4526 static char retval
[] = "l_c_\t%0,%1";
4528 retval
[1] = (dbl_p
? 'd' : 'w');
4529 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4532 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4534 static char retval
[] = "s_c_\t%1,%0";
4536 retval
[1] = (dbl_p
? 'd' : 'w');
4537 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4543 /* Return true if CMP1 is a suitable second operand for integer ordering
4544 test CODE. See also the *sCC patterns in mips.md. */
4547 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4553 return reg_or_0_operand (cmp1
, VOIDmode
);
4557 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4561 return arith_operand (cmp1
, VOIDmode
);
4564 return sle_operand (cmp1
, VOIDmode
);
4567 return sleu_operand (cmp1
, VOIDmode
);
4574 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4575 integer ordering test *CODE, or if an equivalent combination can
4576 be formed by adjusting *CODE and *CMP1. When returning true, update
4577 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4581 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4582 enum machine_mode mode
)
4584 HOST_WIDE_INT plus_one
;
4586 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4589 if (CONST_INT_P (*cmp1
))
4593 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4594 if (INTVAL (*cmp1
) < plus_one
)
4597 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4603 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4607 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4618 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4619 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4620 is nonnull, it's OK to set TARGET to the inverse of the result and
4621 flip *INVERT_PTR instead. */
4624 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4625 rtx target
, rtx cmp0
, rtx cmp1
)
4627 enum machine_mode mode
;
4629 /* First see if there is a MIPS instruction that can do this operation.
4630 If not, try doing the same for the inverse operation. If that also
4631 fails, force CMP1 into a register and try again. */
4632 mode
= GET_MODE (cmp0
);
4633 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4634 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4637 enum rtx_code inv_code
= reverse_condition (code
);
4638 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4640 cmp1
= force_reg (mode
, cmp1
);
4641 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4643 else if (invert_ptr
== 0)
4647 inv_target
= mips_force_binary (GET_MODE (target
),
4648 inv_code
, cmp0
, cmp1
);
4649 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4653 *invert_ptr
= !*invert_ptr
;
4654 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4659 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4660 The register will have the same mode as CMP0. */
4663 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4665 if (cmp1
== const0_rtx
)
4668 if (uns_arith_operand (cmp1
, VOIDmode
))
4669 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4670 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4672 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4673 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4676 /* Convert *CODE into a code that can be used in a floating-point
4677 scc instruction (C.cond.fmt). Return true if the values of
4678 the condition code registers will be inverted, with 0 indicating
4679 that the condition holds. */
4682 mips_reversed_fp_cond (enum rtx_code
*code
)
4689 *code
= reverse_condition_maybe_unordered (*code
);
4697 /* Allocate a floating-point condition-code register of mode MODE.
4699 These condition code registers are used for certain kinds
4700 of compound operation, such as compare and branches, vconds,
4701 and built-in functions. At expand time, their use is entirely
4702 controlled by MIPS-specific code and is entirely internal
4703 to these compound operations.
4705 We could (and did in the past) expose condition-code values
4706 as pseudo registers and leave the register allocator to pick
4707 appropriate registers. The problem is that it is not practically
4708 possible for the rtl optimizers to guarantee that no spills will
4709 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4710 therefore need spill and reload sequences to handle the worst case.
4712 Although such sequences do exist, they are very expensive and are
4713 not something we'd want to use. This is especially true of CCV2 and
4714 CCV4, where all the shuffling would greatly outweigh whatever benefit
4715 the vectorization itself provides.
4717 The main benefit of having more than one condition-code register
4718 is to allow the pipelining of operations, especially those involving
4719 comparisons and conditional moves. We don't really expect the
4720 registers to be live for long periods, and certainly never want
4721 them to be live across calls.
4723 Also, there should be no penalty attached to using all the available
4724 registers. They are simply bits in the same underlying FPU control
4727 We therefore expose the hardware registers from the outset and use
4728 a simple round-robin allocation scheme. */
4731 mips_allocate_fcc (enum machine_mode mode
)
4733 unsigned int regno
, count
;
4735 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
4739 else if (mode
== CCV2mode
)
4741 else if (mode
== CCV4mode
)
4746 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
4747 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
4748 cfun
->machine
->next_fcc
= 0;
4749 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
4750 cfun
->machine
->next_fcc
+= count
;
4751 return gen_rtx_REG (mode
, regno
);
4754 /* Convert a comparison into something that can be used in a branch or
4755 conditional move. On entry, *OP0 and *OP1 are the values being
4756 compared and *CODE is the code used to compare them.
4758 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4759 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4760 otherwise any standard branch condition can be used. The standard branch
4763 - EQ or NE between two registers.
4764 - any comparison between a register and zero. */
4767 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4772 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4774 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4776 else if (*code
== EQ
|| *code
== NE
)
4780 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4784 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4788 /* The comparison needs a separate scc instruction. Store the
4789 result of the scc in *OP0 and compare it against zero. */
4790 bool invert
= false;
4791 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4792 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4793 *code
= (invert
? EQ
: NE
);
4797 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4799 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4800 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4806 enum rtx_code cmp_code
;
4808 /* Floating-point tests use a separate C.cond.fmt comparison to
4809 set a condition code register. The branch or conditional move
4810 will then compare that register against zero.
4812 Set CMP_CODE to the code of the comparison instruction and
4813 *CODE to the code that the branch or move should use. */
4815 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4817 ? mips_allocate_fcc (CCmode
)
4818 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4820 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4824 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4825 and OPERAND[3]. Store the result in OPERANDS[0].
4827 On 64-bit targets, the mode of the comparison and target will always be
4828 SImode, thus possibly narrower than that of the comparison's operands. */
4831 mips_expand_scc (rtx operands
[])
4833 rtx target
= operands
[0];
4834 enum rtx_code code
= GET_CODE (operands
[1]);
4835 rtx op0
= operands
[2];
4836 rtx op1
= operands
[3];
4838 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
4840 if (code
== EQ
|| code
== NE
)
4843 && reg_imm10_operand (op1
, GET_MODE (op1
)))
4844 mips_emit_binary (code
, target
, op0
, op1
);
4847 rtx zie
= mips_zero_if_equal (op0
, op1
);
4848 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4852 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
4855 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4856 CODE and jump to OPERANDS[3] if the condition holds. */
4859 mips_expand_conditional_branch (rtx
*operands
)
4861 enum rtx_code code
= GET_CODE (operands
[0]);
4862 rtx op0
= operands
[1];
4863 rtx op1
= operands
[2];
4866 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
4867 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
4868 emit_jump_insn (gen_condjump (condition
, operands
[3]));
4873 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4874 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4877 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
4878 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
4883 reversed_p
= mips_reversed_fp_cond (&cond
);
4884 cmp_result
= mips_allocate_fcc (CCV2mode
);
4885 emit_insn (gen_scc_ps (cmp_result
,
4886 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
4888 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
4891 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
4895 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4896 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4899 mips_expand_conditional_move (rtx
*operands
)
4902 enum rtx_code code
= GET_CODE (operands
[1]);
4903 rtx op0
= XEXP (operands
[1], 0);
4904 rtx op1
= XEXP (operands
[1], 1);
4906 mips_emit_compare (&code
, &op0
, &op1
, true);
4907 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
4908 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
4909 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
4910 operands
[2], operands
[3])));
4913 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4916 mips_expand_conditional_trap (rtx comparison
)
4919 enum machine_mode mode
;
4922 /* MIPS conditional trap instructions don't have GT or LE flavors,
4923 so we must swap the operands and convert to LT and GE respectively. */
4924 code
= GET_CODE (comparison
);
4931 code
= swap_condition (code
);
4932 op0
= XEXP (comparison
, 1);
4933 op1
= XEXP (comparison
, 0);
4937 op0
= XEXP (comparison
, 0);
4938 op1
= XEXP (comparison
, 1);
4942 mode
= GET_MODE (XEXP (comparison
, 0));
4943 op0
= force_reg (mode
, op0
);
4944 if (!arith_operand (op1
, mode
))
4945 op1
= force_reg (mode
, op1
);
4947 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
4948 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
4952 /* Initialize *CUM for a call to a function of type FNTYPE. */
4955 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
4957 memset (cum
, 0, sizeof (*cum
));
4958 cum
->prototype
= (fntype
&& prototype_p (fntype
));
4959 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
4962 /* Fill INFO with information about a single argument. CUM is the
4963 cumulative state for earlier arguments. MODE is the mode of this
4964 argument and TYPE is its type (if known). NAMED is true if this
4965 is a named (fixed) argument rather than a variable one. */
4968 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
4969 enum machine_mode mode
, const_tree type
, bool named
)
4971 bool doubleword_aligned_p
;
4972 unsigned int num_bytes
, num_words
, max_regs
;
4974 /* Work out the size of the argument. */
4975 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4976 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4978 /* Decide whether it should go in a floating-point register, assuming
4979 one is free. Later code checks for availability.
4981 The checks against UNITS_PER_FPVALUE handle the soft-float and
4982 single-float cases. */
4986 /* The EABI conventions have traditionally been defined in terms
4987 of TYPE_MODE, regardless of the actual type. */
4988 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4989 || mode
== V2SFmode
)
4990 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4995 /* Only leading floating-point scalars are passed in
4996 floating-point registers. We also handle vector floats the same
4997 say, which is OK because they are not covered by the standard ABI. */
4998 info
->fpr_p
= (!cum
->gp_reg_found
4999 && cum
->arg_number
< 2
5001 || SCALAR_FLOAT_TYPE_P (type
)
5002 || VECTOR_FLOAT_TYPE_P (type
))
5003 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5004 || mode
== V2SFmode
)
5005 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5010 /* Scalar, complex and vector floating-point types are passed in
5011 floating-point registers, as long as this is a named rather
5012 than a variable argument. */
5013 info
->fpr_p
= (named
5014 && (type
== 0 || FLOAT_TYPE_P (type
))
5015 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5016 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5017 || mode
== V2SFmode
)
5018 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5020 /* ??? According to the ABI documentation, the real and imaginary
5021 parts of complex floats should be passed in individual registers.
5022 The real and imaginary parts of stack arguments are supposed
5023 to be contiguous and there should be an extra word of padding
5026 This has two problems. First, it makes it impossible to use a
5027 single "void *" va_list type, since register and stack arguments
5028 are passed differently. (At the time of writing, MIPSpro cannot
5029 handle complex float varargs correctly.) Second, it's unclear
5030 what should happen when there is only one register free.
5032 For now, we assume that named complex floats should go into FPRs
5033 if there are two FPRs free, otherwise they should be passed in the
5034 same way as a struct containing two floats. */
5036 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5037 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5039 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5040 info
->fpr_p
= false;
5050 /* See whether the argument has doubleword alignment. */
5051 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5054 /* Set REG_OFFSET to the register count we're interested in.
5055 The EABI allocates the floating-point registers separately,
5056 but the other ABIs allocate them like integer registers. */
5057 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5061 /* Advance to an even register if the argument is doubleword-aligned. */
5062 if (doubleword_aligned_p
)
5063 info
->reg_offset
+= info
->reg_offset
& 1;
5065 /* Work out the offset of a stack argument. */
5066 info
->stack_offset
= cum
->stack_words
;
5067 if (doubleword_aligned_p
)
5068 info
->stack_offset
+= info
->stack_offset
& 1;
5070 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5072 /* Partition the argument between registers and stack. */
5073 info
->reg_words
= MIN (num_words
, max_regs
);
5074 info
->stack_words
= num_words
- info
->reg_words
;
5077 /* INFO describes a register argument that has the normal format for the
5078 argument's mode. Return the register it uses, assuming that FPRs are
5079 available if HARD_FLOAT_P. */
5082 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5084 if (!info
->fpr_p
|| !hard_float_p
)
5085 return GP_ARG_FIRST
+ info
->reg_offset
;
5086 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5087 /* In o32, the second argument is always passed in $f14
5088 for TARGET_DOUBLE_FLOAT, regardless of whether the
5089 first argument was a word or doubleword. */
5090 return FP_ARG_FIRST
+ 2;
5092 return FP_ARG_FIRST
+ info
->reg_offset
;
5095 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5098 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5100 return !TARGET_OLDABI
;
5103 /* Implement TARGET_FUNCTION_ARG. */
5106 mips_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
5107 const_tree type
, bool named
)
5109 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5110 struct mips_arg_info info
;
5112 /* We will be called with a mode of VOIDmode after the last argument
5113 has been seen. Whatever we return will be passed to the call expander.
5114 If we need a MIPS16 fp_code, return a REG with the code stored as
5116 if (mode
== VOIDmode
)
5118 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5119 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
5124 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5126 /* Return straight away if the whole argument is passed on the stack. */
5127 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5130 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5131 contains a double in its entirety, then that 64-bit chunk is passed
5132 in a floating-point register. */
5134 && TARGET_HARD_FLOAT
5137 && TREE_CODE (type
) == RECORD_TYPE
5138 && TYPE_SIZE_UNIT (type
)
5139 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
5143 /* First check to see if there is any such field. */
5144 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5145 if (TREE_CODE (field
) == FIELD_DECL
5146 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5147 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5148 && host_integerp (bit_position (field
), 0)
5149 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5154 /* Now handle the special case by returning a PARALLEL
5155 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5156 chunks are passed in registers. */
5158 HOST_WIDE_INT bitpos
;
5161 /* assign_parms checks the mode of ENTRY_PARM, so we must
5162 use the actual mode here. */
5163 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5166 field
= TYPE_FIELDS (type
);
5167 for (i
= 0; i
< info
.reg_words
; i
++)
5171 for (; field
; field
= DECL_CHAIN (field
))
5172 if (TREE_CODE (field
) == FIELD_DECL
5173 && int_bit_position (field
) >= bitpos
)
5177 && int_bit_position (field
) == bitpos
5178 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5179 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5180 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5182 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
5185 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5186 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5188 bitpos
+= BITS_PER_WORD
;
5194 /* Handle the n32/n64 conventions for passing complex floating-point
5195 arguments in FPR pairs. The real part goes in the lower register
5196 and the imaginary part goes in the upper register. */
5199 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5202 enum machine_mode inner
;
5205 inner
= GET_MODE_INNER (mode
);
5206 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
5207 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
5209 /* Real part in registers, imaginary part on stack. */
5210 gcc_assert (info
.stack_words
== info
.reg_words
);
5211 return gen_rtx_REG (inner
, regno
);
5215 gcc_assert (info
.stack_words
== 0);
5216 real
= gen_rtx_EXPR_LIST (VOIDmode
,
5217 gen_rtx_REG (inner
, regno
),
5219 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
5221 regno
+ info
.reg_words
/ 2),
5222 GEN_INT (GET_MODE_SIZE (inner
)));
5223 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
5227 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
5230 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5233 mips_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
5234 const_tree type
, bool named
)
5236 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5237 struct mips_arg_info info
;
5239 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5242 cum
->gp_reg_found
= true;
5244 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5245 an explanation of what this code does. It assumes that we're using
5246 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5248 if (cum
->arg_number
< 2 && info
.fpr_p
)
5249 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5251 /* Advance the register count. This has the effect of setting
5252 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5253 argument required us to skip the final GPR and pass the whole
5254 argument on the stack. */
5255 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5256 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5257 else if (info
.reg_words
> 0)
5258 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5260 /* Advance the stack word count. */
5261 if (info
.stack_words
> 0)
5262 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5267 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5270 mips_arg_partial_bytes (cumulative_args_t cum
,
5271 enum machine_mode mode
, tree type
, bool named
)
5273 struct mips_arg_info info
;
5275 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5276 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5279 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5280 least PARM_BOUNDARY bits of alignment, but will be given anything up
5281 to STACK_BOUNDARY bits if the type requires it. */
5284 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5286 unsigned int alignment
;
5288 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5289 if (alignment
< PARM_BOUNDARY
)
5290 alignment
= PARM_BOUNDARY
;
5291 if (alignment
> STACK_BOUNDARY
)
5292 alignment
= STACK_BOUNDARY
;
5296 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5297 upward rather than downward. In other words, return true if the
5298 first byte of the stack slot has useful data, false if the last
5302 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
5304 /* On little-endian targets, the first byte of every stack argument
5305 is passed in the first byte of the stack slot. */
5306 if (!BYTES_BIG_ENDIAN
)
5309 /* Otherwise, integral types are padded downward: the last byte of a
5310 stack argument is passed in the last byte of the stack slot. */
5312 ? (INTEGRAL_TYPE_P (type
)
5313 || POINTER_TYPE_P (type
)
5314 || FIXED_POINT_TYPE_P (type
))
5315 : (SCALAR_INT_MODE_P (mode
)
5316 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5319 /* Big-endian o64 pads floating-point arguments downward. */
5320 if (mips_abi
== ABI_O64
)
5321 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5324 /* Other types are padded upward for o32, o64, n32 and n64. */
5325 if (mips_abi
!= ABI_EABI
)
5328 /* Arguments smaller than a stack slot are padded downward. */
5329 if (mode
!= BLKmode
)
5330 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5332 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5335 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5336 if the least significant byte of the register has useful data. Return
5337 the opposite if the most significant byte does. */
5340 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
5342 /* No shifting is required for floating-point arguments. */
5343 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5344 return !BYTES_BIG_ENDIAN
;
5346 /* Otherwise, apply the same padding to register arguments as we do
5347 to stack arguments. */
5348 return mips_pad_arg_upward (mode
, type
);
5351 /* Return nonzero when an argument must be passed by reference. */
5354 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5355 enum machine_mode mode
, const_tree type
,
5356 bool named ATTRIBUTE_UNUSED
)
5358 if (mips_abi
== ABI_EABI
)
5362 /* ??? How should SCmode be handled? */
5363 if (mode
== DImode
|| mode
== DFmode
5364 || mode
== DQmode
|| mode
== UDQmode
5365 || mode
== DAmode
|| mode
== UDAmode
)
5368 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5369 return size
== -1 || size
> UNITS_PER_WORD
;
5373 /* If we have a variable-sized parameter, we have no choice. */
5374 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5378 /* Implement TARGET_CALLEE_COPIES. */
5381 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5382 enum machine_mode mode ATTRIBUTE_UNUSED
,
5383 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5385 return mips_abi
== ABI_EABI
&& named
;
5388 /* See whether VALTYPE is a record whose fields should be returned in
5389 floating-point registers. If so, return the number of fields and
5390 list them in FIELDS (which should have two elements). Return 0
5393 For n32 & n64, a structure with one or two fields is returned in
5394 floating-point registers as long as every field has a floating-point
5398 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5406 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5410 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5412 if (TREE_CODE (field
) != FIELD_DECL
)
5415 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5421 fields
[i
++] = field
;
5426 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5427 a value in the most significant part of $2/$3 if:
5429 - the target is big-endian;
5431 - the value has a structure or union type (we generalize this to
5432 cover aggregates from other languages too); and
5434 - the structure is not returned in floating-point registers. */
5437 mips_return_in_msb (const_tree valtype
)
5441 return (TARGET_NEWABI
5442 && TARGET_BIG_ENDIAN
5443 && AGGREGATE_TYPE_P (valtype
)
5444 && mips_fpr_return_fields (valtype
, fields
) == 0);
5447 /* Return true if the function return value MODE will get returned in a
5448 floating-point register. */
5451 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5453 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5455 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5456 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5459 /* Return the representation of an FPR return register when the
5460 value being returned in FP_RETURN has mode VALUE_MODE and the
5461 return type itself has mode TYPE_MODE. On NewABI targets,
5462 the two modes may be different for structures like:
5464 struct __attribute__((packed)) foo { float f; }
5466 where we return the SFmode value of "f" in FP_RETURN, but where
5467 the structure itself has mode BLKmode. */
5470 mips_return_fpr_single (enum machine_mode type_mode
,
5471 enum machine_mode value_mode
)
5475 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5476 if (type_mode
!= value_mode
)
5478 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5479 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5484 /* Return a composite value in a pair of floating-point registers.
5485 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5486 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5489 For n32 & n64, $f0 always holds the first value and $f2 the second.
5490 Otherwise the values are packed together as closely as possible. */
5493 mips_return_fpr_pair (enum machine_mode mode
,
5494 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5495 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5499 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5500 return gen_rtx_PARALLEL
5503 gen_rtx_EXPR_LIST (VOIDmode
,
5504 gen_rtx_REG (mode1
, FP_RETURN
),
5506 gen_rtx_EXPR_LIST (VOIDmode
,
5507 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5508 GEN_INT (offset2
))));
5512 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5513 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5514 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5517 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5518 enum machine_mode mode
)
5526 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5527 func
= fn_decl_or_type
;
5531 mode
= TYPE_MODE (valtype
);
5532 unsigned_p
= TYPE_UNSIGNED (valtype
);
5534 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5535 return values, promote the mode here too. */
5536 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5538 /* Handle structures whose fields are returned in $f0/$f2. */
5539 switch (mips_fpr_return_fields (valtype
, fields
))
5542 return mips_return_fpr_single (mode
,
5543 TYPE_MODE (TREE_TYPE (fields
[0])));
5546 return mips_return_fpr_pair (mode
,
5547 TYPE_MODE (TREE_TYPE (fields
[0])),
5548 int_byte_position (fields
[0]),
5549 TYPE_MODE (TREE_TYPE (fields
[1])),
5550 int_byte_position (fields
[1]));
5553 /* If a value is passed in the most significant part of a register, see
5554 whether we have to round the mode up to a whole number of words. */
5555 if (mips_return_in_msb (valtype
))
5557 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5558 if (size
% UNITS_PER_WORD
!= 0)
5560 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5561 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5565 /* For EABI, the class of return register depends entirely on MODE.
5566 For example, "struct { some_type x; }" and "union { some_type x; }"
5567 are returned in the same way as a bare "some_type" would be.
5568 Other ABIs only use FPRs for scalar, complex or vector types. */
5569 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5570 return gen_rtx_REG (mode
, GP_RETURN
);
5575 /* Handle long doubles for n32 & n64. */
5577 return mips_return_fpr_pair (mode
,
5579 DImode
, GET_MODE_SIZE (mode
) / 2);
5581 if (mips_return_mode_in_fpr_p (mode
))
5583 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5584 return mips_return_fpr_pair (mode
,
5585 GET_MODE_INNER (mode
), 0,
5586 GET_MODE_INNER (mode
),
5587 GET_MODE_SIZE (mode
) / 2);
5589 return gen_rtx_REG (mode
, FP_RETURN
);
5593 return gen_rtx_REG (mode
, GP_RETURN
);
5596 /* Implement TARGET_FUNCTION_VALUE. */
5599 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5600 bool outgoing ATTRIBUTE_UNUSED
)
5602 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5605 /* Implement TARGET_LIBCALL_VALUE. */
5608 mips_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5610 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5613 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5615 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5616 Currently, R2 and F0 are only implemented here (C has no complex type). */
5619 mips_function_value_regno_p (const unsigned int regno
)
5621 if (regno
== GP_RETURN
5622 || regno
== FP_RETURN
5623 || (LONG_DOUBLE_TYPE_SIZE
== 128
5624 && FP_RETURN
!= GP_RETURN
5625 && regno
== FP_RETURN
+ 2))
5631 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5632 all BLKmode objects are returned in memory. Under the n32, n64
5633 and embedded ABIs, small structures are returned in a register.
5634 Objects with varying size must still be returned in memory, of
5638 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5640 return (TARGET_OLDABI
5641 ? TYPE_MODE (type
) == BLKmode
5642 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5645 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5648 mips_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
5649 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5652 CUMULATIVE_ARGS local_cum
;
5653 int gp_saved
, fp_saved
;
5655 /* The caller has advanced CUM up to, but not beyond, the last named
5656 argument. Advance a local copy of CUM past the last "real" named
5657 argument, to find out how many registers are left over. */
5658 local_cum
= *get_cumulative_args (cum
);
5659 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5662 /* Found out how many registers we need to save. */
5663 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5664 fp_saved
= (EABI_FLOAT_VARARGS_P
5665 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5674 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
5675 REG_PARM_STACK_SPACE (cfun
->decl
)
5676 - gp_saved
* UNITS_PER_WORD
);
5677 mem
= gen_frame_mem (BLKmode
, ptr
);
5678 set_mem_alias_set (mem
, get_varargs_alias_set ());
5680 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5685 /* We can't use move_block_from_reg, because it will use
5687 enum machine_mode mode
;
5690 /* Set OFF to the offset from virtual_incoming_args_rtx of
5691 the first float register. The FP save area lies below
5692 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5693 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5694 off
-= fp_saved
* UNITS_PER_FPREG
;
5696 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5698 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5699 i
+= MAX_FPRS_PER_FMT
)
5703 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
5704 mem
= gen_frame_mem (mode
, ptr
);
5705 set_mem_alias_set (mem
, get_varargs_alias_set ());
5706 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5707 off
+= UNITS_PER_HWFPVALUE
;
5711 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5712 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5713 + fp_saved
* UNITS_PER_FPREG
);
5716 /* Implement TARGET_BUILTIN_VA_LIST. */
5719 mips_build_builtin_va_list (void)
5721 if (EABI_FLOAT_VARARGS_P
)
5723 /* We keep 3 pointers, and two offsets.
5725 Two pointers are to the overflow area, which starts at the CFA.
5726 One of these is constant, for addressing into the GPR save area
5727 below it. The other is advanced up the stack through the
5730 The third pointer is to the bottom of the GPR save area.
5731 Since the FPR save area is just below it, we can address
5732 FPR slots off this pointer.
5734 We also keep two one-byte offsets, which are to be subtracted
5735 from the constant pointers to yield addresses in the GPR and
5736 FPR save areas. These are downcounted as float or non-float
5737 arguments are used, and when they get to zero, the argument
5738 must be obtained from the overflow region. */
5739 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5742 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5744 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5745 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5747 f_gtop
= build_decl (BUILTINS_LOCATION
,
5748 FIELD_DECL
, get_identifier ("__gpr_top"),
5750 f_ftop
= build_decl (BUILTINS_LOCATION
,
5751 FIELD_DECL
, get_identifier ("__fpr_top"),
5753 f_goff
= build_decl (BUILTINS_LOCATION
,
5754 FIELD_DECL
, get_identifier ("__gpr_offset"),
5755 unsigned_char_type_node
);
5756 f_foff
= build_decl (BUILTINS_LOCATION
,
5757 FIELD_DECL
, get_identifier ("__fpr_offset"),
5758 unsigned_char_type_node
);
5759 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5760 warn on every user file. */
5761 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5762 array
= build_array_type (unsigned_char_type_node
,
5763 build_index_type (index
));
5764 f_res
= build_decl (BUILTINS_LOCATION
,
5765 FIELD_DECL
, get_identifier ("__reserved"), array
);
5767 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5768 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5769 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5770 DECL_FIELD_CONTEXT (f_goff
) = record
;
5771 DECL_FIELD_CONTEXT (f_foff
) = record
;
5772 DECL_FIELD_CONTEXT (f_res
) = record
;
5774 TYPE_FIELDS (record
) = f_ovfl
;
5775 DECL_CHAIN (f_ovfl
) = f_gtop
;
5776 DECL_CHAIN (f_gtop
) = f_ftop
;
5777 DECL_CHAIN (f_ftop
) = f_goff
;
5778 DECL_CHAIN (f_goff
) = f_foff
;
5779 DECL_CHAIN (f_foff
) = f_res
;
5781 layout_type (record
);
5785 /* Otherwise, we use 'void *'. */
5786 return ptr_type_node
;
5789 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5792 mips_va_start (tree valist
, rtx nextarg
)
5794 if (EABI_FLOAT_VARARGS_P
)
5796 const CUMULATIVE_ARGS
*cum
;
5797 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5798 tree ovfl
, gtop
, ftop
, goff
, foff
;
5800 int gpr_save_area_size
;
5801 int fpr_save_area_size
;
5804 cum
= &crtl
->args
.info
;
5806 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5808 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5810 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5811 f_gtop
= DECL_CHAIN (f_ovfl
);
5812 f_ftop
= DECL_CHAIN (f_gtop
);
5813 f_goff
= DECL_CHAIN (f_ftop
);
5814 f_foff
= DECL_CHAIN (f_goff
);
5816 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5818 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5820 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5822 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5824 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5827 /* Emit code to initialize OVFL, which points to the next varargs
5828 stack argument. CUM->STACK_WORDS gives the number of stack
5829 words used by named arguments. */
5830 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5831 if (cum
->stack_words
> 0)
5832 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
5833 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5834 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5836 /* Emit code to initialize GTOP, the top of the GPR save area. */
5837 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5838 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5839 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5841 /* Emit code to initialize FTOP, the top of the FPR save area.
5842 This address is gpr_save_area_bytes below GTOP, rounded
5843 down to the next fp-aligned boundary. */
5844 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5845 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5846 fpr_offset
&= -UNITS_PER_FPVALUE
;
5848 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
5849 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5850 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5852 /* Emit code to initialize GOFF, the offset from GTOP of the
5853 next GPR argument. */
5854 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5855 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
5856 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5858 /* Likewise emit code to initialize FOFF, the offset from FTOP
5859 of the next FPR argument. */
5860 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5861 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
5862 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5866 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
5867 std_expand_builtin_va_start (valist
, nextarg
);
5871 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5875 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5878 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
5879 unsigned HOST_WIDE_INT align
, boundary
;
5882 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
5884 type
= build_pointer_type (type
);
5886 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
5887 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
5889 /* When we align parameter on stack for caller, if the parameter
5890 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5891 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5892 here with caller. */
5893 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
5894 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
5896 boundary
/= BITS_PER_UNIT
;
5898 /* Hoist the valist value into a temporary for the moment. */
5899 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
5901 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5902 requires greater alignment, we must perform dynamic alignment. */
5903 if (boundary
> align
)
5905 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5906 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
5907 gimplify_and_add (t
, pre_p
);
5909 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5910 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
5912 build_int_cst (TREE_TYPE (valist
), -boundary
)));
5913 gimplify_and_add (t
, pre_p
);
5918 /* If the actual alignment is less than the alignment of the type,
5919 adjust the type accordingly so that we don't assume strict alignment
5920 when dereferencing the pointer. */
5921 boundary
*= BITS_PER_UNIT
;
5922 if (boundary
< TYPE_ALIGN (type
))
5924 type
= build_variant_type_copy (type
);
5925 TYPE_ALIGN (type
) = boundary
;
5928 /* Compute the rounded size of the type. */
5929 type_size
= size_in_bytes (type
);
5930 rounded_size
= round_up (type_size
, align
);
5932 /* Reduce rounded_size so it's sharable with the postqueue. */
5933 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
5937 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
5939 /* Small args are padded downward. */
5940 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
5941 rounded_size
, size_int (align
));
5942 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
5943 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
5944 addr
= fold_build_pointer_plus (addr
, t
);
5947 /* Compute new value for AP. */
5948 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
5949 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
5950 gimplify_and_add (t
, pre_p
);
5952 addr
= fold_convert (build_pointer_type (type
), addr
);
5955 addr
= build_va_arg_indirect_ref (addr
);
5957 return build_va_arg_indirect_ref (addr
);
5960 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5963 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5969 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
5971 type
= build_pointer_type (type
);
5973 if (!EABI_FLOAT_VARARGS_P
)
5974 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5977 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5978 tree ovfl
, top
, off
, align
;
5979 HOST_WIDE_INT size
, rsize
, osize
;
5982 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5983 f_gtop
= DECL_CHAIN (f_ovfl
);
5984 f_ftop
= DECL_CHAIN (f_gtop
);
5985 f_goff
= DECL_CHAIN (f_ftop
);
5986 f_foff
= DECL_CHAIN (f_goff
);
5990 TOP be the top of the GPR or FPR save area;
5991 OFF be the offset from TOP of the next register;
5992 ADDR_RTX be the address of the argument;
5993 SIZE be the number of bytes in the argument type;
5994 RSIZE be the number of bytes used to store the argument
5995 when it's in the register save area; and
5996 OSIZE be the number of bytes used to store it when it's
5997 in the stack overflow area.
5999 The code we want is:
6001 1: off &= -rsize; // round down
6004 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6009 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6010 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6014 [1] and [9] can sometimes be optimized away. */
6016 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6018 size
= int_size_in_bytes (type
);
6020 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6021 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6023 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6024 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6025 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6026 unshare_expr (valist
), f_foff
, NULL_TREE
);
6028 /* When va_start saves FPR arguments to the stack, each slot
6029 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6030 argument's precision. */
6031 rsize
= UNITS_PER_HWFPVALUE
;
6033 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6034 (= PARM_BOUNDARY bits). This can be different from RSIZE
6037 (1) On 32-bit targets when TYPE is a structure such as:
6039 struct s { float f; };
6041 Such structures are passed in paired FPRs, so RSIZE
6042 will be 8 bytes. However, the structure only takes
6043 up 4 bytes of memory, so OSIZE will only be 4.
6045 (2) In combinations such as -mgp64 -msingle-float
6046 -fshort-double. Doubles passed in registers will then take
6047 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6048 stack take up UNITS_PER_WORD bytes. */
6049 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6053 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6054 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6055 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6056 unshare_expr (valist
), f_goff
, NULL_TREE
);
6057 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6058 if (rsize
> UNITS_PER_WORD
)
6060 /* [1] Emit code for: off &= -rsize. */
6061 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6062 build_int_cst (TREE_TYPE (off
), -rsize
));
6063 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6068 /* [2] Emit code to branch if off == 0. */
6069 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6070 build_int_cst (TREE_TYPE (off
), 0));
6071 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6073 /* [5] Emit code for: off -= rsize. We do this as a form of
6074 post-decrement not available to C. */
6075 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6076 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6078 /* [4] Emit code for:
6079 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6080 t
= fold_convert (sizetype
, t
);
6081 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6082 t
= fold_build_pointer_plus (top
, t
);
6083 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6084 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6085 COND_EXPR_THEN (addr
) = t
;
6087 if (osize
> UNITS_PER_WORD
)
6089 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6090 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6091 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6092 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6093 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6094 unshare_expr (ovfl
), t
);
6099 /* [10, 11] Emit code for:
6100 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6102 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6103 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6104 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6105 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6107 /* String [9] and [10, 11] together. */
6109 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6110 COND_EXPR_ELSE (addr
) = t
;
6112 addr
= fold_convert (build_pointer_type (type
), addr
);
6113 addr
= build_va_arg_indirect_ref (addr
);
6117 addr
= build_va_arg_indirect_ref (addr
);
6122 /* Declare a unique, locally-binding function called NAME, then start
6126 mips_start_unique_function (const char *name
)
6130 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6131 get_identifier (name
),
6132 build_function_type_list (void_type_node
, NULL_TREE
));
6133 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6134 NULL_TREE
, void_type_node
);
6135 TREE_PUBLIC (decl
) = 1;
6136 TREE_STATIC (decl
) = 1;
6138 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
6140 targetm
.asm_out
.unique_section (decl
, 0);
6141 switch_to_section (get_named_section (decl
, NULL
, 0));
6143 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6144 fputs ("\t.hidden\t", asm_out_file
);
6145 assemble_name (asm_out_file
, name
);
6146 putc ('\n', asm_out_file
);
6149 /* Start a definition of function NAME. MIPS16_P indicates whether the
6150 function contains MIPS16 code. */
6153 mips_start_function_definition (const char *name
, bool mips16_p
)
6156 fprintf (asm_out_file
, "\t.set\tmips16\n");
6158 fprintf (asm_out_file
, "\t.set\tnomips16\n");
6160 if (TARGET_MICROMIPS
)
6161 fprintf (asm_out_file
, "\t.set\tmicromips\n");
6162 #ifdef HAVE_GAS_MICROMIPS
6164 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
6167 if (!flag_inhibit_size_directive
)
6169 fputs ("\t.ent\t", asm_out_file
);
6170 assemble_name (asm_out_file
, name
);
6171 fputs ("\n", asm_out_file
);
6174 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
6176 /* Start the definition proper. */
6177 assemble_name (asm_out_file
, name
);
6178 fputs (":\n", asm_out_file
);
6181 /* End a function definition started by mips_start_function_definition. */
6184 mips_end_function_definition (const char *name
)
6186 if (!flag_inhibit_size_directive
)
6188 fputs ("\t.end\t", asm_out_file
);
6189 assemble_name (asm_out_file
, name
);
6190 fputs ("\n", asm_out_file
);
6194 /* Output a definition of the __mips16_rdhwr function. */
6197 mips_output_mips16_rdhwr (void)
6201 name
= "__mips16_rdhwr";
6202 mips_start_unique_function (name
);
6203 mips_start_function_definition (name
, false);
6204 fprintf (asm_out_file
,
6206 "\t.set\tmips32r2\n"
6207 "\t.set\tnoreorder\n"
6211 mips_end_function_definition (name
);
6214 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6217 mips_ok_for_lazy_binding_p (rtx x
)
6219 return (TARGET_USE_GOT
6220 && GET_CODE (x
) == SYMBOL_REF
6221 && !SYMBOL_REF_BIND_NOW_P (x
)
6222 && !mips_symbol_binds_local_p (x
));
6225 /* Load function address ADDR into register DEST. TYPE is as for
6226 mips_expand_call. Return true if we used an explicit lazy-binding
6230 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
6232 /* If we're generating PIC, and this call is to a global function,
6233 try to allow its address to be resolved lazily. This isn't
6234 possible for sibcalls when $gp is call-saved because the value
6235 of $gp on entry to the stub would be our caller's gp, not ours. */
6236 if (TARGET_EXPLICIT_RELOCS
6237 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
6238 && mips_ok_for_lazy_binding_p (addr
))
6240 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
6241 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
6246 mips_emit_move (dest
, addr
);
6251 /* Each locally-defined hard-float MIPS16 function has a local symbol
6252 associated with it. This hash table maps the function symbol (FUNC)
6253 to the local symbol (LOCAL). */
6254 struct GTY(()) mips16_local_alias
{
6258 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
6260 /* Hash table callbacks for mips16_local_aliases. */
6263 mips16_local_aliases_hash (const void *entry
)
6265 const struct mips16_local_alias
*alias
;
6267 alias
= (const struct mips16_local_alias
*) entry
;
6268 return htab_hash_string (XSTR (alias
->func
, 0));
6272 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
6274 const struct mips16_local_alias
*alias1
, *alias2
;
6276 alias1
= (const struct mips16_local_alias
*) entry1
;
6277 alias2
= (const struct mips16_local_alias
*) entry2
;
6278 return rtx_equal_p (alias1
->func
, alias2
->func
);
6281 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6282 Return a local alias for it, creating a new one if necessary. */
6285 mips16_local_alias (rtx func
)
6287 struct mips16_local_alias
*alias
, tmp_alias
;
6290 /* Create the hash table if this is the first call. */
6291 if (mips16_local_aliases
== NULL
)
6292 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
6293 mips16_local_aliases_eq
, NULL
);
6295 /* Look up the function symbol, creating a new entry if need be. */
6296 tmp_alias
.func
= func
;
6297 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
6298 gcc_assert (slot
!= NULL
);
6300 alias
= (struct mips16_local_alias
*) *slot
;
6303 const char *func_name
, *local_name
;
6306 /* Create a new SYMBOL_REF for the local symbol. The choice of
6307 __fn_local_* is based on the __fn_stub_* names that we've
6308 traditionally used for the non-MIPS16 stub. */
6309 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6310 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6311 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6312 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6314 /* Create a new structure to represent the mapping. */
6315 alias
= ggc_alloc_mips16_local_alias ();
6317 alias
->local
= local
;
6320 return alias
->local
;
6323 /* A chained list of functions for which mips16_build_call_stub has already
6324 generated a stub. NAME is the name of the function and FP_RET_P is true
6325 if the function returns a value in floating-point registers. */
6326 struct mips16_stub
{
6327 struct mips16_stub
*next
;
6331 static struct mips16_stub
*mips16_stubs
;
6333 /* Return the two-character string that identifies floating-point
6334 return mode MODE in the name of a MIPS16 function stub. */
6337 mips16_call_stub_mode_suffix (enum machine_mode mode
)
6341 else if (mode
== DFmode
)
6343 else if (mode
== SCmode
)
6345 else if (mode
== DCmode
)
6347 else if (mode
== V2SFmode
)
6353 /* Write instructions to move a 32-bit value between general register
6354 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6355 from GPREG to FPREG and 'f' to move in the opposite direction. */
6358 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6360 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6361 reg_names
[gpreg
], reg_names
[fpreg
]);
6364 /* Likewise for 64-bit values. */
6367 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6370 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6371 reg_names
[gpreg
], reg_names
[fpreg
]);
6372 else if (TARGET_FLOAT64
)
6374 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6375 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6376 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6377 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6381 /* Move the least-significant word. */
6382 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6383 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6384 /* ...then the most significant word. */
6385 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6386 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6390 /* Write out code to move floating-point arguments into or out of
6391 general registers. FP_CODE is the code describing which arguments
6392 are present (see the comment above the definition of CUMULATIVE_ARGS
6393 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6396 mips_output_args_xfer (int fp_code
, char direction
)
6398 unsigned int gparg
, fparg
, f
;
6399 CUMULATIVE_ARGS cum
;
6401 /* This code only works for o32 and o64. */
6402 gcc_assert (TARGET_OLDABI
);
6404 mips_init_cumulative_args (&cum
, NULL
);
6406 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6408 enum machine_mode mode
;
6409 struct mips_arg_info info
;
6413 else if ((f
& 3) == 2)
6418 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6419 gparg
= mips_arg_regno (&info
, false);
6420 fparg
= mips_arg_regno (&info
, true);
6423 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6425 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6427 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6431 /* Write a MIPS16 stub for the current function. This stub is used
6432 for functions which take arguments in the floating-point registers.
6433 It is normal-mode code that moves the floating-point arguments
6434 into the general registers and then jumps to the MIPS16 code. */
6437 mips16_build_function_stub (void)
6439 const char *fnname
, *alias_name
, *separator
;
6440 char *secname
, *stubname
;
6445 /* Create the name of the stub, and its unique section. */
6446 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6447 alias
= mips16_local_alias (symbol
);
6449 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6450 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6451 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6452 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6454 /* Build a decl for the stub. */
6455 stubdecl
= build_decl (BUILTINS_LOCATION
,
6456 FUNCTION_DECL
, get_identifier (stubname
),
6457 build_function_type_list (void_type_node
, NULL_TREE
));
6458 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6459 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6460 RESULT_DECL
, NULL_TREE
, void_type_node
);
6462 /* Output a comment. */
6463 fprintf (asm_out_file
, "\t# Stub function for %s (",
6464 current_function_name ());
6466 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6468 fprintf (asm_out_file
, "%s%s", separator
,
6469 (f
& 3) == 1 ? "float" : "double");
6472 fprintf (asm_out_file
, ")\n");
6474 /* Start the function definition. */
6475 assemble_start_function (stubdecl
, stubname
);
6476 mips_start_function_definition (stubname
, false);
6478 /* If generating pic2 code, either set up the global pointer or
6480 if (TARGET_ABICALLS_PIC2
)
6482 if (TARGET_ABSOLUTE_ABICALLS
)
6483 fprintf (asm_out_file
, "\t.option\tpic0\n");
6486 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6487 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6488 target function is. Use a local GOT access when loading the
6489 symbol, to cut down on the number of unnecessary GOT entries
6490 for stubs that aren't needed. */
6491 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6496 /* Load the address of the MIPS16 function into $25. Do this first so
6497 that targets with coprocessor interlocks can use an MFC1 to fill the
6499 output_asm_insn ("la\t%^,%0", &symbol
);
6501 /* Move the arguments from floating-point registers to general registers. */
6502 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6504 /* Jump to the MIPS16 function. */
6505 output_asm_insn ("jr\t%^", NULL
);
6507 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6508 fprintf (asm_out_file
, "\t.option\tpic2\n");
6510 mips_end_function_definition (stubname
);
6512 /* If the linker needs to create a dynamic symbol for the target
6513 function, it will associate the symbol with the stub (which,
6514 unlike the target function, follows the proper calling conventions).
6515 It is therefore useful to have a local alias for the target function,
6516 so that it can still be identified as MIPS16 code. As an optimization,
6517 this symbol can also be used for indirect MIPS16 references from
6518 within this file. */
6519 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6521 switch_to_section (function_section (current_function_decl
));
6524 /* The current function is a MIPS16 function that returns a value in an FPR.
6525 Copy the return value from its soft-float to its hard-float location.
6526 libgcc2 has special non-MIPS16 helper functions for each case. */
6529 mips16_copy_fpr_return_value (void)
6531 rtx fn
, insn
, retval
;
6533 enum machine_mode return_mode
;
6536 return_type
= DECL_RESULT (current_function_decl
);
6537 return_mode
= DECL_MODE (return_type
);
6539 name
= ACONCAT (("__mips16_ret_",
6540 mips16_call_stub_mode_suffix (return_mode
),
6542 fn
= mips16_stub_function (name
);
6544 /* The function takes arguments in $2 (and possibly $3), so calls
6545 to it cannot be lazily bound. */
6546 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6548 /* Model the call as something that takes the GPR return value as
6549 argument and returns an "updated" value. */
6550 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6551 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6552 const0_rtx
, NULL_RTX
, false);
6553 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6556 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6557 RETVAL is the location of the return value, or null if this is
6558 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6559 arguments and FP_CODE is the code built by mips_function_arg;
6560 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6562 There are three alternatives:
6564 - If a stub was needed, emit the call and return the call insn itself.
6566 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6567 to the new target and return null.
6569 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6572 A stub is needed for calls to functions that, in normal mode,
6573 receive arguments in FPRs or return values in FPRs. The stub
6574 copies the arguments from their soft-float positions to their
6575 hard-float positions, calls the real function, then copies the
6576 return value from its hard-float position to its soft-float
6579 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6580 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6581 automatically redirects the JAL to the stub, otherwise the JAL
6582 continues to call FN directly. */
6585 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6589 struct mips16_stub
*l
;
6592 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6593 we were invoked with the -msoft-float option. */
6594 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6597 /* Figure out whether the value might come back in a floating-point
6599 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6601 /* We don't need to do anything if there were no floating-point
6602 arguments and the value will not be returned in a floating-point
6604 if (fp_code
== 0 && !fp_ret_p
)
6607 /* We don't need to do anything if this is a call to a special
6608 MIPS16 support function. */
6610 if (mips16_stub_function_p (fn
))
6613 /* If we're calling a locally-defined MIPS16 function, we know that
6614 it will return values in both the "soft-float" and "hard-float"
6615 registers. There is no need to use a stub to move the latter
6617 if (fp_code
== 0 && mips16_local_function_p (fn
))
6620 /* This code will only work for o32 and o64 abis. The other ABI's
6621 require more sophisticated support. */
6622 gcc_assert (TARGET_OLDABI
);
6624 /* If we're calling via a function pointer, use one of the magic
6625 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6626 Each stub expects the function address to arrive in register $2. */
6627 if (GET_CODE (fn
) != SYMBOL_REF
6628 || !call_insn_operand (fn
, VOIDmode
))
6631 rtx stub_fn
, insn
, addr
;
6634 /* If this is a locally-defined and locally-binding function,
6635 avoid the stub by calling the local alias directly. */
6636 if (mips16_local_function_p (fn
))
6638 *fn_ptr
= mips16_local_alias (fn
);
6642 /* Create a SYMBOL_REF for the libgcc.a function. */
6644 sprintf (buf
, "__mips16_call_stub_%s_%d",
6645 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6648 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6649 stub_fn
= mips16_stub_function (buf
);
6651 /* The function uses $2 as an argument, so calls to it
6652 cannot be lazily bound. */
6653 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6655 /* Load the target function into $2. */
6656 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6657 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6659 /* Emit the call. */
6660 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6661 args_size
, NULL_RTX
, lazy_p
);
6663 /* Tell GCC that this call does indeed use the value of $2. */
6664 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6666 /* If we are handling a floating-point return value, we need to
6667 save $18 in the function prologue. Putting a note on the
6668 call will mean that df_regs_ever_live_p ($18) will be true if the
6669 call is not eliminated, and we can check that in the prologue
6672 CALL_INSN_FUNCTION_USAGE (insn
) =
6673 gen_rtx_EXPR_LIST (VOIDmode
,
6674 gen_rtx_CLOBBER (VOIDmode
,
6675 gen_rtx_REG (word_mode
, 18)),
6676 CALL_INSN_FUNCTION_USAGE (insn
));
6681 /* We know the function we are going to call. If we have already
6682 built a stub, we don't need to do anything further. */
6683 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6684 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6685 if (strcmp (l
->name
, fnname
) == 0)
6690 const char *separator
;
6691 char *secname
, *stubname
;
6692 tree stubid
, stubdecl
;
6695 /* If the function does not return in FPRs, the special stub
6699 If the function does return in FPRs, the stub section is named
6700 .mips16.call.fp.FNNAME
6702 Build a decl for the stub. */
6703 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6705 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6707 stubid
= get_identifier (stubname
);
6708 stubdecl
= build_decl (BUILTINS_LOCATION
,
6709 FUNCTION_DECL
, stubid
,
6710 build_function_type_list (void_type_node
,
6712 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6713 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6714 RESULT_DECL
, NULL_TREE
,
6717 /* Output a comment. */
6718 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6720 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6724 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6726 fprintf (asm_out_file
, "%s%s", separator
,
6727 (f
& 3) == 1 ? "float" : "double");
6730 fprintf (asm_out_file
, ")\n");
6732 /* Start the function definition. */
6733 assemble_start_function (stubdecl
, stubname
);
6734 mips_start_function_definition (stubname
, false);
6738 fprintf (asm_out_file
, "\t.cfi_startproc\n");
6740 /* Create a fake CFA 4 bytes below the stack pointer.
6741 This works around unwinders (like libgcc's) that expect
6742 the CFA for non-signal frames to be unique. */
6743 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
6745 /* "Save" $sp in itself so we don't use the fake CFA.
6746 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6747 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
6751 /* Load the address of the MIPS16 function into $25. Do this
6752 first so that targets with coprocessor interlocks can use
6753 an MFC1 to fill the delay slot. */
6754 if (TARGET_EXPLICIT_RELOCS
)
6756 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6757 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6760 output_asm_insn ("la\t%^,%0", &fn
);
6763 /* Move the arguments from general registers to floating-point
6765 mips_output_args_xfer (fp_code
, 't');
6769 /* Save the return address in $18 and call the non-MIPS16 function.
6770 The stub's caller knows that $18 might be clobbered, even though
6771 $18 is usually a call-saved register. */
6772 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6773 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6774 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6775 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
6777 /* Move the result from floating-point registers to
6778 general registers. */
6779 switch (GET_MODE (retval
))
6782 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6784 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6786 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6787 TARGET_LITTLE_ENDIAN
6788 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6790 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6792 /* On 64-bit targets, complex floats are returned in
6793 a single GPR, such that "sd" on a suitably-aligned
6794 target would store the value correctly. */
6795 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6796 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6797 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6798 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6799 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6800 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6801 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6802 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6803 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6804 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6805 reg_names
[GP_RETURN
],
6806 reg_names
[GP_RETURN
],
6807 reg_names
[GP_RETURN
+ 1]);
6812 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6816 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6817 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6821 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6827 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6828 fprintf (asm_out_file
, "\t.cfi_endproc\n");
6832 /* Jump to the previously-loaded address. */
6833 output_asm_insn ("jr\t%^", NULL
);
6836 #ifdef ASM_DECLARE_FUNCTION_SIZE
6837 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6840 mips_end_function_definition (stubname
);
6842 /* Record this stub. */
6843 l
= XNEW (struct mips16_stub
);
6844 l
->name
= xstrdup (fnname
);
6845 l
->fp_ret_p
= fp_ret_p
;
6846 l
->next
= mips16_stubs
;
6850 /* If we expect a floating-point return value, but we've built a
6851 stub which does not expect one, then we're in trouble. We can't
6852 use the existing stub, because it won't handle the floating-point
6853 value. We can't build a new stub, because the linker won't know
6854 which stub to use for the various calls in this object file.
6855 Fortunately, this case is illegal, since it means that a function
6856 was declared in two different ways in a single compilation. */
6857 if (fp_ret_p
&& !l
->fp_ret_p
)
6858 error ("cannot handle inconsistent calls to %qs", fnname
);
6860 if (retval
== NULL_RTX
)
6861 insn
= gen_call_internal_direct (fn
, args_size
);
6863 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
6864 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
6866 /* If we are calling a stub which handles a floating-point return
6867 value, we need to arrange to save $18 in the prologue. We do this
6868 by marking the function call as using the register. The prologue
6869 will later see that it is used, and emit code to save it. */
6871 CALL_INSN_FUNCTION_USAGE (insn
) =
6872 gen_rtx_EXPR_LIST (VOIDmode
,
6873 gen_rtx_CLOBBER (VOIDmode
,
6874 gen_rtx_REG (word_mode
, 18)),
6875 CALL_INSN_FUNCTION_USAGE (insn
));
6880 /* Expand a call of type TYPE. RESULT is where the result will go (null
6881 for "call"s and "sibcall"s), ADDR is the address of the function,
6882 ARGS_SIZE is the size of the arguments and AUX is the value passed
6883 to us by mips_function_arg. LAZY_P is true if this call already
6884 involves a lazily-bound function address (such as when calling
6885 functions through a MIPS16 hard-float stub).
6887 Return the call itself. */
6890 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
6891 rtx args_size
, rtx aux
, bool lazy_p
)
6893 rtx orig_addr
, pattern
, insn
;
6896 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
6897 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
6900 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
6905 if (!call_insn_operand (addr
, VOIDmode
))
6907 if (type
== MIPS_CALL_EPILOGUE
)
6908 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
6910 addr
= gen_reg_rtx (Pmode
);
6911 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
6916 rtx (*fn
) (rtx
, rtx
);
6918 if (type
== MIPS_CALL_SIBCALL
)
6919 fn
= gen_sibcall_internal
;
6921 fn
= gen_call_internal
;
6923 pattern
= fn (addr
, args_size
);
6925 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
6927 /* Handle return values created by mips_return_fpr_pair. */
6928 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
6931 if (type
== MIPS_CALL_SIBCALL
)
6932 fn
= gen_sibcall_value_multiple_internal
;
6934 fn
= gen_call_value_multiple_internal
;
6936 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
6937 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
6938 pattern
= fn (reg1
, addr
, args_size
, reg2
);
6942 rtx (*fn
) (rtx
, rtx
, rtx
);
6944 if (type
== MIPS_CALL_SIBCALL
)
6945 fn
= gen_sibcall_value_internal
;
6947 fn
= gen_call_value_internal
;
6949 /* Handle return values created by mips_return_fpr_single. */
6950 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
6951 result
= XEXP (XVECEXP (result
, 0, 0), 0);
6952 pattern
= fn (result
, addr
, args_size
);
6955 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
6958 /* Split call instruction INSN into a $gp-clobbering call and
6959 (where necessary) an instruction to restore $gp from its save slot.
6960 CALL_PATTERN is the pattern of the new call. */
6963 mips_split_call (rtx insn
, rtx call_pattern
)
6965 emit_call_insn (call_pattern
);
6966 if (!find_reg_note (insn
, REG_NORETURN
, 0))
6967 /* Pick a temporary register that is suitable for both MIPS16 and
6968 non-MIPS16 code. $4 and $5 are used for returning complex double
6969 values in soft-float code, so $6 is the first suitable candidate. */
6970 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 2));
6973 /* Return true if a call to DECL may need to use JALX. */
6976 mips_call_may_need_jalx_p (tree decl
)
6978 /* If the current translation unit would use a different mode for DECL,
6979 assume that the call needs JALX. */
6980 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
6983 /* mips_get_compress_mode is always accurate for locally-binding
6984 functions in the current translation unit. */
6985 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
6988 /* When -minterlink-compressed is in effect, assume that functions
6989 could use a different encoding mode unless an attribute explicitly
6990 tells us otherwise. */
6991 if (TARGET_INTERLINK_COMPRESSED
)
6993 if (!TARGET_COMPRESSION
6994 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
6996 if (TARGET_COMPRESSION
6997 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
7004 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7007 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7009 if (!TARGET_SIBCALLS
)
7012 /* Interrupt handlers need special epilogue code and therefore can't
7014 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7017 /* Direct Js are only possible to functions that use the same ISA encoding.
7018 There is no JX counterpoart of JALX. */
7020 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7021 && mips_call_may_need_jalx_p (decl
))
7024 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7025 require $gp to be valid on entry, so sibcalls can only use stubs
7026 if $gp is call-clobbered. */
7028 && TARGET_CALL_SAVED_GP
7029 && !TARGET_ABICALLS_PIC0
7030 && !targetm
.binds_local_p (decl
))
7037 /* Emit code to move general operand SRC into condition-code
7038 register DEST given that SCRATCH is a scratch TFmode FPR.
7045 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
7048 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
7052 /* Change the source to SFmode. */
7054 src
= adjust_address (src
, SFmode
, 0);
7055 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
7056 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
7058 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
7059 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
7061 mips_emit_move (copy_rtx (fp1
), src
);
7062 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
7063 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
7066 /* Implement MOVE_BY_PIECES_P. */
7069 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7073 /* movmemsi is meant to generate code that is at least as good as
7074 move_by_pieces. However, movmemsi effectively uses a by-pieces
7075 implementation both for moves smaller than a word and for
7076 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7077 bytes. We should allow the tree-level optimisers to do such
7078 moves by pieces, as it often exposes other optimization
7079 opportunities. We might as well continue to use movmemsi at
7080 the rtl level though, as it produces better code when
7081 scheduling is disabled (such as at -O). */
7082 if (currently_expanding_to_rtl
)
7084 if (align
< BITS_PER_WORD
)
7085 return size
< UNITS_PER_WORD
;
7086 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7088 /* The default value. If this becomes a target hook, we should
7089 call the default definition instead. */
7090 return (move_by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1)
7091 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7094 /* Implement STORE_BY_PIECES_P. */
7097 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7099 /* Storing by pieces involves moving constants into registers
7100 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7101 We need to decide whether it is cheaper to load the address of
7102 constant data into a register and use a block move instead. */
7104 /* If the data is only byte aligned, then:
7106 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7107 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7110 (a2) A block move of 4 bytes from aligned source data can use an
7111 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7112 4 SBs that we would generate when storing by pieces. */
7113 if (align
<= BITS_PER_UNIT
)
7116 /* If the data is 2-byte aligned, then:
7118 (b1) A block move of less than 4 bytes would use a combination of LBs,
7119 LHs, SBs and SHs. We get better code by using single-instruction
7120 LIs, SBs and SHs instead.
7122 (b2) A block move of 4 bytes from aligned source data would again use
7123 an LW/SWL/SWR sequence. In most cases, loading the address of
7124 the source data would require at least one extra instruction.
7125 It is often more efficient to use 2 single-instruction LIs and
7128 (b3) A block move of up to 3 additional bytes would be like (b1).
7130 (b4) A block move of 8 bytes from aligned source data can use two
7131 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7132 sequences are better than the 4 LIs and 4 SHs that we'd generate
7133 when storing by pieces.
7135 The reasoning for higher alignments is similar:
7137 (c1) A block move of less than 4 bytes would be the same as (b1).
7139 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7140 loading the address of the source data would typically require
7141 at least one extra instruction. It is generally better to use
7144 (c3) A block move of up to 3 additional bytes would be like (b1).
7146 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7147 LD/SD sequence, and in these cases we've traditionally preferred
7148 the memory copy over the more bulky constant moves. */
7152 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7153 Assume that the areas do not overlap. */
7156 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7158 HOST_WIDE_INT offset
, delta
;
7159 unsigned HOST_WIDE_INT bits
;
7161 enum machine_mode mode
;
7164 /* Work out how many bits to move at a time. If both operands have
7165 half-word alignment, it is usually better to move in half words.
7166 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7167 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7168 Otherwise move word-sized chunks. */
7169 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7170 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7171 bits
= BITS_PER_WORD
/ 2;
7173 bits
= BITS_PER_WORD
;
7175 mode
= mode_for_size (bits
, MODE_INT
, 0);
7176 delta
= bits
/ BITS_PER_UNIT
;
7178 /* Allocate a buffer for the temporary registers. */
7179 regs
= XALLOCAVEC (rtx
, length
/ delta
);
7181 /* Load as many BITS-sized chunks as possible. Use a normal load if
7182 the source has enough alignment, otherwise use left/right pairs. */
7183 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7185 regs
[i
] = gen_reg_rtx (mode
);
7186 if (MEM_ALIGN (src
) >= bits
)
7187 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
7190 rtx part
= adjust_address (src
, BLKmode
, offset
);
7191 set_mem_size (part
, delta
);
7192 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
7197 /* Copy the chunks to the destination. */
7198 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7199 if (MEM_ALIGN (dest
) >= bits
)
7200 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
7203 rtx part
= adjust_address (dest
, BLKmode
, offset
);
7204 set_mem_size (part
, delta
);
7205 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
7209 /* Mop up any left-over bytes. */
7210 if (offset
< length
)
7212 src
= adjust_address (src
, BLKmode
, offset
);
7213 dest
= adjust_address (dest
, BLKmode
, offset
);
7214 move_by_pieces (dest
, src
, length
- offset
,
7215 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
7219 /* Helper function for doing a loop-based block operation on memory
7220 reference MEM. Each iteration of the loop will operate on LENGTH
7223 Create a new base register for use within the loop and point it to
7224 the start of MEM. Create a new memory reference that uses this
7225 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7228 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
7229 rtx
*loop_reg
, rtx
*loop_mem
)
7231 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
7233 /* Although the new mem does not refer to a known location,
7234 it does keep up to LENGTH bytes of alignment. */
7235 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
7236 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
7239 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7240 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7241 the memory regions do not overlap. */
7244 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
7245 HOST_WIDE_INT bytes_per_iter
)
7247 rtx label
, src_reg
, dest_reg
, final_src
, test
;
7248 HOST_WIDE_INT leftover
;
7250 leftover
= length
% bytes_per_iter
;
7253 /* Create registers and memory references for use within the loop. */
7254 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
7255 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
7257 /* Calculate the value that SRC_REG should have after the last iteration
7259 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
7262 /* Emit the start of the loop. */
7263 label
= gen_label_rtx ();
7266 /* Emit the loop body. */
7267 mips_block_move_straight (dest
, src
, bytes_per_iter
);
7269 /* Move on to the next block. */
7270 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
7271 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
7273 /* Emit the loop condition. */
7274 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7275 if (Pmode
== DImode
)
7276 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7278 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7280 /* Mop up any left-over bytes. */
7282 mips_block_move_straight (dest
, src
, leftover
);
7285 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7286 memory reference SRC to memory reference DEST. */
7289 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7291 if (CONST_INT_P (length
))
7293 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7295 mips_block_move_straight (dest
, src
, INTVAL (length
));
7300 mips_block_move_loop (dest
, src
, INTVAL (length
),
7301 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7308 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7311 mips_expand_synci_loop (rtx begin
, rtx end
)
7313 rtx inc
, label
, end_label
, cmp_result
, mask
, length
;
7315 /* Create end_label. */
7316 end_label
= gen_label_rtx ();
7318 /* Check if begin equals end. */
7319 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7320 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7322 /* Load INC with the cache line size (rdhwr INC,$1). */
7323 inc
= gen_reg_rtx (Pmode
);
7324 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7326 /* Check if inc is 0. */
7327 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7328 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7330 /* Calculate mask. */
7331 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7333 /* Mask out begin by mask. */
7334 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7336 /* Calculate length. */
7337 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7339 /* Loop back to here. */
7340 label
= gen_label_rtx ();
7343 emit_insn (gen_synci (begin
));
7345 /* Update length. */
7346 mips_emit_binary (MINUS
, length
, length
, inc
);
7349 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7351 /* Check if length is greater than 0. */
7352 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7353 emit_jump_insn (gen_condjump (cmp_result
, label
));
7355 emit_label (end_label
);
7358 /* Expand a QI or HI mode atomic memory operation.
7360 GENERATOR contains a pointer to the gen_* function that generates
7361 the SI mode underlying atomic operation using masks that we
7364 RESULT is the return register for the operation. Its value is NULL
7367 MEM is the location of the atomic access.
7369 OLDVAL is the first operand for the operation.
7371 NEWVAL is the optional second operand for the operation. Its value
7372 is NULL if unused. */
7375 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7376 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7378 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7379 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7381 enum machine_mode mode
;
7383 mode
= GET_MODE (mem
);
7385 /* Compute the address of the containing SImode value. */
7386 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7387 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7388 force_reg (Pmode
, GEN_INT (-4)));
7390 /* Create a memory reference for it. */
7391 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7392 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7393 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7395 /* Work out the byte offset of the QImode or HImode value,
7396 counting from the least significant byte. */
7397 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7398 if (TARGET_BIG_ENDIAN
)
7399 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7401 /* Multiply by eight to convert the shift value from bytes to bits. */
7402 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7404 /* Make the final shift an SImode value, so that it can be used in
7405 SImode operations. */
7406 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7408 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7409 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7410 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7411 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7413 /* Compute the equivalent exclusive mask. */
7414 inverted_mask
= gen_reg_rtx (SImode
);
7415 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
7416 gen_rtx_NOT (SImode
, mask
)));
7418 /* Shift the old value into place. */
7419 if (oldval
!= const0_rtx
)
7421 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7422 oldval
= force_reg (SImode
, oldval
);
7423 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7426 /* Do the same for the new value. */
7427 if (newval
&& newval
!= const0_rtx
)
7429 newval
= convert_modes (SImode
, mode
, newval
, true);
7430 newval
= force_reg (SImode
, newval
);
7431 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7434 /* Do the SImode atomic access. */
7436 res
= gen_reg_rtx (SImode
);
7438 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7440 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7442 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7448 /* Shift and convert the result. */
7449 mips_emit_binary (AND
, res
, res
, mask
);
7450 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7451 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7455 /* Return true if it is possible to use left/right accesses for a
7456 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7457 When returning true, update *LEFT and *RIGHT as follows:
7459 *LEFT is a QImode reference to the first byte if big endian or
7460 the last byte if little endian. This address can be used in the
7461 left-side instructions (LWL, SWL, LDL, SDL).
7463 *RIGHT is a QImode reference to the opposite end of the field and
7464 can be used in the patterning right-side instruction. */
7467 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7468 rtx
*left
, rtx
*right
)
7472 /* Check that the size is valid. */
7473 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7476 /* We can only access byte-aligned values. Since we are always passed
7477 a reference to the first byte of the field, it is not necessary to
7478 do anything with BITPOS after this check. */
7479 if (bitpos
% BITS_PER_UNIT
!= 0)
7482 /* Reject aligned bitfields: we want to use a normal load or store
7483 instead of a left/right pair. */
7484 if (MEM_ALIGN (op
) >= width
)
7487 /* Get references to both ends of the field. */
7488 first
= adjust_address (op
, QImode
, 0);
7489 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7491 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7492 correspond to the MSB and RIGHT to the LSB. */
7493 if (TARGET_BIG_ENDIAN
)
7494 *left
= first
, *right
= last
;
7496 *left
= last
, *right
= first
;
7501 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7502 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7503 the operation is the equivalent of:
7505 (set DEST (*_extract SRC WIDTH BITPOS))
7507 Return true on success. */
7510 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7511 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7513 rtx left
, right
, temp
;
7514 rtx dest1
= NULL_RTX
;
7516 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7517 be a DImode, create a new temp and emit a zero extend at the end. */
7518 if (GET_MODE (dest
) == DImode
7520 && GET_MODE_BITSIZE (SImode
) == width
)
7523 dest
= gen_reg_rtx (SImode
);
7526 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
7529 temp
= gen_reg_rtx (GET_MODE (dest
));
7530 if (GET_MODE (dest
) == DImode
)
7532 emit_insn (gen_mov_ldl (temp
, src
, left
));
7533 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7537 emit_insn (gen_mov_lwl (temp
, src
, left
));
7538 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7541 /* If we were loading 32bits and the original register was DI then
7542 sign/zero extend into the orignal dest. */
7546 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7548 emit_insn (gen_extendsidi2 (dest1
, dest
));
7553 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7554 BITPOS and SRC are the operands passed to the expander; the operation
7555 is the equivalent of:
7557 (set (zero_extract DEST WIDTH BITPOS) SRC)
7559 Return true on success. */
7562 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7563 HOST_WIDE_INT bitpos
)
7566 enum machine_mode mode
;
7568 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
7571 mode
= mode_for_size (width
, MODE_INT
, 0);
7572 src
= gen_lowpart (mode
, src
);
7575 emit_insn (gen_mov_sdl (dest
, src
, left
));
7576 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7580 emit_insn (gen_mov_swl (dest
, src
, left
));
7581 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7586 /* Return true if X is a MEM with the same size as MODE. */
7589 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
7592 && MEM_SIZE_KNOWN_P (x
)
7593 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7596 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7597 source of an "ext" instruction or the destination of an "ins"
7598 instruction. OP must be a register operand and the following
7599 conditions must hold:
7601 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7602 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7603 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7605 Also reject lengths equal to a word as they are better handled
7606 by the move patterns. */
7609 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7611 if (!ISA_HAS_EXT_INS
7612 || !register_operand (op
, VOIDmode
)
7613 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7616 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7619 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7625 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7626 operation if MAXLEN is the maxium length of consecutive bits that
7627 can make up MASK. MODE is the mode of the operation. See
7628 mask_low_and_shift_len for the actual definition. */
7631 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7633 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7636 /* Return true iff OP1 and OP2 are valid operands together for the
7637 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7638 see the table in the comment before the pattern. */
7641 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7643 return (memory_operand (op1
, mode
)
7644 ? and_load_operand (op2
, mode
)
7645 : and_reg_operand (op2
, mode
));
7648 /* The canonical form of a mask-low-and-shift-left operation is
7649 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7650 cleared. Thus we need to shift MASK to the right before checking if it
7651 is a valid mask value. MODE is the mode of the operation. If true
7652 return the length of the mask, otherwise return -1. */
7655 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7657 HOST_WIDE_INT shval
;
7659 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7660 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7663 /* Return true if -msplit-addresses is selected and should be honored.
7665 -msplit-addresses is a half-way house between explicit relocations
7666 and the traditional assembler macros. It can split absolute 32-bit
7667 symbolic constants into a high/lo_sum pair but uses macros for other
7670 Like explicit relocation support for REL targets, it relies
7671 on GNU extensions in the assembler and the linker.
7673 Although this code should work for -O0, it has traditionally
7674 been treated as an optimization. */
7677 mips_split_addresses_p (void)
7679 return (TARGET_SPLIT_ADDRESSES
7683 && !ABI_HAS_64BIT_SYMBOLS
);
7686 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7689 mips_init_relocs (void)
7691 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7692 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7693 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
7694 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7695 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7697 if (TARGET_MIPS16_PCREL_LOADS
)
7698 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
7701 if (ABI_HAS_64BIT_SYMBOLS
)
7703 if (TARGET_EXPLICIT_RELOCS
)
7705 mips_split_p
[SYMBOL_64_HIGH
] = true;
7706 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7707 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7709 mips_split_p
[SYMBOL_64_MID
] = true;
7710 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7711 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7713 mips_split_p
[SYMBOL_64_LOW
] = true;
7714 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7715 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7717 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7718 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7723 if (TARGET_EXPLICIT_RELOCS
7724 || mips_split_addresses_p ()
7727 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7728 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7729 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7736 /* The high part is provided by a pseudo copy of $gp. */
7737 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7738 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7740 else if (TARGET_EXPLICIT_RELOCS
)
7741 /* Small data constants are kept whole until after reload,
7742 then lowered by mips_rewrite_small_data. */
7743 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7745 if (TARGET_EXPLICIT_RELOCS
)
7747 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7750 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7751 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7755 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7756 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7759 /* Expose the use of $28 as soon as possible. */
7760 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7764 /* The HIGH and LO_SUM are matched by special .md patterns. */
7765 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7767 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7768 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7769 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7771 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7772 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7773 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7778 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7780 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7781 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7783 /* Expose the use of $28 as soon as possible. */
7784 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7790 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7791 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7792 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7795 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7796 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7798 if (TARGET_MIPS16_PCREL_LOADS
)
7800 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
7801 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
7805 mips_split_p
[SYMBOL_DTPREL
] = true;
7806 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7807 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7809 mips_split_p
[SYMBOL_TPREL
] = true;
7810 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7811 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7814 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7815 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7818 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7819 in context CONTEXT. RELOCS is the array of relocations to use. */
7822 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7823 const char **relocs
)
7825 enum mips_symbol_type symbol_type
;
7828 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7829 gcc_assert (relocs
[symbol_type
]);
7831 fputs (relocs
[symbol_type
], file
);
7832 output_addr_const (file
, mips_strip_unspec_address (op
));
7833 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7838 /* Start a new block with the given asm switch enabled. If we need
7839 to print a directive, emit PREFIX before it and SUFFIX after it. */
7842 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7843 const char *prefix
, const char *suffix
)
7845 if (asm_switch
->nesting_level
== 0)
7846 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
7847 asm_switch
->nesting_level
++;
7850 /* Likewise, but end a block. */
7853 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7854 const char *prefix
, const char *suffix
)
7856 gcc_assert (asm_switch
->nesting_level
);
7857 asm_switch
->nesting_level
--;
7858 if (asm_switch
->nesting_level
== 0)
7859 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
7862 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7863 that either print a complete line or print nothing. */
7866 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
7868 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
7872 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
7874 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
7877 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7878 The punctuation characters are:
7880 '(' Start a nested ".set noreorder" block.
7881 ')' End a nested ".set noreorder" block.
7882 '[' Start a nested ".set noat" block.
7883 ']' End a nested ".set noat" block.
7884 '<' Start a nested ".set nomacro" block.
7885 '>' End a nested ".set nomacro" block.
7886 '*' Behave like %(%< if generating a delayed-branch sequence.
7887 '#' Print a nop if in a ".set noreorder" block.
7888 '/' Like '#', but do nothing within a delayed-branch sequence.
7889 '?' Print "l" if mips_branch_likely is true
7890 '~' Print a nop if mips_branch_likely is true
7891 '.' Print the name of the register with a hard-wired zero (zero or $0).
7892 '@' Print the name of the assembler temporary register (at or $1).
7893 '^' Print the name of the pic call-through register (t9 or $25).
7894 '+' Print the name of the gp register (usually gp or $28).
7895 '$' Print the name of the stack pointer register (sp or $29).
7896 ':' Print "c" to use the compact version if the delay slot is a nop.
7897 '!' Print "s" to use the short version if the delay slot contains a
7900 See also mips_init_print_operand_pucnt. */
7903 mips_print_operand_punctuation (FILE *file
, int ch
)
7908 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
7912 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
7916 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
7920 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
7924 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
7928 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
7932 if (final_sequence
!= 0)
7934 mips_print_operand_punctuation (file
, '(');
7935 mips_print_operand_punctuation (file
, '<');
7940 if (mips_noreorder
.nesting_level
> 0)
7941 fputs ("\n\tnop", file
);
7945 /* Print an extra newline so that the delayed insn is separated
7946 from the following ones. This looks neater and is consistent
7947 with non-nop delayed sequences. */
7948 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
7949 fputs ("\n\tnop\n", file
);
7953 if (mips_branch_likely
)
7958 if (mips_branch_likely
)
7959 fputs ("\n\tnop", file
);
7963 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
7967 fputs (reg_names
[AT_REGNUM
], file
);
7971 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
7975 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
7979 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
7983 /* When final_sequence is 0, the delay slot will be a nop. We can
7984 use the compact version for microMIPS. */
7985 if (final_sequence
== 0)
7990 /* If the delay slot instruction is short, then use the
7992 if (final_sequence
== 0
7993 || get_attr_length (XVECEXP (final_sequence
, 0, 1)) == 2)
8003 /* Initialize mips_print_operand_punct. */
8006 mips_init_print_operand_punct (void)
8010 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
8011 mips_print_operand_punct
[(unsigned char) *p
] = true;
8014 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8015 associated with condition CODE. Print the condition part of the
8019 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8033 /* Conveniently, the MIPS names for these conditions are the same
8034 as their RTL equivalents. */
8035 fputs (GET_RTX_NAME (code
), file
);
8039 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8044 /* Likewise floating-point branches. */
8047 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8052 fputs ("c1f", file
);
8056 fputs ("c1t", file
);
8060 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8065 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8068 mips_print_operand_punct_valid_p (unsigned char code
)
8070 return mips_print_operand_punct
[code
];
8073 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8075 'X' Print CONST_INT OP in hexadecimal format.
8076 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8077 'd' Print CONST_INT OP in decimal.
8078 'm' Print one less than CONST_INT OP in decimal.
8079 'h' Print the high-part relocation associated with OP, after stripping
8081 'R' Print the low-part relocation associated with OP.
8082 'C' Print the integer branch condition for comparison OP.
8083 'N' Print the inverse of the integer branch condition for comparison OP.
8084 'F' Print the FPU branch condition for comparison OP.
8085 'W' Print the inverse of the FPU branch condition for comparison OP.
8086 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8087 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8088 't' Like 'T', but with the EQ/NE cases reversed
8089 'Y' Print mips_fp_conditions[INTVAL (OP)]
8090 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8091 'q' Print a DSP accumulator register.
8092 'D' Print the second part of a double-word register or memory operand.
8093 'L' Print the low-order register in a double-word register operand.
8094 'M' Print high-order register in a double-word register operand.
8095 'z' Print $0 if OP is zero, otherwise print OP normally.
8096 'b' Print the address of a memory operand, without offset. */
8099 mips_print_operand (FILE *file
, rtx op
, int letter
)
8103 if (mips_print_operand_punct_valid_p (letter
))
8105 mips_print_operand_punctuation (file
, letter
);
8110 code
= GET_CODE (op
);
8115 if (CONST_INT_P (op
))
8116 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8118 output_operand_lossage ("invalid use of '%%%c'", letter
);
8122 if (CONST_INT_P (op
))
8123 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8125 output_operand_lossage ("invalid use of '%%%c'", letter
);
8129 if (CONST_INT_P (op
))
8130 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8132 output_operand_lossage ("invalid use of '%%%c'", letter
);
8136 if (CONST_INT_P (op
))
8137 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
8139 output_operand_lossage ("invalid use of '%%%c'", letter
);
8145 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
8149 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
8153 mips_print_int_branch_condition (file
, code
, letter
);
8157 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
8161 mips_print_float_branch_condition (file
, code
, letter
);
8165 mips_print_float_branch_condition (file
, reverse_condition (code
),
8172 int truth
= (code
== NE
) == (letter
== 'T');
8173 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
8178 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
8179 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
8181 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8188 mips_print_operand (file
, op
, 0);
8194 if (code
== REG
&& MD_REG_P (REGNO (op
)))
8195 fprintf (file
, "$ac0");
8196 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
8197 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
8199 output_operand_lossage ("invalid use of '%%%c'", letter
);
8207 unsigned int regno
= REGNO (op
);
8208 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
8209 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
8212 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
8213 output_operand_lossage ("invalid use of '%%%c'", letter
);
8214 /* We need to print $0 .. $31 for COP0 registers. */
8215 if (COP0_REG_P (regno
))
8216 fprintf (file
, "$%s", ®_names
[regno
][4]);
8218 fprintf (file
, "%s", reg_names
[regno
]);
8224 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
8225 else if (letter
== 'b')
8227 gcc_assert (REG_P (XEXP (op
, 0)));
8228 mips_print_operand (file
, XEXP (op
, 0), 0);
8230 else if (letter
&& letter
!= 'z')
8231 output_operand_lossage ("invalid use of '%%%c'", letter
);
8233 output_address (XEXP (op
, 0));
8237 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
8238 fputs (reg_names
[GP_REG_FIRST
], file
);
8239 else if (letter
&& letter
!= 'z')
8240 output_operand_lossage ("invalid use of '%%%c'", letter
);
8241 else if (CONST_GP_P (op
))
8242 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
8244 output_addr_const (file
, mips_strip_unspec_address (op
));
8250 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8253 mips_print_operand_address (FILE *file
, rtx x
)
8255 struct mips_address_info addr
;
8257 if (mips_classify_address (&addr
, x
, word_mode
, true))
8261 mips_print_operand (file
, addr
.offset
, 0);
8262 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8265 case ADDRESS_LO_SUM
:
8266 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8268 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8271 case ADDRESS_CONST_INT
:
8272 output_addr_const (file
, x
);
8273 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8276 case ADDRESS_SYMBOLIC
:
8277 output_addr_const (file
, mips_strip_unspec_address (x
));
8283 /* Implement TARGET_ENCODE_SECTION_INFO. */
8286 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8288 default_encode_section_info (decl
, rtl
, first
);
8290 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8292 rtx symbol
= XEXP (rtl
, 0);
8293 tree type
= TREE_TYPE (decl
);
8295 /* Encode whether the symbol is short or long. */
8296 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8297 || mips_far_type_p (type
))
8298 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8302 /* Implement TARGET_SELECT_RTX_SECTION. */
8305 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
8306 unsigned HOST_WIDE_INT align
)
8308 /* ??? Consider using mergeable small data sections. */
8309 if (mips_rtx_constant_in_small_data_p (mode
))
8310 return get_named_section (NULL
, ".sdata", 0);
8312 return default_elf_select_rtx_section (mode
, x
, align
);
8315 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8317 The complication here is that, with the combination TARGET_ABICALLS
8318 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8319 absolute addresses, and should therefore not be included in the
8320 read-only part of a DSO. Handle such cases by selecting a normal
8321 data section instead of a read-only one. The logic apes that in
8322 default_function_rodata_section. */
8325 mips_function_rodata_section (tree decl
)
8327 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8328 return default_function_rodata_section (decl
);
8330 if (decl
&& DECL_SECTION_NAME (decl
))
8332 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8333 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8335 char *rname
= ASTRDUP (name
);
8337 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8339 else if (flag_function_sections
8340 && flag_data_sections
8341 && strncmp (name
, ".text.", 6) == 0)
8343 char *rname
= ASTRDUP (name
);
8344 memcpy (rname
+ 1, "data", 4);
8345 return get_section (rname
, SECTION_WRITE
, decl
);
8348 return data_section
;
8351 /* Implement TARGET_IN_SMALL_DATA_P. */
8354 mips_in_small_data_p (const_tree decl
)
8356 unsigned HOST_WIDE_INT size
;
8358 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8361 /* We don't yet generate small-data references for -mabicalls
8362 or VxWorks RTP code. See the related -G handling in
8363 mips_option_override. */
8364 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8367 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8371 /* Reject anything that isn't in a known small-data section. */
8372 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8373 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8376 /* If a symbol is defined externally, the assembler will use the
8377 usual -G rules when deciding how to implement macros. */
8378 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8381 else if (TARGET_EMBEDDED_DATA
)
8383 /* Don't put constants into the small data section: we want them
8384 to be in ROM rather than RAM. */
8385 if (TREE_CODE (decl
) != VAR_DECL
)
8388 if (TREE_READONLY (decl
)
8389 && !TREE_SIDE_EFFECTS (decl
)
8390 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8394 /* Enforce -mlocal-sdata. */
8395 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8398 /* Enforce -mextern-sdata. */
8399 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8401 if (DECL_EXTERNAL (decl
))
8403 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8407 /* We have traditionally not treated zero-sized objects as small data,
8408 so this is now effectively part of the ABI. */
8409 size
= int_size_in_bytes (TREE_TYPE (decl
));
8410 return size
> 0 && size
<= mips_small_data_threshold
;
8413 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8414 anchors for small data: the GP register acts as an anchor in that
8415 case. We also don't want to use them for PC-relative accesses,
8416 where the PC acts as an anchor. */
8419 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8421 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8423 case SYMBOL_PC_RELATIVE
:
8424 case SYMBOL_GP_RELATIVE
:
8428 return default_use_anchors_for_symbol_p (symbol
);
8432 /* The MIPS debug format wants all automatic variables and arguments
8433 to be in terms of the virtual frame pointer (stack pointer before
8434 any adjustment in the function), while the MIPS 3.0 linker wants
8435 the frame pointer to be the stack pointer after the initial
8436 adjustment. So, we do the adjustment here. The arg pointer (which
8437 is eliminated) points to the virtual frame pointer, while the frame
8438 pointer (which may be eliminated) points to the stack pointer after
8439 the initial adjustments. */
8442 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8444 rtx offset2
= const0_rtx
;
8445 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8448 offset
= INTVAL (offset2
);
8450 if (reg
== stack_pointer_rtx
8451 || reg
== frame_pointer_rtx
8452 || reg
== hard_frame_pointer_rtx
)
8454 offset
-= cfun
->machine
->frame
.total_size
;
8455 if (reg
== hard_frame_pointer_rtx
)
8456 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8462 /* Implement ASM_OUTPUT_EXTERNAL. */
8465 mips_output_external (FILE *file
, tree decl
, const char *name
)
8467 default_elf_asm_output_external (file
, decl
, name
);
8469 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8470 set in order to avoid putting out names that are never really
8472 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8474 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8476 /* When using assembler macros, emit .extern directives for
8477 all small-data externs so that the assembler knows how
8480 In most cases it would be safe (though pointless) to emit
8481 .externs for other symbols too. One exception is when an
8482 object is within the -G limit but declared by the user to
8483 be in a section other than .sbss or .sdata. */
8484 fputs ("\t.extern\t", file
);
8485 assemble_name (file
, name
);
8486 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8487 int_size_in_bytes (TREE_TYPE (decl
)));
8492 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8495 mips_output_filename (FILE *stream
, const char *name
)
8497 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8499 if (write_symbols
== DWARF2_DEBUG
)
8501 else if (mips_output_filename_first_time
)
8503 mips_output_filename_first_time
= 0;
8504 num_source_filenames
+= 1;
8505 current_function_file
= name
;
8506 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8507 output_quoted_string (stream
, name
);
8508 putc ('\n', stream
);
8510 /* If we are emitting stabs, let dbxout.c handle this (except for
8511 the mips_output_filename_first_time case). */
8512 else if (write_symbols
== DBX_DEBUG
)
8514 else if (name
!= current_function_file
8515 && strcmp (name
, current_function_file
) != 0)
8517 num_source_filenames
+= 1;
8518 current_function_file
= name
;
8519 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8520 output_quoted_string (stream
, name
);
8521 putc ('\n', stream
);
8525 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8527 static void ATTRIBUTE_UNUSED
8528 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8533 fputs ("\t.dtprelword\t", file
);
8537 fputs ("\t.dtpreldword\t", file
);
8543 output_addr_const (file
, x
);
8544 fputs ("+0x8000", file
);
8547 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8550 mips_dwarf_register_span (rtx reg
)
8553 enum machine_mode mode
;
8555 /* By default, GCC maps increasing register numbers to increasing
8556 memory locations, but paired FPRs are always little-endian,
8557 regardless of the prevailing endianness. */
8558 mode
= GET_MODE (reg
);
8559 if (FP_REG_P (REGNO (reg
))
8560 && TARGET_BIG_ENDIAN
8561 && MAX_FPRS_PER_FMT
> 1
8562 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8564 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8565 high
= mips_subword (reg
, true);
8566 low
= mips_subword (reg
, false);
8567 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8573 /* DSP ALU can bypass data with no delays for the following pairs. */
8574 enum insn_code dspalu_bypass_table
[][2] =
8576 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
8577 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
8578 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
8579 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
8580 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
8581 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
8582 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
8583 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
8587 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
8590 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
8591 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
8592 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
8594 for (i
= 0; i
< num_bypass
; i
++)
8596 if (out_icode
== dspalu_bypass_table
[i
][0]
8597 && in_icode
== dspalu_bypass_table
[i
][1])
8603 /* Implement ASM_OUTPUT_ASCII. */
8606 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8612 fprintf (stream
, "\t.ascii\t\"");
8613 for (i
= 0; i
< len
; i
++)
8617 c
= (unsigned char) string
[i
];
8620 if (c
== '\\' || c
== '\"')
8622 putc ('\\', stream
);
8630 fprintf (stream
, "\\%03o", c
);
8634 if (cur_pos
> 72 && i
+1 < len
)
8637 fprintf (stream
, "\"\n\t.ascii\t\"");
8640 fprintf (stream
, "\"\n");
8643 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8644 Update *ADDR with the operand that should be printed. */
8647 mips_output_tls_reloc_directive (rtx
*addr
)
8649 enum mips_symbol_type type
;
8651 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
8652 *addr
= mips_strip_unspec_address (*addr
);
8656 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
8659 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
8666 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8667 macros, mark the symbol as written so that mips_asm_output_external
8668 won't emit an .extern for it. STREAM is the output file, NAME is the
8669 name of the symbol, INIT_STRING is the string that should be written
8670 before the symbol and FINAL_STRING is the string that should be
8671 written after it. FINAL_STRING is a printf format that consumes the
8672 remaining arguments. */
8675 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
8676 const char *final_string
, ...)
8680 fputs (init_string
, stream
);
8681 assemble_name (stream
, name
);
8682 va_start (ap
, final_string
);
8683 vfprintf (stream
, final_string
, ap
);
8686 if (!TARGET_EXPLICIT_RELOCS
)
8688 tree name_tree
= get_identifier (name
);
8689 TREE_ASM_WRITTEN (name_tree
) = 1;
8693 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8694 NAME is the name of the object and ALIGN is the required alignment
8695 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8696 alignment argument. */
8699 mips_declare_common_object (FILE *stream
, const char *name
,
8700 const char *init_string
,
8701 unsigned HOST_WIDE_INT size
,
8702 unsigned int align
, bool takes_alignment_p
)
8704 if (!takes_alignment_p
)
8706 size
+= (align
/ BITS_PER_UNIT
) - 1;
8707 size
-= size
% (align
/ BITS_PER_UNIT
);
8708 mips_declare_object (stream
, name
, init_string
,
8709 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8712 mips_declare_object (stream
, name
, init_string
,
8713 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
8714 size
, align
/ BITS_PER_UNIT
);
8717 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8718 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8721 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8722 unsigned HOST_WIDE_INT size
,
8725 /* If the target wants uninitialized const declarations in
8726 .rdata then don't put them in .comm. */
8727 if (TARGET_EMBEDDED_DATA
8728 && TARGET_UNINIT_CONST_IN_RODATA
8729 && TREE_CODE (decl
) == VAR_DECL
8730 && TREE_READONLY (decl
)
8731 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8733 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8734 targetm
.asm_out
.globalize_label (stream
, name
);
8736 switch_to_section (readonly_data_section
);
8737 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8738 mips_declare_object (stream
, name
, "",
8739 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8743 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8747 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8748 extern int size_directive_output
;
8750 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8751 definitions except that it uses mips_declare_object to emit the label. */
8754 mips_declare_object_name (FILE *stream
, const char *name
,
8755 tree decl ATTRIBUTE_UNUSED
)
8757 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8758 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8761 size_directive_output
= 0;
8762 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8766 size_directive_output
= 1;
8767 size
= int_size_in_bytes (TREE_TYPE (decl
));
8768 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8771 mips_declare_object (stream
, name
, "", ":\n");
8774 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8777 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8781 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8782 if (!flag_inhibit_size_directive
8783 && DECL_SIZE (decl
) != 0
8786 && DECL_INITIAL (decl
) == error_mark_node
8787 && !size_directive_output
)
8791 size_directive_output
= 1;
8792 size
= int_size_in_bytes (TREE_TYPE (decl
));
8793 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8798 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8799 with the current ABI. */
8802 mips_mdebug_abi_name (void)
8815 return TARGET_64BIT
? "eabi64" : "eabi32";
8821 /* Implement TARGET_ASM_FILE_START. */
8824 mips_file_start (void)
8826 default_file_start ();
8828 /* Generate a special section to describe the ABI switches used to
8829 produce the resultant binary. */
8831 /* Record the ABI itself. Modern versions of binutils encode
8832 this information in the ELF header flags, but GDB needs the
8833 information in order to correctly debug binaries produced by
8834 older binutils. See the function mips_gdbarch_init in
8836 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8837 mips_mdebug_abi_name ());
8839 /* There is no ELF header flag to distinguish long32 forms of the
8840 EABI from long64 forms. Emit a special section to help tools
8841 such as GDB. Do the same for o64, which is sometimes used with
8843 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
8844 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
8845 "\t.previous\n", TARGET_LONG64
? 64 : 32);
8847 /* Record the NaN encoding. */
8848 if (HAVE_AS_NAN
|| mips_nan
!= MIPS_IEEE_754_DEFAULT
)
8849 fprintf (asm_out_file
, "\t.nan\t%s\n",
8850 mips_nan
== MIPS_IEEE_754_2008
? "2008" : "legacy");
8852 #ifdef HAVE_AS_GNU_ATTRIBUTE
8856 /* No floating-point operations, -mno-float. */
8857 if (TARGET_NO_FLOAT
)
8859 /* Soft-float code, -msoft-float. */
8860 else if (!TARGET_HARD_FLOAT_ABI
)
8862 /* Single-float code, -msingle-float. */
8863 else if (!TARGET_DOUBLE_FLOAT
)
8865 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8866 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
8868 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8872 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
8876 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8877 if (TARGET_ABICALLS
)
8879 fprintf (asm_out_file
, "\t.abicalls\n");
8880 if (TARGET_ABICALLS_PIC0
)
8881 fprintf (asm_out_file
, "\t.option\tpic0\n");
8884 if (flag_verbose_asm
)
8885 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8887 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
8890 /* Implement TARGET_ASM_CODE_END. */
8893 mips_code_end (void)
8895 if (mips_need_mips16_rdhwr_p
)
8896 mips_output_mips16_rdhwr ();
8899 /* Make the last instruction frame-related and note that it performs
8900 the operation described by FRAME_PATTERN. */
8903 mips_set_frame_expr (rtx frame_pattern
)
8907 insn
= get_last_insn ();
8908 RTX_FRAME_RELATED_P (insn
) = 1;
8909 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8914 /* Return a frame-related rtx that stores REG at MEM.
8915 REG must be a single register. */
8918 mips_frame_set (rtx mem
, rtx reg
)
8922 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
8923 RTX_FRAME_RELATED_P (set
) = 1;
8928 /* Record that the epilogue has restored call-saved register REG. */
8931 mips_add_cfa_restore (rtx reg
)
8933 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
8934 mips_epilogue
.cfa_restores
);
8937 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8938 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8939 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8940 static const unsigned char mips16e_s2_s8_regs
[] = {
8941 30, 23, 22, 21, 20, 19, 18
8943 static const unsigned char mips16e_a0_a3_regs
[] = {
8947 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8948 ordered from the uppermost in memory to the lowest in memory. */
8949 static const unsigned char mips16e_save_restore_regs
[] = {
8950 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8953 /* Return the index of the lowest X in the range [0, SIZE) for which
8954 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8957 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
8962 for (i
= 0; i
< size
; i
++)
8963 if (BITSET_P (mask
, regs
[i
]))
8969 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8970 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8971 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8972 is true for all indexes (X, SIZE). */
8975 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
8976 unsigned int size
, unsigned int *num_regs_ptr
)
8980 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
8981 for (i
++; i
< size
; i
++)
8982 if (!BITSET_P (*mask_ptr
, regs
[i
]))
8985 *mask_ptr
|= 1 << regs
[i
];
8989 /* Return a simplified form of X using the register values in REG_VALUES.
8990 REG_VALUES[R] is the last value assigned to hard register R, or null
8991 if R has not been modified.
8993 This function is rather limited, but is good enough for our purposes. */
8996 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
8998 x
= avoid_constant_pool_reference (x
);
9002 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9003 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
9004 x0
, GET_MODE (XEXP (x
, 0)));
9007 if (ARITHMETIC_P (x
))
9009 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9010 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
9011 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
9015 && reg_values
[REGNO (x
)]
9016 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
9017 return reg_values
[REGNO (x
)];
9022 /* Return true if (set DEST SRC) stores an argument register into its
9023 caller-allocated save slot, storing the number of that argument
9024 register in *REGNO_PTR if so. REG_VALUES is as for
9025 mips16e_collect_propagate_value. */
9028 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
9029 unsigned int *regno_ptr
)
9031 unsigned int argno
, regno
;
9032 HOST_WIDE_INT offset
, required_offset
;
9035 /* Check that this is a word-mode store. */
9036 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
9039 /* Check that the register being saved is an unmodified argument
9041 regno
= REGNO (src
);
9042 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
9044 argno
= regno
- GP_ARG_FIRST
;
9046 /* Check whether the address is an appropriate stack-pointer or
9047 frame-pointer access. */
9048 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
9049 mips_split_plus (addr
, &base
, &offset
);
9050 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
9051 if (base
== hard_frame_pointer_rtx
)
9052 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9053 else if (base
!= stack_pointer_rtx
)
9055 if (offset
!= required_offset
)
9062 /* A subroutine of mips_expand_prologue, called only when generating
9063 MIPS16e SAVE instructions. Search the start of the function for any
9064 instructions that save argument registers into their caller-allocated
9065 save slots. Delete such instructions and return a value N such that
9066 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9067 instructions redundant. */
9070 mips16e_collect_argument_saves (void)
9072 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
9073 rtx insn
, next
, set
, dest
, src
;
9074 unsigned int nargs
, regno
;
9076 push_topmost_sequence ();
9078 memset (reg_values
, 0, sizeof (reg_values
));
9079 for (insn
= get_insns (); insn
; insn
= next
)
9081 next
= NEXT_INSN (insn
);
9082 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
9088 set
= PATTERN (insn
);
9089 if (GET_CODE (set
) != SET
)
9092 dest
= SET_DEST (set
);
9093 src
= SET_SRC (set
);
9094 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
9096 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
9099 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
9102 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
9103 reg_values
[REGNO (dest
)]
9104 = mips16e_collect_propagate_value (src
, reg_values
);
9108 pop_topmost_sequence ();
9113 /* Return a move between register REGNO and memory location SP + OFFSET.
9114 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9115 Make the move a load if RESTORE_P, otherwise make it a store. */
9118 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
9119 HOST_WIDE_INT offset
, unsigned int regno
)
9123 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
9125 reg
= gen_rtx_REG (SImode
, regno
);
9128 mips_add_cfa_restore (reg
);
9129 return gen_rtx_SET (VOIDmode
, reg
, mem
);
9132 return gen_rtx_SET (VOIDmode
, mem
, reg
);
9133 return mips_frame_set (mem
, reg
);
9136 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9137 The instruction must:
9139 - Allocate or deallocate SIZE bytes in total; SIZE is known
9142 - Save or restore as many registers in *MASK_PTR as possible.
9143 The instruction saves the first registers at the top of the
9144 allocated area, with the other registers below it.
9146 - Save NARGS argument registers above the allocated area.
9148 (NARGS is always zero if RESTORE_P.)
9150 The SAVE and RESTORE instructions cannot save and restore all general
9151 registers, so there may be some registers left over for the caller to
9152 handle. Destructively modify *MASK_PTR so that it contains the registers
9153 that still need to be saved or restored. The caller can save these
9154 registers in the memory immediately below *OFFSET_PTR, which is a
9155 byte offset from the bottom of the allocated stack area. */
9158 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
9159 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
9163 HOST_WIDE_INT offset
, top_offset
;
9164 unsigned int i
, regno
;
9167 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
9169 /* Calculate the number of elements in the PARALLEL. We need one element
9170 for the stack adjustment, one for each argument register save, and one
9171 for each additional register move. */
9173 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9174 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
9177 /* Create the final PARALLEL. */
9178 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
9181 /* Add the stack pointer adjustment. */
9182 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9183 plus_constant (Pmode
, stack_pointer_rtx
,
9184 restore_p
? size
: -size
));
9185 RTX_FRAME_RELATED_P (set
) = 1;
9186 XVECEXP (pattern
, 0, n
++) = set
;
9188 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9189 top_offset
= restore_p
? size
: 0;
9191 /* Save the arguments. */
9192 for (i
= 0; i
< nargs
; i
++)
9194 offset
= top_offset
+ i
* UNITS_PER_WORD
;
9195 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
9197 XVECEXP (pattern
, 0, n
++) = set
;
9200 /* Then fill in the other register moves. */
9201 offset
= top_offset
;
9202 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9204 regno
= mips16e_save_restore_regs
[i
];
9205 if (BITSET_P (*mask_ptr
, regno
))
9207 offset
-= UNITS_PER_WORD
;
9208 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
9209 XVECEXP (pattern
, 0, n
++) = set
;
9210 *mask_ptr
&= ~(1 << regno
);
9214 /* Tell the caller what offset it should use for the remaining registers. */
9215 *offset_ptr
= size
+ (offset
- top_offset
);
9217 gcc_assert (n
== XVECLEN (pattern
, 0));
9222 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9223 pointer. Return true if PATTERN matches the kind of instruction
9224 generated by mips16e_build_save_restore. If INFO is nonnull,
9225 initialize it when returning true. */
9228 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
9229 struct mips16e_save_restore_info
*info
)
9231 unsigned int i
, nargs
, mask
, extra
;
9232 HOST_WIDE_INT top_offset
, save_offset
, offset
;
9233 rtx set
, reg
, mem
, base
;
9236 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
9239 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9240 top_offset
= adjust
> 0 ? adjust
: 0;
9242 /* Interpret all other members of the PARALLEL. */
9243 save_offset
= top_offset
- UNITS_PER_WORD
;
9247 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
9249 /* Check that we have a SET. */
9250 set
= XVECEXP (pattern
, 0, n
);
9251 if (GET_CODE (set
) != SET
)
9254 /* Check that the SET is a load (if restoring) or a store
9256 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
9260 /* Check that the address is the sum of the stack pointer and a
9261 possibly-zero constant offset. */
9262 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
9263 if (base
!= stack_pointer_rtx
)
9266 /* Check that SET's other operand is a register. */
9267 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
9271 /* Check for argument saves. */
9272 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
9273 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
9275 else if (offset
== save_offset
)
9277 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
9278 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
9281 mask
|= 1 << REGNO (reg
);
9282 save_offset
-= UNITS_PER_WORD
;
9288 /* Check that the restrictions on register ranges are met. */
9290 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
9291 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
9292 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
9293 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
9297 /* Make sure that the topmost argument register is not saved twice.
9298 The checks above ensure that the same is then true for the other
9299 argument registers. */
9300 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9303 /* Pass back information, if requested. */
9306 info
->nargs
= nargs
;
9308 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9314 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9315 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9316 the null terminator. */
9319 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9320 unsigned int max_reg
)
9322 if (min_reg
!= max_reg
)
9323 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9325 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9329 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9330 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9333 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9335 static char buffer
[300];
9337 struct mips16e_save_restore_info info
;
9338 unsigned int i
, end
;
9341 /* Parse the pattern. */
9342 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9345 /* Add the mnemonic. */
9346 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9349 /* Save the arguments. */
9351 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9352 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9353 else if (info
.nargs
== 1)
9354 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9356 /* Emit the amount of stack space to allocate or deallocate. */
9357 s
+= sprintf (s
, "%d", (int) info
.size
);
9359 /* Save or restore $16. */
9360 if (BITSET_P (info
.mask
, 16))
9361 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9363 /* Save or restore $17. */
9364 if (BITSET_P (info
.mask
, 17))
9365 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9367 /* Save or restore registers in the range $s2...$s8, which
9368 mips16e_s2_s8_regs lists in decreasing order. Note that this
9369 is a software register range; the hardware registers are not
9370 numbered consecutively. */
9371 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9372 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9374 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9375 mips16e_s2_s8_regs
[i
]);
9377 /* Save or restore registers in the range $a0...$a3. */
9378 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9379 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9381 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9382 mips16e_a0_a3_regs
[end
- 1]);
9384 /* Save or restore $31. */
9385 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9386 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9391 /* Return true if the current function returns its value in a floating-point
9392 register in MIPS16 mode. */
9395 mips16_cfun_returns_in_fpr_p (void)
9397 tree return_type
= DECL_RESULT (current_function_decl
);
9398 return (TARGET_MIPS16
9399 && TARGET_HARD_FLOAT_ABI
9400 && !aggregate_value_p (return_type
, current_function_decl
)
9401 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9404 /* Return true if predicate PRED is true for at least one instruction.
9405 Cache the result in *CACHE, and assume that the result is true
9406 if *CACHE is already true. */
9409 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx
))
9415 push_topmost_sequence ();
9416 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9417 if (USEFUL_INSN_P (insn
) && pred (insn
))
9422 pop_topmost_sequence ();
9427 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9428 See mips_cfun_has_inflexible_gp_ref_p for details. */
9431 mips_insn_has_inflexible_gp_ref_p (rtx insn
)
9433 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9434 indicate that the target could be a traditional MIPS
9435 lazily-binding stub. */
9436 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9439 /* Return true if the current function refers to the global pointer
9440 in a way that forces $28 to be valid. This means that we can't
9441 change the choice of global pointer, even for NewABI code.
9443 One example of this (and one which needs several checks) is that
9444 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9445 (This restriction does not apply to PLTs.) */
9448 mips_cfun_has_inflexible_gp_ref_p (void)
9450 /* If the function has a nonlocal goto, $28 must hold the correct
9451 global pointer for the target function. That is, the target
9452 of the goto implicitly uses $28. */
9453 if (crtl
->has_nonlocal_goto
)
9456 if (TARGET_ABICALLS_PIC2
)
9458 /* Symbolic accesses implicitly use the global pointer unless
9459 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9460 might go to traditional MIPS lazy-binding stubs. */
9461 if (!TARGET_EXPLICIT_RELOCS
)
9464 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9465 can be lazily-bound. */
9469 /* MIPS16 functions that return in FPRs need to call an
9470 external libgcc routine. This call is only made explict
9471 during mips_expand_epilogue, and it too might be lazily bound. */
9472 if (mips16_cfun_returns_in_fpr_p ())
9476 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9477 mips_insn_has_inflexible_gp_ref_p
);
9480 /* Return true if INSN refers to the global pointer in a "flexible" way.
9481 See mips_cfun_has_flexible_gp_ref_p for details. */
9484 mips_insn_has_flexible_gp_ref_p (rtx insn
)
9486 return (get_attr_got (insn
) != GOT_UNSET
9487 || mips_small_data_pattern_p (PATTERN (insn
))
9488 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9491 /* Return true if the current function references the global pointer,
9492 but if those references do not inherently require the global pointer
9493 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9496 mips_cfun_has_flexible_gp_ref_p (void)
9498 /* Reload can sometimes introduce constant pool references
9499 into a function that otherwise didn't need them. For example,
9500 suppose we have an instruction like:
9502 (set (reg:DF R1) (float:DF (reg:SI R2)))
9504 If R2 turns out to be a constant such as 1, the instruction may
9505 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9506 the option of using this constant if R2 doesn't get allocated
9509 In cases like these, reload will have added the constant to the
9510 pool but no instruction will yet refer to it. */
9511 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9514 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9515 mips_insn_has_flexible_gp_ref_p
);
9518 /* Return the register that should be used as the global pointer
9519 within this function. Return INVALID_REGNUM if the function
9520 doesn't need a global pointer. */
9523 mips_global_pointer (void)
9527 /* $gp is always available unless we're using a GOT. */
9528 if (!TARGET_USE_GOT
)
9529 return GLOBAL_POINTER_REGNUM
;
9531 /* If there are inflexible references to $gp, we must use the
9532 standard register. */
9533 if (mips_cfun_has_inflexible_gp_ref_p ())
9534 return GLOBAL_POINTER_REGNUM
;
9536 /* If there are no current references to $gp, then the only uses
9537 we can introduce later are those involved in long branches. */
9538 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9539 return INVALID_REGNUM
;
9541 /* If the global pointer is call-saved, try to use a call-clobbered
9543 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9544 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9545 if (!df_regs_ever_live_p (regno
)
9546 && call_really_used_regs
[regno
]
9547 && !fixed_regs
[regno
]
9548 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9551 return GLOBAL_POINTER_REGNUM
;
9554 /* Return true if the current function's prologue must load the global
9555 pointer value into pic_offset_table_rtx and store the same value in
9556 the function's cprestore slot (if any).
9558 One problem we have to deal with is that, when emitting GOT-based
9559 position independent code, long-branch sequences will need to load
9560 the address of the branch target from the GOT. We don't know until
9561 the very end of compilation whether (and where) the function needs
9562 long branches, so we must ensure that _any_ branch can access the
9563 global pointer in some form. However, we do not want to pessimize
9564 the usual case in which all branches are short.
9566 We handle this as follows:
9568 (1) During reload, we set cfun->machine->global_pointer to
9569 INVALID_REGNUM if we _know_ that the current function
9570 doesn't need a global pointer. This is only valid if
9571 long branches don't need the GOT.
9573 Otherwise, we assume that we might need a global pointer
9574 and pick an appropriate register.
9576 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9577 we ensure that the global pointer is available at every
9578 block boundary bar entry and exit. We do this in one of two ways:
9580 - If the function has a cprestore slot, we ensure that this
9581 slot is valid at every branch. However, as explained in
9582 point (6) below, there is no guarantee that pic_offset_table_rtx
9583 itself is valid if new uses of the global pointer are introduced
9584 after the first post-epilogue split.
9586 We guarantee that the cprestore slot is valid by loading it
9587 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9588 this register live at every block boundary bar function entry
9589 and exit. It is then invalid to move the load (and thus the
9590 preceding store) across a block boundary.
9592 - If the function has no cprestore slot, we guarantee that
9593 pic_offset_table_rtx itself is valid at every branch.
9595 See mips_eh_uses for the handling of the register liveness.
9597 (3) During prologue and epilogue generation, we emit "ghost"
9598 placeholder instructions to manipulate the global pointer.
9600 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9601 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9602 that the function needs a global pointer. (There is no need to set
9603 them earlier than this, and doing it as late as possible leads to
9604 fewer false positives.)
9606 (5) If cfun->machine->must_initialize_gp_p is true during a
9607 split_insns pass, we split the ghost instructions into real
9608 instructions. These split instructions can then be optimized in
9609 the usual way. Otherwise, we keep the ghost instructions intact,
9610 and optimize for the case where they aren't needed. We still
9611 have the option of splitting them later, if we need to introduce
9612 new uses of the global pointer.
9614 For example, the scheduler ignores a ghost instruction that
9615 stores $28 to the stack, but it handles the split form of
9616 the ghost instruction as an ordinary store.
9618 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9619 is true during the first post-epilogue split_insns pass, we split
9620 calls and restore_gp patterns into instructions that explicitly
9621 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9622 we split these patterns into instructions that _don't_ load from
9625 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9626 time of the split, then any instructions that exist at that time
9627 can make free use of pic_offset_table_rtx. However, if we want
9628 to introduce new uses of the global pointer after the split,
9629 we must explicitly load the value from the cprestore slot, since
9630 pic_offset_table_rtx itself might not be valid at a given point
9633 The idea is that we want to be able to delete redundant
9634 loads from the cprestore slot in the usual case where no
9635 long branches are needed.
9637 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9638 of md_reorg, we decide whether the global pointer is needed for
9639 long branches. If so, we set cfun->machine->must_initialize_gp_p
9640 to true and split the ghost instructions into real instructions
9643 Note that the ghost instructions must have a zero length for three reasons:
9645 - Giving the length of the underlying $gp sequence might cause
9646 us to use long branches in cases where they aren't really needed.
9648 - They would perturb things like alignment calculations.
9650 - More importantly, the hazard detection in md_reorg relies on
9651 empty instructions having a zero length.
9653 If we find a long branch and split the ghost instructions at the
9654 end of md_reorg, the split could introduce more long branches.
9655 That isn't a problem though, because we still do the split before
9656 the final shorten_branches pass.
9658 This is extremely ugly, but it seems like the best compromise between
9659 correctness and efficiency. */
9662 mips_must_initialize_gp_p (void)
9664 return cfun
->machine
->must_initialize_gp_p
;
9667 /* Return true if REGNO is a register that is ordinarily call-clobbered
9668 but must nevertheless be preserved by an interrupt handler. */
9671 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
9673 if (MD_REG_P (regno
))
9676 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
9679 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
9681 /* $0 is hard-wired. */
9682 if (regno
== GP_REG_FIRST
)
9685 /* The interrupt handler can treat kernel registers as
9686 scratch registers. */
9687 if (KERNEL_REG_P (regno
))
9690 /* The function will return the stack pointer to its original value
9692 if (regno
== STACK_POINTER_REGNUM
)
9695 /* Otherwise, return true for registers that aren't ordinarily
9697 return call_really_used_regs
[regno
];
9703 /* Return true if the current function should treat register REGNO
9707 mips_cfun_call_saved_reg_p (unsigned int regno
)
9709 /* If the user makes an ordinarily-call-saved register global,
9710 that register is no longer call-saved. */
9711 if (global_regs
[regno
])
9714 /* Interrupt handlers need to save extra registers. */
9715 if (cfun
->machine
->interrupt_handler_p
9716 && mips_interrupt_extra_call_saved_reg_p (regno
))
9719 /* call_insns preserve $28 unless they explicitly say otherwise,
9720 so call_really_used_regs[] treats $28 as call-saved. However,
9721 we want the ABI property rather than the default call_insn
9723 return (regno
== GLOBAL_POINTER_REGNUM
9724 ? TARGET_CALL_SAVED_GP
9725 : !call_really_used_regs
[regno
]);
9728 /* Return true if the function body might clobber register REGNO.
9729 We know that REGNO is call-saved. */
9732 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
9734 /* Some functions should be treated as clobbering all call-saved
9736 if (crtl
->saves_all_registers
)
9739 /* DF handles cases where a register is explicitly referenced in
9740 the rtl. Incoming values are passed in call-clobbered registers,
9741 so we can assume that any live call-saved register is set within
9743 if (df_regs_ever_live_p (regno
))
9746 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9747 These clobbers are not explicit in the rtl. */
9748 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9751 /* If we're using a call-saved global pointer, the function's
9752 prologue will need to set it up. */
9753 if (cfun
->machine
->global_pointer
== regno
)
9756 /* The function's prologue will need to set the frame pointer if
9757 frame_pointer_needed. */
9758 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9761 /* If a MIPS16 function returns a value in FPRs, its epilogue
9762 will need to call an external libgcc routine. This yet-to-be
9763 generated call_insn will clobber $31. */
9764 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9767 /* If REGNO is ordinarily call-clobbered, we must assume that any
9768 called function could modify it. */
9769 if (cfun
->machine
->interrupt_handler_p
9771 && mips_interrupt_extra_call_saved_reg_p (regno
))
9777 /* Return true if the current function must save register REGNO. */
9780 mips_save_reg_p (unsigned int regno
)
9782 if (mips_cfun_call_saved_reg_p (regno
))
9784 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9787 /* Save both registers in an FPR pair if either one is used. This is
9788 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9789 register to be used without the even register. */
9790 if (FP_REG_P (regno
)
9791 && MAX_FPRS_PER_FMT
== 2
9792 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9796 /* We need to save the incoming return address if __builtin_eh_return
9797 is being used to set a different return address. */
9798 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9804 /* Populate the current function's mips_frame_info structure.
9806 MIPS stack frames look like:
9808 +-------------------------------+
9810 | incoming stack arguments |
9812 +-------------------------------+
9814 | caller-allocated save area |
9815 A | for register arguments |
9817 +-------------------------------+ <-- incoming stack pointer
9819 | callee-allocated save area |
9820 B | for arguments that are |
9821 | split between registers and |
9824 +-------------------------------+ <-- arg_pointer_rtx
9826 C | callee-allocated save area |
9827 | for register varargs |
9829 +-------------------------------+ <-- frame_pointer_rtx
9830 | | + cop0_sp_offset
9831 | COP0 reg save area | + UNITS_PER_WORD
9833 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9834 | | + UNITS_PER_WORD
9835 | accumulator save area |
9837 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9838 | | + UNITS_PER_HWFPVALUE
9841 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9842 | | + UNITS_PER_WORD
9845 +-------------------------------+ <-- frame_pointer_rtx with
9846 | | \ -fstack-protector
9847 | local variables | | var_size
9849 +-------------------------------+
9851 | $gp save area | | cprestore_size
9853 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9855 | outgoing stack arguments | |
9857 +-------------------------------+ | args_size
9859 | caller-allocated save area | |
9860 | for register arguments | |
9862 +-------------------------------+ <-- stack_pointer_rtx
9863 frame_pointer_rtx without
9865 hard_frame_pointer_rtx for
9868 At least two of A, B and C will be empty.
9870 Dynamic stack allocations such as alloca insert data at point P.
9871 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9872 hard_frame_pointer_rtx unchanged. */
9875 mips_compute_frame_info (void)
9877 struct mips_frame_info
*frame
;
9878 HOST_WIDE_INT offset
, size
;
9879 unsigned int regno
, i
;
9881 /* Set this function's interrupt properties. */
9882 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
9885 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9886 else if (TARGET_HARD_FLOAT
)
9887 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9888 else if (TARGET_MIPS16
)
9889 error ("interrupt handlers cannot be MIPS16 functions");
9892 cfun
->machine
->interrupt_handler_p
= true;
9893 cfun
->machine
->use_shadow_register_set_p
=
9894 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
9895 cfun
->machine
->keep_interrupts_masked_p
=
9896 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
9897 cfun
->machine
->use_debug_exception_return_p
=
9898 mips_use_debug_exception_return_p (TREE_TYPE
9899 (current_function_decl
));
9903 frame
= &cfun
->machine
->frame
;
9904 memset (frame
, 0, sizeof (*frame
));
9905 size
= get_frame_size ();
9907 cfun
->machine
->global_pointer
= mips_global_pointer ();
9909 /* The first two blocks contain the outgoing argument area and the $gp save
9910 slot. This area isn't needed in leaf functions, but if the
9911 target-independent frame size is nonzero, we have already committed to
9912 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9913 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
9915 /* The MIPS 3.0 linker does not like functions that dynamically
9916 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9917 looks like we are trying to create a second frame pointer to the
9918 function, so allocate some stack space to make it happy. */
9919 if (cfun
->calls_alloca
)
9920 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
9922 frame
->args_size
= 0;
9923 frame
->cprestore_size
= 0;
9927 frame
->args_size
= crtl
->outgoing_args_size
;
9928 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
9930 offset
= frame
->args_size
+ frame
->cprestore_size
;
9932 /* Move above the local variables. */
9933 frame
->var_size
= MIPS_STACK_ALIGN (size
);
9934 offset
+= frame
->var_size
;
9936 /* Find out which GPRs we need to save. */
9937 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9938 if (mips_save_reg_p (regno
))
9941 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
9944 /* If this function calls eh_return, we must also save and restore the
9945 EH data registers. */
9946 if (crtl
->calls_eh_return
)
9947 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
9950 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
9953 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9954 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9955 save all later registers too. */
9956 if (GENERATE_MIPS16E_SAVE_RESTORE
)
9958 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
9959 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
9960 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
9961 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
9964 /* Move above the GPR save area. */
9965 if (frame
->num_gp
> 0)
9967 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
9968 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
9971 /* Find out which FPRs we need to save. This loop must iterate over
9972 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9973 if (TARGET_HARD_FLOAT
)
9974 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
9975 if (mips_save_reg_p (regno
))
9977 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
9978 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
9981 /* Move above the FPR save area. */
9982 if (frame
->num_fp
> 0)
9984 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
9985 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
9988 /* Add in space for the interrupt context information. */
9989 if (cfun
->machine
->interrupt_handler_p
)
9992 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
9995 frame
->acc_mask
|= (1 << 0);
9998 /* Check accumulators 1, 2, 3. */
9999 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
10000 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
10003 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
10006 /* All interrupt context functions need space to preserve STATUS. */
10007 frame
->num_cop0_regs
++;
10009 /* If we don't keep interrupts masked, we need to save EPC. */
10010 if (!cfun
->machine
->keep_interrupts_masked_p
)
10011 frame
->num_cop0_regs
++;
10014 /* Move above the accumulator save area. */
10015 if (frame
->num_acc
> 0)
10017 /* Each accumulator needs 2 words. */
10018 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
10019 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
10022 /* Move above the COP0 register save area. */
10023 if (frame
->num_cop0_regs
> 0)
10025 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
10026 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
10029 /* Move above the callee-allocated varargs save area. */
10030 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
10031 frame
->arg_pointer_offset
= offset
;
10033 /* Move above the callee-allocated area for pretend stack arguments. */
10034 offset
+= crtl
->args
.pretend_args_size
;
10035 frame
->total_size
= offset
;
10037 /* Work out the offsets of the save areas from the top of the frame. */
10038 if (frame
->gp_sp_offset
> 0)
10039 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
10040 if (frame
->fp_sp_offset
> 0)
10041 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
10042 if (frame
->acc_sp_offset
> 0)
10043 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
10044 if (frame
->num_cop0_regs
> 0)
10045 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
10047 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10048 arguments. This tends to increase the chances of using unextended
10049 instructions for local variables and incoming arguments. */
10051 frame
->hard_frame_pointer_offset
= frame
->args_size
;
10054 /* Return the style of GP load sequence that is being used for the
10055 current function. */
10057 enum mips_loadgp_style
10058 mips_current_loadgp_style (void)
10060 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
10061 return LOADGP_NONE
;
10063 if (TARGET_RTP_PIC
)
10066 if (TARGET_ABSOLUTE_ABICALLS
)
10067 return LOADGP_ABSOLUTE
;
10069 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
10072 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10075 mips_frame_pointer_required (void)
10077 /* If the function contains dynamic stack allocations, we need to
10078 use the frame pointer to access the static parts of the frame. */
10079 if (cfun
->calls_alloca
)
10082 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10083 reload may be unable to compute the address of a local variable,
10084 since there is no way to add a large constant to the stack pointer
10085 without using a second temporary register. */
10088 mips_compute_frame_info ();
10089 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
10096 /* Make sure that we're not trying to eliminate to the wrong hard frame
10100 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10102 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
10105 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10106 or argument pointer. TO is either the stack pointer or hard frame
10110 mips_initial_elimination_offset (int from
, int to
)
10112 HOST_WIDE_INT offset
;
10114 mips_compute_frame_info ();
10116 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10119 case FRAME_POINTER_REGNUM
:
10120 if (FRAME_GROWS_DOWNWARD
)
10121 offset
= (cfun
->machine
->frame
.args_size
10122 + cfun
->machine
->frame
.cprestore_size
10123 + cfun
->machine
->frame
.var_size
);
10128 case ARG_POINTER_REGNUM
:
10129 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
10133 gcc_unreachable ();
10136 if (to
== HARD_FRAME_POINTER_REGNUM
)
10137 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10142 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10145 mips_extra_live_on_entry (bitmap regs
)
10147 if (TARGET_USE_GOT
)
10149 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10150 the global pointer. */
10151 if (!TARGET_ABSOLUTE_ABICALLS
)
10152 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10154 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10155 the global pointer. */
10157 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
10159 /* See the comment above load_call<mode> for details. */
10160 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
10164 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10168 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
10173 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
10176 /* Emit code to change the current function's return address to
10177 ADDRESS. SCRATCH is available as a scratch register, if needed.
10178 ADDRESS and SCRATCH are both word-mode GPRs. */
10181 mips_set_return_address (rtx address
, rtx scratch
)
10185 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
10186 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
10187 cfun
->machine
->frame
.gp_sp_offset
);
10188 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
10191 /* Return true if the current function has a cprestore slot. */
10194 mips_cfun_has_cprestore_slot_p (void)
10196 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
10197 && cfun
->machine
->frame
.cprestore_size
> 0);
10200 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10201 cprestore slot. LOAD_P is true if the caller wants to load from
10202 the cprestore slot; it is false if the caller wants to store to
10206 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
10209 const struct mips_frame_info
*frame
;
10211 frame
= &cfun
->machine
->frame
;
10212 /* .cprestore always uses the stack pointer instead of the frame pointer.
10213 We have a free choice for direct stores for non-MIPS16 functions,
10214 and for MIPS16 functions whose cprestore slot is in range of the
10215 stack pointer. Using the stack pointer would sometimes give more
10216 (early) scheduling freedom, but using the frame pointer would
10217 sometimes give more (late) scheduling freedom. It's hard to
10218 predict which applies to a given function, so let's keep things
10221 Loads must always use the frame pointer in functions that call
10222 alloca, and there's little benefit to using the stack pointer
10224 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
10226 *base
= hard_frame_pointer_rtx
;
10227 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
10231 *base
= stack_pointer_rtx
;
10232 *offset
= frame
->args_size
;
10236 /* Return true if X is the load or store address of the cprestore slot;
10237 LOAD_P says which. */
10240 mips_cprestore_address_p (rtx x
, bool load_p
)
10242 rtx given_base
, required_base
;
10243 HOST_WIDE_INT given_offset
, required_offset
;
10245 mips_split_plus (x
, &given_base
, &given_offset
);
10246 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
10247 return given_base
== required_base
&& given_offset
== required_offset
;
10250 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10251 going to load from it, false if we are going to store to it.
10252 Use TEMP as a temporary register if need be. */
10255 mips_cprestore_slot (rtx temp
, bool load_p
)
10258 HOST_WIDE_INT offset
;
10260 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
10261 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
10264 /* Emit instructions to save global pointer value GP into cprestore
10265 slot MEM. OFFSET is the offset that MEM applies to the base register.
10267 MEM may not be a legitimate address. If it isn't, TEMP is a
10268 temporary register that can be used, otherwise it is a SCRATCH. */
10271 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
10273 if (TARGET_CPRESTORE_DIRECTIVE
)
10275 gcc_assert (gp
== pic_offset_table_rtx
);
10276 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
10279 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
10282 /* Restore $gp from its save slot, using TEMP as a temporary base register
10283 if need be. This function is for o32 and o64 abicalls only.
10285 See mips_must_initialize_gp_p for details about how we manage the
10289 mips_restore_gp_from_cprestore_slot (rtx temp
)
10291 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
10293 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
10295 emit_note (NOTE_INSN_DELETED
);
10301 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10302 mips_emit_move (pic_offset_table_rtx
, temp
);
10305 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10306 if (!TARGET_EXPLICIT_RELOCS
)
10307 emit_insn (gen_blockage ());
10310 /* A function to save or store a register. The first argument is the
10311 register and the second is the stack slot. */
10312 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10314 /* Use FN to save or restore register REGNO. MODE is the register's
10315 mode and OFFSET is the offset of its save slot from the current
10319 mips_save_restore_reg (enum machine_mode mode
, int regno
,
10320 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10324 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10326 fn (gen_rtx_REG (mode
, regno
), mem
);
10329 /* Call FN for each accumlator that is saved by the current function.
10330 SP_OFFSET is the offset of the current stack pointer from the start
10334 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10336 HOST_WIDE_INT offset
;
10339 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10340 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10342 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10343 offset
-= UNITS_PER_WORD
;
10344 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10345 offset
-= UNITS_PER_WORD
;
10348 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10349 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10350 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10352 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10353 offset
-= UNITS_PER_WORD
;
10357 /* Save register REG to MEM. Make the instruction frame-related. */
10360 mips_save_reg (rtx reg
, rtx mem
)
10362 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
10366 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
10368 x1
= mips_frame_set (mips_subword (mem
, false),
10369 mips_subword (reg
, false));
10370 x2
= mips_frame_set (mips_subword (mem
, true),
10371 mips_subword (reg
, true));
10372 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10375 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10378 /* Capture the register combinations that are allowed in a SWM or LWM
10379 instruction. The entries are ordered by number of registers set in
10380 the mask. We also ignore the single register encodings because a
10381 normal SW/LW is preferred. */
10383 static const unsigned int umips_swm_mask
[17] = {
10384 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10385 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10386 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10387 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10391 static const unsigned int umips_swm_encoding
[17] = {
10392 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10395 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10396 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10397 stack pointer of the topmost save slot.
10399 Remove from *MASK all registers that were handled using LWM and SWM.
10400 Update *OFFSET so that it points to the first unused save slot. */
10403 umips_build_save_restore (mips_save_restore_fn fn
,
10404 unsigned *mask
, HOST_WIDE_INT
*offset
)
10408 rtx pattern
, set
, reg
, mem
;
10409 HOST_WIDE_INT this_offset
;
10412 /* Try matching $16 to $31 (s0 to ra). */
10413 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
10414 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
10417 if (i
== ARRAY_SIZE (umips_swm_mask
))
10420 /* Get the offset of the lowest save slot. */
10421 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
10422 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
10424 /* LWM/SWM can only support offsets from -2048 to 2047. */
10425 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
10428 /* Create the final PARALLEL. */
10429 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
10430 this_base
= stack_pointer_rtx
;
10432 /* For registers $16-$23 and $30. */
10433 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
10435 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10436 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10437 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
10438 *mask
&= ~(1 << regno
);
10439 reg
= gen_rtx_REG (SImode
, regno
);
10440 if (fn
== mips_save_reg
)
10441 set
= mips_frame_set (mem
, reg
);
10444 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10445 mips_add_cfa_restore (reg
);
10447 XVECEXP (pattern
, 0, j
) = set
;
10450 /* For register $31. */
10451 if (umips_swm_encoding
[i
] >> 4)
10453 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10454 *mask
&= ~(1 << 31);
10455 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10456 reg
= gen_rtx_REG (SImode
, 31);
10457 if (fn
== mips_save_reg
)
10458 set
= mips_frame_set (mem
, reg
);
10461 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10462 mips_add_cfa_restore (reg
);
10464 XVECEXP (pattern
, 0, j
) = set
;
10467 pattern
= emit_insn (pattern
);
10468 if (fn
== mips_save_reg
)
10469 RTX_FRAME_RELATED_P (pattern
) = 1;
10471 /* Adjust the last offset. */
10472 *offset
-= UNITS_PER_WORD
* nregs
;
10477 /* Call FN for each register that is saved by the current function.
10478 SP_OFFSET is the offset of the current stack pointer from the start
10482 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10483 mips_save_restore_fn fn
)
10485 enum machine_mode fpr_mode
;
10487 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
10488 HOST_WIDE_INT offset
;
10491 /* Save registers starting from high to low. The debuggers prefer at least
10492 the return register be stored at func+4, and also it allows us not to
10493 need a nop in the epilogue if at least one register is reloaded in
10494 addition to return address. */
10495 offset
= frame
->gp_sp_offset
- sp_offset
;
10496 mask
= frame
->mask
;
10498 if (TARGET_MICROMIPS
)
10499 umips_build_save_restore (fn
, &mask
, &offset
);
10501 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10502 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10504 /* Record the ra offset for use by mips_function_profiler. */
10505 if (regno
== RETURN_ADDR_REGNUM
)
10506 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10507 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10508 offset
-= UNITS_PER_WORD
;
10511 /* This loop must iterate over the same space as its companion in
10512 mips_compute_frame_info. */
10513 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10514 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10515 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10516 regno
>= FP_REG_FIRST
;
10517 regno
-= MAX_FPRS_PER_FMT
)
10518 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10520 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10521 offset
-= GET_MODE_SIZE (fpr_mode
);
10525 /* Return true if a move between register REGNO and its save slot (MEM)
10526 can be done in a single move. LOAD_P is true if we are loading
10527 from the slot, false if we are storing to it. */
10530 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10532 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10533 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10536 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10537 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10540 /* Emit a move from SRC to DEST, given that one of them is a register
10541 save slot and that the other is a register. TEMP is a temporary
10542 GPR of the same mode that is available if need be. */
10545 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10547 unsigned int regno
;
10552 regno
= REGNO (src
);
10557 regno
= REGNO (dest
);
10561 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
10563 /* We don't yet know whether we'll need this instruction or not.
10564 Postpone the decision by emitting a ghost move. This move
10565 is specifically not frame-related; only the split version is. */
10567 emit_insn (gen_move_gpdi (dest
, src
));
10569 emit_insn (gen_move_gpsi (dest
, src
));
10573 if (regno
== HI_REGNUM
)
10577 mips_emit_move (temp
, src
);
10579 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
10580 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
10582 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
10583 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
10588 emit_insn (gen_mfhidi_ti (temp
,
10589 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
10591 emit_insn (gen_mfhisi_di (temp
,
10592 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
10593 mips_emit_move (dest
, temp
);
10596 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
10597 mips_emit_move (dest
, src
);
10600 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
10601 mips_emit_move (temp
, src
);
10602 mips_emit_move (dest
, temp
);
10605 mips_set_frame_expr (mips_frame_set (dest
, src
));
10608 /* If we're generating n32 or n64 abicalls, and the current function
10609 does not use $28 as its global pointer, emit a cplocal directive.
10610 Use pic_offset_table_rtx as the argument to the directive. */
10613 mips_output_cplocal (void)
10615 if (!TARGET_EXPLICIT_RELOCS
10616 && mips_must_initialize_gp_p ()
10617 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
10618 output_asm_insn (".cplocal %+", 0);
10621 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10624 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10626 const char *fnname
;
10628 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10629 floating-point arguments. */
10631 && TARGET_HARD_FLOAT_ABI
10632 && crtl
->args
.info
.fp_code
!= 0)
10633 mips16_build_function_stub ();
10635 /* Get the function name the same way that toplev.c does before calling
10636 assemble_start_function. This is needed so that the name used here
10637 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10638 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10639 mips_start_function_definition (fnname
, TARGET_MIPS16
);
10641 /* Output MIPS-specific frame information. */
10642 if (!flag_inhibit_size_directive
)
10644 const struct mips_frame_info
*frame
;
10646 frame
= &cfun
->machine
->frame
;
10648 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10650 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
10651 "# vars= " HOST_WIDE_INT_PRINT_DEC
10653 ", args= " HOST_WIDE_INT_PRINT_DEC
10654 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
10655 reg_names
[frame_pointer_needed
10656 ? HARD_FRAME_POINTER_REGNUM
10657 : STACK_POINTER_REGNUM
],
10658 (frame_pointer_needed
10659 ? frame
->total_size
- frame
->hard_frame_pointer_offset
10660 : frame
->total_size
),
10661 reg_names
[RETURN_ADDR_REGNUM
],
10663 frame
->num_gp
, frame
->num_fp
,
10665 frame
->cprestore_size
);
10667 /* .mask MASK, OFFSET. */
10668 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10669 frame
->mask
, frame
->gp_save_offset
);
10671 /* .fmask MASK, OFFSET. */
10672 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10673 frame
->fmask
, frame
->fp_save_offset
);
10676 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10677 Also emit the ".set noreorder; .set nomacro" sequence for functions
10679 if (mips_must_initialize_gp_p ()
10680 && mips_current_loadgp_style () == LOADGP_OLDABI
)
10684 /* This is a fixed-form sequence. The position of the
10685 first two instructions is important because of the
10686 way _gp_disp is defined. */
10687 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10688 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10689 output_asm_insn ("sll\t$2,16", 0);
10690 output_asm_insn ("addu\t$2,$3", 0);
10694 /* .cpload must be in a .set noreorder but not a
10695 .set nomacro block. */
10696 mips_push_asm_switch (&mips_noreorder
);
10697 output_asm_insn (".cpload\t%^", 0);
10698 if (!cfun
->machine
->all_noreorder_p
)
10699 mips_pop_asm_switch (&mips_noreorder
);
10701 mips_push_asm_switch (&mips_nomacro
);
10704 else if (cfun
->machine
->all_noreorder_p
)
10706 mips_push_asm_switch (&mips_noreorder
);
10707 mips_push_asm_switch (&mips_nomacro
);
10710 /* Tell the assembler which register we're using as the global
10711 pointer. This is needed for thunks, since they can use either
10712 explicit relocs or assembler macros. */
10713 mips_output_cplocal ();
10716 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10719 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10720 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10722 const char *fnname
;
10724 /* Reinstate the normal $gp. */
10725 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
10726 mips_output_cplocal ();
10728 if (cfun
->machine
->all_noreorder_p
)
10730 mips_pop_asm_switch (&mips_nomacro
);
10731 mips_pop_asm_switch (&mips_noreorder
);
10734 /* Get the function name the same way that toplev.c does before calling
10735 assemble_start_function. This is needed so that the name used here
10736 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10737 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10738 mips_end_function_definition (fnname
);
10741 /* Emit an optimisation barrier for accesses to the current frame. */
10744 mips_frame_barrier (void)
10746 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
10750 /* The __gnu_local_gp symbol. */
10752 static GTY(()) rtx mips_gnu_local_gp
;
10754 /* If we're generating n32 or n64 abicalls, emit instructions
10755 to set up the global pointer. */
10758 mips_emit_loadgp (void)
10760 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
10762 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10763 switch (mips_current_loadgp_style ())
10765 case LOADGP_ABSOLUTE
:
10766 if (mips_gnu_local_gp
== NULL
)
10768 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
10769 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
10771 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
10772 (pic_reg
, mips_gnu_local_gp
)));
10775 case LOADGP_OLDABI
:
10776 /* Added by mips_output_function_prologue. */
10779 case LOADGP_NEWABI
:
10780 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
10781 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
10782 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
10783 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
10784 (pic_reg
, offset
, incoming_address
)));
10788 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
10789 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
10790 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
10798 emit_insn (PMODE_INSN (gen_copygp_mips16
,
10799 (pic_offset_table_rtx
, pic_reg
)));
10801 /* Emit a blockage if there are implicit uses of the GP register.
10802 This includes profiled functions, because FUNCTION_PROFILE uses
10804 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
10805 emit_insn (gen_loadgp_blockage ());
10808 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10810 #if PROBE_INTERVAL > 32768
10811 #error Cannot use indexed addressing mode for stack probing
10814 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10815 inclusive. These are offsets from the current stack pointer. */
10818 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
10821 sorry ("-fstack-check=specific not implemented for MIPS16");
10823 /* See if we have a constant small number of probes to generate. If so,
10824 that's the easy case. */
10825 if (first
+ size
<= 32768)
10829 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10830 it exceeds SIZE. If only one probe is needed, this will not
10831 generate any code. Then probe at FIRST + SIZE. */
10832 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
10833 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10836 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10840 /* Otherwise, do the same as above, but in a loop. Note that we must be
10841 extra careful with variables wrapping around because we might be at
10842 the very top (or the very bottom) of the address space and we have
10843 to be able to handle this case properly; in particular, we use an
10844 equality test for the loop condition. */
10847 HOST_WIDE_INT rounded_size
;
10848 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
10849 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
10851 /* Sanity check for the addressing mode we're going to use. */
10852 gcc_assert (first
<= 32768);
10855 /* Step 1: round SIZE to the previous multiple of the interval. */
10857 rounded_size
= size
& -PROBE_INTERVAL
;
10860 /* Step 2: compute initial and final value of the loop counter. */
10862 /* TEST_ADDR = SP + FIRST. */
10863 emit_insn (gen_rtx_SET (VOIDmode
, r3
,
10864 plus_constant (Pmode
, stack_pointer_rtx
,
10867 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10868 if (rounded_size
> 32768)
10870 emit_move_insn (r12
, GEN_INT (rounded_size
));
10871 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10872 gen_rtx_MINUS (Pmode
, r3
, r12
)));
10875 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10876 plus_constant (Pmode
, r3
, -rounded_size
)));
10879 /* Step 3: the loop
10881 while (TEST_ADDR != LAST_ADDR)
10883 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10887 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10888 until it is equal to ROUNDED_SIZE. */
10890 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
10893 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10894 that SIZE is equal to ROUNDED_SIZE. */
10896 if (size
!= rounded_size
)
10897 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
10900 /* Make sure nothing is scheduled before we are done. */
10901 emit_insn (gen_blockage ());
10904 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
10905 absolute addresses. */
10908 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
10910 static int labelno
= 0;
10911 char loop_lab
[32], end_lab
[32], tmp
[64];
10914 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
10915 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
10917 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
10919 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10922 strcpy (tmp
, "%(%<beq\t%0,%1,");
10923 output_asm_insn (strcat (tmp
, &end_lab
[1]), xops
);
10925 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10926 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
10927 if (TARGET_64BIT
&& TARGET_LONG64
)
10928 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
10930 output_asm_insn ("addiu\t%0,%0,%1", xops
);
10932 /* Probe at TEST_ADDR and branch. */
10933 fprintf (asm_out_file
, "\tb\t");
10934 assemble_name_raw (asm_out_file
, loop_lab
);
10935 fputc ('\n', asm_out_file
);
10937 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
10939 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
10941 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
10946 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10949 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
10951 return REG_P (*x
) && KERNEL_REG_P (REGNO (*x
));
10954 /* Expand the "prologue" pattern. */
10957 mips_expand_prologue (void)
10959 const struct mips_frame_info
*frame
;
10960 HOST_WIDE_INT size
;
10961 unsigned int nargs
;
10964 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
10966 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10967 or implicitly. If so, we can commit to using a global pointer
10968 straight away, otherwise we need to defer the decision. */
10969 if (mips_cfun_has_inflexible_gp_ref_p ()
10970 || mips_cfun_has_flexible_gp_ref_p ())
10972 cfun
->machine
->must_initialize_gp_p
= true;
10973 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
10976 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
10979 frame
= &cfun
->machine
->frame
;
10980 size
= frame
->total_size
;
10982 if (flag_stack_usage_info
)
10983 current_function_static_stack_size
= size
;
10985 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
10986 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
10988 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10989 bytes beforehand; this is enough to cover the register save area
10990 without going out of range. */
10991 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
10992 || frame
->num_cop0_regs
> 0)
10994 HOST_WIDE_INT step1
;
10996 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
10997 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10999 HOST_WIDE_INT offset
;
11000 unsigned int mask
, regno
;
11002 /* Try to merge argument stores into the save instruction. */
11003 nargs
= mips16e_collect_argument_saves ();
11005 /* Build the save instruction. */
11006 mask
= frame
->mask
;
11007 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
11009 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11010 mips_frame_barrier ();
11013 /* Check if we need to save other registers. */
11014 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11015 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11017 offset
-= UNITS_PER_WORD
;
11018 mips_save_restore_reg (word_mode
, regno
,
11019 offset
, mips_save_reg
);
11024 if (cfun
->machine
->interrupt_handler_p
)
11026 HOST_WIDE_INT offset
;
11029 /* If this interrupt is using a shadow register set, we need to
11030 get the stack pointer from the previous register set. */
11031 if (cfun
->machine
->use_shadow_register_set_p
)
11032 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
11033 stack_pointer_rtx
));
11035 if (!cfun
->machine
->keep_interrupts_masked_p
)
11037 /* Move from COP0 Cause to K0. */
11038 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
11039 gen_rtx_REG (SImode
,
11040 COP0_CAUSE_REG_NUM
)));
11041 /* Move from COP0 EPC to K1. */
11042 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11043 gen_rtx_REG (SImode
,
11044 COP0_EPC_REG_NUM
)));
11047 /* Allocate the first part of the frame. */
11048 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
11050 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11051 mips_frame_barrier ();
11054 /* Start at the uppermost location for saving. */
11055 offset
= frame
->cop0_sp_offset
- size
;
11056 if (!cfun
->machine
->keep_interrupts_masked_p
)
11058 /* Push EPC into its stack slot. */
11059 mem
= gen_frame_mem (word_mode
,
11060 plus_constant (Pmode
, stack_pointer_rtx
,
11062 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11063 offset
-= UNITS_PER_WORD
;
11066 /* Move from COP0 Status to K1. */
11067 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11068 gen_rtx_REG (SImode
,
11069 COP0_STATUS_REG_NUM
)));
11071 /* Right justify the RIPL in k0. */
11072 if (!cfun
->machine
->keep_interrupts_masked_p
)
11073 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
11074 gen_rtx_REG (SImode
, K0_REG_NUM
),
11075 GEN_INT (CAUSE_IPL
)));
11077 /* Push Status into its stack slot. */
11078 mem
= gen_frame_mem (word_mode
,
11079 plus_constant (Pmode
, stack_pointer_rtx
,
11081 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11082 offset
-= UNITS_PER_WORD
;
11084 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11085 if (!cfun
->machine
->keep_interrupts_masked_p
)
11086 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11089 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11091 if (!cfun
->machine
->keep_interrupts_masked_p
)
11092 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11093 IE is already the correct value, so we don't have to do
11094 anything explicit. */
11095 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11098 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11100 /* Disable interrupts by clearing the KSU, ERL, EXL,
11102 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11105 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11109 insn
= gen_add3_insn (stack_pointer_rtx
,
11112 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11113 mips_frame_barrier ();
11116 mips_for_each_saved_acc (size
, mips_save_reg
);
11117 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
11121 /* Allocate the rest of the frame. */
11124 if (SMALL_OPERAND (-size
))
11125 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
11127 GEN_INT (-size
)))) = 1;
11130 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
11133 /* There are no instructions to add or subtract registers
11134 from the stack pointer, so use the frame pointer as a
11135 temporary. We should always be using a frame pointer
11136 in this case anyway. */
11137 gcc_assert (frame_pointer_needed
);
11138 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11139 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
11140 hard_frame_pointer_rtx
,
11141 MIPS_PROLOGUE_TEMP (Pmode
)));
11142 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
11145 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
11147 MIPS_PROLOGUE_TEMP (Pmode
)));
11149 /* Describe the combined effect of the previous instructions. */
11150 mips_set_frame_expr
11151 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
11152 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
11154 mips_frame_barrier ();
11157 /* Set up the frame pointer, if we're using one. */
11158 if (frame_pointer_needed
)
11160 HOST_WIDE_INT offset
;
11162 offset
= frame
->hard_frame_pointer_offset
;
11165 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11166 RTX_FRAME_RELATED_P (insn
) = 1;
11168 else if (SMALL_OPERAND (offset
))
11170 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
11171 stack_pointer_rtx
, GEN_INT (offset
));
11172 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11176 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
11177 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11178 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
11179 hard_frame_pointer_rtx
,
11180 MIPS_PROLOGUE_TEMP (Pmode
)));
11181 mips_set_frame_expr
11182 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
11183 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
11187 mips_emit_loadgp ();
11189 /* Initialize the $gp save slot. */
11190 if (mips_cfun_has_cprestore_slot_p ())
11192 rtx base
, mem
, gp
, temp
;
11193 HOST_WIDE_INT offset
;
11195 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
11196 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11197 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11198 temp
= (SMALL_OPERAND (offset
)
11199 ? gen_rtx_SCRATCH (Pmode
)
11200 : MIPS_PROLOGUE_TEMP (Pmode
));
11201 emit_insn (PMODE_INSN (gen_potential_cprestore
,
11202 (mem
, GEN_INT (offset
), gp
, temp
)));
11204 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11205 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11206 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
11209 /* We need to search back to the last use of K0 or K1. */
11210 if (cfun
->machine
->interrupt_handler_p
)
11212 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
11214 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
11216 /* Emit a move from K1 to COP0 Status after insn. */
11217 gcc_assert (insn
!= NULL_RTX
);
11218 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11219 gen_rtx_REG (SImode
, K1_REG_NUM
)),
11223 /* If we are profiling, make sure no instructions are scheduled before
11224 the call to mcount. */
11226 emit_insn (gen_blockage ());
11229 /* Attach all pending register saves to the previous instruction.
11230 Return that instruction. */
11233 mips_epilogue_emit_cfa_restores (void)
11237 insn
= get_last_insn ();
11238 gcc_assert (insn
&& !REG_NOTES (insn
));
11239 if (mips_epilogue
.cfa_restores
)
11241 RTX_FRAME_RELATED_P (insn
) = 1;
11242 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
11243 mips_epilogue
.cfa_restores
= 0;
11248 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11249 now at REG + OFFSET. */
11252 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
11256 insn
= mips_epilogue_emit_cfa_restores ();
11257 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
11259 RTX_FRAME_RELATED_P (insn
) = 1;
11260 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
11261 plus_constant (Pmode
, reg
, offset
),
11263 mips_epilogue
.cfa_reg
= reg
;
11264 mips_epilogue
.cfa_offset
= offset
;
11268 /* Emit instructions to restore register REG from slot MEM. Also update
11269 the cfa_restores list. */
11272 mips_restore_reg (rtx reg
, rtx mem
)
11274 /* There's no MIPS16 instruction to load $31 directly. Load into
11275 $7 instead and adjust the return insn appropriately. */
11276 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
11277 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
11278 else if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
11280 mips_add_cfa_restore (mips_subword (reg
, true));
11281 mips_add_cfa_restore (mips_subword (reg
, false));
11284 mips_add_cfa_restore (reg
);
11286 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
11287 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
11288 /* The CFA is currently defined in terms of the register whose
11289 value we have just restored. Redefine the CFA in terms of
11290 the stack pointer. */
11291 mips_epilogue_set_cfa (stack_pointer_rtx
,
11292 mips_epilogue
.cfa_restore_sp_offset
);
11295 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11296 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11297 BASE, if not the stack pointer, is available as a temporary. */
11300 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
11302 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
11305 mips_frame_barrier ();
11306 if (offset
== const0_rtx
)
11308 emit_move_insn (stack_pointer_rtx
, base
);
11309 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11311 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
11313 emit_insn (gen_add3_insn (base
, base
, offset
));
11314 mips_epilogue_set_cfa (base
, new_frame_size
);
11315 emit_move_insn (stack_pointer_rtx
, base
);
11319 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
11320 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11324 /* Emit any instructions needed before a return. */
11327 mips_expand_before_return (void)
11329 /* When using a call-clobbered gp, we start out with unified call
11330 insns that include instructions to restore the gp. We then split
11331 these unified calls after reload. These split calls explicitly
11332 clobber gp, so there is no need to define
11333 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11335 For consistency, we should also insert an explicit clobber of $28
11336 before return insns, so that the post-reload optimizers know that
11337 the register is not live on exit. */
11338 if (TARGET_CALL_CLOBBERED_GP
)
11339 emit_clobber (pic_offset_table_rtx
);
11342 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11346 mips_expand_epilogue (bool sibcall_p
)
11348 const struct mips_frame_info
*frame
;
11349 HOST_WIDE_INT step1
, step2
;
11350 rtx base
, adjust
, insn
;
11351 bool use_jraddiusp_p
= false;
11353 if (!sibcall_p
&& mips_can_use_return_insn ())
11355 emit_jump_insn (gen_return ());
11359 /* In MIPS16 mode, if the return value should go into a floating-point
11360 register, we need to call a helper routine to copy it over. */
11361 if (mips16_cfun_returns_in_fpr_p ())
11362 mips16_copy_fpr_return_value ();
11364 /* Split the frame into two. STEP1 is the amount of stack we should
11365 deallocate before restoring the registers. STEP2 is the amount we
11366 should deallocate afterwards.
11368 Start off by assuming that no registers need to be restored. */
11369 frame
= &cfun
->machine
->frame
;
11370 step1
= frame
->total_size
;
11373 /* Work out which register holds the frame address. */
11374 if (!frame_pointer_needed
)
11375 base
= stack_pointer_rtx
;
11378 base
= hard_frame_pointer_rtx
;
11379 step1
-= frame
->hard_frame_pointer_offset
;
11381 mips_epilogue
.cfa_reg
= base
;
11382 mips_epilogue
.cfa_offset
= step1
;
11383 mips_epilogue
.cfa_restores
= NULL_RTX
;
11385 /* If we need to restore registers, deallocate as much stack as
11386 possible in the second step without going out of range. */
11387 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
11388 || frame
->num_cop0_regs
> 0)
11390 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
11394 /* Get an rtx for STEP1 that we can add to BASE. */
11395 adjust
= GEN_INT (step1
);
11396 if (!SMALL_OPERAND (step1
))
11398 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
11399 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
11401 mips_deallocate_stack (base
, adjust
, step2
);
11403 /* If we're using addressing macros, $gp is implicitly used by all
11404 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11406 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
11407 emit_insn (gen_blockage ());
11409 mips_epilogue
.cfa_restore_sp_offset
= step2
;
11410 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
11412 unsigned int regno
, mask
;
11413 HOST_WIDE_INT offset
;
11416 /* Generate the restore instruction. */
11417 mask
= frame
->mask
;
11418 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
11420 /* Restore any other registers manually. */
11421 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11422 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11424 offset
-= UNITS_PER_WORD
;
11425 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
11428 /* Restore the remaining registers and deallocate the final bit
11430 mips_frame_barrier ();
11431 emit_insn (restore
);
11432 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
11436 /* Restore the registers. */
11437 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
11438 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
11441 if (cfun
->machine
->interrupt_handler_p
)
11443 HOST_WIDE_INT offset
;
11446 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
11447 if (!cfun
->machine
->keep_interrupts_masked_p
)
11449 /* Restore the original EPC. */
11450 mem
= gen_frame_mem (word_mode
,
11451 plus_constant (Pmode
, stack_pointer_rtx
,
11453 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11454 offset
-= UNITS_PER_WORD
;
11456 /* Move to COP0 EPC. */
11457 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
11458 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11461 /* Restore the original Status. */
11462 mem
= gen_frame_mem (word_mode
,
11463 plus_constant (Pmode
, stack_pointer_rtx
,
11465 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11466 offset
-= UNITS_PER_WORD
;
11468 /* If we don't use shadow register set, we need to update SP. */
11469 if (!cfun
->machine
->use_shadow_register_set_p
)
11470 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11472 /* The choice of position is somewhat arbitrary in this case. */
11473 mips_epilogue_emit_cfa_restores ();
11475 /* Move to COP0 Status. */
11476 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11477 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11479 else if (TARGET_MICROMIPS
11480 && !crtl
->calls_eh_return
11483 && mips_unsigned_immediate_p (step2
, 5, 2))
11484 use_jraddiusp_p
= true;
11486 /* Deallocate the final bit of the frame. */
11487 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11490 if (!use_jraddiusp_p
)
11491 gcc_assert (!mips_epilogue
.cfa_restores
);
11493 /* Add in the __builtin_eh_return stack adjustment. We need to
11494 use a temporary in MIPS16 code. */
11495 if (crtl
->calls_eh_return
)
11499 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
11500 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
11501 MIPS_EPILOGUE_TEMP (Pmode
),
11502 EH_RETURN_STACKADJ_RTX
));
11503 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
11506 emit_insn (gen_add3_insn (stack_pointer_rtx
,
11508 EH_RETURN_STACKADJ_RTX
));
11513 mips_expand_before_return ();
11514 if (cfun
->machine
->interrupt_handler_p
)
11516 /* Interrupt handlers generate eret or deret. */
11517 if (cfun
->machine
->use_debug_exception_return_p
)
11518 emit_jump_insn (gen_mips_deret ());
11520 emit_jump_insn (gen_mips_eret ());
11526 /* When generating MIPS16 code, the normal
11527 mips_for_each_saved_gpr_and_fpr path will restore the return
11528 address into $7 rather than $31. */
11530 && !GENERATE_MIPS16E_SAVE_RESTORE
11531 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
11533 /* simple_returns cannot rely on values that are only available
11534 on paths through the epilogue (because return paths that do
11535 not pass through the epilogue may nevertheless reuse a
11536 simple_return that occurs at the end of the epilogue).
11537 Use a normal return here instead. */
11538 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
11539 pat
= gen_return_internal (reg
);
11541 else if (use_jraddiusp_p
)
11542 pat
= gen_jraddiusp (GEN_INT (step2
));
11545 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
11546 pat
= gen_simple_return_internal (reg
);
11548 emit_jump_insn (pat
);
11549 if (use_jraddiusp_p
)
11550 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
11554 /* Search from the beginning to the first use of K0 or K1. */
11555 if (cfun
->machine
->interrupt_handler_p
11556 && !cfun
->machine
->keep_interrupts_masked_p
)
11558 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11560 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
11562 gcc_assert (insn
!= NULL_RTX
);
11563 /* Insert disable interrupts before the first use of K0 or K1. */
11564 emit_insn_before (gen_mips_di (), insn
);
11565 emit_insn_before (gen_mips_ehb (), insn
);
11569 /* Return nonzero if this function is known to have a null epilogue.
11570 This allows the optimizer to omit jumps to jumps if no stack
11574 mips_can_use_return_insn (void)
11576 /* Interrupt handlers need to go through the epilogue. */
11577 if (cfun
->machine
->interrupt_handler_p
)
11580 if (!reload_completed
)
11586 /* In MIPS16 mode, a function that returns a floating-point value
11587 needs to arrange to copy the return value into the floating-point
11589 if (mips16_cfun_returns_in_fpr_p ())
11592 return cfun
->machine
->frame
.total_size
== 0;
11595 /* Return true if register REGNO can store a value of mode MODE.
11596 The result of this function is cached in mips_hard_regno_mode_ok. */
11599 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
11602 enum mode_class mclass
;
11604 if (mode
== CCV2mode
)
11605 return (ISA_HAS_8CC
11606 && ST_REG_P (regno
)
11607 && (regno
- ST_REG_FIRST
) % 2 == 0);
11609 if (mode
== CCV4mode
)
11610 return (ISA_HAS_8CC
11611 && ST_REG_P (regno
)
11612 && (regno
- ST_REG_FIRST
) % 4 == 0);
11614 if (mode
== CCmode
)
11615 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
11617 size
= GET_MODE_SIZE (mode
);
11618 mclass
= GET_MODE_CLASS (mode
);
11620 if (GP_REG_P (regno
))
11621 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
11623 if (FP_REG_P (regno
)
11624 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
11625 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
11627 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11628 if (TARGET_LOONGSON_VECTORS
11629 && (mode
== V2SImode
11630 || mode
== V4HImode
11631 || mode
== V8QImode
11632 || mode
== DImode
))
11635 if (mclass
== MODE_FLOAT
11636 || mclass
== MODE_COMPLEX_FLOAT
11637 || mclass
== MODE_VECTOR_FLOAT
)
11638 return size
<= UNITS_PER_FPVALUE
;
11640 /* Allow integer modes that fit into a single register. We need
11641 to put integers into FPRs when using instructions like CVT
11642 and TRUNC. There's no point allowing sizes smaller than a word,
11643 because the FPU has no appropriate load/store instructions. */
11644 if (mclass
== MODE_INT
)
11645 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
11648 if (ACC_REG_P (regno
)
11649 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
11651 if (MD_REG_P (regno
))
11653 /* After a multiplication or division, clobbering HI makes
11654 the value of LO unpredictable, and vice versa. This means
11655 that, for all interesting cases, HI and LO are effectively
11658 We model this by requiring that any value that uses HI
11660 if (size
<= UNITS_PER_WORD
* 2)
11661 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
11665 /* DSP accumulators do not have the same restrictions as
11666 HI and LO, so we can treat them as normal doubleword
11668 if (size
<= UNITS_PER_WORD
)
11671 if (size
<= UNITS_PER_WORD
* 2
11672 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
11677 if (ALL_COP_REG_P (regno
))
11678 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
11680 if (regno
== GOT_VERSION_REGNUM
)
11681 return mode
== SImode
;
11686 /* Implement HARD_REGNO_NREGS. */
11689 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
11691 if (ST_REG_P (regno
))
11692 /* The size of FP status registers is always 4, because they only hold
11693 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11694 return (GET_MODE_SIZE (mode
) + 3) / 4;
11696 if (FP_REG_P (regno
))
11697 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
11699 /* All other registers are word-sized. */
11700 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
11703 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11704 in mips_hard_regno_nregs. */
11707 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
11713 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
11714 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
11716 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
11717 size
= MIN (size
, 4);
11718 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
11720 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
11722 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
11723 size
= MIN (size
, UNITS_PER_FPREG
);
11724 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
11726 if (!hard_reg_set_empty_p (left
))
11727 size
= MIN (size
, UNITS_PER_WORD
);
11728 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
11731 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11734 mips_cannot_change_mode_class (enum machine_mode from
,
11735 enum machine_mode to
,
11736 enum reg_class rclass
)
11738 /* Allow conversions between different Loongson integer vectors,
11739 and between those vectors and DImode. */
11740 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
11741 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
11744 /* Otherwise, there are several problems with changing the modes of
11745 values in floating-point registers:
11747 - When a multi-word value is stored in paired floating-point
11748 registers, the first register always holds the low word. We
11749 therefore can't allow FPRs to change between single-word and
11750 multi-word modes on big-endian targets.
11752 - GCC assumes that each word of a multiword register can be
11753 accessed individually using SUBREGs. This is not true for
11754 floating-point registers if they are bigger than a word.
11756 - Loading a 32-bit value into a 64-bit floating-point register
11757 will not sign-extend the value, despite what LOAD_EXTEND_OP
11758 says. We can't allow FPRs to change from SImode to a wider
11759 mode on 64-bit targets.
11761 - If the FPU has already interpreted a value in one format, we
11762 must not ask it to treat the value as having a different
11765 We therefore disallow all mode changes involving FPRs. */
11767 return reg_classes_intersect_p (FP_REGS
, rclass
);
11770 /* Implement target hook small_register_classes_for_mode_p. */
11773 mips_small_register_classes_for_mode_p (enum machine_mode mode
11776 return TARGET_MIPS16
;
11779 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11782 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
11787 return TARGET_HARD_FLOAT
;
11790 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
11793 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
11800 /* Implement MODES_TIEABLE_P. */
11803 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
11805 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11806 prefer to put one of them in FPRs. */
11807 return (mode1
== mode2
11808 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
11809 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
11812 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11815 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
11817 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
11820 if (reg_class_subset_p (FP_REGS
, rclass
)
11821 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
11824 if (reg_class_subset_p (GR_REGS
, rclass
))
11827 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
11833 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11834 Return a "canonical" class to represent it in later calculations. */
11837 mips_canonicalize_move_class (reg_class_t rclass
)
11839 /* All moves involving accumulator registers have the same cost. */
11840 if (reg_class_subset_p (rclass
, ACC_REGS
))
11843 /* Likewise promote subclasses of general registers to the most
11844 interesting containing class. */
11845 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
11847 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
11848 rclass
= GENERAL_REGS
;
11853 /* Return the cost of moving a value of mode MODE from a register of
11854 class FROM to a GPR. Return 0 for classes that are unions of other
11855 classes handled by this function. */
11858 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
11864 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11868 /* MFLO and MFHI. */
11876 /* LUI followed by MOVF. */
11882 /* This choice of value is historical. */
11890 /* Return the cost of moving a value of mode MODE from a GPR to a
11891 register of class TO. Return 0 for classes that are unions of
11892 other classes handled by this function. */
11895 mips_move_from_gpr_cost (enum machine_mode mode
, reg_class_t to
)
11900 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11904 /* MTLO and MTHI. */
11912 /* A secondary reload through an FPR scratch. */
11913 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
11914 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
11919 /* This choice of value is historical. */
11927 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11928 maximum of the move costs for subclasses; regclass will work out
11929 the maximum for us. */
11932 mips_register_move_cost (enum machine_mode mode
,
11933 reg_class_t from
, reg_class_t to
)
11938 from
= mips_canonicalize_move_class (from
);
11939 to
= mips_canonicalize_move_class (to
);
11941 /* Handle moves that can be done without using general-purpose registers. */
11942 if (from
== FP_REGS
)
11944 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
11948 /* The sequence generated by mips_expand_fcc_reload. */
11952 /* Handle cases in which only one class deviates from the ideal. */
11953 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
11955 return mips_move_from_gpr_cost (mode
, to
);
11957 return mips_move_to_gpr_cost (mode
, from
);
11959 /* Handles cases that require a GPR temporary. */
11960 cost1
= mips_move_to_gpr_cost (mode
, from
);
11963 cost2
= mips_move_from_gpr_cost (mode
, to
);
11965 return cost1
+ cost2
;
11971 /* Implement TARGET_MEMORY_MOVE_COST. */
11974 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
11976 return (mips_cost
->memory_latency
11977 + memory_move_secondary_cost (mode
, rclass
, in
));
11980 /* Return the register class required for a secondary register when
11981 copying between one of the registers in RCLASS and value X, which
11982 has mode MODE. X is the source of the move if IN_P, otherwise it
11983 is the destination. Return NO_REGS if no secondary register is
11987 mips_secondary_reload_class (enum reg_class rclass
,
11988 enum machine_mode mode
, rtx x
, bool in_p
)
11992 /* If X is a constant that cannot be loaded into $25, it must be loaded
11993 into some other GPR. No other register class allows a direct move. */
11994 if (mips_dangerous_for_la25_p (x
))
11995 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
11997 regno
= true_regnum (x
);
12000 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12001 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
12007 /* Copying from accumulator registers to anywhere other than a general
12008 register requires a temporary general register. */
12009 if (reg_class_subset_p (rclass
, ACC_REGS
))
12010 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12011 if (ACC_REG_P (regno
))
12012 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12014 /* We can only copy a value to a condition code register from a
12015 floating-point register, and even then we require a scratch
12016 floating-point register. We can only copy a value out of a
12017 condition-code register into a general register. */
12018 if (reg_class_subset_p (rclass
, ST_REGS
))
12022 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12024 if (ST_REG_P (regno
))
12028 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12031 if (reg_class_subset_p (rclass
, FP_REGS
))
12034 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
12035 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12036 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12039 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
12040 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12043 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
12044 /* We can force the constant to memory and use lwc1
12045 and ldc1. As above, we will use pairs of lwc1s if
12046 ldc1 is not supported. */
12049 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
12050 /* In this case we can use mov.fmt. */
12053 /* Otherwise, we need to reload through an integer register. */
12056 if (FP_REG_P (regno
))
12057 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12062 /* Implement TARGET_MODE_REP_EXTENDED. */
12065 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
12067 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12068 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
12069 return SIGN_EXTEND
;
12074 /* Implement TARGET_VALID_POINTER_MODE. */
12077 mips_valid_pointer_mode (enum machine_mode mode
)
12079 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
12082 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12085 mips_vector_mode_supported_p (enum machine_mode mode
)
12090 return TARGET_PAIRED_SINGLE_FLOAT
;
12105 return TARGET_LOONGSON_VECTORS
;
12112 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12115 mips_scalar_mode_supported_p (enum machine_mode mode
)
12117 if (ALL_FIXED_POINT_MODE_P (mode
)
12118 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
12121 return default_scalar_mode_supported_p (mode
);
12124 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12126 static enum machine_mode
12127 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED
)
12129 if (TARGET_PAIRED_SINGLE_FLOAT
12135 /* Implement TARGET_INIT_LIBFUNCS. */
12138 mips_init_libfuncs (void)
12140 if (TARGET_FIX_VR4120
)
12142 /* Register the special divsi3 and modsi3 functions needed to work
12143 around VR4120 division errata. */
12144 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
12145 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
12148 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
12150 /* Register the MIPS16 -mhard-float stubs. */
12151 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
12152 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
12153 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
12154 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
12156 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
12157 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
12158 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
12159 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
12160 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
12161 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
12162 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
12164 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
12165 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
12166 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
12168 if (TARGET_DOUBLE_FLOAT
)
12170 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
12171 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
12172 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
12173 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
12175 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
12176 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
12177 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
12178 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
12179 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
12180 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
12181 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
12183 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
12184 "__mips16_extendsfdf2");
12185 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
12186 "__mips16_truncdfsf2");
12187 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
12188 "__mips16_fix_truncdfsi");
12189 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
12190 "__mips16_floatsidf");
12191 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
12192 "__mips16_floatunsidf");
12196 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12197 on an external non-MIPS16 routine to implement __sync_synchronize.
12198 Similarly for the rest of the ll/sc libfuncs. */
12201 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
12202 init_sync_libfuncs (UNITS_PER_WORD
);
12206 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12209 mips_process_load_label (rtx target
)
12211 rtx base
, gp
, intop
;
12212 HOST_WIDE_INT offset
;
12214 mips_multi_start ();
12218 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
12219 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12223 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
12224 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12228 gp
= pic_offset_table_rtx
;
12229 if (mips_cfun_has_cprestore_slot_p ())
12231 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
12232 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12233 if (!SMALL_OPERAND (offset
))
12235 intop
= GEN_INT (CONST_HIGH_PART (offset
));
12236 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
12237 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
12240 offset
= CONST_LOW_PART (offset
);
12242 intop
= GEN_INT (offset
);
12243 if (ISA_HAS_LOAD_DELAY
)
12244 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
12246 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
12248 if (ISA_HAS_LOAD_DELAY
)
12249 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
12251 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
12252 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
12257 /* Return the number of instructions needed to load a label into $AT. */
12259 static unsigned int
12260 mips_load_label_num_insns (void)
12262 if (cfun
->machine
->load_label_num_insns
== 0)
12264 mips_process_load_label (pc_rtx
);
12265 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
12267 return cfun
->machine
->load_label_num_insns
;
12270 /* Emit an asm sequence to start a noat block and load the address
12271 of a label into $1. */
12274 mips_output_load_label (rtx target
)
12276 mips_push_asm_switch (&mips_noat
);
12277 if (TARGET_EXPLICIT_RELOCS
)
12279 mips_process_load_label (target
);
12280 mips_multi_write ();
12284 if (Pmode
== DImode
)
12285 output_asm_insn ("dla\t%@,%0", &target
);
12287 output_asm_insn ("la\t%@,%0", &target
);
12291 /* Return the length of INSN. LENGTH is the initial length computed by
12292 attributes in the machine-description file. */
12295 mips_adjust_insn_length (rtx insn
, int length
)
12297 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12298 of a PIC long-branch sequence. Substitute the correct value. */
12299 if (length
== MAX_PIC_BRANCH_LENGTH
12300 && INSN_CODE (insn
) >= 0
12301 && get_attr_type (insn
) == TYPE_BRANCH
)
12303 /* Add the branch-over instruction and its delay slot, if this
12304 is a conditional branch. */
12305 length
= simplejump_p (insn
) ? 0 : 8;
12307 /* Add the size of a load into $AT. */
12308 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
12310 /* Add the length of an indirect jump, ignoring the delay slot. */
12311 length
+= TARGET_COMPRESSION
? 2 : 4;
12314 /* A unconditional jump has an unfilled delay slot if it is not part
12315 of a sequence. A conditional jump normally has a delay slot, but
12316 does not on MIPS16. */
12317 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
12318 length
+= TARGET_MIPS16
? 2 : 4;
12320 /* See how many nops might be needed to avoid hardware hazards. */
12321 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
12322 switch (get_attr_hazard (insn
))
12328 length
+= NOP_INSN_LENGTH
;
12332 length
+= NOP_INSN_LENGTH
* 2;
12339 /* Return the assembly code for INSN, which has the operands given by
12340 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12341 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12342 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12343 version of BRANCH_IF_TRUE. */
12346 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
12347 const char *branch_if_true
,
12348 const char *branch_if_false
)
12350 unsigned int length
;
12351 rtx taken
, not_taken
;
12353 gcc_assert (LABEL_P (operands
[0]));
12355 length
= get_attr_length (insn
);
12358 /* Just a simple conditional branch. */
12359 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
12360 return branch_if_true
;
12363 /* Generate a reversed branch around a direct jump. This fallback does
12364 not use branch-likely instructions. */
12365 mips_branch_likely
= false;
12366 not_taken
= gen_label_rtx ();
12367 taken
= operands
[0];
12369 /* Generate the reversed branch to NOT_TAKEN. */
12370 operands
[0] = not_taken
;
12371 output_asm_insn (branch_if_false
, operands
);
12373 /* If INSN has a delay slot, we must provide delay slots for both the
12374 branch to NOT_TAKEN and the conditional jump. We must also ensure
12375 that INSN's delay slot is executed in the appropriate cases. */
12376 if (final_sequence
)
12378 /* This first delay slot will always be executed, so use INSN's
12379 delay slot if is not annulled. */
12380 if (!INSN_ANNULLED_BRANCH_P (insn
))
12382 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12383 asm_out_file
, optimize
, 1, NULL
);
12384 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12387 output_asm_insn ("nop", 0);
12388 fprintf (asm_out_file
, "\n");
12391 /* Output the unconditional branch to TAKEN. */
12392 if (TARGET_ABSOLUTE_JUMPS
)
12393 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
12396 mips_output_load_label (taken
);
12397 output_asm_insn ("jr\t%@%]%/", 0);
12400 /* Now deal with its delay slot; see above. */
12401 if (final_sequence
)
12403 /* This delay slot will only be executed if the branch is taken.
12404 Use INSN's delay slot if is annulled. */
12405 if (INSN_ANNULLED_BRANCH_P (insn
))
12407 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12408 asm_out_file
, optimize
, 1, NULL
);
12409 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12412 output_asm_insn ("nop", 0);
12413 fprintf (asm_out_file
, "\n");
12416 /* Output NOT_TAKEN. */
12417 targetm
.asm_out
.internal_label (asm_out_file
, "L",
12418 CODE_LABEL_NUMBER (not_taken
));
12422 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12423 if some ordering condition is true. The condition is given by
12424 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12425 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12426 its second is always zero. */
12429 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
12431 const char *branch
[2];
12433 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12434 Make BRANCH[0] branch on the inverse condition. */
12435 switch (GET_CODE (operands
[1]))
12437 /* These cases are equivalent to comparisons against zero. */
12439 inverted_p
= !inverted_p
;
12440 /* Fall through. */
12442 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
12443 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
12446 /* These cases are always true or always false. */
12448 inverted_p
= !inverted_p
;
12449 /* Fall through. */
12451 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
12452 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
12456 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
12457 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
12460 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
12463 /* Start a block of code that needs access to the LL, SC and SYNC
12467 mips_start_ll_sc_sync_block (void)
12469 if (!ISA_HAS_LL_SC
)
12471 output_asm_insn (".set\tpush", 0);
12473 output_asm_insn (".set\tmips3", 0);
12475 output_asm_insn (".set\tmips2", 0);
12479 /* End a block started by mips_start_ll_sc_sync_block. */
12482 mips_end_ll_sc_sync_block (void)
12484 if (!ISA_HAS_LL_SC
)
12485 output_asm_insn (".set\tpop", 0);
12488 /* Output and/or return the asm template for a sync instruction. */
12491 mips_output_sync (void)
12493 mips_start_ll_sc_sync_block ();
12494 output_asm_insn ("sync", 0);
12495 mips_end_ll_sc_sync_block ();
12499 /* Return the asm template associated with sync_insn1 value TYPE.
12500 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12502 static const char *
12503 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
12507 case SYNC_INSN1_MOVE
:
12508 return "move\t%0,%z2";
12509 case SYNC_INSN1_LI
:
12510 return "li\t%0,%2";
12511 case SYNC_INSN1_ADDU
:
12512 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12513 case SYNC_INSN1_ADDIU
:
12514 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12515 case SYNC_INSN1_SUBU
:
12516 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12517 case SYNC_INSN1_AND
:
12518 return "and\t%0,%1,%z2";
12519 case SYNC_INSN1_ANDI
:
12520 return "andi\t%0,%1,%2";
12521 case SYNC_INSN1_OR
:
12522 return "or\t%0,%1,%z2";
12523 case SYNC_INSN1_ORI
:
12524 return "ori\t%0,%1,%2";
12525 case SYNC_INSN1_XOR
:
12526 return "xor\t%0,%1,%z2";
12527 case SYNC_INSN1_XORI
:
12528 return "xori\t%0,%1,%2";
12530 gcc_unreachable ();
12533 /* Return the asm template associated with sync_insn2 value TYPE. */
12535 static const char *
12536 mips_sync_insn2_template (enum attr_sync_insn2 type
)
12540 case SYNC_INSN2_NOP
:
12541 gcc_unreachable ();
12542 case SYNC_INSN2_AND
:
12543 return "and\t%0,%1,%z2";
12544 case SYNC_INSN2_XOR
:
12545 return "xor\t%0,%1,%z2";
12546 case SYNC_INSN2_NOT
:
12547 return "nor\t%0,%1,%.";
12549 gcc_unreachable ();
12552 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12553 the value of the one of the sync_* attributes. Return the operand
12554 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12555 have the associated attribute. */
12558 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
12561 default_value
= operands
[index
- 1];
12562 return default_value
;
12565 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12566 sequence for it. */
12569 mips_process_sync_loop (rtx insn
, rtx
*operands
)
12571 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
12572 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
12573 unsigned int tmp3_insn
;
12574 enum attr_sync_insn1 insn1
;
12575 enum attr_sync_insn2 insn2
;
12578 enum memmodel model
;
12580 /* Read an operand from the sync_WHAT attribute and store it in
12581 variable WHAT. DEFAULT is the default value if no attribute
12583 #define READ_OPERAND(WHAT, DEFAULT) \
12584 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12587 /* Read the memory. */
12588 READ_OPERAND (mem
, 0);
12590 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
12592 /* Read the other attributes. */
12593 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
12594 READ_OPERAND (oldval
, at
);
12595 READ_OPERAND (cmp
, 0);
12596 READ_OPERAND (newval
, at
);
12597 READ_OPERAND (inclusive_mask
, 0);
12598 READ_OPERAND (exclusive_mask
, 0);
12599 READ_OPERAND (required_oldval
, 0);
12600 READ_OPERAND (insn1_op2
, 0);
12601 insn1
= get_attr_sync_insn1 (insn
);
12602 insn2
= get_attr_sync_insn2 (insn
);
12604 /* Don't bother setting CMP result that is never used. */
12605 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
12608 memmodel_attr
= get_attr_sync_memmodel (insn
);
12609 switch (memmodel_attr
)
12612 model
= MEMMODEL_ACQ_REL
;
12615 model
= MEMMODEL_ACQUIRE
;
12618 model
= (enum memmodel
) INTVAL (operands
[memmodel_attr
]);
12621 mips_multi_start ();
12623 /* Output the release side of the memory barrier. */
12624 if (need_atomic_barrier_p (model
, true))
12626 if (required_oldval
== 0 && TARGET_OCTEON
)
12628 /* Octeon doesn't reorder reads, so a full barrier can be
12629 created by using SYNCW to order writes combined with the
12630 write from the following SC. When the SC successfully
12631 completes, we know that all preceding writes are also
12632 committed to the coherent memory system. It is possible
12633 for a single SYNCW to fail, but a pair of them will never
12634 fail, so we use two. */
12635 mips_multi_add_insn ("syncw", NULL
);
12636 mips_multi_add_insn ("syncw", NULL
);
12639 mips_multi_add_insn ("sync", NULL
);
12642 /* Output the branch-back label. */
12643 mips_multi_add_label ("1:");
12645 /* OLDVAL = *MEM. */
12646 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
12647 oldval
, mem
, NULL
);
12649 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12650 if (required_oldval
)
12652 if (inclusive_mask
== 0)
12656 gcc_assert (oldval
!= at
);
12657 mips_multi_add_insn ("and\t%0,%1,%2",
12658 at
, oldval
, inclusive_mask
, NULL
);
12661 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
12663 /* CMP = 0 [delay slot]. */
12665 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
12668 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12669 if (exclusive_mask
== 0)
12673 gcc_assert (oldval
!= at
);
12674 mips_multi_add_insn ("and\t%0,%1,%z2",
12675 at
, oldval
, exclusive_mask
, NULL
);
12679 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12681 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12682 at least one instruction in that case. */
12683 if (insn1
== SYNC_INSN1_MOVE
12684 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
12688 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
12689 newval
, oldval
, insn1_op2
, NULL
);
12693 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12694 if (insn2
== SYNC_INSN2_NOP
)
12698 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
12699 newval
, tmp2
, inclusive_mask
, NULL
);
12702 tmp3_insn
= mips_multi_last_index ();
12704 /* $AT = $TMP1 | $TMP3. */
12705 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
12707 mips_multi_set_operand (tmp3_insn
, 0, at
);
12712 gcc_assert (tmp1
!= tmp3
);
12713 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
12716 /* if (!commit (*MEM = $AT)) goto 1.
12718 This will sometimes be a delayed branch; see the write code below
12720 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
12721 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
12723 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12724 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
12726 mips_multi_copy_insn (tmp3_insn
);
12727 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
12729 else if (!(required_oldval
&& cmp
))
12730 mips_multi_add_insn ("nop", NULL
);
12732 /* CMP = 1 -- either standalone or in a delay slot. */
12733 if (required_oldval
&& cmp
)
12734 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
12736 /* Output the acquire side of the memory barrier. */
12737 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
12738 mips_multi_add_insn ("sync", NULL
);
12740 /* Output the exit label, if needed. */
12741 if (required_oldval
)
12742 mips_multi_add_label ("2:");
12744 #undef READ_OPERAND
12747 /* Output and/or return the asm template for sync loop INSN, which has
12748 the operands given by OPERANDS. */
12751 mips_output_sync_loop (rtx insn
, rtx
*operands
)
12753 mips_process_sync_loop (insn
, operands
);
12755 /* Use branch-likely instructions to work around the LL/SC R10000
12757 mips_branch_likely
= TARGET_FIX_R10000
;
12759 mips_push_asm_switch (&mips_noreorder
);
12760 mips_push_asm_switch (&mips_nomacro
);
12761 mips_push_asm_switch (&mips_noat
);
12762 mips_start_ll_sc_sync_block ();
12764 mips_multi_write ();
12766 mips_end_ll_sc_sync_block ();
12767 mips_pop_asm_switch (&mips_noat
);
12768 mips_pop_asm_switch (&mips_nomacro
);
12769 mips_pop_asm_switch (&mips_noreorder
);
12774 /* Return the number of individual instructions in sync loop INSN,
12775 which has the operands given by OPERANDS. */
12778 mips_sync_loop_insns (rtx insn
, rtx
*operands
)
12780 mips_process_sync_loop (insn
, operands
);
12781 return mips_multi_num_insns
;
12784 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12785 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12787 When working around R4000 and R4400 errata, we need to make sure that
12788 the division is not immediately followed by a shift[1][2]. We also
12789 need to stop the division from being put into a branch delay slot[3].
12790 The easiest way to avoid both problems is to add a nop after the
12791 division. When a divide-by-zero check is needed, this nop can be
12792 used to fill the branch delay slot.
12794 [1] If a double-word or a variable shift executes immediately
12795 after starting an integer division, the shift may give an
12796 incorrect result. See quotations of errata #16 and #28 from
12797 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12798 in mips.md for details.
12800 [2] A similar bug to [1] exists for all revisions of the
12801 R4000 and the R4400 when run in an MC configuration.
12802 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12804 "19. In this following sequence:
12806 ddiv (or ddivu or div or divu)
12807 dsll32 (or dsrl32, dsra32)
12809 if an MPT stall occurs, while the divide is slipping the cpu
12810 pipeline, then the following double shift would end up with an
12813 Workaround: The compiler needs to avoid generating any
12814 sequence with divide followed by extended double shift."
12816 This erratum is also present in "MIPS R4400MC Errata, Processor
12817 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12818 & 3.0" as errata #10 and #4, respectively.
12820 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12821 (also valid for MIPS R4000MC processors):
12823 "52. R4000SC: This bug does not apply for the R4000PC.
12825 There are two flavors of this bug:
12827 1) If the instruction just after divide takes an RF exception
12828 (tlb-refill, tlb-invalid) and gets an instruction cache
12829 miss (both primary and secondary) and the line which is
12830 currently in secondary cache at this index had the first
12831 data word, where the bits 5..2 are set, then R4000 would
12832 get a wrong result for the div.
12837 ------------------- # end-of page. -tlb-refill
12842 ------------------- # end-of page. -tlb-invalid
12845 2) If the divide is in the taken branch delay slot, where the
12846 target takes RF exception and gets an I-cache miss for the
12847 exception vector or where I-cache miss occurs for the
12848 target address, under the above mentioned scenarios, the
12849 div would get wrong results.
12852 j r2 # to next page mapped or unmapped
12853 div r8,r9 # this bug would be there as long
12854 # as there is an ICache miss and
12855 nop # the "data pattern" is present
12858 beq r0, r0, NextPage # to Next page
12862 This bug is present for div, divu, ddiv, and ddivu
12865 Workaround: For item 1), OS could make sure that the next page
12866 after the divide instruction is also mapped. For item 2), the
12867 compiler could make sure that the divide instruction is not in
12868 the branch delay slot."
12870 These processors have PRId values of 0x00004220 and 0x00004300 for
12871 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12874 mips_output_division (const char *division
, rtx
*operands
)
12879 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
12881 output_asm_insn (s
, operands
);
12884 if (TARGET_CHECK_ZERO_DIV
)
12888 output_asm_insn (s
, operands
);
12889 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
12891 else if (GENERATE_DIVIDE_TRAPS
)
12893 /* Avoid long replay penalty on load miss by putting the trap before
12896 output_asm_insn ("teq\t%2,%.,7", operands
);
12899 output_asm_insn (s
, operands
);
12900 s
= "teq\t%2,%.,7";
12905 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
12906 output_asm_insn (s
, operands
);
12907 s
= "break\t7%)\n1:";
12913 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12914 instruction and if OUT_INSN assigns to the accumulator operand. */
12917 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
12919 enum attr_accum_in accum_in
;
12920 int accum_in_opnum
;
12923 if (recog_memoized (in_insn
) < 0)
12926 accum_in
= get_attr_accum_in (in_insn
);
12927 if (accum_in
== ACCUM_IN_NONE
)
12930 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
12932 extract_insn (in_insn
);
12933 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
12934 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
12936 return reg_set_p (accum_in_op
, out_insn
);
12939 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12940 data rather than the address. We need this because the cprestore
12941 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12942 which causes the default routine to abort. We just return false
12946 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
12948 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
12951 return !store_data_bypass_p (out_insn
, in_insn
);
12955 /* Variables and flags used in scheduler hooks when tuning for
12959 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12962 /* If true, then next ALU1/2 instruction will go to ALU1. */
12965 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12968 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12969 int alu1_core_unit_code
;
12970 int alu2_core_unit_code
;
12971 int falu1_core_unit_code
;
12972 int falu2_core_unit_code
;
12974 /* True if current cycle has a multi instruction.
12975 This flag is used in mips_ls2_dfa_post_advance_cycle. */
12976 bool cycle_has_multi_p
;
12978 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
12979 These are used in mips_ls2_dfa_post_advance_cycle to initialize
12981 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
12982 instruction to go ALU1. */
12983 rtx alu1_turn_enabled_insn
;
12984 rtx alu2_turn_enabled_insn
;
12985 rtx falu1_turn_enabled_insn
;
12986 rtx falu2_turn_enabled_insn
;
12989 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12990 dependencies have no cost, except on the 20Kc where output-dependence
12991 is treated like input-dependence. */
12994 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
12995 rtx dep ATTRIBUTE_UNUSED
, int cost
)
12997 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
13000 if (REG_NOTE_KIND (link
) != 0)
13005 /* Return the number of instructions that can be issued per cycle. */
13008 mips_issue_rate (void)
13012 case PROCESSOR_74KC
:
13013 case PROCESSOR_74KF2_1
:
13014 case PROCESSOR_74KF1_1
:
13015 case PROCESSOR_74KF3_2
:
13016 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13017 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13018 but in reality only a maximum of 3 insns can be issued as
13019 floating-point loads and stores also require a slot in the
13021 case PROCESSOR_R10000
:
13022 /* All R10K Processors are quad-issue (being the first MIPS
13023 processors to support this feature). */
13026 case PROCESSOR_20KC
:
13027 case PROCESSOR_R4130
:
13028 case PROCESSOR_R5400
:
13029 case PROCESSOR_R5500
:
13030 case PROCESSOR_R5900
:
13031 case PROCESSOR_R7000
:
13032 case PROCESSOR_R9000
:
13033 case PROCESSOR_OCTEON
:
13034 case PROCESSOR_OCTEON2
:
13037 case PROCESSOR_SB1
:
13038 case PROCESSOR_SB1A
:
13039 /* This is actually 4, but we get better performance if we claim 3.
13040 This is partly because of unwanted speculative code motion with the
13041 larger number, and partly because in most common cases we can't
13042 reach the theoretical max of 4. */
13045 case PROCESSOR_LOONGSON_2E
:
13046 case PROCESSOR_LOONGSON_2F
:
13047 case PROCESSOR_LOONGSON_3A
:
13050 case PROCESSOR_XLP
:
13051 return (reload_completed
? 4 : 3);
13058 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13061 mips_ls2_init_dfa_post_cycle_insn (void)
13064 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13065 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
13069 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13070 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
13074 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13075 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
13079 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13080 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
13083 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
13084 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
13085 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
13086 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
13089 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13090 Init data used in mips_dfa_post_advance_cycle. */
13093 mips_init_dfa_post_cycle_insn (void)
13095 if (TUNE_LOONGSON_2EF
)
13096 mips_ls2_init_dfa_post_cycle_insn ();
13099 /* Initialize STATE when scheduling for Loongson 2E/2F.
13100 Support round-robin dispatch scheme by enabling only one of
13101 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13105 mips_ls2_dfa_post_advance_cycle (state_t state
)
13107 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
13109 /* Though there are no non-pipelined ALU1 insns,
13110 we can get an instruction of type 'multi' before reload. */
13111 gcc_assert (mips_ls2
.cycle_has_multi_p
);
13112 mips_ls2
.alu1_turn_p
= false;
13115 mips_ls2
.cycle_has_multi_p
= false;
13117 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
13118 /* We have a non-pipelined alu instruction in the core,
13119 adjust round-robin counter. */
13120 mips_ls2
.alu1_turn_p
= true;
13122 if (mips_ls2
.alu1_turn_p
)
13124 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
13125 gcc_unreachable ();
13129 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
13130 gcc_unreachable ();
13133 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
13135 /* There are no non-pipelined FALU1 insns. */
13136 gcc_unreachable ();
13137 mips_ls2
.falu1_turn_p
= false;
13140 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
13141 /* We have a non-pipelined falu instruction in the core,
13142 adjust round-robin counter. */
13143 mips_ls2
.falu1_turn_p
= true;
13145 if (mips_ls2
.falu1_turn_p
)
13147 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
13148 gcc_unreachable ();
13152 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
13153 gcc_unreachable ();
13157 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13158 This hook is being called at the start of each cycle. */
13161 mips_dfa_post_advance_cycle (void)
13163 if (TUNE_LOONGSON_2EF
)
13164 mips_ls2_dfa_post_advance_cycle (curr_state
);
13167 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13168 be as wide as the scheduling freedom in the DFA. */
13171 mips_multipass_dfa_lookahead (void)
13173 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13177 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
13186 /* Remove the instruction at index LOWER from ready queue READY and
13187 reinsert it in front of the instruction at index HIGHER. LOWER must
13191 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
13196 new_head
= ready
[lower
];
13197 for (i
= lower
; i
< higher
; i
++)
13198 ready
[i
] = ready
[i
+ 1];
13199 ready
[i
] = new_head
;
13202 /* If the priority of the instruction at POS2 in the ready queue READY
13203 is within LIMIT units of that of the instruction at POS1, swap the
13204 instructions if POS2 is not already less than POS1. */
13207 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
13210 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
13214 temp
= ready
[pos1
];
13215 ready
[pos1
] = ready
[pos2
];
13216 ready
[pos2
] = temp
;
13220 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13221 that may clobber hi or lo. */
13222 static rtx mips_macc_chains_last_hilo
;
13224 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13225 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13228 mips_macc_chains_record (rtx insn
)
13230 if (get_attr_may_clobber_hilo (insn
))
13231 mips_macc_chains_last_hilo
= insn
;
13234 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13235 has NREADY elements, looking for a multiply-add or multiply-subtract
13236 instruction that is cumulative with mips_macc_chains_last_hilo.
13237 If there is one, promote it ahead of anything else that might
13238 clobber hi or lo. */
13241 mips_macc_chains_reorder (rtx
*ready
, int nready
)
13245 if (mips_macc_chains_last_hilo
!= 0)
13246 for (i
= nready
- 1; i
>= 0; i
--)
13247 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
13249 for (j
= nready
- 1; j
> i
; j
--)
13250 if (recog_memoized (ready
[j
]) >= 0
13251 && get_attr_may_clobber_hilo (ready
[j
]))
13253 mips_promote_ready (ready
, i
, j
);
13260 /* The last instruction to be scheduled. */
13261 static rtx vr4130_last_insn
;
13263 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13264 points to an rtx that is initially an instruction. Nullify the rtx
13265 if the instruction uses the value of register X. */
13268 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13273 insn_ptr
= (rtx
*) data
;
13276 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
13280 /* Return true if there is true register dependence between vr4130_last_insn
13284 vr4130_true_reg_dependence_p (rtx insn
)
13286 note_stores (PATTERN (vr4130_last_insn
),
13287 vr4130_true_reg_dependence_p_1
, &insn
);
13291 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13292 the ready queue and that INSN2 is the instruction after it, return
13293 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13294 in which INSN1 and INSN2 can probably issue in parallel, but for
13295 which (INSN2, INSN1) should be less sensitive to instruction
13296 alignment than (INSN1, INSN2). See 4130.md for more details. */
13299 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
13301 sd_iterator_def sd_it
;
13304 /* Check for the following case:
13306 1) there is some other instruction X with an anti dependence on INSN1;
13307 2) X has a higher priority than INSN2; and
13308 3) X is an arithmetic instruction (and thus has no unit restrictions).
13310 If INSN1 is the last instruction blocking X, it would better to
13311 choose (INSN1, X) over (INSN2, INSN1). */
13312 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
13313 if (DEP_TYPE (dep
) == REG_DEP_ANTI
13314 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
13315 && recog_memoized (DEP_CON (dep
)) >= 0
13316 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
13319 if (vr4130_last_insn
!= 0
13320 && recog_memoized (insn1
) >= 0
13321 && recog_memoized (insn2
) >= 0)
13323 /* See whether INSN1 and INSN2 use different execution units,
13324 or if they are both ALU-type instructions. If so, they can
13325 probably execute in parallel. */
13326 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
13327 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
13328 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
13330 /* If only one of the instructions has a dependence on
13331 vr4130_last_insn, prefer to schedule the other one first. */
13332 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
13333 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
13334 if (dep1_p
!= dep2_p
)
13337 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13338 is not an ALU-type instruction and if INSN1 uses the same
13339 execution unit. (Note that if this condition holds, we already
13340 know that INSN2 uses a different execution unit.) */
13341 if (class1
!= VR4130_CLASS_ALU
13342 && recog_memoized (vr4130_last_insn
) >= 0
13343 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
13350 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13351 queue with at least two instructions. Swap the first two if
13352 vr4130_swap_insns_p says that it could be worthwhile. */
13355 vr4130_reorder (rtx
*ready
, int nready
)
13357 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
13358 mips_promote_ready (ready
, nready
- 2, nready
- 1);
13361 /* Record whether last 74k AGEN instruction was a load or store. */
13362 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13364 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13365 resets to TYPE_UNKNOWN state. */
13368 mips_74k_agen_init (rtx insn
)
13370 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
13371 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13374 enum attr_type type
= get_attr_type (insn
);
13375 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
13376 mips_last_74k_agen_insn
= type
;
13380 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13381 loads to be grouped together, and multiple stores to be grouped
13382 together. Swap things around in the ready queue to make this happen. */
13385 mips_74k_agen_reorder (rtx
*ready
, int nready
)
13388 int store_pos
, load_pos
;
13393 for (i
= nready
- 1; i
>= 0; i
--)
13395 rtx insn
= ready
[i
];
13396 if (USEFUL_INSN_P (insn
))
13397 switch (get_attr_type (insn
))
13400 if (store_pos
== -1)
13405 if (load_pos
== -1)
13414 if (load_pos
== -1 || store_pos
== -1)
13417 switch (mips_last_74k_agen_insn
)
13420 /* Prefer to schedule loads since they have a higher latency. */
13422 /* Swap loads to the front of the queue. */
13423 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
13426 /* Swap stores to the front of the queue. */
13427 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
13434 /* Implement TARGET_SCHED_INIT. */
13437 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13438 int max_ready ATTRIBUTE_UNUSED
)
13440 mips_macc_chains_last_hilo
= 0;
13441 vr4130_last_insn
= 0;
13442 mips_74k_agen_init (NULL_RTX
);
13444 /* When scheduling for Loongson2, branch instructions go to ALU1,
13445 therefore basic block is most likely to start with round-robin counter
13446 pointed to ALU2. */
13447 mips_ls2
.alu1_turn_p
= false;
13448 mips_ls2
.falu1_turn_p
= true;
13451 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13454 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13455 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13457 if (!reload_completed
13458 && TUNE_MACC_CHAINS
13460 mips_macc_chains_reorder (ready
, *nreadyp
);
13462 if (reload_completed
13464 && !TARGET_VR4130_ALIGN
13466 vr4130_reorder (ready
, *nreadyp
);
13469 mips_74k_agen_reorder (ready
, *nreadyp
);
13472 /* Implement TARGET_SCHED_REORDER. */
13475 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13476 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13478 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13479 return mips_issue_rate ();
13482 /* Implement TARGET_SCHED_REORDER2. */
13485 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13486 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13488 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13489 return cached_can_issue_more
;
13492 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13495 mips_ls2_variable_issue (rtx insn
)
13497 if (mips_ls2
.alu1_turn_p
)
13499 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
13500 mips_ls2
.alu1_turn_p
= false;
13504 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
13505 mips_ls2
.alu1_turn_p
= true;
13508 if (mips_ls2
.falu1_turn_p
)
13510 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
13511 mips_ls2
.falu1_turn_p
= false;
13515 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
13516 mips_ls2
.falu1_turn_p
= true;
13519 if (recog_memoized (insn
) >= 0)
13520 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
13523 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13526 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13527 rtx insn
, int more
)
13529 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13530 if (USEFUL_INSN_P (insn
))
13532 if (get_attr_type (insn
) != TYPE_GHOST
)
13534 if (!reload_completed
&& TUNE_MACC_CHAINS
)
13535 mips_macc_chains_record (insn
);
13536 vr4130_last_insn
= insn
;
13538 mips_74k_agen_init (insn
);
13539 else if (TUNE_LOONGSON_2EF
)
13540 mips_ls2_variable_issue (insn
);
13543 /* Instructions of type 'multi' should all be split before
13544 the second scheduling pass. */
13545 gcc_assert (!reload_completed
13546 || recog_memoized (insn
) < 0
13547 || get_attr_type (insn
) != TYPE_MULTI
);
13549 cached_can_issue_more
= more
;
13553 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13554 return the first operand of the associated PREF or PREFX insn. */
13557 mips_prefetch_cookie (rtx write
, rtx locality
)
13559 /* store_streamed / load_streamed. */
13560 if (INTVAL (locality
) <= 0)
13561 return GEN_INT (INTVAL (write
) + 4);
13563 /* store / load. */
13564 if (INTVAL (locality
) <= 2)
13567 /* store_retained / load_retained. */
13568 return GEN_INT (INTVAL (write
) + 6);
13571 /* Flags that indicate when a built-in function is available.
13573 BUILTIN_AVAIL_NON_MIPS16
13574 The function is available on the current target, but only
13575 in non-MIPS16 mode. */
13576 #define BUILTIN_AVAIL_NON_MIPS16 1
13578 /* Declare an availability predicate for built-in functions that
13579 require non-MIPS16 mode and also require COND to be true.
13580 NAME is the main part of the predicate's name. */
13581 #define AVAIL_NON_MIPS16(NAME, COND) \
13582 static unsigned int \
13583 mips_builtin_avail_##NAME (void) \
13585 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13588 /* This structure describes a single built-in function. */
13589 struct mips_builtin_description
{
13590 /* The code of the main .md file instruction. See mips_builtin_type
13591 for more information. */
13592 enum insn_code icode
;
13594 /* The floating-point comparison code to use with ICODE, if any. */
13595 enum mips_fp_condition cond
;
13597 /* The name of the built-in function. */
13600 /* Specifies how the function should be expanded. */
13601 enum mips_builtin_type builtin_type
;
13603 /* The function's prototype. */
13604 enum mips_function_type function_type
;
13606 /* Whether the function is available. */
13607 unsigned int (*avail
) (void);
13610 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
13611 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
13612 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
13613 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
13614 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
13615 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
13616 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
13617 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
13618 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
13619 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
13621 /* Construct a mips_builtin_description from the given arguments.
13623 INSN is the name of the associated instruction pattern, without the
13624 leading CODE_FOR_mips_.
13626 CODE is the floating-point condition code associated with the
13627 function. It can be 'f' if the field is not applicable.
13629 NAME is the name of the function itself, without the leading
13632 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13634 AVAIL is the name of the availability predicate, without the leading
13635 mips_builtin_avail_. */
13636 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13637 FUNCTION_TYPE, AVAIL) \
13638 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13639 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13640 mips_builtin_avail_ ## AVAIL }
13642 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13643 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13644 are as for MIPS_BUILTIN. */
13645 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13646 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13648 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13649 are subject to mips_builtin_avail_<AVAIL>. */
13650 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13651 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13652 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13653 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13654 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13656 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13657 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13658 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13659 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13660 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13661 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13663 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13664 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13666 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13667 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13669 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13670 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13673 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13674 are subject to mips_builtin_avail_mips3d. */
13675 #define CMP_4S_BUILTINS(INSN, COND) \
13676 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13677 MIPS_BUILTIN_CMP_ANY, \
13678 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13679 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13680 MIPS_BUILTIN_CMP_ALL, \
13681 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13683 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13684 instruction requires mips_builtin_avail_<AVAIL>. */
13685 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13686 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13687 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13689 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13690 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13693 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13694 #define CMP_BUILTINS(COND) \
13695 MOVTF_BUILTINS (c, COND, paired_single), \
13696 MOVTF_BUILTINS (cabs, COND, mips3d), \
13697 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13698 CMP_PS_BUILTINS (c, COND, paired_single), \
13699 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13700 CMP_4S_BUILTINS (c, COND), \
13701 CMP_4S_BUILTINS (cabs, COND)
13703 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13704 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13705 and AVAIL are as for MIPS_BUILTIN. */
13706 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13707 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13708 FUNCTION_TYPE, AVAIL)
13710 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13711 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13712 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13713 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13714 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13716 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13717 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13718 builtin_description field. */
13719 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13720 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13721 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13722 FUNCTION_TYPE, mips_builtin_avail_loongson }
13724 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13725 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13726 builtin_description field. */
13727 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13728 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13730 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13731 We use functions of this form when the same insn can be usefully applied
13732 to more than one datatype. */
13733 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13734 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13736 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13737 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13738 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13739 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13740 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13741 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13742 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13743 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13745 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13746 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13747 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13748 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13749 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13750 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13751 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13752 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13753 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13754 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13755 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13756 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13757 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13758 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13759 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13760 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13761 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13762 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13763 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13764 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13765 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13766 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13767 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13768 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13769 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13770 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13771 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13772 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13773 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13774 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13776 static const struct mips_builtin_description mips_builtins
[] = {
13777 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13778 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13779 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13780 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13781 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
13782 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13783 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13784 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
13786 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
13787 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13788 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13789 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13790 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13792 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13793 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13794 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13795 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13796 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13797 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13799 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13800 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13801 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13802 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13803 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13804 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13806 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
13808 /* Built-in functions for the SB-1 processor. */
13809 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
13811 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13812 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13813 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13814 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13815 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13816 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13817 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13818 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13819 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13820 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13821 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13822 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13823 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13824 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13825 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
13826 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
13827 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
13828 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13829 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13830 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13831 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13832 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
13833 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
13834 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13835 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13836 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13837 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13838 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13839 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13840 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13841 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13842 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13843 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13844 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13845 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13846 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13847 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13848 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13849 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13850 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13851 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13852 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13853 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13854 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13855 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
13856 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13857 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
13858 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
13859 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13860 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13861 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13862 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13863 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13864 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13865 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13866 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13867 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13868 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13869 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13870 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13871 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
13872 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
13873 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13874 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13875 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13876 BPOSGE_BUILTIN (32, dsp
),
13878 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13879 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
13880 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13881 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13882 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13883 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13884 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13885 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13886 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13887 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13888 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13889 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13890 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13891 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13892 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13893 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13894 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
13895 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13896 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13897 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13898 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13899 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13900 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
13901 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13902 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13903 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13904 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13905 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13906 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13907 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13908 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13909 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13910 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13911 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13912 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13914 /* Built-in functions for the DSP ASE (32-bit only). */
13915 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13916 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13917 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13918 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13919 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13920 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13921 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13922 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13923 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13924 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13925 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13926 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13927 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13928 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13929 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13930 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13931 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13932 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13933 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13934 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13935 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13936 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13937 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13938 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13939 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13940 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
13941 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
13943 /* Built-in functions for the DSP ASE (64-bit only). */
13944 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
13946 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13947 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13948 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13949 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13950 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13951 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13952 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13953 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13954 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13955 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13957 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13958 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
13959 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
13960 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
13961 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13962 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13963 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13964 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13965 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13966 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13967 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
13968 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
13969 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13970 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13971 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13972 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13973 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
13974 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13975 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13976 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13977 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
13978 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13979 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13980 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13981 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13982 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13983 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13984 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13985 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13986 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13987 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13988 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13989 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13990 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13991 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13992 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13993 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13994 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13995 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
13996 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
13997 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13998 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13999 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14000 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14001 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14002 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14003 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14004 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14005 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
14006 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14007 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14008 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14009 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14010 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
14011 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
14012 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14013 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14014 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14015 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
14016 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14017 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
14018 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
14019 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14020 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14021 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14022 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14023 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14024 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14025 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14026 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14027 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14028 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14029 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14030 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14031 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14032 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14033 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14034 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14035 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14036 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14037 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14038 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14039 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14040 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
14041 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14042 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14043 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14044 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14045 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14046 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14047 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14048 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14049 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14050 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14051 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14052 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14053 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14054 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14055 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14056 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14058 /* Sundry other built-in functions. */
14059 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
14062 /* Index I is the function declaration for mips_builtins[I], or null if the
14063 function isn't defined on this target. */
14064 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
14066 /* MODE is a vector mode whose elements have type TYPE. Return the type
14067 of the vector itself. */
14070 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
14072 static tree types
[2 * (int) MAX_MACHINE_MODE
];
14075 mode_index
= (int) mode
;
14077 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
14078 mode_index
+= MAX_MACHINE_MODE
;
14080 if (types
[mode_index
] == NULL_TREE
)
14081 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
14082 return types
[mode_index
];
14085 /* Return a type for 'const volatile void *'. */
14088 mips_build_cvpointer_type (void)
14092 if (cache
== NULL_TREE
)
14093 cache
= build_pointer_type (build_qualified_type
14095 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
14099 /* Source-level argument types. */
14100 #define MIPS_ATYPE_VOID void_type_node
14101 #define MIPS_ATYPE_INT integer_type_node
14102 #define MIPS_ATYPE_POINTER ptr_type_node
14103 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14105 /* Standard mode-based argument types. */
14106 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14107 #define MIPS_ATYPE_SI intSI_type_node
14108 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14109 #define MIPS_ATYPE_DI intDI_type_node
14110 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14111 #define MIPS_ATYPE_SF float_type_node
14112 #define MIPS_ATYPE_DF double_type_node
14114 /* Vector argument types. */
14115 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14116 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14117 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14118 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14119 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14120 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14121 #define MIPS_ATYPE_UV2SI \
14122 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14123 #define MIPS_ATYPE_UV4HI \
14124 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14125 #define MIPS_ATYPE_UV8QI \
14126 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14128 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14129 their associated MIPS_ATYPEs. */
14130 #define MIPS_FTYPE_ATYPES1(A, B) \
14131 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14133 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14134 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14136 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14137 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14139 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14140 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14143 /* Return the function type associated with function prototype TYPE. */
14146 mips_build_function_type (enum mips_function_type type
)
14148 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
14150 if (types
[(int) type
] == NULL_TREE
)
14153 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14154 case MIPS_FTYPE_NAME##NUM ARGS: \
14155 types[(int) type] \
14156 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14159 #include "config/mips/mips-ftypes.def"
14160 #undef DEF_MIPS_FTYPE
14162 gcc_unreachable ();
14165 return types
[(int) type
];
14168 /* Implement TARGET_INIT_BUILTINS. */
14171 mips_init_builtins (void)
14173 const struct mips_builtin_description
*d
;
14176 /* Iterate through all of the bdesc arrays, initializing all of the
14177 builtin functions. */
14178 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
14180 d
= &mips_builtins
[i
];
14182 mips_builtin_decls
[i
]
14183 = add_builtin_function (d
->name
,
14184 mips_build_function_type (d
->function_type
),
14185 i
, BUILT_IN_MD
, NULL
, NULL
);
14189 /* Implement TARGET_BUILTIN_DECL. */
14192 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
14194 if (code
>= ARRAY_SIZE (mips_builtins
))
14195 return error_mark_node
;
14196 return mips_builtin_decls
[code
];
14199 /* Take argument ARGNO from EXP's argument list and convert it into
14200 an expand operand. Store the operand in *OP. */
14203 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
14204 unsigned int argno
)
14209 arg
= CALL_EXPR_ARG (exp
, argno
);
14210 value
= expand_normal (arg
);
14211 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
14214 /* Expand instruction ICODE as part of a built-in function sequence.
14215 Use the first NOPS elements of OPS as the instruction's operands.
14216 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14217 instruction has no target.
14219 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14222 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
14223 struct expand_operand
*ops
, bool has_target_p
)
14225 if (!maybe_expand_insn (icode
, nops
, ops
))
14227 error ("invalid argument to built-in function");
14228 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
14230 return has_target_p
? ops
[0].value
: const0_rtx
;
14233 /* Expand a floating-point comparison for built-in function call EXP.
14234 The first NARGS arguments are the values to be compared. ICODE is
14235 the .md pattern that does the comparison and COND is the condition
14236 that is being tested. Return an rtx for the result. */
14239 mips_expand_builtin_compare_1 (enum insn_code icode
,
14240 enum mips_fp_condition cond
,
14241 tree exp
, int nargs
)
14243 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14247 /* The instruction should have a target operand, an operand for each
14248 argument, and an operand for COND. */
14249 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
14251 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
14253 create_fixed_operand (&ops
[opno
++], output
);
14254 for (argno
= 0; argno
< nargs
; argno
++)
14255 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14256 create_integer_operand (&ops
[opno
++], (int) cond
);
14257 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
14260 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14261 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14262 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14263 suggests a good place to put the result. */
14266 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
14269 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14272 /* Map any target to operand 0. */
14275 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
14277 /* Map the arguments to the other operands. */
14278 gcc_assert (opno
+ call_expr_nargs (exp
)
14279 == insn_data
[icode
].n_generator_args
);
14280 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
14281 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14283 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
14286 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14287 function; TYPE says which. EXP is the CALL_EXPR that calls the
14288 function, ICODE is the instruction that should be used to compare
14289 the first two arguments, and COND is the condition it should test.
14290 TARGET, if nonnull, suggests a good place to put the result. */
14293 mips_expand_builtin_movtf (enum mips_builtin_type type
,
14294 enum insn_code icode
, enum mips_fp_condition cond
,
14295 rtx target
, tree exp
)
14297 struct expand_operand ops
[4];
14300 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
14301 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
14302 if (type
== MIPS_BUILTIN_MOVT
)
14304 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
14305 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
14309 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
14310 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
14312 create_fixed_operand (&ops
[3], cmp_result
);
14313 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
14317 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14318 into TARGET otherwise. Return TARGET. */
14321 mips_builtin_branch_and_move (rtx condition
, rtx target
,
14322 rtx value_if_true
, rtx value_if_false
)
14324 rtx true_label
, done_label
;
14326 true_label
= gen_label_rtx ();
14327 done_label
= gen_label_rtx ();
14329 /* First assume that CONDITION is false. */
14330 mips_emit_move (target
, value_if_false
);
14332 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14333 emit_jump_insn (gen_condjump (condition
, true_label
));
14334 emit_jump_insn (gen_jump (done_label
));
14337 /* Fix TARGET if CONDITION is true. */
14338 emit_label (true_label
);
14339 mips_emit_move (target
, value_if_true
);
14341 emit_label (done_label
);
14345 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14346 the CALL_EXPR that calls the function, ICODE is the code of the
14347 comparison instruction, and COND is the condition it should test.
14348 TARGET, if nonnull, suggests a good place to put the boolean result. */
14351 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
14352 enum insn_code icode
, enum mips_fp_condition cond
,
14353 rtx target
, tree exp
)
14355 rtx offset
, condition
, cmp_result
;
14357 if (target
== 0 || GET_MODE (target
) != SImode
)
14358 target
= gen_reg_rtx (SImode
);
14359 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
14360 call_expr_nargs (exp
));
14362 /* If the comparison sets more than one register, we define the result
14363 to be 0 if all registers are false and -1 if all registers are true.
14364 The value of the complete result is indeterminate otherwise. */
14365 switch (builtin_type
)
14367 case MIPS_BUILTIN_CMP_ALL
:
14368 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
14369 return mips_builtin_branch_and_move (condition
, target
,
14370 const0_rtx
, const1_rtx
);
14372 case MIPS_BUILTIN_CMP_UPPER
:
14373 case MIPS_BUILTIN_CMP_LOWER
:
14374 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
14375 condition
= gen_single_cc (cmp_result
, offset
);
14376 return mips_builtin_branch_and_move (condition
, target
,
14377 const1_rtx
, const0_rtx
);
14380 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
14381 return mips_builtin_branch_and_move (condition
, target
,
14382 const1_rtx
, const0_rtx
);
14386 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14387 if nonnull, suggests a good place to put the boolean result. */
14390 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
14392 rtx condition
, cmp_result
;
14395 if (target
== 0 || GET_MODE (target
) != SImode
)
14396 target
= gen_reg_rtx (SImode
);
14398 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
14400 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
14405 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
14406 return mips_builtin_branch_and_move (condition
, target
,
14407 const1_rtx
, const0_rtx
);
14410 /* Implement TARGET_EXPAND_BUILTIN. */
14413 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14414 enum machine_mode mode
, int ignore
)
14417 unsigned int fcode
, avail
;
14418 const struct mips_builtin_description
*d
;
14420 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14421 fcode
= DECL_FUNCTION_CODE (fndecl
);
14422 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
14423 d
= &mips_builtins
[fcode
];
14424 avail
= d
->avail ();
14425 gcc_assert (avail
!= 0);
14428 error ("built-in function %qE not supported for MIPS16",
14429 DECL_NAME (fndecl
));
14430 return ignore
? const0_rtx
: CONST0_RTX (mode
);
14432 switch (d
->builtin_type
)
14434 case MIPS_BUILTIN_DIRECT
:
14435 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
14437 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
14438 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
14440 case MIPS_BUILTIN_MOVT
:
14441 case MIPS_BUILTIN_MOVF
:
14442 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
14443 d
->cond
, target
, exp
);
14445 case MIPS_BUILTIN_CMP_ANY
:
14446 case MIPS_BUILTIN_CMP_ALL
:
14447 case MIPS_BUILTIN_CMP_UPPER
:
14448 case MIPS_BUILTIN_CMP_LOWER
:
14449 case MIPS_BUILTIN_CMP_SINGLE
:
14450 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
14451 d
->cond
, target
, exp
);
14453 case MIPS_BUILTIN_BPOSGE32
:
14454 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
14456 gcc_unreachable ();
14459 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14460 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14461 struct mips16_constant
{
14462 struct mips16_constant
*next
;
14465 enum machine_mode mode
;
14468 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14469 first constant, HIGHEST_ADDRESS is the highest address that the first
14470 byte of the pool can have, and INSN_ADDRESS is the current instruction
14472 struct mips16_constant_pool
{
14473 struct mips16_constant
*first
;
14474 int highest_address
;
14478 /* Add constant VALUE to POOL and return its label. MODE is the
14479 value's mode (used for CONST_INTs, etc.). */
14482 mips16_add_constant (struct mips16_constant_pool
*pool
,
14483 rtx value
, enum machine_mode mode
)
14485 struct mips16_constant
**p
, *c
;
14486 bool first_of_size_p
;
14488 /* See whether the constant is already in the pool. If so, return the
14489 existing label, otherwise leave P pointing to the place where the
14490 constant should be added.
14492 Keep the pool sorted in increasing order of mode size so that we can
14493 reduce the number of alignments needed. */
14494 first_of_size_p
= true;
14495 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
14497 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
14498 return (*p
)->label
;
14499 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
14501 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
14502 first_of_size_p
= false;
14505 /* In the worst case, the constant needed by the earliest instruction
14506 will end up at the end of the pool. The entire pool must then be
14507 accessible from that instruction.
14509 When adding the first constant, set the pool's highest address to
14510 the address of the first out-of-range byte. Adjust this address
14511 downwards each time a new constant is added. */
14512 if (pool
->first
== 0)
14513 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14514 of the instruction with the lowest two bits clear. The base PC
14515 value for LDPC has the lowest three bits clear. Assume the worst
14516 case here; namely that the PC-relative instruction occupies the
14517 last 2 bytes in an aligned word. */
14518 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
14519 pool
->highest_address
-= GET_MODE_SIZE (mode
);
14520 if (first_of_size_p
)
14521 /* Take into account the worst possible padding due to alignment. */
14522 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
14524 /* Create a new entry. */
14525 c
= XNEW (struct mips16_constant
);
14528 c
->label
= gen_label_rtx ();
14535 /* Output constant VALUE after instruction INSN and return the last
14536 instruction emitted. MODE is the mode of the constant. */
14539 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
14541 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
14543 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
14544 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
14547 if (SCALAR_FLOAT_MODE_P (mode
))
14548 return emit_insn_after (gen_consttable_float (value
), insn
);
14550 if (VECTOR_MODE_P (mode
))
14554 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
14555 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
14556 CONST_VECTOR_ELT (value
, i
), insn
);
14560 gcc_unreachable ();
14563 /* Dump out the constants in CONSTANTS after INSN. */
14566 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
14568 struct mips16_constant
*c
, *next
;
14572 for (c
= constants
; c
!= NULL
; c
= next
)
14574 /* If necessary, increase the alignment of PC. */
14575 if (align
< GET_MODE_SIZE (c
->mode
))
14577 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
14578 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
14580 align
= GET_MODE_SIZE (c
->mode
);
14582 insn
= emit_label_after (c
->label
, insn
);
14583 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
14589 emit_barrier_after (insn
);
14592 /* Return the length of instruction INSN. */
14595 mips16_insn_length (rtx insn
)
14597 if (JUMP_TABLE_DATA_P (insn
))
14599 rtx body
= PATTERN (insn
);
14600 if (GET_CODE (body
) == ADDR_VEC
)
14601 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
14602 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
14603 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
14605 gcc_unreachable ();
14607 return get_attr_length (insn
);
14610 /* If *X is a symbolic constant that refers to the constant pool, add
14611 the constant to POOL and rewrite *X to use the constant's label. */
14614 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
14616 rtx base
, offset
, label
;
14618 split_const (*x
, &base
, &offset
);
14619 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
14621 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
14622 get_pool_mode (base
));
14623 base
= gen_rtx_LABEL_REF (Pmode
, label
);
14624 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
14628 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14629 INSN is the instruction we're rewriting and POOL points to the current
14631 struct mips16_rewrite_pool_refs_info
{
14633 struct mips16_constant_pool
*pool
;
14636 /* Rewrite *X so that constant pool references refer to the constant's
14637 label instead. DATA points to a mips16_rewrite_pool_refs_info
14641 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
14643 struct mips16_rewrite_pool_refs_info
*info
=
14644 (struct mips16_rewrite_pool_refs_info
*) data
;
14646 if (force_to_mem_operand (*x
, Pmode
))
14648 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
14649 validate_change (info
->insn
, x
, mem
, false);
14654 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
14658 /* Don't rewrite the __mips16_rdwr symbol. */
14659 if (GET_CODE (*x
) == UNSPEC
&& XINT (*x
, 1) == UNSPEC_TLS_GET_TP
)
14662 if (TARGET_MIPS16_TEXT_LOADS
)
14663 mips16_rewrite_pool_constant (info
->pool
, x
);
14665 return GET_CODE (*x
) == CONST
? -1 : 0;
14668 /* Return whether CFG is used in mips_reorg. */
14671 mips_cfg_in_reorg (void)
14673 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
14674 || TARGET_RELAX_PIC_CALLS
);
14677 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14678 otherwise assume that they are already split. */
14681 mips16_lay_out_constants (bool split_p
)
14683 struct mips16_constant_pool pool
;
14684 struct mips16_rewrite_pool_refs_info info
;
14687 if (!TARGET_MIPS16_PCREL_LOADS
)
14692 if (mips_cfg_in_reorg ())
14693 split_all_insns ();
14695 split_all_insns_noflow ();
14698 memset (&pool
, 0, sizeof (pool
));
14699 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14701 /* Rewrite constant pool references in INSN. */
14702 if (USEFUL_INSN_P (insn
))
14706 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
14709 pool
.insn_address
+= mips16_insn_length (insn
);
14711 if (pool
.first
!= NULL
)
14713 /* If there are no natural barriers between the first user of
14714 the pool and the highest acceptable address, we'll need to
14715 create a new instruction to jump around the constant pool.
14716 In the worst case, this instruction will be 4 bytes long.
14718 If it's too late to do this transformation after INSN,
14719 do it immediately before INSN. */
14720 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
14724 label
= gen_label_rtx ();
14726 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
14727 JUMP_LABEL (jump
) = label
;
14728 LABEL_NUSES (label
) = 1;
14729 barrier
= emit_barrier_after (jump
);
14731 emit_label_after (label
, barrier
);
14732 pool
.insn_address
+= 4;
14735 /* See whether the constant pool is now out of range of the first
14736 user. If so, output the constants after the previous barrier.
14737 Note that any instructions between BARRIER and INSN (inclusive)
14738 will use negative offsets to refer to the pool. */
14739 if (pool
.insn_address
> pool
.highest_address
)
14741 mips16_emit_constants (pool
.first
, barrier
);
14745 else if (BARRIER_P (insn
))
14749 mips16_emit_constants (pool
.first
, get_last_insn ());
14752 /* Return true if it is worth r10k_simplify_address's while replacing
14753 an address with X. We are looking for constants, and for addresses
14754 at a known offset from the incoming stack pointer. */
14757 r10k_simplified_address_p (rtx x
)
14759 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
14761 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
14764 /* X is an expression that appears in INSN. Try to use the UD chains
14765 to simplify it, returning the simplified form on success and the
14766 original form otherwise. Replace the incoming value of $sp with
14767 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14770 r10k_simplify_address (rtx x
, rtx insn
)
14772 rtx newx
, op0
, op1
, set
, def_insn
, note
;
14774 struct df_link
*defs
;
14779 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14780 if (op0
!= XEXP (x
, 0))
14781 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
14782 op0
, GET_MODE (XEXP (x
, 0)));
14784 else if (BINARY_P (x
))
14786 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14787 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
14788 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
14789 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
14791 else if (GET_CODE (x
) == LO_SUM
)
14793 /* LO_SUMs can be offset from HIGHs, if we know they won't
14794 overflow. See mips_classify_address for the rationale behind
14796 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14797 if (GET_CODE (op0
) == HIGH
)
14798 newx
= XEXP (x
, 1);
14800 else if (REG_P (x
))
14802 /* Uses are recorded by regno_reg_rtx, not X itself. */
14803 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
14805 defs
= DF_REF_CHAIN (use
);
14807 /* Require a single definition. */
14808 if (defs
&& defs
->next
== NULL
)
14811 if (DF_REF_IS_ARTIFICIAL (def
))
14813 /* Replace the incoming value of $sp with
14814 virtual_incoming_args_rtx. */
14815 if (x
== stack_pointer_rtx
14816 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR
)
14817 newx
= virtual_incoming_args_rtx
;
14819 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
14822 /* Make sure that DEF_INSN is a single set of REG. */
14823 def_insn
= DF_REF_INSN (def
);
14824 if (NONJUMP_INSN_P (def_insn
))
14826 set
= single_set (def_insn
);
14827 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
14829 /* Prefer to use notes, since the def-use chains
14830 are often shorter. */
14831 note
= find_reg_equal_equiv_note (def_insn
);
14833 newx
= XEXP (note
, 0);
14835 newx
= SET_SRC (set
);
14836 newx
= r10k_simplify_address (newx
, def_insn
);
14842 if (newx
&& r10k_simplified_address_p (newx
))
14847 /* Return true if ADDRESS is known to be an uncached address
14848 on R10K systems. */
14851 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
14853 unsigned HOST_WIDE_INT upper
;
14855 /* Check for KSEG1. */
14856 if (address
+ 0x60000000 < 0x20000000)
14859 /* Check for uncached XKPHYS addresses. */
14860 if (Pmode
== DImode
)
14862 upper
= (address
>> 40) & 0xf9ffff;
14863 if (upper
== 0x900000 || upper
== 0xb80000)
14869 /* Return true if we can prove that an access to address X in instruction
14870 INSN would be safe from R10K speculation. This X is a general
14871 expression; it might not be a legitimate address. */
14874 r10k_safe_address_p (rtx x
, rtx insn
)
14877 HOST_WIDE_INT offset_val
;
14879 x
= r10k_simplify_address (x
, insn
);
14881 /* Check for references to the stack frame. It doesn't really matter
14882 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14883 allows us to assume that accesses to any part of the eventual frame
14884 is safe from speculation at any point in the function. */
14885 mips_split_plus (x
, &base
, &offset_val
);
14886 if (base
== virtual_incoming_args_rtx
14887 && offset_val
>= -cfun
->machine
->frame
.total_size
14888 && offset_val
< cfun
->machine
->frame
.args_size
)
14891 /* Check for uncached addresses. */
14892 if (CONST_INT_P (x
))
14893 return r10k_uncached_address_p (INTVAL (x
));
14895 /* Check for accesses to a static object. */
14896 split_const (x
, &base
, &offset
);
14897 return offset_within_block_p (base
, INTVAL (offset
));
14900 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14901 an in-range access to an automatic variable, or to an object with
14902 a link-time-constant address. */
14905 r10k_safe_mem_expr_p (tree expr
, HOST_WIDE_INT offset
)
14907 HOST_WIDE_INT bitoffset
, bitsize
;
14908 tree inner
, var_offset
;
14909 enum machine_mode mode
;
14910 int unsigned_p
, volatile_p
;
14912 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
14913 &unsigned_p
, &volatile_p
, false);
14914 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
14917 offset
+= bitoffset
/ BITS_PER_UNIT
;
14918 return offset
>= 0 && offset
< tree_low_cst (DECL_SIZE_UNIT (inner
), 1);
14921 /* A for_each_rtx callback for which DATA points to the instruction
14922 containing *X. Stop the search if we find a MEM that is not safe
14923 from R10K speculation. */
14926 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
14935 && MEM_OFFSET_KNOWN_P (mem
)
14936 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
14939 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
14945 /* A note_stores callback for which DATA points to an instruction pointer.
14946 If *DATA is nonnull, make it null if it X contains a MEM that is not
14947 safe from R10K speculation. */
14950 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
14955 insn_ptr
= (rtx
*) data
;
14956 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
14957 *insn_ptr
= NULL_RTX
;
14960 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14961 Return nonzero if the call is not to a declared function. */
14964 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
14973 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
14979 /* Return true if instruction INSN needs to be protected by an R10K
14983 r10k_needs_protection_p (rtx insn
)
14986 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
14988 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
14990 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
14991 return insn
== NULL_RTX
;
14994 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
14997 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14998 edge is unconditional. */
15001 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
15006 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
15007 if (!single_succ_p (e
->src
)
15008 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
15009 || (e
->flags
& EDGE_COMPLEX
) != 0)
15014 /* Implement -mr10k-cache-barrier= for the current function. */
15017 r10k_insert_cache_barriers (void)
15019 int *rev_post_order
;
15022 sbitmap protected_bbs
;
15023 rtx insn
, end
, unprotected_region
;
15027 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15031 /* Calculate dominators. */
15032 calculate_dominance_info (CDI_DOMINATORS
);
15034 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15035 X is protected by a cache barrier. */
15036 protected_bbs
= sbitmap_alloc (last_basic_block
);
15037 bitmap_clear (protected_bbs
);
15039 /* Iterate over the basic blocks in reverse post-order. */
15040 rev_post_order
= XNEWVEC (int, last_basic_block
);
15041 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
15042 for (i
= 0; i
< n
; i
++)
15044 bb
= BASIC_BLOCK (rev_post_order
[i
]);
15046 /* If this block is only reached by unconditional edges, and if the
15047 source of every edge is protected, the beginning of the block is
15049 if (r10k_protected_bb_p (bb
, protected_bbs
))
15050 unprotected_region
= NULL_RTX
;
15052 unprotected_region
= pc_rtx
;
15053 end
= NEXT_INSN (BB_END (bb
));
15055 /* UNPROTECTED_REGION is:
15057 - null if we are processing a protected region,
15058 - pc_rtx if we are processing an unprotected region but have
15059 not yet found the first instruction in it
15060 - the first instruction in an unprotected region otherwise. */
15061 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
15063 if (unprotected_region
&& USEFUL_INSN_P (insn
))
15065 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
15066 /* This CACHE instruction protects the following code. */
15067 unprotected_region
= NULL_RTX
;
15070 /* See if INSN is the first instruction in this
15071 unprotected region. */
15072 if (unprotected_region
== pc_rtx
)
15073 unprotected_region
= insn
;
15075 /* See if INSN needs to be protected. If so,
15076 we must insert a cache barrier somewhere between
15077 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15078 clear which position is better performance-wise,
15079 but as a tie-breaker, we assume that it is better
15080 to allow delay slots to be back-filled where
15081 possible, and that it is better not to insert
15082 barriers in the middle of already-scheduled code.
15083 We therefore insert the barrier at the beginning
15085 if (r10k_needs_protection_p (insn
))
15087 emit_insn_before (gen_r10k_cache_barrier (),
15088 unprotected_region
);
15089 unprotected_region
= NULL_RTX
;
15095 /* The called function is not required to protect the exit path.
15096 The code that follows a call is therefore unprotected. */
15097 unprotected_region
= pc_rtx
;
15100 /* Record whether the end of this block is protected. */
15101 if (unprotected_region
== NULL_RTX
)
15102 bitmap_set_bit (protected_bbs
, bb
->index
);
15104 XDELETEVEC (rev_post_order
);
15106 sbitmap_free (protected_bbs
);
15108 free_dominance_info (CDI_DOMINATORS
);
15111 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15112 otherwise. If INSN has two call rtx, then store the second one in
15116 mips_call_expr_from_insn (rtx insn
, rtx
*second_call
)
15121 if (!CALL_P (insn
))
15124 x
= PATTERN (insn
);
15125 if (GET_CODE (x
) == PARALLEL
)
15127 /* Calls returning complex values have two CALL rtx. Look for the second
15128 one here, and return it via the SECOND_CALL arg. */
15129 x2
= XVECEXP (x
, 0, 1);
15130 if (GET_CODE (x2
) == SET
)
15132 if (GET_CODE (x2
) == CALL
)
15135 x
= XVECEXP (x
, 0, 0);
15137 if (GET_CODE (x
) == SET
)
15139 gcc_assert (GET_CODE (x
) == CALL
);
15144 /* REG is set in DEF. See if the definition is one of the ways we load a
15145 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15146 If it is, return the symbol reference of the function, otherwise return
15149 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15150 the values of source registers, otherwise treat such registers as
15151 having an unknown value. */
15154 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
15158 if (DF_REF_IS_ARTIFICIAL (def
))
15161 def_insn
= DF_REF_INSN (def
);
15162 set
= single_set (def_insn
);
15163 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
15165 rtx note
, src
, symbol
;
15167 /* First see whether the source is a plain symbol. This is used
15168 when calling symbols that are not lazily bound. */
15169 src
= SET_SRC (set
);
15170 if (GET_CODE (src
) == SYMBOL_REF
)
15173 /* Handle %call16 references. */
15174 symbol
= mips_strip_unspec_call (src
);
15177 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15181 /* If we have something more complicated, look for a
15182 REG_EQUAL or REG_EQUIV note. */
15183 note
= find_reg_equal_equiv_note (def_insn
);
15184 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
15185 return XEXP (note
, 0);
15187 /* Follow at most one simple register copy. Such copies are
15188 interesting in cases like:
15192 locally_binding_fn (...);
15197 locally_binding_fn (...);
15199 locally_binding_fn (...);
15201 where the load of locally_binding_fn can legitimately be
15202 hoisted or shared. However, we do not expect to see complex
15203 chains of copies, so a full worklist solution to the problem
15204 would probably be overkill. */
15205 if (recurse_p
&& REG_P (src
))
15206 return mips_find_pic_call_symbol (def_insn
, src
, false);
15212 /* Find the definition of the use of REG in INSN. See if the definition
15213 is one of the ways we load a register with a symbol address for a
15214 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15215 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15216 mips_pic_call_symbol_from_set. */
15219 mips_find_pic_call_symbol (rtx insn
, rtx reg
, bool recurse_p
)
15222 struct df_link
*defs
;
15225 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
15228 defs
= DF_REF_CHAIN (use
);
15231 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15235 /* If we have more than one definition, they need to be identical. */
15236 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
15240 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15241 if (!rtx_equal_p (symbol
, other
))
15248 /* Replace the args_size operand of the call expression CALL with the
15249 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15252 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
15256 args_size
= XEXP (call
, 1);
15257 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
15258 gen_rtvec (2, args_size
, symbol
),
15262 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15263 if instead of the arg_size argument it contains the call attributes. If
15264 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15265 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15269 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
15271 rtx args_size
, symbol
;
15273 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
15276 args_size
= operands
[args_size_opno
];
15277 if (GET_CODE (args_size
) != UNSPEC
)
15279 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
15281 symbol
= XVECEXP (args_size
, 0, 1);
15282 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15284 operands
[args_size_opno
] = symbol
;
15288 /* Use DF to annotate PIC indirect calls with the function symbol they
15292 mips_annotate_pic_calls (void)
15298 FOR_BB_INSNS (bb
, insn
)
15300 rtx call
, reg
, symbol
, second_call
;
15303 call
= mips_call_expr_from_insn (insn
, &second_call
);
15306 gcc_assert (MEM_P (XEXP (call
, 0)));
15307 reg
= XEXP (XEXP (call
, 0), 0);
15311 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
15314 mips_annotate_pic_call_expr (call
, symbol
);
15316 mips_annotate_pic_call_expr (second_call
, symbol
);
15321 /* A temporary variable used by for_each_rtx callbacks, etc. */
15322 static rtx mips_sim_insn
;
15324 /* A structure representing the state of the processor pipeline.
15325 Used by the mips_sim_* family of functions. */
15327 /* The maximum number of instructions that can be issued in a cycle.
15328 (Caches mips_issue_rate.) */
15329 unsigned int issue_rate
;
15331 /* The current simulation time. */
15334 /* How many more instructions can be issued in the current cycle. */
15335 unsigned int insns_left
;
15337 /* LAST_SET[X].INSN is the last instruction to set register X.
15338 LAST_SET[X].TIME is the time at which that instruction was issued.
15339 INSN is null if no instruction has yet set register X. */
15343 } last_set
[FIRST_PSEUDO_REGISTER
];
15345 /* The pipeline's current DFA state. */
15349 /* Reset STATE to the initial simulation state. */
15352 mips_sim_reset (struct mips_sim
*state
)
15354 curr_state
= state
->dfa_state
;
15357 state
->insns_left
= state
->issue_rate
;
15358 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
15359 state_reset (curr_state
);
15361 targetm
.sched
.init (0, false, 0);
15362 advance_state (curr_state
);
15365 /* Initialize STATE before its first use. DFA_STATE points to an
15366 allocated but uninitialized DFA state. */
15369 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
15371 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
15372 targetm
.sched
.init_dfa_pre_cycle_insn ();
15374 if (targetm
.sched
.init_dfa_post_cycle_insn
)
15375 targetm
.sched
.init_dfa_post_cycle_insn ();
15377 state
->issue_rate
= mips_issue_rate ();
15378 state
->dfa_state
= dfa_state
;
15379 mips_sim_reset (state
);
15382 /* Advance STATE by one clock cycle. */
15385 mips_sim_next_cycle (struct mips_sim
*state
)
15387 curr_state
= state
->dfa_state
;
15390 state
->insns_left
= state
->issue_rate
;
15391 advance_state (curr_state
);
15394 /* Advance simulation state STATE until instruction INSN can read
15398 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
15400 unsigned int regno
, end_regno
;
15402 end_regno
= END_REGNO (reg
);
15403 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
15404 if (state
->last_set
[regno
].insn
!= 0)
15408 t
= (state
->last_set
[regno
].time
15409 + insn_latency (state
->last_set
[regno
].insn
, insn
));
15410 while (state
->time
< t
)
15411 mips_sim_next_cycle (state
);
15415 /* A for_each_rtx callback. If *X is a register, advance simulation state
15416 DATA until mips_sim_insn can read the register's value. */
15419 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
15422 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
15426 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15429 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
15431 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
15434 /* Advance simulation state STATE until all of INSN's register
15435 dependencies are satisfied. */
15438 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
15440 mips_sim_insn
= insn
;
15441 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
15444 /* Advance simulation state STATE until the units required by
15445 instruction INSN are available. */
15448 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
15452 tmp_state
= alloca (state_size ());
15453 while (state
->insns_left
== 0
15454 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
15455 state_transition (tmp_state
, insn
) >= 0))
15456 mips_sim_next_cycle (state
);
15459 /* Advance simulation state STATE until INSN is ready to issue. */
15462 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
15464 mips_sim_wait_regs (state
, insn
);
15465 mips_sim_wait_units (state
, insn
);
15468 /* mips_sim_insn has just set X. Update the LAST_SET array
15469 in simulation state DATA. */
15472 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
15474 struct mips_sim
*state
;
15476 state
= (struct mips_sim
*) data
;
15479 unsigned int regno
, end_regno
;
15481 end_regno
= END_REGNO (x
);
15482 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
15484 state
->last_set
[regno
].insn
= mips_sim_insn
;
15485 state
->last_set
[regno
].time
= state
->time
;
15490 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15491 can issue immediately (i.e., that mips_sim_wait_insn has already
15495 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
15497 curr_state
= state
->dfa_state
;
15499 state_transition (curr_state
, insn
);
15500 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
15501 state
->insns_left
);
15503 mips_sim_insn
= insn
;
15504 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
15507 /* Simulate issuing a NOP in state STATE. */
15510 mips_sim_issue_nop (struct mips_sim
*state
)
15512 if (state
->insns_left
== 0)
15513 mips_sim_next_cycle (state
);
15514 state
->insns_left
--;
15517 /* Update simulation state STATE so that it's ready to accept the instruction
15518 after INSN. INSN should be part of the main rtl chain, not a member of a
15522 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
15524 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15526 mips_sim_issue_nop (state
);
15528 switch (GET_CODE (SEQ_BEGIN (insn
)))
15532 /* We can't predict the processor state after a call or label. */
15533 mips_sim_reset (state
);
15537 /* The delay slots of branch likely instructions are only executed
15538 when the branch is taken. Therefore, if the caller has simulated
15539 the delay slot instruction, STATE does not really reflect the state
15540 of the pipeline for the instruction after the delay slot. Also,
15541 branch likely instructions tend to incur a penalty when not taken,
15542 so there will probably be an extra delay between the branch and
15543 the instruction after the delay slot. */
15544 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
15545 mips_sim_reset (state
);
15553 /* Use simulator state STATE to calculate the execution time of
15554 instruction sequence SEQ. */
15556 static unsigned int
15557 mips_seq_time (struct mips_sim
*state
, rtx seq
)
15559 mips_sim_reset (state
);
15560 for (rtx insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
15562 mips_sim_wait_insn (state
, insn
);
15563 mips_sim_issue_insn (state
, insn
);
15565 return state
->time
;
15568 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15569 setting SETTING, using STATE to simulate instruction sequences. */
15571 static unsigned int
15572 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
15574 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
15577 enum machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
15578 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
15579 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
15581 /* If the target provides mulsidi3_32bit then that's the most likely
15582 consumer of the result. Test for bypasses. */
15583 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
15585 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
15586 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
15589 unsigned int time
= mips_seq_time (state
, get_insns ());
15594 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15595 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15596 Prefer MULT -- which is shorter -- in the event of a tie. */
15599 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
15602 /* No MTLO or MTHI available. */
15603 mips_tuning_info
.fast_mult_zero_zero_p
= true;
15606 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
15607 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
15608 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
15612 /* Set up costs based on the current architecture and tuning settings. */
15615 mips_set_tuning_info (void)
15617 if (mips_tuning_info
.initialized_p
15618 && mips_tuning_info
.arch
== mips_arch
15619 && mips_tuning_info
.tune
== mips_tune
15620 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
15623 mips_tuning_info
.arch
= mips_arch
;
15624 mips_tuning_info
.tune
= mips_tune
;
15625 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
15626 mips_tuning_info
.initialized_p
= true;
15630 struct mips_sim state
;
15631 mips_sim_init (&state
, alloca (state_size ()));
15633 mips_set_fast_mult_zero_zero_p (&state
);
15638 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15641 mips_expand_to_rtl_hook (void)
15643 /* We need to call this at a point where we can safely create sequences
15644 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15645 need to call it at a point where the DFA infrastructure is not
15646 already in use, so we can't just call it lazily on demand.
15648 At present, mips_tuning_info is only needed during post-expand
15649 RTL passes such as split_insns, so this hook should be early enough.
15650 We may need to move the call elsewhere if mips_tuning_info starts
15651 to be used for other things (such as rtx_costs, or expanders that
15652 could be called during gimple optimization). */
15653 mips_set_tuning_info ();
15656 /* The VR4130 pipeline issues aligned pairs of instructions together,
15657 but it stalls the second instruction if it depends on the first.
15658 In order to cut down the amount of logic required, this dependence
15659 check is not based on a full instruction decode. Instead, any non-SPECIAL
15660 instruction is assumed to modify the register specified by bits 20-16
15661 (which is usually the "rt" field).
15663 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15664 input, so we can end up with a false dependence between the branch
15665 and its delay slot. If this situation occurs in instruction INSN,
15666 try to avoid it by swapping rs and rt. */
15669 vr4130_avoid_branch_rt_conflict (rtx insn
)
15673 first
= SEQ_BEGIN (insn
);
15674 second
= SEQ_END (insn
);
15676 && NONJUMP_INSN_P (second
)
15677 && GET_CODE (PATTERN (first
)) == SET
15678 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
15679 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
15681 /* Check for the right kind of condition. */
15682 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
15683 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
15684 && REG_P (XEXP (cond
, 0))
15685 && REG_P (XEXP (cond
, 1))
15686 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
15687 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
15689 /* SECOND mentions the rt register but not the rs register. */
15690 rtx tmp
= XEXP (cond
, 0);
15691 XEXP (cond
, 0) = XEXP (cond
, 1);
15692 XEXP (cond
, 1) = tmp
;
15697 /* Implement -mvr4130-align. Go through each basic block and simulate the
15698 processor pipeline. If we find that a pair of instructions could execute
15699 in parallel, and the first of those instructions is not 8-byte aligned,
15700 insert a nop to make it aligned. */
15703 vr4130_align_insns (void)
15705 struct mips_sim state
;
15706 rtx insn
, subinsn
, last
, last2
, next
;
15711 /* LAST is the last instruction before INSN to have a nonzero length.
15712 LAST2 is the last such instruction before LAST. */
15716 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15719 mips_sim_init (&state
, alloca (state_size ()));
15720 for (insn
= get_insns (); insn
!= 0; insn
= next
)
15722 unsigned int length
;
15724 next
= NEXT_INSN (insn
);
15726 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15727 This isn't really related to the alignment pass, but we do it on
15728 the fly to avoid a separate instruction walk. */
15729 vr4130_avoid_branch_rt_conflict (insn
);
15731 length
= get_attr_length (insn
);
15732 if (length
> 0 && USEFUL_INSN_P (insn
))
15733 FOR_EACH_SUBINSN (subinsn
, insn
)
15735 mips_sim_wait_insn (&state
, subinsn
);
15737 /* If we want this instruction to issue in parallel with the
15738 previous one, make sure that the previous instruction is
15739 aligned. There are several reasons why this isn't worthwhile
15740 when the second instruction is a call:
15742 - Calls are less likely to be performance critical,
15743 - There's a good chance that the delay slot can execute
15744 in parallel with the call.
15745 - The return address would then be unaligned.
15747 In general, if we're going to insert a nop between instructions
15748 X and Y, it's better to insert it immediately after X. That
15749 way, if the nop makes Y aligned, it will also align any labels
15750 between X and Y. */
15751 if (state
.insns_left
!= state
.issue_rate
15752 && !CALL_P (subinsn
))
15754 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
15756 /* SUBINSN is the first instruction in INSN and INSN is
15757 aligned. We want to align the previous instruction
15758 instead, so insert a nop between LAST2 and LAST.
15760 Note that LAST could be either a single instruction
15761 or a branch with a delay slot. In the latter case,
15762 LAST, like INSN, is already aligned, but the delay
15763 slot must have some extra delay that stops it from
15764 issuing at the same time as the branch. We therefore
15765 insert a nop before the branch in order to align its
15767 gcc_assert (last2
);
15768 emit_insn_after (gen_nop (), last2
);
15771 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
15773 /* SUBINSN is the delay slot of INSN, but INSN is
15774 currently unaligned. Insert a nop between
15775 LAST and INSN to align it. */
15777 emit_insn_after (gen_nop (), last
);
15781 mips_sim_issue_insn (&state
, subinsn
);
15783 mips_sim_finish_insn (&state
, insn
);
15785 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15786 length
= get_attr_length (insn
);
15789 /* If the instruction is an asm statement or multi-instruction
15790 mips.md patern, the length is only an estimate. Insert an
15791 8 byte alignment after it so that the following instructions
15792 can be handled correctly. */
15793 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
15794 && (recog_memoized (insn
) < 0 || length
>= 8))
15796 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
15797 next
= NEXT_INSN (next
);
15798 mips_sim_next_cycle (&state
);
15801 else if (length
& 4)
15802 aligned_p
= !aligned_p
;
15807 /* See whether INSN is an aligned label. */
15808 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
15814 /* This structure records that the current function has a LO_SUM
15815 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15816 the largest offset applied to BASE by all such LO_SUMs. */
15817 struct mips_lo_sum_offset
{
15819 HOST_WIDE_INT offset
;
15822 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15825 mips_hash_base (rtx base
)
15827 int do_not_record_p
;
15829 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
15832 /* Hashtable helpers. */
15834 struct mips_lo_sum_offset_hasher
: typed_free_remove
<mips_lo_sum_offset
>
15836 typedef mips_lo_sum_offset value_type
;
15837 typedef rtx_def compare_type
;
15838 static inline hashval_t
hash (const value_type
*);
15839 static inline bool equal (const value_type
*, const compare_type
*);
15842 /* Hash-table callbacks for mips_lo_sum_offsets. */
15845 mips_lo_sum_offset_hasher::hash (const value_type
*entry
)
15847 return mips_hash_base (entry
->base
);
15851 mips_lo_sum_offset_hasher::equal (const value_type
*entry
,
15852 const compare_type
*value
)
15854 return rtx_equal_p (entry
->base
, value
);
15857 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
15859 /* Look up symbolic constant X in HTAB, which is a hash table of
15860 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15861 paired with a recorded LO_SUM, otherwise record X in the table. */
15864 mips_lo_sum_offset_lookup (mips_offset_table htab
, rtx x
,
15865 enum insert_option option
)
15868 mips_lo_sum_offset
**slot
;
15869 struct mips_lo_sum_offset
*entry
;
15871 /* Split X into a base and offset. */
15872 split_const (x
, &base
, &offset
);
15873 if (UNSPEC_ADDRESS_P (base
))
15874 base
= UNSPEC_ADDRESS (base
);
15876 /* Look up the base in the hash table. */
15877 slot
= htab
.find_slot_with_hash (base
, mips_hash_base (base
), option
);
15881 entry
= (struct mips_lo_sum_offset
*) *slot
;
15882 if (option
== INSERT
)
15886 entry
= XNEW (struct mips_lo_sum_offset
);
15887 entry
->base
= base
;
15888 entry
->offset
= INTVAL (offset
);
15893 if (INTVAL (offset
) > entry
->offset
)
15894 entry
->offset
= INTVAL (offset
);
15897 return INTVAL (offset
) <= entry
->offset
;
15900 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15901 Record every LO_SUM in *LOC. */
15904 mips_record_lo_sum (rtx
*loc
, void *data
)
15906 if (GET_CODE (*loc
) == LO_SUM
)
15907 mips_lo_sum_offset_lookup (*(mips_offset_table
*) data
,
15908 XEXP (*loc
, 1), INSERT
);
15912 /* Return true if INSN is a SET of an orphaned high-part relocation.
15913 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15914 LO_SUMs in the current function. */
15917 mips_orphaned_high_part_p (mips_offset_table htab
, rtx insn
)
15919 enum mips_symbol_type type
;
15922 set
= single_set (insn
);
15925 /* Check for %his. */
15927 if (GET_CODE (x
) == HIGH
15928 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
15929 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
15931 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15932 if (GET_CODE (x
) == UNSPEC
15933 && XINT (x
, 1) == UNSPEC_LOAD_GOT
15934 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
15935 SYMBOL_CONTEXT_LEA
, &type
)
15936 && type
== SYMBOL_GOTOFF_PAGE
)
15937 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
15942 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15943 INSN and a previous instruction, avoid it by inserting nops after
15946 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15947 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15948 before using the value of that register. *HILO_DELAY counts the
15949 number of instructions since the last hilo hazard (that is,
15950 the number of instructions since the last MFLO or MFHI).
15952 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15953 for the next instruction.
15955 LO_REG is an rtx for the LO register, used in dependence checking. */
15958 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
15959 rtx
*delayed_reg
, rtx lo_reg
)
15964 pattern
= PATTERN (insn
);
15966 /* Do not put the whole function in .set noreorder if it contains
15967 an asm statement. We don't know whether there will be hazards
15968 between the asm statement and the gcc-generated code. */
15969 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
15970 cfun
->machine
->all_noreorder_p
= false;
15972 /* Ignore zero-length instructions (barriers and the like). */
15973 ninsns
= get_attr_length (insn
) / 4;
15977 /* Work out how many nops are needed. Note that we only care about
15978 registers that are explicitly mentioned in the instruction's pattern.
15979 It doesn't matter that calls use the argument registers or that they
15980 clobber hi and lo. */
15981 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
15982 nops
= 2 - *hilo_delay
;
15983 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
15988 /* Insert the nops between this instruction and the previous one.
15989 Each new nop takes us further from the last hilo hazard. */
15990 *hilo_delay
+= nops
;
15992 emit_insn_after (gen_hazard_nop (), after
);
15994 /* Set up the state for the next instruction. */
15995 *hilo_delay
+= ninsns
;
15997 if (INSN_CODE (insn
) >= 0)
15998 switch (get_attr_hazard (insn
))
16008 set
= single_set (insn
);
16010 *delayed_reg
= SET_DEST (set
);
16015 /* Go through the instruction stream and insert nops where necessary.
16016 Also delete any high-part relocations whose partnering low parts
16017 are now all dead. See if the whole function can then be put into
16018 .set noreorder and .set nomacro. */
16021 mips_reorg_process_insns (void)
16023 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
16025 mips_offset_table htab
;
16027 /* Force all instructions to be split into their final form. */
16028 split_all_insns_noflow ();
16030 /* Recalculate instruction lengths without taking nops into account. */
16031 cfun
->machine
->ignore_hazard_length_p
= true;
16032 shorten_branches (get_insns ());
16034 cfun
->machine
->all_noreorder_p
= true;
16036 /* We don't track MIPS16 PC-relative offsets closely enough to make
16037 a good job of "set .noreorder" code in MIPS16 mode. */
16039 cfun
->machine
->all_noreorder_p
= false;
16041 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16042 if (!TARGET_EXPLICIT_RELOCS
)
16043 cfun
->machine
->all_noreorder_p
= false;
16045 /* Profiled functions can't be all noreorder because the profiler
16046 support uses assembler macros. */
16048 cfun
->machine
->all_noreorder_p
= false;
16050 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
16051 because we rely on the assembler to work around some errata.
16052 The r5900 too has several bugs. */
16053 if (TARGET_FIX_VR4120
|| TARGET_FIX_24K
|| TARGET_MIPS5900
)
16054 cfun
->machine
->all_noreorder_p
= false;
16056 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16057 MFHI instructions. Note that we avoid using MFLO and MFHI if
16058 the VR4130 MACC and DMACC instructions are available instead;
16059 see the *mfhilo_{si,di}_macc patterns. */
16060 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
16061 cfun
->machine
->all_noreorder_p
= false;
16065 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16066 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16067 FOR_EACH_SUBINSN (subinsn
, insn
)
16068 if (USEFUL_INSN_P (subinsn
))
16069 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, &htab
);
16074 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
16076 /* Make a second pass over the instructions. Delete orphaned
16077 high-part relocations or turn them into NOPs. Avoid hazards
16078 by inserting NOPs. */
16079 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
16081 next_insn
= NEXT_INSN (insn
);
16082 if (USEFUL_INSN_P (insn
))
16084 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
16086 /* If we find an orphaned high-part relocation in a delay
16087 slot, it's easier to turn that instruction into a NOP than
16088 to delete it. The delay slot will be a NOP either way. */
16089 FOR_EACH_SUBINSN (subinsn
, insn
)
16090 if (INSN_P (subinsn
))
16092 if (mips_orphaned_high_part_p (htab
, subinsn
))
16094 PATTERN (subinsn
) = gen_nop ();
16095 INSN_CODE (subinsn
) = CODE_FOR_nop
;
16097 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
16098 &delayed_reg
, lo_reg
);
16104 /* INSN is a single instruction. Delete it if it's an
16105 orphaned high-part relocation. */
16106 if (mips_orphaned_high_part_p (htab
, insn
))
16107 delete_insn (insn
);
16108 /* Also delete cache barriers if the last instruction
16109 was an annulled branch. INSN will not be speculatively
16111 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
16113 && JUMP_P (SEQ_BEGIN (last_insn
))
16114 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
16115 delete_insn (insn
);
16118 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
16119 &delayed_reg
, lo_reg
);
16129 /* Return true if the function has a long branch instruction. */
16132 mips_has_long_branch_p (void)
16137 /* We need up-to-date instruction lengths. */
16138 shorten_branches (get_insns ());
16140 /* Look for a branch that is longer than normal. The normal length for
16141 non-MIPS16 branches is 8, because the length includes the delay slot.
16142 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16143 but they have no delay slot. */
16144 normal_length
= (TARGET_MIPS16
? 4 : 8);
16145 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16146 FOR_EACH_SUBINSN (subinsn
, insn
)
16147 if (JUMP_P (subinsn
)
16148 && get_attr_length (subinsn
) > normal_length
16149 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
16155 /* If we are using a GOT, but have not decided to use a global pointer yet,
16156 see whether we need one to implement long branches. Convert the ghost
16157 global-pointer instructions into real ones if so. */
16160 mips_expand_ghost_gp_insns (void)
16162 /* Quick exit if we already know that we will or won't need a
16164 if (!TARGET_USE_GOT
16165 || cfun
->machine
->global_pointer
== INVALID_REGNUM
16166 || mips_must_initialize_gp_p ())
16169 /* Run a full check for long branches. */
16170 if (!mips_has_long_branch_p ())
16173 /* We've now established that we need $gp. */
16174 cfun
->machine
->must_initialize_gp_p
= true;
16175 split_all_insns_noflow ();
16180 /* Subroutine of mips_reorg to manage passes that require DF. */
16183 mips_df_reorg (void)
16185 /* Create def-use chains. */
16186 df_set_flags (DF_EQ_NOTES
);
16187 df_chain_add_problem (DF_UD_CHAIN
);
16190 if (TARGET_RELAX_PIC_CALLS
)
16191 mips_annotate_pic_calls ();
16193 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
16194 r10k_insert_cache_barriers ();
16196 df_finish_pass (false);
16199 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16200 called very late in mips_reorg, but the caller is required to run
16201 mips16_lay_out_constants on the result. */
16204 mips16_load_branch_target (rtx dest
, rtx src
)
16206 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
16210 if (mips_cfun_has_cprestore_slot_p ())
16211 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
16213 mips_emit_move (dest
, pic_offset_table_rtx
);
16214 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
16215 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
16216 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16217 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
16218 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16219 gen_rtx_LO_SUM (Pmode
, dest
, low
)));
16223 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
16224 mips_emit_move (dest
, src
);
16228 /* If we're compiling a MIPS16 function, look for and split any long branches.
16229 This must be called after all other instruction modifications in
16233 mips16_split_long_branches (void)
16235 bool something_changed
;
16237 if (!TARGET_MIPS16
)
16240 /* Loop until the alignments for all targets are sufficient. */
16245 shorten_branches (get_insns ());
16246 something_changed
= false;
16247 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16249 && get_attr_length (insn
) > 4
16250 && (any_condjump_p (insn
) || any_uncondjump_p (insn
)))
16252 rtx old_label
, new_label
, temp
, saved_temp
;
16253 rtx target
, jump
, jump_sequence
;
16257 /* Free up a MIPS16 register by saving it in $1. */
16258 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
16259 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
16260 emit_move_insn (saved_temp
, temp
);
16262 /* Load the branch target into TEMP. */
16263 old_label
= JUMP_LABEL (insn
);
16264 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
16265 mips16_load_branch_target (temp
, target
);
16267 /* Jump to the target and restore the register's
16269 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
16270 (temp
, temp
, saved_temp
)));
16271 JUMP_LABEL (jump
) = old_label
;
16272 LABEL_NUSES (old_label
)++;
16274 /* Rewrite any symbolic references that are supposed to use
16275 a PC-relative constant pool. */
16276 mips16_lay_out_constants (false);
16278 if (simplejump_p (insn
))
16279 /* We're going to replace INSN with a longer form. */
16280 new_label
= NULL_RTX
;
16283 /* Create a branch-around label for the original
16285 new_label
= gen_label_rtx ();
16286 emit_label (new_label
);
16289 jump_sequence
= get_insns ();
16292 emit_insn_after (jump_sequence
, insn
);
16294 invert_jump (insn
, new_label
, false);
16296 delete_insn (insn
);
16297 something_changed
= true;
16300 while (something_changed
);
16303 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16308 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16309 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16310 to date if the CFG is available. */
16311 if (mips_cfg_in_reorg ())
16312 compute_bb_for_insn ();
16313 mips16_lay_out_constants (true);
16314 if (mips_cfg_in_reorg ())
16317 free_bb_for_insn ();
16321 /* We use a machine specific pass to do a second machine dependent reorg
16322 pass after delay branch scheduling. */
16324 static unsigned int
16325 mips_machine_reorg2 (void)
16327 mips_reorg_process_insns ();
16329 && TARGET_EXPLICIT_RELOCS
16331 && TARGET_VR4130_ALIGN
)
16332 vr4130_align_insns ();
16333 if (mips_expand_ghost_gp_insns ())
16334 /* The expansion could invalidate some of the VR4130 alignment
16335 optimizations, but this should be an extremely rare case anyhow. */
16336 mips_reorg_process_insns ();
16337 mips16_split_long_branches ();
16343 const pass_data pass_data_mips_machine_reorg2
=
16345 RTL_PASS
, /* type */
16346 "mach2", /* name */
16347 OPTGROUP_NONE
, /* optinfo_flags */
16348 false, /* has_gate */
16349 true, /* has_execute */
16350 TV_MACH_DEP
, /* tv_id */
16351 0, /* properties_required */
16352 0, /* properties_provided */
16353 0, /* properties_destroyed */
16354 0, /* todo_flags_start */
16355 TODO_verify_rtl_sharing
, /* todo_flags_finish */
16358 class pass_mips_machine_reorg2
: public rtl_opt_pass
16361 pass_mips_machine_reorg2(gcc::context
*ctxt
)
16362 : rtl_opt_pass(pass_data_mips_machine_reorg2
, ctxt
)
16365 /* opt_pass methods: */
16366 unsigned int execute () { return mips_machine_reorg2 (); }
16368 }; // class pass_mips_machine_reorg2
16370 } // anon namespace
16373 make_pass_mips_machine_reorg2 (gcc::context
*ctxt
)
16375 return new pass_mips_machine_reorg2 (ctxt
);
16379 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16380 in order to avoid duplicating too much logic from elsewhere. */
16383 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
16384 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
16387 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
16388 bool use_sibcall_p
;
16390 /* Pretend to be a post-reload pass while generating rtl. */
16391 reload_completed
= 1;
16393 /* Mark the end of the (empty) prologue. */
16394 emit_note (NOTE_INSN_PROLOGUE_END
);
16396 /* Determine if we can use a sibcall to call FUNCTION directly. */
16397 fnaddr
= XEXP (DECL_RTL (function
), 0);
16398 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
16399 && const_call_insn_operand (fnaddr
, Pmode
));
16401 /* Determine if we need to load FNADDR from the GOT. */
16403 && (mips_got_symbol_type_p
16404 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
16406 /* Pick a global pointer. Use a call-clobbered register if
16407 TARGET_CALL_SAVED_GP. */
16408 cfun
->machine
->global_pointer
16409 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
16410 cfun
->machine
->must_initialize_gp_p
= true;
16411 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
16413 /* Set up the global pointer for n32 or n64 abicalls. */
16414 mips_emit_loadgp ();
16417 /* We need two temporary registers in some cases. */
16418 temp1
= gen_rtx_REG (Pmode
, 2);
16419 temp2
= gen_rtx_REG (Pmode
, 3);
16421 /* Find out which register contains the "this" pointer. */
16422 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
16423 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
16425 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
16427 /* Add DELTA to THIS_RTX. */
16430 rtx offset
= GEN_INT (delta
);
16431 if (!SMALL_OPERAND (delta
))
16433 mips_emit_move (temp1
, offset
);
16436 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
16439 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16440 if (vcall_offset
!= 0)
16444 /* Set TEMP1 to *THIS_RTX. */
16445 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
16447 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16448 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
16450 /* Load the offset and add it to THIS_RTX. */
16451 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
16452 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
16455 /* Jump to the target function. Use a sibcall if direct jumps are
16456 allowed, otherwise load the address into a register first. */
16459 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
16460 SIBLING_CALL_P (insn
) = 1;
16464 /* This is messy. GAS treats "la $25,foo" as part of a call
16465 sequence and may allow a global "foo" to be lazily bound.
16466 The general move patterns therefore reject this combination.
16468 In this context, lazy binding would actually be OK
16469 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16470 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16471 We must therefore load the address via a temporary
16472 register if mips_dangerous_for_la25_p.
16474 If we jump to the temporary register rather than $25,
16475 the assembler can use the move insn to fill the jump's
16478 We can use the same technique for MIPS16 code, where $25
16479 is not a valid JR register. */
16480 if (TARGET_USE_PIC_FN_ADDR_REG
16482 && !mips_dangerous_for_la25_p (fnaddr
))
16483 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
16484 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
16486 if (TARGET_USE_PIC_FN_ADDR_REG
16487 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
16488 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
16489 emit_jump_insn (gen_indirect_jump (temp1
));
16492 /* Run just enough of rest_of_compilation. This sequence was
16493 "borrowed" from alpha.c. */
16494 insn
= get_insns ();
16495 split_all_insns_noflow ();
16496 mips16_lay_out_constants (true);
16497 shorten_branches (insn
);
16498 final_start_function (insn
, file
, 1);
16499 final (insn
, file
, 1);
16500 final_end_function ();
16502 /* Clean up the vars set above. Note that final_end_function resets
16503 the global pointer for us. */
16504 reload_completed
= 0;
16508 /* The last argument passed to mips_set_compression_mode,
16509 or negative if the function hasn't been called yet. */
16510 static unsigned int old_compression_mode
= -1;
16512 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16513 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16516 mips_set_compression_mode (unsigned int compression_mode
)
16519 if (compression_mode
== old_compression_mode
)
16522 /* Restore base settings of various flags. */
16523 target_flags
= mips_base_target_flags
;
16524 flag_schedule_insns
= mips_base_schedule_insns
;
16525 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
16526 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
16527 align_loops
= mips_base_align_loops
;
16528 align_jumps
= mips_base_align_jumps
;
16529 align_functions
= mips_base_align_functions
;
16530 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
16531 target_flags
|= compression_mode
;
16533 if (compression_mode
& MASK_MIPS16
)
16535 /* Switch to MIPS16 mode. */
16536 target_flags
|= MASK_MIPS16
;
16538 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16539 target_flags
&= ~MASK_SYNCI
;
16541 /* Don't run the scheduler before reload, since it tends to
16542 increase register pressure. */
16543 flag_schedule_insns
= 0;
16545 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16546 the whole function to be in a single section. */
16547 flag_reorder_blocks_and_partition
= 0;
16549 /* Don't move loop invariants, because it tends to increase
16550 register pressure. It also introduces an extra move in cases
16551 where the constant is the first operand in a two-operand binary
16552 instruction, or when it forms a register argument to a functon
16554 flag_move_loop_invariants
= 0;
16556 target_flags
|= MASK_EXPLICIT_RELOCS
;
16558 /* Experiments suggest we get the best overall section-anchor
16559 results from using the range of an unextended LW or SW. Code
16560 that makes heavy use of byte or short accesses can do better
16561 with ranges of 0...31 and 0...63 respectively, but most code is
16562 sensitive to the range of LW and SW instead. */
16563 targetm
.min_anchor_offset
= 0;
16564 targetm
.max_anchor_offset
= 127;
16566 targetm
.const_anchor
= 0;
16568 /* MIPS16 has no BAL instruction. */
16569 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
16571 /* The R4000 errata don't apply to any known MIPS16 cores.
16572 It's simpler to make the R4000 fixes and MIPS16 mode
16573 mutually exclusive. */
16574 target_flags
&= ~MASK_FIX_R4000
;
16576 if (flag_pic
&& !TARGET_OLDABI
)
16577 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16580 sorry ("MIPS16 -mxgot code");
16582 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
16583 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16587 /* Switch to microMIPS or the standard encoding. */
16589 if (TARGET_MICROMIPS
)
16590 /* Avoid branch likely. */
16591 target_flags
&= ~MASK_BRANCHLIKELY
;
16593 /* Provide default values for align_* for 64-bit targets. */
16596 if (align_loops
== 0)
16598 if (align_jumps
== 0)
16600 if (align_functions
== 0)
16601 align_functions
= 8;
16604 targetm
.min_anchor_offset
= -32768;
16605 targetm
.max_anchor_offset
= 32767;
16607 targetm
.const_anchor
= 0x8000;
16610 /* (Re)initialize MIPS target internals for new ISA. */
16611 mips_init_relocs ();
16613 if (compression_mode
& MASK_MIPS16
)
16615 if (!mips16_globals
)
16616 mips16_globals
= save_target_globals_default_opts ();
16618 restore_target_globals (mips16_globals
);
16621 restore_target_globals (&default_target_globals
);
16623 old_compression_mode
= compression_mode
;
16626 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16627 function should use the MIPS16 or microMIPS ISA and switch modes
16631 mips_set_current_function (tree fndecl
)
16633 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
16636 /* Allocate a chunk of memory for per-function machine-dependent data. */
16638 static struct machine_function
*
16639 mips_init_machine_status (void)
16641 return ggc_alloc_cleared_machine_function ();
16644 /* Return the processor associated with the given ISA level, or null
16645 if the ISA isn't valid. */
16647 static const struct mips_cpu_info
*
16648 mips_cpu_info_from_isa (int isa
)
16652 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16653 if (mips_cpu_info_table
[i
].isa
== isa
)
16654 return mips_cpu_info_table
+ i
;
16659 /* Return a mips_cpu_info entry determined by an option valued
16662 static const struct mips_cpu_info
*
16663 mips_cpu_info_from_opt (int opt
)
16667 case MIPS_ARCH_OPTION_FROM_ABI
:
16668 /* 'from-abi' selects the most compatible architecture for the
16669 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16670 ABIs. For the EABIs, we have to decide whether we're using
16671 the 32-bit or 64-bit version. */
16672 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
16673 : ABI_NEEDS_64BIT_REGS
? 3
16674 : (TARGET_64BIT
? 3 : 1));
16676 case MIPS_ARCH_OPTION_NATIVE
:
16677 gcc_unreachable ();
16680 return &mips_cpu_info_table
[opt
];
16684 /* Return a default mips_cpu_info entry, given that no -march= option
16685 was explicitly specified. */
16687 static const struct mips_cpu_info
*
16688 mips_default_arch (void)
16690 #if defined (MIPS_CPU_STRING_DEFAULT)
16692 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16693 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
16694 return mips_cpu_info_table
+ i
;
16695 gcc_unreachable ();
16696 #elif defined (MIPS_ISA_DEFAULT)
16697 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
16699 /* 'from-abi' makes a good default: you get whatever the ABI
16701 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
16705 /* Set up globals to generate code for the ISA or processor
16706 described by INFO. */
16709 mips_set_architecture (const struct mips_cpu_info
*info
)
16713 mips_arch_info
= info
;
16714 mips_arch
= info
->cpu
;
16715 mips_isa
= info
->isa
;
16719 /* Likewise for tuning. */
16722 mips_set_tune (const struct mips_cpu_info
*info
)
16726 mips_tune_info
= info
;
16727 mips_tune
= info
->cpu
;
16731 /* Implement TARGET_OPTION_OVERRIDE. */
16734 mips_option_override (void)
16736 int i
, start
, regno
, mode
;
16738 if (global_options_set
.x_mips_isa_option
)
16739 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
16741 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16742 SUBTARGET_OVERRIDE_OPTIONS
;
16745 /* MIPS16 and microMIPS cannot coexist. */
16746 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
16747 error ("unsupported combination: %s", "-mips16 -mmicromips");
16749 /* Save the base compression state and process flags as though we
16750 were generating uncompressed code. */
16751 mips_base_compression_flags
= TARGET_COMPRESSION
;
16752 target_flags
&= ~TARGET_COMPRESSION
;
16754 /* -mno-float overrides -mhard-float and -msoft-float. */
16755 if (TARGET_NO_FLOAT
)
16757 target_flags
|= MASK_SOFT_FLOAT_ABI
;
16758 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
16761 if (TARGET_FLIP_MIPS16
)
16762 TARGET_INTERLINK_COMPRESSED
= 1;
16764 /* Set the small data limit. */
16765 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
16767 : MIPS_DEFAULT_GVALUE
);
16769 /* The following code determines the architecture and register size.
16770 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16771 The GAS and GCC code should be kept in sync as much as possible. */
16773 if (global_options_set
.x_mips_arch_option
)
16774 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
16776 if (mips_isa_option_info
!= 0)
16778 if (mips_arch_info
== 0)
16779 mips_set_architecture (mips_isa_option_info
);
16780 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
16781 error ("%<-%s%> conflicts with the other architecture options, "
16782 "which specify a %s processor",
16783 mips_isa_option_info
->name
,
16784 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
16787 if (mips_arch_info
== 0)
16788 mips_set_architecture (mips_default_arch ());
16790 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
16791 error ("%<-march=%s%> is not compatible with the selected ABI",
16792 mips_arch_info
->name
);
16794 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16795 if (global_options_set
.x_mips_tune_option
)
16796 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
16798 if (mips_tune_info
== 0)
16799 mips_set_tune (mips_arch_info
);
16801 if ((target_flags_explicit
& MASK_64BIT
) != 0)
16803 /* The user specified the size of the integer registers. Make sure
16804 it agrees with the ABI and ISA. */
16805 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
16806 error ("%<-mgp64%> used with a 32-bit processor");
16807 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
16808 error ("%<-mgp32%> used with a 64-bit ABI");
16809 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
16810 error ("%<-mgp64%> used with a 32-bit ABI");
16814 /* Infer the integer register size from the ABI and processor.
16815 Restrict ourselves to 32-bit registers if that's all the
16816 processor has, or if the ABI cannot handle 64-bit registers. */
16817 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
16818 target_flags
&= ~MASK_64BIT
;
16820 target_flags
|= MASK_64BIT
;
16823 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
16825 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
16826 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16827 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
16828 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16829 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
16831 if (!ISA_HAS_MXHC1
)
16832 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16833 " the target supports the mfhc1 and mthc1 instructions");
16834 else if (mips_abi
!= ABI_32
)
16835 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16841 /* -msingle-float selects 32-bit float registers. Otherwise the
16842 float registers should be the same size as the integer ones. */
16843 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
16844 target_flags
|= MASK_FLOAT64
;
16846 target_flags
&= ~MASK_FLOAT64
;
16849 /* End of code shared with GAS. */
16851 /* The R5900 FPU only supports single precision. */
16852 if (TARGET_MIPS5900
&& TARGET_HARD_FLOAT_ABI
&& TARGET_DOUBLE_FLOAT
)
16853 error ("unsupported combination: %s",
16854 "-march=r5900 -mhard-float -mdouble-float");
16856 /* If a -mlong* option was given, check that it matches the ABI,
16857 otherwise infer the -mlong* setting from the other options. */
16858 if ((target_flags_explicit
& MASK_LONG64
) != 0)
16862 if (mips_abi
== ABI_N32
)
16863 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16864 else if (mips_abi
== ABI_32
)
16865 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16866 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
16867 /* We have traditionally allowed non-abicalls code to use
16868 an LP64 form of o64. However, it would take a bit more
16869 effort to support the combination of 32-bit GOT entries
16870 and 64-bit pointers, so we treat the abicalls case as
16872 error ("the combination of %qs and %qs is incompatible with %qs",
16873 "-mabi=o64", "-mabicalls", "-mlong64");
16877 if (mips_abi
== ABI_64
)
16878 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16883 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
16884 target_flags
|= MASK_LONG64
;
16886 target_flags
&= ~MASK_LONG64
;
16889 if (!TARGET_OLDABI
)
16890 flag_pcc_struct_return
= 0;
16892 /* Decide which rtx_costs structure to use. */
16894 mips_cost
= &mips_rtx_cost_optimize_size
;
16896 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
16898 /* If the user hasn't specified a branch cost, use the processor's
16900 if (mips_branch_cost
== 0)
16901 mips_branch_cost
= mips_cost
->branch_cost
;
16903 /* If neither -mbranch-likely nor -mno-branch-likely was given
16904 on the command line, set MASK_BRANCHLIKELY based on the target
16905 architecture and tuning flags. Annulled delay slots are a
16906 size win, so we only consider the processor-specific tuning
16907 for !optimize_size. */
16908 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
16910 if (ISA_HAS_BRANCHLIKELY
16912 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
16913 target_flags
|= MASK_BRANCHLIKELY
;
16915 target_flags
&= ~MASK_BRANCHLIKELY
;
16917 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
16918 warning (0, "the %qs architecture does not support branch-likely"
16919 " instructions", mips_arch_info
->name
);
16921 /* If the user hasn't specified -mimadd or -mno-imadd set
16922 MASK_IMADD based on the target architecture and tuning
16924 if ((target_flags_explicit
& MASK_IMADD
) == 0)
16926 if (ISA_HAS_MADD_MSUB
&&
16927 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
16928 target_flags
|= MASK_IMADD
;
16930 target_flags
&= ~MASK_IMADD
;
16932 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
16933 warning (0, "the %qs architecture does not support madd or msub"
16934 " instructions", mips_arch_info
->name
);
16936 /* The effect of -mabicalls isn't defined for the EABI. */
16937 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
16939 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16940 target_flags
&= ~MASK_ABICALLS
;
16943 /* PIC requires -mabicalls. */
16946 if (mips_abi
== ABI_EABI
)
16947 error ("cannot generate position-independent code for %qs",
16949 else if (!TARGET_ABICALLS
)
16950 error ("position-independent code requires %qs", "-mabicalls");
16953 if (TARGET_ABICALLS_PIC2
)
16954 /* We need to set flag_pic for executables as well as DSOs
16955 because we may reference symbols that are not defined in
16956 the final executable. (MIPS does not use things like
16957 copy relocs, for example.)
16959 There is a body of code that uses __PIC__ to distinguish
16960 between -mabicalls and -mno-abicalls code. The non-__PIC__
16961 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16962 long as any indirect jumps use $25. */
16965 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16966 faster code, but at the expense of more nops. Enable it at -O3 and
16968 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
16969 target_flags
|= MASK_VR4130_ALIGN
;
16971 /* Prefer a call to memcpy over inline code when optimizing for size,
16972 though see MOVE_RATIO in mips.h. */
16973 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
16974 target_flags
|= MASK_MEMCPY
;
16976 /* If we have a nonzero small-data limit, check that the -mgpopt
16977 setting is consistent with the other target flags. */
16978 if (mips_small_data_threshold
> 0)
16982 if (!TARGET_EXPLICIT_RELOCS
)
16983 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
16985 TARGET_LOCAL_SDATA
= false;
16986 TARGET_EXTERN_SDATA
= false;
16990 if (TARGET_VXWORKS_RTP
)
16991 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
16993 if (TARGET_ABICALLS
)
16994 warning (0, "cannot use small-data accesses for %qs",
16999 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17000 for all its floating point. */
17001 if (mips_nan
!= MIPS_IEEE_754_2008
)
17003 REAL_MODE_FORMAT (SFmode
) = &mips_single_format
;
17004 REAL_MODE_FORMAT (DFmode
) = &mips_double_format
;
17005 REAL_MODE_FORMAT (TFmode
) = &mips_quad_format
;
17008 /* Make sure that the user didn't turn off paired single support when
17009 MIPS-3D support is requested. */
17011 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
17012 && !TARGET_PAIRED_SINGLE_FLOAT
)
17013 error ("%<-mips3d%> requires %<-mpaired-single%>");
17015 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17017 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
17019 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17020 and TARGET_HARD_FLOAT_ABI are both true. */
17021 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
17022 error ("%qs must be used with %qs",
17023 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
17024 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
17026 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
17028 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
17029 warning (0, "the %qs architecture does not support paired-single"
17030 " instructions", mips_arch_info
->name
);
17032 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
17033 && !TARGET_CACHE_BUILTIN
)
17035 error ("%qs requires a target that provides the %qs instruction",
17036 "-mr10k-cache-barrier", "cache");
17037 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
17040 /* If TARGET_DSPR2, enable MASK_DSP. */
17042 target_flags
|= MASK_DSP
;
17044 /* .eh_frame addresses should be the same width as a C pointer.
17045 Most MIPS ABIs support only one pointer size, so the assembler
17046 will usually know exactly how big an .eh_frame address is.
17048 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17049 originally defined to use 64-bit pointers (i.e. it is LP64), and
17050 this is still the default mode. However, we also support an n32-like
17051 ILP32 mode, which is selected by -mlong32. The problem is that the
17052 assembler has traditionally not had an -mlong option, so it has
17053 traditionally not known whether we're using the ILP32 or LP64 form.
17055 As it happens, gas versions up to and including 2.19 use _32-bit_
17056 addresses for EABI64 .cfi_* directives. This is wrong for the
17057 default LP64 mode, so we can't use the directives by default.
17058 Moreover, since gas's current behavior is at odds with gcc's
17059 default behavior, it seems unwise to rely on future versions
17060 of gas behaving the same way. We therefore avoid using .cfi
17061 directives for -mlong32 as well. */
17062 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
17063 flag_dwarf2_cfi_asm
= 0;
17065 /* .cfi_* directives generate a read-only section, so fall back on
17066 manual .eh_frame creation if we need the section to be writable. */
17067 if (TARGET_WRITABLE_EH_FRAME
)
17068 flag_dwarf2_cfi_asm
= 0;
17070 mips_init_print_operand_punct ();
17072 /* Set up array to map GCC register number to debug register number.
17073 Ignore the special purpose register numbers. */
17075 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17077 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
17078 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
17079 mips_dwarf_regno
[i
] = i
;
17081 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
17084 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
17085 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
17086 mips_dbx_regno
[i
] = i
+ start
;
17088 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
17089 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
17090 mips_dbx_regno
[i
] = i
+ start
;
17092 /* Accumulator debug registers use big-endian ordering. */
17093 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
17094 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
17095 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
17096 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
17097 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
17099 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
17100 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
17103 /* Set up mips_hard_regno_mode_ok. */
17104 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
17105 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
17106 mips_hard_regno_mode_ok
[mode
][regno
]
17107 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
17109 /* Function to allocate machine-dependent function status. */
17110 init_machine_status
= &mips_init_machine_status
;
17112 /* Default to working around R4000 errata only if the processor
17113 was selected explicitly. */
17114 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
17115 && strcmp (mips_arch_info
->name
, "r4000") == 0)
17116 target_flags
|= MASK_FIX_R4000
;
17118 /* Default to working around R4400 errata only if the processor
17119 was selected explicitly. */
17120 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
17121 && strcmp (mips_arch_info
->name
, "r4400") == 0)
17122 target_flags
|= MASK_FIX_R4400
;
17124 /* Default to working around R10000 errata only if the processor
17125 was selected explicitly. */
17126 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
17127 && strcmp (mips_arch_info
->name
, "r10000") == 0)
17128 target_flags
|= MASK_FIX_R10000
;
17130 /* Make sure that branch-likely instructions available when using
17131 -mfix-r10000. The instructions are not available if either:
17133 1. -mno-branch-likely was passed.
17134 2. The selected ISA does not support branch-likely and
17135 the command line does not include -mbranch-likely. */
17136 if (TARGET_FIX_R10000
17137 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
17138 ? !ISA_HAS_BRANCHLIKELY
17139 : !TARGET_BRANCHLIKELY
))
17140 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17142 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
17144 warning (0, "the %qs architecture does not support the synci "
17145 "instruction", mips_arch_info
->name
);
17146 target_flags
&= ~MASK_SYNCI
;
17149 /* Only optimize PIC indirect calls if they are actually required. */
17150 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
17151 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17153 /* Save base state of options. */
17154 mips_base_target_flags
= target_flags
;
17155 mips_base_schedule_insns
= flag_schedule_insns
;
17156 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
17157 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
17158 mips_base_align_loops
= align_loops
;
17159 mips_base_align_jumps
= align_jumps
;
17160 mips_base_align_functions
= align_functions
;
17162 /* Now select the ISA mode.
17164 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17165 later if required. */
17166 mips_set_compression_mode (0);
17168 /* We register a second machine specific reorg pass after delay slot
17169 filling. Registering the pass must be done at start up. It's
17170 convenient to do it here. */
17171 opt_pass
*new_pass
= make_pass_mips_machine_reorg2 (g
);
17172 struct register_pass_info insert_pass_mips_machine_reorg2
=
17174 new_pass
, /* pass */
17175 "dbr", /* reference_pass_name */
17176 1, /* ref_pass_instance_number */
17177 PASS_POS_INSERT_AFTER
/* po_op */
17179 register_pass (&insert_pass_mips_machine_reorg2
);
17181 if (TARGET_HARD_FLOAT_ABI
&& TARGET_MIPS5900
)
17182 REAL_MODE_FORMAT (SFmode
) = &spu_single_format
;
17185 /* Swap the register information for registers I and I + 1, which
17186 currently have the wrong endianness. Note that the registers'
17187 fixedness and call-clobberedness might have been set on the
17191 mips_swap_registers (unsigned int i
)
17196 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17197 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17199 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
17200 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
17201 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
17202 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
17208 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17211 mips_conditional_register_usage (void)
17216 /* These DSP control register fields are global. */
17217 global_regs
[CCDSP_PO_REGNUM
] = 1;
17218 global_regs
[CCDSP_SC_REGNUM
] = 1;
17221 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17222 reg_class_contents
[(int) DSP_ACC_REGS
]);
17224 if (!TARGET_HARD_FLOAT
)
17226 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17227 reg_class_contents
[(int) FP_REGS
]);
17228 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17229 reg_class_contents
[(int) ST_REGS
]);
17231 else if (!ISA_HAS_8CC
)
17233 /* We only have a single condition-code register. We implement
17234 this by fixing all the condition-code registers and generating
17235 RTL that refers directly to ST_REG_FIRST. */
17236 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17237 reg_class_contents
[(int) ST_REGS
]);
17238 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
17239 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
17243 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17244 are call-saved, and saving them via a MIPS16 register would
17245 probably waste more time than just reloading the value.
17247 We permit the $t temporary registers when optimizing for speed
17248 but not when optimizing for space because using them results in
17249 code that is larger (but faster) then not using them. We do
17250 allow $24 (t8) because it is used in CMP and CMPI instructions
17251 and $25 (t9) because it is used as the function call address in
17254 fixed_regs
[18] = call_used_regs
[18] = 1;
17255 fixed_regs
[19] = call_used_regs
[19] = 1;
17256 fixed_regs
[20] = call_used_regs
[20] = 1;
17257 fixed_regs
[21] = call_used_regs
[21] = 1;
17258 fixed_regs
[22] = call_used_regs
[22] = 1;
17259 fixed_regs
[23] = call_used_regs
[23] = 1;
17260 fixed_regs
[26] = call_used_regs
[26] = 1;
17261 fixed_regs
[27] = call_used_regs
[27] = 1;
17262 fixed_regs
[30] = call_used_regs
[30] = 1;
17265 fixed_regs
[8] = call_used_regs
[8] = 1;
17266 fixed_regs
[9] = call_used_regs
[9] = 1;
17267 fixed_regs
[10] = call_used_regs
[10] = 1;
17268 fixed_regs
[11] = call_used_regs
[11] = 1;
17269 fixed_regs
[12] = call_used_regs
[12] = 1;
17270 fixed_regs
[13] = call_used_regs
[13] = 1;
17271 fixed_regs
[14] = call_used_regs
[14] = 1;
17272 fixed_regs
[15] = call_used_regs
[15] = 1;
17275 /* Do not allow HI and LO to be treated as register operands.
17276 There are no MTHI or MTLO instructions (or any real need
17277 for them) and one-way registers cannot easily be reloaded. */
17278 AND_COMPL_HARD_REG_SET (operand_reg_set
,
17279 reg_class_contents
[(int) MD_REGS
]);
17281 /* $f20-$f23 are call-clobbered for n64. */
17282 if (mips_abi
== ABI_64
)
17285 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
17286 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17288 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17290 if (mips_abi
== ABI_N32
)
17293 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
17294 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17296 /* Make sure that double-register accumulator values are correctly
17297 ordered for the current endianness. */
17298 if (TARGET_LITTLE_ENDIAN
)
17300 unsigned int regno
;
17302 mips_swap_registers (MD_REG_FIRST
);
17303 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
17304 mips_swap_registers (regno
);
17308 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
17309 other registers for instructions for which it is possible. This
17310 encourages the compiler to use CMP in cases where an XOR would
17311 require some register shuffling. */
17314 mips_order_regs_for_local_alloc (void)
17318 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17319 reg_alloc_order
[i
] = i
;
17323 /* It really doesn't matter where we put register 0, since it is
17324 a fixed register anyhow. */
17325 reg_alloc_order
[0] = 24;
17326 reg_alloc_order
[24] = 0;
17330 /* Implement EH_USES. */
17333 mips_eh_uses (unsigned int regno
)
17335 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
17337 /* We need to force certain registers to be live in order to handle
17338 PIC long branches correctly. See mips_must_initialize_gp_p for
17340 if (mips_cfun_has_cprestore_slot_p ())
17342 if (regno
== CPRESTORE_SLOT_REGNUM
)
17347 if (cfun
->machine
->global_pointer
== regno
)
17355 /* Implement EPILOGUE_USES. */
17358 mips_epilogue_uses (unsigned int regno
)
17360 /* Say that the epilogue uses the return address register. Note that
17361 in the case of sibcalls, the values "used by the epilogue" are
17362 considered live at the start of the called function. */
17363 if (regno
== RETURN_ADDR_REGNUM
)
17366 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17367 See the comment above load_call<mode> for details. */
17368 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
17371 /* An interrupt handler must preserve some registers that are
17372 ordinarily call-clobbered. */
17373 if (cfun
->machine
->interrupt_handler_p
17374 && mips_interrupt_extra_call_saved_reg_p (regno
))
17380 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17383 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
17385 return REG_P (*x
) && REGNO (*x
) == AT_REGNUM
;
17388 /* Return true if INSN needs to be wrapped in ".set noat".
17389 INSN has NOPERANDS operands, stored in OPVEC. */
17392 mips_need_noat_wrapper_p (rtx insn
, rtx
*opvec
, int noperands
)
17396 if (recog_memoized (insn
) >= 0)
17397 for (i
= 0; i
< noperands
; i
++)
17398 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
17403 /* Implement FINAL_PRESCAN_INSN. */
17406 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
17408 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17409 mips_push_asm_switch (&mips_noat
);
17412 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17415 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx insn
,
17416 rtx
*opvec
, int noperands
)
17418 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17419 mips_pop_asm_switch (&mips_noat
);
17422 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17423 EXT_CODE is the code of the extension used. Return NULL if widening
17424 multiplication shouldn't be used. */
17427 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
17431 signed_p
= ext_code
== SIGN_EXTEND
;
17434 /* Don't use widening multiplication with MULT when we have DMUL. Even
17435 with the extension of its input operands DMUL is faster. Note that
17436 the extension is not needed for signed multiplication. In order to
17437 ensure that we always remove the redundant sign-extension in this
17438 case we still expand mulsidi3 for DMUL. */
17440 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
17443 ? gen_mulsidi3_64bit_mips16
17444 : gen_umulsidi3_64bit_mips16
);
17445 if (TARGET_FIX_R4000
)
17447 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
17453 ? gen_mulsidi3_32bit_mips16
17454 : gen_umulsidi3_32bit_mips16
);
17455 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
17456 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
17457 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
17461 /* Return true if PATTERN matches the kind of instruction generated by
17462 umips_build_save_restore. SAVE_P is true for store. */
17465 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
17469 HOST_WIDE_INT first_offset
= 0;
17470 rtx first_base
= 0;
17471 unsigned int regmask
= 0;
17473 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
17475 rtx set
, reg
, mem
, this_base
;
17476 HOST_WIDE_INT this_offset
;
17478 /* Check that we have a SET. */
17479 set
= XVECEXP (pattern
, 0, n
);
17480 if (GET_CODE (set
) != SET
)
17483 /* Check that the SET is a load (if restoring) or a store
17485 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17486 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
17489 /* Check that the address is the sum of base and a possibly-zero
17490 constant offset. Determine if the offset is in range. */
17491 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
17492 if (!REG_P (this_base
))
17497 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
17499 first_base
= this_base
;
17500 first_offset
= this_offset
;
17504 /* Check that the save slots are consecutive. */
17505 if (REGNO (this_base
) != REGNO (first_base
)
17506 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
17510 /* Check that SET's other operand is a register. */
17511 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
17515 regmask
|= 1 << REGNO (reg
);
17518 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
17519 if (regmask
== umips_swm_mask
[i
])
17525 /* Return the assembly instruction for microMIPS LWM or SWM.
17526 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17529 umips_output_save_restore (bool save_p
, rtx pattern
)
17531 static char buffer
[300];
17534 HOST_WIDE_INT offset
;
17535 rtx base
, mem
, set
, last_set
, last_reg
;
17537 /* Parse the pattern. */
17538 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
17540 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
17542 n
= XVECLEN (pattern
, 0);
17544 set
= XVECEXP (pattern
, 0, 0);
17545 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17546 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
17548 last_set
= XVECEXP (pattern
, 0, n
- 1);
17549 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
17551 if (REGNO (last_reg
) == 31)
17554 gcc_assert (n
<= 9);
17558 s
+= sprintf (s
, "%s,", reg_names
[16]);
17560 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
17562 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
17565 if (REGNO (last_reg
) == 31)
17566 s
+= sprintf (s
, "%s,", reg_names
[31]);
17568 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
17572 /* Return true if MEM1 and MEM2 use the same base register, and the
17573 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17574 register into (from) which the contents of MEM1 will be loaded
17575 (stored), depending on the value of LOAD_P.
17576 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17579 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
17580 rtx first_reg
, rtx mem1
, rtx mem2
)
17583 HOST_WIDE_INT offset1
, offset2
;
17585 if (!MEM_P (mem1
) || !MEM_P (mem2
))
17588 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
17589 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
17591 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
17594 /* Avoid invalid load pair instructions. */
17595 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
17598 /* We must avoid this case for anti-dependence.
17601 first_reg is $2, but the base is $3. */
17604 && REGNO (first_reg
) + 1 == REGNO (base1
))
17607 if (offset2
!= offset1
+ 4)
17610 if (!UMIPS_12BIT_OFFSET_P (offset1
))
17616 /* OPERANDS describes the operands to a pair of SETs, in the order
17617 dest1, src1, dest2, src2. Return true if the operands can be used
17618 in an LWP or SWP instruction; LOAD_P says which. */
17621 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
17623 rtx reg1
, reg2
, mem1
, mem2
;
17627 reg1
= operands
[0];
17628 reg2
= operands
[2];
17629 mem1
= operands
[1];
17630 mem2
= operands
[3];
17634 reg1
= operands
[1];
17635 reg2
= operands
[3];
17636 mem1
= operands
[0];
17637 mem2
= operands
[2];
17640 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17641 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
17643 if (REGNO (reg1
) == REGNO (reg2
) + 1)
17644 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
17649 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17650 the first register is REG and the first memory slot is MEM.
17651 LOAD_P is true for LWP. */
17654 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
17656 rtx ops
[] = {reg
, mem
};
17659 output_asm_insn ("lwp\t%0,%1", ops
);
17661 output_asm_insn ("swp\t%0,%1", ops
);
17664 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17665 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17668 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
17670 rtx reg1
, reg2
, mem1
, mem2
;
17673 reg1
= operands
[0];
17674 reg2
= operands
[2];
17675 mem1
= operands
[1];
17676 mem2
= operands
[3];
17680 reg1
= operands
[1];
17681 reg2
= operands
[3];
17682 mem1
= operands
[0];
17683 mem2
= operands
[2];
17686 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17688 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
17692 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
17693 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
17696 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17699 umips_movep_target_p (rtx reg1
, rtx reg2
)
17701 int regno1
, regno2
, pair
;
17703 static const int match
[8] = {
17704 0x00000060, /* 5, 6 */
17705 0x000000a0, /* 5, 7 */
17706 0x000000c0, /* 6, 7 */
17707 0x00200010, /* 4, 21 */
17708 0x00400010, /* 4, 22 */
17709 0x00000030, /* 4, 5 */
17710 0x00000050, /* 4, 6 */
17711 0x00000090 /* 4, 7 */
17714 if (!REG_P (reg1
) || !REG_P (reg2
))
17717 regno1
= REGNO (reg1
);
17718 regno2
= REGNO (reg2
);
17720 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
17723 pair
= (1 << regno1
) | (1 << regno2
);
17725 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
17726 if (pair
== match
[i
])
17732 /* Return the size in bytes of the trampoline code, padded to
17733 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17734 function address immediately follow. */
17737 mips_trampoline_code_size (void)
17739 if (TARGET_USE_PIC_FN_ADDR_REG
)
17741 else if (ptr_mode
== DImode
)
17743 else if (ISA_HAS_LOAD_DELAY
)
17749 /* Implement TARGET_TRAMPOLINE_INIT. */
17752 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
17754 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
17757 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
17759 /* Work out the offsets of the pointers from the start of the
17760 trampoline code. */
17761 end_addr_offset
= mips_trampoline_code_size ();
17762 static_chain_offset
= end_addr_offset
;
17763 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
17765 /* Get pointers to the beginning and end of the code block. */
17766 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
17767 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
17769 #define OP(X) gen_int_mode (X, SImode)
17771 /* Build up the code in TRAMPOLINE. */
17773 if (TARGET_USE_PIC_FN_ADDR_REG
)
17775 /* $25 contains the address of the trampoline. Emit code of the form:
17777 l[wd] $1, target_function_offset($25)
17778 l[wd] $static_chain, static_chain_offset($25)
17781 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
17782 target_function_offset
,
17783 PIC_FUNCTION_ADDR_REGNUM
));
17784 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17785 static_chain_offset
,
17786 PIC_FUNCTION_ADDR_REGNUM
));
17787 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
17788 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
17790 else if (ptr_mode
== DImode
)
17792 /* It's too cumbersome to create the full 64-bit address, so let's
17798 1: l[wd] $25, target_function_offset - 12($31)
17799 l[wd] $static_chain, static_chain_offset - 12($31)
17803 where 12 is the offset of "1:" from the start of the code block. */
17804 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
17805 trampoline
[i
++] = OP (MIPS_BAL (1));
17806 trampoline
[i
++] = OP (MIPS_NOP
);
17807 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
17808 target_function_offset
- 12,
17809 RETURN_ADDR_REGNUM
));
17810 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17811 static_chain_offset
- 12,
17812 RETURN_ADDR_REGNUM
));
17813 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17814 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
17818 /* If the target has load delays, emit:
17820 lui $1, %hi(end_addr)
17821 lw $25, %lo(end_addr + ...)($1)
17822 lw $static_chain, %lo(end_addr + ...)($1)
17828 lui $1, %hi(end_addr)
17829 lw $25, %lo(end_addr + ...)($1)
17831 lw $static_chain, %lo(end_addr + ...)($1). */
17833 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
17834 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
17835 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
17836 NULL
, false, OPTAB_WIDEN
);
17837 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
17838 NULL
, false, OPTAB_WIDEN
);
17839 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
17841 /* Emit the LUI. */
17842 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
17843 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
17844 NULL
, false, OPTAB_WIDEN
);
17846 /* Emit the load of the target function. */
17847 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
17848 target_function_offset
- end_addr_offset
,
17850 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
17851 NULL
, false, OPTAB_WIDEN
);
17853 /* Emit the JR here, if we can. */
17854 if (!ISA_HAS_LOAD_DELAY
)
17855 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17857 /* Emit the load of the static chain register. */
17858 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17859 static_chain_offset
- end_addr_offset
,
17861 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
17862 NULL
, false, OPTAB_WIDEN
);
17864 /* Emit the JR, if we couldn't above. */
17865 if (ISA_HAS_LOAD_DELAY
)
17867 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17868 trampoline
[i
++] = OP (MIPS_NOP
);
17874 /* Copy the trampoline code. Leave any padding uninitialized. */
17875 for (j
= 0; j
< i
; j
++)
17877 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
17878 mips_emit_move (mem
, trampoline
[j
]);
17881 /* Set up the static chain pointer field. */
17882 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
17883 mips_emit_move (mem
, chain_value
);
17885 /* Set up the target function field. */
17886 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
17887 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
17889 /* Flush the code part of the trampoline. */
17890 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
17891 emit_insn (gen_clear_cache (addr
, end_addr
));
17894 /* Implement FUNCTION_PROFILER. */
17896 void mips_function_profiler (FILE *file
)
17899 sorry ("mips16 function profiling");
17900 if (TARGET_LONG_CALLS
)
17902 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
17903 if (Pmode
== DImode
)
17904 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
17906 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
17908 mips_push_asm_switch (&mips_noat
);
17909 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
17910 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
17911 /* _mcount treats $2 as the static chain register. */
17912 if (cfun
->static_chain_decl
!= NULL
)
17913 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
17914 reg_names
[STATIC_CHAIN_REGNUM
]);
17915 if (TARGET_MCOUNT_RA_ADDRESS
)
17917 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
17918 ra save location. */
17919 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
17920 /* ra not saved, pass zero. */
17921 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
17923 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
17924 Pmode
== DImode
? "dla" : "la", reg_names
[12],
17925 cfun
->machine
->frame
.ra_fp_offset
,
17926 reg_names
[STACK_POINTER_REGNUM
]);
17928 if (!TARGET_NEWABI
)
17930 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
17931 TARGET_64BIT
? "dsubu" : "subu",
17932 reg_names
[STACK_POINTER_REGNUM
],
17933 reg_names
[STACK_POINTER_REGNUM
],
17934 Pmode
== DImode
? 16 : 8);
17936 if (TARGET_LONG_CALLS
)
17937 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
17939 fprintf (file
, "\tjal\t_mcount\n");
17940 mips_pop_asm_switch (&mips_noat
);
17941 /* _mcount treats $2 as the static chain register. */
17942 if (cfun
->static_chain_decl
!= NULL
)
17943 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
17947 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
17948 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
17949 when TARGET_LOONGSON_VECTORS is true. */
17951 static unsigned HOST_WIDE_INT
17952 mips_shift_truncation_mask (enum machine_mode mode
)
17954 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
17957 return GET_MODE_BITSIZE (mode
) - 1;
17960 /* Implement TARGET_PREPARE_PCH_SAVE. */
17963 mips_prepare_pch_save (void)
17965 /* We are called in a context where the current MIPS16 vs. non-MIPS16
17966 setting should be irrelevant. The question then is: which setting
17967 makes most sense at load time?
17969 The PCH is loaded before the first token is read. We should never
17970 have switched into MIPS16 mode by that point, and thus should not
17971 have populated mips16_globals. Nor can we load the entire contents
17972 of mips16_globals from the PCH file, because mips16_globals contains
17973 a combination of GGC and non-GGC data.
17975 There is therefore no point in trying save the GGC part of
17976 mips16_globals to the PCH file, or to preserve MIPS16ness across
17977 the PCH save and load. The loading compiler would not have access
17978 to the non-GGC parts of mips16_globals (either from the PCH file,
17979 or from a copy that the loading compiler generated itself) and would
17980 have to call target_reinit anyway.
17982 It therefore seems best to switch back to non-MIPS16 mode at
17983 save time, and to ensure that mips16_globals remains null after
17985 mips_set_compression_mode (0);
17986 mips16_globals
= 0;
17989 /* Generate or test for an insn that supports a constant permutation. */
17991 #define MAX_VECT_LEN 8
17993 struct expand_vec_perm_d
17995 rtx target
, op0
, op1
;
17996 unsigned char perm
[MAX_VECT_LEN
];
17997 enum machine_mode vmode
;
17998 unsigned char nelt
;
18003 /* Construct (set target (vec_select op0 (parallel perm))) and
18004 return true if that's a valid instruction in the active ISA. */
18007 mips_expand_vselect (rtx target
, rtx op0
,
18008 const unsigned char *perm
, unsigned nelt
)
18010 rtx rperm
[MAX_VECT_LEN
], x
;
18013 for (i
= 0; i
< nelt
; ++i
)
18014 rperm
[i
] = GEN_INT (perm
[i
]);
18016 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
18017 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
18018 x
= gen_rtx_SET (VOIDmode
, target
, x
);
18021 if (recog_memoized (x
) < 0)
18029 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18032 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
18033 const unsigned char *perm
, unsigned nelt
)
18035 enum machine_mode v2mode
;
18038 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
18039 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
18040 return mips_expand_vselect (target
, x
, perm
, nelt
);
18043 /* Recognize patterns for even-odd extraction. */
18046 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
18048 unsigned i
, odd
, nelt
= d
->nelt
;
18049 rtx t0
, t1
, t2
, t3
;
18051 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18053 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18060 for (i
= 1; i
< nelt
; ++i
)
18061 if (d
->perm
[i
] != i
* 2 + odd
)
18067 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18068 t0
= gen_reg_rtx (d
->vmode
);
18069 t1
= gen_reg_rtx (d
->vmode
);
18073 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
18074 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
18076 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
18078 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
18082 t2
= gen_reg_rtx (d
->vmode
);
18083 t3
= gen_reg_rtx (d
->vmode
);
18084 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
18085 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
18086 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
18087 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
18089 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
18091 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
18095 gcc_unreachable ();
18100 /* Recognize patterns for the Loongson PSHUFH instruction. */
18103 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
18108 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18110 if (d
->vmode
!= V4HImode
)
18115 /* Convert the selector into the packed 8-bit form for pshufh. */
18116 /* Recall that loongson is little-endian only. No big-endian
18117 adjustment required. */
18118 for (i
= mask
= 0; i
< 4; i
++)
18119 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
18120 rmask
= force_reg (SImode
, GEN_INT (mask
));
18122 if (d
->one_vector_p
)
18123 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
18126 rtx t0
, t1
, x
, merge
, rmerge
[4];
18128 t0
= gen_reg_rtx (V4HImode
);
18129 t1
= gen_reg_rtx (V4HImode
);
18130 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
18131 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
18133 for (i
= 0; i
< 4; ++i
)
18134 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
18135 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
18136 merge
= force_reg (V4HImode
, merge
);
18138 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
18139 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18141 x
= gen_rtx_NOT (V4HImode
, merge
);
18142 x
= gen_rtx_AND (V4HImode
, x
, t0
);
18143 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18145 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
18146 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
18152 /* Recognize broadcast patterns for the Loongson. */
18155 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
18160 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18162 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18163 if (d
->vmode
!= V8QImode
)
18165 if (!d
->one_vector_p
)
18169 for (i
= 1; i
< 8; ++i
)
18170 if (d
->perm
[i
] != elt
)
18176 /* With one interleave we put two of the desired element adjacent. */
18177 t0
= gen_reg_rtx (V8QImode
);
18179 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
18181 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
18183 /* Shuffle that one HImode element into all locations. */
18186 t1
= gen_reg_rtx (V4HImode
);
18187 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
18188 force_reg (SImode
, GEN_INT (elt
))));
18190 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
18195 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
18197 unsigned int i
, nelt
= d
->nelt
;
18198 unsigned char perm2
[MAX_VECT_LEN
];
18200 if (d
->one_vector_p
)
18202 /* Try interleave with alternating operands. */
18203 memcpy (perm2
, d
->perm
, sizeof(perm2
));
18204 for (i
= 1; i
< nelt
; i
+= 2)
18206 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
18211 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
18215 /* Try again with swapped operands. */
18216 for (i
= 0; i
< nelt
; ++i
)
18217 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
18218 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
18222 if (mips_expand_vpc_loongson_even_odd (d
))
18224 if (mips_expand_vpc_loongson_pshufh (d
))
18226 if (mips_expand_vpc_loongson_bcast (d
))
18231 /* Expand a vec_perm_const pattern. */
18234 mips_expand_vec_perm_const (rtx operands
[4])
18236 struct expand_vec_perm_d d
;
18237 int i
, nelt
, which
;
18238 unsigned char orig_perm
[MAX_VECT_LEN
];
18242 d
.target
= operands
[0];
18243 d
.op0
= operands
[1];
18244 d
.op1
= operands
[2];
18247 d
.vmode
= GET_MODE (d
.target
);
18248 gcc_assert (VECTOR_MODE_P (d
.vmode
));
18249 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18250 d
.testing_p
= false;
18252 for (i
= which
= 0; i
< nelt
; ++i
)
18254 rtx e
= XVECEXP (sel
, 0, i
);
18255 int ei
= INTVAL (e
) & (2 * nelt
- 1);
18256 which
|= (ei
< nelt
? 1 : 2);
18259 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18267 d
.one_vector_p
= false;
18268 if (!rtx_equal_p (d
.op0
, d
.op1
))
18273 for (i
= 0; i
< nelt
; ++i
)
18274 d
.perm
[i
] &= nelt
- 1;
18276 d
.one_vector_p
= true;
18281 d
.one_vector_p
= true;
18285 ok
= mips_expand_vec_perm_const_1 (&d
);
18287 /* If we were given a two-vector permutation which just happened to
18288 have both input vectors equal, we folded this into a one-vector
18289 permutation. There are several loongson patterns that are matched
18290 via direct vec_select+vec_concat expansion, but we do not have
18291 support in mips_expand_vec_perm_const_1 to guess the adjustment
18292 that should be made for a single operand. Just try again with
18293 the original permutation. */
18294 if (!ok
&& which
== 3)
18296 d
.op0
= operands
[1];
18297 d
.op1
= operands
[2];
18298 d
.one_vector_p
= false;
18299 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18300 ok
= mips_expand_vec_perm_const_1 (&d
);
18306 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18309 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
18310 const unsigned char *sel
)
18312 struct expand_vec_perm_d d
;
18313 unsigned int i
, nelt
, which
;
18317 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18318 d
.testing_p
= true;
18319 memcpy (d
.perm
, sel
, nelt
);
18321 /* Categorize the set of elements in the selector. */
18322 for (i
= which
= 0; i
< nelt
; ++i
)
18324 unsigned char e
= d
.perm
[i
];
18325 gcc_assert (e
< 2 * nelt
);
18326 which
|= (e
< nelt
? 1 : 2);
18329 /* For all elements from second vector, fold the elements to first. */
18331 for (i
= 0; i
< nelt
; ++i
)
18334 /* Check whether the mask can be applied to the vector type. */
18335 d
.one_vector_p
= (which
!= 3);
18337 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
18338 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
18339 if (!d
.one_vector_p
)
18340 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
18343 ret
= mips_expand_vec_perm_const_1 (&d
);
18349 /* Expand an integral vector unpack operation. */
18352 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
18354 enum machine_mode imode
= GET_MODE (operands
[1]);
18355 rtx (*unpack
) (rtx
, rtx
, rtx
);
18356 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
18357 rtx tmp
, dest
, zero
;
18363 unpack
= gen_loongson_punpckhbh
;
18365 unpack
= gen_loongson_punpcklbh
;
18366 cmpgt
= gen_loongson_pcmpgtb
;
18370 unpack
= gen_loongson_punpckhhw
;
18372 unpack
= gen_loongson_punpcklhw
;
18373 cmpgt
= gen_loongson_pcmpgth
;
18376 gcc_unreachable ();
18379 zero
= force_reg (imode
, CONST0_RTX (imode
));
18384 tmp
= gen_reg_rtx (imode
);
18385 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
18388 dest
= gen_reg_rtx (imode
);
18389 emit_insn (unpack (dest
, operands
[1], tmp
));
18391 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
18394 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18397 mips_constant_elt_p (rtx x
)
18399 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
18402 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18405 mips_expand_vi_broadcast (enum machine_mode vmode
, rtx target
, rtx elt
)
18407 struct expand_vec_perm_d d
;
18411 if (elt
!= const0_rtx
)
18412 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
18414 elt
= gen_lowpart (DImode
, elt
);
18416 t1
= gen_reg_rtx (vmode
);
18420 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
18423 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
18426 gcc_unreachable ();
18429 memset (&d
, 0, sizeof (d
));
18434 d
.nelt
= GET_MODE_NUNITS (vmode
);
18435 d
.one_vector_p
= true;
18437 ok
= mips_expand_vec_perm_const_1 (&d
);
18441 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18442 elements of VALS with zeros, copy the constant vector to TARGET. */
18445 mips_expand_vi_constant (enum machine_mode vmode
, unsigned nelt
,
18446 rtx target
, rtx vals
)
18448 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
18451 for (i
= 0; i
< nelt
; ++i
)
18453 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
18454 RTVEC_ELT (vec
, i
) = const0_rtx
;
18457 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
18461 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18464 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
18466 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
18468 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
18469 GEN_INT (one_var
)));
18472 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18475 mips_expand_vi_general (enum machine_mode vmode
, enum machine_mode imode
,
18476 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
18478 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
18479 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
18482 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
18484 for (i
= 0; i
< nelt
; ++i
)
18486 rtx x
= XVECEXP (vals
, 0, i
);
18487 if (!mips_constant_elt_p (x
))
18488 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
18491 emit_move_insn (target
, mem
);
18494 /* Expand a vector initialization. */
18497 mips_expand_vector_init (rtx target
, rtx vals
)
18499 enum machine_mode vmode
= GET_MODE (target
);
18500 enum machine_mode imode
= GET_MODE_INNER (vmode
);
18501 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
18502 unsigned nvar
= 0, one_var
= -1u;
18503 bool all_same
= true;
18506 for (i
= 0; i
< nelt
; ++i
)
18508 x
= XVECEXP (vals
, 0, i
);
18509 if (!mips_constant_elt_p (x
))
18510 nvar
++, one_var
= i
;
18511 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
18515 /* Load constants from the pool, or whatever's handy. */
18518 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
18522 /* For two-part initialization, always use CONCAT. */
18525 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
18526 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
18527 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
18528 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18532 /* Loongson is the only cpu with vectors with more elements. */
18533 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
18535 /* If all values are identical, broadcast the value. */
18538 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
18542 /* If we've only got one non-variable V4HImode, use PINSRH. */
18543 if (nvar
== 1 && vmode
== V4HImode
)
18545 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
18549 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
18552 /* Expand a vector reduction. */
18555 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
18557 enum machine_mode vmode
= GET_MODE (in
);
18558 unsigned char perm2
[2];
18559 rtx last
, next
, fold
, x
;
18563 fold
= gen_reg_rtx (vmode
);
18567 /* Use PUL/PLU to produce { L, H } op { H, L }.
18568 By reversing the pair order, rather than a pure interleave high,
18569 we avoid erroneous exceptional conditions that we might otherwise
18570 produce from the computation of H op H. */
18573 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
18578 /* Use interleave to produce { H, L } op { H, H }. */
18579 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
18583 /* Perform the first reduction with interleave,
18584 and subsequent reductions with shifts. */
18585 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
18587 next
= gen_reg_rtx (vmode
);
18588 emit_insn (gen (next
, last
, fold
));
18591 fold
= gen_reg_rtx (vmode
);
18592 x
= force_reg (SImode
, GEN_INT (16));
18593 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
18597 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
18599 next
= gen_reg_rtx (vmode
);
18600 emit_insn (gen (next
, last
, fold
));
18603 fold
= gen_reg_rtx (vmode
);
18604 x
= force_reg (SImode
, GEN_INT (16));
18605 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18607 next
= gen_reg_rtx (vmode
);
18608 emit_insn (gen (next
, last
, fold
));
18611 fold
= gen_reg_rtx (vmode
);
18612 x
= force_reg (SImode
, GEN_INT (8));
18613 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18617 gcc_unreachable ();
18620 emit_insn (gen (target
, last
, fold
));
18623 /* Expand a vector minimum/maximum. */
18626 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
18627 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
18629 enum machine_mode vmode
= GET_MODE (target
);
18632 tc
= gen_reg_rtx (vmode
);
18633 t0
= gen_reg_rtx (vmode
);
18634 t1
= gen_reg_rtx (vmode
);
18637 emit_insn (cmp (tc
, op0
, op1
));
18639 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
18640 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18642 x
= gen_rtx_NOT (vmode
, tc
);
18643 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
18644 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18646 x
= gen_rtx_IOR (vmode
, t0
, t1
);
18647 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18650 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
18653 mips_case_values_threshold (void)
18655 /* In MIPS16 mode using a larger case threshold generates smaller code. */
18656 if (TARGET_MIPS16
&& optimize_size
)
18659 return default_case_values_threshold ();
18662 /* Initialize the GCC target structure. */
18663 #undef TARGET_ASM_ALIGNED_HI_OP
18664 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18665 #undef TARGET_ASM_ALIGNED_SI_OP
18666 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18667 #undef TARGET_ASM_ALIGNED_DI_OP
18668 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18670 #undef TARGET_OPTION_OVERRIDE
18671 #define TARGET_OPTION_OVERRIDE mips_option_override
18673 #undef TARGET_LEGITIMIZE_ADDRESS
18674 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18676 #undef TARGET_ASM_FUNCTION_PROLOGUE
18677 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18678 #undef TARGET_ASM_FUNCTION_EPILOGUE
18679 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18680 #undef TARGET_ASM_SELECT_RTX_SECTION
18681 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18682 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18683 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18685 #undef TARGET_SCHED_INIT
18686 #define TARGET_SCHED_INIT mips_sched_init
18687 #undef TARGET_SCHED_REORDER
18688 #define TARGET_SCHED_REORDER mips_sched_reorder
18689 #undef TARGET_SCHED_REORDER2
18690 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18691 #undef TARGET_SCHED_VARIABLE_ISSUE
18692 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18693 #undef TARGET_SCHED_ADJUST_COST
18694 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18695 #undef TARGET_SCHED_ISSUE_RATE
18696 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18697 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18698 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18699 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18700 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18701 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18702 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18703 mips_multipass_dfa_lookahead
18704 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18705 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18706 mips_small_register_classes_for_mode_p
18708 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18709 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18711 #undef TARGET_INSERT_ATTRIBUTES
18712 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18713 #undef TARGET_MERGE_DECL_ATTRIBUTES
18714 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18715 #undef TARGET_CAN_INLINE_P
18716 #define TARGET_CAN_INLINE_P mips_can_inline_p
18717 #undef TARGET_SET_CURRENT_FUNCTION
18718 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18720 #undef TARGET_VALID_POINTER_MODE
18721 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18722 #undef TARGET_REGISTER_MOVE_COST
18723 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18724 #undef TARGET_MEMORY_MOVE_COST
18725 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18726 #undef TARGET_RTX_COSTS
18727 #define TARGET_RTX_COSTS mips_rtx_costs
18728 #undef TARGET_ADDRESS_COST
18729 #define TARGET_ADDRESS_COST mips_address_cost
18731 #undef TARGET_IN_SMALL_DATA_P
18732 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18734 #undef TARGET_MACHINE_DEPENDENT_REORG
18735 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18737 #undef TARGET_PREFERRED_RELOAD_CLASS
18738 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18740 #undef TARGET_EXPAND_TO_RTL_HOOK
18741 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18742 #undef TARGET_ASM_FILE_START
18743 #define TARGET_ASM_FILE_START mips_file_start
18744 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18745 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18746 #undef TARGET_ASM_CODE_END
18747 #define TARGET_ASM_CODE_END mips_code_end
18749 #undef TARGET_INIT_LIBFUNCS
18750 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18752 #undef TARGET_BUILD_BUILTIN_VA_LIST
18753 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18754 #undef TARGET_EXPAND_BUILTIN_VA_START
18755 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18756 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18757 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18759 #undef TARGET_PROMOTE_FUNCTION_MODE
18760 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
18761 #undef TARGET_PROMOTE_PROTOTYPES
18762 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18764 #undef TARGET_FUNCTION_VALUE
18765 #define TARGET_FUNCTION_VALUE mips_function_value
18766 #undef TARGET_LIBCALL_VALUE
18767 #define TARGET_LIBCALL_VALUE mips_libcall_value
18768 #undef TARGET_FUNCTION_VALUE_REGNO_P
18769 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
18770 #undef TARGET_RETURN_IN_MEMORY
18771 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
18772 #undef TARGET_RETURN_IN_MSB
18773 #define TARGET_RETURN_IN_MSB mips_return_in_msb
18775 #undef TARGET_ASM_OUTPUT_MI_THUNK
18776 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
18777 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
18778 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
18780 #undef TARGET_PRINT_OPERAND
18781 #define TARGET_PRINT_OPERAND mips_print_operand
18782 #undef TARGET_PRINT_OPERAND_ADDRESS
18783 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
18784 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
18785 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
18787 #undef TARGET_SETUP_INCOMING_VARARGS
18788 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
18789 #undef TARGET_STRICT_ARGUMENT_NAMING
18790 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
18791 #undef TARGET_MUST_PASS_IN_STACK
18792 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
18793 #undef TARGET_PASS_BY_REFERENCE
18794 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
18795 #undef TARGET_CALLEE_COPIES
18796 #define TARGET_CALLEE_COPIES mips_callee_copies
18797 #undef TARGET_ARG_PARTIAL_BYTES
18798 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
18799 #undef TARGET_FUNCTION_ARG
18800 #define TARGET_FUNCTION_ARG mips_function_arg
18801 #undef TARGET_FUNCTION_ARG_ADVANCE
18802 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
18803 #undef TARGET_FUNCTION_ARG_BOUNDARY
18804 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
18806 #undef TARGET_MODE_REP_EXTENDED
18807 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
18809 #undef TARGET_VECTOR_MODE_SUPPORTED_P
18810 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
18812 #undef TARGET_SCALAR_MODE_SUPPORTED_P
18813 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
18815 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
18816 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
18818 #undef TARGET_INIT_BUILTINS
18819 #define TARGET_INIT_BUILTINS mips_init_builtins
18820 #undef TARGET_BUILTIN_DECL
18821 #define TARGET_BUILTIN_DECL mips_builtin_decl
18822 #undef TARGET_EXPAND_BUILTIN
18823 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
18825 #undef TARGET_HAVE_TLS
18826 #define TARGET_HAVE_TLS HAVE_AS_TLS
18828 #undef TARGET_CANNOT_FORCE_CONST_MEM
18829 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
18831 #undef TARGET_LEGITIMATE_CONSTANT_P
18832 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
18834 #undef TARGET_ENCODE_SECTION_INFO
18835 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
18837 #undef TARGET_ATTRIBUTE_TABLE
18838 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
18839 /* All our function attributes are related to how out-of-line copies should
18840 be compiled or called. They don't in themselves prevent inlining. */
18841 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
18842 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
18844 #undef TARGET_EXTRA_LIVE_ON_ENTRY
18845 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
18847 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
18848 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
18849 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
18850 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
18852 #undef TARGET_COMP_TYPE_ATTRIBUTES
18853 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
18855 #ifdef HAVE_AS_DTPRELWORD
18856 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
18857 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
18859 #undef TARGET_DWARF_REGISTER_SPAN
18860 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
18862 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
18863 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
18865 #undef TARGET_LEGITIMATE_ADDRESS_P
18866 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
18868 #undef TARGET_FRAME_POINTER_REQUIRED
18869 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
18871 #undef TARGET_CAN_ELIMINATE
18872 #define TARGET_CAN_ELIMINATE mips_can_eliminate
18874 #undef TARGET_CONDITIONAL_REGISTER_USAGE
18875 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
18877 #undef TARGET_TRAMPOLINE_INIT
18878 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
18880 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
18881 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
18883 #undef TARGET_SHIFT_TRUNCATION_MASK
18884 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
18886 #undef TARGET_PREPARE_PCH_SAVE
18887 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
18889 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
18890 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
18892 #undef TARGET_CASE_VALUES_THRESHOLD
18893 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
18895 struct gcc_target targetm
= TARGET_INITIALIZER
;
18897 #include "gt-mips.h"