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(mips_output_lineno): Use LOCAL_LABEL_PREFIX.
[gcc.git] / gcc / config / mips / mips.c
1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93, 94, 1995 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23
24 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
25 calling convention in 64 bit mode. It doesn't work though, and should
26 be replaced with something better designed. */
27
28 #include "config.h"
29 #include "rtl.h"
30 #include "regs.h"
31 #include "hard-reg-set.h"
32 #include "real.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "insn-flags.h"
36 #include "insn-attr.h"
37 #include "insn-codes.h"
38 #include "recog.h"
39 #include "output.h"
40
41 #undef MAX /* sys/param.h may also define these */
42 #undef MIN
43
44 #include <stdio.h>
45 #include <signal.h>
46 #include <sys/types.h>
47 #include <sys/file.h>
48 #include <ctype.h>
49 #include "tree.h"
50 #include "expr.h"
51 #include "flags.h"
52
53 #ifndef R_OK
54 #define R_OK 4
55 #define W_OK 2
56 #define X_OK 1
57 #endif
58
59 #if defined(USG) || defined(NO_STAB_H)
60 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
61 #else
62 #include <stab.h> /* On BSD, use the system's stab.h. */
63 #endif /* not USG */
64
65 #ifdef __GNU_STAB__
66 #define STAB_CODE_TYPE enum __stab_debug_code
67 #else
68 #define STAB_CODE_TYPE int
69 #endif
70
71 extern void abort ();
72 extern int atoi ();
73 extern char *getenv ();
74 extern char *mktemp ();
75
76 extern rtx adj_offsettable_operand ();
77 extern rtx copy_to_reg ();
78 extern void error ();
79 extern void fatal ();
80 extern tree lookup_name ();
81 extern void pfatal_with_name ();
82 extern void warning ();
83
84 extern tree current_function_decl;
85 extern FILE *asm_out_file;
86
87 /* Enumeration for all of the relational tests, so that we can build
88 arrays indexed by the test type, and not worry about the order
89 of EQ, NE, etc. */
90
91 enum internal_test {
92 ITEST_EQ,
93 ITEST_NE,
94 ITEST_GT,
95 ITEST_GE,
96 ITEST_LT,
97 ITEST_LE,
98 ITEST_GTU,
99 ITEST_GEU,
100 ITEST_LTU,
101 ITEST_LEU,
102 ITEST_MAX
103 };
104
105 /* Global variables for machine-dependent things. */
106
107 /* Threshold for data being put into the small data/bss area, instead
108 of the normal data area (references to the small data/bss area take
109 1 instruction, and use the global pointer, references to the normal
110 data area takes 2 instructions). */
111 int mips_section_threshold = -1;
112
113 /* Count the number of .file directives, so that .loc is up to date. */
114 int num_source_filenames = 0;
115
116 /* Count the number of sdb related labels are generated (to find block
117 start and end boundaries). */
118 int sdb_label_count = 0;
119
120 /* Next label # for each statment for Silicon Graphics IRIS systems. */
121 int sym_lineno = 0;
122
123 /* Non-zero if inside of a function, because the stupid MIPS asm can't
124 handle .files inside of functions. */
125 int inside_function = 0;
126
127 /* Files to separate the text and the data output, so that all of the data
128 can be emitted before the text, which will mean that the assembler will
129 generate smaller code, based on the global pointer. */
130 FILE *asm_out_data_file;
131 FILE *asm_out_text_file;
132
133 /* Linked list of all externals that are to be emitted when optimizing
134 for the global pointer if they haven't been declared by the end of
135 the program with an appropriate .comm or initialization. */
136
137 struct extern_list {
138 struct extern_list *next; /* next external */
139 char *name; /* name of the external */
140 int size; /* size in bytes */
141 } *extern_head = 0;
142
143 /* Name of the file containing the current function. */
144 char *current_function_file = "";
145
146 /* Warning given that Mips ECOFF can't support changing files
147 within a function. */
148 int file_in_function_warning = FALSE;
149
150 /* Whether to suppress issuing .loc's because the user attempted
151 to change the filename within a function. */
152 int ignore_line_number = FALSE;
153
154 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
155 int set_noreorder;
156 int set_noat;
157 int set_nomacro;
158 int set_volatile;
159
160 /* The next branch instruction is a branch likely, not branch normal. */
161 int mips_branch_likely;
162
163 /* Count of delay slots and how many are filled. */
164 int dslots_load_total;
165 int dslots_load_filled;
166 int dslots_jump_total;
167 int dslots_jump_filled;
168
169 /* # of nops needed by previous insn */
170 int dslots_number_nops;
171
172 /* Number of 1/2/3 word references to data items (ie, not jal's). */
173 int num_refs[3];
174
175 /* registers to check for load delay */
176 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
177
178 /* Cached operands, and operator to compare for use in set/branch on
179 condition codes. */
180 rtx branch_cmp[2];
181
182 /* what type of branch to use */
183 enum cmp_type branch_type;
184
185 /* Number of previously seen half-pic pointers and references. */
186 static int prev_half_pic_ptrs = 0;
187 static int prev_half_pic_refs = 0;
188
189 /* which cpu are we scheduling for */
190 enum processor_type mips_cpu;
191
192 /* which instruction set architecture to use. */
193 int mips_isa;
194
195 /* Strings to hold which cpu and instruction set architecture to use. */
196 char *mips_cpu_string; /* for -mcpu=<xxx> */
197 char *mips_isa_string; /* for -mips{1,2,3,4} */
198
199 /* Generating calls to position independent functions? */
200 enum mips_abicalls_type mips_abicalls;
201
202 /* High and low marks for floating point values which we will accept
203 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
204 initialized in override_options. */
205 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
206
207 /* Array giving truth value on whether or not a given hard register
208 can support a given mode. */
209 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
210
211 /* Current frame information calculated by compute_frame_size. */
212 struct mips_frame_info current_frame_info;
213
214 /* Zero structure to initialize current_frame_info. */
215 struct mips_frame_info zero_frame_info;
216
217 /* Temporary filename used to buffer .text until end of program
218 for -mgpopt. */
219 static char *temp_filename;
220
221 /* Pseudo-reg holding the address of the current function when
222 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
223 by mips_finalize_pic if it was created. */
224 rtx embedded_pic_fnaddr_rtx;
225
226 /* List of all MIPS punctuation characters used by print_operand. */
227 char mips_print_operand_punct[256];
228
229 /* Map GCC register number to debugger register number. */
230 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
231
232 /* Buffer to use to enclose a load/store operation with %{ %} to
233 turn on .set volatile. */
234 static char volatile_buffer[60];
235
236 /* Hardware names for the registers. If -mrnames is used, this
237 will be overwritten with mips_sw_reg_names. */
238
239 char mips_reg_names[][8] =
240 {
241 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
242 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
243 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
244 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
245 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
246 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
247 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
248 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
249 "hi", "lo", "accum","$fcr31"
250 };
251
252 /* Mips software names for the registers, used to overwrite the
253 mips_reg_names array. */
254
255 char mips_sw_reg_names[][8] =
256 {
257 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
258 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
259 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
260 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
261 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
262 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
263 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
264 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
265 "hi", "lo", "accum","$fcr31"
266 };
267
268 /* Map hard register number to register class */
269 enum reg_class mips_regno_to_class[] =
270 {
271 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
272 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
273 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
274 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
275 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
276 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
277 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
278 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
279 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
280 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
281 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
282 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
283 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
284 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
285 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
286 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
287 HI_REG, LO_REG, HILO_REG, ST_REGS
288 };
289
290 /* Map register constraint character to register class. */
291 enum reg_class mips_char_to_class[256] =
292 {
293 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
294 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
295 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
296 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
297 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
298 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
299 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
300 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
301 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
302 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
303 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
304 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
305 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
306 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
307 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
308 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
309 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
310 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
311 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
312 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
313 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
314 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
315 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
316 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
317 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
318 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
319 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
320 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
321 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
322 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
323 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
324 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
325 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
326 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
327 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
328 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
329 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
330 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
331 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
332 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
333 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
334 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
335 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
336 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
337 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
338 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
339 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
340 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
341 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
342 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
343 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
344 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
345 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
346 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
347 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
348 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
349 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
350 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
351 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
352 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
353 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
354 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
355 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
356 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
357 };
358
359 \f
360 /* Return truth value of whether OP can be used as an operands
361 where a register or 16 bit unsigned integer is needed. */
362
363 int
364 uns_arith_operand (op, mode)
365 rtx op;
366 enum machine_mode mode;
367 {
368 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
369 return TRUE;
370
371 return register_operand (op, mode);
372 }
373
374 /* Return truth value of whether OP can be used as an operands
375 where a 16 bit integer is needed */
376
377 int
378 arith_operand (op, mode)
379 rtx op;
380 enum machine_mode mode;
381 {
382 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
383 return TRUE;
384
385 return register_operand (op, mode);
386 }
387
388 /* Return truth value of whether OP can be used as an operand in a two
389 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
390
391 int
392 arith32_operand (op, mode)
393 rtx op;
394 enum machine_mode mode;
395 {
396 if (GET_CODE (op) == CONST_INT)
397 return TRUE;
398
399 return register_operand (op, mode);
400 }
401
402 /* Return truth value of whether OP is a integer which fits in 16 bits */
403
404 int
405 small_int (op, mode)
406 rtx op;
407 enum machine_mode mode;
408 {
409 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
410 }
411
412 /* Return truth value of whether OP is a 32 bit integer which is too big to
413 be loaded with one instruction. */
414
415 int
416 large_int (op, mode)
417 rtx op;
418 enum machine_mode mode;
419 {
420 HOST_WIDE_INT value;
421
422 if (GET_CODE (op) != CONST_INT)
423 return FALSE;
424
425 value = INTVAL (op);
426 if ((value & ~0x0000ffff) == 0) /* ior reg,$r0,value */
427 return FALSE;
428
429 if (((unsigned long)(value + 32768)) <= 32767) /* subu reg,$r0,value */
430 return FALSE;
431
432 if ((value & 0x0000ffff) == 0) /* lui reg,value>>16 */
433 return FALSE;
434
435 return TRUE;
436 }
437
438 /* Return truth value of whether OP is a register or the constant 0. */
439
440 int
441 reg_or_0_operand (op, mode)
442 rtx op;
443 enum machine_mode mode;
444 {
445 switch (GET_CODE (op))
446 {
447 default:
448 break;
449
450 case CONST_INT:
451 return (INTVAL (op) == 0);
452
453 case CONST_DOUBLE:
454 if (op != CONST0_RTX (mode))
455 return FALSE;
456
457 return TRUE;
458
459 case REG:
460 case SUBREG:
461 return register_operand (op, mode);
462 }
463
464 return FALSE;
465 }
466
467 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
468
469 int
470 mips_const_double_ok (op, mode)
471 rtx op;
472 enum machine_mode mode;
473 {
474 REAL_VALUE_TYPE d;
475
476 if (GET_CODE (op) != CONST_DOUBLE)
477 return FALSE;
478
479 if (mode == VOIDmode)
480 return TRUE;
481
482 if (mode != SFmode && mode != DFmode)
483 return FALSE;
484
485 if (op == CONST0_RTX (mode))
486 return TRUE;
487
488 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
489 if (ABI_64BIT)
490 return FALSE;
491
492 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
493
494 if (REAL_VALUE_ISNAN (d))
495 return FALSE;
496
497 if (REAL_VALUE_NEGATIVE (d))
498 d = REAL_VALUE_NEGATE (d);
499
500 if (mode == DFmode)
501 {
502 if (REAL_VALUES_LESS (d, dfhigh)
503 && REAL_VALUES_LESS (dflow, d))
504 return TRUE;
505 }
506 else
507 {
508 if (REAL_VALUES_LESS (d, sfhigh)
509 && REAL_VALUES_LESS (sflow, d))
510 return TRUE;
511 }
512
513 return FALSE;
514 }
515
516 /* Return truth value if a memory operand fits in a single instruction
517 (ie, register + small offset). */
518
519 int
520 simple_memory_operand (op, mode)
521 rtx op;
522 enum machine_mode mode;
523 {
524 rtx addr, plus0, plus1;
525
526 /* Eliminate non-memory operations */
527 if (GET_CODE (op) != MEM)
528 return FALSE;
529
530 /* dword operations really put out 2 instructions, so eliminate them. */
531 if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD)
532 return FALSE;
533
534 /* Decode the address now. */
535 addr = XEXP (op, 0);
536 switch (GET_CODE (addr))
537 {
538 default:
539 break;
540
541 case REG:
542 return TRUE;
543
544 case CONST_INT:
545 return SMALL_INT (op);
546
547 case PLUS:
548 plus0 = XEXP (addr, 0);
549 plus1 = XEXP (addr, 1);
550 if (GET_CODE (plus0) == REG
551 && GET_CODE (plus1) == CONST_INT
552 && SMALL_INT (plus1))
553 return TRUE;
554
555 else if (GET_CODE (plus1) == REG
556 && GET_CODE (plus0) == CONST_INT
557 && SMALL_INT (plus0))
558 return TRUE;
559
560 else
561 return FALSE;
562
563 #if 0
564 /* We used to allow small symbol refs here (ie, stuff in .sdata
565 or .sbss), but this causes some bugs in G++. Also, it won't
566 interfere if the MIPS linker rewrites the store instruction
567 because the function is PIC. */
568
569 case LABEL_REF: /* never gp relative */
570 break;
571
572 case CONST:
573 /* If -G 0, we can never have a GP relative memory operation.
574 Also, save some time if not optimizing. */
575 if (!TARGET_GP_OPT)
576 return FALSE;
577
578 {
579 rtx offset = const0_rtx;
580 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
581 if (GET_CODE (op) != SYMBOL_REF)
582 return FALSE;
583
584 /* let's be paranoid.... */
585 if (! SMALL_INT (offset))
586 return FALSE;
587 }
588 /* fall through */
589
590 case SYMBOL_REF:
591 return SYMBOL_REF_FLAG (addr);
592 #endif
593 }
594
595 return FALSE;
596 }
597
598 /* Return true if the code of this rtx pattern is EQ or NE. */
599
600 int
601 equality_op (op, mode)
602 rtx op;
603 enum machine_mode mode;
604 {
605 if (mode != GET_MODE (op))
606 return FALSE;
607
608 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
609 }
610
611 /* Return true if the code is a relational operations (EQ, LE, etc.) */
612
613 int
614 cmp_op (op, mode)
615 rtx op;
616 enum machine_mode mode;
617 {
618 if (mode != GET_MODE (op))
619 return FALSE;
620
621 return (GET_RTX_CLASS (GET_CODE (op)) == '<');
622 }
623
624 /* Return true if the operand is either the PC or a label_ref. */
625
626 int
627 pc_or_label_operand (op, mode)
628 rtx op;
629 enum machine_mode mode;
630 {
631 if (op == pc_rtx)
632 return TRUE;
633
634 if (GET_CODE (op) == LABEL_REF)
635 return TRUE;
636
637 return FALSE;
638 }
639
640 /* Test for a valid operand for a call instruction.
641 Don't allow the arg pointer register or virtual regs
642 since they may change into reg + const, which the patterns
643 can't handle yet. */
644
645 int
646 call_insn_operand (op, mode)
647 rtx op;
648 enum machine_mode mode;
649 {
650 if (GET_CODE (op) == MEM
651 && (CONSTANT_ADDRESS_P (XEXP (op, 0))
652 || (GET_CODE (XEXP (op, 0)) == REG
653 && XEXP (op, 0) != arg_pointer_rtx
654 && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
655 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
656 return 1;
657 return 0;
658 }
659 \f
660 /* Returns an operand string for the given instruction's delay slot,
661 after updating filled delay slot statistics.
662
663 We assume that operands[0] is the target register that is set.
664
665 In order to check the next insn, most of this functionality is moved
666 to FINAL_PRESCAN_INSN, and we just set the global variables that
667 it needs. */
668
669 /* ??? This function no longer does anything useful, because final_prescan_insn
670 now will never emit a nop. */
671
672 char *
673 mips_fill_delay_slot (ret, type, operands, cur_insn)
674 char *ret; /* normal string to return */
675 enum delay_type type; /* type of delay */
676 rtx operands[]; /* operands to use */
677 rtx cur_insn; /* current insn */
678 {
679 register rtx set_reg;
680 register enum machine_mode mode;
681 register rtx next_insn = (cur_insn) ? NEXT_INSN (cur_insn) : (rtx)0;
682 register int num_nops;
683
684 if (type == DELAY_LOAD || type == DELAY_FCMP)
685 num_nops = 1;
686
687 else if (type == DELAY_HILO)
688 num_nops = 2;
689
690 else
691 num_nops = 0;
692
693 /* Make sure that we don't put nop's after labels. */
694 next_insn = NEXT_INSN (cur_insn);
695 while (next_insn != (rtx)0 && GET_CODE (next_insn) == NOTE)
696 next_insn = NEXT_INSN (next_insn);
697
698 dslots_load_total += num_nops;
699 if (TARGET_DEBUG_F_MODE
700 || !optimize
701 || type == DELAY_NONE
702 || operands == (rtx *)0
703 || cur_insn == (rtx)0
704 || next_insn == (rtx)0
705 || GET_CODE (next_insn) == CODE_LABEL
706 || (set_reg = operands[0]) == (rtx)0)
707 {
708 dslots_number_nops = 0;
709 mips_load_reg = (rtx)0;
710 mips_load_reg2 = (rtx)0;
711 mips_load_reg3 = (rtx)0;
712 mips_load_reg4 = (rtx)0;
713 return ret;
714 }
715
716 set_reg = operands[0];
717 if (set_reg == (rtx)0)
718 return ret;
719
720 while (GET_CODE (set_reg) == SUBREG)
721 set_reg = SUBREG_REG (set_reg);
722
723 mode = GET_MODE (set_reg);
724 dslots_number_nops = num_nops;
725 mips_load_reg = set_reg;
726 if (GET_MODE_SIZE (mode)
727 > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
728 mips_load_reg2 = gen_rtx (REG, SImode, REGNO (set_reg) + 1);
729 else
730 mips_load_reg2 = 0;
731
732 if (type == DELAY_HILO)
733 {
734 mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST);
735 mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1);
736 }
737 else
738 {
739 mips_load_reg3 = 0;
740 mips_load_reg4 = 0;
741 }
742
743 return ret;
744 }
745
746 \f
747 /* Determine whether a memory reference takes one (based off of the GP pointer),
748 two (normal), or three (label + reg) instructions, and bump the appropriate
749 counter for -mstats. */
750
751 void
752 mips_count_memory_refs (op, num)
753 rtx op;
754 int num;
755 {
756 int additional = 0;
757 int n_words = 0;
758 rtx addr, plus0, plus1;
759 enum rtx_code code0, code1;
760 int looping;
761
762 if (TARGET_DEBUG_B_MODE)
763 {
764 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
765 debug_rtx (op);
766 }
767
768 /* Skip MEM if passed, otherwise handle movsi of address. */
769 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
770
771 /* Loop, going through the address RTL */
772 do
773 {
774 looping = FALSE;
775 switch (GET_CODE (addr))
776 {
777 default:
778 break;
779
780 case REG:
781 case CONST_INT:
782 break;
783
784 case PLUS:
785 plus0 = XEXP (addr, 0);
786 plus1 = XEXP (addr, 1);
787 code0 = GET_CODE (plus0);
788 code1 = GET_CODE (plus1);
789
790 if (code0 == REG)
791 {
792 additional++;
793 addr = plus1;
794 looping = TRUE;
795 continue;
796 }
797
798 if (code0 == CONST_INT)
799 {
800 addr = plus1;
801 looping = TRUE;
802 continue;
803 }
804
805 if (code1 == REG)
806 {
807 additional++;
808 addr = plus0;
809 looping = TRUE;
810 continue;
811 }
812
813 if (code1 == CONST_INT)
814 {
815 addr = plus0;
816 looping = TRUE;
817 continue;
818 }
819
820 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
821 {
822 addr = plus0;
823 looping = TRUE;
824 continue;
825 }
826
827 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
828 {
829 addr = plus1;
830 looping = TRUE;
831 continue;
832 }
833
834 break;
835
836 case LABEL_REF:
837 n_words = 2; /* always 2 words */
838 break;
839
840 case CONST:
841 addr = XEXP (addr, 0);
842 looping = TRUE;
843 continue;
844
845 case SYMBOL_REF:
846 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
847 break;
848 }
849 }
850 while (looping);
851
852 if (n_words == 0)
853 return;
854
855 n_words += additional;
856 if (n_words > 3)
857 n_words = 3;
858
859 num_refs[n_words-1] += num;
860 }
861
862 \f
863 /* Return RTL for the offset from the current function to the
864 argument. */
865
866 rtx
867 embedded_pic_offset (x)
868 rtx x;
869 {
870 if (embedded_pic_fnaddr_rtx == NULL)
871 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
872 return gen_rtx (CONST, Pmode,
873 gen_rtx (MINUS, Pmode, x,
874 XEXP (DECL_RTL (current_function_decl), 0)));
875 }
876
877 /* Return the appropriate instructions to move one operand to another. */
878
879 char *
880 mips_move_1word (operands, insn, unsignedp)
881 rtx operands[];
882 rtx insn;
883 int unsignedp;
884 {
885 char *ret = 0;
886 rtx op0 = operands[0];
887 rtx op1 = operands[1];
888 enum rtx_code code0 = GET_CODE (op0);
889 enum rtx_code code1 = GET_CODE (op1);
890 enum machine_mode mode = GET_MODE (op0);
891 int subreg_word0 = 0;
892 int subreg_word1 = 0;
893 enum delay_type delay = DELAY_NONE;
894
895 while (code0 == SUBREG)
896 {
897 subreg_word0 += SUBREG_WORD (op0);
898 op0 = SUBREG_REG (op0);
899 code0 = GET_CODE (op0);
900 }
901
902 while (code1 == SUBREG)
903 {
904 subreg_word1 += SUBREG_WORD (op1);
905 op1 = SUBREG_REG (op1);
906 code1 = GET_CODE (op1);
907 }
908
909 if (code0 == REG)
910 {
911 int regno0 = REGNO (op0) + subreg_word0;
912
913 if (code1 == REG)
914 {
915 int regno1 = REGNO (op1) + subreg_word1;
916
917 /* Just in case, don't do anything for assigning a register
918 to itself, unless we are filling a delay slot. */
919 if (regno0 == regno1 && set_nomacro == 0)
920 ret = "";
921
922 else if (GP_REG_P (regno0))
923 {
924 if (GP_REG_P (regno1))
925 ret = "move\t%0,%1";
926
927 else if (MD_REG_P (regno1))
928 {
929 delay = DELAY_HILO;
930 if (regno1 != HILO_REGNUM)
931 ret = "mf%1\t%0";
932 else
933 ret = "mflo\t%0";
934 }
935
936 else
937 {
938 delay = DELAY_LOAD;
939 if (FP_REG_P (regno1))
940 ret = "mfc1\t%0,%1";
941
942 else if (regno1 == FPSW_REGNUM)
943 ret = "cfc1\t%0,$31";
944 }
945 }
946
947 else if (FP_REG_P (regno0))
948 {
949 if (GP_REG_P (regno1))
950 {
951 delay = DELAY_LOAD;
952 ret = "mtc1\t%1,%0";
953 }
954
955 if (FP_REG_P (regno1))
956 ret = "mov.s\t%0,%1";
957 }
958
959 else if (MD_REG_P (regno0))
960 {
961 if (GP_REG_P (regno1))
962 {
963 delay = DELAY_HILO;
964 if (regno0 != HILO_REGNUM)
965 ret = "mt%0\t%1";
966 }
967 }
968
969 else if (regno0 == FPSW_REGNUM)
970 {
971 if (GP_REG_P (regno1))
972 {
973 delay = DELAY_LOAD;
974 ret = "ctc1\t%0,$31";
975 }
976 }
977 }
978
979 else if (code1 == MEM)
980 {
981 delay = DELAY_LOAD;
982
983 if (TARGET_STATS)
984 mips_count_memory_refs (op1, 1);
985
986 if (GP_REG_P (regno0))
987 {
988 /* For loads, use the mode of the memory item, instead of the
989 target, so zero/sign extend can use this code as well. */
990 switch (GET_MODE (op1))
991 {
992 default:
993 break;
994 case SFmode:
995 ret = "lw\t%0,%1";
996 break;
997 case SImode:
998 ret = ((unsignedp && TARGET_64BIT)
999 ? "lwu\t%0,%1"
1000 : "lw\t%0,%1");
1001 break;
1002 case HImode:
1003 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1004 break;
1005 case QImode:
1006 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1007 break;
1008 }
1009 }
1010
1011 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1012 ret = "l.s\t%0,%1";
1013
1014 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1015 {
1016 int i = strlen (ret);
1017 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1018 abort ();
1019
1020 sprintf (volatile_buffer, "%%{%s%%}", ret);
1021 ret = volatile_buffer;
1022 }
1023 }
1024
1025 else if (code1 == CONST_INT
1026 || (code1 == CONST_DOUBLE
1027 && GET_MODE (op1) == VOIDmode))
1028 {
1029 if (code1 == CONST_DOUBLE)
1030 {
1031 /* This can happen when storing constants into long long
1032 bitfields. Just store the least significant word of
1033 the value. */
1034 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1035 }
1036
1037 if (INTVAL (op1) == 0)
1038 {
1039 if (GP_REG_P (regno0))
1040 ret = "move\t%0,%z1";
1041
1042 else if (FP_REG_P (regno0))
1043 {
1044 delay = DELAY_LOAD;
1045 ret = "mtc1\t%z1,%0";
1046 }
1047
1048 else if (MD_REG_P (regno0))
1049 {
1050 delay = DELAY_HILO;
1051 ret = "mt%0\t%.";
1052 }
1053 }
1054
1055 else if (GP_REG_P (regno0))
1056 ret = (INTVAL (op1) < 0) ? "li\t%0,%1\t\t\t# %X1" : "li\t%0,%X1\t\t# %1";
1057 }
1058
1059 else if (code1 == CONST_DOUBLE && mode == SFmode)
1060 {
1061 if (op1 == CONST0_RTX (SFmode))
1062 {
1063 if (GP_REG_P (regno0))
1064 ret = "move\t%0,%.";
1065
1066 else if (FP_REG_P (regno0))
1067 {
1068 delay = DELAY_LOAD;
1069 ret = "mtc1\t%.,%0";
1070 }
1071 }
1072
1073 else
1074 {
1075 delay = DELAY_LOAD;
1076 ret = "li.s\t%0,%1";
1077 }
1078 }
1079
1080 else if (code1 == LABEL_REF)
1081 {
1082 if (TARGET_STATS)
1083 mips_count_memory_refs (op1, 1);
1084
1085 ret = "la\t%0,%a1";
1086 }
1087
1088 else if (code1 == SYMBOL_REF || code1 == CONST)
1089 {
1090 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
1091 {
1092 rtx offset = const0_rtx;
1093
1094 if (GET_CODE (op1) == CONST)
1095 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
1096
1097 if (GET_CODE (op1) == SYMBOL_REF)
1098 {
1099 operands[2] = HALF_PIC_PTR (op1);
1100
1101 if (TARGET_STATS)
1102 mips_count_memory_refs (operands[2], 1);
1103
1104 if (INTVAL (offset) == 0)
1105 {
1106 delay = DELAY_LOAD;
1107 ret = (unsignedp && TARGET_64BIT
1108 ? "lwu\t%0,%2"
1109 : "lw\t%0,%2");
1110 }
1111 else
1112 {
1113 dslots_load_total++;
1114 operands[3] = offset;
1115 if (unsignedp && TARGET_64BIT)
1116 ret = (SMALL_INT (offset))
1117 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1118 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1119 else
1120 ret = (SMALL_INT (offset))
1121 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1122 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1123 }
1124 }
1125 }
1126 else
1127 {
1128 if (TARGET_STATS)
1129 mips_count_memory_refs (op1, 1);
1130
1131 ret = "la\t%0,%a1";
1132 }
1133 }
1134
1135 else if (code1 == PLUS)
1136 {
1137 rtx add_op0 = XEXP (op1, 0);
1138 rtx add_op1 = XEXP (op1, 1);
1139
1140 if (GET_CODE (XEXP (op1, 1)) == REG && GET_CODE (XEXP (op1, 0)) == CONST_INT)
1141 {
1142 add_op0 = XEXP (op1, 1); /* reverse operands */
1143 add_op1 = XEXP (op1, 0);
1144 }
1145
1146 operands[2] = add_op0;
1147 operands[3] = add_op1;
1148 ret = "add%:\t%0,%2,%3";
1149 }
1150 }
1151
1152 else if (code0 == MEM)
1153 {
1154 if (TARGET_STATS)
1155 mips_count_memory_refs (op0, 1);
1156
1157 if (code1 == REG)
1158 {
1159 int regno1 = REGNO (op1) + subreg_word1;
1160
1161 if (GP_REG_P (regno1))
1162 {
1163 switch (mode)
1164 {
1165 default: break;
1166 case SFmode: ret = "sw\t%1,%0"; break;
1167 case SImode: ret = "sw\t%1,%0"; break;
1168 case HImode: ret = "sh\t%1,%0"; break;
1169 case QImode: ret = "sb\t%1,%0"; break;
1170 }
1171 }
1172
1173 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
1174 ret = "s.s\t%1,%0";
1175 }
1176
1177 else if (code1 == CONST_INT && INTVAL (op1) == 0)
1178 {
1179 switch (mode)
1180 {
1181 default: break;
1182 case SFmode: ret = "sw\t%z1,%0"; break;
1183 case SImode: ret = "sw\t%z1,%0"; break;
1184 case HImode: ret = "sh\t%z1,%0"; break;
1185 case QImode: ret = "sb\t%z1,%0"; break;
1186 }
1187 }
1188
1189 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
1190 {
1191 switch (mode)
1192 {
1193 default: break;
1194 case SFmode: ret = "sw\t%.,%0"; break;
1195 case SImode: ret = "sw\t%.,%0"; break;
1196 case HImode: ret = "sh\t%.,%0"; break;
1197 case QImode: ret = "sb\t%.,%0"; break;
1198 }
1199 }
1200
1201 if (ret != (char *)0 && MEM_VOLATILE_P (op0))
1202 {
1203 int i = strlen (ret);
1204 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1205 abort ();
1206
1207 sprintf (volatile_buffer, "%%{%s%%}", ret);
1208 ret = volatile_buffer;
1209 }
1210 }
1211
1212 if (ret == (char *)0)
1213 {
1214 abort_with_insn (insn, "Bad move");
1215 return 0;
1216 }
1217
1218 if (delay != DELAY_NONE)
1219 return mips_fill_delay_slot (ret, delay, operands, insn);
1220
1221 return ret;
1222 }
1223
1224 \f
1225 /* Return the appropriate instructions to move 2 words */
1226
1227 char *
1228 mips_move_2words (operands, insn)
1229 rtx operands[];
1230 rtx insn;
1231 {
1232 char *ret = 0;
1233 rtx op0 = operands[0];
1234 rtx op1 = operands[1];
1235 enum rtx_code code0 = GET_CODE (operands[0]);
1236 enum rtx_code code1 = GET_CODE (operands[1]);
1237 int subreg_word0 = 0;
1238 int subreg_word1 = 0;
1239 enum delay_type delay = DELAY_NONE;
1240
1241 while (code0 == SUBREG)
1242 {
1243 subreg_word0 += SUBREG_WORD (op0);
1244 op0 = SUBREG_REG (op0);
1245 code0 = GET_CODE (op0);
1246 }
1247
1248 while (code1 == SUBREG)
1249 {
1250 subreg_word1 += SUBREG_WORD (op1);
1251 op1 = SUBREG_REG (op1);
1252 code1 = GET_CODE (op1);
1253 }
1254
1255 if (code0 == REG)
1256 {
1257 int regno0 = REGNO (op0) + subreg_word0;
1258
1259 if (code1 == REG)
1260 {
1261 int regno1 = REGNO (op1) + subreg_word1;
1262
1263 /* Just in case, don't do anything for assigning a register
1264 to itself, unless we are filling a delay slot. */
1265 if (regno0 == regno1 && set_nomacro == 0)
1266 ret = "";
1267
1268 else if (FP_REG_P (regno0))
1269 {
1270 if (FP_REG_P (regno1))
1271 ret = "mov.d\t%0,%1";
1272
1273 else
1274 {
1275 delay = DELAY_LOAD;
1276 if (TARGET_FLOAT64)
1277 {
1278 if (!TARGET_64BIT)
1279 abort_with_insn (insn, "Bad move");
1280 #ifdef TARGET_FP_CALL_32
1281 if (FP_CALL_GP_REG_P (regno1))
1282 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1283 else
1284 #endif
1285 ret = "dmtc1\t%1,%0";
1286 }
1287 else
1288 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1289 }
1290 }
1291
1292 else if (FP_REG_P (regno1))
1293 {
1294 delay = DELAY_LOAD;
1295 if (TARGET_FLOAT64)
1296 {
1297 if (!TARGET_64BIT)
1298 abort_with_insn (insn, "Bad move");
1299 #ifdef TARGET_FP_CALL_32
1300 if (FP_CALL_GP_REG_P (regno0))
1301 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1302 else
1303 #endif
1304 ret = "dmfc1\t%0,%1";
1305 }
1306 else
1307 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1308 }
1309
1310 else if (MD_REG_P (regno0) && GP_REG_P (regno1))
1311 {
1312 delay = DELAY_HILO;
1313 if (TARGET_64BIT)
1314 {
1315 if (regno0 != HILO_REGNUM)
1316 ret = "mt%0\t%1";
1317 else if (regno1 == 0)
1318 ret = "mtlo\t%.\n\tmthi\t%.";
1319 }
1320 else
1321 ret = "mthi\t%M1\n\tmtlo\t%L1";
1322 }
1323
1324 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
1325 {
1326 delay = DELAY_HILO;
1327 if (TARGET_64BIT)
1328 {
1329 if (regno1 != HILO_REGNUM)
1330 ret = "mf%1\t%0";
1331 }
1332 else
1333 ret = "mfhi\t%M0\n\tmflo\t%L0";
1334 }
1335
1336 else if (TARGET_64BIT)
1337 ret = "move\t%0,%1";
1338
1339 else if (regno0 != (regno1+1))
1340 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
1341
1342 else
1343 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
1344 }
1345
1346 else if (code1 == CONST_DOUBLE)
1347 {
1348 /* Move zero from $0 unless !TARGET_64BIT and recipient
1349 is 64-bit fp reg, in which case generate a constant. */
1350 if (op1 != CONST0_RTX (GET_MODE (op1))
1351 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
1352 {
1353 if (GET_MODE (op1) == DFmode)
1354 {
1355 delay = DELAY_LOAD;
1356 #ifdef TARGET_FP_CALL_32
1357 if (FP_CALL_GP_REG_P (regno0))
1358 {
1359 if (TARGET_FLOAT64 && !TARGET_64BIT)
1360 {
1361 split_double (op1, operands + 2, operands + 3);
1362 ret = "li\t%0,%2\n\tli\t%D0,%3";
1363 }
1364 else
1365 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1366 }
1367 else
1368 #endif
1369 ret = "li.d\t%0,%1";
1370 }
1371
1372 else if (TARGET_64BIT)
1373 ret = "dli\t%0,%1";
1374
1375 else
1376 {
1377 split_double (op1, operands + 2, operands + 3);
1378 ret = "li\t%0,%2\n\tli\t%D0,%3";
1379 }
1380 }
1381
1382 else
1383 {
1384 if (GP_REG_P (regno0))
1385 ret = (TARGET_64BIT
1386 #ifdef TARGET_FP_CALL_32
1387 && ! FP_CALL_GP_REG_P (regno0)
1388 #endif
1389 )
1390 ? "move\t%0,%."
1391 : "move\t%0,%.\n\tmove\t%D0,%.";
1392
1393 else if (FP_REG_P (regno0))
1394 {
1395 delay = DELAY_LOAD;
1396 ret = (TARGET_64BIT)
1397 ? "dmtc1\t%.,%0"
1398 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1399 }
1400 }
1401 }
1402
1403 else if (code1 == CONST_INT && INTVAL (op1) == 0)
1404 {
1405 if (GP_REG_P (regno0))
1406 ret = (TARGET_64BIT)
1407 ? "move\t%0,%."
1408 : "move\t%0,%.\n\tmove\t%D0,%.";
1409
1410 else if (FP_REG_P (regno0))
1411 {
1412 delay = DELAY_LOAD;
1413 ret = (TARGET_64BIT)
1414 ? "dmtc1\t%.,%0"
1415 : (TARGET_FLOAT64
1416 ? "li.d\t%0,%1"
1417 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1418 }
1419 else if (MD_REG_P (regno0))
1420 {
1421 delay = DELAY_HILO;
1422 if (regno0 != HILO_REGNUM)
1423 ret = "mt%0\t%.\n";
1424 else
1425 ret = "mtlo\t%.\n\tmthi\t%.";
1426 }
1427 }
1428
1429 else if (code1 == CONST_INT && GET_MODE (op0) == DImode && GP_REG_P (regno0))
1430 {
1431 if (TARGET_64BIT)
1432 {
1433 if (HOST_BITS_PER_WIDE_INT < 64)
1434 /* We can't use 'X' for negative numbers, because then we won't
1435 get the right value for the upper 32 bits. */
1436 ret = ((INTVAL (op1) < 0) ? "dli\t%0,%1\t\t\t# %X1"
1437 : "dli\t%0,%X1\t\t# %1");
1438 else
1439 /* We must use 'X', because otherwise LONG_MIN will print as
1440 a number that the assembler won't accept. */
1441 ret = "dli\t%0,%X1\t\t# %1";
1442 }
1443 else
1444 {
1445 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
1446 ret = "li\t%M0,%2\n\tli\t%L0,%1";
1447 }
1448 }
1449
1450 else if (code1 == MEM)
1451 {
1452 delay = DELAY_LOAD;
1453
1454 if (TARGET_STATS)
1455 mips_count_memory_refs (op1, 2);
1456
1457 if (FP_REG_P (regno0))
1458 ret = "l.d\t%0,%1";
1459
1460 else if (TARGET_64BIT)
1461 {
1462 #ifdef TARGET_FP_CALL_32
1463 if (FP_CALL_GP_REG_P (regno0))
1464 {
1465 if (offsettable_address_p (FALSE, SImode, op1))
1466 ret = "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1467 else
1468 ret = "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1469 }
1470 else
1471 #endif
1472 ret = "ld\t%0,%1";
1473 }
1474
1475 else if (offsettable_address_p (1, DFmode, XEXP (op1, 0)))
1476 {
1477 operands[2] = adj_offsettable_operand (op1, 4);
1478 if (reg_mentioned_p (op0, op1))
1479 ret = "lw\t%D0,%2\n\tlw\t%0,%1";
1480 else
1481 ret = "lw\t%0,%1\n\tlw\t%D0,%2";
1482 }
1483
1484 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1485 {
1486 int i = strlen (ret);
1487 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1488 abort ();
1489
1490 sprintf (volatile_buffer, "%%{%s%%}", ret);
1491 ret = volatile_buffer;
1492 }
1493 }
1494
1495 else if (code1 == LABEL_REF
1496 || code1 == SYMBOL_REF
1497 || code1 == CONST)
1498 {
1499 if (TARGET_STATS)
1500 mips_count_memory_refs (op1, 2);
1501
1502 ret = "dla\t%0,%a1";
1503 }
1504 }
1505
1506 else if (code0 == MEM)
1507 {
1508 if (code1 == REG)
1509 {
1510 int regno1 = REGNO (op1) + subreg_word1;
1511
1512 if (FP_REG_P (regno1))
1513 ret = "s.d\t%1,%0";
1514
1515 else if (TARGET_64BIT)
1516 {
1517 #ifdef TARGET_FP_CALL_32
1518 if (FP_CALL_GP_REG_P (regno1))
1519 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1520 else
1521 #endif
1522 ret = "sd\t%1,%0";
1523 }
1524
1525 else if (offsettable_address_p (1, DFmode, XEXP (op0, 0)))
1526 {
1527 operands[2] = adj_offsettable_operand (op0, 4);
1528 ret = "sw\t%1,%0\n\tsw\t%D1,%2";
1529 }
1530 }
1531
1532 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
1533 || (code1 == CONST_DOUBLE
1534 && op1 == CONST0_RTX (GET_MODE (op1))))
1535 && (TARGET_64BIT
1536 || offsettable_address_p (1, DFmode, XEXP (op0, 0))))
1537 {
1538 if (TARGET_64BIT)
1539 ret = "sd\t%.,%0";
1540 else
1541 {
1542 operands[2] = adj_offsettable_operand (op0, 4);
1543 ret = "sw\t%.,%0\n\tsw\t%.,%2";
1544 }
1545 }
1546
1547 if (TARGET_STATS)
1548 mips_count_memory_refs (op0, 2);
1549
1550 if (ret != (char *)0 && MEM_VOLATILE_P (op0))
1551 {
1552 int i = strlen (ret);
1553 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1554 abort ();
1555
1556 sprintf (volatile_buffer, "%%{%s%%}", ret);
1557 ret = volatile_buffer;
1558 }
1559 }
1560
1561 if (ret == (char *)0)
1562 {
1563 abort_with_insn (insn, "Bad move");
1564 return 0;
1565 }
1566
1567 if (delay != DELAY_NONE)
1568 return mips_fill_delay_slot (ret, delay, operands, insn);
1569
1570 return ret;
1571 }
1572
1573 \f
1574 /* Provide the costs of an addressing mode that contains ADDR.
1575 If ADDR is not a valid address, its cost is irrelevant. */
1576
1577 int
1578 mips_address_cost (addr)
1579 rtx addr;
1580 {
1581 switch (GET_CODE (addr))
1582 {
1583 default:
1584 break;
1585
1586 case LO_SUM:
1587 case HIGH:
1588 return 1;
1589
1590 case LABEL_REF:
1591 return 2;
1592
1593 case CONST:
1594 {
1595 rtx offset = const0_rtx;
1596 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
1597 if (GET_CODE (addr) == LABEL_REF)
1598 return 2;
1599
1600 if (GET_CODE (addr) != SYMBOL_REF)
1601 return 4;
1602
1603 if (! SMALL_INT (offset))
1604 return 2;
1605 }
1606 /* fall through */
1607
1608 case SYMBOL_REF:
1609 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
1610
1611 case PLUS:
1612 {
1613 register rtx plus0 = XEXP (addr, 0);
1614 register rtx plus1 = XEXP (addr, 1);
1615
1616 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1617 {
1618 plus0 = XEXP (addr, 1);
1619 plus1 = XEXP (addr, 0);
1620 }
1621
1622 if (GET_CODE (plus0) != REG)
1623 break;
1624
1625 switch (GET_CODE (plus1))
1626 {
1627 default:
1628 break;
1629
1630 case CONST_INT:
1631 return (SMALL_INT (plus1) ? 1 : 2);
1632
1633 case CONST:
1634 case SYMBOL_REF:
1635 case LABEL_REF:
1636 case HIGH:
1637 case LO_SUM:
1638 return mips_address_cost (plus1) + 1;
1639 }
1640 }
1641 }
1642
1643 return 4;
1644 }
1645
1646 /* Return true if X is an address which needs a temporary register when
1647 reloaded while generating PIC code. */
1648
1649 int
1650 pic_address_needs_scratch (x)
1651 rtx x;
1652 {
1653 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1654 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
1655 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1656 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1657 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
1658 return 1;
1659
1660 return 0;
1661 }
1662 \f
1663 /* Make normal rtx_code into something we can index from an array */
1664
1665 static enum internal_test
1666 map_test_to_internal_test (test_code)
1667 enum rtx_code test_code;
1668 {
1669 enum internal_test test = ITEST_MAX;
1670
1671 switch (test_code)
1672 {
1673 default: break;
1674 case EQ: test = ITEST_EQ; break;
1675 case NE: test = ITEST_NE; break;
1676 case GT: test = ITEST_GT; break;
1677 case GE: test = ITEST_GE; break;
1678 case LT: test = ITEST_LT; break;
1679 case LE: test = ITEST_LE; break;
1680 case GTU: test = ITEST_GTU; break;
1681 case GEU: test = ITEST_GEU; break;
1682 case LTU: test = ITEST_LTU; break;
1683 case LEU: test = ITEST_LEU; break;
1684 }
1685
1686 return test;
1687 }
1688
1689 \f
1690 /* Generate the code to compare two integer values. The return value is:
1691 (reg:SI xx) The pseudo register the comparison is in
1692 (rtx)0 No register, generate a simple branch.
1693
1694 ??? This is called with result nonzero by the Scond patterns in
1695 mips.md. These patterns are called with a target in the mode of
1696 the Scond instruction pattern. Since this must be a constant, we
1697 must use SImode. This means that if RESULT is non-zero, it will
1698 always be an SImode register, even if TARGET_64BIT is true. We
1699 cope with this by calling convert_move rather than emit_move_insn.
1700 This will sometimes lead to an unnecessary extension of the result;
1701 for example:
1702
1703 long long
1704 foo (long long i)
1705 {
1706 return i < 5;
1707 }
1708
1709 */
1710
1711 rtx
1712 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
1713 enum rtx_code test_code; /* relational test (EQ, etc) */
1714 rtx result; /* result to store comp. or 0 if branch */
1715 rtx cmp0; /* first operand to compare */
1716 rtx cmp1; /* second operand to compare */
1717 int *p_invert; /* NULL or ptr to hold whether branch needs */
1718 /* to reverse its test */
1719 {
1720 struct cmp_info {
1721 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
1722 int const_low; /* low bound of constant we can accept */
1723 int const_high; /* high bound of constant we can accept */
1724 int const_add; /* constant to add (convert LE -> LT) */
1725 int reverse_regs; /* reverse registers in test */
1726 int invert_const; /* != 0 if invert value if cmp1 is constant */
1727 int invert_reg; /* != 0 if invert value if cmp1 is register */
1728 int unsignedp; /* != 0 for unsigned comparisons. */
1729 };
1730
1731 static struct cmp_info info[ (int)ITEST_MAX ] = {
1732
1733 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
1734 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
1735 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
1736 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
1737 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
1738 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
1739 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
1740 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
1741 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
1742 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
1743 };
1744
1745 enum internal_test test;
1746 enum machine_mode mode;
1747 struct cmp_info *p_info;
1748 int branch_p;
1749 int eqne_p;
1750 int invert;
1751 rtx reg;
1752 rtx reg2;
1753
1754 test = map_test_to_internal_test (test_code);
1755 if (test == ITEST_MAX)
1756 abort ();
1757
1758 p_info = &info[ (int)test ];
1759 eqne_p = (p_info->test_code == XOR);
1760
1761 mode = GET_MODE (cmp0);
1762 if (mode == VOIDmode)
1763 mode = GET_MODE (cmp1);
1764
1765 /* Eliminate simple branches */
1766 branch_p = (result == (rtx)0);
1767 if (branch_p)
1768 {
1769 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
1770 {
1771 /* Comparisons against zero are simple branches */
1772 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
1773 return (rtx)0;
1774
1775 /* Test for beq/bne. */
1776 if (eqne_p)
1777 return (rtx)0;
1778 }
1779
1780 /* allocate a pseudo to calculate the value in. */
1781 result = gen_reg_rtx (mode);
1782 }
1783
1784 /* Make sure we can handle any constants given to us. */
1785 if (GET_CODE (cmp0) == CONST_INT)
1786 cmp0 = force_reg (mode, cmp0);
1787
1788 if (GET_CODE (cmp1) == CONST_INT)
1789 {
1790 HOST_WIDE_INT value = INTVAL (cmp1);
1791 if (value < p_info->const_low
1792 || value > p_info->const_high
1793 /* ??? Why? And why wasn't the similar code below modified too? */
1794 || (TARGET_64BIT
1795 && HOST_BITS_PER_WIDE_INT < 64
1796 && p_info->const_add != 0
1797 && ((p_info->unsignedp
1798 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
1799 > INTVAL (cmp1))
1800 : (value + p_info->const_add) > INTVAL (cmp1))
1801 != (p_info->const_add > 0))))
1802 cmp1 = force_reg (mode, cmp1);
1803 }
1804
1805 /* See if we need to invert the result. */
1806 invert = (GET_CODE (cmp1) == CONST_INT)
1807 ? p_info->invert_const
1808 : p_info->invert_reg;
1809
1810 if (p_invert != (int *)0)
1811 {
1812 *p_invert = invert;
1813 invert = FALSE;
1814 }
1815
1816 /* Comparison to constants, may involve adding 1 to change a LT into LE.
1817 Comparison between two registers, may involve switching operands. */
1818 if (GET_CODE (cmp1) == CONST_INT)
1819 {
1820 if (p_info->const_add != 0)
1821 {
1822 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
1823 /* If modification of cmp1 caused overflow,
1824 we would get the wrong answer if we follow the usual path;
1825 thus, x > 0xffffffffu would turn into x > 0u. */
1826 if ((p_info->unsignedp
1827 ? (unsigned HOST_WIDE_INT) new > INTVAL (cmp1)
1828 : new > INTVAL (cmp1))
1829 != (p_info->const_add > 0))
1830 {
1831 /* This test is always true, but if INVERT is true then
1832 the result of the test needs to be inverted so 0 should
1833 be returned instead. */
1834 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
1835 return result;
1836 }
1837 else
1838 cmp1 = GEN_INT (new);
1839 }
1840 }
1841 else if (p_info->reverse_regs)
1842 {
1843 rtx temp = cmp0;
1844 cmp0 = cmp1;
1845 cmp1 = temp;
1846 }
1847
1848 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
1849 reg = cmp0;
1850 else
1851 {
1852 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
1853 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
1854 }
1855
1856 if (test == ITEST_NE)
1857 {
1858 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
1859 invert = FALSE;
1860 }
1861
1862 else if (test == ITEST_EQ)
1863 {
1864 reg2 = (invert) ? gen_reg_rtx (mode) : result;
1865 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
1866 reg = reg2;
1867 }
1868
1869 if (invert)
1870 convert_move (result, gen_rtx (XOR, mode, reg, const1_rtx), 0);
1871
1872 return result;
1873 }
1874
1875 \f
1876 /* Emit the common code for doing conditional branches.
1877 operand[0] is the label to jump to.
1878 The comparison operands are saved away by cmp{si,di,sf,df}. */
1879
1880 void
1881 gen_conditional_branch (operands, test_code)
1882 rtx operands[];
1883 enum rtx_code test_code;
1884 {
1885 static enum machine_mode mode_map[(int)CMP_MAX][(int)ITEST_MAX] = {
1886 { /* CMP_SI */
1887 SImode, /* eq */
1888 SImode, /* ne */
1889 SImode, /* gt */
1890 SImode, /* ge */
1891 SImode, /* lt */
1892 SImode, /* le */
1893 SImode, /* gtu */
1894 SImode, /* geu */
1895 SImode, /* ltu */
1896 SImode, /* leu */
1897 },
1898 { /* CMP_DI */
1899 DImode, /* eq */
1900 DImode, /* ne */
1901 DImode, /* gt */
1902 DImode, /* ge */
1903 DImode, /* lt */
1904 DImode, /* le */
1905 DImode, /* gtu */
1906 DImode, /* geu */
1907 DImode, /* ltu */
1908 DImode, /* leu */
1909 },
1910 { /* CMP_SF */
1911 CC_FPmode, /* eq */
1912 CC_REV_FPmode, /* ne */
1913 CC_FPmode, /* gt */
1914 CC_FPmode, /* ge */
1915 CC_FPmode, /* lt */
1916 CC_FPmode, /* le */
1917 VOIDmode, /* gtu */
1918 VOIDmode, /* geu */
1919 VOIDmode, /* ltu */
1920 VOIDmode, /* leu */
1921 },
1922 { /* CMP_DF */
1923 CC_FPmode, /* eq */
1924 CC_REV_FPmode, /* ne */
1925 CC_FPmode, /* gt */
1926 CC_FPmode, /* ge */
1927 CC_FPmode, /* lt */
1928 CC_FPmode, /* le */
1929 VOIDmode, /* gtu */
1930 VOIDmode, /* geu */
1931 VOIDmode, /* ltu */
1932 VOIDmode, /* leu */
1933 },
1934 };
1935
1936 enum machine_mode mode;
1937 enum cmp_type type = branch_type;
1938 rtx cmp0 = branch_cmp[0];
1939 rtx cmp1 = branch_cmp[1];
1940 rtx label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]);
1941 rtx label2 = pc_rtx;
1942 rtx reg = (rtx)0;
1943 int invert = 0;
1944 enum internal_test test = map_test_to_internal_test (test_code);
1945
1946 if (test == ITEST_MAX)
1947 {
1948 mode = word_mode;
1949 goto fail;
1950 }
1951
1952 /* Get the machine mode to use (CCmode, CC_EQmode, CC_FPmode, or CC_REV_FPmode). */
1953 mode = mode_map[(int)type][(int)test];
1954 if (mode == VOIDmode)
1955 goto fail;
1956
1957 switch (type)
1958 {
1959 default:
1960 goto fail;
1961
1962 case CMP_SI:
1963 case CMP_DI:
1964 reg = gen_int_relational (test_code, (rtx)0, cmp0, cmp1, &invert);
1965 if (reg != (rtx)0)
1966 {
1967 cmp0 = reg;
1968 cmp1 = const0_rtx;
1969 test_code = NE;
1970 }
1971
1972 /* Make sure not non-zero constant if ==/!= */
1973 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
1974 cmp1 = force_reg (mode, cmp1);
1975
1976 break;
1977
1978 case CMP_DF:
1979 case CMP_SF:
1980 {
1981 rtx reg = gen_rtx (REG, mode, FPSW_REGNUM);
1982 emit_insn (gen_rtx (SET, VOIDmode, reg, gen_rtx (test_code, mode, cmp0, cmp1)));
1983 cmp0 = reg;
1984 cmp1 = const0_rtx;
1985 test_code = NE;
1986 }
1987 break;
1988 }
1989
1990 /* Generate the jump */
1991 if (invert)
1992 {
1993 label2 = label1;
1994 label1 = pc_rtx;
1995 }
1996
1997 emit_jump_insn (gen_rtx (SET, VOIDmode,
1998 pc_rtx,
1999 gen_rtx (IF_THEN_ELSE, VOIDmode,
2000 gen_rtx (test_code, mode, cmp0, cmp1),
2001 label1,
2002 label2)));
2003
2004 return;
2005
2006 fail:
2007 abort_with_insn (gen_rtx (test_code, mode, cmp0, cmp1), "bad test");
2008 }
2009
2010 \f
2011 #if 0
2012 /* Internal code to generate the load and store of one word/short/byte.
2013 The load is emitted directly, and the store insn is returned. */
2014
2015 #define UNITS_PER_MIPS_DWORD 8
2016 #define UNITS_PER_MIPS_WORD 4
2017 #define UNITS_PER_MIPS_HWORD 2
2018
2019 static rtx
2020 block_move_load_store (dest_reg, src_reg, p_bytes, p_offset, align, orig_src)
2021 rtx src_reg; /* register holding source memory address */
2022 rtx dest_reg; /* register holding dest. memory address */
2023 int *p_bytes; /* pointer to # bytes remaining */
2024 int *p_offset; /* pointer to current offset */
2025 int align; /* alignment */
2026 rtx orig_src; /* original source for making a reg note */
2027 {
2028 int bytes; /* # bytes remaining */
2029 int offset; /* offset to use */
2030 int size; /* size in bytes of load/store */
2031 enum machine_mode mode; /* mode to use for load/store */
2032 rtx reg; /* temporary register */
2033 rtx src_addr; /* source address */
2034 rtx dest_addr; /* destination address */
2035 rtx insn; /* insn of the load */
2036 rtx orig_src_addr; /* original source address */
2037 rtx (*load_func)(); /* function to generate load insn */
2038 rtx (*store_func)(); /* function to generate destination insn */
2039
2040 bytes = *p_bytes;
2041 if (bytes <= 0 || align <= 0)
2042 abort ();
2043
2044 if (bytes >= UNITS_PER_MIPS_DWORD && align >= UNIS_PER_MIPS_DWORD)
2045 {
2046 mode = DImode;
2047 size = UNITS_PER_MIPS_DWORD;
2048 load_func = gen_movdi;
2049 store_func = gen_movdi;
2050 }
2051 else if (bytes >= UNITS_PER_MIPS_WORD && align >= UNITS_PER_MIPS_WORD)
2052 {
2053 mode = SImode;
2054 size = UNITS_PER_MIPS_WORD;
2055 load_func = gen_movsi;
2056 store_func = gen_movsi;
2057 }
2058
2059 #if 0
2060 /* Don't generate unaligned moves here, rather defer those to the
2061 general movestrsi_internal pattern.
2062 If this gets commented back in, then should add the dword equivalent. */
2063 else if (bytes >= UNITS_PER_MIPS_WORD)
2064 {
2065 mode = SImode;
2066 size = UNITS_PER_MIPS_WORD;
2067 load_func = gen_movsi_ulw;
2068 store_func = gen_movsi_usw;
2069 }
2070 #endif
2071
2072 else if (bytes >= UNITS_PER_MIPS_SHORT && align >= UNITS_PER_MIPS_SHORT)
2073 {
2074 mode = HImode;
2075 size = UNITS_PER_MIPS_SHORT;
2076 load_func = gen_movhi;
2077 store_func = gen_movhi;
2078 }
2079
2080 else
2081 {
2082 mode = QImode;
2083 size = 1;
2084 load_func = gen_movqi;
2085 store_func = gen_movqi;
2086 }
2087
2088 offset = *p_offset;
2089 *p_offset = offset + size;
2090 *p_bytes = bytes - size;
2091
2092 if (offset == 0)
2093 {
2094 src_addr = src_reg;
2095 dest_addr = dest_reg;
2096 }
2097 else
2098 {
2099 src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset));
2100 dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset));
2101 }
2102
2103 reg = gen_reg_rtx (mode);
2104 insn = emit_insn ((*load_func) (reg, gen_rtx (MEM, mode, src_addr)));
2105 orig_src_addr = XEXP (orig_src, 0);
2106 if (CONSTANT_P (orig_src_addr))
2107 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUIV,
2108 plus_constant (orig_src_addr, offset),
2109 REG_NOTES (insn));
2110
2111 return (*store_func) (gen_rtx (MEM, mode, dest_addr), reg);
2112 }
2113 #endif
2114
2115 \f
2116 /* Write a series of loads/stores to move some bytes. Generate load/stores as follows:
2117
2118 load 1
2119 load 2
2120 load 3
2121 store 1
2122 load 4
2123 store 2
2124 load 5
2125 store 3
2126 ...
2127
2128 This way, no NOP's are needed, except at the end, and only
2129 two temp registers are needed. Two delay slots are used
2130 in deference to the R4000. */
2131
2132 #if 0
2133 static void
2134 block_move_sequence (dest_reg, src_reg, bytes, align, orig_src)
2135 rtx dest_reg; /* register holding destination address */
2136 rtx src_reg; /* register holding source address */
2137 int bytes; /* # bytes to move */
2138 int align; /* max alignment to assume */
2139 rtx orig_src; /* original source for making a reg note */
2140 {
2141 int offset = 0;
2142 rtx prev2_store = (rtx)0;
2143 rtx prev_store = (rtx)0;
2144 rtx cur_store = (rtx)0;
2145
2146 while (bytes > 0)
2147 {
2148 /* Is there a store to do? */
2149 if (prev2_store)
2150 emit_insn (prev2_store);
2151
2152 prev2_store = prev_store;
2153 prev_store = cur_store;
2154 cur_store = block_move_load_store (dest_reg, src_reg,
2155 &bytes, &offset,
2156 align, orig_src);
2157 }
2158
2159 /* Finish up last three stores. */
2160 if (prev2_store)
2161 emit_insn (prev2_store);
2162
2163 if (prev_store)
2164 emit_insn (prev_store);
2165
2166 if (cur_store)
2167 emit_insn (cur_store);
2168 }
2169 #endif
2170
2171 \f
2172 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2173
2174 do {
2175 temp1 = src[0];
2176 temp2 = src[1];
2177 ...
2178 temp<last> = src[MAX_MOVE_REGS-1];
2179 dest[0] = temp1;
2180 dest[1] = temp2;
2181 ...
2182 dest[MAX_MOVE_REGS-1] = temp<last>;
2183 src += MAX_MOVE_REGS;
2184 dest += MAX_MOVE_REGS;
2185 } while (src != final);
2186
2187 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2188 registers are needed.
2189
2190 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2191 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2192 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2193
2194 #define MAX_MOVE_REGS 4
2195 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2196
2197 /* ??? Should add code to use DWORD load/stores. */
2198
2199 static void
2200 block_move_loop (dest_reg, src_reg, bytes, align, orig_src)
2201 rtx dest_reg; /* register holding destination address */
2202 rtx src_reg; /* register holding source address */
2203 int bytes; /* # bytes to move */
2204 int align; /* alignment */
2205 rtx orig_src; /* original source for making a reg note */
2206 {
2207 rtx dest_mem = gen_rtx (MEM, BLKmode, dest_reg);
2208 rtx src_mem = gen_rtx (MEM, BLKmode, src_reg);
2209 rtx align_rtx = GEN_INT (align);
2210 rtx label;
2211 rtx final_src;
2212 rtx bytes_rtx;
2213 int leftover;
2214
2215 if (bytes < 2*MAX_MOVE_BYTES)
2216 abort ();
2217
2218 leftover = bytes % MAX_MOVE_BYTES;
2219 bytes -= leftover;
2220
2221 label = gen_label_rtx ();
2222 final_src = gen_reg_rtx (Pmode);
2223 bytes_rtx = GEN_INT (bytes);
2224
2225 if (bytes > 0x7fff)
2226 {
2227 if (TARGET_LONG64)
2228 {
2229 emit_insn (gen_movdi (final_src, bytes_rtx));
2230 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
2231 }
2232 else
2233 {
2234 emit_insn (gen_movsi (final_src, bytes_rtx));
2235 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2236 }
2237 }
2238 else
2239 {
2240 if (TARGET_LONG64)
2241 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
2242 else
2243 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
2244 }
2245
2246 emit_label (label);
2247
2248 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
2249 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
2250 if (TARGET_LONG64)
2251 {
2252 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
2253 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
2254 emit_insn (gen_cmpdi (src_reg, final_src));
2255 }
2256 else
2257 {
2258 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
2259 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
2260 emit_insn (gen_cmpsi (src_reg, final_src));
2261 }
2262 emit_jump_insn (gen_bne (label));
2263
2264 if (leftover)
2265 emit_insn (gen_movstrsi_internal (dest_mem, src_mem,
2266 GEN_INT (leftover),
2267 align_rtx));
2268 }
2269
2270 \f
2271 /* Use a library function to move some bytes. */
2272
2273 static void
2274 block_move_call (dest_reg, src_reg, bytes_rtx)
2275 rtx dest_reg;
2276 rtx src_reg;
2277 rtx bytes_rtx;
2278 {
2279 /* We want to pass the size as Pmode, which will normally be SImode
2280 but will be DImode if we are using 64 bit longs and pointers. */
2281 if (GET_MODE (bytes_rtx) != VOIDmode
2282 && GET_MODE (bytes_rtx) != Pmode)
2283 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, TRUE);
2284
2285 #ifdef TARGET_MEM_FUNCTIONS
2286 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2287 VOIDmode, 3,
2288 dest_reg, Pmode,
2289 src_reg, Pmode,
2290 bytes_rtx, Pmode);
2291 #else
2292 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2293 VOIDmode, 3,
2294 src_reg, Pmode,
2295 dest_reg, Pmode,
2296 bytes_rtx, Pmode);
2297 #endif
2298 }
2299
2300 \f
2301 /* Expand string/block move operations.
2302
2303 operands[0] is the pointer to the destination.
2304 operands[1] is the pointer to the source.
2305 operands[2] is the number of bytes to move.
2306 operands[3] is the alignment. */
2307
2308 void
2309 expand_block_move (operands)
2310 rtx operands[];
2311 {
2312 rtx bytes_rtx = operands[2];
2313 rtx align_rtx = operands[3];
2314 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2315 int bytes = (constp ? INTVAL (bytes_rtx) : 0);
2316 int align = INTVAL (align_rtx);
2317 rtx orig_src = operands[1];
2318 rtx src_reg;
2319 rtx dest_reg;
2320
2321 if (constp && bytes <= 0)
2322 return;
2323
2324 if (align > UNITS_PER_WORD)
2325 align = UNITS_PER_WORD;
2326
2327 /* Move the address into scratch registers. */
2328 dest_reg = copy_addr_to_reg (XEXP (operands[0], 0));
2329 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2330
2331 if (TARGET_MEMCPY)
2332 block_move_call (dest_reg, src_reg, bytes_rtx);
2333
2334 #if 0
2335 else if (constp && bytes <= 3*align)
2336 block_move_sequence (dest_reg, src_reg, bytes, align, orig_src);
2337 #endif
2338
2339 else if (constp && bytes <= 2*MAX_MOVE_BYTES)
2340 emit_insn (gen_movstrsi_internal (gen_rtx (MEM, BLKmode, dest_reg),
2341 gen_rtx (MEM, BLKmode, src_reg),
2342 bytes_rtx, align_rtx));
2343
2344 else if (constp && align >= UNITS_PER_WORD && optimize)
2345 block_move_loop (dest_reg, src_reg, bytes, align, orig_src);
2346
2347 else if (constp && optimize)
2348 {
2349 /* If the alignment is not word aligned, generate a test at
2350 runtime, to see whether things wound up aligned, and we
2351 can use the faster lw/sw instead ulw/usw. */
2352
2353 rtx temp = gen_reg_rtx (Pmode);
2354 rtx aligned_label = gen_label_rtx ();
2355 rtx join_label = gen_label_rtx ();
2356 int leftover = bytes % MAX_MOVE_BYTES;
2357
2358 bytes -= leftover;
2359
2360 if (TARGET_LONG64)
2361 {
2362 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
2363 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD-1)));
2364 emit_insn (gen_cmpdi (temp, const0_rtx));
2365 }
2366 else
2367 {
2368 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
2369 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD-1)));
2370 emit_insn (gen_cmpsi (temp, const0_rtx));
2371 }
2372 emit_jump_insn (gen_beq (aligned_label));
2373
2374 /* Unaligned loop. */
2375 block_move_loop (dest_reg, src_reg, bytes, 1, orig_src);
2376 emit_jump_insn (gen_jump (join_label));
2377 emit_barrier ();
2378
2379 /* Aligned loop. */
2380 emit_label (aligned_label);
2381 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_src);
2382 emit_label (join_label);
2383
2384 /* Bytes at the end of the loop. */
2385 if (leftover)
2386 {
2387 #if 0
2388 if (leftover <= 3*align)
2389 block_move_sequence (dest_reg, src_reg, leftover, align, orig_src);
2390
2391 else
2392 #endif
2393 emit_insn (gen_movstrsi_internal (gen_rtx (MEM, BLKmode, dest_reg),
2394 gen_rtx (MEM, BLKmode, src_reg),
2395 GEN_INT (leftover),
2396 GEN_INT (align)));
2397 }
2398 }
2399
2400 else
2401 block_move_call (dest_reg, src_reg, bytes_rtx);
2402 }
2403
2404 \f
2405 /* Emit load/stores for a small constant block_move.
2406
2407 operands[0] is the memory address of the destination.
2408 operands[1] is the memory address of the source.
2409 operands[2] is the number of bytes to move.
2410 operands[3] is the alignment.
2411 operands[4] is a temp register.
2412 operands[5] is a temp register.
2413 ...
2414 operands[3+num_regs] is the last temp register.
2415
2416 The block move type can be one of the following:
2417 BLOCK_MOVE_NORMAL Do all of the block move.
2418 BLOCK_MOVE_NOT_LAST Do all but the last store.
2419 BLOCK_MOVE_LAST Do just the last store. */
2420
2421 char *
2422 output_block_move (insn, operands, num_regs, move_type)
2423 rtx insn;
2424 rtx operands[];
2425 int num_regs;
2426 enum block_move_type move_type;
2427 {
2428 rtx dest_reg = XEXP (operands[0], 0);
2429 rtx src_reg = XEXP (operands[1], 0);
2430 int bytes = INTVAL (operands[2]);
2431 int align = INTVAL (operands[3]);
2432 int num = 0;
2433 int offset = 0;
2434 int use_lwl_lwr = FALSE;
2435 int last_operand = num_regs+4;
2436 int safe_regs = 4;
2437 int i;
2438 rtx xoperands[10];
2439
2440 struct {
2441 char *load; /* load insn without nop */
2442 char *load_nop; /* load insn with trailing nop */
2443 char *store; /* store insn */
2444 char *final; /* if last_store used: NULL or swr */
2445 char *last_store; /* last store instruction */
2446 int offset; /* current offset */
2447 enum machine_mode mode; /* mode to use on (MEM) */
2448 } load_store[4];
2449
2450 /* Detect a bug in GCC, where it can give us a register
2451 the same as one of the addressing registers and reduce
2452 the number of registers available. */
2453 for (i = 4;
2454 i < last_operand && safe_regs < (sizeof(xoperands) / sizeof(xoperands[0]));
2455 i++)
2456 {
2457 if (!reg_mentioned_p (operands[i], operands[0])
2458 && !reg_mentioned_p (operands[i], operands[1]))
2459
2460 xoperands[safe_regs++] = operands[i];
2461 }
2462
2463 if (safe_regs < last_operand)
2464 {
2465 xoperands[0] = operands[0];
2466 xoperands[1] = operands[1];
2467 xoperands[2] = operands[2];
2468 xoperands[3] = operands[3];
2469 return output_block_move (insn, xoperands, safe_regs-4, move_type);
2470 }
2471
2472 /* If we are given global or static addresses, and we would be
2473 emitting a few instructions, try to save time by using a
2474 temporary register for the pointer. */
2475 if (num_regs > 2 && (bytes > 2*align || move_type != BLOCK_MOVE_NORMAL))
2476 {
2477 if (CONSTANT_P (src_reg))
2478 {
2479 if (TARGET_STATS)
2480 mips_count_memory_refs (operands[1], 1);
2481
2482 src_reg = operands[ 3 + num_regs-- ];
2483 if (move_type != BLOCK_MOVE_LAST)
2484 {
2485 xoperands[1] = operands[1];
2486 xoperands[0] = src_reg;
2487 if (Pmode == DImode)
2488 output_asm_insn ("dla\t%0,%1", xoperands);
2489 else
2490 output_asm_insn ("la\t%0,%1", xoperands);
2491 }
2492 }
2493
2494 if (CONSTANT_P (dest_reg))
2495 {
2496 if (TARGET_STATS)
2497 mips_count_memory_refs (operands[0], 1);
2498
2499 dest_reg = operands[ 3 + num_regs-- ];
2500 if (move_type != BLOCK_MOVE_LAST)
2501 {
2502 xoperands[1] = operands[0];
2503 xoperands[0] = dest_reg;
2504 if (Pmode == DImode)
2505 output_asm_insn ("dla\t%0,%1", xoperands);
2506 else
2507 output_asm_insn ("la\t%0,%1", xoperands);
2508 }
2509 }
2510 }
2511
2512 if (num_regs > (sizeof (load_store) / sizeof (load_store[0])))
2513 num_regs = (sizeof (load_store) / sizeof (load_store[0]));
2514
2515 else if (num_regs < 1)
2516 abort_with_insn (insn, "Cannot do block move, not enough scratch registers");
2517
2518 while (bytes > 0)
2519 {
2520 load_store[num].offset = offset;
2521
2522 if (TARGET_64BIT && bytes >= 8 && align >= 8)
2523 {
2524 load_store[num].load = "ld\t%0,%1";
2525 load_store[num].load_nop = "ld\t%0,%1%#";
2526 load_store[num].store = "sd\t%0,%1";
2527 load_store[num].last_store = "sd\t%0,%1";
2528 load_store[num].final = (char *)0;
2529 load_store[num].mode = DImode;
2530 offset += 8;
2531 bytes -= 8;
2532 }
2533
2534 /* ??? Fails because of a MIPS assembler bug? */
2535 else if (TARGET_64BIT && bytes >= 8)
2536 {
2537 if (BYTES_BIG_ENDIAN)
2538 {
2539 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
2540 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
2541 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
2542 load_store[num].last_store = "sdr\t%0,%2";
2543 load_store[num].final = "sdl\t%0,%1";
2544 }
2545 else
2546 {
2547 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
2548 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
2549 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
2550 load_store[num].last_store = "sdr\t%0,%1";
2551 load_store[num].final = "sdl\t%0,%2";
2552 }
2553 load_store[num].mode = DImode;
2554 offset += 8;
2555 bytes -= 8;
2556 use_lwl_lwr = TRUE;
2557 }
2558
2559 else if (bytes >= 4 && align >= 4)
2560 {
2561 load_store[num].load = "lw\t%0,%1";
2562 load_store[num].load_nop = "lw\t%0,%1%#";
2563 load_store[num].store = "sw\t%0,%1";
2564 load_store[num].last_store = "sw\t%0,%1";
2565 load_store[num].final = (char *)0;
2566 load_store[num].mode = SImode;
2567 offset += 4;
2568 bytes -= 4;
2569 }
2570
2571 else if (bytes >= 4)
2572 {
2573 if (BYTES_BIG_ENDIAN)
2574 {
2575 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
2576 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2577 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
2578 load_store[num].last_store = "swr\t%0,%2";
2579 load_store[num].final = "swl\t%0,%1";
2580 }
2581 else
2582 {
2583 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
2584 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2585 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
2586 load_store[num].last_store = "swr\t%0,%1";
2587 load_store[num].final = "swl\t%0,%2";
2588 }
2589 load_store[num].mode = SImode;
2590 offset += 4;
2591 bytes -= 4;
2592 use_lwl_lwr = TRUE;
2593 }
2594
2595 else if (bytes >= 2 && align >= 2)
2596 {
2597 load_store[num].load = "lh\t%0,%1";
2598 load_store[num].load_nop = "lh\t%0,%1%#";
2599 load_store[num].store = "sh\t%0,%1";
2600 load_store[num].last_store = "sh\t%0,%1";
2601 load_store[num].final = (char *)0;
2602 load_store[num].mode = HImode;
2603 offset += 2;
2604 bytes -= 2;
2605 }
2606
2607 else
2608 {
2609 load_store[num].load = "lb\t%0,%1";
2610 load_store[num].load_nop = "lb\t%0,%1%#";
2611 load_store[num].store = "sb\t%0,%1";
2612 load_store[num].last_store = "sb\t%0,%1";
2613 load_store[num].final = (char *)0;
2614 load_store[num].mode = QImode;
2615 offset++;
2616 bytes--;
2617 }
2618
2619 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
2620 {
2621 dslots_load_total++;
2622 dslots_load_filled++;
2623
2624 if (CONSTANT_P (src_reg))
2625 mips_count_memory_refs (src_reg, 1);
2626
2627 if (CONSTANT_P (dest_reg))
2628 mips_count_memory_refs (dest_reg, 1);
2629 }
2630
2631 /* Emit load/stores now if we have run out of registers or are
2632 at the end of the move. */
2633
2634 if (++num == num_regs || bytes == 0)
2635 {
2636 /* If only load/store, we need a NOP after the load. */
2637 if (num == 1)
2638 {
2639 load_store[0].load = load_store[0].load_nop;
2640 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
2641 dslots_load_filled--;
2642 }
2643
2644 if (move_type != BLOCK_MOVE_LAST)
2645 {
2646 for (i = 0; i < num; i++)
2647 {
2648 int offset;
2649
2650 if (!operands[i+4])
2651 abort ();
2652
2653 if (GET_MODE (operands[i+4]) != load_store[i].mode)
2654 operands[i+4] = gen_rtx (REG, load_store[i].mode, REGNO (operands[i+4]));
2655
2656 offset = load_store[i].offset;
2657 xoperands[0] = operands[i+4];
2658 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
2659 plus_constant (src_reg, offset));
2660
2661 if (use_lwl_lwr)
2662 {
2663 int extra_offset;
2664 extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
2665 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
2666 plus_constant (src_reg,
2667 extra_offset
2668 + offset));
2669 }
2670
2671 output_asm_insn (load_store[i].load, xoperands);
2672 }
2673 }
2674
2675 for (i = 0; i < num; i++)
2676 {
2677 int last_p = (i == num-1 && bytes == 0);
2678 int offset = load_store[i].offset;
2679
2680 xoperands[0] = operands[i+4];
2681 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
2682 plus_constant (dest_reg, offset));
2683
2684
2685 if (use_lwl_lwr)
2686 {
2687 int extra_offset;
2688 extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
2689 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
2690 plus_constant (dest_reg,
2691 extra_offset
2692 + offset));
2693 }
2694
2695 if (move_type == BLOCK_MOVE_NORMAL)
2696 output_asm_insn (load_store[i].store, xoperands);
2697
2698 else if (move_type == BLOCK_MOVE_NOT_LAST)
2699 {
2700 if (!last_p)
2701 output_asm_insn (load_store[i].store, xoperands);
2702
2703 else if (load_store[i].final != (char *)0)
2704 output_asm_insn (load_store[i].final, xoperands);
2705 }
2706
2707 else if (last_p)
2708 output_asm_insn (load_store[i].last_store, xoperands);
2709 }
2710
2711 num = 0; /* reset load_store */
2712 use_lwl_lwr = FALSE;
2713 }
2714 }
2715
2716 return "";
2717 }
2718
2719 \f
2720 /* Argument support functions. */
2721
2722 /* Initialize CUMULATIVE_ARGS for a function. */
2723
2724 void
2725 init_cumulative_args (cum, fntype, libname)
2726 CUMULATIVE_ARGS *cum; /* argument info to initialize */
2727 tree fntype; /* tree ptr for function decl */
2728 rtx libname; /* SYMBOL_REF of library name or 0 */
2729 {
2730 static CUMULATIVE_ARGS zero_cum;
2731 tree param, next_param;
2732
2733 if (TARGET_DEBUG_E_MODE)
2734 {
2735 fprintf (stderr, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
2736 if (!fntype)
2737 fputc ('\n', stderr);
2738
2739 else
2740 {
2741 tree ret_type = TREE_TYPE (fntype);
2742 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
2743 tree_code_name[ (int)TREE_CODE (fntype) ],
2744 tree_code_name[ (int)TREE_CODE (ret_type) ]);
2745 }
2746 }
2747
2748 *cum = zero_cum;
2749
2750 /* Determine if this function has variable arguments. This is
2751 indicated by the last argument being 'void_type_mode' if there
2752 are no variable arguments. The standard MIPS calling sequence
2753 passes all arguments in the general purpose registers in this
2754 case. */
2755
2756 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
2757 param != (tree)0;
2758 param = next_param)
2759 {
2760 next_param = TREE_CHAIN (param);
2761 if (next_param == (tree)0 && TREE_VALUE (param) != void_type_node)
2762 cum->gp_reg_found = 1;
2763 }
2764 }
2765
2766 /* Advance the argument to the next argument position. */
2767
2768 void
2769 function_arg_advance (cum, mode, type, named)
2770 CUMULATIVE_ARGS *cum; /* current arg information */
2771 enum machine_mode mode; /* current arg mode */
2772 tree type; /* type of the argument or 0 if lib support */
2773 int named; /* whether or not the argument was named */
2774 {
2775 if (TARGET_DEBUG_E_MODE)
2776 fprintf (stderr,
2777 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
2778 cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode),
2779 type, named);
2780
2781 cum->arg_number++;
2782 switch (mode)
2783 {
2784 case VOIDmode:
2785 break;
2786
2787 default:
2788 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
2789 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
2790 abort ();
2791 cum->gp_reg_found = 1;
2792 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
2793 / UNITS_PER_WORD);
2794 break;
2795
2796 case BLKmode:
2797 cum->gp_reg_found = 1;
2798 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
2799 / UNITS_PER_WORD);
2800 break;
2801
2802 case SFmode:
2803 cum->arg_words++;
2804 break;
2805
2806 case DFmode:
2807 cum->arg_words += (TARGET_64BIT ? 1 : 2);
2808 break;
2809
2810 case DImode:
2811 cum->gp_reg_found = 1;
2812 cum->arg_words += (TARGET_64BIT ? 1 : 2);
2813 break;
2814
2815 case QImode:
2816 case HImode:
2817 case SImode:
2818 cum->gp_reg_found = 1;
2819 cum->arg_words++;
2820 break;
2821 }
2822 }
2823
2824 /* Return an RTL expression containing the register for the given mode,
2825 or 0 if the argument is to be passed on the stack. */
2826
2827 struct rtx_def *
2828 function_arg (cum, mode, type, named)
2829 CUMULATIVE_ARGS *cum; /* current arg information */
2830 enum machine_mode mode; /* current arg mode */
2831 tree type; /* type of the argument or 0 if lib support */
2832 int named; /* != 0 for normal args, == 0 for ... args */
2833 {
2834 rtx ret;
2835 int regbase = -1;
2836 int bias = 0;
2837 int struct_p = ((type != (tree)0)
2838 && (TREE_CODE (type) == RECORD_TYPE
2839 || TREE_CODE (type) == UNION_TYPE));
2840
2841 if (TARGET_DEBUG_E_MODE)
2842 fprintf (stderr,
2843 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
2844 cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode),
2845 type, named);
2846
2847 switch (mode)
2848 {
2849 case SFmode:
2850 if (! ABI_64BIT || mips_isa < 3)
2851 {
2852 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
2853 regbase = GP_ARG_FIRST;
2854 else
2855 {
2856 regbase = FP_ARG_FIRST;
2857 /* If the first arg was a float in a floating point register,
2858 then set bias to align this float arg properly. */
2859 if (cum->arg_words == 1)
2860 bias = 1;
2861 }
2862 }
2863 else
2864 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
2865 break;
2866
2867 case DFmode:
2868 if (! TARGET_64BIT)
2869 cum->arg_words += (cum->arg_words & 1);
2870 if (! ABI_64BIT || mips_isa < 3)
2871 regbase = ((cum->gp_reg_found
2872 || TARGET_SOFT_FLOAT
2873 || TARGET_SINGLE_FLOAT
2874 || cum->arg_number >= 2)
2875 ? GP_ARG_FIRST
2876 : FP_ARG_FIRST);
2877 else
2878 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
2879 ? GP_ARG_FIRST : FP_ARG_FIRST);
2880 break;
2881
2882 default:
2883 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
2884 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
2885 abort ();
2886
2887 /* Drops through. */
2888 case BLKmode:
2889 if (type != (tree)0 && TYPE_ALIGN (type) > BITS_PER_WORD
2890 && ! TARGET_64BIT)
2891 cum->arg_words += (cum->arg_words & 1);
2892
2893 regbase = GP_ARG_FIRST;
2894 break;
2895
2896 case VOIDmode:
2897 case QImode:
2898 case HImode:
2899 case SImode:
2900 regbase = GP_ARG_FIRST;
2901 break;
2902
2903 case DImode:
2904 if (! TARGET_64BIT)
2905 cum->arg_words += (cum->arg_words & 1);
2906 regbase = GP_ARG_FIRST;
2907 }
2908
2909 if (cum->arg_words >= MAX_ARGS_IN_REGISTERS)
2910 {
2911 if (TARGET_DEBUG_E_MODE)
2912 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
2913
2914 ret = (rtx)0;
2915 }
2916 else
2917 {
2918 if (regbase == -1)
2919 abort ();
2920
2921 ret = gen_rtx (REG, mode, regbase + cum->arg_words + bias);
2922
2923 if (TARGET_DEBUG_E_MODE)
2924 fprintf (stderr, "%s%s\n", reg_names[regbase + cum->arg_words + bias],
2925 struct_p ? ", [struct]" : "");
2926
2927 /* The following is a hack in order to pass 1 byte structures
2928 the same way that the MIPS compiler does (namely by passing
2929 the structure in the high byte or half word of the register).
2930 This also makes varargs work. If we have such a structure,
2931 we save the adjustment RTL, and the call define expands will
2932 emit them. For the VOIDmode argument (argument after the
2933 last real argument), pass back a parallel vector holding each
2934 of the adjustments. */
2935
2936 /* ??? function_arg can be called more than once for each argument.
2937 As a result, we compute more adjustments than we need here.
2938 See the CUMULATIVE_ARGS definition in mips.h. */
2939
2940 /* ??? This scheme requires everything smaller than the word size to
2941 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
2942 that would mean every int needs to be shifted left, which is very
2943 inefficient. Let's not carry this compatibility to the 64 bit
2944 calling convention for now. */
2945
2946 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
2947 && ! TARGET_64BIT)
2948 {
2949 rtx amount = GEN_INT (BITS_PER_WORD
2950 - int_size_in_bytes (type) * BITS_PER_UNIT);
2951 rtx reg = gen_rtx (REG, word_mode, regbase + cum->arg_words + bias);
2952 if (TARGET_64BIT)
2953 cum->adjust[ cum->num_adjusts++ ] = gen_ashldi3 (reg, reg, amount);
2954 else
2955 cum->adjust[ cum->num_adjusts++ ] = gen_ashlsi3 (reg, reg, amount);
2956 }
2957 }
2958
2959 if (mode == VOIDmode && cum->num_adjusts > 0)
2960 ret = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (cum->num_adjusts, cum->adjust));
2961
2962 return ret;
2963 }
2964
2965
2966 int
2967 function_arg_partial_nregs (cum, mode, type, named)
2968 CUMULATIVE_ARGS *cum; /* current arg information */
2969 enum machine_mode mode; /* current arg mode */
2970 tree type; /* type of the argument or 0 if lib support */
2971 int named; /* != 0 for normal args, == 0 for ... args */
2972 {
2973 if ((mode == BLKmode
2974 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
2975 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
2976 && cum->arg_words < MAX_ARGS_IN_REGISTERS)
2977 {
2978 int words;
2979 if (mode == BLKmode)
2980 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
2981 / UNITS_PER_WORD);
2982 else
2983 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2984
2985 if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS)
2986 return 0; /* structure fits in registers */
2987
2988 if (TARGET_DEBUG_E_MODE)
2989 fprintf (stderr, "function_arg_partial_nregs = %d\n",
2990 MAX_ARGS_IN_REGISTERS - cum->arg_words);
2991
2992 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
2993 }
2994
2995 else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1
2996 && ! TARGET_64BIT)
2997 {
2998 if (TARGET_DEBUG_E_MODE)
2999 fprintf (stderr, "function_arg_partial_nregs = 1\n");
3000
3001 return 1;
3002 }
3003
3004 return 0;
3005 }
3006
3007 \f
3008 /* Print the options used in the assembly file. */
3009
3010 static struct {char *name; int value;} target_switches []
3011 = TARGET_SWITCHES;
3012
3013 void
3014 print_options (out)
3015 FILE *out;
3016 {
3017 int line_len;
3018 int len;
3019 int j;
3020 char **p;
3021 int mask = TARGET_DEFAULT;
3022
3023 /* Allow assembly language comparisons with -mdebug eliminating the
3024 compiler version number and switch lists. */
3025
3026 if (TARGET_DEBUG_MODE)
3027 return;
3028
3029 fprintf (out, "\n # %s %s", language_string, version_string);
3030 #ifdef TARGET_VERSION_INTERNAL
3031 TARGET_VERSION_INTERNAL (out);
3032 #endif
3033 #ifdef __GNUC__
3034 fprintf (out, " compiled by GNU C\n\n");
3035 #else
3036 fprintf (out, " compiled by CC\n\n");
3037 #endif
3038
3039 fprintf (out, " # Cc1 defaults:");
3040 line_len = 32767;
3041 for (j = 0; j < sizeof target_switches / sizeof target_switches[0]; j++)
3042 {
3043 if (target_switches[j].name[0] != '\0'
3044 && target_switches[j].value > 0
3045 && (target_switches[j].value & mask) == target_switches[j].value)
3046 {
3047 mask &= ~ target_switches[j].value;
3048 len = strlen (target_switches[j].name) + 1;
3049 if (len + line_len > 79)
3050 {
3051 line_len = 2;
3052 fputs ("\n #", out);
3053 }
3054 fprintf (out, " -m%s", target_switches[j].name);
3055 line_len += len;
3056 }
3057 }
3058
3059 fprintf (out, "\n\n # Cc1 arguments (-G value = %d, Cpu = %s, ISA = %d):",
3060 mips_section_threshold, mips_cpu_string, mips_isa);
3061
3062 line_len = 32767;
3063 for (p = &save_argv[1]; *p != (char *)0; p++)
3064 {
3065 char *arg = *p;
3066 if (*arg == '-')
3067 {
3068 len = strlen (arg) + 1;
3069 if (len + line_len > 79)
3070 {
3071 line_len = 2;
3072 fputs ("\n #", out);
3073 }
3074 fprintf (out, " %s", *p);
3075 line_len += len;
3076 }
3077 }
3078
3079 fputs ("\n\n", out);
3080 }
3081
3082 \f
3083 /* Abort after printing out a specific insn. */
3084
3085 void
3086 abort_with_insn (insn, reason)
3087 rtx insn;
3088 char *reason;
3089 {
3090 error (reason);
3091 debug_rtx (insn);
3092 abort ();
3093 }
3094
3095 /* Write a message to stderr (for use in macros expanded in files that do not
3096 include stdio.h). */
3097
3098 void
3099 trace (s, s1, s2)
3100 char *s, *s1, *s2;
3101 {
3102 fprintf (stderr, s, s1, s2);
3103 }
3104
3105 \f
3106 #ifdef SIGINFO
3107
3108 static void
3109 siginfo (signo)
3110 int signo;
3111 {
3112 fprintf (stderr, "compiling '%s' in '%s'\n",
3113 (current_function_name != (char *)0) ? current_function_name : "<toplevel>",
3114 (current_function_file != (char *)0) ? current_function_file : "<no file>");
3115 fflush (stderr);
3116 }
3117 #endif /* SIGINFO */
3118
3119 \f
3120 /* Set up the threshold for data to go into the small data area, instead
3121 of the normal data area, and detect any conflicts in the switches. */
3122
3123 void
3124 override_options ()
3125 {
3126 register int i, start;
3127 register int regno;
3128 register enum machine_mode mode;
3129
3130 mips_section_threshold = (g_switch_set) ? g_switch_value : MIPS_DEFAULT_GVALUE;
3131
3132 if (mips_section_threshold <= 0)
3133 target_flags &= ~MASK_GPOPT;
3134 else if (optimize)
3135 target_flags |= MASK_GPOPT;
3136
3137 /* Get the architectural level. */
3138 if (mips_isa_string == (char *)0)
3139 {
3140 #ifdef MIPS_ISA_DEFAULT
3141 mips_isa = MIPS_ISA_DEFAULT;
3142 #else
3143 mips_isa = 1;
3144 #endif
3145 }
3146
3147 else if (isdigit (*mips_isa_string))
3148 {
3149 mips_isa = atoi (mips_isa_string);
3150 if (mips_isa < 1 || mips_isa > 4)
3151 {
3152 error ("-mips%d not supported", mips_isa);
3153 mips_isa = 1;
3154 }
3155 }
3156
3157 else
3158 {
3159 error ("bad value (%s) for -mips switch", mips_isa_string);
3160 mips_isa = 1;
3161 }
3162
3163 /* Identify the processor type */
3164 if (mips_cpu_string == (char *)0
3165 || !strcmp (mips_cpu_string, "default")
3166 || !strcmp (mips_cpu_string, "DEFAULT"))
3167 {
3168 switch (mips_isa)
3169 {
3170 default:
3171 mips_cpu_string = "3000";
3172 mips_cpu = PROCESSOR_R3000;
3173 break;
3174 case 2:
3175 mips_cpu_string = "6000";
3176 mips_cpu = PROCESSOR_R6000;
3177 break;
3178 case 3:
3179 mips_cpu_string = "4000";
3180 mips_cpu = PROCESSOR_R4000;
3181 break;
3182 case 4:
3183 mips_cpu_string = "8000";
3184 mips_cpu = PROCESSOR_R8000;
3185 break;
3186 }
3187
3188 #ifdef MIPS_CPU_DEFAULT
3189 if (mips_isa_string == (char *)0)
3190 {
3191 mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
3192 mips_cpu = MIPS_CPU_DEFAULT;
3193 }
3194 #endif
3195 }
3196
3197 else
3198 {
3199 char *p = mips_cpu_string;
3200
3201 if (*p == 'r' || *p == 'R')
3202 p++;
3203
3204 /* Since there is no difference between a R2000 and R3000 in
3205 terms of the scheduler, we collapse them into just an R3000. */
3206
3207 mips_cpu = PROCESSOR_DEFAULT;
3208 switch (*p)
3209 {
3210 case '2':
3211 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
3212 mips_cpu = PROCESSOR_R3000;
3213 break;
3214
3215 case '3':
3216 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
3217 mips_cpu = PROCESSOR_R3000;
3218 break;
3219
3220 case '4':
3221 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
3222 mips_cpu = PROCESSOR_R4000;
3223 /* The r4400 is exactly the same as the r4000 from the compiler's
3224 viewpoint. */
3225 else if (!strcmp (p, "4400"))
3226 mips_cpu = PROCESSOR_R4000;
3227 else if (!strcmp (p, "4600"))
3228 mips_cpu = PROCESSOR_R4600;
3229 else if (!strcmp (p, "4650"))
3230 mips_cpu = PROCESSOR_R4650;
3231 break;
3232
3233 case '6':
3234 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
3235 mips_cpu = PROCESSOR_R6000;
3236 break;
3237
3238 case '8':
3239 if (!strcmp (p, "8000"))
3240 mips_cpu = PROCESSOR_R8000;
3241 break;
3242
3243 case 'o':
3244 if (!strcmp (p, "orion"))
3245 mips_cpu = PROCESSOR_R4600;
3246 break;
3247 }
3248
3249 if (mips_cpu == PROCESSOR_DEFAULT)
3250 {
3251 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
3252 mips_cpu_string = "default";
3253 }
3254 }
3255
3256 if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
3257 || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
3258 || ((mips_cpu == PROCESSOR_R4000
3259 || mips_cpu == PROCESSOR_R4600
3260 || mips_cpu == PROCESSOR_R4650)
3261 && mips_isa > 3))
3262 error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
3263
3264 /* make sure sizes of ints/longs/etc. are ok */
3265 if (mips_isa < 3)
3266 {
3267 if (TARGET_INT64)
3268 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3269
3270 else if (TARGET_LONG64)
3271 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3272
3273 else if (TARGET_FLOAT64)
3274 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3275
3276 else if (TARGET_64BIT)
3277 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3278 }
3279
3280 if (ABI_64BIT && mips_isa >= 3)
3281 flag_pcc_struct_return = 0;
3282
3283 /* Tell halfpic.c that we have half-pic code if we do. */
3284 if (TARGET_HALF_PIC)
3285 HALF_PIC_INIT ();
3286
3287 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3288 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3289 /* ??? -non_shared turns off pic code generation, but this is not
3290 implemented. */
3291 if (TARGET_ABICALLS)
3292 {
3293 mips_abicalls = MIPS_ABICALLS_YES;
3294 flag_pic = 1;
3295 if (mips_section_threshold > 0)
3296 warning ("-G is incompatible with PIC code which is the default");
3297 }
3298 else
3299 mips_abicalls = MIPS_ABICALLS_NO;
3300
3301 /* -membedded-pic is a form of PIC code suitable for embedded
3302 systems. All calls are made using PC relative addressing, and
3303 all data is addressed using the $gp register. This requires gas,
3304 which does most of the work, and GNU ld, which automatically
3305 expands PC relative calls which are out of range into a longer
3306 instruction sequence. All gcc really does differently is
3307 generate a different sequence for a switch. */
3308 if (TARGET_EMBEDDED_PIC)
3309 {
3310 flag_pic = 1;
3311 if (TARGET_ABICALLS)
3312 warning ("-membedded-pic and -mabicalls are incompatible");
3313 if (g_switch_set)
3314 warning ("-G and -membedded-pic are incompatible");
3315 /* Setting mips_section_threshold is not required, because gas
3316 will force everything to be GP addressable anyhow, but
3317 setting it will cause gcc to make better estimates of the
3318 number of instructions required to access a particular data
3319 item. */
3320 mips_section_threshold = 0x7fffffff;
3321 }
3322
3323 /* -mrnames says to use the MIPS software convention for register
3324 names instead of the hardware names (ie, $a0 instead of $4).
3325 We do this by switching the names in mips_reg_names, which the
3326 reg_names points into via the REGISTER_NAMES macro. */
3327
3328 if (TARGET_NAME_REGS)
3329 bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names, sizeof (mips_reg_names));
3330
3331 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3332 is currently being compiled. */
3333 #ifdef SIGINFO
3334 if (getenv ("GCC_SIGINFO") != (char *)0)
3335 {
3336 struct sigaction action;
3337 action.sa_handler = siginfo;
3338 action.sa_mask = 0;
3339 action.sa_flags = SA_RESTART;
3340 sigaction (SIGINFO, &action, (struct sigaction *)0);
3341 }
3342 #endif
3343
3344 #if defined(_IOLBF)
3345 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3346 /* If -mstats and -quiet, make stderr line buffered. */
3347 if (quiet_flag && TARGET_STATS)
3348 setvbuf (stderr, (char *)0, _IOLBF, BUFSIZ);
3349 #endif
3350 #endif
3351
3352 /* Initialize the high and low values for legitimate floating point
3353 constants. Rather than trying to get the accuracy down to the
3354 last bit, just use approximate ranges. */
3355 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
3356 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
3357 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
3358 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
3359
3360 mips_print_operand_punct['?'] = TRUE;
3361 mips_print_operand_punct['#'] = TRUE;
3362 mips_print_operand_punct['&'] = TRUE;
3363 mips_print_operand_punct['!'] = TRUE;
3364 mips_print_operand_punct['*'] = TRUE;
3365 mips_print_operand_punct['@'] = TRUE;
3366 mips_print_operand_punct['.'] = TRUE;
3367 mips_print_operand_punct['('] = TRUE;
3368 mips_print_operand_punct[')'] = TRUE;
3369 mips_print_operand_punct['['] = TRUE;
3370 mips_print_operand_punct[']'] = TRUE;
3371 mips_print_operand_punct['<'] = TRUE;
3372 mips_print_operand_punct['>'] = TRUE;
3373 mips_print_operand_punct['{'] = TRUE;
3374 mips_print_operand_punct['}'] = TRUE;
3375 mips_print_operand_punct['^'] = TRUE;
3376
3377 mips_char_to_class['d'] = GR_REGS;
3378 mips_char_to_class['f'] = ((TARGET_HARD_FLOAT) ? FP_REGS : NO_REGS);
3379 mips_char_to_class['h'] = HI_REG;
3380 mips_char_to_class['l'] = LO_REG;
3381 mips_char_to_class['a'] = HILO_REG;
3382 mips_char_to_class['x'] = MD_REGS;
3383 mips_char_to_class['b'] = ALL_REGS;
3384 mips_char_to_class['y'] = GR_REGS;
3385 mips_char_to_class['z'] = ST_REGS;
3386
3387 /* Set up array to map GCC register number to debug register number.
3388 Ignore the special purpose register numbers. */
3389
3390 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3391 mips_dbx_regno[i] = -1;
3392
3393 start = GP_DBX_FIRST - GP_REG_FIRST;
3394 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
3395 mips_dbx_regno[i] = i + start;
3396
3397 start = FP_DBX_FIRST - FP_REG_FIRST;
3398 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
3399 mips_dbx_regno[i] = i + start;
3400
3401 /* Set up array giving whether a given register can hold a given mode.
3402 At present, restrict ints from being in FP registers, because reload
3403 is a little enthusiastic about storing extra values in FP registers,
3404 and this is not good for things like OS kernels. Also, due to the
3405 mandatory delay, it is as fast to load from cached memory as to move
3406 from the FP register. */
3407
3408 for (mode = VOIDmode;
3409 mode != MAX_MACHINE_MODE;
3410 mode = (enum machine_mode)((int)mode + 1))
3411 {
3412 register int size = GET_MODE_SIZE (mode);
3413 register enum mode_class class = GET_MODE_CLASS (mode);
3414
3415 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
3416 {
3417 register int temp;
3418
3419 if (mode == CC_FPmode || mode == CC_REV_FPmode)
3420 temp = (regno == FPSW_REGNUM);
3421
3422 else if (GP_REG_P (regno))
3423 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
3424
3425 else if (FP_REG_P (regno))
3426 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
3427 && (class == MODE_FLOAT
3428 || class == MODE_COMPLEX_FLOAT
3429 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
3430 && (! TARGET_SINGLE_FLOAT || size <= 4));
3431
3432 else if (MD_REG_P (regno))
3433 temp = (size <= UNITS_PER_WORD
3434 || (regno == MD_REG_FIRST && size == 2 * UNITS_PER_WORD));
3435
3436 else
3437 temp = FALSE;
3438
3439 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
3440 }
3441 }
3442 }
3443
3444 \f
3445 /*
3446 * The MIPS debug format wants all automatic variables and arguments
3447 * to be in terms of the virtual frame pointer (stack pointer before
3448 * any adjustment in the function), while the MIPS 3.0 linker wants
3449 * the frame pointer to be the stack pointer after the initial
3450 * adjustment. So, we do the adjustment here. The arg pointer (which
3451 * is eliminated) points to the virtual frame pointer, while the frame
3452 * pointer (which may be eliminated) points to the stack pointer after
3453 * the initial adjustments.
3454 */
3455
3456 int
3457 mips_debugger_offset (addr, offset)
3458 rtx addr;
3459 int offset;
3460 {
3461 rtx offset2 = const0_rtx;
3462 rtx reg = eliminate_constant_term (addr, &offset2);
3463
3464 if (!offset)
3465 offset = INTVAL (offset2);
3466
3467 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx)
3468 {
3469 int frame_size = (!current_frame_info.initialized)
3470 ? compute_frame_size (get_frame_size ())
3471 : current_frame_info.total_size;
3472
3473 offset = offset - frame_size;
3474 }
3475 /* sdbout_parms does not want this to crash for unrecognized cases. */
3476 #if 0
3477 else if (reg != arg_pointer_rtx)
3478 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
3479 #endif
3480
3481 return offset;
3482 }
3483
3484 \f
3485 /* A C compound statement to output to stdio stream STREAM the
3486 assembler syntax for an instruction operand X. X is an RTL
3487 expression.
3488
3489 CODE is a value that can be used to specify one of several ways
3490 of printing the operand. It is used when identical operands
3491 must be printed differently depending on the context. CODE
3492 comes from the `%' specification that was used to request
3493 printing of the operand. If the specification was just `%DIGIT'
3494 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3495 is the ASCII code for LTR.
3496
3497 If X is a register, this macro should print the register's name.
3498 The names can be found in an array `reg_names' whose type is
3499 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3500
3501 When the machine description has a specification `%PUNCT' (a `%'
3502 followed by a punctuation character), this macro is called with
3503 a null pointer for X and the punctuation character for CODE.
3504
3505 The MIPS specific codes are:
3506
3507 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3508 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3509 'd' output integer constant in decimal,
3510 'z' if the operand is 0, use $0 instead of normal operand.
3511 'D' print second register of double-word register operand.
3512 'L' print low-order register of double-word register operand.
3513 'M' print high-order register of double-word register operand.
3514 'C' print part of opcode for a branch condition.
3515 'N' print part of opcode for a branch condition, inverted.
3516 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3517 'B' print 'z' for EQ, 'n' for NE
3518 'b' print 'n' for EQ, 'z' for NE
3519 'T' print 'f' for EQ, 't' for NE
3520 't' print 't' for EQ, 'f' for NE
3521 '(' Turn on .set noreorder
3522 ')' Turn on .set reorder
3523 '[' Turn on .set noat
3524 ']' Turn on .set at
3525 '<' Turn on .set nomacro
3526 '>' Turn on .set macro
3527 '{' Turn on .set volatile (not GAS)
3528 '}' Turn on .set novolatile (not GAS)
3529 '&' Turn on .set noreorder if filling delay slots
3530 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3531 '!' Turn on .set nomacro if filling delay slots
3532 '#' Print nop if in a .set noreorder section.
3533 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3534 '@' Print the name of the assembler temporary register (at or $1).
3535 '.' Print the name of the register with a hard-wired zero (zero or $0).
3536 '^' Print the name of the pic call-through register (t9 or $25). */
3537
3538 void
3539 print_operand (file, op, letter)
3540 FILE *file; /* file to write to */
3541 rtx op; /* operand to print */
3542 int letter; /* %<letter> or 0 */
3543 {
3544 register enum rtx_code code;
3545
3546 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
3547 {
3548 switch (letter)
3549 {
3550 default:
3551 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
3552 break;
3553
3554 case '?':
3555 if (mips_branch_likely)
3556 putc ('l', file);
3557 break;
3558
3559 case '@':
3560 fputs (reg_names [GP_REG_FIRST + 1], file);
3561 break;
3562
3563 case '^':
3564 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
3565 break;
3566
3567 case '.':
3568 fputs (reg_names [GP_REG_FIRST + 0], file);
3569 break;
3570
3571 case '&':
3572 if (final_sequence != 0 && set_noreorder++ == 0)
3573 fputs (".set\tnoreorder\n\t", file);
3574 break;
3575
3576 case '*':
3577 if (final_sequence != 0)
3578 {
3579 if (set_noreorder++ == 0)
3580 fputs (".set\tnoreorder\n\t", file);
3581
3582 if (set_nomacro++ == 0)
3583 fputs (".set\tnomacro\n\t", file);
3584 }
3585 break;
3586
3587 case '!':
3588 if (final_sequence != 0 && set_nomacro++ == 0)
3589 fputs ("\n\t.set\tnomacro", file);
3590 break;
3591
3592 case '#':
3593 if (set_noreorder != 0)
3594 fputs ("\n\tnop", file);
3595
3596 else if (TARGET_STATS)
3597 fputs ("\n\t#nop", file);
3598
3599 break;
3600
3601 case '(':
3602 if (set_noreorder++ == 0)
3603 fputs (".set\tnoreorder\n\t", file);
3604 break;
3605
3606 case ')':
3607 if (set_noreorder == 0)
3608 error ("internal error: %%) found without a %%( in assembler pattern");
3609
3610 else if (--set_noreorder == 0)
3611 fputs ("\n\t.set\treorder", file);
3612
3613 break;
3614
3615 case '[':
3616 if (set_noat++ == 0)
3617 fputs (".set\tnoat\n\t", file);
3618 break;
3619
3620 case ']':
3621 if (set_noat == 0)
3622 error ("internal error: %%] found without a %%[ in assembler pattern");
3623
3624 else if (--set_noat == 0)
3625 fputs ("\n\t.set\tat", file);
3626
3627 break;
3628
3629 case '<':
3630 if (set_nomacro++ == 0)
3631 fputs (".set\tnomacro\n\t", file);
3632 break;
3633
3634 case '>':
3635 if (set_nomacro == 0)
3636 error ("internal error: %%> found without a %%< in assembler pattern");
3637
3638 else if (--set_nomacro == 0)
3639 fputs ("\n\t.set\tmacro", file);
3640
3641 break;
3642
3643 case '{':
3644 if (set_volatile++ == 0)
3645 fprintf (file, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS) ? "" : "#");
3646 break;
3647
3648 case '}':
3649 if (set_volatile == 0)
3650 error ("internal error: %%} found without a %%{ in assembler pattern");
3651
3652 else if (--set_volatile == 0)
3653 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
3654
3655 break;
3656 }
3657 return;
3658 }
3659
3660 if (! op)
3661 {
3662 error ("PRINT_OPERAND null pointer");
3663 return;
3664 }
3665
3666 code = GET_CODE (op);
3667 if (letter == 'C')
3668 switch (code)
3669 {
3670 case EQ: fputs ("eq", file); break;
3671 case NE: fputs ("ne", file); break;
3672 case GT: fputs ("gt", file); break;
3673 case GE: fputs ("ge", file); break;
3674 case LT: fputs ("lt", file); break;
3675 case LE: fputs ("le", file); break;
3676 case GTU: fputs ("gtu", file); break;
3677 case GEU: fputs ("geu", file); break;
3678 case LTU: fputs ("ltu", file); break;
3679 case LEU: fputs ("leu", file); break;
3680
3681 default:
3682 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
3683 }
3684
3685 else if (letter == 'N')
3686 switch (code)
3687 {
3688 case EQ: fputs ("ne", file); break;
3689 case NE: fputs ("eq", file); break;
3690 case GT: fputs ("le", file); break;
3691 case GE: fputs ("lt", file); break;
3692 case LT: fputs ("ge", file); break;
3693 case LE: fputs ("gt", file); break;
3694 case GTU: fputs ("leu", file); break;
3695 case GEU: fputs ("ltu", file); break;
3696 case LTU: fputs ("geu", file); break;
3697 case LEU: fputs ("gtu", file); break;
3698
3699 default:
3700 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
3701 }
3702
3703 else if (letter == 'S')
3704 {
3705 char buffer[100];
3706
3707 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
3708 assemble_name (file, buffer);
3709 }
3710
3711 else if (code == REG)
3712 {
3713 register int regnum = REGNO (op);
3714
3715 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
3716 || (letter == 'L' && WORDS_BIG_ENDIAN)
3717 || letter == 'D')
3718 regnum++;
3719
3720 fprintf (file, "%s", reg_names[regnum]);
3721 }
3722
3723 else if (code == MEM)
3724 output_address (XEXP (op, 0));
3725
3726 else if (code == CONST_DOUBLE
3727 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
3728 {
3729 REAL_VALUE_TYPE d;
3730 char s[30];
3731
3732 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
3733 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
3734 fprintf (file, s);
3735 }
3736
3737 else if ((letter == 'x') && (GET_CODE(op) == CONST_INT))
3738 fprintf (file, "0x%04x", 0xffff & (INTVAL(op)));
3739
3740 else if ((letter == 'X') && (GET_CODE(op) == CONST_INT)
3741 && HOST_BITS_PER_WIDE_INT == 32)
3742 fprintf (file, "0x%08x", INTVAL(op));
3743
3744 else if ((letter == 'X') && (GET_CODE(op) == CONST_INT)
3745 && HOST_BITS_PER_WIDE_INT == 64)
3746 fprintf (file, "0x%016lx", INTVAL(op));
3747
3748 else if ((letter == 'd') && (GET_CODE(op) == CONST_INT))
3749 fprintf (file, "%d", (INTVAL(op)));
3750
3751 else if (letter == 'z'
3752 && (GET_CODE (op) == CONST_INT)
3753 && INTVAL (op) == 0)
3754 fputs (reg_names[GP_REG_FIRST], file);
3755
3756 else if (letter == 'd' || letter == 'x' || letter == 'X')
3757 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter);
3758
3759 else if (letter == 'B')
3760 fputs (code == EQ ? "z" : "n", file);
3761 else if (letter == 'b')
3762 fputs (code == EQ ? "n" : "z", file);
3763 else if (letter == 'T')
3764 fputs (code == EQ ? "f" : "t", file);
3765 else if (letter == 't')
3766 fputs (code == EQ ? "t" : "f", file);
3767
3768 else
3769 output_addr_const (file, op);
3770 }
3771
3772 \f
3773 /* A C compound statement to output to stdio stream STREAM the
3774 assembler syntax for an instruction operand that is a memory
3775 reference whose address is ADDR. ADDR is an RTL expression.
3776
3777 On some machines, the syntax for a symbolic address depends on
3778 the section that the address refers to. On these machines,
3779 define the macro `ENCODE_SECTION_INFO' to store the information
3780 into the `symbol_ref', and then check for it here. */
3781
3782 void
3783 print_operand_address (file, addr)
3784 FILE *file;
3785 rtx addr;
3786 {
3787 if (!addr)
3788 error ("PRINT_OPERAND_ADDRESS, null pointer");
3789
3790 else
3791 switch (GET_CODE (addr))
3792 {
3793 default:
3794 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
3795 break;
3796
3797 case REG:
3798 if (REGNO (addr) == ARG_POINTER_REGNUM)
3799 abort_with_insn (addr, "Arg pointer not eliminated.");
3800
3801 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
3802 break;
3803
3804 case PLUS:
3805 {
3806 register rtx reg = (rtx)0;
3807 register rtx offset = (rtx)0;
3808 register rtx arg0 = XEXP (addr, 0);
3809 register rtx arg1 = XEXP (addr, 1);
3810
3811 if (GET_CODE (arg0) == REG)
3812 {
3813 reg = arg0;
3814 offset = arg1;
3815 if (GET_CODE (offset) == REG)
3816 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
3817 }
3818 else if (GET_CODE (arg1) == REG)
3819 {
3820 reg = arg1;
3821 offset = arg0;
3822 }
3823 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
3824 {
3825 output_addr_const (file, addr);
3826 break;
3827 }
3828 else
3829 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
3830
3831 if (!CONSTANT_P (offset))
3832 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
3833
3834 if (REGNO (reg) == ARG_POINTER_REGNUM)
3835 abort_with_insn (addr, "Arg pointer not eliminated.");
3836
3837 output_addr_const (file, offset);
3838 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
3839 }
3840 break;
3841
3842 case LABEL_REF:
3843 case SYMBOL_REF:
3844 case CONST_INT:
3845 case CONST:
3846 output_addr_const (file, addr);
3847 break;
3848 }
3849 }
3850
3851 \f
3852 /* If optimizing for the global pointer, keep track of all of
3853 the externs, so that at the end of the file, we can emit
3854 the appropriate .extern declaration for them, before writing
3855 out the text section. We assume that all names passed to
3856 us are in the permanent obstack, so that they will be valid
3857 at the end of the compilation.
3858
3859 If we have -G 0, or the extern size is unknown, don't bother
3860 emitting the .externs. */
3861
3862 int
3863 mips_output_external (file, decl, name)
3864 FILE *file;
3865 tree decl;
3866 char *name;
3867 {
3868 register struct extern_list *p;
3869 int len;
3870
3871 if (TARGET_GP_OPT
3872 && ((TREE_CODE (decl)) != FUNCTION_DECL)
3873 && ((len = int_size_in_bytes (TREE_TYPE (decl))) > 0))
3874 {
3875 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
3876 p->next = extern_head;
3877 p->name = name;
3878 p->size = len;
3879 extern_head = p;
3880 }
3881
3882 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
3883 if (TREE_CODE (decl) == FUNCTION_DECL
3884 /* ??? Don't include alloca, since gcc will always expand it
3885 inline. If we don't do this, libg++ fails to build. */
3886 && strcmp (name, "alloca")
3887 /* ??? Don't include __builtin_next_arg, because then gcc will not
3888 bootstrap under Irix 5.1. */
3889 && strcmp (name, "__builtin_next_arg"))
3890 {
3891 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
3892 p->next = extern_head;
3893 p->name = name;
3894 p->size = -1;
3895 extern_head = p;
3896 }
3897 #endif
3898
3899 return 0;
3900 }
3901
3902 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
3903 int
3904 mips_output_external_libcall (file, name)
3905 FILE *file;
3906 char *name;
3907 {
3908 register struct extern_list *p;
3909
3910 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
3911 p->next = extern_head;
3912 p->name = name;
3913 p->size = -1;
3914 extern_head = p;
3915
3916 return 0;
3917 }
3918 #endif
3919
3920 \f
3921 /* Compute a string to use as a temporary file name. */
3922
3923 /* On MSDOS, write temp files in current dir
3924 because there's no place else we can expect to use. */
3925 #if __MSDOS__
3926 #ifndef P_tmpdir
3927 #define P_tmpdir "./"
3928 #endif
3929 #endif
3930
3931 static FILE *
3932 make_temp_file ()
3933 {
3934 FILE *stream;
3935 char *base = getenv ("TMPDIR");
3936 int len;
3937
3938 if (base == (char *)0)
3939 {
3940 #ifdef P_tmpdir
3941 if (access (P_tmpdir, R_OK | W_OK) == 0)
3942 base = P_tmpdir;
3943 else
3944 #endif
3945 if (access ("/usr/tmp", R_OK | W_OK) == 0)
3946 base = "/usr/tmp/";
3947 else
3948 base = "/tmp/";
3949 }
3950
3951 len = strlen (base);
3952 /* temp_filename is global, so we must use malloc, not alloca. */
3953 temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX"));
3954 strcpy (temp_filename, base);
3955 if (len > 0 && temp_filename[len-1] != '/')
3956 temp_filename[len++] = '/';
3957
3958 strcpy (temp_filename + len, "ctXXXXXX");
3959 mktemp (temp_filename);
3960
3961 stream = fopen (temp_filename, "w+");
3962 if (!stream)
3963 pfatal_with_name (temp_filename);
3964
3965 #ifndef __MSDOS__
3966 /* In MSDOS, we cannot unlink the temporary file until we are finished using
3967 it. Otherwise, we delete it now, so that it will be gone even if the
3968 compiler happens to crash. */
3969 unlink (temp_filename);
3970 #endif
3971 return stream;
3972 }
3973
3974 \f
3975 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
3976 for .file's that start within a function. If we are smuggling stabs, try to
3977 put out a MIPS ECOFF file and a stab. */
3978
3979 void
3980 mips_output_filename (stream, name)
3981 FILE *stream;
3982 char *name;
3983 {
3984 static int first_time = TRUE;
3985 char ltext_label_name[100];
3986
3987 if (first_time)
3988 {
3989 first_time = FALSE;
3990 SET_FILE_NUMBER ();
3991 current_function_file = name;
3992 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
3993 /* This tells mips-tfile that stabs will follow. */
3994 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
3995 fprintf (stream, "\t#@stabs\n");
3996 }
3997
3998 else if (write_symbols == DBX_DEBUG)
3999 {
4000 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
4001 fprintf (stream, "%s ", ASM_STABS_OP);
4002 output_quoted_string (stream, name);
4003 fprintf (stream, ",%d,0,0,%s\n", N_SOL, &ltext_label_name[1]);
4004 }
4005
4006 else if (name != current_function_file
4007 && strcmp (name, current_function_file) != 0)
4008 {
4009 if (inside_function && !TARGET_GAS)
4010 {
4011 if (!file_in_function_warning)
4012 {
4013 file_in_function_warning = TRUE;
4014 ignore_line_number = TRUE;
4015 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
4016 }
4017 }
4018 else
4019 {
4020 SET_FILE_NUMBER ();
4021 current_function_file = name;
4022 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
4023 }
4024 }
4025 }
4026
4027 \f
4028 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4029 as well as a .loc, since it is possible that MIPS ECOFF might not be
4030 able to represent the location for inlines that come from a different
4031 file. */
4032
4033 void
4034 mips_output_lineno (stream, line)
4035 FILE *stream;
4036 int line;
4037 {
4038 if (write_symbols == DBX_DEBUG)
4039 {
4040 ++sym_lineno;
4041 fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
4042 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
4043 LOCAL_LABEL_PREFIX, sym_lineno);
4044 }
4045
4046 else
4047 {
4048 fprintf (stream, "\n\t%s.loc\t%d %d\n",
4049 (ignore_line_number) ? "#" : "",
4050 num_source_filenames, line);
4051
4052 LABEL_AFTER_LOC (stream);
4053 }
4054 }
4055
4056 \f
4057 /* If defined, a C statement to be executed just prior to the
4058 output of assembler code for INSN, to modify the extracted
4059 operands so they will be output differently.
4060
4061 Here the argument OPVEC is the vector containing the operands
4062 extracted from INSN, and NOPERANDS is the number of elements of
4063 the vector which contain meaningful data for this insn. The
4064 contents of this vector are what will be used to convert the
4065 insn template into assembler code, so you can change the
4066 assembler output by changing the contents of the vector.
4067
4068 We use it to check if the current insn needs a nop in front of it
4069 because of load delays, and also to update the delay slot
4070 statistics. */
4071
4072 /* ??? There is no real need for this function, because it never actually
4073 emits a NOP anymore. */
4074
4075 void
4076 final_prescan_insn (insn, opvec, noperands)
4077 rtx insn;
4078 rtx opvec[];
4079 int noperands;
4080 {
4081 if (dslots_number_nops > 0)
4082 {
4083 rtx pattern = PATTERN (insn);
4084 int length = get_attr_length (insn);
4085
4086 /* Do we need to emit a NOP? */
4087 if (length == 0
4088 || (mips_load_reg != (rtx)0 && reg_mentioned_p (mips_load_reg, pattern))
4089 || (mips_load_reg2 != (rtx)0 && reg_mentioned_p (mips_load_reg2, pattern))
4090 || (mips_load_reg3 != (rtx)0 && reg_mentioned_p (mips_load_reg3, pattern))
4091 || (mips_load_reg4 != (rtx)0 && reg_mentioned_p (mips_load_reg4, pattern)))
4092 fputs ("\t#nop\n", asm_out_file);
4093
4094 else
4095 dslots_load_filled++;
4096
4097 while (--dslots_number_nops > 0)
4098 fputs ("\t#nop\n", asm_out_file);
4099
4100 mips_load_reg = (rtx)0;
4101 mips_load_reg2 = (rtx)0;
4102 mips_load_reg3 = (rtx)0;
4103 mips_load_reg4 = (rtx)0;
4104 }
4105
4106 if (TARGET_STATS)
4107 {
4108 enum rtx_code code = GET_CODE (insn);
4109 if (code == JUMP_INSN || code == CALL_INSN)
4110 dslots_jump_total++;
4111 }
4112 }
4113
4114 \f
4115 /* Output at beginning of assembler file.
4116 If we are optimizing to use the global pointer, create a temporary
4117 file to hold all of the text stuff, and write it out to the end.
4118 This is needed because the MIPS assembler is evidently one pass,
4119 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4120 declaration when the code is processed, it generates a two
4121 instruction sequence. */
4122
4123 void
4124 mips_asm_file_start (stream)
4125 FILE *stream;
4126 {
4127 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
4128
4129 /* Versions of the MIPS assembler before 2.20 generate errors
4130 if a branch inside of a .set noreorder section jumps to a
4131 label outside of the .set noreorder section. Revision 2.20
4132 just set nobopt silently rather than fixing the bug. */
4133
4134 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
4135 fprintf (stream, "\t.set\tnobopt\n");
4136
4137 /* Generate the pseudo ops that System V.4 wants. */
4138 #ifndef ABICALLS_ASM_OP
4139 #define ABICALLS_ASM_OP ".abicalls"
4140 #endif
4141 if (TARGET_ABICALLS)
4142 /* ??? but do not want this (or want pic0) if -non-shared? */
4143 fprintf (stream, "\t%s\n", ABICALLS_ASM_OP);
4144
4145 /* Start a section, so that the first .popsection directive is guaranteed
4146 to have a previously defined section to pop back to. */
4147 if (ABI_64BIT && mips_isa >= 3)
4148 fprintf (stream, "\t.section\t.text\n");
4149
4150 /* This code exists so that we can put all externs before all symbol
4151 references. This is necessary for the assembler's global pointer
4152 optimizations to work. */
4153 /* ??? Current versions of gas do not require that externs occur before
4154 symbol references. This means that this code is unnecessary when
4155 gas is being used. This gas feature hasn't been well tested as yet
4156 though. */
4157 if (TARGET_GP_OPT)
4158 {
4159 asm_out_data_file = stream;
4160 asm_out_text_file = make_temp_file ();
4161 }
4162 else
4163 asm_out_data_file = asm_out_text_file = stream;
4164
4165 print_options (stream);
4166 }
4167
4168 \f
4169 /* If we are optimizing the global pointer, emit the text section now
4170 and any small externs which did not have .comm, etc that are
4171 needed. Also, give a warning if the data area is more than 32K and
4172 -pic because 3 instructions are needed to reference the data
4173 pointers. */
4174
4175 void
4176 mips_asm_file_end (file)
4177 FILE *file;
4178 {
4179 char buffer[8192];
4180 tree name_tree;
4181 struct extern_list *p;
4182 int len;
4183
4184 if (HALF_PIC_P ())
4185 HALF_PIC_FINISH (file);
4186
4187 if (extern_head)
4188 {
4189 fputs ("\n", file);
4190
4191 for (p = extern_head; p != 0; p = p->next)
4192 {
4193 name_tree = get_identifier (p->name);
4194
4195 /* Positively ensure only one .extern for any given symbol. */
4196 if (! TREE_ASM_WRITTEN (name_tree))
4197 {
4198 TREE_ASM_WRITTEN (name_tree) = 1;
4199 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4200 if (p->size == -1)
4201 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
4202 else
4203 #endif
4204 {
4205 fputs ("\t.extern\t", file);
4206 assemble_name (file, p->name);
4207 fprintf (file, ", %d\n", p->size);
4208 }
4209 }
4210 }
4211 }
4212
4213 if (TARGET_GP_OPT)
4214 {
4215 fprintf (file, "\n\t.text\n");
4216 rewind (asm_out_text_file);
4217 if (ferror (asm_out_text_file))
4218 fatal_io_error (temp_filename);
4219
4220 while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
4221 if (fwrite (buffer, 1, len, file) != len)
4222 pfatal_with_name (asm_file_name);
4223
4224 if (len < 0)
4225 pfatal_with_name (temp_filename);
4226
4227 if (fclose (asm_out_text_file) != 0)
4228 pfatal_with_name (temp_filename);
4229
4230 #ifdef __MSDOS__
4231 unlink (temp_filename);
4232 #endif
4233 }
4234 }
4235
4236 \f
4237 /* Emit either a label, .comm, or .lcomm directive, and mark
4238 that the symbol is used, so that we don't emit an .extern
4239 for it in mips_asm_file_end. */
4240
4241 void
4242 mips_declare_object (stream, name, init_string, final_string, size)
4243 FILE *stream;
4244 char *name;
4245 char *init_string;
4246 char *final_string;
4247 int size;
4248 {
4249 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
4250 assemble_name (stream, name);
4251 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
4252
4253 if (TARGET_GP_OPT)
4254 {
4255 tree name_tree = get_identifier (name);
4256 TREE_ASM_WRITTEN (name_tree) = 1;
4257 }
4258 }
4259
4260 \f
4261 /* Output a double precision value to the assembler. If both the
4262 host and target are IEEE, emit the values in hex. */
4263
4264 void
4265 mips_output_double (stream, value)
4266 FILE *stream;
4267 REAL_VALUE_TYPE value;
4268 {
4269 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4270 long value_long[2];
4271 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
4272
4273 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4274 value_long[0], value, value_long[1]);
4275 #else
4276 fprintf (stream, "\t.double\t%.20g\n", value);
4277 #endif
4278 }
4279
4280
4281 /* Output a single precision value to the assembler. If both the
4282 host and target are IEEE, emit the values in hex. */
4283
4284 void
4285 mips_output_float (stream, value)
4286 FILE *stream;
4287 REAL_VALUE_TYPE value;
4288 {
4289 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4290 long value_long;
4291 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
4292
4293 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
4294 #else
4295 fprintf (stream, "\t.float\t%.12g\n", value);
4296 #endif
4297 }
4298
4299 \f
4300 /* Return TRUE if any register used in the epilogue is used. This to insure
4301 any insn put into the epilogue delay slots is safe. */
4302
4303 int
4304 epilogue_reg_mentioned_p (insn)
4305 rtx insn;
4306 {
4307 register char *fmt;
4308 register int i;
4309 register enum rtx_code code;
4310 register int regno;
4311
4312 if (insn == (rtx)0)
4313 return 0;
4314
4315 if (GET_CODE (insn) == LABEL_REF)
4316 return 0;
4317
4318 code = GET_CODE (insn);
4319 switch (code)
4320 {
4321 case REG:
4322 regno = REGNO (insn);
4323 if (regno == STACK_POINTER_REGNUM)
4324 return 1;
4325
4326 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
4327 return 1;
4328
4329 if (!call_used_regs[regno])
4330 return 1;
4331
4332 if (regno != MIPS_TEMP1_REGNUM && regno != MIPS_TEMP2_REGNUM)
4333 return 0;
4334
4335 if (!current_frame_info.initialized)
4336 compute_frame_size (get_frame_size ());
4337
4338 return (current_frame_info.total_size >= 32768);
4339
4340 case SCRATCH:
4341 case CC0:
4342 case PC:
4343 case CONST_INT:
4344 case CONST_DOUBLE:
4345 return 0;
4346 }
4347
4348 fmt = GET_RTX_FORMAT (code);
4349 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4350 {
4351 if (fmt[i] == 'E')
4352 {
4353 register int j;
4354 for (j = XVECLEN (insn, i) - 1; j >= 0; j--)
4355 if (epilogue_reg_mentioned_p (XVECEXP (insn, i, j)))
4356 return 1;
4357 }
4358 else if (fmt[i] == 'e' && epilogue_reg_mentioned_p (XEXP (insn, i)))
4359 return 1;
4360 }
4361
4362 return 0;
4363 }
4364
4365 \f
4366 /* When generating embedded PIC code we may need to get the address of
4367 the current function. We will need it if we take the address of
4368 any symbol in the .text section. */
4369
4370 void
4371 mips_finalize_pic ()
4372 {
4373 rtx seq;
4374
4375 if (! TARGET_EMBEDDED_PIC)
4376 return;
4377 if (embedded_pic_fnaddr_rtx == NULL)
4378 return;
4379
4380 start_sequence ();
4381
4382 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
4383 XEXP (DECL_RTL (current_function_decl), 0)));
4384
4385 seq = gen_sequence ();
4386 end_sequence ();
4387 emit_insn_after (seq, get_insns ());
4388
4389 embedded_pic_fnaddr_rtx = NULL;
4390 }
4391
4392 \f
4393 /* Return the bytes needed to compute the frame pointer from the current
4394 stack pointer.
4395
4396 Mips stack frames look like:
4397
4398 Before call After call
4399 +-----------------------+ +-----------------------+
4400 high | | | |
4401 mem. | | | |
4402 | caller's temps. | | caller's temps. |
4403 | | | |
4404 +-----------------------+ +-----------------------+
4405 | | | |
4406 | arguments on stack. | | arguments on stack. |
4407 | | | |
4408 +-----------------------+ +-----------------------+
4409 | 4 words to save | | 4 words to save |
4410 | arguments passed | | arguments passed |
4411 | in registers, even | | in registers, even |
4412 SP->| if not passed. | VFP->| if not passed. |
4413 +-----------------------+ +-----------------------+
4414 | |
4415 | fp register save |
4416 | |
4417 +-----------------------+
4418 | |
4419 | gp register save |
4420 | |
4421 +-----------------------+
4422 | |
4423 | local variables |
4424 | |
4425 +-----------------------+
4426 | |
4427 | alloca allocations |
4428 | |
4429 +-----------------------+
4430 | |
4431 | GP save for V.4 abi |
4432 | |
4433 +-----------------------+
4434 | |
4435 | arguments on stack |
4436 | |
4437 +-----------------------+
4438 | 4 words to save |
4439 | arguments passed |
4440 | in registers, even |
4441 low SP->| if not passed. |
4442 memory +-----------------------+
4443
4444 */
4445
4446 long
4447 compute_frame_size (size)
4448 int size; /* # of var. bytes allocated */
4449 {
4450 int regno;
4451 long total_size; /* # bytes that the entire frame takes up */
4452 long var_size; /* # bytes that variables take up */
4453 long args_size; /* # bytes that outgoing arguments take up */
4454 long extra_size; /* # extra bytes */
4455 long gp_reg_rounded; /* # bytes needed to store gp after rounding */
4456 long gp_reg_size; /* # bytes needed to store gp regs */
4457 long fp_reg_size; /* # bytes needed to store fp regs */
4458 long mask; /* mask of saved gp registers */
4459 long fmask; /* mask of saved fp registers */
4460 int fp_inc; /* 1 or 2 depending on the size of fp regs */
4461 long fp_bits; /* bitmask to use for each fp register */
4462
4463 gp_reg_size = 0;
4464 fp_reg_size = 0;
4465 mask = 0;
4466 fmask = 0;
4467 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
4468 var_size = MIPS_STACK_ALIGN (size);
4469 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
4470
4471 /* The MIPS 3.0 linker does not like functions that dynamically
4472 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4473 looks like we are trying to create a second frame pointer to the
4474 function, so allocate some stack space to make it happy. */
4475
4476 if (args_size == 0 && current_function_calls_alloca)
4477 args_size = 4*UNITS_PER_WORD;
4478
4479 total_size = var_size + args_size + extra_size;
4480
4481 /* Calculate space needed for gp registers. */
4482 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
4483 {
4484 if (MUST_SAVE_REGISTER (regno))
4485 {
4486 gp_reg_size += UNITS_PER_WORD;
4487 mask |= 1L << (regno - GP_REG_FIRST);
4488 }
4489 }
4490
4491 /* Calculate space needed for fp registers. */
4492 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
4493 {
4494 fp_inc = 1;
4495 fp_bits = 1;
4496 }
4497 else
4498 {
4499 fp_inc = 2;
4500 fp_bits = 3;
4501 }
4502
4503 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += fp_inc)
4504 {
4505 if (regs_ever_live[regno] && !call_used_regs[regno])
4506 {
4507 fp_reg_size += fp_inc * UNITS_PER_FPREG;
4508 fmask |= fp_bits << (regno - FP_REG_FIRST);
4509 }
4510 }
4511
4512 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
4513 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
4514
4515 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4516 for leaf routines (total_size == extra_size) to save the gp reg.
4517 The gp reg is callee saved in the 64 bit ABI, so all routines must
4518 save the gp reg. */
4519 if (total_size == extra_size && ! (ABI_64BIT && mips_isa >= 3))
4520 total_size = extra_size = 0;
4521 else if (TARGET_ABICALLS)
4522 {
4523 /* Add the context-pointer to the saved registers. */
4524 gp_reg_size += UNITS_PER_WORD;
4525 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
4526 total_size -= gp_reg_rounded;
4527 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
4528 total_size += gp_reg_rounded;
4529 }
4530
4531 /* Add in space reserved on the stack by the callee for storing arguments
4532 passed in registers. */
4533 if (ABI_64BIT && mips_isa >= 3)
4534 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
4535
4536 /* Save other computed information. */
4537 current_frame_info.total_size = total_size;
4538 current_frame_info.var_size = var_size;
4539 current_frame_info.args_size = args_size;
4540 current_frame_info.extra_size = extra_size;
4541 current_frame_info.gp_reg_size = gp_reg_size;
4542 current_frame_info.fp_reg_size = fp_reg_size;
4543 current_frame_info.mask = mask;
4544 current_frame_info.fmask = fmask;
4545 current_frame_info.initialized = reload_completed;
4546 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
4547 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
4548
4549 if (mask)
4550 {
4551 unsigned long offset = (args_size + extra_size + var_size
4552 + gp_reg_size - UNITS_PER_WORD);
4553 current_frame_info.gp_sp_offset = offset;
4554 current_frame_info.gp_save_offset = offset - total_size;
4555 }
4556 else
4557 {
4558 current_frame_info.gp_sp_offset = 0;
4559 current_frame_info.gp_save_offset = 0;
4560 }
4561
4562
4563 if (fmask)
4564 {
4565 unsigned long offset = (args_size + extra_size + var_size
4566 + gp_reg_rounded + fp_reg_size
4567 - fp_inc * UNITS_PER_FPREG);
4568 current_frame_info.fp_sp_offset = offset;
4569 current_frame_info.fp_save_offset = offset - total_size + UNITS_PER_WORD;
4570 }
4571 else
4572 {
4573 current_frame_info.fp_sp_offset = 0;
4574 current_frame_info.fp_save_offset = 0;
4575 }
4576
4577 /* Ok, we're done. */
4578 return total_size;
4579 }
4580
4581 \f
4582 /* Common code to emit the insns (or to write the instructions to a file)
4583 to save/restore registers.
4584
4585 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4586 is not modified within save_restore_insns. */
4587
4588 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4589
4590 static void
4591 save_restore_insns (store_p, large_reg, large_offset, file)
4592 int store_p; /* true if this is prologue */
4593 rtx large_reg; /* register holding large offset constant or NULL */
4594 long large_offset; /* large constant offset value */
4595 FILE *file; /* file to write instructions to instead of making RTL */
4596 {
4597 long mask = current_frame_info.mask;
4598 long fmask = current_frame_info.fmask;
4599 int regno;
4600 rtx base_reg_rtx;
4601 long base_offset;
4602 long gp_offset;
4603 long fp_offset;
4604 long end_offset;
4605
4606 if (frame_pointer_needed && !BITSET_P (mask, FRAME_POINTER_REGNUM - GP_REG_FIRST))
4607 abort ();
4608
4609 if (mask == 0 && fmask == 0)
4610 return;
4611
4612 /* Save registers starting from high to low. The debuggers prefer
4613 at least the return register be stored at func+4, and also it
4614 allows us not to need a nop in the epilog if at least one
4615 register is reloaded in addition to return address. */
4616
4617 /* Save GP registers if needed. */
4618 if (mask)
4619 {
4620 /* Pick which pointer to use as a base register. For small
4621 frames, just use the stack pointer. Otherwise, use a
4622 temporary register. Save 2 cycles if the save area is near
4623 the end of a large frame, by reusing the constant created in
4624 the prologue/epilogue to adjust the stack frame. */
4625
4626 gp_offset = current_frame_info.gp_sp_offset;
4627 end_offset = gp_offset - (current_frame_info.gp_reg_size - UNITS_PER_WORD);
4628
4629 if (gp_offset < 0 || end_offset < 0)
4630 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
4631 gp_offset, end_offset);
4632
4633 else if (gp_offset < 32768)
4634 {
4635 base_reg_rtx = stack_pointer_rtx;
4636 base_offset = 0;
4637 }
4638
4639 else if (large_reg != (rtx)0
4640 && (((unsigned long)(large_offset - gp_offset)) < 32768)
4641 && (((unsigned long)(large_offset - end_offset)) < 32768))
4642 {
4643 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
4644 base_offset = large_offset;
4645 if (file == (FILE *)0)
4646 {
4647 if (TARGET_LONG64)
4648 emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
4649 else
4650 emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
4651 }
4652 else
4653 fprintf (file, "\t%s\t%s,%s,%s\n",
4654 TARGET_LONG64 ? "daddu" : "addu",
4655 reg_names[MIPS_TEMP2_REGNUM],
4656 reg_names[REGNO (large_reg)],
4657 reg_names[STACK_POINTER_REGNUM]);
4658 }
4659
4660 else
4661 {
4662 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
4663 base_offset = gp_offset;
4664 if (file == (FILE *)0)
4665 {
4666 emit_move_insn (base_reg_rtx, GEN_INT (gp_offset));
4667 if (TARGET_LONG64)
4668 emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
4669 else
4670 emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
4671 }
4672 else
4673 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
4674 reg_names[MIPS_TEMP2_REGNUM],
4675 (long)base_offset,
4676 (long)base_offset,
4677 TARGET_LONG64 ? "daddu" : "addu",
4678 reg_names[MIPS_TEMP2_REGNUM],
4679 reg_names[MIPS_TEMP2_REGNUM],
4680 reg_names[STACK_POINTER_REGNUM]);
4681 }
4682
4683 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
4684 {
4685 if (BITSET_P (mask, regno - GP_REG_FIRST))
4686 {
4687 if (file == (FILE *)0)
4688 {
4689 rtx reg_rtx = gen_rtx (REG, word_mode, regno);
4690 rtx mem_rtx = gen_rtx (MEM, word_mode,
4691 gen_rtx (PLUS, Pmode, base_reg_rtx,
4692 GEN_INT (gp_offset - base_offset)));
4693
4694 if (store_p)
4695 emit_move_insn (mem_rtx, reg_rtx);
4696 else if (!TARGET_ABICALLS || (ABI_64BIT && mips_isa >= 3)
4697 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
4698 emit_move_insn (reg_rtx, mem_rtx);
4699 }
4700 else
4701 {
4702 if (store_p || !TARGET_ABICALLS || (ABI_64BIT && mips_isa >= 3)
4703 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
4704 fprintf (file, "\t%s\t%s,%ld(%s)\n",
4705 (TARGET_64BIT
4706 ? (store_p) ? "sd" : "ld"
4707 : (store_p) ? "sw" : "lw"),
4708 reg_names[regno],
4709 gp_offset - base_offset,
4710 reg_names[REGNO(base_reg_rtx)]);
4711
4712 }
4713 gp_offset -= UNITS_PER_WORD;
4714 }
4715 }
4716 }
4717 else
4718 {
4719 base_reg_rtx = (rtx)0; /* Make sure these are initialzed */
4720 base_offset = 0;
4721 }
4722
4723 /* Save floating point registers if needed. */
4724 if (fmask)
4725 {
4726 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
4727 int fp_size = fp_inc * UNITS_PER_FPREG;
4728
4729 /* Pick which pointer to use as a base register. */
4730 fp_offset = current_frame_info.fp_sp_offset;
4731 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
4732
4733 if (fp_offset < 0 || end_offset < 0)
4734 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
4735 fp_offset, end_offset);
4736
4737 else if (fp_offset < 32768)
4738 {
4739 base_reg_rtx = stack_pointer_rtx;
4740 base_offset = 0;
4741 }
4742
4743 else if (base_reg_rtx != (rtx)0
4744 && (((unsigned long)(base_offset - fp_offset)) < 32768)
4745 && (((unsigned long)(base_offset - end_offset)) < 32768))
4746 {
4747 ; /* already set up for gp registers above */
4748 }
4749
4750 else if (large_reg != (rtx)0
4751 && (((unsigned long)(large_offset - fp_offset)) < 32768)
4752 && (((unsigned long)(large_offset - end_offset)) < 32768))
4753 {
4754 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
4755 base_offset = large_offset;
4756 if (file == (FILE *)0)
4757 {
4758 if (TARGET_LONG64)
4759 emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
4760 else
4761 emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
4762 }
4763 else
4764 fprintf (file, "\t%s\t%s,%s,%s\n",
4765 TARGET_LONG64 ? "daddu" : "addu",
4766 reg_names[MIPS_TEMP2_REGNUM],
4767 reg_names[REGNO (large_reg)],
4768 reg_names[STACK_POINTER_REGNUM]);
4769 }
4770
4771 else
4772 {
4773 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
4774 base_offset = fp_offset;
4775 if (file == (FILE *)0)
4776 {
4777 emit_move_insn (base_reg_rtx, GEN_INT (fp_offset));
4778 if (TARGET_LONG64)
4779 emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
4780 else
4781 emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
4782 }
4783 else
4784 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
4785 reg_names[MIPS_TEMP2_REGNUM],
4786 (long)base_offset,
4787 (long)base_offset,
4788 TARGET_LONG64 ? "daddu" : "addu",
4789 reg_names[MIPS_TEMP2_REGNUM],
4790 reg_names[MIPS_TEMP2_REGNUM],
4791 reg_names[STACK_POINTER_REGNUM]);
4792 }
4793
4794 for (regno = FP_REG_LAST-1; regno >= FP_REG_FIRST; regno -= fp_inc)
4795 {
4796 if (BITSET_P (fmask, regno - FP_REG_FIRST))
4797 {
4798 if (file == (FILE *)0)
4799 {
4800 enum machine_mode sz =
4801 TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4802 rtx reg_rtx = gen_rtx (REG, sz, regno);
4803 rtx mem_rtx = gen_rtx (MEM, sz,
4804 gen_rtx (PLUS, Pmode, base_reg_rtx,
4805 GEN_INT (fp_offset - base_offset)));
4806
4807 if (store_p)
4808 emit_move_insn (mem_rtx, reg_rtx);
4809 else
4810 emit_move_insn (reg_rtx, mem_rtx);
4811 }
4812 else
4813 fprintf (file, "\t%s\t%s,%ld(%s)\n",
4814 (TARGET_SINGLE_FLOAT
4815 ? ((store_p) ? "s.s" : "l.s")
4816 : ((store_p) ? "s.d" : "l.d")),
4817 reg_names[regno],
4818 fp_offset - base_offset,
4819 reg_names[REGNO(base_reg_rtx)]);
4820
4821
4822 fp_offset -= fp_size;
4823 }
4824 }
4825 }
4826 }
4827
4828 \f
4829 /* Set up the stack and frame (if desired) for the function. */
4830
4831 void
4832 function_prologue (file, size)
4833 FILE *file;
4834 int size;
4835 {
4836 long tsize = current_frame_info.total_size;
4837
4838 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
4839
4840 #ifdef SDB_DEBUGGING_INFO
4841 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
4842 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
4843 #endif
4844
4845 inside_function = 1;
4846 fputs ("\t.ent\t", file);
4847 assemble_name (file, current_function_name);
4848 fputs ("\n", file);
4849
4850 assemble_name (file, current_function_name);
4851 fputs (":\n", file);
4852
4853 fprintf (file, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
4854 reg_names[ (frame_pointer_needed) ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ],
4855 tsize,
4856 reg_names[31 + GP_REG_FIRST],
4857 current_frame_info.var_size,
4858 current_frame_info.num_gp,
4859 current_frame_info.num_fp,
4860 current_function_outgoing_args_size,
4861 current_frame_info.extra_size);
4862
4863 fprintf (file, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
4864 current_frame_info.mask,
4865 current_frame_info.gp_save_offset,
4866 current_frame_info.fmask,
4867 current_frame_info.fp_save_offset);
4868
4869 if (TARGET_ABICALLS && ! (ABI_64BIT && mips_isa >= 3))
4870 {
4871 char *sp_str = reg_names[STACK_POINTER_REGNUM];
4872
4873 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
4874 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
4875 if (tsize > 0)
4876 {
4877 fprintf (file, "\t%s\t%s,%s,%d\n",
4878 (TARGET_LONG64 ? "dsubu" : "subu"),
4879 sp_str, sp_str, tsize);
4880 fprintf (file, "\t.cprestore %d\n", current_frame_info.args_size);
4881 }
4882 }
4883 }
4884
4885 \f
4886 /* Expand the prologue into a bunch of separate insns. */
4887
4888 void
4889 mips_expand_prologue ()
4890 {
4891 int regno;
4892 long tsize;
4893 rtx tmp_rtx = (rtx)0;
4894 char *arg_name = (char *)0;
4895 tree fndecl = current_function_decl;
4896 tree fntype = TREE_TYPE (fndecl);
4897 tree fnargs = (TREE_CODE (fntype) != METHOD_TYPE)
4898 ? DECL_ARGUMENTS (fndecl)
4899 : 0;
4900 rtx next_arg_reg;
4901 int i;
4902 tree next_arg;
4903 tree cur_arg;
4904 CUMULATIVE_ARGS args_so_far;
4905
4906 /* If struct value address is treated as the first argument, make it so. */
4907 if (aggregate_value_p (DECL_RESULT (fndecl))
4908 && ! current_function_returns_pcc_struct
4909 && struct_value_incoming_rtx == 0)
4910 {
4911 tree type = build_pointer_type (fntype);
4912 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
4913 DECL_ARG_TYPE (function_result_decl) = type;
4914 TREE_CHAIN (function_result_decl) = fnargs;
4915 fnargs = function_result_decl;
4916 }
4917
4918 /* Determine the last argument, and get its name. */
4919
4920 INIT_CUMULATIVE_ARGS (args_so_far, fntype, (rtx)0);
4921 regno = GP_ARG_FIRST;
4922
4923 for (cur_arg = fnargs; cur_arg != (tree)0; cur_arg = next_arg)
4924 {
4925 tree passed_type = DECL_ARG_TYPE (cur_arg);
4926 enum machine_mode passed_mode = TYPE_MODE (passed_type);
4927 rtx entry_parm;
4928
4929 if (TYPE_NEEDS_CONSTRUCTING (passed_type))
4930 {
4931 passed_type = build_pointer_type (passed_type);
4932 passed_mode = Pmode;
4933 }
4934
4935 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
4936
4937 if (entry_parm)
4938 {
4939 int words;
4940
4941 /* passed in a register, so will get homed automatically */
4942 if (GET_MODE (entry_parm) == BLKmode)
4943 words = (int_size_in_bytes (passed_type) + 3) / 4;
4944 else
4945 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
4946
4947 regno = REGNO (entry_parm) + words - 1;
4948 }
4949 else
4950 {
4951 regno = GP_ARG_LAST+1;
4952 break;
4953 }
4954
4955 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
4956
4957 next_arg = TREE_CHAIN (cur_arg);
4958 if (next_arg == (tree)0)
4959 {
4960 if (DECL_NAME (cur_arg))
4961 arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg));
4962
4963 break;
4964 }
4965 }
4966
4967 /* In order to pass small structures by value in registers
4968 compatibly with the MIPS compiler, we need to shift the value
4969 into the high part of the register. Function_arg has encoded a
4970 PARALLEL rtx, holding a vector of adjustments to be made as the
4971 next_arg_reg variable, so we split up the insns, and emit them
4972 separately. */
4973
4974 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
4975 if (next_arg_reg != (rtx)0 && GET_CODE (next_arg_reg) == PARALLEL)
4976 {
4977 rtvec adjust = XVEC (next_arg_reg, 0);
4978 int num = GET_NUM_ELEM (adjust);
4979
4980 for (i = 0; i < num; i++)
4981 {
4982 rtx pattern = RTVEC_ELT (adjust, i);
4983 if (GET_CODE (pattern) != SET
4984 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
4985 abort_with_insn (pattern, "Insn is not a shift");
4986
4987 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
4988 emit_insn (pattern);
4989 }
4990 }
4991
4992 tsize = compute_frame_size (get_frame_size ());
4993
4994 /* If this function is a varargs function, store any registers that
4995 would normally hold arguments ($4 - $7) on the stack. */
4996 if ((! ABI_64BIT || mips_isa < 3)
4997 && ((TYPE_ARG_TYPES (fntype) != 0
4998 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
4999 || (arg_name != (char *)0
5000 && ((arg_name[0] == '_' && strcmp (arg_name, "__builtin_va_alist") == 0)
5001 || (arg_name[0] == 'v' && strcmp (arg_name, "va_alist") == 0)))))
5002 {
5003 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
5004 rtx ptr = stack_pointer_rtx;
5005
5006 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
5007 if (TARGET_ABICALLS && ! (ABI_64BIT && mips_isa >= 3))
5008 offset += tsize;
5009
5010 for (; regno <= GP_ARG_LAST; regno++)
5011 {
5012 if (offset != 0)
5013 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
5014 emit_move_insn (gen_rtx (MEM, word_mode, ptr),
5015 gen_rtx (REG, word_mode, regno));
5016 offset += UNITS_PER_WORD;
5017 }
5018 }
5019
5020 if (tsize > 0)
5021 {
5022 rtx tsize_rtx = GEN_INT (tsize);
5023
5024 /* If we are doing svr4-abi, sp move is done by function_prologue. */
5025 if (!TARGET_ABICALLS || (ABI_64BIT && mips_isa >= 3))
5026 {
5027 if (tsize > 32767)
5028 {
5029 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
5030 emit_move_insn (tmp_rtx, tsize_rtx);
5031 tsize_rtx = tmp_rtx;
5032 }
5033
5034 if (TARGET_LONG64)
5035 emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
5036 tsize_rtx));
5037 else
5038 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
5039 tsize_rtx));
5040 }
5041
5042 save_restore_insns (TRUE, tmp_rtx, tsize, (FILE *)0);
5043
5044 if (frame_pointer_needed)
5045 {
5046 if (TARGET_64BIT)
5047 emit_insn (gen_movdi (frame_pointer_rtx, stack_pointer_rtx));
5048 else
5049 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
5050 }
5051
5052 if (TARGET_ABICALLS && (ABI_64BIT && mips_isa >= 3))
5053 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0)));
5054 }
5055
5056 /* If we are profiling, make sure no instructions are scheduled before
5057 the call to mcount. */
5058
5059 if (profile_flag || profile_block_flag)
5060 emit_insn (gen_blockage ());
5061 }
5062
5063 \f
5064 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
5065
5066 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5067 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5068
5069 void
5070 function_epilogue (file, size)
5071 FILE *file;
5072 int size;
5073 {
5074 long tsize;
5075 char *sp_str = reg_names[STACK_POINTER_REGNUM];
5076 char *t1_str = reg_names[MIPS_TEMP1_REGNUM];
5077 rtx epilogue_delay = current_function_epilogue_delay_list;
5078 int noreorder = (epilogue_delay != 0);
5079 int noepilogue = FALSE;
5080 int load_nop = FALSE;
5081 int load_only_r31;
5082 rtx tmp_rtx = (rtx)0;
5083 rtx restore_rtx;
5084 int i;
5085
5086 /* The epilogue does not depend on any registers, but the stack
5087 registers, so we assume that if we have 1 pending nop, it can be
5088 ignored, and 2 it must be filled (2 nops occur for integer
5089 multiply and divide). */
5090
5091 if (dslots_number_nops > 0)
5092 {
5093 if (dslots_number_nops == 1)
5094 {
5095 dslots_number_nops = 0;
5096 dslots_load_filled++;
5097 }
5098 else
5099 {
5100 while (--dslots_number_nops > 0)
5101 fputs ("\t#nop\n", asm_out_file);
5102 }
5103 }
5104
5105 if (set_noat != 0)
5106 {
5107 set_noat = 0;
5108 fputs ("\t.set\tat\n", file);
5109 error ("internal gcc error: .set noat left on in epilogue");
5110 }
5111
5112 if (set_nomacro != 0)
5113 {
5114 set_nomacro = 0;
5115 fputs ("\t.set\tmacro\n", file);
5116 error ("internal gcc error: .set nomacro left on in epilogue");
5117 }
5118
5119 if (set_noreorder != 0)
5120 {
5121 set_noreorder = 0;
5122 fputs ("\t.set\treorder\n", file);
5123 error ("internal gcc error: .set noreorder left on in epilogue");
5124 }
5125
5126 if (set_volatile != 0)
5127 {
5128 set_volatile = 0;
5129 fprintf (file, "\t%s.set\tnovolatile\n", (TARGET_MIPS_AS) ? "" : "#");
5130 error ("internal gcc error: .set volatile left on in epilogue");
5131 }
5132
5133 size = MIPS_STACK_ALIGN (size);
5134 tsize = (!current_frame_info.initialized)
5135 ? compute_frame_size (size)
5136 : current_frame_info.total_size;
5137
5138 if (tsize == 0 && epilogue_delay == 0)
5139 {
5140 rtx insn = get_last_insn ();
5141
5142 /* If the last insn was a BARRIER, we don't have to write any code
5143 because a jump (aka return) was put there. */
5144 if (GET_CODE (insn) == NOTE)
5145 insn = prev_nonnote_insn (insn);
5146 if (insn && GET_CODE (insn) == BARRIER)
5147 noepilogue = TRUE;
5148
5149 noreorder = FALSE;
5150 }
5151
5152 if (!noepilogue)
5153 {
5154 /* In the reload sequence, we don't need to fill the load delay
5155 slots for most of the loads, also see if we can fill the final
5156 delay slot if not otherwise filled by the reload sequence. */
5157
5158 if (noreorder)
5159 fprintf (file, "\t.set\tnoreorder\n");
5160
5161 if (tsize > 32767)
5162 {
5163 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n", t1_str, (long)tsize, (long)tsize);
5164 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
5165 }
5166
5167 if (frame_pointer_needed)
5168 fprintf (file, "\tmove\t%s,%s\t\t\t# sp not trusted here\n",
5169 sp_str, reg_names[FRAME_POINTER_REGNUM]);
5170
5171 save_restore_insns (FALSE, tmp_rtx, tsize, file);
5172
5173 load_only_r31 = (((current_frame_info.mask
5174 & ~ (TARGET_ABICALLS && ! (ABI_64BIT && mips_isa >= 3)
5175 ? PIC_OFFSET_TABLE_MASK : 0))
5176 == RA_MASK)
5177 && current_frame_info.fmask == 0);
5178
5179 if (noreorder)
5180 {
5181 /* If the only register saved is the return address, we need a
5182 nop, unless we have an instruction to put into it. Otherwise
5183 we don't since reloading multiple registers doesn't reference
5184 the register being loaded. */
5185
5186 if (load_only_r31)
5187 {
5188 if (epilogue_delay)
5189 final_scan_insn (XEXP (epilogue_delay, 0),
5190 file,
5191 1, /* optimize */
5192 -2, /* prescan */
5193 1); /* nopeepholes */
5194 else
5195 {
5196 fprintf (file, "\tnop\n");
5197 load_nop = TRUE;
5198 }
5199 }
5200
5201 fprintf (file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 31]);
5202
5203 if (tsize > 32767)
5204 fprintf (file, "\t%s\t%s,%s,%s\n",
5205 TARGET_LONG64 ? "daddu" : "addu",
5206 sp_str, sp_str, t1_str);
5207
5208 else if (tsize > 0)
5209 fprintf (file, "\t%s\t%s,%s,%d\n",
5210 TARGET_LONG64 ? "daddu" : "addu",
5211 sp_str, sp_str, tsize);
5212
5213 else if (!load_only_r31 && epilogue_delay != 0)
5214 final_scan_insn (XEXP (epilogue_delay, 0),
5215 file,
5216 1, /* optimize */
5217 -2, /* prescan */
5218 1); /* nopeepholes */
5219
5220 fprintf (file, "\t.set\treorder\n");
5221 }
5222
5223 else
5224 {
5225 if (tsize > 32767)
5226 fprintf (file, "\t%s\t%s,%s,%s\n",
5227 TARGET_LONG64 ? "daddu" : "addu",
5228 sp_str, sp_str, t1_str);
5229
5230 else if (tsize > 0)
5231 fprintf (file, "\t%s\t%s,%s,%d\n",
5232 TARGET_LONG64 ? "daddu" : "addu",
5233 sp_str, sp_str, tsize);
5234
5235 fprintf (file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 31]);
5236 }
5237 }
5238
5239 fputs ("\t.end\t", file);
5240 assemble_name (file, current_function_name);
5241 fputs ("\n", file);
5242
5243 if (TARGET_STATS)
5244 {
5245 int num_gp_regs = current_frame_info.gp_reg_size / 4;
5246 int num_fp_regs = current_frame_info.fp_reg_size / 8;
5247 int num_regs = num_gp_regs + num_fp_regs;
5248 char *name = current_function_name;
5249
5250 if (name[0] == '*')
5251 name++;
5252
5253 dslots_load_total += num_regs;
5254
5255 if (!noepilogue)
5256 dslots_jump_total++;
5257
5258 if (noreorder)
5259 {
5260 dslots_load_filled += num_regs;
5261
5262 /* If the only register saved is the return register, we
5263 can't fill this register's delay slot. */
5264
5265 if (load_only_r31 && epilogue_delay == 0)
5266 dslots_load_filled--;
5267
5268 if (tsize > 0 || (!load_only_r31 && epilogue_delay != 0))
5269 dslots_jump_filled++;
5270 }
5271
5272 fprintf (stderr,
5273 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5274 name,
5275 (frame_pointer_needed) ? 'y' : 'n',
5276 ((current_frame_info.mask & RA_MASK) != 0) ? 'n' : 'y',
5277 (current_function_calls_alloca) ? 'y' : 'n',
5278 (current_function_calls_setjmp) ? 'y' : 'n',
5279 (long)current_frame_info.total_size,
5280 (long)current_function_outgoing_args_size,
5281 num_gp_regs, num_fp_regs,
5282 dslots_load_total, dslots_load_filled,
5283 dslots_jump_total, dslots_jump_filled,
5284 num_refs[0], num_refs[1], num_refs[2]);
5285
5286 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
5287 {
5288 fprintf (stderr, " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
5289 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
5290 }
5291
5292 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
5293 {
5294 fprintf (stderr, " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
5295 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
5296 }
5297
5298 fputc ('\n', stderr);
5299 }
5300
5301 /* Reset state info for each function. */
5302 inside_function = FALSE;
5303 ignore_line_number = FALSE;
5304 dslots_load_total = 0;
5305 dslots_jump_total = 0;
5306 dslots_load_filled = 0;
5307 dslots_jump_filled = 0;
5308 num_refs[0] = 0;
5309 num_refs[1] = 0;
5310 num_refs[2] = 0;
5311 mips_load_reg = (rtx)0;
5312 mips_load_reg2 = (rtx)0;
5313 current_frame_info = zero_frame_info;
5314
5315 /* Restore the output file if optimizing the GP (optimizing the GP causes
5316 the text to be diverted to a tempfile, so that data decls come before
5317 references to the data). */
5318
5319 if (TARGET_GP_OPT)
5320 asm_out_file = asm_out_data_file;
5321 }
5322
5323 \f
5324 /* Expand the epilogue into a bunch of separate insns. */
5325
5326 void
5327 mips_expand_epilogue ()
5328 {
5329 long tsize = current_frame_info.total_size;
5330 rtx tsize_rtx = GEN_INT (tsize);
5331 rtx tmp_rtx = (rtx)0;
5332
5333 if (tsize > 32767)
5334 {
5335 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
5336 emit_move_insn (tmp_rtx, tsize_rtx);
5337 tsize_rtx = tmp_rtx;
5338 }
5339
5340 if (tsize > 0)
5341 {
5342 if (frame_pointer_needed)
5343 {
5344 if (TARGET_LONG64)
5345 emit_insn (gen_movdi (stack_pointer_rtx, frame_pointer_rtx));
5346 else
5347 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
5348 }
5349
5350 save_restore_insns (FALSE, tmp_rtx, tsize, (FILE *)0);
5351
5352 if (TARGET_LONG64)
5353 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
5354 tsize_rtx));
5355 else
5356 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
5357 tsize_rtx));
5358 }
5359
5360 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode, GP_REG_FIRST+31)));
5361 }
5362
5363 \f
5364 /* Define the number of delay slots needed for the function epilogue.
5365
5366 On the mips, we need a slot if either no stack has been allocated,
5367 or the only register saved is the return register. */
5368
5369 int
5370 mips_epilogue_delay_slots ()
5371 {
5372 if (!current_frame_info.initialized)
5373 (void) compute_frame_size (get_frame_size ());
5374
5375 if (current_frame_info.total_size == 0)
5376 return 1;
5377
5378 if (current_frame_info.mask == RA_MASK && current_frame_info.fmask == 0)
5379 return 1;
5380
5381 return 0;
5382 }
5383
5384 \f
5385 /* Return true if this function is known to have a null epilogue.
5386 This allows the optimizer to omit jumps to jumps if no stack
5387 was created. */
5388
5389 int
5390 simple_epilogue_p ()
5391 {
5392 if (!reload_completed)
5393 return 0;
5394
5395 if (current_frame_info.initialized)
5396 return current_frame_info.total_size == 0;
5397
5398 return (compute_frame_size (get_frame_size ())) == 0;
5399 }
5400 \f
5401 /* Choose the section to use for the constant rtx expression X that has
5402 mode MODE. */
5403
5404 mips_select_rtx_section (mode, x)
5405 enum machine_mode mode;
5406 rtx x;
5407 {
5408 if (TARGET_EMBEDDED_DATA)
5409 {
5410 /* For embedded applications, always put constants in read-only data,
5411 in order to reduce RAM usage. */
5412 READONLY_DATA_SECTION ();
5413 }
5414 else
5415 {
5416 /* For hosted applications, always put constants in small data if
5417 possible, as this gives the best performance. */
5418
5419 if (GET_MODE_SIZE (mode) <= mips_section_threshold
5420 && mips_section_threshold > 0)
5421 SMALL_DATA_SECTION ();
5422 else
5423 READONLY_DATA_SECTION ();
5424 }
5425 }
5426
5427 /* Choose the section to use for DECL. RELOC is true if its value contains
5428 any relocatable expression. */
5429
5430 mips_select_section (decl, reloc)
5431 tree decl;
5432 int reloc;
5433 {
5434 int size = int_size_in_bytes (TREE_TYPE (decl));
5435
5436 if (TARGET_EMBEDDED_PIC
5437 && TREE_CODE (decl) == STRING_CST
5438 && !flag_writable_strings)
5439 {
5440 /* For embedded position independent code, put constant strings
5441 in the text section, because the data section is limited to
5442 64K in size. */
5443
5444 text_section ();
5445 }
5446 else if (TARGET_EMBEDDED_DATA)
5447 {
5448 /* For embedded applications, always put an object in read-only data
5449 if possible, in order to reduce RAM usage. */
5450
5451 if (((TREE_CODE (decl) == VAR_DECL
5452 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
5453 && DECL_INITIAL (decl)
5454 && (DECL_INITIAL (decl) == error_mark_node
5455 || TREE_CONSTANT (DECL_INITIAL (decl))))
5456 /* Deal with calls from output_constant_def_contents. */
5457 || (TREE_CODE (decl) != VAR_DECL
5458 && (TREE_CODE (decl) != STRING_CST
5459 || !flag_writable_strings)))
5460 && ! (flag_pic && reloc))
5461 READONLY_DATA_SECTION ();
5462 else if (size > 0 && size <= mips_section_threshold)
5463 SMALL_DATA_SECTION ();
5464 else
5465 data_section ();
5466 }
5467 else
5468 {
5469 /* For hosted applications, always put an object in small data if
5470 possible, as this gives the best performance. */
5471
5472 if (size > 0 && size <= mips_section_threshold)
5473 SMALL_DATA_SECTION ();
5474 else if (((TREE_CODE (decl) == VAR_DECL
5475 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
5476 && DECL_INITIAL (decl)
5477 && (DECL_INITIAL (decl) == error_mark_node
5478 || TREE_CONSTANT (DECL_INITIAL (decl))))
5479 /* Deal with calls from output_constant_def_contents. */
5480 || (TREE_CODE (decl) != VAR_DECL
5481 && (TREE_CODE (decl) != STRING_CST
5482 || !flag_writable_strings)))
5483 && ! (flag_pic && reloc))
5484 READONLY_DATA_SECTION ();
5485 else
5486 data_section ();
5487 }
5488 }
5489 \f
5490 #if ABI_64BIT
5491 /* Support functions for the 64 bit ABI. */
5492
5493 /* Return the register to be used for word INDEX of a variable with type TYPE
5494 being passed starting at general purpose reg REGNO.
5495
5496 If the word being passed is a single field of a structure which has type
5497 double, then pass it in a floating point reg instead of a general purpose
5498 reg. Otherwise, we return the default value REGNO + INDEX. */
5499
5500 rtx
5501 type_dependent_reg (regno, index, type)
5502 int regno;
5503 int index;
5504 tree type;
5505 {
5506 tree field;
5507 tree offset;
5508
5509 /* If type isn't a structure type, return the default value now. */
5510 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_isa < 3)
5511 return gen_rtx (REG, word_mode, regno + index);
5512
5513 /* Iterate through the structure fields to find which one corresponds to
5514 this index. */
5515 offset = size_int (index * BITS_PER_WORD);
5516 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5517 {
5518 if (! tree_int_cst_lt (DECL_FIELD_BITPOS (field), offset))
5519 break;
5520 }
5521
5522 if (field && tree_int_cst_equal (DECL_FIELD_BITPOS (field), offset)
5523 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
5524 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5525 return gen_rtx (REG, DFmode,
5526 regno + index + FP_ARG_FIRST - GP_ARG_FIRST);
5527 else
5528 return gen_rtx (REG, word_mode, regno + index);
5529 }
5530
5531 /* Return register to use for a function return value with VALTYPE for function
5532 FUNC. */
5533
5534 rtx
5535 mips_function_value (valtype, func)
5536 tree valtype;
5537 tree func;
5538 {
5539 int reg = GP_RETURN;
5540 enum machine_mode mode = TYPE_MODE (valtype);
5541 enum mode_class mclass = GET_MODE_CLASS (mode);
5542
5543 if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
5544 reg = FP_RETURN;
5545 else if (TREE_CODE (valtype) == RECORD_TYPE && mips_isa >= 3)
5546 {
5547 /* A struct with only one or two floating point fields is returned in
5548 the floating point registers. */
5549 tree field;
5550 int i;
5551
5552 for (i = 0, field = TYPE_FIELDS (valtype); field;
5553 field = TREE_CHAIN (field), i++)
5554 {
5555 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
5556 break;
5557 }
5558
5559 if (! field)
5560 reg = FP_RETURN;
5561 }
5562
5563 return gen_rtx (REG, mode, reg);
5564 }
5565 #endif
5566
5567 /* This function returns the register class required for a secondary
5568 register when copying between one of the registers in CLASS, and X,
5569 using MODE. If IN_P is nonzero, the copy is going from X to the
5570 register, otherwise the register is the source. A return value of
5571 NO_REGS means that no secondary register is required. */
5572
5573 enum reg_class
5574 mips_secondary_reload_class (class, mode, x, in_p)
5575 enum reg_class class;
5576 enum machine_mode mode;
5577 rtx x;
5578 int in_p;
5579 {
5580 int regno = -1;
5581
5582 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
5583 regno = true_regnum (x);
5584
5585 /* We always require a general register when copying anything to
5586 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
5587 to a general register, or when copying from register 0. */
5588 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
5589 {
5590 if (! in_p
5591 && GP_REG_P (regno)
5592 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
5593 return NO_REGS;
5594 return GR_REGS;
5595 }
5596 if (regno == HILO_REGNUM)
5597 {
5598 if (in_p
5599 && class == GR_REGS
5600 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
5601 return NO_REGS;
5602 return GR_REGS;
5603 }
5604
5605 /* Copying from HI or LO to anywhere other than a general register
5606 requires a general register. */
5607 if (class == HI_REG || class == LO_REG || class == MD_REGS)
5608 {
5609 if (GP_REG_P (regno))
5610 return NO_REGS;
5611 return GR_REGS;
5612 }
5613 if (MD_REG_P (regno))
5614 {
5615 if (class == GR_REGS)
5616 return NO_REGS;
5617 return GR_REGS;
5618 }
5619
5620 return NO_REGS;
5621 }