projects / gcc.git / blob
? search:


21693bab533032cefa370cac334bc0cd979509f8
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Contributed by A. Lichnewsky, lich@inria.inria.fr
3 Changed by Michael Meissner, meissner@osf.org
4 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
5 Brendan Eich, brendan@microunity.com.
6 Copyright (C) 1989, 90-5, 1996 Free Software Foundation, Inc.
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25
26 /* Standard GCC variables that we reference. */
27
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int current_function_calls_alloca;
31 extern int flag_omit_frame_pointer;
32 extern int frame_pointer_needed;
33 extern char *language_string;
34 extern int may_call_alloca;
35 extern int optimize;
36 extern char **save_argv;
37 extern int target_flags;
38 extern char *version_string;
39
40 /* MIPS external variables defined in mips.c. */
41
42 /* comparison type */
43 enum cmp_type {
44 CMP_SI, /* compare four byte integers */
45 CMP_DI, /* compare eight byte integers */
46 CMP_SF, /* compare single precision floats */
47 CMP_DF, /* compare double precision floats */
48 CMP_MAX /* max comparison type */
49 };
50
51 /* types of delay slot */
52 enum delay_type {
53 DELAY_NONE, /* no delay slot */
54 DELAY_LOAD, /* load from memory delay */
55 DELAY_HILO, /* move from/to hi/lo registers */
56 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
57 };
58
59 /* Which processor to schedule for. Since there is no difference between
60 a R2000 and R3000 in terms of the scheduler, we collapse them into
61 just an R3000. The elements of the enumeration must match exactly
62 the cpu attribute in the mips.md machine description. */
63
64 enum processor_type {
65 PROCESSOR_DEFAULT,
66 PROCESSOR_R3000,
67 PROCESSOR_R6000,
68 PROCESSOR_R4000,
69 PROCESSOR_R4600,
70 PROCESSOR_R4650,
71 PROCESSOR_R8000
72 };
73
74 /* Recast the cpu class to be the cpu attribute. */
75 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
76
77 /* Whether to emit abicalls code sequences or not. */
78
79 enum mips_abicalls_type {
80 MIPS_ABICALLS_NO,
81 MIPS_ABICALLS_YES
82 };
83
84 /* Recast the abicalls class to be the abicalls attribute. */
85 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
86
87 /* Which type of block move to do (whether or not the last store is
88 split out so it can fill a branch delay slot). */
89
90 enum block_move_type {
91 BLOCK_MOVE_NORMAL, /* generate complete block move */
92 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
93 BLOCK_MOVE_LAST /* generate just the last store */
94 };
95
96 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
97 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
98 extern char *current_function_file; /* filename current function is in */
99 extern int num_source_filenames; /* current .file # */
100 extern int inside_function; /* != 0 if inside of a function */
101 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
102 extern int file_in_function_warning; /* warning given about .file in func */
103 extern int sdb_label_count; /* block start/end next label # */
104 extern int sdb_begin_function_line; /* Starting Line of current function */
105 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
106 extern int g_switch_value; /* value of the -G xx switch */
107 extern int g_switch_set; /* whether -G xx was passed. */
108 extern int sym_lineno; /* sgi next label # for each stmt */
109 extern int set_noreorder; /* # of nested .set noreorder's */
110 extern int set_nomacro; /* # of nested .set nomacro's */
111 extern int set_noat; /* # of nested .set noat's */
112 extern int set_volatile; /* # of nested .set volatile's */
113 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
114 extern int mips_dbx_regno[]; /* Map register # to debug register # */
115 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
116 extern enum cmp_type branch_type; /* what type of branch to use */
117 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
118 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
119 extern int mips_isa; /* architectural level */
120 extern char *mips_cpu_string; /* for -mcpu=<xxx> */
121 extern char *mips_isa_string; /* for -mips{1,2,3,4} */
122 extern int dslots_load_total; /* total # load related delay slots */
123 extern int dslots_load_filled; /* # filled load delay slots */
124 extern int dslots_jump_total; /* total # jump related delay slots */
125 extern int dslots_jump_filled; /* # filled jump delay slots */
126 extern int dslots_number_nops; /* # of nops needed by previous insn */
127 extern int num_refs[3]; /* # 1/2/3 word references */
128 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
129 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
130 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
131 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
132 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
133
134 /* Functions within mips.c that we reference. */
135
136 extern void abort_with_insn ();
137 extern int arith32_operand ();
138 extern int arith_operand ();
139 extern int cmp_op ();
140 extern long compute_frame_size ();
141 extern int epilogue_reg_mentioned_p ();
142 extern void expand_block_move ();
143 extern int equality_op ();
144 extern void final_prescan_insn ();
145 extern struct rtx_def * function_arg ();
146 extern void function_arg_advance ();
147 extern int function_arg_partial_nregs ();
148 extern void function_epilogue ();
149 extern void function_prologue ();
150 extern void gen_conditional_branch ();
151 extern struct rtx_def * gen_int_relational ();
152 extern void init_cumulative_args ();
153 extern int large_int ();
154 extern int mips_address_cost ();
155 extern void mips_asm_file_end ();
156 extern void mips_asm_file_start ();
157 extern int mips_const_double_ok ();
158 extern void mips_count_memory_refs ();
159 extern int mips_debugger_offset ();
160 extern void mips_declare_object ();
161 extern int mips_epilogue_delay_slots ();
162 extern void mips_expand_epilogue ();
163 extern void mips_expand_prologue ();
164 extern char *mips_fill_delay_slot ();
165 extern char *mips_move_1word ();
166 extern char *mips_move_2words ();
167 extern void mips_output_double ();
168 extern int mips_output_external ();
169 extern void mips_output_float ();
170 extern void mips_output_filename ();
171 extern void mips_output_lineno ();
172 extern char *output_block_move ();
173 extern void override_options ();
174 extern int pc_or_label_operand ();
175 extern void print_operand_address ();
176 extern void print_operand ();
177 extern void print_options ();
178 extern int reg_or_0_operand ();
179 extern int simple_epilogue_p ();
180 extern int simple_memory_operand ();
181 extern int small_int ();
182 extern void trace();
183 extern int uns_arith_operand ();
184 extern struct rtx_def * embedded_pic_offset ();
185
186 /* Recognition functions that return if a condition is true. */
187 extern int address_operand ();
188 extern int const_double_operand ();
189 extern int const_int_operand ();
190 extern int general_operand ();
191 extern int immediate_operand ();
192 extern int memory_address_p ();
193 extern int memory_operand ();
194 extern int nonimmediate_operand ();
195 extern int nonmemory_operand ();
196 extern int register_operand ();
197 extern int scratch_operand ();
198
199 /* Functions to change what output section we are using. */
200 extern void data_section ();
201 extern void rdata_section ();
202 extern void readonly_data_section ();
203 extern void sdata_section ();
204 extern void text_section ();
205
206 /* Functions in the rest of the compiler that we reference. */
207 extern void abort_with_insn ();
208 extern void debug_rtx ();
209 extern void fatal_io_error ();
210 extern int get_frame_size ();
211 extern int offsettable_address_p ();
212 extern void output_address ();
213 extern char *permalloc ();
214 extern int reg_mentioned_p ();
215
216 /* Functions in the standard library that we reference. */
217 extern int atoi ();
218 extern char *getenv ();
219 extern char *mktemp ();
220
221
222 /* Stubs for half-pic support if not OSF/1 reference platform. */
223
224 #ifndef HALF_PIC_P
225 #define HALF_PIC_P() 0
226 #define HALF_PIC_NUMBER_PTRS 0
227 #define HALF_PIC_NUMBER_REFS 0
228 #define HALF_PIC_ENCODE(DECL)
229 #define HALF_PIC_DECLARE(NAME)
230 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
231 #define HALF_PIC_ADDRESS_P(X) 0
232 #define HALF_PIC_PTR(X) X
233 #define HALF_PIC_FINISH(STREAM)
234 #endif
235
236 \f
237 /* Run-time compilation parameters selecting different hardware subsets. */
238
239 /* Macros used in the machine description to test the flags. */
240
241 /* Bits for real switches */
242 #define MASK_INT64 0x00000001 /* ints are 64 bits */
243 #define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
244 #define MASK_UNUSED 0x00000004
245 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
246 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
247 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
248 #define MASK_STATS 0x00000040 /* print statistics to stderr */
249 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
250 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
251 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
252 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
253 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
254 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
255 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
256 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
257 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
258 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
259 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
260 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
261 #define MASK_UNUSED1 0x00080000
262
263 /* Dummy switches used only in spec's*/
264 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
265
266 /* Debug switches, not documented */
267 #define MASK_DEBUG 0x40000000 /* Eliminate version # in .s file */
268 #define MASK_DEBUG_A 0x20000000 /* don't allow <label>($reg) addrs */
269 #define MASK_DEBUG_B 0x10000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
270 #define MASK_DEBUG_C 0x08000000 /* don't expand seq, etc. */
271 #define MASK_DEBUG_D 0x04000000 /* don't do define_split's */
272 #define MASK_DEBUG_E 0x02000000 /* function_arg debug */
273 #define MASK_DEBUG_F 0x01000000 /* don't try to suppress load nop's */
274 #define MASK_DEBUG_G 0x00800000 /* don't support 64 bit arithmetic */
275 #define MASK_DEBUG_H 0x00400000 /* allow ints in FP registers */
276 #define MASK_DEBUG_I 0x00200000 /* unused */
277 #define MASK_DEBUG_J 0x00100000 /* unused */
278
279 /* r4000 64 bit sizes */
280 #define TARGET_INT64 (target_flags & MASK_INT64)
281 #define TARGET_LONG64 (target_flags & MASK_LONG64)
282 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
283 #define TARGET_64BIT (target_flags & MASK_64BIT)
284
285 /* Mips vs. GNU assembler */
286 #define TARGET_GAS (target_flags & MASK_GAS)
287 #define TARGET_UNIX_ASM (!TARGET_GAS)
288 #define TARGET_MIPS_AS TARGET_UNIX_ASM
289
290 /* Debug Mode */
291 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
292 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
293 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
294 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
295 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
296 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
297 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
298 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
299 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
300 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
301 #define TARGET_DEBUG_J_MODE (target_flags & MASK_DEBUG_J)
302
303 /* Reg. Naming in .s ($21 vs. $a0) */
304 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
305
306 /* Optimize for Sdata/Sbss */
307 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
308
309 /* print program statistics */
310 #define TARGET_STATS (target_flags & MASK_STATS)
311
312 /* call memcpy instead of inline code */
313 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
314
315 /* .abicalls, etc from Pyramid V.4 */
316 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
317
318 /* OSF pic references to externs */
319 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
320
321 /* software floating point */
322 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
323 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
324
325 /* always call through a register */
326 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
327
328 /* generate embedded PIC code;
329 requires gas. */
330 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
331
332 /* for embedded systems, optimize for
333 reduced RAM space instead of for
334 fastest code. */
335 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
336
337 /* generate big endian code. */
338 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
339
340 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
341 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
342
343 #define TARGET_MAD (target_flags & MASK_MAD)
344
345 /* Macro to define tables used to set the flags.
346 This is a list in braces of pairs in braces,
347 each pair being { "NAME", VALUE }
348 where VALUE is the bits to set or minus the bits to clear.
349 An empty string NAME is used to identify the default VALUE. */
350
351 #define TARGET_SWITCHES \
352 { \
353 {"int64", MASK_INT64 | MASK_LONG64}, \
354 {"long64", MASK_LONG64}, \
355 {"mips-as", -MASK_GAS}, \
356 {"gas", MASK_GAS}, \
357 {"rnames", MASK_NAME_REGS}, \
358 {"no-rnames", -MASK_NAME_REGS}, \
359 {"gpOPT", MASK_GPOPT}, \
360 {"gpopt", MASK_GPOPT}, \
361 {"no-gpOPT", -MASK_GPOPT}, \
362 {"no-gpopt", -MASK_GPOPT}, \
363 {"stats", MASK_STATS}, \
364 {"no-stats", -MASK_STATS}, \
365 {"memcpy", MASK_MEMCPY}, \
366 {"no-memcpy", -MASK_MEMCPY}, \
367 {"mips-tfile", MASK_MIPS_TFILE}, \
368 {"no-mips-tfile", -MASK_MIPS_TFILE}, \
369 {"soft-float", MASK_SOFT_FLOAT}, \
370 {"hard-float", -MASK_SOFT_FLOAT}, \
371 {"fp64", MASK_FLOAT64}, \
372 {"fp32", -MASK_FLOAT64}, \
373 {"gp64", MASK_64BIT}, \
374 {"gp32", -MASK_64BIT}, \
375 {"abicalls", MASK_ABICALLS}, \
376 {"no-abicalls", -MASK_ABICALLS}, \
377 {"half-pic", MASK_HALF_PIC}, \
378 {"no-half-pic", -MASK_HALF_PIC}, \
379 {"long-calls", MASK_LONG_CALLS}, \
380 {"no-long-calls", -MASK_LONG_CALLS}, \
381 {"embedded-pic", MASK_EMBEDDED_PIC}, \
382 {"no-embedded-pic", -MASK_EMBEDDED_PIC}, \
383 {"embedded-data", MASK_EMBEDDED_DATA}, \
384 {"no-embedded-data", -MASK_EMBEDDED_DATA}, \
385 {"eb", MASK_BIG_ENDIAN}, \
386 {"el", -MASK_BIG_ENDIAN}, \
387 {"single-float", MASK_SINGLE_FLOAT}, \
388 {"double-float", -MASK_SINGLE_FLOAT}, \
389 {"mad", MASK_MAD}, \
390 {"no-mad", -MASK_MAD}, \
391 {"4650", MASK_MAD | MASK_SINGLE_FLOAT}, \
392 {"debug", MASK_DEBUG}, \
393 {"debuga", MASK_DEBUG_A}, \
394 {"debugb", MASK_DEBUG_B}, \
395 {"debugc", MASK_DEBUG_C}, \
396 {"debugd", MASK_DEBUG_D}, \
397 {"debuge", MASK_DEBUG_E}, \
398 {"debugf", MASK_DEBUG_F}, \
399 {"debugg", MASK_DEBUG_G}, \
400 {"debugh", MASK_DEBUG_H}, \
401 {"debugi", MASK_DEBUG_I}, \
402 {"debugj", MASK_DEBUG_J}, \
403 {"", (TARGET_DEFAULT \
404 | TARGET_CPU_DEFAULT \
405 | TARGET_ENDIAN_DEFAULT)} \
406 }
407
408 /* Default target_flags if no switches are specified */
409
410 #ifndef TARGET_DEFAULT
411 #define TARGET_DEFAULT 0
412 #endif
413
414 #ifndef TARGET_CPU_DEFAULT
415 #define TARGET_CPU_DEFAULT 0
416 #endif
417
418 #ifndef TARGET_ENDIAN_DEFAULT
419 #ifndef DECSTATION
420 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
421 #else
422 #define TARGET_ENDIAN_DEFAULT 0
423 #endif
424 #endif
425
426 #ifndef MULTILIB_DEFAULTS
427 #if TARGET_ENDIAN_DEFAULT == 0
428 #define MULTILIB_DEFAULTS { "EL", "mips1" }
429 #else
430 #define MULTILIB_DEFAULTS { "EB", "mips1" }
431 #endif
432 #endif
433
434 /* This macro is similar to `TARGET_SWITCHES' but defines names of
435 command options that have values. Its definition is an
436 initializer with a subgrouping for each command option.
437
438 Each subgrouping contains a string constant, that defines the
439 fixed part of the option name, and the address of a variable.
440 The variable, type `char *', is set to the variable part of the
441 given option if the fixed part matches. The actual option name
442 is made by appending `-m' to the specified name.
443
444 Here is an example which defines `-mshort-data-NUMBER'. If the
445 given option is `-mshort-data-512', the variable `m88k_short_data'
446 will be set to the string `"512"'.
447
448 extern char *m88k_short_data;
449 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
450
451 #define TARGET_OPTIONS \
452 { \
453 { "cpu=", &mips_cpu_string }, \
454 { "ips", &mips_isa_string } \
455 }
456
457 /* Macros to decide whether certain features are available or not,
458 depending on the instruction set architecture level. */
459
460 #define BRANCH_LIKELY_P() (mips_isa >= 2)
461 #define HAVE_SQRT_P() (mips_isa >= 2)
462
463 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
464 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
465 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
466 target_flags, and -mgp64 sets MASK_64BIT.
467
468 Setting MASK_64BIT in target_flags will cause gcc to assume that
469 registers are 64 bits wide. int, long and void * will be 32 bit;
470 this may be changed with -mint64 or -mlong64.
471
472 The gen* programs link code that refers to MASK_64BIT. They don't
473 actually use the information in target_flags; they just refer to
474 it. */
475 \f
476 /* Switch Recognition by gcc.c. Add -G xx support */
477
478 #ifdef SWITCH_TAKES_ARG
479 #undef SWITCH_TAKES_ARG
480 #endif
481
482 #define SWITCH_TAKES_ARG(CHAR) \
483 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
484
485 /* Sometimes certain combinations of command options do not make sense
486 on a particular target machine. You can define a macro
487 `OVERRIDE_OPTIONS' to take account of this. This macro, if
488 defined, is executed once just after all the command options have
489 been parsed.
490
491 On the MIPS, it is used to handle -G. We also use it to set up all
492 of the tables referenced in the other macros. */
493
494 #define OVERRIDE_OPTIONS override_options ()
495
496 /* Zero or more C statements that may conditionally modify two
497 variables `fixed_regs' and `call_used_regs' (both of type `char
498 []') after they have been initialized from the two preceding
499 macros.
500
501 This is necessary in case the fixed or call-clobbered registers
502 depend on target flags.
503
504 You need not define this macro if it has no work to do.
505
506 If the usage of an entire class of registers depends on the target
507 flags, you may indicate this to GCC by using this macro to modify
508 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
509 the classes which should not be used by GCC. Also define the macro
510 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
511 letter for a class that shouldn't be used.
512
513 (However, if this class is not included in `GENERAL_REGS' and all
514 of the insn patterns whose constraints permit this class are
515 controlled by target switches, then GCC will automatically avoid
516 using these registers when the target switches are opposed to
517 them.) */
518
519 #define CONDITIONAL_REGISTER_USAGE \
520 do \
521 { \
522 if (!TARGET_HARD_FLOAT) \
523 { \
524 int regno; \
525 \
526 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
527 fixed_regs[regno] = call_used_regs[regno] = 1; \
528 } \
529 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
530 } \
531 while (0)
532
533 /* This is meant to be redefined in the host dependent files */
534 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
535
536 /* Show we can debug even without a frame pointer. */
537 #define CAN_DEBUG_WITHOUT_FP
538 \f
539 /* Complain about missing specs and predefines that should be defined in each
540 of the target tm files to override the defaults. This is mostly a place-
541 holder until I can get each of the files updated [mm]. */
542
543 #if defined(OSF_OS) \
544 || defined(DECSTATION) \
545 || defined(SGI_TARGET) \
546 || defined(MIPS_NEWS) \
547 || defined(MIPS_SYSV) \
548 || defined(MIPS_SVR4) \
549 || defined(MIPS_BSD43)
550
551 #ifndef CPP_PREDEFINES
552 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
553 #endif
554
555 #ifndef LIB_SPEC
556 #error "Define LIB_SPEC in the appropriate tm.h file"
557 #endif
558
559 #ifndef STARTFILE_SPEC
560 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
561 #endif
562
563 #ifndef MACHINE_TYPE
564 #error "Define MACHINE_TYPE in the appropriate tm.h file"
565 #endif
566 #endif
567
568 /* Tell collect what flags to pass to nm. */
569 #ifndef NM_FLAGS
570 #define NM_FLAGS "-Bp"
571 #endif
572
573 \f
574 /* Names to predefine in the preprocessor for this target machine. */
575
576 #ifndef CPP_PREDEFINES
577 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
578 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
579 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
580 #endif
581
582 /* Extra switches sometimes passed to the assembler. */
583
584 #ifndef ASM_SPEC
585 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
586 /* GAS */
587 #define ASM_SPEC "\
588 %{mmips-as: \
589 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
590 %{pipe: %e-pipe is not supported.} \
591 %{K}} \
592 %{!mmips-as: \
593 %{mcpu=*} %{m4650} %{mmad:-m4650}} \
594 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{v} \
595 %{noasmopt:-O0} \
596 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}} \
597 %{g} %{g0} %{g1} %{g2} %{g3} \
598 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
599 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
600 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
601 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
602 %{membedded-pic}"
603
604 #else
605 /* not GAS */
606 #define ASM_SPEC "\
607 %{!mgas: \
608 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
609 %{pipe: %e-pipe is not supported.} \
610 %{K}} \
611 %{mgas: \
612 %{mcpu=*} %{m4650} %{mmad:-m4650}} \
613 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{v} \
614 %{noasmopt:-O0} \
615 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}} \
616 %{g} %{g0} %{g1} %{g2} %{g3} \
617 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
618 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
619 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
620 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
621 %{membedded-pic}"
622
623 #endif
624 #endif /* ASM_SPEC */
625
626 /* Specify to run a post-processor, mips-tfile after the assembler
627 has run to stuff the mips debug information into the object file.
628 This is needed because the $#!%^ MIPS assembler provides no way
629 of specifying such information in the assembly file. If we are
630 cross compiling, disable mips-tfile unless the user specifies
631 -mmips-tfile. */
632
633 #ifndef ASM_FINAL_SPEC
634 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
635 /* GAS */
636 #define ASM_FINAL_SPEC "\
637 %{mmips-as: %{!mno-mips-tfile: \
638 \n mips-tfile %{v*: -v} \
639 %{K: -I %b.o~} \
640 %{!K: %{save-temps: -I %b.o~}} \
641 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
642 %{.s:%i} %{!.s:%g.s}}}"
643
644 #else
645 /* not GAS */
646 #define ASM_FINAL_SPEC "\
647 %{!mgas: %{!mno-mips-tfile: \
648 \n mips-tfile %{v*: -v} \
649 %{K: -I %b.o~} \
650 %{!K: %{save-temps: -I %b.o~}} \
651 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
652 %{.s:%i} %{!.s:%g.s}}}"
653
654 #endif
655 #endif /* ASM_FINAL_SPEC */
656
657 /* Redefinition of libraries used. Mips doesn't support normal
658 UNIX style profiling via calling _mcount. It does offer
659 profiling that samples the PC, so do what we can... */
660
661 #ifndef LIB_SPEC
662 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
663 #endif
664
665 /* Extra switches sometimes passed to the linker. */
666 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
667 will interpret it as a -b option. */
668
669 #ifndef LINK_SPEC
670 #define LINK_SPEC "\
671 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
672 %{bestGnum} %{shared} %{non_shared}"
673 #endif /* LINK_SPEC defined */
674
675 /* Specs for the compiler proper */
676
677 #ifndef CC1_SPEC
678 #define CC1_SPEC "\
679 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
680 %{mips1:-mfp32 -mgp32}%{mips2:-mfp32 -mgp32}\
681 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
682 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
683 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
684 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
685 %{m4650:-mcpu=r4650} \
686 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
687 %{pic-none: -mno-half-pic} \
688 %{pic-lib: -mhalf-pic} \
689 %{pic-extern: -mhalf-pic} \
690 %{pic-calls: -mhalf-pic} \
691 %{save-temps: }"
692 #endif
693
694 /* Preprocessor specs */
695
696 #ifndef CPP_SPEC
697 #define CPP_SPEC "\
698 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
699 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
700 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
701 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C} \
702 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
703 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
704 %{!.S:%{!.s: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}} \
705 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
706 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
707 %{mips3:-U__mips -D__mips=3 -D__mips64} \
708 %{mips4:-U__mips -D__mips=4 -D__mips64} \
709 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
710 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
711 %{m4650:%{!msoft-float:-D__mips_single_float}} \
712 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
713 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}}"
714 #endif
715
716 /* If defined, this macro is an additional prefix to try after
717 `STANDARD_EXEC_PREFIX'. */
718
719 #ifndef MD_EXEC_PREFIX
720 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
721 #endif
722
723 #ifndef MD_STARTFILE_PREFIX
724 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
725 #endif
726
727 \f
728 /* Print subsidiary information on the compiler version in use. */
729
730 #define MIPS_VERSION "[AL 1.1, MM 40]"
731
732 #ifndef MACHINE_TYPE
733 #define MACHINE_TYPE "BSD Mips"
734 #endif
735
736 #ifndef TARGET_VERSION_INTERNAL
737 #define TARGET_VERSION_INTERNAL(STREAM) \
738 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
739 #endif
740
741 #ifndef TARGET_VERSION
742 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
743 #endif
744
745 \f
746 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
747 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
748 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
749
750 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
751 #define PREFERRED_DEBUGGING_TYPE ((len > 1 && !strncmp (str, "ggdb", len)) ? DBX_DEBUG : SDB_DEBUG)
752 #endif
753
754 /* By default, turn on GDB extensions. */
755 #define DEFAULT_GDB_EXTENSIONS 1
756
757 /* If we are passing smuggling stabs through the MIPS ECOFF object
758 format, put a comment in front of the .stab<x> operation so
759 that the MIPS assembler does not choke. The mips-tfile program
760 will correctly put the stab into the object file. */
761
762 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
763 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
764 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
765
766 /* Local compiler-generated symbols must have a prefix that the assembler
767 understands. By default, this is $, although some targets (e.g.,
768 NetBSD-ELF) need to override this. */
769
770 #ifndef LOCAL_LABEL_PREFIX
771 #define LOCAL_LABEL_PREFIX "$"
772 #endif
773
774 /* By default on the mips, external symbols do not have an underscore
775 prepended, but some targets (e.g., NetBSD) require this. */
776
777 #ifndef USER_LABEL_PREFIX
778 #define USER_LABEL_PREFIX ""
779 #endif
780
781 /* Forward references to tags are allowed. */
782 #define SDB_ALLOW_FORWARD_REFERENCES
783
784 /* Unknown tags are also allowed. */
785 #define SDB_ALLOW_UNKNOWN_REFERENCES
786
787 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
788 since the length can run past this up to a continuation point. */
789 #define DBX_CONTIN_LENGTH 1500
790
791
792 /* How to renumber registers for dbx and gdb. */
793 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
794
795
796 /* Overrides for the COFF debug format. */
797 #define PUT_SDB_SCL(a) \
798 do { \
799 extern FILE *asm_out_text_file; \
800 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
801 } while (0)
802
803 #define PUT_SDB_INT_VAL(a) \
804 do { \
805 extern FILE *asm_out_text_file; \
806 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
807 } while (0)
808
809 #define PUT_SDB_VAL(a) \
810 do { \
811 extern FILE *asm_out_text_file; \
812 fputs ("\t.val\t", asm_out_text_file); \
813 output_addr_const (asm_out_text_file, (a)); \
814 fputc (';', asm_out_text_file); \
815 } while (0)
816
817 #define PUT_SDB_DEF(a) \
818 do { \
819 extern FILE *asm_out_text_file; \
820 fprintf (asm_out_text_file, "\t%s.def\t", \
821 (TARGET_GAS) ? "" : "#"); \
822 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
823 fputc (';', asm_out_text_file); \
824 } while (0)
825
826 #define PUT_SDB_PLAIN_DEF(a) \
827 do { \
828 extern FILE *asm_out_text_file; \
829 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
830 (TARGET_GAS) ? "" : "#", (a)); \
831 } while (0)
832
833 #define PUT_SDB_ENDEF \
834 do { \
835 extern FILE *asm_out_text_file; \
836 fprintf (asm_out_text_file, "\t.endef\n"); \
837 } while (0)
838
839 #define PUT_SDB_TYPE(a) \
840 do { \
841 extern FILE *asm_out_text_file; \
842 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
843 } while (0)
844
845 #define PUT_SDB_SIZE(a) \
846 do { \
847 extern FILE *asm_out_text_file; \
848 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
849 } while (0)
850
851 #define PUT_SDB_DIM(a) \
852 do { \
853 extern FILE *asm_out_text_file; \
854 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
855 } while (0)
856
857 #ifndef PUT_SDB_START_DIM
858 #define PUT_SDB_START_DIM \
859 do { \
860 extern FILE *asm_out_text_file; \
861 fprintf (asm_out_text_file, "\t.dim\t"); \
862 } while (0)
863 #endif
864
865 #ifndef PUT_SDB_NEXT_DIM
866 #define PUT_SDB_NEXT_DIM(a) \
867 do { \
868 extern FILE *asm_out_text_file; \
869 fprintf (asm_out_text_file, "%d,", a); \
870 } while (0)
871 #endif
872
873 #ifndef PUT_SDB_LAST_DIM
874 #define PUT_SDB_LAST_DIM(a) \
875 do { \
876 extern FILE *asm_out_text_file; \
877 fprintf (asm_out_text_file, "%d;", a); \
878 } while (0)
879 #endif
880
881 #define PUT_SDB_TAG(a) \
882 do { \
883 extern FILE *asm_out_text_file; \
884 fprintf (asm_out_text_file, "\t.tag\t"); \
885 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
886 fputc (';', asm_out_text_file); \
887 } while (0)
888
889 /* For block start and end, we create labels, so that
890 later we can figure out where the correct offset is.
891 The normal .ent/.end serve well enough for functions,
892 so those are just commented out. */
893
894 #define PUT_SDB_BLOCK_START(LINE) \
895 do { \
896 extern FILE *asm_out_text_file; \
897 fprintf (asm_out_text_file, \
898 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
899 LOCAL_LABEL_PREFIX, \
900 sdb_label_count, \
901 (TARGET_GAS) ? "" : "#", \
902 LOCAL_LABEL_PREFIX, \
903 sdb_label_count, \
904 (LINE)); \
905 sdb_label_count++; \
906 } while (0)
907
908 #define PUT_SDB_BLOCK_END(LINE) \
909 do { \
910 extern FILE *asm_out_text_file; \
911 fprintf (asm_out_text_file, \
912 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
913 LOCAL_LABEL_PREFIX, \
914 sdb_label_count, \
915 (TARGET_GAS) ? "" : "#", \
916 LOCAL_LABEL_PREFIX, \
917 sdb_label_count, \
918 (LINE)); \
919 sdb_label_count++; \
920 } while (0)
921
922 #define PUT_SDB_FUNCTION_START(LINE)
923
924 #define PUT_SDB_FUNCTION_END(LINE) \
925 do { \
926 extern FILE *asm_out_text_file; \
927 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
928 } while (0)
929
930 #define PUT_SDB_EPILOGUE_END(NAME)
931
932 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
933 sprintf ((BUFFER), ".%dfake", (NUMBER));
934
935 /* Correct the offset of automatic variables and arguments. Note that
936 the MIPS debug format wants all automatic variables and arguments
937 to be in terms of the virtual frame pointer (stack pointer before
938 any adjustment in the function), while the MIPS 3.0 linker wants
939 the frame pointer to be the stack pointer after the initial
940 adjustment. */
941
942 #define DEBUGGER_AUTO_OFFSET(X) mips_debugger_offset (X, 0)
943 #define DEBUGGER_ARG_OFFSET(OFFSET, X) mips_debugger_offset (X, OFFSET)
944
945
946 /* Tell collect that the object format is ECOFF */
947 #ifndef OBJECT_FORMAT_ROSE
948 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
949 #define EXTENDED_COFF /* ECOFF, not normal coff */
950 #endif
951
952 #if 0 /* These definitions normally have no effect because
953 MIPS systems define USE_COLLECT2, so
954 assemble_constructor does nothing anyway. */
955
956 /* Don't use the default definitions, because we don't have gld.
957 Also, we don't want stabs when generating ECOFF output.
958 Instead we depend on collect to handle these. */
959
960 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
961 #define ASM_OUTPUT_DESTRUCTOR(file, name)
962
963 #endif /* 0 */
964 \f
965 /* Target machine storage layout */
966
967 /* Define in order to support both big and little endian float formats
968 in the same gcc binary. */
969 #define REAL_ARITHMETIC
970
971 /* Define this if most significant bit is lowest numbered
972 in instructions that operate on numbered bit-fields.
973 */
974 #define BITS_BIG_ENDIAN 0
975
976 /* Define this if most significant byte of a word is the lowest numbered. */
977 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
978
979 /* Define this if most significant word of a multiword number is the lowest. */
980 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
981
982 /* Define this to set the endianness to use in libgcc2.c, which can
983 not depend on target_flags. */
984 #if !defined(MIPSEL) && !defined(__MIPSEL__)
985 #define LIBGCC2_WORDS_BIG_ENDIAN 1
986 #else
987 #define LIBGCC2_WORDS_BIG_ENDIAN 0
988 #endif
989
990 /* Number of bits in an addressable storage unit */
991 #define BITS_PER_UNIT 8
992
993 /* Width in bits of a "word", which is the contents of a machine register.
994 Note that this is not necessarily the width of data type `int';
995 if using 16-bit ints on a 68000, this would still be 32.
996 But on a machine with 16-bit registers, this would be 16. */
997 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
998 #define MAX_BITS_PER_WORD 64
999
1000 /* Width of a word, in units (bytes). */
1001 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1002 #define MIN_UNITS_PER_WORD 4
1003
1004 /* For MIPS, width of a floating point register. */
1005 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1006
1007 /* A C expression for the size in bits of the type `int' on the
1008 target machine. If you don't define this, the default is one
1009 word. */
1010 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1011 #define MAX_INT_TYPE_SIZE 64
1012
1013 /* Tell the preprocessor the maximum size of wchar_t. */
1014 #ifndef MAX_WCHAR_TYPE_SIZE
1015 #ifndef WCHAR_TYPE_SIZE
1016 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1017 #endif
1018 #endif
1019
1020 /* A C expression for the size in bits of the type `short' on the
1021 target machine. If you don't define this, the default is half a
1022 word. (If this would be less than one storage unit, it is
1023 rounded up to one unit.) */
1024 #define SHORT_TYPE_SIZE 16
1025
1026 /* A C expression for the size in bits of the type `long' on the
1027 target machine. If you don't define this, the default is one
1028 word. */
1029 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1030 #define MAX_LONG_TYPE_SIZE 64
1031
1032 /* A C expression for the size in bits of the type `long long' on the
1033 target machine. If you don't define this, the default is two
1034 words. */
1035 #define LONG_LONG_TYPE_SIZE 64
1036
1037 /* A C expression for the size in bits of the type `char' on the
1038 target machine. If you don't define this, the default is one
1039 quarter of a word. (If this would be less than one storage unit,
1040 it is rounded up to one unit.) */
1041 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1042
1043 /* A C expression for the size in bits of the type `float' on the
1044 target machine. If you don't define this, the default is one
1045 word. */
1046 #define FLOAT_TYPE_SIZE 32
1047
1048 /* A C expression for the size in bits of the type `double' on the
1049 target machine. If you don't define this, the default is two
1050 words. */
1051 #define DOUBLE_TYPE_SIZE 64
1052
1053 /* A C expression for the size in bits of the type `long double' on
1054 the target machine. If you don't define this, the default is two
1055 words. */
1056 #define LONG_DOUBLE_TYPE_SIZE 64
1057
1058 /* Width in bits of a pointer.
1059 See also the macro `Pmode' defined below. */
1060 #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
1061
1062 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1063 #define POINTER_BOUNDARY (TARGET_LONG64 ? 64 : 32)
1064
1065 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1066 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1067
1068 /* Allocation boundary (in *bits*) for the code of a function. */
1069 #define FUNCTION_BOUNDARY 32
1070
1071 /* Alignment of field after `int : 0' in a structure. */
1072 #define EMPTY_FIELD_BOUNDARY (TARGET_LONG64 ? 64 : 32)
1073
1074 /* Every structure's size must be a multiple of this. */
1075 /* 8 is observed right on a DECstation and on riscos 4.02. */
1076 #define STRUCTURE_SIZE_BOUNDARY 8
1077
1078 /* There is no point aligning anything to a rounder boundary than this. */
1079 #define BIGGEST_ALIGNMENT 64
1080
1081 /* Biggest alignment any structure field can require in bits. */
1082 #define BIGGEST_FIELD_ALIGNMENT 64
1083
1084 /* Set this nonzero if move instructions will actually fail to work
1085 when given unaligned data. */
1086 #define STRICT_ALIGNMENT 1
1087
1088 /* Define this if you wish to imitate the way many other C compilers
1089 handle alignment of bitfields and the structures that contain
1090 them.
1091
1092 The behavior is that the type written for a bitfield (`int',
1093 `short', or other integer type) imposes an alignment for the
1094 entire structure, as if the structure really did contain an
1095 ordinary field of that type. In addition, the bitfield is placed
1096 within the structure so that it would fit within such a field,
1097 not crossing a boundary for it.
1098
1099 Thus, on most machines, a bitfield whose type is written as `int'
1100 would not cross a four-byte boundary, and would force four-byte
1101 alignment for the whole structure. (The alignment used may not
1102 be four bytes; it is controlled by the other alignment
1103 parameters.)
1104
1105 If the macro is defined, its definition should be a C expression;
1106 a nonzero value for the expression enables this behavior. */
1107
1108 #define PCC_BITFIELD_TYPE_MATTERS 1
1109
1110 /* If defined, a C expression to compute the alignment given to a
1111 constant that is being placed in memory. CONSTANT is the constant
1112 and ALIGN is the alignment that the object would ordinarily have.
1113 The value of this macro is used instead of that alignment to align
1114 the object.
1115
1116 If this macro is not defined, then ALIGN is used.
1117
1118 The typical use of this macro is to increase alignment for string
1119 constants to be word aligned so that `strcpy' calls that copy
1120 constants can be done inline. */
1121
1122 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1123 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1124 && (ALIGN) < BITS_PER_WORD \
1125 ? BITS_PER_WORD \
1126 : (ALIGN))
1127
1128 /* If defined, a C expression to compute the alignment for a static
1129 variable. TYPE is the data type, and ALIGN is the alignment that
1130 the object would ordinarily have. The value of this macro is used
1131 instead of that alignment to align the object.
1132
1133 If this macro is not defined, then ALIGN is used.
1134
1135 One use of this macro is to increase alignment of medium-size
1136 data to make it all fit in fewer cache lines. Another is to
1137 cause character arrays to be word-aligned so that `strcpy' calls
1138 that copy constants to character arrays can be done inline. */
1139
1140 #undef DATA_ALIGNMENT
1141 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1142 ((((ALIGN) < BITS_PER_WORD) \
1143 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1144 || TREE_CODE (TYPE) == UNION_TYPE \
1145 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1146
1147 /* Define this macro if an argument declared as `char' or `short' in a
1148 prototype should actually be passed as an `int'. In addition to
1149 avoiding errors in certain cases of mismatch, it also makes for
1150 better code on certain machines. */
1151
1152 #define PROMOTE_PROTOTYPES
1153
1154 /* Define if operations between registers always perform the operation
1155 on the full register even if a narrower mode is specified. */
1156 #define WORD_REGISTER_OPERATIONS
1157
1158 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1159 will either zero-extend or sign-extend. The value of this macro should
1160 be the code that says which one of the two operations is implicitly
1161 done, NIL if none. */
1162 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1163 \f
1164 /* Standard register usage. */
1165
1166 /* Number of actual hardware registers.
1167 The hardware registers are assigned numbers for the compiler
1168 from 0 to just below FIRST_PSEUDO_REGISTER.
1169 All registers that the compiler knows about must be given numbers,
1170 even those that are not normally considered general registers.
1171
1172 On the Mips, we have 32 integer registers, 32 floating point
1173 registers and the special registers hi, lo, hilo, fp status, and rap.
1174 The hilo register is only used in 64 bit mode. It represents a 64
1175 bit value stored as two 32 bit values in the hi and lo registers;
1176 this is the result of the mult instruction. rap is a pointer to the
1177 stack where the return address reg ($31) was stored. This is needed
1178 for C++ exception handling. */
1179
1180 #define FIRST_PSEUDO_REGISTER 69
1181
1182 /* 1 for registers that have pervasive standard uses
1183 and are not available for the register allocator.
1184
1185 On the MIPS, see conventions, page D-2 */
1186
1187 #define FIXED_REGISTERS \
1188 { \
1189 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1190 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1191 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1192 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1193 0, 0, 0, 1, 1 \
1194 }
1195
1196
1197 /* 1 for registers not available across function calls.
1198 These must include the FIXED_REGISTERS and also any
1199 registers that can be used without being saved.
1200 The latter must include the registers where values are returned
1201 and the register where structure-value addresses are passed.
1202 Aside from that, you can include as many other registers as you like. */
1203
1204 #define CALL_USED_REGISTERS \
1205 { \
1206 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1207 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1208 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1209 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1210 1, 1, 1, 1, 1 \
1211 }
1212
1213
1214 /* Internal macros to classify a register number as to whether it's a
1215 general purpose register, a floating point register, a
1216 multiply/divide register, or a status register. */
1217
1218 #define GP_REG_FIRST 0
1219 #define GP_REG_LAST 31
1220 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1221 #define GP_DBX_FIRST 0
1222
1223 #define FP_REG_FIRST 32
1224 #define FP_REG_LAST 63
1225 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1226 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1227
1228 #define MD_REG_FIRST 64
1229 #define MD_REG_LAST 66
1230 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1231
1232 #define ST_REG_FIRST 67
1233 #define ST_REG_LAST 67
1234 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1235
1236 #define RAP_REG_NUM 68
1237
1238 #define AT_REGNUM (GP_REG_FIRST + 1)
1239 #define HI_REGNUM (MD_REG_FIRST + 0)
1240 #define LO_REGNUM (MD_REG_FIRST + 1)
1241 #define HILO_REGNUM (MD_REG_FIRST + 2)
1242 #define FPSW_REGNUM ST_REG_FIRST
1243
1244 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1245 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1246 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1247 #define ST_REG_P(REGNO) ((REGNO) == ST_REG_FIRST)
1248
1249 /* Return number of consecutive hard regs needed starting at reg REGNO
1250 to hold something of mode MODE.
1251 This is ordinarily the length in words of a value of mode MODE
1252 but can be less for certain modes in special long registers.
1253
1254 On the MIPS, all general registers are one word long. Except on
1255 the R4000 with the FR bit set, the floating point uses register
1256 pairs, with the second register not being allocatable. */
1257
1258 #define HARD_REGNO_NREGS(REGNO, MODE) \
1259 (! FP_REG_P (REGNO) \
1260 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1261 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1262
1263 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1264 MODE. In 32 bit mode, require that DImode and DFmode be in even
1265 registers. For DImode, this makes some of the insns easier to
1266 write, since you don't have to worry about a DImode value in
1267 registers 3 & 4, producing a result in 4 & 5.
1268
1269 To make the code simpler HARD_REGNO_MODE_OK now just references an
1270 array built in override_options. Because machmodes.h is not yet
1271 included before this file is processed, the MODE bound can't be
1272 expressed here. */
1273
1274 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1275
1276 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1277 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1278
1279 /* Value is 1 if it is a good idea to tie two pseudo registers
1280 when one has mode MODE1 and one has mode MODE2.
1281 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1282 for any hard reg, then this must be 0 for correct output. */
1283 #define MODES_TIEABLE_P(MODE1, MODE2) \
1284 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1285 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1286 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1287 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1288
1289 /* MIPS pc is not overloaded on a register. */
1290 /* #define PC_REGNUM xx */
1291
1292 /* Register to use for pushing function arguments. */
1293 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1294
1295 /* Offset from the stack pointer to the first available location. */
1296 #define STACK_POINTER_OFFSET 0
1297
1298 /* Base register for access to local variables of the function. */
1299 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 30)
1300
1301 /* Value should be nonzero if functions must have frame pointers.
1302 Zero means the frame pointer need not be set up (and parms
1303 may be accessed via the stack pointer) in functions that seem suitable.
1304 This is computed in `reload', in reload1.c. */
1305 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1306
1307 /* Base register for access to arguments of the function. */
1308 #define ARG_POINTER_REGNUM GP_REG_FIRST
1309
1310 /* Fake register that holds the address on the stack of the
1311 current function's return address. */
1312 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1313
1314 /* Register in which static-chain is passed to a function. */
1315 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1316
1317 /* If the structure value address is passed in a register, then
1318 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1319 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1320
1321 /* If the structure value address is not passed in a register, define
1322 `STRUCT_VALUE' as an expression returning an RTX for the place
1323 where the address is passed. If it returns 0, the address is
1324 passed as an "invisible" first argument. */
1325 #define STRUCT_VALUE 0
1326
1327 /* Mips registers used in prologue/epilogue code when the stack frame
1328 is larger than 32K bytes. These registers must come from the
1329 scratch register set, and not used for passing and returning
1330 arguments and any other information used in the calling sequence
1331 (such as pic). Must start at 12, since t0/t3 are parameter passing
1332 registers in the 64 bit ABI. */
1333
1334 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1335 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1336
1337 /* Define this macro if it is as good or better to call a constant
1338 function address than to call an address kept in a register. */
1339 #define NO_FUNCTION_CSE 1
1340
1341 /* Define this macro if it is as good or better for a function to
1342 call itself with an explicit address than to call an address
1343 kept in a register. */
1344 #define NO_RECURSIVE_FUNCTION_CSE 1
1345
1346 /* The register number of the register used to address a table of
1347 static data addresses in memory. In some cases this register is
1348 defined by a processor's "application binary interface" (ABI).
1349 When this macro is defined, RTL is generated for this register
1350 once, as with the stack pointer and frame pointer registers. If
1351 this macro is not defined, it is up to the machine-dependent
1352 files to allocate such a register (if necessary). */
1353 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1354
1355 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1356
1357 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1358 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1359 isn't always called for static inline functions. */
1360 #define INIT_EXPANDERS embedded_pic_fnaddr_rtx = NULL;
1361 \f
1362 /* Define the classes of registers for register constraints in the
1363 machine description. Also define ranges of constants.
1364
1365 One of the classes must always be named ALL_REGS and include all hard regs.
1366 If there is more than one class, another class must be named NO_REGS
1367 and contain no registers.
1368
1369 The name GENERAL_REGS must be the name of a class (or an alias for
1370 another name such as ALL_REGS). This is the class of registers
1371 that is allowed by "g" or "r" in a register constraint.
1372 Also, registers outside this class are allocated only when
1373 instructions express preferences for them.
1374
1375 The classes must be numbered in nondecreasing order; that is,
1376 a larger-numbered class must never be contained completely
1377 in a smaller-numbered class.
1378
1379 For any two classes, it is very desirable that there be another
1380 class that represents their union. */
1381
1382 enum reg_class
1383 {
1384 NO_REGS, /* no registers in set */
1385 GR_REGS, /* integer registers */
1386 FP_REGS, /* floating point registers */
1387 HI_REG, /* hi register */
1388 LO_REG, /* lo register */
1389 HILO_REG, /* hilo register pair for 64 bit mode mult */
1390 MD_REGS, /* multiply/divide registers (hi/lo) */
1391 ST_REGS, /* status registers (fp status) */
1392 ALL_REGS, /* all registers */
1393 LIM_REG_CLASSES /* max value + 1 */
1394 };
1395
1396 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1397
1398 #define GENERAL_REGS GR_REGS
1399
1400 /* An initializer containing the names of the register classes as C
1401 string constants. These names are used in writing some of the
1402 debugging dumps. */
1403
1404 #define REG_CLASS_NAMES \
1405 { \
1406 "NO_REGS", \
1407 "GR_REGS", \
1408 "FP_REGS", \
1409 "HI_REG", \
1410 "LO_REG", \
1411 "HILO_REG", \
1412 "MD_REGS", \
1413 "ST_REGS", \
1414 "ALL_REGS" \
1415 }
1416
1417 /* An initializer containing the contents of the register classes,
1418 as integers which are bit masks. The Nth integer specifies the
1419 contents of class N. The way the integer MASK is interpreted is
1420 that register R is in the class if `MASK & (1 << R)' is 1.
1421
1422 When the machine has more than 32 registers, an integer does not
1423 suffice. Then the integers are replaced by sub-initializers,
1424 braced groupings containing several integers. Each
1425 sub-initializer must be suitable as an initializer for the type
1426 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1427
1428 #define REG_CLASS_CONTENTS \
1429 { \
1430 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1431 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1432 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1433 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1434 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1435 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1436 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1437 { 0x00000000, 0x00000000, 0x00000008 }, /* status registers */ \
1438 { 0xffffffff, 0xffffffff, 0x0000000f } /* all registers */ \
1439 }
1440
1441
1442 /* A C expression whose value is a register class containing hard
1443 register REGNO. In general there is more that one such class;
1444 choose a class which is "minimal", meaning that no smaller class
1445 also contains the register. */
1446
1447 extern enum reg_class mips_regno_to_class[];
1448
1449 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1450
1451 /* A macro whose definition is the name of the class to which a
1452 valid base register must belong. A base register is one used in
1453 an address which is the register value plus a displacement. */
1454
1455 #define BASE_REG_CLASS GR_REGS
1456
1457 /* A macro whose definition is the name of the class to which a
1458 valid index register must belong. An index register is one used
1459 in an address where its value is either multiplied by a scale
1460 factor or added to another register (as well as added to a
1461 displacement). */
1462
1463 #define INDEX_REG_CLASS NO_REGS
1464
1465
1466 /* REGISTER AND CONSTANT CLASSES */
1467
1468 /* Get reg_class from a letter such as appears in the machine
1469 description.
1470
1471 DEFINED REGISTER CLASSES:
1472
1473 'd' General (aka integer) registers
1474 'f' Floating point registers
1475 'h' Hi register
1476 'l' Lo register
1477 'x' Multiply/divide registers
1478 'a' HILO_REG
1479 'z' FP Status register
1480 'b' All registers */
1481
1482 extern enum reg_class mips_char_to_class[];
1483
1484 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1485
1486 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1487 string can be used to stand for particular ranges of immediate
1488 operands. This macro defines what the ranges are. C is the
1489 letter, and VALUE is a constant value. Return 1 if VALUE is
1490 in the range specified by C. */
1491
1492 /* For MIPS:
1493
1494 `I' is used for the range of constants an arithmetic insn can
1495 actually contain (16 bits signed integers).
1496
1497 `J' is used for the range which is just zero (ie, $r0).
1498
1499 `K' is used for the range of constants a logical insn can actually
1500 contain (16 bit zero-extended integers).
1501
1502 `L' is used for the range of constants that be loaded with lui
1503 (ie, the bottom 16 bits are zero).
1504
1505 `M' is used for the range of constants that take two words to load
1506 (ie, not matched by `I', `K', and `L').
1507
1508 `N' is used for negative 16 bit constants.
1509
1510 `O' is an exact power of 2 (not yet used in the md file).
1511
1512 `P' is used for positive 16 bit constants. */
1513
1514 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1515 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1516
1517 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1518 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1519 : (C) == 'J' ? ((VALUE) == 0) \
1520 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1521 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1522 && (((VALUE) & ~2147483647) == 0 \
1523 || ((VALUE) & ~2147483647) == ~2147483647)) \
1524 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1525 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1526 && (((VALUE) & 0x0000ffff) != 0 \
1527 || (((VALUE) & ~2147483647) != 0 \
1528 && ((VALUE) & ~2147483647) != ~2147483647))) \
1529 : (C) == 'N' ? (((VALUE) & ~0x0000ffff) == ~0x0000ffff) \
1530 : (C) == 'O' ? (exact_log2 (VALUE) >= 0) \
1531 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1532 : 0)
1533
1534 /* Similar, but for floating constants, and defining letters G and H.
1535 Here VALUE is the CONST_DOUBLE rtx itself. */
1536
1537 /* For Mips
1538
1539 'G' : Floating point 0 */
1540
1541 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1542 ((C) == 'G' \
1543 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1544
1545 /* Letters in the range `Q' through `U' may be defined in a
1546 machine-dependent fashion to stand for arbitrary operand types.
1547 The machine description macro `EXTRA_CONSTRAINT' is passed the
1548 operand as its first argument and the constraint letter as its
1549 second operand.
1550
1551 `Q' is for memory references which take more than 1 instruction.
1552 `R' is for memory references which take 1 word for the instruction.
1553 `S' is for references to extern items which are PIC for OSF/rose. */
1554
1555 #define EXTRA_CONSTRAINT(OP,CODE) \
1556 ((GET_CODE (OP) != MEM) ? FALSE \
1557 : ((CODE) == 'Q') ? !simple_memory_operand (OP, GET_MODE (OP)) \
1558 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1559 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1560 && HALF_PIC_ADDRESS_P (OP)) \
1561 : FALSE)
1562
1563 /* Given an rtx X being reloaded into a reg required to be
1564 in class CLASS, return the class of reg to actually use.
1565 In general this is just CLASS; but on some machines
1566 in some cases it is preferable to use a more restrictive class. */
1567
1568 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1569 ((CLASS) != ALL_REGS \
1570 ? (CLASS) \
1571 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1572 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1573 ? (TARGET_SOFT_FLOAT ? GR_REGS : FP_REGS) \
1574 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1575 || GET_MODE (X) == VOIDmode) \
1576 ? GR_REGS \
1577 : (CLASS))))
1578
1579 /* Certain machines have the property that some registers cannot be
1580 copied to some other registers without using memory. Define this
1581 macro on those machines to be a C expression that is non-zero if
1582 objects of mode MODE in registers of CLASS1 can only be copied to
1583 registers of class CLASS2 by storing a register of CLASS1 into
1584 memory and loading that memory location into a register of CLASS2.
1585
1586 Do not define this macro if its value would always be zero. */
1587
1588 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1589 ((!TARGET_DEBUG_H_MODE \
1590 && GET_MODE_CLASS (MODE) == MODE_INT \
1591 && ((CLASS1 == FP_REGS && CLASS2 == GR_REGS) \
1592 || (CLASS1 == GR_REGS && CLASS2 == FP_REGS))) \
1593 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1594 && ((CLASS1 == GR_REGS && CLASS2 == FP_REGS) \
1595 || (CLASS2 == GR_REGS && CLASS1 == FP_REGS))))
1596
1597 /* The HI and LO registers can only be reloaded via the general
1598 registers. */
1599
1600 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1601 mips_secondary_reload_class (CLASS, MODE, X, 1)
1602 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1603 mips_secondary_reload_class (CLASS, MODE, X, 0)
1604
1605 /* Not declared above, with the other functions, because enum
1606 reg_class is not declared yet. */
1607 extern enum reg_class mips_secondary_reload_class ();
1608
1609 /* Return the maximum number of consecutive registers
1610 needed to represent mode MODE in a register of class CLASS. */
1611
1612 #define CLASS_UNITS(mode, size) \
1613 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1614
1615 #define CLASS_MAX_NREGS(CLASS, MODE) \
1616 ((CLASS) == FP_REGS \
1617 ? (TARGET_FLOAT64 \
1618 ? CLASS_UNITS (MODE, 8) \
1619 : 2 * CLASS_UNITS (MODE, 8)) \
1620 : CLASS_UNITS (MODE, UNITS_PER_WORD))
1621
1622 /* If defined, this is a C expression whose value should be
1623 nonzero if the insn INSN has the effect of mysteriously
1624 clobbering the contents of hard register number REGNO. By
1625 "mysterious" we mean that the insn's RTL expression doesn't
1626 describe such an effect.
1627
1628 If this macro is not defined, it means that no insn clobbers
1629 registers mysteriously. This is the usual situation; all else
1630 being equal, it is best for the RTL expression to show all the
1631 activity. */
1632
1633 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
1634
1635 \f
1636 /* Stack layout; function entry, exit and calling. */
1637
1638 /* Don't enable support for the 64 bit ABI calling convention.
1639 Some embedded code depends on the old 64 bit calling convention. */
1640 #define ABI_64BIT 0
1641
1642 /* Define this if pushing a word on the stack
1643 makes the stack pointer a smaller address. */
1644 #define STACK_GROWS_DOWNWARD
1645
1646 /* Define this if the nominal address of the stack frame
1647 is at the high-address end of the local variables;
1648 that is, each additional local variable allocated
1649 goes at a more negative offset in the frame. */
1650 /* #define FRAME_GROWS_DOWNWARD */
1651
1652 /* Offset within stack frame to start allocating local variables at.
1653 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1654 first local allocated. Otherwise, it is the offset to the BEGINNING
1655 of the first local allocated. */
1656 #define STARTING_FRAME_OFFSET \
1657 (current_function_outgoing_args_size \
1658 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1659
1660 /* Offset from the stack pointer register to an item dynamically
1661 allocated on the stack, e.g., by `alloca'.
1662
1663 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1664 length of the outgoing arguments. The default is correct for most
1665 machines. See `function.c' for details.
1666
1667 The MIPS ABI states that functions which dynamically allocate the
1668 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
1669 we are trying to create a second frame pointer to the function, so
1670 allocate some stack space to make it happy.
1671
1672 However, the linker currently complains about linking any code that
1673 dynamically allocates stack space, and there seems to be a bug in
1674 STACK_DYNAMIC_OFFSET, so don't define this right now. */
1675
1676 #if 0
1677 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1678 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
1679 ? 4*UNITS_PER_WORD \
1680 : current_function_outgoing_args_size)
1681 #endif
1682
1683 /* The return address for the current frame is in r31 is this is a leaf
1684 function. Otherwise, it is on the stack. It is at a variable offset
1685 from sp/fp/ap, so we define a fake hard register rap which is a
1686 poiner to the return address on the stack. This always gets eliminated
1687 during reload to be either the frame pointer or the stack pointer plus
1688 an offset. */
1689
1690 /* ??? This definition fails for leaf functions. There is currently no
1691 general solution for this problem. */
1692
1693 /* ??? There appears to be no way to get the return address of any previous
1694 frame except by disassembling instructions in the prologue/epilogue.
1695 So currently we support only the current frame. */
1696
1697 #define RETURN_ADDR_RTX(count, frame) \
1698 ((count == 0) \
1699 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
1700 : (fatal ("RETURN_ADDR_RTX not supported for count != 0"), (rtx) 0))
1701
1702 /* Structure to be filled in by compute_frame_size with register
1703 save masks, and offsets for the current function. */
1704
1705 struct mips_frame_info
1706 {
1707 long total_size; /* # bytes that the entire frame takes up */
1708 long var_size; /* # bytes that variables take up */
1709 long args_size; /* # bytes that outgoing arguments take up */
1710 long extra_size; /* # bytes of extra gunk */
1711 int gp_reg_size; /* # bytes needed to store gp regs */
1712 int fp_reg_size; /* # bytes needed to store fp regs */
1713 long mask; /* mask of saved gp registers */
1714 long fmask; /* mask of saved fp registers */
1715 long gp_save_offset; /* offset from vfp to store gp registers */
1716 long fp_save_offset; /* offset from vfp to store fp registers */
1717 long gp_sp_offset; /* offset from new sp to store gp registers */
1718 long fp_sp_offset; /* offset from new sp to store fp registers */
1719 int initialized; /* != 0 if frame size already calculated */
1720 int num_gp; /* number of gp registers saved */
1721 int num_fp; /* number of fp registers saved */
1722 };
1723
1724 extern struct mips_frame_info current_frame_info;
1725
1726 /* Store in the variable DEPTH the initial difference between the
1727 frame pointer reg contents and the stack pointer reg contents,
1728 as of the start of the function body. This depends on the layout
1729 of the fixed parts of the stack frame and on how registers are saved. */
1730
1731 /* #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
1732 ((VAR) = compute_frame_size (get_frame_size ())) */
1733
1734 /* If defined, this macro specifies a table of register pairs used to
1735 eliminate unneeded registers that point into the stack frame. If
1736 it is not defined, the only elimination attempted by the compiler
1737 is to replace references to the frame pointer with references to
1738 the stack pointer.
1739
1740 The definition of this macro is a list of structure
1741 initializations, each of which specifies an original and
1742 replacement register.
1743
1744 On some machines, the position of the argument pointer is not
1745 known until the compilation is completed. In such a case, a
1746 separate hard register must be used for the argument pointer.
1747 This register can be eliminated by replacing it with either the
1748 frame pointer or the argument pointer, depending on whether or not
1749 the frame pointer has been eliminated.
1750
1751 In this case, you might specify:
1752 #define ELIMINABLE_REGS \
1753 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1754 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1755 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1756
1757 Note that the elimination of the argument pointer with the stack
1758 pointer is specified first since that is the preferred elimination. */
1759
1760 #define ELIMINABLE_REGS \
1761 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1762 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1763 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1764 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1765 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1766
1767 /* A C expression that returns non-zero if the compiler is allowed to
1768 try to replace register number FROM-REG with register number
1769 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
1770 defined, and will usually be the constant 1, since most of the
1771 cases preventing register elimination are things that the compiler
1772 already knows about. */
1773
1774 #define CAN_ELIMINATE(FROM, TO) \
1775 (!frame_pointer_needed \
1776 || ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1777 || ((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
1778 && (TO) == FRAME_POINTER_REGNUM))
1779
1780 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1781 specifies the initial difference between the specified pair of
1782 registers. This macro must be defined if `ELIMINABLE_REGS' is
1783 defined. */
1784
1785 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1786 { compute_frame_size (get_frame_size ()); \
1787 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1788 (OFFSET) = 0; \
1789 else if ((FROM) == ARG_POINTER_REGNUM \
1790 && ((TO) == FRAME_POINTER_REGNUM \
1791 || (TO) == STACK_POINTER_REGNUM)) \
1792 (OFFSET) = (current_frame_info.total_size \
1793 - (ABI_64BIT && mips_isa >= 3 \
1794 ? current_function_pretend_args_size \
1795 : 0)); \
1796 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
1797 && ((TO) == FRAME_POINTER_REGNUM \
1798 || (TO) == STACK_POINTER_REGNUM)) \
1799 (OFFSET) = current_frame_info.gp_sp_offset; \
1800 else \
1801 abort (); \
1802 }
1803
1804 /* If we generate an insn to push BYTES bytes,
1805 this says how many the stack pointer really advances by.
1806 On the vax, sp@- in a byte insn really pushes a word. */
1807
1808 /* #define PUSH_ROUNDING(BYTES) 0 */
1809
1810 /* If defined, the maximum amount of space required for outgoing
1811 arguments will be computed and placed into the variable
1812 `current_function_outgoing_args_size'. No space will be pushed
1813 onto the stack for each call; instead, the function prologue
1814 should increase the stack frame size by this amount.
1815
1816 It is not proper to define both `PUSH_ROUNDING' and
1817 `ACCUMULATE_OUTGOING_ARGS'. */
1818 #define ACCUMULATE_OUTGOING_ARGS
1819
1820 /* Offset from the argument pointer register to the first argument's
1821 address. On some machines it may depend on the data type of the
1822 function.
1823
1824 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
1825 the first argument's address.
1826
1827 On the MIPS, we must skip the first argument position if we are
1828 returning a structure or a union, to account for its address being
1829 passed in $4. However, at the current time, this produces a compiler
1830 that can't bootstrap, so comment it out for now. */
1831
1832 #if 0
1833 #define FIRST_PARM_OFFSET(FNDECL) \
1834 (FNDECL != 0 \
1835 && TREE_TYPE (FNDECL) != 0 \
1836 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
1837 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
1838 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
1839 ? UNITS_PER_WORD \
1840 : 0)
1841 #else
1842 #define FIRST_PARM_OFFSET(FNDECL) 0
1843 #endif
1844
1845 /* When a parameter is passed in a register, stack space is still
1846 allocated for it. For the MIPS, stack space must be allocated, cf
1847 Asm Lang Prog Guide page 7-8.
1848
1849 BEWARE that some space is also allocated for non existing arguments
1850 in register. In case an argument list is of form GF used registers
1851 are a0 (a2,a3), but we should push over a1... */
1852
1853 #define REG_PARM_STACK_SPACE(FNDECL) \
1854 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
1855
1856 /* Define this if it is the responsibility of the caller to
1857 allocate the area reserved for arguments passed in registers.
1858 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1859 of this macro is to determine whether the space is included in
1860 `current_function_outgoing_args_size'. */
1861 #define OUTGOING_REG_PARM_STACK_SPACE
1862
1863 /* Align stack frames on 64 bits (Double Word ). */
1864 #define STACK_BOUNDARY 64
1865
1866 /* Make sure 4 words are always allocated on the stack. */
1867
1868 #ifndef STACK_ARGS_ADJUST
1869 #define STACK_ARGS_ADJUST(SIZE) \
1870 { \
1871 if (SIZE.constant < 4 * UNITS_PER_WORD) \
1872 SIZE.constant = 4 * UNITS_PER_WORD; \
1873 }
1874 #endif
1875
1876 \f
1877 /* A C expression that should indicate the number of bytes of its
1878 own arguments that a function function pops on returning, or 0
1879 if the function pops no arguments and the caller must therefore
1880 pop them all after the function returns.
1881
1882 FUNDECL is the declaration node of the function (as a tree).
1883
1884 FUNTYPE is a C variable whose value is a tree node that
1885 describes the function in question. Normally it is a node of
1886 type `FUNCTION_TYPE' that describes the data type of the function.
1887 From this it is possible to obtain the data types of the value
1888 and arguments (if known).
1889
1890 When a call to a library function is being considered, FUNTYPE
1891 will contain an identifier node for the library function. Thus,
1892 if you need to distinguish among various library functions, you
1893 can do so by their names. Note that "library function" in this
1894 context means a function used to perform arithmetic, whose name
1895 is known specially in the compiler and was not mentioned in the
1896 C code being compiled.
1897
1898 STACK-SIZE is the number of bytes of arguments passed on the
1899 stack. If a variable number of bytes is passed, it is zero, and
1900 argument popping will always be the responsibility of the
1901 calling function. */
1902
1903 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1904
1905
1906 /* Symbolic macros for the registers used to return integer and floating
1907 point values. */
1908
1909 #define GP_RETURN (GP_REG_FIRST + 2)
1910 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1911
1912 /* Symbolic macros for the first/last argument registers. */
1913
1914 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1915 #define GP_ARG_LAST (GP_REG_FIRST + 7)
1916 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1917 #define FP_ARG_LAST (FP_REG_FIRST + 15)
1918
1919 #define MAX_ARGS_IN_REGISTERS 4
1920
1921 /* Define how to find the value returned by a library function
1922 assuming the value has mode MODE. */
1923
1924 #define LIBCALL_VALUE(MODE) \
1925 gen_rtx (REG, MODE, \
1926 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
1927 && (! TARGET_SINGLE_FLOAT \
1928 || GET_MODE_SIZE (MODE) <= 4)) \
1929 ? FP_RETURN \
1930 : GP_RETURN))
1931
1932 /* Define how to find the value returned by a function.
1933 VALTYPE is the data type of the value (as a tree).
1934 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1935 otherwise, FUNC is 0. */
1936
1937 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1938
1939
1940 /* 1 if N is a possible register number for a function value.
1941 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1942 Currently, R2 and F0 are only implemented here (C has no complex type) */
1943
1944 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
1945
1946 /* 1 if N is a possible register number for function argument passing. */
1947
1948 #define FUNCTION_ARG_REGNO_P(N) (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
1949 || ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST \
1950 && (0 == (N) % 2)))
1951
1952 /* A C expression which can inhibit the returning of certain function
1953 values in registers, based on the type of value. A nonzero value says
1954 to return the function value in memory, just as large structures are
1955 always returned. Here TYPE will be a C expression of type
1956 `tree', representing the data type of the value.
1957
1958 Note that values of mode `BLKmode' must be explicitly
1959 handled by this macro. Also, the option `-fpcc-struct-return'
1960 takes effect regardless of this macro. On most systems, it is
1961 possible to leave the macro undefined; this causes a default
1962 definition to be used, whose value is the constant 1 for BLKmode
1963 values, and 0 otherwise.
1964
1965 GCC normally converts 1 byte structures into chars, 2 byte
1966 structs into shorts, and 4 byte structs into ints, and returns
1967 them this way. Defining the following macro overrides this,
1968 to give us MIPS cc compatibility. */
1969
1970 #define RETURN_IN_MEMORY(TYPE) \
1971 (TYPE_MODE (TYPE) == BLKmode)
1972 \f
1973 /* A code distinguishing the floating point format of the target
1974 machine. There are three defined values: IEEE_FLOAT_FORMAT,
1975 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
1976
1977 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
1978
1979 \f
1980 /* Define a data type for recording info about an argument list
1981 during the scan of that argument list. This data type should
1982 hold all necessary information about the function itself
1983 and about the args processed so far, enough to enable macros
1984 such as FUNCTION_ARG to determine where the next arg should go.
1985 */
1986
1987 typedef struct mips_args {
1988 int gp_reg_found; /* whether a gp register was found yet */
1989 int arg_number; /* argument number */
1990 int arg_words; /* # total words the arguments take */
1991 int num_adjusts; /* number of adjustments made */
1992 /* Adjustments made to args pass in regs. */
1993 /* ??? The size is doubled to work around a
1994 bug in the code that sets the adjustments
1995 in function_arg. */
1996 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
1997 } CUMULATIVE_ARGS;
1998
1999 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2000 for a call to a function whose data type is FNTYPE.
2001 For a library call, FNTYPE is 0.
2002
2003 */
2004
2005 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
2006 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2007
2008 /* Update the data in CUM to advance over an argument
2009 of mode MODE and data type TYPE.
2010 (TYPE is null for libcalls where that information may not be available.) */
2011
2012 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2013 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2014
2015 /* Determine where to put an argument to a function.
2016 Value is zero to push the argument on the stack,
2017 or a hard register in which to store the argument.
2018
2019 MODE is the argument's machine mode.
2020 TYPE is the data type of the argument (as a tree).
2021 This is null for libcalls where that information may
2022 not be available.
2023 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2024 the preceding args and about the function being called.
2025 NAMED is nonzero if this argument is a named parameter
2026 (otherwise it is an extra parameter matching an ellipsis). */
2027
2028 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2029 function_arg( &CUM, MODE, TYPE, NAMED)
2030
2031 /* For an arg passed partly in registers and partly in memory,
2032 this is the number of registers used.
2033 For args passed entirely in registers or entirely in memory, zero. */
2034
2035 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2036 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2037
2038 /* If defined, a C expression that gives the alignment boundary, in
2039 bits, of an argument with the specified mode and type. If it is
2040 not defined, `PARM_BOUNDARY' is used for all arguments. */
2041
2042 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2043 (((TYPE) != 0) \
2044 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2045 ? PARM_BOUNDARY \
2046 : TYPE_ALIGN(TYPE)) \
2047 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2048 ? PARM_BOUNDARY \
2049 : GET_MODE_ALIGNMENT(MODE)))
2050
2051 \f
2052 /* This macro generates the assembly code for function entry.
2053 FILE is a stdio stream to output the code to.
2054 SIZE is an int: how many units of temporary storage to allocate.
2055 Refer to the array `regs_ever_live' to determine which registers
2056 to save; `regs_ever_live[I]' is nonzero if register number I
2057 is ever used in the function. This macro is responsible for
2058 knowing which registers should not be saved even if used. */
2059
2060 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2061
2062 /* This macro generates the assembly code for function exit,
2063 on machines that need it. If FUNCTION_EPILOGUE is not defined
2064 then individual return instructions are generated for each
2065 return statement. Args are same as for FUNCTION_PROLOGUE. */
2066
2067 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2068
2069 /* Define the number of delay slots needed for the function epilogue.
2070
2071 On the mips, we need a slot if either no stack has been allocated,
2072 or the only register saved is the return register. */
2073
2074 #define DELAY_SLOTS_FOR_EPILOGUE mips_epilogue_delay_slots ()
2075
2076 /* Define whether INSN can be placed in delay slot N for the epilogue.
2077 No references to the stack must be made, since on the MIPS, the
2078 delay slot is done after the stack has been cleaned up. */
2079
2080 #define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN,N) \
2081 (get_attr_dslot (INSN) == DSLOT_NO \
2082 && get_attr_length (INSN) == 1 \
2083 && ! epilogue_reg_mentioned_p (PATTERN (INSN)))
2084
2085 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2086
2087 #define MUST_SAVE_REGISTER(regno) \
2088 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2089 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
2090 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2091
2092 /* ALIGN FRAMES on double word boundaries */
2093
2094 #define MIPS_STACK_ALIGN(LOC) (((LOC)+7) & ~7)
2095
2096 \f
2097 /* Output assembler code to FILE to increment profiler label # LABELNO
2098 for profiling a function entry. */
2099
2100 #define FUNCTION_PROFILER(FILE, LABELNO) \
2101 { \
2102 fprintf (FILE, "\t.set\tnoreorder\n"); \
2103 fprintf (FILE, "\t.set\tnoat\n"); \
2104 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2105 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2106 fprintf (FILE, "\tjal\t_mcount\n"); \
2107 fprintf (FILE, \
2108 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2109 TARGET_64BIT ? "dsubu" : "subu", \
2110 reg_names[STACK_POINTER_REGNUM], \
2111 reg_names[STACK_POINTER_REGNUM], \
2112 TARGET_LONG64 ? 16 : 8); \
2113 fprintf (FILE, "\t.set\treorder\n"); \
2114 fprintf (FILE, "\t.set\tat\n"); \
2115 }
2116
2117 /* Define this macro if the code for function profiling should come
2118 before the function prologue. Normally, the profiling code comes
2119 after. */
2120
2121 /* #define PROFILE_BEFORE_PROLOGUE */
2122
2123 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2124 the stack pointer does not matter. The value is tested only in
2125 functions that have frame pointers.
2126 No definition is equivalent to always zero. */
2127
2128 #define EXIT_IGNORE_STACK 1
2129
2130 \f
2131 /* A C statement to output, on the stream FILE, assembler code for a
2132 block of data that contains the constant parts of a trampoline.
2133 This code should not include a label--the label is taken care of
2134 automatically. */
2135
2136 #define TRAMPOLINE_TEMPLATE(STREAM) \
2137 { \
2138 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2139 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2140 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2141 if (TARGET_LONG64) \
2142 { \
2143 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2144 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2145 } \
2146 else \
2147 { \
2148 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2149 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2150 } \
2151 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2152 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2153 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2154 if (TARGET_LONG64) \
2155 { \
2156 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2157 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2158 } \
2159 else \
2160 { \
2161 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2162 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2163 } \
2164 }
2165
2166 /* A C expression for the size in bytes of the trampoline, as an
2167 integer. */
2168
2169 #define TRAMPOLINE_SIZE (32 + (TARGET_LONG64 ? 16 : 8))
2170
2171 /* Alignment required for trampolines, in bits. */
2172
2173 #define TRAMPOLINE_ALIGNMENT (TARGET_LONG64 ? 64 : 32)
2174
2175 /* A C statement to initialize the variable parts of a trampoline.
2176 ADDR is an RTX for the address of the trampoline; FNADDR is an
2177 RTX for the address of the nested function; STATIC_CHAIN is an
2178 RTX for the static chain value that should be passed to the
2179 function when it is called. */
2180
2181 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2182 { \
2183 rtx addr = ADDR; \
2184 if (TARGET_LONG64) \
2185 { \
2186 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2187 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2188 } \
2189 else \
2190 { \
2191 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2192 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2193 } \
2194 \
2195 /* Flush the instruction cache. */ \
2196 /* ??? Should check the return value for errors. */ \
2197 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "cacheflush"), \
2198 0, VOIDmode, 3, addr, Pmode, \
2199 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2200 GEN_INT (1), TYPE_MODE (integer_type_node)); \
2201 }
2202 \f
2203 /* Addressing modes, and classification of registers for them. */
2204
2205 /* #define HAVE_POST_INCREMENT */
2206 /* #define HAVE_POST_DECREMENT */
2207
2208 /* #define HAVE_PRE_DECREMENT */
2209 /* #define HAVE_PRE_INCREMENT */
2210
2211 /* These assume that REGNO is a hard or pseudo reg number.
2212 They give nonzero only if REGNO is a hard reg of the suitable class
2213 or a pseudo reg currently allocated to a suitable hard reg.
2214 These definitions are NOT overridden anywhere. */
2215
2216 #define GP_REG_OR_PSEUDO_STRICT_P(regno) \
2217 GP_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno])
2218
2219 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno) \
2220 (((regno) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (regno)))
2221
2222 #define REGNO_OK_FOR_INDEX_P(regno) 0
2223 #define REGNO_OK_FOR_BASE_P(regno) GP_REG_OR_PSEUDO_STRICT_P (regno)
2224
2225 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2226 and check its validity for a certain class.
2227 We have two alternate definitions for each of them.
2228 The usual definition accepts all pseudo regs; the other rejects them all.
2229 The symbol REG_OK_STRICT causes the latter definition to be used.
2230
2231 Most source files want to accept pseudo regs in the hope that
2232 they will get allocated to the class that the insn wants them to be in.
2233 Some source files that are used after register allocation
2234 need to be strict. */
2235
2236 #ifndef REG_OK_STRICT
2237
2238 #define REG_OK_STRICT_P 0
2239 #define REG_OK_FOR_INDEX_P(X) 0
2240 #define REG_OK_FOR_BASE_P(X) GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X))
2241
2242 #else
2243
2244 #define REG_OK_STRICT_P 1
2245 #define REG_OK_FOR_INDEX_P(X) 0
2246 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2247
2248 #endif
2249
2250 \f
2251 /* Maximum number of registers that can appear in a valid memory address. */
2252
2253 #define MAX_REGS_PER_ADDRESS 1
2254
2255 /* A C compound statement with a conditional `goto LABEL;' executed
2256 if X (an RTX) is a legitimate memory address on the target
2257 machine for a memory operand of mode MODE.
2258
2259 It usually pays to define several simpler macros to serve as
2260 subroutines for this one. Otherwise it may be too complicated
2261 to understand.
2262
2263 This macro must exist in two variants: a strict variant and a
2264 non-strict one. The strict variant is used in the reload pass.
2265 It must be defined so that any pseudo-register that has not been
2266 allocated a hard register is considered a memory reference. In
2267 contexts where some kind of register is required, a
2268 pseudo-register with no hard register must be rejected.
2269
2270 The non-strict variant is used in other passes. It must be
2271 defined to accept all pseudo-registers in every context where
2272 some kind of register is required.
2273
2274 Compiler source files that want to use the strict variant of
2275 this macro define the macro `REG_OK_STRICT'. You should use an
2276 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2277 in that case and the non-strict variant otherwise.
2278
2279 Typically among the subroutines used to define
2280 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2281 acceptable registers for various purposes (one for base
2282 registers, one for index registers, and so on). Then only these
2283 subroutine macros need have two variants; the higher levels of
2284 macros may be the same whether strict or not.
2285
2286 Normally, constant addresses which are the sum of a `symbol_ref'
2287 and an integer are stored inside a `const' RTX to mark them as
2288 constant. Therefore, there is no need to recognize such sums
2289 specifically as legitimate addresses. Normally you would simply
2290 recognize any `const' as legitimate.
2291
2292 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2293 constant sums that are not marked with `const'. It assumes
2294 that a naked `plus' indicates indexing. If so, then you *must*
2295 reject such naked constant sums as illegitimate addresses, so
2296 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2297
2298 On some machines, whether a symbolic address is legitimate
2299 depends on the section that the address refers to. On these
2300 machines, define the macro `ENCODE_SECTION_INFO' to store the
2301 information into the `symbol_ref', and then check for it here.
2302 When you see a `const', you will have to look inside it to find
2303 the `symbol_ref' in order to determine the section. */
2304
2305 #if 1
2306 #define GO_PRINTF(x) trace(x)
2307 #define GO_PRINTF2(x,y) trace(x,y)
2308 #define GO_DEBUG_RTX(x) debug_rtx(x)
2309
2310 #else
2311 #define GO_PRINTF(x)
2312 #define GO_PRINTF2(x,y)
2313 #define GO_DEBUG_RTX(x)
2314 #endif
2315
2316 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2317 { \
2318 register rtx xinsn = (X); \
2319 \
2320 if (TARGET_DEBUG_B_MODE) \
2321 { \
2322 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2323 (REG_OK_STRICT_P) ? "" : "not "); \
2324 GO_DEBUG_RTX (xinsn); \
2325 } \
2326 \
2327 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
2328 goto ADDR; \
2329 \
2330 if (CONSTANT_ADDRESS_P (xinsn)) \
2331 goto ADDR; \
2332 \
2333 if (GET_CODE (xinsn) == PLUS) \
2334 { \
2335 register rtx xplus0 = XEXP (xinsn, 0); \
2336 register rtx xplus1 = XEXP (xinsn, 1); \
2337 register enum rtx_code code0 = GET_CODE (xplus0); \
2338 register enum rtx_code code1 = GET_CODE (xplus1); \
2339 \
2340 if (code0 != REG && code1 == REG) \
2341 { \
2342 xplus0 = XEXP (xinsn, 1); \
2343 xplus1 = XEXP (xinsn, 0); \
2344 code0 = GET_CODE (xplus0); \
2345 code1 = GET_CODE (xplus1); \
2346 } \
2347 \
2348 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0)) \
2349 { \
2350 if (code1 == CONST_INT \
2351 && INTVAL (xplus1) >= -32768 \
2352 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2353 goto ADDR; \
2354 \
2355 /* For some code sequences, you actually get better code by \
2356 pretending that the MIPS supports an address mode of a \
2357 constant address + a register, even though the real \
2358 machine doesn't support it. This is because the \
2359 assembler can use $r1 to load just the high 16 bits, add \
2360 in the register, and fold the low 16 bits into the memory \
2361 reference, whereas the compiler generates a 4 instruction \
2362 sequence. On the other hand, CSE is not as effective. \
2363 It would be a win to generate the lui directly, but the \
2364 MIPS assembler does not have syntax to generate the \
2365 appropriate relocation. */ \
2366 \
2367 /* Also accept CONST_INT addresses here, so no else. */ \
2368 /* Reject combining an embedded PIC text segment reference \
2369 with a register. That requires an additional \
2370 instruction. */ \
2371 /* ??? Reject combining an address with a register for the MIPS \
2372 64 bit ABI, because the SGI assembler can not handle this. */ \
2373 if (!TARGET_DEBUG_A_MODE \
2374 && ! ABI_64BIT \
2375 && CONSTANT_ADDRESS_P (xplus1) \
2376 && (!TARGET_EMBEDDED_PIC \
2377 || code1 != CONST \
2378 || GET_CODE (XEXP (xplus1, 0)) != MINUS)) \
2379 goto ADDR; \
2380 } \
2381 } \
2382 \
2383 if (TARGET_DEBUG_B_MODE) \
2384 GO_PRINTF ("Not a legitimate address\n"); \
2385 }
2386
2387
2388 /* A C expression that is 1 if the RTX X is a constant which is a
2389 valid address. This is defined to be the same as `CONSTANT_P (X)',
2390 but rejecting CONST_DOUBLE. */
2391 /* When pic, we must reject addresses of the form symbol+large int.
2392 This is because an instruction `sw $4,s+70000' needs to be converted
2393 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2394 assembler would use $at as a temp to load in the large offset. In this
2395 case $at is already in use. We convert such problem addresses to
2396 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2397 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2398 #define CONSTANT_ADDRESS_P(X) \
2399 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2400 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2401 || (GET_CODE (X) == CONST \
2402 && ! (flag_pic && pic_address_needs_scratch (X)) \
2403 && ! ABI_64BIT)) \
2404 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2405
2406 /* Define this, so that when PIC, reload won't try to reload invalid
2407 addresses which require two reload registers. */
2408
2409 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2410
2411 /* Nonzero if the constant value X is a legitimate general operand.
2412 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2413
2414 At present, GAS doesn't understand li.[sd], so don't allow it
2415 to be generated at present. Also, the MIPS assembler does not
2416 grok li.d Infinity. */
2417
2418 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2419 #define LEGITIMATE_CONSTANT_P(X) \
2420 ((GET_CODE (X) != CONST_DOUBLE \
2421 || mips_const_double_ok (X, GET_MODE (X))) \
2422 && ! (GET_CODE (X) == CONST && ABI_64BIT))
2423
2424 /* A C compound statement that attempts to replace X with a valid
2425 memory address for an operand of mode MODE. WIN will be a C
2426 statement label elsewhere in the code; the macro definition may
2427 use
2428
2429 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2430
2431 to avoid further processing if the address has become legitimate.
2432
2433 X will always be the result of a call to `break_out_memory_refs',
2434 and OLDX will be the operand that was given to that function to
2435 produce X.
2436
2437 The code generated by this macro should not alter the
2438 substructure of X. If it transforms X into a more legitimate
2439 form, it should assign X (which will always be a C variable) a
2440 new value.
2441
2442 It is not necessary for this macro to come up with a legitimate
2443 address. The compiler has standard ways of doing so in all
2444 cases. In fact, it is safe for this macro to do nothing. But
2445 often a machine-dependent strategy can generate better code.
2446
2447 For the MIPS, transform:
2448
2449 memory(X + <large int>)
2450
2451 into:
2452
2453 Y = <large int> & ~0x7fff;
2454 Z = X + Y
2455 memory (Z + (<large int> & 0x7fff));
2456
2457 This is for CSE to find several similar references, and only use one Z.
2458
2459 When PIC, convert addresses of the form memory (symbol+large int) to
2460 memory (reg+large int). */
2461
2462
2463 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2464 { \
2465 register rtx xinsn = (X); \
2466 \
2467 if (TARGET_DEBUG_B_MODE) \
2468 { \
2469 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2470 GO_DEBUG_RTX (xinsn); \
2471 } \
2472 \
2473 if (GET_CODE (xinsn) == CONST \
2474 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2475 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2476 || ABI_64BIT)) \
2477 { \
2478 rtx ptr_reg = gen_reg_rtx (Pmode); \
2479 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2480 \
2481 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2482 \
2483 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
2484 if (SMALL_INT (constant)) \
2485 goto WIN; \
2486 /* Otherwise we fall through so the code below will fix the \
2487 constant. */ \
2488 xinsn = X; \
2489 } \
2490 \
2491 if (GET_CODE (xinsn) == PLUS) \
2492 { \
2493 register rtx xplus0 = XEXP (xinsn, 0); \
2494 register rtx xplus1 = XEXP (xinsn, 1); \
2495 register enum rtx_code code0 = GET_CODE (xplus0); \
2496 register enum rtx_code code1 = GET_CODE (xplus1); \
2497 \
2498 if (code0 != REG && code1 == REG) \
2499 { \
2500 xplus0 = XEXP (xinsn, 1); \
2501 xplus1 = XEXP (xinsn, 0); \
2502 code0 = GET_CODE (xplus0); \
2503 code1 = GET_CODE (xplus1); \
2504 } \
2505 \
2506 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
2507 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2508 { \
2509 rtx int_reg = gen_reg_rtx (Pmode); \
2510 rtx ptr_reg = gen_reg_rtx (Pmode); \
2511 \
2512 emit_move_insn (int_reg, \
2513 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2514 \
2515 emit_insn (gen_rtx (SET, VOIDmode, \
2516 ptr_reg, \
2517 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
2518 \
2519 X = gen_rtx (PLUS, Pmode, ptr_reg, \
2520 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
2521 goto WIN; \
2522 } \
2523 } \
2524 \
2525 if (TARGET_DEBUG_B_MODE) \
2526 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
2527 }
2528
2529
2530 /* A C statement or compound statement with a conditional `goto
2531 LABEL;' executed if memory address X (an RTX) can have different
2532 meanings depending on the machine mode of the memory reference it
2533 is used for.
2534
2535 Autoincrement and autodecrement addresses typically have
2536 mode-dependent effects because the amount of the increment or
2537 decrement is the size of the operand being addressed. Some
2538 machines have other mode-dependent addresses. Many RISC machines
2539 have no mode-dependent addresses.
2540
2541 You may assume that ADDR is a valid address for the machine. */
2542
2543 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2544
2545
2546 /* Define this macro if references to a symbol must be treated
2547 differently depending on something about the variable or
2548 function named by the symbol (such as what section it is in).
2549
2550 The macro definition, if any, is executed immediately after the
2551 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
2552 The value of the rtl will be a `mem' whose address is a
2553 `symbol_ref'.
2554
2555 The usual thing for this macro to do is to a flag in the
2556 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
2557 name string in the `symbol_ref' (if one bit is not enough
2558 information).
2559
2560 The best way to modify the name string is by adding text to the
2561 beginning, with suitable punctuation to prevent any ambiguity.
2562 Allocate the new name in `saveable_obstack'. You will have to
2563 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
2564 and output the name accordingly.
2565
2566 You can also check the information stored in the `symbol_ref' in
2567 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
2568 `PRINT_OPERAND_ADDRESS'. */
2569
2570 #define ENCODE_SECTION_INFO(DECL) \
2571 do \
2572 { \
2573 if (TARGET_EMBEDDED_PIC) \
2574 { \
2575 if (TREE_CODE (DECL) == VAR_DECL) \
2576 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2577 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
2578 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
2579 else if (TREE_CODE (DECL) == STRING_CST \
2580 && ! flag_writable_strings) \
2581 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
2582 else \
2583 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
2584 } \
2585 \
2586 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL) \
2587 { \
2588 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
2589 \
2590 if (size > 0 && size <= mips_section_threshold) \
2591 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2592 } \
2593 \
2594 else if (HALF_PIC_P ()) \
2595 HALF_PIC_ENCODE (DECL); \
2596 } \
2597 while (0)
2598
2599 \f
2600 /* Specify the machine mode that this machine uses
2601 for the index in the tablejump instruction. */
2602 #define CASE_VECTOR_MODE (TARGET_LONG64 ? DImode : SImode)
2603
2604 /* Define this if the tablejump instruction expects the table
2605 to contain offsets from the address of the table.
2606 Do not define this if the table should contain absolute addresses. */
2607 /* #define CASE_VECTOR_PC_RELATIVE */
2608
2609 /* Specify the tree operation to be used to convert reals to integers. */
2610 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2611
2612 /* This is the kind of divide that is easiest to do in the general case. */
2613 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2614
2615 /* Define this as 1 if `char' should by default be signed; else as 0. */
2616 #ifndef DEFAULT_SIGNED_CHAR
2617 #define DEFAULT_SIGNED_CHAR 1
2618 #endif
2619
2620 /* Max number of bytes we can move from memory to memory
2621 in one reasonably fast instruction. */
2622 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2623 #define MAX_MOVE_MAX 8
2624
2625 /* Define this macro as a C expression which is nonzero if
2626 accessing less than a word of memory (i.e. a `char' or a
2627 `short') is no faster than accessing a word of memory, i.e., if
2628 such access require more than one instruction or if there is no
2629 difference in cost between byte and (aligned) word loads.
2630
2631 On RISC machines, it tends to generate better code to define
2632 this as 1, since it avoids making a QI or HI mode register. */
2633 #define SLOW_BYTE_ACCESS 1
2634
2635 /* We assume that the store-condition-codes instructions store 0 for false
2636 and some other value for true. This is the value stored for true. */
2637
2638 #define STORE_FLAG_VALUE 1
2639
2640 /* Define this if zero-extension is slow (more than one real instruction). */
2641 #define SLOW_ZERO_EXTEND
2642
2643 /* Define this to be nonzero if shift instructions ignore all but the low-order
2644 few bits. */
2645 #define SHIFT_COUNT_TRUNCATED 1
2646
2647 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2648 is done just by pretending it is already truncated. */
2649 /* In 64 bit mode, 32 bit instructions require that register values be properly
2650 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
2651 converts a value >32 bits to a value <32 bits. */
2652 /* ??? This results in inefficient code for 64 bit to 32 conversions.
2653 Something needs to be done about this. Perhaps not use any 32 bit
2654 instructions? Perhaps use PROMOTE_MODE? */
2655 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2656 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2657
2658 /* Define this macro to control use of the character `$' in
2659 identifier names. The value should be 0, 1, or 2. 0 means `$'
2660 is not allowed by default; 1 means it is allowed by default if
2661 `-traditional' is used; 2 means it is allowed by default provided
2662 `-ansi' is not used. 1 is the default; there is no need to
2663 define this macro in that case. */
2664
2665 #ifndef DOLLARS_IN_IDENTIFIERS
2666 #define DOLLARS_IN_IDENTIFIERS 1
2667 #endif
2668
2669 /* Specify the machine mode that pointers have.
2670 After generation of rtl, the compiler makes no further distinction
2671 between pointers and any other objects of this machine mode. */
2672
2673 #define Pmode (TARGET_LONG64 ? DImode : SImode)
2674
2675 /* A function address in a call instruction
2676 is a word address (for indexing purposes)
2677 so give the MEM rtx a words's mode. */
2678
2679 #define FUNCTION_MODE (TARGET_LONG64 ? DImode : SImode)
2680
2681 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
2682 memset, instead of the BSD functions bcopy and bzero. */
2683
2684 #if defined(MIPS_SYSV) || defined(OSF_OS)
2685 #define TARGET_MEM_FUNCTIONS
2686 #endif
2687
2688 \f
2689 /* A part of a C `switch' statement that describes the relative
2690 costs of constant RTL expressions. It must contain `case'
2691 labels for expression codes `const_int', `const', `symbol_ref',
2692 `label_ref' and `const_double'. Each case must ultimately reach
2693 a `return' statement to return the relative cost of the use of
2694 that kind of constant value in an expression. The cost may
2695 depend on the precise value of the constant, which is available
2696 for examination in X.
2697
2698 CODE is the expression code--redundant, since it can be obtained
2699 with `GET_CODE (X)'. */
2700
2701 #define CONST_COSTS(X,CODE,OUTER_CODE) \
2702 case CONST_INT: \
2703 /* Always return 0, since we don't have different sized \
2704 instructions, hence different costs according to Richard \
2705 Kenner */ \
2706 return 0; \
2707 \
2708 case LABEL_REF: \
2709 return COSTS_N_INSNS (2); \
2710 \
2711 case CONST: \
2712 { \
2713 rtx offset = const0_rtx; \
2714 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
2715 \
2716 if (GET_CODE (symref) == LABEL_REF) \
2717 return COSTS_N_INSNS (2); \
2718 \
2719 if (GET_CODE (symref) != SYMBOL_REF) \
2720 return COSTS_N_INSNS (4); \
2721 \
2722 /* let's be paranoid.... */ \
2723 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
2724 return COSTS_N_INSNS (2); \
2725 \
2726 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
2727 } \
2728 \
2729 case SYMBOL_REF: \
2730 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
2731 \
2732 case CONST_DOUBLE: \
2733 { \
2734 rtx high, low; \
2735 split_double (X, &high, &low); \
2736 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
2737 || low == CONST0_RTX (GET_MODE (low))) \
2738 ? 2 : 4); \
2739 }
2740
2741 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2742 This can be used, for example, to indicate how costly a multiply
2743 instruction is. In writing this macro, you can use the construct
2744 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
2745
2746 This macro is optional; do not define it if the default cost
2747 assumptions are adequate for the target machine.
2748
2749 If -mdebugd is used, change the multiply cost to 2, so multiply by
2750 a constant isn't converted to a series of shifts. This helps
2751 strength reduction, and also makes it easier to identify what the
2752 compiler is doing. */
2753
2754 /* ??? Fix this to be right for the R8000. */
2755 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2756 case MEM: \
2757 { \
2758 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
2759 if (simple_memory_operand (X, GET_MODE (X))) \
2760 return COSTS_N_INSNS (num_words); \
2761 \
2762 return COSTS_N_INSNS (2*num_words); \
2763 } \
2764 \
2765 case FFS: \
2766 return COSTS_N_INSNS (6); \
2767 \
2768 case NOT: \
2769 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
2770 \
2771 case AND: \
2772 case IOR: \
2773 case XOR: \
2774 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
2775 return COSTS_N_INSNS (2); \
2776 \
2777 return COSTS_N_INSNS (1); \
2778 \
2779 case ASHIFT: \
2780 case ASHIFTRT: \
2781 case LSHIFTRT: \
2782 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
2783 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
2784 \
2785 return COSTS_N_INSNS (1); \
2786 \
2787 case ABS: \
2788 { \
2789 enum machine_mode xmode = GET_MODE (X); \
2790 if (xmode == SFmode || xmode == DFmode) \
2791 return COSTS_N_INSNS (1); \
2792 \
2793 return COSTS_N_INSNS (4); \
2794 } \
2795 \
2796 case PLUS: \
2797 case MINUS: \
2798 { \
2799 enum machine_mode xmode = GET_MODE (X); \
2800 if (xmode == SFmode || xmode == DFmode) \
2801 { \
2802 if (mips_cpu == PROCESSOR_R3000) \
2803 return COSTS_N_INSNS (2); \
2804 else if (mips_cpu == PROCESSOR_R6000) \
2805 return COSTS_N_INSNS (3); \
2806 else \
2807 return COSTS_N_INSNS (6); \
2808 } \
2809 \
2810 if (xmode == DImode && !TARGET_64BIT) \
2811 return COSTS_N_INSNS (4); \
2812 \
2813 return COSTS_N_INSNS (1); \
2814 } \
2815 \
2816 case NEG: \
2817 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 4 : 1); \
2818 \
2819 case MULT: \
2820 { \
2821 enum machine_mode xmode = GET_MODE (X); \
2822 if (xmode == SFmode) \
2823 { \
2824 if (mips_cpu == PROCESSOR_R3000) \
2825 return COSTS_N_INSNS (4); \
2826 else if (mips_cpu == PROCESSOR_R6000) \
2827 return COSTS_N_INSNS (5); \
2828 else \
2829 return COSTS_N_INSNS (7); \
2830 } \
2831 \
2832 if (xmode == DFmode) \
2833 { \
2834 if (mips_cpu == PROCESSOR_R3000) \
2835 return COSTS_N_INSNS (5); \
2836 else if (mips_cpu == PROCESSOR_R6000) \
2837 return COSTS_N_INSNS (6); \
2838 else \
2839 return COSTS_N_INSNS (8); \
2840 } \
2841 \
2842 if (mips_cpu == PROCESSOR_R3000) \
2843 return COSTS_N_INSNS (12); \
2844 else if (mips_cpu == PROCESSOR_R6000) \
2845 return COSTS_N_INSNS (17); \
2846 else \
2847 return COSTS_N_INSNS (10); \
2848 } \
2849 \
2850 case DIV: \
2851 case MOD: \
2852 { \
2853 enum machine_mode xmode = GET_MODE (X); \
2854 if (xmode == SFmode) \
2855 { \
2856 if (mips_cpu == PROCESSOR_R3000) \
2857 return COSTS_N_INSNS (12); \
2858 else if (mips_cpu == PROCESSOR_R6000) \
2859 return COSTS_N_INSNS (15); \
2860 else \
2861 return COSTS_N_INSNS (23); \
2862 } \
2863 \
2864 if (xmode == DFmode) \
2865 { \
2866 if (mips_cpu == PROCESSOR_R3000) \
2867 return COSTS_N_INSNS (19); \
2868 else if (mips_cpu == PROCESSOR_R6000) \
2869 return COSTS_N_INSNS (16); \
2870 else \
2871 return COSTS_N_INSNS (36); \
2872 } \
2873 } \
2874 /* fall through */ \
2875 \
2876 case UDIV: \
2877 case UMOD: \
2878 if (mips_cpu == PROCESSOR_R3000) \
2879 return COSTS_N_INSNS (35); \
2880 else if (mips_cpu == PROCESSOR_R6000) \
2881 return COSTS_N_INSNS (38); \
2882 else \
2883 return COSTS_N_INSNS (69);
2884
2885 /* An expression giving the cost of an addressing mode that
2886 contains ADDRESS. If not defined, the cost is computed from the
2887 form of the ADDRESS expression and the `CONST_COSTS' values.
2888
2889 For most CISC machines, the default cost is a good approximation
2890 of the true cost of the addressing mode. However, on RISC
2891 machines, all instructions normally have the same length and
2892 execution time. Hence all addresses will have equal costs.
2893
2894 In cases where more than one form of an address is known, the
2895 form with the lowest cost will be used. If multiple forms have
2896 the same, lowest, cost, the one that is the most complex will be
2897 used.
2898
2899 For example, suppose an address that is equal to the sum of a
2900 register and a constant is used twice in the same basic block.
2901 When this macro is not defined, the address will be computed in
2902 a register and memory references will be indirect through that
2903 register. On machines where the cost of the addressing mode
2904 containing the sum is no higher than that of a simple indirect
2905 reference, this will produce an additional instruction and
2906 possibly require an additional register. Proper specification
2907 of this macro eliminates this overhead for such machines.
2908
2909 Similar use of this macro is made in strength reduction of loops.
2910
2911 ADDRESS need not be valid as an address. In such a case, the
2912 cost is not relevant and can be any value; invalid addresses
2913 need not be assigned a different cost.
2914
2915 On machines where an address involving more than one register is
2916 as cheap as an address computation involving only one register,
2917 defining `ADDRESS_COST' to reflect this can cause two registers
2918 to be live over a region of code where only one would have been
2919 if `ADDRESS_COST' were not defined in that manner. This effect
2920 should be considered in the definition of this macro.
2921 Equivalent costs should probably only be given to addresses with
2922 different numbers of registers on machines with lots of registers.
2923
2924 This macro will normally either not be defined or be defined as
2925 a constant. */
2926
2927 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
2928
2929 /* A C expression for the cost of moving data from a register in
2930 class FROM to one in class TO. The classes are expressed using
2931 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2932 the default; other values are interpreted relative to that.
2933
2934 It is not required that the cost always equal 2 when FROM is the
2935 same as TO; on some machines it is expensive to move between
2936 registers if they are not general registers.
2937
2938 If reload sees an insn consisting of a single `set' between two
2939 hard registers, and if `REGISTER_MOVE_COST' applied to their
2940 classes returns a value of 2, reload does not check to ensure
2941 that the constraints of the insn are met. Setting a cost of
2942 other than 2 will allow reload to verify that the constraints are
2943 met. You should do this if the `movM' pattern's constraints do
2944 not allow such copying. */
2945
2946 #define REGISTER_MOVE_COST(FROM, TO) \
2947 ((FROM) == GR_REGS && (TO) == GR_REGS ? 2 \
2948 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
2949 : (FROM) == GR_REGS && (TO) == FP_REGS ? 4 \
2950 : (FROM) == FP_REGS && (TO) == GR_REGS ? 4 \
2951 : (((FROM) == HI_REG || (FROM) == LO_REG \
2952 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
2953 && (TO) == GR_REGS) ? 6 \
2954 : (((TO) == HI_REG || (TO) == LO_REG \
2955 || (TO) == MD_REGS || (FROM) == HILO_REG) \
2956 && (FROM) == GR_REGS) ? 6 \
2957 : 12)
2958
2959 /* ??? Fix this to be right for the R8000. */
2960 #define MEMORY_MOVE_COST(MODE) \
2961 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4)
2962
2963 /* A C expression for the cost of a branch instruction. A value of
2964 1 is the default; other values are interpreted relative to that. */
2965
2966 /* ??? Fix this to be right for the R8000. */
2967 #define BRANCH_COST \
2968 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 2 : 1)
2969
2970 /* A C statement (sans semicolon) to update the integer variable COST
2971 based on the relationship between INSN that is dependent on
2972 DEP_INSN through the dependence LINK. The default is to make no
2973 adjustment to COST. On the MIPS, ignore the cost of anti- and
2974 output-dependencies. */
2975
2976 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
2977 if (REG_NOTE_KIND (LINK) != 0) \
2978 (COST) = 0; /* Anti or output dependence. */
2979 \f
2980 /* Optionally define this if you have added predicates to
2981 `MACHINE.c'. This macro is called within an initializer of an
2982 array of structures. The first field in the structure is the
2983 name of a predicate and the second field is an array of rtl
2984 codes. For each predicate, list all rtl codes that can be in
2985 expressions matched by the predicate. The list should have a
2986 trailing comma. Here is an example of two entries in the list
2987 for a typical RISC machine:
2988
2989 #define PREDICATE_CODES \
2990 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
2991 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
2992
2993 Defining this macro does not affect the generated code (however,
2994 incorrect definitions that omit an rtl code that may be matched
2995 by the predicate can cause the compiler to malfunction).
2996 Instead, it allows the table built by `genrecog' to be more
2997 compact and efficient, thus speeding up the compiler. The most
2998 important predicates to include in the list specified by this
2999 macro are thoses used in the most insn patterns. */
3000
3001 #define PREDICATE_CODES \
3002 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3003 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3004 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3005 {"reg_or_0_operand", { REG, CONST_INT, SUBREG }}, \
3006 {"small_int", { CONST_INT }}, \
3007 {"large_int", { CONST_INT }}, \
3008 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3009 {"simple_memory_operand", { MEM, SUBREG }}, \
3010 {"equality_op", { EQ, NE }}, \
3011 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3012 LTU, LEU }}, \
3013 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3014 {"call_insn_operand", { MEM }}, \
3015
3016 \f
3017 /* If defined, a C statement to be executed just prior to the
3018 output of assembler code for INSN, to modify the extracted
3019 operands so they will be output differently.
3020
3021 Here the argument OPVEC is the vector containing the operands
3022 extracted from INSN, and NOPERANDS is the number of elements of
3023 the vector which contain meaningful data for this insn. The
3024 contents of this vector are what will be used to convert the
3025 insn template into assembler code, so you can change the
3026 assembler output by changing the contents of the vector.
3027
3028 We use it to check if the current insn needs a nop in front of it
3029 because of load delays, and also to update the delay slot
3030 statistics. */
3031
3032 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3033 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3034
3035 \f
3036 /* Tell final.c how to eliminate redundant test instructions.
3037 Here we define machine-dependent flags and fields in cc_status
3038 (see `conditions.h'). */
3039
3040 /* A list of names to be used for additional modes for condition code
3041 values in registers. These names are added to `enum machine_mode'
3042 and all have class `MODE_CC'. By convention, they should start
3043 with `CC' and end with `mode'.
3044
3045 You should only define this macro if your machine does not use
3046 `cc0' and only if additional modes are required.
3047
3048 On the MIPS, we use CC_FPmode for all floating point except for not
3049 equal, CC_REV_FPmode for not equal (to reverse the sense of the
3050 jump), CC_EQmode for integer equality/inequality comparisons,
3051 CC_0mode for comparisons against 0, and CCmode for other integer
3052 comparisons. */
3053
3054 #define EXTRA_CC_MODES CC_EQmode, CC_FPmode, CC_0mode, CC_REV_FPmode
3055
3056 /* A list of C strings giving the names for the modes listed in
3057 `EXTRA_CC_MODES'. */
3058
3059 #define EXTRA_CC_NAMES "CC_EQ", "CC_FP", "CC_0", "CC_REV_FP"
3060
3061 /* Returns a mode from class `MODE_CC' to be used when comparison
3062 operation code OP is applied to rtx X. */
3063
3064 #define SELECT_CC_MODE(OP, X, Y) \
3065 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
3066 ? SImode \
3067 : ((OP == NE) ? CC_REV_FPmode : CC_FPmode))
3068
3069 \f
3070 /* Control the assembler format that we output. */
3071
3072 /* Output at beginning of assembler file.
3073 If we are optimizing to use the global pointer, create a temporary
3074 file to hold all of the text stuff, and write it out to the end.
3075 This is needed because the MIPS assembler is evidently one pass,
3076 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3077 declaration when the code is processed, it generates a two
3078 instruction sequence. */
3079
3080 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3081
3082 /* Output to assembler file text saying following lines
3083 may contain character constants, extra white space, comments, etc. */
3084
3085 #define ASM_APP_ON " #APP\n"
3086
3087 /* Output to assembler file text saying following lines
3088 no longer contain unusual constructs. */
3089
3090 #define ASM_APP_OFF " #NO_APP\n"
3091
3092 /* How to refer to registers in assembler output.
3093 This sequence is indexed by compiler's hard-register-number (see above).
3094
3095 In order to support the two different conventions for register names,
3096 we use the name of a table set up in mips.c, which is overwritten
3097 if -mrnames is used. */
3098
3099 #define REGISTER_NAMES \
3100 { \
3101 &mips_reg_names[ 0][0], \
3102 &mips_reg_names[ 1][0], \
3103 &mips_reg_names[ 2][0], \
3104 &mips_reg_names[ 3][0], \
3105 &mips_reg_names[ 4][0], \
3106 &mips_reg_names[ 5][0], \
3107 &mips_reg_names[ 6][0], \
3108 &mips_reg_names[ 7][0], \
3109 &mips_reg_names[ 8][0], \
3110 &mips_reg_names[ 9][0], \
3111 &mips_reg_names[10][0], \
3112 &mips_reg_names[11][0], \
3113 &mips_reg_names[12][0], \
3114 &mips_reg_names[13][0], \
3115 &mips_reg_names[14][0], \
3116 &mips_reg_names[15][0], \
3117 &mips_reg_names[16][0], \
3118 &mips_reg_names[17][0], \
3119 &mips_reg_names[18][0], \
3120 &mips_reg_names[19][0], \
3121 &mips_reg_names[20][0], \
3122 &mips_reg_names[21][0], \
3123 &mips_reg_names[22][0], \
3124 &mips_reg_names[23][0], \
3125 &mips_reg_names[24][0], \
3126 &mips_reg_names[25][0], \
3127 &mips_reg_names[26][0], \
3128 &mips_reg_names[27][0], \
3129 &mips_reg_names[28][0], \
3130 &mips_reg_names[29][0], \
3131 &mips_reg_names[30][0], \
3132 &mips_reg_names[31][0], \
3133 &mips_reg_names[32][0], \
3134 &mips_reg_names[33][0], \
3135 &mips_reg_names[34][0], \
3136 &mips_reg_names[35][0], \
3137 &mips_reg_names[36][0], \
3138 &mips_reg_names[37][0], \
3139 &mips_reg_names[38][0], \
3140 &mips_reg_names[39][0], \
3141 &mips_reg_names[40][0], \
3142 &mips_reg_names[41][0], \
3143 &mips_reg_names[42][0], \
3144 &mips_reg_names[43][0], \
3145 &mips_reg_names[44][0], \
3146 &mips_reg_names[45][0], \
3147 &mips_reg_names[46][0], \
3148 &mips_reg_names[47][0], \
3149 &mips_reg_names[48][0], \
3150 &mips_reg_names[49][0], \
3151 &mips_reg_names[50][0], \
3152 &mips_reg_names[51][0], \
3153 &mips_reg_names[52][0], \
3154 &mips_reg_names[53][0], \
3155 &mips_reg_names[54][0], \
3156 &mips_reg_names[55][0], \
3157 &mips_reg_names[56][0], \
3158 &mips_reg_names[57][0], \
3159 &mips_reg_names[58][0], \
3160 &mips_reg_names[59][0], \
3161 &mips_reg_names[60][0], \
3162 &mips_reg_names[61][0], \
3163 &mips_reg_names[62][0], \
3164 &mips_reg_names[63][0], \
3165 &mips_reg_names[64][0], \
3166 &mips_reg_names[65][0], \
3167 &mips_reg_names[66][0], \
3168 &mips_reg_names[67][0], \
3169 &mips_reg_names[68][0], \
3170 }
3171
3172 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3173 So define this for it. */
3174 #define DEBUG_REGISTER_NAMES \
3175 { \
3176 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3177 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3178 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3179 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3180 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3181 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3182 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3183 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3184 "hi", "lo", "accum","$fcr31","$rap" \
3185 }
3186
3187 /* If defined, a C initializer for an array of structures
3188 containing a name and a register number. This macro defines
3189 additional names for hard registers, thus allowing the `asm'
3190 option in declarations to refer to registers using alternate
3191 names.
3192
3193 We define both names for the integer registers here. */
3194
3195 #define ADDITIONAL_REGISTER_NAMES \
3196 { \
3197 { "$0", 0 + GP_REG_FIRST }, \
3198 { "$1", 1 + GP_REG_FIRST }, \
3199 { "$2", 2 + GP_REG_FIRST }, \
3200 { "$3", 3 + GP_REG_FIRST }, \
3201 { "$4", 4 + GP_REG_FIRST }, \
3202 { "$5", 5 + GP_REG_FIRST }, \
3203 { "$6", 6 + GP_REG_FIRST }, \
3204 { "$7", 7 + GP_REG_FIRST }, \
3205 { "$8", 8 + GP_REG_FIRST }, \
3206 { "$9", 9 + GP_REG_FIRST }, \
3207 { "$10", 10 + GP_REG_FIRST }, \
3208 { "$11", 11 + GP_REG_FIRST }, \
3209 { "$12", 12 + GP_REG_FIRST }, \
3210 { "$13", 13 + GP_REG_FIRST }, \
3211 { "$14", 14 + GP_REG_FIRST }, \
3212 { "$15", 15 + GP_REG_FIRST }, \
3213 { "$16", 16 + GP_REG_FIRST }, \
3214 { "$17", 17 + GP_REG_FIRST }, \
3215 { "$18", 18 + GP_REG_FIRST }, \
3216 { "$19", 19 + GP_REG_FIRST }, \
3217 { "$20", 20 + GP_REG_FIRST }, \
3218 { "$21", 21 + GP_REG_FIRST }, \
3219 { "$22", 22 + GP_REG_FIRST }, \
3220 { "$23", 23 + GP_REG_FIRST }, \
3221 { "$24", 24 + GP_REG_FIRST }, \
3222 { "$25", 25 + GP_REG_FIRST }, \
3223 { "$26", 26 + GP_REG_FIRST }, \
3224 { "$27", 27 + GP_REG_FIRST }, \
3225 { "$28", 28 + GP_REG_FIRST }, \
3226 { "$29", 29 + GP_REG_FIRST }, \
3227 { "$30", 30 + GP_REG_FIRST }, \
3228 { "$31", 31 + GP_REG_FIRST }, \
3229 { "$sp", 29 + GP_REG_FIRST }, \
3230 { "$fp", 30 + GP_REG_FIRST }, \
3231 { "at", 1 + GP_REG_FIRST }, \
3232 { "v0", 2 + GP_REG_FIRST }, \
3233 { "v1", 3 + GP_REG_FIRST }, \
3234 { "a0", 4 + GP_REG_FIRST }, \
3235 { "a1", 5 + GP_REG_FIRST }, \
3236 { "a2", 6 + GP_REG_FIRST }, \
3237 { "a3", 7 + GP_REG_FIRST }, \
3238 { "t0", 8 + GP_REG_FIRST }, \
3239 { "t1", 9 + GP_REG_FIRST }, \
3240 { "t2", 10 + GP_REG_FIRST }, \
3241 { "t3", 11 + GP_REG_FIRST }, \
3242 { "t4", 12 + GP_REG_FIRST }, \
3243 { "t5", 13 + GP_REG_FIRST }, \
3244 { "t6", 14 + GP_REG_FIRST }, \
3245 { "t7", 15 + GP_REG_FIRST }, \
3246 { "s0", 16 + GP_REG_FIRST }, \
3247 { "s1", 17 + GP_REG_FIRST }, \
3248 { "s2", 18 + GP_REG_FIRST }, \
3249 { "s3", 19 + GP_REG_FIRST }, \
3250 { "s4", 20 + GP_REG_FIRST }, \
3251 { "s5", 21 + GP_REG_FIRST }, \
3252 { "s6", 22 + GP_REG_FIRST }, \
3253 { "s7", 23 + GP_REG_FIRST }, \
3254 { "t8", 24 + GP_REG_FIRST }, \
3255 { "t9", 25 + GP_REG_FIRST }, \
3256 { "k0", 26 + GP_REG_FIRST }, \
3257 { "k1", 27 + GP_REG_FIRST }, \
3258 { "gp", 28 + GP_REG_FIRST }, \
3259 { "sp", 29 + GP_REG_FIRST }, \
3260 { "fp", 30 + GP_REG_FIRST }, \
3261 { "ra", 31 + GP_REG_FIRST }, \
3262 { "$sp", 29 + GP_REG_FIRST }, \
3263 { "$fp", 30 + GP_REG_FIRST }, \
3264 { "cc", FPSW_REGNUM }, \
3265 }
3266
3267 /* Define results of standard character escape sequences. */
3268 #define TARGET_BELL 007
3269 #define TARGET_BS 010
3270 #define TARGET_TAB 011
3271 #define TARGET_NEWLINE 012
3272 #define TARGET_VT 013
3273 #define TARGET_FF 014
3274 #define TARGET_CR 015
3275
3276 /* A C compound statement to output to stdio stream STREAM the
3277 assembler syntax for an instruction operand X. X is an RTL
3278 expression.
3279
3280 CODE is a value that can be used to specify one of several ways
3281 of printing the operand. It is used when identical operands
3282 must be printed differently depending on the context. CODE
3283 comes from the `%' specification that was used to request
3284 printing of the operand. If the specification was just `%DIGIT'
3285 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3286 is the ASCII code for LTR.
3287
3288 If X is a register, this macro should print the register's name.
3289 The names can be found in an array `reg_names' whose type is
3290 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3291
3292 When the machine description has a specification `%PUNCT' (a `%'
3293 followed by a punctuation character), this macro is called with
3294 a null pointer for X and the punctuation character for CODE.
3295
3296 See mips.c for the MIPS specific codes. */
3297
3298 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3299
3300 /* A C expression which evaluates to true if CODE is a valid
3301 punctuation character for use in the `PRINT_OPERAND' macro. If
3302 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3303 punctuation characters (except for the standard one, `%') are
3304 used in this way. */
3305
3306 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3307
3308 /* A C compound statement to output to stdio stream STREAM the
3309 assembler syntax for an instruction operand that is a memory
3310 reference whose address is ADDR. ADDR is an RTL expression.
3311
3312 On some machines, the syntax for a symbolic address depends on
3313 the section that the address refers to. On these machines,
3314 define the macro `ENCODE_SECTION_INFO' to store the information
3315 into the `symbol_ref', and then check for it here. */
3316
3317 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3318
3319
3320 /* A C statement, to be executed after all slot-filler instructions
3321 have been output. If necessary, call `dbr_sequence_length' to
3322 determine the number of slots filled in a sequence (zero if not
3323 currently outputting a sequence), to decide how many no-ops to
3324 output, or whatever.
3325
3326 Don't define this macro if it has nothing to do, but it is
3327 helpful in reading assembly output if the extent of the delay
3328 sequence is made explicit (e.g. with white space).
3329
3330 Note that output routines for instructions with delay slots must
3331 be prepared to deal with not being output as part of a sequence
3332 (i.e. when the scheduling pass is not run, or when no slot
3333 fillers could be found.) The variable `final_sequence' is null
3334 when not processing a sequence, otherwise it contains the
3335 `sequence' rtx being output. */
3336
3337 #define DBR_OUTPUT_SEQEND(STREAM) \
3338 do \
3339 { \
3340 if (set_nomacro > 0 && --set_nomacro == 0) \
3341 fputs ("\t.set\tmacro\n", STREAM); \
3342 \
3343 if (set_noreorder > 0 && --set_noreorder == 0) \
3344 fputs ("\t.set\treorder\n", STREAM); \
3345 \
3346 dslots_jump_filled++; \
3347 fputs ("\n", STREAM); \
3348 } \
3349 while (0)
3350
3351
3352 /* How to tell the debugger about changes of source files. Note, the
3353 mips ECOFF format cannot deal with changes of files inside of
3354 functions, which means the output of parser generators like bison
3355 is generally not debuggable without using the -l switch. Lose,
3356 lose, lose. Silicon graphics seems to want all .file's hardwired
3357 to 1. */
3358
3359 #ifndef SET_FILE_NUMBER
3360 #define SET_FILE_NUMBER() ++num_source_filenames
3361 #endif
3362
3363 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3364 mips_output_filename (STREAM, NAME)
3365
3366 /* This is defined so that it can be overridden in iris6.h. */
3367 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3368 do \
3369 { \
3370 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3371 output_quoted_string (STREAM, NAME); \
3372 fputs ("\n", STREAM); \
3373 } \
3374 while (0)
3375
3376 /* This is how to output a note the debugger telling it the line number
3377 to which the following sequence of instructions corresponds.
3378 Silicon graphics puts a label after each .loc. */
3379
3380 #ifndef LABEL_AFTER_LOC
3381 #define LABEL_AFTER_LOC(STREAM)
3382 #endif
3383
3384 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3385 mips_output_lineno (STREAM, LINE)
3386
3387 /* The MIPS implementation uses some labels for it's own purpose. The
3388 following lists what labels are created, and are all formed by the
3389 pattern $L[a-z].*. The machine independent portion of GCC creates
3390 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3391
3392 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3393 $Lb[0-9]+ Begin blocks for MIPS debug support
3394 $Lc[0-9]+ Label for use in s<xx> operation.
3395 $Le[0-9]+ End blocks for MIPS debug support
3396 $Lp\..+ Half-pic labels. */
3397
3398 /* This is how to output the definition of a user-level label named NAME,
3399 such as the label on a static function or variable NAME.
3400
3401 If we are optimizing the gp, remember that this label has been put
3402 out, so we know not to emit an .extern for it in mips_asm_file_end.
3403 We use one of the common bits in the IDENTIFIER tree node for this,
3404 since those bits seem to be unused, and we don't have any method
3405 of getting the decl nodes from the name. */
3406
3407 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
3408 do { \
3409 assemble_name (STREAM, NAME); \
3410 fputs (":\n", STREAM); \
3411 } while (0)
3412
3413
3414 /* A C statement (sans semicolon) to output to the stdio stream
3415 STREAM any text necessary for declaring the name NAME of an
3416 initialized variable which is being defined. This macro must
3417 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3418 The argument DECL is the `VAR_DECL' tree node representing the
3419 variable.
3420
3421 If this macro is not defined, then the variable name is defined
3422 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3423
3424 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3425 do \
3426 { \
3427 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3428 HALF_PIC_DECLARE (NAME); \
3429 } \
3430 while (0)
3431
3432
3433 /* This is how to output a command to make the user-level label named NAME
3434 defined for reference from other files. */
3435
3436 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
3437 do { \
3438 fputs ("\t.globl\t", STREAM); \
3439 assemble_name (STREAM, NAME); \
3440 fputs ("\n", STREAM); \
3441 } while (0)
3442
3443 /* This says how to define a global common symbol. */
3444
3445 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
3446 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
3447
3448 /* This says how to define a local common symbol (ie, not visible to
3449 linker). */
3450
3451 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3452 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
3453
3454
3455 /* This says how to output an external. It would be possible not to
3456 output anything and let undefined symbol become external. However
3457 the assembler uses length information on externals to allocate in
3458 data/sdata bss/sbss, thereby saving exec time. */
3459
3460 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3461 mips_output_external(STREAM,DECL,NAME)
3462
3463 /* This says what to print at the end of the assembly file */
3464 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
3465
3466
3467 /* This is how to declare a function name. The actual work of
3468 emitting the label is moved to function_prologue, so that we can
3469 get the line number correctly emitted before the .ent directive,
3470 and after any .file directives.
3471
3472 Also, switch files if we are optimizing the global pointer. */
3473
3474 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
3475 { \
3476 extern FILE *asm_out_text_file; \
3477 if (TARGET_GP_OPT) \
3478 { \
3479 STREAM = asm_out_text_file; \
3480 /* ??? text_section gets called too soon. If the previous \
3481 function is in a special section and we're not, we have \
3482 to switch back to the text section. We can't call \
3483 text_section again as gcc thinks we're already there. */ \
3484 /* ??? See varasm.c. There are other things that get output \
3485 too early, like alignment (before we've switched STREAM). */ \
3486 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
3487 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
3488 } \
3489 \
3490 HALF_PIC_DECLARE (NAME); \
3491 }
3492
3493 /* This is how to output a reference to a user-level label named NAME.
3494 `assemble_name' uses this. */
3495
3496 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
3497 fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, NAME)
3498
3499 /* This is how to output an internal numbered label where
3500 PREFIX is the class of label and NUM is the number within the class. */
3501
3502 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
3503 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
3504
3505 /* This is how to store into the string LABEL
3506 the symbol_ref name of an internal numbered label where
3507 PREFIX is the class of label and NUM is the number within the class.
3508 This is suitable for output with `assemble_name'. */
3509
3510 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3511 sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
3512
3513 /* This is how to output an assembler line defining a `double' constant. */
3514
3515 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
3516 mips_output_double (STREAM, VALUE)
3517
3518
3519 /* This is how to output an assembler line defining a `float' constant. */
3520
3521 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
3522 mips_output_float (STREAM, VALUE)
3523
3524
3525 /* This is how to output an assembler line defining an `int' constant. */
3526
3527 #define ASM_OUTPUT_INT(STREAM,VALUE) \
3528 do { \
3529 fprintf (STREAM, "\t.word\t"); \
3530 output_addr_const (STREAM, (VALUE)); \
3531 fprintf (STREAM, "\n"); \
3532 } while (0)
3533
3534 /* Likewise for 64 bit, `char' and `short' constants. */
3535
3536 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
3537 do { \
3538 if (TARGET_64BIT) \
3539 { \
3540 fprintf (STREAM, "\t.dword\t"); \
3541 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
3542 /* We can't use 'X' for negative numbers, because then we won't \
3543 get the right value for the upper 32 bits. */ \
3544 output_addr_const (STREAM, VALUE); \
3545 else \
3546 /* We must use 'X', because otherwise LONG_MIN will print as \
3547 a number that the Irix 6 assembler won't accept. */ \
3548 print_operand (STREAM, VALUE, 'X'); \
3549 fprintf (STREAM, "\n"); \
3550 } \
3551 else \
3552 { \
3553 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
3554 UNITS_PER_WORD, 1); \
3555 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
3556 UNITS_PER_WORD, 1); \
3557 } \
3558 } while (0)
3559
3560 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
3561 { \
3562 fprintf (STREAM, "\t.half\t"); \
3563 output_addr_const (STREAM, (VALUE)); \
3564 fprintf (STREAM, "\n"); \
3565 }
3566
3567 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
3568 { \
3569 fprintf (STREAM, "\t.byte\t"); \
3570 output_addr_const (STREAM, (VALUE)); \
3571 fprintf (STREAM, "\n"); \
3572 }
3573
3574 /* This is how to output an assembler line for a numeric constant byte. */
3575
3576 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
3577 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
3578
3579 /* This is how to output an element of a case-vector that is absolute. */
3580
3581 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3582 fprintf (STREAM, "\t%s\t%sL%d\n", \
3583 TARGET_LONG64 ? ".dword" : ".word", \
3584 LOCAL_LABEL_PREFIX, \
3585 VALUE)
3586
3587 /* This is how to output an element of a case-vector that is relative.
3588 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3589 TARGET_EMBEDDED_PIC). */
3590
3591 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, VALUE, REL) \
3592 do { \
3593 if (TARGET_EMBEDDED_PIC) \
3594 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3595 TARGET_LONG64 ? ".dword" : ".word", \
3596 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3597 else if (! ABI_64BIT) \
3598 fprintf (STREAM, "\t%s\t%sL%d\n", \
3599 TARGET_LONG64 ? ".gpdword" : ".gpword", \
3600 LOCAL_LABEL_PREFIX, VALUE); \
3601 else \
3602 /* ??? Why does this one use . and not LOCAL_LABEL_PREFIX? */ \
3603 fprintf (STREAM, "\t%s\t.L%d\n", \
3604 TARGET_LONG64 ? ".dword" : ".word", \
3605 VALUE); \
3606 } while (0)
3607
3608 /* When generating embedded PIC code we want to put the jump table in
3609 the .text section. In all other cases, we want to put the jump
3610 table in the .rdata section. Unfortunately, we can't use
3611 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3612 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3613 section if appropriate. */
3614 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3615 do { \
3616 if (TARGET_EMBEDDED_PIC) \
3617 text_section (); \
3618 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
3619 } while (0)
3620
3621 /* This is how to output an assembler line
3622 that says to advance the location counter
3623 to a multiple of 2**LOG bytes. */
3624
3625 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3626 { \
3627 int mask = (1 << (LOG)) - 1; \
3628 fprintf (STREAM, "\t.align\t%d\n", (LOG)); \
3629 }
3630
3631 /* This is how to output an assembler line to to advance the location
3632 counter by SIZE bytes. */
3633
3634 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3635 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
3636
3637 /* This is how to output a string. */
3638 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3639 do { \
3640 register int i, c, len = (LEN), cur_pos = 17; \
3641 register unsigned char *string = (unsigned char *)(STRING); \
3642 fprintf ((STREAM), "\t.ascii\t\""); \
3643 for (i = 0; i < len; i++) \
3644 { \
3645 register int c = string[i]; \
3646 \
3647 switch (c) \
3648 { \
3649 case '\"': \
3650 case '\\': \
3651 putc ('\\', (STREAM)); \
3652 putc (c, (STREAM)); \
3653 cur_pos += 2; \
3654 break; \
3655 \
3656 case TARGET_NEWLINE: \
3657 fputs ("\\n", (STREAM)); \
3658 if (i+1 < len \
3659 && (((c = string[i+1]) >= '\040' && c <= '~') \
3660 || c == TARGET_TAB)) \
3661 cur_pos = 32767; /* break right here */ \
3662 else \
3663 cur_pos += 2; \
3664 break; \
3665 \
3666 case TARGET_TAB: \
3667 fputs ("\\t", (STREAM)); \
3668 cur_pos += 2; \
3669 break; \
3670 \
3671 case TARGET_FF: \
3672 fputs ("\\f", (STREAM)); \
3673 cur_pos += 2; \
3674 break; \
3675 \
3676 case TARGET_BS: \
3677 fputs ("\\b", (STREAM)); \
3678 cur_pos += 2; \
3679 break; \
3680 \
3681 case TARGET_CR: \
3682 fputs ("\\r", (STREAM)); \
3683 cur_pos += 2; \
3684 break; \
3685 \
3686 default: \
3687 if (c >= ' ' && c < 0177) \
3688 { \
3689 putc (c, (STREAM)); \
3690 cur_pos++; \
3691 } \
3692 else \
3693 { \
3694 fprintf ((STREAM), "\\%03o", c); \
3695 cur_pos += 4; \
3696 } \
3697 } \
3698 \
3699 if (cur_pos > 72 && i+1 < len) \
3700 { \
3701 cur_pos = 17; \
3702 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
3703 } \
3704 } \
3705 fprintf ((STREAM), "\"\n"); \
3706 } while (0)
3707
3708 /* Handle certain cpp directives used in header files on sysV. */
3709 #define SCCS_DIRECTIVE
3710
3711 /* Output #ident as a in the read-only data section. */
3712 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3713 { \
3714 char *p = STRING; \
3715 int size = strlen (p) + 1; \
3716 rdata_section (); \
3717 assemble_string (p, size); \
3718 }
3719 \f
3720 /* Default to -G 8 */
3721 #ifndef MIPS_DEFAULT_GVALUE
3722 #define MIPS_DEFAULT_GVALUE 8
3723 #endif
3724
3725 /* Define the strings to put out for each section in the object file. */
3726 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3727 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3728 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3729 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3730 #define READONLY_DATA_SECTION rdata_section
3731 #define SMALL_DATA_SECTION sdata_section
3732
3733 /* What other sections we support other than the normal .data/.text. */
3734
3735 #define EXTRA_SECTIONS in_sdata, in_rdata
3736
3737 /* Define the additional functions to select our additional sections. */
3738
3739 /* on the MIPS it is not a good idea to put constants in the text
3740 section, since this defeats the sdata/data mechanism. This is
3741 especially true when -O is used. In this case an effort is made to
3742 address with faster (gp) register relative addressing, which can
3743 only get at sdata and sbss items (there is no stext !!) However,
3744 if the constant is too large for sdata, and it's readonly, it
3745 will go into the .rdata section. */
3746
3747 #define EXTRA_SECTION_FUNCTIONS \
3748 void \
3749 sdata_section () \
3750 { \
3751 if (in_section != in_sdata) \
3752 { \
3753 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
3754 in_section = in_sdata; \
3755 } \
3756 } \
3757 \
3758 void \
3759 rdata_section () \
3760 { \
3761 if (in_section != in_rdata) \
3762 { \
3763 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
3764 in_section = in_rdata; \
3765 } \
3766 }
3767
3768 /* Given a decl node or constant node, choose the section to output it in
3769 and select that section. */
3770
3771 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
3772
3773 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
3774
3775 \f
3776 /* Store in OUTPUT a string (made with alloca) containing
3777 an assembler-name for a local static variable named NAME.
3778 LABELNO is an integer which is different for each call. */
3779
3780 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
3781 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
3782 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
3783
3784 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3785 do \
3786 { \
3787 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3788 TARGET_64BIT ? "dsubu" : "subu", \
3789 reg_names[STACK_POINTER_REGNUM], \
3790 reg_names[STACK_POINTER_REGNUM], \
3791 TARGET_64BIT ? "sd" : "sw", \
3792 reg_names[REGNO], \
3793 reg_names[STACK_POINTER_REGNUM]); \
3794 } \
3795 while (0)
3796
3797 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3798 do \
3799 { \
3800 if (! set_noreorder) \
3801 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3802 \
3803 dslots_load_total++; \
3804 dslots_load_filled++; \
3805 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3806 TARGET_64BIT ? "ld" : "lw", \
3807 reg_names[REGNO], \
3808 reg_names[STACK_POINTER_REGNUM], \
3809 TARGET_64BIT ? "daddu" : "addu", \
3810 reg_names[STACK_POINTER_REGNUM], \
3811 reg_names[STACK_POINTER_REGNUM]); \
3812 \
3813 if (! set_noreorder) \
3814 fprintf (STREAM, "\t.set\treorder\n"); \
3815 } \
3816 while (0)
3817
3818 /* Define the parentheses used to group arithmetic operations
3819 in assembler code. */
3820
3821 #define ASM_OPEN_PAREN "("
3822 #define ASM_CLOSE_PAREN ")"
3823
3824 /* How to start an assembler comment. */
3825 #ifndef ASM_COMMENT_START
3826 #define ASM_COMMENT_START "\t\t# "
3827 #endif
3828
3829 \f
3830
3831 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
3832 and mips-tdump.c to print them out.
3833
3834 These must match the corresponding definitions in gdb/mipsread.c.
3835 Unfortunately, gcc and gdb do not currently share any directories. */
3836
3837 #define CODE_MASK 0x8F300
3838 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
3839 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
3840 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
3841
3842 \f
3843 /* Default definitions for size_t and ptrdiff_t. */
3844
3845 #ifndef SIZE_TYPE
3846 #define NO_BUILTIN_SIZE_TYPE
3847 #define SIZE_TYPE (TARGET_LONG64 ? "long unsigned int" : "unsigned int")
3848 #endif
3849
3850 #ifndef PTRDIFF_TYPE
3851 #define NO_BUILTIN_PTRDIFF_TYPE
3852 #define PTRDIFF_TYPE (TARGET_LONG64 ? "long int" : "int")
3853 #endif