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install.texi (--with-mips-plt): Document.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF2_1,
45 PROCESSOR_24KF1_1,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF2_1,
48 PROCESSOR_74KF1_1,
49 PROCESSOR_74KF3_2,
50 PROCESSOR_LOONGSON_2E,
51 PROCESSOR_LOONGSON_2F,
52 PROCESSOR_M4K,
53 PROCESSOR_R3900,
54 PROCESSOR_R6000,
55 PROCESSOR_R4000,
56 PROCESSOR_R4100,
57 PROCESSOR_R4111,
58 PROCESSOR_R4120,
59 PROCESSOR_R4130,
60 PROCESSOR_R4300,
61 PROCESSOR_R4600,
62 PROCESSOR_R4650,
63 PROCESSOR_R5000,
64 PROCESSOR_R5400,
65 PROCESSOR_R5500,
66 PROCESSOR_R7000,
67 PROCESSOR_R8000,
68 PROCESSOR_R9000,
69 PROCESSOR_SB1,
70 PROCESSOR_SB1A,
71 PROCESSOR_SR71000,
72 PROCESSOR_XLR,
73 PROCESSOR_MAX
74 };
75
76 /* Costs of various operations on the different architectures. */
77
78 struct mips_rtx_cost_data
79 {
80 unsigned short fp_add;
81 unsigned short fp_mult_sf;
82 unsigned short fp_mult_df;
83 unsigned short fp_div_sf;
84 unsigned short fp_div_df;
85 unsigned short int_mult_si;
86 unsigned short int_mult_di;
87 unsigned short int_div_si;
88 unsigned short int_div_di;
89 unsigned short branch_cost;
90 unsigned short memory_latency;
91 };
92
93 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
94 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
95 to work on a 64-bit machine. */
96
97 #define ABI_32 0
98 #define ABI_N32 1
99 #define ABI_64 2
100 #define ABI_EABI 3
101 #define ABI_O64 4
102
103 /* Masks that affect tuning.
104
105 PTF_AVOID_BRANCHLIKELY
106 Set if it is usually not profitable to use branch-likely instructions
107 for this target, typically because the branches are always predicted
108 taken and so incur a large overhead when not taken. */
109 #define PTF_AVOID_BRANCHLIKELY 0x1
110
111 /* Information about one recognized processor. Defined here for the
112 benefit of TARGET_CPU_CPP_BUILTINS. */
113 struct mips_cpu_info {
114 /* The 'canonical' name of the processor as far as GCC is concerned.
115 It's typically a manufacturer's prefix followed by a numerical
116 designation. It should be lowercase. */
117 const char *name;
118
119 /* The internal processor number that most closely matches this
120 entry. Several processors can have the same value, if there's no
121 difference between them from GCC's point of view. */
122 enum processor_type cpu;
123
124 /* The ISA level that the processor implements. */
125 int isa;
126
127 /* A mask of PTF_* values. */
128 unsigned int tune_flags;
129 };
130
131 /* Enumerates the setting of the -mcode-readable option. */
132 enum mips_code_readable_setting {
133 CODE_READABLE_NO,
134 CODE_READABLE_PCREL,
135 CODE_READABLE_YES
136 };
137
138 /* Macros to silence warnings about numbers being signed in traditional
139 C and unsigned in ISO C when compiled on 32-bit hosts. */
140
141 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
142 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
143 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
144
145 \f
146 /* Run-time compilation parameters selecting different hardware subsets. */
147
148 /* True if we are generating position-independent VxWorks RTP code. */
149 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
150
151 /* True if the output file is marked as ".abicalls; .option pic0"
152 (-call_nonpic). */
153 #define TARGET_ABICALLS_PIC0 \
154 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
155
156 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
157 #define TARGET_ABICALLS_PIC2 \
158 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
159
160 /* True if the call patterns should be split into a jalr followed by
161 an instruction to restore $gp. It is only safe to split the load
162 from the call when every use of $gp is explicit. */
163
164 #define TARGET_SPLIT_CALLS \
165 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
166
167 /* True if we're generating a form of -mabicalls in which we can use
168 operators like %hi and %lo to refer to locally-binding symbols.
169 We can only do this for -mno-shared, and only then if we can use
170 relocation operations instead of assembly macros. It isn't really
171 worth using absolute sequences for 64-bit symbols because GOT
172 accesses are so much shorter. */
173
174 #define TARGET_ABSOLUTE_ABICALLS \
175 (TARGET_ABICALLS \
176 && !TARGET_SHARED \
177 && TARGET_EXPLICIT_RELOCS \
178 && !ABI_HAS_64BIT_SYMBOLS)
179
180 /* True if we can optimize sibling calls. For simplicity, we only
181 handle cases in which call_insn_operand will reject invalid
182 sibcall addresses. There are two cases in which this isn't true:
183
184 - TARGET_MIPS16. call_insn_operand accepts constant addresses
185 but there is no direct jump instruction. It isn't worth
186 using sibling calls in this case anyway; they would usually
187 be longer than normal calls.
188
189 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
190 accepts global constants, but all sibcalls must be indirect. */
191 #define TARGET_SIBCALLS \
192 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
193
194 /* True if we need to use a global offset table to access some symbols. */
195 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
196
197 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
198 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
199
200 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
201 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
202
203 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
204 This is true for both the PIC and non-PIC VxWorks RTP modes. */
205 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
206
207 /* True if .gpword or .gpdword should be used for switch tables.
208
209 Although GAS does understand .gpdword, the SGI linker mishandles
210 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
211 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
212 #define TARGET_GPWORD \
213 (TARGET_ABICALLS \
214 && !TARGET_ABSOLUTE_ABICALLS \
215 && !(mips_abi == ABI_64 && TARGET_IRIX))
216
217 /* Generate mips16 code */
218 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
219 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
220 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
221 /* Generate mips16e register save/restore sequences. */
222 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
223
224 /* True if we're generating a form of MIPS16 code in which general
225 text loads are allowed. */
226 #define TARGET_MIPS16_TEXT_LOADS \
227 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
228
229 /* True if we're generating a form of MIPS16 code in which PC-relative
230 loads are allowed. */
231 #define TARGET_MIPS16_PCREL_LOADS \
232 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
233
234 /* Generic ISA defines. */
235 #define ISA_MIPS1 (mips_isa == 1)
236 #define ISA_MIPS2 (mips_isa == 2)
237 #define ISA_MIPS3 (mips_isa == 3)
238 #define ISA_MIPS4 (mips_isa == 4)
239 #define ISA_MIPS32 (mips_isa == 32)
240 #define ISA_MIPS32R2 (mips_isa == 33)
241 #define ISA_MIPS64 (mips_isa == 64)
242 #define ISA_MIPS64R2 (mips_isa == 65)
243
244 /* Architecture target defines. */
245 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
246 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
247 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
248 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
249 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
250 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
251 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
252 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
253 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
254 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
255 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
256 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
257 || mips_arch == PROCESSOR_SB1A)
258 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
259
260 /* Scheduling target defines. */
261 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
262 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
263 || mips_tune == PROCESSOR_24KF2_1 \
264 || mips_tune == PROCESSOR_24KF1_1)
265 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
266 || mips_tune == PROCESSOR_74KF2_1 \
267 || mips_tune == PROCESSOR_74KF1_1 \
268 || mips_tune == PROCESSOR_74KF3_2)
269 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
270 || mips_tune == PROCESSOR_LOONGSON_2F)
271 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
272 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
273 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
274 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
275 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
276 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
277 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
278 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
279 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
280 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
281 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
282 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
283 || mips_tune == PROCESSOR_SB1A)
284
285 /* Whether vector modes and intrinsics for ST Microelectronics
286 Loongson-2E/2F processors should be enabled. In o32 pairs of
287 floating-point registers provide 64-bit values. */
288 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
289 && TARGET_LOONGSON_2EF)
290
291 /* True if the pre-reload scheduler should try to create chains of
292 multiply-add or multiply-subtract instructions. For example,
293 suppose we have:
294
295 t1 = a * b
296 t2 = t1 + c * d
297 t3 = e * f
298 t4 = t3 - g * h
299
300 t1 will have a higher priority than t2 and t3 will have a higher
301 priority than t4. However, before reload, there is no dependence
302 between t1 and t3, and they can often have similar priorities.
303 The scheduler will then tend to prefer:
304
305 t1 = a * b
306 t3 = e * f
307 t2 = t1 + c * d
308 t4 = t3 - g * h
309
310 which stops us from making full use of macc/madd-style instructions.
311 This sort of situation occurs frequently in Fourier transforms and
312 in unrolled loops.
313
314 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
315 queue so that chained multiply-add and multiply-subtract instructions
316 appear ahead of any other instruction that is likely to clobber lo.
317 In the example above, if t2 and t3 become ready at the same time,
318 the code ensures that t2 is scheduled first.
319
320 Multiply-accumulate instructions are a bigger win for some targets
321 than others, so this macro is defined on an opt-in basis. */
322 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
323 || TUNE_MIPS4120 \
324 || TUNE_MIPS4130 \
325 || TUNE_24K)
326
327 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
328 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
329
330 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
331 directly accessible, while the command-line options select
332 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
333 in use. */
334 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
335 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
336
337 /* IRIX specific stuff. */
338 #define TARGET_IRIX 0
339 #define TARGET_IRIX6 0
340
341 /* Define preprocessor macros for the -march and -mtune options.
342 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
343 processor. If INFO's canonical name is "foo", define PREFIX to
344 be "foo", and define an additional macro PREFIX_FOO. */
345 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
346 do \
347 { \
348 char *macro, *p; \
349 \
350 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
351 for (p = macro; *p != 0; p++) \
352 *p = TOUPPER (*p); \
353 \
354 builtin_define (macro); \
355 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
356 free (macro); \
357 } \
358 while (0)
359
360 /* Target CPU builtins. */
361 #define TARGET_CPU_CPP_BUILTINS() \
362 do \
363 { \
364 /* Everyone but IRIX defines this to mips. */ \
365 if (!TARGET_IRIX) \
366 builtin_assert ("machine=mips"); \
367 \
368 builtin_assert ("cpu=mips"); \
369 builtin_define ("__mips__"); \
370 builtin_define ("_mips"); \
371 \
372 /* We do this here because __mips is defined below and so we \
373 can't use builtin_define_std. We don't ever want to define \
374 "mips" for VxWorks because some of the VxWorks headers \
375 construct include filenames from a root directory macro, \
376 an architecture macro and a filename, where the architecture \
377 macro expands to 'mips'. If we define 'mips' to 1, the \
378 architecture macro expands to 1 as well. */ \
379 if (!flag_iso && !TARGET_VXWORKS) \
380 builtin_define ("mips"); \
381 \
382 if (TARGET_64BIT) \
383 builtin_define ("__mips64"); \
384 \
385 if (!TARGET_IRIX) \
386 { \
387 /* Treat _R3000 and _R4000 like register-size \
388 defines, which is how they've historically \
389 been used. */ \
390 if (TARGET_64BIT) \
391 { \
392 builtin_define_std ("R4000"); \
393 builtin_define ("_R4000"); \
394 } \
395 else \
396 { \
397 builtin_define_std ("R3000"); \
398 builtin_define ("_R3000"); \
399 } \
400 } \
401 if (TARGET_FLOAT64) \
402 builtin_define ("__mips_fpr=64"); \
403 else \
404 builtin_define ("__mips_fpr=32"); \
405 \
406 if (mips_base_mips16) \
407 builtin_define ("__mips16"); \
408 \
409 if (TARGET_MIPS3D) \
410 builtin_define ("__mips3d"); \
411 \
412 if (TARGET_SMARTMIPS) \
413 builtin_define ("__mips_smartmips"); \
414 \
415 if (TARGET_DSP) \
416 { \
417 builtin_define ("__mips_dsp"); \
418 if (TARGET_DSPR2) \
419 { \
420 builtin_define ("__mips_dspr2"); \
421 builtin_define ("__mips_dsp_rev=2"); \
422 } \
423 else \
424 builtin_define ("__mips_dsp_rev=1"); \
425 } \
426 \
427 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
428 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
429 \
430 if (ISA_MIPS1) \
431 { \
432 builtin_define ("__mips=1"); \
433 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
434 } \
435 else if (ISA_MIPS2) \
436 { \
437 builtin_define ("__mips=2"); \
438 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
439 } \
440 else if (ISA_MIPS3) \
441 { \
442 builtin_define ("__mips=3"); \
443 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
444 } \
445 else if (ISA_MIPS4) \
446 { \
447 builtin_define ("__mips=4"); \
448 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
449 } \
450 else if (ISA_MIPS32) \
451 { \
452 builtin_define ("__mips=32"); \
453 builtin_define ("__mips_isa_rev=1"); \
454 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
455 } \
456 else if (ISA_MIPS32R2) \
457 { \
458 builtin_define ("__mips=32"); \
459 builtin_define ("__mips_isa_rev=2"); \
460 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
461 } \
462 else if (ISA_MIPS64) \
463 { \
464 builtin_define ("__mips=64"); \
465 builtin_define ("__mips_isa_rev=1"); \
466 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
467 } \
468 else if (ISA_MIPS64R2) \
469 { \
470 builtin_define ("__mips=64"); \
471 builtin_define ("__mips_isa_rev=2"); \
472 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
473 } \
474 \
475 switch (mips_abi) \
476 { \
477 case ABI_32: \
478 builtin_define ("_ABIO32=1"); \
479 builtin_define ("_MIPS_SIM=_ABIO32"); \
480 break; \
481 \
482 case ABI_N32: \
483 builtin_define ("_ABIN32=2"); \
484 builtin_define ("_MIPS_SIM=_ABIN32"); \
485 break; \
486 \
487 case ABI_64: \
488 builtin_define ("_ABI64=3"); \
489 builtin_define ("_MIPS_SIM=_ABI64"); \
490 break; \
491 \
492 case ABI_O64: \
493 builtin_define ("_ABIO64=4"); \
494 builtin_define ("_MIPS_SIM=_ABIO64"); \
495 break; \
496 } \
497 \
498 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
499 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
500 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
501 builtin_define_with_int_value ("_MIPS_FPSET", \
502 32 / MAX_FPRS_PER_FMT); \
503 \
504 /* These defines reflect the ABI in use, not whether the \
505 FPU is directly accessible. */ \
506 if (TARGET_HARD_FLOAT_ABI) \
507 builtin_define ("__mips_hard_float"); \
508 else \
509 builtin_define ("__mips_soft_float"); \
510 \
511 if (TARGET_SINGLE_FLOAT) \
512 builtin_define ("__mips_single_float"); \
513 \
514 if (TARGET_PAIRED_SINGLE_FLOAT) \
515 builtin_define ("__mips_paired_single_float"); \
516 \
517 if (TARGET_BIG_ENDIAN) \
518 { \
519 builtin_define_std ("MIPSEB"); \
520 builtin_define ("_MIPSEB"); \
521 } \
522 else \
523 { \
524 builtin_define_std ("MIPSEL"); \
525 builtin_define ("_MIPSEL"); \
526 } \
527 \
528 /* Whether Loongson vector modes are enabled. */ \
529 if (TARGET_LOONGSON_VECTORS) \
530 builtin_define ("__mips_loongson_vector_rev"); \
531 \
532 /* Macros dependent on the C dialect. */ \
533 if (preprocessing_asm_p ()) \
534 { \
535 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
536 builtin_define ("_LANGUAGE_ASSEMBLY"); \
537 } \
538 else if (c_dialect_cxx ()) \
539 { \
540 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
541 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
542 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
543 } \
544 else \
545 { \
546 builtin_define_std ("LANGUAGE_C"); \
547 builtin_define ("_LANGUAGE_C"); \
548 } \
549 if (c_dialect_objc ()) \
550 { \
551 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
552 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
553 /* Bizarre, but needed at least for Irix. */ \
554 builtin_define_std ("LANGUAGE_C"); \
555 builtin_define ("_LANGUAGE_C"); \
556 } \
557 \
558 if (mips_abi == ABI_EABI) \
559 builtin_define ("__mips_eabi"); \
560 } \
561 while (0)
562
563 /* Default target_flags if no switches are specified */
564
565 #ifndef TARGET_DEFAULT
566 #define TARGET_DEFAULT 0
567 #endif
568
569 #ifndef TARGET_CPU_DEFAULT
570 #define TARGET_CPU_DEFAULT 0
571 #endif
572
573 #ifndef TARGET_ENDIAN_DEFAULT
574 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
575 #endif
576
577 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
578 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
579 #endif
580
581 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
582 #ifndef MIPS_ISA_DEFAULT
583 #ifndef MIPS_CPU_STRING_DEFAULT
584 #define MIPS_CPU_STRING_DEFAULT "from-abi"
585 #endif
586 #endif
587
588 #ifdef IN_LIBGCC2
589 #undef TARGET_64BIT
590 /* Make this compile time constant for libgcc2 */
591 #ifdef __mips64
592 #define TARGET_64BIT 1
593 #else
594 #define TARGET_64BIT 0
595 #endif
596 #endif /* IN_LIBGCC2 */
597
598 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
599 when compiled with hardware floating point. This is because MIPS16
600 code cannot save and restore the floating-point registers, which is
601 important if in a mixed MIPS16/non-MIPS16 environment. */
602
603 #ifdef IN_LIBGCC2
604 #if __mips_hard_float
605 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
606 #endif
607 #endif /* IN_LIBGCC2 */
608
609 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
610
611 #ifndef MULTILIB_ENDIAN_DEFAULT
612 #if TARGET_ENDIAN_DEFAULT == 0
613 #define MULTILIB_ENDIAN_DEFAULT "EL"
614 #else
615 #define MULTILIB_ENDIAN_DEFAULT "EB"
616 #endif
617 #endif
618
619 #ifndef MULTILIB_ISA_DEFAULT
620 # if MIPS_ISA_DEFAULT == 1
621 # define MULTILIB_ISA_DEFAULT "mips1"
622 # else
623 # if MIPS_ISA_DEFAULT == 2
624 # define MULTILIB_ISA_DEFAULT "mips2"
625 # else
626 # if MIPS_ISA_DEFAULT == 3
627 # define MULTILIB_ISA_DEFAULT "mips3"
628 # else
629 # if MIPS_ISA_DEFAULT == 4
630 # define MULTILIB_ISA_DEFAULT "mips4"
631 # else
632 # if MIPS_ISA_DEFAULT == 32
633 # define MULTILIB_ISA_DEFAULT "mips32"
634 # else
635 # if MIPS_ISA_DEFAULT == 33
636 # define MULTILIB_ISA_DEFAULT "mips32r2"
637 # else
638 # if MIPS_ISA_DEFAULT == 64
639 # define MULTILIB_ISA_DEFAULT "mips64"
640 # else
641 # if MIPS_ISA_DEFAULT == 65
642 # define MULTILIB_ISA_DEFAULT "mips64r2"
643 # else
644 # define MULTILIB_ISA_DEFAULT "mips1"
645 # endif
646 # endif
647 # endif
648 # endif
649 # endif
650 # endif
651 # endif
652 # endif
653 #endif
654
655 #ifndef MULTILIB_DEFAULTS
656 #define MULTILIB_DEFAULTS \
657 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
658 #endif
659
660 /* We must pass -EL to the linker by default for little endian embedded
661 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
662 linker will default to using big-endian output files. The OUTPUT_FORMAT
663 line must be in the linker script, otherwise -EB/-EL will not work. */
664
665 #ifndef ENDIAN_SPEC
666 #if TARGET_ENDIAN_DEFAULT == 0
667 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
668 #else
669 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
670 #endif
671 #endif
672
673 /* A spec condition that matches all non-mips16 -mips arguments. */
674
675 #define MIPS_ISA_LEVEL_OPTION_SPEC \
676 "mips1|mips2|mips3|mips4|mips32*|mips64*"
677
678 /* A spec condition that matches all non-mips16 architecture arguments. */
679
680 #define MIPS_ARCH_OPTION_SPEC \
681 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
682
683 /* A spec that infers a -mips argument from an -march argument,
684 or injects the default if no architecture is specified. */
685
686 #define MIPS_ISA_LEVEL_SPEC \
687 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
688 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
689 %{march=mips2|march=r6000:-mips2} \
690 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
691 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \
692 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
693 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
694 |march=34k*|march=74k*: -mips32r2} \
695 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
696 %{march=mips64r2: -mips64r2} \
697 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
698
699 /* A spec that infers a -mhard-float or -msoft-float setting from an
700 -march argument. Note that soft-float and hard-float code are not
701 link-compatible. */
702
703 #define MIPS_ARCH_FLOAT_SPEC \
704 "%{mhard-float|msoft-float|march=mips*:; \
705 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
706 |march=34kc|march=74kc|march=5kc: -msoft-float; \
707 march=*: -mhard-float}"
708
709 /* A spec condition that matches 32-bit options. It only works if
710 MIPS_ISA_LEVEL_SPEC has been applied. */
711
712 #define MIPS_32BIT_OPTION_SPEC \
713 "mips1|mips2|mips32*|mgp32"
714
715 /* Support for a compile-time default CPU, et cetera. The rules are:
716 --with-arch is ignored if -march is specified or a -mips is specified
717 (other than -mips16).
718 --with-tune is ignored if -mtune is specified.
719 --with-abi is ignored if -mabi is specified.
720 --with-float is ignored if -mhard-float or -msoft-float are
721 specified.
722 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
723 specified. */
724 #define OPTION_DEFAULT_SPECS \
725 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
726 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
727 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
728 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
729 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
730 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
731 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }
732
733
734 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
735 && ISA_HAS_COND_TRAP)
736
737 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
738
739 /* True if the ABI can only work with 64-bit integer registers. We
740 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
741 otherwise floating-point registers must also be 64-bit. */
742 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
743
744 /* Likewise for 32-bit regs. */
745 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
746
747 /* True if symbols are 64 bits wide. At present, n64 is the only
748 ABI for which this is true. */
749 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
750
751 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
752 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
753 || ISA_MIPS4 \
754 || ISA_MIPS64 \
755 || ISA_MIPS64R2)
756
757 /* ISA has branch likely instructions (e.g. mips2). */
758 /* Disable branchlikely for tx39 until compare rewrite. They haven't
759 been generated up to this point. */
760 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
761
762 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
763 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
764 || TARGET_MIPS5400 \
765 || TARGET_MIPS5500 \
766 || TARGET_MIPS7000 \
767 || TARGET_MIPS9000 \
768 || TARGET_MAD \
769 || ISA_MIPS32 \
770 || ISA_MIPS32R2 \
771 || ISA_MIPS64 \
772 || ISA_MIPS64R2) \
773 && !TARGET_MIPS16)
774
775 /* ISA has the floating-point conditional move instructions introduced
776 in mips4. */
777 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
778 || ISA_MIPS32 \
779 || ISA_MIPS32R2 \
780 || ISA_MIPS64 \
781 || ISA_MIPS64R2) \
782 && !TARGET_MIPS5500 \
783 && !TARGET_MIPS16)
784
785 /* ISA has the integer conditional move instructions introduced in mips4 and
786 ST Loongson 2E/2F. */
787 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
788
789 /* ISA has LDC1 and SDC1. */
790 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
791
792 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
793 branch on CC, and move (both FP and non-FP) on CC. */
794 #define ISA_HAS_8CC (ISA_MIPS4 \
795 || ISA_MIPS32 \
796 || ISA_MIPS32R2 \
797 || ISA_MIPS64 \
798 || ISA_MIPS64R2)
799
800 /* This is a catch all for other mips4 instructions: indexed load, the
801 FP madd and msub instructions, and the FP recip and recip sqrt
802 instructions. */
803 #define ISA_HAS_FP4 ((ISA_MIPS4 \
804 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
805 || ISA_MIPS64 \
806 || ISA_MIPS64R2) \
807 && !TARGET_MIPS16)
808
809 /* ISA has paired-single instructions. */
810 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
811
812 /* ISA has conditional trap instructions. */
813 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
814 && !TARGET_MIPS16)
815
816 /* ISA has integer multiply-accumulate instructions, madd and msub. */
817 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
818 || ISA_MIPS32R2 \
819 || ISA_MIPS64 \
820 || ISA_MIPS64R2) \
821 && !TARGET_MIPS16)
822
823 /* Integer multiply-accumulate instructions should be generated. */
824 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
825
826 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
827 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
828
829 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
830 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
831
832 /* ISA has floating-point nmadd and nmsub instructions
833 'd = -((a * b) [+-] c)'. */
834 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
835 ((ISA_MIPS4 \
836 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
837 || ISA_MIPS64 \
838 || ISA_MIPS64R2) \
839 && (!TARGET_MIPS5400 || TARGET_MAD) \
840 && !TARGET_MIPS16)
841
842 /* ISA has floating-point nmadd and nmsub instructions
843 'c = -((a * b) [+-] c)'. */
844 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
845 TARGET_LOONGSON_2EF
846
847 /* ISA has count leading zeroes/ones instruction (not implemented). */
848 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
849 || ISA_MIPS32R2 \
850 || ISA_MIPS64 \
851 || ISA_MIPS64R2) \
852 && !TARGET_MIPS16)
853
854 /* ISA has three operand multiply instructions that put
855 the high part in an accumulator: mulhi or mulhiu. */
856 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
857 || TARGET_MIPS5500 \
858 || TARGET_SR71K) \
859 && !TARGET_MIPS16)
860
861 /* ISA has three operand multiply instructions that
862 negates the result and puts the result in an accumulator. */
863 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
864 || TARGET_MIPS5500 \
865 || TARGET_SR71K) \
866 && !TARGET_MIPS16)
867
868 /* ISA has three operand multiply instructions that subtracts the
869 result from a 4th operand and puts the result in an accumulator. */
870 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
871 || TARGET_MIPS5500 \
872 || TARGET_SR71K) \
873 && !TARGET_MIPS16)
874
875 /* ISA has three operand multiply instructions that the result
876 from a 4th operand and puts the result in an accumulator. */
877 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
878 || TARGET_MIPS4130 \
879 || TARGET_MIPS5400 \
880 || TARGET_MIPS5500 \
881 || TARGET_SR71K) \
882 && !TARGET_MIPS16)
883
884 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
885 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
886 || TARGET_MIPS4130) \
887 && !TARGET_MIPS16)
888
889 /* ISA has the "ror" (rotate right) instructions. */
890 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
891 || ISA_MIPS64R2 \
892 || TARGET_MIPS5400 \
893 || TARGET_MIPS5500 \
894 || TARGET_SR71K \
895 || TARGET_SMARTMIPS) \
896 && !TARGET_MIPS16)
897
898 /* ISA has data prefetch instructions. This controls use of 'pref'. */
899 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
900 || ISA_MIPS32 \
901 || ISA_MIPS32R2 \
902 || ISA_MIPS64 \
903 || ISA_MIPS64R2) \
904 && !TARGET_MIPS16)
905
906 /* ISA has data indexed prefetch instructions. This controls use of
907 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
908 (prefx is a cop1x instruction, so can only be used if FP is
909 enabled.) */
910 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
911 || ISA_MIPS32R2 \
912 || ISA_MIPS64 \
913 || ISA_MIPS64R2) \
914 && !TARGET_MIPS16)
915
916 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
917 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
918 also requires TARGET_DOUBLE_FLOAT. */
919 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
920
921 /* ISA includes the MIPS32r2 seb and seh instructions. */
922 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
923 || ISA_MIPS64R2) \
924 && !TARGET_MIPS16)
925
926 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
927 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
928 || ISA_MIPS64R2) \
929 && !TARGET_MIPS16)
930
931 /* ISA has instructions for accessing top part of 64-bit fp regs. */
932 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
933 && (ISA_MIPS32R2 \
934 || ISA_MIPS64R2))
935
936 /* ISA has lwxs instruction (load w/scaled index address. */
937 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
938
939 /* The DSP ASE is available. */
940 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
941
942 /* Revision 2 of the DSP ASE is available. */
943 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
944
945 /* True if the result of a load is not available to the next instruction.
946 A nop will then be needed between instructions like "lw $4,..."
947 and "addiu $4,$4,1". */
948 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
949 && !TARGET_MIPS3900 \
950 && !TARGET_MIPS16)
951
952 /* Likewise mtc1 and mfc1. */
953 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
954 && !TARGET_LOONGSON_2EF)
955
956 /* Likewise floating-point comparisons. */
957 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
958 && !TARGET_LOONGSON_2EF)
959
960 /* True if mflo and mfhi can be immediately followed by instructions
961 which write to the HI and LO registers.
962
963 According to MIPS specifications, MIPS ISAs I, II, and III need
964 (at least) two instructions between the reads of HI/LO and
965 instructions which write them, and later ISAs do not. Contradicting
966 the MIPS specifications, some MIPS IV processor user manuals (e.g.
967 the UM for the NEC Vr5000) document needing the instructions between
968 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
969 MIPS64 and later ISAs to have the interlocks, plus any specific
970 earlier-ISA CPUs for which CPU documentation declares that the
971 instructions are really interlocked. */
972 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
973 || ISA_MIPS32R2 \
974 || ISA_MIPS64 \
975 || ISA_MIPS64R2 \
976 || TARGET_MIPS5500 \
977 || TARGET_LOONGSON_2EF)
978
979 /* ISA includes synci, jr.hb and jalr.hb. */
980 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
981 || ISA_MIPS64R2) \
982 && !TARGET_MIPS16)
983
984 /* ISA includes sync. */
985 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
986 #define GENERATE_SYNC \
987 (target_flags_explicit & MASK_LLSC \
988 ? TARGET_LLSC && !TARGET_MIPS16 \
989 : ISA_HAS_SYNC)
990
991 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
992 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
993 instructions. */
994 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
995 #define GENERATE_LL_SC \
996 (target_flags_explicit & MASK_LLSC \
997 ? TARGET_LLSC && !TARGET_MIPS16 \
998 : ISA_HAS_LL_SC)
999 \f
1000 /* Add -G xx support. */
1001
1002 #undef SWITCH_TAKES_ARG
1003 #define SWITCH_TAKES_ARG(CHAR) \
1004 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1005
1006 #define OVERRIDE_OPTIONS mips_override_options ()
1007
1008 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1009
1010 /* Show we can debug even without a frame pointer. */
1011 #define CAN_DEBUG_WITHOUT_FP
1012 \f
1013 /* Tell collect what flags to pass to nm. */
1014 #ifndef NM_FLAGS
1015 #define NM_FLAGS "-Bn"
1016 #endif
1017
1018 \f
1019 #ifndef MIPS_ABI_DEFAULT
1020 #define MIPS_ABI_DEFAULT ABI_32
1021 #endif
1022
1023 /* Use the most portable ABI flag for the ASM specs. */
1024
1025 #if MIPS_ABI_DEFAULT == ABI_32
1026 #define MULTILIB_ABI_DEFAULT "mabi=32"
1027 #endif
1028
1029 #if MIPS_ABI_DEFAULT == ABI_O64
1030 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1031 #endif
1032
1033 #if MIPS_ABI_DEFAULT == ABI_N32
1034 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1035 #endif
1036
1037 #if MIPS_ABI_DEFAULT == ABI_64
1038 #define MULTILIB_ABI_DEFAULT "mabi=64"
1039 #endif
1040
1041 #if MIPS_ABI_DEFAULT == ABI_EABI
1042 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1043 #endif
1044
1045 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1046 to the assembler. It may be overridden by subtargets. */
1047 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1048 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1049 %{noasmopt:-O0} \
1050 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1051 #endif
1052
1053 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1054 the assembler. It may be overridden by subtargets.
1055
1056 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1057 COFF debugging info. */
1058
1059 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1060 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1061 %{g} %{g0} %{g1} %{g2} %{g3} \
1062 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1063 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1064 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1065 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1066 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1067 #endif
1068
1069 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1070 overridden by subtargets. */
1071
1072 #ifndef SUBTARGET_ASM_SPEC
1073 #define SUBTARGET_ASM_SPEC ""
1074 #endif
1075
1076 #undef ASM_SPEC
1077 #define ASM_SPEC "\
1078 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1079 %{mips32*} %{mips64*} \
1080 %{mips16} %{mno-mips16:-no-mips16} \
1081 %{mips3d} %{mno-mips3d:-no-mips3d} \
1082 %{mdmx} %{mno-mdmx:-no-mdmx} \
1083 %{mdsp} %{mno-dsp} \
1084 %{mdspr2} %{mno-dspr2} \
1085 %{msmartmips} %{mno-smartmips} \
1086 %{mmt} %{mno-mt} \
1087 %{mfix-vr4120} %{mfix-vr4130} \
1088 %(subtarget_asm_optimizing_spec) \
1089 %(subtarget_asm_debugging_spec) \
1090 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1091 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1092 %{mfp32} %{mfp64} \
1093 %{mshared} %{mno-shared} \
1094 %{msym32} %{mno-sym32} \
1095 %{mtune=*} %{v} \
1096 %(subtarget_asm_spec)"
1097
1098 /* Extra switches sometimes passed to the linker. */
1099 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1100 will interpret it as a -b option. */
1101
1102 #ifndef LINK_SPEC
1103 #define LINK_SPEC "\
1104 %(endian_spec) \
1105 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1106 %{bestGnum} %{shared} %{non_shared}"
1107 #endif /* LINK_SPEC defined */
1108
1109
1110 /* Specs for the compiler proper */
1111
1112 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1113 overridden by subtargets. */
1114 #ifndef SUBTARGET_CC1_SPEC
1115 #define SUBTARGET_CC1_SPEC ""
1116 #endif
1117
1118 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1119
1120 #undef CC1_SPEC
1121 #define CC1_SPEC "\
1122 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1123 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1124 %{save-temps: } \
1125 %(subtarget_cc1_spec)"
1126
1127 /* Preprocessor specs. */
1128
1129 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1130 overridden by subtargets. */
1131 #ifndef SUBTARGET_CPP_SPEC
1132 #define SUBTARGET_CPP_SPEC ""
1133 #endif
1134
1135 #define CPP_SPEC "%(subtarget_cpp_spec)"
1136
1137 /* This macro defines names of additional specifications to put in the specs
1138 that can be used in various specifications like CC1_SPEC. Its definition
1139 is an initializer with a subgrouping for each command option.
1140
1141 Each subgrouping contains a string constant, that defines the
1142 specification name, and a string constant that used by the GCC driver
1143 program.
1144
1145 Do not define this macro if it does not need to do anything. */
1146
1147 #define EXTRA_SPECS \
1148 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1149 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1150 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1151 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1152 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1153 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1154 { "endian_spec", ENDIAN_SPEC }, \
1155 SUBTARGET_EXTRA_SPECS
1156
1157 #ifndef SUBTARGET_EXTRA_SPECS
1158 #define SUBTARGET_EXTRA_SPECS
1159 #endif
1160 \f
1161 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1162 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1163
1164 #ifndef PREFERRED_DEBUGGING_TYPE
1165 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1166 #endif
1167
1168 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1169
1170 /* By default, turn on GDB extensions. */
1171 #define DEFAULT_GDB_EXTENSIONS 1
1172
1173 /* Local compiler-generated symbols must have a prefix that the assembler
1174 understands. By default, this is $, although some targets (e.g.,
1175 NetBSD-ELF) need to override this. */
1176
1177 #ifndef LOCAL_LABEL_PREFIX
1178 #define LOCAL_LABEL_PREFIX "$"
1179 #endif
1180
1181 /* By default on the mips, external symbols do not have an underscore
1182 prepended, but some targets (e.g., NetBSD) require this. */
1183
1184 #ifndef USER_LABEL_PREFIX
1185 #define USER_LABEL_PREFIX ""
1186 #endif
1187
1188 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1189 since the length can run past this up to a continuation point. */
1190 #undef DBX_CONTIN_LENGTH
1191 #define DBX_CONTIN_LENGTH 1500
1192
1193 /* How to renumber registers for dbx and gdb. */
1194 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1195
1196 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1197 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1198
1199 /* The DWARF 2 CFA column which tracks the return address. */
1200 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1201
1202 /* Before the prologue, RA lives in r31. */
1203 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1204
1205 /* Describe how we implement __builtin_eh_return. */
1206 #define EH_RETURN_DATA_REGNO(N) \
1207 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1208
1209 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1210
1211 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1212 The default for this in 64-bit mode is 8, which causes problems with
1213 SFmode register saves. */
1214 #define DWARF_CIE_DATA_ALIGNMENT -4
1215
1216 /* Correct the offset of automatic variables and arguments. Note that
1217 the MIPS debug format wants all automatic variables and arguments
1218 to be in terms of the virtual frame pointer (stack pointer before
1219 any adjustment in the function), while the MIPS 3.0 linker wants
1220 the frame pointer to be the stack pointer after the initial
1221 adjustment. */
1222
1223 #define DEBUGGER_AUTO_OFFSET(X) \
1224 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1225 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1226 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1227 \f
1228 /* Target machine storage layout */
1229
1230 #define BITS_BIG_ENDIAN 0
1231 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1232 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1233
1234 /* Define this to set the endianness to use in libgcc2.c, which can
1235 not depend on target_flags. */
1236 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1237 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1238 #else
1239 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1240 #endif
1241
1242 #define MAX_BITS_PER_WORD 64
1243
1244 /* Width of a word, in units (bytes). */
1245 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1246 #ifndef IN_LIBGCC2
1247 #define MIN_UNITS_PER_WORD 4
1248 #endif
1249
1250 /* For MIPS, width of a floating point register. */
1251 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1252
1253 /* The number of consecutive floating-point registers needed to store the
1254 largest format supported by the FPU. */
1255 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1256
1257 /* The number of consecutive floating-point registers needed to store the
1258 smallest format supported by the FPU. */
1259 #define MIN_FPRS_PER_FMT \
1260 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1261 ? 1 : MAX_FPRS_PER_FMT)
1262
1263 /* The largest size of value that can be held in floating-point
1264 registers and moved with a single instruction. */
1265 #define UNITS_PER_HWFPVALUE \
1266 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1267
1268 /* The largest size of value that can be held in floating-point
1269 registers. */
1270 #define UNITS_PER_FPVALUE \
1271 (TARGET_SOFT_FLOAT_ABI ? 0 \
1272 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1273 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1274
1275 /* The number of bytes in a double. */
1276 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1277
1278 #define UNITS_PER_SIMD_WORD(MODE) \
1279 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1280
1281 /* Set the sizes of the core types. */
1282 #define SHORT_TYPE_SIZE 16
1283 #define INT_TYPE_SIZE 32
1284 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1285 #define LONG_LONG_TYPE_SIZE 64
1286
1287 #define FLOAT_TYPE_SIZE 32
1288 #define DOUBLE_TYPE_SIZE 64
1289 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1290
1291 /* Define the sizes of fixed-point types. */
1292 #define SHORT_FRACT_TYPE_SIZE 8
1293 #define FRACT_TYPE_SIZE 16
1294 #define LONG_FRACT_TYPE_SIZE 32
1295 #define LONG_LONG_FRACT_TYPE_SIZE 64
1296
1297 #define SHORT_ACCUM_TYPE_SIZE 16
1298 #define ACCUM_TYPE_SIZE 32
1299 #define LONG_ACCUM_TYPE_SIZE 64
1300 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1301 doesn't support 128-bit integers for MIPS32 currently. */
1302 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1303
1304 /* long double is not a fixed mode, but the idea is that, if we
1305 support long double, we also want a 128-bit integer type. */
1306 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1307
1308 #ifdef IN_LIBGCC2
1309 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1310 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1311 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1312 # else
1313 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1314 # endif
1315 #endif
1316
1317 /* Width in bits of a pointer. */
1318 #ifndef POINTER_SIZE
1319 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1320 #endif
1321
1322 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1323 #define PARM_BOUNDARY BITS_PER_WORD
1324
1325 /* Allocation boundary (in *bits*) for the code of a function. */
1326 #define FUNCTION_BOUNDARY 32
1327
1328 /* Alignment of field after `int : 0' in a structure. */
1329 #define EMPTY_FIELD_BOUNDARY 32
1330
1331 /* Every structure's size must be a multiple of this. */
1332 /* 8 is observed right on a DECstation and on riscos 4.02. */
1333 #define STRUCTURE_SIZE_BOUNDARY 8
1334
1335 /* There is no point aligning anything to a rounder boundary than this. */
1336 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1337
1338 /* All accesses must be aligned. */
1339 #define STRICT_ALIGNMENT 1
1340
1341 /* Define this if you wish to imitate the way many other C compilers
1342 handle alignment of bitfields and the structures that contain
1343 them.
1344
1345 The behavior is that the type written for a bit-field (`int',
1346 `short', or other integer type) imposes an alignment for the
1347 entire structure, as if the structure really did contain an
1348 ordinary field of that type. In addition, the bit-field is placed
1349 within the structure so that it would fit within such a field,
1350 not crossing a boundary for it.
1351
1352 Thus, on most machines, a bit-field whose type is written as `int'
1353 would not cross a four-byte boundary, and would force four-byte
1354 alignment for the whole structure. (The alignment used may not
1355 be four bytes; it is controlled by the other alignment
1356 parameters.)
1357
1358 If the macro is defined, its definition should be a C expression;
1359 a nonzero value for the expression enables this behavior. */
1360
1361 #define PCC_BITFIELD_TYPE_MATTERS 1
1362
1363 /* If defined, a C expression to compute the alignment given to a
1364 constant that is being placed in memory. CONSTANT is the constant
1365 and ALIGN is the alignment that the object would ordinarily have.
1366 The value of this macro is used instead of that alignment to align
1367 the object.
1368
1369 If this macro is not defined, then ALIGN is used.
1370
1371 The typical use of this macro is to increase alignment for string
1372 constants to be word aligned so that `strcpy' calls that copy
1373 constants can be done inline. */
1374
1375 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1376 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1377 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1378
1379 /* If defined, a C expression to compute the alignment for a static
1380 variable. TYPE is the data type, and ALIGN is the alignment that
1381 the object would ordinarily have. The value of this macro is used
1382 instead of that alignment to align the object.
1383
1384 If this macro is not defined, then ALIGN is used.
1385
1386 One use of this macro is to increase alignment of medium-size
1387 data to make it all fit in fewer cache lines. Another is to
1388 cause character arrays to be word-aligned so that `strcpy' calls
1389 that copy constants to character arrays can be done inline. */
1390
1391 #undef DATA_ALIGNMENT
1392 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1393 ((((ALIGN) < BITS_PER_WORD) \
1394 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1395 || TREE_CODE (TYPE) == UNION_TYPE \
1396 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1397
1398 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1399 character arrays to be word-aligned so that `strcpy' calls that copy
1400 constants to character arrays can be done inline, and 'strcmp' can be
1401 optimised to use word loads. */
1402 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1403 DATA_ALIGNMENT (TYPE, ALIGN)
1404
1405 #define PAD_VARARGS_DOWN \
1406 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1407
1408 /* Define if operations between registers always perform the operation
1409 on the full register even if a narrower mode is specified. */
1410 #define WORD_REGISTER_OPERATIONS
1411
1412 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1413 moves. All other references are zero extended. */
1414 #define LOAD_EXTEND_OP(MODE) \
1415 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1416 ? SIGN_EXTEND : ZERO_EXTEND)
1417
1418 /* Define this macro if it is advisable to hold scalars in registers
1419 in a wider mode than that declared by the program. In such cases,
1420 the value is constrained to be within the bounds of the declared
1421 type, but kept valid in the wider mode. The signedness of the
1422 extension may differ from that of the type. */
1423
1424 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1425 if (GET_MODE_CLASS (MODE) == MODE_INT \
1426 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1427 { \
1428 if ((MODE) == SImode) \
1429 (UNSIGNEDP) = 0; \
1430 (MODE) = Pmode; \
1431 }
1432
1433 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1434 Extensions of pointers to word_mode must be signed. */
1435 #define POINTERS_EXTEND_UNSIGNED false
1436
1437 /* Define if loading short immediate values into registers sign extends. */
1438 #define SHORT_IMMEDIATES_SIGN_EXTEND
1439
1440 /* The [d]clz instructions have the natural values at 0. */
1441
1442 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1443 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1444 \f
1445 /* Standard register usage. */
1446
1447 /* Number of hardware registers. We have:
1448
1449 - 32 integer registers
1450 - 32 floating point registers
1451 - 8 condition code registers
1452 - 2 accumulator registers (hi and lo)
1453 - 32 registers each for coprocessors 0, 2 and 3
1454 - 3 fake registers:
1455 - ARG_POINTER_REGNUM
1456 - FRAME_POINTER_REGNUM
1457 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1458 - 3 dummy entries that were used at various times in the past.
1459 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1460 - 6 DSP control registers */
1461
1462 #define FIRST_PSEUDO_REGISTER 188
1463
1464 /* By default, fix the kernel registers ($26 and $27), the global
1465 pointer ($28) and the stack pointer ($29). This can change
1466 depending on the command-line options.
1467
1468 Regarding coprocessor registers: without evidence to the contrary,
1469 it's best to assume that each coprocessor register has a unique
1470 use. This can be overridden, in, e.g., mips_override_options or
1471 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1472 for a particular target. */
1473
1474 #define FIXED_REGISTERS \
1475 { \
1476 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1477 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1478 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1479 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1480 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1481 /* COP0 registers */ \
1482 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1483 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1484 /* COP2 registers */ \
1485 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1486 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1487 /* COP3 registers */ \
1488 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1489 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1490 /* 6 DSP accumulator registers & 6 control registers */ \
1491 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1492 }
1493
1494
1495 /* Set up this array for o32 by default.
1496
1497 Note that we don't mark $31 as a call-clobbered register. The idea is
1498 that it's really the call instructions themselves which clobber $31.
1499 We don't care what the called function does with it afterwards.
1500
1501 This approach makes it easier to implement sibcalls. Unlike normal
1502 calls, sibcalls don't clobber $31, so the register reaches the
1503 called function in tact. EPILOGUE_USES says that $31 is useful
1504 to the called function. */
1505
1506 #define CALL_USED_REGISTERS \
1507 { \
1508 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1509 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1510 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1511 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1512 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1513 /* COP0 registers */ \
1514 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1515 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1516 /* COP2 registers */ \
1517 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1518 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1519 /* COP3 registers */ \
1520 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1521 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1522 /* 6 DSP accumulator registers & 6 control registers */ \
1523 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1524 }
1525
1526
1527 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1528
1529 #define CALL_REALLY_USED_REGISTERS \
1530 { /* General registers. */ \
1531 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1532 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1533 /* Floating-point registers. */ \
1534 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1535 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1536 /* Others. */ \
1537 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1538 /* COP0 registers */ \
1539 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1540 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1541 /* COP2 registers */ \
1542 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1543 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1544 /* COP3 registers */ \
1545 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1547 /* 6 DSP accumulator registers & 6 control registers */ \
1548 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1549 }
1550
1551 /* Internal macros to classify a register number as to whether it's a
1552 general purpose register, a floating point register, a
1553 multiply/divide register, or a status register. */
1554
1555 #define GP_REG_FIRST 0
1556 #define GP_REG_LAST 31
1557 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1558 #define GP_DBX_FIRST 0
1559
1560 #define FP_REG_FIRST 32
1561 #define FP_REG_LAST 63
1562 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1563 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1564
1565 #define MD_REG_FIRST 64
1566 #define MD_REG_LAST 65
1567 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1568 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1569
1570 /* The DWARF 2 CFA column which tracks the return address from a
1571 signal handler context. This means that to maintain backwards
1572 compatibility, no hard register can be assigned this column if it
1573 would need to be handled by the DWARF unwinder. */
1574 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1575
1576 #define ST_REG_FIRST 67
1577 #define ST_REG_LAST 74
1578 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1579
1580
1581 /* FIXME: renumber. */
1582 #define COP0_REG_FIRST 80
1583 #define COP0_REG_LAST 111
1584 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1585
1586 #define COP2_REG_FIRST 112
1587 #define COP2_REG_LAST 143
1588 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1589
1590 #define COP3_REG_FIRST 144
1591 #define COP3_REG_LAST 175
1592 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1593 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1594 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1595
1596 #define DSP_ACC_REG_FIRST 176
1597 #define DSP_ACC_REG_LAST 181
1598 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1599
1600 #define AT_REGNUM (GP_REG_FIRST + 1)
1601 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1602 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1603
1604 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1605 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1606 should be used instead. */
1607 #define FPSW_REGNUM ST_REG_FIRST
1608
1609 #define GP_REG_P(REGNO) \
1610 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1611 #define M16_REG_P(REGNO) \
1612 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1613 #define FP_REG_P(REGNO) \
1614 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1615 #define MD_REG_P(REGNO) \
1616 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1617 #define ST_REG_P(REGNO) \
1618 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1619 #define COP0_REG_P(REGNO) \
1620 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1621 #define COP2_REG_P(REGNO) \
1622 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1623 #define COP3_REG_P(REGNO) \
1624 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1625 #define ALL_COP_REG_P(REGNO) \
1626 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1627 /* Test if REGNO is one of the 6 new DSP accumulators. */
1628 #define DSP_ACC_REG_P(REGNO) \
1629 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1630 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1631 #define ACC_REG_P(REGNO) \
1632 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1633
1634 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1635
1636 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1637 to initialize the mips16 gp pseudo register. */
1638 #define CONST_GP_P(X) \
1639 (GET_CODE (X) == CONST \
1640 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1641 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1642
1643 /* Return coprocessor number from register number. */
1644
1645 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1646 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1647 : COP3_REG_P (REGNO) ? '3' : '?')
1648
1649
1650 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1651
1652 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1653 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1654
1655 #define MODES_TIEABLE_P mips_modes_tieable_p
1656
1657 /* Register to use for pushing function arguments. */
1658 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1659
1660 /* These two registers don't really exist: they get eliminated to either
1661 the stack or hard frame pointer. */
1662 #define ARG_POINTER_REGNUM 77
1663 #define FRAME_POINTER_REGNUM 78
1664
1665 /* $30 is not available on the mips16, so we use $17 as the frame
1666 pointer. */
1667 #define HARD_FRAME_POINTER_REGNUM \
1668 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1669
1670 #define FRAME_POINTER_REQUIRED (mips_frame_pointer_required ())
1671
1672 /* Register in which static-chain is passed to a function. */
1673 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1674
1675 /* Registers used as temporaries in prologue/epilogue code:
1676
1677 - If a MIPS16 PIC function needs access to _gp, it first loads
1678 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1679
1680 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1681 register. The register must not conflict with MIPS16_PIC_TEMP.
1682
1683 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1684 register.
1685
1686 If we're generating MIPS16 code, these registers must come from the
1687 core set of 8. The prologue registers mustn't conflict with any
1688 incoming arguments, the static chain pointer, or the frame pointer.
1689 The epilogue temporary mustn't conflict with the return registers,
1690 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1691 or the EH data registers. */
1692
1693 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1694 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1695 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1696
1697 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1698 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1699 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1700
1701 /* Define this macro if it is as good or better to call a constant
1702 function address than to call an address kept in a register. */
1703 #define NO_FUNCTION_CSE 1
1704
1705 /* The ABI-defined global pointer. Sometimes we use a different
1706 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1707 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1708
1709 /* We normally use $28 as the global pointer. However, when generating
1710 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1711 register instead. They can then avoid saving and restoring $28
1712 and perhaps avoid using a frame at all.
1713
1714 When a leaf function uses something other than $28, mips_expand_prologue
1715 will modify pic_offset_table_rtx in place. Take the register number
1716 from there after reload. */
1717 #define PIC_OFFSET_TABLE_REGNUM \
1718 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1719
1720 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1721 \f
1722 /* Define the classes of registers for register constraints in the
1723 machine description. Also define ranges of constants.
1724
1725 One of the classes must always be named ALL_REGS and include all hard regs.
1726 If there is more than one class, another class must be named NO_REGS
1727 and contain no registers.
1728
1729 The name GENERAL_REGS must be the name of a class (or an alias for
1730 another name such as ALL_REGS). This is the class of registers
1731 that is allowed by "g" or "r" in a register constraint.
1732 Also, registers outside this class are allocated only when
1733 instructions express preferences for them.
1734
1735 The classes must be numbered in nondecreasing order; that is,
1736 a larger-numbered class must never be contained completely
1737 in a smaller-numbered class.
1738
1739 For any two classes, it is very desirable that there be another
1740 class that represents their union. */
1741
1742 enum reg_class
1743 {
1744 NO_REGS, /* no registers in set */
1745 M16_REGS, /* mips16 directly accessible registers */
1746 T_REG, /* mips16 T register ($24) */
1747 M16_T_REGS, /* mips16 registers plus T register */
1748 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1749 V1_REG, /* Register $v1 ($3) used for TLS access. */
1750 LEA_REGS, /* Every GPR except $25 */
1751 GR_REGS, /* integer registers */
1752 FP_REGS, /* floating point registers */
1753 MD0_REG, /* first multiply/divide register */
1754 MD1_REG, /* second multiply/divide register */
1755 MD_REGS, /* multiply/divide registers (hi/lo) */
1756 COP0_REGS, /* generic coprocessor classes */
1757 COP2_REGS,
1758 COP3_REGS,
1759 HI_AND_GR_REGS, /* union classes */
1760 LO_AND_GR_REGS,
1761 HI_AND_FP_REGS,
1762 COP0_AND_GR_REGS,
1763 COP2_AND_GR_REGS,
1764 COP3_AND_GR_REGS,
1765 ALL_COP_REGS,
1766 ALL_COP_AND_GR_REGS,
1767 ST_REGS, /* status registers (fp status) */
1768 DSP_ACC_REGS, /* DSP accumulator registers */
1769 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1770 ALL_REGS, /* all registers */
1771 LIM_REG_CLASSES /* max value + 1 */
1772 };
1773
1774 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1775
1776 #define GENERAL_REGS GR_REGS
1777
1778 /* An initializer containing the names of the register classes as C
1779 string constants. These names are used in writing some of the
1780 debugging dumps. */
1781
1782 #define REG_CLASS_NAMES \
1783 { \
1784 "NO_REGS", \
1785 "M16_REGS", \
1786 "T_REG", \
1787 "M16_T_REGS", \
1788 "PIC_FN_ADDR_REG", \
1789 "V1_REG", \
1790 "LEA_REGS", \
1791 "GR_REGS", \
1792 "FP_REGS", \
1793 "MD0_REG", \
1794 "MD1_REG", \
1795 "MD_REGS", \
1796 /* coprocessor registers */ \
1797 "COP0_REGS", \
1798 "COP2_REGS", \
1799 "COP3_REGS", \
1800 "HI_AND_GR_REGS", \
1801 "LO_AND_GR_REGS", \
1802 "HI_AND_FP_REGS", \
1803 "COP0_AND_GR_REGS", \
1804 "COP2_AND_GR_REGS", \
1805 "COP3_AND_GR_REGS", \
1806 "ALL_COP_REGS", \
1807 "ALL_COP_AND_GR_REGS", \
1808 "ST_REGS", \
1809 "DSP_ACC_REGS", \
1810 "ACC_REGS", \
1811 "ALL_REGS" \
1812 }
1813
1814 /* An initializer containing the contents of the register classes,
1815 as integers which are bit masks. The Nth integer specifies the
1816 contents of class N. The way the integer MASK is interpreted is
1817 that register R is in the class if `MASK & (1 << R)' is 1.
1818
1819 When the machine has more than 32 registers, an integer does not
1820 suffice. Then the integers are replaced by sub-initializers,
1821 braced groupings containing several integers. Each
1822 sub-initializer must be suitable as an initializer for the type
1823 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1824
1825 #define REG_CLASS_CONTENTS \
1826 { \
1827 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1828 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1829 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1830 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1831 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1832 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1833 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1834 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1835 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1836 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1837 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1838 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1839 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1840 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1841 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1842 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1843 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1844 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1845 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1846 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1847 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1848 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1849 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1850 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1851 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1852 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1853 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1854 }
1855
1856
1857 /* A C expression whose value is a register class containing hard
1858 register REGNO. In general there is more that one such class;
1859 choose a class which is "minimal", meaning that no smaller class
1860 also contains the register. */
1861
1862 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1863
1864 /* A macro whose definition is the name of the class to which a
1865 valid base register must belong. A base register is one used in
1866 an address which is the register value plus a displacement. */
1867
1868 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1869
1870 /* A macro whose definition is the name of the class to which a
1871 valid index register must belong. An index register is one used
1872 in an address where its value is either multiplied by a scale
1873 factor or added to another register (as well as added to a
1874 displacement). */
1875
1876 #define INDEX_REG_CLASS NO_REGS
1877
1878 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1879 registers explicitly used in the rtl to be used as spill registers
1880 but prevents the compiler from extending the lifetime of these
1881 registers. */
1882
1883 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1884
1885 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1886 is the default value (allocate the registers in numeric order). We
1887 define it just so that we can override it for the mips16 target in
1888 ORDER_REGS_FOR_LOCAL_ALLOC. */
1889
1890 #define REG_ALLOC_ORDER \
1891 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1892 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1893 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1894 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1895 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1896 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1897 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1898 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1899 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1900 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1901 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1902 176,177,178,179,180,181,182,183,184,185,186,187 \
1903 }
1904
1905 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1906 to be rearranged based on a particular function. On the mips16, we
1907 want to allocate $24 (T_REG) before other registers for
1908 instructions for which it is possible. */
1909
1910 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1911
1912 /* True if VALUE is an unsigned 6-bit number. */
1913
1914 #define UIMM6_OPERAND(VALUE) \
1915 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1916
1917 /* True if VALUE is a signed 10-bit number. */
1918
1919 #define IMM10_OPERAND(VALUE) \
1920 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1921
1922 /* True if VALUE is a signed 16-bit number. */
1923
1924 #define SMALL_OPERAND(VALUE) \
1925 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1926
1927 /* True if VALUE is an unsigned 16-bit number. */
1928
1929 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1930 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1931
1932 /* True if VALUE can be loaded into a register using LUI. */
1933
1934 #define LUI_OPERAND(VALUE) \
1935 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1936 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1937
1938 /* Return a value X with the low 16 bits clear, and such that
1939 VALUE - X is a signed 16-bit value. */
1940
1941 #define CONST_HIGH_PART(VALUE) \
1942 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1943
1944 #define CONST_LOW_PART(VALUE) \
1945 ((VALUE) - CONST_HIGH_PART (VALUE))
1946
1947 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1948 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1949 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1950
1951 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1952 mips_preferred_reload_class (X, CLASS)
1953
1954 /* The HI and LO registers can only be reloaded via the general
1955 registers. Condition code registers can only be loaded to the
1956 general registers, and from the floating point registers. */
1957
1958 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1959 mips_secondary_reload_class (CLASS, MODE, X, true)
1960 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1961 mips_secondary_reload_class (CLASS, MODE, X, false)
1962
1963 /* Return the maximum number of consecutive registers
1964 needed to represent mode MODE in a register of class CLASS. */
1965
1966 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1967
1968 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1969 mips_cannot_change_mode_class (FROM, TO, CLASS)
1970 \f
1971 /* Stack layout; function entry, exit and calling. */
1972
1973 #define STACK_GROWS_DOWNWARD
1974
1975 /* The offset of the first local variable from the beginning of the frame.
1976 See mips_compute_frame_info for details about the frame layout. */
1977
1978 #define STARTING_FRAME_OFFSET \
1979 (crtl->outgoing_args_size \
1980 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1981
1982 #define RETURN_ADDR_RTX mips_return_addr
1983
1984 /* Mask off the MIPS16 ISA bit in unwind addresses.
1985
1986 The reason for this is a little subtle. When unwinding a call,
1987 we are given the call's return address, which on most targets
1988 is the address of the following instruction. However, what we
1989 actually want to find is the EH region for the call itself.
1990 The target-independent unwind code therefore searches for "RA - 1".
1991
1992 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
1993 RA - 1 is therefore the real (even-valued) start of the return
1994 instruction. EH region labels are usually odd-valued MIPS16 symbols
1995 too, so a search for an even address within a MIPS16 region would
1996 usually work.
1997
1998 However, there is an exception. If the end of an EH region is also
1999 the end of a function, the end label is allowed to be even. This is
2000 necessary because a following non-MIPS16 function may also need EH
2001 information for its first instruction.
2002
2003 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2004 non-ISA-encoded address. This probably isn't ideal, but it is
2005 the traditional (legacy) behavior. It is therefore only safe
2006 to search MIPS EH regions for an _odd-valued_ address.
2007
2008 Masking off the ISA bit means that the target-independent code
2009 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2010 #define MASK_RETURN_ADDR GEN_INT (-2)
2011
2012
2013 /* Similarly, don't use the least-significant bit to tell pointers to
2014 code from vtable index. */
2015
2016 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2017
2018 /* The eliminations to $17 are only used for mips16 code. See the
2019 definition of HARD_FRAME_POINTER_REGNUM. */
2020
2021 #define ELIMINABLE_REGS \
2022 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2023 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2024 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2025 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2026 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2027 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2028
2029 /* Make sure that we're not trying to eliminate to the wrong hard frame
2030 pointer. */
2031 #define CAN_ELIMINATE(FROM, TO) \
2032 ((TO) == HARD_FRAME_POINTER_REGNUM || (TO) == STACK_POINTER_REGNUM)
2033
2034 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2035 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2036
2037 /* Allocate stack space for arguments at the beginning of each function. */
2038 #define ACCUMULATE_OUTGOING_ARGS 1
2039
2040 /* The argument pointer always points to the first argument. */
2041 #define FIRST_PARM_OFFSET(FNDECL) 0
2042
2043 /* o32 and o64 reserve stack space for all argument registers. */
2044 #define REG_PARM_STACK_SPACE(FNDECL) \
2045 (TARGET_OLDABI \
2046 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2047 : 0)
2048
2049 /* Define this if it is the responsibility of the caller to
2050 allocate the area reserved for arguments passed in registers.
2051 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2052 of this macro is to determine whether the space is included in
2053 `crtl->outgoing_args_size'. */
2054 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2055
2056 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2057 \f
2058 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2059
2060 /* Symbolic macros for the registers used to return integer and floating
2061 point values. */
2062
2063 #define GP_RETURN (GP_REG_FIRST + 2)
2064 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2065
2066 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2067
2068 /* Symbolic macros for the first/last argument registers. */
2069
2070 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2071 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2072 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2073 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2074
2075 #define LIBCALL_VALUE(MODE) \
2076 mips_function_value (NULL_TREE, MODE)
2077
2078 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2079 mips_function_value (VALTYPE, VOIDmode)
2080
2081 /* 1 if N is a possible register number for a function value.
2082 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2083 Currently, R2 and F0 are only implemented here (C has no complex type) */
2084
2085 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2086 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2087 && (N) == FP_RETURN + 2))
2088
2089 /* 1 if N is a possible register number for function argument passing.
2090 We have no FP argument registers when soft-float. When FP registers
2091 are 32 bits, we can't directly reference the odd numbered ones. */
2092
2093 #define FUNCTION_ARG_REGNO_P(N) \
2094 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2095 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2096 && !fixed_regs[N])
2097 \f
2098 /* This structure has to cope with two different argument allocation
2099 schemes. Most MIPS ABIs view the arguments as a structure, of which
2100 the first N words go in registers and the rest go on the stack. If I
2101 < N, the Ith word might go in Ith integer argument register or in a
2102 floating-point register. For these ABIs, we only need to remember
2103 the offset of the current argument into the structure.
2104
2105 The EABI instead allocates the integer and floating-point arguments
2106 separately. The first N words of FP arguments go in FP registers,
2107 the rest go on the stack. Likewise, the first N words of the other
2108 arguments go in integer registers, and the rest go on the stack. We
2109 need to maintain three counts: the number of integer registers used,
2110 the number of floating-point registers used, and the number of words
2111 passed on the stack.
2112
2113 We could keep separate information for the two ABIs (a word count for
2114 the standard ABIs, and three separate counts for the EABI). But it
2115 seems simpler to view the standard ABIs as forms of EABI that do not
2116 allocate floating-point registers.
2117
2118 So for the standard ABIs, the first N words are allocated to integer
2119 registers, and mips_function_arg decides on an argument-by-argument
2120 basis whether that argument should really go in an integer register,
2121 or in a floating-point one. */
2122
2123 typedef struct mips_args {
2124 /* Always true for varargs functions. Otherwise true if at least
2125 one argument has been passed in an integer register. */
2126 int gp_reg_found;
2127
2128 /* The number of arguments seen so far. */
2129 unsigned int arg_number;
2130
2131 /* The number of integer registers used so far. For all ABIs except
2132 EABI, this is the number of words that have been added to the
2133 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2134 unsigned int num_gprs;
2135
2136 /* For EABI, the number of floating-point registers used so far. */
2137 unsigned int num_fprs;
2138
2139 /* The number of words passed on the stack. */
2140 unsigned int stack_words;
2141
2142 /* On the mips16, we need to keep track of which floating point
2143 arguments were passed in general registers, but would have been
2144 passed in the FP regs if this were a 32-bit function, so that we
2145 can move them to the FP regs if we wind up calling a 32-bit
2146 function. We record this information in fp_code, encoded in base
2147 four. A zero digit means no floating point argument, a one digit
2148 means an SFmode argument, and a two digit means a DFmode argument,
2149 and a three digit is not used. The low order digit is the first
2150 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2151 an SFmode argument. ??? A more sophisticated approach will be
2152 needed if MIPS_ABI != ABI_32. */
2153 int fp_code;
2154
2155 /* True if the function has a prototype. */
2156 int prototype;
2157 } CUMULATIVE_ARGS;
2158
2159 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2160 for a call to a function whose data type is FNTYPE.
2161 For a library call, FNTYPE is 0. */
2162
2163 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2164 mips_init_cumulative_args (&CUM, FNTYPE)
2165
2166 /* Update the data in CUM to advance over an argument
2167 of mode MODE and data type TYPE.
2168 (TYPE is null for libcalls where that information may not be available.) */
2169
2170 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2171 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
2172
2173 /* Determine where to put an argument to a function.
2174 Value is zero to push the argument on the stack,
2175 or a hard register in which to store the argument.
2176
2177 MODE is the argument's machine mode.
2178 TYPE is the data type of the argument (as a tree).
2179 This is null for libcalls where that information may
2180 not be available.
2181 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2182 the preceding args and about the function being called.
2183 NAMED is nonzero if this argument is a named parameter
2184 (otherwise it is an extra parameter matching an ellipsis). */
2185
2186 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2187 mips_function_arg (&CUM, MODE, TYPE, NAMED)
2188
2189 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2190
2191 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2192 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2193
2194 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2195 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2196
2197 /* True if using EABI and varargs can be passed in floating-point
2198 registers. Under these conditions, we need a more complex form
2199 of va_list, which tracks GPR, FPR and stack arguments separately. */
2200 #define EABI_FLOAT_VARARGS_P \
2201 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2202
2203 \f
2204 /* Say that the epilogue uses the return address register. Note that
2205 in the case of sibcalls, the values "used by the epilogue" are
2206 considered live at the start of the called function.
2207
2208 If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
2209 See the comment above load_call<mode> for details. */
2210 #define EPILOGUE_USES(REGNO) \
2211 ((REGNO) == 31 || (TARGET_USE_GOT && (REGNO) == GOT_VERSION_REGNUM))
2212
2213 /* Treat LOC as a byte offset from the stack pointer and round it up
2214 to the next fully-aligned offset. */
2215 #define MIPS_STACK_ALIGN(LOC) \
2216 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2217
2218 \f
2219 /* Output assembler code to FILE to increment profiler label # LABELNO
2220 for profiling a function entry. */
2221
2222 #define FUNCTION_PROFILER(FILE, LABELNO) \
2223 { \
2224 if (TARGET_MIPS16) \
2225 sorry ("mips16 function profiling"); \
2226 fprintf (FILE, "\t.set\tnoat\n"); \
2227 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2228 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2229 /* _mcount treats $2 as the static chain register. */ \
2230 if (cfun->static_chain_decl != NULL) \
2231 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[2], \
2232 reg_names[STATIC_CHAIN_REGNUM]); \
2233 if (!TARGET_NEWABI) \
2234 { \
2235 fprintf (FILE, \
2236 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2237 TARGET_64BIT ? "dsubu" : "subu", \
2238 reg_names[STACK_POINTER_REGNUM], \
2239 reg_names[STACK_POINTER_REGNUM], \
2240 Pmode == DImode ? 16 : 8); \
2241 } \
2242 fprintf (FILE, "\tjal\t_mcount\n"); \
2243 fprintf (FILE, "\t.set\tat\n"); \
2244 /* _mcount treats $2 as the static chain register. */ \
2245 if (cfun->static_chain_decl != NULL) \
2246 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], \
2247 reg_names[2]); \
2248 }
2249
2250 /* The profiler preserves all interesting registers, including $31. */
2251 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2252
2253 /* No mips port has ever used the profiler counter word, so don't emit it
2254 or the label for it. */
2255
2256 #define NO_PROFILE_COUNTERS 1
2257
2258 /* Define this macro if the code for function profiling should come
2259 before the function prologue. Normally, the profiling code comes
2260 after. */
2261
2262 /* #define PROFILE_BEFORE_PROLOGUE */
2263
2264 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2265 the stack pointer does not matter. The value is tested only in
2266 functions that have frame pointers.
2267 No definition is equivalent to always zero. */
2268
2269 #define EXIT_IGNORE_STACK 1
2270
2271 \f
2272 /* A C statement to output, on the stream FILE, assembler code for a
2273 block of data that contains the constant parts of a trampoline.
2274 This code should not include a label--the label is taken care of
2275 automatically. */
2276
2277 #define TRAMPOLINE_TEMPLATE(STREAM) \
2278 { \
2279 if (ptr_mode == DImode) \
2280 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2281 else \
2282 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2283 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2284 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2285 if (ptr_mode == DImode) \
2286 { \
2287 fprintf (STREAM, "\t.word\t0xdff90014\t\t# ld $25,20($31)\n"); \
2288 fprintf (STREAM, "\t.word\t0xdfef001c\t\t# ld $15,28($31)\n"); \
2289 } \
2290 else \
2291 { \
2292 fprintf (STREAM, "\t.word\t0x8ff90010\t\t# lw $25,16($31)\n"); \
2293 fprintf (STREAM, "\t.word\t0x8fef0014\t\t# lw $15,20($31)\n"); \
2294 } \
2295 fprintf (STREAM, "\t.word\t0x03200008\t\t# jr $25\n"); \
2296 if (ptr_mode == DImode) \
2297 { \
2298 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2299 fprintf (STREAM, "\t.word\t0x00000000\t\t# <padding>\n"); \
2300 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2301 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2302 } \
2303 else \
2304 { \
2305 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2306 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2307 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2308 } \
2309 }
2310
2311 /* A C expression for the size in bytes of the trampoline, as an
2312 integer. */
2313
2314 #define TRAMPOLINE_SIZE (ptr_mode == DImode ? 48 : 36)
2315
2316 /* Alignment required for trampolines, in bits. */
2317
2318 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2319
2320 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2321 program and data caches. */
2322
2323 #ifndef CACHE_FLUSH_FUNC
2324 #define CACHE_FLUSH_FUNC "_flush_cache"
2325 #endif
2326
2327 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2328 /* Flush both caches. We need to flush the data cache in case \
2329 the system has a write-back cache. */ \
2330 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2331 0, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2332 GEN_INT (3), TYPE_MODE (integer_type_node))
2333
2334 /* A C statement to initialize the variable parts of a trampoline.
2335 ADDR is an RTX for the address of the trampoline; FNADDR is an
2336 RTX for the address of the nested function; STATIC_CHAIN is an
2337 RTX for the static chain value that should be passed to the
2338 function when it is called. */
2339
2340 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2341 { \
2342 rtx func_addr, chain_addr, end_addr; \
2343 \
2344 func_addr = plus_constant (ADDR, ptr_mode == DImode ? 32 : 28); \
2345 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2346 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2347 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2348 end_addr = gen_reg_rtx (Pmode); \
2349 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2350 GEN_INT (TRAMPOLINE_SIZE))); \
2351 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2352 }
2353 \f
2354 /* Addressing modes, and classification of registers for them. */
2355
2356 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2357 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2358 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2359
2360 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2361 and check its validity for a certain class.
2362 We have two alternate definitions for each of them.
2363 The usual definition accepts all pseudo regs; the other rejects them all.
2364 The symbol REG_OK_STRICT causes the latter definition to be used.
2365
2366 Most source files want to accept pseudo regs in the hope that
2367 they will get allocated to the class that the insn wants them to be in.
2368 Some source files that are used after register allocation
2369 need to be strict. */
2370
2371 #ifndef REG_OK_STRICT
2372 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2373 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2374 #else
2375 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2376 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2377 #endif
2378
2379 #define REG_OK_FOR_INDEX_P(X) 0
2380
2381 \f
2382 /* Maximum number of registers that can appear in a valid memory address. */
2383
2384 #define MAX_REGS_PER_ADDRESS 1
2385
2386 #ifdef REG_OK_STRICT
2387 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2388 { \
2389 if (mips_legitimate_address_p (MODE, X, 1)) \
2390 goto ADDR; \
2391 }
2392 #else
2393 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2394 { \
2395 if (mips_legitimate_address_p (MODE, X, 0)) \
2396 goto ADDR; \
2397 }
2398 #endif
2399
2400 /* Check for constness inline but use mips_legitimate_address_p
2401 to check whether a constant really is an address. */
2402
2403 #define CONSTANT_ADDRESS_P(X) \
2404 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2405
2406 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2407
2408 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2409 do { \
2410 if (mips_legitimize_address (&(X), MODE)) \
2411 goto WIN; \
2412 } while (0)
2413
2414
2415 /* A C statement or compound statement with a conditional `goto
2416 LABEL;' executed if memory address X (an RTX) can have different
2417 meanings depending on the machine mode of the memory reference it
2418 is used for.
2419
2420 Autoincrement and autodecrement addresses typically have
2421 mode-dependent effects because the amount of the increment or
2422 decrement is the size of the operand being addressed. Some
2423 machines have other mode-dependent addresses. Many RISC machines
2424 have no mode-dependent addresses.
2425
2426 You may assume that ADDR is a valid address for the machine. */
2427
2428 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2429
2430 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2431 'the start of the function that this code is output in'. */
2432
2433 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2434 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2435 asm_fprintf ((FILE), "%U%s", \
2436 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2437 else \
2438 asm_fprintf ((FILE), "%U%s", (NAME))
2439 \f
2440 /* Flag to mark a function decl symbol that requires a long call. */
2441 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2442 #define SYMBOL_REF_LONG_CALL_P(X) \
2443 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2444
2445 /* This flag marks functions that cannot be lazily bound. */
2446 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2447 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2448 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2449
2450 /* True if we're generating a form of MIPS16 code in which jump tables
2451 are stored in the text section and encoded as 16-bit PC-relative
2452 offsets. This is only possible when general text loads are allowed,
2453 since the table access itself will be an "lh" instruction. */
2454 /* ??? 16-bit offsets can overflow in large functions. */
2455 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2456
2457 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2458
2459 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2460
2461 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2462
2463 /* Define this as 1 if `char' should by default be signed; else as 0. */
2464 #ifndef DEFAULT_SIGNED_CHAR
2465 #define DEFAULT_SIGNED_CHAR 1
2466 #endif
2467
2468 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2469 we generally don't want to use them for copying arbitrary data.
2470 A single N-word move is usually the same cost as N single-word moves. */
2471 #define MOVE_MAX UNITS_PER_WORD
2472 #define MAX_MOVE_MAX 8
2473
2474 /* Define this macro as a C expression which is nonzero if
2475 accessing less than a word of memory (i.e. a `char' or a
2476 `short') is no faster than accessing a word of memory, i.e., if
2477 such access require more than one instruction or if there is no
2478 difference in cost between byte and (aligned) word loads.
2479
2480 On RISC machines, it tends to generate better code to define
2481 this as 1, since it avoids making a QI or HI mode register.
2482
2483 But, generating word accesses for -mips16 is generally bad as shifts
2484 (often extended) would be needed for byte accesses. */
2485 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2486
2487 /* Define this to be nonzero if shift instructions ignore all but the low-order
2488 few bits. */
2489 #define SHIFT_COUNT_TRUNCATED 1
2490
2491 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2492 is done just by pretending it is already truncated. */
2493 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2494 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2495
2496
2497 /* Specify the machine mode that pointers have.
2498 After generation of rtl, the compiler makes no further distinction
2499 between pointers and any other objects of this machine mode. */
2500
2501 #ifndef Pmode
2502 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2503 #endif
2504
2505 /* Give call MEMs SImode since it is the "most permissive" mode
2506 for both 32-bit and 64-bit targets. */
2507
2508 #define FUNCTION_MODE SImode
2509
2510 \f
2511 /* A C expression for the cost of moving data from a register in
2512 class FROM to one in class TO. The classes are expressed using
2513 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2514 the default; other values are interpreted relative to that.
2515
2516 It is not required that the cost always equal 2 when FROM is the
2517 same as TO; on some machines it is expensive to move between
2518 registers if they are not general registers.
2519
2520 If reload sees an insn consisting of a single `set' between two
2521 hard registers, and if `REGISTER_MOVE_COST' applied to their
2522 classes returns a value of 2, reload does not check to ensure
2523 that the constraints of the insn are met. Setting a cost of
2524 other than 2 will allow reload to verify that the constraints are
2525 met. You should do this if the `movM' pattern's constraints do
2526 not allow such copying. */
2527
2528 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2529 mips_register_move_cost (MODE, FROM, TO)
2530
2531 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2532 (mips_cost->memory_latency \
2533 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2534
2535 /* Define if copies to/from condition code registers should be avoided.
2536
2537 This is needed for the MIPS because reload_outcc is not complete;
2538 it needs to handle cases where the source is a general or another
2539 condition code register. */
2540 #define AVOID_CCMODE_COPIES
2541
2542 /* A C expression for the cost of a branch instruction. A value of
2543 1 is the default; other values are interpreted relative to that. */
2544
2545 #define BRANCH_COST mips_branch_cost
2546 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2547
2548 /* If defined, modifies the length assigned to instruction INSN as a
2549 function of the context in which it is used. LENGTH is an lvalue
2550 that contains the initially computed length of the insn and should
2551 be updated with the correct length of the insn. */
2552 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2553 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2554
2555 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2556 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2557 its operands. */
2558 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2559 "%*" OPCODE "%?\t" OPERANDS "%/"
2560
2561 /* Return the asm template for a call. INSN is the instruction's mnemonic
2562 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2563 of the target.
2564
2565 When generating GOT code without explicit relocation operators,
2566 all calls should use assembly macros. Otherwise, all indirect
2567 calls should use "jr" or "jalr"; we will arrange to restore $gp
2568 afterwards if necessary. Finally, we can only generate direct
2569 calls for -mabicalls by temporarily switching to non-PIC mode. */
2570 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2571 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2572 ? "%*" INSN "\t%" #OPNO "%/" \
2573 : REG_P (OPERANDS[OPNO]) \
2574 ? "%*" INSN "r\t%" #OPNO "%/" \
2575 : TARGET_ABICALLS_PIC2 \
2576 ? (".option\tpic0\n\t" \
2577 "%*" INSN "\t%" #OPNO "%/\n\t" \
2578 ".option\tpic2") \
2579 : "%*" INSN "\t%" #OPNO "%/")
2580 \f
2581 /* Control the assembler format that we output. */
2582
2583 /* Output to assembler file text saying following lines
2584 may contain character constants, extra white space, comments, etc. */
2585
2586 #ifndef ASM_APP_ON
2587 #define ASM_APP_ON " #APP\n"
2588 #endif
2589
2590 /* Output to assembler file text saying following lines
2591 no longer contain unusual constructs. */
2592
2593 #ifndef ASM_APP_OFF
2594 #define ASM_APP_OFF " #NO_APP\n"
2595 #endif
2596
2597 #define REGISTER_NAMES \
2598 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2599 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2600 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2601 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2602 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2603 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2604 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2605 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2606 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2607 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2608 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2609 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2610 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2611 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2612 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2613 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2614 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2615 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2616 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2617 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2618 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2619 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2620 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2621 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2622
2623 /* List the "software" names for each register. Also list the numerical
2624 names for $fp and $sp. */
2625
2626 #define ADDITIONAL_REGISTER_NAMES \
2627 { \
2628 { "$29", 29 + GP_REG_FIRST }, \
2629 { "$30", 30 + GP_REG_FIRST }, \
2630 { "at", 1 + GP_REG_FIRST }, \
2631 { "v0", 2 + GP_REG_FIRST }, \
2632 { "v1", 3 + GP_REG_FIRST }, \
2633 { "a0", 4 + GP_REG_FIRST }, \
2634 { "a1", 5 + GP_REG_FIRST }, \
2635 { "a2", 6 + GP_REG_FIRST }, \
2636 { "a3", 7 + GP_REG_FIRST }, \
2637 { "t0", 8 + GP_REG_FIRST }, \
2638 { "t1", 9 + GP_REG_FIRST }, \
2639 { "t2", 10 + GP_REG_FIRST }, \
2640 { "t3", 11 + GP_REG_FIRST }, \
2641 { "t4", 12 + GP_REG_FIRST }, \
2642 { "t5", 13 + GP_REG_FIRST }, \
2643 { "t6", 14 + GP_REG_FIRST }, \
2644 { "t7", 15 + GP_REG_FIRST }, \
2645 { "s0", 16 + GP_REG_FIRST }, \
2646 { "s1", 17 + GP_REG_FIRST }, \
2647 { "s2", 18 + GP_REG_FIRST }, \
2648 { "s3", 19 + GP_REG_FIRST }, \
2649 { "s4", 20 + GP_REG_FIRST }, \
2650 { "s5", 21 + GP_REG_FIRST }, \
2651 { "s6", 22 + GP_REG_FIRST }, \
2652 { "s7", 23 + GP_REG_FIRST }, \
2653 { "t8", 24 + GP_REG_FIRST }, \
2654 { "t9", 25 + GP_REG_FIRST }, \
2655 { "k0", 26 + GP_REG_FIRST }, \
2656 { "k1", 27 + GP_REG_FIRST }, \
2657 { "gp", 28 + GP_REG_FIRST }, \
2658 { "sp", 29 + GP_REG_FIRST }, \
2659 { "fp", 30 + GP_REG_FIRST }, \
2660 { "ra", 31 + GP_REG_FIRST }, \
2661 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2662 }
2663
2664 /* This is meant to be redefined in the host dependent files. It is a
2665 set of alternative names and regnums for mips coprocessors. */
2666
2667 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2668
2669 #define PRINT_OPERAND mips_print_operand
2670 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2671 #define PRINT_OPERAND_ADDRESS mips_print_operand_address
2672
2673 /* A C statement, to be executed after all slot-filler instructions
2674 have been output. If necessary, call `dbr_sequence_length' to
2675 determine the number of slots filled in a sequence (zero if not
2676 currently outputting a sequence), to decide how many no-ops to
2677 output, or whatever.
2678
2679 Don't define this macro if it has nothing to do, but it is
2680 helpful in reading assembly output if the extent of the delay
2681 sequence is made explicit (e.g. with white space).
2682
2683 Note that output routines for instructions with delay slots must
2684 be prepared to deal with not being output as part of a sequence
2685 (i.e. when the scheduling pass is not run, or when no slot
2686 fillers could be found.) The variable `final_sequence' is null
2687 when not processing a sequence, otherwise it contains the
2688 `sequence' rtx being output. */
2689
2690 #define DBR_OUTPUT_SEQEND(STREAM) \
2691 do \
2692 { \
2693 if (set_nomacro > 0 && --set_nomacro == 0) \
2694 fputs ("\t.set\tmacro\n", STREAM); \
2695 \
2696 if (set_noreorder > 0 && --set_noreorder == 0) \
2697 fputs ("\t.set\treorder\n", STREAM); \
2698 \
2699 fputs ("\n", STREAM); \
2700 } \
2701 while (0)
2702
2703 /* How to tell the debugger about changes of source files. */
2704 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
2705
2706 /* mips-tfile does not understand .stabd directives. */
2707 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2708 dbxout_begin_stabn_sline (LINE); \
2709 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2710 } while (0)
2711
2712 /* Use .loc directives for SDB line numbers. */
2713 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2714 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2715
2716 /* The MIPS implementation uses some labels for its own purpose. The
2717 following lists what labels are created, and are all formed by the
2718 pattern $L[a-z].*. The machine independent portion of GCC creates
2719 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2720
2721 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2722 $Lb[0-9]+ Begin blocks for MIPS debug support
2723 $Lc[0-9]+ Label for use in s<xx> operation.
2724 $Le[0-9]+ End blocks for MIPS debug support */
2725
2726 #undef ASM_DECLARE_OBJECT_NAME
2727 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2728 mips_declare_object (STREAM, NAME, "", ":\n")
2729
2730 /* Globalizing directive for a label. */
2731 #define GLOBAL_ASM_OP "\t.globl\t"
2732
2733 /* This says how to define a global common symbol. */
2734
2735 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2736
2737 /* This says how to define a local common symbol (i.e., not visible to
2738 linker). */
2739
2740 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2741 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2742 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2743 #endif
2744
2745 /* This says how to output an external. It would be possible not to
2746 output anything and let undefined symbol become external. However
2747 the assembler uses length information on externals to allocate in
2748 data/sdata bss/sbss, thereby saving exec time. */
2749
2750 #undef ASM_OUTPUT_EXTERNAL
2751 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2752 mips_output_external(STREAM,DECL,NAME)
2753
2754 /* This is how to declare a function name. The actual work of
2755 emitting the label is moved to function_prologue, so that we can
2756 get the line number correctly emitted before the .ent directive,
2757 and after any .file directives. Define as empty so that the function
2758 is not declared before the .ent directive elsewhere. */
2759
2760 #undef ASM_DECLARE_FUNCTION_NAME
2761 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2762
2763 /* This is how to store into the string LABEL
2764 the symbol_ref name of an internal numbered label where
2765 PREFIX is the class of label and NUM is the number within the class.
2766 This is suitable for output with `assemble_name'. */
2767
2768 #undef ASM_GENERATE_INTERNAL_LABEL
2769 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2770 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2771
2772 /* This is how to output an element of a case-vector that is absolute. */
2773
2774 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2775 fprintf (STREAM, "\t%s\t%sL%d\n", \
2776 ptr_mode == DImode ? ".dword" : ".word", \
2777 LOCAL_LABEL_PREFIX, \
2778 VALUE)
2779
2780 /* This is how to output an element of a case-vector. We can make the
2781 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2782 is supported. */
2783
2784 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2785 do { \
2786 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2787 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2788 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2789 else if (TARGET_GPWORD) \
2790 fprintf (STREAM, "\t%s\t%sL%d\n", \
2791 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2792 LOCAL_LABEL_PREFIX, VALUE); \
2793 else if (TARGET_RTP_PIC) \
2794 { \
2795 /* Make the entry relative to the start of the function. */ \
2796 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2797 fprintf (STREAM, "\t%s\t%sL%d-", \
2798 Pmode == DImode ? ".dword" : ".word", \
2799 LOCAL_LABEL_PREFIX, VALUE); \
2800 assemble_name (STREAM, XSTR (fnsym, 0)); \
2801 fprintf (STREAM, "\n"); \
2802 } \
2803 else \
2804 fprintf (STREAM, "\t%s\t%sL%d\n", \
2805 ptr_mode == DImode ? ".dword" : ".word", \
2806 LOCAL_LABEL_PREFIX, VALUE); \
2807 } while (0)
2808
2809 /* This is how to output an assembler line
2810 that says to advance the location counter
2811 to a multiple of 2**LOG bytes. */
2812
2813 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2814 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2815
2816 /* This is how to output an assembler line to advance the location
2817 counter by SIZE bytes. */
2818
2819 #undef ASM_OUTPUT_SKIP
2820 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2821 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2822
2823 /* This is how to output a string. */
2824 #undef ASM_OUTPUT_ASCII
2825 #define ASM_OUTPUT_ASCII mips_output_ascii
2826
2827 /* Output #ident as a in the read-only data section. */
2828 #undef ASM_OUTPUT_IDENT
2829 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2830 { \
2831 const char *p = STRING; \
2832 int size = strlen (p) + 1; \
2833 switch_to_section (readonly_data_section); \
2834 assemble_string (p, size); \
2835 }
2836 \f
2837 /* Default to -G 8 */
2838 #ifndef MIPS_DEFAULT_GVALUE
2839 #define MIPS_DEFAULT_GVALUE 8
2840 #endif
2841
2842 /* Define the strings to put out for each section in the object file. */
2843 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2844 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2845
2846 #undef READONLY_DATA_SECTION_ASM_OP
2847 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2848 \f
2849 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2850 do \
2851 { \
2852 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2853 TARGET_64BIT ? "daddiu" : "addiu", \
2854 reg_names[STACK_POINTER_REGNUM], \
2855 reg_names[STACK_POINTER_REGNUM], \
2856 TARGET_64BIT ? "sd" : "sw", \
2857 reg_names[REGNO], \
2858 reg_names[STACK_POINTER_REGNUM]); \
2859 } \
2860 while (0)
2861
2862 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2863 do \
2864 { \
2865 if (! set_noreorder) \
2866 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2867 \
2868 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2869 TARGET_64BIT ? "ld" : "lw", \
2870 reg_names[REGNO], \
2871 reg_names[STACK_POINTER_REGNUM], \
2872 TARGET_64BIT ? "daddu" : "addu", \
2873 reg_names[STACK_POINTER_REGNUM], \
2874 reg_names[STACK_POINTER_REGNUM]); \
2875 \
2876 if (! set_noreorder) \
2877 fprintf (STREAM, "\t.set\treorder\n"); \
2878 } \
2879 while (0)
2880
2881 /* How to start an assembler comment.
2882 The leading space is important (the mips native assembler requires it). */
2883 #ifndef ASM_COMMENT_START
2884 #define ASM_COMMENT_START " #"
2885 #endif
2886 \f
2887 /* Default definitions for size_t and ptrdiff_t. We must override the
2888 definitions from ../svr4.h on mips-*-linux-gnu. */
2889
2890 #undef SIZE_TYPE
2891 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2892
2893 #undef PTRDIFF_TYPE
2894 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2895
2896 /* The maximum number of bytes that can be copied by one iteration of
2897 a movmemsi loop; see mips_block_move_loop. */
2898 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2899 (UNITS_PER_WORD * 4)
2900
2901 /* The maximum number of bytes that can be copied by a straight-line
2902 implementation of movmemsi; see mips_block_move_straight. We want
2903 to make sure that any loop-based implementation will iterate at
2904 least twice. */
2905 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2906 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2907
2908 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2909 values were determined experimentally by benchmarking with CSiBE.
2910 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2911 for o32 where we have to restore $gp afterwards as well as make an
2912 indirect call), but in practice, bumping this up higher for
2913 TARGET_ABICALLS doesn't make much difference to code size. */
2914
2915 #define MIPS_CALL_RATIO 8
2916
2917 /* Any loop-based implementation of movmemsi will have at least
2918 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2919 moves, so allow individual copies of fewer elements.
2920
2921 When movmemsi is not available, use a value approximating
2922 the length of a memcpy call sequence, so that move_by_pieces
2923 will generate inline code if it is shorter than a function call.
2924 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2925 we'll have to generate a load/store pair for each, halve the
2926 value of MIPS_CALL_RATIO to take that into account. */
2927
2928 #define MOVE_RATIO \
2929 (HAVE_movmemsi \
2930 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2931 : MIPS_CALL_RATIO / 2)
2932
2933 /* movmemsi is meant to generate code that is at least as good as
2934 move_by_pieces. However, movmemsi effectively uses a by-pieces
2935 implementation both for moves smaller than a word and for word-aligned
2936 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
2937 allow the tree-level optimisers to do such moves by pieces, as it
2938 often exposes other optimization opportunities. We might as well
2939 continue to use movmemsi at the rtl level though, as it produces
2940 better code when scheduling is disabled (such as at -O). */
2941
2942 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2943 (HAVE_movmemsi \
2944 ? (!currently_expanding_to_rtl \
2945 && ((ALIGN) < BITS_PER_WORD \
2946 ? (SIZE) < UNITS_PER_WORD \
2947 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
2948 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2949 < (unsigned int) MOVE_RATIO))
2950
2951 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2952 of the length of a memset call, but use the default otherwise. */
2953
2954 #define CLEAR_RATIO \
2955 (optimize_size ? MIPS_CALL_RATIO : 15)
2956
2957 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2958 optimizing for size adjust the ratio to account for the overhead of
2959 loading the constant and replicating it across the word. */
2960
2961 #define SET_RATIO \
2962 (optimize_size ? MIPS_CALL_RATIO - 2 : 15)
2963
2964 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2965 in that case each word takes 3 insns (lui, ori, sw), or more in
2966 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2967 and let the move_by_pieces code copy the string from read-only
2968 memory. In the future, this could be tuned further for multi-issue
2969 CPUs that can issue stores down one pipe and arithmetic instructions
2970 down another; in that case, the lui/ori/sw combination would be a
2971 win for long enough strings. */
2972
2973 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2974 \f
2975 #ifndef __mips16
2976 /* Since the bits of the _init and _fini function is spread across
2977 many object files, each potentially with its own GP, we must assume
2978 we need to load our GP. We don't preserve $gp or $ra, since each
2979 init/fini chunk is supposed to initialize $gp, and crti/crtn
2980 already take care of preserving $ra and, when appropriate, $gp. */
2981 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2982 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2983 asm (SECTION_OP "\n\
2984 .set noreorder\n\
2985 bal 1f\n\
2986 nop\n\
2987 1: .cpload $31\n\
2988 .set reorder\n\
2989 jal " USER_LABEL_PREFIX #FUNC "\n\
2990 " TEXT_SECTION_ASM_OP);
2991 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2992 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2993 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2994 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2995 asm (SECTION_OP "\n\
2996 .set noreorder\n\
2997 bal 1f\n\
2998 nop\n\
2999 1: .set reorder\n\
3000 .cpsetup $31, $2, 1b\n\
3001 jal " USER_LABEL_PREFIX #FUNC "\n\
3002 " TEXT_SECTION_ASM_OP);
3003 #endif
3004 #endif
3005
3006 #ifndef HAVE_AS_TLS
3007 #define HAVE_AS_TLS 0
3008 #endif
3009
3010 /* Return an asm string that atomically:
3011
3012 - Compares memory reference %1 to register %2 and, if they are
3013 equal, changes %1 to %3.
3014
3015 - Sets register %0 to the old value of memory reference %1.
3016
3017 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
3018 and OP is the instruction that should be used to load %3 into a
3019 register. */
3020 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
3021 "%(%<%[%|sync\n" \
3022 "1:\tll" SUFFIX "\t%0,%1\n" \
3023 "\tbne\t%0,%z2,2f\n" \
3024 "\t" OP "\t%@,%3\n" \
3025 "\tsc" SUFFIX "\t%@,%1\n" \
3026 "\tbeq\t%@,%.,1b\n" \
3027 "\tnop\n" \
3028 "\tsync%-%]%>%)\n" \
3029 "2:\n"
3030
3031 /* Return an asm string that atomically:
3032
3033 - Given that %2 contains a bit mask and %3 the inverted mask and
3034 that %4 and %5 have already been ANDed with %2.
3035
3036 - Compares the bits in memory reference %1 selected by mask %2 to
3037 register %4 and, if they are equal, changes the selected bits
3038 in memory to %5.
3039
3040 - Sets register %0 to the old value of memory reference %1.
3041
3042 OPS are the instructions needed to OR %5 with %@. */
3043 #define MIPS_COMPARE_AND_SWAP_12(OPS) \
3044 "%(%<%[%|sync\n" \
3045 "1:\tll\t%0,%1\n" \
3046 "\tand\t%@,%0,%2\n" \
3047 "\tbne\t%@,%z4,2f\n" \
3048 "\tand\t%@,%0,%3\n" \
3049 OPS \
3050 "\tsc\t%@,%1\n" \
3051 "\tbeq\t%@,%.,1b\n" \
3052 "\tnop\n" \
3053 "\tsync%-%]%>%)\n" \
3054 "2:\n"
3055
3056 #define MIPS_COMPARE_AND_SWAP_12_ZERO_OP ""
3057 #define MIPS_COMPARE_AND_SWAP_12_NONZERO_OP "\tor\t%@,%@,%5\n"
3058
3059
3060 /* Return an asm string that atomically:
3061
3062 - Sets memory reference %0 to %0 INSN %1.
3063
3064 SUFFIX is the suffix that should be added to "ll" and "sc"
3065 instructions. */
3066 #define MIPS_SYNC_OP(SUFFIX, INSN) \
3067 "%(%<%[%|sync\n" \
3068 "1:\tll" SUFFIX "\t%@,%0\n" \
3069 "\t" INSN "\t%@,%@,%1\n" \
3070 "\tsc" SUFFIX "\t%@,%0\n" \
3071 "\tbeq\t%@,%.,1b\n" \
3072 "\tnop\n" \
3073 "\tsync%-%]%>%)"
3074
3075 /* Return an asm string that atomically:
3076
3077 - Given that %1 contains a bit mask and %2 the inverted mask and
3078 that %3 has already been ANDed with %1.
3079
3080 - Sets the selected bits of memory reference %0 to %0 INSN %3.
3081
3082 - Uses scratch register %4.
3083
3084 NOT_OP are the optional instructions to do a bit-wise not
3085 operation in conjunction with an AND INSN to generate a sync_nand
3086 operation. */
3087 #define MIPS_SYNC_OP_12(INSN, NOT_OP) \
3088 "%(%<%[%|sync\n" \
3089 "1:\tll\t%4,%0\n" \
3090 "\tand\t%@,%4,%2\n" \
3091 NOT_OP \
3092 "\t" INSN "\t%4,%4,%z3\n" \
3093 "\tand\t%4,%4,%1\n" \
3094 "\tor\t%@,%@,%4\n" \
3095 "\tsc\t%@,%0\n" \
3096 "\tbeq\t%@,%.,1b\n" \
3097 "\tnop\n" \
3098 "\tsync%-%]%>%)"
3099
3100 #define MIPS_SYNC_OP_12_NOT_NOP ""
3101 #define MIPS_SYNC_OP_12_NOT_NOT "\tnor\t%4,%4,%.\n"
3102
3103 /* Return an asm string that atomically:
3104
3105 - Given that %2 contains a bit mask and %3 the inverted mask and
3106 that %4 has already been ANDed with %2.
3107
3108 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3109
3110 - Sets %0 to the original value of %1.
3111
3112 - Uses scratch register %5.
3113
3114 NOT_OP are the optional instructions to do a bit-wise not
3115 operation in conjunction with an AND INSN to generate a sync_nand
3116 operation.
3117
3118 REG is used in conjunction with NOT_OP and is used to select the
3119 register operated on by the INSN. */
3120 #define MIPS_SYNC_OLD_OP_12(INSN, NOT_OP, REG) \
3121 "%(%<%[%|sync\n" \
3122 "1:\tll\t%0,%1\n" \
3123 "\tand\t%@,%0,%3\n" \
3124 NOT_OP \
3125 "\t" INSN "\t%5," REG ",%z4\n" \
3126 "\tand\t%5,%5,%2\n" \
3127 "\tor\t%@,%@,%5\n" \
3128 "\tsc\t%@,%1\n" \
3129 "\tbeq\t%@,%.,1b\n" \
3130 "\tnop\n" \
3131 "\tsync%-%]%>%)"
3132
3133 #define MIPS_SYNC_OLD_OP_12_NOT_NOP ""
3134 #define MIPS_SYNC_OLD_OP_12_NOT_NOP_REG "%0"
3135 #define MIPS_SYNC_OLD_OP_12_NOT_NOT "\tnor\t%5,%0,%.\n"
3136 #define MIPS_SYNC_OLD_OP_12_NOT_NOT_REG "%5"
3137
3138 /* Return an asm string that atomically:
3139
3140 - Given that %2 contains a bit mask and %3 the inverted mask and
3141 that %4 has already been ANDed with %2.
3142
3143 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3144
3145 - Sets %0 to the new value of %1.
3146
3147 NOT_OP are the optional instructions to do a bit-wise not
3148 operation in conjunction with an AND INSN to generate a sync_nand
3149 operation. */
3150 #define MIPS_SYNC_NEW_OP_12(INSN, NOT_OP) \
3151 "%(%<%[%|sync\n" \
3152 "1:\tll\t%0,%1\n" \
3153 "\tand\t%@,%0,%3\n" \
3154 NOT_OP \
3155 "\t" INSN "\t%0,%0,%z4\n" \
3156 "\tand\t%0,%0,%2\n" \
3157 "\tor\t%@,%@,%0\n" \
3158 "\tsc\t%@,%1\n" \
3159 "\tbeq\t%@,%.,1b\n" \
3160 "\tnop\n" \
3161 "\tsync%-%]%>%)"
3162
3163 #define MIPS_SYNC_NEW_OP_12_NOT_NOP ""
3164 #define MIPS_SYNC_NEW_OP_12_NOT_NOT "\tnor\t%0,%0,%.\n"
3165
3166 /* Return an asm string that atomically:
3167
3168 - Sets memory reference %1 to %1 INSN %2.
3169
3170 - Sets register %0 to the old value of memory reference %1.
3171
3172 SUFFIX is the suffix that should be added to "ll" and "sc"
3173 instructions. */
3174 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
3175 "%(%<%[%|sync\n" \
3176 "1:\tll" SUFFIX "\t%0,%1\n" \
3177 "\t" INSN "\t%@,%0,%2\n" \
3178 "\tsc" SUFFIX "\t%@,%1\n" \
3179 "\tbeq\t%@,%.,1b\n" \
3180 "\tnop\n" \
3181 "\tsync%-%]%>%)"
3182
3183 /* Return an asm string that atomically:
3184
3185 - Sets memory reference %1 to %1 INSN %2.
3186
3187 - Sets register %0 to the new value of memory reference %1.
3188
3189 SUFFIX is the suffix that should be added to "ll" and "sc"
3190 instructions. */
3191 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
3192 "%(%<%[%|sync\n" \
3193 "1:\tll" SUFFIX "\t%0,%1\n" \
3194 "\t" INSN "\t%@,%0,%2\n" \
3195 "\tsc" SUFFIX "\t%@,%1\n" \
3196 "\tbeq\t%@,%.,1b\n" \
3197 "\t" INSN "\t%0,%0,%2\n" \
3198 "\tsync%-%]%>%)"
3199
3200 /* Return an asm string that atomically:
3201
3202 - Sets memory reference %0 to ~%0 AND %1.
3203
3204 SUFFIX is the suffix that should be added to "ll" and "sc"
3205 instructions. INSN is the and instruction needed to and a register
3206 with %2. */
3207 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
3208 "%(%<%[%|sync\n" \
3209 "1:\tll" SUFFIX "\t%@,%0\n" \
3210 "\tnor\t%@,%@,%.\n" \
3211 "\t" INSN "\t%@,%@,%1\n" \
3212 "\tsc" SUFFIX "\t%@,%0\n" \
3213 "\tbeq\t%@,%.,1b\n" \
3214 "\tnop\n" \
3215 "\tsync%-%]%>%)"
3216
3217 /* Return an asm string that atomically:
3218
3219 - Sets memory reference %1 to ~%1 AND %2.
3220
3221 - Sets register %0 to the old value of memory reference %1.
3222
3223 SUFFIX is the suffix that should be added to "ll" and "sc"
3224 instructions. INSN is the and instruction needed to and a register
3225 with %2. */
3226 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
3227 "%(%<%[%|sync\n" \
3228 "1:\tll" SUFFIX "\t%0,%1\n" \
3229 "\tnor\t%@,%0,%.\n" \
3230 "\t" INSN "\t%@,%@,%2\n" \
3231 "\tsc" SUFFIX "\t%@,%1\n" \
3232 "\tbeq\t%@,%.,1b\n" \
3233 "\tnop\n" \
3234 "\tsync%-%]%>%)"
3235
3236 /* Return an asm string that atomically:
3237
3238 - Sets memory reference %1 to ~%1 AND %2.
3239
3240 - Sets register %0 to the new value of memory reference %1.
3241
3242 SUFFIX is the suffix that should be added to "ll" and "sc"
3243 instructions. INSN is the and instruction needed to and a register
3244 with %2. */
3245 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
3246 "%(%<%[%|sync\n" \
3247 "1:\tll" SUFFIX "\t%0,%1\n" \
3248 "\tnor\t%0,%0,%.\n" \
3249 "\t" INSN "\t%@,%0,%2\n" \
3250 "\tsc" SUFFIX "\t%@,%1\n" \
3251 "\tbeq\t%@,%.,1b\n" \
3252 "\t" INSN "\t%0,%0,%2\n" \
3253 "\tsync%-%]%>%)"
3254
3255 /* Return an asm string that atomically:
3256
3257 - Sets memory reference %1 to %2.
3258
3259 - Sets register %0 to the old value of memory reference %1.
3260
3261 SUFFIX is the suffix that should be added to "ll" and "sc"
3262 instructions. OP is the and instruction that should be used to
3263 load %2 into a register. */
3264 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3265 "%(%<%[%|\n" \
3266 "1:\tll" SUFFIX "\t%0,%1\n" \
3267 "\t" OP "\t%@,%2\n" \
3268 "\tsc" SUFFIX "\t%@,%1\n" \
3269 "\tbeq\t%@,%.,1b\n" \
3270 "\tnop\n" \
3271 "\tsync%-%]%>%)"
3272
3273 /* Return an asm string that atomically:
3274
3275 - Given that %2 contains an inclusive mask, %3 and exclusive mask
3276 and %4 has already been ANDed with the inclusive mask.
3277
3278 - Sets bits selected by the inclusive mask of memory reference %1
3279 to %4.
3280
3281 - Sets register %0 to the old value of memory reference %1.
3282
3283 OPS are the instructions needed to OR %4 with %@.
3284
3285 Operand %2 is unused, but needed as to give the test_and_set_12
3286 insn the five operands expected by the expander. */
3287 #define MIPS_SYNC_EXCHANGE_12(OPS) \
3288 "%(%<%[%|\n" \
3289 "1:\tll\t%0,%1\n" \
3290 "\tand\t%@,%0,%3\n" \
3291 OPS \
3292 "\tsc\t%@,%1\n" \
3293 "\tbeq\t%@,%.,1b\n" \
3294 "\tnop\n" \
3295 "\tsync%-%]%>%)"
3296
3297 #define MIPS_SYNC_EXCHANGE_12_ZERO_OP ""
3298 #define MIPS_SYNC_EXCHANGE_12_NONZERO_OP "\tor\t%@,%@,%4\n"
3299
3300 #ifndef USED_FOR_TARGET
3301 extern const enum reg_class mips_regno_to_class[];
3302 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3303 extern bool mips_print_operand_punct[256];
3304 extern const char *current_function_file; /* filename current function is in */
3305 extern int num_source_filenames; /* current .file # */
3306 extern int set_noreorder; /* # of nested .set noreorder's */
3307 extern int set_nomacro; /* # of nested .set nomacro's */
3308 extern int mips_dbx_regno[];
3309 extern int mips_dwarf_regno[];
3310 extern bool mips_split_p[];
3311 extern bool mips_split_hi_p[];
3312 extern GTY(()) rtx cmp_operands[2];
3313 extern enum processor_type mips_arch; /* which cpu to codegen for */
3314 extern enum processor_type mips_tune; /* which cpu to schedule for */
3315 extern int mips_isa; /* architectural level */
3316 extern int mips_abi; /* which ABI to use */
3317 extern const struct mips_cpu_info *mips_arch_info;
3318 extern const struct mips_cpu_info *mips_tune_info;
3319 extern const struct mips_rtx_cost_data *mips_cost;
3320 extern bool mips_base_mips16;
3321 extern enum mips_code_readable_setting mips_code_readable;
3322 #endif
3323
3324 /* Enable querying of DFA units. */
3325 #define CPU_UNITS_QUERY 1