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[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF2_1,
45 PROCESSOR_24KF1_1,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF2_1,
48 PROCESSOR_74KF1_1,
49 PROCESSOR_74KF3_2,
50 PROCESSOR_M4K,
51 PROCESSOR_R3900,
52 PROCESSOR_R6000,
53 PROCESSOR_R4000,
54 PROCESSOR_R4100,
55 PROCESSOR_R4111,
56 PROCESSOR_R4120,
57 PROCESSOR_R4130,
58 PROCESSOR_R4300,
59 PROCESSOR_R4600,
60 PROCESSOR_R4650,
61 PROCESSOR_R5000,
62 PROCESSOR_R5400,
63 PROCESSOR_R5500,
64 PROCESSOR_R7000,
65 PROCESSOR_R8000,
66 PROCESSOR_R9000,
67 PROCESSOR_SB1,
68 PROCESSOR_SB1A,
69 PROCESSOR_SR71000,
70 PROCESSOR_MAX
71 };
72
73 /* Costs of various operations on the different architectures. */
74
75 struct mips_rtx_cost_data
76 {
77 unsigned short fp_add;
78 unsigned short fp_mult_sf;
79 unsigned short fp_mult_df;
80 unsigned short fp_div_sf;
81 unsigned short fp_div_df;
82 unsigned short int_mult_si;
83 unsigned short int_mult_di;
84 unsigned short int_div_si;
85 unsigned short int_div_di;
86 unsigned short branch_cost;
87 unsigned short memory_latency;
88 };
89
90 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
91 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
92 to work on a 64-bit machine. */
93
94 #define ABI_32 0
95 #define ABI_N32 1
96 #define ABI_64 2
97 #define ABI_EABI 3
98 #define ABI_O64 4
99
100 /* Information about one recognized processor. Defined here for the
101 benefit of TARGET_CPU_CPP_BUILTINS. */
102 struct mips_cpu_info {
103 /* The 'canonical' name of the processor as far as GCC is concerned.
104 It's typically a manufacturer's prefix followed by a numerical
105 designation. It should be lowercase. */
106 const char *name;
107
108 /* The internal processor number that most closely matches this
109 entry. Several processors can have the same value, if there's no
110 difference between them from GCC's point of view. */
111 enum processor_type cpu;
112
113 /* The ISA level that the processor implements. */
114 int isa;
115 };
116
117 /* Enumerates the setting of the -mcode-readable option. */
118 enum mips_code_readable_setting {
119 CODE_READABLE_NO,
120 CODE_READABLE_PCREL,
121 CODE_READABLE_YES
122 };
123
124 #ifndef USED_FOR_TARGET
125 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
126 extern const char *current_function_file; /* filename current function is in */
127 extern int num_source_filenames; /* current .file # */
128 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
129 extern int sym_lineno; /* sgi next label # for each stmt */
130 extern int set_noreorder; /* # of nested .set noreorder's */
131 extern int set_nomacro; /* # of nested .set nomacro's */
132 extern int set_noat; /* # of nested .set noat's */
133 extern int set_volatile; /* # of nested .set volatile's */
134 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
135 extern int mips_dbx_regno[];
136 extern int mips_dwarf_regno[];
137 extern bool mips_split_p[];
138 extern GTY(()) rtx cmp_operands[2];
139 extern enum processor_type mips_arch; /* which cpu to codegen for */
140 extern enum processor_type mips_tune; /* which cpu to schedule for */
141 extern int mips_isa; /* architectural level */
142 extern int mips_abi; /* which ABI to use */
143 extern const struct mips_cpu_info mips_cpu_info_table[];
144 extern const struct mips_cpu_info *mips_arch_info;
145 extern const struct mips_cpu_info *mips_tune_info;
146 extern const struct mips_rtx_cost_data *mips_cost;
147 extern enum mips_code_readable_setting mips_code_readable;
148 #endif
149
150 /* Macros to silence warnings about numbers being signed in traditional
151 C and unsigned in ISO C when compiled on 32-bit hosts. */
152
153 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
154 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
155 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
156
157 \f
158 /* Run-time compilation parameters selecting different hardware subsets. */
159
160 /* True if we are generating position-independent VxWorks RTP code. */
161 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
162
163 /* True if the call patterns should be split into a jalr followed by
164 an instruction to restore $gp. It is only safe to split the load
165 from the call when every use of $gp is explicit. */
166
167 #define TARGET_SPLIT_CALLS \
168 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
169
170 /* True if we're generating a form of -mabicalls in which we can use
171 operators like %hi and %lo to refer to locally-binding symbols.
172 We can only do this for -mno-shared, and only then if we can use
173 relocation operations instead of assembly macros. It isn't really
174 worth using absolute sequences for 64-bit symbols because GOT
175 accesses are so much shorter. */
176
177 #define TARGET_ABSOLUTE_ABICALLS \
178 (TARGET_ABICALLS \
179 && !TARGET_SHARED \
180 && TARGET_EXPLICIT_RELOCS \
181 && !ABI_HAS_64BIT_SYMBOLS)
182
183 /* True if we can optimize sibling calls. For simplicity, we only
184 handle cases in which call_insn_operand will reject invalid
185 sibcall addresses. There are two cases in which this isn't true:
186
187 - TARGET_MIPS16. call_insn_operand accepts constant addresses
188 but there is no direct jump instruction. It isn't worth
189 using sibling calls in this case anyway; they would usually
190 be longer than normal calls.
191
192 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
193 accepts global constants, but all sibcalls must be indirect. */
194 #define TARGET_SIBCALLS \
195 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
196
197 /* True if we need to use a global offset table to access some symbols. */
198 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
199
200 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
201 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
202
203 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
204 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
205
206 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
207 This is true for both the PIC and non-PIC VxWorks RTP modes. */
208 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
209
210 /* True if .gpword or .gpdword should be used for switch tables.
211
212 Although GAS does understand .gpdword, the SGI linker mishandles
213 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
214 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
215 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
216
217 /* Generate mips16 code */
218 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
219 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
220 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
221 /* Generate mips16e register save/restore sequences. */
222 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
223
224 /* True if we're generating a form of MIPS16 code in which general
225 text loads are allowed. */
226 #define TARGET_MIPS16_TEXT_LOADS \
227 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
228
229 /* True if we're generating a form of MIPS16 code in which PC-relative
230 loads are allowed. */
231 #define TARGET_MIPS16_PCREL_LOADS \
232 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
233
234 /* Generic ISA defines. */
235 #define ISA_MIPS1 (mips_isa == 1)
236 #define ISA_MIPS2 (mips_isa == 2)
237 #define ISA_MIPS3 (mips_isa == 3)
238 #define ISA_MIPS4 (mips_isa == 4)
239 #define ISA_MIPS32 (mips_isa == 32)
240 #define ISA_MIPS32R2 (mips_isa == 33)
241 #define ISA_MIPS64 (mips_isa == 64)
242
243 /* Architecture target defines. */
244 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
245 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
246 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
247 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
248 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
249 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
250 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
251 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
252 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
253 || mips_arch == PROCESSOR_SB1A)
254 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
255
256 /* Scheduling target defines. */
257 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
258 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
259 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
260 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
261 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
262 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
263 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
264 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
265 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
266 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
267 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
268 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
269 || mips_tune == PROCESSOR_SB1A)
270 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
271 || mips_tune == PROCESSOR_24KF2_1 \
272 || mips_tune == PROCESSOR_24KF1_1)
273 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
274 || mips_tune == PROCESSOR_74KF2_1 \
275 || mips_tune == PROCESSOR_74KF1_1 \
276 || mips_tune == PROCESSOR_74KF3_2)
277 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
278
279 /* True if the pre-reload scheduler should try to create chains of
280 multiply-add or multiply-subtract instructions. For example,
281 suppose we have:
282
283 t1 = a * b
284 t2 = t1 + c * d
285 t3 = e * f
286 t4 = t3 - g * h
287
288 t1 will have a higher priority than t2 and t3 will have a higher
289 priority than t4. However, before reload, there is no dependence
290 between t1 and t3, and they can often have similar priorities.
291 The scheduler will then tend to prefer:
292
293 t1 = a * b
294 t3 = e * f
295 t2 = t1 + c * d
296 t4 = t3 - g * h
297
298 which stops us from making full use of macc/madd-style instructions.
299 This sort of situation occurs frequently in Fourier transforms and
300 in unrolled loops.
301
302 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
303 queue so that chained multiply-add and multiply-subtract instructions
304 appear ahead of any other instruction that is likely to clobber lo.
305 In the example above, if t2 and t3 become ready at the same time,
306 the code ensures that t2 is scheduled first.
307
308 Multiply-accumulate instructions are a bigger win for some targets
309 than others, so this macro is defined on an opt-in basis. */
310 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
311 || TUNE_MIPS4120 \
312 || TUNE_MIPS4130 \
313 || TUNE_24K)
314
315 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
316 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
317
318 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
319 directly accessible, while the command-line options select
320 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
321 in use. */
322 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
323 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
324
325 /* IRIX specific stuff. */
326 #define TARGET_IRIX 0
327 #define TARGET_IRIX6 0
328
329 /* Define preprocessor macros for the -march and -mtune options.
330 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
331 processor. If INFO's canonical name is "foo", define PREFIX to
332 be "foo", and define an additional macro PREFIX_FOO. */
333 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
334 do \
335 { \
336 char *macro, *p; \
337 \
338 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
339 for (p = macro; *p != 0; p++) \
340 *p = TOUPPER (*p); \
341 \
342 builtin_define (macro); \
343 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
344 free (macro); \
345 } \
346 while (0)
347
348 /* Target CPU builtins. */
349 #define TARGET_CPU_CPP_BUILTINS() \
350 do \
351 { \
352 /* Everyone but IRIX defines this to mips. */ \
353 if (!TARGET_IRIX) \
354 builtin_assert ("machine=mips"); \
355 \
356 builtin_assert ("cpu=mips"); \
357 builtin_define ("__mips__"); \
358 builtin_define ("_mips"); \
359 \
360 /* We do this here because __mips is defined below and so we \
361 can't use builtin_define_std. We don't ever want to define \
362 "mips" for VxWorks because some of the VxWorks headers \
363 construct include filenames from a root directory macro, \
364 an architecture macro and a filename, where the architecture \
365 macro expands to 'mips'. If we define 'mips' to 1, the \
366 architecture macro expands to 1 as well. */ \
367 if (!flag_iso && !TARGET_VXWORKS) \
368 builtin_define ("mips"); \
369 \
370 if (TARGET_64BIT) \
371 builtin_define ("__mips64"); \
372 \
373 if (!TARGET_IRIX) \
374 { \
375 /* Treat _R3000 and _R4000 like register-size \
376 defines, which is how they've historically \
377 been used. */ \
378 if (TARGET_64BIT) \
379 { \
380 builtin_define_std ("R4000"); \
381 builtin_define ("_R4000"); \
382 } \
383 else \
384 { \
385 builtin_define_std ("R3000"); \
386 builtin_define ("_R3000"); \
387 } \
388 } \
389 if (TARGET_FLOAT64) \
390 builtin_define ("__mips_fpr=64"); \
391 else \
392 builtin_define ("__mips_fpr=32"); \
393 \
394 if (TARGET_MIPS16) \
395 builtin_define ("__mips16"); \
396 \
397 if (TARGET_MIPS3D) \
398 builtin_define ("__mips3d"); \
399 \
400 if (TARGET_SMARTMIPS) \
401 builtin_define ("__mips_smartmips"); \
402 \
403 if (TARGET_DSP) \
404 { \
405 builtin_define ("__mips_dsp"); \
406 if (TARGET_DSPR2) \
407 { \
408 builtin_define ("__mips_dspr2"); \
409 builtin_define ("__mips_dsp_rev=2"); \
410 } \
411 else \
412 builtin_define ("__mips_dsp_rev=1"); \
413 } \
414 \
415 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
416 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
417 \
418 if (ISA_MIPS1) \
419 { \
420 builtin_define ("__mips=1"); \
421 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
422 } \
423 else if (ISA_MIPS2) \
424 { \
425 builtin_define ("__mips=2"); \
426 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
427 } \
428 else if (ISA_MIPS3) \
429 { \
430 builtin_define ("__mips=3"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
432 } \
433 else if (ISA_MIPS4) \
434 { \
435 builtin_define ("__mips=4"); \
436 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
437 } \
438 else if (ISA_MIPS32) \
439 { \
440 builtin_define ("__mips=32"); \
441 builtin_define ("__mips_isa_rev=1"); \
442 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
443 } \
444 else if (ISA_MIPS32R2) \
445 { \
446 builtin_define ("__mips=32"); \
447 builtin_define ("__mips_isa_rev=2"); \
448 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
449 } \
450 else if (ISA_MIPS64) \
451 { \
452 builtin_define ("__mips=64"); \
453 builtin_define ("__mips_isa_rev=1"); \
454 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
455 } \
456 \
457 switch (mips_abi) \
458 { \
459 case ABI_32: \
460 builtin_define ("_ABIO32=1"); \
461 builtin_define ("_MIPS_SIM=_ABIO32"); \
462 break; \
463 \
464 case ABI_N32: \
465 builtin_define ("_ABIN32=2"); \
466 builtin_define ("_MIPS_SIM=_ABIN32"); \
467 break; \
468 \
469 case ABI_64: \
470 builtin_define ("_ABI64=3"); \
471 builtin_define ("_MIPS_SIM=_ABI64"); \
472 break; \
473 \
474 case ABI_O64: \
475 builtin_define ("_ABIO64=4"); \
476 builtin_define ("_MIPS_SIM=_ABIO64"); \
477 break; \
478 } \
479 \
480 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
481 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
482 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
483 builtin_define_with_int_value ("_MIPS_FPSET", \
484 32 / MAX_FPRS_PER_FMT); \
485 \
486 /* These defines reflect the ABI in use, not whether the \
487 FPU is directly accessible. */ \
488 if (TARGET_HARD_FLOAT_ABI) \
489 builtin_define ("__mips_hard_float"); \
490 else \
491 builtin_define ("__mips_soft_float"); \
492 \
493 if (TARGET_SINGLE_FLOAT) \
494 builtin_define ("__mips_single_float"); \
495 \
496 if (TARGET_PAIRED_SINGLE_FLOAT) \
497 builtin_define ("__mips_paired_single_float"); \
498 \
499 if (TARGET_BIG_ENDIAN) \
500 { \
501 builtin_define_std ("MIPSEB"); \
502 builtin_define ("_MIPSEB"); \
503 } \
504 else \
505 { \
506 builtin_define_std ("MIPSEL"); \
507 builtin_define ("_MIPSEL"); \
508 } \
509 \
510 /* Macros dependent on the C dialect. */ \
511 if (preprocessing_asm_p ()) \
512 { \
513 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
514 builtin_define ("_LANGUAGE_ASSEMBLY"); \
515 } \
516 else if (c_dialect_cxx ()) \
517 { \
518 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
519 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
520 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
521 } \
522 else \
523 { \
524 builtin_define_std ("LANGUAGE_C"); \
525 builtin_define ("_LANGUAGE_C"); \
526 } \
527 if (c_dialect_objc ()) \
528 { \
529 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
530 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
531 /* Bizarre, but needed at least for Irix. */ \
532 builtin_define_std ("LANGUAGE_C"); \
533 builtin_define ("_LANGUAGE_C"); \
534 } \
535 \
536 if (mips_abi == ABI_EABI) \
537 builtin_define ("__mips_eabi"); \
538 } \
539 while (0)
540
541 /* Default target_flags if no switches are specified */
542
543 #ifndef TARGET_DEFAULT
544 #define TARGET_DEFAULT 0
545 #endif
546
547 #ifndef TARGET_CPU_DEFAULT
548 #define TARGET_CPU_DEFAULT 0
549 #endif
550
551 #ifndef TARGET_ENDIAN_DEFAULT
552 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
553 #endif
554
555 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
556 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
557 #endif
558
559 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
560 #ifndef MIPS_ISA_DEFAULT
561 #ifndef MIPS_CPU_STRING_DEFAULT
562 #define MIPS_CPU_STRING_DEFAULT "from-abi"
563 #endif
564 #endif
565
566 #ifdef IN_LIBGCC2
567 #undef TARGET_64BIT
568 /* Make this compile time constant for libgcc2 */
569 #ifdef __mips64
570 #define TARGET_64BIT 1
571 #else
572 #define TARGET_64BIT 0
573 #endif
574 #endif /* IN_LIBGCC2 */
575
576 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
577
578 #ifndef MULTILIB_ENDIAN_DEFAULT
579 #if TARGET_ENDIAN_DEFAULT == 0
580 #define MULTILIB_ENDIAN_DEFAULT "EL"
581 #else
582 #define MULTILIB_ENDIAN_DEFAULT "EB"
583 #endif
584 #endif
585
586 #ifndef MULTILIB_ISA_DEFAULT
587 # if MIPS_ISA_DEFAULT == 1
588 # define MULTILIB_ISA_DEFAULT "mips1"
589 # else
590 # if MIPS_ISA_DEFAULT == 2
591 # define MULTILIB_ISA_DEFAULT "mips2"
592 # else
593 # if MIPS_ISA_DEFAULT == 3
594 # define MULTILIB_ISA_DEFAULT "mips3"
595 # else
596 # if MIPS_ISA_DEFAULT == 4
597 # define MULTILIB_ISA_DEFAULT "mips4"
598 # else
599 # if MIPS_ISA_DEFAULT == 32
600 # define MULTILIB_ISA_DEFAULT "mips32"
601 # else
602 # if MIPS_ISA_DEFAULT == 33
603 # define MULTILIB_ISA_DEFAULT "mips32r2"
604 # else
605 # if MIPS_ISA_DEFAULT == 64
606 # define MULTILIB_ISA_DEFAULT "mips64"
607 # else
608 # define MULTILIB_ISA_DEFAULT "mips1"
609 # endif
610 # endif
611 # endif
612 # endif
613 # endif
614 # endif
615 # endif
616 #endif
617
618 #ifndef MULTILIB_DEFAULTS
619 #define MULTILIB_DEFAULTS \
620 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
621 #endif
622
623 /* We must pass -EL to the linker by default for little endian embedded
624 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
625 linker will default to using big-endian output files. The OUTPUT_FORMAT
626 line must be in the linker script, otherwise -EB/-EL will not work. */
627
628 #ifndef ENDIAN_SPEC
629 #if TARGET_ENDIAN_DEFAULT == 0
630 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
631 #else
632 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
633 #endif
634 #endif
635
636 /* A spec condition that matches all non-mips16 -mips arguments. */
637
638 #define MIPS_ISA_LEVEL_OPTION_SPEC \
639 "mips1|mips2|mips3|mips4|mips32*|mips64*"
640
641 /* A spec condition that matches all non-mips16 architecture arguments. */
642
643 #define MIPS_ARCH_OPTION_SPEC \
644 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
645
646 /* A spec that infers a -mips argument from an -march argument,
647 or injects the default if no architecture is specified. */
648
649 #define MIPS_ISA_LEVEL_SPEC \
650 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
651 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
652 %{march=mips2|march=r6000:-mips2} \
653 %{march=mips3|march=r4*|march=vr4*|march=orion:-mips3} \
654 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \
655 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
656 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
657 |march=34k*|march=74k*: -mips32r2} \
658 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
659 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
660
661 /* A spec that infers a -mhard-float or -msoft-float setting from an
662 -march argument. Note that soft-float and hard-float code are not
663 link-compatible. */
664
665 #define MIPS_ARCH_FLOAT_SPEC \
666 "%{mhard-float|msoft-float|march=mips*:; \
667 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
668 |march=34kc|march=74kc|march=5kc: -msoft-float; \
669 march=*: -mhard-float}"
670
671 /* A spec condition that matches 32-bit options. It only works if
672 MIPS_ISA_LEVEL_SPEC has been applied. */
673
674 #define MIPS_32BIT_OPTION_SPEC \
675 "mips1|mips2|mips32*|mgp32"
676
677 /* Support for a compile-time default CPU, et cetera. The rules are:
678 --with-arch is ignored if -march is specified or a -mips is specified
679 (other than -mips16).
680 --with-tune is ignored if -mtune is specified.
681 --with-abi is ignored if -mabi is specified.
682 --with-float is ignored if -mhard-float or -msoft-float are
683 specified.
684 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
685 specified. */
686 #define OPTION_DEFAULT_SPECS \
687 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
688 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
689 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
690 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
691 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
692
693
694 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
695 && ISA_HAS_COND_TRAP)
696
697 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
698 && !TARGET_SR71K \
699 && !TARGET_MIPS16)
700
701 /* True if the ABI can only work with 64-bit integer registers. We
702 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
703 otherwise floating-point registers must also be 64-bit. */
704 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
705
706 /* Likewise for 32-bit regs. */
707 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
708
709 /* True if symbols are 64 bits wide. At present, n64 is the only
710 ABI for which this is true. */
711 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
712
713 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
714 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
715 || ISA_MIPS4 \
716 || ISA_MIPS64)
717
718 /* ISA has branch likely instructions (e.g. mips2). */
719 /* Disable branchlikely for tx39 until compare rewrite. They haven't
720 been generated up to this point. */
721 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
722
723 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
724 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
725 || TARGET_MIPS5400 \
726 || TARGET_MIPS5500 \
727 || TARGET_MIPS7000 \
728 || TARGET_MIPS9000 \
729 || TARGET_MAD \
730 || ISA_MIPS32 \
731 || ISA_MIPS32R2 \
732 || ISA_MIPS64) \
733 && !TARGET_MIPS16)
734
735 /* ISA has the conditional move instructions introduced in mips4. */
736 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
737 || ISA_MIPS32 \
738 || ISA_MIPS32R2 \
739 || ISA_MIPS64) \
740 && !TARGET_MIPS5500 \
741 && !TARGET_MIPS16)
742
743 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
744 branch on CC, and move (both FP and non-FP) on CC. */
745 #define ISA_HAS_8CC (ISA_MIPS4 \
746 || ISA_MIPS32 \
747 || ISA_MIPS32R2 \
748 || ISA_MIPS64)
749
750 /* This is a catch all for other mips4 instructions: indexed load, the
751 FP madd and msub instructions, and the FP recip and recip sqrt
752 instructions. */
753 #define ISA_HAS_FP4 ((ISA_MIPS4 \
754 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
755 || ISA_MIPS64) \
756 && !TARGET_MIPS16)
757
758 /* ISA has conditional trap instructions. */
759 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
760 && !TARGET_MIPS16)
761
762 /* ISA has integer multiply-accumulate instructions, madd and msub. */
763 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
764 || ISA_MIPS32R2 \
765 || ISA_MIPS64) \
766 && !TARGET_MIPS16)
767
768 /* Integer multiply-accumulate instructions should be generated. */
769 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
770
771 /* ISA has floating-point nmadd and nmsub instructions. */
772 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
773 || ISA_MIPS64) \
774 && (!TARGET_MIPS5400 || TARGET_MAD) \
775 && !TARGET_MIPS16)
776
777 /* ISA has count leading zeroes/ones instruction (not implemented). */
778 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
779 || ISA_MIPS32R2 \
780 || ISA_MIPS64) \
781 && !TARGET_MIPS16)
782
783 /* ISA has three operand multiply instructions that put
784 the high part in an accumulator: mulhi or mulhiu. */
785 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
786 || TARGET_MIPS5500 \
787 || TARGET_SR71K) \
788 && !TARGET_MIPS16)
789
790 /* ISA has three operand multiply instructions that
791 negates the result and puts the result in an accumulator. */
792 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
793 || TARGET_MIPS5500 \
794 || TARGET_SR71K) \
795 && !TARGET_MIPS16)
796
797 /* ISA has three operand multiply instructions that subtracts the
798 result from a 4th operand and puts the result in an accumulator. */
799 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
800 || TARGET_MIPS5500 \
801 || TARGET_SR71K) \
802 && !TARGET_MIPS16)
803
804 /* ISA has three operand multiply instructions that the result
805 from a 4th operand and puts the result in an accumulator. */
806 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
807 || TARGET_MIPS4130 \
808 || TARGET_MIPS5400 \
809 || TARGET_MIPS5500 \
810 || TARGET_SR71K) \
811 && !TARGET_MIPS16)
812
813 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
814 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
815 || TARGET_MIPS4130) \
816 && !TARGET_MIPS16)
817
818 /* ISA has the "ror" (rotate right) instructions. */
819 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
820 || TARGET_MIPS5400 \
821 || TARGET_MIPS5500 \
822 || TARGET_SR71K \
823 || TARGET_SMARTMIPS) \
824 && !TARGET_MIPS16)
825
826 /* ISA has data prefetch instructions. This controls use of 'pref'. */
827 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
828 || ISA_MIPS32 \
829 || ISA_MIPS32R2 \
830 || ISA_MIPS64) \
831 && !TARGET_MIPS16)
832
833 /* ISA has data indexed prefetch instructions. This controls use of
834 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
835 (prefx is a cop1x instruction, so can only be used if FP is
836 enabled.) */
837 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
838 || ISA_MIPS32R2 \
839 || ISA_MIPS64) \
840 && !TARGET_MIPS16)
841
842 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
843 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
844 also requires TARGET_DOUBLE_FLOAT. */
845 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
846
847 /* ISA includes the MIPS32r2 seb and seh instructions. */
848 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
849 && !TARGET_MIPS16)
850
851 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
852 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
853 && !TARGET_MIPS16)
854
855 /* ISA has instructions for accessing top part of 64-bit fp regs. */
856 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
857
858 /* ISA has lwxs instruction (load w/scaled index address. */
859 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
860
861 /* True if the result of a load is not available to the next instruction.
862 A nop will then be needed between instructions like "lw $4,..."
863 and "addiu $4,$4,1". */
864 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
865 && !TARGET_MIPS3900 \
866 && !TARGET_MIPS16)
867
868 /* Likewise mtc1 and mfc1. */
869 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
870
871 /* Likewise floating-point comparisons. */
872 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
873
874 /* True if mflo and mfhi can be immediately followed by instructions
875 which write to the HI and LO registers.
876
877 According to MIPS specifications, MIPS ISAs I, II, and III need
878 (at least) two instructions between the reads of HI/LO and
879 instructions which write them, and later ISAs do not. Contradicting
880 the MIPS specifications, some MIPS IV processor user manuals (e.g.
881 the UM for the NEC Vr5000) document needing the instructions between
882 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
883 MIPS64 and later ISAs to have the interlocks, plus any specific
884 earlier-ISA CPUs for which CPU documentation declares that the
885 instructions are really interlocked. */
886 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
887 || ISA_MIPS32R2 \
888 || ISA_MIPS64 \
889 || TARGET_MIPS5500)
890
891 /* ISA includes synci, jr.hb and jalr.hb. */
892 #define ISA_HAS_SYNCI (ISA_MIPS32R2 && !TARGET_MIPS16)
893
894 /* ISA includes sync. */
895 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
896
897 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
898 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
899 instructions. */
900 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
901 \f
902 /* Add -G xx support. */
903
904 #undef SWITCH_TAKES_ARG
905 #define SWITCH_TAKES_ARG(CHAR) \
906 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
907
908 #define OVERRIDE_OPTIONS override_options ()
909
910 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
911
912 /* Show we can debug even without a frame pointer. */
913 #define CAN_DEBUG_WITHOUT_FP
914 \f
915 /* Tell collect what flags to pass to nm. */
916 #ifndef NM_FLAGS
917 #define NM_FLAGS "-Bn"
918 #endif
919
920 \f
921 #ifndef MIPS_ABI_DEFAULT
922 #define MIPS_ABI_DEFAULT ABI_32
923 #endif
924
925 /* Use the most portable ABI flag for the ASM specs. */
926
927 #if MIPS_ABI_DEFAULT == ABI_32
928 #define MULTILIB_ABI_DEFAULT "mabi=32"
929 #endif
930
931 #if MIPS_ABI_DEFAULT == ABI_O64
932 #define MULTILIB_ABI_DEFAULT "mabi=o64"
933 #endif
934
935 #if MIPS_ABI_DEFAULT == ABI_N32
936 #define MULTILIB_ABI_DEFAULT "mabi=n32"
937 #endif
938
939 #if MIPS_ABI_DEFAULT == ABI_64
940 #define MULTILIB_ABI_DEFAULT "mabi=64"
941 #endif
942
943 #if MIPS_ABI_DEFAULT == ABI_EABI
944 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
945 #endif
946
947 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
948 to the assembler. It may be overridden by subtargets. */
949 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
950 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
951 %{noasmopt:-O0} \
952 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
953 #endif
954
955 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
956 the assembler. It may be overridden by subtargets.
957
958 Beginning with gas 2.13, -mdebug must be passed to correctly handle
959 COFF debugging info. */
960
961 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
962 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
963 %{g} %{g0} %{g1} %{g2} %{g3} \
964 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
965 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
966 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
967 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
968 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
969 #endif
970
971 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
972 overridden by subtargets. */
973
974 #ifndef SUBTARGET_ASM_SPEC
975 #define SUBTARGET_ASM_SPEC ""
976 #endif
977
978 #undef ASM_SPEC
979 #define ASM_SPEC "\
980 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
981 %{mips32} %{mips32r2} %{mips64} \
982 %{mips16} %{mno-mips16:-no-mips16} \
983 %{mips3d} %{mno-mips3d:-no-mips3d} \
984 %{mdmx} %{mno-mdmx:-no-mdmx} \
985 %{mdsp} %{mno-dsp} \
986 %{mdspr2} %{mno-dspr2} \
987 %{msmartmips} %{mno-smartmips} \
988 %{mmt} %{mno-mt} \
989 %{mfix-vr4120} %{mfix-vr4130} \
990 %(subtarget_asm_optimizing_spec) \
991 %(subtarget_asm_debugging_spec) \
992 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
993 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
994 %{mfp32} %{mfp64} \
995 %{mshared} %{mno-shared} \
996 %{msym32} %{mno-sym32} \
997 %{mtune=*} %{v} \
998 %(subtarget_asm_spec)"
999
1000 /* Extra switches sometimes passed to the linker. */
1001 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1002 will interpret it as a -b option. */
1003
1004 #ifndef LINK_SPEC
1005 #define LINK_SPEC "\
1006 %(endian_spec) \
1007 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1008 %{bestGnum} %{shared} %{non_shared}"
1009 #endif /* LINK_SPEC defined */
1010
1011
1012 /* Specs for the compiler proper */
1013
1014 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1015 overridden by subtargets. */
1016 #ifndef SUBTARGET_CC1_SPEC
1017 #define SUBTARGET_CC1_SPEC ""
1018 #endif
1019
1020 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1021
1022 #undef CC1_SPEC
1023 #define CC1_SPEC "\
1024 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1025 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1026 %{save-temps: } \
1027 %(subtarget_cc1_spec)"
1028
1029 /* Preprocessor specs. */
1030
1031 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1032 overridden by subtargets. */
1033 #ifndef SUBTARGET_CPP_SPEC
1034 #define SUBTARGET_CPP_SPEC ""
1035 #endif
1036
1037 #define CPP_SPEC "%(subtarget_cpp_spec)"
1038
1039 /* This macro defines names of additional specifications to put in the specs
1040 that can be used in various specifications like CC1_SPEC. Its definition
1041 is an initializer with a subgrouping for each command option.
1042
1043 Each subgrouping contains a string constant, that defines the
1044 specification name, and a string constant that used by the GCC driver
1045 program.
1046
1047 Do not define this macro if it does not need to do anything. */
1048
1049 #define EXTRA_SPECS \
1050 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1051 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1052 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1053 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1054 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1055 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1056 { "endian_spec", ENDIAN_SPEC }, \
1057 SUBTARGET_EXTRA_SPECS
1058
1059 #ifndef SUBTARGET_EXTRA_SPECS
1060 #define SUBTARGET_EXTRA_SPECS
1061 #endif
1062 \f
1063 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1064 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1065 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1066
1067 #ifndef PREFERRED_DEBUGGING_TYPE
1068 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1069 #endif
1070
1071 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1072
1073 /* By default, turn on GDB extensions. */
1074 #define DEFAULT_GDB_EXTENSIONS 1
1075
1076 /* Local compiler-generated symbols must have a prefix that the assembler
1077 understands. By default, this is $, although some targets (e.g.,
1078 NetBSD-ELF) need to override this. */
1079
1080 #ifndef LOCAL_LABEL_PREFIX
1081 #define LOCAL_LABEL_PREFIX "$"
1082 #endif
1083
1084 /* By default on the mips, external symbols do not have an underscore
1085 prepended, but some targets (e.g., NetBSD) require this. */
1086
1087 #ifndef USER_LABEL_PREFIX
1088 #define USER_LABEL_PREFIX ""
1089 #endif
1090
1091 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1092 since the length can run past this up to a continuation point. */
1093 #undef DBX_CONTIN_LENGTH
1094 #define DBX_CONTIN_LENGTH 1500
1095
1096 /* How to renumber registers for dbx and gdb. */
1097 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1098
1099 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1100 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1101
1102 /* The DWARF 2 CFA column which tracks the return address. */
1103 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1104
1105 /* Before the prologue, RA lives in r31. */
1106 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1107
1108 /* Describe how we implement __builtin_eh_return. */
1109 #define EH_RETURN_DATA_REGNO(N) \
1110 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1111
1112 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1113
1114 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1115 The default for this in 64-bit mode is 8, which causes problems with
1116 SFmode register saves. */
1117 #define DWARF_CIE_DATA_ALIGNMENT -4
1118
1119 /* Correct the offset of automatic variables and arguments. Note that
1120 the MIPS debug format wants all automatic variables and arguments
1121 to be in terms of the virtual frame pointer (stack pointer before
1122 any adjustment in the function), while the MIPS 3.0 linker wants
1123 the frame pointer to be the stack pointer after the initial
1124 adjustment. */
1125
1126 #define DEBUGGER_AUTO_OFFSET(X) \
1127 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1128 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1129 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1130 \f
1131 /* Target machine storage layout */
1132
1133 #define BITS_BIG_ENDIAN 0
1134 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1135 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1136
1137 /* Define this to set the endianness to use in libgcc2.c, which can
1138 not depend on target_flags. */
1139 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1140 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1141 #else
1142 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1143 #endif
1144
1145 #define MAX_BITS_PER_WORD 64
1146
1147 /* Width of a word, in units (bytes). */
1148 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1149 #ifndef IN_LIBGCC2
1150 #define MIN_UNITS_PER_WORD 4
1151 #endif
1152
1153 /* For MIPS, width of a floating point register. */
1154 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1155
1156 /* The number of consecutive floating-point registers needed to store the
1157 largest format supported by the FPU. */
1158 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1159
1160 /* The number of consecutive floating-point registers needed to store the
1161 smallest format supported by the FPU. */
1162 #define MIN_FPRS_PER_FMT \
1163 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 ? 1 : MAX_FPRS_PER_FMT)
1164
1165 /* The largest size of value that can be held in floating-point
1166 registers and moved with a single instruction. */
1167 #define UNITS_PER_HWFPVALUE \
1168 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1169
1170 /* The largest size of value that can be held in floating-point
1171 registers. */
1172 #define UNITS_PER_FPVALUE \
1173 (TARGET_SOFT_FLOAT_ABI ? 0 \
1174 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1175 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1176
1177 /* The number of bytes in a double. */
1178 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1179
1180 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1181
1182 /* Set the sizes of the core types. */
1183 #define SHORT_TYPE_SIZE 16
1184 #define INT_TYPE_SIZE 32
1185 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1186 #define LONG_LONG_TYPE_SIZE 64
1187
1188 #define FLOAT_TYPE_SIZE 32
1189 #define DOUBLE_TYPE_SIZE 64
1190 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1191
1192 /* Define the sizes of fixed-point types. */
1193 #define SHORT_FRACT_TYPE_SIZE 8
1194 #define FRACT_TYPE_SIZE 16
1195 #define LONG_FRACT_TYPE_SIZE 32
1196 #define LONG_LONG_FRACT_TYPE_SIZE 64
1197
1198 #define SHORT_ACCUM_TYPE_SIZE 16
1199 #define ACCUM_TYPE_SIZE 32
1200 #define LONG_ACCUM_TYPE_SIZE 64
1201 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1202 doesn't support 128-bit integers for MIPS32 currently. */
1203 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1204
1205 /* long double is not a fixed mode, but the idea is that, if we
1206 support long double, we also want a 128-bit integer type. */
1207 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1208
1209 #ifdef IN_LIBGCC2
1210 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1211 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1212 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1213 # else
1214 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1215 # endif
1216 #endif
1217
1218 /* Width in bits of a pointer. */
1219 #ifndef POINTER_SIZE
1220 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1221 #endif
1222
1223 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1224 #define PARM_BOUNDARY BITS_PER_WORD
1225
1226 /* Allocation boundary (in *bits*) for the code of a function. */
1227 #define FUNCTION_BOUNDARY 32
1228
1229 /* Alignment of field after `int : 0' in a structure. */
1230 #define EMPTY_FIELD_BOUNDARY 32
1231
1232 /* Every structure's size must be a multiple of this. */
1233 /* 8 is observed right on a DECstation and on riscos 4.02. */
1234 #define STRUCTURE_SIZE_BOUNDARY 8
1235
1236 /* There is no point aligning anything to a rounder boundary than this. */
1237 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1238
1239 /* All accesses must be aligned. */
1240 #define STRICT_ALIGNMENT 1
1241
1242 /* Define this if you wish to imitate the way many other C compilers
1243 handle alignment of bitfields and the structures that contain
1244 them.
1245
1246 The behavior is that the type written for a bit-field (`int',
1247 `short', or other integer type) imposes an alignment for the
1248 entire structure, as if the structure really did contain an
1249 ordinary field of that type. In addition, the bit-field is placed
1250 within the structure so that it would fit within such a field,
1251 not crossing a boundary for it.
1252
1253 Thus, on most machines, a bit-field whose type is written as `int'
1254 would not cross a four-byte boundary, and would force four-byte
1255 alignment for the whole structure. (The alignment used may not
1256 be four bytes; it is controlled by the other alignment
1257 parameters.)
1258
1259 If the macro is defined, its definition should be a C expression;
1260 a nonzero value for the expression enables this behavior. */
1261
1262 #define PCC_BITFIELD_TYPE_MATTERS 1
1263
1264 /* If defined, a C expression to compute the alignment given to a
1265 constant that is being placed in memory. CONSTANT is the constant
1266 and ALIGN is the alignment that the object would ordinarily have.
1267 The value of this macro is used instead of that alignment to align
1268 the object.
1269
1270 If this macro is not defined, then ALIGN is used.
1271
1272 The typical use of this macro is to increase alignment for string
1273 constants to be word aligned so that `strcpy' calls that copy
1274 constants can be done inline. */
1275
1276 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1277 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1278 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1279
1280 /* If defined, a C expression to compute the alignment for a static
1281 variable. TYPE is the data type, and ALIGN is the alignment that
1282 the object would ordinarily have. The value of this macro is used
1283 instead of that alignment to align the object.
1284
1285 If this macro is not defined, then ALIGN is used.
1286
1287 One use of this macro is to increase alignment of medium-size
1288 data to make it all fit in fewer cache lines. Another is to
1289 cause character arrays to be word-aligned so that `strcpy' calls
1290 that copy constants to character arrays can be done inline. */
1291
1292 #undef DATA_ALIGNMENT
1293 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1294 ((((ALIGN) < BITS_PER_WORD) \
1295 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1296 || TREE_CODE (TYPE) == UNION_TYPE \
1297 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1298
1299
1300 #define PAD_VARARGS_DOWN \
1301 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1302
1303 /* Define if operations between registers always perform the operation
1304 on the full register even if a narrower mode is specified. */
1305 #define WORD_REGISTER_OPERATIONS
1306
1307 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1308 moves. All other references are zero extended. */
1309 #define LOAD_EXTEND_OP(MODE) \
1310 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1311 ? SIGN_EXTEND : ZERO_EXTEND)
1312
1313 /* Define this macro if it is advisable to hold scalars in registers
1314 in a wider mode than that declared by the program. In such cases,
1315 the value is constrained to be within the bounds of the declared
1316 type, but kept valid in the wider mode. The signedness of the
1317 extension may differ from that of the type. */
1318
1319 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1320 if (GET_MODE_CLASS (MODE) == MODE_INT \
1321 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1322 { \
1323 if ((MODE) == SImode) \
1324 (UNSIGNEDP) = 0; \
1325 (MODE) = Pmode; \
1326 }
1327
1328 /* Define if loading short immediate values into registers sign extends. */
1329 #define SHORT_IMMEDIATES_SIGN_EXTEND
1330
1331 /* The [d]clz instructions have the natural values at 0. */
1332
1333 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1334 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1335 \f
1336 /* Standard register usage. */
1337
1338 /* Number of hardware registers. We have:
1339
1340 - 32 integer registers
1341 - 32 floating point registers
1342 - 8 condition code registers
1343 - 2 accumulator registers (hi and lo)
1344 - 32 registers each for coprocessors 0, 2 and 3
1345 - 3 fake registers:
1346 - ARG_POINTER_REGNUM
1347 - FRAME_POINTER_REGNUM
1348 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1349 - 3 dummy entries that were used at various times in the past.
1350 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1351 - 6 DSP control registers */
1352
1353 #define FIRST_PSEUDO_REGISTER 188
1354
1355 /* By default, fix the kernel registers ($26 and $27), the global
1356 pointer ($28) and the stack pointer ($29). This can change
1357 depending on the command-line options.
1358
1359 Regarding coprocessor registers: without evidence to the contrary,
1360 it's best to assume that each coprocessor register has a unique
1361 use. This can be overridden, in, e.g., override_options() or
1362 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1363 for a particular target. */
1364
1365 #define FIXED_REGISTERS \
1366 { \
1367 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1368 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1369 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1370 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1371 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1372 /* COP0 registers */ \
1373 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1374 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1375 /* COP2 registers */ \
1376 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1377 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1378 /* COP3 registers */ \
1379 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1380 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1381 /* 6 DSP accumulator registers & 6 control registers */ \
1382 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1383 }
1384
1385
1386 /* Set up this array for o32 by default.
1387
1388 Note that we don't mark $31 as a call-clobbered register. The idea is
1389 that it's really the call instructions themselves which clobber $31.
1390 We don't care what the called function does with it afterwards.
1391
1392 This approach makes it easier to implement sibcalls. Unlike normal
1393 calls, sibcalls don't clobber $31, so the register reaches the
1394 called function in tact. EPILOGUE_USES says that $31 is useful
1395 to the called function. */
1396
1397 #define CALL_USED_REGISTERS \
1398 { \
1399 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1400 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1401 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1402 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1403 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1404 /* COP0 registers */ \
1405 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1406 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1407 /* COP2 registers */ \
1408 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1409 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1410 /* COP3 registers */ \
1411 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1412 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1413 /* 6 DSP accumulator registers & 6 control registers */ \
1414 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1415 }
1416
1417
1418 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1419
1420 #define CALL_REALLY_USED_REGISTERS \
1421 { /* General registers. */ \
1422 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1423 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1424 /* Floating-point registers. */ \
1425 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1426 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1427 /* Others. */ \
1428 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1429 /* COP0 registers */ \
1430 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1431 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1432 /* COP2 registers */ \
1433 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1434 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1435 /* COP3 registers */ \
1436 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1437 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1438 /* 6 DSP accumulator registers & 6 control registers */ \
1439 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1440 }
1441
1442 /* Internal macros to classify a register number as to whether it's a
1443 general purpose register, a floating point register, a
1444 multiply/divide register, or a status register. */
1445
1446 #define GP_REG_FIRST 0
1447 #define GP_REG_LAST 31
1448 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1449 #define GP_DBX_FIRST 0
1450
1451 #define FP_REG_FIRST 32
1452 #define FP_REG_LAST 63
1453 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1454 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1455
1456 #define MD_REG_FIRST 64
1457 #define MD_REG_LAST 65
1458 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1459 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1460
1461 /* The DWARF 2 CFA column which tracks the return address from a
1462 signal handler context. This means that to maintain backwards
1463 compatibility, no hard register can be assigned this column if it
1464 would need to be handled by the DWARF unwinder. */
1465 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1466
1467 #define ST_REG_FIRST 67
1468 #define ST_REG_LAST 74
1469 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1470
1471
1472 /* FIXME: renumber. */
1473 #define COP0_REG_FIRST 80
1474 #define COP0_REG_LAST 111
1475 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1476
1477 #define COP2_REG_FIRST 112
1478 #define COP2_REG_LAST 143
1479 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1480
1481 #define COP3_REG_FIRST 144
1482 #define COP3_REG_LAST 175
1483 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1484 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1485 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1486
1487 #define DSP_ACC_REG_FIRST 176
1488 #define DSP_ACC_REG_LAST 181
1489 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1490
1491 #define AT_REGNUM (GP_REG_FIRST + 1)
1492 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1493 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1494
1495 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1496 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1497 should be used instead. */
1498 #define FPSW_REGNUM ST_REG_FIRST
1499
1500 #define GP_REG_P(REGNO) \
1501 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1502 #define M16_REG_P(REGNO) \
1503 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1504 #define FP_REG_P(REGNO) \
1505 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1506 #define MD_REG_P(REGNO) \
1507 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1508 #define ST_REG_P(REGNO) \
1509 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1510 #define COP0_REG_P(REGNO) \
1511 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1512 #define COP2_REG_P(REGNO) \
1513 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1514 #define COP3_REG_P(REGNO) \
1515 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1516 #define ALL_COP_REG_P(REGNO) \
1517 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1518 /* Test if REGNO is one of the 6 new DSP accumulators. */
1519 #define DSP_ACC_REG_P(REGNO) \
1520 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1521 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1522 #define ACC_REG_P(REGNO) \
1523 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1524
1525 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1526
1527 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1528 to initialize the mips16 gp pseudo register. */
1529 #define CONST_GP_P(X) \
1530 (GET_CODE (X) == CONST \
1531 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1532 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1533
1534 /* Return coprocessor number from register number. */
1535
1536 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1537 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1538 : COP3_REG_P (REGNO) ? '3' : '?')
1539
1540
1541 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1542
1543 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1544 array built in override_options. Because machmodes.h is not yet
1545 included before this file is processed, the MODE bound can't be
1546 expressed here. */
1547
1548 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1549
1550 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1551 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1552
1553 /* Value is 1 if it is a good idea to tie two pseudo registers
1554 when one has mode MODE1 and one has mode MODE2.
1555 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1556 for any hard reg, then this must be 0 for correct output. */
1557 #define MODES_TIEABLE_P(MODE1, MODE2) \
1558 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1559 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1560 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1561 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1562
1563 /* Register to use for pushing function arguments. */
1564 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1565
1566 /* These two registers don't really exist: they get eliminated to either
1567 the stack or hard frame pointer. */
1568 #define ARG_POINTER_REGNUM 77
1569 #define FRAME_POINTER_REGNUM 78
1570
1571 /* $30 is not available on the mips16, so we use $17 as the frame
1572 pointer. */
1573 #define HARD_FRAME_POINTER_REGNUM \
1574 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1575
1576 /* Value should be nonzero if functions must have frame pointers.
1577 Zero means the frame pointer need not be set up (and parms
1578 may be accessed via the stack pointer) in functions that seem suitable.
1579 This is computed in `reload', in reload1.c. */
1580 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1581
1582 /* Register in which static-chain is passed to a function. */
1583 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1584
1585 /* Registers used as temporaries in prologue/epilogue code. If we're
1586 generating mips16 code, these registers must come from the core set
1587 of 8. The prologue register mustn't conflict with any incoming
1588 arguments, the static chain pointer, or the frame pointer. The
1589 epilogue temporary mustn't conflict with the return registers, the
1590 frame pointer, the EH stack adjustment, or the EH data registers. */
1591
1592 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1593 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1594
1595 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1596 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1597
1598 /* Define this macro if it is as good or better to call a constant
1599 function address than to call an address kept in a register. */
1600 #define NO_FUNCTION_CSE 1
1601
1602 /* The ABI-defined global pointer. Sometimes we use a different
1603 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1604 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1605
1606 /* We normally use $28 as the global pointer. However, when generating
1607 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1608 register instead. They can then avoid saving and restoring $28
1609 and perhaps avoid using a frame at all.
1610
1611 When a leaf function uses something other than $28, mips_expand_prologue
1612 will modify pic_offset_table_rtx in place. Take the register number
1613 from there after reload. */
1614 #define PIC_OFFSET_TABLE_REGNUM \
1615 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1616
1617 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1618 \f
1619 /* Define the classes of registers for register constraints in the
1620 machine description. Also define ranges of constants.
1621
1622 One of the classes must always be named ALL_REGS and include all hard regs.
1623 If there is more than one class, another class must be named NO_REGS
1624 and contain no registers.
1625
1626 The name GENERAL_REGS must be the name of a class (or an alias for
1627 another name such as ALL_REGS). This is the class of registers
1628 that is allowed by "g" or "r" in a register constraint.
1629 Also, registers outside this class are allocated only when
1630 instructions express preferences for them.
1631
1632 The classes must be numbered in nondecreasing order; that is,
1633 a larger-numbered class must never be contained completely
1634 in a smaller-numbered class.
1635
1636 For any two classes, it is very desirable that there be another
1637 class that represents their union. */
1638
1639 enum reg_class
1640 {
1641 NO_REGS, /* no registers in set */
1642 M16_NA_REGS, /* mips16 regs not used to pass args */
1643 M16_REGS, /* mips16 directly accessible registers */
1644 T_REG, /* mips16 T register ($24) */
1645 M16_T_REGS, /* mips16 registers plus T register */
1646 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1647 V1_REG, /* Register $v1 ($3) used for TLS access. */
1648 LEA_REGS, /* Every GPR except $25 */
1649 GR_REGS, /* integer registers */
1650 FP_REGS, /* floating point registers */
1651 MD0_REG, /* first multiply/divide register */
1652 MD1_REG, /* second multiply/divide register */
1653 MD_REGS, /* multiply/divide registers (hi/lo) */
1654 COP0_REGS, /* generic coprocessor classes */
1655 COP2_REGS,
1656 COP3_REGS,
1657 HI_AND_GR_REGS, /* union classes */
1658 LO_AND_GR_REGS,
1659 HI_AND_FP_REGS,
1660 COP0_AND_GR_REGS,
1661 COP2_AND_GR_REGS,
1662 COP3_AND_GR_REGS,
1663 ALL_COP_REGS,
1664 ALL_COP_AND_GR_REGS,
1665 ST_REGS, /* status registers (fp status) */
1666 DSP_ACC_REGS, /* DSP accumulator registers */
1667 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1668 ALL_REGS, /* all registers */
1669 LIM_REG_CLASSES /* max value + 1 */
1670 };
1671
1672 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1673
1674 #define GENERAL_REGS GR_REGS
1675
1676 /* An initializer containing the names of the register classes as C
1677 string constants. These names are used in writing some of the
1678 debugging dumps. */
1679
1680 #define REG_CLASS_NAMES \
1681 { \
1682 "NO_REGS", \
1683 "M16_NA_REGS", \
1684 "M16_REGS", \
1685 "T_REG", \
1686 "M16_T_REGS", \
1687 "PIC_FN_ADDR_REG", \
1688 "V1_REG", \
1689 "LEA_REGS", \
1690 "GR_REGS", \
1691 "FP_REGS", \
1692 "MD0_REG", \
1693 "MD1_REG", \
1694 "MD_REGS", \
1695 /* coprocessor registers */ \
1696 "COP0_REGS", \
1697 "COP2_REGS", \
1698 "COP3_REGS", \
1699 "HI_AND_GR_REGS", \
1700 "LO_AND_GR_REGS", \
1701 "HI_AND_FP_REGS", \
1702 "COP0_AND_GR_REGS", \
1703 "COP2_AND_GR_REGS", \
1704 "COP3_AND_GR_REGS", \
1705 "ALL_COP_REGS", \
1706 "ALL_COP_AND_GR_REGS", \
1707 "ST_REGS", \
1708 "DSP_ACC_REGS", \
1709 "ACC_REGS", \
1710 "ALL_REGS" \
1711 }
1712
1713 /* An initializer containing the contents of the register classes,
1714 as integers which are bit masks. The Nth integer specifies the
1715 contents of class N. The way the integer MASK is interpreted is
1716 that register R is in the class if `MASK & (1 << R)' is 1.
1717
1718 When the machine has more than 32 registers, an integer does not
1719 suffice. Then the integers are replaced by sub-initializers,
1720 braced groupings containing several integers. Each
1721 sub-initializer must be suitable as an initializer for the type
1722 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1723
1724 #define REG_CLASS_CONTENTS \
1725 { \
1726 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1727 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1728 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1729 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1730 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1731 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1732 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1733 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1734 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1735 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1736 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1737 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1738 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1739 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1740 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1741 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1742 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1743 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1744 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1745 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1746 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1747 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1748 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1749 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1750 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1751 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1752 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1753 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1754 }
1755
1756
1757 /* A C expression whose value is a register class containing hard
1758 register REGNO. In general there is more that one such class;
1759 choose a class which is "minimal", meaning that no smaller class
1760 also contains the register. */
1761
1762 extern const enum reg_class mips_regno_to_class[];
1763
1764 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1765
1766 /* A macro whose definition is the name of the class to which a
1767 valid base register must belong. A base register is one used in
1768 an address which is the register value plus a displacement. */
1769
1770 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1771
1772 /* A macro whose definition is the name of the class to which a
1773 valid index register must belong. An index register is one used
1774 in an address where its value is either multiplied by a scale
1775 factor or added to another register (as well as added to a
1776 displacement). */
1777
1778 #define INDEX_REG_CLASS NO_REGS
1779
1780 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1781 registers explicitly used in the rtl to be used as spill registers
1782 but prevents the compiler from extending the lifetime of these
1783 registers. */
1784
1785 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1786
1787 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1788 is the default value (allocate the registers in numeric order). We
1789 define it just so that we can override it for the mips16 target in
1790 ORDER_REGS_FOR_LOCAL_ALLOC. */
1791
1792 #define REG_ALLOC_ORDER \
1793 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1794 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1795 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1796 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1797 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1798 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1799 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1800 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1801 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1802 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1803 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1804 176,177,178,179,180,181,182,183,184,185,186,187 \
1805 }
1806
1807 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1808 to be rearranged based on a particular function. On the mips16, we
1809 want to allocate $24 (T_REG) before other registers for
1810 instructions for which it is possible. */
1811
1812 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1813
1814 /* True if VALUE is an unsigned 6-bit number. */
1815
1816 #define UIMM6_OPERAND(VALUE) \
1817 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1818
1819 /* True if VALUE is a signed 10-bit number. */
1820
1821 #define IMM10_OPERAND(VALUE) \
1822 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1823
1824 /* True if VALUE is a signed 16-bit number. */
1825
1826 #define SMALL_OPERAND(VALUE) \
1827 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1828
1829 /* True if VALUE is an unsigned 16-bit number. */
1830
1831 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1832 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1833
1834 /* True if VALUE can be loaded into a register using LUI. */
1835
1836 #define LUI_OPERAND(VALUE) \
1837 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1838 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1839
1840 /* Return a value X with the low 16 bits clear, and such that
1841 VALUE - X is a signed 16-bit value. */
1842
1843 #define CONST_HIGH_PART(VALUE) \
1844 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1845
1846 #define CONST_LOW_PART(VALUE) \
1847 ((VALUE) - CONST_HIGH_PART (VALUE))
1848
1849 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1850 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1851 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1852
1853 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1854 mips_preferred_reload_class (X, CLASS)
1855
1856 /* The HI and LO registers can only be reloaded via the general
1857 registers. Condition code registers can only be loaded to the
1858 general registers, and from the floating point registers. */
1859
1860 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1861 mips_secondary_reload_class (CLASS, MODE, X, 1)
1862 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1863 mips_secondary_reload_class (CLASS, MODE, X, 0)
1864
1865 /* Return the maximum number of consecutive registers
1866 needed to represent mode MODE in a register of class CLASS. */
1867
1868 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1869
1870 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1871 mips_cannot_change_mode_class (FROM, TO, CLASS)
1872 \f
1873 /* Stack layout; function entry, exit and calling. */
1874
1875 #define STACK_GROWS_DOWNWARD
1876
1877 /* The offset of the first local variable from the beginning of the frame.
1878 See compute_frame_size for details about the frame layout.
1879
1880 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1881 we assume that we will need 16 bytes of argument space. This is because
1882 the value profiling code may emit calls to cmpdi2 in leaf functions.
1883 Without this hack, the local variables will start at sp+8 and the gp save
1884 area will be at sp+16, and thus they will overlap. compute_frame_size is
1885 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1886 will end up as 24 instead of 8. This won't be needed if profiling code is
1887 inserted before virtual register instantiation. */
1888
1889 #define STARTING_FRAME_OFFSET \
1890 ((flag_profile_values && ! TARGET_64BIT \
1891 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1892 : current_function_outgoing_args_size) \
1893 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1894
1895 #define RETURN_ADDR_RTX mips_return_addr
1896
1897 /* Since the mips16 ISA mode is encoded in the least-significant bit
1898 of the address, mask it off return addresses for purposes of
1899 finding exception handling regions. */
1900
1901 #define MASK_RETURN_ADDR GEN_INT (-2)
1902
1903
1904 /* Similarly, don't use the least-significant bit to tell pointers to
1905 code from vtable index. */
1906
1907 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1908
1909 /* The eliminations to $17 are only used for mips16 code. See the
1910 definition of HARD_FRAME_POINTER_REGNUM. */
1911
1912 #define ELIMINABLE_REGS \
1913 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1914 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1915 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1916 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1917 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1918 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1919
1920 /* We can always eliminate to the hard frame pointer. We can eliminate
1921 to the stack pointer unless a frame pointer is needed.
1922
1923 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1924 reload may be unable to compute the address of a local variable,
1925 since there is no way to add a large constant to the stack pointer
1926 without using a temporary register. */
1927 #define CAN_ELIMINATE(FROM, TO) \
1928 ((TO) == HARD_FRAME_POINTER_REGNUM \
1929 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1930 && (!TARGET_MIPS16 \
1931 || compute_frame_size (get_frame_size ()) < 32768)))
1932
1933 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1934 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1935
1936 /* Allocate stack space for arguments at the beginning of each function. */
1937 #define ACCUMULATE_OUTGOING_ARGS 1
1938
1939 /* The argument pointer always points to the first argument. */
1940 #define FIRST_PARM_OFFSET(FNDECL) 0
1941
1942 /* o32 and o64 reserve stack space for all argument registers. */
1943 #define REG_PARM_STACK_SPACE(FNDECL) \
1944 (TARGET_OLDABI \
1945 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1946 : 0)
1947
1948 /* Define this if it is the responsibility of the caller to
1949 allocate the area reserved for arguments passed in registers.
1950 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1951 of this macro is to determine whether the space is included in
1952 `current_function_outgoing_args_size'. */
1953 #define OUTGOING_REG_PARM_STACK_SPACE 1
1954
1955 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1956 \f
1957 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1958
1959 /* Symbolic macros for the registers used to return integer and floating
1960 point values. */
1961
1962 #define GP_RETURN (GP_REG_FIRST + 2)
1963 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1964
1965 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1966
1967 /* Symbolic macros for the first/last argument registers. */
1968
1969 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1970 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1971 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1972 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1973
1974 #define LIBCALL_VALUE(MODE) \
1975 mips_function_value (NULL_TREE, NULL, (MODE))
1976
1977 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1978 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1979
1980 /* 1 if N is a possible register number for a function value.
1981 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1982 Currently, R2 and F0 are only implemented here (C has no complex type) */
1983
1984 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1985 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1986 && (N) == FP_RETURN + 2))
1987
1988 /* 1 if N is a possible register number for function argument passing.
1989 We have no FP argument registers when soft-float. When FP registers
1990 are 32 bits, we can't directly reference the odd numbered ones. */
1991
1992 #define FUNCTION_ARG_REGNO_P(N) \
1993 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1994 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1995 && !fixed_regs[N])
1996 \f
1997 /* This structure has to cope with two different argument allocation
1998 schemes. Most MIPS ABIs view the arguments as a structure, of which
1999 the first N words go in registers and the rest go on the stack. If I
2000 < N, the Ith word might go in Ith integer argument register or in a
2001 floating-point register. For these ABIs, we only need to remember
2002 the offset of the current argument into the structure.
2003
2004 The EABI instead allocates the integer and floating-point arguments
2005 separately. The first N words of FP arguments go in FP registers,
2006 the rest go on the stack. Likewise, the first N words of the other
2007 arguments go in integer registers, and the rest go on the stack. We
2008 need to maintain three counts: the number of integer registers used,
2009 the number of floating-point registers used, and the number of words
2010 passed on the stack.
2011
2012 We could keep separate information for the two ABIs (a word count for
2013 the standard ABIs, and three separate counts for the EABI). But it
2014 seems simpler to view the standard ABIs as forms of EABI that do not
2015 allocate floating-point registers.
2016
2017 So for the standard ABIs, the first N words are allocated to integer
2018 registers, and function_arg decides on an argument-by-argument basis
2019 whether that argument should really go in an integer register, or in
2020 a floating-point one. */
2021
2022 typedef struct mips_args {
2023 /* Always true for varargs functions. Otherwise true if at least
2024 one argument has been passed in an integer register. */
2025 int gp_reg_found;
2026
2027 /* The number of arguments seen so far. */
2028 unsigned int arg_number;
2029
2030 /* The number of integer registers used so far. For all ABIs except
2031 EABI, this is the number of words that have been added to the
2032 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2033 unsigned int num_gprs;
2034
2035 /* For EABI, the number of floating-point registers used so far. */
2036 unsigned int num_fprs;
2037
2038 /* The number of words passed on the stack. */
2039 unsigned int stack_words;
2040
2041 /* On the mips16, we need to keep track of which floating point
2042 arguments were passed in general registers, but would have been
2043 passed in the FP regs if this were a 32-bit function, so that we
2044 can move them to the FP regs if we wind up calling a 32-bit
2045 function. We record this information in fp_code, encoded in base
2046 four. A zero digit means no floating point argument, a one digit
2047 means an SFmode argument, and a two digit means a DFmode argument,
2048 and a three digit is not used. The low order digit is the first
2049 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2050 an SFmode argument. ??? A more sophisticated approach will be
2051 needed if MIPS_ABI != ABI_32. */
2052 int fp_code;
2053
2054 /* True if the function has a prototype. */
2055 int prototype;
2056 } CUMULATIVE_ARGS;
2057
2058 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2059 for a call to a function whose data type is FNTYPE.
2060 For a library call, FNTYPE is 0. */
2061
2062 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2063 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2064
2065 /* Update the data in CUM to advance over an argument
2066 of mode MODE and data type TYPE.
2067 (TYPE is null for libcalls where that information may not be available.) */
2068
2069 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2070 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2071
2072 /* Determine where to put an argument to a function.
2073 Value is zero to push the argument on the stack,
2074 or a hard register in which to store the argument.
2075
2076 MODE is the argument's machine mode.
2077 TYPE is the data type of the argument (as a tree).
2078 This is null for libcalls where that information may
2079 not be available.
2080 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2081 the preceding args and about the function being called.
2082 NAMED is nonzero if this argument is a named parameter
2083 (otherwise it is an extra parameter matching an ellipsis). */
2084
2085 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2086 function_arg( &CUM, MODE, TYPE, NAMED)
2087
2088 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
2089
2090 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2091 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2092
2093 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2094 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2095
2096 /* True if using EABI and varargs can be passed in floating-point
2097 registers. Under these conditions, we need a more complex form
2098 of va_list, which tracks GPR, FPR and stack arguments separately. */
2099 #define EABI_FLOAT_VARARGS_P \
2100 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2101
2102 \f
2103 /* Say that the epilogue uses the return address register. Note that
2104 in the case of sibcalls, the values "used by the epilogue" are
2105 considered live at the start of the called function. */
2106 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2107
2108 /* Treat LOC as a byte offset from the stack pointer and round it up
2109 to the next fully-aligned offset. */
2110 #define MIPS_STACK_ALIGN(LOC) \
2111 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2112
2113 \f
2114 /* Implement `va_start' for varargs and stdarg. */
2115 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2116 mips_va_start (valist, nextarg)
2117 \f
2118 /* Output assembler code to FILE to increment profiler label # LABELNO
2119 for profiling a function entry. */
2120
2121 #define FUNCTION_PROFILER(FILE, LABELNO) \
2122 { \
2123 if (TARGET_MIPS16) \
2124 sorry ("mips16 function profiling"); \
2125 fprintf (FILE, "\t.set\tnoat\n"); \
2126 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2127 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2128 if (!TARGET_NEWABI) \
2129 { \
2130 fprintf (FILE, \
2131 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2132 TARGET_64BIT ? "dsubu" : "subu", \
2133 reg_names[STACK_POINTER_REGNUM], \
2134 reg_names[STACK_POINTER_REGNUM], \
2135 Pmode == DImode ? 16 : 8); \
2136 } \
2137 fprintf (FILE, "\tjal\t_mcount\n"); \
2138 fprintf (FILE, "\t.set\tat\n"); \
2139 }
2140
2141 /* No mips port has ever used the profiler counter word, so don't emit it
2142 or the label for it. */
2143
2144 #define NO_PROFILE_COUNTERS 1
2145
2146 /* Define this macro if the code for function profiling should come
2147 before the function prologue. Normally, the profiling code comes
2148 after. */
2149
2150 /* #define PROFILE_BEFORE_PROLOGUE */
2151
2152 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2153 the stack pointer does not matter. The value is tested only in
2154 functions that have frame pointers.
2155 No definition is equivalent to always zero. */
2156
2157 #define EXIT_IGNORE_STACK 1
2158
2159 \f
2160 /* A C statement to output, on the stream FILE, assembler code for a
2161 block of data that contains the constant parts of a trampoline.
2162 This code should not include a label--the label is taken care of
2163 automatically. */
2164
2165 #define TRAMPOLINE_TEMPLATE(STREAM) \
2166 { \
2167 if (ptr_mode == DImode) \
2168 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2169 else \
2170 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2171 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2172 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2173 if (ptr_mode == DImode) \
2174 { \
2175 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2176 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2177 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2178 } \
2179 else \
2180 { \
2181 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2182 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2183 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2184 } \
2185 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2186 if (ptr_mode == DImode) \
2187 { \
2188 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2189 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2190 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2191 } \
2192 else \
2193 { \
2194 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2195 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2196 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2197 } \
2198 }
2199
2200 /* A C expression for the size in bytes of the trampoline, as an
2201 integer. */
2202
2203 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2204
2205 /* Alignment required for trampolines, in bits. */
2206
2207 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2208
2209 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2210 program and data caches. */
2211
2212 #ifndef CACHE_FLUSH_FUNC
2213 #define CACHE_FLUSH_FUNC "_flush_cache"
2214 #endif
2215
2216 /* A C statement to initialize the variable parts of a trampoline.
2217 ADDR is an RTX for the address of the trampoline; FNADDR is an
2218 RTX for the address of the nested function; STATIC_CHAIN is an
2219 RTX for the static chain value that should be passed to the
2220 function when it is called. */
2221
2222 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2223 { \
2224 rtx func_addr, chain_addr, end_addr; \
2225 \
2226 func_addr = plus_constant (ADDR, 32); \
2227 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2228 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2229 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2230 end_addr = gen_reg_rtx (Pmode); \
2231 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2232 GEN_INT (TRAMPOLINE_SIZE))); \
2233 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2234 }
2235 \f
2236 /* Addressing modes, and classification of registers for them. */
2237
2238 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2239 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2240 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2241
2242 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2243 and check its validity for a certain class.
2244 We have two alternate definitions for each of them.
2245 The usual definition accepts all pseudo regs; the other rejects them all.
2246 The symbol REG_OK_STRICT causes the latter definition to be used.
2247
2248 Most source files want to accept pseudo regs in the hope that
2249 they will get allocated to the class that the insn wants them to be in.
2250 Some source files that are used after register allocation
2251 need to be strict. */
2252
2253 #ifndef REG_OK_STRICT
2254 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2255 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2256 #else
2257 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2258 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2259 #endif
2260
2261 #define REG_OK_FOR_INDEX_P(X) 0
2262
2263 \f
2264 /* Maximum number of registers that can appear in a valid memory address. */
2265
2266 #define MAX_REGS_PER_ADDRESS 1
2267
2268 #ifdef REG_OK_STRICT
2269 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2270 { \
2271 if (mips_legitimate_address_p (MODE, X, 1)) \
2272 goto ADDR; \
2273 }
2274 #else
2275 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2276 { \
2277 if (mips_legitimate_address_p (MODE, X, 0)) \
2278 goto ADDR; \
2279 }
2280 #endif
2281
2282 /* Check for constness inline but use mips_legitimate_address_p
2283 to check whether a constant really is an address. */
2284
2285 #define CONSTANT_ADDRESS_P(X) \
2286 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2287
2288 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2289
2290 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2291 do { \
2292 if (mips_legitimize_address (&(X), MODE)) \
2293 goto WIN; \
2294 } while (0)
2295
2296
2297 /* A C statement or compound statement with a conditional `goto
2298 LABEL;' executed if memory address X (an RTX) can have different
2299 meanings depending on the machine mode of the memory reference it
2300 is used for.
2301
2302 Autoincrement and autodecrement addresses typically have
2303 mode-dependent effects because the amount of the increment or
2304 decrement is the size of the operand being addressed. Some
2305 machines have other mode-dependent addresses. Many RISC machines
2306 have no mode-dependent addresses.
2307
2308 You may assume that ADDR is a valid address for the machine. */
2309
2310 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2311
2312 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2313 'the start of the function that this code is output in'. */
2314
2315 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2316 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2317 asm_fprintf ((FILE), "%U%s", \
2318 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2319 else \
2320 asm_fprintf ((FILE), "%U%s", (NAME))
2321 \f
2322 /* Flag to mark a function decl symbol that requires a long call. */
2323 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2324 #define SYMBOL_REF_LONG_CALL_P(X) \
2325 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2326
2327 /* Flag to mark a function decl symbol a "mips16" function. */
2328 #define SYMBOL_FLAG_MIPS16_FUNC (SYMBOL_FLAG_MACH_DEP << 1)
2329 #define SYMBOL_REF_MIPS16_FUNC_P(RTX) \
2330 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_MIPS16_FUNC) != 0)
2331
2332 /* True if we're generating a form of MIPS16 code in which jump tables
2333 are stored in the text section and encoded as 16-bit PC-relative
2334 offsets. This is only possible when general text loads are allowed,
2335 since the table access itself will be an "lh" instruction. */
2336 /* ??? 16-bit offsets can overflow in large functions. */
2337 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2338
2339 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2340
2341 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2342
2343 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2344
2345 /* Define this as 1 if `char' should by default be signed; else as 0. */
2346 #ifndef DEFAULT_SIGNED_CHAR
2347 #define DEFAULT_SIGNED_CHAR 1
2348 #endif
2349
2350 /* Max number of bytes we can move from memory to memory
2351 in one reasonably fast instruction. */
2352 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2353 #define MAX_MOVE_MAX 8
2354
2355 /* Define this macro as a C expression which is nonzero if
2356 accessing less than a word of memory (i.e. a `char' or a
2357 `short') is no faster than accessing a word of memory, i.e., if
2358 such access require more than one instruction or if there is no
2359 difference in cost between byte and (aligned) word loads.
2360
2361 On RISC machines, it tends to generate better code to define
2362 this as 1, since it avoids making a QI or HI mode register.
2363
2364 But, generating word accesses for -mips16 is generally bad as shifts
2365 (often extended) would be needed for byte accesses. */
2366 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2367
2368 /* Define this to be nonzero if shift instructions ignore all but the low-order
2369 few bits. */
2370 #define SHIFT_COUNT_TRUNCATED 1
2371
2372 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2373 is done just by pretending it is already truncated. */
2374 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2375 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2376
2377
2378 /* Specify the machine mode that pointers have.
2379 After generation of rtl, the compiler makes no further distinction
2380 between pointers and any other objects of this machine mode. */
2381
2382 #ifndef Pmode
2383 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2384 #endif
2385
2386 /* Give call MEMs SImode since it is the "most permissive" mode
2387 for both 32-bit and 64-bit targets. */
2388
2389 #define FUNCTION_MODE SImode
2390
2391 \f
2392 /* A C expression for the cost of moving data from a register in
2393 class FROM to one in class TO. The classes are expressed using
2394 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2395 the default; other values are interpreted relative to that.
2396
2397 It is not required that the cost always equal 2 when FROM is the
2398 same as TO; on some machines it is expensive to move between
2399 registers if they are not general registers.
2400
2401 If reload sees an insn consisting of a single `set' between two
2402 hard registers, and if `REGISTER_MOVE_COST' applied to their
2403 classes returns a value of 2, reload does not check to ensure
2404 that the constraints of the insn are met. Setting a cost of
2405 other than 2 will allow reload to verify that the constraints are
2406 met. You should do this if the `movM' pattern's constraints do
2407 not allow such copying. */
2408
2409 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2410 mips_register_move_cost (MODE, FROM, TO)
2411
2412 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2413 (mips_cost->memory_latency \
2414 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2415
2416 /* Define if copies to/from condition code registers should be avoided.
2417
2418 This is needed for the MIPS because reload_outcc is not complete;
2419 it needs to handle cases where the source is a general or another
2420 condition code register. */
2421 #define AVOID_CCMODE_COPIES
2422
2423 /* A C expression for the cost of a branch instruction. A value of
2424 1 is the default; other values are interpreted relative to that. */
2425
2426 #define BRANCH_COST mips_branch_cost
2427 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2428
2429 /* If defined, modifies the length assigned to instruction INSN as a
2430 function of the context in which it is used. LENGTH is an lvalue
2431 that contains the initially computed length of the insn and should
2432 be updated with the correct length of the insn. */
2433 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2434 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2435
2436 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2437 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2438 its operands. */
2439 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2440 "%*" OPCODE "%?\t" OPERANDS "%/"
2441
2442 /* Return the asm template for a call. INSN is the instruction's mnemonic
2443 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2444 of the target.
2445
2446 When generating GOT code without explicit relocation operators,
2447 all calls should use assembly macros. Otherwise, all indirect
2448 calls should use "jr" or "jalr"; we will arrange to restore $gp
2449 afterwards if necessary. Finally, we can only generate direct
2450 calls for -mabicalls by temporarily switching to non-PIC mode. */
2451 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2452 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2453 ? "%*" INSN "\t%" #OPNO "%/" \
2454 : REG_P (OPERANDS[OPNO]) \
2455 ? "%*" INSN "r\t%" #OPNO "%/" \
2456 : TARGET_ABICALLS \
2457 ? (".option\tpic0\n\t" \
2458 "%*" INSN "\t%" #OPNO "%/\n\t" \
2459 ".option\tpic2") \
2460 : "%*" INSN "\t%" #OPNO "%/")
2461 \f
2462 /* Control the assembler format that we output. */
2463
2464 /* Output to assembler file text saying following lines
2465 may contain character constants, extra white space, comments, etc. */
2466
2467 #ifndef ASM_APP_ON
2468 #define ASM_APP_ON " #APP\n"
2469 #endif
2470
2471 /* Output to assembler file text saying following lines
2472 no longer contain unusual constructs. */
2473
2474 #ifndef ASM_APP_OFF
2475 #define ASM_APP_OFF " #NO_APP\n"
2476 #endif
2477
2478 #define REGISTER_NAMES \
2479 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2480 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2481 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2482 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2483 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2484 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2485 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2486 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2487 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2488 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2489 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2490 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2491 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2492 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2493 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2494 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2495 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2496 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2497 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2498 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2499 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2500 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2501 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2502 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2503
2504 /* List the "software" names for each register. Also list the numerical
2505 names for $fp and $sp. */
2506
2507 #define ADDITIONAL_REGISTER_NAMES \
2508 { \
2509 { "$29", 29 + GP_REG_FIRST }, \
2510 { "$30", 30 + GP_REG_FIRST }, \
2511 { "at", 1 + GP_REG_FIRST }, \
2512 { "v0", 2 + GP_REG_FIRST }, \
2513 { "v1", 3 + GP_REG_FIRST }, \
2514 { "a0", 4 + GP_REG_FIRST }, \
2515 { "a1", 5 + GP_REG_FIRST }, \
2516 { "a2", 6 + GP_REG_FIRST }, \
2517 { "a3", 7 + GP_REG_FIRST }, \
2518 { "t0", 8 + GP_REG_FIRST }, \
2519 { "t1", 9 + GP_REG_FIRST }, \
2520 { "t2", 10 + GP_REG_FIRST }, \
2521 { "t3", 11 + GP_REG_FIRST }, \
2522 { "t4", 12 + GP_REG_FIRST }, \
2523 { "t5", 13 + GP_REG_FIRST }, \
2524 { "t6", 14 + GP_REG_FIRST }, \
2525 { "t7", 15 + GP_REG_FIRST }, \
2526 { "s0", 16 + GP_REG_FIRST }, \
2527 { "s1", 17 + GP_REG_FIRST }, \
2528 { "s2", 18 + GP_REG_FIRST }, \
2529 { "s3", 19 + GP_REG_FIRST }, \
2530 { "s4", 20 + GP_REG_FIRST }, \
2531 { "s5", 21 + GP_REG_FIRST }, \
2532 { "s6", 22 + GP_REG_FIRST }, \
2533 { "s7", 23 + GP_REG_FIRST }, \
2534 { "t8", 24 + GP_REG_FIRST }, \
2535 { "t9", 25 + GP_REG_FIRST }, \
2536 { "k0", 26 + GP_REG_FIRST }, \
2537 { "k1", 27 + GP_REG_FIRST }, \
2538 { "gp", 28 + GP_REG_FIRST }, \
2539 { "sp", 29 + GP_REG_FIRST }, \
2540 { "fp", 30 + GP_REG_FIRST }, \
2541 { "ra", 31 + GP_REG_FIRST }, \
2542 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2543 }
2544
2545 /* This is meant to be redefined in the host dependent files. It is a
2546 set of alternative names and regnums for mips coprocessors. */
2547
2548 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2549
2550 /* A C compound statement to output to stdio stream STREAM the
2551 assembler syntax for an instruction operand X. X is an RTL
2552 expression.
2553
2554 CODE is a value that can be used to specify one of several ways
2555 of printing the operand. It is used when identical operands
2556 must be printed differently depending on the context. CODE
2557 comes from the `%' specification that was used to request
2558 printing of the operand. If the specification was just `%DIGIT'
2559 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2560 is the ASCII code for LTR.
2561
2562 If X is a register, this macro should print the register's name.
2563 The names can be found in an array `reg_names' whose type is
2564 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2565
2566 When the machine description has a specification `%PUNCT' (a `%'
2567 followed by a punctuation character), this macro is called with
2568 a null pointer for X and the punctuation character for CODE.
2569
2570 See mips.c for the MIPS specific codes. */
2571
2572 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2573
2574 /* A C expression which evaluates to true if CODE is a valid
2575 punctuation character for use in the `PRINT_OPERAND' macro. If
2576 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2577 punctuation characters (except for the standard one, `%') are
2578 used in this way. */
2579
2580 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2581
2582 /* A C compound statement to output to stdio stream STREAM the
2583 assembler syntax for an instruction operand that is a memory
2584 reference whose address is ADDR. ADDR is an RTL expression. */
2585
2586 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2587
2588
2589 /* A C statement, to be executed after all slot-filler instructions
2590 have been output. If necessary, call `dbr_sequence_length' to
2591 determine the number of slots filled in a sequence (zero if not
2592 currently outputting a sequence), to decide how many no-ops to
2593 output, or whatever.
2594
2595 Don't define this macro if it has nothing to do, but it is
2596 helpful in reading assembly output if the extent of the delay
2597 sequence is made explicit (e.g. with white space).
2598
2599 Note that output routines for instructions with delay slots must
2600 be prepared to deal with not being output as part of a sequence
2601 (i.e. when the scheduling pass is not run, or when no slot
2602 fillers could be found.) The variable `final_sequence' is null
2603 when not processing a sequence, otherwise it contains the
2604 `sequence' rtx being output. */
2605
2606 #define DBR_OUTPUT_SEQEND(STREAM) \
2607 do \
2608 { \
2609 if (set_nomacro > 0 && --set_nomacro == 0) \
2610 fputs ("\t.set\tmacro\n", STREAM); \
2611 \
2612 if (set_noreorder > 0 && --set_noreorder == 0) \
2613 fputs ("\t.set\treorder\n", STREAM); \
2614 \
2615 fputs ("\n", STREAM); \
2616 } \
2617 while (0)
2618
2619
2620 /* How to tell the debugger about changes of source files. */
2621 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2622 mips_output_filename (STREAM, NAME)
2623
2624 /* mips-tfile does not understand .stabd directives. */
2625 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2626 dbxout_begin_stabn_sline (LINE); \
2627 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2628 } while (0)
2629
2630 /* Use .loc directives for SDB line numbers. */
2631 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2632 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2633
2634 /* The MIPS implementation uses some labels for its own purpose. The
2635 following lists what labels are created, and are all formed by the
2636 pattern $L[a-z].*. The machine independent portion of GCC creates
2637 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2638
2639 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2640 $Lb[0-9]+ Begin blocks for MIPS debug support
2641 $Lc[0-9]+ Label for use in s<xx> operation.
2642 $Le[0-9]+ End blocks for MIPS debug support */
2643
2644 #undef ASM_DECLARE_OBJECT_NAME
2645 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2646 mips_declare_object (STREAM, NAME, "", ":\n")
2647
2648 /* Globalizing directive for a label. */
2649 #define GLOBAL_ASM_OP "\t.globl\t"
2650
2651 /* This says how to define a global common symbol. */
2652
2653 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2654
2655 /* This says how to define a local common symbol (i.e., not visible to
2656 linker). */
2657
2658 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2659 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2660 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2661 #endif
2662
2663 /* This says how to output an external. It would be possible not to
2664 output anything and let undefined symbol become external. However
2665 the assembler uses length information on externals to allocate in
2666 data/sdata bss/sbss, thereby saving exec time. */
2667
2668 #undef ASM_OUTPUT_EXTERNAL
2669 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2670 mips_output_external(STREAM,DECL,NAME)
2671
2672 /* This is how to declare a function name. The actual work of
2673 emitting the label is moved to function_prologue, so that we can
2674 get the line number correctly emitted before the .ent directive,
2675 and after any .file directives. Define as empty so that the function
2676 is not declared before the .ent directive elsewhere. */
2677
2678 #undef ASM_DECLARE_FUNCTION_NAME
2679 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2680
2681 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2682 #define FUNCTION_NAME_ALREADY_DECLARED 0
2683 #endif
2684
2685 /* This is how to store into the string LABEL
2686 the symbol_ref name of an internal numbered label where
2687 PREFIX is the class of label and NUM is the number within the class.
2688 This is suitable for output with `assemble_name'. */
2689
2690 #undef ASM_GENERATE_INTERNAL_LABEL
2691 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2692 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2693
2694 /* This is how to output an element of a case-vector that is absolute. */
2695
2696 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2697 fprintf (STREAM, "\t%s\t%sL%d\n", \
2698 ptr_mode == DImode ? ".dword" : ".word", \
2699 LOCAL_LABEL_PREFIX, \
2700 VALUE)
2701
2702 /* This is how to output an element of a case-vector. We can make the
2703 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2704 is supported. */
2705
2706 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2707 do { \
2708 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2709 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2710 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2711 else if (TARGET_GPWORD) \
2712 fprintf (STREAM, "\t%s\t%sL%d\n", \
2713 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2714 LOCAL_LABEL_PREFIX, VALUE); \
2715 else if (TARGET_RTP_PIC) \
2716 { \
2717 /* Make the entry relative to the start of the function. */ \
2718 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2719 fprintf (STREAM, "\t%s\t%sL%d-", \
2720 Pmode == DImode ? ".dword" : ".word", \
2721 LOCAL_LABEL_PREFIX, VALUE); \
2722 assemble_name (STREAM, XSTR (fnsym, 0)); \
2723 fprintf (STREAM, "\n"); \
2724 } \
2725 else \
2726 fprintf (STREAM, "\t%s\t%sL%d\n", \
2727 ptr_mode == DImode ? ".dword" : ".word", \
2728 LOCAL_LABEL_PREFIX, VALUE); \
2729 } while (0)
2730
2731 /* This is how to output an assembler line
2732 that says to advance the location counter
2733 to a multiple of 2**LOG bytes. */
2734
2735 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2736 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2737
2738 /* This is how to output an assembler line to advance the location
2739 counter by SIZE bytes. */
2740
2741 #undef ASM_OUTPUT_SKIP
2742 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2743 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2744
2745 /* This is how to output a string. */
2746 #undef ASM_OUTPUT_ASCII
2747 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2748 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2749
2750 /* Output #ident as a in the read-only data section. */
2751 #undef ASM_OUTPUT_IDENT
2752 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2753 { \
2754 const char *p = STRING; \
2755 int size = strlen (p) + 1; \
2756 switch_to_section (readonly_data_section); \
2757 assemble_string (p, size); \
2758 }
2759 \f
2760 /* Default to -G 8 */
2761 #ifndef MIPS_DEFAULT_GVALUE
2762 #define MIPS_DEFAULT_GVALUE 8
2763 #endif
2764
2765 /* Define the strings to put out for each section in the object file. */
2766 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2767 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2768
2769 #undef READONLY_DATA_SECTION_ASM_OP
2770 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2771 \f
2772 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2773 do \
2774 { \
2775 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2776 TARGET_64BIT ? "dsubu" : "subu", \
2777 reg_names[STACK_POINTER_REGNUM], \
2778 reg_names[STACK_POINTER_REGNUM], \
2779 TARGET_64BIT ? "sd" : "sw", \
2780 reg_names[REGNO], \
2781 reg_names[STACK_POINTER_REGNUM]); \
2782 } \
2783 while (0)
2784
2785 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2786 do \
2787 { \
2788 if (! set_noreorder) \
2789 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2790 \
2791 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2792 TARGET_64BIT ? "ld" : "lw", \
2793 reg_names[REGNO], \
2794 reg_names[STACK_POINTER_REGNUM], \
2795 TARGET_64BIT ? "daddu" : "addu", \
2796 reg_names[STACK_POINTER_REGNUM], \
2797 reg_names[STACK_POINTER_REGNUM]); \
2798 \
2799 if (! set_noreorder) \
2800 fprintf (STREAM, "\t.set\treorder\n"); \
2801 } \
2802 while (0)
2803
2804 /* How to start an assembler comment.
2805 The leading space is important (the mips native assembler requires it). */
2806 #ifndef ASM_COMMENT_START
2807 #define ASM_COMMENT_START " #"
2808 #endif
2809 \f
2810 /* Default definitions for size_t and ptrdiff_t. We must override the
2811 definitions from ../svr4.h on mips-*-linux-gnu. */
2812
2813 #undef SIZE_TYPE
2814 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2815
2816 #undef PTRDIFF_TYPE
2817 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2818
2819 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2820 values were determined experimentally by benchmarking with CSiBE.
2821 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2822 for o32 where we have to restore $gp afterwards as well as make an
2823 indirect call), but in practice, bumping this up higher for
2824 TARGET_ABICALLS doesn't make much difference to code size. */
2825
2826 #define MIPS_CALL_RATIO 8
2827
2828 /* Define MOVE_RATIO to encourage use of movmemsi when enabled,
2829 since it should always generate code at least as good as
2830 move_by_pieces(). But when inline movmemsi pattern is disabled
2831 (i.e., with -mips16 or -mmemcpy), instead use a value approximating
2832 the length of a memcpy call sequence, so that move_by_pieces will
2833 generate inline code if it is shorter than a function call.
2834 Since move_by_pieces_ninsns() counts memory-to-memory moves, but
2835 we'll have to generate a load/store pair for each, halve the value of
2836 MIPS_CALL_RATIO to take that into account.
2837 The default value for MOVE_RATIO when HAVE_movmemsi is true is 2.
2838 There is no point to setting it to less than this to try to disable
2839 move_by_pieces entirely, because that also disables some desirable
2840 tree-level optimizations, specifically related to optimizing a
2841 one-byte string copy into a simple move byte operation. */
2842
2843 #define MOVE_RATIO \
2844 ((TARGET_MIPS16 || TARGET_MEMCPY) ? MIPS_CALL_RATIO / 2 : 2)
2845
2846 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2847 of the length of a memset call, but use the default otherwise. */
2848
2849 #define CLEAR_RATIO \
2850 (optimize_size ? MIPS_CALL_RATIO : 15)
2851
2852 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2853 optimizing for size adjust the ratio to account for the overhead of
2854 loading the constant and replicating it across the word. */
2855
2856 #define SET_RATIO \
2857 (optimize_size ? MIPS_CALL_RATIO - 2 : 15)
2858
2859 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2860 in that case each word takes 3 insns (lui, ori, sw), or more in
2861 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2862 and let the move_by_pieces code copy the string from read-only
2863 memory. In the future, this could be tuned further for multi-issue
2864 CPUs that can issue stores down one pipe and arithmetic instructions
2865 down another; in that case, the lui/ori/sw combination would be a
2866 win for long enough strings. */
2867
2868 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2869 \f
2870 #ifndef __mips16
2871 /* Since the bits of the _init and _fini function is spread across
2872 many object files, each potentially with its own GP, we must assume
2873 we need to load our GP. We don't preserve $gp or $ra, since each
2874 init/fini chunk is supposed to initialize $gp, and crti/crtn
2875 already take care of preserving $ra and, when appropriate, $gp. */
2876 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2877 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2878 asm (SECTION_OP "\n\
2879 .set noreorder\n\
2880 bal 1f\n\
2881 nop\n\
2882 1: .cpload $31\n\
2883 .set reorder\n\
2884 jal " USER_LABEL_PREFIX #FUNC "\n\
2885 " TEXT_SECTION_ASM_OP);
2886 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2887 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2888 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2889 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2890 asm (SECTION_OP "\n\
2891 .set noreorder\n\
2892 bal 1f\n\
2893 nop\n\
2894 1: .set reorder\n\
2895 .cpsetup $31, $2, 1b\n\
2896 jal " USER_LABEL_PREFIX #FUNC "\n\
2897 " TEXT_SECTION_ASM_OP);
2898 #endif
2899 #endif
2900
2901 #ifndef HAVE_AS_TLS
2902 #define HAVE_AS_TLS 0
2903 #endif
2904
2905 /* Return an asm string that atomically:
2906
2907 - Compares memory reference %1 to register %2 and, if they are
2908 equal, changes %1 to %3.
2909
2910 - Sets register %0 to the old value of memory reference %1.
2911
2912 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
2913 and OP is the instruction that should be used to load %3 into a
2914 register. */
2915 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
2916 "%(%<%[sync\n" \
2917 "1:\tll" SUFFIX "\t%0,%1\n" \
2918 "\tbne\t%0,%2,2f\n" \
2919 "\t" OP "\t%@,%3\n" \
2920 "\tsc" SUFFIX "\t%@,%1\n" \
2921 "\tbeq\t%@,%.,1b\n" \
2922 "\tnop\n" \
2923 "2:%]%>%)"
2924
2925 /* Return an asm string that atomically:
2926
2927 - Sets memory reference %0 to %0 INSN %1.
2928
2929 SUFFIX is the suffix that should be added to "ll" and "sc"
2930 instructions. */
2931 #define MIPS_SYNC_OP(SUFFIX, INSN) \
2932 "%(%<%[sync\n" \
2933 "1:\tll" SUFFIX "\t%@,%0\n" \
2934 "\t" INSN "\t%@,%@,%1\n" \
2935 "\tsc" SUFFIX "\t%@,%0\n" \
2936 "\tbeq\t%@,%.,1b\n" \
2937 "\tnop%]%>%)"
2938
2939 /* Return an asm string that atomically:
2940
2941 - Sets memory reference %1 to %1 INSN %2.
2942
2943 - Sets register %0 to the old value of memory reference %1.
2944
2945 SUFFIX is the suffix that should be added to "ll" and "sc"
2946 instructions. */
2947 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
2948 "%(%<%[sync\n" \
2949 "1:\tll" SUFFIX "\t%0,%1\n" \
2950 "\t" INSN "\t%@,%0,%2\n" \
2951 "\tsc" SUFFIX "\t%@,%1\n" \
2952 "\tbeq\t%@,%.,1b\n" \
2953 "\tnop%]%>%)"
2954
2955 /* Return an asm string that atomically:
2956
2957 - Sets memory reference %1 to %1 INSN %2.
2958
2959 - Sets register %0 to the new value of memory reference %1.
2960
2961 SUFFIX is the suffix that should be added to "ll" and "sc"
2962 instructions. */
2963 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
2964 "%(%<%[sync\n" \
2965 "1:\tll" SUFFIX "\t%0,%1\n" \
2966 "\t" INSN "\t%@,%0,%2\n" \
2967 "\tsc" SUFFIX "\t%@,%1\n" \
2968 "\tbeq\t%@,%.,1b\n" \
2969 "\t" INSN "\t%0,%0,%2%]%>%)"
2970
2971 /* Return an asm string that atomically:
2972
2973 - Sets memory reference %0 to ~%0 AND %1.
2974
2975 SUFFIX is the suffix that should be added to "ll" and "sc"
2976 instructions. INSN is the and instruction needed to and a register
2977 with %2. */
2978 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
2979 "%(%<%[sync\n" \
2980 "1:\tll" SUFFIX "\t%@,%0\n" \
2981 "\tnor\t%@,%@,%.\n" \
2982 "\t" INSN "\t%@,%@,%1\n" \
2983 "\tsc" SUFFIX "\t%@,%0\n" \
2984 "\tbeq\t%@,%.,1b\n" \
2985 "\tnop%]%>%)"
2986
2987 /* Return an asm string that atomically:
2988
2989 - Sets memory reference %1 to ~%1 AND %2.
2990
2991 - Sets register %0 to the old value of memory reference %1.
2992
2993 SUFFIX is the suffix that should be added to "ll" and "sc"
2994 instructions. INSN is the and instruction needed to and a register
2995 with %2. */
2996 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
2997 "%(%<%[sync\n" \
2998 "1:\tll" SUFFIX "\t%0,%1\n" \
2999 "\tnor\t%@,%0,%.\n" \
3000 "\t" INSN "\t%@,%@,%2\n" \
3001 "\tsc" SUFFIX "\t%@,%1\n" \
3002 "\tbeq\t%@,%.,1b\n" \
3003 "\tnop%]%>%)"
3004
3005 /* Return an asm string that atomically:
3006
3007 - Sets memory reference %1 to ~%1 AND %2.
3008
3009 - Sets register %0 to the new value of memory reference %1.
3010
3011 SUFFIX is the suffix that should be added to "ll" and "sc"
3012 instructions. INSN is the and instruction needed to and a register
3013 with %2. */
3014 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
3015 "%(%<%[sync\n" \
3016 "1:\tll" SUFFIX "\t%0,%1\n" \
3017 "\tnor\t%0,%0,%.\n" \
3018 "\t" INSN "\t%@,%0,%2\n" \
3019 "\tsc" SUFFIX "\t%@,%1\n" \
3020 "\tbeq\t%@,%.,1b\n" \
3021 "\t" INSN "\t%0,%0,%2%]%>%)"
3022
3023 /* Return an asm string that atomically:
3024
3025 - Sets memory reference %1 to %2.
3026
3027 - Sets register %0 to the old value of memory reference %1.
3028
3029 SUFFIX is the suffix that should be added to "ll" and "sc"
3030 instructions. OP is the and instruction that should be used to
3031 load %2 into a register. */
3032 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3033 "%(%<%[\n" \
3034 "1:\tll" SUFFIX "\t%0,%1\n" \
3035 "\t" OP "\t%@,%2\n" \
3036 "\tsc" SUFFIX "\t%@,%1\n" \
3037 "\tbeq\t%@,%.,1b\n" \
3038 "\tnop\n" \
3039 "\tsync%]%>%)"
3040