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mips-protos.h (mips_cfun_has_cprestore_slot_p): Declare.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF2_1,
45 PROCESSOR_24KF1_1,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF2_1,
48 PROCESSOR_74KF1_1,
49 PROCESSOR_74KF3_2,
50 PROCESSOR_LOONGSON_2E,
51 PROCESSOR_LOONGSON_2F,
52 PROCESSOR_M4K,
53 PROCESSOR_OCTEON,
54 PROCESSOR_R3900,
55 PROCESSOR_R6000,
56 PROCESSOR_R4000,
57 PROCESSOR_R4100,
58 PROCESSOR_R4111,
59 PROCESSOR_R4120,
60 PROCESSOR_R4130,
61 PROCESSOR_R4300,
62 PROCESSOR_R4600,
63 PROCESSOR_R4650,
64 PROCESSOR_R5000,
65 PROCESSOR_R5400,
66 PROCESSOR_R5500,
67 PROCESSOR_R7000,
68 PROCESSOR_R8000,
69 PROCESSOR_R9000,
70 PROCESSOR_R10000,
71 PROCESSOR_SB1,
72 PROCESSOR_SB1A,
73 PROCESSOR_SR71000,
74 PROCESSOR_XLR,
75 PROCESSOR_MAX
76 };
77
78 /* Costs of various operations on the different architectures. */
79
80 struct mips_rtx_cost_data
81 {
82 unsigned short fp_add;
83 unsigned short fp_mult_sf;
84 unsigned short fp_mult_df;
85 unsigned short fp_div_sf;
86 unsigned short fp_div_df;
87 unsigned short int_mult_si;
88 unsigned short int_mult_di;
89 unsigned short int_div_si;
90 unsigned short int_div_di;
91 unsigned short branch_cost;
92 unsigned short memory_latency;
93 };
94
95 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
96 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
97 to work on a 64-bit machine. */
98
99 #define ABI_32 0
100 #define ABI_N32 1
101 #define ABI_64 2
102 #define ABI_EABI 3
103 #define ABI_O64 4
104
105 /* Masks that affect tuning.
106
107 PTF_AVOID_BRANCHLIKELY
108 Set if it is usually not profitable to use branch-likely instructions
109 for this target, typically because the branches are always predicted
110 taken and so incur a large overhead when not taken. */
111 #define PTF_AVOID_BRANCHLIKELY 0x1
112
113 /* Information about one recognized processor. Defined here for the
114 benefit of TARGET_CPU_CPP_BUILTINS. */
115 struct mips_cpu_info {
116 /* The 'canonical' name of the processor as far as GCC is concerned.
117 It's typically a manufacturer's prefix followed by a numerical
118 designation. It should be lowercase. */
119 const char *name;
120
121 /* The internal processor number that most closely matches this
122 entry. Several processors can have the same value, if there's no
123 difference between them from GCC's point of view. */
124 enum processor_type cpu;
125
126 /* The ISA level that the processor implements. */
127 int isa;
128
129 /* A mask of PTF_* values. */
130 unsigned int tune_flags;
131 };
132
133 /* Enumerates the setting of the -mcode-readable option. */
134 enum mips_code_readable_setting {
135 CODE_READABLE_NO,
136 CODE_READABLE_PCREL,
137 CODE_READABLE_YES
138 };
139
140 /* Macros to silence warnings about numbers being signed in traditional
141 C and unsigned in ISO C when compiled on 32-bit hosts. */
142
143 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
144 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
145 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
146
147 \f
148 /* Run-time compilation parameters selecting different hardware subsets. */
149
150 /* True if we are generating position-independent VxWorks RTP code. */
151 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
152
153 /* True if the output file is marked as ".abicalls; .option pic0"
154 (-call_nonpic). */
155 #define TARGET_ABICALLS_PIC0 \
156 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
157
158 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
159 #define TARGET_ABICALLS_PIC2 \
160 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
161
162 /* True if the call patterns should be split into a jalr followed by
163 an instruction to restore $gp. It is only safe to split the load
164 from the call when every use of $gp is explicit.
165
166 See mips_must_initialize_gp_p for details about how we manage the
167 global pointer. */
168
169 #define TARGET_SPLIT_CALLS \
170 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
171
172 /* True if we're generating a form of -mabicalls in which we can use
173 operators like %hi and %lo to refer to locally-binding symbols.
174 We can only do this for -mno-shared, and only then if we can use
175 relocation operations instead of assembly macros. It isn't really
176 worth using absolute sequences for 64-bit symbols because GOT
177 accesses are so much shorter. */
178
179 #define TARGET_ABSOLUTE_ABICALLS \
180 (TARGET_ABICALLS \
181 && !TARGET_SHARED \
182 && TARGET_EXPLICIT_RELOCS \
183 && !ABI_HAS_64BIT_SYMBOLS)
184
185 /* True if we can optimize sibling calls. For simplicity, we only
186 handle cases in which call_insn_operand will reject invalid
187 sibcall addresses. There are two cases in which this isn't true:
188
189 - TARGET_MIPS16. call_insn_operand accepts constant addresses
190 but there is no direct jump instruction. It isn't worth
191 using sibling calls in this case anyway; they would usually
192 be longer than normal calls.
193
194 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
195 accepts global constants, but all sibcalls must be indirect. */
196 #define TARGET_SIBCALLS \
197 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
198
199 /* True if we need to use a global offset table to access some symbols. */
200 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
201
202 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
203 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
204
205 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
206 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
207
208 /* True if we should use .cprestore to store to the cprestore slot.
209
210 We continue to use .cprestore for explicit-reloc code so that JALs
211 inside inline asms will work correctly. */
212 #define TARGET_CPRESTORE_DIRECTIVE \
213 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
214
215 /* True if we can use the J and JAL instructions. */
216 #define TARGET_ABSOLUTE_JUMPS \
217 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
218
219 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
220 This is true for both the PIC and non-PIC VxWorks RTP modes. */
221 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
222
223 /* True if .gpword or .gpdword should be used for switch tables.
224
225 Although GAS does understand .gpdword, the SGI linker mishandles
226 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
227 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
228 #define TARGET_GPWORD \
229 (TARGET_ABICALLS \
230 && !TARGET_ABSOLUTE_ABICALLS \
231 && !(mips_abi == ABI_64 && TARGET_IRIX))
232
233 /* Generate mips16 code */
234 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
235 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
236 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
237 /* Generate mips16e register save/restore sequences. */
238 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
239
240 /* True if we're generating a form of MIPS16 code in which general
241 text loads are allowed. */
242 #define TARGET_MIPS16_TEXT_LOADS \
243 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
244
245 /* True if we're generating a form of MIPS16 code in which PC-relative
246 loads are allowed. */
247 #define TARGET_MIPS16_PCREL_LOADS \
248 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
249
250 /* Generic ISA defines. */
251 #define ISA_MIPS1 (mips_isa == 1)
252 #define ISA_MIPS2 (mips_isa == 2)
253 #define ISA_MIPS3 (mips_isa == 3)
254 #define ISA_MIPS4 (mips_isa == 4)
255 #define ISA_MIPS32 (mips_isa == 32)
256 #define ISA_MIPS32R2 (mips_isa == 33)
257 #define ISA_MIPS64 (mips_isa == 64)
258 #define ISA_MIPS64R2 (mips_isa == 65)
259
260 /* Architecture target defines. */
261 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
262 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
263 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
264 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
265 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
266 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
267 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
268 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
269 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
270 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
271 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
272 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
273 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
274 || mips_arch == PROCESSOR_SB1A)
275 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
276
277 /* Scheduling target defines. */
278 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
279 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
280 || mips_tune == PROCESSOR_24KF2_1 \
281 || mips_tune == PROCESSOR_24KF1_1)
282 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
283 || mips_tune == PROCESSOR_74KF2_1 \
284 || mips_tune == PROCESSOR_74KF1_1 \
285 || mips_tune == PROCESSOR_74KF3_2)
286 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
287 || mips_tune == PROCESSOR_LOONGSON_2F)
288 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
289 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
290 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
291 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
292 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
293 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
294 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
295 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
296 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
297 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
298 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
299 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
300 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
301 || mips_tune == PROCESSOR_SB1A)
302
303 /* Whether vector modes and intrinsics for ST Microelectronics
304 Loongson-2E/2F processors should be enabled. In o32 pairs of
305 floating-point registers provide 64-bit values. */
306 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
307 && TARGET_LOONGSON_2EF)
308
309 /* True if the pre-reload scheduler should try to create chains of
310 multiply-add or multiply-subtract instructions. For example,
311 suppose we have:
312
313 t1 = a * b
314 t2 = t1 + c * d
315 t3 = e * f
316 t4 = t3 - g * h
317
318 t1 will have a higher priority than t2 and t3 will have a higher
319 priority than t4. However, before reload, there is no dependence
320 between t1 and t3, and they can often have similar priorities.
321 The scheduler will then tend to prefer:
322
323 t1 = a * b
324 t3 = e * f
325 t2 = t1 + c * d
326 t4 = t3 - g * h
327
328 which stops us from making full use of macc/madd-style instructions.
329 This sort of situation occurs frequently in Fourier transforms and
330 in unrolled loops.
331
332 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
333 queue so that chained multiply-add and multiply-subtract instructions
334 appear ahead of any other instruction that is likely to clobber lo.
335 In the example above, if t2 and t3 become ready at the same time,
336 the code ensures that t2 is scheduled first.
337
338 Multiply-accumulate instructions are a bigger win for some targets
339 than others, so this macro is defined on an opt-in basis. */
340 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
341 || TUNE_MIPS4120 \
342 || TUNE_MIPS4130 \
343 || TUNE_24K)
344
345 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
346 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
347
348 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
349 directly accessible, while the command-line options select
350 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
351 in use. */
352 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
353 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
354
355 /* False if SC acts as a memory barrier with respect to itself,
356 otherwise a SYNC will be emitted after SC for atomic operations
357 that require ordering between the SC and following loads and
358 stores. It does not tell anything about ordering of loads and
359 stores prior to and following the SC, only about the SC itself and
360 those loads and stores follow it. */
361 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
362
363 /* IRIX specific stuff. */
364 #define TARGET_IRIX 0
365 #define TARGET_IRIX6 0
366
367 /* Define preprocessor macros for the -march and -mtune options.
368 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
369 processor. If INFO's canonical name is "foo", define PREFIX to
370 be "foo", and define an additional macro PREFIX_FOO. */
371 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
372 do \
373 { \
374 char *macro, *p; \
375 \
376 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
377 for (p = macro; *p != 0; p++) \
378 *p = TOUPPER (*p); \
379 \
380 builtin_define (macro); \
381 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
382 free (macro); \
383 } \
384 while (0)
385
386 /* Target CPU builtins. */
387 #define TARGET_CPU_CPP_BUILTINS() \
388 do \
389 { \
390 /* Everyone but IRIX defines this to mips. */ \
391 if (!TARGET_IRIX) \
392 builtin_assert ("machine=mips"); \
393 \
394 builtin_assert ("cpu=mips"); \
395 builtin_define ("__mips__"); \
396 builtin_define ("_mips"); \
397 \
398 /* We do this here because __mips is defined below and so we \
399 can't use builtin_define_std. We don't ever want to define \
400 "mips" for VxWorks because some of the VxWorks headers \
401 construct include filenames from a root directory macro, \
402 an architecture macro and a filename, where the architecture \
403 macro expands to 'mips'. If we define 'mips' to 1, the \
404 architecture macro expands to 1 as well. */ \
405 if (!flag_iso && !TARGET_VXWORKS) \
406 builtin_define ("mips"); \
407 \
408 if (TARGET_64BIT) \
409 builtin_define ("__mips64"); \
410 \
411 if (!TARGET_IRIX) \
412 { \
413 /* Treat _R3000 and _R4000 like register-size \
414 defines, which is how they've historically \
415 been used. */ \
416 if (TARGET_64BIT) \
417 { \
418 builtin_define_std ("R4000"); \
419 builtin_define ("_R4000"); \
420 } \
421 else \
422 { \
423 builtin_define_std ("R3000"); \
424 builtin_define ("_R3000"); \
425 } \
426 } \
427 if (TARGET_FLOAT64) \
428 builtin_define ("__mips_fpr=64"); \
429 else \
430 builtin_define ("__mips_fpr=32"); \
431 \
432 if (mips_base_mips16) \
433 builtin_define ("__mips16"); \
434 \
435 if (TARGET_MIPS3D) \
436 builtin_define ("__mips3d"); \
437 \
438 if (TARGET_SMARTMIPS) \
439 builtin_define ("__mips_smartmips"); \
440 \
441 if (TARGET_DSP) \
442 { \
443 builtin_define ("__mips_dsp"); \
444 if (TARGET_DSPR2) \
445 { \
446 builtin_define ("__mips_dspr2"); \
447 builtin_define ("__mips_dsp_rev=2"); \
448 } \
449 else \
450 builtin_define ("__mips_dsp_rev=1"); \
451 } \
452 \
453 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
454 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
455 \
456 if (ISA_MIPS1) \
457 { \
458 builtin_define ("__mips=1"); \
459 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
460 } \
461 else if (ISA_MIPS2) \
462 { \
463 builtin_define ("__mips=2"); \
464 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
465 } \
466 else if (ISA_MIPS3) \
467 { \
468 builtin_define ("__mips=3"); \
469 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
470 } \
471 else if (ISA_MIPS4) \
472 { \
473 builtin_define ("__mips=4"); \
474 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
475 } \
476 else if (ISA_MIPS32) \
477 { \
478 builtin_define ("__mips=32"); \
479 builtin_define ("__mips_isa_rev=1"); \
480 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
481 } \
482 else if (ISA_MIPS32R2) \
483 { \
484 builtin_define ("__mips=32"); \
485 builtin_define ("__mips_isa_rev=2"); \
486 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
487 } \
488 else if (ISA_MIPS64) \
489 { \
490 builtin_define ("__mips=64"); \
491 builtin_define ("__mips_isa_rev=1"); \
492 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
493 } \
494 else if (ISA_MIPS64R2) \
495 { \
496 builtin_define ("__mips=64"); \
497 builtin_define ("__mips_isa_rev=2"); \
498 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
499 } \
500 \
501 switch (mips_abi) \
502 { \
503 case ABI_32: \
504 builtin_define ("_ABIO32=1"); \
505 builtin_define ("_MIPS_SIM=_ABIO32"); \
506 break; \
507 \
508 case ABI_N32: \
509 builtin_define ("_ABIN32=2"); \
510 builtin_define ("_MIPS_SIM=_ABIN32"); \
511 break; \
512 \
513 case ABI_64: \
514 builtin_define ("_ABI64=3"); \
515 builtin_define ("_MIPS_SIM=_ABI64"); \
516 break; \
517 \
518 case ABI_O64: \
519 builtin_define ("_ABIO64=4"); \
520 builtin_define ("_MIPS_SIM=_ABIO64"); \
521 break; \
522 } \
523 \
524 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
525 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
526 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
527 builtin_define_with_int_value ("_MIPS_FPSET", \
528 32 / MAX_FPRS_PER_FMT); \
529 \
530 /* These defines reflect the ABI in use, not whether the \
531 FPU is directly accessible. */ \
532 if (TARGET_HARD_FLOAT_ABI) \
533 builtin_define ("__mips_hard_float"); \
534 else \
535 builtin_define ("__mips_soft_float"); \
536 \
537 if (TARGET_SINGLE_FLOAT) \
538 builtin_define ("__mips_single_float"); \
539 \
540 if (TARGET_PAIRED_SINGLE_FLOAT) \
541 builtin_define ("__mips_paired_single_float"); \
542 \
543 if (TARGET_BIG_ENDIAN) \
544 { \
545 builtin_define_std ("MIPSEB"); \
546 builtin_define ("_MIPSEB"); \
547 } \
548 else \
549 { \
550 builtin_define_std ("MIPSEL"); \
551 builtin_define ("_MIPSEL"); \
552 } \
553 \
554 /* Whether calls should go through $25. The separate __PIC__ \
555 macro indicates whether abicalls code might use a GOT. */ \
556 if (TARGET_ABICALLS) \
557 builtin_define ("__mips_abicalls"); \
558 \
559 /* Whether Loongson vector modes are enabled. */ \
560 if (TARGET_LOONGSON_VECTORS) \
561 builtin_define ("__mips_loongson_vector_rev"); \
562 \
563 /* Historical Octeon macro. */ \
564 if (TARGET_OCTEON) \
565 builtin_define ("__OCTEON__"); \
566 \
567 /* Macros dependent on the C dialect. */ \
568 if (preprocessing_asm_p ()) \
569 { \
570 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
571 builtin_define ("_LANGUAGE_ASSEMBLY"); \
572 } \
573 else if (c_dialect_cxx ()) \
574 { \
575 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
576 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
577 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
578 } \
579 else \
580 { \
581 builtin_define_std ("LANGUAGE_C"); \
582 builtin_define ("_LANGUAGE_C"); \
583 } \
584 if (c_dialect_objc ()) \
585 { \
586 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
587 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
588 /* Bizarre, but needed at least for Irix. */ \
589 builtin_define_std ("LANGUAGE_C"); \
590 builtin_define ("_LANGUAGE_C"); \
591 } \
592 \
593 if (mips_abi == ABI_EABI) \
594 builtin_define ("__mips_eabi"); \
595 \
596 if (TARGET_CACHE_BUILTIN) \
597 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
598 } \
599 while (0)
600
601 /* Default target_flags if no switches are specified */
602
603 #ifndef TARGET_DEFAULT
604 #define TARGET_DEFAULT 0
605 #endif
606
607 #ifndef TARGET_CPU_DEFAULT
608 #define TARGET_CPU_DEFAULT 0
609 #endif
610
611 #ifndef TARGET_ENDIAN_DEFAULT
612 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
613 #endif
614
615 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
616 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
617 #endif
618
619 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
620 #ifndef MIPS_ISA_DEFAULT
621 #ifndef MIPS_CPU_STRING_DEFAULT
622 #define MIPS_CPU_STRING_DEFAULT "from-abi"
623 #endif
624 #endif
625
626 #ifdef IN_LIBGCC2
627 #undef TARGET_64BIT
628 /* Make this compile time constant for libgcc2 */
629 #ifdef __mips64
630 #define TARGET_64BIT 1
631 #else
632 #define TARGET_64BIT 0
633 #endif
634 #endif /* IN_LIBGCC2 */
635
636 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
637 when compiled with hardware floating point. This is because MIPS16
638 code cannot save and restore the floating-point registers, which is
639 important if in a mixed MIPS16/non-MIPS16 environment. */
640
641 #ifdef IN_LIBGCC2
642 #if __mips_hard_float
643 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
644 #endif
645 #endif /* IN_LIBGCC2 */
646
647 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
648
649 #ifndef MULTILIB_ENDIAN_DEFAULT
650 #if TARGET_ENDIAN_DEFAULT == 0
651 #define MULTILIB_ENDIAN_DEFAULT "EL"
652 #else
653 #define MULTILIB_ENDIAN_DEFAULT "EB"
654 #endif
655 #endif
656
657 #ifndef MULTILIB_ISA_DEFAULT
658 # if MIPS_ISA_DEFAULT == 1
659 # define MULTILIB_ISA_DEFAULT "mips1"
660 # else
661 # if MIPS_ISA_DEFAULT == 2
662 # define MULTILIB_ISA_DEFAULT "mips2"
663 # else
664 # if MIPS_ISA_DEFAULT == 3
665 # define MULTILIB_ISA_DEFAULT "mips3"
666 # else
667 # if MIPS_ISA_DEFAULT == 4
668 # define MULTILIB_ISA_DEFAULT "mips4"
669 # else
670 # if MIPS_ISA_DEFAULT == 32
671 # define MULTILIB_ISA_DEFAULT "mips32"
672 # else
673 # if MIPS_ISA_DEFAULT == 33
674 # define MULTILIB_ISA_DEFAULT "mips32r2"
675 # else
676 # if MIPS_ISA_DEFAULT == 64
677 # define MULTILIB_ISA_DEFAULT "mips64"
678 # else
679 # if MIPS_ISA_DEFAULT == 65
680 # define MULTILIB_ISA_DEFAULT "mips64r2"
681 # else
682 # define MULTILIB_ISA_DEFAULT "mips1"
683 # endif
684 # endif
685 # endif
686 # endif
687 # endif
688 # endif
689 # endif
690 # endif
691 #endif
692
693 #ifndef MIPS_ABI_DEFAULT
694 #define MIPS_ABI_DEFAULT ABI_32
695 #endif
696
697 /* Use the most portable ABI flag for the ASM specs. */
698
699 #if MIPS_ABI_DEFAULT == ABI_32
700 #define MULTILIB_ABI_DEFAULT "mabi=32"
701 #endif
702
703 #if MIPS_ABI_DEFAULT == ABI_O64
704 #define MULTILIB_ABI_DEFAULT "mabi=o64"
705 #endif
706
707 #if MIPS_ABI_DEFAULT == ABI_N32
708 #define MULTILIB_ABI_DEFAULT "mabi=n32"
709 #endif
710
711 #if MIPS_ABI_DEFAULT == ABI_64
712 #define MULTILIB_ABI_DEFAULT "mabi=64"
713 #endif
714
715 #if MIPS_ABI_DEFAULT == ABI_EABI
716 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
717 #endif
718
719 #ifndef MULTILIB_DEFAULTS
720 #define MULTILIB_DEFAULTS \
721 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
722 #endif
723
724 /* We must pass -EL to the linker by default for little endian embedded
725 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
726 linker will default to using big-endian output files. The OUTPUT_FORMAT
727 line must be in the linker script, otherwise -EB/-EL will not work. */
728
729 #ifndef ENDIAN_SPEC
730 #if TARGET_ENDIAN_DEFAULT == 0
731 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
732 #else
733 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
734 #endif
735 #endif
736
737 /* A spec condition that matches all non-mips16 -mips arguments. */
738
739 #define MIPS_ISA_LEVEL_OPTION_SPEC \
740 "mips1|mips2|mips3|mips4|mips32*|mips64*"
741
742 /* A spec condition that matches all non-mips16 architecture arguments. */
743
744 #define MIPS_ARCH_OPTION_SPEC \
745 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
746
747 /* A spec that infers a -mips argument from an -march argument,
748 or injects the default if no architecture is specified. */
749
750 #define MIPS_ISA_LEVEL_SPEC \
751 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
752 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
753 %{march=mips2|march=r6000:-mips2} \
754 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
755 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
756 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
757 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
758 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
759 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
760 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
761 |march=xlr: -mips64} \
762 %{march=mips64r2|march=octeon: -mips64r2} \
763 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
764
765 /* A spec that infers a -mhard-float or -msoft-float setting from an
766 -march argument. Note that soft-float and hard-float code are not
767 link-compatible. */
768
769 #define MIPS_ARCH_FLOAT_SPEC \
770 "%{mhard-float|msoft-float|march=mips*:; \
771 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
772 |march=34kc|march=74kc|march=1004kc|march=5kc \
773 |march=octeon|march=xlr: -msoft-float; \
774 march=*: -mhard-float}"
775
776 /* A spec condition that matches 32-bit options. It only works if
777 MIPS_ISA_LEVEL_SPEC has been applied. */
778
779 #define MIPS_32BIT_OPTION_SPEC \
780 "mips1|mips2|mips32*|mgp32"
781
782 #if MIPS_ABI_DEFAULT == ABI_O64 \
783 || MIPS_ABI_DEFAULT == ABI_N32 \
784 || MIPS_ABI_DEFAULT == ABI_64
785 #define OPT_ARCH64 "mabi=32|mgp32:;"
786 #define OPT_ARCH32 "mabi=32|mgp32"
787 #else
788 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
789 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
790 #endif
791
792 /* Support for a compile-time default CPU, et cetera. The rules are:
793 --with-arch is ignored if -march is specified or a -mips is specified
794 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
795 --with-tune is ignored if -mtune is specified; likewise
796 --with-tune-32 and --with-tune-64.
797 --with-abi is ignored if -mabi is specified.
798 --with-float is ignored if -mhard-float or -msoft-float are
799 specified.
800 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
801 specified. */
802 #define OPTION_DEFAULT_SPECS \
803 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
804 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
805 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
806 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
807 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
808 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
809 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
810 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
811 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
812 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
813 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
814 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
815
816
817 /* A spec that infers the -mdsp setting from an -march argument. */
818 #define BASE_DRIVER_SELF_SPECS \
819 "%{!mno-dsp:%{march=24ke*|march=34k*|march=74k*|march=1004k*: -mdsp}}"
820
821 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
822
823 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
824 && ISA_HAS_COND_TRAP)
825
826 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
827
828 /* True if the ABI can only work with 64-bit integer registers. We
829 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
830 otherwise floating-point registers must also be 64-bit. */
831 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
832
833 /* Likewise for 32-bit regs. */
834 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
835
836 /* True if the file format uses 64-bit symbols. At present, this is
837 only true for n64, which uses 64-bit ELF. */
838 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
839
840 /* True if symbols are 64 bits wide. This is usually determined by
841 the ABI's file format, but it can be overridden by -msym32. Note that
842 overriding the size with -msym32 changes the ABI of relocatable objects,
843 although it doesn't change the ABI of a fully-linked object. */
844 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS && !TARGET_SYM32)
845
846 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
847 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
848 || ISA_MIPS4 \
849 || ISA_MIPS64 \
850 || ISA_MIPS64R2)
851
852 /* ISA has branch likely instructions (e.g. mips2). */
853 /* Disable branchlikely for tx39 until compare rewrite. They haven't
854 been generated up to this point. */
855 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
856
857 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
858 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
859 || TARGET_MIPS5400 \
860 || TARGET_MIPS5500 \
861 || TARGET_MIPS7000 \
862 || TARGET_MIPS9000 \
863 || TARGET_MAD \
864 || ISA_MIPS32 \
865 || ISA_MIPS32R2 \
866 || ISA_MIPS64 \
867 || ISA_MIPS64R2) \
868 && !TARGET_MIPS16)
869
870 /* ISA has a three-operand multiplication instruction. */
871 #define ISA_HAS_DMUL3 (TARGET_64BIT \
872 && TARGET_OCTEON \
873 && !TARGET_MIPS16)
874
875 /* ISA has the floating-point conditional move instructions introduced
876 in mips4. */
877 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
878 || ISA_MIPS32 \
879 || ISA_MIPS32R2 \
880 || ISA_MIPS64 \
881 || ISA_MIPS64R2) \
882 && !TARGET_MIPS5500 \
883 && !TARGET_MIPS16)
884
885 /* ISA has the integer conditional move instructions introduced in mips4 and
886 ST Loongson 2E/2F. */
887 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
888
889 /* ISA has LDC1 and SDC1. */
890 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
891
892 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
893 branch on CC, and move (both FP and non-FP) on CC. */
894 #define ISA_HAS_8CC (ISA_MIPS4 \
895 || ISA_MIPS32 \
896 || ISA_MIPS32R2 \
897 || ISA_MIPS64 \
898 || ISA_MIPS64R2)
899
900 /* This is a catch all for other mips4 instructions: indexed load, the
901 FP madd and msub instructions, and the FP recip and recip sqrt
902 instructions. */
903 #define ISA_HAS_FP4 ((ISA_MIPS4 \
904 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
905 || ISA_MIPS64 \
906 || ISA_MIPS64R2) \
907 && !TARGET_MIPS16)
908
909 /* ISA has paired-single instructions. */
910 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
911
912 /* ISA has conditional trap instructions. */
913 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
914 && !TARGET_MIPS16)
915
916 /* ISA has integer multiply-accumulate instructions, madd and msub. */
917 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
918 || ISA_MIPS32R2 \
919 || ISA_MIPS64 \
920 || ISA_MIPS64R2) \
921 && !TARGET_MIPS16)
922
923 /* Integer multiply-accumulate instructions should be generated. */
924 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
925
926 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
927 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
928
929 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
930 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
931
932 /* ISA has floating-point nmadd and nmsub instructions
933 'd = -((a * b) [+-] c)'. */
934 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
935 ((ISA_MIPS4 \
936 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
937 || ISA_MIPS64 \
938 || ISA_MIPS64R2) \
939 && (!TARGET_MIPS5400 || TARGET_MAD) \
940 && !TARGET_MIPS16)
941
942 /* ISA has floating-point nmadd and nmsub instructions
943 'c = -((a * b) [+-] c)'. */
944 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
945 TARGET_LOONGSON_2EF
946
947 /* ISA has count leading zeroes/ones instruction (not implemented). */
948 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
949 || ISA_MIPS32R2 \
950 || ISA_MIPS64 \
951 || ISA_MIPS64R2) \
952 && !TARGET_MIPS16)
953
954 /* ISA has three operand multiply instructions that put
955 the high part in an accumulator: mulhi or mulhiu. */
956 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
957 || TARGET_MIPS5500 \
958 || TARGET_SR71K) \
959 && !TARGET_MIPS16)
960
961 /* ISA has three operand multiply instructions that
962 negates the result and puts the result in an accumulator. */
963 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
964 || TARGET_MIPS5500 \
965 || TARGET_SR71K) \
966 && !TARGET_MIPS16)
967
968 /* ISA has three operand multiply instructions that subtracts the
969 result from a 4th operand and puts the result in an accumulator. */
970 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
971 || TARGET_MIPS5500 \
972 || TARGET_SR71K) \
973 && !TARGET_MIPS16)
974
975 /* ISA has three operand multiply instructions that the result
976 from a 4th operand and puts the result in an accumulator. */
977 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
978 || TARGET_MIPS4130 \
979 || TARGET_MIPS5400 \
980 || TARGET_MIPS5500 \
981 || TARGET_SR71K) \
982 && !TARGET_MIPS16)
983
984 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
985 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
986 || TARGET_MIPS4130) \
987 && !TARGET_MIPS16)
988
989 /* ISA has the "ror" (rotate right) instructions. */
990 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
991 || ISA_MIPS64R2 \
992 || TARGET_MIPS5400 \
993 || TARGET_MIPS5500 \
994 || TARGET_SR71K \
995 || TARGET_SMARTMIPS) \
996 && !TARGET_MIPS16)
997
998 /* ISA has data prefetch instructions. This controls use of 'pref'. */
999 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1000 || TARGET_LOONGSON_2EF \
1001 || ISA_MIPS32 \
1002 || ISA_MIPS32R2 \
1003 || ISA_MIPS64 \
1004 || ISA_MIPS64R2) \
1005 && !TARGET_MIPS16)
1006
1007 /* ISA has data indexed prefetch instructions. This controls use of
1008 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1009 (prefx is a cop1x instruction, so can only be used if FP is
1010 enabled.) */
1011 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
1012 || ISA_MIPS32R2 \
1013 || ISA_MIPS64 \
1014 || ISA_MIPS64R2) \
1015 && !TARGET_MIPS16)
1016
1017 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1018 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1019 also requires TARGET_DOUBLE_FLOAT. */
1020 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1021
1022 /* ISA includes the MIPS32r2 seb and seh instructions. */
1023 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
1024 || ISA_MIPS64R2) \
1025 && !TARGET_MIPS16)
1026
1027 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1028 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
1029 || ISA_MIPS64R2) \
1030 && !TARGET_MIPS16)
1031
1032 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1033 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
1034 && (ISA_MIPS32R2 \
1035 || ISA_MIPS64R2))
1036
1037 /* ISA has lwxs instruction (load w/scaled index address. */
1038 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
1039
1040 /* The DSP ASE is available. */
1041 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1042
1043 /* Revision 2 of the DSP ASE is available. */
1044 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1045
1046 /* True if the result of a load is not available to the next instruction.
1047 A nop will then be needed between instructions like "lw $4,..."
1048 and "addiu $4,$4,1". */
1049 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1050 && !TARGET_MIPS3900 \
1051 && !TARGET_MIPS16)
1052
1053 /* Likewise mtc1 and mfc1. */
1054 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1055 && !TARGET_LOONGSON_2EF)
1056
1057 /* Likewise floating-point comparisons. */
1058 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1059 && !TARGET_LOONGSON_2EF)
1060
1061 /* True if mflo and mfhi can be immediately followed by instructions
1062 which write to the HI and LO registers.
1063
1064 According to MIPS specifications, MIPS ISAs I, II, and III need
1065 (at least) two instructions between the reads of HI/LO and
1066 instructions which write them, and later ISAs do not. Contradicting
1067 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1068 the UM for the NEC Vr5000) document needing the instructions between
1069 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1070 MIPS64 and later ISAs to have the interlocks, plus any specific
1071 earlier-ISA CPUs for which CPU documentation declares that the
1072 instructions are really interlocked. */
1073 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1074 || ISA_MIPS32R2 \
1075 || ISA_MIPS64 \
1076 || ISA_MIPS64R2 \
1077 || TARGET_MIPS5500 \
1078 || TARGET_LOONGSON_2EF)
1079
1080 /* ISA includes synci, jr.hb and jalr.hb. */
1081 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1082 || ISA_MIPS64R2) \
1083 && !TARGET_MIPS16)
1084
1085 /* ISA includes sync. */
1086 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1087 #define GENERATE_SYNC \
1088 (target_flags_explicit & MASK_LLSC \
1089 ? TARGET_LLSC && !TARGET_MIPS16 \
1090 : ISA_HAS_SYNC)
1091
1092 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1093 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1094 instructions. */
1095 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1096 #define GENERATE_LL_SC \
1097 (target_flags_explicit & MASK_LLSC \
1098 ? TARGET_LLSC && !TARGET_MIPS16 \
1099 : ISA_HAS_LL_SC)
1100
1101 /* ISA includes the baddu instruction. */
1102 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1103
1104 /* ISA includes the bbit* instructions. */
1105 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1106
1107 /* ISA includes the cins instruction. */
1108 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1109
1110 /* ISA includes the exts instruction. */
1111 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1112
1113 /* ISA includes the seq and sne instructions. */
1114 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1115
1116 /* ISA includes the pop instruction. */
1117 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1118
1119 /* The CACHE instruction is available in non-MIPS16 code. */
1120 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1121
1122 /* The CACHE instruction is available. */
1123 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1124 \f
1125 /* Add -G xx support. */
1126
1127 #undef SWITCH_TAKES_ARG
1128 #define SWITCH_TAKES_ARG(CHAR) \
1129 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1130
1131 #define OVERRIDE_OPTIONS mips_override_options ()
1132
1133 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1134
1135 /* Show we can debug even without a frame pointer. */
1136 #define CAN_DEBUG_WITHOUT_FP
1137 \f
1138 /* Tell collect what flags to pass to nm. */
1139 #ifndef NM_FLAGS
1140 #define NM_FLAGS "-Bn"
1141 #endif
1142
1143 \f
1144 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1145 to the assembler. It may be overridden by subtargets. */
1146 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1147 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1148 %{noasmopt:-O0} \
1149 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1150 #endif
1151
1152 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1153 the assembler. It may be overridden by subtargets.
1154
1155 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1156 COFF debugging info. */
1157
1158 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1159 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1160 %{g} %{g0} %{g1} %{g2} %{g3} \
1161 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1162 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1163 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1164 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1165 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1166 #endif
1167
1168 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1169 overridden by subtargets. */
1170
1171 #ifndef SUBTARGET_ASM_SPEC
1172 #define SUBTARGET_ASM_SPEC ""
1173 #endif
1174
1175 #undef ASM_SPEC
1176 #define ASM_SPEC "\
1177 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1178 %{mips32*} %{mips64*} \
1179 %{mips16} %{mno-mips16:-no-mips16} \
1180 %{mips3d} %{mno-mips3d:-no-mips3d} \
1181 %{mdmx} %{mno-mdmx:-no-mdmx} \
1182 %{mdsp} %{mno-dsp} \
1183 %{mdspr2} %{mno-dspr2} \
1184 %{msmartmips} %{mno-smartmips} \
1185 %{mmt} %{mno-mt} \
1186 %{mfix-vr4120} %{mfix-vr4130} \
1187 %(subtarget_asm_optimizing_spec) \
1188 %(subtarget_asm_debugging_spec) \
1189 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1190 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1191 %{mfp32} %{mfp64} \
1192 %{mshared} %{mno-shared} \
1193 %{msym32} %{mno-sym32} \
1194 %{mtune=*} %{v} \
1195 %(subtarget_asm_spec)"
1196
1197 /* Extra switches sometimes passed to the linker. */
1198 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1199 will interpret it as a -b option. */
1200
1201 #ifndef LINK_SPEC
1202 #define LINK_SPEC "\
1203 %(endian_spec) \
1204 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1205 %{bestGnum} %{shared} %{non_shared}"
1206 #endif /* LINK_SPEC defined */
1207
1208
1209 /* Specs for the compiler proper */
1210
1211 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1212 overridden by subtargets. */
1213 #ifndef SUBTARGET_CC1_SPEC
1214 #define SUBTARGET_CC1_SPEC ""
1215 #endif
1216
1217 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1218
1219 #undef CC1_SPEC
1220 #define CC1_SPEC "\
1221 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1222 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1223 %{save-temps: } \
1224 %(subtarget_cc1_spec)"
1225
1226 /* Preprocessor specs. */
1227
1228 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1229 overridden by subtargets. */
1230 #ifndef SUBTARGET_CPP_SPEC
1231 #define SUBTARGET_CPP_SPEC ""
1232 #endif
1233
1234 #define CPP_SPEC "%(subtarget_cpp_spec)"
1235
1236 /* This macro defines names of additional specifications to put in the specs
1237 that can be used in various specifications like CC1_SPEC. Its definition
1238 is an initializer with a subgrouping for each command option.
1239
1240 Each subgrouping contains a string constant, that defines the
1241 specification name, and a string constant that used by the GCC driver
1242 program.
1243
1244 Do not define this macro if it does not need to do anything. */
1245
1246 #define EXTRA_SPECS \
1247 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1248 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1249 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1250 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1251 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1252 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1253 { "endian_spec", ENDIAN_SPEC }, \
1254 SUBTARGET_EXTRA_SPECS
1255
1256 #ifndef SUBTARGET_EXTRA_SPECS
1257 #define SUBTARGET_EXTRA_SPECS
1258 #endif
1259 \f
1260 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1261 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1262
1263 #ifndef PREFERRED_DEBUGGING_TYPE
1264 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1265 #endif
1266
1267 /* The size of DWARF addresses should be the same as the size of symbols
1268 in the target file format. They shouldn't depend on things like -msym32,
1269 because many DWARF consumers do not allow the mixture of address sizes
1270 that one would then get from linking -msym32 code with -msym64 code.
1271
1272 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1273 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1274 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1275
1276 /* By default, turn on GDB extensions. */
1277 #define DEFAULT_GDB_EXTENSIONS 1
1278
1279 /* Local compiler-generated symbols must have a prefix that the assembler
1280 understands. By default, this is $, although some targets (e.g.,
1281 NetBSD-ELF) need to override this. */
1282
1283 #ifndef LOCAL_LABEL_PREFIX
1284 #define LOCAL_LABEL_PREFIX "$"
1285 #endif
1286
1287 /* By default on the mips, external symbols do not have an underscore
1288 prepended, but some targets (e.g., NetBSD) require this. */
1289
1290 #ifndef USER_LABEL_PREFIX
1291 #define USER_LABEL_PREFIX ""
1292 #endif
1293
1294 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1295 since the length can run past this up to a continuation point. */
1296 #undef DBX_CONTIN_LENGTH
1297 #define DBX_CONTIN_LENGTH 1500
1298
1299 /* How to renumber registers for dbx and gdb. */
1300 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1301
1302 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1303 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1304
1305 /* The DWARF 2 CFA column which tracks the return address. */
1306 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1307
1308 /* Before the prologue, RA lives in r31. */
1309 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1310
1311 /* Describe how we implement __builtin_eh_return. */
1312 #define EH_RETURN_DATA_REGNO(N) \
1313 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1314
1315 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1316
1317 #define EH_USES(N) mips_eh_uses (N)
1318
1319 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1320 The default for this in 64-bit mode is 8, which causes problems with
1321 SFmode register saves. */
1322 #define DWARF_CIE_DATA_ALIGNMENT -4
1323
1324 /* Correct the offset of automatic variables and arguments. Note that
1325 the MIPS debug format wants all automatic variables and arguments
1326 to be in terms of the virtual frame pointer (stack pointer before
1327 any adjustment in the function), while the MIPS 3.0 linker wants
1328 the frame pointer to be the stack pointer after the initial
1329 adjustment. */
1330
1331 #define DEBUGGER_AUTO_OFFSET(X) \
1332 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1333 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1334 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1335 \f
1336 /* Target machine storage layout */
1337
1338 #define BITS_BIG_ENDIAN 0
1339 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1340 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1341
1342 /* Define this to set the endianness to use in libgcc2.c, which can
1343 not depend on target_flags. */
1344 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1345 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1346 #else
1347 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1348 #endif
1349
1350 #define MAX_BITS_PER_WORD 64
1351
1352 /* Width of a word, in units (bytes). */
1353 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1354 #ifndef IN_LIBGCC2
1355 #define MIN_UNITS_PER_WORD 4
1356 #endif
1357
1358 /* For MIPS, width of a floating point register. */
1359 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1360
1361 /* The number of consecutive floating-point registers needed to store the
1362 largest format supported by the FPU. */
1363 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1364
1365 /* The number of consecutive floating-point registers needed to store the
1366 smallest format supported by the FPU. */
1367 #define MIN_FPRS_PER_FMT \
1368 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1369 ? 1 : MAX_FPRS_PER_FMT)
1370
1371 /* The largest size of value that can be held in floating-point
1372 registers and moved with a single instruction. */
1373 #define UNITS_PER_HWFPVALUE \
1374 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1375
1376 /* The largest size of value that can be held in floating-point
1377 registers. */
1378 #define UNITS_PER_FPVALUE \
1379 (TARGET_SOFT_FLOAT_ABI ? 0 \
1380 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1381 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1382
1383 /* The number of bytes in a double. */
1384 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1385
1386 #define UNITS_PER_SIMD_WORD(MODE) \
1387 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1388
1389 /* Set the sizes of the core types. */
1390 #define SHORT_TYPE_SIZE 16
1391 #define INT_TYPE_SIZE 32
1392 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1393 #define LONG_LONG_TYPE_SIZE 64
1394
1395 #define FLOAT_TYPE_SIZE 32
1396 #define DOUBLE_TYPE_SIZE 64
1397 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1398
1399 /* Define the sizes of fixed-point types. */
1400 #define SHORT_FRACT_TYPE_SIZE 8
1401 #define FRACT_TYPE_SIZE 16
1402 #define LONG_FRACT_TYPE_SIZE 32
1403 #define LONG_LONG_FRACT_TYPE_SIZE 64
1404
1405 #define SHORT_ACCUM_TYPE_SIZE 16
1406 #define ACCUM_TYPE_SIZE 32
1407 #define LONG_ACCUM_TYPE_SIZE 64
1408 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1409 doesn't support 128-bit integers for MIPS32 currently. */
1410 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1411
1412 /* long double is not a fixed mode, but the idea is that, if we
1413 support long double, we also want a 128-bit integer type. */
1414 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1415
1416 #ifdef IN_LIBGCC2
1417 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1418 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1419 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1420 # else
1421 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1422 # endif
1423 #endif
1424
1425 /* Width in bits of a pointer. */
1426 #ifndef POINTER_SIZE
1427 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1428 #endif
1429
1430 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1431 #define PARM_BOUNDARY BITS_PER_WORD
1432
1433 /* Allocation boundary (in *bits*) for the code of a function. */
1434 #define FUNCTION_BOUNDARY 32
1435
1436 /* Alignment of field after `int : 0' in a structure. */
1437 #define EMPTY_FIELD_BOUNDARY 32
1438
1439 /* Every structure's size must be a multiple of this. */
1440 /* 8 is observed right on a DECstation and on riscos 4.02. */
1441 #define STRUCTURE_SIZE_BOUNDARY 8
1442
1443 /* There is no point aligning anything to a rounder boundary than this. */
1444 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1445
1446 /* All accesses must be aligned. */
1447 #define STRICT_ALIGNMENT 1
1448
1449 /* Define this if you wish to imitate the way many other C compilers
1450 handle alignment of bitfields and the structures that contain
1451 them.
1452
1453 The behavior is that the type written for a bit-field (`int',
1454 `short', or other integer type) imposes an alignment for the
1455 entire structure, as if the structure really did contain an
1456 ordinary field of that type. In addition, the bit-field is placed
1457 within the structure so that it would fit within such a field,
1458 not crossing a boundary for it.
1459
1460 Thus, on most machines, a bit-field whose type is written as `int'
1461 would not cross a four-byte boundary, and would force four-byte
1462 alignment for the whole structure. (The alignment used may not
1463 be four bytes; it is controlled by the other alignment
1464 parameters.)
1465
1466 If the macro is defined, its definition should be a C expression;
1467 a nonzero value for the expression enables this behavior. */
1468
1469 #define PCC_BITFIELD_TYPE_MATTERS 1
1470
1471 /* If defined, a C expression to compute the alignment given to a
1472 constant that is being placed in memory. CONSTANT is the constant
1473 and ALIGN is the alignment that the object would ordinarily have.
1474 The value of this macro is used instead of that alignment to align
1475 the object.
1476
1477 If this macro is not defined, then ALIGN is used.
1478
1479 The typical use of this macro is to increase alignment for string
1480 constants to be word aligned so that `strcpy' calls that copy
1481 constants can be done inline. */
1482
1483 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1484 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1485 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1486
1487 /* If defined, a C expression to compute the alignment for a static
1488 variable. TYPE is the data type, and ALIGN is the alignment that
1489 the object would ordinarily have. The value of this macro is used
1490 instead of that alignment to align the object.
1491
1492 If this macro is not defined, then ALIGN is used.
1493
1494 One use of this macro is to increase alignment of medium-size
1495 data to make it all fit in fewer cache lines. Another is to
1496 cause character arrays to be word-aligned so that `strcpy' calls
1497 that copy constants to character arrays can be done inline. */
1498
1499 #undef DATA_ALIGNMENT
1500 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1501 ((((ALIGN) < BITS_PER_WORD) \
1502 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1503 || TREE_CODE (TYPE) == UNION_TYPE \
1504 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1505
1506 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1507 character arrays to be word-aligned so that `strcpy' calls that copy
1508 constants to character arrays can be done inline, and 'strcmp' can be
1509 optimised to use word loads. */
1510 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1511 DATA_ALIGNMENT (TYPE, ALIGN)
1512
1513 #define PAD_VARARGS_DOWN \
1514 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1515
1516 /* Define if operations between registers always perform the operation
1517 on the full register even if a narrower mode is specified. */
1518 #define WORD_REGISTER_OPERATIONS
1519
1520 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1521 moves. All other references are zero extended. */
1522 #define LOAD_EXTEND_OP(MODE) \
1523 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1524 ? SIGN_EXTEND : ZERO_EXTEND)
1525
1526 /* Define this macro if it is advisable to hold scalars in registers
1527 in a wider mode than that declared by the program. In such cases,
1528 the value is constrained to be within the bounds of the declared
1529 type, but kept valid in the wider mode. The signedness of the
1530 extension may differ from that of the type. */
1531
1532 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1533 if (GET_MODE_CLASS (MODE) == MODE_INT \
1534 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1535 { \
1536 if ((MODE) == SImode) \
1537 (UNSIGNEDP) = 0; \
1538 (MODE) = Pmode; \
1539 }
1540
1541 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1542 Extensions of pointers to word_mode must be signed. */
1543 #define POINTERS_EXTEND_UNSIGNED false
1544
1545 /* Define if loading short immediate values into registers sign extends. */
1546 #define SHORT_IMMEDIATES_SIGN_EXTEND
1547
1548 /* The [d]clz instructions have the natural values at 0. */
1549
1550 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1551 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1552 \f
1553 /* Standard register usage. */
1554
1555 /* Number of hardware registers. We have:
1556
1557 - 32 integer registers
1558 - 32 floating point registers
1559 - 8 condition code registers
1560 - 2 accumulator registers (hi and lo)
1561 - 32 registers each for coprocessors 0, 2 and 3
1562 - 4 fake registers:
1563 - ARG_POINTER_REGNUM
1564 - FRAME_POINTER_REGNUM
1565 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1566 - CPRESTORE_SLOT_REGNUM
1567 - 2 dummy entries that were used at various times in the past.
1568 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1569 - 6 DSP control registers */
1570
1571 #define FIRST_PSEUDO_REGISTER 188
1572
1573 /* By default, fix the kernel registers ($26 and $27), the global
1574 pointer ($28) and the stack pointer ($29). This can change
1575 depending on the command-line options.
1576
1577 Regarding coprocessor registers: without evidence to the contrary,
1578 it's best to assume that each coprocessor register has a unique
1579 use. This can be overridden, in, e.g., mips_override_options or
1580 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1581 for a particular target. */
1582
1583 #define FIXED_REGISTERS \
1584 { \
1585 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1588 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1589 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1590 /* COP0 registers */ \
1591 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1592 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1593 /* COP2 registers */ \
1594 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1595 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1596 /* COP3 registers */ \
1597 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1598 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1599 /* 6 DSP accumulator registers & 6 control registers */ \
1600 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1601 }
1602
1603
1604 /* Set up this array for o32 by default.
1605
1606 Note that we don't mark $31 as a call-clobbered register. The idea is
1607 that it's really the call instructions themselves which clobber $31.
1608 We don't care what the called function does with it afterwards.
1609
1610 This approach makes it easier to implement sibcalls. Unlike normal
1611 calls, sibcalls don't clobber $31, so the register reaches the
1612 called function in tact. EPILOGUE_USES says that $31 is useful
1613 to the called function. */
1614
1615 #define CALL_USED_REGISTERS \
1616 { \
1617 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1618 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1619 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1620 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1621 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1622 /* COP0 registers */ \
1623 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1624 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1625 /* COP2 registers */ \
1626 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1627 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1628 /* COP3 registers */ \
1629 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1630 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1631 /* 6 DSP accumulator registers & 6 control registers */ \
1632 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1633 }
1634
1635
1636 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1637
1638 #define CALL_REALLY_USED_REGISTERS \
1639 { /* General registers. */ \
1640 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1641 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1642 /* Floating-point registers. */ \
1643 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1644 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1645 /* Others. */ \
1646 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1647 /* COP0 registers */ \
1648 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1649 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1650 /* COP2 registers */ \
1651 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1652 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1653 /* COP3 registers */ \
1654 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1655 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1656 /* 6 DSP accumulator registers & 6 control registers */ \
1657 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1658 }
1659
1660 /* Internal macros to classify a register number as to whether it's a
1661 general purpose register, a floating point register, a
1662 multiply/divide register, or a status register. */
1663
1664 #define GP_REG_FIRST 0
1665 #define GP_REG_LAST 31
1666 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1667 #define GP_DBX_FIRST 0
1668 #define K0_REG_NUM (GP_REG_FIRST + 26)
1669 #define K1_REG_NUM (GP_REG_FIRST + 27)
1670 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1671
1672 #define FP_REG_FIRST 32
1673 #define FP_REG_LAST 63
1674 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1675 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1676
1677 #define MD_REG_FIRST 64
1678 #define MD_REG_LAST 65
1679 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1680 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1681
1682 /* The DWARF 2 CFA column which tracks the return address from a
1683 signal handler context. This means that to maintain backwards
1684 compatibility, no hard register can be assigned this column if it
1685 would need to be handled by the DWARF unwinder. */
1686 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1687
1688 #define ST_REG_FIRST 67
1689 #define ST_REG_LAST 74
1690 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1691
1692
1693 /* FIXME: renumber. */
1694 #define COP0_REG_FIRST 80
1695 #define COP0_REG_LAST 111
1696 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1697
1698 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1699 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1700 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1701
1702 #define COP2_REG_FIRST 112
1703 #define COP2_REG_LAST 143
1704 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1705
1706 #define COP3_REG_FIRST 144
1707 #define COP3_REG_LAST 175
1708 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1709 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1710 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1711
1712 #define DSP_ACC_REG_FIRST 176
1713 #define DSP_ACC_REG_LAST 181
1714 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1715
1716 #define AT_REGNUM (GP_REG_FIRST + 1)
1717 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1718 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1719
1720 /* A few bitfield locations for the coprocessor registers. */
1721 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1722 the cause register for the EIC interrupt mode. */
1723 #define CAUSE_IPL 10
1724 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1725 #define SR_IPL 10
1726 /* Exception Level is at bit 1 of the status register. */
1727 #define SR_EXL 1
1728 /* Interrupt Enable is at bit 0 of the status register. */
1729 #define SR_IE 0
1730
1731 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1732 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1733 should be used instead. */
1734 #define FPSW_REGNUM ST_REG_FIRST
1735
1736 #define GP_REG_P(REGNO) \
1737 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1738 #define M16_REG_P(REGNO) \
1739 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1740 #define FP_REG_P(REGNO) \
1741 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1742 #define MD_REG_P(REGNO) \
1743 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1744 #define ST_REG_P(REGNO) \
1745 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1746 #define COP0_REG_P(REGNO) \
1747 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1748 #define COP2_REG_P(REGNO) \
1749 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1750 #define COP3_REG_P(REGNO) \
1751 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1752 #define ALL_COP_REG_P(REGNO) \
1753 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1754 /* Test if REGNO is one of the 6 new DSP accumulators. */
1755 #define DSP_ACC_REG_P(REGNO) \
1756 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1757 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1758 #define ACC_REG_P(REGNO) \
1759 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1760
1761 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1762
1763 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1764 to initialize the mips16 gp pseudo register. */
1765 #define CONST_GP_P(X) \
1766 (GET_CODE (X) == CONST \
1767 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1768 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1769
1770 /* Return coprocessor number from register number. */
1771
1772 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1773 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1774 : COP3_REG_P (REGNO) ? '3' : '?')
1775
1776
1777 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1778
1779 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1780 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1781
1782 #define MODES_TIEABLE_P mips_modes_tieable_p
1783
1784 /* Register to use for pushing function arguments. */
1785 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1786
1787 /* These two registers don't really exist: they get eliminated to either
1788 the stack or hard frame pointer. */
1789 #define ARG_POINTER_REGNUM 77
1790 #define FRAME_POINTER_REGNUM 78
1791
1792 /* $30 is not available on the mips16, so we use $17 as the frame
1793 pointer. */
1794 #define HARD_FRAME_POINTER_REGNUM \
1795 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1796
1797 /* Register in which static-chain is passed to a function. */
1798 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1799
1800 /* Registers used as temporaries in prologue/epilogue code:
1801
1802 - If a MIPS16 PIC function needs access to _gp, it first loads
1803 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1804
1805 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1806 register. The register must not conflict with MIPS16_PIC_TEMP.
1807
1808 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1809 register.
1810
1811 If we're generating MIPS16 code, these registers must come from the
1812 core set of 8. The prologue registers mustn't conflict with any
1813 incoming arguments, the static chain pointer, or the frame pointer.
1814 The epilogue temporary mustn't conflict with the return registers,
1815 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1816 or the EH data registers.
1817
1818 If we're generating interrupt handlers, we use K0 as a temporary register
1819 in prologue/epilogue code. */
1820
1821 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1822 #define MIPS_PROLOGUE_TEMP_REGNUM \
1823 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1824 #define MIPS_EPILOGUE_TEMP_REGNUM \
1825 (cfun->machine->interrupt_handler_p \
1826 ? K0_REG_NUM \
1827 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1828
1829 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1830 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1831 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1832
1833 /* Define this macro if it is as good or better to call a constant
1834 function address than to call an address kept in a register. */
1835 #define NO_FUNCTION_CSE 1
1836
1837 /* The ABI-defined global pointer. Sometimes we use a different
1838 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1839 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1840
1841 /* We normally use $28 as the global pointer. However, when generating
1842 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1843 register instead. They can then avoid saving and restoring $28
1844 and perhaps avoid using a frame at all.
1845
1846 When a leaf function uses something other than $28, mips_expand_prologue
1847 will modify pic_offset_table_rtx in place. Take the register number
1848 from there after reload. */
1849 #define PIC_OFFSET_TABLE_REGNUM \
1850 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1851
1852 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1853 \f
1854 /* Define the classes of registers for register constraints in the
1855 machine description. Also define ranges of constants.
1856
1857 One of the classes must always be named ALL_REGS and include all hard regs.
1858 If there is more than one class, another class must be named NO_REGS
1859 and contain no registers.
1860
1861 The name GENERAL_REGS must be the name of a class (or an alias for
1862 another name such as ALL_REGS). This is the class of registers
1863 that is allowed by "g" or "r" in a register constraint.
1864 Also, registers outside this class are allocated only when
1865 instructions express preferences for them.
1866
1867 The classes must be numbered in nondecreasing order; that is,
1868 a larger-numbered class must never be contained completely
1869 in a smaller-numbered class.
1870
1871 For any two classes, it is very desirable that there be another
1872 class that represents their union. */
1873
1874 enum reg_class
1875 {
1876 NO_REGS, /* no registers in set */
1877 M16_REGS, /* mips16 directly accessible registers */
1878 T_REG, /* mips16 T register ($24) */
1879 M16_T_REGS, /* mips16 registers plus T register */
1880 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1881 V1_REG, /* Register $v1 ($3) used for TLS access. */
1882 LEA_REGS, /* Every GPR except $25 */
1883 GR_REGS, /* integer registers */
1884 FP_REGS, /* floating point registers */
1885 MD0_REG, /* first multiply/divide register */
1886 MD1_REG, /* second multiply/divide register */
1887 MD_REGS, /* multiply/divide registers (hi/lo) */
1888 COP0_REGS, /* generic coprocessor classes */
1889 COP2_REGS,
1890 COP3_REGS,
1891 ST_REGS, /* status registers (fp status) */
1892 DSP_ACC_REGS, /* DSP accumulator registers */
1893 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1894 FRAME_REGS, /* $arg and $frame */
1895 GR_AND_MD0_REGS, /* union classes */
1896 GR_AND_MD1_REGS,
1897 GR_AND_MD_REGS,
1898 GR_AND_ACC_REGS,
1899 ALL_REGS, /* all registers */
1900 LIM_REG_CLASSES /* max value + 1 */
1901 };
1902
1903 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1904
1905 #define GENERAL_REGS GR_REGS
1906
1907 /* An initializer containing the names of the register classes as C
1908 string constants. These names are used in writing some of the
1909 debugging dumps. */
1910
1911 #define REG_CLASS_NAMES \
1912 { \
1913 "NO_REGS", \
1914 "M16_REGS", \
1915 "T_REG", \
1916 "M16_T_REGS", \
1917 "PIC_FN_ADDR_REG", \
1918 "V1_REG", \
1919 "LEA_REGS", \
1920 "GR_REGS", \
1921 "FP_REGS", \
1922 "MD0_REG", \
1923 "MD1_REG", \
1924 "MD_REGS", \
1925 /* coprocessor registers */ \
1926 "COP0_REGS", \
1927 "COP2_REGS", \
1928 "COP3_REGS", \
1929 "ST_REGS", \
1930 "DSP_ACC_REGS", \
1931 "ACC_REGS", \
1932 "FRAME_REGS", \
1933 "GR_AND_MD0_REGS", \
1934 "GR_AND_MD1_REGS", \
1935 "GR_AND_MD_REGS", \
1936 "GR_AND_ACC_REGS", \
1937 "ALL_REGS" \
1938 }
1939
1940 /* An initializer containing the contents of the register classes,
1941 as integers which are bit masks. The Nth integer specifies the
1942 contents of class N. The way the integer MASK is interpreted is
1943 that register R is in the class if `MASK & (1 << R)' is 1.
1944
1945 When the machine has more than 32 registers, an integer does not
1946 suffice. Then the integers are replaced by sub-initializers,
1947 braced groupings containing several integers. Each
1948 sub-initializer must be suitable as an initializer for the type
1949 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1950
1951 #define REG_CLASS_CONTENTS \
1952 { \
1953 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1954 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1955 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1956 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1957 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1958 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1959 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1960 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1961 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1962 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1963 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1964 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1965 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1966 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1967 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1968 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1969 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1970 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1971 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1972 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1973 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1974 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1975 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1976 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1977 }
1978
1979
1980 /* A C expression whose value is a register class containing hard
1981 register REGNO. In general there is more that one such class;
1982 choose a class which is "minimal", meaning that no smaller class
1983 also contains the register. */
1984
1985 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1986
1987 /* A macro whose definition is the name of the class to which a
1988 valid base register must belong. A base register is one used in
1989 an address which is the register value plus a displacement. */
1990
1991 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1992
1993 /* A macro whose definition is the name of the class to which a
1994 valid index register must belong. An index register is one used
1995 in an address where its value is either multiplied by a scale
1996 factor or added to another register (as well as added to a
1997 displacement). */
1998
1999 #define INDEX_REG_CLASS NO_REGS
2000
2001 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2002 registers explicitly used in the rtl to be used as spill registers
2003 but prevents the compiler from extending the lifetime of these
2004 registers. */
2005
2006 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2007
2008 /* We generally want to put call-clobbered registers ahead of
2009 call-saved ones. (IRA expects this.) */
2010
2011 #define REG_ALLOC_ORDER \
2012 { /* Accumulator registers. When GPRs and accumulators have equal \
2013 cost, we generally prefer to use accumulators. For example, \
2014 a division of multiplication result is better allocated to LO, \
2015 so that we put the MFLO at the point of use instead of at the \
2016 point of definition. It's also needed if we're to take advantage \
2017 of the extra accumulators available with -mdspr2. In some cases, \
2018 it can also help to reduce register pressure. */ \
2019 64, 65,176,177,178,179,180,181, \
2020 /* Call-clobbered GPRs. */ \
2021 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2022 24, 25, 31, \
2023 /* The global pointer. This is call-clobbered for o32 and o64 \
2024 abicalls, call-saved for n32 and n64 abicalls, and a program \
2025 invariant otherwise. Putting it between the call-clobbered \
2026 and call-saved registers should cope with all eventualities. */ \
2027 28, \
2028 /* Call-saved GPRs. */ \
2029 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2030 /* GPRs that can never be exposed to the register allocator. */ \
2031 0, 26, 27, 29, \
2032 /* Call-clobbered FPRs. */ \
2033 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2034 48, 49, 50, 51, \
2035 /* FPRs that are usually call-saved. The odd ones are actually \
2036 call-clobbered for n32, but listing them ahead of the even \
2037 registers might encourage the register allocator to fragment \
2038 the available FPR pairs. We need paired FPRs to store long \
2039 doubles, so it isn't clear that using a different order \
2040 for n32 would be a win. */ \
2041 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2042 /* None of the remaining classes have defined call-saved \
2043 registers. */ \
2044 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2045 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2046 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2047 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2048 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2049 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2050 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2051 182,183,184,185,186,187 \
2052 }
2053
2054 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2055 to be rearranged based on a particular function. On the mips16, we
2056 want to allocate $24 (T_REG) before other registers for
2057 instructions for which it is possible. */
2058
2059 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2060
2061 /* True if VALUE is an unsigned 6-bit number. */
2062
2063 #define UIMM6_OPERAND(VALUE) \
2064 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2065
2066 /* True if VALUE is a signed 10-bit number. */
2067
2068 #define IMM10_OPERAND(VALUE) \
2069 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2070
2071 /* True if VALUE is a signed 16-bit number. */
2072
2073 #define SMALL_OPERAND(VALUE) \
2074 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2075
2076 /* True if VALUE is an unsigned 16-bit number. */
2077
2078 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2079 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2080
2081 /* True if VALUE can be loaded into a register using LUI. */
2082
2083 #define LUI_OPERAND(VALUE) \
2084 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2085 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2086
2087 /* Return a value X with the low 16 bits clear, and such that
2088 VALUE - X is a signed 16-bit value. */
2089
2090 #define CONST_HIGH_PART(VALUE) \
2091 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2092
2093 #define CONST_LOW_PART(VALUE) \
2094 ((VALUE) - CONST_HIGH_PART (VALUE))
2095
2096 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2097 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2098 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2099
2100 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2101 mips_preferred_reload_class (X, CLASS)
2102
2103 /* The HI and LO registers can only be reloaded via the general
2104 registers. Condition code registers can only be loaded to the
2105 general registers, and from the floating point registers. */
2106
2107 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2108 mips_secondary_reload_class (CLASS, MODE, X, true)
2109 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2110 mips_secondary_reload_class (CLASS, MODE, X, false)
2111
2112 /* Return the maximum number of consecutive registers
2113 needed to represent mode MODE in a register of class CLASS. */
2114
2115 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2116
2117 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2118 mips_cannot_change_mode_class (FROM, TO, CLASS)
2119 \f
2120 /* Stack layout; function entry, exit and calling. */
2121
2122 #define STACK_GROWS_DOWNWARD
2123
2124 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2125
2126 /* Size of the area allocated in the frame to save the GP. */
2127
2128 #define MIPS_GP_SAVE_AREA_SIZE \
2129 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2130
2131 /* The offset of the first local variable from the frame pointer. See
2132 mips_compute_frame_info for details about the frame layout. */
2133
2134 #define STARTING_FRAME_OFFSET \
2135 (FRAME_GROWS_DOWNWARD \
2136 ? 0 \
2137 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2138
2139 #define RETURN_ADDR_RTX mips_return_addr
2140
2141 /* Mask off the MIPS16 ISA bit in unwind addresses.
2142
2143 The reason for this is a little subtle. When unwinding a call,
2144 we are given the call's return address, which on most targets
2145 is the address of the following instruction. However, what we
2146 actually want to find is the EH region for the call itself.
2147 The target-independent unwind code therefore searches for "RA - 1".
2148
2149 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2150 RA - 1 is therefore the real (even-valued) start of the return
2151 instruction. EH region labels are usually odd-valued MIPS16 symbols
2152 too, so a search for an even address within a MIPS16 region would
2153 usually work.
2154
2155 However, there is an exception. If the end of an EH region is also
2156 the end of a function, the end label is allowed to be even. This is
2157 necessary because a following non-MIPS16 function may also need EH
2158 information for its first instruction.
2159
2160 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2161 non-ISA-encoded address. This probably isn't ideal, but it is
2162 the traditional (legacy) behavior. It is therefore only safe
2163 to search MIPS EH regions for an _odd-valued_ address.
2164
2165 Masking off the ISA bit means that the target-independent code
2166 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2167 #define MASK_RETURN_ADDR GEN_INT (-2)
2168
2169
2170 /* Similarly, don't use the least-significant bit to tell pointers to
2171 code from vtable index. */
2172
2173 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2174
2175 /* The eliminations to $17 are only used for mips16 code. See the
2176 definition of HARD_FRAME_POINTER_REGNUM. */
2177
2178 #define ELIMINABLE_REGS \
2179 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2180 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2181 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2182 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2183 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2184 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2185
2186 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2187 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2188
2189 /* Allocate stack space for arguments at the beginning of each function. */
2190 #define ACCUMULATE_OUTGOING_ARGS 1
2191
2192 /* The argument pointer always points to the first argument. */
2193 #define FIRST_PARM_OFFSET(FNDECL) 0
2194
2195 /* o32 and o64 reserve stack space for all argument registers. */
2196 #define REG_PARM_STACK_SPACE(FNDECL) \
2197 (TARGET_OLDABI \
2198 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2199 : 0)
2200
2201 /* Define this if it is the responsibility of the caller to
2202 allocate the area reserved for arguments passed in registers.
2203 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2204 of this macro is to determine whether the space is included in
2205 `crtl->outgoing_args_size'. */
2206 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2207
2208 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2209 \f
2210 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2211
2212 /* Symbolic macros for the registers used to return integer and floating
2213 point values. */
2214
2215 #define GP_RETURN (GP_REG_FIRST + 2)
2216 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2217
2218 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2219
2220 /* Symbolic macros for the first/last argument registers. */
2221
2222 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2223 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2224 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2225 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2226
2227 #define LIBCALL_VALUE(MODE) \
2228 mips_function_value (NULL_TREE, NULL_TREE, MODE)
2229
2230 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2231 mips_function_value (VALTYPE, FUNC, VOIDmode)
2232
2233 /* 1 if N is a possible register number for a function value.
2234 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2235 Currently, R2 and F0 are only implemented here (C has no complex type) */
2236
2237 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2238 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2239 && (N) == FP_RETURN + 2))
2240
2241 /* 1 if N is a possible register number for function argument passing.
2242 We have no FP argument registers when soft-float. When FP registers
2243 are 32 bits, we can't directly reference the odd numbered ones. */
2244
2245 #define FUNCTION_ARG_REGNO_P(N) \
2246 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2247 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2248 && !fixed_regs[N])
2249 \f
2250 /* This structure has to cope with two different argument allocation
2251 schemes. Most MIPS ABIs view the arguments as a structure, of which
2252 the first N words go in registers and the rest go on the stack. If I
2253 < N, the Ith word might go in Ith integer argument register or in a
2254 floating-point register. For these ABIs, we only need to remember
2255 the offset of the current argument into the structure.
2256
2257 The EABI instead allocates the integer and floating-point arguments
2258 separately. The first N words of FP arguments go in FP registers,
2259 the rest go on the stack. Likewise, the first N words of the other
2260 arguments go in integer registers, and the rest go on the stack. We
2261 need to maintain three counts: the number of integer registers used,
2262 the number of floating-point registers used, and the number of words
2263 passed on the stack.
2264
2265 We could keep separate information for the two ABIs (a word count for
2266 the standard ABIs, and three separate counts for the EABI). But it
2267 seems simpler to view the standard ABIs as forms of EABI that do not
2268 allocate floating-point registers.
2269
2270 So for the standard ABIs, the first N words are allocated to integer
2271 registers, and mips_function_arg decides on an argument-by-argument
2272 basis whether that argument should really go in an integer register,
2273 or in a floating-point one. */
2274
2275 typedef struct mips_args {
2276 /* Always true for varargs functions. Otherwise true if at least
2277 one argument has been passed in an integer register. */
2278 int gp_reg_found;
2279
2280 /* The number of arguments seen so far. */
2281 unsigned int arg_number;
2282
2283 /* The number of integer registers used so far. For all ABIs except
2284 EABI, this is the number of words that have been added to the
2285 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2286 unsigned int num_gprs;
2287
2288 /* For EABI, the number of floating-point registers used so far. */
2289 unsigned int num_fprs;
2290
2291 /* The number of words passed on the stack. */
2292 unsigned int stack_words;
2293
2294 /* On the mips16, we need to keep track of which floating point
2295 arguments were passed in general registers, but would have been
2296 passed in the FP regs if this were a 32-bit function, so that we
2297 can move them to the FP regs if we wind up calling a 32-bit
2298 function. We record this information in fp_code, encoded in base
2299 four. A zero digit means no floating point argument, a one digit
2300 means an SFmode argument, and a two digit means a DFmode argument,
2301 and a three digit is not used. The low order digit is the first
2302 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2303 an SFmode argument. ??? A more sophisticated approach will be
2304 needed if MIPS_ABI != ABI_32. */
2305 int fp_code;
2306
2307 /* True if the function has a prototype. */
2308 int prototype;
2309 } CUMULATIVE_ARGS;
2310
2311 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2312 for a call to a function whose data type is FNTYPE.
2313 For a library call, FNTYPE is 0. */
2314
2315 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2316 mips_init_cumulative_args (&CUM, FNTYPE)
2317
2318 /* Update the data in CUM to advance over an argument
2319 of mode MODE and data type TYPE.
2320 (TYPE is null for libcalls where that information may not be available.) */
2321
2322 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2323 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
2324
2325 /* Determine where to put an argument to a function.
2326 Value is zero to push the argument on the stack,
2327 or a hard register in which to store the argument.
2328
2329 MODE is the argument's machine mode.
2330 TYPE is the data type of the argument (as a tree).
2331 This is null for libcalls where that information may
2332 not be available.
2333 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2334 the preceding args and about the function being called.
2335 NAMED is nonzero if this argument is a named parameter
2336 (otherwise it is an extra parameter matching an ellipsis). */
2337
2338 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2339 mips_function_arg (&CUM, MODE, TYPE, NAMED)
2340
2341 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2342
2343 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2344 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2345
2346 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2347 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2348
2349 /* True if using EABI and varargs can be passed in floating-point
2350 registers. Under these conditions, we need a more complex form
2351 of va_list, which tracks GPR, FPR and stack arguments separately. */
2352 #define EABI_FLOAT_VARARGS_P \
2353 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2354
2355 \f
2356 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2357
2358 /* Treat LOC as a byte offset from the stack pointer and round it up
2359 to the next fully-aligned offset. */
2360 #define MIPS_STACK_ALIGN(LOC) \
2361 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2362
2363 \f
2364 /* Output assembler code to FILE to increment profiler label # LABELNO
2365 for profiling a function entry. */
2366
2367 #define FUNCTION_PROFILER(FILE, LABELNO) \
2368 { \
2369 if (TARGET_MIPS16) \
2370 sorry ("mips16 function profiling"); \
2371 if (TARGET_LONG_CALLS) \
2372 { \
2373 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */ \
2374 if (Pmode == DImode) \
2375 fprintf (FILE, "\tdla\t%s,_mcount\n", reg_names[GP_REG_FIRST + 3]); \
2376 else \
2377 fprintf (FILE, "\tla\t%s,_mcount\n", reg_names[GP_REG_FIRST + 3]); \
2378 } \
2379 mips_push_asm_switch (&mips_noat); \
2380 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2381 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2382 /* _mcount treats $2 as the static chain register. */ \
2383 if (cfun->static_chain_decl != NULL) \
2384 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[2], \
2385 reg_names[STATIC_CHAIN_REGNUM]); \
2386 if (!TARGET_NEWABI) \
2387 { \
2388 fprintf (FILE, \
2389 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2390 TARGET_64BIT ? "dsubu" : "subu", \
2391 reg_names[STACK_POINTER_REGNUM], \
2392 reg_names[STACK_POINTER_REGNUM], \
2393 Pmode == DImode ? 16 : 8); \
2394 } \
2395 if (TARGET_LONG_CALLS) \
2396 fprintf (FILE, "\tjalr\t%s\n", reg_names[GP_REG_FIRST + 3]); \
2397 else \
2398 fprintf (FILE, "\tjal\t_mcount\n"); \
2399 mips_pop_asm_switch (&mips_noat); \
2400 /* _mcount treats $2 as the static chain register. */ \
2401 if (cfun->static_chain_decl != NULL) \
2402 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], \
2403 reg_names[2]); \
2404 }
2405
2406 /* The profiler preserves all interesting registers, including $31. */
2407 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2408
2409 /* No mips port has ever used the profiler counter word, so don't emit it
2410 or the label for it. */
2411
2412 #define NO_PROFILE_COUNTERS 1
2413
2414 /* Define this macro if the code for function profiling should come
2415 before the function prologue. Normally, the profiling code comes
2416 after. */
2417
2418 /* #define PROFILE_BEFORE_PROLOGUE */
2419
2420 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2421 the stack pointer does not matter. The value is tested only in
2422 functions that have frame pointers.
2423 No definition is equivalent to always zero. */
2424
2425 #define EXIT_IGNORE_STACK 1
2426
2427 \f
2428 /* A C statement to output, on the stream FILE, assembler code for a
2429 block of data that contains the constant parts of a trampoline.
2430 This code should not include a label--the label is taken care of
2431 automatically. */
2432
2433 #define TRAMPOLINE_TEMPLATE(STREAM) \
2434 { \
2435 if (ptr_mode == DImode) \
2436 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2437 else \
2438 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2439 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2440 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2441 if (ptr_mode == DImode) \
2442 { \
2443 fprintf (STREAM, "\t.word\t0xdff90014\t\t# ld $25,20($31)\n"); \
2444 fprintf (STREAM, "\t.word\t0xdfef001c\t\t# ld $15,28($31)\n"); \
2445 } \
2446 else \
2447 { \
2448 fprintf (STREAM, "\t.word\t0x8ff90010\t\t# lw $25,16($31)\n"); \
2449 fprintf (STREAM, "\t.word\t0x8fef0014\t\t# lw $15,20($31)\n"); \
2450 } \
2451 fprintf (STREAM, "\t.word\t0x03200008\t\t# jr $25\n"); \
2452 if (ptr_mode == DImode) \
2453 { \
2454 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2455 fprintf (STREAM, "\t.word\t0x00000000\t\t# <padding>\n"); \
2456 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2457 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2458 } \
2459 else \
2460 { \
2461 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2462 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2463 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2464 } \
2465 }
2466
2467 /* A C expression for the size in bytes of the trampoline, as an
2468 integer. */
2469
2470 #define TRAMPOLINE_SIZE (ptr_mode == DImode ? 48 : 36)
2471
2472 /* Alignment required for trampolines, in bits. */
2473
2474 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2475
2476 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2477 program and data caches. */
2478
2479 #ifndef CACHE_FLUSH_FUNC
2480 #define CACHE_FLUSH_FUNC "_flush_cache"
2481 #endif
2482
2483 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2484 /* Flush both caches. We need to flush the data cache in case \
2485 the system has a write-back cache. */ \
2486 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2487 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2488 GEN_INT (3), TYPE_MODE (integer_type_node))
2489
2490 /* A C statement to initialize the variable parts of a trampoline.
2491 ADDR is an RTX for the address of the trampoline; FNADDR is an
2492 RTX for the address of the nested function; STATIC_CHAIN is an
2493 RTX for the static chain value that should be passed to the
2494 function when it is called. */
2495
2496 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2497 { \
2498 rtx func_addr, chain_addr, end_addr; \
2499 \
2500 func_addr = plus_constant (ADDR, ptr_mode == DImode ? 32 : 28); \
2501 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2502 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2503 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2504 end_addr = gen_reg_rtx (Pmode); \
2505 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2506 GEN_INT (TRAMPOLINE_SIZE))); \
2507 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2508 }
2509 \f
2510 /* Addressing modes, and classification of registers for them. */
2511
2512 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2513 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2514 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2515
2516 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2517 and check its validity for a certain class.
2518 We have two alternate definitions for each of them.
2519 The usual definition accepts all pseudo regs; the other rejects them all.
2520 The symbol REG_OK_STRICT causes the latter definition to be used.
2521
2522 Most source files want to accept pseudo regs in the hope that
2523 they will get allocated to the class that the insn wants them to be in.
2524 Some source files that are used after register allocation
2525 need to be strict. */
2526
2527 #ifndef REG_OK_STRICT
2528 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2529 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2530 #else
2531 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2532 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2533 #endif
2534
2535 #define REG_OK_FOR_INDEX_P(X) 0
2536
2537 \f
2538 /* Maximum number of registers that can appear in a valid memory address. */
2539
2540 #define MAX_REGS_PER_ADDRESS 1
2541
2542 /* Check for constness inline but use mips_legitimate_address_p
2543 to check whether a constant really is an address. */
2544
2545 #define CONSTANT_ADDRESS_P(X) \
2546 (CONSTANT_P (X) && memory_address_p (SImode, X))
2547
2548 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2549
2550 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2551 'the start of the function that this code is output in'. */
2552
2553 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2554 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2555 asm_fprintf ((FILE), "%U%s", \
2556 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2557 else \
2558 asm_fprintf ((FILE), "%U%s", (NAME))
2559 \f
2560 /* Flag to mark a function decl symbol that requires a long call. */
2561 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2562 #define SYMBOL_REF_LONG_CALL_P(X) \
2563 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2564
2565 /* This flag marks functions that cannot be lazily bound. */
2566 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2567 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2568 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2569
2570 /* True if we're generating a form of MIPS16 code in which jump tables
2571 are stored in the text section and encoded as 16-bit PC-relative
2572 offsets. This is only possible when general text loads are allowed,
2573 since the table access itself will be an "lh" instruction. */
2574 /* ??? 16-bit offsets can overflow in large functions. */
2575 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2576
2577 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2578
2579 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2580
2581 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2582
2583 /* Define this as 1 if `char' should by default be signed; else as 0. */
2584 #ifndef DEFAULT_SIGNED_CHAR
2585 #define DEFAULT_SIGNED_CHAR 1
2586 #endif
2587
2588 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2589 we generally don't want to use them for copying arbitrary data.
2590 A single N-word move is usually the same cost as N single-word moves. */
2591 #define MOVE_MAX UNITS_PER_WORD
2592 #define MAX_MOVE_MAX 8
2593
2594 /* Define this macro as a C expression which is nonzero if
2595 accessing less than a word of memory (i.e. a `char' or a
2596 `short') is no faster than accessing a word of memory, i.e., if
2597 such access require more than one instruction or if there is no
2598 difference in cost between byte and (aligned) word loads.
2599
2600 On RISC machines, it tends to generate better code to define
2601 this as 1, since it avoids making a QI or HI mode register.
2602
2603 But, generating word accesses for -mips16 is generally bad as shifts
2604 (often extended) would be needed for byte accesses. */
2605 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2606
2607 /* Define this to be nonzero if shift instructions ignore all but the low-order
2608 few bits. */
2609 #define SHIFT_COUNT_TRUNCATED 1
2610
2611 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2612 is done just by pretending it is already truncated. */
2613 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2614 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2615
2616
2617 /* Specify the machine mode that pointers have.
2618 After generation of rtl, the compiler makes no further distinction
2619 between pointers and any other objects of this machine mode. */
2620
2621 #ifndef Pmode
2622 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2623 #endif
2624
2625 /* Give call MEMs SImode since it is the "most permissive" mode
2626 for both 32-bit and 64-bit targets. */
2627
2628 #define FUNCTION_MODE SImode
2629
2630 \f
2631 /* A C expression for the cost of moving data from a register in
2632 class FROM to one in class TO. The classes are expressed using
2633 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2634 the default; other values are interpreted relative to that.
2635
2636 It is not required that the cost always equal 2 when FROM is the
2637 same as TO; on some machines it is expensive to move between
2638 registers if they are not general registers.
2639
2640 If reload sees an insn consisting of a single `set' between two
2641 hard registers, and if `REGISTER_MOVE_COST' applied to their
2642 classes returns a value of 2, reload does not check to ensure
2643 that the constraints of the insn are met. Setting a cost of
2644 other than 2 will allow reload to verify that the constraints are
2645 met. You should do this if the `movM' pattern's constraints do
2646 not allow such copying. */
2647
2648 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2649 mips_register_move_cost (MODE, FROM, TO)
2650
2651 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2652 (mips_cost->memory_latency \
2653 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2654
2655 /* Define if copies to/from condition code registers should be avoided.
2656
2657 This is needed for the MIPS because reload_outcc is not complete;
2658 it needs to handle cases where the source is a general or another
2659 condition code register. */
2660 #define AVOID_CCMODE_COPIES
2661
2662 /* A C expression for the cost of a branch instruction. A value of
2663 1 is the default; other values are interpreted relative to that. */
2664
2665 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2666 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2667
2668 /* If defined, modifies the length assigned to instruction INSN as a
2669 function of the context in which it is used. LENGTH is an lvalue
2670 that contains the initially computed length of the insn and should
2671 be updated with the correct length of the insn. */
2672 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2673 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2674
2675 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2676 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2677 its operands. */
2678 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2679 "%*" OPCODE "%?\t" OPERANDS "%/"
2680
2681 /* Return an asm string that forces INSN to be treated as an absolute
2682 J or JAL instruction instead of an assembler macro. */
2683 #define MIPS_ABSOLUTE_JUMP(INSN) \
2684 (TARGET_ABICALLS_PIC2 \
2685 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2686 : INSN)
2687
2688 /* Return the asm template for a call. INSN is the instruction's mnemonic
2689 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2690 of the target.
2691
2692 When generating GOT code without explicit relocation operators,
2693 all calls should use assembly macros. Otherwise, all indirect
2694 calls should use "jr" or "jalr"; we will arrange to restore $gp
2695 afterwards if necessary. Finally, we can only generate direct
2696 calls for -mabicalls by temporarily switching to non-PIC mode. */
2697 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2698 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2699 ? "%*" INSN "\t%" #OPNO "%/" \
2700 : REG_P (OPERANDS[OPNO]) \
2701 ? "%*" INSN "r\t%" #OPNO "%/" \
2702 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2703 \f
2704 /* Control the assembler format that we output. */
2705
2706 /* Output to assembler file text saying following lines
2707 may contain character constants, extra white space, comments, etc. */
2708
2709 #ifndef ASM_APP_ON
2710 #define ASM_APP_ON " #APP\n"
2711 #endif
2712
2713 /* Output to assembler file text saying following lines
2714 no longer contain unusual constructs. */
2715
2716 #ifndef ASM_APP_OFF
2717 #define ASM_APP_OFF " #NO_APP\n"
2718 #endif
2719
2720 #define REGISTER_NAMES \
2721 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2722 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2723 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2724 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2725 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2726 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2727 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2728 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2729 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2730 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2731 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2732 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2733 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2734 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2735 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2736 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2737 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2738 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2739 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2740 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2741 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2742 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2743 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2744 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2745
2746 /* List the "software" names for each register. Also list the numerical
2747 names for $fp and $sp. */
2748
2749 #define ADDITIONAL_REGISTER_NAMES \
2750 { \
2751 { "$29", 29 + GP_REG_FIRST }, \
2752 { "$30", 30 + GP_REG_FIRST }, \
2753 { "at", 1 + GP_REG_FIRST }, \
2754 { "v0", 2 + GP_REG_FIRST }, \
2755 { "v1", 3 + GP_REG_FIRST }, \
2756 { "a0", 4 + GP_REG_FIRST }, \
2757 { "a1", 5 + GP_REG_FIRST }, \
2758 { "a2", 6 + GP_REG_FIRST }, \
2759 { "a3", 7 + GP_REG_FIRST }, \
2760 { "t0", 8 + GP_REG_FIRST }, \
2761 { "t1", 9 + GP_REG_FIRST }, \
2762 { "t2", 10 + GP_REG_FIRST }, \
2763 { "t3", 11 + GP_REG_FIRST }, \
2764 { "t4", 12 + GP_REG_FIRST }, \
2765 { "t5", 13 + GP_REG_FIRST }, \
2766 { "t6", 14 + GP_REG_FIRST }, \
2767 { "t7", 15 + GP_REG_FIRST }, \
2768 { "s0", 16 + GP_REG_FIRST }, \
2769 { "s1", 17 + GP_REG_FIRST }, \
2770 { "s2", 18 + GP_REG_FIRST }, \
2771 { "s3", 19 + GP_REG_FIRST }, \
2772 { "s4", 20 + GP_REG_FIRST }, \
2773 { "s5", 21 + GP_REG_FIRST }, \
2774 { "s6", 22 + GP_REG_FIRST }, \
2775 { "s7", 23 + GP_REG_FIRST }, \
2776 { "t8", 24 + GP_REG_FIRST }, \
2777 { "t9", 25 + GP_REG_FIRST }, \
2778 { "k0", 26 + GP_REG_FIRST }, \
2779 { "k1", 27 + GP_REG_FIRST }, \
2780 { "gp", 28 + GP_REG_FIRST }, \
2781 { "sp", 29 + GP_REG_FIRST }, \
2782 { "fp", 30 + GP_REG_FIRST }, \
2783 { "ra", 31 + GP_REG_FIRST }, \
2784 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2785 }
2786
2787 /* This is meant to be redefined in the host dependent files. It is a
2788 set of alternative names and regnums for mips coprocessors. */
2789
2790 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2791
2792 #define PRINT_OPERAND mips_print_operand
2793 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2794 #define PRINT_OPERAND_ADDRESS mips_print_operand_address
2795
2796 #define DBR_OUTPUT_SEQEND(STREAM) \
2797 do \
2798 { \
2799 /* Undo the effect of '%*'. */ \
2800 mips_pop_asm_switch (&mips_nomacro); \
2801 mips_pop_asm_switch (&mips_noreorder); \
2802 /* Emit a blank line after the delay slot for emphasis. */ \
2803 fputs ("\n", STREAM); \
2804 } \
2805 while (0)
2806
2807 /* How to tell the debugger about changes of source files. */
2808 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
2809
2810 /* mips-tfile does not understand .stabd directives. */
2811 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2812 dbxout_begin_stabn_sline (LINE); \
2813 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2814 } while (0)
2815
2816 /* Use .loc directives for SDB line numbers. */
2817 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2818 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2819
2820 /* The MIPS implementation uses some labels for its own purpose. The
2821 following lists what labels are created, and are all formed by the
2822 pattern $L[a-z].*. The machine independent portion of GCC creates
2823 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2824
2825 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2826 $Lb[0-9]+ Begin blocks for MIPS debug support
2827 $Lc[0-9]+ Label for use in s<xx> operation.
2828 $Le[0-9]+ End blocks for MIPS debug support */
2829
2830 #undef ASM_DECLARE_OBJECT_NAME
2831 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2832 mips_declare_object (STREAM, NAME, "", ":\n")
2833
2834 /* Globalizing directive for a label. */
2835 #define GLOBAL_ASM_OP "\t.globl\t"
2836
2837 /* This says how to define a global common symbol. */
2838
2839 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2840
2841 /* This says how to define a local common symbol (i.e., not visible to
2842 linker). */
2843
2844 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2845 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2846 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2847 #endif
2848
2849 /* This says how to output an external. It would be possible not to
2850 output anything and let undefined symbol become external. However
2851 the assembler uses length information on externals to allocate in
2852 data/sdata bss/sbss, thereby saving exec time. */
2853
2854 #undef ASM_OUTPUT_EXTERNAL
2855 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2856 mips_output_external(STREAM,DECL,NAME)
2857
2858 /* This is how to declare a function name. The actual work of
2859 emitting the label is moved to function_prologue, so that we can
2860 get the line number correctly emitted before the .ent directive,
2861 and after any .file directives. Define as empty so that the function
2862 is not declared before the .ent directive elsewhere. */
2863
2864 #undef ASM_DECLARE_FUNCTION_NAME
2865 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2866
2867 /* This is how to store into the string LABEL
2868 the symbol_ref name of an internal numbered label where
2869 PREFIX is the class of label and NUM is the number within the class.
2870 This is suitable for output with `assemble_name'. */
2871
2872 #undef ASM_GENERATE_INTERNAL_LABEL
2873 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2874 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2875
2876 /* Print debug labels as "foo = ." rather than "foo:" because they should
2877 represent a byte pointer rather than an ISA-encoded address. This is
2878 particularly important for code like:
2879
2880 $LFBxxx = .
2881 .cfi_startproc
2882 ...
2883 .section .gcc_except_table,...
2884 ...
2885 .uleb128 foo-$LFBxxx
2886
2887 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2888 likewise a byte pointer rather than an ISA-encoded address.
2889
2890 At the time of writing, this hook is not used for the function end
2891 label:
2892
2893 $LFExxx:
2894 .end foo
2895
2896 But this doesn't matter, because GAS doesn't treat a pre-.end label
2897 as a MIPS16 one anyway. */
2898
2899 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2900 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2901
2902 /* This is how to output an element of a case-vector that is absolute. */
2903
2904 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2905 fprintf (STREAM, "\t%s\t%sL%d\n", \
2906 ptr_mode == DImode ? ".dword" : ".word", \
2907 LOCAL_LABEL_PREFIX, \
2908 VALUE)
2909
2910 /* This is how to output an element of a case-vector. We can make the
2911 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2912 is supported. */
2913
2914 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2915 do { \
2916 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2917 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2918 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2919 else if (TARGET_GPWORD) \
2920 fprintf (STREAM, "\t%s\t%sL%d\n", \
2921 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2922 LOCAL_LABEL_PREFIX, VALUE); \
2923 else if (TARGET_RTP_PIC) \
2924 { \
2925 /* Make the entry relative to the start of the function. */ \
2926 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2927 fprintf (STREAM, "\t%s\t%sL%d-", \
2928 Pmode == DImode ? ".dword" : ".word", \
2929 LOCAL_LABEL_PREFIX, VALUE); \
2930 assemble_name (STREAM, XSTR (fnsym, 0)); \
2931 fprintf (STREAM, "\n"); \
2932 } \
2933 else \
2934 fprintf (STREAM, "\t%s\t%sL%d\n", \
2935 ptr_mode == DImode ? ".dword" : ".word", \
2936 LOCAL_LABEL_PREFIX, VALUE); \
2937 } while (0)
2938
2939 /* This is how to output an assembler line
2940 that says to advance the location counter
2941 to a multiple of 2**LOG bytes. */
2942
2943 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2944 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2945
2946 /* This is how to output an assembler line to advance the location
2947 counter by SIZE bytes. */
2948
2949 #undef ASM_OUTPUT_SKIP
2950 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2951 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2952
2953 /* This is how to output a string. */
2954 #undef ASM_OUTPUT_ASCII
2955 #define ASM_OUTPUT_ASCII mips_output_ascii
2956
2957 /* Output #ident as a in the read-only data section. */
2958 #undef ASM_OUTPUT_IDENT
2959 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2960 { \
2961 const char *p = STRING; \
2962 int size = strlen (p) + 1; \
2963 switch_to_section (readonly_data_section); \
2964 assemble_string (p, size); \
2965 }
2966 \f
2967 /* Default to -G 8 */
2968 #ifndef MIPS_DEFAULT_GVALUE
2969 #define MIPS_DEFAULT_GVALUE 8
2970 #endif
2971
2972 /* Define the strings to put out for each section in the object file. */
2973 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2974 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2975
2976 #undef READONLY_DATA_SECTION_ASM_OP
2977 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2978 \f
2979 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2980 do \
2981 { \
2982 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2983 TARGET_64BIT ? "daddiu" : "addiu", \
2984 reg_names[STACK_POINTER_REGNUM], \
2985 reg_names[STACK_POINTER_REGNUM], \
2986 TARGET_64BIT ? "sd" : "sw", \
2987 reg_names[REGNO], \
2988 reg_names[STACK_POINTER_REGNUM]); \
2989 } \
2990 while (0)
2991
2992 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2993 do \
2994 { \
2995 mips_push_asm_switch (&mips_noreorder); \
2996 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2997 TARGET_64BIT ? "ld" : "lw", \
2998 reg_names[REGNO], \
2999 reg_names[STACK_POINTER_REGNUM], \
3000 TARGET_64BIT ? "daddu" : "addu", \
3001 reg_names[STACK_POINTER_REGNUM], \
3002 reg_names[STACK_POINTER_REGNUM]); \
3003 mips_pop_asm_switch (&mips_noreorder); \
3004 } \
3005 while (0)
3006
3007 /* How to start an assembler comment.
3008 The leading space is important (the mips native assembler requires it). */
3009 #ifndef ASM_COMMENT_START
3010 #define ASM_COMMENT_START " #"
3011 #endif
3012 \f
3013 /* Default definitions for size_t and ptrdiff_t. We must override the
3014 definitions from ../svr4.h on mips-*-linux-gnu. */
3015
3016 #undef SIZE_TYPE
3017 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3018
3019 #undef PTRDIFF_TYPE
3020 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3021
3022 /* The maximum number of bytes that can be copied by one iteration of
3023 a movmemsi loop; see mips_block_move_loop. */
3024 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
3025 (UNITS_PER_WORD * 4)
3026
3027 /* The maximum number of bytes that can be copied by a straight-line
3028 implementation of movmemsi; see mips_block_move_straight. We want
3029 to make sure that any loop-based implementation will iterate at
3030 least twice. */
3031 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
3032 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
3033
3034 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
3035 values were determined experimentally by benchmarking with CSiBE.
3036 In theory, the call overhead is higher for TARGET_ABICALLS (especially
3037 for o32 where we have to restore $gp afterwards as well as make an
3038 indirect call), but in practice, bumping this up higher for
3039 TARGET_ABICALLS doesn't make much difference to code size. */
3040
3041 #define MIPS_CALL_RATIO 8
3042
3043 /* Any loop-based implementation of movmemsi will have at least
3044 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
3045 moves, so allow individual copies of fewer elements.
3046
3047 When movmemsi is not available, use a value approximating
3048 the length of a memcpy call sequence, so that move_by_pieces
3049 will generate inline code if it is shorter than a function call.
3050 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3051 we'll have to generate a load/store pair for each, halve the
3052 value of MIPS_CALL_RATIO to take that into account. */
3053
3054 #define MOVE_RATIO(speed) \
3055 (HAVE_movmemsi \
3056 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3057 : MIPS_CALL_RATIO / 2)
3058
3059 /* movmemsi is meant to generate code that is at least as good as
3060 move_by_pieces. However, movmemsi effectively uses a by-pieces
3061 implementation both for moves smaller than a word and for word-aligned
3062 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
3063 allow the tree-level optimisers to do such moves by pieces, as it
3064 often exposes other optimization opportunities. We might as well
3065 continue to use movmemsi at the rtl level though, as it produces
3066 better code when scheduling is disabled (such as at -O). */
3067
3068 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
3069 (HAVE_movmemsi \
3070 ? (!currently_expanding_to_rtl \
3071 && ((ALIGN) < BITS_PER_WORD \
3072 ? (SIZE) < UNITS_PER_WORD \
3073 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
3074 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
3075 < (unsigned int) MOVE_RATIO (false)))
3076
3077 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
3078 of the length of a memset call, but use the default otherwise. */
3079
3080 #define CLEAR_RATIO(speed)\
3081 ((speed) ? 15 : MIPS_CALL_RATIO)
3082
3083 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3084 optimizing for size adjust the ratio to account for the overhead of
3085 loading the constant and replicating it across the word. */
3086
3087 #define SET_RATIO(speed) \
3088 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3089
3090 /* STORE_BY_PIECES_P can be used when copying a constant string, but
3091 in that case each word takes 3 insns (lui, ori, sw), or more in
3092 64-bit mode, instead of 2 (lw, sw). For now we always fail this
3093 and let the move_by_pieces code copy the string from read-only
3094 memory. In the future, this could be tuned further for multi-issue
3095 CPUs that can issue stores down one pipe and arithmetic instructions
3096 down another; in that case, the lui/ori/sw combination would be a
3097 win for long enough strings. */
3098
3099 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
3100 \f
3101 #ifndef __mips16
3102 /* Since the bits of the _init and _fini function is spread across
3103 many object files, each potentially with its own GP, we must assume
3104 we need to load our GP. We don't preserve $gp or $ra, since each
3105 init/fini chunk is supposed to initialize $gp, and crti/crtn
3106 already take care of preserving $ra and, when appropriate, $gp. */
3107 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3108 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3109 asm (SECTION_OP "\n\
3110 .set noreorder\n\
3111 bal 1f\n\
3112 nop\n\
3113 1: .cpload $31\n\
3114 .set reorder\n\
3115 jal " USER_LABEL_PREFIX #FUNC "\n\
3116 " TEXT_SECTION_ASM_OP);
3117 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3118 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3119 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3120 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3121 asm (SECTION_OP "\n\
3122 .set noreorder\n\
3123 bal 1f\n\
3124 nop\n\
3125 1: .set reorder\n\
3126 .cpsetup $31, $2, 1b\n\
3127 jal " USER_LABEL_PREFIX #FUNC "\n\
3128 " TEXT_SECTION_ASM_OP);
3129 #endif
3130 #endif
3131
3132 #ifndef HAVE_AS_TLS
3133 #define HAVE_AS_TLS 0
3134 #endif
3135
3136 #ifndef USED_FOR_TARGET
3137 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3138 struct mips_asm_switch {
3139 /* The FOO in the description above. */
3140 const char *name;
3141
3142 /* The current block nesting level, or 0 if we aren't in a block. */
3143 int nesting_level;
3144 };
3145
3146 extern const enum reg_class mips_regno_to_class[];
3147 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3148 extern bool mips_print_operand_punct[256];
3149 extern const char *current_function_file; /* filename current function is in */
3150 extern int num_source_filenames; /* current .file # */
3151 extern struct mips_asm_switch mips_noreorder;
3152 extern struct mips_asm_switch mips_nomacro;
3153 extern struct mips_asm_switch mips_noat;
3154 extern int mips_dbx_regno[];
3155 extern int mips_dwarf_regno[];
3156 extern bool mips_split_p[];
3157 extern bool mips_split_hi_p[];
3158 extern enum processor_type mips_arch; /* which cpu to codegen for */
3159 extern enum processor_type mips_tune; /* which cpu to schedule for */
3160 extern int mips_isa; /* architectural level */
3161 extern int mips_abi; /* which ABI to use */
3162 extern const struct mips_cpu_info *mips_arch_info;
3163 extern const struct mips_cpu_info *mips_tune_info;
3164 extern const struct mips_rtx_cost_data *mips_cost;
3165 extern bool mips_base_mips16;
3166 extern enum mips_code_readable_setting mips_code_readable;
3167 #endif
3168
3169 /* Enable querying of DFA units. */
3170 #define CPU_UNITS_QUERY 1
3171
3172 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3173 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3174
3175 /* This is necessary to avoid a warning about comparing different enum
3176 types. */
3177 #define mips_tune_attr ((enum attr_cpu) mips_tune)