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[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF,
45 PROCESSOR_24KX,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF,
48 PROCESSOR_74KX,
49 PROCESSOR_M4K,
50 PROCESSOR_R3900,
51 PROCESSOR_R6000,
52 PROCESSOR_R4000,
53 PROCESSOR_R4100,
54 PROCESSOR_R4111,
55 PROCESSOR_R4120,
56 PROCESSOR_R4130,
57 PROCESSOR_R4300,
58 PROCESSOR_R4600,
59 PROCESSOR_R4650,
60 PROCESSOR_R5000,
61 PROCESSOR_R5400,
62 PROCESSOR_R5500,
63 PROCESSOR_R7000,
64 PROCESSOR_R8000,
65 PROCESSOR_R9000,
66 PROCESSOR_SB1,
67 PROCESSOR_SB1A,
68 PROCESSOR_SR71000,
69 PROCESSOR_MAX
70 };
71
72 /* Costs of various operations on the different architectures. */
73
74 struct mips_rtx_cost_data
75 {
76 unsigned short fp_add;
77 unsigned short fp_mult_sf;
78 unsigned short fp_mult_df;
79 unsigned short fp_div_sf;
80 unsigned short fp_div_df;
81 unsigned short int_mult_si;
82 unsigned short int_mult_di;
83 unsigned short int_div_si;
84 unsigned short int_div_di;
85 unsigned short branch_cost;
86 unsigned short memory_latency;
87 };
88
89 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
90 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
91 to work on a 64-bit machine. */
92
93 #define ABI_32 0
94 #define ABI_N32 1
95 #define ABI_64 2
96 #define ABI_EABI 3
97 #define ABI_O64 4
98
99 /* Information about one recognized processor. Defined here for the
100 benefit of TARGET_CPU_CPP_BUILTINS. */
101 struct mips_cpu_info {
102 /* The 'canonical' name of the processor as far as GCC is concerned.
103 It's typically a manufacturer's prefix followed by a numerical
104 designation. It should be lowercase. */
105 const char *name;
106
107 /* The internal processor number that most closely matches this
108 entry. Several processors can have the same value, if there's no
109 difference between them from GCC's point of view. */
110 enum processor_type cpu;
111
112 /* The ISA level that the processor implements. */
113 int isa;
114 };
115
116 #ifndef USED_FOR_TARGET
117 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
118 extern const char *current_function_file; /* filename current function is in */
119 extern int num_source_filenames; /* current .file # */
120 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
121 extern int sym_lineno; /* sgi next label # for each stmt */
122 extern int set_noreorder; /* # of nested .set noreorder's */
123 extern int set_nomacro; /* # of nested .set nomacro's */
124 extern int set_noat; /* # of nested .set noat's */
125 extern int set_volatile; /* # of nested .set volatile's */
126 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
127 extern int mips_dbx_regno[]; /* Map register # to debug register # */
128 extern bool mips_split_p[];
129 extern GTY(()) rtx cmp_operands[2];
130 extern enum processor_type mips_arch; /* which cpu to codegen for */
131 extern enum processor_type mips_tune; /* which cpu to schedule for */
132 extern int mips_isa; /* architectural level */
133 extern int mips_abi; /* which ABI to use */
134 extern int mips16_hard_float; /* mips16 without -msoft-float */
135 extern const struct mips_cpu_info mips_cpu_info_table[];
136 extern const struct mips_cpu_info *mips_arch_info;
137 extern const struct mips_cpu_info *mips_tune_info;
138 extern const struct mips_rtx_cost_data *mips_cost;
139 #endif
140
141 /* Macros to silence warnings about numbers being signed in traditional
142 C and unsigned in ISO C when compiled on 32-bit hosts. */
143
144 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
145 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
146 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
147
148 \f
149 /* Run-time compilation parameters selecting different hardware subsets. */
150
151 /* True if we are generating position-independent VxWorks RTP code. */
152 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
153
154 /* True if the call patterns should be split into a jalr followed by
155 an instruction to restore $gp. It is only safe to split the load
156 from the call when every use of $gp is explicit. */
157
158 #define TARGET_SPLIT_CALLS \
159 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
160
161 /* True if we're generating a form of -mabicalls in which we can use
162 operators like %hi and %lo to refer to locally-binding symbols.
163 We can only do this for -mno-shared, and only then if we can use
164 relocation operations instead of assembly macros. It isn't really
165 worth using absolute sequences for 64-bit symbols because GOT
166 accesses are so much shorter. */
167
168 #define TARGET_ABSOLUTE_ABICALLS \
169 (TARGET_ABICALLS \
170 && !TARGET_SHARED \
171 && TARGET_EXPLICIT_RELOCS \
172 && !ABI_HAS_64BIT_SYMBOLS)
173
174 /* True if we can optimize sibling calls. For simplicity, we only
175 handle cases in which call_insn_operand will reject invalid
176 sibcall addresses. There are two cases in which this isn't true:
177
178 - TARGET_MIPS16. call_insn_operand accepts constant addresses
179 but there is no direct jump instruction. It isn't worth
180 using sibling calls in this case anyway; they would usually
181 be longer than normal calls.
182
183 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
184 accepts global constants, but all sibcalls must be indirect. */
185 #define TARGET_SIBCALLS \
186 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
187
188 /* True if we need to use a global offset table to access some symbols. */
189 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
190
191 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
192 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
193
194 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
195 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
196
197 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
198 This is true for both the PIC and non-PIC VxWorks RTP modes. */
199 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
200
201 /* True if .gpword or .gpdword should be used for switch tables.
202
203 Although GAS does understand .gpdword, the SGI linker mishandles
204 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
205 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
206 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
207
208 /* Generate mips16 code */
209 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
210 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
211 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
212
213 /* Generic ISA defines. */
214 #define ISA_MIPS1 (mips_isa == 1)
215 #define ISA_MIPS2 (mips_isa == 2)
216 #define ISA_MIPS3 (mips_isa == 3)
217 #define ISA_MIPS4 (mips_isa == 4)
218 #define ISA_MIPS32 (mips_isa == 32)
219 #define ISA_MIPS32R2 (mips_isa == 33)
220 #define ISA_MIPS64 (mips_isa == 64)
221
222 /* Architecture target defines. */
223 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
224 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
225 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
226 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
227 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
228 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
229 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
230 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
231 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
232 || mips_arch == PROCESSOR_SB1A)
233 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
234
235 /* Scheduling target defines. */
236 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
237 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
238 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
239 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
240 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
241 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
242 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
243 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
244 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
245 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
246 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
247 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
248 || mips_tune == PROCESSOR_SB1A)
249 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
250 || mips_tune == PROCESSOR_74KF \
251 || mips_tune == PROCESSOR_74KX)
252
253 /* True if the pre-reload scheduler should try to create chains of
254 multiply-add or multiply-subtract instructions. For example,
255 suppose we have:
256
257 t1 = a * b
258 t2 = t1 + c * d
259 t3 = e * f
260 t4 = t3 - g * h
261
262 t1 will have a higher priority than t2 and t3 will have a higher
263 priority than t4. However, before reload, there is no dependence
264 between t1 and t3, and they can often have similar priorities.
265 The scheduler will then tend to prefer:
266
267 t1 = a * b
268 t3 = e * f
269 t2 = t1 + c * d
270 t4 = t3 - g * h
271
272 which stops us from making full use of macc/madd-style instructions.
273 This sort of situation occurs frequently in Fourier transforms and
274 in unrolled loops.
275
276 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
277 queue so that chained multiply-add and multiply-subtract instructions
278 appear ahead of any other instruction that is likely to clobber lo.
279 In the example above, if t2 and t3 become ready at the same time,
280 the code ensures that t2 is scheduled first.
281
282 Multiply-accumulate instructions are a bigger win for some targets
283 than others, so this macro is defined on an opt-in basis. */
284 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
285 || TUNE_MIPS4120 \
286 || TUNE_MIPS4130)
287
288 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
289 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
290
291 /* IRIX specific stuff. */
292 #define TARGET_IRIX 0
293 #define TARGET_IRIX6 0
294
295 /* Define preprocessor macros for the -march and -mtune options.
296 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
297 processor. If INFO's canonical name is "foo", define PREFIX to
298 be "foo", and define an additional macro PREFIX_FOO. */
299 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
300 do \
301 { \
302 char *macro, *p; \
303 \
304 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
305 for (p = macro; *p != 0; p++) \
306 *p = TOUPPER (*p); \
307 \
308 builtin_define (macro); \
309 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
310 free (macro); \
311 } \
312 while (0)
313
314 /* Target CPU builtins. */
315 #define TARGET_CPU_CPP_BUILTINS() \
316 do \
317 { \
318 /* Everyone but IRIX defines this to mips. */ \
319 if (!TARGET_IRIX) \
320 builtin_assert ("machine=mips"); \
321 \
322 builtin_assert ("cpu=mips"); \
323 builtin_define ("__mips__"); \
324 builtin_define ("_mips"); \
325 \
326 /* We do this here because __mips is defined below \
327 and so we can't use builtin_define_std. */ \
328 if (!flag_iso) \
329 builtin_define ("mips"); \
330 \
331 if (TARGET_64BIT) \
332 builtin_define ("__mips64"); \
333 \
334 if (!TARGET_IRIX) \
335 { \
336 /* Treat _R3000 and _R4000 like register-size \
337 defines, which is how they've historically \
338 been used. */ \
339 if (TARGET_64BIT) \
340 { \
341 builtin_define_std ("R4000"); \
342 builtin_define ("_R4000"); \
343 } \
344 else \
345 { \
346 builtin_define_std ("R3000"); \
347 builtin_define ("_R3000"); \
348 } \
349 } \
350 if (TARGET_FLOAT64) \
351 builtin_define ("__mips_fpr=64"); \
352 else \
353 builtin_define ("__mips_fpr=32"); \
354 \
355 if (TARGET_MIPS16) \
356 builtin_define ("__mips16"); \
357 \
358 if (TARGET_MIPS3D) \
359 builtin_define ("__mips3d"); \
360 \
361 if (TARGET_DSP) \
362 builtin_define ("__mips_dsp"); \
363 \
364 if (TARGET_DSPR2) \
365 builtin_define ("__mips_dspr2"); \
366 \
367 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
368 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
369 \
370 if (ISA_MIPS1) \
371 { \
372 builtin_define ("__mips=1"); \
373 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
374 } \
375 else if (ISA_MIPS2) \
376 { \
377 builtin_define ("__mips=2"); \
378 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
379 } \
380 else if (ISA_MIPS3) \
381 { \
382 builtin_define ("__mips=3"); \
383 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
384 } \
385 else if (ISA_MIPS4) \
386 { \
387 builtin_define ("__mips=4"); \
388 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
389 } \
390 else if (ISA_MIPS32) \
391 { \
392 builtin_define ("__mips=32"); \
393 builtin_define ("__mips_isa_rev=1"); \
394 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
395 } \
396 else if (ISA_MIPS32R2) \
397 { \
398 builtin_define ("__mips=32"); \
399 builtin_define ("__mips_isa_rev=2"); \
400 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
401 } \
402 else if (ISA_MIPS64) \
403 { \
404 builtin_define ("__mips=64"); \
405 builtin_define ("__mips_isa_rev=1"); \
406 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
407 } \
408 \
409 if (TARGET_HARD_FLOAT) \
410 builtin_define ("__mips_hard_float"); \
411 else if (TARGET_SOFT_FLOAT) \
412 builtin_define ("__mips_soft_float"); \
413 \
414 if (TARGET_SINGLE_FLOAT) \
415 builtin_define ("__mips_single_float"); \
416 \
417 if (TARGET_PAIRED_SINGLE_FLOAT) \
418 builtin_define ("__mips_paired_single_float"); \
419 \
420 if (TARGET_BIG_ENDIAN) \
421 { \
422 builtin_define_std ("MIPSEB"); \
423 builtin_define ("_MIPSEB"); \
424 } \
425 else \
426 { \
427 builtin_define_std ("MIPSEL"); \
428 builtin_define ("_MIPSEL"); \
429 } \
430 \
431 /* Macros dependent on the C dialect. */ \
432 if (preprocessing_asm_p ()) \
433 { \
434 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
435 builtin_define ("_LANGUAGE_ASSEMBLY"); \
436 } \
437 else if (c_dialect_cxx ()) \
438 { \
439 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
440 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
441 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
442 } \
443 else \
444 { \
445 builtin_define_std ("LANGUAGE_C"); \
446 builtin_define ("_LANGUAGE_C"); \
447 } \
448 if (c_dialect_objc ()) \
449 { \
450 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
451 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
452 /* Bizarre, but needed at least for Irix. */ \
453 builtin_define_std ("LANGUAGE_C"); \
454 builtin_define ("_LANGUAGE_C"); \
455 } \
456 \
457 if (mips_abi == ABI_EABI) \
458 builtin_define ("__mips_eabi"); \
459 \
460 } while (0)
461
462 /* Default target_flags if no switches are specified */
463
464 #ifndef TARGET_DEFAULT
465 #define TARGET_DEFAULT 0
466 #endif
467
468 #ifndef TARGET_CPU_DEFAULT
469 #define TARGET_CPU_DEFAULT 0
470 #endif
471
472 #ifndef TARGET_ENDIAN_DEFAULT
473 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
474 #endif
475
476 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
477 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
478 #endif
479
480 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
481 #ifndef MIPS_ISA_DEFAULT
482 #ifndef MIPS_CPU_STRING_DEFAULT
483 #define MIPS_CPU_STRING_DEFAULT "from-abi"
484 #endif
485 #endif
486
487 #ifdef IN_LIBGCC2
488 #undef TARGET_64BIT
489 /* Make this compile time constant for libgcc2 */
490 #ifdef __mips64
491 #define TARGET_64BIT 1
492 #else
493 #define TARGET_64BIT 0
494 #endif
495 #endif /* IN_LIBGCC2 */
496
497 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
498
499 #ifndef MULTILIB_ENDIAN_DEFAULT
500 #if TARGET_ENDIAN_DEFAULT == 0
501 #define MULTILIB_ENDIAN_DEFAULT "EL"
502 #else
503 #define MULTILIB_ENDIAN_DEFAULT "EB"
504 #endif
505 #endif
506
507 #ifndef MULTILIB_ISA_DEFAULT
508 # if MIPS_ISA_DEFAULT == 1
509 # define MULTILIB_ISA_DEFAULT "mips1"
510 # else
511 # if MIPS_ISA_DEFAULT == 2
512 # define MULTILIB_ISA_DEFAULT "mips2"
513 # else
514 # if MIPS_ISA_DEFAULT == 3
515 # define MULTILIB_ISA_DEFAULT "mips3"
516 # else
517 # if MIPS_ISA_DEFAULT == 4
518 # define MULTILIB_ISA_DEFAULT "mips4"
519 # else
520 # if MIPS_ISA_DEFAULT == 32
521 # define MULTILIB_ISA_DEFAULT "mips32"
522 # else
523 # if MIPS_ISA_DEFAULT == 33
524 # define MULTILIB_ISA_DEFAULT "mips32r2"
525 # else
526 # if MIPS_ISA_DEFAULT == 64
527 # define MULTILIB_ISA_DEFAULT "mips64"
528 # else
529 # define MULTILIB_ISA_DEFAULT "mips1"
530 # endif
531 # endif
532 # endif
533 # endif
534 # endif
535 # endif
536 # endif
537 #endif
538
539 #ifndef MULTILIB_DEFAULTS
540 #define MULTILIB_DEFAULTS \
541 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
542 #endif
543
544 /* We must pass -EL to the linker by default for little endian embedded
545 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
546 linker will default to using big-endian output files. The OUTPUT_FORMAT
547 line must be in the linker script, otherwise -EB/-EL will not work. */
548
549 #ifndef ENDIAN_SPEC
550 #if TARGET_ENDIAN_DEFAULT == 0
551 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
552 #else
553 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
554 #endif
555 #endif
556
557 /* Support for a compile-time default CPU, et cetera. The rules are:
558 --with-arch is ignored if -march is specified or a -mips is specified
559 (other than -mips16).
560 --with-tune is ignored if -mtune is specified.
561 --with-abi is ignored if -mabi is specified.
562 --with-float is ignored if -mhard-float or -msoft-float are
563 specified.
564 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
565 specified. */
566 #define OPTION_DEFAULT_SPECS \
567 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
568 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
569 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
570 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
571 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
572
573
574 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
575 && ISA_HAS_COND_TRAP)
576
577 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
578 && !TARGET_SR71K \
579 && !TARGET_MIPS16)
580
581 /* True if the ABI can only work with 64-bit integer registers. We
582 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
583 otherwise floating-point registers must also be 64-bit. */
584 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
585
586 /* Likewise for 32-bit regs. */
587 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
588
589 /* True if symbols are 64 bits wide. At present, n64 is the only
590 ABI for which this is true. */
591 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
592
593 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
594 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
595 || ISA_MIPS4 \
596 || ISA_MIPS64)
597
598 /* ISA has branch likely instructions (e.g. mips2). */
599 /* Disable branchlikely for tx39 until compare rewrite. They haven't
600 been generated up to this point. */
601 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
602
603 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
604 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
605 || TARGET_MIPS5400 \
606 || TARGET_MIPS5500 \
607 || TARGET_MIPS7000 \
608 || TARGET_MIPS9000 \
609 || TARGET_MAD \
610 || ISA_MIPS32 \
611 || ISA_MIPS32R2 \
612 || ISA_MIPS64) \
613 && !TARGET_MIPS16)
614
615 /* ISA has the conditional move instructions introduced in mips4. */
616 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
617 || ISA_MIPS32 \
618 || ISA_MIPS32R2 \
619 || ISA_MIPS64) \
620 && !TARGET_MIPS5500 \
621 && !TARGET_MIPS16)
622
623 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
624 branch on CC, and move (both FP and non-FP) on CC. */
625 #define ISA_HAS_8CC (ISA_MIPS4 \
626 || ISA_MIPS32 \
627 || ISA_MIPS32R2 \
628 || ISA_MIPS64)
629
630 /* This is a catch all for other mips4 instructions: indexed load, the
631 FP madd and msub instructions, and the FP recip and recip sqrt
632 instructions. */
633 #define ISA_HAS_FP4 ((ISA_MIPS4 \
634 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
635 || ISA_MIPS64) \
636 && !TARGET_MIPS16)
637
638 /* ISA has conditional trap instructions. */
639 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
640 && !TARGET_MIPS16)
641
642 /* ISA has integer multiply-accumulate instructions, madd and msub. */
643 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
644 || ISA_MIPS32R2 \
645 || ISA_MIPS64) \
646 && !TARGET_MIPS16)
647
648 /* Integer multiply-accumulate instructions should be generated. */
649 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
650
651 /* ISA has floating-point nmadd and nmsub instructions. */
652 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
653 || ISA_MIPS64) \
654 && (!TARGET_MIPS5400 || TARGET_MAD) \
655 && !TARGET_MIPS16)
656
657 /* ISA has count leading zeroes/ones instruction (not implemented). */
658 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
659 || ISA_MIPS32R2 \
660 || ISA_MIPS64) \
661 && !TARGET_MIPS16)
662
663 /* ISA has three operand multiply instructions that put
664 the high part in an accumulator: mulhi or mulhiu. */
665 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
666 || TARGET_MIPS5500 \
667 || TARGET_SR71K) \
668 && !TARGET_MIPS16)
669
670 /* ISA has three operand multiply instructions that
671 negates the result and puts the result in an accumulator. */
672 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
673 || TARGET_MIPS5500 \
674 || TARGET_SR71K) \
675 && !TARGET_MIPS16)
676
677 /* ISA has three operand multiply instructions that subtracts the
678 result from a 4th operand and puts the result in an accumulator. */
679 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
680 || TARGET_MIPS5500 \
681 || TARGET_SR71K) \
682 && !TARGET_MIPS16)
683
684 /* ISA has three operand multiply instructions that the result
685 from a 4th operand and puts the result in an accumulator. */
686 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
687 || TARGET_MIPS4130 \
688 || TARGET_MIPS5400 \
689 || TARGET_MIPS5500 \
690 || TARGET_SR71K) \
691 && !TARGET_MIPS16)
692
693 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
694 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
695 || TARGET_MIPS4130) \
696 && !TARGET_MIPS16)
697
698 /* ISA has the "ror" (rotate right) instructions. */
699 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
700 || TARGET_MIPS5400 \
701 || TARGET_MIPS5500 \
702 || TARGET_SR71K) \
703 && !TARGET_MIPS16)
704
705 /* ISA has data prefetch instructions. This controls use of 'pref'. */
706 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
707 || ISA_MIPS32 \
708 || ISA_MIPS32R2 \
709 || ISA_MIPS64) \
710 && !TARGET_MIPS16)
711
712 /* ISA has data indexed prefetch instructions. This controls use of
713 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
714 (prefx is a cop1x instruction, so can only be used if FP is
715 enabled.) */
716 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
717 || ISA_MIPS32R2 \
718 || ISA_MIPS64) \
719 && !TARGET_MIPS16)
720
721 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
722 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
723 also requires TARGET_DOUBLE_FLOAT. */
724 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
725
726 /* ISA includes the MIPS32r2 seb and seh instructions. */
727 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
728 && !TARGET_MIPS16)
729
730 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
731 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
732 && !TARGET_MIPS16)
733
734 /* ISA has instructions for accessing top part of 64-bit fp regs. */
735 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
736
737 /* True if the result of a load is not available to the next instruction.
738 A nop will then be needed between instructions like "lw $4,..."
739 and "addiu $4,$4,1". */
740 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
741 && !TARGET_MIPS3900 \
742 && !TARGET_MIPS16)
743
744 /* Likewise mtc1 and mfc1. */
745 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
746
747 /* Likewise floating-point comparisons. */
748 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
749
750 /* True if mflo and mfhi can be immediately followed by instructions
751 which write to the HI and LO registers.
752
753 According to MIPS specifications, MIPS ISAs I, II, and III need
754 (at least) two instructions between the reads of HI/LO and
755 instructions which write them, and later ISAs do not. Contradicting
756 the MIPS specifications, some MIPS IV processor user manuals (e.g.
757 the UM for the NEC Vr5000) document needing the instructions between
758 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
759 MIPS64 and later ISAs to have the interlocks, plus any specific
760 earlier-ISA CPUs for which CPU documentation declares that the
761 instructions are really interlocked. */
762 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
763 || ISA_MIPS32R2 \
764 || ISA_MIPS64 \
765 || TARGET_MIPS5500)
766 \f
767 /* Add -G xx support. */
768
769 #undef SWITCH_TAKES_ARG
770 #define SWITCH_TAKES_ARG(CHAR) \
771 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
772
773 #define OVERRIDE_OPTIONS override_options ()
774
775 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
776
777 /* Show we can debug even without a frame pointer. */
778 #define CAN_DEBUG_WITHOUT_FP
779 \f
780 /* Tell collect what flags to pass to nm. */
781 #ifndef NM_FLAGS
782 #define NM_FLAGS "-Bn"
783 #endif
784
785 \f
786 #ifndef MIPS_ABI_DEFAULT
787 #define MIPS_ABI_DEFAULT ABI_32
788 #endif
789
790 /* Use the most portable ABI flag for the ASM specs. */
791
792 #if MIPS_ABI_DEFAULT == ABI_32
793 #define MULTILIB_ABI_DEFAULT "mabi=32"
794 #endif
795
796 #if MIPS_ABI_DEFAULT == ABI_O64
797 #define MULTILIB_ABI_DEFAULT "mabi=o64"
798 #endif
799
800 #if MIPS_ABI_DEFAULT == ABI_N32
801 #define MULTILIB_ABI_DEFAULT "mabi=n32"
802 #endif
803
804 #if MIPS_ABI_DEFAULT == ABI_64
805 #define MULTILIB_ABI_DEFAULT "mabi=64"
806 #endif
807
808 #if MIPS_ABI_DEFAULT == ABI_EABI
809 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
810 #endif
811
812 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
813 to the assembler. It may be overridden by subtargets. */
814 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
815 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
816 %{noasmopt:-O0} \
817 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
818 #endif
819
820 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
821 the assembler. It may be overridden by subtargets.
822
823 Beginning with gas 2.13, -mdebug must be passed to correctly handle
824 COFF debugging info. */
825
826 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
827 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
828 %{g} %{g0} %{g1} %{g2} %{g3} \
829 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
830 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
831 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
832 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
833 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
834 #endif
835
836 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
837 overridden by subtargets. */
838
839 #ifndef SUBTARGET_ASM_SPEC
840 #define SUBTARGET_ASM_SPEC ""
841 #endif
842
843 #undef ASM_SPEC
844 #define ASM_SPEC "\
845 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
846 %{mips32} %{mips32r2} %{mips64} \
847 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
848 %{mips3d:-mips3d} \
849 %{mdsp} \
850 %{mdspr2} \
851 %{mfix-vr4120} %{mfix-vr4130} \
852 %(subtarget_asm_optimizing_spec) \
853 %(subtarget_asm_debugging_spec) \
854 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
855 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
856 %{mfp32} %{mfp64} \
857 %{mshared} %{mno-shared} \
858 %{msym32} %{mno-sym32} \
859 %{mtune=*} %{v} \
860 %(subtarget_asm_spec)"
861
862 /* Extra switches sometimes passed to the linker. */
863 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
864 will interpret it as a -b option. */
865
866 #ifndef LINK_SPEC
867 #define LINK_SPEC "\
868 %(endian_spec) \
869 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
870 %{bestGnum} %{shared} %{non_shared}"
871 #endif /* LINK_SPEC defined */
872
873
874 /* Specs for the compiler proper */
875
876 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
877 overridden by subtargets. */
878 #ifndef SUBTARGET_CC1_SPEC
879 #define SUBTARGET_CC1_SPEC ""
880 #endif
881
882 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
883
884 #undef CC1_SPEC
885 #define CC1_SPEC "\
886 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
887 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
888 %{save-temps: } \
889 %(subtarget_cc1_spec)"
890
891 /* Preprocessor specs. */
892
893 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
894 overridden by subtargets. */
895 #ifndef SUBTARGET_CPP_SPEC
896 #define SUBTARGET_CPP_SPEC ""
897 #endif
898
899 #define CPP_SPEC "%(subtarget_cpp_spec)"
900
901 /* This macro defines names of additional specifications to put in the specs
902 that can be used in various specifications like CC1_SPEC. Its definition
903 is an initializer with a subgrouping for each command option.
904
905 Each subgrouping contains a string constant, that defines the
906 specification name, and a string constant that used by the GCC driver
907 program.
908
909 Do not define this macro if it does not need to do anything. */
910
911 #define EXTRA_SPECS \
912 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
913 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
914 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
915 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
916 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
917 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
918 { "endian_spec", ENDIAN_SPEC }, \
919 SUBTARGET_EXTRA_SPECS
920
921 #ifndef SUBTARGET_EXTRA_SPECS
922 #define SUBTARGET_EXTRA_SPECS
923 #endif
924 \f
925 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
926 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
927 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
928
929 #ifndef PREFERRED_DEBUGGING_TYPE
930 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
931 #endif
932
933 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
934
935 /* By default, turn on GDB extensions. */
936 #define DEFAULT_GDB_EXTENSIONS 1
937
938 /* Local compiler-generated symbols must have a prefix that the assembler
939 understands. By default, this is $, although some targets (e.g.,
940 NetBSD-ELF) need to override this. */
941
942 #ifndef LOCAL_LABEL_PREFIX
943 #define LOCAL_LABEL_PREFIX "$"
944 #endif
945
946 /* By default on the mips, external symbols do not have an underscore
947 prepended, but some targets (e.g., NetBSD) require this. */
948
949 #ifndef USER_LABEL_PREFIX
950 #define USER_LABEL_PREFIX ""
951 #endif
952
953 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
954 since the length can run past this up to a continuation point. */
955 #undef DBX_CONTIN_LENGTH
956 #define DBX_CONTIN_LENGTH 1500
957
958 /* How to renumber registers for dbx and gdb. */
959 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
960
961 /* The mapping from gcc register number to DWARF 2 CFA column number. */
962 #define DWARF_FRAME_REGNUM(REG) (REG)
963
964 /* The DWARF 2 CFA column which tracks the return address. */
965 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
966
967 /* The DWARF 2 CFA column which tracks the return address from a
968 signal handler context. */
969 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
970
971 /* Before the prologue, RA lives in r31. */
972 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
973
974 /* Describe how we implement __builtin_eh_return. */
975 #define EH_RETURN_DATA_REGNO(N) \
976 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
977
978 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
979
980 /* Offsets recorded in opcodes are a multiple of this alignment factor.
981 The default for this in 64-bit mode is 8, which causes problems with
982 SFmode register saves. */
983 #define DWARF_CIE_DATA_ALIGNMENT -4
984
985 /* Correct the offset of automatic variables and arguments. Note that
986 the MIPS debug format wants all automatic variables and arguments
987 to be in terms of the virtual frame pointer (stack pointer before
988 any adjustment in the function), while the MIPS 3.0 linker wants
989 the frame pointer to be the stack pointer after the initial
990 adjustment. */
991
992 #define DEBUGGER_AUTO_OFFSET(X) \
993 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
994 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
995 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
996 \f
997 /* Target machine storage layout */
998
999 #define BITS_BIG_ENDIAN 0
1000 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1001 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1002
1003 /* Define this to set the endianness to use in libgcc2.c, which can
1004 not depend on target_flags. */
1005 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1006 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1007 #else
1008 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1009 #endif
1010
1011 #define MAX_BITS_PER_WORD 64
1012
1013 /* Width of a word, in units (bytes). */
1014 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1015 #ifndef IN_LIBGCC2
1016 #define MIN_UNITS_PER_WORD 4
1017 #endif
1018
1019 /* For MIPS, width of a floating point register. */
1020 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1021
1022 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1023 the next available register. */
1024 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1025
1026 /* The largest size of value that can be held in floating-point
1027 registers and moved with a single instruction. */
1028 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1029
1030 /* The largest size of value that can be held in floating-point
1031 registers. */
1032 #define UNITS_PER_FPVALUE \
1033 (TARGET_SOFT_FLOAT ? 0 \
1034 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1035 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1036
1037 /* The number of bytes in a double. */
1038 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1039
1040 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1041
1042 /* Set the sizes of the core types. */
1043 #define SHORT_TYPE_SIZE 16
1044 #define INT_TYPE_SIZE 32
1045 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1046 #define LONG_LONG_TYPE_SIZE 64
1047
1048 #define FLOAT_TYPE_SIZE 32
1049 #define DOUBLE_TYPE_SIZE 64
1050 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1051
1052 /* long double is not a fixed mode, but the idea is that, if we
1053 support long double, we also want a 128-bit integer type. */
1054 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1055
1056 #ifdef IN_LIBGCC2
1057 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1058 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1059 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1060 # else
1061 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1062 # endif
1063 #endif
1064
1065 /* Width in bits of a pointer. */
1066 #ifndef POINTER_SIZE
1067 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1068 #endif
1069
1070 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1071 #define PARM_BOUNDARY BITS_PER_WORD
1072
1073 /* Allocation boundary (in *bits*) for the code of a function. */
1074 #define FUNCTION_BOUNDARY 32
1075
1076 /* Alignment of field after `int : 0' in a structure. */
1077 #define EMPTY_FIELD_BOUNDARY 32
1078
1079 /* Every structure's size must be a multiple of this. */
1080 /* 8 is observed right on a DECstation and on riscos 4.02. */
1081 #define STRUCTURE_SIZE_BOUNDARY 8
1082
1083 /* There is no point aligning anything to a rounder boundary than this. */
1084 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1085
1086 /* All accesses must be aligned. */
1087 #define STRICT_ALIGNMENT 1
1088
1089 /* Define this if you wish to imitate the way many other C compilers
1090 handle alignment of bitfields and the structures that contain
1091 them.
1092
1093 The behavior is that the type written for a bit-field (`int',
1094 `short', or other integer type) imposes an alignment for the
1095 entire structure, as if the structure really did contain an
1096 ordinary field of that type. In addition, the bit-field is placed
1097 within the structure so that it would fit within such a field,
1098 not crossing a boundary for it.
1099
1100 Thus, on most machines, a bit-field whose type is written as `int'
1101 would not cross a four-byte boundary, and would force four-byte
1102 alignment for the whole structure. (The alignment used may not
1103 be four bytes; it is controlled by the other alignment
1104 parameters.)
1105
1106 If the macro is defined, its definition should be a C expression;
1107 a nonzero value for the expression enables this behavior. */
1108
1109 #define PCC_BITFIELD_TYPE_MATTERS 1
1110
1111 /* If defined, a C expression to compute the alignment given to a
1112 constant that is being placed in memory. CONSTANT is the constant
1113 and ALIGN is the alignment that the object would ordinarily have.
1114 The value of this macro is used instead of that alignment to align
1115 the object.
1116
1117 If this macro is not defined, then ALIGN is used.
1118
1119 The typical use of this macro is to increase alignment for string
1120 constants to be word aligned so that `strcpy' calls that copy
1121 constants can be done inline. */
1122
1123 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1124 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1125 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1126
1127 /* If defined, a C expression to compute the alignment for a static
1128 variable. TYPE is the data type, and ALIGN is the alignment that
1129 the object would ordinarily have. The value of this macro is used
1130 instead of that alignment to align the object.
1131
1132 If this macro is not defined, then ALIGN is used.
1133
1134 One use of this macro is to increase alignment of medium-size
1135 data to make it all fit in fewer cache lines. Another is to
1136 cause character arrays to be word-aligned so that `strcpy' calls
1137 that copy constants to character arrays can be done inline. */
1138
1139 #undef DATA_ALIGNMENT
1140 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1141 ((((ALIGN) < BITS_PER_WORD) \
1142 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1143 || TREE_CODE (TYPE) == UNION_TYPE \
1144 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1145
1146
1147 #define PAD_VARARGS_DOWN \
1148 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1149
1150 /* Define if operations between registers always perform the operation
1151 on the full register even if a narrower mode is specified. */
1152 #define WORD_REGISTER_OPERATIONS
1153
1154 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1155 moves. All other references are zero extended. */
1156 #define LOAD_EXTEND_OP(MODE) \
1157 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1158 ? SIGN_EXTEND : ZERO_EXTEND)
1159
1160 /* Define this macro if it is advisable to hold scalars in registers
1161 in a wider mode than that declared by the program. In such cases,
1162 the value is constrained to be within the bounds of the declared
1163 type, but kept valid in the wider mode. The signedness of the
1164 extension may differ from that of the type. */
1165
1166 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1167 if (GET_MODE_CLASS (MODE) == MODE_INT \
1168 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1169 { \
1170 if ((MODE) == SImode) \
1171 (UNSIGNEDP) = 0; \
1172 (MODE) = Pmode; \
1173 }
1174
1175 /* Define if loading short immediate values into registers sign extends. */
1176 #define SHORT_IMMEDIATES_SIGN_EXTEND
1177
1178 /* The [d]clz instructions have the natural values at 0. */
1179
1180 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1181 ((VALUE) = GET_MODE_BITSIZE (MODE), true)
1182 \f
1183 /* Standard register usage. */
1184
1185 /* Number of hardware registers. We have:
1186
1187 - 32 integer registers
1188 - 32 floating point registers
1189 - 8 condition code registers
1190 - 2 accumulator registers (hi and lo)
1191 - 32 registers each for coprocessors 0, 2 and 3
1192 - 3 fake registers:
1193 - ARG_POINTER_REGNUM
1194 - FRAME_POINTER_REGNUM
1195 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1196 - 3 dummy entries that were used at various times in the past.
1197 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1198 - 6 DSP control registers */
1199
1200 #define FIRST_PSEUDO_REGISTER 188
1201
1202 /* By default, fix the kernel registers ($26 and $27), the global
1203 pointer ($28) and the stack pointer ($29). This can change
1204 depending on the command-line options.
1205
1206 Regarding coprocessor registers: without evidence to the contrary,
1207 it's best to assume that each coprocessor register has a unique
1208 use. This can be overridden, in, e.g., override_options() or
1209 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1210 for a particular target. */
1211
1212 #define FIXED_REGISTERS \
1213 { \
1214 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1218 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1219 /* COP0 registers */ \
1220 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1221 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1222 /* COP2 registers */ \
1223 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1224 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1225 /* COP3 registers */ \
1226 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1227 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1228 /* 6 DSP accumulator registers & 6 control registers */ \
1229 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1230 }
1231
1232
1233 /* Set up this array for o32 by default.
1234
1235 Note that we don't mark $31 as a call-clobbered register. The idea is
1236 that it's really the call instructions themselves which clobber $31.
1237 We don't care what the called function does with it afterwards.
1238
1239 This approach makes it easier to implement sibcalls. Unlike normal
1240 calls, sibcalls don't clobber $31, so the register reaches the
1241 called function in tact. EPILOGUE_USES says that $31 is useful
1242 to the called function. */
1243
1244 #define CALL_USED_REGISTERS \
1245 { \
1246 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1247 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1248 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1249 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1250 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1251 /* COP0 registers */ \
1252 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1253 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1254 /* COP2 registers */ \
1255 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1256 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1257 /* COP3 registers */ \
1258 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1259 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1260 /* 6 DSP accumulator registers & 6 control registers */ \
1261 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1262 }
1263
1264
1265 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1266
1267 #define CALL_REALLY_USED_REGISTERS \
1268 { /* General registers. */ \
1269 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1270 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1271 /* Floating-point registers. */ \
1272 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1273 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1274 /* Others. */ \
1275 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1276 /* COP0 registers */ \
1277 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1278 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1279 /* COP2 registers */ \
1280 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1281 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1282 /* COP3 registers */ \
1283 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1284 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1285 /* 6 DSP accumulator registers & 6 control registers */ \
1286 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1287 }
1288
1289 /* Internal macros to classify a register number as to whether it's a
1290 general purpose register, a floating point register, a
1291 multiply/divide register, or a status register. */
1292
1293 #define GP_REG_FIRST 0
1294 #define GP_REG_LAST 31
1295 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1296 #define GP_DBX_FIRST 0
1297
1298 #define FP_REG_FIRST 32
1299 #define FP_REG_LAST 63
1300 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1301 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1302
1303 #define MD_REG_FIRST 64
1304 #define MD_REG_LAST 65
1305 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1306 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1307
1308 #define ST_REG_FIRST 67
1309 #define ST_REG_LAST 74
1310 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1311
1312
1313 /* FIXME: renumber. */
1314 #define COP0_REG_FIRST 80
1315 #define COP0_REG_LAST 111
1316 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1317
1318 #define COP2_REG_FIRST 112
1319 #define COP2_REG_LAST 143
1320 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1321
1322 #define COP3_REG_FIRST 144
1323 #define COP3_REG_LAST 175
1324 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1325 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1326 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1327
1328 #define DSP_ACC_REG_FIRST 176
1329 #define DSP_ACC_REG_LAST 181
1330 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1331
1332 #define AT_REGNUM (GP_REG_FIRST + 1)
1333 #define HI_REGNUM (MD_REG_FIRST + 0)
1334 #define LO_REGNUM (MD_REG_FIRST + 1)
1335 #define AC1HI_REGNUM (DSP_ACC_REG_FIRST + 0)
1336 #define AC1LO_REGNUM (DSP_ACC_REG_FIRST + 1)
1337 #define AC2HI_REGNUM (DSP_ACC_REG_FIRST + 2)
1338 #define AC2LO_REGNUM (DSP_ACC_REG_FIRST + 3)
1339 #define AC3HI_REGNUM (DSP_ACC_REG_FIRST + 4)
1340 #define AC3LO_REGNUM (DSP_ACC_REG_FIRST + 5)
1341
1342 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1343 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1344 should be used instead. */
1345 #define FPSW_REGNUM ST_REG_FIRST
1346
1347 #define GP_REG_P(REGNO) \
1348 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1349 #define M16_REG_P(REGNO) \
1350 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1351 #define FP_REG_P(REGNO) \
1352 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1353 #define MD_REG_P(REGNO) \
1354 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1355 #define ST_REG_P(REGNO) \
1356 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1357 #define COP0_REG_P(REGNO) \
1358 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1359 #define COP2_REG_P(REGNO) \
1360 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1361 #define COP3_REG_P(REGNO) \
1362 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1363 #define ALL_COP_REG_P(REGNO) \
1364 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1365 /* Test if REGNO is one of the 6 new DSP accumulators. */
1366 #define DSP_ACC_REG_P(REGNO) \
1367 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1368 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1369 #define ACC_REG_P(REGNO) \
1370 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1371 /* Test if REGNO is HI or the first register of 3 new DSP accumulator pairs. */
1372 #define ACC_HI_REG_P(REGNO) \
1373 ((REGNO) == HI_REGNUM || (REGNO) == AC1HI_REGNUM || (REGNO) == AC2HI_REGNUM \
1374 || (REGNO) == AC3HI_REGNUM)
1375
1376 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1377
1378 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1379 to initialize the mips16 gp pseudo register. */
1380 #define CONST_GP_P(X) \
1381 (GET_CODE (X) == CONST \
1382 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1383 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1384
1385 /* Return coprocessor number from register number. */
1386
1387 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1388 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1389 : COP3_REG_P (REGNO) ? '3' : '?')
1390
1391
1392 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1393
1394 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1395 array built in override_options. Because machmodes.h is not yet
1396 included before this file is processed, the MODE bound can't be
1397 expressed here. */
1398
1399 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1400
1401 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1402 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1403
1404 /* Value is 1 if it is a good idea to tie two pseudo registers
1405 when one has mode MODE1 and one has mode MODE2.
1406 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1407 for any hard reg, then this must be 0 for correct output. */
1408 #define MODES_TIEABLE_P(MODE1, MODE2) \
1409 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1410 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1411 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1412 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1413
1414 /* Register to use for pushing function arguments. */
1415 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1416
1417 /* These two registers don't really exist: they get eliminated to either
1418 the stack or hard frame pointer. */
1419 #define ARG_POINTER_REGNUM 77
1420 #define FRAME_POINTER_REGNUM 78
1421
1422 /* $30 is not available on the mips16, so we use $17 as the frame
1423 pointer. */
1424 #define HARD_FRAME_POINTER_REGNUM \
1425 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1426
1427 /* Value should be nonzero if functions must have frame pointers.
1428 Zero means the frame pointer need not be set up (and parms
1429 may be accessed via the stack pointer) in functions that seem suitable.
1430 This is computed in `reload', in reload1.c. */
1431 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1432
1433 /* Register in which static-chain is passed to a function. */
1434 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1435
1436 /* Registers used as temporaries in prologue/epilogue code. If we're
1437 generating mips16 code, these registers must come from the core set
1438 of 8. The prologue register mustn't conflict with any incoming
1439 arguments, the static chain pointer, or the frame pointer. The
1440 epilogue temporary mustn't conflict with the return registers, the
1441 frame pointer, the EH stack adjustment, or the EH data registers. */
1442
1443 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1444 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1445
1446 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1447 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1448
1449 /* Define this macro if it is as good or better to call a constant
1450 function address than to call an address kept in a register. */
1451 #define NO_FUNCTION_CSE 1
1452
1453 /* The ABI-defined global pointer. Sometimes we use a different
1454 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1455 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1456
1457 /* We normally use $28 as the global pointer. However, when generating
1458 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1459 register instead. They can then avoid saving and restoring $28
1460 and perhaps avoid using a frame at all.
1461
1462 When a leaf function uses something other than $28, mips_expand_prologue
1463 will modify pic_offset_table_rtx in place. Take the register number
1464 from there after reload. */
1465 #define PIC_OFFSET_TABLE_REGNUM \
1466 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1467
1468 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1469 \f
1470 /* Define the classes of registers for register constraints in the
1471 machine description. Also define ranges of constants.
1472
1473 One of the classes must always be named ALL_REGS and include all hard regs.
1474 If there is more than one class, another class must be named NO_REGS
1475 and contain no registers.
1476
1477 The name GENERAL_REGS must be the name of a class (or an alias for
1478 another name such as ALL_REGS). This is the class of registers
1479 that is allowed by "g" or "r" in a register constraint.
1480 Also, registers outside this class are allocated only when
1481 instructions express preferences for them.
1482
1483 The classes must be numbered in nondecreasing order; that is,
1484 a larger-numbered class must never be contained completely
1485 in a smaller-numbered class.
1486
1487 For any two classes, it is very desirable that there be another
1488 class that represents their union. */
1489
1490 enum reg_class
1491 {
1492 NO_REGS, /* no registers in set */
1493 M16_NA_REGS, /* mips16 regs not used to pass args */
1494 M16_REGS, /* mips16 directly accessible registers */
1495 T_REG, /* mips16 T register ($24) */
1496 M16_T_REGS, /* mips16 registers plus T register */
1497 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1498 V1_REG, /* Register $v1 ($3) used for TLS access. */
1499 LEA_REGS, /* Every GPR except $25 */
1500 GR_REGS, /* integer registers */
1501 FP_REGS, /* floating point registers */
1502 HI_REG, /* hi register */
1503 LO_REG, /* lo register */
1504 MD_REGS, /* multiply/divide registers (hi/lo) */
1505 COP0_REGS, /* generic coprocessor classes */
1506 COP2_REGS,
1507 COP3_REGS,
1508 HI_AND_GR_REGS, /* union classes */
1509 LO_AND_GR_REGS,
1510 HI_AND_FP_REGS,
1511 COP0_AND_GR_REGS,
1512 COP2_AND_GR_REGS,
1513 COP3_AND_GR_REGS,
1514 ALL_COP_REGS,
1515 ALL_COP_AND_GR_REGS,
1516 ST_REGS, /* status registers (fp status) */
1517 DSP_ACC_REGS, /* DSP accumulator registers */
1518 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1519 ALL_REGS, /* all registers */
1520 LIM_REG_CLASSES /* max value + 1 */
1521 };
1522
1523 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1524
1525 #define GENERAL_REGS GR_REGS
1526
1527 /* An initializer containing the names of the register classes as C
1528 string constants. These names are used in writing some of the
1529 debugging dumps. */
1530
1531 #define REG_CLASS_NAMES \
1532 { \
1533 "NO_REGS", \
1534 "M16_NA_REGS", \
1535 "M16_REGS", \
1536 "T_REG", \
1537 "M16_T_REGS", \
1538 "PIC_FN_ADDR_REG", \
1539 "V1_REG", \
1540 "LEA_REGS", \
1541 "GR_REGS", \
1542 "FP_REGS", \
1543 "HI_REG", \
1544 "LO_REG", \
1545 "MD_REGS", \
1546 /* coprocessor registers */ \
1547 "COP0_REGS", \
1548 "COP2_REGS", \
1549 "COP3_REGS", \
1550 "HI_AND_GR_REGS", \
1551 "LO_AND_GR_REGS", \
1552 "HI_AND_FP_REGS", \
1553 "COP0_AND_GR_REGS", \
1554 "COP2_AND_GR_REGS", \
1555 "COP3_AND_GR_REGS", \
1556 "ALL_COP_REGS", \
1557 "ALL_COP_AND_GR_REGS", \
1558 "ST_REGS", \
1559 "DSP_ACC_REGS", \
1560 "ACC_REGS", \
1561 "ALL_REGS" \
1562 }
1563
1564 /* An initializer containing the contents of the register classes,
1565 as integers which are bit masks. The Nth integer specifies the
1566 contents of class N. The way the integer MASK is interpreted is
1567 that register R is in the class if `MASK & (1 << R)' is 1.
1568
1569 When the machine has more than 32 registers, an integer does not
1570 suffice. Then the integers are replaced by sub-initializers,
1571 braced groupings containing several integers. Each
1572 sub-initializer must be suitable as an initializer for the type
1573 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1574
1575 #define REG_CLASS_CONTENTS \
1576 { \
1577 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1578 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1579 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1580 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1581 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1582 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1583 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1584 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1585 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1586 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1587 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1588 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1589 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1590 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1591 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1592 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1593 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1594 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1595 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1596 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1597 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1598 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1599 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1600 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1601 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1602 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1603 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1604 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1605 }
1606
1607
1608 /* A C expression whose value is a register class containing hard
1609 register REGNO. In general there is more that one such class;
1610 choose a class which is "minimal", meaning that no smaller class
1611 also contains the register. */
1612
1613 extern const enum reg_class mips_regno_to_class[];
1614
1615 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1616
1617 /* A macro whose definition is the name of the class to which a
1618 valid base register must belong. A base register is one used in
1619 an address which is the register value plus a displacement. */
1620
1621 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1622
1623 /* A macro whose definition is the name of the class to which a
1624 valid index register must belong. An index register is one used
1625 in an address where its value is either multiplied by a scale
1626 factor or added to another register (as well as added to a
1627 displacement). */
1628
1629 #define INDEX_REG_CLASS NO_REGS
1630
1631 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1632 registers explicitly used in the rtl to be used as spill registers
1633 but prevents the compiler from extending the lifetime of these
1634 registers. */
1635
1636 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1637
1638 /* This macro is used later on in the file. */
1639 #define GR_REG_CLASS_P(CLASS) \
1640 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1641 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1642 || (CLASS) == V1_REG \
1643 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1644
1645 /* This macro is also used later on in the file. */
1646 #define COP_REG_CLASS_P(CLASS) \
1647 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1648
1649 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1650 is the default value (allocate the registers in numeric order). We
1651 define it just so that we can override it for the mips16 target in
1652 ORDER_REGS_FOR_LOCAL_ALLOC. */
1653
1654 #define REG_ALLOC_ORDER \
1655 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1656 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1657 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1658 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1659 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1660 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1661 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1662 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1663 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1664 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1665 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1666 176,177,178,179,180,181,182,183,184,185,186,187 \
1667 }
1668
1669 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1670 to be rearranged based on a particular function. On the mips16, we
1671 want to allocate $24 (T_REG) before other registers for
1672 instructions for which it is possible. */
1673
1674 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1675
1676 /* True if VALUE is an unsigned 6-bit number. */
1677
1678 #define UIMM6_OPERAND(VALUE) \
1679 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1680
1681 /* True if VALUE is a signed 10-bit number. */
1682
1683 #define IMM10_OPERAND(VALUE) \
1684 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1685
1686 /* True if VALUE is a signed 16-bit number. */
1687
1688 #define SMALL_OPERAND(VALUE) \
1689 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1690
1691 /* True if VALUE is an unsigned 16-bit number. */
1692
1693 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1694 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1695
1696 /* True if VALUE can be loaded into a register using LUI. */
1697
1698 #define LUI_OPERAND(VALUE) \
1699 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1700 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1701
1702 /* Return a value X with the low 16 bits clear, and such that
1703 VALUE - X is a signed 16-bit value. */
1704
1705 #define CONST_HIGH_PART(VALUE) \
1706 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1707
1708 #define CONST_LOW_PART(VALUE) \
1709 ((VALUE) - CONST_HIGH_PART (VALUE))
1710
1711 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1712 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1713 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1714
1715 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1716 mips_preferred_reload_class (X, CLASS)
1717
1718 /* Certain machines have the property that some registers cannot be
1719 copied to some other registers without using memory. Define this
1720 macro on those machines to be a C expression that is nonzero if
1721 objects of mode MODE in registers of CLASS1 can only be copied to
1722 registers of class CLASS2 by storing a register of CLASS1 into
1723 memory and loading that memory location into a register of CLASS2.
1724
1725 Do not define this macro if its value would always be zero. */
1726 #if 0
1727 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1728 ((!TARGET_DEBUG_H_MODE \
1729 && GET_MODE_CLASS (MODE) == MODE_INT \
1730 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1731 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1732 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1733 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1734 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1735 #endif
1736 /* The HI and LO registers can only be reloaded via the general
1737 registers. Condition code registers can only be loaded to the
1738 general registers, and from the floating point registers. */
1739
1740 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1741 mips_secondary_reload_class (CLASS, MODE, X, 1)
1742 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1743 mips_secondary_reload_class (CLASS, MODE, X, 0)
1744
1745 /* Return the maximum number of consecutive registers
1746 needed to represent mode MODE in a register of class CLASS. */
1747
1748 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1749
1750 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1751 mips_cannot_change_mode_class (FROM, TO, CLASS)
1752 \f
1753 /* Stack layout; function entry, exit and calling. */
1754
1755 #define STACK_GROWS_DOWNWARD
1756
1757 /* The offset of the first local variable from the beginning of the frame.
1758 See compute_frame_size for details about the frame layout.
1759
1760 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1761 we assume that we will need 16 bytes of argument space. This is because
1762 the value profiling code may emit calls to cmpdi2 in leaf functions.
1763 Without this hack, the local variables will start at sp+8 and the gp save
1764 area will be at sp+16, and thus they will overlap. compute_frame_size is
1765 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1766 will end up as 24 instead of 8. This won't be needed if profiling code is
1767 inserted before virtual register instantiation. */
1768
1769 #define STARTING_FRAME_OFFSET \
1770 ((flag_profile_values && ! TARGET_64BIT \
1771 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1772 : current_function_outgoing_args_size) \
1773 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1774
1775 #define RETURN_ADDR_RTX mips_return_addr
1776
1777 /* Since the mips16 ISA mode is encoded in the least-significant bit
1778 of the address, mask it off return addresses for purposes of
1779 finding exception handling regions. */
1780
1781 #define MASK_RETURN_ADDR GEN_INT (-2)
1782
1783
1784 /* Similarly, don't use the least-significant bit to tell pointers to
1785 code from vtable index. */
1786
1787 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1788
1789 /* The eliminations to $17 are only used for mips16 code. See the
1790 definition of HARD_FRAME_POINTER_REGNUM. */
1791
1792 #define ELIMINABLE_REGS \
1793 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1794 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1795 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1796 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1797 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1798 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1799
1800 /* We can always eliminate to the hard frame pointer. We can eliminate
1801 to the stack pointer unless a frame pointer is needed.
1802
1803 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1804 reload may be unable to compute the address of a local variable,
1805 since there is no way to add a large constant to the stack pointer
1806 without using a temporary register. */
1807 #define CAN_ELIMINATE(FROM, TO) \
1808 ((TO) == HARD_FRAME_POINTER_REGNUM \
1809 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1810 && (!TARGET_MIPS16 \
1811 || compute_frame_size (get_frame_size ()) < 32768)))
1812
1813 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1814 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1815
1816 /* Allocate stack space for arguments at the beginning of each function. */
1817 #define ACCUMULATE_OUTGOING_ARGS 1
1818
1819 /* The argument pointer always points to the first argument. */
1820 #define FIRST_PARM_OFFSET(FNDECL) 0
1821
1822 /* o32 and o64 reserve stack space for all argument registers. */
1823 #define REG_PARM_STACK_SPACE(FNDECL) \
1824 (TARGET_OLDABI \
1825 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1826 : 0)
1827
1828 /* Define this if it is the responsibility of the caller to
1829 allocate the area reserved for arguments passed in registers.
1830 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1831 of this macro is to determine whether the space is included in
1832 `current_function_outgoing_args_size'. */
1833 #define OUTGOING_REG_PARM_STACK_SPACE 1
1834
1835 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1836 \f
1837 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1838
1839 /* Symbolic macros for the registers used to return integer and floating
1840 point values. */
1841
1842 #define GP_RETURN (GP_REG_FIRST + 2)
1843 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1844
1845 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1846
1847 /* Symbolic macros for the first/last argument registers. */
1848
1849 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1850 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1851 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1852 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1853
1854 #define LIBCALL_VALUE(MODE) \
1855 mips_function_value (NULL_TREE, NULL, (MODE))
1856
1857 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1858 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1859
1860 /* 1 if N is a possible register number for a function value.
1861 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1862 Currently, R2 and F0 are only implemented here (C has no complex type) */
1863
1864 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1865 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1866 && (N) == FP_RETURN + 2))
1867
1868 /* 1 if N is a possible register number for function argument passing.
1869 We have no FP argument registers when soft-float. When FP registers
1870 are 32 bits, we can't directly reference the odd numbered ones. */
1871
1872 #define FUNCTION_ARG_REGNO_P(N) \
1873 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1874 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1875 && !fixed_regs[N])
1876 \f
1877 /* This structure has to cope with two different argument allocation
1878 schemes. Most MIPS ABIs view the arguments as a structure, of which
1879 the first N words go in registers and the rest go on the stack. If I
1880 < N, the Ith word might go in Ith integer argument register or in a
1881 floating-point register. For these ABIs, we only need to remember
1882 the offset of the current argument into the structure.
1883
1884 The EABI instead allocates the integer and floating-point arguments
1885 separately. The first N words of FP arguments go in FP registers,
1886 the rest go on the stack. Likewise, the first N words of the other
1887 arguments go in integer registers, and the rest go on the stack. We
1888 need to maintain three counts: the number of integer registers used,
1889 the number of floating-point registers used, and the number of words
1890 passed on the stack.
1891
1892 We could keep separate information for the two ABIs (a word count for
1893 the standard ABIs, and three separate counts for the EABI). But it
1894 seems simpler to view the standard ABIs as forms of EABI that do not
1895 allocate floating-point registers.
1896
1897 So for the standard ABIs, the first N words are allocated to integer
1898 registers, and function_arg decides on an argument-by-argument basis
1899 whether that argument should really go in an integer register, or in
1900 a floating-point one. */
1901
1902 typedef struct mips_args {
1903 /* Always true for varargs functions. Otherwise true if at least
1904 one argument has been passed in an integer register. */
1905 int gp_reg_found;
1906
1907 /* The number of arguments seen so far. */
1908 unsigned int arg_number;
1909
1910 /* The number of integer registers used so far. For all ABIs except
1911 EABI, this is the number of words that have been added to the
1912 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
1913 unsigned int num_gprs;
1914
1915 /* For EABI, the number of floating-point registers used so far. */
1916 unsigned int num_fprs;
1917
1918 /* The number of words passed on the stack. */
1919 unsigned int stack_words;
1920
1921 /* On the mips16, we need to keep track of which floating point
1922 arguments were passed in general registers, but would have been
1923 passed in the FP regs if this were a 32-bit function, so that we
1924 can move them to the FP regs if we wind up calling a 32-bit
1925 function. We record this information in fp_code, encoded in base
1926 four. A zero digit means no floating point argument, a one digit
1927 means an SFmode argument, and a two digit means a DFmode argument,
1928 and a three digit is not used. The low order digit is the first
1929 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
1930 an SFmode argument. ??? A more sophisticated approach will be
1931 needed if MIPS_ABI != ABI_32. */
1932 int fp_code;
1933
1934 /* True if the function has a prototype. */
1935 int prototype;
1936 } CUMULATIVE_ARGS;
1937
1938 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1939 for a call to a function whose data type is FNTYPE.
1940 For a library call, FNTYPE is 0. */
1941
1942 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1943 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
1944
1945 /* Update the data in CUM to advance over an argument
1946 of mode MODE and data type TYPE.
1947 (TYPE is null for libcalls where that information may not be available.) */
1948
1949 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1950 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1951
1952 /* Determine where to put an argument to a function.
1953 Value is zero to push the argument on the stack,
1954 or a hard register in which to store the argument.
1955
1956 MODE is the argument's machine mode.
1957 TYPE is the data type of the argument (as a tree).
1958 This is null for libcalls where that information may
1959 not be available.
1960 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1961 the preceding args and about the function being called.
1962 NAMED is nonzero if this argument is a named parameter
1963 (otherwise it is an extra parameter matching an ellipsis). */
1964
1965 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1966 function_arg( &CUM, MODE, TYPE, NAMED)
1967
1968 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
1969
1970 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1971 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
1972
1973 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1974 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
1975
1976 /* True if using EABI and varargs can be passed in floating-point
1977 registers. Under these conditions, we need a more complex form
1978 of va_list, which tracks GPR, FPR and stack arguments separately. */
1979 #define EABI_FLOAT_VARARGS_P \
1980 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
1981
1982 \f
1983 /* Say that the epilogue uses the return address register. Note that
1984 in the case of sibcalls, the values "used by the epilogue" are
1985 considered live at the start of the called function. */
1986 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
1987
1988 /* Treat LOC as a byte offset from the stack pointer and round it up
1989 to the next fully-aligned offset. */
1990 #define MIPS_STACK_ALIGN(LOC) \
1991 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
1992
1993 \f
1994 /* Implement `va_start' for varargs and stdarg. */
1995 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1996 mips_va_start (valist, nextarg)
1997 \f
1998 /* Output assembler code to FILE to increment profiler label # LABELNO
1999 for profiling a function entry. */
2000
2001 #define FUNCTION_PROFILER(FILE, LABELNO) \
2002 { \
2003 if (TARGET_MIPS16) \
2004 sorry ("mips16 function profiling"); \
2005 fprintf (FILE, "\t.set\tnoat\n"); \
2006 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2007 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2008 if (!TARGET_NEWABI) \
2009 { \
2010 fprintf (FILE, \
2011 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2012 TARGET_64BIT ? "dsubu" : "subu", \
2013 reg_names[STACK_POINTER_REGNUM], \
2014 reg_names[STACK_POINTER_REGNUM], \
2015 Pmode == DImode ? 16 : 8); \
2016 } \
2017 fprintf (FILE, "\tjal\t_mcount\n"); \
2018 fprintf (FILE, "\t.set\tat\n"); \
2019 }
2020
2021 /* No mips port has ever used the profiler counter word, so don't emit it
2022 or the label for it. */
2023
2024 #define NO_PROFILE_COUNTERS 1
2025
2026 /* Define this macro if the code for function profiling should come
2027 before the function prologue. Normally, the profiling code comes
2028 after. */
2029
2030 /* #define PROFILE_BEFORE_PROLOGUE */
2031
2032 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2033 the stack pointer does not matter. The value is tested only in
2034 functions that have frame pointers.
2035 No definition is equivalent to always zero. */
2036
2037 #define EXIT_IGNORE_STACK 1
2038
2039 \f
2040 /* A C statement to output, on the stream FILE, assembler code for a
2041 block of data that contains the constant parts of a trampoline.
2042 This code should not include a label--the label is taken care of
2043 automatically. */
2044
2045 #define TRAMPOLINE_TEMPLATE(STREAM) \
2046 { \
2047 if (ptr_mode == DImode) \
2048 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2049 else \
2050 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2051 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2052 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2053 if (ptr_mode == DImode) \
2054 { \
2055 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2056 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2057 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2058 } \
2059 else \
2060 { \
2061 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2062 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2063 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2064 } \
2065 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2066 if (ptr_mode == DImode) \
2067 { \
2068 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2069 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2070 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2071 } \
2072 else \
2073 { \
2074 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2075 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2076 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2077 } \
2078 }
2079
2080 /* A C expression for the size in bytes of the trampoline, as an
2081 integer. */
2082
2083 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2084
2085 /* Alignment required for trampolines, in bits. */
2086
2087 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2088
2089 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2090 program and data caches. */
2091
2092 #ifndef CACHE_FLUSH_FUNC
2093 #define CACHE_FLUSH_FUNC "_flush_cache"
2094 #endif
2095
2096 /* A C statement to initialize the variable parts of a trampoline.
2097 ADDR is an RTX for the address of the trampoline; FNADDR is an
2098 RTX for the address of the nested function; STATIC_CHAIN is an
2099 RTX for the static chain value that should be passed to the
2100 function when it is called. */
2101
2102 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2103 { \
2104 rtx func_addr, chain_addr; \
2105 \
2106 func_addr = plus_constant (ADDR, 32); \
2107 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2108 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2109 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2110 \
2111 /* Flush both caches. We need to flush the data cache in case \
2112 the system has a write-back cache. */ \
2113 /* ??? Should check the return value for errors. */ \
2114 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2115 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2116 0, VOIDmode, 3, ADDR, Pmode, \
2117 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2118 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2119 }
2120 \f
2121 /* Addressing modes, and classification of registers for them. */
2122
2123 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2124 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2125 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2126
2127 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2128 and check its validity for a certain class.
2129 We have two alternate definitions for each of them.
2130 The usual definition accepts all pseudo regs; the other rejects them all.
2131 The symbol REG_OK_STRICT causes the latter definition to be used.
2132
2133 Most source files want to accept pseudo regs in the hope that
2134 they will get allocated to the class that the insn wants them to be in.
2135 Some source files that are used after register allocation
2136 need to be strict. */
2137
2138 #ifndef REG_OK_STRICT
2139 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2140 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2141 #else
2142 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2143 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2144 #endif
2145
2146 #define REG_OK_FOR_INDEX_P(X) 0
2147
2148 \f
2149 /* Maximum number of registers that can appear in a valid memory address. */
2150
2151 #define MAX_REGS_PER_ADDRESS 1
2152
2153 #ifdef REG_OK_STRICT
2154 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2155 { \
2156 if (mips_legitimate_address_p (MODE, X, 1)) \
2157 goto ADDR; \
2158 }
2159 #else
2160 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2161 { \
2162 if (mips_legitimate_address_p (MODE, X, 0)) \
2163 goto ADDR; \
2164 }
2165 #endif
2166
2167 /* Check for constness inline but use mips_legitimate_address_p
2168 to check whether a constant really is an address. */
2169
2170 #define CONSTANT_ADDRESS_P(X) \
2171 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2172
2173 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2174
2175 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2176 do { \
2177 if (mips_legitimize_address (&(X), MODE)) \
2178 goto WIN; \
2179 } while (0)
2180
2181
2182 /* A C statement or compound statement with a conditional `goto
2183 LABEL;' executed if memory address X (an RTX) can have different
2184 meanings depending on the machine mode of the memory reference it
2185 is used for.
2186
2187 Autoincrement and autodecrement addresses typically have
2188 mode-dependent effects because the amount of the increment or
2189 decrement is the size of the operand being addressed. Some
2190 machines have other mode-dependent addresses. Many RISC machines
2191 have no mode-dependent addresses.
2192
2193 You may assume that ADDR is a valid address for the machine. */
2194
2195 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2196
2197 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2198 'the start of the function that this code is output in'. */
2199
2200 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2201 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2202 asm_fprintf ((FILE), "%U%s", \
2203 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2204 else \
2205 asm_fprintf ((FILE), "%U%s", (NAME))
2206 \f
2207 /* Flag to mark a function decl symbol that requires a long call. */
2208 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2209 #define SYMBOL_REF_LONG_CALL_P(X) \
2210 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2211
2212 /* Specify the machine mode that this machine uses
2213 for the index in the tablejump instruction.
2214 ??? Using HImode in mips16 mode can cause overflow. */
2215 #define CASE_VECTOR_MODE \
2216 (TARGET_MIPS16 ? HImode : ptr_mode)
2217
2218 /* Define as C expression which evaluates to nonzero if the tablejump
2219 instruction expects the table to contain offsets from the address of the
2220 table.
2221 Do not define this if the table should contain absolute addresses. */
2222 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2223
2224 /* Define this as 1 if `char' should by default be signed; else as 0. */
2225 #ifndef DEFAULT_SIGNED_CHAR
2226 #define DEFAULT_SIGNED_CHAR 1
2227 #endif
2228
2229 /* Max number of bytes we can move from memory to memory
2230 in one reasonably fast instruction. */
2231 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2232 #define MAX_MOVE_MAX 8
2233
2234 /* Define this macro as a C expression which is nonzero if
2235 accessing less than a word of memory (i.e. a `char' or a
2236 `short') is no faster than accessing a word of memory, i.e., if
2237 such access require more than one instruction or if there is no
2238 difference in cost between byte and (aligned) word loads.
2239
2240 On RISC machines, it tends to generate better code to define
2241 this as 1, since it avoids making a QI or HI mode register. */
2242 #define SLOW_BYTE_ACCESS 1
2243
2244 /* Define this to be nonzero if shift instructions ignore all but the low-order
2245 few bits. */
2246 #define SHIFT_COUNT_TRUNCATED 1
2247
2248 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2249 is done just by pretending it is already truncated. */
2250 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2251 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2252
2253
2254 /* Specify the machine mode that pointers have.
2255 After generation of rtl, the compiler makes no further distinction
2256 between pointers and any other objects of this machine mode. */
2257
2258 #ifndef Pmode
2259 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2260 #endif
2261
2262 /* Give call MEMs SImode since it is the "most permissive" mode
2263 for both 32-bit and 64-bit targets. */
2264
2265 #define FUNCTION_MODE SImode
2266
2267 \f
2268 /* The cost of loading values from the constant pool. It should be
2269 larger than the cost of any constant we want to synthesize in-line. */
2270
2271 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2272
2273 /* A C expression for the cost of moving data from a register in
2274 class FROM to one in class TO. The classes are expressed using
2275 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2276 the default; other values are interpreted relative to that.
2277
2278 It is not required that the cost always equal 2 when FROM is the
2279 same as TO; on some machines it is expensive to move between
2280 registers if they are not general registers.
2281
2282 If reload sees an insn consisting of a single `set' between two
2283 hard registers, and if `REGISTER_MOVE_COST' applied to their
2284 classes returns a value of 2, reload does not check to ensure
2285 that the constraints of the insn are met. Setting a cost of
2286 other than 2 will allow reload to verify that the constraints are
2287 met. You should do this if the `movM' pattern's constraints do
2288 not allow such copying. */
2289
2290 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2291 mips_register_move_cost (MODE, FROM, TO)
2292
2293 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2294 (mips_cost->memory_latency \
2295 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2296
2297 /* Define if copies to/from condition code registers should be avoided.
2298
2299 This is needed for the MIPS because reload_outcc is not complete;
2300 it needs to handle cases where the source is a general or another
2301 condition code register. */
2302 #define AVOID_CCMODE_COPIES
2303
2304 /* A C expression for the cost of a branch instruction. A value of
2305 1 is the default; other values are interpreted relative to that. */
2306
2307 #define BRANCH_COST mips_cost->branch_cost
2308 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2309
2310 /* If defined, modifies the length assigned to instruction INSN as a
2311 function of the context in which it is used. LENGTH is an lvalue
2312 that contains the initially computed length of the insn and should
2313 be updated with the correct length of the insn. */
2314 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2315 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2316
2317 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2318 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2319 its operands. */
2320 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2321 "%*" OPCODE "%?\t" OPERANDS "%/"
2322
2323 /* Return the asm template for a call. INSN is the instruction's mnemonic
2324 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2325 of the target.
2326
2327 When generating GOT code without explicit relocation operators,
2328 all calls should use assembly macros. Otherwise, all indirect
2329 calls should use "jr" or "jalr"; we will arrange to restore $gp
2330 afterwards if necessary. Finally, we can only generate direct
2331 calls for -mabicalls by temporarily switching to non-PIC mode. */
2332 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2333 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2334 ? "%*" INSN "\t%" #OPNO "%/" \
2335 : REG_P (OPERANDS[OPNO]) \
2336 ? "%*" INSN "r\t%" #OPNO "%/" \
2337 : TARGET_ABICALLS \
2338 ? (".option\tpic0\n\t" \
2339 "%*" INSN "\t%" #OPNO "%/\n\t" \
2340 ".option\tpic2") \
2341 : "%*" INSN "\t%" #OPNO "%/")
2342 \f
2343 /* Control the assembler format that we output. */
2344
2345 /* Output to assembler file text saying following lines
2346 may contain character constants, extra white space, comments, etc. */
2347
2348 #ifndef ASM_APP_ON
2349 #define ASM_APP_ON " #APP\n"
2350 #endif
2351
2352 /* Output to assembler file text saying following lines
2353 no longer contain unusual constructs. */
2354
2355 #ifndef ASM_APP_OFF
2356 #define ASM_APP_OFF " #NO_APP\n"
2357 #endif
2358
2359 #define REGISTER_NAMES \
2360 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2361 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2362 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2363 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2364 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2365 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2366 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2367 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2368 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2369 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2370 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2371 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2372 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2373 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2374 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2375 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2376 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2377 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2378 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2379 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2380 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2381 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2382 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2383 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2384
2385 /* List the "software" names for each register. Also list the numerical
2386 names for $fp and $sp. */
2387
2388 #define ADDITIONAL_REGISTER_NAMES \
2389 { \
2390 { "$29", 29 + GP_REG_FIRST }, \
2391 { "$30", 30 + GP_REG_FIRST }, \
2392 { "at", 1 + GP_REG_FIRST }, \
2393 { "v0", 2 + GP_REG_FIRST }, \
2394 { "v1", 3 + GP_REG_FIRST }, \
2395 { "a0", 4 + GP_REG_FIRST }, \
2396 { "a1", 5 + GP_REG_FIRST }, \
2397 { "a2", 6 + GP_REG_FIRST }, \
2398 { "a3", 7 + GP_REG_FIRST }, \
2399 { "t0", 8 + GP_REG_FIRST }, \
2400 { "t1", 9 + GP_REG_FIRST }, \
2401 { "t2", 10 + GP_REG_FIRST }, \
2402 { "t3", 11 + GP_REG_FIRST }, \
2403 { "t4", 12 + GP_REG_FIRST }, \
2404 { "t5", 13 + GP_REG_FIRST }, \
2405 { "t6", 14 + GP_REG_FIRST }, \
2406 { "t7", 15 + GP_REG_FIRST }, \
2407 { "s0", 16 + GP_REG_FIRST }, \
2408 { "s1", 17 + GP_REG_FIRST }, \
2409 { "s2", 18 + GP_REG_FIRST }, \
2410 { "s3", 19 + GP_REG_FIRST }, \
2411 { "s4", 20 + GP_REG_FIRST }, \
2412 { "s5", 21 + GP_REG_FIRST }, \
2413 { "s6", 22 + GP_REG_FIRST }, \
2414 { "s7", 23 + GP_REG_FIRST }, \
2415 { "t8", 24 + GP_REG_FIRST }, \
2416 { "t9", 25 + GP_REG_FIRST }, \
2417 { "k0", 26 + GP_REG_FIRST }, \
2418 { "k1", 27 + GP_REG_FIRST }, \
2419 { "gp", 28 + GP_REG_FIRST }, \
2420 { "sp", 29 + GP_REG_FIRST }, \
2421 { "fp", 30 + GP_REG_FIRST }, \
2422 { "ra", 31 + GP_REG_FIRST }, \
2423 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2424 }
2425
2426 /* This is meant to be redefined in the host dependent files. It is a
2427 set of alternative names and regnums for mips coprocessors. */
2428
2429 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2430
2431 /* A C compound statement to output to stdio stream STREAM the
2432 assembler syntax for an instruction operand X. X is an RTL
2433 expression.
2434
2435 CODE is a value that can be used to specify one of several ways
2436 of printing the operand. It is used when identical operands
2437 must be printed differently depending on the context. CODE
2438 comes from the `%' specification that was used to request
2439 printing of the operand. If the specification was just `%DIGIT'
2440 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2441 is the ASCII code for LTR.
2442
2443 If X is a register, this macro should print the register's name.
2444 The names can be found in an array `reg_names' whose type is
2445 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2446
2447 When the machine description has a specification `%PUNCT' (a `%'
2448 followed by a punctuation character), this macro is called with
2449 a null pointer for X and the punctuation character for CODE.
2450
2451 See mips.c for the MIPS specific codes. */
2452
2453 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2454
2455 /* A C expression which evaluates to true if CODE is a valid
2456 punctuation character for use in the `PRINT_OPERAND' macro. If
2457 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2458 punctuation characters (except for the standard one, `%') are
2459 used in this way. */
2460
2461 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2462
2463 /* A C compound statement to output to stdio stream STREAM the
2464 assembler syntax for an instruction operand that is a memory
2465 reference whose address is ADDR. ADDR is an RTL expression. */
2466
2467 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2468
2469
2470 /* A C statement, to be executed after all slot-filler instructions
2471 have been output. If necessary, call `dbr_sequence_length' to
2472 determine the number of slots filled in a sequence (zero if not
2473 currently outputting a sequence), to decide how many no-ops to
2474 output, or whatever.
2475
2476 Don't define this macro if it has nothing to do, but it is
2477 helpful in reading assembly output if the extent of the delay
2478 sequence is made explicit (e.g. with white space).
2479
2480 Note that output routines for instructions with delay slots must
2481 be prepared to deal with not being output as part of a sequence
2482 (i.e. when the scheduling pass is not run, or when no slot
2483 fillers could be found.) The variable `final_sequence' is null
2484 when not processing a sequence, otherwise it contains the
2485 `sequence' rtx being output. */
2486
2487 #define DBR_OUTPUT_SEQEND(STREAM) \
2488 do \
2489 { \
2490 if (set_nomacro > 0 && --set_nomacro == 0) \
2491 fputs ("\t.set\tmacro\n", STREAM); \
2492 \
2493 if (set_noreorder > 0 && --set_noreorder == 0) \
2494 fputs ("\t.set\treorder\n", STREAM); \
2495 \
2496 fputs ("\n", STREAM); \
2497 } \
2498 while (0)
2499
2500
2501 /* How to tell the debugger about changes of source files. */
2502 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2503 mips_output_filename (STREAM, NAME)
2504
2505 /* mips-tfile does not understand .stabd directives. */
2506 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2507 dbxout_begin_stabn_sline (LINE); \
2508 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2509 } while (0)
2510
2511 /* Use .loc directives for SDB line numbers. */
2512 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2513 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2514
2515 /* The MIPS implementation uses some labels for its own purpose. The
2516 following lists what labels are created, and are all formed by the
2517 pattern $L[a-z].*. The machine independent portion of GCC creates
2518 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2519
2520 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2521 $Lb[0-9]+ Begin blocks for MIPS debug support
2522 $Lc[0-9]+ Label for use in s<xx> operation.
2523 $Le[0-9]+ End blocks for MIPS debug support */
2524
2525 #undef ASM_DECLARE_OBJECT_NAME
2526 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2527 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2528
2529 /* Globalizing directive for a label. */
2530 #define GLOBAL_ASM_OP "\t.globl\t"
2531
2532 /* This says how to define a global common symbol. */
2533
2534 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2535
2536 /* This says how to define a local common symbol (i.e., not visible to
2537 linker). */
2538
2539 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2540 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2541 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2542 #endif
2543
2544 /* This says how to output an external. It would be possible not to
2545 output anything and let undefined symbol become external. However
2546 the assembler uses length information on externals to allocate in
2547 data/sdata bss/sbss, thereby saving exec time. */
2548
2549 #undef ASM_OUTPUT_EXTERNAL
2550 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2551 mips_output_external(STREAM,DECL,NAME)
2552
2553 /* This is how to declare a function name. The actual work of
2554 emitting the label is moved to function_prologue, so that we can
2555 get the line number correctly emitted before the .ent directive,
2556 and after any .file directives. Define as empty so that the function
2557 is not declared before the .ent directive elsewhere. */
2558
2559 #undef ASM_DECLARE_FUNCTION_NAME
2560 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2561
2562 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2563 #define FUNCTION_NAME_ALREADY_DECLARED 0
2564 #endif
2565
2566 /* This is how to store into the string LABEL
2567 the symbol_ref name of an internal numbered label where
2568 PREFIX is the class of label and NUM is the number within the class.
2569 This is suitable for output with `assemble_name'. */
2570
2571 #undef ASM_GENERATE_INTERNAL_LABEL
2572 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2573 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2574
2575 /* This is how to output an element of a case-vector that is absolute. */
2576
2577 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2578 fprintf (STREAM, "\t%s\t%sL%d\n", \
2579 ptr_mode == DImode ? ".dword" : ".word", \
2580 LOCAL_LABEL_PREFIX, \
2581 VALUE)
2582
2583 /* This is how to output an element of a case-vector. We can make the
2584 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2585 is supported. */
2586
2587 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2588 do { \
2589 if (TARGET_MIPS16) \
2590 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2591 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2592 else if (TARGET_GPWORD) \
2593 fprintf (STREAM, "\t%s\t%sL%d\n", \
2594 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2595 LOCAL_LABEL_PREFIX, VALUE); \
2596 else if (TARGET_RTP_PIC) \
2597 { \
2598 /* Make the entry relative to the start of the function. */ \
2599 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2600 fprintf (STREAM, "\t%s\t%sL%d-", \
2601 Pmode == DImode ? ".dword" : ".word", \
2602 LOCAL_LABEL_PREFIX, VALUE); \
2603 assemble_name (STREAM, XSTR (fnsym, 0)); \
2604 fprintf (STREAM, "\n"); \
2605 } \
2606 else \
2607 fprintf (STREAM, "\t%s\t%sL%d\n", \
2608 ptr_mode == DImode ? ".dword" : ".word", \
2609 LOCAL_LABEL_PREFIX, VALUE); \
2610 } while (0)
2611
2612 /* When generating MIPS16 code, we want the jump table to be in the text
2613 section so that we can load its address using a PC-relative addition. */
2614 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16
2615
2616 /* This is how to output an assembler line
2617 that says to advance the location counter
2618 to a multiple of 2**LOG bytes. */
2619
2620 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2621 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2622
2623 /* This is how to output an assembler line to advance the location
2624 counter by SIZE bytes. */
2625
2626 #undef ASM_OUTPUT_SKIP
2627 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2628 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2629
2630 /* This is how to output a string. */
2631 #undef ASM_OUTPUT_ASCII
2632 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2633 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2634
2635 /* Output #ident as a in the read-only data section. */
2636 #undef ASM_OUTPUT_IDENT
2637 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2638 { \
2639 const char *p = STRING; \
2640 int size = strlen (p) + 1; \
2641 switch_to_section (readonly_data_section); \
2642 assemble_string (p, size); \
2643 }
2644 \f
2645 /* Default to -G 8 */
2646 #ifndef MIPS_DEFAULT_GVALUE
2647 #define MIPS_DEFAULT_GVALUE 8
2648 #endif
2649
2650 /* Define the strings to put out for each section in the object file. */
2651 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2652 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2653
2654 #undef READONLY_DATA_SECTION_ASM_OP
2655 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2656 \f
2657 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2658 do \
2659 { \
2660 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2661 TARGET_64BIT ? "dsubu" : "subu", \
2662 reg_names[STACK_POINTER_REGNUM], \
2663 reg_names[STACK_POINTER_REGNUM], \
2664 TARGET_64BIT ? "sd" : "sw", \
2665 reg_names[REGNO], \
2666 reg_names[STACK_POINTER_REGNUM]); \
2667 } \
2668 while (0)
2669
2670 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2671 do \
2672 { \
2673 if (! set_noreorder) \
2674 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2675 \
2676 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2677 TARGET_64BIT ? "ld" : "lw", \
2678 reg_names[REGNO], \
2679 reg_names[STACK_POINTER_REGNUM], \
2680 TARGET_64BIT ? "daddu" : "addu", \
2681 reg_names[STACK_POINTER_REGNUM], \
2682 reg_names[STACK_POINTER_REGNUM]); \
2683 \
2684 if (! set_noreorder) \
2685 fprintf (STREAM, "\t.set\treorder\n"); \
2686 } \
2687 while (0)
2688
2689 /* How to start an assembler comment.
2690 The leading space is important (the mips native assembler requires it). */
2691 #ifndef ASM_COMMENT_START
2692 #define ASM_COMMENT_START " #"
2693 #endif
2694 \f
2695 /* Default definitions for size_t and ptrdiff_t. We must override the
2696 definitions from ../svr4.h on mips-*-linux-gnu. */
2697
2698 #undef SIZE_TYPE
2699 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2700
2701 #undef PTRDIFF_TYPE
2702 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2703 \f
2704 #ifndef __mips16
2705 /* Since the bits of the _init and _fini function is spread across
2706 many object files, each potentially with its own GP, we must assume
2707 we need to load our GP. We don't preserve $gp or $ra, since each
2708 init/fini chunk is supposed to initialize $gp, and crti/crtn
2709 already take care of preserving $ra and, when appropriate, $gp. */
2710 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2711 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2712 asm (SECTION_OP "\n\
2713 .set noreorder\n\
2714 bal 1f\n\
2715 nop\n\
2716 1: .cpload $31\n\
2717 .set reorder\n\
2718 jal " USER_LABEL_PREFIX #FUNC "\n\
2719 " TEXT_SECTION_ASM_OP);
2720 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2721 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2722 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2723 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2724 asm (SECTION_OP "\n\
2725 .set noreorder\n\
2726 bal 1f\n\
2727 nop\n\
2728 1: .set reorder\n\
2729 .cpsetup $31, $2, 1b\n\
2730 jal " USER_LABEL_PREFIX #FUNC "\n\
2731 " TEXT_SECTION_ASM_OP);
2732 #endif
2733 #endif
2734
2735 #ifndef HAVE_AS_TLS
2736 #define HAVE_AS_TLS 0
2737 #endif