gcc/config/mips/mips.h

   1 /* Definitions of target machine for GNU compiler.  MIPS version.
   2    Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
   3    1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   4    Contributed by A. Lichnewsky (lich@inria.inria.fr).
   5    Changed by Michael Meissner  (meissner@osf.org).
   6    64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
   7    Brendan Eich (brendan@microunity.com).
   8
   9 This file is part of GNU CC.
  10
  11 GNU CC is free software; you can redistribute it and/or modify
  12 it under the terms of the GNU General Public License as published by
  13 the Free Software Foundation; either version 2, or (at your option)
  14 any later version.
  15
  16 GNU CC is distributed in the hope that it will be useful,
  17 but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 GNU General Public License for more details.
  20
  21 You should have received a copy of the GNU General Public License
  22 along with GNU CC; see the file COPYING.  If not, write to
  23 the Free Software Foundation, 59 Temple Place - Suite 330,
  24 Boston, MA 02111-1307, USA.  */
  25
  26
  27 /* Standard GCC variables that we reference.  */
  28
  29 extern char    *asm_file_name;
  30 extern char     call_used_regs[];
  31 extern int      may_call_alloca;
  32 extern char   **save_argv;
  33 extern int      target_flags;
  34
  35 /* MIPS external variables defined in mips.c.  */
  36
  37 /* comparison type */
  38 enum cmp_type {
  39   CMP_SI,                               /* compare four byte integers */
  40   CMP_DI,                               /* compare eight byte integers */
  41   CMP_SF,                               /* compare single precision floats */
  42   CMP_DF,                               /* compare double precision floats */
  43   CMP_MAX                               /* max comparison type */
  44 };
  45
  46 /* types of delay slot */
  47 enum delay_type {
  48   DELAY_NONE,                           /* no delay slot */
  49   DELAY_LOAD,                           /* load from memory delay */
  50   DELAY_HILO,                           /* move from/to hi/lo registers */
  51   DELAY_FCMP                            /* delay after doing c.<xx>.{d,s} */
  52 };
  53
  54 /* Which processor to schedule for.  Since there is no difference between
  55    a R2000 and R3000 in terms of the scheduler, we collapse them into
  56    just an R3000.  The elements of the enumeration must match exactly
  57    the cpu attribute in the mips.md machine description.  */
  58
  59 enum processor_type {
  60   PROCESSOR_DEFAULT,
  61   PROCESSOR_R3000,
  62   PROCESSOR_R3900,
  63   PROCESSOR_R6000,
  64   PROCESSOR_R4000,
  65   PROCESSOR_R4100,
  66   PROCESSOR_R4300,
  67   PROCESSOR_R4600,
  68   PROCESSOR_R4650,
  69   PROCESSOR_R5000,
  70   PROCESSOR_R8000,
  71   PROCESSOR_R4KC,
  72   PROCESSOR_R5KC,
  73   PROCESSOR_R20KC
  74 };
  75
  76 /* Recast the cpu class to be the cpu attribute.  */
  77 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
  78
  79 /* Which ABI to use.  These are constants because abi64.h must check their
  80    value at preprocessing time.
  81
  82    ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
  83    defined by SGI.  ABI_O64 is o32 extended to work on a 64 bit machine.  */
  84
  85 #define ABI_32  0
  86 #define ABI_N32 1
  87 #define ABI_64  2
  88 #define ABI_EABI 3
  89 #define ABI_O64  4
  90 /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
  91    which is not the same as the above EABI (defined by Cygnus,
  92    Greenhills, and Toshiba?).  MEABI is not yet complete or published,
  93    but at this point it looks like N32 as far as calling conventions go,
  94    but allows for either 32 or 64 bit registers.
  95
  96    Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
  97    EABI the legacy EABI.  In the end we may end up calling both ABI's
  98    EABI but give them different version numbers, but for now I'm going
  99    with different names.  */
 100 #define ABI_MEABI 5
 101
 102 /* Whether to emit abicalls code sequences or not.  */
 103
 104 enum mips_abicalls_type {
 105   MIPS_ABICALLS_NO,
 106   MIPS_ABICALLS_YES
 107 };
 108
 109 /* Recast the abicalls class to be the abicalls attribute.  */
 110 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
 111
 112 /* Which type of block move to do (whether or not the last store is
 113    split out so it can fill a branch delay slot).  */
 114
 115 enum block_move_type {
 116   BLOCK_MOVE_NORMAL,                    /* generate complete block move */
 117   BLOCK_MOVE_NOT_LAST,                  /* generate all but last store */
 118   BLOCK_MOVE_LAST                       /* generate just the last store */
 119 };
 120
 121 extern char mips_reg_names[][8];        /* register names (a0 vs. $4).  */
 122 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
 123 extern const char *current_function_file; /* filename current function is in */
 124 extern int num_source_filenames;        /* current .file # */
 125 extern int inside_function;             /* != 0 if inside of a function */
 126 extern int ignore_line_number;          /* != 0 if we are to ignore next .loc */
 127 extern int file_in_function_warning;    /* warning given about .file in func */
 128 extern int sdb_label_count;             /* block start/end next label # */
 129 extern int sdb_begin_function_line;     /* Starting Line of current function */
 130 extern int mips_section_threshold;      /* # bytes of data/sdata cutoff */
 131 extern int g_switch_value;              /* value of the -G xx switch */
 132 extern int g_switch_set;                /* whether -G xx was passed.  */
 133 extern int sym_lineno;                  /* sgi next label # for each stmt */
 134 extern int set_noreorder;               /* # of nested .set noreorder's  */
 135 extern int set_nomacro;                 /* # of nested .set nomacro's  */
 136 extern int set_noat;                    /* # of nested .set noat's  */
 137 extern int set_volatile;                /* # of nested .set volatile's  */
 138 extern int mips_branch_likely;          /* emit 'l' after br (branch likely) */
 139 extern int mips_dbx_regno[];            /* Map register # to debug register # */
 140 extern GTY(()) rtx branch_cmp[2];       /* operands for compare */
 141 extern enum cmp_type branch_type;       /* what type of branch to use */
 142 extern enum processor_type mips_arch;   /* which cpu to codegen for */
 143 extern enum processor_type mips_tune;   /* which cpu to schedule for */
 144 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
 145 extern int mips_isa;                    /* architectural level */
 146 extern int mips16;                      /* whether generating mips16 code */
 147 extern int mips16_hard_float;           /* mips16 without -msoft-float */
 148 extern int mips_entry;                  /* generate entry/exit for mips16 */
 149 extern const char *mips_cpu_string;     /* for -mcpu=<xxx> */
 150 extern const char *mips_arch_string;    /* for -march=<xxx> */
 151 extern const char *mips_tune_string;    /* for -mtune=<xxx> */
 152 extern const char *mips_isa_string;     /* for -mips{1,2,3,4} */
 153 extern const char *mips_abi_string;     /* for -mabi={32,n32,64} */
 154 extern const char *mips_entry_string;   /* for -mentry */
 155 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
 156 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
 157 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
 158 extern int mips_split_addresses;        /* perform high/lo_sum support */
 159 extern int dslots_load_total;           /* total # load related delay slots */
 160 extern int dslots_load_filled;          /* # filled load delay slots */
 161 extern int dslots_jump_total;           /* total # jump related delay slots */
 162 extern int dslots_jump_filled;          /* # filled jump delay slots */
 163 extern int dslots_number_nops;          /* # of nops needed by previous insn */
 164 extern int num_refs[3];                 /* # 1/2/3 word references */
 165 extern GTY(()) rtx mips_load_reg;       /* register to check for load delay */
 166 extern GTY(()) rtx mips_load_reg2;      /* 2nd reg to check for load delay */
 167 extern GTY(()) rtx mips_load_reg3;      /* 3rd reg to check for load delay */
 168 extern GTY(()) rtx mips_load_reg4;      /* 4th reg to check for load delay */
 169 extern int mips_string_length;          /* length of strings for mips16 */
 170
 171 /* Functions to change what output section we are using.  */
 172 extern void             sdata_section PARAMS ((void));
 173 extern void             sbss_section PARAMS ((void));
 174
 175 /* Macros to silence warnings about numbers being signed in traditional
 176    C and unsigned in ISO C when compiled on 32-bit hosts.  */
 177
 178 #define BITMASK_HIGH    (((unsigned long)1) << 31)      /* 0x80000000 */
 179 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16)   /* 0xffff0000 */
 180 #define BITMASK_LOWER16 ((unsigned long)0xffff)         /* 0x0000ffff */
 181
 182 \f
 183 /* Run-time compilation parameters selecting different hardware subsets.  */
 184
 185 /* Macros used in the machine description to test the flags.  */
 186
 187                                         /* Bits for real switches */
 188 #define MASK_INT64         0x00000001   /* ints are 64 bits */
 189 #define MASK_LONG64        0x00000002   /* longs are 64 bits */
 190 #define MASK_SPLIT_ADDR    0x00000004   /* Address splitting is enabled.  */
 191 #define MASK_GPOPT         0x00000008   /* Optimize for global pointer */
 192 #define MASK_GAS           0x00000010   /* Gas used instead of MIPS as */
 193 #define MASK_NAME_REGS     0x00000020   /* Use MIPS s/w reg name convention */
 194 #define MASK_STATS         0x00000040   /* print statistics to stderr */
 195 #define MASK_MEMCPY        0x00000080   /* call memcpy instead of inline code*/
 196 #define MASK_SOFT_FLOAT    0x00000100   /* software floating point */
 197 #define MASK_FLOAT64       0x00000200   /* fp registers are 64 bits */
 198 #define MASK_ABICALLS      0x00000400   /* emit .abicalls/.cprestore/.cpload */
 199 #define MASK_UNUSED1       0x00000800   /* Unused Mask.  */
 200 #define MASK_LONG_CALLS    0x00001000   /* Always call through a register */
 201 #define MASK_64BIT         0x00002000   /* Use 64 bit GP registers and insns */
 202 #define MASK_EMBEDDED_PIC  0x00004000   /* Generate embedded PIC code */
 203 #define MASK_EMBEDDED_DATA 0x00008000   /* Reduce RAM usage, not fast code */
 204 #define MASK_BIG_ENDIAN    0x00010000   /* Generate big endian code */
 205 #define MASK_SINGLE_FLOAT  0x00020000   /* Only single precision FPU.  */
 206 #define MASK_MAD           0x00040000   /* Generate mad/madu as on 4650.  */
 207 #define MASK_4300_MUL_FIX  0x00080000   /* Work-around early Vr4300 CPU bug */
 208 #define MASK_MIPS16        0x00100000   /* Generate mips16 code */
 209 #define MASK_NO_CHECK_ZERO_DIV \
 210                            0x00200000   /* divide by zero checking */
 211 #define MASK_CHECK_RANGE_DIV \
 212                            0x00400000   /* divide result range checking */
 213 #define MASK_UNINIT_CONST_IN_RODATA \
 214                            0x00800000   /* Store uninitialized
 215                                            consts in rodata */
 216 #define MASK_NO_FUSED_MADD 0x01000000   /* Don't generate floating point
 217                                            multiply-add operations.  */
 218
 219                                         /* Debug switches, not documented */
 220 #define MASK_DEBUG      0               /* unused */
 221 #define MASK_DEBUG_A    0               /* don't allow <label>($reg) addrs */
 222 #define MASK_DEBUG_B    0               /* GO_IF_LEGITIMATE_ADDRESS debug */
 223 #define MASK_DEBUG_C    0               /* don't expand seq, etc.  */
 224 #define MASK_DEBUG_D    0               /* don't do define_split's */
 225 #define MASK_DEBUG_E    0               /* function_arg debug */
 226 #define MASK_DEBUG_F    0               /* ??? */
 227 #define MASK_DEBUG_G    0               /* don't support 64 bit arithmetic */
 228 #define MASK_DEBUG_H    0               /* allow ints in FP registers */
 229 #define MASK_DEBUG_I    0               /* unused */
 230
 231                                         /* Dummy switches used only in specs */
 232 #define MASK_MIPS_TFILE 0               /* flag for mips-tfile usage */
 233
 234                                         /* r4000 64 bit sizes */
 235 #define TARGET_INT64            (target_flags & MASK_INT64)
 236 #define TARGET_LONG64           (target_flags & MASK_LONG64)
 237 #define TARGET_FLOAT64          (target_flags & MASK_FLOAT64)
 238 #define TARGET_64BIT            (target_flags & MASK_64BIT)
 239
 240                                         /* Mips vs. GNU linker */
 241 #define TARGET_SPLIT_ADDRESSES  (target_flags & MASK_SPLIT_ADDR)
 242
 243                                         /* Mips vs. GNU assembler */
 244 #define TARGET_GAS              (target_flags & MASK_GAS)
 245 #define TARGET_MIPS_AS          (!TARGET_GAS)
 246
 247                                         /* Debug Modes */
 248 #define TARGET_DEBUG_MODE       (target_flags & MASK_DEBUG)
 249 #define TARGET_DEBUG_A_MODE     (target_flags & MASK_DEBUG_A)
 250 #define TARGET_DEBUG_B_MODE     (target_flags & MASK_DEBUG_B)
 251 #define TARGET_DEBUG_C_MODE     (target_flags & MASK_DEBUG_C)
 252 #define TARGET_DEBUG_D_MODE     (target_flags & MASK_DEBUG_D)
 253 #define TARGET_DEBUG_E_MODE     (target_flags & MASK_DEBUG_E)
 254 #define TARGET_DEBUG_F_MODE     (target_flags & MASK_DEBUG_F)
 255 #define TARGET_DEBUG_G_MODE     (target_flags & MASK_DEBUG_G)
 256 #define TARGET_DEBUG_H_MODE     (target_flags & MASK_DEBUG_H)
 257 #define TARGET_DEBUG_I_MODE     (target_flags & MASK_DEBUG_I)
 258
 259                                         /* Reg. Naming in .s ($21 vs. $a0) */
 260 #define TARGET_NAME_REGS        (target_flags & MASK_NAME_REGS)
 261
 262                                         /* Optimize for Sdata/Sbss */
 263 #define TARGET_GP_OPT           (target_flags & MASK_GPOPT)
 264
 265                                         /* print program statistics */
 266 #define TARGET_STATS            (target_flags & MASK_STATS)
 267
 268                                         /* call memcpy instead of inline code */
 269 #define TARGET_MEMCPY           (target_flags & MASK_MEMCPY)
 270
 271                                         /* .abicalls, etc from Pyramid V.4 */
 272 #define TARGET_ABICALLS         (target_flags & MASK_ABICALLS)
 273
 274                                         /* software floating point */
 275 #define TARGET_SOFT_FLOAT       (target_flags & MASK_SOFT_FLOAT)
 276 #define TARGET_HARD_FLOAT       (! TARGET_SOFT_FLOAT)
 277
 278                                         /* always call through a register */
 279 #define TARGET_LONG_CALLS       (target_flags & MASK_LONG_CALLS)
 280
 281                                         /* generate embedded PIC code;
 282                                            requires gas.  */
 283 #define TARGET_EMBEDDED_PIC     (target_flags & MASK_EMBEDDED_PIC)
 284
 285                                         /* for embedded systems, optimize for
 286                                            reduced RAM space instead of for
 287                                            fastest code.  */
 288 #define TARGET_EMBEDDED_DATA    (target_flags & MASK_EMBEDDED_DATA)
 289
 290                                         /* always store uninitialized const
 291                                            variables in rodata, requires
 292                                            TARGET_EMBEDDED_DATA.  */
 293 #define TARGET_UNINIT_CONST_IN_RODATA   (target_flags & MASK_UNINIT_CONST_IN_RODATA)
 294
 295                                         /* generate big endian code.  */
 296 #define TARGET_BIG_ENDIAN       (target_flags & MASK_BIG_ENDIAN)
 297
 298 #define TARGET_SINGLE_FLOAT     (target_flags & MASK_SINGLE_FLOAT)
 299 #define TARGET_DOUBLE_FLOAT     (! TARGET_SINGLE_FLOAT)
 300
 301 #define TARGET_MAD              (target_flags & MASK_MAD)
 302
 303 #define TARGET_FUSED_MADD       (! (target_flags & MASK_NO_FUSED_MADD))
 304
 305 #define TARGET_4300_MUL_FIX     (target_flags & MASK_4300_MUL_FIX)
 306
 307 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
 308 #define TARGET_CHECK_RANGE_DIV  (target_flags & MASK_CHECK_RANGE_DIV)
 309
 310 /* This is true if we must enable the assembly language file switching
 311    code.  */
 312
 313 #define TARGET_FILE_SWITCHING \
 314   (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
 315
 316 /* We must disable the function end stabs when doing the file switching trick,
 317    because the Lscope stabs end up in the wrong place, making it impossible
 318    to debug the resulting code.  */
 319 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
 320
 321                                         /* Generate mips16 code */
 322 #define TARGET_MIPS16           (target_flags & MASK_MIPS16)
 323
 324 /* Generic ISA defines.  */
 325 #define ISA_MIPS1                   (mips_isa == 1)
 326 #define ISA_MIPS2                   (mips_isa == 2)
 327 #define ISA_MIPS3                   (mips_isa == 3)
 328 #define ISA_MIPS4                   (mips_isa == 4)
 329 #define ISA_MIPS32                  (mips_isa == 32)
 330 #define ISA_MIPS64                  (mips_isa == 64)
 331
 332 /* Architecture target defines.  */
 333 #define TARGET_MIPS3900             (mips_arch == PROCESSOR_R3900)
 334 #define TARGET_MIPS4000             (mips_arch == PROCESSOR_R4000)
 335 #define TARGET_MIPS4100             (mips_arch == PROCESSOR_R4100)
 336 #define TARGET_MIPS4300             (mips_arch == PROCESSOR_R4300)
 337 #define TARGET_MIPS4KC              (mips_arch == PROCESSOR_R4KC)
 338 #define TARGET_MIPS5KC              (mips_arch == PROCESSOR_R5KC)
 339
 340 /* Scheduling target defines.  */
 341 #define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)
 342 #define TUNE_MIPS3900               (mips_tune == PROCESSOR_R3900)
 343 #define TUNE_MIPS4000               (mips_tune == PROCESSOR_R4000)
 344 #define TUNE_MIPS5000               (mips_tune == PROCESSOR_R5000)
 345 #define TUNE_MIPS6000               (mips_tune == PROCESSOR_R6000)
 346
 347 /* Target CPU builtins.  */
 348 #define TARGET_CPU_CPP_BUILTINS()                               \
 349   do                                                            \
 350     {                                                           \
 351       builtin_assert ("cpu=mips");                              \
 352       builtin_define ("__mips__");                              \
 353       builtin_define ("_mips");                                 \
 354                                                                 \
 355       /* We do this here because __mips is defined below        \
 356          and so we can't use builtin_define_std.  */            \
 357       if (!flag_iso)                                            \
 358           builtin_define ("mips");                              \
 359                                                                 \
 360       if (TARGET_64BIT)                                         \
 361         {                                                       \
 362           builtin_define ("__mips64");                          \
 363           /* Silly, but will do until processor defines.  */    \
 364           builtin_define_std ("R4000");                         \
 365           builtin_define ("_R4000");                            \
 366         }                                                       \
 367       else                                                      \
 368         {                                                       \
 369           /* Ditto.  */                                         \
 370           builtin_define_std ("R3000");                         \
 371           builtin_define ("_R3000");                            \
 372         }                                                       \
 373       if (TARGET_FLOAT64)                                       \
 374           builtin_define ("__mips_fpr=64");                     \
 375       else                                                      \
 376           builtin_define ("__mips_fpr=32");                     \
 377                                                                 \
 378       if (TARGET_MIPS16)                                        \
 379           builtin_define ("__mips16");                          \
 380                                                                 \
 381       if (ISA_MIPS1)                                            \
 382         {                                                       \
 383           builtin_define ("__mips=1");                          \
 384           builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1");         \
 385         }                                                       \
 386       else if (ISA_MIPS2)                                       \
 387         {                                                       \
 388           builtin_define ("__mips=2");                          \
 389           builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2");         \
 390         }                                                       \
 391       else if (ISA_MIPS3)                                       \
 392         {                                                       \
 393           builtin_define ("__mips=3");                          \
 394           builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3");         \
 395         }                                                       \
 396       else if (ISA_MIPS4)                                       \
 397         {                                                       \
 398           builtin_define ("__mips=4");                          \
 399           builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4");         \
 400         }                                                       \
 401       else if (ISA_MIPS32)                                      \
 402         {                                                       \
 403           builtin_define ("__mips=32");                         \
 404           builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32");        \
 405         }                                                       \
 406       else if (ISA_MIPS64)                                      \
 407         {                                                       \
 408           builtin_define ("__mips=64");                         \
 409           builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64");        \
 410         }                                                       \
 411                                                                 \
 412       if (TARGET_HARD_FLOAT)                                    \
 413           builtin_define ("__mips_hard_float");                 \
 414       else if (TARGET_SOFT_FLOAT)                               \
 415           builtin_define ("__mips_soft_float");                 \
 416                                                                 \
 417       if (TARGET_SINGLE_FLOAT)                                  \
 418           builtin_define ("__mips_single_float");               \
 419                                                                 \
 420       if (TARGET_BIG_ENDIAN)                                    \
 421         {                                                       \
 422           builtin_define_std ("MIPSEB");                        \
 423           builtin_define ("_MIPSEB");                           \
 424         }                                                       \
 425       else                                                      \
 426         {                                                       \
 427           builtin_define_std ("MIPSEL");                        \
 428           builtin_define ("_MIPSEL");                           \
 429         }                                                       \
 430                                                                 \
 431         /* Macros dependent on the C dialect.  */               \
 432       if (preprocessing_asm_p ())                               \
 433         {                                                       \
 434           builtin_define_std ("LANGUAGE_ASSEMBLY");             \
 435           builtin_define ("_LANGUAGE_ASSEMBLY");                \
 436         }                                                       \
 437       else if (c_language == clk_c)                             \
 438         {                                                       \
 439           builtin_define_std ("LANGUAGE_C");                    \
 440           builtin_define ("_LANGUAGE_C");                       \
 441         }                                                       \
 442       else if (c_language == clk_cplusplus)                     \
 443         {                                                       \
 444           builtin_define ("_LANGUAGE_C_PLUS_PLUS");             \
 445           builtin_define ("__LANGUAGE_C_PLUS_PLUS");            \
 446           builtin_define ("__LANGUAGE_C_PLUS_PLUS__");          \
 447         }                                                       \
 448       else if (c_language == clk_objective_c)                   \
 449         {                                                       \
 450           builtin_define ("_LANGUAGE_OBJECTIVE_C");             \
 451           builtin_define ("__LANGUAGE_OBJECTIVE_C");            \
 452           /* Bizzare, but needed at least for Irix.  */         \
 453           builtin_define_std ("LANGUAGE_C");                    \
 454           builtin_define ("_LANGUAGE_C");                       \
 455         }                                                       \
 456                                                                 \
 457       if (mips_abi == ABI_EABI)                                 \
 458         builtin_define ("__mips_eabi");                         \
 459                                                                 \
 460 } while (0)
 461
 462
 463
 464 /* Macro to define tables used to set the flags.
 465    This is a list in braces of pairs in braces,
 466    each pair being { "NAME", VALUE }
 467    where VALUE is the bits to set or minus the bits to clear.
 468    An empty string NAME is used to identify the default VALUE.  */
 469
 470 #define TARGET_SWITCHES                                                 \
 471 {                                                                       \
 472   {"no-crt0",          0,                                               \
 473      N_("No default crt0.o") },                                         \
 474   {"int64",               MASK_INT64 | MASK_LONG64,                     \
 475      N_("Use 64-bit int type")},                                        \
 476   {"long64",              MASK_LONG64,                                  \
 477      N_("Use 64-bit long type")},                                       \
 478   {"long32",             -(MASK_LONG64 | MASK_INT64),                   \
 479      N_("Use 32-bit long type")},                                       \
 480   {"split-addresses",     MASK_SPLIT_ADDR,                              \
 481      N_("Optimize lui/addiu address loads")},                           \
 482   {"no-split-addresses", -MASK_SPLIT_ADDR,                              \
 483      N_("Don't optimize lui/addiu address loads")},                     \
 484   {"mips-as",            -MASK_GAS,                                     \
 485      N_("Use MIPS as")},                                                \
 486   {"gas",                 MASK_GAS,                                     \
 487      N_("Use GNU as")},                                                 \
 488   {"rnames",              MASK_NAME_REGS,                               \
 489      N_("Use symbolic register names")},                                \
 490   {"no-rnames",          -MASK_NAME_REGS,                               \
 491      N_("Don't use symbolic register names")},                          \
 492   {"gpOPT",               MASK_GPOPT,                                   \
 493      N_("Use GP relative sdata/sbss sections")},                        \
 494   {"gpopt",               MASK_GPOPT,                                   \
 495      N_("Use GP relative sdata/sbss sections")},                        \
 496   {"no-gpOPT",           -MASK_GPOPT,                                   \
 497      N_("Don't use GP relative sdata/sbss sections")},                  \
 498   {"no-gpopt",           -MASK_GPOPT,                                   \
 499      N_("Don't use GP relative sdata/sbss sections")},                  \
 500   {"stats",               MASK_STATS,                                   \
 501      N_("Output compiler statistics")},                                 \
 502   {"no-stats",           -MASK_STATS,                                   \
 503      N_("Don't output compiler statistics")},                           \
 504   {"memcpy",              MASK_MEMCPY,                                  \
 505      N_("Don't optimize block moves")},                                 \
 506   {"no-memcpy",          -MASK_MEMCPY,                                  \
 507      N_("Optimize block moves")},                                       \
 508   {"mips-tfile",          MASK_MIPS_TFILE,                              \
 509      N_("Use mips-tfile asm postpass")},                                \
 510   {"no-mips-tfile",      -MASK_MIPS_TFILE,                              \
 511      N_("Don't use mips-tfile asm postpass")},                          \
 512   {"soft-float",          MASK_SOFT_FLOAT,                              \
 513      N_("Use software floating point")},                                \
 514   {"hard-float",         -MASK_SOFT_FLOAT,                              \
 515      N_("Use hardware floating point")},                                \
 516   {"fp64",                MASK_FLOAT64,                                 \
 517      N_("Use 64-bit FP registers")},                                    \
 518   {"fp32",               -MASK_FLOAT64,                                 \
 519      N_("Use 32-bit FP registers")},                                    \
 520   {"gp64",                MASK_64BIT,                                   \
 521      N_("Use 64-bit general registers")},                               \
 522   {"gp32",               -MASK_64BIT,                                   \
 523      N_("Use 32-bit general registers")},                               \
 524   {"abicalls",            MASK_ABICALLS,                                \
 525      N_("Use Irix PIC")},                                               \
 526   {"no-abicalls",        -MASK_ABICALLS,                                \
 527      N_("Don't use Irix PIC")},                                         \
 528   {"long-calls",          MASK_LONG_CALLS,                              \
 529      N_("Use indirect calls")},                                         \
 530   {"no-long-calls",      -MASK_LONG_CALLS,                              \
 531      N_("Don't use indirect calls")},                                   \
 532   {"embedded-pic",        MASK_EMBEDDED_PIC,                            \
 533      N_("Use embedded PIC")},                                           \
 534   {"no-embedded-pic",    -MASK_EMBEDDED_PIC,                            \
 535      N_("Don't use embedded PIC")},                                     \
 536   {"embedded-data",       MASK_EMBEDDED_DATA,                           \
 537      N_("Use ROM instead of RAM")},                                     \
 538   {"no-embedded-data",   -MASK_EMBEDDED_DATA,                           \
 539      N_("Don't use ROM instead of RAM")},                               \
 540   {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA,               \
 541      N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
 542   {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA,           \
 543      N_("Don't put uninitialized constants in ROM")},                   \
 544   {"eb",                  MASK_BIG_ENDIAN,                              \
 545      N_("Use big-endian byte order")},                                  \
 546   {"el",                 -MASK_BIG_ENDIAN,                              \
 547      N_("Use little-endian byte order")},                               \
 548   {"single-float",        MASK_SINGLE_FLOAT,                            \
 549      N_("Use single (32-bit) FP only")},                                \
 550   {"double-float",       -MASK_SINGLE_FLOAT,                            \
 551      N_("Don't use single (32-bit) FP only")},                          \
 552   {"mad",                 MASK_MAD,                                     \
 553      N_("Use multiply accumulate")},                                    \
 554   {"no-mad",             -MASK_MAD,                                     \
 555      N_("Don't use multiply accumulate")},                              \
 556   {"no-fused-madd",       MASK_NO_FUSED_MADD,                           \
 557      N_("Don't generate fused multiply/add instructions")},             \
 558   {"fused-madd",         -MASK_NO_FUSED_MADD,                           \
 559      N_("Generate fused multiply/add instructions")},                   \
 560   {"fix4300",             MASK_4300_MUL_FIX,                            \
 561      N_("Work around early 4300 hardware bug")},                        \
 562   {"no-fix4300",         -MASK_4300_MUL_FIX,                            \
 563      N_("Don't work around early 4300 hardware bug")},                  \
 564   {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV,                       \
 565      N_("Trap on integer divide by zero")},                             \
 566   {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV,                    \
 567      N_("Don't trap on integer divide by zero")},                       \
 568   {"check-range-division",MASK_CHECK_RANGE_DIV,                         \
 569      N_("Trap on integer divide overflow")},                            \
 570   {"no-check-range-division",-MASK_CHECK_RANGE_DIV,                     \
 571      N_("Don't trap on integer divide overflow")},                      \
 572   {"debug",               MASK_DEBUG,                                   \
 573      NULL},                                                             \
 574   {"debuga",              MASK_DEBUG_A,                                 \
 575      NULL},                                                             \
 576   {"debugb",              MASK_DEBUG_B,                                 \
 577      NULL},                                                             \
 578   {"debugc",              MASK_DEBUG_C,                                 \
 579      NULL},                                                             \
 580   {"debugd",              MASK_DEBUG_D,                                 \
 581      NULL},                                                             \
 582   {"debuge",              MASK_DEBUG_E,                                 \
 583      NULL},                                                             \
 584   {"debugf",              MASK_DEBUG_F,                                 \
 585      NULL},                                                             \
 586   {"debugg",              MASK_DEBUG_G,                                 \
 587      NULL},                                                             \
 588   {"debugh",              MASK_DEBUG_H,                                 \
 589      NULL},                                                             \
 590   {"debugi",              MASK_DEBUG_I,                                 \
 591      NULL},                                                             \
 592   {"",                    (TARGET_DEFAULT                               \
 593                            | TARGET_CPU_DEFAULT                         \
 594                            | TARGET_ENDIAN_DEFAULT),                    \
 595      NULL},                                                             \
 596 }
 597
 598 /* Default target_flags if no switches are specified  */
 599
 600 #ifndef TARGET_DEFAULT
 601 #define TARGET_DEFAULT 0
 602 #endif
 603
 604 #ifndef TARGET_CPU_DEFAULT
 605 #define TARGET_CPU_DEFAULT 0
 606 #endif
 607
 608 #ifndef TARGET_ENDIAN_DEFAULT
 609 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
 610 #endif
 611
 612 #ifndef MIPS_ISA_DEFAULT
 613 #define MIPS_ISA_DEFAULT 1
 614 #endif
 615
 616 #ifdef IN_LIBGCC2
 617 #undef TARGET_64BIT
 618 /* Make this compile time constant for libgcc2 */
 619 #ifdef __mips64
 620 #define TARGET_64BIT            1
 621 #else
 622 #define TARGET_64BIT            0
 623 #endif
 624 #endif /* IN_LIBGCC2 */
 625
 626 #ifndef MULTILIB_ENDIAN_DEFAULT
 627 #if TARGET_ENDIAN_DEFAULT == 0
 628 #define MULTILIB_ENDIAN_DEFAULT "EL"
 629 #else
 630 #define MULTILIB_ENDIAN_DEFAULT "EB"
 631 #endif
 632 #endif
 633
 634 #ifndef MULTILIB_ISA_DEFAULT
 635 #  if MIPS_ISA_DEFAULT == 1
 636 #    define MULTILIB_ISA_DEFAULT "mips1"
 637 #  else
 638 #    if MIPS_ISA_DEFAULT == 2
 639 #      define MULTILIB_ISA_DEFAULT "mips2"
 640 #    else
 641 #      if MIPS_ISA_DEFAULT == 3
 642 #        define MULTILIB_ISA_DEFAULT "mips3"
 643 #      else
 644 #        if MIPS_ISA_DEFAULT == 4
 645 #          define MULTILIB_ISA_DEFAULT "mips4"
 646 #        else
 647 #          if MIPS_ISA_DEFAULT == 32
 648 #            define MULTILIB_ISA_DEFAULT "mips32"
 649 #          else
 650 #            if MIPS_ISA_DEFAULT == 64
 651 #              define MULTILIB_ISA_DEFAULT "mips64"
 652 #            else
 653 #          define MULTILIB_ISA_DEFAULT "mips1"
 654 #         endif
 655 #        endif
 656 #       endif
 657 #      endif
 658 #    endif
 659 #  endif
 660 #endif
 661
 662 #ifndef MULTILIB_DEFAULTS
 663 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
 664 #endif
 665
 666 /* We must pass -EL to the linker by default for little endian embedded
 667    targets using linker scripts with a OUTPUT_FORMAT line.  Otherwise, the
 668    linker will default to using big-endian output files.  The OUTPUT_FORMAT
 669    line must be in the linker script, otherwise -EB/-EL will not work.  */
 670
 671 #ifndef ENDIAN_SPEC
 672 #if TARGET_ENDIAN_DEFAULT == 0
 673 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
 674 #else
 675 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
 676 #endif
 677 #endif
 678
 679 #define TARGET_OPTIONS                                                  \
 680 {                                                                       \
 681   SUBTARGET_TARGET_OPTIONS                                              \
 682   { "cpu=",     &mips_cpu_string,                                       \
 683       N_("Specify CPU for scheduling purposes")},                       \
 684   { "tune=",    &mips_tune_string,                                      \
 685       N_("Specify CPU for scheduling purposes")},                       \
 686   { "arch=",    &mips_arch_string,                                      \
 687       N_("Specify CPU for code generation purposes")},                  \
 688   { "ips",      &mips_isa_string,                                       \
 689       N_("Specify a Standard MIPS ISA")},                               \
 690   { "entry",    &mips_entry_string,                                     \
 691       N_("Use mips16 entry/exit psuedo ops")},                          \
 692   { "no-mips16", &mips_no_mips16_string,                                \
 693       N_("Don't use MIPS16 instructions")},                             \
 694   { "explicit-type-size", &mips_explicit_type_size_string,              \
 695       NULL},                                                            \
 696   { "no-flush-func", &mips_cache_flush_func,                            \
 697       N_("Don't call any cache flush functions")},                      \
 698   { "flush-func=", &mips_cache_flush_func,                              \
 699       N_("Specify cache flush function")},                              \
 700 }
 701
 702 /* This is meant to be redefined in the host dependent files.  */
 703 #define SUBTARGET_TARGET_OPTIONS
 704
 705 #define GENERATE_BRANCHLIKELY   (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
 706
 707 /* Generate three-operand multiply instructions for SImode.  */
 708 #define GENERATE_MULT3_SI       ((TARGET_MIPS3900                       \
 709                                   || ISA_MIPS32                         \
 710                                   || ISA_MIPS64)                        \
 711                                  && !TARGET_MIPS16)
 712
 713 /* Generate three-operand multiply instructions for DImode.  */
 714 #define GENERATE_MULT3_DI       ((TARGET_MIPS3900)                      \
 715                                  && !TARGET_MIPS16)
 716
 717 /* Macros to decide whether certain features are available or not,
 718    depending on the instruction set architecture level.  */
 719
 720 #define BRANCH_LIKELY_P()       GENERATE_BRANCHLIKELY
 721 #define HAVE_SQRT_P()           (!ISA_MIPS1)
 722
 723 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3).  */
 724 #define ISA_HAS_64BIT_REGS      (ISA_MIPS3                              \
 725                                  || ISA_MIPS4                           \
 726                                  || ISA_MIPS64)
 727
 728 /* ISA has branch likely instructions (eg. mips2).  */
 729 /* Disable branchlikely for tx39 until compare rewrite.  They haven't
 730    been generated up to this point.  */
 731 #define ISA_HAS_BRANCHLIKELY    (!ISA_MIPS1                             \
 732                                  && !TARGET_MIPS16)
 733
 734 /* ISA has the conditional move instructions introduced in mips4.  */
 735 #define ISA_HAS_CONDMOVE        ((ISA_MIPS4                             \
 736                                   || ISA_MIPS32                         \
 737                                   || ISA_MIPS64)                        \
 738                                  && !TARGET_MIPS16)
 739
 740 /* ISA has just the integer condition move instructions (movn,movz) */
 741 #define ISA_HAS_INT_CONDMOVE     0
 742
 743 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
 744    branch on CC, and move (both FP and non-FP) on CC.  */
 745 #define ISA_HAS_8CC             (ISA_MIPS4                              \
 746                                  || ISA_MIPS32                          \
 747                                  || ISA_MIPS64)
 748
 749 /* This is a catch all for the other new mips4 instructions: indexed load and
 750    indexed prefetch instructions, the FP madd and msub instructions,
 751    and the FP recip and recip sqrt instructions */
 752 #define ISA_HAS_FP4             ((ISA_MIPS4                             \
 753                                   || ISA_MIPS64)                        \
 754                                  && !TARGET_MIPS16)
 755
 756 /* ISA has conditional trap instructions.  */
 757 #define ISA_HAS_COND_TRAP       (!ISA_MIPS1                             \
 758                                  && !TARGET_MIPS16)
 759
 760 /* ISA has integer multiply-accumulate instructions, madd and msub.  */
 761 #define ISA_HAS_MADD_MSUB       ((ISA_MIPS32                            \
 762                                   || ISA_MIPS64                         \
 763                                   ) && !TARGET_MIPS16)
 764
 765 /* ISA has floating-point nmadd and nmsub instructions.  */
 766 #define ISA_HAS_NMADD_NMSUB     ((ISA_MIPS4                             \
 767                                   || ISA_MIPS64)                        \
 768                                  && ! TARGET_MIPS16)
 769
 770 /* ISA has count leading zeroes/ones instruction (not implemented).  */
 771 #define ISA_HAS_CLZ_CLO         ((ISA_MIPS32                            \
 772                                   || ISA_MIPS64                         \
 773                                  ) && !TARGET_MIPS16)
 774
 775 /* ISA has double-word count leading zeroes/ones instruction (not
 776    implemented).  */
 777 #define ISA_HAS_DCLZ_DCLO       (ISA_MIPS64                             \
 778                                  && !TARGET_MIPS16)
 779
 780 /* ISA has data prefetch instruction.  */
 781 #define ISA_HAS_PREFETCH        ((ISA_MIPS4                             \
 782                                   || ISA_MIPS32                         \
 783                                   || ISA_MIPS64)                        \
 784                                  && !TARGET_MIPS16)
 785
 786 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
 787    -mips2 sets -mfp32 and -mgp32.  This can be overridden by an explicit
 788    -mfp32, -mfp64, -mgp32 or -mgp64.  -mfp64 sets MASK_FLOAT64 in
 789    target_flags, and -mgp64 sets MASK_64BIT.
 790
 791    Setting MASK_64BIT in target_flags will cause gcc to assume that
 792    registers are 64 bits wide.  int, long and void * will be 32 bit;
 793    this may be changed with -mint64 or -mlong64.
 794
 795    The gen* programs link code that refers to MASK_64BIT.  They don't
 796    actually use the information in target_flags; they just refer to
 797    it.  */
 798 \f
 799 /* Switch  Recognition by gcc.c.  Add -G xx support */
 800
 801 #undef  SWITCH_TAKES_ARG
 802 #define SWITCH_TAKES_ARG(CHAR)                                          \
 803   (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
 804
 805 /* Sometimes certain combinations of command options do not make sense
 806    on a particular target machine.  You can define a macro
 807    `OVERRIDE_OPTIONS' to take account of this.  This macro, if
 808    defined, is executed once just after all the command options have
 809    been parsed.
 810
 811    On the MIPS, it is used to handle -G.  We also use it to set up all
 812    of the tables referenced in the other macros.  */
 813
 814 #define OVERRIDE_OPTIONS override_options ()
 815
 816 /* Zero or more C statements that may conditionally modify two
 817    variables `fixed_regs' and `call_used_regs' (both of type `char
 818    []') after they have been initialized from the two preceding
 819    macros.
 820
 821    This is necessary in case the fixed or call-clobbered registers
 822    depend on target flags.
 823
 824    You need not define this macro if it has no work to do.
 825
 826    If the usage of an entire class of registers depends on the target
 827    flags, you may indicate this to GCC by using this macro to modify
 828    `fixed_regs' and `call_used_regs' to 1 for each of the registers in
 829    the classes which should not be used by GCC.  Also define the macro
 830    `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
 831    letter for a class that shouldn't be used.
 832
 833    (However, if this class is not included in `GENERAL_REGS' and all
 834    of the insn patterns whose constraints permit this class are
 835    controlled by target switches, then GCC will automatically avoid
 836    using these registers when the target switches are opposed to
 837    them.)  */
 838
 839 #define CONDITIONAL_REGISTER_USAGE                                      \
 840 do                                                                      \
 841   {                                                                     \
 842     if (!TARGET_HARD_FLOAT)                                             \
 843       {                                                                 \
 844         int regno;                                                      \
 845                                                                         \
 846         for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)       \
 847           fixed_regs[regno] = call_used_regs[regno] = 1;                \
 848         for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)       \
 849           fixed_regs[regno] = call_used_regs[regno] = 1;                \
 850       }                                                                 \
 851     else if (! ISA_HAS_8CC)                                             \
 852       {                                                                 \
 853         int regno;                                                      \
 854                                                                         \
 855         /* We only have a single condition code register.  We           \
 856            implement this by hiding all the condition code registers,   \
 857            and generating RTL that refers directly to ST_REG_FIRST.  */ \
 858         for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)       \
 859           fixed_regs[regno] = call_used_regs[regno] = 1;                \
 860       }                                                                 \
 861     /* In mips16 mode, we permit the $t temporary registers to be used  \
 862        for reload.  We prohibit the unused $s registers, since they     \
 863        are caller saved, and saving them via a mips16 register would    \
 864        probably waste more time than just reloading the value.  */      \
 865     if (TARGET_MIPS16)                                                  \
 866       {                                                                 \
 867         fixed_regs[18] = call_used_regs[18] = 1;                        \
 868         fixed_regs[19] = call_used_regs[19] = 1;                        \
 869         fixed_regs[20] = call_used_regs[20] = 1;                        \
 870         fixed_regs[21] = call_used_regs[21] = 1;                        \
 871         fixed_regs[22] = call_used_regs[22] = 1;                        \
 872         fixed_regs[23] = call_used_regs[23] = 1;                        \
 873         fixed_regs[26] = call_used_regs[26] = 1;                        \
 874         fixed_regs[27] = call_used_regs[27] = 1;                        \
 875         fixed_regs[30] = call_used_regs[30] = 1;                        \
 876       }                                                                 \
 877     SUBTARGET_CONDITIONAL_REGISTER_USAGE                                \
 878   }                                                                     \
 879 while (0)
 880
 881 /* This is meant to be redefined in the host dependent files.  */
 882 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
 883
 884 /* Show we can debug even without a frame pointer.  */
 885 #define CAN_DEBUG_WITHOUT_FP
 886 \f
 887 /* Tell collect what flags to pass to nm.  */
 888 #ifndef NM_FLAGS
 889 #define NM_FLAGS "-Bn"
 890 #endif
 891
 892 \f
 893 /* Assembler specs.  */
 894
 895 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
 896    than gas.  */
 897
 898 #define MIPS_AS_ASM_SPEC "\
 899 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
 900 %{pipe: %e-pipe is not supported} \
 901 %{K} %(subtarget_mips_as_asm_spec)"
 902
 903 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
 904    rather than gas.  It may be overridden by subtargets.  */
 905
 906 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
 907 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
 908 #endif
 909
 910 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
 911    assembler.  */
 912
 913 #define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64} %(abi_gas_asm_spec) %{mabi=32:%{!mips*:-mips1}}"
 914
 915
 916 extern int mips_abi;
 917
 918 #ifndef MIPS_ABI_DEFAULT
 919 #define MIPS_ABI_DEFAULT ABI_32
 920 #endif
 921
 922 #ifndef ABI_GAS_ASM_SPEC
 923 #define ABI_GAS_ASM_SPEC ""
 924 #endif
 925
 926 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
 927    GAS_ASM_SPEC as the default, depending upon the value of
 928    TARGET_DEFAULT.  */
 929
 930 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
 931 /* GAS */
 932
 933 #define TARGET_ASM_SPEC "\
 934 %{mmips-as: %(mips_as_asm_spec)} \
 935 %{!mmips-as: %(gas_asm_spec)}"
 936
 937 #else /* not GAS */
 938
 939 #define TARGET_ASM_SPEC "\
 940 %{!mgas: %(mips_as_asm_spec)} \
 941 %{mgas: %(gas_asm_spec)}"
 942
 943 #endif /* not GAS */
 944
 945 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
 946    to the assembler.  It may be overridden by subtargets.  */
 947 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
 948 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
 949 %{noasmopt:-O0} \
 950 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
 951 #endif
 952
 953 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
 954    the assembler.  It may be overridden by subtargets.  */
 955 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
 956 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
 957 %{g} %{g0} %{g1} %{g2} %{g3} \
 958 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
 959 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
 960 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
 961 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
 962 #endif
 963
 964 /* SUBTARGET_ASM_SPEC is always passed to the assembler.  It may be
 965    overridden by subtargets.  */
 966
 967 #ifndef SUBTARGET_ASM_SPEC
 968 #define SUBTARGET_ASM_SPEC ""
 969 #endif
 970
 971 /* ASM_SPEC is the set of arguments to pass to the assembler.  */
 972
 973 #undef ASM_SPEC
 974 #define ASM_SPEC "\
 975 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
 976 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
 977 %(subtarget_asm_optimizing_spec) \
 978 %(subtarget_asm_debugging_spec) \
 979 %{membedded-pic} \
 980 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
 981 %(target_asm_spec) \
 982 %(subtarget_asm_spec)"
 983
 984 /* Specify to run a post-processor, mips-tfile after the assembler
 985    has run to stuff the mips debug information into the object file.
 986    This is needed because the $#!%^ MIPS assembler provides no way
 987    of specifying such information in the assembly file.  If we are
 988    cross compiling, disable mips-tfile unless the user specifies
 989    -mmips-tfile.  */
 990
 991 #ifndef ASM_FINAL_SPEC
 992 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
 993 /* GAS */
 994 #define ASM_FINAL_SPEC "\
 995 %{mmips-as: %{!mno-mips-tfile: \
 996         \n mips-tfile %{v*: -v} \
 997                 %{K: -I %b.o~} \
 998                 %{!K: %{save-temps: -I %b.o~}} \
 999                 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1000                 %{.s:%i} %{!.s:%g.s}}}"
1001
1002 #else
1003 /* not GAS */
1004 #define ASM_FINAL_SPEC "\
1005 %{!mgas: %{!mno-mips-tfile: \
1006         \n mips-tfile %{v*: -v} \
1007                 %{K: -I %b.o~} \
1008                 %{!K: %{save-temps: -I %b.o~}} \
1009                 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1010                 %{.s:%i} %{!.s:%g.s}}}"
1011
1012 #endif
1013 #endif  /* ASM_FINAL_SPEC */
1014
1015 /* Redefinition of libraries used.  Mips doesn't support normal
1016    UNIX style profiling via calling _mcount.  It does offer
1017    profiling that samples the PC, so do what we can...  */
1018
1019 #ifndef LIB_SPEC
1020 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1021 #endif
1022
1023 /* Extra switches sometimes passed to the linker.  */
1024 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1025   will interpret it as a -b option.  */
1026
1027 #ifndef LINK_SPEC
1028 #define LINK_SPEC "\
1029 %(endian_spec) \
1030 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
1031 %{bestGnum} %{shared} %{non_shared}"
1032 #endif  /* LINK_SPEC defined */
1033
1034
1035 /* Specs for the compiler proper */
1036
1037 /* SUBTARGET_CC1_SPEC is passed to the compiler proper.  It may be
1038    overridden by subtargets.  */
1039 #ifndef SUBTARGET_CC1_SPEC
1040 #define SUBTARGET_CC1_SPEC ""
1041 #endif
1042
1043 /* CC1_SPEC is the set of arguments to pass to the compiler proper.  */
1044 /* Note, we will need to adjust the following if we ever find a MIPS variant
1045    that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1046    that show up in this case.  */
1047
1048 #ifndef CC1_SPEC
1049 #define CC1_SPEC "\
1050 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1051 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
1052 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1053 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1054 %{mips32:-mfp32 -mgp32} \
1055 %{mips64:%{!msingle-float:-mfp64} -mgp64} \
1056 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
1057 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
1058 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
1059 %{mgp32: %{mfp64:%emay not use both -mgp32 and -mfp64} %{!mfp32: -mfp32}} \
1060 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1061 %{save-temps: } \
1062 %(subtarget_cc1_spec)"
1063 #endif
1064
1065 /* Preprocessor specs.  */
1066
1067 /* SUBTARGET_CPP_SPEC is passed to the preprocessor.  It may be
1068    overridden by subtargets.  */
1069 #ifndef SUBTARGET_CPP_SPEC
1070 #define SUBTARGET_CPP_SPEC ""
1071 #endif
1072
1073 #define CPP_SPEC "%(subtarget_cpp_spec)"
1074
1075 /* This macro defines names of additional specifications to put in the specs
1076    that can be used in various specifications like CC1_SPEC.  Its definition
1077    is an initializer with a subgrouping for each command option.
1078
1079    Each subgrouping contains a string constant, that defines the
1080    specification name, and a string constant that used by the GNU CC driver
1081    program.
1082
1083    Do not define this macro if it does not need to do anything.  */
1084
1085 #define EXTRA_SPECS                                                     \
1086   { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC },                         \
1087   { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },                         \
1088   { "mips_as_asm_spec", MIPS_AS_ASM_SPEC },                             \
1089   { "gas_asm_spec", GAS_ASM_SPEC },                                     \
1090   { "abi_gas_asm_spec", ABI_GAS_ASM_SPEC },                             \
1091   { "target_asm_spec", TARGET_ASM_SPEC },                               \
1092   { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC },         \
1093   { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC },   \
1094   { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC },     \
1095   { "subtarget_asm_spec", SUBTARGET_ASM_SPEC },                         \
1096   { "endian_spec", ENDIAN_SPEC },                                       \
1097   SUBTARGET_EXTRA_SPECS
1098
1099 #ifndef SUBTARGET_EXTRA_SPECS
1100 #define SUBTARGET_EXTRA_SPECS
1101 #endif
1102
1103 /* If defined, this macro is an additional prefix to try after
1104    `STANDARD_EXEC_PREFIX'.  */
1105
1106 #ifndef MD_EXEC_PREFIX
1107 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1108 #endif
1109
1110 #ifndef MD_STARTFILE_PREFIX
1111 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1112 #endif
1113
1114 \f
1115 /* Print subsidiary information on the compiler version in use.  */
1116
1117 #define MIPS_VERSION "[AL 1.1, MM 40]"
1118
1119 #ifndef MACHINE_TYPE
1120 #define MACHINE_TYPE "BSD Mips"
1121 #endif
1122
1123 #ifndef TARGET_VERSION_INTERNAL
1124 #define TARGET_VERSION_INTERNAL(STREAM)                                 \
1125   fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1126 #endif
1127
1128 #ifndef TARGET_VERSION
1129 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1130 #endif
1131
1132 \f
1133 #define SDB_DEBUGGING_INFO              /* generate info for mips-tfile */
1134 #define DBX_DEBUGGING_INFO              /* generate stabs (OSF/rose) */
1135 #define MIPS_DEBUGGING_INFO             /* MIPS specific debugging info */
1136
1137 #ifndef PREFERRED_DEBUGGING_TYPE        /* assume SDB_DEBUGGING_INFO */
1138 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1139 #endif
1140
1141 /* By default, turn on GDB extensions.  */
1142 #define DEFAULT_GDB_EXTENSIONS 1
1143
1144 /* If we are passing smuggling stabs through the MIPS ECOFF object
1145    format, put a comment in front of the .stab<x> operation so
1146    that the MIPS assembler does not choke.  The mips-tfile program
1147    will correctly put the stab into the object file.  */
1148
1149 #define ASM_STABS_OP    ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1150 #define ASM_STABN_OP    ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1151 #define ASM_STABD_OP    ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1152
1153 /* Local compiler-generated symbols must have a prefix that the assembler
1154    understands.   By default, this is $, although some targets (e.g.,
1155    NetBSD-ELF) need to override this.  */
1156
1157 #ifndef LOCAL_LABEL_PREFIX
1158 #define LOCAL_LABEL_PREFIX      "$"
1159 #endif
1160
1161 /* By default on the mips, external symbols do not have an underscore
1162    prepended, but some targets (e.g., NetBSD) require this.  */
1163
1164 #ifndef USER_LABEL_PREFIX
1165 #define USER_LABEL_PREFIX       ""
1166 #endif
1167
1168 /* Forward references to tags are allowed.  */
1169 #define SDB_ALLOW_FORWARD_REFERENCES
1170
1171 /* Unknown tags are also allowed.  */
1172 #define SDB_ALLOW_UNKNOWN_REFERENCES
1173
1174 /* On Sun 4, this limit is 2048.  We use 1500 to be safe,
1175    since the length can run past this up to a continuation point.  */
1176 #undef DBX_CONTIN_LENGTH
1177 #define DBX_CONTIN_LENGTH 1500
1178
1179 /* How to renumber registers for dbx and gdb.  */
1180 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1181
1182 /* The mapping from gcc register number to DWARF 2 CFA column number.
1183    This mapping does not allow for tracking register 0, since SGI's broken
1184    dwarf reader thinks column 0 is used for the frame address, but since
1185    register 0 is fixed this is not a problem.  */
1186 #define DWARF_FRAME_REGNUM(REG)                         \
1187   (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1188
1189 /* The DWARF 2 CFA column which tracks the return address.  */
1190 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1191
1192 /* Before the prologue, RA lives in r31.  */
1193 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1194
1195 /* Describe how we implement __builtin_eh_return.  */
1196 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1197 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1198
1199 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1200    The default for this in 64-bit mode is 8, which causes problems with
1201    SFmode register saves.  */
1202 #define DWARF_CIE_DATA_ALIGNMENT 4
1203
1204 /* Overrides for the COFF debug format.  */
1205 #define PUT_SDB_SCL(a)                                  \
1206 do {                                                    \
1207   extern FILE *asm_out_text_file;                       \
1208   fprintf (asm_out_text_file, "\t.scl\t%d;", (a));      \
1209 } while (0)
1210
1211 #define PUT_SDB_INT_VAL(a)                              \
1212 do {                                                    \
1213   extern FILE *asm_out_text_file;                       \
1214   fprintf (asm_out_text_file, "\t.val\t");              \
1215   fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1216   fprintf (asm_out_text_file, ";");                     \
1217 } while (0)
1218
1219 #define PUT_SDB_VAL(a)                                  \
1220 do {                                                    \
1221   extern FILE *asm_out_text_file;                       \
1222   fputs ("\t.val\t", asm_out_text_file);                \
1223   output_addr_const (asm_out_text_file, (a));           \
1224   fputc (';', asm_out_text_file);                       \
1225 } while (0)
1226
1227 #define PUT_SDB_DEF(a)                                  \
1228 do {                                                    \
1229   extern FILE *asm_out_text_file;                       \
1230   fprintf (asm_out_text_file, "\t%s.def\t",             \
1231            (TARGET_GAS) ? "" : "#");                    \
1232   ASM_OUTPUT_LABELREF (asm_out_text_file, a);           \
1233   fputc (';', asm_out_text_file);                       \
1234 } while (0)
1235
1236 #define PUT_SDB_PLAIN_DEF(a)                            \
1237 do {                                                    \
1238   extern FILE *asm_out_text_file;                       \
1239   fprintf (asm_out_text_file, "\t%s.def\t.%s;",         \
1240            (TARGET_GAS) ? "" : "#", (a));               \
1241 } while (0)
1242
1243 #define PUT_SDB_ENDEF                                   \
1244 do {                                                    \
1245   extern FILE *asm_out_text_file;                       \
1246   fprintf (asm_out_text_file, "\t.endef\n");            \
1247 } while (0)
1248
1249 #define PUT_SDB_TYPE(a)                                 \
1250 do {                                                    \
1251   extern FILE *asm_out_text_file;                       \
1252   fprintf (asm_out_text_file, "\t.type\t0x%x;", (a));   \
1253 } while (0)
1254
1255 #define PUT_SDB_SIZE(a)                                 \
1256 do {                                                    \
1257   extern FILE *asm_out_text_file;                       \
1258   fprintf (asm_out_text_file, "\t.size\t");             \
1259   fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1260   fprintf (asm_out_text_file, ";");                     \
1261 } while (0)
1262
1263 #define PUT_SDB_DIM(a)                                  \
1264 do {                                                    \
1265   extern FILE *asm_out_text_file;                       \
1266   fprintf (asm_out_text_file, "\t.dim\t%d;", (a));      \
1267 } while (0)
1268
1269 #ifndef PUT_SDB_START_DIM
1270 #define PUT_SDB_START_DIM                               \
1271 do {                                                    \
1272   extern FILE *asm_out_text_file;                       \
1273   fprintf (asm_out_text_file, "\t.dim\t");              \
1274 } while (0)
1275 #endif
1276
1277 #ifndef PUT_SDB_NEXT_DIM
1278 #define PUT_SDB_NEXT_DIM(a)                             \
1279 do {                                                    \
1280   extern FILE *asm_out_text_file;                       \
1281   fprintf (asm_out_text_file, "%d,", a);                \
1282 } while (0)
1283 #endif
1284
1285 #ifndef PUT_SDB_LAST_DIM
1286 #define PUT_SDB_LAST_DIM(a)                             \
1287 do {                                                    \
1288   extern FILE *asm_out_text_file;                       \
1289   fprintf (asm_out_text_file, "%d;", a);                \
1290 } while (0)
1291 #endif
1292
1293 #define PUT_SDB_TAG(a)                                  \
1294 do {                                                    \
1295   extern FILE *asm_out_text_file;                       \
1296   fprintf (asm_out_text_file, "\t.tag\t");              \
1297   ASM_OUTPUT_LABELREF (asm_out_text_file, a);           \
1298   fputc (';', asm_out_text_file);                       \
1299 } while (0)
1300
1301 /* For block start and end, we create labels, so that
1302    later we can figure out where the correct offset is.
1303    The normal .ent/.end serve well enough for functions,
1304    so those are just commented out.  */
1305
1306 #define PUT_SDB_BLOCK_START(LINE)                       \
1307 do {                                                    \
1308   extern FILE *asm_out_text_file;                       \
1309   fprintf (asm_out_text_file,                           \
1310            "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n",         \
1311            LOCAL_LABEL_PREFIX,                          \
1312            sdb_label_count,                             \
1313            (TARGET_GAS) ? "" : "#",                     \
1314            LOCAL_LABEL_PREFIX,                          \
1315            sdb_label_count,                             \
1316            (LINE));                                     \
1317   sdb_label_count++;                                    \
1318 } while (0)
1319
1320 #define PUT_SDB_BLOCK_END(LINE)                         \
1321 do {                                                    \
1322   extern FILE *asm_out_text_file;                       \
1323   fprintf (asm_out_text_file,                           \
1324            "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n",          \
1325            LOCAL_LABEL_PREFIX,                          \
1326            sdb_label_count,                             \
1327            (TARGET_GAS) ? "" : "#",                     \
1328            LOCAL_LABEL_PREFIX,                          \
1329            sdb_label_count,                             \
1330            (LINE));                                     \
1331   sdb_label_count++;                                    \
1332 } while (0)
1333
1334 #define PUT_SDB_FUNCTION_START(LINE)
1335
1336 #define PUT_SDB_FUNCTION_END(LINE)                      \
1337 do {                                                    \
1338   extern FILE *asm_out_text_file;                       \
1339   ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1340 } while (0)
1341
1342 #define PUT_SDB_EPILOGUE_END(NAME)
1343
1344 #define PUT_SDB_SRC_FILE(FILENAME)                      \
1345 do {                                                    \
1346   extern FILE *asm_out_text_file;                       \
1347   output_file_directive (asm_out_text_file, (FILENAME));\
1348 } while (0)
1349
1350 #define SDB_GENERATE_FAKE(BUFFER, NUMBER)               \
1351   sprintf ((BUFFER), ".%dfake", (NUMBER));
1352
1353 /* Correct the offset of automatic variables and arguments.  Note that
1354    the MIPS debug format wants all automatic variables and arguments
1355    to be in terms of the virtual frame pointer (stack pointer before
1356    any adjustment in the function), while the MIPS 3.0 linker wants
1357    the frame pointer to be the stack pointer after the initial
1358    adjustment.  */
1359
1360 #define DEBUGGER_AUTO_OFFSET(X)                         \
1361   mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1362 #define DEBUGGER_ARG_OFFSET(OFFSET, X)                  \
1363   mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1364
1365 /* Tell collect that the object format is ECOFF */
1366 #ifndef OBJECT_FORMAT_ROSE
1367 #define OBJECT_FORMAT_COFF      /* Object file looks like COFF */
1368 #define EXTENDED_COFF           /* ECOFF, not normal coff */
1369 #endif
1370 \f
1371 /* Target machine storage layout */
1372
1373 /* Define this if most significant bit is lowest numbered
1374    in instructions that operate on numbered bit-fields.
1375 */
1376 #define BITS_BIG_ENDIAN 0
1377
1378 /* Define this if most significant byte of a word is the lowest numbered.  */
1379 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1380
1381 /* Define this if most significant word of a multiword number is the lowest.  */
1382 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1383
1384 /* Define this to set the endianness to use in libgcc2.c, which can
1385    not depend on target_flags.  */
1386 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1387 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1388 #else
1389 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1390 #endif
1391
1392 #define MAX_BITS_PER_WORD 64
1393
1394 /* Width of a word, in units (bytes).  */
1395 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1396 #define MIN_UNITS_PER_WORD 4
1397
1398 /* For MIPS, width of a floating point register.  */
1399 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1400
1401 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1402    the next available register.  */
1403 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1404
1405 /* The largest size of value that can be held in floating-point registers.  */
1406 #define UNITS_PER_FPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1407
1408 /* The number of bytes in a double.  */
1409 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1410
1411 /* A C expression for the size in bits of the type `int' on the
1412    target machine.  If you don't define this, the default is one
1413    word.  */
1414 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1415
1416 /* Tell the preprocessor the maximum size of wchar_t.  */
1417 #ifndef MAX_WCHAR_TYPE_SIZE
1418 #ifndef WCHAR_TYPE_SIZE
1419 #define MAX_WCHAR_TYPE_SIZE 64
1420 #endif
1421 #endif
1422
1423 /* A C expression for the size in bits of the type `short' on the
1424    target machine.  If you don't define this, the default is half a
1425    word.  (If this would be less than one storage unit, it is
1426    rounded up to one unit.)  */
1427 #define SHORT_TYPE_SIZE 16
1428
1429 /* A C expression for the size in bits of the type `long' on the
1430    target machine.  If you don't define this, the default is one
1431    word.  */
1432 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1433 #define MAX_LONG_TYPE_SIZE 64
1434
1435 /* A C expression for the size in bits of the type `long long' on the
1436    target machine.  If you don't define this, the default is two
1437    words.  */
1438 #define LONG_LONG_TYPE_SIZE 64
1439
1440 /* A C expression for the size in bits of the type `float' on the
1441    target machine.  If you don't define this, the default is one
1442    word.  */
1443 #define FLOAT_TYPE_SIZE 32
1444
1445 /* A C expression for the size in bits of the type `double' on the
1446    target machine.  If you don't define this, the default is two
1447    words.  */
1448 #define DOUBLE_TYPE_SIZE 64
1449
1450 /* A C expression for the size in bits of the type `long double' on
1451    the target machine.  If you don't define this, the default is two
1452    words.  */
1453 #define LONG_DOUBLE_TYPE_SIZE 64
1454
1455 /* Width in bits of a pointer.
1456    See also the macro `Pmode' defined below.  */
1457 #ifndef POINTER_SIZE
1458 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1459 #endif
1460
1461 /* Allocation boundary (in *bits*) for storing pointers in memory.  */
1462 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1463
1464 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
1465 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1466                         || mips_abi == ABI_64 \
1467                         || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1468
1469 /* Allocation boundary (in *bits*) for the code of a function.  */
1470 #define FUNCTION_BOUNDARY 32
1471
1472 /* Alignment of field after `int : 0' in a structure.  */
1473 #define EMPTY_FIELD_BOUNDARY 32
1474
1475 /* Every structure's size must be a multiple of this.  */
1476 /* 8 is observed right on a DECstation and on riscos 4.02.  */
1477 #define STRUCTURE_SIZE_BOUNDARY 8
1478
1479 /* There is no point aligning anything to a rounder boundary than this.  */
1480 #define BIGGEST_ALIGNMENT 64
1481
1482 /* Set this nonzero if move instructions will actually fail to work
1483    when given unaligned data.  */
1484 #define STRICT_ALIGNMENT 1
1485
1486 /* Define this if you wish to imitate the way many other C compilers
1487    handle alignment of bitfields and the structures that contain
1488    them.
1489
1490    The behavior is that the type written for a bitfield (`int',
1491    `short', or other integer type) imposes an alignment for the
1492    entire structure, as if the structure really did contain an
1493    ordinary field of that type.  In addition, the bitfield is placed
1494    within the structure so that it would fit within such a field,
1495    not crossing a boundary for it.
1496
1497    Thus, on most machines, a bitfield whose type is written as `int'
1498    would not cross a four-byte boundary, and would force four-byte
1499    alignment for the whole structure.  (The alignment used may not
1500    be four bytes; it is controlled by the other alignment
1501    parameters.)
1502
1503    If the macro is defined, its definition should be a C expression;
1504    a nonzero value for the expression enables this behavior.  */
1505
1506 #define PCC_BITFIELD_TYPE_MATTERS 1
1507
1508 /* If defined, a C expression to compute the alignment given to a
1509    constant that is being placed in memory.  CONSTANT is the constant
1510    and ALIGN is the alignment that the object would ordinarily have.
1511    The value of this macro is used instead of that alignment to align
1512    the object.
1513
1514    If this macro is not defined, then ALIGN is used.
1515
1516    The typical use of this macro is to increase alignment for string
1517    constants to be word aligned so that `strcpy' calls that copy
1518    constants can be done inline.  */
1519
1520 #define CONSTANT_ALIGNMENT(EXP, ALIGN)                                  \
1521   ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)   \
1522    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1523
1524 /* If defined, a C expression to compute the alignment for a static
1525    variable.  TYPE is the data type, and ALIGN is the alignment that
1526    the object would ordinarily have.  The value of this macro is used
1527    instead of that alignment to align the object.
1528
1529    If this macro is not defined, then ALIGN is used.
1530
1531    One use of this macro is to increase alignment of medium-size
1532    data to make it all fit in fewer cache lines.  Another is to
1533    cause character arrays to be word-aligned so that `strcpy' calls
1534    that copy constants to character arrays can be done inline.  */
1535
1536 #undef DATA_ALIGNMENT
1537 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
1538   ((((ALIGN) < BITS_PER_WORD)                                           \
1539     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
1540         || TREE_CODE (TYPE) == UNION_TYPE                               \
1541         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1542
1543
1544 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1545
1546 #define PAD_VARARGS_DOWN (TARGET_64BIT                                  \
1547                           || mips_abi == ABI_MEABI                      \
1548                              ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1549
1550 /* Define this macro if an argument declared as `char' or `short' in a
1551    prototype should actually be passed as an `int'.  In addition to
1552    avoiding errors in certain cases of mismatch, it also makes for
1553    better code on certain machines.  */
1554
1555 #define PROMOTE_PROTOTYPES 1
1556
1557 /* Define if operations between registers always perform the operation
1558    on the full register even if a narrower mode is specified.  */
1559 #define WORD_REGISTER_OPERATIONS
1560
1561 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1562    will either zero-extend or sign-extend.  The value of this macro should
1563    be the code that says which one of the two operations is implicitly
1564    done, NIL if none.
1565
1566    When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1567    moves.  All other referces are zero extended.  */
1568 #define LOAD_EXTEND_OP(MODE) \
1569   (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1570    ? SIGN_EXTEND : ZERO_EXTEND)
1571
1572 /* Define this macro if it is advisable to hold scalars in registers
1573    in a wider mode than that declared by the program.  In such cases,
1574    the value is constrained to be within the bounds of the declared
1575    type, but kept valid in the wider mode.  The signedness of the
1576    extension may differ from that of the type.
1577
1578    We promote any value smaller than SImode up to SImode.  We don't
1579    want to promote to DImode when in 64 bit mode, because that would
1580    prevent us from using the faster SImode multiply and divide
1581    instructions.  */
1582
1583 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
1584   if (GET_MODE_CLASS (MODE) == MODE_INT         \
1585       && GET_MODE_SIZE (MODE) < 4)              \
1586     (MODE) = SImode;
1587
1588 /* Define this if function arguments should also be promoted using the above
1589    procedure.  */
1590
1591 #define PROMOTE_FUNCTION_ARGS
1592
1593 /* Likewise, if the function return value is promoted.  */
1594
1595 #define PROMOTE_FUNCTION_RETURN
1596 \f
1597 /* Standard register usage.  */
1598
1599 /* Number of actual hardware registers.
1600    The hardware registers are assigned numbers for the compiler
1601    from 0 to just below FIRST_PSEUDO_REGISTER.
1602    All registers that the compiler knows about must be given numbers,
1603    even those that are not normally considered general registers.
1604
1605    On the Mips, we have 32 integer registers, 32 floating point
1606    registers, 8 condition code registers, and the special registers
1607    hi, lo, hilo, and rap.  Afetr that we have 32 COP0 registers, 32
1608    COP2 registers, and 32 COp3 registers.  (COP1 is the floating-point
1609    processor.)  The 8 condition code registers are only used if
1610    mips_isa >= 4.  The hilo register is only used in 64 bit mode.  It
1611    represents a 64 bit value stored as two 32 bit values in the hi and
1612    lo registers; this is the result of the mult instruction.  rap is a
1613    pointer to the stack where the return address reg ($31) was stored.
1614    This is needed for C++ exception handling.  */
1615
1616 #define FIRST_PSEUDO_REGISTER 176
1617
1618 /* 1 for registers that have pervasive standard uses
1619    and are not available for the register allocator.
1620
1621    On the MIPS, see conventions, page D-2  */
1622
1623 /* Regarding coprocessor registers: without evidence to the contrary,
1624    it's best to assume that each coprocessor register has a unique
1625    use.  This can be overridden, in, e.g., override_options() or
1626    CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1627    for a particular target.  */
1628
1629 #define FIXED_REGISTERS                                                 \
1630 {                                                                       \
1631   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1632   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1,                       \
1633   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1634   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1635   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,                       \
1636   /* COP0 registers */                                                  \
1637   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1638   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1639   /* COP2 registers */                                                  \
1640   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1641   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1642   /* COP3 registers */                                                  \
1643   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1644   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1                        \
1645 }
1646
1647
1648 /* 1 for registers not available across function calls.
1649    These must include the FIXED_REGISTERS and also any
1650    registers that can be used without being saved.
1651    The latter must include the registers where values are returned
1652    and the register where structure-value addresses are passed.
1653    Aside from that, you can include as many other registers as you like.  */
1654
1655 #define CALL_USED_REGISTERS                                             \
1656 {                                                                       \
1657   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1658   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1,                       \
1659   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1660   1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1661   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0,                       \
1662   /* COP0 registers */                                                  \
1663   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1664   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1665   /* COP2 registers */                                                  \
1666   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1667   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1668   /* COP3 registers */                                                  \
1669   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1670   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1                        \
1671 }
1672
1673 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1674    problem which makes CALL_USED_REGISTERS *always* include
1675    all the FIXED_REGISTERS.  Until this problem has been
1676    resolved this macro can be used to overcome this situation.
1677    In particular, block_propagate() requires this list
1678    be acurate, or we can remove registers which should be live.
1679    This macro is used in regs_invalidated_by_call.  */
1680
1681
1682 #define CALL_REALLY_USED_REGISTERS                                      \
1683 { /* General registers.  */                                             \
1684   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1685   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1,                       \
1686   /* Floating-point registers.  */                                      \
1687   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
1688   1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1689   /* Others.  */                                                        \
1690   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0,                       \
1691   /* COP0 registers */                                                  \
1692   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1693   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1694   /* COP2 registers */                                                  \
1695   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1696   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1697   /* COP3 registers */                                                  \
1698   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
1699   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0                        \
1700 }
1701
1702 /* Internal macros to classify a register number as to whether it's a
1703    general purpose register, a floating point register, a
1704    multiply/divide register, or a status register.  */
1705
1706 #define GP_REG_FIRST 0
1707 #define GP_REG_LAST  31
1708 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
1709 #define GP_DBX_FIRST 0
1710
1711 #define FP_REG_FIRST 32
1712 #define FP_REG_LAST  63
1713 #define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
1714 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1715
1716 #define MD_REG_FIRST 64
1717 #define MD_REG_LAST  66
1718 #define MD_REG_NUM   (MD_REG_LAST - MD_REG_FIRST + 1)
1719
1720 #define ST_REG_FIRST 67
1721 #define ST_REG_LAST  74
1722 #define ST_REG_NUM   (ST_REG_LAST - ST_REG_FIRST + 1)
1723
1724 #define RAP_REG_NUM   75
1725
1726 #define COP0_REG_FIRST 80
1727 #define COP0_REG_LAST 111
1728 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1729
1730 #define COP2_REG_FIRST 112
1731 #define COP2_REG_LAST 143
1732 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1733
1734 #define COP3_REG_FIRST 144
1735 #define COP3_REG_LAST 175
1736 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1737 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively.  */
1738 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1739
1740 #define AT_REGNUM       (GP_REG_FIRST + 1)
1741 #define HI_REGNUM       (MD_REG_FIRST + 0)
1742 #define LO_REGNUM       (MD_REG_FIRST + 1)
1743 #define HILO_REGNUM     (MD_REG_FIRST + 2)
1744
1745 /* FPSW_REGNUM is the single condition code used if mips_isa < 4.  If
1746    mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1747    should be used instead.  */
1748 #define FPSW_REGNUM     ST_REG_FIRST
1749
1750 #define GP_REG_P(REGNO) \
1751   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1752 #define M16_REG_P(REGNO) \
1753   (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1754 #define FP_REG_P(REGNO)  \
1755   ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1756 #define MD_REG_P(REGNO) \
1757   ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1758 #define ST_REG_P(REGNO) \
1759   ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1760 #define COP0_REG_P(REGNO) \
1761   ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1762 #define COP2_REG_P(REGNO) \
1763   ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1764 #define COP3_REG_P(REGNO) \
1765   ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1766 #define ALL_COP_REG_P(REGNO) \
1767   ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1768
1769 /* Return coprocessor number from register number.  */
1770
1771 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO)                               \
1772   (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2'                  \
1773    : COP3_REG_P (REGNO) ? '3' : '?')
1774
1775 /* Return number of consecutive hard regs needed starting at reg REGNO
1776    to hold something of mode MODE.
1777    This is ordinarily the length in words of a value of mode MODE
1778    but can be less for certain modes in special long registers.
1779
1780    On the MIPS, all general registers are one word long.  Except on
1781    the R4000 with the FR bit set, the floating point uses register
1782    pairs, with the second register not being allocable.  */
1783
1784 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1785
1786 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1787    MODE.  In 32 bit mode, require that DImode and DFmode be in even
1788    registers.  For DImode, this makes some of the insns easier to
1789    write, since you don't have to worry about a DImode value in
1790    registers 3 & 4, producing a result in 4 & 5.
1791
1792    To make the code simpler HARD_REGNO_MODE_OK now just references an
1793    array built in override_options.  Because machmodes.h is not yet
1794    included before this file is processed, the MODE bound can't be
1795    expressed here.  */
1796
1797 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1798
1799 #define HARD_REGNO_MODE_OK(REGNO, MODE)                                 \
1800   mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1801
1802 /* Value is 1 if it is a good idea to tie two pseudo registers
1803    when one has mode MODE1 and one has mode MODE2.
1804    If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1805    for any hard reg, then this must be 0 for correct output.  */
1806 #define MODES_TIEABLE_P(MODE1, MODE2)                                   \
1807   ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||                             \
1808     GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)                       \
1809    == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||                          \
1810        GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1811
1812 /* MIPS pc is not overloaded on a register.     */
1813 /* #define PC_REGNUM xx                         */
1814
1815 /* Register to use for pushing function arguments.  */
1816 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1817
1818 /* Offset from the stack pointer to the first available location.  Use
1819    the default value zero.  */
1820 /* #define STACK_POINTER_OFFSET 0 */
1821
1822 /* Base register for access to local variables of the function.  We
1823    pretend that the frame pointer is $1, and then eliminate it to
1824    HARD_FRAME_POINTER_REGNUM.  We can get away with this because $1 is
1825    a fixed register, and will not be used for anything else.  */
1826 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1827
1828 /* Temporary scratch register for use by the assembler.  */
1829 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1830
1831 /* $30 is not available on the mips16, so we use $17 as the frame
1832    pointer.  */
1833 #define HARD_FRAME_POINTER_REGNUM \
1834   (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1835
1836 /* Value should be nonzero if functions must have frame pointers.
1837    Zero means the frame pointer need not be set up (and parms
1838    may be accessed via the stack pointer) in functions that seem suitable.
1839    This is computed in `reload', in reload1.c.  */
1840 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1841
1842 /* Base register for access to arguments of the function.  */
1843 #define ARG_POINTER_REGNUM GP_REG_FIRST
1844
1845 /* Fake register that holds the address on the stack of the
1846    current function's return address.  */
1847 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1848
1849 /* Register in which static-chain is passed to a function.  */
1850 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1851
1852 /* If the structure value address is passed in a register, then
1853    `STRUCT_VALUE_REGNUM' should be the number of that register.  */
1854 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1855
1856 /* If the structure value address is not passed in a register, define
1857    `STRUCT_VALUE' as an expression returning an RTX for the place
1858    where the address is passed.  If it returns 0, the address is
1859    passed as an "invisible" first argument.  */
1860 #define STRUCT_VALUE 0
1861
1862 /* Mips registers used in prologue/epilogue code when the stack frame
1863    is larger than 32K bytes.  These registers must come from the
1864    scratch register set, and not used for passing and returning
1865    arguments and any other information used in the calling sequence
1866    (such as pic).  Must start at 12, since t0/t3 are parameter passing
1867    registers in the 64 bit ABI.  */
1868
1869 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1870 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1871
1872 /* Define this macro if it is as good or better to call a constant
1873    function address than to call an address kept in a register.  */
1874 #define NO_FUNCTION_CSE 1
1875
1876 /* Define this macro if it is as good or better for a function to
1877    call itself with an explicit address than to call an address
1878    kept in a register.  */
1879 #define NO_RECURSIVE_FUNCTION_CSE 1
1880
1881 /* The register number of the register used to address a table of
1882    static data addresses in memory.  In some cases this register is
1883    defined by a processor's "application binary interface" (ABI).
1884    When this macro is defined, RTL is generated for this register
1885    once, as with the stack pointer and frame pointer registers.  If
1886    this macro is not defined, it is up to the machine-dependent
1887    files to allocate such a register (if necessary).  */
1888 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1889
1890 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1891 \f
1892 /* Define the classes of registers for register constraints in the
1893    machine description.  Also define ranges of constants.
1894
1895    One of the classes must always be named ALL_REGS and include all hard regs.
1896    If there is more than one class, another class must be named NO_REGS
1897    and contain no registers.
1898
1899    The name GENERAL_REGS must be the name of a class (or an alias for
1900    another name such as ALL_REGS).  This is the class of registers
1901    that is allowed by "g" or "r" in a register constraint.
1902    Also, registers outside this class are allocated only when
1903    instructions express preferences for them.
1904
1905    The classes must be numbered in nondecreasing order; that is,
1906    a larger-numbered class must never be contained completely
1907    in a smaller-numbered class.
1908
1909    For any two classes, it is very desirable that there be another
1910    class that represents their union.  */
1911
1912 enum reg_class
1913 {
1914   NO_REGS,                      /* no registers in set */
1915   M16_NA_REGS,                  /* mips16 regs not used to pass args */
1916   M16_REGS,                     /* mips16 directly accessible registers */
1917   T_REG,                        /* mips16 T register ($24) */
1918   M16_T_REGS,                   /* mips16 registers plus T register */
1919   GR_REGS,                      /* integer registers */
1920   FP_REGS,                      /* floating point registers */
1921   HI_REG,                       /* hi register */
1922   LO_REG,                       /* lo register */
1923   HILO_REG,                     /* hilo register pair for 64 bit mode mult */
1924   MD_REGS,                      /* multiply/divide registers (hi/lo) */
1925   COP0_REGS,                    /* generic coprocessor classes */
1926   COP2_REGS,
1927   COP3_REGS,
1928   HI_AND_GR_REGS,               /* union classes */
1929   LO_AND_GR_REGS,
1930   HILO_AND_GR_REGS,
1931   HI_AND_FP_REGS,
1932   COP0_AND_GR_REGS,
1933   COP2_AND_GR_REGS,
1934   COP3_AND_GR_REGS,
1935   ALL_COP_REGS,
1936   ALL_COP_AND_GR_REGS,
1937   ST_REGS,                      /* status registers (fp status) */
1938   ALL_REGS,                     /* all registers */
1939   LIM_REG_CLASSES               /* max value + 1 */
1940 };
1941
1942 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1943
1944 #define GENERAL_REGS GR_REGS
1945
1946 /* An initializer containing the names of the register classes as C
1947    string constants.  These names are used in writing some of the
1948    debugging dumps.  */
1949
1950 #define REG_CLASS_NAMES                                                 \
1951 {                                                                       \
1952   "NO_REGS",                                                            \
1953   "M16_NA_REGS",                                                        \
1954   "M16_REGS",                                                           \
1955   "T_REG",                                                              \
1956   "M16_T_REGS",                                                         \
1957   "GR_REGS",                                                            \
1958   "FP_REGS",                                                            \
1959   "HI_REG",                                                             \
1960   "LO_REG",                                                             \
1961   "HILO_REG",                                                           \
1962   "MD_REGS",                                                            \
1963   /* coprocessor registers */                                           \
1964   "COP0_REGS",                                                          \
1965   "COP2_REGS",                                                          \
1966   "COP3_REGS",                                                          \
1967   "HI_AND_GR_REGS",                                                     \
1968   "LO_AND_GR_REGS",                                                     \
1969   "HILO_AND_GR_REGS",                                                   \
1970   "HI_AND_FP_REGS",                                                     \
1971   "COP0_AND_GR_REGS",                                                   \
1972   "COP2_AND_GR_REGS",                                                   \
1973   "COP3_AND_GR_REGS",                                                   \
1974   "ALL_COP_REGS",                                                       \
1975   "ALL_COP_AND_GR_REGS",                                                \
1976   "ST_REGS",                                                            \
1977   "ALL_REGS"                                                            \
1978 }
1979
1980 /* An initializer containing the contents of the register classes,
1981    as integers which are bit masks.  The Nth integer specifies the
1982    contents of class N.  The way the integer MASK is interpreted is
1983    that register R is in the class if `MASK & (1 << R)' is 1.
1984
1985    When the machine has more than 32 registers, an integer does not
1986    suffice.  Then the integers are replaced by sub-initializers,
1987    braced groupings containing several integers.  Each
1988    sub-initializer must be suitable as an initializer for the type
1989    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
1990
1991 #define REG_CLASS_CONTENTS                                              \
1992 {                                                                       \
1993   { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* no registers */      \
1994   { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* mips16 nonarg regs */\
1995   { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* mips16 registers */  \
1996   { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* mips16 T register */ \
1997   { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* mips16 and T regs */ \
1998   { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* integer registers */ \
1999   { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },   /* floating registers*/ \
2000   { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },   /* hi register */       \
2001   { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 },   /* lo register */       \
2002   { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 },   /* hilo register */     \
2003   { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 },   /* mul/div registers */ \
2004   { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2005   { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2006   { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2007   { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },   /* union classes */     \
2008   { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 },                           \
2009   { 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 },                           \
2010   { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },                           \
2011   { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 },                   \
2012   { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 },   \
2013   { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2014   { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2015   { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2016   { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 },   /* status registers */  \
2017   { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff }    /* all registers */     \
2018 }
2019
2020
2021 /* A C expression whose value is a register class containing hard
2022    register REGNO.  In general there is more that one such class;
2023    choose a class which is "minimal", meaning that no smaller class
2024    also contains the register.  */
2025
2026 extern const enum reg_class mips_regno_to_class[];
2027
2028 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2029
2030 /* A macro whose definition is the name of the class to which a
2031    valid base register must belong.  A base register is one used in
2032    an address which is the register value plus a displacement.  */
2033
2034 #define BASE_REG_CLASS  (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2035
2036 /* A macro whose definition is the name of the class to which a
2037    valid index register must belong.  An index register is one used
2038    in an address where its value is either multiplied by a scale
2039    factor or added to another register (as well as added to a
2040    displacement).  */
2041
2042 #define INDEX_REG_CLASS NO_REGS
2043
2044 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2045    registers explicitly used in the rtl to be used as spill registers
2046    but prevents the compiler from extending the lifetime of these
2047    registers.  */
2048
2049 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2050
2051 /* This macro is used later on in the file.  */
2052 #define GR_REG_CLASS_P(CLASS)                                           \
2053   ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG        \
2054    || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2055
2056 /* This macro is also used later on in the file.  */
2057 #define COP_REG_CLASS_P(CLASS)                                          \
2058   ((CLASS)  == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2059
2060 /* REG_ALLOC_ORDER is to order in which to allocate registers.  This
2061    is the default value (allocate the registers in numeric order).  We
2062    define it just so that we can override it for the mips16 target in
2063    ORDER_REGS_FOR_LOCAL_ALLOC.  */
2064
2065 #define REG_ALLOC_ORDER                                                 \
2066 {  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,       \
2067   16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,       \
2068   32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,       \
2069   48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,       \
2070   64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,       \
2071   80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,       \
2072   96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111,      \
2073   112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,      \
2074   128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,      \
2075   144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,      \
2076   160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175       \
2077 }
2078
2079 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2080    to be rearranged based on a particular function.  On the mips16, we
2081    want to allocate $24 (T_REG) before other registers for
2082    instructions for which it is possible.  */
2083
2084 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2085
2086 /* REGISTER AND CONSTANT CLASSES */
2087
2088 /* Get reg_class from a letter such as appears in the machine
2089    description.
2090
2091    DEFINED REGISTER CLASSES:
2092
2093    'd'  General (aka integer) registers
2094         Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2095    'y'  General registers (in both mips16 and non mips16 mode)
2096    'e'  mips16 non argument registers (M16_NA_REGS)
2097    't'  mips16 temporary register ($24)
2098    'f'  Floating point registers
2099    'h'  Hi register
2100    'l'  Lo register
2101    'x'  Multiply/divide registers
2102    'a'  HILO_REG
2103    'z'  FP Status register
2104    'B'  Cop0 register
2105    'C'  Cop2 register
2106    'D'  Cop3 register
2107    'b'  All registers */
2108
2109 extern enum reg_class mips_char_to_class[256];
2110
2111 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2112
2113 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2114    string can be used to stand for particular ranges of immediate
2115    operands.  This macro defines what the ranges are.  C is the
2116    letter, and VALUE is a constant value.  Return 1 if VALUE is
2117    in the range specified by C.  */
2118
2119 /* For MIPS:
2120
2121    `I'  is used for the range of constants an arithmetic insn can
2122         actually contain (16 bits signed integers).
2123
2124    `J'  is used for the range which is just zero (ie, $r0).
2125
2126    `K'  is used for the range of constants a logical insn can actually
2127         contain (16 bit zero-extended integers).
2128
2129    `L'  is used for the range of constants that be loaded with lui
2130         (ie, the bottom 16 bits are zero).
2131
2132    `M'  is used for the range of constants that take two words to load
2133         (ie, not matched by `I', `K', and `L').
2134
2135    `N'  is used for negative 16 bit constants other than -65536.
2136
2137    `O'  is a 15 bit signed integer.
2138
2139    `P'  is used for positive 16 bit constants.  */
2140
2141 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2142 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2143
2144 #define CONST_OK_FOR_LETTER_P(VALUE, C)                                 \
2145   ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
2146    : (C) == 'J' ? ((VALUE) == 0)                                        \
2147    : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000)          \
2148    : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0                          \
2149                    && (((VALUE) & ~2147483647) == 0                     \
2150                        || ((VALUE) & ~2147483647) == ~2147483647))      \
2151    : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0)                       \
2152                    && (((VALUE) & ~0x0000ffff) != ~0x0000ffff)          \
2153                    && (((VALUE) & 0x0000ffff) != 0                      \
2154                        || (((VALUE) & ~2147483647) != 0                 \
2155                            && ((VALUE) & ~2147483647) != ~2147483647))) \
2156    : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2157    : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2158    : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0))      \
2159    : 0)
2160
2161 /* Similar, but for floating constants, and defining letters G and H.
2162    Here VALUE is the CONST_DOUBLE rtx itself.  */
2163
2164 /* For Mips
2165
2166   'G'   : Floating point 0 */
2167
2168 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)                          \
2169   ((C) == 'G'                                                           \
2170    && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2171
2172 /* Letters in the range `Q' through `U' may be defined in a
2173    machine-dependent fashion to stand for arbitrary operand types.
2174    The machine description macro `EXTRA_CONSTRAINT' is passed the
2175    operand as its first argument and the constraint letter as its
2176    second operand.
2177
2178    `Q'  is for mips16 GP relative constants
2179    `R'  is for memory references which take 1 word for the instruction.
2180    `T'  is for memory addresses that can be used to load two words.  */
2181
2182 #define EXTRA_CONSTRAINT(OP,CODE)                                       \
2183   (((CODE) == 'T')        ? double_memory_operand (OP, GET_MODE (OP))   \
2184    : ((CODE) == 'Q')      ? (GET_CODE (OP) == CONST                     \
2185                              && mips16_gp_offset_p (OP))                \
2186    : (GET_CODE (OP) != MEM) ? FALSE                                     \
2187    : ((CODE) == 'R')      ? simple_memory_operand (OP, GET_MODE (OP))   \
2188    : FALSE)
2189
2190 /* Given an rtx X being reloaded into a reg required to be
2191    in class CLASS, return the class of reg to actually use.
2192    In general this is just CLASS; but on some machines
2193    in some cases it is preferable to use a more restrictive class.  */
2194
2195 #define PREFERRED_RELOAD_CLASS(X,CLASS)                                 \
2196   ((CLASS) != ALL_REGS                                                  \
2197    ? (! TARGET_MIPS16                                                   \
2198       ? (CLASS)                                                         \
2199       : ((CLASS) != GR_REGS                                             \
2200          ? (CLASS)                                                      \
2201          : M16_REGS))                                                   \
2202    : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT                      \
2203        || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)          \
2204       ? (TARGET_SOFT_FLOAT                                              \
2205          ? (TARGET_MIPS16 ? M16_REGS : GR_REGS)                         \
2206          : FP_REGS)                                                     \
2207       : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT                     \
2208           || GET_MODE (X) == VOIDmode)                                  \
2209          ? (TARGET_MIPS16 ? M16_REGS : GR_REGS)                         \
2210          : (CLASS))))
2211
2212 /* Certain machines have the property that some registers cannot be
2213    copied to some other registers without using memory.  Define this
2214    macro on those machines to be a C expression that is non-zero if
2215    objects of mode MODE in registers of CLASS1 can only be copied to
2216    registers of class CLASS2 by storing a register of CLASS1 into
2217    memory and loading that memory location into a register of CLASS2.
2218
2219    Do not define this macro if its value would always be zero.  */
2220 #if 0
2221 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)                   \
2222   ((!TARGET_DEBUG_H_MODE                                                \
2223     && GET_MODE_CLASS (MODE) == MODE_INT                                \
2224     && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2))                  \
2225         || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS)))             \
2226    || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode              \
2227        && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS)               \
2228            || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2229 #endif
2230 /* The HI and LO registers can only be reloaded via the general
2231    registers.  Condition code registers can only be loaded to the
2232    general registers, and from the floating point registers.  */
2233
2234 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)                    \
2235   mips_secondary_reload_class (CLASS, MODE, X, 1)
2236 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)                   \
2237   mips_secondary_reload_class (CLASS, MODE, X, 0)
2238
2239 /* Return the maximum number of consecutive registers
2240    needed to represent mode MODE in a register of class CLASS.  */
2241
2242 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2243
2244 /* If defined, gives a class of registers that cannot be used as the
2245    operand of a SUBREG that changes the mode of the object illegally.
2246    When FP regs are larger than integer regs... Er, anyone remember what
2247    goes wrong?
2248
2249    In little-endian mode, the hi-lo registers are numbered backwards,
2250    so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
2251    word as intended.  */
2252
2253 #define CLASS_CANNOT_CHANGE_MODE                                        \
2254   (TARGET_BIG_ENDIAN                                                    \
2255    ? (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)             \
2256    : (TARGET_FLOAT64 && ! TARGET_64BIT ? HI_AND_FP_REGS : HI_REG))
2257
2258 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.  */
2259
2260 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2261   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2262 \f
2263 /* Stack layout; function entry, exit and calling.  */
2264
2265 /* Define this if pushing a word on the stack
2266    makes the stack pointer a smaller address.  */
2267 #define STACK_GROWS_DOWNWARD
2268
2269 /* Define this if the nominal address of the stack frame
2270    is at the high-address end of the local variables;
2271    that is, each additional local variable allocated
2272    goes at a more negative offset in the frame.  */
2273 /* #define FRAME_GROWS_DOWNWARD */
2274
2275 /* Offset within stack frame to start allocating local variables at.
2276    If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2277    first local allocated.  Otherwise, it is the offset to the BEGINNING
2278    of the first local allocated.  */
2279 #define STARTING_FRAME_OFFSET                                           \
2280   (current_function_outgoing_args_size                                  \
2281    + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2282
2283 /* Offset from the stack pointer register to an item dynamically
2284    allocated on the stack, e.g., by `alloca'.
2285
2286    The default value for this macro is `STACK_POINTER_OFFSET' plus the
2287    length of the outgoing arguments.  The default is correct for most
2288    machines.  See `function.c' for details.
2289
2290    The MIPS ABI states that functions which dynamically allocate the
2291    stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2292    we are trying to create a second frame pointer to the function, so
2293    allocate some stack space to make it happy.
2294
2295    However, the linker currently complains about linking any code that
2296    dynamically allocates stack space, and there seems to be a bug in
2297    STACK_DYNAMIC_OFFSET, so don't define this right now.  */
2298
2299 #if 0
2300 #define STACK_DYNAMIC_OFFSET(FUNDECL)                                   \
2301   ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2302         ? 4*UNITS_PER_WORD                                              \
2303         : current_function_outgoing_args_size)
2304 #endif
2305
2306 /* The return address for the current frame is in r31 if this is a leaf
2307    function.  Otherwise, it is on the stack.  It is at a variable offset
2308    from sp/fp/ap, so we define a fake hard register rap which is a
2309    poiner to the return address on the stack.  This always gets eliminated
2310    during reload to be either the frame pointer or the stack pointer plus
2311    an offset.  */
2312
2313 /* ??? This definition fails for leaf functions.  There is currently no
2314    general solution for this problem.  */
2315
2316 /* ??? There appears to be no way to get the return address of any previous
2317    frame except by disassembling instructions in the prologue/epilogue.
2318    So currently we support only the current frame.  */
2319
2320 #define RETURN_ADDR_RTX(count, frame)                                   \
2321   (((count) == 0)                                                       \
2322    ? (leaf_function_p ()                                                \
2323       ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31)                          \
2324       : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode,                         \
2325                                          RETURN_ADDRESS_POINTER_REGNUM))) \
2326    : (rtx) 0)
2327
2328 /* Since the mips16 ISA mode is encoded in the least-significant bit
2329    of the address, mask it off return addresses for purposes of
2330    finding exception handling regions.  */
2331
2332 #define MASK_RETURN_ADDR GEN_INT (-2)
2333
2334 /* Similarly, don't use the least-significant bit to tell pointers to
2335    code from vtable index.  */
2336
2337 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2338
2339 /* If defined, this macro specifies a table of register pairs used to
2340    eliminate unneeded registers that point into the stack frame.  If
2341    it is not defined, the only elimination attempted by the compiler
2342    is to replace references to the frame pointer with references to
2343    the stack pointer.
2344
2345    The definition of this macro is a list of structure
2346    initializations, each of which specifies an original and
2347    replacement register.
2348
2349    On some machines, the position of the argument pointer is not
2350    known until the compilation is completed.  In such a case, a
2351    separate hard register must be used for the argument pointer.
2352    This register can be eliminated by replacing it with either the
2353    frame pointer or the argument pointer, depending on whether or not
2354    the frame pointer has been eliminated.
2355
2356    In this case, you might specify:
2357         #define ELIMINABLE_REGS  \
2358         {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2359          {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2360          {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2361
2362    Note that the elimination of the argument pointer with the stack
2363    pointer is specified first since that is the preferred elimination.
2364
2365    The eliminations to $17 are only used on the mips16.  See the
2366    definition of HARD_FRAME_POINTER_REGNUM.  */
2367
2368 #define ELIMINABLE_REGS                                                 \
2369 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
2370  { ARG_POINTER_REGNUM,   GP_REG_FIRST + 30},                            \
2371  { ARG_POINTER_REGNUM,   GP_REG_FIRST + 17},                            \
2372  { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},                \
2373  { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30},                   \
2374  { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17},                   \
2375  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
2376  { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30},                            \
2377  { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2378
2379 /* A C expression that returns non-zero if the compiler is allowed to
2380    try to replace register number FROM-REG with register number
2381    TO-REG.  This macro need only be defined if `ELIMINABLE_REGS' is
2382    defined, and will usually be the constant 1, since most of the
2383    cases preventing register elimination are things that the compiler
2384    already knows about.
2385
2386    When not in mips16 and mips64, we can always eliminate to the
2387    frame pointer.  We can eliminate to the stack pointer unless
2388    a frame pointer is needed.  In mips16 mode, we need a frame
2389    pointer for a large frame; otherwise, reload may be unable
2390    to compute the address of a local variable, since there is
2391    no way to add a large constant to the stack pointer
2392    without using a temporary register.
2393
2394    In mips16, for some instructions (eg lwu), we can't eliminate the
2395    frame pointer for the stack pointer.  These instructions are
2396    only generated in TARGET_64BIT mode.
2397    */
2398
2399 #define CAN_ELIMINATE(FROM, TO)                                         \
2400   (((FROM) == RETURN_ADDRESS_POINTER_REGNUM                             \
2401     && (((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed)        \
2402         || (TO) == HARD_FRAME_POINTER_REGNUM))                          \
2403    || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM                          \
2404       && ((TO) == HARD_FRAME_POINTER_REGNUM                             \
2405           || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed    \
2406               && ! (TARGET_MIPS16 && TARGET_64BIT)                      \
2407               && (! TARGET_MIPS16                                       \
2408                   || compute_frame_size (get_frame_size ()) < 32768)))))
2409
2410 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2411         (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2412
2413 /* If we generate an insn to push BYTES bytes,
2414    this says how many the stack pointer really advances by.
2415    On the VAX, sp@- in a byte insn really pushes a word.  */
2416
2417 /* #define PUSH_ROUNDING(BYTES) 0 */
2418
2419 /* If defined, the maximum amount of space required for outgoing
2420    arguments will be computed and placed into the variable
2421    `current_function_outgoing_args_size'.  No space will be pushed
2422    onto the stack for each call; instead, the function prologue
2423    should increase the stack frame size by this amount.
2424
2425    It is not proper to define both `PUSH_ROUNDING' and
2426    `ACCUMULATE_OUTGOING_ARGS'.  */
2427 #define ACCUMULATE_OUTGOING_ARGS 1
2428
2429 /* Offset from the argument pointer register to the first argument's
2430    address.  On some machines it may depend on the data type of the
2431    function.
2432
2433    If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2434    the first argument's address.
2435
2436    On the MIPS, we must skip the first argument position if we are
2437    returning a structure or a union, to account for its address being
2438    passed in $4.  However, at the current time, this produces a compiler
2439    that can't bootstrap, so comment it out for now.  */
2440
2441 #if 0
2442 #define FIRST_PARM_OFFSET(FNDECL)                                       \
2443   (FNDECL != 0                                                          \
2444    && TREE_TYPE (FNDECL) != 0                                           \
2445    && TREE_TYPE (TREE_TYPE (FNDECL)) != 0                               \
2446    && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE        \
2447        || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE)     \
2448                 ? UNITS_PER_WORD                                        \
2449                 : 0)
2450 #else
2451 #define FIRST_PARM_OFFSET(FNDECL) 0
2452 #endif
2453
2454 /* When a parameter is passed in a register, stack space is still
2455    allocated for it.  For the MIPS, stack space must be allocated, cf
2456    Asm Lang Prog Guide page 7-8.
2457
2458    BEWARE that some space is also allocated for non existing arguments
2459    in register. In case an argument list is of form GF used registers
2460    are a0 (a2,a3), but we should push over a1...  */
2461
2462 #define REG_PARM_STACK_SPACE(FNDECL)    \
2463   ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2464
2465 /* Define this if it is the responsibility of the caller to
2466    allocate the area reserved for arguments passed in registers.
2467    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2468    of this macro is to determine whether the space is included in
2469    `current_function_outgoing_args_size'.  */
2470 #define OUTGOING_REG_PARM_STACK_SPACE
2471
2472 /* Align stack frames on 64 bits (Double Word ).  */
2473 #ifndef STACK_BOUNDARY
2474 #define STACK_BOUNDARY 64
2475 #endif
2476
2477 /* Make sure 4 words are always allocated on the stack.  */
2478
2479 #ifndef STACK_ARGS_ADJUST
2480 #define STACK_ARGS_ADJUST(SIZE)                                         \
2481 {                                                                       \
2482   if (SIZE.constant < 4 * UNITS_PER_WORD)                               \
2483     SIZE.constant = 4 * UNITS_PER_WORD;                                 \
2484 }
2485 #endif
2486
2487 \f
2488 /* A C expression that should indicate the number of bytes of its
2489    own arguments that a function pops on returning, or 0
2490    if the function pops no arguments and the caller must therefore
2491    pop them all after the function returns.
2492
2493    FUNDECL is the declaration node of the function (as a tree).
2494
2495    FUNTYPE is a C variable whose value is a tree node that
2496    describes the function in question.  Normally it is a node of
2497    type `FUNCTION_TYPE' that describes the data type of the function.
2498    From this it is possible to obtain the data types of the value
2499    and arguments (if known).
2500
2501    When a call to a library function is being considered, FUNTYPE
2502    will contain an identifier node for the library function.  Thus,
2503    if you need to distinguish among various library functions, you
2504    can do so by their names.  Note that "library function" in this
2505    context means a function used to perform arithmetic, whose name
2506    is known specially in the compiler and was not mentioned in the
2507    C code being compiled.
2508
2509    STACK-SIZE is the number of bytes of arguments passed on the
2510    stack.  If a variable number of bytes is passed, it is zero, and
2511    argument popping will always be the responsibility of the
2512    calling function.  */
2513
2514 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2515
2516
2517 /* Symbolic macros for the registers used to return integer and floating
2518    point values.  */
2519
2520 #define GP_RETURN (GP_REG_FIRST + 2)
2521 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2522
2523 /* Symbolic macros for the first/last argument registers.  */
2524
2525 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2526 #define GP_ARG_LAST  (GP_REG_FIRST + 7)
2527 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2528 #define FP_ARG_LAST  (FP_REG_FIRST + 15)
2529
2530 #define MAX_ARGS_IN_REGISTERS   4
2531
2532 /* Define how to find the value returned by a library function
2533    assuming the value has mode MODE.  Because we define
2534    PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2535    PROMOTE_MODE does.  */
2536
2537 #define LIBCALL_VALUE(MODE) \
2538   mips_function_value (NULL_TREE, NULL, (MODE))
2539
2540 /* Define how to find the value returned by a function.
2541    VALTYPE is the data type of the value (as a tree).
2542    If the precise function being called is known, FUNC is its FUNCTION_DECL;
2543    otherwise, FUNC is 0.  */
2544
2545 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2546   mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2547
2548 /* 1 if N is a possible register number for a function value.
2549    On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2550    Currently, R2 and F0 are only implemented  here (C has no complex type)  */
2551
2552 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2553
2554 /* 1 if N is a possible register number for function argument passing.
2555    We have no FP argument registers when soft-float.  When FP registers
2556    are 32 bits, we can't directly reference the odd numbered ones.  */
2557 /* For o64 we should be checking the mode for SFmode as well.  */
2558
2559 #define FUNCTION_ARG_REGNO_P(N)                                 \
2560   ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST)                    \
2561     || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST)                \
2562         && ((N) % FP_INC == 0) && mips_abi != ABI_O64))         \
2563    && !fixed_regs[N])
2564
2565 /* A C expression which can inhibit the returning of certain function
2566    values in registers, based on the type of value.  A nonzero value says
2567    to return the function value in memory, just as large structures are
2568    always returned.  Here TYPE will be a C expression of type
2569    `tree', representing the data type of the value.
2570
2571    Note that values of mode `BLKmode' must be explicitly
2572    handled by this macro.  Also, the option `-fpcc-struct-return'
2573    takes effect regardless of this macro.  On most systems, it is
2574    possible to leave the macro undefined; this causes a default
2575    definition to be used, whose value is the constant 1 for BLKmode
2576    values, and 0 otherwise.
2577
2578    GCC normally converts 1 byte structures into chars, 2 byte
2579    structs into shorts, and 4 byte structs into ints, and returns
2580    them this way.  Defining the following macro overrides this,
2581    to give us MIPS cc compatibility.  */
2582
2583 #define RETURN_IN_MEMORY(TYPE)  \
2584         mips_return_in_memory (TYPE)
2585
2586 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL)       \
2587         (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE),   \
2588                                                       (TYPE), (NO_RTL))
2589 \f
2590
2591 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2592
2593 \f
2594 /* Define a data type for recording info about an argument list
2595    during the scan of that argument list.  This data type should
2596    hold all necessary information about the function itself
2597    and about the args processed so far, enough to enable macros
2598    such as FUNCTION_ARG to determine where the next arg should go.
2599
2600    This structure has to cope with two different argument allocation
2601    schemes.  Most MIPS ABIs view the arguments as a struct, of which the
2602    first N words go in registers and the rest go on the stack.  If I < N,
2603    the Ith word might go in Ith integer argument register or the
2604    Ith floating-point one.  In some cases, it has to go in both (see
2605    function_arg).  For these ABIs, we only need to remember the number
2606    of words passed so far.
2607
2608    The EABI instead allocates the integer and floating-point arguments
2609    separately.  The first N words of FP arguments go in FP registers,
2610    the rest go on the stack.  Likewise, the first N words of the other
2611    arguments go in integer registers, and the rest go on the stack.  We
2612    need to maintain three counts: the number of integer registers used,
2613    the number of floating-point registers used, and the number of words
2614    passed on the stack.
2615
2616    We could keep separate information for the two ABIs (a word count for
2617    the standard ABIs, and three separate counts for the EABI).  But it
2618    seems simpler to view the standard ABIs as forms of EABI that do not
2619    allocate floating-point registers.
2620
2621    So for the standard ABIs, the first N words are allocated to integer
2622    registers, and function_arg decides on an argument-by-argument basis
2623    whether that argument should really go in an integer register, or in
2624    a floating-point one.  */
2625
2626 typedef struct mips_args {
2627   /* Always true for varargs functions.  Otherwise true if at least
2628      one argument has been passed in an integer register.  */
2629   int gp_reg_found;
2630
2631   /* The number of arguments seen so far.  */
2632   unsigned int arg_number;
2633
2634   /* For EABI, the number of integer registers used so far.  For other
2635      ABIs, the number of words passed in registers (whether integer
2636      or floating-point).  */
2637   unsigned int num_gprs;
2638
2639   /* For EABI, the number of floating-point registers used so far.  */
2640   unsigned int num_fprs;
2641
2642   /* The number of words passed on the stack.  */
2643   unsigned int stack_words;
2644
2645   /* On the mips16, we need to keep track of which floating point
2646      arguments were passed in general registers, but would have been
2647      passed in the FP regs if this were a 32 bit function, so that we
2648      can move them to the FP regs if we wind up calling a 32 bit
2649      function.  We record this information in fp_code, encoded in base
2650      four.  A zero digit means no floating point argument, a one digit
2651      means an SFmode argument, and a two digit means a DFmode argument,
2652      and a three digit is not used.  The low order digit is the first
2653      argument.  Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2654      an SFmode argument.  ??? A more sophisticated approach will be
2655      needed if MIPS_ABI != ABI_32.  */
2656   int fp_code;
2657
2658   /* True if the function has a prototype.  */
2659   int prototype;
2660
2661   /* When a structure does not take up a full register, the argument
2662      should sometimes be shifted left so that it occupies the high part
2663      of the register.  These two fields describe an array of ashl
2664      patterns for doing this.  See function_arg_advance, which creates
2665      the shift patterns, and function_arg, which returns them when given
2666      a VOIDmode argument.  */
2667   unsigned int num_adjusts;
2668   rtx adjust[MAX_ARGS_IN_REGISTERS];
2669 } CUMULATIVE_ARGS;
2670
2671 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2672    for a call to a function whose data type is FNTYPE.
2673    For a library call, FNTYPE is 0.
2674
2675 */
2676
2677 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)               \
2678   init_cumulative_args (&CUM, FNTYPE, LIBNAME)                          \
2679
2680 /* Update the data in CUM to advance over an argument
2681    of mode MODE and data type TYPE.
2682    (TYPE is null for libcalls where that information may not be available.)  */
2683
2684 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)                    \
2685   function_arg_advance (&CUM, MODE, TYPE, NAMED)
2686
2687 /* Determine where to put an argument to a function.
2688    Value is zero to push the argument on the stack,
2689    or a hard register in which to store the argument.
2690
2691    MODE is the argument's machine mode.
2692    TYPE is the data type of the argument (as a tree).
2693     This is null for libcalls where that information may
2694     not be available.
2695    CUM is a variable of type CUMULATIVE_ARGS which gives info about
2696     the preceding args and about the function being called.
2697    NAMED is nonzero if this argument is a named parameter
2698     (otherwise it is an extra parameter matching an ellipsis).  */
2699
2700 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2701   function_arg( &CUM, MODE, TYPE, NAMED)
2702
2703 /* For an arg passed partly in registers and partly in memory,
2704    this is the number of registers used.
2705    For args passed entirely in registers or entirely in memory, zero.  */
2706
2707 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2708   function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2709
2710 /* If defined, a C expression that gives the alignment boundary, in
2711    bits, of an argument with the specified mode and type.  If it is
2712    not defined,  `PARM_BOUNDARY' is used for all arguments.  */
2713
2714 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE)                               \
2715   (((TYPE) != 0)                                                        \
2716         ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY)                          \
2717                 ? PARM_BOUNDARY                                         \
2718                 : TYPE_ALIGN(TYPE))                                     \
2719         : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY)                  \
2720                 ? PARM_BOUNDARY                                         \
2721                 : GET_MODE_ALIGNMENT(MODE)))
2722
2723 /* True if using EABI and varargs can be passed in floating-point
2724    registers.  Under these conditions, we need a more complex form
2725    of va_list, which tracks GPR, FPR and stack arguments separately.  */
2726 #define EABI_FLOAT_VARARGS_P \
2727         (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2728
2729 \f
2730 /* Tell prologue and epilogue if register REGNO should be saved / restored.  */
2731
2732 #define MUST_SAVE_REGISTER(regno) \
2733  ((regs_ever_live[regno] && !call_used_regs[regno])                     \
2734   || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)       \
2735   || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2736
2737 /* ALIGN FRAMES on double word boundaries */
2738 #ifndef MIPS_STACK_ALIGN
2739 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2740 #endif
2741
2742 \f
2743 /* Define the `__builtin_va_list' type for the ABI.  */
2744 #define BUILD_VA_LIST_TYPE(VALIST) \
2745   (VALIST) = mips_build_va_list ()
2746
2747 /* Implement `va_start' for varargs and stdarg.  */
2748 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2749   mips_va_start (stdarg, valist, nextarg)
2750
2751 /* Implement `va_arg'.  */
2752 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2753   mips_va_arg (valist, type)
2754 \f
2755 /* Output assembler code to FILE to increment profiler label # LABELNO
2756    for profiling a function entry.  */
2757
2758 #define FUNCTION_PROFILER(FILE, LABELNO)                                \
2759 {                                                                       \
2760   if (TARGET_MIPS16)                                                    \
2761     sorry ("mips16 function profiling");                                \
2762   fprintf (FILE, "\t.set\tnoat\n");                                     \
2763   fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",    \
2764            reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);  \
2765   fprintf (FILE,                                                        \
2766            "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",    \
2767            TARGET_64BIT ? "dsubu" : "subu",                             \
2768            reg_names[STACK_POINTER_REGNUM],                             \
2769            reg_names[STACK_POINTER_REGNUM],                             \
2770            Pmode == DImode ? 16 : 8);                                   \
2771   fprintf (FILE, "\tjal\t_mcount\n");                                   \
2772   fprintf (FILE, "\t.set\tat\n");                                       \
2773 }
2774
2775 /* Define this macro if the code for function profiling should come
2776    before the function prologue.  Normally, the profiling code comes
2777    after.  */
2778
2779 /* #define PROFILE_BEFORE_PROLOGUE */
2780
2781 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2782    the stack pointer does not matter.  The value is tested only in
2783    functions that have frame pointers.
2784    No definition is equivalent to always zero.  */
2785
2786 #define EXIT_IGNORE_STACK 1
2787
2788 \f
2789 /* A C statement to output, on the stream FILE, assembler code for a
2790    block of data that contains the constant parts of a trampoline.
2791    This code should not include a label--the label is taken care of
2792    automatically.  */
2793
2794 #define TRAMPOLINE_TEMPLATE(STREAM)                                      \
2795 {                                                                        \
2796   fprintf (STREAM, "\t.word\t0x03e00821\t\t# move   $1,$31\n");         \
2797   fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n");         \
2798   fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n");                   \
2799   if (Pmode == DImode)                                                  \
2800     {                                                                   \
2801       fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld     $3,20($31)\n"); \
2802       fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld     $2,28($31)\n"); \
2803     }                                                                   \
2804   else                                                                  \
2805     {                                                                   \
2806       fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw     $3,20($31)\n"); \
2807       fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw     $2,24($31)\n"); \
2808     }                                                                   \
2809   fprintf (STREAM, "\t.word\t0x0060c821\t\t# move   $25,$3 (abicalls)\n"); \
2810   fprintf (STREAM, "\t.word\t0x00600008\t\t# jr     $3\n");             \
2811   fprintf (STREAM, "\t.word\t0x0020f821\t\t# move   $31,$1\n");         \
2812   if (Pmode == DImode)                                                  \
2813     {                                                                   \
2814       fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2815       fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2816     }                                                                   \
2817   else                                                                  \
2818     {                                                                   \
2819       fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2820       fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2821     }                                                                   \
2822 }
2823
2824 /* A C expression for the size in bytes of the trampoline, as an
2825    integer.  */
2826
2827 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2828
2829 /* Alignment required for trampolines, in bits.  */
2830
2831 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2832
2833 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2834    program and data caches.  */
2835
2836 #ifndef CACHE_FLUSH_FUNC
2837 #define CACHE_FLUSH_FUNC "_flush_cache"
2838 #endif
2839
2840 /* A C statement to initialize the variable parts of a trampoline.
2841    ADDR is an RTX for the address of the trampoline; FNADDR is an
2842    RTX for the address of the nested function; STATIC_CHAIN is an
2843    RTX for the static chain value that should be passed to the
2844    function when it is called.  */
2845
2846 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN)                            \
2847 {                                                                           \
2848   rtx addr = ADDR;                                                          \
2849   if (Pmode == DImode)                                                      \
2850     {                                                                       \
2851       emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2852       emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2853     }                                                                       \
2854   else                                                                      \
2855     {                                                                       \
2856       emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2857       emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2858     }                                                                       \
2859                                                                             \
2860   /* Flush both caches.  We need to flush the data cache in case            \
2861      the system has a write-back cache.  */                                 \
2862   /* ??? Should check the return value for errors.  */                      \
2863   if (mips_cache_flush_func && mips_cache_flush_func[0])                    \
2864     emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func),   \
2865                        0, VOIDmode, 3, addr, Pmode,                         \
2866                        GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2867                        GEN_INT (3), TYPE_MODE (integer_type_node));         \
2868 }
2869 \f
2870 /* Addressing modes, and classification of registers for them.  */
2871
2872 /* #define HAVE_POST_INCREMENT 0 */
2873 /* #define HAVE_POST_DECREMENT 0 */
2874
2875 /* #define HAVE_PRE_DECREMENT 0 */
2876 /* #define HAVE_PRE_INCREMENT 0 */
2877
2878 /* These assume that REGNO is a hard or pseudo reg number.
2879    They give nonzero only if REGNO is a hard reg of the suitable class
2880    or a pseudo reg currently allocated to a suitable hard reg.
2881    These definitions are NOT overridden anywhere.  */
2882
2883 #define BASE_REG_P(regno, mode)                                 \
2884   (TARGET_MIPS16                                                \
2885    ? (M16_REG_P (regno)                                         \
2886       || (regno) == FRAME_POINTER_REGNUM                        \
2887       || (regno) == ARG_POINTER_REGNUM                          \
2888       || ((regno) == STACK_POINTER_REGNUM                       \
2889           && (GET_MODE_SIZE (mode) == 4                         \
2890               || GET_MODE_SIZE (mode) == 8)))                   \
2891    : GP_REG_P (regno))
2892
2893 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)                              \
2894   BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2895              (mode))
2896
2897 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2898   (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2899
2900 #define REGNO_OK_FOR_INDEX_P(regno)     0
2901 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2902   GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2903
2904 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2905    and check its validity for a certain class.
2906    We have two alternate definitions for each of them.
2907    The usual definition accepts all pseudo regs; the other rejects them all.
2908    The symbol REG_OK_STRICT causes the latter definition to be used.
2909
2910    Most source files want to accept pseudo regs in the hope that
2911    they will get allocated to the class that the insn wants them to be in.
2912    Some source files that are used after register allocation
2913    need to be strict.  */
2914
2915 #ifndef REG_OK_STRICT
2916 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2917   mips_reg_mode_ok_for_base_p (X, MODE, 0)
2918 #else
2919 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2920   mips_reg_mode_ok_for_base_p (X, MODE, 1)
2921 #endif
2922
2923 #define REG_OK_FOR_INDEX_P(X) 0
2924
2925 \f
2926 /* Maximum number of registers that can appear in a valid memory address.  */
2927
2928 #define MAX_REGS_PER_ADDRESS 1
2929
2930 /* A C compound statement with a conditional `goto LABEL;' executed
2931    if X (an RTX) is a legitimate memory address on the target
2932    machine for a memory operand of mode MODE.  */
2933
2934 #if 1
2935 #define GO_PRINTF(x)    fprintf(stderr, (x))
2936 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2937 #define GO_DEBUG_RTX(x) debug_rtx(x)
2938
2939 #else
2940 #define GO_PRINTF(x)
2941 #define GO_PRINTF2(x,y)
2942 #define GO_DEBUG_RTX(x)
2943 #endif
2944
2945 #ifdef REG_OK_STRICT
2946 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2947 {                                               \
2948   if (mips_legitimate_address_p (MODE, X, 1))   \
2949     goto ADDR;                                  \
2950 }
2951 #else
2952 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2953 {                                               \
2954   if (mips_legitimate_address_p (MODE, X, 0))   \
2955     goto ADDR;                                  \
2956 }
2957 #endif
2958
2959 /* A C expression that is 1 if the RTX X is a constant which is a
2960    valid address.  This is defined to be the same as `CONSTANT_P (X)',
2961    but rejecting CONST_DOUBLE.  */
2962 /* When pic, we must reject addresses of the form symbol+large int.
2963    This is because an instruction `sw $4,s+70000' needs to be converted
2964    by the assembler to `lw $at,s($gp);sw $4,70000($at)'.  Normally the
2965    assembler would use $at as a temp to load in the large offset.  In this
2966    case $at is already in use.  We convert such problem addresses to
2967    `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS.  */
2968 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them
2969    when !TARGET_GAS.  */
2970 /* We should be rejecting everything but const addresses.  */
2971 #define CONSTANT_ADDRESS_P(X)                                           \
2972   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF              \
2973     || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH                \
2974     || (GET_CODE (X) == CONST                                           \
2975         && ! (flag_pic && pic_address_needs_scratch (X))                \
2976         && (TARGET_GAS)                                                 \
2977         && (mips_abi != ABI_N32                                         \
2978             && mips_abi != ABI_64)))
2979
2980
2981 /* Define this, so that when PIC, reload won't try to reload invalid
2982    addresses which require two reload registers.  */
2983
2984 #define LEGITIMATE_PIC_OPERAND_P(X)  (! pic_address_needs_scratch (X))
2985
2986 /* Nonzero if the constant value X is a legitimate general operand.
2987    It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2988
2989    At present, GAS doesn't understand li.[sd], so don't allow it
2990    to be generated at present.  Also, the MIPS assembler does not
2991    grok li.d Infinity.  */
2992
2993 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
2994    Note that the Irix 6 assembler problem may already be fixed.
2995    Note also that the GET_CODE (X) == CONST test catches the mips16
2996    gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
2997    a LEGITIMATE_CONSTANT.  If we ever want mips16 and ABI_N32 or
2998    ABI_64 to work together, we'll need to fix this.  */
2999 #define LEGITIMATE_CONSTANT_P(X)                                        \
3000   ((GET_CODE (X) != CONST_DOUBLE                                        \
3001     || mips_const_double_ok (X, GET_MODE (X)))                          \
3002    && ! (GET_CODE (X) == CONST                                          \
3003          && ! TARGET_GAS                                                \
3004          && (mips_abi == ABI_N32                                        \
3005              || mips_abi == ABI_64))                                    \
3006    && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
3007
3008 /* A C compound statement that attempts to replace X with a valid
3009    memory address for an operand of mode MODE.  WIN will be a C
3010    statement label elsewhere in the code; the macro definition may
3011    use
3012
3013           GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3014
3015    to avoid further processing if the address has become legitimate.
3016
3017    X will always be the result of a call to `break_out_memory_refs',
3018    and OLDX will be the operand that was given to that function to
3019    produce X.
3020
3021    The code generated by this macro should not alter the
3022    substructure of X.  If it transforms X into a more legitimate
3023    form, it should assign X (which will always be a C variable) a
3024    new value.
3025
3026    It is not necessary for this macro to come up with a legitimate
3027    address.  The compiler has standard ways of doing so in all
3028    cases.  In fact, it is safe for this macro to do nothing.  But
3029    often a machine-dependent strategy can generate better code.
3030
3031    For the MIPS, transform:
3032
3033         memory(X + <large int>)
3034
3035    into:
3036
3037         Y = <large int> & ~0x7fff;
3038         Z = X + Y
3039         memory (Z + (<large int> & 0x7fff));
3040
3041    This is for CSE to find several similar references, and only use one Z.
3042
3043    When PIC, convert addresses of the form memory (symbol+large int) to
3044    memory (reg+large int).  */
3045
3046
3047 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)                             \
3048 {                                                                       \
3049   register rtx xinsn = (X);                                             \
3050                                                                         \
3051   if (TARGET_DEBUG_B_MODE)                                              \
3052     {                                                                   \
3053       GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n");                  \
3054       GO_DEBUG_RTX (xinsn);                                             \
3055     }                                                                   \
3056                                                                         \
3057   if (mips_split_addresses && mips_check_split (X, MODE))               \
3058     {                                                                   \
3059       /* ??? Is this ever executed?  */                                 \
3060       X = gen_rtx_LO_SUM (Pmode,                                        \
3061                           copy_to_mode_reg (Pmode,                      \
3062                                             gen_rtx (HIGH, Pmode, X)),  \
3063                           X);                                           \
3064       goto WIN;                                                         \
3065     }                                                                   \
3066                                                                         \
3067   if (GET_CODE (xinsn) == CONST                                         \
3068       && ((flag_pic && pic_address_needs_scratch (xinsn))               \
3069           /* ??? SGI's Irix 6 assembler can't handle CONST.  */         \
3070           || (!TARGET_GAS                                               \
3071               && (mips_abi == ABI_N32                                   \
3072                   || mips_abi == ABI_64))))                             \
3073     {                                                                   \
3074       rtx ptr_reg = gen_reg_rtx (Pmode);                                \
3075       rtx constant = XEXP (XEXP (xinsn, 0), 1);                         \
3076                                                                         \
3077       emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0));              \
3078                                                                         \
3079       X = gen_rtx_PLUS (Pmode, ptr_reg, constant);                      \
3080       if (SMALL_INT (constant))                                         \
3081         goto WIN;                                                       \
3082       /* Otherwise we fall through so the code below will fix the       \
3083          constant.  */                                                  \
3084       xinsn = X;                                                        \
3085     }                                                                   \
3086                                                                         \
3087   if (GET_CODE (xinsn) == PLUS)                                         \
3088     {                                                                   \
3089       register rtx xplus0 = XEXP (xinsn, 0);                            \
3090       register rtx xplus1 = XEXP (xinsn, 1);                            \
3091       register enum rtx_code code0 = GET_CODE (xplus0);                 \
3092       register enum rtx_code code1 = GET_CODE (xplus1);                 \
3093                                                                         \
3094       if (code0 != REG && code1 == REG)                                 \
3095         {                                                               \
3096           xplus0 = XEXP (xinsn, 1);                                     \
3097           xplus1 = XEXP (xinsn, 0);                                     \
3098           code0 = GET_CODE (xplus0);                                    \
3099           code1 = GET_CODE (xplus1);                                    \
3100         }                                                               \
3101                                                                         \
3102       if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)         \
3103           && code1 == CONST_INT && !SMALL_INT (xplus1))                 \
3104         {                                                               \
3105           rtx int_reg = gen_reg_rtx (Pmode);                            \
3106           rtx ptr_reg = gen_reg_rtx (Pmode);                            \
3107                                                                         \
3108           emit_move_insn (int_reg,                                      \
3109                           GEN_INT (INTVAL (xplus1) & ~ 0x7fff));        \
3110                                                                         \
3111           emit_insn (gen_rtx_SET (VOIDmode,                             \
3112                                   ptr_reg,                              \
3113                                   gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3114                                                                         \
3115           X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff);        \
3116           goto WIN;                                                     \
3117         }                                                               \
3118     }                                                                   \
3119                                                                         \
3120   if (TARGET_DEBUG_B_MODE)                                              \
3121     GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n");                  \
3122 }
3123
3124
3125 /* A C statement or compound statement with a conditional `goto
3126    LABEL;' executed if memory address X (an RTX) can have different
3127    meanings depending on the machine mode of the memory reference it
3128    is used for.
3129
3130    Autoincrement and autodecrement addresses typically have
3131    mode-dependent effects because the amount of the increment or
3132    decrement is the size of the operand being addressed.  Some
3133    machines have other mode-dependent addresses.  Many RISC machines
3134    have no mode-dependent addresses.
3135
3136    You may assume that ADDR is a valid address for the machine.  */
3137
3138 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3139
3140 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3141    'the start of the function that this code is output in'.  */
3142
3143 #define ASM_OUTPUT_LABELREF(FILE,NAME)  \
3144   if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)                         \
3145     asm_fprintf ((FILE), "%U%s",                                        \
3146                  XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3147   else                                                                  \
3148     asm_fprintf ((FILE), "%U%s", (NAME))
3149
3150 /* The mips16 wants the constant pool to be after the function,
3151    because the PC relative load instructions use unsigned offsets.  */
3152
3153 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3154
3155 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE)    \
3156   mips_string_length = 0;
3157
3158 #if 0
3159 /* In mips16 mode, put most string constants after the function.  */
3160 #define CONSTANT_AFTER_FUNCTION_P(tree)                         \
3161   (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3162 #endif
3163 \f
3164 /* Specify the machine mode that this machine uses
3165    for the index in the tablejump instruction.
3166    ??? Using HImode in mips16 mode can cause overflow.  However, the
3167    overflow is no more likely than the overflow in a branch
3168    instruction.  Large functions can currently break in both ways.  */
3169 #define CASE_VECTOR_MODE \
3170   (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3171
3172 /* Define as C expression which evaluates to nonzero if the tablejump
3173    instruction expects the table to contain offsets from the address of the
3174    table.
3175    Do not define this if the table should contain absolute addresses.  */
3176 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3177
3178 /* Define this as 1 if `char' should by default be signed; else as 0.  */
3179 #ifndef DEFAULT_SIGNED_CHAR
3180 #define DEFAULT_SIGNED_CHAR 1
3181 #endif
3182
3183 /* Max number of bytes we can move from memory to memory
3184    in one reasonably fast instruction.  */
3185 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3186 #define MAX_MOVE_MAX 8
3187
3188 /* Define this macro as a C expression which is nonzero if
3189    accessing less than a word of memory (i.e. a `char' or a
3190    `short') is no faster than accessing a word of memory, i.e., if
3191    such access require more than one instruction or if there is no
3192    difference in cost between byte and (aligned) word loads.
3193
3194    On RISC machines, it tends to generate better code to define
3195    this as 1, since it avoids making a QI or HI mode register.  */
3196 #define SLOW_BYTE_ACCESS 1
3197
3198 /* We assume that the store-condition-codes instructions store 0 for false
3199    and some other value for true.  This is the value stored for true.  */
3200
3201 #define STORE_FLAG_VALUE 1
3202
3203 /* Define this to be nonzero if shift instructions ignore all but the low-order
3204    few bits.  */
3205 #define SHIFT_COUNT_TRUNCATED 1
3206
3207 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3208    is done just by pretending it is already truncated.  */
3209 /* In 64 bit mode, 32 bit instructions require that register values be properly
3210    sign-extended to 64 bits.  As a result, a truncate is not a no-op if it
3211    converts a value >32 bits to a value <32 bits.  */
3212 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3213    Something needs to be done about this.  Perhaps not use any 32 bit
3214    instructions?  Perhaps use PROMOTE_MODE?  */
3215 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3216   (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3217
3218 /* Specify the machine mode that pointers have.
3219    After generation of rtl, the compiler makes no further distinction
3220    between pointers and any other objects of this machine mode.
3221
3222    For MIPS we make pointers are the smaller of longs and gp-registers.  */
3223
3224 #ifndef Pmode
3225 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3226 #endif
3227
3228 /* A function address in a call instruction
3229    is a word address (for indexing purposes)
3230    so give the MEM rtx a words's mode.  */
3231
3232 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3233
3234 \f
3235 /* A part of a C `switch' statement that describes the relative
3236    costs of constant RTL expressions.  It must contain `case'
3237    labels for expression codes `const_int', `const', `symbol_ref',
3238    `label_ref' and `const_double'.  Each case must ultimately reach
3239    a `return' statement to return the relative cost of the use of
3240    that kind of constant value in an expression.  The cost may
3241    depend on the precise value of the constant, which is available
3242    for examination in X.
3243
3244    CODE is the expression code--redundant, since it can be obtained
3245    with `GET_CODE (X)'.  */
3246
3247 #define CONST_COSTS(X,CODE,OUTER_CODE)                                  \
3248   case CONST_INT:                                                       \
3249     if (! TARGET_MIPS16)                                                \
3250       {                                                                 \
3251         /* Always return 0, since we don't have different sized         \
3252            instructions, hence different costs according to Richard     \
3253            Kenner */                                                    \
3254         return 0;                                                       \
3255       }                                                                 \
3256     if ((OUTER_CODE) == SET)                                            \
3257       {                                                                 \
3258         if (INTVAL (X) >= 0 && INTVAL (X) < 0x100)                      \
3259           return 0;                                                     \
3260         else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000)              \
3261                  || (INTVAL (X) < 0 && INTVAL (X) > -0x100))            \
3262           return COSTS_N_INSNS (1);                                     \
3263         else                                                            \
3264           return COSTS_N_INSNS (2);                                     \
3265       }                                                                 \
3266     /* A PLUS could be an address.  We don't want to force an address   \
3267        to use a register, so accept any signed 16 bit value without     \
3268        complaint.  */                                                   \
3269     if ((OUTER_CODE) == PLUS                                            \
3270         && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000)                \
3271       return 0;                                                         \
3272     /* A number between 1 and 8 inclusive is efficient for a shift.     \
3273        Otherwise, we will need an extended instruction.  */             \
3274     if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT              \
3275         || (OUTER_CODE) == LSHIFTRT)                                    \
3276       {                                                                 \
3277         if (INTVAL (X) >= 1 && INTVAL (X) <= 8)                         \
3278           return 0;                                                     \
3279         return COSTS_N_INSNS (1);                                       \
3280       }                                                                 \
3281     /* We can use cmpi for an xor with an unsigned 16 bit value.  */    \
3282     if ((OUTER_CODE) == XOR                                             \
3283         && INTVAL (X) >= 0 && INTVAL (X) < 0x10000)                     \
3284       return 0;                                                         \
3285     /* We may be able to use slt or sltu for a comparison with a        \
3286        signed 16 bit value.  (The boundary conditions aren't quite      \
3287        right, but this is just a heuristic anyhow.)  */                 \
3288     if (((OUTER_CODE) == LT || (OUTER_CODE) == LE                       \
3289          || (OUTER_CODE) == GE || (OUTER_CODE) == GT                    \
3290          || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU                  \
3291          || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU)                 \
3292         && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000)                \
3293       return 0;                                                         \
3294     /* Equality comparisons with 0 are cheap.  */                       \
3295     if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE)                      \
3296         && INTVAL (X) == 0)                                             \
3297       return 0;                                                         \
3298                                                                         \
3299     /* Otherwise, work out the cost to load the value into a            \
3300        register.  */                                                    \
3301     if (INTVAL (X) >= 0 && INTVAL (X) < 0x100)                          \
3302       return COSTS_N_INSNS (1);                                         \
3303     else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000)                  \
3304              || (INTVAL (X) < 0 && INTVAL (X) > -0x100))                \
3305       return COSTS_N_INSNS (2);                                         \
3306     else                                                                \
3307       return COSTS_N_INSNS (3);                                         \
3308                                                                         \
3309   case LABEL_REF:                                                       \
3310     return COSTS_N_INSNS (2);                                           \
3311                                                                         \
3312   case CONST:                                                           \
3313     {                                                                   \
3314       rtx offset = const0_rtx;                                          \
3315       rtx symref = eliminate_constant_term (XEXP (X, 0), &offset);      \
3316                                                                         \
3317       if (TARGET_MIPS16 && mips16_gp_offset_p (X))                      \
3318         {                                                               \
3319           /* Treat this like a signed 16 bit CONST_INT.  */             \
3320           if ((OUTER_CODE) == PLUS)                                     \
3321             return 0;                                                   \
3322           else if ((OUTER_CODE) == SET)                                 \
3323             return COSTS_N_INSNS (1);                                   \
3324           else                                                          \
3325             return COSTS_N_INSNS (2);                                   \
3326         }                                                               \
3327                                                                         \
3328       if (GET_CODE (symref) == LABEL_REF)                               \
3329         return COSTS_N_INSNS (2);                                       \
3330                                                                         \
3331       if (GET_CODE (symref) != SYMBOL_REF)                              \
3332         return COSTS_N_INSNS (4);                                       \
3333                                                                         \
3334       /* let's be paranoid....  */                                      \
3335       if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767)          \
3336         return COSTS_N_INSNS (2);                                       \
3337                                                                         \
3338       return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2);          \
3339     }                                                                   \
3340                                                                         \
3341   case SYMBOL_REF:                                                      \
3342     return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2);                 \
3343                                                                         \
3344   case CONST_DOUBLE:                                                    \
3345     {                                                                   \
3346       rtx high, low;                                                    \
3347       if (TARGET_MIPS16)                                                \
3348         return COSTS_N_INSNS (4);                                       \
3349       split_double (X, &high, &low);                                    \
3350       return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high))       \
3351                              || low == CONST0_RTX (GET_MODE (low)))     \
3352                             ? 2 : 4);                                   \
3353     }
3354
3355 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3356    This can be used, for example, to indicate how costly a multiply
3357    instruction is.  In writing this macro, you can use the construct
3358    `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3359
3360    This macro is optional; do not define it if the default cost
3361    assumptions are adequate for the target machine.
3362
3363    If -mdebugd is used, change the multiply cost to 2, so multiply by
3364    a constant isn't converted to a series of shifts.  This helps
3365    strength reduction, and also makes it easier to identify what the
3366    compiler is doing.  */
3367
3368 /* ??? Fix this to be right for the R8000.  */
3369 #define RTX_COSTS(X,CODE,OUTER_CODE)                                    \
3370   case MEM:                                                             \
3371     {                                                                   \
3372       int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3373       if (simple_memory_operand (X, GET_MODE (X)))                      \
3374         return COSTS_N_INSNS (num_words);                               \
3375                                                                         \
3376       return COSTS_N_INSNS (2*num_words);                               \
3377     }                                                                   \
3378                                                                         \
3379   case FFS:                                                             \
3380     return COSTS_N_INSNS (6);                                           \
3381                                                                         \
3382   case NOT:                                                             \
3383     return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3384                                                                         \
3385   case AND:                                                             \
3386   case IOR:                                                             \
3387   case XOR:                                                             \
3388     if (GET_MODE (X) == DImode && !TARGET_64BIT)                        \
3389       return COSTS_N_INSNS (2);                                         \
3390                                                                         \
3391     break;                                                              \
3392                                                                         \
3393   case ASHIFT:                                                          \
3394   case ASHIFTRT:                                                        \
3395   case LSHIFTRT:                                                        \
3396     if (GET_MODE (X) == DImode && !TARGET_64BIT)                        \
3397       return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3398                                                                         \
3399     break;                                                              \
3400                                                                         \
3401   case ABS:                                                             \
3402     {                                                                   \
3403       enum machine_mode xmode = GET_MODE (X);                           \
3404       if (xmode == SFmode || xmode == DFmode)                           \
3405         return COSTS_N_INSNS (1);                                       \
3406                                                                         \
3407       return COSTS_N_INSNS (4);                                         \
3408     }                                                                   \
3409                                                                         \
3410   case PLUS:                                                            \
3411   case MINUS:                                                           \
3412     {                                                                   \
3413       enum machine_mode xmode = GET_MODE (X);                           \
3414       if (xmode == SFmode || xmode == DFmode)                           \
3415         {                                                               \
3416           if (TUNE_MIPS3000                                             \
3417               || TUNE_MIPS3900)                                         \
3418             return COSTS_N_INSNS (2);                                   \
3419           else if (TUNE_MIPS6000)                                       \
3420             return COSTS_N_INSNS (3);                                   \
3421           else                                                          \
3422             return COSTS_N_INSNS (6);                                   \
3423         }                                                               \
3424                                                                         \
3425       if (xmode == DImode && !TARGET_64BIT)                             \
3426         return COSTS_N_INSNS (4);                                       \
3427                                                                         \
3428       break;                                                            \
3429     }                                                                   \
3430                                                                         \
3431   case NEG:                                                             \
3432     if (GET_MODE (X) == DImode && !TARGET_64BIT)                        \
3433       return 4;                                                         \
3434                                                                         \
3435     break;                                                              \
3436                                                                         \
3437   case MULT:                                                            \
3438     {                                                                   \
3439       enum machine_mode xmode = GET_MODE (X);                           \
3440       if (xmode == SFmode)                                              \
3441         {                                                               \
3442           if (TUNE_MIPS3000                                             \
3443               || TUNE_MIPS3900                                          \
3444               || TUNE_MIPS5000)                                         \
3445             return COSTS_N_INSNS (4);                                   \
3446           else if (TUNE_MIPS6000)                                       \
3447             return COSTS_N_INSNS (5);                                   \
3448           else                                                          \
3449             return COSTS_N_INSNS (7);                                   \
3450         }                                                               \
3451                                                                         \
3452       if (xmode == DFmode)                                              \
3453         {                                                               \
3454           if (TUNE_MIPS3000                                             \
3455               || TUNE_MIPS3900                                          \
3456               || TUNE_MIPS5000)                                         \
3457             return COSTS_N_INSNS (5);                                   \
3458           else if (TUNE_MIPS6000)                                       \
3459             return COSTS_N_INSNS (6);                                   \
3460           else                                                          \
3461             return COSTS_N_INSNS (8);                                   \
3462         }                                                               \
3463                                                                         \
3464       if (TUNE_MIPS3000)                                                \
3465         return COSTS_N_INSNS (12);                                      \
3466       else if (TUNE_MIPS3900)                                           \
3467         return COSTS_N_INSNS (2);                                       \
3468       else if (TUNE_MIPS6000)                                           \
3469         return COSTS_N_INSNS (17);                                      \
3470       else if (TUNE_MIPS5000)                                           \
3471         return COSTS_N_INSNS (5);                                       \
3472       else                                                              \
3473         return COSTS_N_INSNS (10);                                      \
3474     }                                                                   \
3475                                                                         \
3476   case DIV:                                                             \
3477   case MOD:                                                             \
3478     {                                                                   \
3479       enum machine_mode xmode = GET_MODE (X);                           \
3480       if (xmode == SFmode)                                              \
3481         {                                                               \
3482           if (TUNE_MIPS3000                                             \
3483               || TUNE_MIPS3900)                                         \
3484             return COSTS_N_INSNS (12);                                  \
3485           else if (TUNE_MIPS6000)                                       \
3486             return COSTS_N_INSNS (15);                                  \
3487           else                                                          \
3488             return COSTS_N_INSNS (23);                                  \
3489         }                                                               \
3490                                                                         \
3491       if (xmode == DFmode)                                              \
3492         {                                                               \
3493           if (TUNE_MIPS3000                                             \
3494               || TUNE_MIPS3900)                                         \
3495             return COSTS_N_INSNS (19);                                  \
3496           else if (TUNE_MIPS6000)                                       \
3497             return COSTS_N_INSNS (16);                                  \
3498           else                                                          \
3499             return COSTS_N_INSNS (36);                                  \
3500         }                                                               \
3501     }                                                                   \
3502     /* fall through */                                                  \
3503                                                                         \
3504   case UDIV:                                                            \
3505   case UMOD:                                                            \
3506     if (TUNE_MIPS3000                                                   \
3507         || TUNE_MIPS3900)                                               \
3508       return COSTS_N_INSNS (35);                                        \
3509     else if (TUNE_MIPS6000)                                             \
3510       return COSTS_N_INSNS (38);                                        \
3511     else if (TUNE_MIPS5000)                                             \
3512       return COSTS_N_INSNS (36);                                        \
3513     else                                                                \
3514       return COSTS_N_INSNS (69);                                        \
3515                                                                         \
3516   case SIGN_EXTEND:                                                     \
3517     /* A sign extend from SImode to DImode in 64 bit mode is often      \
3518        zero instructions, because the result can often be used          \
3519        directly by another instruction; we'll call it one.  */          \
3520     if (TARGET_64BIT && GET_MODE (X) == DImode                          \
3521         && GET_MODE (XEXP (X, 0)) == SImode)                            \
3522       return COSTS_N_INSNS (1);                                         \
3523     else                                                                \
3524       return COSTS_N_INSNS (2);                                         \
3525                                                                         \
3526   case ZERO_EXTEND:                                                     \
3527     if (TARGET_64BIT && GET_MODE (X) == DImode                          \
3528         && GET_MODE (XEXP (X, 0)) == SImode)                            \
3529       return COSTS_N_INSNS (2);                                         \
3530     else                                                                \
3531       return COSTS_N_INSNS (1);
3532
3533 /* An expression giving the cost of an addressing mode that
3534    contains ADDRESS.  If not defined, the cost is computed from the
3535    form of the ADDRESS expression and the `CONST_COSTS' values.
3536
3537    For most CISC machines, the default cost is a good approximation
3538    of the true cost of the addressing mode.  However, on RISC
3539    machines, all instructions normally have the same length and
3540    execution time.  Hence all addresses will have equal costs.
3541
3542    In cases where more than one form of an address is known, the
3543    form with the lowest cost will be used.  If multiple forms have
3544    the same, lowest, cost, the one that is the most complex will be
3545    used.
3546
3547    For example, suppose an address that is equal to the sum of a
3548    register and a constant is used twice in the same basic block.
3549    When this macro is not defined, the address will be computed in
3550    a register and memory references will be indirect through that
3551    register.  On machines where the cost of the addressing mode
3552    containing the sum is no higher than that of a simple indirect
3553    reference, this will produce an additional instruction and
3554    possibly require an additional register.  Proper specification
3555    of this macro eliminates this overhead for such machines.
3556
3557    Similar use of this macro is made in strength reduction of loops.
3558
3559    ADDRESS need not be valid as an address.  In such a case, the
3560    cost is not relevant and can be any value; invalid addresses
3561    need not be assigned a different cost.
3562
3563    On machines where an address involving more than one register is
3564    as cheap as an address computation involving only one register,
3565    defining `ADDRESS_COST' to reflect this can cause two registers
3566    to be live over a region of code where only one would have been
3567    if `ADDRESS_COST' were not defined in that manner.  This effect
3568    should be considered in the definition of this macro.
3569    Equivalent costs should probably only be given to addresses with
3570    different numbers of registers on machines with lots of registers.
3571
3572    This macro will normally either not be defined or be defined as
3573    a constant.  */
3574
3575 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3576
3577 /* A C expression for the cost of moving data from a register in
3578    class FROM to one in class TO.  The classes are expressed using
3579    the enumeration values such as `GENERAL_REGS'.  A value of 2 is
3580    the default; other values are interpreted relative to that.
3581
3582    It is not required that the cost always equal 2 when FROM is the
3583    same as TO; on some machines it is expensive to move between
3584    registers if they are not general registers.
3585
3586    If reload sees an insn consisting of a single `set' between two
3587    hard registers, and if `REGISTER_MOVE_COST' applied to their
3588    classes returns a value of 2, reload does not check to ensure
3589    that the constraints of the insn are met.  Setting a cost of
3590    other than 2 will allow reload to verify that the constraints are
3591    met.  You should do this if the `movM' pattern's constraints do
3592    not allow such copying. */
3593
3594 #define REGISTER_MOVE_COST(MODE, FROM, TO)                              \
3595   mips_register_move_cost (MODE, FROM, TO)
3596
3597 /* ??? Fix this to be right for the R8000.  */
3598 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3599   (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3600    + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3601
3602 /* Define if copies to/from condition code registers should be avoided.
3603
3604    This is needed for the MIPS because reload_outcc is not complete;
3605    it needs to handle cases where the source is a general or another
3606    condition code register.  */
3607 #define AVOID_CCMODE_COPIES
3608
3609 /* A C expression for the cost of a branch instruction.  A value of
3610    1 is the default; other values are interpreted relative to that.  */
3611
3612 /* ??? Fix this to be right for the R8000.  */
3613 #define BRANCH_COST                                                     \
3614   ((! TARGET_MIPS16                                                     \
3615     && (TUNE_MIPS4000 || TUNE_MIPS6000))        \
3616    ? 2 : 1)
3617
3618 /* If defined, modifies the length assigned to instruction INSN as a
3619    function of the context in which it is used.  LENGTH is an lvalue
3620    that contains the initially computed length of the insn and should
3621    be updated with the correct length of the insn.  */
3622 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3623   ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3624
3625 \f
3626 /* Optionally define this if you have added predicates to
3627    `MACHINE.c'.  This macro is called within an initializer of an
3628    array of structures.  The first field in the structure is the
3629    name of a predicate and the second field is an array of rtl
3630    codes.  For each predicate, list all rtl codes that can be in
3631    expressions matched by the predicate.  The list should have a
3632    trailing comma.  Here is an example of two entries in the list
3633    for a typical RISC machine:
3634
3635    #define PREDICATE_CODES \
3636      {"gen_reg_rtx_operand", {SUBREG, REG}},  \
3637      {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3638
3639    Defining this macro does not affect the generated code (however,
3640    incorrect definitions that omit an rtl code that may be matched
3641    by the predicate can cause the compiler to malfunction).
3642    Instead, it allows the table built by `genrecog' to be more
3643    compact and efficient, thus speeding up the compiler.  The most
3644    important predicates to include in the list specified by this
3645    macro are thoses used in the most insn patterns.  */
3646
3647 #define PREDICATE_CODES                                                 \
3648   {"uns_arith_operand",         { REG, CONST_INT, SUBREG }},            \
3649   {"arith_operand",             { REG, CONST_INT, SUBREG }},            \
3650   {"arith32_operand",           { REG, CONST_INT, SUBREG }},            \
3651   {"reg_or_0_operand",          { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3652   {"true_reg_or_0_operand",     { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3653   {"small_int",                 { CONST_INT }},                         \
3654   {"large_int",                 { CONST_INT }},                         \
3655   {"mips_const_double_ok",      { CONST_DOUBLE }},                      \
3656   {"const_float_1_operand",     { CONST_DOUBLE }},                      \
3657   {"simple_memory_operand",     { MEM, SUBREG }},                       \
3658   {"equality_op",               { EQ, NE }},                            \
3659   {"cmp_op",                    { EQ, NE, GT, GE, GTU, GEU, LT, LE,     \
3660                                   LTU, LEU }},                          \
3661   {"trap_cmp_op",               { EQ, NE, GE, GEU, LT, LTU }},          \
3662   {"pc_or_label_operand",       { PC, LABEL_REF }},                     \
3663   {"call_insn_operand",         { CONST_INT, CONST, SYMBOL_REF, REG}},  \
3664   {"move_operand",              { CONST_INT, CONST_DOUBLE, CONST,       \
3665                                   SYMBOL_REF, LABEL_REF, SUBREG,        \
3666                                   REG, MEM}},                           \
3667   {"movdi_operand",             { CONST_INT, CONST_DOUBLE, CONST,       \
3668                                   SYMBOL_REF, LABEL_REF, SUBREG, REG,   \
3669                                   MEM, SIGN_EXTEND }},                  \
3670   {"se_register_operand",       { SUBREG, REG, SIGN_EXTEND }},          \
3671   {"se_reg_or_0_operand",       { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3672                                   SIGN_EXTEND }},                       \
3673   {"se_uns_arith_operand",      { REG, CONST_INT, SUBREG,               \
3674                                   SIGN_EXTEND }},                       \
3675   {"se_arith_operand",          { REG, CONST_INT, SUBREG,               \
3676                                   SIGN_EXTEND }},                       \
3677   {"se_nonmemory_operand",      { CONST_INT, CONST_DOUBLE, CONST,       \
3678                                   SYMBOL_REF, LABEL_REF, SUBREG,        \
3679                                   REG, SIGN_EXTEND }},                  \
3680   {"se_nonimmediate_operand",   { SUBREG, REG, MEM, SIGN_EXTEND }},     \
3681   {"consttable_operand",        { LABEL_REF, SYMBOL_REF, CONST_INT,     \
3682                                   CONST_DOUBLE, CONST }},               \
3683   {"extend_operator",           { SIGN_EXTEND, ZERO_EXTEND }},          \
3684   {"highpart_shift_operator",   { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3685
3686 /* A list of predicates that do special things with modes, and so
3687    should not elicit warnings for VOIDmode match_operand.  */
3688
3689 #define SPECIAL_MODE_PREDICATES \
3690   "pc_or_label_operand",
3691
3692 \f
3693 /* If defined, a C statement to be executed just prior to the
3694    output of assembler code for INSN, to modify the extracted
3695    operands so they will be output differently.
3696
3697    Here the argument OPVEC is the vector containing the operands
3698    extracted from INSN, and NOPERANDS is the number of elements of
3699    the vector which contain meaningful data for this insn.  The
3700    contents of this vector are what will be used to convert the
3701    insn template into assembler code, so you can change the
3702    assembler output by changing the contents of the vector.
3703
3704    We use it to check if the current insn needs a nop in front of it
3705    because of load delays, and also to update the delay slot
3706    statistics.  */
3707
3708 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)                      \
3709   final_prescan_insn (INSN, OPVEC, NOPERANDS)
3710
3711 \f
3712 /* Control the assembler format that we output.  */
3713
3714 /* Output at beginning of assembler file.
3715    If we are optimizing to use the global pointer, create a temporary
3716    file to hold all of the text stuff, and write it out to the end.
3717    This is needed because the MIPS assembler is evidently one pass,
3718    and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3719    declaration when the code is processed, it generates a two
3720    instruction sequence.  */
3721
3722 #undef ASM_FILE_START
3723 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3724
3725 /* Output to assembler file text saying following lines
3726    may contain character constants, extra white space, comments, etc.  */
3727
3728 #ifndef ASM_APP_ON
3729 #define ASM_APP_ON " #APP\n"
3730 #endif
3731
3732 /* Output to assembler file text saying following lines
3733    no longer contain unusual constructs.  */
3734
3735 #ifndef ASM_APP_OFF
3736 #define ASM_APP_OFF " #NO_APP\n"
3737 #endif
3738
3739 /* How to refer to registers in assembler output.
3740    This sequence is indexed by compiler's hard-register-number (see above).
3741
3742    In order to support the two different conventions for register names,
3743    we use the name of a table set up in mips.c, which is overwritten
3744    if -mrnames is used.  */
3745
3746 #define REGISTER_NAMES                                                  \
3747 {                                                                       \
3748   &mips_reg_names[ 0][0],                                               \
3749   &mips_reg_names[ 1][0],                                               \
3750   &mips_reg_names[ 2][0],                                               \
3751   &mips_reg_names[ 3][0],                                               \
3752   &mips_reg_names[ 4][0],                                               \
3753   &mips_reg_names[ 5][0],                                               \
3754   &mips_reg_names[ 6][0],                                               \
3755   &mips_reg_names[ 7][0],                                               \
3756   &mips_reg_names[ 8][0],                                               \
3757   &mips_reg_names[ 9][0],                                               \
3758   &mips_reg_names[10][0],                                               \
3759   &mips_reg_names[11][0],                                               \
3760   &mips_reg_names[12][0],                                               \
3761   &mips_reg_names[13][0],                                               \
3762   &mips_reg_names[14][0],                                               \
3763   &mips_reg_names[15][0],                                               \
3764   &mips_reg_names[16][0],                                               \
3765   &mips_reg_names[17][0],                                               \
3766   &mips_reg_names[18][0],                                               \
3767   &mips_reg_names[19][0],                                               \
3768   &mips_reg_names[20][0],                                               \
3769   &mips_reg_names[21][0],                                               \
3770   &mips_reg_names[22][0],                                               \
3771   &mips_reg_names[23][0],                                               \
3772   &mips_reg_names[24][0],                                               \
3773   &mips_reg_names[25][0],                                               \
3774   &mips_reg_names[26][0],                                               \
3775   &mips_reg_names[27][0],                                               \
3776   &mips_reg_names[28][0],                                               \
3777   &mips_reg_names[29][0],                                               \
3778   &mips_reg_names[30][0],                                               \
3779   &mips_reg_names[31][0],                                               \
3780   &mips_reg_names[32][0],                                               \
3781   &mips_reg_names[33][0],                                               \
3782   &mips_reg_names[34][0],                                               \
3783   &mips_reg_names[35][0],                                               \
3784   &mips_reg_names[36][0],                                               \
3785   &mips_reg_names[37][0],                                               \
3786   &mips_reg_names[38][0],                                               \
3787   &mips_reg_names[39][0],                                               \
3788   &mips_reg_names[40][0],                                               \
3789   &mips_reg_names[41][0],                                               \
3790   &mips_reg_names[42][0],                                               \
3791   &mips_reg_names[43][0],                                               \
3792   &mips_reg_names[44][0],                                               \
3793   &mips_reg_names[45][0],                                               \
3794   &mips_reg_names[46][0],                                               \
3795   &mips_reg_names[47][0],                                               \
3796   &mips_reg_names[48][0],                                               \
3797   &mips_reg_names[49][0],                                               \
3798   &mips_reg_names[50][0],                                               \
3799   &mips_reg_names[51][0],                                               \
3800   &mips_reg_names[52][0],                                               \
3801   &mips_reg_names[53][0],                                               \
3802   &mips_reg_names[54][0],                                               \
3803   &mips_reg_names[55][0],                                               \
3804   &mips_reg_names[56][0],                                               \
3805   &mips_reg_names[57][0],                                               \
3806   &mips_reg_names[58][0],                                               \
3807   &mips_reg_names[59][0],                                               \
3808   &mips_reg_names[60][0],                                               \
3809   &mips_reg_names[61][0],                                               \
3810   &mips_reg_names[62][0],                                               \
3811   &mips_reg_names[63][0],                                               \
3812   &mips_reg_names[64][0],                                               \
3813   &mips_reg_names[65][0],                                               \
3814   &mips_reg_names[66][0],                                               \
3815   &mips_reg_names[67][0],                                               \
3816   &mips_reg_names[68][0],                                               \
3817   &mips_reg_names[69][0],                                               \
3818   &mips_reg_names[70][0],                                               \
3819   &mips_reg_names[71][0],                                               \
3820   &mips_reg_names[72][0],                                               \
3821   &mips_reg_names[73][0],                                               \
3822   &mips_reg_names[74][0],                                               \
3823   &mips_reg_names[75][0],                                               \
3824   &mips_reg_names[76][0],                                               \
3825   &mips_reg_names[77][0],                                               \
3826   &mips_reg_names[78][0],                                               \
3827   &mips_reg_names[79][0],                                               \
3828   &mips_reg_names[80][0],                                               \
3829   &mips_reg_names[81][0],                                               \
3830   &mips_reg_names[82][0],                                               \
3831   &mips_reg_names[83][0],                                               \
3832   &mips_reg_names[84][0],                                               \
3833   &mips_reg_names[85][0],                                               \
3834   &mips_reg_names[86][0],                                               \
3835   &mips_reg_names[87][0],                                               \
3836   &mips_reg_names[88][0],                                               \
3837   &mips_reg_names[89][0],                                               \
3838   &mips_reg_names[90][0],                                               \
3839   &mips_reg_names[91][0],                                               \
3840   &mips_reg_names[92][0],                                               \
3841   &mips_reg_names[93][0],                                               \
3842   &mips_reg_names[94][0],                                               \
3843   &mips_reg_names[95][0],                                               \
3844   &mips_reg_names[96][0],                                               \
3845   &mips_reg_names[97][0],                                               \
3846   &mips_reg_names[98][0],                                               \
3847   &mips_reg_names[99][0],                                               \
3848   &mips_reg_names[100][0],                                              \
3849   &mips_reg_names[101][0],                                              \
3850   &mips_reg_names[102][0],                                              \
3851   &mips_reg_names[103][0],                                              \
3852   &mips_reg_names[104][0],                                              \
3853   &mips_reg_names[105][0],                                              \
3854   &mips_reg_names[106][0],                                              \
3855   &mips_reg_names[107][0],                                              \
3856   &mips_reg_names[108][0],                                              \
3857   &mips_reg_names[109][0],                                              \
3858   &mips_reg_names[110][0],                                              \
3859   &mips_reg_names[111][0],                                              \
3860   &mips_reg_names[112][0],                                              \
3861   &mips_reg_names[113][0],                                              \
3862   &mips_reg_names[114][0],                                              \
3863   &mips_reg_names[115][0],                                              \
3864   &mips_reg_names[116][0],                                              \
3865   &mips_reg_names[117][0],                                              \
3866   &mips_reg_names[118][0],                                              \
3867   &mips_reg_names[119][0],                                              \
3868   &mips_reg_names[120][0],                                              \
3869   &mips_reg_names[121][0],                                              \
3870   &mips_reg_names[122][0],                                              \
3871   &mips_reg_names[123][0],                                              \
3872   &mips_reg_names[124][0],                                              \
3873   &mips_reg_names[125][0],                                              \
3874   &mips_reg_names[126][0],                                              \
3875   &mips_reg_names[127][0],                                              \
3876   &mips_reg_names[128][0],                                              \
3877   &mips_reg_names[129][0],                                              \
3878   &mips_reg_names[130][0],                                              \
3879   &mips_reg_names[131][0],                                              \
3880   &mips_reg_names[132][0],                                              \
3881   &mips_reg_names[133][0],                                              \
3882   &mips_reg_names[134][0],                                              \
3883   &mips_reg_names[135][0],                                              \
3884   &mips_reg_names[136][0],                                              \
3885   &mips_reg_names[137][0],                                              \
3886   &mips_reg_names[138][0],                                              \
3887   &mips_reg_names[139][0],                                              \
3888   &mips_reg_names[140][0],                                              \
3889   &mips_reg_names[141][0],                                              \
3890   &mips_reg_names[142][0],                                              \
3891   &mips_reg_names[143][0],                                              \
3892   &mips_reg_names[144][0],                                              \
3893   &mips_reg_names[145][0],                                              \
3894   &mips_reg_names[146][0],                                              \
3895   &mips_reg_names[147][0],                                              \
3896   &mips_reg_names[148][0],                                              \
3897   &mips_reg_names[149][0],                                              \
3898   &mips_reg_names[150][0],                                              \
3899   &mips_reg_names[151][0],                                              \
3900   &mips_reg_names[152][0],                                              \
3901   &mips_reg_names[153][0],                                              \
3902   &mips_reg_names[154][0],                                              \
3903   &mips_reg_names[155][0],                                              \
3904   &mips_reg_names[156][0],                                              \
3905   &mips_reg_names[157][0],                                              \
3906   &mips_reg_names[158][0],                                              \
3907   &mips_reg_names[159][0],                                              \
3908   &mips_reg_names[160][0],                                              \
3909   &mips_reg_names[161][0],                                              \
3910   &mips_reg_names[162][0],                                              \
3911   &mips_reg_names[163][0],                                              \
3912   &mips_reg_names[164][0],                                              \
3913   &mips_reg_names[165][0],                                              \
3914   &mips_reg_names[166][0],                                              \
3915   &mips_reg_names[167][0],                                              \
3916   &mips_reg_names[168][0],                                              \
3917   &mips_reg_names[169][0],                                              \
3918   &mips_reg_names[170][0],                                              \
3919   &mips_reg_names[171][0],                                              \
3920   &mips_reg_names[172][0],                                              \
3921   &mips_reg_names[173][0],                                              \
3922   &mips_reg_names[174][0],                                              \
3923   &mips_reg_names[175][0]                                               \
3924 }
3925
3926 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3927    So define this for it.  */
3928 #define DEBUG_REGISTER_NAMES                                            \
3929 {                                                                       \
3930   "$0",   "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",         \
3931   "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",         \
3932   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",         \
3933   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "$fp",  "ra",         \
3934   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",        \
3935   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",       \
3936   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",       \
3937   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",       \
3938   "hi",   "lo",   "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",      \
3939   "$fcc5","$fcc6","$fcc7","$rap", "",     "",     "",     "",           \
3940   "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
3941   "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
3942   "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
3943   "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
3944   "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
3945   "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
3946   "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
3947   "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
3948   "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
3949   "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
3950   "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
3951   "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
3952 }
3953
3954 /* If defined, a C initializer for an array of structures
3955    containing a name and a register number.  This macro defines
3956    additional names for hard registers, thus allowing the `asm'
3957    option in declarations to refer to registers using alternate
3958    names.
3959
3960    We define both names for the integer registers here.  */
3961
3962 #define ADDITIONAL_REGISTER_NAMES                                       \
3963 {                                                                       \
3964   { "$0",        0 + GP_REG_FIRST },                                    \
3965   { "$1",        1 + GP_REG_FIRST },                                    \
3966   { "$2",        2 + GP_REG_FIRST },                                    \
3967   { "$3",        3 + GP_REG_FIRST },                                    \
3968   { "$4",        4 + GP_REG_FIRST },                                    \
3969   { "$5",        5 + GP_REG_FIRST },                                    \
3970   { "$6",        6 + GP_REG_FIRST },                                    \
3971   { "$7",        7 + GP_REG_FIRST },                                    \
3972   { "$8",        8 + GP_REG_FIRST },                                    \
3973   { "$9",        9 + GP_REG_FIRST },                                    \
3974   { "$10",      10 + GP_REG_FIRST },                                    \
3975   { "$11",      11 + GP_REG_FIRST },                                    \
3976   { "$12",      12 + GP_REG_FIRST },                                    \
3977   { "$13",      13 + GP_REG_FIRST },                                    \
3978   { "$14",      14 + GP_REG_FIRST },                                    \
3979   { "$15",      15 + GP_REG_FIRST },                                    \
3980   { "$16",      16 + GP_REG_FIRST },                                    \
3981   { "$17",      17 + GP_REG_FIRST },                                    \
3982   { "$18",      18 + GP_REG_FIRST },                                    \
3983   { "$19",      19 + GP_REG_FIRST },                                    \
3984   { "$20",      20 + GP_REG_FIRST },                                    \
3985   { "$21",      21 + GP_REG_FIRST },                                    \
3986   { "$22",      22 + GP_REG_FIRST },                                    \
3987   { "$23",      23 + GP_REG_FIRST },                                    \
3988   { "$24",      24 + GP_REG_FIRST },                                    \
3989   { "$25",      25 + GP_REG_FIRST },                                    \
3990   { "$26",      26 + GP_REG_FIRST },                                    \
3991   { "$27",      27 + GP_REG_FIRST },                                    \
3992   { "$28",      28 + GP_REG_FIRST },                                    \
3993   { "$29",      29 + GP_REG_FIRST },                                    \
3994   { "$30",      30 + GP_REG_FIRST },                                    \
3995   { "$31",      31 + GP_REG_FIRST },                                    \
3996   { "$sp",      29 + GP_REG_FIRST },                                    \
3997   { "$fp",      30 + GP_REG_FIRST },                                    \
3998   { "at",        1 + GP_REG_FIRST },                                    \
3999   { "v0",        2 + GP_REG_FIRST },                                    \
4000   { "v1",        3 + GP_REG_FIRST },                                    \
4001   { "a0",        4 + GP_REG_FIRST },                                    \
4002   { "a1",        5 + GP_REG_FIRST },                                    \
4003   { "a2",        6 + GP_REG_FIRST },                                    \
4004   { "a3",        7 + GP_REG_FIRST },                                    \
4005   { "t0",        8 + GP_REG_FIRST },                                    \
4006   { "t1",        9 + GP_REG_FIRST },                                    \
4007   { "t2",       10 + GP_REG_FIRST },                                    \
4008   { "t3",       11 + GP_REG_FIRST },                                    \
4009   { "t4",       12 + GP_REG_FIRST },                                    \
4010   { "t5",       13 + GP_REG_FIRST },                                    \
4011   { "t6",       14 + GP_REG_FIRST },                                    \
4012   { "t7",       15 + GP_REG_FIRST },                                    \
4013   { "s0",       16 + GP_REG_FIRST },                                    \
4014   { "s1",       17 + GP_REG_FIRST },                                    \
4015   { "s2",       18 + GP_REG_FIRST },                                    \
4016   { "s3",       19 + GP_REG_FIRST },                                    \
4017   { "s4",       20 + GP_REG_FIRST },                                    \
4018   { "s5",       21 + GP_REG_FIRST },                                    \
4019   { "s6",       22 + GP_REG_FIRST },                                    \
4020   { "s7",       23 + GP_REG_FIRST },                                    \
4021   { "t8",       24 + GP_REG_FIRST },                                    \
4022   { "t9",       25 + GP_REG_FIRST },                                    \
4023   { "k0",       26 + GP_REG_FIRST },                                    \
4024   { "k1",       27 + GP_REG_FIRST },                                    \
4025   { "gp",       28 + GP_REG_FIRST },                                    \
4026   { "sp",       29 + GP_REG_FIRST },                                    \
4027   { "fp",       30 + GP_REG_FIRST },                                    \
4028   { "ra",       31 + GP_REG_FIRST },                                    \
4029   { "$sp",      29 + GP_REG_FIRST },                                    \
4030   { "$fp",      30 + GP_REG_FIRST }                                     \
4031   ALL_COP_ADDITIONAL_REGISTER_NAMES                                     \
4032 }
4033
4034 /* This is meant to be redefined in the host dependent files.  It is a
4035    set of alternative names and regnums for mips coprocessors.  */
4036
4037 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
4038
4039 /* A C compound statement to output to stdio stream STREAM the
4040    assembler syntax for an instruction operand X.  X is an RTL
4041    expression.
4042
4043    CODE is a value that can be used to specify one of several ways
4044    of printing the operand.  It is used when identical operands
4045    must be printed differently depending on the context.  CODE
4046    comes from the `%' specification that was used to request
4047    printing of the operand.  If the specification was just `%DIGIT'
4048    then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4049    is the ASCII code for LTR.
4050
4051    If X is a register, this macro should print the register's name.
4052    The names can be found in an array `reg_names' whose type is
4053    `char *[]'.  `reg_names' is initialized from `REGISTER_NAMES'.
4054
4055    When the machine description has a specification `%PUNCT' (a `%'
4056    followed by a punctuation character), this macro is called with
4057    a null pointer for X and the punctuation character for CODE.
4058
4059    See mips.c for the MIPS specific codes.  */
4060
4061 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4062
4063 /* A C expression which evaluates to true if CODE is a valid
4064    punctuation character for use in the `PRINT_OPERAND' macro.  If
4065    `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4066    punctuation characters (except for the standard one, `%') are
4067    used in this way.  */
4068
4069 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4070
4071 /* A C compound statement to output to stdio stream STREAM the
4072    assembler syntax for an instruction operand that is a memory
4073    reference whose address is ADDR.  ADDR is an RTL expression.  */
4074
4075 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4076
4077
4078 /* A C statement, to be executed after all slot-filler instructions
4079    have been output.  If necessary, call `dbr_sequence_length' to
4080    determine the number of slots filled in a sequence (zero if not
4081    currently outputting a sequence), to decide how many no-ops to
4082    output, or whatever.
4083
4084    Don't define this macro if it has nothing to do, but it is
4085    helpful in reading assembly output if the extent of the delay
4086    sequence is made explicit (e.g. with white space).
4087
4088    Note that output routines for instructions with delay slots must
4089    be prepared to deal with not being output as part of a sequence
4090    (i.e.  when the scheduling pass is not run, or when no slot
4091    fillers could be found.)  The variable `final_sequence' is null
4092    when not processing a sequence, otherwise it contains the
4093    `sequence' rtx being output.  */
4094
4095 #define DBR_OUTPUT_SEQEND(STREAM)                                       \
4096 do                                                                      \
4097   {                                                                     \
4098     if (set_nomacro > 0 && --set_nomacro == 0)                          \
4099       fputs ("\t.set\tmacro\n", STREAM);                                \
4100                                                                         \
4101     if (set_noreorder > 0 && --set_noreorder == 0)                      \
4102       fputs ("\t.set\treorder\n", STREAM);                              \
4103                                                                         \
4104     dslots_jump_filled++;                                               \
4105     fputs ("\n", STREAM);                                               \
4106   }                                                                     \
4107 while (0)
4108
4109
4110 /* How to tell the debugger about changes of source files.  Note, the
4111    mips ECOFF format cannot deal with changes of files inside of
4112    functions, which means the output of parser generators like bison
4113    is generally not debuggable without using the -l switch.  Lose,
4114    lose, lose.  Silicon graphics seems to want all .file's hardwired
4115    to 1.  */
4116
4117 #ifndef SET_FILE_NUMBER
4118 #define SET_FILE_NUMBER() ++num_source_filenames
4119 #endif
4120
4121 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME)                        \
4122   mips_output_filename (STREAM, NAME)
4123
4124 /* This is defined so that it can be overridden in iris6.h.  */
4125 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4126 do                                                              \
4127   {                                                             \
4128     fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES);     \
4129     output_quoted_string (STREAM, NAME);                        \
4130     fputs ("\n", STREAM);                                       \
4131   }                                                             \
4132 while (0)
4133
4134 /* This is how to output a note the debugger telling it the line number
4135    to which the following sequence of instructions corresponds.
4136    Silicon graphics puts a label after each .loc.  */
4137
4138 #ifndef LABEL_AFTER_LOC
4139 #define LABEL_AFTER_LOC(STREAM)
4140 #endif
4141
4142 #ifndef ASM_OUTPUT_SOURCE_LINE
4143 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE)                            \
4144   mips_output_lineno (STREAM, LINE)
4145 #endif
4146
4147 /* The MIPS implementation uses some labels for its own purpose.  The
4148    following lists what labels are created, and are all formed by the
4149    pattern $L[a-z].*.  The machine independent portion of GCC creates
4150    labels matching:  $L[A-Z][0-9]+ and $L[0-9]+.
4151
4152         LM[0-9]+        Silicon Graphics/ECOFF stabs label before each stmt.
4153         $Lb[0-9]+       Begin blocks for MIPS debug support
4154         $Lc[0-9]+       Label for use in s<xx> operation.
4155         $Le[0-9]+       End blocks for MIPS debug support  */
4156
4157 /* This is how to output the definition of a user-level label named NAME,
4158    such as the label on a static function or variable NAME.
4159
4160    If we are optimizing the gp, remember that this label has been put
4161    out, so we know not to emit an .extern for it in mips_asm_file_end.
4162    We use one of the common bits in the IDENTIFIER tree node for this,
4163    since those bits seem to be unused, and we don't have any method
4164    of getting the decl nodes from the name.  */
4165
4166 #define ASM_OUTPUT_LABEL(STREAM,NAME)                                   \
4167 do {                                                                    \
4168   assemble_name (STREAM, NAME);                                         \
4169   fputs (":\n", STREAM);                                                \
4170 } while (0)
4171
4172
4173 /* A C statement (sans semicolon) to output to the stdio stream
4174    STREAM any text necessary for declaring the name NAME of an
4175    initialized variable which is being defined.  This macro must
4176    output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4177    The argument DECL is the `VAR_DECL' tree node representing the
4178    variable.
4179
4180    If this macro is not defined, then the variable name is defined
4181    in the usual manner as a label (by means of `ASM_OUTPUT_LABEL').  */
4182
4183 #undef ASM_DECLARE_OBJECT_NAME
4184 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL)                     \
4185 do                                                                      \
4186  {                                                                      \
4187    mips_declare_object (STREAM, NAME, "", ":\n", 0);                    \
4188  }                                                                      \
4189 while (0)
4190
4191
4192 /* This is how to output a command to make the user-level label named NAME
4193    defined for reference from other files.  */
4194
4195 #define ASM_GLOBALIZE_LABEL(STREAM,NAME)                                \
4196   do {                                                                  \
4197     fputs ("\t.globl\t", STREAM);                                       \
4198     assemble_name (STREAM, NAME);                                       \
4199     fputs ("\n", STREAM);                                               \
4200   } while (0)
4201
4202 /* This says how to define a global common symbol.  */
4203
4204 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4205   do {                                                                  \
4206     /* If the target wants uninitialized const declarations in          \
4207        .rdata then don't put them in .comm */                           \
4208     if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA           \
4209         && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL)         \
4210         && (DECL_INITIAL (DECL) == 0                                    \
4211             || DECL_INITIAL (DECL) == error_mark_node))                 \
4212       {                                                                 \
4213         if (TREE_PUBLIC (DECL) && DECL_NAME (DECL))                     \
4214           ASM_GLOBALIZE_LABEL (STREAM, NAME);                           \
4215                                                                         \
4216         readonly_data_section ();                                       \
4217         ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT));  \
4218         mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n",     \
4219             (SIZE));                                                    \
4220       }                                                                 \
4221     else                                                                \
4222         mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n",      \
4223           (SIZE));                                                      \
4224   } while (0)
4225
4226
4227 /* This says how to define a local common symbol (ie, not visible to
4228    linker).  */
4229
4230 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED)                   \
4231   mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4232
4233
4234 /* This says how to output an external.  It would be possible not to
4235    output anything and let undefined symbol become external. However
4236    the assembler uses length information on externals to allocate in
4237    data/sdata bss/sbss, thereby saving exec time.  */
4238
4239 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4240   mips_output_external(STREAM,DECL,NAME)
4241
4242 /* This says what to print at the end of the assembly file */
4243 #undef ASM_FILE_END
4244 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4245
4246
4247 /* Play switch file games if we're optimizing the global pointer.  */
4248
4249 #undef TEXT_SECTION
4250 #define TEXT_SECTION()                                  \
4251 do {                                                    \
4252   extern FILE *asm_out_text_file;                       \
4253   if (TARGET_FILE_SWITCHING)                            \
4254     asm_out_file = asm_out_text_file;                   \
4255   fputs (TEXT_SECTION_ASM_OP, asm_out_file);            \
4256   fputc ('\n', asm_out_file);                           \
4257 } while (0)
4258
4259
4260 /* This is how to declare a function name.  The actual work of
4261    emitting the label is moved to function_prologue, so that we can
4262    get the line number correctly emitted before the .ent directive,
4263    and after any .file directives.  Define as empty so that the function
4264    is not declared before the .ent directive elsewhere.  */
4265
4266 #undef ASM_DECLARE_FUNCTION_NAME
4267 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
4268
4269
4270 /* This is how to output an internal numbered label where
4271    PREFIX is the class of label and NUM is the number within the class.  */
4272
4273 #undef ASM_OUTPUT_INTERNAL_LABEL
4274 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM)                    \
4275   fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4276
4277 /* This is how to store into the string LABEL
4278    the symbol_ref name of an internal numbered label where
4279    PREFIX is the class of label and NUM is the number within the class.
4280    This is suitable for output with `assemble_name'.  */
4281
4282 #undef ASM_GENERATE_INTERNAL_LABEL
4283 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
4284   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4285
4286 /* This is how to output an element of a case-vector that is absolute.  */
4287
4288 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
4289   fprintf (STREAM, "\t%s\t%sL%d\n",                                     \
4290            Pmode == DImode ? ".dword" : ".word",                        \
4291            LOCAL_LABEL_PREFIX,                                          \
4292            VALUE)
4293
4294 /* This is how to output an element of a case-vector that is relative.
4295    This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4296    TARGET_EMBEDDED_PIC).  */
4297
4298 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
4299 do {                                                                    \
4300   if (TARGET_MIPS16)                                                    \
4301     fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n",                          \
4302              LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL);       \
4303   else if (TARGET_EMBEDDED_PIC)                                         \
4304     fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n",                            \
4305              Pmode == DImode ? ".dword" : ".word",                      \
4306              LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL);       \
4307   else if (mips_abi == ABI_32 || mips_abi == ABI_O64)                   \
4308     fprintf (STREAM, "\t%s\t%sL%d\n",                                   \
4309              Pmode == DImode ? ".gpdword" : ".gpword",                  \
4310              LOCAL_LABEL_PREFIX, VALUE);                                \
4311   else                                                                  \
4312     fprintf (STREAM, "\t%s\t%sL%d\n",                                   \
4313              Pmode == DImode ? ".dword" : ".word",                      \
4314              LOCAL_LABEL_PREFIX, VALUE);                                \
4315 } while (0)
4316
4317 /* When generating embedded PIC or mips16 code we want to put the jump
4318    table in the .text section.  In all other cases, we want to put the
4319    jump table in the .rdata section.  Unfortunately, we can't use
4320    JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4321    Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4322    section if appropriate.  */
4323 #undef ASM_OUTPUT_CASE_LABEL
4324 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN)                  \
4325 do {                                                                    \
4326   if (TARGET_EMBEDDED_PIC || TARGET_MIPS16)                             \
4327     function_section (current_function_decl);                           \
4328   ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM);                        \
4329 } while (0)
4330
4331 /* This is how to output an assembler line
4332    that says to advance the location counter
4333    to a multiple of 2**LOG bytes.  */
4334
4335 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
4336   fprintf (STREAM, "\t.align\t%d\n", (LOG))
4337
4338 /* This is how to output an assembler line to advance the location
4339    counter by SIZE bytes.  */
4340
4341 #undef ASM_OUTPUT_SKIP
4342 #define ASM_OUTPUT_SKIP(STREAM,SIZE)                                    \
4343   fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4344
4345 /* This is how to output a string.  */
4346 #undef ASM_OUTPUT_ASCII
4347 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN)                           \
4348   mips_output_ascii (STREAM, STRING, LEN)
4349
4350 /* Handle certain cpp directives used in header files on sysV.  */
4351 #define SCCS_DIRECTIVE
4352
4353 /* Output #ident as a in the read-only data section.  */
4354 #undef  ASM_OUTPUT_IDENT
4355 #define ASM_OUTPUT_IDENT(FILE, STRING)                                  \
4356 {                                                                       \
4357   const char *p = STRING;                                               \
4358   int size = strlen (p) + 1;                                            \
4359   readonly_data_section ();                                             \
4360   assemble_string (p, size);                                            \
4361 }
4362 \f
4363 /* Default to -G 8 */
4364 #ifndef MIPS_DEFAULT_GVALUE
4365 #define MIPS_DEFAULT_GVALUE 8
4366 #endif
4367
4368 /* Define the strings to put out for each section in the object file.  */
4369 #define TEXT_SECTION_ASM_OP     "\t.text"       /* instructions */
4370 #define DATA_SECTION_ASM_OP     "\t.data"       /* large data */
4371 #define SDATA_SECTION_ASM_OP    "\t.sdata"      /* small data */
4372 #ifndef READONLY_DATA_SECTION_ASM_OP
4373 #define READONLY_DATA_SECTION_ASM_OP    "\t.rdata"      /* read-only data */
4374 #endif
4375 #define SMALL_DATA_SECTION      sdata_section
4376
4377 /* What other sections we support other than the normal .data/.text.  */
4378
4379 #undef EXTRA_SECTIONS
4380 #define EXTRA_SECTIONS in_sdata
4381
4382 /* Define the additional functions to select our additional sections.  */
4383
4384 /* on the MIPS it is not a good idea to put constants in the text
4385    section, since this defeats the sdata/data mechanism. This is
4386    especially true when -O is used. In this case an effort is made to
4387    address with faster (gp) register relative addressing, which can
4388    only get at sdata and sbss items (there is no stext !!)  However,
4389    if the constant is too large for sdata, and it's readonly, it
4390    will go into the .rdata section.  */
4391
4392 #undef EXTRA_SECTION_FUNCTIONS
4393 #define EXTRA_SECTION_FUNCTIONS                                         \
4394 void                                                                    \
4395 sdata_section ()                                                        \
4396 {                                                                       \
4397   if (in_section != in_sdata)                                           \
4398     {                                                                   \
4399       fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP);             \
4400       in_section = in_sdata;                                            \
4401     }                                                                   \
4402 }
4403
4404 /* Given a decl node or constant node, choose the section to output it in
4405    and select that section.  */
4406
4407 #undef  TARGET_ASM_SELECT_SECTION
4408 #define TARGET_ASM_SELECT_SECTION  mips_select_section
4409 \f
4410 /* Store in OUTPUT a string (made with alloca) containing
4411    an assembler-name for a local static variable named NAME.
4412    LABELNO is an integer which is different for each call.  */
4413
4414 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)                  \
4415 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),                    \
4416   sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4417
4418 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)                               \
4419 do                                                                      \
4420   {                                                                     \
4421     fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n",                 \
4422              TARGET_64BIT ? "dsubu" : "subu",                           \
4423              reg_names[STACK_POINTER_REGNUM],                           \
4424              reg_names[STACK_POINTER_REGNUM],                           \
4425              TARGET_64BIT ? "sd" : "sw",                                \
4426              reg_names[REGNO],                                          \
4427              reg_names[STACK_POINTER_REGNUM]);                          \
4428   }                                                                     \
4429 while (0)
4430
4431 #define ASM_OUTPUT_REG_POP(STREAM,REGNO)                                \
4432 do                                                                      \
4433   {                                                                     \
4434     if (! set_noreorder)                                                \
4435       fprintf (STREAM, "\t.set\tnoreorder\n");                          \
4436                                                                         \
4437     dslots_load_total++;                                                \
4438     dslots_load_filled++;                                               \
4439     fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n",                 \
4440              TARGET_64BIT ? "ld" : "lw",                                \
4441              reg_names[REGNO],                                          \
4442              reg_names[STACK_POINTER_REGNUM],                           \
4443              TARGET_64BIT ? "daddu" : "addu",                           \
4444              reg_names[STACK_POINTER_REGNUM],                           \
4445              reg_names[STACK_POINTER_REGNUM]);                          \
4446                                                                         \
4447     if (! set_noreorder)                                                \
4448       fprintf (STREAM, "\t.set\treorder\n");                            \
4449   }                                                                     \
4450 while (0)
4451
4452 /* How to start an assembler comment.
4453    The leading space is important (the mips native assembler requires it).  */
4454 #ifndef ASM_COMMENT_START
4455 #define ASM_COMMENT_START " #"
4456 #endif
4457 \f
4458
4459 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4460    and mips-tdump.c to print them out.
4461
4462    These must match the corresponding definitions in gdb/mipsread.c.
4463    Unfortunately, gcc and gdb do not currently share any directories.  */
4464
4465 #define CODE_MASK 0x8F300
4466 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4467 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4468 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4469
4470 \f
4471 /* Default definitions for size_t and ptrdiff_t.  */
4472
4473 #ifndef SIZE_TYPE
4474 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4475 #endif
4476
4477 #ifndef PTRDIFF_TYPE
4478 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4479 #endif
4480
4481 /* See mips_expand_prologue's use of loadgp for when this should be
4482    true.  */
4483
4484 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS                \
4485                                          && mips_abi != ABI_32          \
4486                                          && mips_abi != ABI_O64)
4487 \f
4488 /* In mips16 mode, we need to look through the function to check for
4489    PC relative loads that are out of range.  */
4490 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4491
4492 /* We need to use a special set of functions to handle hard floating
4493    point code in mips16 mode.  */
4494
4495 #ifndef INIT_SUBTARGET_OPTABS
4496 #define INIT_SUBTARGET_OPTABS
4497 #endif
4498
4499 #define INIT_TARGET_OPTABS                                              \
4500 do                                                                      \
4501   {                                                                     \
4502     if (! TARGET_MIPS16 || ! mips16_hard_float)                         \
4503       INIT_SUBTARGET_OPTABS;                                            \
4504     else                                                                \
4505       {                                                                 \
4506         add_optab->handlers[(int) SFmode].libfunc =                     \
4507           init_one_libfunc ("__mips16_addsf3");                         \
4508         sub_optab->handlers[(int) SFmode].libfunc =                     \
4509           init_one_libfunc ("__mips16_subsf3");                         \
4510         smul_optab->handlers[(int) SFmode].libfunc =                    \
4511           init_one_libfunc ("__mips16_mulsf3");                         \
4512         sdiv_optab->handlers[(int) SFmode].libfunc =                    \
4513           init_one_libfunc ("__mips16_divsf3");                         \
4514                                                                         \
4515         eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2");            \
4516         nesf2_libfunc = init_one_libfunc ("__mips16_nesf2");            \
4517         gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2");            \
4518         gesf2_libfunc = init_one_libfunc ("__mips16_gesf2");            \
4519         ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2");            \
4520         lesf2_libfunc = init_one_libfunc ("__mips16_lesf2");            \
4521                                                                         \
4522         floatsisf_libfunc =                                             \
4523           init_one_libfunc ("__mips16_floatsisf");                      \
4524         fixsfsi_libfunc =                                               \
4525           init_one_libfunc ("__mips16_fixsfsi");                        \
4526                                                                         \
4527         if (TARGET_DOUBLE_FLOAT)                                        \
4528           {                                                             \
4529             add_optab->handlers[(int) DFmode].libfunc =                 \
4530               init_one_libfunc ("__mips16_adddf3");                     \
4531             sub_optab->handlers[(int) DFmode].libfunc =                 \
4532               init_one_libfunc ("__mips16_subdf3");                     \
4533             smul_optab->handlers[(int) DFmode].libfunc =                \
4534               init_one_libfunc ("__mips16_muldf3");                     \
4535             sdiv_optab->handlers[(int) DFmode].libfunc =                \
4536               init_one_libfunc ("__mips16_divdf3");                     \
4537                                                                         \
4538             extendsfdf2_libfunc =                                       \
4539               init_one_libfunc ("__mips16_extendsfdf2");                \
4540             truncdfsf2_libfunc =                                        \
4541               init_one_libfunc ("__mips16_truncdfsf2");                 \
4542                                                                         \
4543             eqdf2_libfunc =                                             \
4544               init_one_libfunc ("__mips16_eqdf2");                      \
4545             nedf2_libfunc =                                             \
4546               init_one_libfunc ("__mips16_nedf2");                      \
4547             gtdf2_libfunc =                                             \
4548               init_one_libfunc ("__mips16_gtdf2");                      \
4549             gedf2_libfunc =                                             \
4550               init_one_libfunc ("__mips16_gedf2");                      \
4551             ltdf2_libfunc =                                             \
4552               init_one_libfunc ("__mips16_ltdf2");                      \
4553             ledf2_libfunc =                                             \
4554               init_one_libfunc ("__mips16_ledf2");                      \
4555                                                                         \
4556             floatsidf_libfunc =                                         \
4557               init_one_libfunc ("__mips16_floatsidf");                  \
4558             fixdfsi_libfunc =                                           \
4559               init_one_libfunc ("__mips16_fixdfsi");                    \
4560           }                                                             \
4561       }                                                                 \
4562   }                                                                     \
4563 while (0)
4564
4565 #define DFMODE_NAN \
4566         unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4567         unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4568 #define SFMODE_NAN \
4569         unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4570         unsigned short SFlittlenan[2] = {0xffff, 0xffbf}