projects / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
reginfo.c (init_reg_sets_1): Adjust comments.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Costs of various operations on the different architectures. */
32
33 struct mips_rtx_cost_data
34 {
35 unsigned short fp_add;
36 unsigned short fp_mult_sf;
37 unsigned short fp_mult_df;
38 unsigned short fp_div_sf;
39 unsigned short fp_div_df;
40 unsigned short int_mult_si;
41 unsigned short int_mult_di;
42 unsigned short int_div_si;
43 unsigned short int_div_di;
44 unsigned short branch_cost;
45 unsigned short memory_latency;
46 };
47
48 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
49 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
50 to work on a 64-bit machine. */
51
52 #define ABI_32 0
53 #define ABI_N32 1
54 #define ABI_64 2
55 #define ABI_EABI 3
56 #define ABI_O64 4
57
58 /* Masks that affect tuning.
59
60 PTF_AVOID_BRANCHLIKELY
61 Set if it is usually not profitable to use branch-likely instructions
62 for this target, typically because the branches are always predicted
63 taken and so incur a large overhead when not taken. */
64 #define PTF_AVOID_BRANCHLIKELY 0x1
65
66 /* Information about one recognized processor. Defined here for the
67 benefit of TARGET_CPU_CPP_BUILTINS. */
68 struct mips_cpu_info {
69 /* The 'canonical' name of the processor as far as GCC is concerned.
70 It's typically a manufacturer's prefix followed by a numerical
71 designation. It should be lowercase. */
72 const char *name;
73
74 /* The internal processor number that most closely matches this
75 entry. Several processors can have the same value, if there's no
76 difference between them from GCC's point of view. */
77 enum processor cpu;
78
79 /* The ISA level that the processor implements. */
80 int isa;
81
82 /* A mask of PTF_* values. */
83 unsigned int tune_flags;
84 };
85
86 /* Enumerates the setting of the -mcode-readable option. */
87 enum mips_code_readable_setting {
88 CODE_READABLE_NO,
89 CODE_READABLE_PCREL,
90 CODE_READABLE_YES
91 };
92
93 /* Macros to silence warnings about numbers being signed in traditional
94 C and unsigned in ISO C when compiled on 32-bit hosts. */
95
96 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
97 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
98 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
99
100 \f
101 /* Run-time compilation parameters selecting different hardware subsets. */
102
103 /* True if we are generating position-independent VxWorks RTP code. */
104 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
105
106 /* True if the output file is marked as ".abicalls; .option pic0"
107 (-call_nonpic). */
108 #define TARGET_ABICALLS_PIC0 \
109 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
110
111 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
112 #define TARGET_ABICALLS_PIC2 \
113 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
114
115 /* True if the call patterns should be split into a jalr followed by
116 an instruction to restore $gp. It is only safe to split the load
117 from the call when every use of $gp is explicit.
118
119 See mips_must_initialize_gp_p for details about how we manage the
120 global pointer. */
121
122 #define TARGET_SPLIT_CALLS \
123 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
124
125 /* True if we're generating a form of -mabicalls in which we can use
126 operators like %hi and %lo to refer to locally-binding symbols.
127 We can only do this for -mno-shared, and only then if we can use
128 relocation operations instead of assembly macros. It isn't really
129 worth using absolute sequences for 64-bit symbols because GOT
130 accesses are so much shorter. */
131
132 #define TARGET_ABSOLUTE_ABICALLS \
133 (TARGET_ABICALLS \
134 && !TARGET_SHARED \
135 && TARGET_EXPLICIT_RELOCS \
136 && !ABI_HAS_64BIT_SYMBOLS)
137
138 /* True if we can optimize sibling calls. For simplicity, we only
139 handle cases in which call_insn_operand will reject invalid
140 sibcall addresses. There are two cases in which this isn't true:
141
142 - TARGET_MIPS16. call_insn_operand accepts constant addresses
143 but there is no direct jump instruction. It isn't worth
144 using sibling calls in this case anyway; they would usually
145 be longer than normal calls.
146
147 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
148 accepts global constants, but all sibcalls must be indirect. */
149 #define TARGET_SIBCALLS \
150 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
151
152 /* True if we need to use a global offset table to access some symbols. */
153 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
154
155 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
156 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
157
158 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
159 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
160
161 /* True if we should use .cprestore to store to the cprestore slot.
162
163 We continue to use .cprestore for explicit-reloc code so that JALs
164 inside inline asms will work correctly. */
165 #define TARGET_CPRESTORE_DIRECTIVE \
166 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
167
168 /* True if we can use the J and JAL instructions. */
169 #define TARGET_ABSOLUTE_JUMPS \
170 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
171
172 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
173 This is true for both the PIC and non-PIC VxWorks RTP modes. */
174 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
175
176 /* True if .gpword or .gpdword should be used for switch tables.
177
178 Although GAS does understand .gpdword, the SGI linker mishandles
179 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
180 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
181 #define TARGET_GPWORD \
182 (TARGET_ABICALLS \
183 && !TARGET_ABSOLUTE_ABICALLS \
184 && !(mips_abi == ABI_64 && TARGET_IRIX6))
185
186 /* True if the output must have a writable .eh_frame.
187 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
188 #ifdef HAVE_LD_PERSONALITY_RELAXATION
189 #define TARGET_WRITABLE_EH_FRAME 0
190 #else
191 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
192 #endif
193
194 /* Generate mips16 code */
195 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
196 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
197 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
198 /* Generate mips16e register save/restore sequences. */
199 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
200
201 /* True if we're generating a form of MIPS16 code in which general
202 text loads are allowed. */
203 #define TARGET_MIPS16_TEXT_LOADS \
204 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
205
206 /* True if we're generating a form of MIPS16 code in which PC-relative
207 loads are allowed. */
208 #define TARGET_MIPS16_PCREL_LOADS \
209 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
210
211 /* Generic ISA defines. */
212 #define ISA_MIPS1 (mips_isa == 1)
213 #define ISA_MIPS2 (mips_isa == 2)
214 #define ISA_MIPS3 (mips_isa == 3)
215 #define ISA_MIPS4 (mips_isa == 4)
216 #define ISA_MIPS32 (mips_isa == 32)
217 #define ISA_MIPS32R2 (mips_isa == 33)
218 #define ISA_MIPS64 (mips_isa == 64)
219 #define ISA_MIPS64R2 (mips_isa == 65)
220
221 /* Architecture target defines. */
222 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
223 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
224 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
225 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
226 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
227 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
228 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
229 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
230 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
231 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
232 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
233 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
234 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
235 || mips_arch == PROCESSOR_SB1A)
236 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
237
238 /* Scheduling target defines. */
239 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
240 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
241 || mips_tune == PROCESSOR_24KF2_1 \
242 || mips_tune == PROCESSOR_24KF1_1)
243 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
244 || mips_tune == PROCESSOR_74KF2_1 \
245 || mips_tune == PROCESSOR_74KF1_1 \
246 || mips_tune == PROCESSOR_74KF3_2)
247 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
248 || mips_tune == PROCESSOR_LOONGSON_2F)
249 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
250 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
251 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
252 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
253 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
254 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
255 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
256 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
257 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
258 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
259 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
260 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
261 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
262 || mips_tune == PROCESSOR_SB1A)
263
264 /* Whether vector modes and intrinsics for ST Microelectronics
265 Loongson-2E/2F processors should be enabled. In o32 pairs of
266 floating-point registers provide 64-bit values. */
267 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
268 && TARGET_LOONGSON_2EF)
269
270 /* True if the pre-reload scheduler should try to create chains of
271 multiply-add or multiply-subtract instructions. For example,
272 suppose we have:
273
274 t1 = a * b
275 t2 = t1 + c * d
276 t3 = e * f
277 t4 = t3 - g * h
278
279 t1 will have a higher priority than t2 and t3 will have a higher
280 priority than t4. However, before reload, there is no dependence
281 between t1 and t3, and they can often have similar priorities.
282 The scheduler will then tend to prefer:
283
284 t1 = a * b
285 t3 = e * f
286 t2 = t1 + c * d
287 t4 = t3 - g * h
288
289 which stops us from making full use of macc/madd-style instructions.
290 This sort of situation occurs frequently in Fourier transforms and
291 in unrolled loops.
292
293 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
294 queue so that chained multiply-add and multiply-subtract instructions
295 appear ahead of any other instruction that is likely to clobber lo.
296 In the example above, if t2 and t3 become ready at the same time,
297 the code ensures that t2 is scheduled first.
298
299 Multiply-accumulate instructions are a bigger win for some targets
300 than others, so this macro is defined on an opt-in basis. */
301 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
302 || TUNE_MIPS4120 \
303 || TUNE_MIPS4130 \
304 || TUNE_24K)
305
306 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
307 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
308
309 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
310 directly accessible, while the command-line options select
311 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
312 in use. */
313 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
314 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
315
316 /* False if SC acts as a memory barrier with respect to itself,
317 otherwise a SYNC will be emitted after SC for atomic operations
318 that require ordering between the SC and following loads and
319 stores. It does not tell anything about ordering of loads and
320 stores prior to and following the SC, only about the SC itself and
321 those loads and stores follow it. */
322 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
323
324 /* IRIX specific stuff. */
325 #define TARGET_IRIX6 0
326
327 /* Define preprocessor macros for the -march and -mtune options.
328 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
329 processor. If INFO's canonical name is "foo", define PREFIX to
330 be "foo", and define an additional macro PREFIX_FOO. */
331 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
332 do \
333 { \
334 char *macro, *p; \
335 \
336 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
337 for (p = macro; *p != 0; p++) \
338 *p = TOUPPER (*p); \
339 \
340 builtin_define (macro); \
341 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
342 free (macro); \
343 } \
344 while (0)
345
346 /* Target CPU builtins. */
347 #define TARGET_CPU_CPP_BUILTINS() \
348 do \
349 { \
350 /* Everyone but IRIX defines this to mips. */ \
351 if (!TARGET_IRIX6) \
352 builtin_assert ("machine=mips"); \
353 \
354 builtin_assert ("cpu=mips"); \
355 builtin_define ("__mips__"); \
356 builtin_define ("_mips"); \
357 \
358 /* We do this here because __mips is defined below and so we \
359 can't use builtin_define_std. We don't ever want to define \
360 "mips" for VxWorks because some of the VxWorks headers \
361 construct include filenames from a root directory macro, \
362 an architecture macro and a filename, where the architecture \
363 macro expands to 'mips'. If we define 'mips' to 1, the \
364 architecture macro expands to 1 as well. */ \
365 if (!flag_iso && !TARGET_VXWORKS) \
366 builtin_define ("mips"); \
367 \
368 if (TARGET_64BIT) \
369 builtin_define ("__mips64"); \
370 \
371 if (!TARGET_IRIX6) \
372 { \
373 /* Treat _R3000 and _R4000 like register-size \
374 defines, which is how they've historically \
375 been used. */ \
376 if (TARGET_64BIT) \
377 { \
378 builtin_define_std ("R4000"); \
379 builtin_define ("_R4000"); \
380 } \
381 else \
382 { \
383 builtin_define_std ("R3000"); \
384 builtin_define ("_R3000"); \
385 } \
386 } \
387 if (TARGET_FLOAT64) \
388 builtin_define ("__mips_fpr=64"); \
389 else \
390 builtin_define ("__mips_fpr=32"); \
391 \
392 if (mips_base_mips16) \
393 builtin_define ("__mips16"); \
394 \
395 if (TARGET_MIPS3D) \
396 builtin_define ("__mips3d"); \
397 \
398 if (TARGET_SMARTMIPS) \
399 builtin_define ("__mips_smartmips"); \
400 \
401 if (TARGET_DSP) \
402 { \
403 builtin_define ("__mips_dsp"); \
404 if (TARGET_DSPR2) \
405 { \
406 builtin_define ("__mips_dspr2"); \
407 builtin_define ("__mips_dsp_rev=2"); \
408 } \
409 else \
410 builtin_define ("__mips_dsp_rev=1"); \
411 } \
412 \
413 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
414 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
415 \
416 if (ISA_MIPS1) \
417 { \
418 builtin_define ("__mips=1"); \
419 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
420 } \
421 else if (ISA_MIPS2) \
422 { \
423 builtin_define ("__mips=2"); \
424 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
425 } \
426 else if (ISA_MIPS3) \
427 { \
428 builtin_define ("__mips=3"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
430 } \
431 else if (ISA_MIPS4) \
432 { \
433 builtin_define ("__mips=4"); \
434 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
435 } \
436 else if (ISA_MIPS32) \
437 { \
438 builtin_define ("__mips=32"); \
439 builtin_define ("__mips_isa_rev=1"); \
440 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
441 } \
442 else if (ISA_MIPS32R2) \
443 { \
444 builtin_define ("__mips=32"); \
445 builtin_define ("__mips_isa_rev=2"); \
446 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
447 } \
448 else if (ISA_MIPS64) \
449 { \
450 builtin_define ("__mips=64"); \
451 builtin_define ("__mips_isa_rev=1"); \
452 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
453 } \
454 else if (ISA_MIPS64R2) \
455 { \
456 builtin_define ("__mips=64"); \
457 builtin_define ("__mips_isa_rev=2"); \
458 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
459 } \
460 \
461 switch (mips_abi) \
462 { \
463 case ABI_32: \
464 builtin_define ("_ABIO32=1"); \
465 builtin_define ("_MIPS_SIM=_ABIO32"); \
466 break; \
467 \
468 case ABI_N32: \
469 builtin_define ("_ABIN32=2"); \
470 builtin_define ("_MIPS_SIM=_ABIN32"); \
471 break; \
472 \
473 case ABI_64: \
474 builtin_define ("_ABI64=3"); \
475 builtin_define ("_MIPS_SIM=_ABI64"); \
476 break; \
477 \
478 case ABI_O64: \
479 builtin_define ("_ABIO64=4"); \
480 builtin_define ("_MIPS_SIM=_ABIO64"); \
481 break; \
482 } \
483 \
484 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
485 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
486 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
487 builtin_define_with_int_value ("_MIPS_FPSET", \
488 32 / MAX_FPRS_PER_FMT); \
489 \
490 /* These defines reflect the ABI in use, not whether the \
491 FPU is directly accessible. */ \
492 if (TARGET_NO_FLOAT) \
493 builtin_define ("__mips_no_float"); \
494 else if (TARGET_HARD_FLOAT_ABI) \
495 builtin_define ("__mips_hard_float"); \
496 else \
497 builtin_define ("__mips_soft_float"); \
498 \
499 if (TARGET_SINGLE_FLOAT) \
500 builtin_define ("__mips_single_float"); \
501 \
502 if (TARGET_PAIRED_SINGLE_FLOAT) \
503 builtin_define ("__mips_paired_single_float"); \
504 \
505 if (TARGET_BIG_ENDIAN) \
506 { \
507 builtin_define_std ("MIPSEB"); \
508 builtin_define ("_MIPSEB"); \
509 } \
510 else \
511 { \
512 builtin_define_std ("MIPSEL"); \
513 builtin_define ("_MIPSEL"); \
514 } \
515 \
516 /* Whether calls should go through $25. The separate __PIC__ \
517 macro indicates whether abicalls code might use a GOT. */ \
518 if (TARGET_ABICALLS) \
519 builtin_define ("__mips_abicalls"); \
520 \
521 /* Whether Loongson vector modes are enabled. */ \
522 if (TARGET_LOONGSON_VECTORS) \
523 builtin_define ("__mips_loongson_vector_rev"); \
524 \
525 /* Historical Octeon macro. */ \
526 if (TARGET_OCTEON) \
527 builtin_define ("__OCTEON__"); \
528 \
529 /* Macros dependent on the C dialect. */ \
530 if (preprocessing_asm_p ()) \
531 { \
532 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
533 builtin_define ("_LANGUAGE_ASSEMBLY"); \
534 } \
535 else if (c_dialect_cxx ()) \
536 { \
537 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
538 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
539 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
540 } \
541 else \
542 { \
543 builtin_define_std ("LANGUAGE_C"); \
544 builtin_define ("_LANGUAGE_C"); \
545 } \
546 if (c_dialect_objc ()) \
547 { \
548 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
549 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
550 /* Bizarre, but needed at least for Irix. */ \
551 builtin_define_std ("LANGUAGE_C"); \
552 builtin_define ("_LANGUAGE_C"); \
553 } \
554 \
555 if (mips_abi == ABI_EABI) \
556 builtin_define ("__mips_eabi"); \
557 \
558 if (TARGET_CACHE_BUILTIN) \
559 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
560 } \
561 while (0)
562
563 /* Default target_flags if no switches are specified */
564
565 #ifndef TARGET_DEFAULT
566 #define TARGET_DEFAULT 0
567 #endif
568
569 #ifndef TARGET_CPU_DEFAULT
570 #define TARGET_CPU_DEFAULT 0
571 #endif
572
573 #ifndef TARGET_ENDIAN_DEFAULT
574 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
575 #endif
576
577 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
578 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
579 #endif
580
581 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
582 #ifndef MIPS_ISA_DEFAULT
583 #ifndef MIPS_CPU_STRING_DEFAULT
584 #define MIPS_CPU_STRING_DEFAULT "from-abi"
585 #endif
586 #endif
587
588 #ifdef IN_LIBGCC2
589 #undef TARGET_64BIT
590 /* Make this compile time constant for libgcc2 */
591 #ifdef __mips64
592 #define TARGET_64BIT 1
593 #else
594 #define TARGET_64BIT 0
595 #endif
596 #endif /* IN_LIBGCC2 */
597
598 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
599 when compiled with hardware floating point. This is because MIPS16
600 code cannot save and restore the floating-point registers, which is
601 important if in a mixed MIPS16/non-MIPS16 environment. */
602
603 #ifdef IN_LIBGCC2
604 #if __mips_hard_float
605 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
606 #endif
607 #endif /* IN_LIBGCC2 */
608
609 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
610
611 #ifndef MULTILIB_ENDIAN_DEFAULT
612 #if TARGET_ENDIAN_DEFAULT == 0
613 #define MULTILIB_ENDIAN_DEFAULT "EL"
614 #else
615 #define MULTILIB_ENDIAN_DEFAULT "EB"
616 #endif
617 #endif
618
619 #ifndef MULTILIB_ISA_DEFAULT
620 # if MIPS_ISA_DEFAULT == 1
621 # define MULTILIB_ISA_DEFAULT "mips1"
622 # else
623 # if MIPS_ISA_DEFAULT == 2
624 # define MULTILIB_ISA_DEFAULT "mips2"
625 # else
626 # if MIPS_ISA_DEFAULT == 3
627 # define MULTILIB_ISA_DEFAULT "mips3"
628 # else
629 # if MIPS_ISA_DEFAULT == 4
630 # define MULTILIB_ISA_DEFAULT "mips4"
631 # else
632 # if MIPS_ISA_DEFAULT == 32
633 # define MULTILIB_ISA_DEFAULT "mips32"
634 # else
635 # if MIPS_ISA_DEFAULT == 33
636 # define MULTILIB_ISA_DEFAULT "mips32r2"
637 # else
638 # if MIPS_ISA_DEFAULT == 64
639 # define MULTILIB_ISA_DEFAULT "mips64"
640 # else
641 # if MIPS_ISA_DEFAULT == 65
642 # define MULTILIB_ISA_DEFAULT "mips64r2"
643 # else
644 # define MULTILIB_ISA_DEFAULT "mips1"
645 # endif
646 # endif
647 # endif
648 # endif
649 # endif
650 # endif
651 # endif
652 # endif
653 #endif
654
655 #ifndef MIPS_ABI_DEFAULT
656 #define MIPS_ABI_DEFAULT ABI_32
657 #endif
658
659 /* Use the most portable ABI flag for the ASM specs. */
660
661 #if MIPS_ABI_DEFAULT == ABI_32
662 #define MULTILIB_ABI_DEFAULT "mabi=32"
663 #endif
664
665 #if MIPS_ABI_DEFAULT == ABI_O64
666 #define MULTILIB_ABI_DEFAULT "mabi=o64"
667 #endif
668
669 #if MIPS_ABI_DEFAULT == ABI_N32
670 #define MULTILIB_ABI_DEFAULT "mabi=n32"
671 #endif
672
673 #if MIPS_ABI_DEFAULT == ABI_64
674 #define MULTILIB_ABI_DEFAULT "mabi=64"
675 #endif
676
677 #if MIPS_ABI_DEFAULT == ABI_EABI
678 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
679 #endif
680
681 #ifndef MULTILIB_DEFAULTS
682 #define MULTILIB_DEFAULTS \
683 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
684 #endif
685
686 /* We must pass -EL to the linker by default for little endian embedded
687 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
688 linker will default to using big-endian output files. The OUTPUT_FORMAT
689 line must be in the linker script, otherwise -EB/-EL will not work. */
690
691 #ifndef ENDIAN_SPEC
692 #if TARGET_ENDIAN_DEFAULT == 0
693 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
694 #else
695 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
696 #endif
697 #endif
698
699 /* A spec condition that matches all non-mips16 -mips arguments. */
700
701 #define MIPS_ISA_LEVEL_OPTION_SPEC \
702 "mips1|mips2|mips3|mips4|mips32*|mips64*"
703
704 /* A spec condition that matches all non-mips16 architecture arguments. */
705
706 #define MIPS_ARCH_OPTION_SPEC \
707 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
708
709 /* A spec that infers a -mips argument from an -march argument,
710 or injects the default if no architecture is specified. */
711
712 #define MIPS_ISA_LEVEL_SPEC \
713 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
714 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
715 %{march=mips2|march=r6000:-mips2} \
716 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
717 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
718 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
719 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
720 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
721 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
722 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
723 |march=xlr: -mips64} \
724 %{march=mips64r2|march=octeon: -mips64r2} \
725 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
726
727 /* A spec that infers a -mhard-float or -msoft-float setting from an
728 -march argument. Note that soft-float and hard-float code are not
729 link-compatible. */
730
731 #define MIPS_ARCH_FLOAT_SPEC \
732 "%{mhard-float|msoft-float|march=mips*:; \
733 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
734 |march=34kc|march=74kc|march=1004kc|march=5kc \
735 |march=octeon|march=xlr: -msoft-float; \
736 march=*: -mhard-float}"
737
738 /* A spec condition that matches 32-bit options. It only works if
739 MIPS_ISA_LEVEL_SPEC has been applied. */
740
741 #define MIPS_32BIT_OPTION_SPEC \
742 "mips1|mips2|mips32*|mgp32"
743
744 #if MIPS_ABI_DEFAULT == ABI_O64 \
745 || MIPS_ABI_DEFAULT == ABI_N32 \
746 || MIPS_ABI_DEFAULT == ABI_64
747 #define OPT_ARCH64 "mabi=32|mgp32:;"
748 #define OPT_ARCH32 "mabi=32|mgp32"
749 #else
750 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
751 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
752 #endif
753
754 /* Support for a compile-time default CPU, et cetera. The rules are:
755 --with-arch is ignored if -march is specified or a -mips is specified
756 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
757 --with-tune is ignored if -mtune is specified; likewise
758 --with-tune-32 and --with-tune-64.
759 --with-abi is ignored if -mabi is specified.
760 --with-float is ignored if -mhard-float or -msoft-float are
761 specified.
762 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
763 specified. */
764 #define OPTION_DEFAULT_SPECS \
765 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
766 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
767 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
768 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
769 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
770 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
771 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
772 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
773 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
774 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
775 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
776 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
777
778
779 /* A spec that infers the -mdsp setting from an -march argument. */
780 #define BASE_DRIVER_SELF_SPECS \
781 "%{!mno-dsp:%{march=24ke*|march=34k*|march=74k*|march=1004k*: -mdsp}}"
782
783 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
784
785 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
786 && ISA_HAS_COND_TRAP)
787
788 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
789
790 /* True if the ABI can only work with 64-bit integer registers. We
791 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
792 otherwise floating-point registers must also be 64-bit. */
793 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
794
795 /* Likewise for 32-bit regs. */
796 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
797
798 /* True if the file format uses 64-bit symbols. At present, this is
799 only true for n64, which uses 64-bit ELF. */
800 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
801
802 /* True if symbols are 64 bits wide. This is usually determined by
803 the ABI's file format, but it can be overridden by -msym32. Note that
804 overriding the size with -msym32 changes the ABI of relocatable objects,
805 although it doesn't change the ABI of a fully-linked object. */
806 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS && !TARGET_SYM32)
807
808 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
809 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
810 || ISA_MIPS4 \
811 || ISA_MIPS64 \
812 || ISA_MIPS64R2)
813
814 /* ISA has branch likely instructions (e.g. mips2). */
815 /* Disable branchlikely for tx39 until compare rewrite. They haven't
816 been generated up to this point. */
817 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
818
819 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
820 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
821 || TARGET_MIPS5400 \
822 || TARGET_MIPS5500 \
823 || TARGET_MIPS7000 \
824 || TARGET_MIPS9000 \
825 || TARGET_MAD \
826 || ISA_MIPS32 \
827 || ISA_MIPS32R2 \
828 || ISA_MIPS64 \
829 || ISA_MIPS64R2) \
830 && !TARGET_MIPS16)
831
832 /* ISA has a three-operand multiplication instruction. */
833 #define ISA_HAS_DMUL3 (TARGET_64BIT \
834 && TARGET_OCTEON \
835 && !TARGET_MIPS16)
836
837 /* ISA has the floating-point conditional move instructions introduced
838 in mips4. */
839 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
840 || ISA_MIPS32 \
841 || ISA_MIPS32R2 \
842 || ISA_MIPS64 \
843 || ISA_MIPS64R2) \
844 && !TARGET_MIPS5500 \
845 && !TARGET_MIPS16)
846
847 /* ISA has the integer conditional move instructions introduced in mips4 and
848 ST Loongson 2E/2F. */
849 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
850
851 /* ISA has LDC1 and SDC1. */
852 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
853
854 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
855 branch on CC, and move (both FP and non-FP) on CC. */
856 #define ISA_HAS_8CC (ISA_MIPS4 \
857 || ISA_MIPS32 \
858 || ISA_MIPS32R2 \
859 || ISA_MIPS64 \
860 || ISA_MIPS64R2)
861
862 /* This is a catch all for other mips4 instructions: indexed load, the
863 FP madd and msub instructions, and the FP recip and recip sqrt
864 instructions. */
865 #define ISA_HAS_FP4 ((ISA_MIPS4 \
866 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
867 || ISA_MIPS64 \
868 || ISA_MIPS64R2) \
869 && !TARGET_MIPS16)
870
871 /* ISA has paired-single instructions. */
872 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
873
874 /* ISA has conditional trap instructions. */
875 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
876 && !TARGET_MIPS16)
877
878 /* ISA has integer multiply-accumulate instructions, madd and msub. */
879 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
880 || ISA_MIPS32R2 \
881 || ISA_MIPS64 \
882 || ISA_MIPS64R2) \
883 && !TARGET_MIPS16)
884
885 /* Integer multiply-accumulate instructions should be generated. */
886 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
887
888 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
889 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
890
891 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
892 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
893
894 /* ISA has floating-point nmadd and nmsub instructions
895 'd = -((a * b) [+-] c)'. */
896 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
897 ((ISA_MIPS4 \
898 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
899 || ISA_MIPS64 \
900 || ISA_MIPS64R2) \
901 && (!TARGET_MIPS5400 || TARGET_MAD) \
902 && !TARGET_MIPS16)
903
904 /* ISA has floating-point nmadd and nmsub instructions
905 'c = -((a * b) [+-] c)'. */
906 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
907 TARGET_LOONGSON_2EF
908
909 /* ISA has count leading zeroes/ones instruction (not implemented). */
910 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
911 || ISA_MIPS32R2 \
912 || ISA_MIPS64 \
913 || ISA_MIPS64R2) \
914 && !TARGET_MIPS16)
915
916 /* ISA has three operand multiply instructions that put
917 the high part in an accumulator: mulhi or mulhiu. */
918 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
919 || TARGET_MIPS5500 \
920 || TARGET_SR71K) \
921 && !TARGET_MIPS16)
922
923 /* ISA has three operand multiply instructions that
924 negates the result and puts the result in an accumulator. */
925 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
926 || TARGET_MIPS5500 \
927 || TARGET_SR71K) \
928 && !TARGET_MIPS16)
929
930 /* ISA has three operand multiply instructions that subtracts the
931 result from a 4th operand and puts the result in an accumulator. */
932 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
933 || TARGET_MIPS5500 \
934 || TARGET_SR71K) \
935 && !TARGET_MIPS16)
936
937 /* ISA has three operand multiply instructions that the result
938 from a 4th operand and puts the result in an accumulator. */
939 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
940 || TARGET_MIPS4130 \
941 || TARGET_MIPS5400 \
942 || TARGET_MIPS5500 \
943 || TARGET_SR71K) \
944 && !TARGET_MIPS16)
945
946 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
947 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
948 || TARGET_MIPS4130) \
949 && !TARGET_MIPS16)
950
951 /* ISA has the "ror" (rotate right) instructions. */
952 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
953 || ISA_MIPS64R2 \
954 || TARGET_MIPS5400 \
955 || TARGET_MIPS5500 \
956 || TARGET_SR71K \
957 || TARGET_SMARTMIPS) \
958 && !TARGET_MIPS16)
959
960 /* ISA has data prefetch instructions. This controls use of 'pref'. */
961 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
962 || TARGET_LOONGSON_2EF \
963 || ISA_MIPS32 \
964 || ISA_MIPS32R2 \
965 || ISA_MIPS64 \
966 || ISA_MIPS64R2) \
967 && !TARGET_MIPS16)
968
969 /* ISA has data indexed prefetch instructions. This controls use of
970 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
971 (prefx is a cop1x instruction, so can only be used if FP is
972 enabled.) */
973 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
974 || ISA_MIPS32R2 \
975 || ISA_MIPS64 \
976 || ISA_MIPS64R2) \
977 && !TARGET_MIPS16)
978
979 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
980 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
981 also requires TARGET_DOUBLE_FLOAT. */
982 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
983
984 /* ISA includes the MIPS32r2 seb and seh instructions. */
985 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
986 || ISA_MIPS64R2) \
987 && !TARGET_MIPS16)
988
989 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
990 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
991 || ISA_MIPS64R2) \
992 && !TARGET_MIPS16)
993
994 /* ISA has instructions for accessing top part of 64-bit fp regs. */
995 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
996 && (ISA_MIPS32R2 \
997 || ISA_MIPS64R2))
998
999 /* ISA has lwxs instruction (load w/scaled index address. */
1000 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
1001
1002 /* The DSP ASE is available. */
1003 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1004
1005 /* Revision 2 of the DSP ASE is available. */
1006 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1007
1008 /* True if the result of a load is not available to the next instruction.
1009 A nop will then be needed between instructions like "lw $4,..."
1010 and "addiu $4,$4,1". */
1011 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1012 && !TARGET_MIPS3900 \
1013 && !TARGET_MIPS16)
1014
1015 /* Likewise mtc1 and mfc1. */
1016 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1017 && !TARGET_LOONGSON_2EF)
1018
1019 /* Likewise floating-point comparisons. */
1020 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1021 && !TARGET_LOONGSON_2EF)
1022
1023 /* True if mflo and mfhi can be immediately followed by instructions
1024 which write to the HI and LO registers.
1025
1026 According to MIPS specifications, MIPS ISAs I, II, and III need
1027 (at least) two instructions between the reads of HI/LO and
1028 instructions which write them, and later ISAs do not. Contradicting
1029 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1030 the UM for the NEC Vr5000) document needing the instructions between
1031 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1032 MIPS64 and later ISAs to have the interlocks, plus any specific
1033 earlier-ISA CPUs for which CPU documentation declares that the
1034 instructions are really interlocked. */
1035 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1036 || ISA_MIPS32R2 \
1037 || ISA_MIPS64 \
1038 || ISA_MIPS64R2 \
1039 || TARGET_MIPS5500 \
1040 || TARGET_LOONGSON_2EF)
1041
1042 /* ISA includes synci, jr.hb and jalr.hb. */
1043 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1044 || ISA_MIPS64R2) \
1045 && !TARGET_MIPS16)
1046
1047 /* ISA includes sync. */
1048 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1049 #define GENERATE_SYNC \
1050 (target_flags_explicit & MASK_LLSC \
1051 ? TARGET_LLSC && !TARGET_MIPS16 \
1052 : ISA_HAS_SYNC)
1053
1054 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1055 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1056 instructions. */
1057 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1058 #define GENERATE_LL_SC \
1059 (target_flags_explicit & MASK_LLSC \
1060 ? TARGET_LLSC && !TARGET_MIPS16 \
1061 : ISA_HAS_LL_SC)
1062
1063 /* ISA includes the baddu instruction. */
1064 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1065
1066 /* ISA includes the bbit* instructions. */
1067 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1068
1069 /* ISA includes the cins instruction. */
1070 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1071
1072 /* ISA includes the exts instruction. */
1073 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1074
1075 /* ISA includes the seq and sne instructions. */
1076 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1077
1078 /* ISA includes the pop instruction. */
1079 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1080
1081 /* The CACHE instruction is available in non-MIPS16 code. */
1082 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1083
1084 /* The CACHE instruction is available. */
1085 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1086 \f
1087 /* Add -G xx support. */
1088
1089 #undef SWITCH_TAKES_ARG
1090 #define SWITCH_TAKES_ARG(CHAR) \
1091 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1092
1093 #define OVERRIDE_OPTIONS mips_override_options ()
1094
1095 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1096
1097 /* Show we can debug even without a frame pointer. */
1098 #define CAN_DEBUG_WITHOUT_FP
1099 \f
1100 /* Tell collect what flags to pass to nm. */
1101 #ifndef NM_FLAGS
1102 #define NM_FLAGS "-Bn"
1103 #endif
1104
1105 \f
1106 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1107 to the assembler. It may be overridden by subtargets. */
1108 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1109 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1110 %{noasmopt:-O0} \
1111 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1112 #endif
1113
1114 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1115 the assembler. It may be overridden by subtargets.
1116
1117 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1118 COFF debugging info. */
1119
1120 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1121 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1122 %{g} %{g0} %{g1} %{g2} %{g3} \
1123 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1124 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1125 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1126 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1127 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1128 #endif
1129
1130 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1131 overridden by subtargets. */
1132
1133 #ifndef SUBTARGET_ASM_SPEC
1134 #define SUBTARGET_ASM_SPEC ""
1135 #endif
1136
1137 #undef ASM_SPEC
1138 #define ASM_SPEC "\
1139 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1140 %{mips32*} %{mips64*} \
1141 %{mips16} %{mno-mips16:-no-mips16} \
1142 %{mips3d} %{mno-mips3d:-no-mips3d} \
1143 %{mdmx} %{mno-mdmx:-no-mdmx} \
1144 %{mdsp} %{mno-dsp} \
1145 %{mdspr2} %{mno-dspr2} \
1146 %{msmartmips} %{mno-smartmips} \
1147 %{mmt} %{mno-mt} \
1148 %{mfix-vr4120} %{mfix-vr4130} \
1149 %(subtarget_asm_optimizing_spec) \
1150 %(subtarget_asm_debugging_spec) \
1151 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1152 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1153 %{mfp32} %{mfp64} \
1154 %{mshared} %{mno-shared} \
1155 %{msym32} %{mno-sym32} \
1156 %{mtune=*} %{v} \
1157 %(subtarget_asm_spec)"
1158
1159 /* Extra switches sometimes passed to the linker. */
1160 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1161 will interpret it as a -b option. */
1162
1163 #ifndef LINK_SPEC
1164 #define LINK_SPEC "\
1165 %(endian_spec) \
1166 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1167 %{bestGnum} %{shared} %{non_shared}"
1168 #endif /* LINK_SPEC defined */
1169
1170
1171 /* Specs for the compiler proper */
1172
1173 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1174 overridden by subtargets. */
1175 #ifndef SUBTARGET_CC1_SPEC
1176 #define SUBTARGET_CC1_SPEC ""
1177 #endif
1178
1179 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1180
1181 #undef CC1_SPEC
1182 #define CC1_SPEC "\
1183 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1184 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1185 %{save-temps: } \
1186 %(subtarget_cc1_spec)"
1187
1188 /* Preprocessor specs. */
1189
1190 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1191 overridden by subtargets. */
1192 #ifndef SUBTARGET_CPP_SPEC
1193 #define SUBTARGET_CPP_SPEC ""
1194 #endif
1195
1196 #define CPP_SPEC "%(subtarget_cpp_spec)"
1197
1198 /* This macro defines names of additional specifications to put in the specs
1199 that can be used in various specifications like CC1_SPEC. Its definition
1200 is an initializer with a subgrouping for each command option.
1201
1202 Each subgrouping contains a string constant, that defines the
1203 specification name, and a string constant that used by the GCC driver
1204 program.
1205
1206 Do not define this macro if it does not need to do anything. */
1207
1208 #define EXTRA_SPECS \
1209 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1210 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1211 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1212 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1213 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1214 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1215 { "endian_spec", ENDIAN_SPEC }, \
1216 SUBTARGET_EXTRA_SPECS
1217
1218 #ifndef SUBTARGET_EXTRA_SPECS
1219 #define SUBTARGET_EXTRA_SPECS
1220 #endif
1221 \f
1222 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1223 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1224
1225 #ifndef PREFERRED_DEBUGGING_TYPE
1226 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1227 #endif
1228
1229 /* The size of DWARF addresses should be the same as the size of symbols
1230 in the target file format. They shouldn't depend on things like -msym32,
1231 because many DWARF consumers do not allow the mixture of address sizes
1232 that one would then get from linking -msym32 code with -msym64 code.
1233
1234 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1235 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1236 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1237
1238 /* By default, turn on GDB extensions. */
1239 #define DEFAULT_GDB_EXTENSIONS 1
1240
1241 /* Local compiler-generated symbols must have a prefix that the assembler
1242 understands. By default, this is $, although some targets (e.g.,
1243 NetBSD-ELF) need to override this. */
1244
1245 #ifndef LOCAL_LABEL_PREFIX
1246 #define LOCAL_LABEL_PREFIX "$"
1247 #endif
1248
1249 /* By default on the mips, external symbols do not have an underscore
1250 prepended, but some targets (e.g., NetBSD) require this. */
1251
1252 #ifndef USER_LABEL_PREFIX
1253 #define USER_LABEL_PREFIX ""
1254 #endif
1255
1256 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1257 since the length can run past this up to a continuation point. */
1258 #undef DBX_CONTIN_LENGTH
1259 #define DBX_CONTIN_LENGTH 1500
1260
1261 /* How to renumber registers for dbx and gdb. */
1262 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1263
1264 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1265 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1266
1267 /* The DWARF 2 CFA column which tracks the return address. */
1268 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1269
1270 /* Before the prologue, RA lives in r31. */
1271 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1272
1273 /* Describe how we implement __builtin_eh_return. */
1274 #define EH_RETURN_DATA_REGNO(N) \
1275 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1276
1277 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1278
1279 #define EH_USES(N) mips_eh_uses (N)
1280
1281 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1282 The default for this in 64-bit mode is 8, which causes problems with
1283 SFmode register saves. */
1284 #define DWARF_CIE_DATA_ALIGNMENT -4
1285
1286 /* Correct the offset of automatic variables and arguments. Note that
1287 the MIPS debug format wants all automatic variables and arguments
1288 to be in terms of the virtual frame pointer (stack pointer before
1289 any adjustment in the function), while the MIPS 3.0 linker wants
1290 the frame pointer to be the stack pointer after the initial
1291 adjustment. */
1292
1293 #define DEBUGGER_AUTO_OFFSET(X) \
1294 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1295 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1296 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1297 \f
1298 /* Target machine storage layout */
1299
1300 #define BITS_BIG_ENDIAN 0
1301 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1302 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1303
1304 /* Define this to set the endianness to use in libgcc2.c, which can
1305 not depend on target_flags. */
1306 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1307 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1308 #else
1309 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1310 #endif
1311
1312 #define MAX_BITS_PER_WORD 64
1313
1314 /* Width of a word, in units (bytes). */
1315 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1316 #ifndef IN_LIBGCC2
1317 #define MIN_UNITS_PER_WORD 4
1318 #endif
1319
1320 /* For MIPS, width of a floating point register. */
1321 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1322
1323 /* The number of consecutive floating-point registers needed to store the
1324 largest format supported by the FPU. */
1325 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1326
1327 /* The number of consecutive floating-point registers needed to store the
1328 smallest format supported by the FPU. */
1329 #define MIN_FPRS_PER_FMT \
1330 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1331 ? 1 : MAX_FPRS_PER_FMT)
1332
1333 /* The largest size of value that can be held in floating-point
1334 registers and moved with a single instruction. */
1335 #define UNITS_PER_HWFPVALUE \
1336 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1337
1338 /* The largest size of value that can be held in floating-point
1339 registers. */
1340 #define UNITS_PER_FPVALUE \
1341 (TARGET_SOFT_FLOAT_ABI ? 0 \
1342 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1343 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1344
1345 /* The number of bytes in a double. */
1346 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1347
1348 #define UNITS_PER_SIMD_WORD(MODE) \
1349 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1350
1351 /* Set the sizes of the core types. */
1352 #define SHORT_TYPE_SIZE 16
1353 #define INT_TYPE_SIZE 32
1354 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1355 #define LONG_LONG_TYPE_SIZE 64
1356
1357 #define FLOAT_TYPE_SIZE 32
1358 #define DOUBLE_TYPE_SIZE 64
1359 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1360
1361 /* Define the sizes of fixed-point types. */
1362 #define SHORT_FRACT_TYPE_SIZE 8
1363 #define FRACT_TYPE_SIZE 16
1364 #define LONG_FRACT_TYPE_SIZE 32
1365 #define LONG_LONG_FRACT_TYPE_SIZE 64
1366
1367 #define SHORT_ACCUM_TYPE_SIZE 16
1368 #define ACCUM_TYPE_SIZE 32
1369 #define LONG_ACCUM_TYPE_SIZE 64
1370 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1371 doesn't support 128-bit integers for MIPS32 currently. */
1372 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1373
1374 /* long double is not a fixed mode, but the idea is that, if we
1375 support long double, we also want a 128-bit integer type. */
1376 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1377
1378 #ifdef IN_LIBGCC2
1379 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1380 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1381 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1382 # else
1383 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1384 # endif
1385 #endif
1386
1387 /* Width in bits of a pointer. */
1388 #ifndef POINTER_SIZE
1389 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1390 #endif
1391
1392 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1393 #define PARM_BOUNDARY BITS_PER_WORD
1394
1395 /* Allocation boundary (in *bits*) for the code of a function. */
1396 #define FUNCTION_BOUNDARY 32
1397
1398 /* Alignment of field after `int : 0' in a structure. */
1399 #define EMPTY_FIELD_BOUNDARY 32
1400
1401 /* Every structure's size must be a multiple of this. */
1402 /* 8 is observed right on a DECstation and on riscos 4.02. */
1403 #define STRUCTURE_SIZE_BOUNDARY 8
1404
1405 /* There is no point aligning anything to a rounder boundary than this. */
1406 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1407
1408 /* All accesses must be aligned. */
1409 #define STRICT_ALIGNMENT 1
1410
1411 /* Define this if you wish to imitate the way many other C compilers
1412 handle alignment of bitfields and the structures that contain
1413 them.
1414
1415 The behavior is that the type written for a bit-field (`int',
1416 `short', or other integer type) imposes an alignment for the
1417 entire structure, as if the structure really did contain an
1418 ordinary field of that type. In addition, the bit-field is placed
1419 within the structure so that it would fit within such a field,
1420 not crossing a boundary for it.
1421
1422 Thus, on most machines, a bit-field whose type is written as `int'
1423 would not cross a four-byte boundary, and would force four-byte
1424 alignment for the whole structure. (The alignment used may not
1425 be four bytes; it is controlled by the other alignment
1426 parameters.)
1427
1428 If the macro is defined, its definition should be a C expression;
1429 a nonzero value for the expression enables this behavior. */
1430
1431 #define PCC_BITFIELD_TYPE_MATTERS 1
1432
1433 /* If defined, a C expression to compute the alignment given to a
1434 constant that is being placed in memory. CONSTANT is the constant
1435 and ALIGN is the alignment that the object would ordinarily have.
1436 The value of this macro is used instead of that alignment to align
1437 the object.
1438
1439 If this macro is not defined, then ALIGN is used.
1440
1441 The typical use of this macro is to increase alignment for string
1442 constants to be word aligned so that `strcpy' calls that copy
1443 constants can be done inline. */
1444
1445 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1446 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1447 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1448
1449 /* If defined, a C expression to compute the alignment for a static
1450 variable. TYPE is the data type, and ALIGN is the alignment that
1451 the object would ordinarily have. The value of this macro is used
1452 instead of that alignment to align the object.
1453
1454 If this macro is not defined, then ALIGN is used.
1455
1456 One use of this macro is to increase alignment of medium-size
1457 data to make it all fit in fewer cache lines. Another is to
1458 cause character arrays to be word-aligned so that `strcpy' calls
1459 that copy constants to character arrays can be done inline. */
1460
1461 #undef DATA_ALIGNMENT
1462 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1463 ((((ALIGN) < BITS_PER_WORD) \
1464 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1465 || TREE_CODE (TYPE) == UNION_TYPE \
1466 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1467
1468 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1469 character arrays to be word-aligned so that `strcpy' calls that copy
1470 constants to character arrays can be done inline, and 'strcmp' can be
1471 optimised to use word loads. */
1472 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1473 DATA_ALIGNMENT (TYPE, ALIGN)
1474
1475 #define PAD_VARARGS_DOWN \
1476 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1477
1478 /* Define if operations between registers always perform the operation
1479 on the full register even if a narrower mode is specified. */
1480 #define WORD_REGISTER_OPERATIONS
1481
1482 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1483 moves. All other references are zero extended. */
1484 #define LOAD_EXTEND_OP(MODE) \
1485 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1486 ? SIGN_EXTEND : ZERO_EXTEND)
1487
1488 /* Define this macro if it is advisable to hold scalars in registers
1489 in a wider mode than that declared by the program. In such cases,
1490 the value is constrained to be within the bounds of the declared
1491 type, but kept valid in the wider mode. The signedness of the
1492 extension may differ from that of the type. */
1493
1494 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1495 if (GET_MODE_CLASS (MODE) == MODE_INT \
1496 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1497 { \
1498 if ((MODE) == SImode) \
1499 (UNSIGNEDP) = 0; \
1500 (MODE) = Pmode; \
1501 }
1502
1503 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1504 Extensions of pointers to word_mode must be signed. */
1505 #define POINTERS_EXTEND_UNSIGNED false
1506
1507 /* Define if loading short immediate values into registers sign extends. */
1508 #define SHORT_IMMEDIATES_SIGN_EXTEND
1509
1510 /* The [d]clz instructions have the natural values at 0. */
1511
1512 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1513 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1514 \f
1515 /* Standard register usage. */
1516
1517 /* Number of hardware registers. We have:
1518
1519 - 32 integer registers
1520 - 32 floating point registers
1521 - 8 condition code registers
1522 - 2 accumulator registers (hi and lo)
1523 - 32 registers each for coprocessors 0, 2 and 3
1524 - 4 fake registers:
1525 - ARG_POINTER_REGNUM
1526 - FRAME_POINTER_REGNUM
1527 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1528 - CPRESTORE_SLOT_REGNUM
1529 - 2 dummy entries that were used at various times in the past.
1530 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1531 - 6 DSP control registers */
1532
1533 #define FIRST_PSEUDO_REGISTER 188
1534
1535 /* By default, fix the kernel registers ($26 and $27), the global
1536 pointer ($28) and the stack pointer ($29). This can change
1537 depending on the command-line options.
1538
1539 Regarding coprocessor registers: without evidence to the contrary,
1540 it's best to assume that each coprocessor register has a unique
1541 use. This can be overridden, in, e.g., mips_override_options or
1542 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1543 for a particular target. */
1544
1545 #define FIXED_REGISTERS \
1546 { \
1547 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1549 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1550 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1551 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1552 /* COP0 registers */ \
1553 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1554 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1555 /* COP2 registers */ \
1556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1557 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1558 /* COP3 registers */ \
1559 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1561 /* 6 DSP accumulator registers & 6 control registers */ \
1562 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1563 }
1564
1565
1566 /* Set up this array for o32 by default.
1567
1568 Note that we don't mark $31 as a call-clobbered register. The idea is
1569 that it's really the call instructions themselves which clobber $31.
1570 We don't care what the called function does with it afterwards.
1571
1572 This approach makes it easier to implement sibcalls. Unlike normal
1573 calls, sibcalls don't clobber $31, so the register reaches the
1574 called function in tact. EPILOGUE_USES says that $31 is useful
1575 to the called function. */
1576
1577 #define CALL_USED_REGISTERS \
1578 { \
1579 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1580 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1581 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1582 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1583 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1584 /* COP0 registers */ \
1585 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1586 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1587 /* COP2 registers */ \
1588 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1589 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1590 /* COP3 registers */ \
1591 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1592 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1593 /* 6 DSP accumulator registers & 6 control registers */ \
1594 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1595 }
1596
1597
1598 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1599
1600 #define CALL_REALLY_USED_REGISTERS \
1601 { /* General registers. */ \
1602 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1603 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1604 /* Floating-point registers. */ \
1605 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1606 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1607 /* Others. */ \
1608 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1609 /* COP0 registers */ \
1610 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1611 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1612 /* COP2 registers */ \
1613 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1614 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1615 /* COP3 registers */ \
1616 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1617 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1618 /* 6 DSP accumulator registers & 6 control registers */ \
1619 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1620 }
1621
1622 /* Internal macros to classify a register number as to whether it's a
1623 general purpose register, a floating point register, a
1624 multiply/divide register, or a status register. */
1625
1626 #define GP_REG_FIRST 0
1627 #define GP_REG_LAST 31
1628 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1629 #define GP_DBX_FIRST 0
1630 #define K0_REG_NUM (GP_REG_FIRST + 26)
1631 #define K1_REG_NUM (GP_REG_FIRST + 27)
1632 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1633
1634 #define FP_REG_FIRST 32
1635 #define FP_REG_LAST 63
1636 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1637 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1638
1639 #define MD_REG_FIRST 64
1640 #define MD_REG_LAST 65
1641 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1642 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1643
1644 /* The DWARF 2 CFA column which tracks the return address from a
1645 signal handler context. This means that to maintain backwards
1646 compatibility, no hard register can be assigned this column if it
1647 would need to be handled by the DWARF unwinder. */
1648 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1649
1650 #define ST_REG_FIRST 67
1651 #define ST_REG_LAST 74
1652 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1653
1654
1655 /* FIXME: renumber. */
1656 #define COP0_REG_FIRST 80
1657 #define COP0_REG_LAST 111
1658 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1659
1660 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1661 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1662 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1663
1664 #define COP2_REG_FIRST 112
1665 #define COP2_REG_LAST 143
1666 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1667
1668 #define COP3_REG_FIRST 144
1669 #define COP3_REG_LAST 175
1670 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1671 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1672 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1673
1674 #define DSP_ACC_REG_FIRST 176
1675 #define DSP_ACC_REG_LAST 181
1676 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1677
1678 #define AT_REGNUM (GP_REG_FIRST + 1)
1679 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1680 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1681
1682 /* A few bitfield locations for the coprocessor registers. */
1683 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1684 the cause register for the EIC interrupt mode. */
1685 #define CAUSE_IPL 10
1686 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1687 #define SR_IPL 10
1688 /* Exception Level is at bit 1 of the status register. */
1689 #define SR_EXL 1
1690 /* Interrupt Enable is at bit 0 of the status register. */
1691 #define SR_IE 0
1692
1693 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1694 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1695 should be used instead. */
1696 #define FPSW_REGNUM ST_REG_FIRST
1697
1698 #define GP_REG_P(REGNO) \
1699 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1700 #define M16_REG_P(REGNO) \
1701 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1702 #define FP_REG_P(REGNO) \
1703 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1704 #define MD_REG_P(REGNO) \
1705 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1706 #define ST_REG_P(REGNO) \
1707 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1708 #define COP0_REG_P(REGNO) \
1709 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1710 #define COP2_REG_P(REGNO) \
1711 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1712 #define COP3_REG_P(REGNO) \
1713 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1714 #define ALL_COP_REG_P(REGNO) \
1715 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1716 /* Test if REGNO is one of the 6 new DSP accumulators. */
1717 #define DSP_ACC_REG_P(REGNO) \
1718 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1719 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1720 #define ACC_REG_P(REGNO) \
1721 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1722
1723 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1724
1725 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1726 to initialize the mips16 gp pseudo register. */
1727 #define CONST_GP_P(X) \
1728 (GET_CODE (X) == CONST \
1729 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1730 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1731
1732 /* Return coprocessor number from register number. */
1733
1734 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1735 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1736 : COP3_REG_P (REGNO) ? '3' : '?')
1737
1738
1739 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1740
1741 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1742 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1743
1744 #define MODES_TIEABLE_P mips_modes_tieable_p
1745
1746 /* Register to use for pushing function arguments. */
1747 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1748
1749 /* These two registers don't really exist: they get eliminated to either
1750 the stack or hard frame pointer. */
1751 #define ARG_POINTER_REGNUM 77
1752 #define FRAME_POINTER_REGNUM 78
1753
1754 /* $30 is not available on the mips16, so we use $17 as the frame
1755 pointer. */
1756 #define HARD_FRAME_POINTER_REGNUM \
1757 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1758
1759 /* Register in which static-chain is passed to a function. */
1760 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1761
1762 /* Registers used as temporaries in prologue/epilogue code:
1763
1764 - If a MIPS16 PIC function needs access to _gp, it first loads
1765 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1766
1767 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1768 register. The register must not conflict with MIPS16_PIC_TEMP.
1769
1770 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1771 register.
1772
1773 If we're generating MIPS16 code, these registers must come from the
1774 core set of 8. The prologue registers mustn't conflict with any
1775 incoming arguments, the static chain pointer, or the frame pointer.
1776 The epilogue temporary mustn't conflict with the return registers,
1777 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1778 or the EH data registers.
1779
1780 If we're generating interrupt handlers, we use K0 as a temporary register
1781 in prologue/epilogue code. */
1782
1783 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1784 #define MIPS_PROLOGUE_TEMP_REGNUM \
1785 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1786 #define MIPS_EPILOGUE_TEMP_REGNUM \
1787 (cfun->machine->interrupt_handler_p \
1788 ? K0_REG_NUM \
1789 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1790
1791 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1792 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1793 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1794
1795 /* Define this macro if it is as good or better to call a constant
1796 function address than to call an address kept in a register. */
1797 #define NO_FUNCTION_CSE 1
1798
1799 /* The ABI-defined global pointer. Sometimes we use a different
1800 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1801 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1802
1803 /* We normally use $28 as the global pointer. However, when generating
1804 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1805 register instead. They can then avoid saving and restoring $28
1806 and perhaps avoid using a frame at all.
1807
1808 When a leaf function uses something other than $28, mips_expand_prologue
1809 will modify pic_offset_table_rtx in place. Take the register number
1810 from there after reload. */
1811 #define PIC_OFFSET_TABLE_REGNUM \
1812 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1813
1814 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1815 \f
1816 /* Define the classes of registers for register constraints in the
1817 machine description. Also define ranges of constants.
1818
1819 One of the classes must always be named ALL_REGS and include all hard regs.
1820 If there is more than one class, another class must be named NO_REGS
1821 and contain no registers.
1822
1823 The name GENERAL_REGS must be the name of a class (or an alias for
1824 another name such as ALL_REGS). This is the class of registers
1825 that is allowed by "g" or "r" in a register constraint.
1826 Also, registers outside this class are allocated only when
1827 instructions express preferences for them.
1828
1829 The classes must be numbered in nondecreasing order; that is,
1830 a larger-numbered class must never be contained completely
1831 in a smaller-numbered class.
1832
1833 For any two classes, it is very desirable that there be another
1834 class that represents their union. */
1835
1836 enum reg_class
1837 {
1838 NO_REGS, /* no registers in set */
1839 M16_REGS, /* mips16 directly accessible registers */
1840 T_REG, /* mips16 T register ($24) */
1841 M16_T_REGS, /* mips16 registers plus T register */
1842 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1843 V1_REG, /* Register $v1 ($3) used for TLS access. */
1844 LEA_REGS, /* Every GPR except $25 */
1845 GR_REGS, /* integer registers */
1846 FP_REGS, /* floating point registers */
1847 MD0_REG, /* first multiply/divide register */
1848 MD1_REG, /* second multiply/divide register */
1849 MD_REGS, /* multiply/divide registers (hi/lo) */
1850 COP0_REGS, /* generic coprocessor classes */
1851 COP2_REGS,
1852 COP3_REGS,
1853 ST_REGS, /* status registers (fp status) */
1854 DSP_ACC_REGS, /* DSP accumulator registers */
1855 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1856 FRAME_REGS, /* $arg and $frame */
1857 GR_AND_MD0_REGS, /* union classes */
1858 GR_AND_MD1_REGS,
1859 GR_AND_MD_REGS,
1860 GR_AND_ACC_REGS,
1861 ALL_REGS, /* all registers */
1862 LIM_REG_CLASSES /* max value + 1 */
1863 };
1864
1865 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1866
1867 #define GENERAL_REGS GR_REGS
1868
1869 /* An initializer containing the names of the register classes as C
1870 string constants. These names are used in writing some of the
1871 debugging dumps. */
1872
1873 #define REG_CLASS_NAMES \
1874 { \
1875 "NO_REGS", \
1876 "M16_REGS", \
1877 "T_REG", \
1878 "M16_T_REGS", \
1879 "PIC_FN_ADDR_REG", \
1880 "V1_REG", \
1881 "LEA_REGS", \
1882 "GR_REGS", \
1883 "FP_REGS", \
1884 "MD0_REG", \
1885 "MD1_REG", \
1886 "MD_REGS", \
1887 /* coprocessor registers */ \
1888 "COP0_REGS", \
1889 "COP2_REGS", \
1890 "COP3_REGS", \
1891 "ST_REGS", \
1892 "DSP_ACC_REGS", \
1893 "ACC_REGS", \
1894 "FRAME_REGS", \
1895 "GR_AND_MD0_REGS", \
1896 "GR_AND_MD1_REGS", \
1897 "GR_AND_MD_REGS", \
1898 "GR_AND_ACC_REGS", \
1899 "ALL_REGS" \
1900 }
1901
1902 /* An initializer containing the contents of the register classes,
1903 as integers which are bit masks. The Nth integer specifies the
1904 contents of class N. The way the integer MASK is interpreted is
1905 that register R is in the class if `MASK & (1 << R)' is 1.
1906
1907 When the machine has more than 32 registers, an integer does not
1908 suffice. Then the integers are replaced by sub-initializers,
1909 braced groupings containing several integers. Each
1910 sub-initializer must be suitable as an initializer for the type
1911 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1912
1913 #define REG_CLASS_CONTENTS \
1914 { \
1915 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1916 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1917 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1918 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1919 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1920 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1921 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1922 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1923 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1924 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1925 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1926 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1927 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1928 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1929 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1930 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1931 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1932 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1933 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1934 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1935 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1936 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1937 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1938 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1939 }
1940
1941
1942 /* A C expression whose value is a register class containing hard
1943 register REGNO. In general there is more that one such class;
1944 choose a class which is "minimal", meaning that no smaller class
1945 also contains the register. */
1946
1947 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1948
1949 /* A macro whose definition is the name of the class to which a
1950 valid base register must belong. A base register is one used in
1951 an address which is the register value plus a displacement. */
1952
1953 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1954
1955 /* A macro whose definition is the name of the class to which a
1956 valid index register must belong. An index register is one used
1957 in an address where its value is either multiplied by a scale
1958 factor or added to another register (as well as added to a
1959 displacement). */
1960
1961 #define INDEX_REG_CLASS NO_REGS
1962
1963 /* We generally want to put call-clobbered registers ahead of
1964 call-saved ones. (IRA expects this.) */
1965
1966 #define REG_ALLOC_ORDER \
1967 { /* Accumulator registers. When GPRs and accumulators have equal \
1968 cost, we generally prefer to use accumulators. For example, \
1969 a division of multiplication result is better allocated to LO, \
1970 so that we put the MFLO at the point of use instead of at the \
1971 point of definition. It's also needed if we're to take advantage \
1972 of the extra accumulators available with -mdspr2. In some cases, \
1973 it can also help to reduce register pressure. */ \
1974 64, 65,176,177,178,179,180,181, \
1975 /* Call-clobbered GPRs. */ \
1976 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1977 24, 25, 31, \
1978 /* The global pointer. This is call-clobbered for o32 and o64 \
1979 abicalls, call-saved for n32 and n64 abicalls, and a program \
1980 invariant otherwise. Putting it between the call-clobbered \
1981 and call-saved registers should cope with all eventualities. */ \
1982 28, \
1983 /* Call-saved GPRs. */ \
1984 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1985 /* GPRs that can never be exposed to the register allocator. */ \
1986 0, 26, 27, 29, \
1987 /* Call-clobbered FPRs. */ \
1988 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1989 48, 49, 50, 51, \
1990 /* FPRs that are usually call-saved. The odd ones are actually \
1991 call-clobbered for n32, but listing them ahead of the even \
1992 registers might encourage the register allocator to fragment \
1993 the available FPR pairs. We need paired FPRs to store long \
1994 doubles, so it isn't clear that using a different order \
1995 for n32 would be a win. */ \
1996 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1997 /* None of the remaining classes have defined call-saved \
1998 registers. */ \
1999 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2000 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2001 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2002 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2003 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2004 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2005 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2006 182,183,184,185,186,187 \
2007 }
2008
2009 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
2010 to be rearranged based on a particular function. On the mips16, we
2011 want to allocate $24 (T_REG) before other registers for
2012 instructions for which it is possible. */
2013
2014 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2015
2016 /* True if VALUE is an unsigned 6-bit number. */
2017
2018 #define UIMM6_OPERAND(VALUE) \
2019 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2020
2021 /* True if VALUE is a signed 10-bit number. */
2022
2023 #define IMM10_OPERAND(VALUE) \
2024 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2025
2026 /* True if VALUE is a signed 16-bit number. */
2027
2028 #define SMALL_OPERAND(VALUE) \
2029 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2030
2031 /* True if VALUE is an unsigned 16-bit number. */
2032
2033 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2034 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2035
2036 /* True if VALUE can be loaded into a register using LUI. */
2037
2038 #define LUI_OPERAND(VALUE) \
2039 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2040 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2041
2042 /* Return a value X with the low 16 bits clear, and such that
2043 VALUE - X is a signed 16-bit value. */
2044
2045 #define CONST_HIGH_PART(VALUE) \
2046 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2047
2048 #define CONST_LOW_PART(VALUE) \
2049 ((VALUE) - CONST_HIGH_PART (VALUE))
2050
2051 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2052 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2053 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2054
2055 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2056 mips_preferred_reload_class (X, CLASS)
2057
2058 /* The HI and LO registers can only be reloaded via the general
2059 registers. Condition code registers can only be loaded to the
2060 general registers, and from the floating point registers. */
2061
2062 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2063 mips_secondary_reload_class (CLASS, MODE, X, true)
2064 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2065 mips_secondary_reload_class (CLASS, MODE, X, false)
2066
2067 /* Return the maximum number of consecutive registers
2068 needed to represent mode MODE in a register of class CLASS. */
2069
2070 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2071
2072 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2073 mips_cannot_change_mode_class (FROM, TO, CLASS)
2074 \f
2075 /* Stack layout; function entry, exit and calling. */
2076
2077 #define STACK_GROWS_DOWNWARD
2078
2079 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2080
2081 /* Size of the area allocated in the frame to save the GP. */
2082
2083 #define MIPS_GP_SAVE_AREA_SIZE \
2084 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2085
2086 /* The offset of the first local variable from the frame pointer. See
2087 mips_compute_frame_info for details about the frame layout. */
2088
2089 #define STARTING_FRAME_OFFSET \
2090 (FRAME_GROWS_DOWNWARD \
2091 ? 0 \
2092 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2093
2094 #define RETURN_ADDR_RTX mips_return_addr
2095
2096 /* Mask off the MIPS16 ISA bit in unwind addresses.
2097
2098 The reason for this is a little subtle. When unwinding a call,
2099 we are given the call's return address, which on most targets
2100 is the address of the following instruction. However, what we
2101 actually want to find is the EH region for the call itself.
2102 The target-independent unwind code therefore searches for "RA - 1".
2103
2104 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2105 RA - 1 is therefore the real (even-valued) start of the return
2106 instruction. EH region labels are usually odd-valued MIPS16 symbols
2107 too, so a search for an even address within a MIPS16 region would
2108 usually work.
2109
2110 However, there is an exception. If the end of an EH region is also
2111 the end of a function, the end label is allowed to be even. This is
2112 necessary because a following non-MIPS16 function may also need EH
2113 information for its first instruction.
2114
2115 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2116 non-ISA-encoded address. This probably isn't ideal, but it is
2117 the traditional (legacy) behavior. It is therefore only safe
2118 to search MIPS EH regions for an _odd-valued_ address.
2119
2120 Masking off the ISA bit means that the target-independent code
2121 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2122 #define MASK_RETURN_ADDR GEN_INT (-2)
2123
2124
2125 /* Similarly, don't use the least-significant bit to tell pointers to
2126 code from vtable index. */
2127
2128 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2129
2130 /* The eliminations to $17 are only used for mips16 code. See the
2131 definition of HARD_FRAME_POINTER_REGNUM. */
2132
2133 #define ELIMINABLE_REGS \
2134 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2135 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2136 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2137 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2138 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2139 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2140
2141 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2142 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2143
2144 /* Allocate stack space for arguments at the beginning of each function. */
2145 #define ACCUMULATE_OUTGOING_ARGS 1
2146
2147 /* The argument pointer always points to the first argument. */
2148 #define FIRST_PARM_OFFSET(FNDECL) 0
2149
2150 /* o32 and o64 reserve stack space for all argument registers. */
2151 #define REG_PARM_STACK_SPACE(FNDECL) \
2152 (TARGET_OLDABI \
2153 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2154 : 0)
2155
2156 /* Define this if it is the responsibility of the caller to
2157 allocate the area reserved for arguments passed in registers.
2158 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2159 of this macro is to determine whether the space is included in
2160 `crtl->outgoing_args_size'. */
2161 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2162
2163 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2164 \f
2165 /* Symbolic macros for the registers used to return integer and floating
2166 point values. */
2167
2168 #define GP_RETURN (GP_REG_FIRST + 2)
2169 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2170
2171 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2172
2173 /* Symbolic macros for the first/last argument registers. */
2174
2175 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2176 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2177 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2178 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2179
2180 #define LIBCALL_VALUE(MODE) \
2181 mips_function_value (NULL_TREE, NULL_TREE, MODE)
2182
2183 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2184 mips_function_value (VALTYPE, FUNC, VOIDmode)
2185
2186 /* 1 if N is a possible register number for a function value.
2187 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2188 Currently, R2 and F0 are only implemented here (C has no complex type) */
2189
2190 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2191 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2192 && (N) == FP_RETURN + 2))
2193
2194 /* 1 if N is a possible register number for function argument passing.
2195 We have no FP argument registers when soft-float. When FP registers
2196 are 32 bits, we can't directly reference the odd numbered ones. */
2197
2198 #define FUNCTION_ARG_REGNO_P(N) \
2199 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2200 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2201 && !fixed_regs[N])
2202 \f
2203 /* This structure has to cope with two different argument allocation
2204 schemes. Most MIPS ABIs view the arguments as a structure, of which
2205 the first N words go in registers and the rest go on the stack. If I
2206 < N, the Ith word might go in Ith integer argument register or in a
2207 floating-point register. For these ABIs, we only need to remember
2208 the offset of the current argument into the structure.
2209
2210 The EABI instead allocates the integer and floating-point arguments
2211 separately. The first N words of FP arguments go in FP registers,
2212 the rest go on the stack. Likewise, the first N words of the other
2213 arguments go in integer registers, and the rest go on the stack. We
2214 need to maintain three counts: the number of integer registers used,
2215 the number of floating-point registers used, and the number of words
2216 passed on the stack.
2217
2218 We could keep separate information for the two ABIs (a word count for
2219 the standard ABIs, and three separate counts for the EABI). But it
2220 seems simpler to view the standard ABIs as forms of EABI that do not
2221 allocate floating-point registers.
2222
2223 So for the standard ABIs, the first N words are allocated to integer
2224 registers, and mips_function_arg decides on an argument-by-argument
2225 basis whether that argument should really go in an integer register,
2226 or in a floating-point one. */
2227
2228 typedef struct mips_args {
2229 /* Always true for varargs functions. Otherwise true if at least
2230 one argument has been passed in an integer register. */
2231 int gp_reg_found;
2232
2233 /* The number of arguments seen so far. */
2234 unsigned int arg_number;
2235
2236 /* The number of integer registers used so far. For all ABIs except
2237 EABI, this is the number of words that have been added to the
2238 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2239 unsigned int num_gprs;
2240
2241 /* For EABI, the number of floating-point registers used so far. */
2242 unsigned int num_fprs;
2243
2244 /* The number of words passed on the stack. */
2245 unsigned int stack_words;
2246
2247 /* On the mips16, we need to keep track of which floating point
2248 arguments were passed in general registers, but would have been
2249 passed in the FP regs if this were a 32-bit function, so that we
2250 can move them to the FP regs if we wind up calling a 32-bit
2251 function. We record this information in fp_code, encoded in base
2252 four. A zero digit means no floating point argument, a one digit
2253 means an SFmode argument, and a two digit means a DFmode argument,
2254 and a three digit is not used. The low order digit is the first
2255 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2256 an SFmode argument. ??? A more sophisticated approach will be
2257 needed if MIPS_ABI != ABI_32. */
2258 int fp_code;
2259
2260 /* True if the function has a prototype. */
2261 int prototype;
2262 } CUMULATIVE_ARGS;
2263
2264 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2265 for a call to a function whose data type is FNTYPE.
2266 For a library call, FNTYPE is 0. */
2267
2268 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2269 mips_init_cumulative_args (&CUM, FNTYPE)
2270
2271 /* Update the data in CUM to advance over an argument
2272 of mode MODE and data type TYPE.
2273 (TYPE is null for libcalls where that information may not be available.) */
2274
2275 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2276 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
2277
2278 /* Determine where to put an argument to a function.
2279 Value is zero to push the argument on the stack,
2280 or a hard register in which to store the argument.
2281
2282 MODE is the argument's machine mode.
2283 TYPE is the data type of the argument (as a tree).
2284 This is null for libcalls where that information may
2285 not be available.
2286 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2287 the preceding args and about the function being called.
2288 NAMED is nonzero if this argument is a named parameter
2289 (otherwise it is an extra parameter matching an ellipsis). */
2290
2291 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2292 mips_function_arg (&CUM, MODE, TYPE, NAMED)
2293
2294 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2295
2296 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2297 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2298
2299 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2300 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2301
2302 /* True if using EABI and varargs can be passed in floating-point
2303 registers. Under these conditions, we need a more complex form
2304 of va_list, which tracks GPR, FPR and stack arguments separately. */
2305 #define EABI_FLOAT_VARARGS_P \
2306 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2307
2308 \f
2309 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2310
2311 /* Treat LOC as a byte offset from the stack pointer and round it up
2312 to the next fully-aligned offset. */
2313 #define MIPS_STACK_ALIGN(LOC) \
2314 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2315
2316 \f
2317 /* Output assembler code to FILE to increment profiler label # LABELNO
2318 for profiling a function entry. */
2319
2320 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2321
2322 /* The profiler preserves all interesting registers, including $31. */
2323 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2324
2325 /* No mips port has ever used the profiler counter word, so don't emit it
2326 or the label for it. */
2327
2328 #define NO_PROFILE_COUNTERS 1
2329
2330 /* Define this macro if the code for function profiling should come
2331 before the function prologue. Normally, the profiling code comes
2332 after. */
2333
2334 /* #define PROFILE_BEFORE_PROLOGUE */
2335
2336 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2337 the stack pointer does not matter. The value is tested only in
2338 functions that have frame pointers.
2339 No definition is equivalent to always zero. */
2340
2341 #define EXIT_IGNORE_STACK 1
2342
2343 \f
2344 /* Trampolines are a block of code followed by two pointers. */
2345
2346 #define TRAMPOLINE_SIZE \
2347 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2348
2349 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2350 pointers from a single LUI base. */
2351
2352 #define TRAMPOLINE_ALIGNMENT 64
2353
2354 /* mips_trampoline_init calls this library function to flush
2355 program and data caches. */
2356
2357 #ifndef CACHE_FLUSH_FUNC
2358 #define CACHE_FLUSH_FUNC "_flush_cache"
2359 #endif
2360
2361 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2362 /* Flush both caches. We need to flush the data cache in case \
2363 the system has a write-back cache. */ \
2364 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2365 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2366 GEN_INT (3), TYPE_MODE (integer_type_node))
2367
2368 \f
2369 /* Addressing modes, and classification of registers for them. */
2370
2371 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2372 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2373 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2374
2375 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2376 and check its validity for a certain class.
2377 We have two alternate definitions for each of them.
2378 The usual definition accepts all pseudo regs; the other rejects them all.
2379 The symbol REG_OK_STRICT causes the latter definition to be used.
2380
2381 Most source files want to accept pseudo regs in the hope that
2382 they will get allocated to the class that the insn wants them to be in.
2383 Some source files that are used after register allocation
2384 need to be strict. */
2385
2386 #ifndef REG_OK_STRICT
2387 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2388 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2389 #else
2390 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2391 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2392 #endif
2393
2394 #define REG_OK_FOR_INDEX_P(X) 0
2395
2396 \f
2397 /* Maximum number of registers that can appear in a valid memory address. */
2398
2399 #define MAX_REGS_PER_ADDRESS 1
2400
2401 /* Check for constness inline but use mips_legitimate_address_p
2402 to check whether a constant really is an address. */
2403
2404 #define CONSTANT_ADDRESS_P(X) \
2405 (CONSTANT_P (X) && memory_address_p (SImode, X))
2406
2407 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2408
2409 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2410 'the start of the function that this code is output in'. */
2411
2412 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2413 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2414 asm_fprintf ((FILE), "%U%s", \
2415 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2416 else \
2417 asm_fprintf ((FILE), "%U%s", (NAME))
2418 \f
2419 /* Flag to mark a function decl symbol that requires a long call. */
2420 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2421 #define SYMBOL_REF_LONG_CALL_P(X) \
2422 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2423
2424 /* This flag marks functions that cannot be lazily bound. */
2425 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2426 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2427 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2428
2429 /* True if we're generating a form of MIPS16 code in which jump tables
2430 are stored in the text section and encoded as 16-bit PC-relative
2431 offsets. This is only possible when general text loads are allowed,
2432 since the table access itself will be an "lh" instruction. */
2433 /* ??? 16-bit offsets can overflow in large functions. */
2434 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2435
2436 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2437
2438 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2439
2440 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2441
2442 /* Define this as 1 if `char' should by default be signed; else as 0. */
2443 #ifndef DEFAULT_SIGNED_CHAR
2444 #define DEFAULT_SIGNED_CHAR 1
2445 #endif
2446
2447 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2448 we generally don't want to use them for copying arbitrary data.
2449 A single N-word move is usually the same cost as N single-word moves. */
2450 #define MOVE_MAX UNITS_PER_WORD
2451 #define MAX_MOVE_MAX 8
2452
2453 /* Define this macro as a C expression which is nonzero if
2454 accessing less than a word of memory (i.e. a `char' or a
2455 `short') is no faster than accessing a word of memory, i.e., if
2456 such access require more than one instruction or if there is no
2457 difference in cost between byte and (aligned) word loads.
2458
2459 On RISC machines, it tends to generate better code to define
2460 this as 1, since it avoids making a QI or HI mode register.
2461
2462 But, generating word accesses for -mips16 is generally bad as shifts
2463 (often extended) would be needed for byte accesses. */
2464 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2465
2466 /* Define this to be nonzero if shift instructions ignore all but the low-order
2467 few bits. */
2468 #define SHIFT_COUNT_TRUNCATED 1
2469
2470 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2471 is done just by pretending it is already truncated. */
2472 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2473 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2474
2475
2476 /* Specify the machine mode that pointers have.
2477 After generation of rtl, the compiler makes no further distinction
2478 between pointers and any other objects of this machine mode. */
2479
2480 #ifndef Pmode
2481 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2482 #endif
2483
2484 /* Give call MEMs SImode since it is the "most permissive" mode
2485 for both 32-bit and 64-bit targets. */
2486
2487 #define FUNCTION_MODE SImode
2488
2489 \f
2490 /* A C expression for the cost of moving data from a register in
2491 class FROM to one in class TO. The classes are expressed using
2492 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2493 the default; other values are interpreted relative to that.
2494
2495 It is not required that the cost always equal 2 when FROM is the
2496 same as TO; on some machines it is expensive to move between
2497 registers if they are not general registers.
2498
2499 If reload sees an insn consisting of a single `set' between two
2500 hard registers, and if `REGISTER_MOVE_COST' applied to their
2501 classes returns a value of 2, reload does not check to ensure
2502 that the constraints of the insn are met. Setting a cost of
2503 other than 2 will allow reload to verify that the constraints are
2504 met. You should do this if the `movM' pattern's constraints do
2505 not allow such copying. */
2506
2507 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2508 mips_register_move_cost (MODE, FROM, TO)
2509
2510 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2511 (mips_cost->memory_latency \
2512 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2513
2514 /* Define if copies to/from condition code registers should be avoided.
2515
2516 This is needed for the MIPS because reload_outcc is not complete;
2517 it needs to handle cases where the source is a general or another
2518 condition code register. */
2519 #define AVOID_CCMODE_COPIES
2520
2521 /* A C expression for the cost of a branch instruction. A value of
2522 1 is the default; other values are interpreted relative to that. */
2523
2524 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2525 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2526
2527 /* If defined, modifies the length assigned to instruction INSN as a
2528 function of the context in which it is used. LENGTH is an lvalue
2529 that contains the initially computed length of the insn and should
2530 be updated with the correct length of the insn. */
2531 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2532 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2533
2534 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2535 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2536 its operands. */
2537 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2538 "%*" OPCODE "%?\t" OPERANDS "%/"
2539
2540 /* Return an asm string that forces INSN to be treated as an absolute
2541 J or JAL instruction instead of an assembler macro. */
2542 #define MIPS_ABSOLUTE_JUMP(INSN) \
2543 (TARGET_ABICALLS_PIC2 \
2544 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2545 : INSN)
2546
2547 /* Return the asm template for a call. INSN is the instruction's mnemonic
2548 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2549 number of the target. SIZE_OPNO is the operand number of the argument size
2550 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2551 -1 and the call is indirect, use the function symbol from the call
2552 attributes to attach a R_MIPS_JALR relocation to the call.
2553
2554 When generating GOT code without explicit relocation operators,
2555 all calls should use assembly macros. Otherwise, all indirect
2556 calls should use "jr" or "jalr"; we will arrange to restore $gp
2557 afterwards if necessary. Finally, we can only generate direct
2558 calls for -mabicalls by temporarily switching to non-PIC mode. */
2559 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2560 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2561 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2562 : (REG_P (OPERANDS[TARGET_OPNO]) \
2563 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2564 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2565 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2566 : REG_P (OPERANDS[TARGET_OPNO]) \
2567 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2568 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2569 \f
2570 /* Control the assembler format that we output. */
2571
2572 /* Output to assembler file text saying following lines
2573 may contain character constants, extra white space, comments, etc. */
2574
2575 #ifndef ASM_APP_ON
2576 #define ASM_APP_ON " #APP\n"
2577 #endif
2578
2579 /* Output to assembler file text saying following lines
2580 no longer contain unusual constructs. */
2581
2582 #ifndef ASM_APP_OFF
2583 #define ASM_APP_OFF " #NO_APP\n"
2584 #endif
2585
2586 #define REGISTER_NAMES \
2587 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2588 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2589 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2590 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2591 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2592 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2593 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2594 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2595 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2596 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2597 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2598 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2599 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2600 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2601 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2602 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2603 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2604 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2605 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2606 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2607 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2608 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2609 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2610 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2611
2612 /* List the "software" names for each register. Also list the numerical
2613 names for $fp and $sp. */
2614
2615 #define ADDITIONAL_REGISTER_NAMES \
2616 { \
2617 { "$29", 29 + GP_REG_FIRST }, \
2618 { "$30", 30 + GP_REG_FIRST }, \
2619 { "at", 1 + GP_REG_FIRST }, \
2620 { "v0", 2 + GP_REG_FIRST }, \
2621 { "v1", 3 + GP_REG_FIRST }, \
2622 { "a0", 4 + GP_REG_FIRST }, \
2623 { "a1", 5 + GP_REG_FIRST }, \
2624 { "a2", 6 + GP_REG_FIRST }, \
2625 { "a3", 7 + GP_REG_FIRST }, \
2626 { "t0", 8 + GP_REG_FIRST }, \
2627 { "t1", 9 + GP_REG_FIRST }, \
2628 { "t2", 10 + GP_REG_FIRST }, \
2629 { "t3", 11 + GP_REG_FIRST }, \
2630 { "t4", 12 + GP_REG_FIRST }, \
2631 { "t5", 13 + GP_REG_FIRST }, \
2632 { "t6", 14 + GP_REG_FIRST }, \
2633 { "t7", 15 + GP_REG_FIRST }, \
2634 { "s0", 16 + GP_REG_FIRST }, \
2635 { "s1", 17 + GP_REG_FIRST }, \
2636 { "s2", 18 + GP_REG_FIRST }, \
2637 { "s3", 19 + GP_REG_FIRST }, \
2638 { "s4", 20 + GP_REG_FIRST }, \
2639 { "s5", 21 + GP_REG_FIRST }, \
2640 { "s6", 22 + GP_REG_FIRST }, \
2641 { "s7", 23 + GP_REG_FIRST }, \
2642 { "t8", 24 + GP_REG_FIRST }, \
2643 { "t9", 25 + GP_REG_FIRST }, \
2644 { "k0", 26 + GP_REG_FIRST }, \
2645 { "k1", 27 + GP_REG_FIRST }, \
2646 { "gp", 28 + GP_REG_FIRST }, \
2647 { "sp", 29 + GP_REG_FIRST }, \
2648 { "fp", 30 + GP_REG_FIRST }, \
2649 { "ra", 31 + GP_REG_FIRST }, \
2650 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2651 }
2652
2653 /* This is meant to be redefined in the host dependent files. It is a
2654 set of alternative names and regnums for mips coprocessors. */
2655
2656 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2657
2658 #define DBR_OUTPUT_SEQEND(STREAM) \
2659 do \
2660 { \
2661 /* Undo the effect of '%*'. */ \
2662 mips_pop_asm_switch (&mips_nomacro); \
2663 mips_pop_asm_switch (&mips_noreorder); \
2664 /* Emit a blank line after the delay slot for emphasis. */ \
2665 fputs ("\n", STREAM); \
2666 } \
2667 while (0)
2668
2669 /* How to tell the debugger about changes of source files. */
2670 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
2671
2672 /* mips-tfile does not understand .stabd directives. */
2673 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2674 dbxout_begin_stabn_sline (LINE); \
2675 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2676 } while (0)
2677
2678 /* Use .loc directives for SDB line numbers. */
2679 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2680 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2681
2682 /* The MIPS implementation uses some labels for its own purpose. The
2683 following lists what labels are created, and are all formed by the
2684 pattern $L[a-z].*. The machine independent portion of GCC creates
2685 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2686
2687 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2688 $Lb[0-9]+ Begin blocks for MIPS debug support
2689 $Lc[0-9]+ Label for use in s<xx> operation.
2690 $Le[0-9]+ End blocks for MIPS debug support */
2691
2692 #undef ASM_DECLARE_OBJECT_NAME
2693 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2694 mips_declare_object (STREAM, NAME, "", ":\n")
2695
2696 /* Globalizing directive for a label. */
2697 #define GLOBAL_ASM_OP "\t.globl\t"
2698
2699 /* This says how to define a global common symbol. */
2700
2701 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2702
2703 /* This says how to define a local common symbol (i.e., not visible to
2704 linker). */
2705
2706 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2707 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2708 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2709 #endif
2710
2711 /* This says how to output an external. It would be possible not to
2712 output anything and let undefined symbol become external. However
2713 the assembler uses length information on externals to allocate in
2714 data/sdata bss/sbss, thereby saving exec time. */
2715
2716 #undef ASM_OUTPUT_EXTERNAL
2717 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2718 mips_output_external(STREAM,DECL,NAME)
2719
2720 /* This is how to declare a function name. The actual work of
2721 emitting the label is moved to function_prologue, so that we can
2722 get the line number correctly emitted before the .ent directive,
2723 and after any .file directives. Define as empty so that the function
2724 is not declared before the .ent directive elsewhere. */
2725
2726 #undef ASM_DECLARE_FUNCTION_NAME
2727 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2728
2729 /* This is how to store into the string LABEL
2730 the symbol_ref name of an internal numbered label where
2731 PREFIX is the class of label and NUM is the number within the class.
2732 This is suitable for output with `assemble_name'. */
2733
2734 #undef ASM_GENERATE_INTERNAL_LABEL
2735 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2736 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2737
2738 /* Print debug labels as "foo = ." rather than "foo:" because they should
2739 represent a byte pointer rather than an ISA-encoded address. This is
2740 particularly important for code like:
2741
2742 $LFBxxx = .
2743 .cfi_startproc
2744 ...
2745 .section .gcc_except_table,...
2746 ...
2747 .uleb128 foo-$LFBxxx
2748
2749 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2750 likewise a byte pointer rather than an ISA-encoded address.
2751
2752 At the time of writing, this hook is not used for the function end
2753 label:
2754
2755 $LFExxx:
2756 .end foo
2757
2758 But this doesn't matter, because GAS doesn't treat a pre-.end label
2759 as a MIPS16 one anyway. */
2760
2761 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2762 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2763
2764 /* This is how to output an element of a case-vector that is absolute. */
2765
2766 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2767 fprintf (STREAM, "\t%s\t%sL%d\n", \
2768 ptr_mode == DImode ? ".dword" : ".word", \
2769 LOCAL_LABEL_PREFIX, \
2770 VALUE)
2771
2772 /* This is how to output an element of a case-vector. We can make the
2773 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2774 is supported. */
2775
2776 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2777 do { \
2778 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2779 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2780 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2781 else if (TARGET_GPWORD) \
2782 fprintf (STREAM, "\t%s\t%sL%d\n", \
2783 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2784 LOCAL_LABEL_PREFIX, VALUE); \
2785 else if (TARGET_RTP_PIC) \
2786 { \
2787 /* Make the entry relative to the start of the function. */ \
2788 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2789 fprintf (STREAM, "\t%s\t%sL%d-", \
2790 Pmode == DImode ? ".dword" : ".word", \
2791 LOCAL_LABEL_PREFIX, VALUE); \
2792 assemble_name (STREAM, XSTR (fnsym, 0)); \
2793 fprintf (STREAM, "\n"); \
2794 } \
2795 else \
2796 fprintf (STREAM, "\t%s\t%sL%d\n", \
2797 ptr_mode == DImode ? ".dword" : ".word", \
2798 LOCAL_LABEL_PREFIX, VALUE); \
2799 } while (0)
2800
2801 /* This is how to output an assembler line
2802 that says to advance the location counter
2803 to a multiple of 2**LOG bytes. */
2804
2805 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2806 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2807
2808 /* This is how to output an assembler line to advance the location
2809 counter by SIZE bytes. */
2810
2811 #undef ASM_OUTPUT_SKIP
2812 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2813 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2814
2815 /* This is how to output a string. */
2816 #undef ASM_OUTPUT_ASCII
2817 #define ASM_OUTPUT_ASCII mips_output_ascii
2818
2819 /* Output #ident as a in the read-only data section. */
2820 #undef ASM_OUTPUT_IDENT
2821 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2822 { \
2823 const char *p = STRING; \
2824 int size = strlen (p) + 1; \
2825 switch_to_section (readonly_data_section); \
2826 assemble_string (p, size); \
2827 }
2828 \f
2829 /* Default to -G 8 */
2830 #ifndef MIPS_DEFAULT_GVALUE
2831 #define MIPS_DEFAULT_GVALUE 8
2832 #endif
2833
2834 /* Define the strings to put out for each section in the object file. */
2835 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2836 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2837
2838 #undef READONLY_DATA_SECTION_ASM_OP
2839 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2840 \f
2841 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2842 do \
2843 { \
2844 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2845 TARGET_64BIT ? "daddiu" : "addiu", \
2846 reg_names[STACK_POINTER_REGNUM], \
2847 reg_names[STACK_POINTER_REGNUM], \
2848 TARGET_64BIT ? "sd" : "sw", \
2849 reg_names[REGNO], \
2850 reg_names[STACK_POINTER_REGNUM]); \
2851 } \
2852 while (0)
2853
2854 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2855 do \
2856 { \
2857 mips_push_asm_switch (&mips_noreorder); \
2858 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2859 TARGET_64BIT ? "ld" : "lw", \
2860 reg_names[REGNO], \
2861 reg_names[STACK_POINTER_REGNUM], \
2862 TARGET_64BIT ? "daddu" : "addu", \
2863 reg_names[STACK_POINTER_REGNUM], \
2864 reg_names[STACK_POINTER_REGNUM]); \
2865 mips_pop_asm_switch (&mips_noreorder); \
2866 } \
2867 while (0)
2868
2869 /* How to start an assembler comment.
2870 The leading space is important (the mips native assembler requires it). */
2871 #ifndef ASM_COMMENT_START
2872 #define ASM_COMMENT_START " #"
2873 #endif
2874 \f
2875 /* Default definitions for size_t and ptrdiff_t. We must override the
2876 definitions from ../svr4.h on mips-*-linux-gnu. */
2877
2878 #undef SIZE_TYPE
2879 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2880
2881 #undef PTRDIFF_TYPE
2882 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2883
2884 /* The maximum number of bytes that can be copied by one iteration of
2885 a movmemsi loop; see mips_block_move_loop. */
2886 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2887 (UNITS_PER_WORD * 4)
2888
2889 /* The maximum number of bytes that can be copied by a straight-line
2890 implementation of movmemsi; see mips_block_move_straight. We want
2891 to make sure that any loop-based implementation will iterate at
2892 least twice. */
2893 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2894 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2895
2896 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2897 values were determined experimentally by benchmarking with CSiBE.
2898 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2899 for o32 where we have to restore $gp afterwards as well as make an
2900 indirect call), but in practice, bumping this up higher for
2901 TARGET_ABICALLS doesn't make much difference to code size. */
2902
2903 #define MIPS_CALL_RATIO 8
2904
2905 /* Any loop-based implementation of movmemsi will have at least
2906 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2907 moves, so allow individual copies of fewer elements.
2908
2909 When movmemsi is not available, use a value approximating
2910 the length of a memcpy call sequence, so that move_by_pieces
2911 will generate inline code if it is shorter than a function call.
2912 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2913 we'll have to generate a load/store pair for each, halve the
2914 value of MIPS_CALL_RATIO to take that into account. */
2915
2916 #define MOVE_RATIO(speed) \
2917 (HAVE_movmemsi \
2918 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2919 : MIPS_CALL_RATIO / 2)
2920
2921 /* movmemsi is meant to generate code that is at least as good as
2922 move_by_pieces. However, movmemsi effectively uses a by-pieces
2923 implementation both for moves smaller than a word and for word-aligned
2924 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
2925 allow the tree-level optimisers to do such moves by pieces, as it
2926 often exposes other optimization opportunities. We might as well
2927 continue to use movmemsi at the rtl level though, as it produces
2928 better code when scheduling is disabled (such as at -O). */
2929
2930 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2931 (HAVE_movmemsi \
2932 ? (!currently_expanding_to_rtl \
2933 && ((ALIGN) < BITS_PER_WORD \
2934 ? (SIZE) < UNITS_PER_WORD \
2935 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
2936 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2937 < (unsigned int) MOVE_RATIO (false)))
2938
2939 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2940 of the length of a memset call, but use the default otherwise. */
2941
2942 #define CLEAR_RATIO(speed)\
2943 ((speed) ? 15 : MIPS_CALL_RATIO)
2944
2945 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2946 optimizing for size adjust the ratio to account for the overhead of
2947 loading the constant and replicating it across the word. */
2948
2949 #define SET_RATIO(speed) \
2950 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2951
2952 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2953 in that case each word takes 3 insns (lui, ori, sw), or more in
2954 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2955 and let the move_by_pieces code copy the string from read-only
2956 memory. In the future, this could be tuned further for multi-issue
2957 CPUs that can issue stores down one pipe and arithmetic instructions
2958 down another; in that case, the lui/ori/sw combination would be a
2959 win for long enough strings. */
2960
2961 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2962 \f
2963 #ifndef __mips16
2964 /* Since the bits of the _init and _fini function is spread across
2965 many object files, each potentially with its own GP, we must assume
2966 we need to load our GP. We don't preserve $gp or $ra, since each
2967 init/fini chunk is supposed to initialize $gp, and crti/crtn
2968 already take care of preserving $ra and, when appropriate, $gp. */
2969 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2970 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2971 asm (SECTION_OP "\n\
2972 .set noreorder\n\
2973 bal 1f\n\
2974 nop\n\
2975 1: .cpload $31\n\
2976 .set reorder\n\
2977 jal " USER_LABEL_PREFIX #FUNC "\n\
2978 " TEXT_SECTION_ASM_OP);
2979 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2980 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2981 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2982 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2983 asm (SECTION_OP "\n\
2984 .set noreorder\n\
2985 bal 1f\n\
2986 nop\n\
2987 1: .set reorder\n\
2988 .cpsetup $31, $2, 1b\n\
2989 jal " USER_LABEL_PREFIX #FUNC "\n\
2990 " TEXT_SECTION_ASM_OP);
2991 #endif
2992 #endif
2993
2994 #ifndef HAVE_AS_TLS
2995 #define HAVE_AS_TLS 0
2996 #endif
2997
2998 #ifndef USED_FOR_TARGET
2999 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3000 struct mips_asm_switch {
3001 /* The FOO in the description above. */
3002 const char *name;
3003
3004 /* The current block nesting level, or 0 if we aren't in a block. */
3005 int nesting_level;
3006 };
3007
3008 extern const enum reg_class mips_regno_to_class[];
3009 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3010 extern const char *current_function_file; /* filename current function is in */
3011 extern int num_source_filenames; /* current .file # */
3012 extern struct mips_asm_switch mips_noreorder;
3013 extern struct mips_asm_switch mips_nomacro;
3014 extern struct mips_asm_switch mips_noat;
3015 extern int mips_dbx_regno[];
3016 extern int mips_dwarf_regno[];
3017 extern bool mips_split_p[];
3018 extern bool mips_split_hi_p[];
3019 extern enum processor mips_arch; /* which cpu to codegen for */
3020 extern enum processor mips_tune; /* which cpu to schedule for */
3021 extern int mips_isa; /* architectural level */
3022 extern int mips_abi; /* which ABI to use */
3023 extern const struct mips_cpu_info *mips_arch_info;
3024 extern const struct mips_cpu_info *mips_tune_info;
3025 extern const struct mips_rtx_cost_data *mips_cost;
3026 extern bool mips_base_mips16;
3027 extern enum mips_code_readable_setting mips_code_readable;
3028 #endif
3029
3030 /* Enable querying of DFA units. */
3031 #define CPU_UNITS_QUERY 1
3032
3033 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3034 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3035
3036 /* As on most targets, we want the .eh_frame section to be read-only where
3037 possible. And as on most targets, this means two things:
3038
3039 (a) Non-locally-binding pointers must have an indirect encoding,
3040 so that the addresses in the .eh_frame section itself become
3041 locally-binding.
3042
3043 (b) A shared library's .eh_frame section must encode locally-binding
3044 pointers in a relative (relocation-free) form.
3045
3046 However, MIPS has traditionally not allowed directives like:
3047
3048 .long x-.
3049
3050 in cases where "x" is in a different section, or is not defined in the
3051 same assembly file. We are therefore unable to emit the PC-relative
3052 form required by (b) at assembly time.
3053
3054 Fortunately, the linker is able to convert absolute addresses into
3055 PC-relative addresses on our behalf. Unfortunately, only certain
3056 versions of the linker know how to do this for indirect pointers,
3057 and for personality data. We must fall back on using writable
3058 .eh_frame sections for shared libraries if the linker does not
3059 support this feature. */
3060 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3061 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)