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re PR middle-end/33190 (tm.texi describes some non-existing hooks)
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
4 2012
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky (lich@inria.inria.fr).
7 Changed by Michael Meissner (meissner@osf.org).
8 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
9 Brendan Eich (brendan@microunity.com).
10
11 This file is part of GCC.
12
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
16 any later version.
17
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
26
27
28 #include "config/vxworks-dummy.h"
29
30 #ifdef GENERATOR_FILE
31 /* This is used in some insn conditions, so needs to be declared, but
32 does not need to be defined. */
33 extern int target_flags_explicit;
34 #endif
35
36 /* MIPS external variables defined in mips.c. */
37
38 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
39 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
40 to work on a 64-bit machine. */
41
42 #define ABI_32 0
43 #define ABI_N32 1
44 #define ABI_64 2
45 #define ABI_EABI 3
46 #define ABI_O64 4
47
48 /* Masks that affect tuning.
49
50 PTF_AVOID_BRANCHLIKELY
51 Set if it is usually not profitable to use branch-likely instructions
52 for this target, typically because the branches are always predicted
53 taken and so incur a large overhead when not taken. */
54 #define PTF_AVOID_BRANCHLIKELY 0x1
55
56 /* Information about one recognized processor. Defined here for the
57 benefit of TARGET_CPU_CPP_BUILTINS. */
58 struct mips_cpu_info {
59 /* The 'canonical' name of the processor as far as GCC is concerned.
60 It's typically a manufacturer's prefix followed by a numerical
61 designation. It should be lowercase. */
62 const char *name;
63
64 /* The internal processor number that most closely matches this
65 entry. Several processors can have the same value, if there's no
66 difference between them from GCC's point of view. */
67 enum processor cpu;
68
69 /* The ISA level that the processor implements. */
70 int isa;
71
72 /* A mask of PTF_* values. */
73 unsigned int tune_flags;
74 };
75
76 #include "config/mips/mips-opts.h"
77
78 /* Macros to silence warnings about numbers being signed in traditional
79 C and unsigned in ISO C when compiled on 32-bit hosts. */
80
81 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
82 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
83 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
84
85 \f
86 /* Run-time compilation parameters selecting different hardware subsets. */
87
88 /* True if we are generating position-independent VxWorks RTP code. */
89 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
90
91 /* True if the output file is marked as ".abicalls; .option pic0"
92 (-call_nonpic). */
93 #define TARGET_ABICALLS_PIC0 \
94 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
95
96 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
97 #define TARGET_ABICALLS_PIC2 \
98 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
99
100 /* True if the call patterns should be split into a jalr followed by
101 an instruction to restore $gp. It is only safe to split the load
102 from the call when every use of $gp is explicit.
103
104 See mips_must_initialize_gp_p for details about how we manage the
105 global pointer. */
106
107 #define TARGET_SPLIT_CALLS \
108 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
109
110 /* True if we're generating a form of -mabicalls in which we can use
111 operators like %hi and %lo to refer to locally-binding symbols.
112 We can only do this for -mno-shared, and only then if we can use
113 relocation operations instead of assembly macros. It isn't really
114 worth using absolute sequences for 64-bit symbols because GOT
115 accesses are so much shorter. */
116
117 #define TARGET_ABSOLUTE_ABICALLS \
118 (TARGET_ABICALLS \
119 && !TARGET_SHARED \
120 && TARGET_EXPLICIT_RELOCS \
121 && !ABI_HAS_64BIT_SYMBOLS)
122
123 /* True if we can optimize sibling calls. For simplicity, we only
124 handle cases in which call_insn_operand will reject invalid
125 sibcall addresses. There are two cases in which this isn't true:
126
127 - TARGET_MIPS16. call_insn_operand accepts constant addresses
128 but there is no direct jump instruction. It isn't worth
129 using sibling calls in this case anyway; they would usually
130 be longer than normal calls.
131
132 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
133 accepts global constants, but all sibcalls must be indirect. */
134 #define TARGET_SIBCALLS \
135 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
136
137 /* True if we need to use a global offset table to access some symbols. */
138 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
139
140 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
141 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
142
143 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
144 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
145
146 /* True if we should use .cprestore to store to the cprestore slot.
147
148 We continue to use .cprestore for explicit-reloc code so that JALs
149 inside inline asms will work correctly. */
150 #define TARGET_CPRESTORE_DIRECTIVE \
151 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
152
153 /* True if we can use the J and JAL instructions. */
154 #define TARGET_ABSOLUTE_JUMPS \
155 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
156
157 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
158 This is true for both the PIC and non-PIC VxWorks RTP modes. */
159 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
160
161 /* True if .gpword or .gpdword should be used for switch tables. */
162 #define TARGET_GPWORD \
163 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
164
165 /* True if the output must have a writable .eh_frame.
166 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
167 #ifdef HAVE_LD_PERSONALITY_RELAXATION
168 #define TARGET_WRITABLE_EH_FRAME 0
169 #else
170 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
171 #endif
172
173 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
174 #ifdef HAVE_AS_DSPR1_MULT
175 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
176 #else
177 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
178 #endif
179
180 /* Generate mips16 code */
181 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
182 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
183 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
184 /* Generate mips16e register save/restore sequences. */
185 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
186
187 /* True if we're generating a form of MIPS16 code in which general
188 text loads are allowed. */
189 #define TARGET_MIPS16_TEXT_LOADS \
190 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
191
192 /* True if we're generating a form of MIPS16 code in which PC-relative
193 loads are allowed. */
194 #define TARGET_MIPS16_PCREL_LOADS \
195 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
196
197 /* Generic ISA defines. */
198 #define ISA_MIPS1 (mips_isa == 1)
199 #define ISA_MIPS2 (mips_isa == 2)
200 #define ISA_MIPS3 (mips_isa == 3)
201 #define ISA_MIPS4 (mips_isa == 4)
202 #define ISA_MIPS32 (mips_isa == 32)
203 #define ISA_MIPS32R2 (mips_isa == 33)
204 #define ISA_MIPS64 (mips_isa == 64)
205 #define ISA_MIPS64R2 (mips_isa == 65)
206
207 /* Architecture target defines. */
208 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
209 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
210 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
211 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
212 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
213 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
214 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
215 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
216 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
217 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
218 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
219 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
220 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
221 || mips_arch == PROCESSOR_OCTEON2)
222 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
223 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
224 || mips_arch == PROCESSOR_SB1A)
225 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
226 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
227
228 /* Scheduling target defines. */
229 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
230 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
231 || mips_tune == PROCESSOR_24KF2_1 \
232 || mips_tune == PROCESSOR_24KF1_1)
233 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
234 || mips_tune == PROCESSOR_74KF2_1 \
235 || mips_tune == PROCESSOR_74KF1_1 \
236 || mips_tune == PROCESSOR_74KF3_2)
237 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
238 || mips_tune == PROCESSOR_LOONGSON_2F)
239 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
240 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
241 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
242 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
243 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
244 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
245 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
246 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
247 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
248 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
249 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
250 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
251 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
252 || mips_tune == PROCESSOR_OCTEON2)
253 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
254 || mips_tune == PROCESSOR_SB1A)
255
256 /* Whether vector modes and intrinsics for ST Microelectronics
257 Loongson-2E/2F processors should be enabled. In o32 pairs of
258 floating-point registers provide 64-bit values. */
259 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
260 && (TARGET_LOONGSON_2EF \
261 || TARGET_LOONGSON_3A))
262
263 /* True if the pre-reload scheduler should try to create chains of
264 multiply-add or multiply-subtract instructions. For example,
265 suppose we have:
266
267 t1 = a * b
268 t2 = t1 + c * d
269 t3 = e * f
270 t4 = t3 - g * h
271
272 t1 will have a higher priority than t2 and t3 will have a higher
273 priority than t4. However, before reload, there is no dependence
274 between t1 and t3, and they can often have similar priorities.
275 The scheduler will then tend to prefer:
276
277 t1 = a * b
278 t3 = e * f
279 t2 = t1 + c * d
280 t4 = t3 - g * h
281
282 which stops us from making full use of macc/madd-style instructions.
283 This sort of situation occurs frequently in Fourier transforms and
284 in unrolled loops.
285
286 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
287 queue so that chained multiply-add and multiply-subtract instructions
288 appear ahead of any other instruction that is likely to clobber lo.
289 In the example above, if t2 and t3 become ready at the same time,
290 the code ensures that t2 is scheduled first.
291
292 Multiply-accumulate instructions are a bigger win for some targets
293 than others, so this macro is defined on an opt-in basis. */
294 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
295 || TUNE_MIPS4120 \
296 || TUNE_MIPS4130 \
297 || TUNE_24K)
298
299 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
300 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
301
302 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
303 directly accessible, while the command-line options select
304 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
305 in use. */
306 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
307 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
308
309 /* False if SC acts as a memory barrier with respect to itself,
310 otherwise a SYNC will be emitted after SC for atomic operations
311 that require ordering between the SC and following loads and
312 stores. It does not tell anything about ordering of loads and
313 stores prior to and following the SC, only about the SC itself and
314 those loads and stores follow it. */
315 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
316
317 /* Define preprocessor macros for the -march and -mtune options.
318 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
319 processor. If INFO's canonical name is "foo", define PREFIX to
320 be "foo", and define an additional macro PREFIX_FOO. */
321 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
322 do \
323 { \
324 char *macro, *p; \
325 \
326 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
327 for (p = macro; *p != 0; p++) \
328 if (*p == '+') \
329 *p = 'P'; \
330 else \
331 *p = TOUPPER (*p); \
332 \
333 builtin_define (macro); \
334 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
335 free (macro); \
336 } \
337 while (0)
338
339 /* Target CPU builtins. */
340 #define TARGET_CPU_CPP_BUILTINS() \
341 do \
342 { \
343 builtin_assert ("machine=mips"); \
344 builtin_assert ("cpu=mips"); \
345 builtin_define ("__mips__"); \
346 builtin_define ("_mips"); \
347 \
348 /* We do this here because __mips is defined below and so we \
349 can't use builtin_define_std. We don't ever want to define \
350 "mips" for VxWorks because some of the VxWorks headers \
351 construct include filenames from a root directory macro, \
352 an architecture macro and a filename, where the architecture \
353 macro expands to 'mips'. If we define 'mips' to 1, the \
354 architecture macro expands to 1 as well. */ \
355 if (!flag_iso && !TARGET_VXWORKS) \
356 builtin_define ("mips"); \
357 \
358 if (TARGET_64BIT) \
359 builtin_define ("__mips64"); \
360 \
361 /* Treat _R3000 and _R4000 like register-size \
362 defines, which is how they've historically \
363 been used. */ \
364 if (TARGET_64BIT) \
365 { \
366 builtin_define_std ("R4000"); \
367 builtin_define ("_R4000"); \
368 } \
369 else \
370 { \
371 builtin_define_std ("R3000"); \
372 builtin_define ("_R3000"); \
373 } \
374 \
375 if (TARGET_FLOAT64) \
376 builtin_define ("__mips_fpr=64"); \
377 else \
378 builtin_define ("__mips_fpr=32"); \
379 \
380 if (mips_base_mips16) \
381 builtin_define ("__mips16"); \
382 \
383 if (TARGET_MIPS3D) \
384 builtin_define ("__mips3d"); \
385 \
386 if (TARGET_SMARTMIPS) \
387 builtin_define ("__mips_smartmips"); \
388 \
389 if (TARGET_DSP) \
390 { \
391 builtin_define ("__mips_dsp"); \
392 if (TARGET_DSPR2) \
393 { \
394 builtin_define ("__mips_dspr2"); \
395 builtin_define ("__mips_dsp_rev=2"); \
396 } \
397 else \
398 builtin_define ("__mips_dsp_rev=1"); \
399 } \
400 \
401 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
402 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
403 \
404 if (ISA_MIPS1) \
405 { \
406 builtin_define ("__mips=1"); \
407 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
408 } \
409 else if (ISA_MIPS2) \
410 { \
411 builtin_define ("__mips=2"); \
412 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
413 } \
414 else if (ISA_MIPS3) \
415 { \
416 builtin_define ("__mips=3"); \
417 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
418 } \
419 else if (ISA_MIPS4) \
420 { \
421 builtin_define ("__mips=4"); \
422 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
423 } \
424 else if (ISA_MIPS32) \
425 { \
426 builtin_define ("__mips=32"); \
427 builtin_define ("__mips_isa_rev=1"); \
428 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
429 } \
430 else if (ISA_MIPS32R2) \
431 { \
432 builtin_define ("__mips=32"); \
433 builtin_define ("__mips_isa_rev=2"); \
434 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
435 } \
436 else if (ISA_MIPS64) \
437 { \
438 builtin_define ("__mips=64"); \
439 builtin_define ("__mips_isa_rev=1"); \
440 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
441 } \
442 else if (ISA_MIPS64R2) \
443 { \
444 builtin_define ("__mips=64"); \
445 builtin_define ("__mips_isa_rev=2"); \
446 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
447 } \
448 \
449 switch (mips_abi) \
450 { \
451 case ABI_32: \
452 builtin_define ("_ABIO32=1"); \
453 builtin_define ("_MIPS_SIM=_ABIO32"); \
454 break; \
455 \
456 case ABI_N32: \
457 builtin_define ("_ABIN32=2"); \
458 builtin_define ("_MIPS_SIM=_ABIN32"); \
459 break; \
460 \
461 case ABI_64: \
462 builtin_define ("_ABI64=3"); \
463 builtin_define ("_MIPS_SIM=_ABI64"); \
464 break; \
465 \
466 case ABI_O64: \
467 builtin_define ("_ABIO64=4"); \
468 builtin_define ("_MIPS_SIM=_ABIO64"); \
469 break; \
470 } \
471 \
472 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
473 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
474 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
475 builtin_define_with_int_value ("_MIPS_FPSET", \
476 32 / MAX_FPRS_PER_FMT); \
477 \
478 /* These defines reflect the ABI in use, not whether the \
479 FPU is directly accessible. */ \
480 if (TARGET_NO_FLOAT) \
481 builtin_define ("__mips_no_float"); \
482 else if (TARGET_HARD_FLOAT_ABI) \
483 builtin_define ("__mips_hard_float"); \
484 else \
485 builtin_define ("__mips_soft_float"); \
486 \
487 if (TARGET_SINGLE_FLOAT) \
488 builtin_define ("__mips_single_float"); \
489 \
490 if (TARGET_PAIRED_SINGLE_FLOAT) \
491 builtin_define ("__mips_paired_single_float"); \
492 \
493 if (TARGET_BIG_ENDIAN) \
494 { \
495 builtin_define_std ("MIPSEB"); \
496 builtin_define ("_MIPSEB"); \
497 } \
498 else \
499 { \
500 builtin_define_std ("MIPSEL"); \
501 builtin_define ("_MIPSEL"); \
502 } \
503 \
504 /* Whether calls should go through $25. The separate __PIC__ \
505 macro indicates whether abicalls code might use a GOT. */ \
506 if (TARGET_ABICALLS) \
507 builtin_define ("__mips_abicalls"); \
508 \
509 /* Whether Loongson vector modes are enabled. */ \
510 if (TARGET_LOONGSON_VECTORS) \
511 builtin_define ("__mips_loongson_vector_rev"); \
512 \
513 /* Historical Octeon macro. */ \
514 if (TARGET_OCTEON) \
515 builtin_define ("__OCTEON__"); \
516 \
517 /* Macros dependent on the C dialect. */ \
518 if (preprocessing_asm_p ()) \
519 { \
520 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
521 builtin_define ("_LANGUAGE_ASSEMBLY"); \
522 } \
523 else if (c_dialect_cxx ()) \
524 { \
525 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
526 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
527 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
528 } \
529 else \
530 { \
531 builtin_define_std ("LANGUAGE_C"); \
532 builtin_define ("_LANGUAGE_C"); \
533 } \
534 if (c_dialect_objc ()) \
535 { \
536 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
537 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
538 /* Bizarre, but retained for backwards compatibility. */ \
539 builtin_define_std ("LANGUAGE_C"); \
540 builtin_define ("_LANGUAGE_C"); \
541 } \
542 \
543 if (mips_abi == ABI_EABI) \
544 builtin_define ("__mips_eabi"); \
545 \
546 if (TARGET_CACHE_BUILTIN) \
547 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
548 } \
549 while (0)
550
551 /* Default target_flags if no switches are specified */
552
553 #ifndef TARGET_DEFAULT
554 #define TARGET_DEFAULT 0
555 #endif
556
557 #ifndef TARGET_CPU_DEFAULT
558 #define TARGET_CPU_DEFAULT 0
559 #endif
560
561 #ifndef TARGET_ENDIAN_DEFAULT
562 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
563 #endif
564
565 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
566 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
567 #endif
568
569 #ifdef IN_LIBGCC2
570 #undef TARGET_64BIT
571 /* Make this compile time constant for libgcc2 */
572 #ifdef __mips64
573 #define TARGET_64BIT 1
574 #else
575 #define TARGET_64BIT 0
576 #endif
577 #endif /* IN_LIBGCC2 */
578
579 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
580 when compiled with hardware floating point. This is because MIPS16
581 code cannot save and restore the floating-point registers, which is
582 important if in a mixed MIPS16/non-MIPS16 environment. */
583
584 #ifdef IN_LIBGCC2
585 #if __mips_hard_float
586 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
587 #endif
588 #endif /* IN_LIBGCC2 */
589
590 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
591
592 #ifndef MULTILIB_ENDIAN_DEFAULT
593 #if TARGET_ENDIAN_DEFAULT == 0
594 #define MULTILIB_ENDIAN_DEFAULT "EL"
595 #else
596 #define MULTILIB_ENDIAN_DEFAULT "EB"
597 #endif
598 #endif
599
600 #ifndef MULTILIB_ISA_DEFAULT
601 # if MIPS_ISA_DEFAULT == 1
602 # define MULTILIB_ISA_DEFAULT "mips1"
603 # else
604 # if MIPS_ISA_DEFAULT == 2
605 # define MULTILIB_ISA_DEFAULT "mips2"
606 # else
607 # if MIPS_ISA_DEFAULT == 3
608 # define MULTILIB_ISA_DEFAULT "mips3"
609 # else
610 # if MIPS_ISA_DEFAULT == 4
611 # define MULTILIB_ISA_DEFAULT "mips4"
612 # else
613 # if MIPS_ISA_DEFAULT == 32
614 # define MULTILIB_ISA_DEFAULT "mips32"
615 # else
616 # if MIPS_ISA_DEFAULT == 33
617 # define MULTILIB_ISA_DEFAULT "mips32r2"
618 # else
619 # if MIPS_ISA_DEFAULT == 64
620 # define MULTILIB_ISA_DEFAULT "mips64"
621 # else
622 # if MIPS_ISA_DEFAULT == 65
623 # define MULTILIB_ISA_DEFAULT "mips64r2"
624 # else
625 # define MULTILIB_ISA_DEFAULT "mips1"
626 # endif
627 # endif
628 # endif
629 # endif
630 # endif
631 # endif
632 # endif
633 # endif
634 #endif
635
636 #ifndef MIPS_ABI_DEFAULT
637 #define MIPS_ABI_DEFAULT ABI_32
638 #endif
639
640 /* Use the most portable ABI flag for the ASM specs. */
641
642 #if MIPS_ABI_DEFAULT == ABI_32
643 #define MULTILIB_ABI_DEFAULT "mabi=32"
644 #endif
645
646 #if MIPS_ABI_DEFAULT == ABI_O64
647 #define MULTILIB_ABI_DEFAULT "mabi=o64"
648 #endif
649
650 #if MIPS_ABI_DEFAULT == ABI_N32
651 #define MULTILIB_ABI_DEFAULT "mabi=n32"
652 #endif
653
654 #if MIPS_ABI_DEFAULT == ABI_64
655 #define MULTILIB_ABI_DEFAULT "mabi=64"
656 #endif
657
658 #if MIPS_ABI_DEFAULT == ABI_EABI
659 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
660 #endif
661
662 #ifndef MULTILIB_DEFAULTS
663 #define MULTILIB_DEFAULTS \
664 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
665 #endif
666
667 /* We must pass -EL to the linker by default for little endian embedded
668 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
669 linker will default to using big-endian output files. The OUTPUT_FORMAT
670 line must be in the linker script, otherwise -EB/-EL will not work. */
671
672 #ifndef ENDIAN_SPEC
673 #if TARGET_ENDIAN_DEFAULT == 0
674 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
675 #else
676 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
677 #endif
678 #endif
679
680 /* A spec condition that matches all non-mips16 -mips arguments. */
681
682 #define MIPS_ISA_LEVEL_OPTION_SPEC \
683 "mips1|mips2|mips3|mips4|mips32*|mips64*"
684
685 /* A spec condition that matches all non-mips16 architecture arguments. */
686
687 #define MIPS_ARCH_OPTION_SPEC \
688 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
689
690 /* A spec that infers a -mips argument from an -march argument,
691 or injects the default if no architecture is specified. */
692
693 #define MIPS_ISA_LEVEL_SPEC \
694 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
695 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
696 %{march=mips2|march=r6000:-mips2} \
697 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
698 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
699 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
700 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
701 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
702 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
703 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
704 |march=xlr|march=loongson3a: -mips64} \
705 %{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
706 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
707
708 /* A spec that infers a -mhard-float or -msoft-float setting from an
709 -march argument. Note that soft-float and hard-float code are not
710 link-compatible. */
711
712 #define MIPS_ARCH_FLOAT_SPEC \
713 "%{mhard-float|msoft-float|march=mips*:; \
714 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
715 |march=34kc|march=74kc|march=1004kc|march=5kc \
716 |march=octeon|march=xlr: -msoft-float; \
717 march=*: -mhard-float}"
718
719 /* A spec condition that matches 32-bit options. It only works if
720 MIPS_ISA_LEVEL_SPEC has been applied. */
721
722 #define MIPS_32BIT_OPTION_SPEC \
723 "mips1|mips2|mips32*|mgp32"
724
725 #if MIPS_ABI_DEFAULT == ABI_O64 \
726 || MIPS_ABI_DEFAULT == ABI_N32 \
727 || MIPS_ABI_DEFAULT == ABI_64
728 #define OPT_ARCH64 "mabi=32|mgp32:;"
729 #define OPT_ARCH32 "mabi=32|mgp32"
730 #else
731 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
732 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
733 #endif
734
735 /* Support for a compile-time default CPU, et cetera. The rules are:
736 --with-arch is ignored if -march is specified or a -mips is specified
737 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
738 --with-tune is ignored if -mtune is specified; likewise
739 --with-tune-32 and --with-tune-64.
740 --with-abi is ignored if -mabi is specified.
741 --with-float is ignored if -mhard-float or -msoft-float are
742 specified.
743 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
744 specified. */
745 #define OPTION_DEFAULT_SPECS \
746 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
747 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
748 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
749 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
750 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
751 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
752 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
753 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
754 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
755 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
756 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
757 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
758
759
760 /* A spec that infers the -mdsp setting from an -march argument. */
761 #define BASE_DRIVER_SELF_SPECS \
762 "%{!mno-dsp: \
763 %{march=24ke*|march=34k*|march=1004k*: -mdsp} \
764 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
765
766 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
767
768 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
769 && ISA_HAS_COND_TRAP)
770
771 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
772
773 /* True if the ABI can only work with 64-bit integer registers. We
774 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
775 otherwise floating-point registers must also be 64-bit. */
776 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
777
778 /* Likewise for 32-bit regs. */
779 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
780
781 /* True if the file format uses 64-bit symbols. At present, this is
782 only true for n64, which uses 64-bit ELF. */
783 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
784
785 /* True if symbols are 64 bits wide. This is usually determined by
786 the ABI's file format, but it can be overridden by -msym32. Note that
787 overriding the size with -msym32 changes the ABI of relocatable objects,
788 although it doesn't change the ABI of a fully-linked object. */
789 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
790 && Pmode == DImode \
791 && !TARGET_SYM32)
792
793 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
794 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
795 || ISA_MIPS4 \
796 || ISA_MIPS64 \
797 || ISA_MIPS64R2)
798
799 /* ISA has branch likely instructions (e.g. mips2). */
800 /* Disable branchlikely for tx39 until compare rewrite. They haven't
801 been generated up to this point. */
802 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
803
804 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
805 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
806 || TARGET_MIPS5400 \
807 || TARGET_MIPS5500 \
808 || TARGET_MIPS7000 \
809 || TARGET_MIPS9000 \
810 || TARGET_MAD \
811 || ISA_MIPS32 \
812 || ISA_MIPS32R2 \
813 || ISA_MIPS64 \
814 || ISA_MIPS64R2) \
815 && !TARGET_MIPS16)
816
817 /* ISA has a three-operand multiplication instruction. */
818 #define ISA_HAS_DMUL3 (TARGET_64BIT \
819 && TARGET_OCTEON \
820 && !TARGET_MIPS16)
821
822 /* ISA has the floating-point conditional move instructions introduced
823 in mips4. */
824 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
825 || ISA_MIPS32 \
826 || ISA_MIPS32R2 \
827 || ISA_MIPS64 \
828 || ISA_MIPS64R2) \
829 && !TARGET_MIPS5500 \
830 && !TARGET_MIPS16)
831
832 /* ISA has the integer conditional move instructions introduced in mips4 and
833 ST Loongson 2E/2F. */
834 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
835
836 /* ISA has LDC1 and SDC1. */
837 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
838
839 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
840 branch on CC, and move (both FP and non-FP) on CC. */
841 #define ISA_HAS_8CC (ISA_MIPS4 \
842 || ISA_MIPS32 \
843 || ISA_MIPS32R2 \
844 || ISA_MIPS64 \
845 || ISA_MIPS64R2)
846
847 /* This is a catch all for other mips4 instructions: indexed load, the
848 FP madd and msub instructions, and the FP recip and recip sqrt
849 instructions. */
850 #define ISA_HAS_FP4 ((ISA_MIPS4 \
851 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
852 || ISA_MIPS64 \
853 || ISA_MIPS64R2) \
854 && !TARGET_MIPS16)
855
856 /* ISA has paired-single instructions. */
857 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
858
859 /* ISA has conditional trap instructions. */
860 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
861 && !TARGET_MIPS16)
862
863 /* ISA has integer multiply-accumulate instructions, madd and msub. */
864 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
865 || ISA_MIPS32R2 \
866 || ISA_MIPS64 \
867 || ISA_MIPS64R2) \
868 && !TARGET_MIPS16)
869
870 /* Integer multiply-accumulate instructions should be generated. */
871 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
872
873 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
874 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
875
876 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
877 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
878
879 /* ISA has floating-point nmadd and nmsub instructions
880 'd = -((a * b) [+-] c)'. */
881 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
882 ((ISA_MIPS4 \
883 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
884 || ISA_MIPS64 \
885 || ISA_MIPS64R2) \
886 && (!TARGET_MIPS5400 || TARGET_MAD) \
887 && !TARGET_MIPS16)
888
889 /* ISA has floating-point nmadd and nmsub instructions
890 'c = -((a * b) [+-] c)'. */
891 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
892 TARGET_LOONGSON_2EF
893
894 /* ISA has count leading zeroes/ones instruction (not implemented). */
895 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
896 || ISA_MIPS32R2 \
897 || ISA_MIPS64 \
898 || ISA_MIPS64R2) \
899 && !TARGET_MIPS16)
900
901 /* ISA has three operand multiply instructions that put
902 the high part in an accumulator: mulhi or mulhiu. */
903 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
904 || TARGET_MIPS5500 \
905 || TARGET_SR71K) \
906 && !TARGET_MIPS16)
907
908 /* ISA has three operand multiply instructions that
909 negates the result and puts the result in an accumulator. */
910 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
911 || TARGET_MIPS5500 \
912 || TARGET_SR71K) \
913 && !TARGET_MIPS16)
914
915 /* ISA has three operand multiply instructions that subtracts the
916 result from a 4th operand and puts the result in an accumulator. */
917 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
918 || TARGET_MIPS5500 \
919 || TARGET_SR71K) \
920 && !TARGET_MIPS16)
921
922 /* ISA has three operand multiply instructions that the result
923 from a 4th operand and puts the result in an accumulator. */
924 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
925 || TARGET_MIPS4130 \
926 || TARGET_MIPS5400 \
927 || TARGET_MIPS5500 \
928 || TARGET_SR71K) \
929 && !TARGET_MIPS16)
930
931 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
932 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
933 || TARGET_MIPS4130) \
934 && !TARGET_MIPS16)
935
936 /* ISA has the "ror" (rotate right) instructions. */
937 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
938 || ISA_MIPS64R2 \
939 || TARGET_MIPS5400 \
940 || TARGET_MIPS5500 \
941 || TARGET_SR71K \
942 || TARGET_SMARTMIPS) \
943 && !TARGET_MIPS16)
944
945 /* ISA has data prefetch instructions. This controls use of 'pref'. */
946 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
947 || TARGET_LOONGSON_2EF \
948 || ISA_MIPS32 \
949 || ISA_MIPS32R2 \
950 || ISA_MIPS64 \
951 || ISA_MIPS64R2) \
952 && !TARGET_MIPS16)
953
954 /* ISA has data indexed prefetch instructions. This controls use of
955 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
956 (prefx is a cop1x instruction, so can only be used if FP is
957 enabled.) */
958 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
959 || ISA_MIPS32R2 \
960 || ISA_MIPS64 \
961 || ISA_MIPS64R2) \
962 && !TARGET_MIPS16)
963
964 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
965 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
966 also requires TARGET_DOUBLE_FLOAT. */
967 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
968
969 /* ISA includes the MIPS32r2 seb and seh instructions. */
970 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
971 || ISA_MIPS64R2) \
972 && !TARGET_MIPS16)
973
974 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
975 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
976 || ISA_MIPS64R2) \
977 && !TARGET_MIPS16)
978
979 /* ISA has instructions for accessing top part of 64-bit fp regs. */
980 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
981 && (ISA_MIPS32R2 \
982 || ISA_MIPS64R2))
983
984 /* ISA has lwxs instruction (load w/scaled index address. */
985 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
986
987 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
988 #define ISA_HAS_LBX (TARGET_OCTEON2)
989 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
990 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
991 #define ISA_HAS_LHUX (TARGET_OCTEON2)
992 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
993 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
994 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
995 && TARGET_64BIT)
996
997 /* The DSP ASE is available. */
998 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
999
1000 /* Revision 2 of the DSP ASE is available. */
1001 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1002
1003 /* True if the result of a load is not available to the next instruction.
1004 A nop will then be needed between instructions like "lw $4,..."
1005 and "addiu $4,$4,1". */
1006 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1007 && !TARGET_MIPS3900 \
1008 && !TARGET_MIPS16)
1009
1010 /* Likewise mtc1 and mfc1. */
1011 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1012 && !TARGET_LOONGSON_2EF)
1013
1014 /* Likewise floating-point comparisons. */
1015 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1016 && !TARGET_LOONGSON_2EF)
1017
1018 /* True if mflo and mfhi can be immediately followed by instructions
1019 which write to the HI and LO registers.
1020
1021 According to MIPS specifications, MIPS ISAs I, II, and III need
1022 (at least) two instructions between the reads of HI/LO and
1023 instructions which write them, and later ISAs do not. Contradicting
1024 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1025 the UM for the NEC Vr5000) document needing the instructions between
1026 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1027 MIPS64 and later ISAs to have the interlocks, plus any specific
1028 earlier-ISA CPUs for which CPU documentation declares that the
1029 instructions are really interlocked. */
1030 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1031 || ISA_MIPS32R2 \
1032 || ISA_MIPS64 \
1033 || ISA_MIPS64R2 \
1034 || TARGET_MIPS5500 \
1035 || TARGET_LOONGSON_2EF)
1036
1037 /* ISA includes synci, jr.hb and jalr.hb. */
1038 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1039 || ISA_MIPS64R2) \
1040 && !TARGET_MIPS16)
1041
1042 /* ISA includes sync. */
1043 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1044 #define GENERATE_SYNC \
1045 (target_flags_explicit & MASK_LLSC \
1046 ? TARGET_LLSC && !TARGET_MIPS16 \
1047 : ISA_HAS_SYNC)
1048
1049 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1050 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1051 instructions. */
1052 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1053 #define GENERATE_LL_SC \
1054 (target_flags_explicit & MASK_LLSC \
1055 ? TARGET_LLSC && !TARGET_MIPS16 \
1056 : ISA_HAS_LL_SC)
1057
1058 #define ISA_HAS_SWAP (TARGET_XLP)
1059 #define ISA_HAS_LDADD (TARGET_XLP)
1060
1061 /* ISA includes the baddu instruction. */
1062 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1063
1064 /* ISA includes the bbit* instructions. */
1065 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1066
1067 /* ISA includes the cins instruction. */
1068 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1069
1070 /* ISA includes the exts instruction. */
1071 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1072
1073 /* ISA includes the seq and sne instructions. */
1074 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1075
1076 /* ISA includes the pop instruction. */
1077 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1078
1079 /* The CACHE instruction is available in non-MIPS16 code. */
1080 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1081
1082 /* The CACHE instruction is available. */
1083 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1084 \f
1085 /* Tell collect what flags to pass to nm. */
1086 #ifndef NM_FLAGS
1087 #define NM_FLAGS "-Bn"
1088 #endif
1089
1090 \f
1091 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1092 the assembler. It may be overridden by subtargets.
1093
1094 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1095 COFF debugging info. */
1096
1097 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1098 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1099 %{g} %{g0} %{g1} %{g2} %{g3} \
1100 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1101 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1102 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1103 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1104 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1105 #endif
1106
1107 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1108 overridden by subtargets. */
1109
1110 #ifndef SUBTARGET_ASM_SPEC
1111 #define SUBTARGET_ASM_SPEC ""
1112 #endif
1113
1114 #undef ASM_SPEC
1115 #define ASM_SPEC "\
1116 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1117 %{mips32*} %{mips64*} \
1118 %{mips16} %{mno-mips16:-no-mips16} \
1119 %{mips3d} %{mno-mips3d:-no-mips3d} \
1120 %{mdmx} %{mno-mdmx:-no-mdmx} \
1121 %{mdsp} %{mno-dsp} \
1122 %{mdspr2} %{mno-dspr2} \
1123 %{msmartmips} %{mno-smartmips} \
1124 %{mmt} %{mno-mt} \
1125 %{mfix-vr4120} %{mfix-vr4130} \
1126 %{mfix-24k} \
1127 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1128 %(subtarget_asm_debugging_spec) \
1129 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1130 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1131 %{mfp32} %{mfp64} \
1132 %{mshared} %{mno-shared} \
1133 %{msym32} %{mno-sym32} \
1134 %{mtune=*} \
1135 %(subtarget_asm_spec)"
1136
1137 /* Extra switches sometimes passed to the linker. */
1138
1139 #ifndef LINK_SPEC
1140 #define LINK_SPEC "\
1141 %(endian_spec) \
1142 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1143 %{shared}"
1144 #endif /* LINK_SPEC defined */
1145
1146
1147 /* Specs for the compiler proper */
1148
1149 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1150 overridden by subtargets. */
1151 #ifndef SUBTARGET_CC1_SPEC
1152 #define SUBTARGET_CC1_SPEC ""
1153 #endif
1154
1155 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1156
1157 #undef CC1_SPEC
1158 #define CC1_SPEC "\
1159 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1160 %(subtarget_cc1_spec)"
1161
1162 /* Preprocessor specs. */
1163
1164 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1165 overridden by subtargets. */
1166 #ifndef SUBTARGET_CPP_SPEC
1167 #define SUBTARGET_CPP_SPEC ""
1168 #endif
1169
1170 #define CPP_SPEC "%(subtarget_cpp_spec)"
1171
1172 /* This macro defines names of additional specifications to put in the specs
1173 that can be used in various specifications like CC1_SPEC. Its definition
1174 is an initializer with a subgrouping for each command option.
1175
1176 Each subgrouping contains a string constant, that defines the
1177 specification name, and a string constant that used by the GCC driver
1178 program.
1179
1180 Do not define this macro if it does not need to do anything. */
1181
1182 #define EXTRA_SPECS \
1183 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1184 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1185 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1186 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1187 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1188 { "endian_spec", ENDIAN_SPEC }, \
1189 SUBTARGET_EXTRA_SPECS
1190
1191 #ifndef SUBTARGET_EXTRA_SPECS
1192 #define SUBTARGET_EXTRA_SPECS
1193 #endif
1194 \f
1195 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1196 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1197
1198 #ifndef PREFERRED_DEBUGGING_TYPE
1199 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1200 #endif
1201
1202 /* The size of DWARF addresses should be the same as the size of symbols
1203 in the target file format. They shouldn't depend on things like -msym32,
1204 because many DWARF consumers do not allow the mixture of address sizes
1205 that one would then get from linking -msym32 code with -msym64 code.
1206
1207 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1208 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1209 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1210
1211 /* By default, turn on GDB extensions. */
1212 #define DEFAULT_GDB_EXTENSIONS 1
1213
1214 /* Local compiler-generated symbols must have a prefix that the assembler
1215 understands. By default, this is $, although some targets (e.g.,
1216 NetBSD-ELF) need to override this. */
1217
1218 #ifndef LOCAL_LABEL_PREFIX
1219 #define LOCAL_LABEL_PREFIX "$"
1220 #endif
1221
1222 /* By default on the mips, external symbols do not have an underscore
1223 prepended, but some targets (e.g., NetBSD) require this. */
1224
1225 #ifndef USER_LABEL_PREFIX
1226 #define USER_LABEL_PREFIX ""
1227 #endif
1228
1229 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1230 since the length can run past this up to a continuation point. */
1231 #undef DBX_CONTIN_LENGTH
1232 #define DBX_CONTIN_LENGTH 1500
1233
1234 /* How to renumber registers for dbx and gdb. */
1235 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1236
1237 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1238 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1239
1240 /* The DWARF 2 CFA column which tracks the return address. */
1241 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1242
1243 /* Before the prologue, RA lives in r31. */
1244 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1245
1246 /* Describe how we implement __builtin_eh_return. */
1247 #define EH_RETURN_DATA_REGNO(N) \
1248 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1249
1250 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1251
1252 #define EH_USES(N) mips_eh_uses (N)
1253
1254 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1255 The default for this in 64-bit mode is 8, which causes problems with
1256 SFmode register saves. */
1257 #define DWARF_CIE_DATA_ALIGNMENT -4
1258
1259 /* Correct the offset of automatic variables and arguments. Note that
1260 the MIPS debug format wants all automatic variables and arguments
1261 to be in terms of the virtual frame pointer (stack pointer before
1262 any adjustment in the function), while the MIPS 3.0 linker wants
1263 the frame pointer to be the stack pointer after the initial
1264 adjustment. */
1265
1266 #define DEBUGGER_AUTO_OFFSET(X) \
1267 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1268 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1269 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1270 \f
1271 /* Target machine storage layout */
1272
1273 #define BITS_BIG_ENDIAN 0
1274 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1275 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1276
1277 #define MAX_BITS_PER_WORD 64
1278
1279 /* Width of a word, in units (bytes). */
1280 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1281 #ifndef IN_LIBGCC2
1282 #define MIN_UNITS_PER_WORD 4
1283 #endif
1284
1285 /* For MIPS, width of a floating point register. */
1286 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1287
1288 /* The number of consecutive floating-point registers needed to store the
1289 largest format supported by the FPU. */
1290 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1291
1292 /* The number of consecutive floating-point registers needed to store the
1293 smallest format supported by the FPU. */
1294 #define MIN_FPRS_PER_FMT \
1295 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1296 ? 1 : MAX_FPRS_PER_FMT)
1297
1298 /* The largest size of value that can be held in floating-point
1299 registers and moved with a single instruction. */
1300 #define UNITS_PER_HWFPVALUE \
1301 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1302
1303 /* The largest size of value that can be held in floating-point
1304 registers. */
1305 #define UNITS_PER_FPVALUE \
1306 (TARGET_SOFT_FLOAT_ABI ? 0 \
1307 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1308 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1309
1310 /* The number of bytes in a double. */
1311 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1312
1313 /* Set the sizes of the core types. */
1314 #define SHORT_TYPE_SIZE 16
1315 #define INT_TYPE_SIZE 32
1316 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1317 #define LONG_LONG_TYPE_SIZE 64
1318
1319 #define FLOAT_TYPE_SIZE 32
1320 #define DOUBLE_TYPE_SIZE 64
1321 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1322
1323 /* Define the sizes of fixed-point types. */
1324 #define SHORT_FRACT_TYPE_SIZE 8
1325 #define FRACT_TYPE_SIZE 16
1326 #define LONG_FRACT_TYPE_SIZE 32
1327 #define LONG_LONG_FRACT_TYPE_SIZE 64
1328
1329 #define SHORT_ACCUM_TYPE_SIZE 16
1330 #define ACCUM_TYPE_SIZE 32
1331 #define LONG_ACCUM_TYPE_SIZE 64
1332 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1333 doesn't support 128-bit integers for MIPS32 currently. */
1334 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1335
1336 /* long double is not a fixed mode, but the idea is that, if we
1337 support long double, we also want a 128-bit integer type. */
1338 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1339
1340 #ifdef IN_LIBGCC2
1341 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1342 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1343 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1344 # else
1345 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1346 # endif
1347 #endif
1348
1349 /* Width in bits of a pointer. */
1350 #ifndef POINTER_SIZE
1351 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1352 #endif
1353
1354 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1355 #define PARM_BOUNDARY BITS_PER_WORD
1356
1357 /* Allocation boundary (in *bits*) for the code of a function. */
1358 #define FUNCTION_BOUNDARY 32
1359
1360 /* Alignment of field after `int : 0' in a structure. */
1361 #define EMPTY_FIELD_BOUNDARY 32
1362
1363 /* Every structure's size must be a multiple of this. */
1364 /* 8 is observed right on a DECstation and on riscos 4.02. */
1365 #define STRUCTURE_SIZE_BOUNDARY 8
1366
1367 /* There is no point aligning anything to a rounder boundary than this. */
1368 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1369
1370 /* All accesses must be aligned. */
1371 #define STRICT_ALIGNMENT 1
1372
1373 /* Define this if you wish to imitate the way many other C compilers
1374 handle alignment of bitfields and the structures that contain
1375 them.
1376
1377 The behavior is that the type written for a bit-field (`int',
1378 `short', or other integer type) imposes an alignment for the
1379 entire structure, as if the structure really did contain an
1380 ordinary field of that type. In addition, the bit-field is placed
1381 within the structure so that it would fit within such a field,
1382 not crossing a boundary for it.
1383
1384 Thus, on most machines, a bit-field whose type is written as `int'
1385 would not cross a four-byte boundary, and would force four-byte
1386 alignment for the whole structure. (The alignment used may not
1387 be four bytes; it is controlled by the other alignment
1388 parameters.)
1389
1390 If the macro is defined, its definition should be a C expression;
1391 a nonzero value for the expression enables this behavior. */
1392
1393 #define PCC_BITFIELD_TYPE_MATTERS 1
1394
1395 /* If defined, a C expression to compute the alignment given to a
1396 constant that is being placed in memory. CONSTANT is the constant
1397 and ALIGN is the alignment that the object would ordinarily have.
1398 The value of this macro is used instead of that alignment to align
1399 the object.
1400
1401 If this macro is not defined, then ALIGN is used.
1402
1403 The typical use of this macro is to increase alignment for string
1404 constants to be word aligned so that `strcpy' calls that copy
1405 constants can be done inline. */
1406
1407 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1408 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1409 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1410
1411 /* If defined, a C expression to compute the alignment for a static
1412 variable. TYPE is the data type, and ALIGN is the alignment that
1413 the object would ordinarily have. The value of this macro is used
1414 instead of that alignment to align the object.
1415
1416 If this macro is not defined, then ALIGN is used.
1417
1418 One use of this macro is to increase alignment of medium-size
1419 data to make it all fit in fewer cache lines. Another is to
1420 cause character arrays to be word-aligned so that `strcpy' calls
1421 that copy constants to character arrays can be done inline. */
1422
1423 #undef DATA_ALIGNMENT
1424 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1425 ((((ALIGN) < BITS_PER_WORD) \
1426 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1427 || TREE_CODE (TYPE) == UNION_TYPE \
1428 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1429
1430 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1431 character arrays to be word-aligned so that `strcpy' calls that copy
1432 constants to character arrays can be done inline, and 'strcmp' can be
1433 optimised to use word loads. */
1434 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1435 DATA_ALIGNMENT (TYPE, ALIGN)
1436
1437 #define PAD_VARARGS_DOWN \
1438 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1439
1440 /* Define if operations between registers always perform the operation
1441 on the full register even if a narrower mode is specified. */
1442 #define WORD_REGISTER_OPERATIONS
1443
1444 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1445 moves. All other references are zero extended. */
1446 #define LOAD_EXTEND_OP(MODE) \
1447 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1448 ? SIGN_EXTEND : ZERO_EXTEND)
1449
1450 /* Define this macro if it is advisable to hold scalars in registers
1451 in a wider mode than that declared by the program. In such cases,
1452 the value is constrained to be within the bounds of the declared
1453 type, but kept valid in the wider mode. The signedness of the
1454 extension may differ from that of the type. */
1455
1456 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1457 if (GET_MODE_CLASS (MODE) == MODE_INT \
1458 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1459 { \
1460 if ((MODE) == SImode) \
1461 (UNSIGNEDP) = 0; \
1462 (MODE) = Pmode; \
1463 }
1464
1465 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1466 Extensions of pointers to word_mode must be signed. */
1467 #define POINTERS_EXTEND_UNSIGNED false
1468
1469 /* Define if loading short immediate values into registers sign extends. */
1470 #define SHORT_IMMEDIATES_SIGN_EXTEND
1471
1472 /* The [d]clz instructions have the natural values at 0. */
1473
1474 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1475 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1476 \f
1477 /* Standard register usage. */
1478
1479 /* Number of hardware registers. We have:
1480
1481 - 32 integer registers
1482 - 32 floating point registers
1483 - 8 condition code registers
1484 - 2 accumulator registers (hi and lo)
1485 - 32 registers each for coprocessors 0, 2 and 3
1486 - 4 fake registers:
1487 - ARG_POINTER_REGNUM
1488 - FRAME_POINTER_REGNUM
1489 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1490 - CPRESTORE_SLOT_REGNUM
1491 - 2 dummy entries that were used at various times in the past.
1492 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1493 - 6 DSP control registers */
1494
1495 #define FIRST_PSEUDO_REGISTER 188
1496
1497 /* By default, fix the kernel registers ($26 and $27), the global
1498 pointer ($28) and the stack pointer ($29). This can change
1499 depending on the command-line options.
1500
1501 Regarding coprocessor registers: without evidence to the contrary,
1502 it's best to assume that each coprocessor register has a unique
1503 use. This can be overridden, in, e.g., mips_option_override or
1504 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1505 inappropriate for a particular target. */
1506
1507 #define FIXED_REGISTERS \
1508 { \
1509 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1510 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1512 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1513 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1514 /* COP0 registers */ \
1515 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1516 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1517 /* COP2 registers */ \
1518 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1519 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1520 /* COP3 registers */ \
1521 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1522 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1523 /* 6 DSP accumulator registers & 6 control registers */ \
1524 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1525 }
1526
1527
1528 /* Set up this array for o32 by default.
1529
1530 Note that we don't mark $31 as a call-clobbered register. The idea is
1531 that it's really the call instructions themselves which clobber $31.
1532 We don't care what the called function does with it afterwards.
1533
1534 This approach makes it easier to implement sibcalls. Unlike normal
1535 calls, sibcalls don't clobber $31, so the register reaches the
1536 called function in tact. EPILOGUE_USES says that $31 is useful
1537 to the called function. */
1538
1539 #define CALL_USED_REGISTERS \
1540 { \
1541 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1542 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1543 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1544 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1545 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1546 /* COP0 registers */ \
1547 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1548 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1549 /* COP2 registers */ \
1550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1551 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1552 /* COP3 registers */ \
1553 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1554 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1555 /* 6 DSP accumulator registers & 6 control registers */ \
1556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1557 }
1558
1559
1560 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1561
1562 #define CALL_REALLY_USED_REGISTERS \
1563 { /* General registers. */ \
1564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1565 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1566 /* Floating-point registers. */ \
1567 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1568 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1569 /* Others. */ \
1570 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1571 /* COP0 registers */ \
1572 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1573 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1574 /* COP2 registers */ \
1575 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1576 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1577 /* COP3 registers */ \
1578 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1579 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1580 /* 6 DSP accumulator registers & 6 control registers */ \
1581 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1582 }
1583
1584 /* Internal macros to classify a register number as to whether it's a
1585 general purpose register, a floating point register, a
1586 multiply/divide register, or a status register. */
1587
1588 #define GP_REG_FIRST 0
1589 #define GP_REG_LAST 31
1590 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1591 #define GP_DBX_FIRST 0
1592 #define K0_REG_NUM (GP_REG_FIRST + 26)
1593 #define K1_REG_NUM (GP_REG_FIRST + 27)
1594 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1595
1596 #define FP_REG_FIRST 32
1597 #define FP_REG_LAST 63
1598 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1599 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1600
1601 #define MD_REG_FIRST 64
1602 #define MD_REG_LAST 65
1603 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1604 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1605
1606 /* The DWARF 2 CFA column which tracks the return address from a
1607 signal handler context. This means that to maintain backwards
1608 compatibility, no hard register can be assigned this column if it
1609 would need to be handled by the DWARF unwinder. */
1610 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1611
1612 #define ST_REG_FIRST 67
1613 #define ST_REG_LAST 74
1614 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1615
1616
1617 /* FIXME: renumber. */
1618 #define COP0_REG_FIRST 80
1619 #define COP0_REG_LAST 111
1620 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1621
1622 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1623 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1624 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1625
1626 #define COP2_REG_FIRST 112
1627 #define COP2_REG_LAST 143
1628 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1629
1630 #define COP3_REG_FIRST 144
1631 #define COP3_REG_LAST 175
1632 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1633 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1634 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1635
1636 #define DSP_ACC_REG_FIRST 176
1637 #define DSP_ACC_REG_LAST 181
1638 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1639
1640 #define AT_REGNUM (GP_REG_FIRST + 1)
1641 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1642 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1643
1644 /* A few bitfield locations for the coprocessor registers. */
1645 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1646 the cause register for the EIC interrupt mode. */
1647 #define CAUSE_IPL 10
1648 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1649 #define SR_IPL 10
1650 /* Exception Level is at bit 1 of the status register. */
1651 #define SR_EXL 1
1652 /* Interrupt Enable is at bit 0 of the status register. */
1653 #define SR_IE 0
1654
1655 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1656 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1657 should be used instead. */
1658 #define FPSW_REGNUM ST_REG_FIRST
1659
1660 #define GP_REG_P(REGNO) \
1661 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1662 #define M16_REG_P(REGNO) \
1663 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1664 #define FP_REG_P(REGNO) \
1665 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1666 #define MD_REG_P(REGNO) \
1667 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1668 #define ST_REG_P(REGNO) \
1669 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1670 #define COP0_REG_P(REGNO) \
1671 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1672 #define COP2_REG_P(REGNO) \
1673 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1674 #define COP3_REG_P(REGNO) \
1675 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1676 #define ALL_COP_REG_P(REGNO) \
1677 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1678 /* Test if REGNO is one of the 6 new DSP accumulators. */
1679 #define DSP_ACC_REG_P(REGNO) \
1680 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1681 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1682 #define ACC_REG_P(REGNO) \
1683 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1684
1685 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1686
1687 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1688 to initialize the mips16 gp pseudo register. */
1689 #define CONST_GP_P(X) \
1690 (GET_CODE (X) == CONST \
1691 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1692 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1693
1694 /* Return coprocessor number from register number. */
1695
1696 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1697 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1698 : COP3_REG_P (REGNO) ? '3' : '?')
1699
1700
1701 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1702
1703 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1704 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1705
1706 #define MODES_TIEABLE_P mips_modes_tieable_p
1707
1708 /* Register to use for pushing function arguments. */
1709 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1710
1711 /* These two registers don't really exist: they get eliminated to either
1712 the stack or hard frame pointer. */
1713 #define ARG_POINTER_REGNUM 77
1714 #define FRAME_POINTER_REGNUM 78
1715
1716 /* $30 is not available on the mips16, so we use $17 as the frame
1717 pointer. */
1718 #define HARD_FRAME_POINTER_REGNUM \
1719 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1720
1721 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1722 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1723
1724 /* Register in which static-chain is passed to a function. */
1725 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1726
1727 /* Registers used as temporaries in prologue/epilogue code:
1728
1729 - If a MIPS16 PIC function needs access to _gp, it first loads
1730 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1731
1732 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1733 register. The register must not conflict with MIPS16_PIC_TEMP.
1734
1735 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1736 register.
1737
1738 If we're generating MIPS16 code, these registers must come from the
1739 core set of 8. The prologue registers mustn't conflict with any
1740 incoming arguments, the static chain pointer, or the frame pointer.
1741 The epilogue temporary mustn't conflict with the return registers,
1742 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1743 or the EH data registers.
1744
1745 If we're generating interrupt handlers, we use K0 as a temporary register
1746 in prologue/epilogue code. */
1747
1748 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1749 #define MIPS_PROLOGUE_TEMP_REGNUM \
1750 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1751 #define MIPS_EPILOGUE_TEMP_REGNUM \
1752 (cfun->machine->interrupt_handler_p \
1753 ? K0_REG_NUM \
1754 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1755
1756 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1757 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1758 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1759
1760 /* Define this macro if it is as good or better to call a constant
1761 function address than to call an address kept in a register. */
1762 #define NO_FUNCTION_CSE 1
1763
1764 /* The ABI-defined global pointer. Sometimes we use a different
1765 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1766 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1767
1768 /* We normally use $28 as the global pointer. However, when generating
1769 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1770 register instead. They can then avoid saving and restoring $28
1771 and perhaps avoid using a frame at all.
1772
1773 When a leaf function uses something other than $28, mips_expand_prologue
1774 will modify pic_offset_table_rtx in place. Take the register number
1775 from there after reload. */
1776 #define PIC_OFFSET_TABLE_REGNUM \
1777 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1778 \f
1779 /* Define the classes of registers for register constraints in the
1780 machine description. Also define ranges of constants.
1781
1782 One of the classes must always be named ALL_REGS and include all hard regs.
1783 If there is more than one class, another class must be named NO_REGS
1784 and contain no registers.
1785
1786 The name GENERAL_REGS must be the name of a class (or an alias for
1787 another name such as ALL_REGS). This is the class of registers
1788 that is allowed by "g" or "r" in a register constraint.
1789 Also, registers outside this class are allocated only when
1790 instructions express preferences for them.
1791
1792 The classes must be numbered in nondecreasing order; that is,
1793 a larger-numbered class must never be contained completely
1794 in a smaller-numbered class.
1795
1796 For any two classes, it is very desirable that there be another
1797 class that represents their union. */
1798
1799 enum reg_class
1800 {
1801 NO_REGS, /* no registers in set */
1802 M16_REGS, /* mips16 directly accessible registers */
1803 T_REG, /* mips16 T register ($24) */
1804 M16_T_REGS, /* mips16 registers plus T register */
1805 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1806 V1_REG, /* Register $v1 ($3) used for TLS access. */
1807 LEA_REGS, /* Every GPR except $25 */
1808 GR_REGS, /* integer registers */
1809 FP_REGS, /* floating point registers */
1810 MD0_REG, /* first multiply/divide register */
1811 MD1_REG, /* second multiply/divide register */
1812 MD_REGS, /* multiply/divide registers (hi/lo) */
1813 COP0_REGS, /* generic coprocessor classes */
1814 COP2_REGS,
1815 COP3_REGS,
1816 ST_REGS, /* status registers (fp status) */
1817 DSP_ACC_REGS, /* DSP accumulator registers */
1818 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1819 FRAME_REGS, /* $arg and $frame */
1820 GR_AND_MD0_REGS, /* union classes */
1821 GR_AND_MD1_REGS,
1822 GR_AND_MD_REGS,
1823 GR_AND_ACC_REGS,
1824 ALL_REGS, /* all registers */
1825 LIM_REG_CLASSES /* max value + 1 */
1826 };
1827
1828 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1829
1830 #define GENERAL_REGS GR_REGS
1831
1832 /* An initializer containing the names of the register classes as C
1833 string constants. These names are used in writing some of the
1834 debugging dumps. */
1835
1836 #define REG_CLASS_NAMES \
1837 { \
1838 "NO_REGS", \
1839 "M16_REGS", \
1840 "T_REG", \
1841 "M16_T_REGS", \
1842 "PIC_FN_ADDR_REG", \
1843 "V1_REG", \
1844 "LEA_REGS", \
1845 "GR_REGS", \
1846 "FP_REGS", \
1847 "MD0_REG", \
1848 "MD1_REG", \
1849 "MD_REGS", \
1850 /* coprocessor registers */ \
1851 "COP0_REGS", \
1852 "COP2_REGS", \
1853 "COP3_REGS", \
1854 "ST_REGS", \
1855 "DSP_ACC_REGS", \
1856 "ACC_REGS", \
1857 "FRAME_REGS", \
1858 "GR_AND_MD0_REGS", \
1859 "GR_AND_MD1_REGS", \
1860 "GR_AND_MD_REGS", \
1861 "GR_AND_ACC_REGS", \
1862 "ALL_REGS" \
1863 }
1864
1865 /* An initializer containing the contents of the register classes,
1866 as integers which are bit masks. The Nth integer specifies the
1867 contents of class N. The way the integer MASK is interpreted is
1868 that register R is in the class if `MASK & (1 << R)' is 1.
1869
1870 When the machine has more than 32 registers, an integer does not
1871 suffice. Then the integers are replaced by sub-initializers,
1872 braced groupings containing several integers. Each
1873 sub-initializer must be suitable as an initializer for the type
1874 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1875
1876 #define REG_CLASS_CONTENTS \
1877 { \
1878 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1879 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1880 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1881 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1882 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1883 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1884 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1885 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1886 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1887 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1888 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1889 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1890 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1891 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1892 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1893 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1894 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1895 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1896 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1897 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1898 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1899 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1900 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1901 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1902 }
1903
1904
1905 /* A C expression whose value is a register class containing hard
1906 register REGNO. In general there is more that one such class;
1907 choose a class which is "minimal", meaning that no smaller class
1908 also contains the register. */
1909
1910 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1911
1912 /* A macro whose definition is the name of the class to which a
1913 valid base register must belong. A base register is one used in
1914 an address which is the register value plus a displacement. */
1915
1916 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1917
1918 /* A macro whose definition is the name of the class to which a
1919 valid index register must belong. An index register is one used
1920 in an address where its value is either multiplied by a scale
1921 factor or added to another register (as well as added to a
1922 displacement). */
1923
1924 #define INDEX_REG_CLASS NO_REGS
1925
1926 /* We generally want to put call-clobbered registers ahead of
1927 call-saved ones. (IRA expects this.) */
1928
1929 #define REG_ALLOC_ORDER \
1930 { /* Accumulator registers. When GPRs and accumulators have equal \
1931 cost, we generally prefer to use accumulators. For example, \
1932 a division of multiplication result is better allocated to LO, \
1933 so that we put the MFLO at the point of use instead of at the \
1934 point of definition. It's also needed if we're to take advantage \
1935 of the extra accumulators available with -mdspr2. In some cases, \
1936 it can also help to reduce register pressure. */ \
1937 64, 65,176,177,178,179,180,181, \
1938 /* Call-clobbered GPRs. */ \
1939 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1940 24, 25, 31, \
1941 /* The global pointer. This is call-clobbered for o32 and o64 \
1942 abicalls, call-saved for n32 and n64 abicalls, and a program \
1943 invariant otherwise. Putting it between the call-clobbered \
1944 and call-saved registers should cope with all eventualities. */ \
1945 28, \
1946 /* Call-saved GPRs. */ \
1947 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1948 /* GPRs that can never be exposed to the register allocator. */ \
1949 0, 26, 27, 29, \
1950 /* Call-clobbered FPRs. */ \
1951 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1952 48, 49, 50, 51, \
1953 /* FPRs that are usually call-saved. The odd ones are actually \
1954 call-clobbered for n32, but listing them ahead of the even \
1955 registers might encourage the register allocator to fragment \
1956 the available FPR pairs. We need paired FPRs to store long \
1957 doubles, so it isn't clear that using a different order \
1958 for n32 would be a win. */ \
1959 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1960 /* None of the remaining classes have defined call-saved \
1961 registers. */ \
1962 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1963 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1964 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1965 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1966 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1967 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1968 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1969 182,183,184,185,186,187 \
1970 }
1971
1972 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1973 to be rearranged based on a particular function. On the mips16, we
1974 want to allocate $24 (T_REG) before other registers for
1975 instructions for which it is possible. */
1976
1977 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
1978
1979 /* True if VALUE is an unsigned 6-bit number. */
1980
1981 #define UIMM6_OPERAND(VALUE) \
1982 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1983
1984 /* True if VALUE is a signed 10-bit number. */
1985
1986 #define IMM10_OPERAND(VALUE) \
1987 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1988
1989 /* True if VALUE is a signed 16-bit number. */
1990
1991 #define SMALL_OPERAND(VALUE) \
1992 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1993
1994 /* True if VALUE is an unsigned 16-bit number. */
1995
1996 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1997 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1998
1999 /* True if VALUE can be loaded into a register using LUI. */
2000
2001 #define LUI_OPERAND(VALUE) \
2002 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2003 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2004
2005 /* Return a value X with the low 16 bits clear, and such that
2006 VALUE - X is a signed 16-bit value. */
2007
2008 #define CONST_HIGH_PART(VALUE) \
2009 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2010
2011 #define CONST_LOW_PART(VALUE) \
2012 ((VALUE) - CONST_HIGH_PART (VALUE))
2013
2014 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2015 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2016 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2017
2018 /* The HI and LO registers can only be reloaded via the general
2019 registers. Condition code registers can only be loaded to the
2020 general registers, and from the floating point registers. */
2021
2022 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2023 mips_secondary_reload_class (CLASS, MODE, X, true)
2024 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2025 mips_secondary_reload_class (CLASS, MODE, X, false)
2026
2027 /* Return the maximum number of consecutive registers
2028 needed to represent mode MODE in a register of class CLASS. */
2029
2030 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2031
2032 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2033 mips_cannot_change_mode_class (FROM, TO, CLASS)
2034 \f
2035 /* Stack layout; function entry, exit and calling. */
2036
2037 #define STACK_GROWS_DOWNWARD
2038
2039 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2040
2041 /* Size of the area allocated in the frame to save the GP. */
2042
2043 #define MIPS_GP_SAVE_AREA_SIZE \
2044 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2045
2046 /* The offset of the first local variable from the frame pointer. See
2047 mips_compute_frame_info for details about the frame layout. */
2048
2049 #define STARTING_FRAME_OFFSET \
2050 (FRAME_GROWS_DOWNWARD \
2051 ? 0 \
2052 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2053
2054 #define RETURN_ADDR_RTX mips_return_addr
2055
2056 /* Mask off the MIPS16 ISA bit in unwind addresses.
2057
2058 The reason for this is a little subtle. When unwinding a call,
2059 we are given the call's return address, which on most targets
2060 is the address of the following instruction. However, what we
2061 actually want to find is the EH region for the call itself.
2062 The target-independent unwind code therefore searches for "RA - 1".
2063
2064 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2065 RA - 1 is therefore the real (even-valued) start of the return
2066 instruction. EH region labels are usually odd-valued MIPS16 symbols
2067 too, so a search for an even address within a MIPS16 region would
2068 usually work.
2069
2070 However, there is an exception. If the end of an EH region is also
2071 the end of a function, the end label is allowed to be even. This is
2072 necessary because a following non-MIPS16 function may also need EH
2073 information for its first instruction.
2074
2075 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2076 non-ISA-encoded address. This probably isn't ideal, but it is
2077 the traditional (legacy) behavior. It is therefore only safe
2078 to search MIPS EH regions for an _odd-valued_ address.
2079
2080 Masking off the ISA bit means that the target-independent code
2081 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2082 #define MASK_RETURN_ADDR GEN_INT (-2)
2083
2084
2085 /* Similarly, don't use the least-significant bit to tell pointers to
2086 code from vtable index. */
2087
2088 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2089
2090 /* The eliminations to $17 are only used for mips16 code. See the
2091 definition of HARD_FRAME_POINTER_REGNUM. */
2092
2093 #define ELIMINABLE_REGS \
2094 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2095 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2096 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2097 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2098 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2099 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2100
2101 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2102 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2103
2104 /* Allocate stack space for arguments at the beginning of each function. */
2105 #define ACCUMULATE_OUTGOING_ARGS 1
2106
2107 /* The argument pointer always points to the first argument. */
2108 #define FIRST_PARM_OFFSET(FNDECL) 0
2109
2110 /* o32 and o64 reserve stack space for all argument registers. */
2111 #define REG_PARM_STACK_SPACE(FNDECL) \
2112 (TARGET_OLDABI \
2113 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2114 : 0)
2115
2116 /* Define this if it is the responsibility of the caller to
2117 allocate the area reserved for arguments passed in registers.
2118 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2119 of this macro is to determine whether the space is included in
2120 `crtl->outgoing_args_size'. */
2121 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2122
2123 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2124 \f
2125 /* Symbolic macros for the registers used to return integer and floating
2126 point values. */
2127
2128 #define GP_RETURN (GP_REG_FIRST + 2)
2129 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2130
2131 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2132
2133 /* Symbolic macros for the first/last argument registers. */
2134
2135 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2136 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2137 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2138 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2139
2140 /* 1 if N is a possible register number for function argument passing.
2141 We have no FP argument registers when soft-float. When FP registers
2142 are 32 bits, we can't directly reference the odd numbered ones. */
2143
2144 #define FUNCTION_ARG_REGNO_P(N) \
2145 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2146 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2147 && !fixed_regs[N])
2148 \f
2149 /* This structure has to cope with two different argument allocation
2150 schemes. Most MIPS ABIs view the arguments as a structure, of which
2151 the first N words go in registers and the rest go on the stack. If I
2152 < N, the Ith word might go in Ith integer argument register or in a
2153 floating-point register. For these ABIs, we only need to remember
2154 the offset of the current argument into the structure.
2155
2156 The EABI instead allocates the integer and floating-point arguments
2157 separately. The first N words of FP arguments go in FP registers,
2158 the rest go on the stack. Likewise, the first N words of the other
2159 arguments go in integer registers, and the rest go on the stack. We
2160 need to maintain three counts: the number of integer registers used,
2161 the number of floating-point registers used, and the number of words
2162 passed on the stack.
2163
2164 We could keep separate information for the two ABIs (a word count for
2165 the standard ABIs, and three separate counts for the EABI). But it
2166 seems simpler to view the standard ABIs as forms of EABI that do not
2167 allocate floating-point registers.
2168
2169 So for the standard ABIs, the first N words are allocated to integer
2170 registers, and mips_function_arg decides on an argument-by-argument
2171 basis whether that argument should really go in an integer register,
2172 or in a floating-point one. */
2173
2174 typedef struct mips_args {
2175 /* Always true for varargs functions. Otherwise true if at least
2176 one argument has been passed in an integer register. */
2177 int gp_reg_found;
2178
2179 /* The number of arguments seen so far. */
2180 unsigned int arg_number;
2181
2182 /* The number of integer registers used so far. For all ABIs except
2183 EABI, this is the number of words that have been added to the
2184 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2185 unsigned int num_gprs;
2186
2187 /* For EABI, the number of floating-point registers used so far. */
2188 unsigned int num_fprs;
2189
2190 /* The number of words passed on the stack. */
2191 unsigned int stack_words;
2192
2193 /* On the mips16, we need to keep track of which floating point
2194 arguments were passed in general registers, but would have been
2195 passed in the FP regs if this were a 32-bit function, so that we
2196 can move them to the FP regs if we wind up calling a 32-bit
2197 function. We record this information in fp_code, encoded in base
2198 four. A zero digit means no floating point argument, a one digit
2199 means an SFmode argument, and a two digit means a DFmode argument,
2200 and a three digit is not used. The low order digit is the first
2201 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2202 an SFmode argument. ??? A more sophisticated approach will be
2203 needed if MIPS_ABI != ABI_32. */
2204 int fp_code;
2205
2206 /* True if the function has a prototype. */
2207 int prototype;
2208 } CUMULATIVE_ARGS;
2209
2210 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2211 for a call to a function whose data type is FNTYPE.
2212 For a library call, FNTYPE is 0. */
2213
2214 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2215 mips_init_cumulative_args (&CUM, FNTYPE)
2216
2217 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2218 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2219
2220 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2221 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2222
2223 /* True if using EABI and varargs can be passed in floating-point
2224 registers. Under these conditions, we need a more complex form
2225 of va_list, which tracks GPR, FPR and stack arguments separately. */
2226 #define EABI_FLOAT_VARARGS_P \
2227 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2228
2229 \f
2230 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2231
2232 /* Treat LOC as a byte offset from the stack pointer and round it up
2233 to the next fully-aligned offset. */
2234 #define MIPS_STACK_ALIGN(LOC) \
2235 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2236
2237 \f
2238 /* Output assembler code to FILE to increment profiler label # LABELNO
2239 for profiling a function entry. */
2240
2241 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2242
2243 /* The profiler preserves all interesting registers, including $31. */
2244 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2245
2246 /* No mips port has ever used the profiler counter word, so don't emit it
2247 or the label for it. */
2248
2249 #define NO_PROFILE_COUNTERS 1
2250
2251 /* Define this macro if the code for function profiling should come
2252 before the function prologue. Normally, the profiling code comes
2253 after. */
2254
2255 /* #define PROFILE_BEFORE_PROLOGUE */
2256
2257 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2258 the stack pointer does not matter. The value is tested only in
2259 functions that have frame pointers.
2260 No definition is equivalent to always zero. */
2261
2262 #define EXIT_IGNORE_STACK 1
2263
2264 \f
2265 /* Trampolines are a block of code followed by two pointers. */
2266
2267 #define TRAMPOLINE_SIZE \
2268 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2269
2270 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2271 pointers from a single LUI base. */
2272
2273 #define TRAMPOLINE_ALIGNMENT 64
2274
2275 /* mips_trampoline_init calls this library function to flush
2276 program and data caches. */
2277
2278 #ifndef CACHE_FLUSH_FUNC
2279 #define CACHE_FLUSH_FUNC "_flush_cache"
2280 #endif
2281
2282 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2283 /* Flush both caches. We need to flush the data cache in case \
2284 the system has a write-back cache. */ \
2285 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2286 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2287 GEN_INT (3), TYPE_MODE (integer_type_node))
2288
2289 \f
2290 /* Addressing modes, and classification of registers for them. */
2291
2292 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2293 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2294 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2295 \f
2296 /* Maximum number of registers that can appear in a valid memory address. */
2297
2298 #define MAX_REGS_PER_ADDRESS 1
2299
2300 /* Check for constness inline but use mips_legitimate_address_p
2301 to check whether a constant really is an address. */
2302
2303 #define CONSTANT_ADDRESS_P(X) \
2304 (CONSTANT_P (X) && memory_address_p (SImode, X))
2305
2306 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2307 'the start of the function that this code is output in'. */
2308
2309 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2310 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2311 asm_fprintf ((FILE), "%U%s", \
2312 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2313 else \
2314 asm_fprintf ((FILE), "%U%s", (NAME))
2315 \f
2316 /* Flag to mark a function decl symbol that requires a long call. */
2317 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2318 #define SYMBOL_REF_LONG_CALL_P(X) \
2319 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2320
2321 /* This flag marks functions that cannot be lazily bound. */
2322 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2323 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2324 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2325
2326 /* True if we're generating a form of MIPS16 code in which jump tables
2327 are stored in the text section and encoded as 16-bit PC-relative
2328 offsets. This is only possible when general text loads are allowed,
2329 since the table access itself will be an "lh" instruction. */
2330 /* ??? 16-bit offsets can overflow in large functions. */
2331 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2332
2333 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2334
2335 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2336
2337 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2338
2339 /* Define this as 1 if `char' should by default be signed; else as 0. */
2340 #ifndef DEFAULT_SIGNED_CHAR
2341 #define DEFAULT_SIGNED_CHAR 1
2342 #endif
2343
2344 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2345 we generally don't want to use them for copying arbitrary data.
2346 A single N-word move is usually the same cost as N single-word moves. */
2347 #define MOVE_MAX UNITS_PER_WORD
2348 #define MAX_MOVE_MAX 8
2349
2350 /* Define this macro as a C expression which is nonzero if
2351 accessing less than a word of memory (i.e. a `char' or a
2352 `short') is no faster than accessing a word of memory, i.e., if
2353 such access require more than one instruction or if there is no
2354 difference in cost between byte and (aligned) word loads.
2355
2356 On RISC machines, it tends to generate better code to define
2357 this as 1, since it avoids making a QI or HI mode register.
2358
2359 But, generating word accesses for -mips16 is generally bad as shifts
2360 (often extended) would be needed for byte accesses. */
2361 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2362
2363 /* Standard MIPS integer shifts truncate the shift amount to the
2364 width of the shifted operand. However, Loongson vector shifts
2365 do not truncate the shift amount at all. */
2366 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2367
2368 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2369 is done just by pretending it is already truncated. */
2370 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2371 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2372
2373
2374 /* Specify the machine mode that pointers have.
2375 After generation of rtl, the compiler makes no further distinction
2376 between pointers and any other objects of this machine mode. */
2377
2378 #ifndef Pmode
2379 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2380 #endif
2381
2382 /* Give call MEMs SImode since it is the "most permissive" mode
2383 for both 32-bit and 64-bit targets. */
2384
2385 #define FUNCTION_MODE SImode
2386
2387 \f
2388
2389 /* Define if copies to/from condition code registers should be avoided.
2390
2391 This is needed for the MIPS because reload_outcc is not complete;
2392 it needs to handle cases where the source is a general or another
2393 condition code register. */
2394 #define AVOID_CCMODE_COPIES
2395
2396 /* A C expression for the cost of a branch instruction. A value of
2397 1 is the default; other values are interpreted relative to that. */
2398
2399 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2400 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2401
2402 /* If defined, modifies the length assigned to instruction INSN as a
2403 function of the context in which it is used. LENGTH is an lvalue
2404 that contains the initially computed length of the insn and should
2405 be updated with the correct length of the insn. */
2406 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2407 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2408
2409 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2410 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2411 its operands. */
2412 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2413 "%*" OPCODE "%?\t" OPERANDS "%/"
2414
2415 /* Return an asm string that forces INSN to be treated as an absolute
2416 J or JAL instruction instead of an assembler macro. */
2417 #define MIPS_ABSOLUTE_JUMP(INSN) \
2418 (TARGET_ABICALLS_PIC2 \
2419 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2420 : INSN)
2421
2422 /* Return the asm template for a call. INSN is the instruction's mnemonic
2423 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2424 number of the target. SIZE_OPNO is the operand number of the argument size
2425 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2426 -1 and the call is indirect, use the function symbol from the call
2427 attributes to attach a R_MIPS_JALR relocation to the call.
2428
2429 When generating GOT code without explicit relocation operators,
2430 all calls should use assembly macros. Otherwise, all indirect
2431 calls should use "jr" or "jalr"; we will arrange to restore $gp
2432 afterwards if necessary. Finally, we can only generate direct
2433 calls for -mabicalls by temporarily switching to non-PIC mode. */
2434 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2435 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2436 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2437 : (REG_P (OPERANDS[TARGET_OPNO]) \
2438 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2439 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2440 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2441 : REG_P (OPERANDS[TARGET_OPNO]) \
2442 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2443 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2444 \f
2445 /* Control the assembler format that we output. */
2446
2447 /* Output to assembler file text saying following lines
2448 may contain character constants, extra white space, comments, etc. */
2449
2450 #ifndef ASM_APP_ON
2451 #define ASM_APP_ON " #APP\n"
2452 #endif
2453
2454 /* Output to assembler file text saying following lines
2455 no longer contain unusual constructs. */
2456
2457 #ifndef ASM_APP_OFF
2458 #define ASM_APP_OFF " #NO_APP\n"
2459 #endif
2460
2461 #define REGISTER_NAMES \
2462 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2463 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2464 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2465 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2466 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2467 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2468 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2469 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2470 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2471 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2472 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2473 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2474 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2475 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2476 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2477 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2478 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2479 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2480 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2481 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2482 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2483 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2484 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2485 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2486
2487 /* List the "software" names for each register. Also list the numerical
2488 names for $fp and $sp. */
2489
2490 #define ADDITIONAL_REGISTER_NAMES \
2491 { \
2492 { "$29", 29 + GP_REG_FIRST }, \
2493 { "$30", 30 + GP_REG_FIRST }, \
2494 { "at", 1 + GP_REG_FIRST }, \
2495 { "v0", 2 + GP_REG_FIRST }, \
2496 { "v1", 3 + GP_REG_FIRST }, \
2497 { "a0", 4 + GP_REG_FIRST }, \
2498 { "a1", 5 + GP_REG_FIRST }, \
2499 { "a2", 6 + GP_REG_FIRST }, \
2500 { "a3", 7 + GP_REG_FIRST }, \
2501 { "t0", 8 + GP_REG_FIRST }, \
2502 { "t1", 9 + GP_REG_FIRST }, \
2503 { "t2", 10 + GP_REG_FIRST }, \
2504 { "t3", 11 + GP_REG_FIRST }, \
2505 { "t4", 12 + GP_REG_FIRST }, \
2506 { "t5", 13 + GP_REG_FIRST }, \
2507 { "t6", 14 + GP_REG_FIRST }, \
2508 { "t7", 15 + GP_REG_FIRST }, \
2509 { "s0", 16 + GP_REG_FIRST }, \
2510 { "s1", 17 + GP_REG_FIRST }, \
2511 { "s2", 18 + GP_REG_FIRST }, \
2512 { "s3", 19 + GP_REG_FIRST }, \
2513 { "s4", 20 + GP_REG_FIRST }, \
2514 { "s5", 21 + GP_REG_FIRST }, \
2515 { "s6", 22 + GP_REG_FIRST }, \
2516 { "s7", 23 + GP_REG_FIRST }, \
2517 { "t8", 24 + GP_REG_FIRST }, \
2518 { "t9", 25 + GP_REG_FIRST }, \
2519 { "k0", 26 + GP_REG_FIRST }, \
2520 { "k1", 27 + GP_REG_FIRST }, \
2521 { "gp", 28 + GP_REG_FIRST }, \
2522 { "sp", 29 + GP_REG_FIRST }, \
2523 { "fp", 30 + GP_REG_FIRST }, \
2524 { "ra", 31 + GP_REG_FIRST } \
2525 }
2526
2527 #define DBR_OUTPUT_SEQEND(STREAM) \
2528 do \
2529 { \
2530 /* Undo the effect of '%*'. */ \
2531 mips_pop_asm_switch (&mips_nomacro); \
2532 mips_pop_asm_switch (&mips_noreorder); \
2533 /* Emit a blank line after the delay slot for emphasis. */ \
2534 fputs ("\n", STREAM); \
2535 } \
2536 while (0)
2537
2538 /* The MIPS implementation uses some labels for its own purpose. The
2539 following lists what labels are created, and are all formed by the
2540 pattern $L[a-z].*. The machine independent portion of GCC creates
2541 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2542
2543 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2544 $Lb[0-9]+ Begin blocks for MIPS debug support
2545 $Lc[0-9]+ Label for use in s<xx> operation.
2546 $Le[0-9]+ End blocks for MIPS debug support */
2547
2548 #undef ASM_DECLARE_OBJECT_NAME
2549 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2550 mips_declare_object (STREAM, NAME, "", ":\n")
2551
2552 /* Globalizing directive for a label. */
2553 #define GLOBAL_ASM_OP "\t.globl\t"
2554
2555 /* This says how to define a global common symbol. */
2556
2557 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2558
2559 /* This says how to define a local common symbol (i.e., not visible to
2560 linker). */
2561
2562 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2563 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2564 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2565 #endif
2566
2567 /* This says how to output an external. It would be possible not to
2568 output anything and let undefined symbol become external. However
2569 the assembler uses length information on externals to allocate in
2570 data/sdata bss/sbss, thereby saving exec time. */
2571
2572 #undef ASM_OUTPUT_EXTERNAL
2573 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2574 mips_output_external(STREAM,DECL,NAME)
2575
2576 /* This is how to declare a function name. The actual work of
2577 emitting the label is moved to function_prologue, so that we can
2578 get the line number correctly emitted before the .ent directive,
2579 and after any .file directives. Define as empty so that the function
2580 is not declared before the .ent directive elsewhere. */
2581
2582 #undef ASM_DECLARE_FUNCTION_NAME
2583 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2584
2585 /* This is how to store into the string LABEL
2586 the symbol_ref name of an internal numbered label where
2587 PREFIX is the class of label and NUM is the number within the class.
2588 This is suitable for output with `assemble_name'. */
2589
2590 #undef ASM_GENERATE_INTERNAL_LABEL
2591 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2592 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2593
2594 /* Print debug labels as "foo = ." rather than "foo:" because they should
2595 represent a byte pointer rather than an ISA-encoded address. This is
2596 particularly important for code like:
2597
2598 $LFBxxx = .
2599 .cfi_startproc
2600 ...
2601 .section .gcc_except_table,...
2602 ...
2603 .uleb128 foo-$LFBxxx
2604
2605 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2606 likewise a byte pointer rather than an ISA-encoded address.
2607
2608 At the time of writing, this hook is not used for the function end
2609 label:
2610
2611 $LFExxx:
2612 .end foo
2613
2614 But this doesn't matter, because GAS doesn't treat a pre-.end label
2615 as a MIPS16 one anyway. */
2616
2617 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2618 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2619
2620 /* This is how to output an element of a case-vector that is absolute. */
2621
2622 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2623 fprintf (STREAM, "\t%s\t%sL%d\n", \
2624 ptr_mode == DImode ? ".dword" : ".word", \
2625 LOCAL_LABEL_PREFIX, \
2626 VALUE)
2627
2628 /* This is how to output an element of a case-vector. We can make the
2629 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2630 is supported. */
2631
2632 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2633 do { \
2634 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2635 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2636 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2637 else if (TARGET_GPWORD) \
2638 fprintf (STREAM, "\t%s\t%sL%d\n", \
2639 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2640 LOCAL_LABEL_PREFIX, VALUE); \
2641 else if (TARGET_RTP_PIC) \
2642 { \
2643 /* Make the entry relative to the start of the function. */ \
2644 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2645 fprintf (STREAM, "\t%s\t%sL%d-", \
2646 Pmode == DImode ? ".dword" : ".word", \
2647 LOCAL_LABEL_PREFIX, VALUE); \
2648 assemble_name (STREAM, XSTR (fnsym, 0)); \
2649 fprintf (STREAM, "\n"); \
2650 } \
2651 else \
2652 fprintf (STREAM, "\t%s\t%sL%d\n", \
2653 ptr_mode == DImode ? ".dword" : ".word", \
2654 LOCAL_LABEL_PREFIX, VALUE); \
2655 } while (0)
2656
2657 /* This is how to output an assembler line
2658 that says to advance the location counter
2659 to a multiple of 2**LOG bytes. */
2660
2661 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2662 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2663
2664 /* This is how to output an assembler line to advance the location
2665 counter by SIZE bytes. */
2666
2667 #undef ASM_OUTPUT_SKIP
2668 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2669 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2670
2671 /* This is how to output a string. */
2672 #undef ASM_OUTPUT_ASCII
2673 #define ASM_OUTPUT_ASCII mips_output_ascii
2674
2675 \f
2676 /* Default to -G 8 */
2677 #ifndef MIPS_DEFAULT_GVALUE
2678 #define MIPS_DEFAULT_GVALUE 8
2679 #endif
2680
2681 /* Define the strings to put out for each section in the object file. */
2682 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2683 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2684
2685 #undef READONLY_DATA_SECTION_ASM_OP
2686 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2687 \f
2688 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2689 do \
2690 { \
2691 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2692 TARGET_64BIT ? "daddiu" : "addiu", \
2693 reg_names[STACK_POINTER_REGNUM], \
2694 reg_names[STACK_POINTER_REGNUM], \
2695 TARGET_64BIT ? "sd" : "sw", \
2696 reg_names[REGNO], \
2697 reg_names[STACK_POINTER_REGNUM]); \
2698 } \
2699 while (0)
2700
2701 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2702 do \
2703 { \
2704 mips_push_asm_switch (&mips_noreorder); \
2705 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2706 TARGET_64BIT ? "ld" : "lw", \
2707 reg_names[REGNO], \
2708 reg_names[STACK_POINTER_REGNUM], \
2709 TARGET_64BIT ? "daddu" : "addu", \
2710 reg_names[STACK_POINTER_REGNUM], \
2711 reg_names[STACK_POINTER_REGNUM]); \
2712 mips_pop_asm_switch (&mips_noreorder); \
2713 } \
2714 while (0)
2715
2716 /* How to start an assembler comment.
2717 The leading space is important (the mips native assembler requires it). */
2718 #ifndef ASM_COMMENT_START
2719 #define ASM_COMMENT_START " #"
2720 #endif
2721 \f
2722 #undef SIZE_TYPE
2723 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2724
2725 #undef PTRDIFF_TYPE
2726 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2727
2728 /* The maximum number of bytes that can be copied by one iteration of
2729 a movmemsi loop; see mips_block_move_loop. */
2730 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2731 (UNITS_PER_WORD * 4)
2732
2733 /* The maximum number of bytes that can be copied by a straight-line
2734 implementation of movmemsi; see mips_block_move_straight. We want
2735 to make sure that any loop-based implementation will iterate at
2736 least twice. */
2737 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2738 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2739
2740 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2741 values were determined experimentally by benchmarking with CSiBE.
2742 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2743 for o32 where we have to restore $gp afterwards as well as make an
2744 indirect call), but in practice, bumping this up higher for
2745 TARGET_ABICALLS doesn't make much difference to code size. */
2746
2747 #define MIPS_CALL_RATIO 8
2748
2749 /* Any loop-based implementation of movmemsi will have at least
2750 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2751 moves, so allow individual copies of fewer elements.
2752
2753 When movmemsi is not available, use a value approximating
2754 the length of a memcpy call sequence, so that move_by_pieces
2755 will generate inline code if it is shorter than a function call.
2756 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2757 we'll have to generate a load/store pair for each, halve the
2758 value of MIPS_CALL_RATIO to take that into account. */
2759
2760 #define MOVE_RATIO(speed) \
2761 (HAVE_movmemsi \
2762 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2763 : MIPS_CALL_RATIO / 2)
2764
2765 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2766 mips_move_by_pieces_p (SIZE, ALIGN)
2767
2768 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2769 of the length of a memset call, but use the default otherwise. */
2770
2771 #define CLEAR_RATIO(speed)\
2772 ((speed) ? 15 : MIPS_CALL_RATIO)
2773
2774 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2775 optimizing for size adjust the ratio to account for the overhead of
2776 loading the constant and replicating it across the word. */
2777
2778 #define SET_RATIO(speed) \
2779 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2780
2781 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2782 mips_store_by_pieces_p (SIZE, ALIGN)
2783 \f
2784 #ifndef __mips16
2785 /* Since the bits of the _init and _fini function is spread across
2786 many object files, each potentially with its own GP, we must assume
2787 we need to load our GP. We don't preserve $gp or $ra, since each
2788 init/fini chunk is supposed to initialize $gp, and crti/crtn
2789 already take care of preserving $ra and, when appropriate, $gp. */
2790 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2791 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2792 asm (SECTION_OP "\n\
2793 .set noreorder\n\
2794 bal 1f\n\
2795 nop\n\
2796 1: .cpload $31\n\
2797 .set reorder\n\
2798 jal " USER_LABEL_PREFIX #FUNC "\n\
2799 " TEXT_SECTION_ASM_OP);
2800 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2801 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2802 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2803 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2804 asm (SECTION_OP "\n\
2805 .set noreorder\n\
2806 bal 1f\n\
2807 nop\n\
2808 1: .set reorder\n\
2809 .cpsetup $31, $2, 1b\n\
2810 jal " USER_LABEL_PREFIX #FUNC "\n\
2811 " TEXT_SECTION_ASM_OP);
2812 #endif
2813 #endif
2814
2815 #ifndef HAVE_AS_TLS
2816 #define HAVE_AS_TLS 0
2817 #endif
2818
2819 #ifndef USED_FOR_TARGET
2820 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2821 struct mips_asm_switch {
2822 /* The FOO in the description above. */
2823 const char *name;
2824
2825 /* The current block nesting level, or 0 if we aren't in a block. */
2826 int nesting_level;
2827 };
2828
2829 extern const enum reg_class mips_regno_to_class[];
2830 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2831 extern const char *current_function_file; /* filename current function is in */
2832 extern int num_source_filenames; /* current .file # */
2833 extern struct mips_asm_switch mips_noreorder;
2834 extern struct mips_asm_switch mips_nomacro;
2835 extern struct mips_asm_switch mips_noat;
2836 extern int mips_dbx_regno[];
2837 extern int mips_dwarf_regno[];
2838 extern bool mips_split_p[];
2839 extern bool mips_split_hi_p[];
2840 extern bool mips_use_pcrel_pool_p[];
2841 extern const char *mips_lo_relocs[];
2842 extern const char *mips_hi_relocs[];
2843 extern enum processor mips_arch; /* which cpu to codegen for */
2844 extern enum processor mips_tune; /* which cpu to schedule for */
2845 extern int mips_isa; /* architectural level */
2846 extern const struct mips_cpu_info *mips_arch_info;
2847 extern const struct mips_cpu_info *mips_tune_info;
2848 extern bool mips_base_mips16;
2849 extern GTY(()) struct target_globals *mips16_globals;
2850 #endif
2851
2852 /* Enable querying of DFA units. */
2853 #define CPU_UNITS_QUERY 1
2854
2855 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2856 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2857
2858 /* As on most targets, we want the .eh_frame section to be read-only where
2859 possible. And as on most targets, this means two things:
2860
2861 (a) Non-locally-binding pointers must have an indirect encoding,
2862 so that the addresses in the .eh_frame section itself become
2863 locally-binding.
2864
2865 (b) A shared library's .eh_frame section must encode locally-binding
2866 pointers in a relative (relocation-free) form.
2867
2868 However, MIPS has traditionally not allowed directives like:
2869
2870 .long x-.
2871
2872 in cases where "x" is in a different section, or is not defined in the
2873 same assembly file. We are therefore unable to emit the PC-relative
2874 form required by (b) at assembly time.
2875
2876 Fortunately, the linker is able to convert absolute addresses into
2877 PC-relative addresses on our behalf. Unfortunately, only certain
2878 versions of the linker know how to do this for indirect pointers,
2879 and for personality data. We must fall back on using writable
2880 .eh_frame sections for shared libraries if the linker does not
2881 support this feature. */
2882 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2883 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2884
2885 /* For switching between MIPS16 and non-MIPS16 modes. */
2886 #define SWITCHABLE_TARGET 1
2887
2888 /* Several named MIPS patterns depend on Pmode. These patterns have the
2889 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2890 Add the appropriate suffix to generator function NAME and invoke it
2891 with arguments ARGS. */
2892 #define PMODE_INSN(NAME, ARGS) \
2893 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)