projects / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
expr.h (move_by_pieces_ninsns): Declare.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 #ifdef GENERATOR_FILE
30 /* This is used in some insn conditions, so needs to be declared, but
31 does not need to be defined. */
32 extern int target_flags_explicit;
33 #endif
34
35 /* MIPS external variables defined in mips.c. */
36
37 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
38 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
39 to work on a 64-bit machine. */
40
41 #define ABI_32 0
42 #define ABI_N32 1
43 #define ABI_64 2
44 #define ABI_EABI 3
45 #define ABI_O64 4
46
47 /* Masks that affect tuning.
48
49 PTF_AVOID_BRANCHLIKELY
50 Set if it is usually not profitable to use branch-likely instructions
51 for this target, typically because the branches are always predicted
52 taken and so incur a large overhead when not taken. */
53 #define PTF_AVOID_BRANCHLIKELY 0x1
54
55 /* Information about one recognized processor. Defined here for the
56 benefit of TARGET_CPU_CPP_BUILTINS. */
57 struct mips_cpu_info {
58 /* The 'canonical' name of the processor as far as GCC is concerned.
59 It's typically a manufacturer's prefix followed by a numerical
60 designation. It should be lowercase. */
61 const char *name;
62
63 /* The internal processor number that most closely matches this
64 entry. Several processors can have the same value, if there's no
65 difference between them from GCC's point of view. */
66 enum processor cpu;
67
68 /* The ISA level that the processor implements. */
69 int isa;
70
71 /* A mask of PTF_* values. */
72 unsigned int tune_flags;
73 };
74
75 #include "config/mips/mips-opts.h"
76
77 /* Macros to silence warnings about numbers being signed in traditional
78 C and unsigned in ISO C when compiled on 32-bit hosts. */
79
80 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
81 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
82 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
83
84 \f
85 /* Run-time compilation parameters selecting different hardware subsets. */
86
87 /* True if we are generating position-independent VxWorks RTP code. */
88 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
89
90 /* True if the output file is marked as ".abicalls; .option pic0"
91 (-call_nonpic). */
92 #define TARGET_ABICALLS_PIC0 \
93 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
94
95 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
96 #define TARGET_ABICALLS_PIC2 \
97 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
98
99 /* True if the call patterns should be split into a jalr followed by
100 an instruction to restore $gp. It is only safe to split the load
101 from the call when every use of $gp is explicit.
102
103 See mips_must_initialize_gp_p for details about how we manage the
104 global pointer. */
105
106 #define TARGET_SPLIT_CALLS \
107 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
108
109 /* True if we're generating a form of -mabicalls in which we can use
110 operators like %hi and %lo to refer to locally-binding symbols.
111 We can only do this for -mno-shared, and only then if we can use
112 relocation operations instead of assembly macros. It isn't really
113 worth using absolute sequences for 64-bit symbols because GOT
114 accesses are so much shorter. */
115
116 #define TARGET_ABSOLUTE_ABICALLS \
117 (TARGET_ABICALLS \
118 && !TARGET_SHARED \
119 && TARGET_EXPLICIT_RELOCS \
120 && !ABI_HAS_64BIT_SYMBOLS)
121
122 /* True if we can optimize sibling calls. For simplicity, we only
123 handle cases in which call_insn_operand will reject invalid
124 sibcall addresses. There are two cases in which this isn't true:
125
126 - TARGET_MIPS16. call_insn_operand accepts constant addresses
127 but there is no direct jump instruction. It isn't worth
128 using sibling calls in this case anyway; they would usually
129 be longer than normal calls.
130
131 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
132 accepts global constants, but all sibcalls must be indirect. */
133 #define TARGET_SIBCALLS \
134 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
135
136 /* True if we need to use a global offset table to access some symbols. */
137 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
138
139 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
140 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
141
142 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
143 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
144
145 /* True if we should use .cprestore to store to the cprestore slot.
146
147 We continue to use .cprestore for explicit-reloc code so that JALs
148 inside inline asms will work correctly. */
149 #define TARGET_CPRESTORE_DIRECTIVE \
150 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
151
152 /* True if we can use the J and JAL instructions. */
153 #define TARGET_ABSOLUTE_JUMPS \
154 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
155
156 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
157 This is true for both the PIC and non-PIC VxWorks RTP modes. */
158 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
159
160 /* True if .gpword or .gpdword should be used for switch tables.
161
162 Although GAS does understand .gpdword, the SGI linker mishandles
163 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
164 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
165 #define TARGET_GPWORD \
166 (TARGET_ABICALLS \
167 && !TARGET_ABSOLUTE_ABICALLS \
168 && !(mips_abi == ABI_64 && TARGET_IRIX6))
169
170 /* True if the output must have a writable .eh_frame.
171 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
172 #ifdef HAVE_LD_PERSONALITY_RELAXATION
173 #define TARGET_WRITABLE_EH_FRAME 0
174 #else
175 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
176 #endif
177
178 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
179 #ifdef HAVE_AS_DSPR1_MULT
180 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
181 #else
182 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
183 #endif
184
185 /* Generate mips16 code */
186 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
187 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
188 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
189 /* Generate mips16e register save/restore sequences. */
190 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
191
192 /* True if we're generating a form of MIPS16 code in which general
193 text loads are allowed. */
194 #define TARGET_MIPS16_TEXT_LOADS \
195 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
196
197 /* True if we're generating a form of MIPS16 code in which PC-relative
198 loads are allowed. */
199 #define TARGET_MIPS16_PCREL_LOADS \
200 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
201
202 /* Generic ISA defines. */
203 #define ISA_MIPS1 (mips_isa == 1)
204 #define ISA_MIPS2 (mips_isa == 2)
205 #define ISA_MIPS3 (mips_isa == 3)
206 #define ISA_MIPS4 (mips_isa == 4)
207 #define ISA_MIPS32 (mips_isa == 32)
208 #define ISA_MIPS32R2 (mips_isa == 33)
209 #define ISA_MIPS64 (mips_isa == 64)
210 #define ISA_MIPS64R2 (mips_isa == 65)
211
212 /* Architecture target defines. */
213 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
214 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
215 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
216 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
217 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
218 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
219 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
220 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
221 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
222 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
223 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
224 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
225 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
226 || mips_arch == PROCESSOR_OCTEON2)
227 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
228 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
229 || mips_arch == PROCESSOR_SB1A)
230 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
231
232 /* Scheduling target defines. */
233 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
234 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
235 || mips_tune == PROCESSOR_24KF2_1 \
236 || mips_tune == PROCESSOR_24KF1_1)
237 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
238 || mips_tune == PROCESSOR_74KF2_1 \
239 || mips_tune == PROCESSOR_74KF1_1 \
240 || mips_tune == PROCESSOR_74KF3_2)
241 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
242 || mips_tune == PROCESSOR_LOONGSON_2F)
243 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
244 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
245 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
246 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
247 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
248 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
249 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
250 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
251 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
252 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
253 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
254 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
255 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
256 || mips_tune == PROCESSOR_OCTEON2)
257 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
258 || mips_tune == PROCESSOR_SB1A)
259
260 /* Whether vector modes and intrinsics for ST Microelectronics
261 Loongson-2E/2F processors should be enabled. In o32 pairs of
262 floating-point registers provide 64-bit values. */
263 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
264 && (TARGET_LOONGSON_2EF \
265 || TARGET_LOONGSON_3A))
266
267 /* True if the pre-reload scheduler should try to create chains of
268 multiply-add or multiply-subtract instructions. For example,
269 suppose we have:
270
271 t1 = a * b
272 t2 = t1 + c * d
273 t3 = e * f
274 t4 = t3 - g * h
275
276 t1 will have a higher priority than t2 and t3 will have a higher
277 priority than t4. However, before reload, there is no dependence
278 between t1 and t3, and they can often have similar priorities.
279 The scheduler will then tend to prefer:
280
281 t1 = a * b
282 t3 = e * f
283 t2 = t1 + c * d
284 t4 = t3 - g * h
285
286 which stops us from making full use of macc/madd-style instructions.
287 This sort of situation occurs frequently in Fourier transforms and
288 in unrolled loops.
289
290 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
291 queue so that chained multiply-add and multiply-subtract instructions
292 appear ahead of any other instruction that is likely to clobber lo.
293 In the example above, if t2 and t3 become ready at the same time,
294 the code ensures that t2 is scheduled first.
295
296 Multiply-accumulate instructions are a bigger win for some targets
297 than others, so this macro is defined on an opt-in basis. */
298 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
299 || TUNE_MIPS4120 \
300 || TUNE_MIPS4130 \
301 || TUNE_24K)
302
303 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
304 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
305
306 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
307 directly accessible, while the command-line options select
308 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
309 in use. */
310 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
311 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
312
313 /* False if SC acts as a memory barrier with respect to itself,
314 otherwise a SYNC will be emitted after SC for atomic operations
315 that require ordering between the SC and following loads and
316 stores. It does not tell anything about ordering of loads and
317 stores prior to and following the SC, only about the SC itself and
318 those loads and stores follow it. */
319 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
320
321 /* IRIX specific stuff. */
322 #define TARGET_IRIX6 0
323
324 /* Define preprocessor macros for the -march and -mtune options.
325 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
326 processor. If INFO's canonical name is "foo", define PREFIX to
327 be "foo", and define an additional macro PREFIX_FOO. */
328 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
329 do \
330 { \
331 char *macro, *p; \
332 \
333 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
334 for (p = macro; *p != 0; p++) \
335 if (*p == '+') \
336 *p = 'P'; \
337 else \
338 *p = TOUPPER (*p); \
339 \
340 builtin_define (macro); \
341 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
342 free (macro); \
343 } \
344 while (0)
345
346 /* Target CPU builtins. */
347 #define TARGET_CPU_CPP_BUILTINS() \
348 do \
349 { \
350 /* Everyone but IRIX defines this to mips. */ \
351 if (!TARGET_IRIX6) \
352 builtin_assert ("machine=mips"); \
353 \
354 builtin_assert ("cpu=mips"); \
355 builtin_define ("__mips__"); \
356 builtin_define ("_mips"); \
357 \
358 /* We do this here because __mips is defined below and so we \
359 can't use builtin_define_std. We don't ever want to define \
360 "mips" for VxWorks because some of the VxWorks headers \
361 construct include filenames from a root directory macro, \
362 an architecture macro and a filename, where the architecture \
363 macro expands to 'mips'. If we define 'mips' to 1, the \
364 architecture macro expands to 1 as well. */ \
365 if (!flag_iso && !TARGET_VXWORKS) \
366 builtin_define ("mips"); \
367 \
368 if (TARGET_64BIT) \
369 builtin_define ("__mips64"); \
370 \
371 if (!TARGET_IRIX6) \
372 { \
373 /* Treat _R3000 and _R4000 like register-size \
374 defines, which is how they've historically \
375 been used. */ \
376 if (TARGET_64BIT) \
377 { \
378 builtin_define_std ("R4000"); \
379 builtin_define ("_R4000"); \
380 } \
381 else \
382 { \
383 builtin_define_std ("R3000"); \
384 builtin_define ("_R3000"); \
385 } \
386 } \
387 if (TARGET_FLOAT64) \
388 builtin_define ("__mips_fpr=64"); \
389 else \
390 builtin_define ("__mips_fpr=32"); \
391 \
392 if (mips_base_mips16) \
393 builtin_define ("__mips16"); \
394 \
395 if (TARGET_MIPS3D) \
396 builtin_define ("__mips3d"); \
397 \
398 if (TARGET_SMARTMIPS) \
399 builtin_define ("__mips_smartmips"); \
400 \
401 if (TARGET_DSP) \
402 { \
403 builtin_define ("__mips_dsp"); \
404 if (TARGET_DSPR2) \
405 { \
406 builtin_define ("__mips_dspr2"); \
407 builtin_define ("__mips_dsp_rev=2"); \
408 } \
409 else \
410 builtin_define ("__mips_dsp_rev=1"); \
411 } \
412 \
413 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
414 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
415 \
416 if (ISA_MIPS1) \
417 { \
418 builtin_define ("__mips=1"); \
419 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
420 } \
421 else if (ISA_MIPS2) \
422 { \
423 builtin_define ("__mips=2"); \
424 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
425 } \
426 else if (ISA_MIPS3) \
427 { \
428 builtin_define ("__mips=3"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
430 } \
431 else if (ISA_MIPS4) \
432 { \
433 builtin_define ("__mips=4"); \
434 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
435 } \
436 else if (ISA_MIPS32) \
437 { \
438 builtin_define ("__mips=32"); \
439 builtin_define ("__mips_isa_rev=1"); \
440 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
441 } \
442 else if (ISA_MIPS32R2) \
443 { \
444 builtin_define ("__mips=32"); \
445 builtin_define ("__mips_isa_rev=2"); \
446 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
447 } \
448 else if (ISA_MIPS64) \
449 { \
450 builtin_define ("__mips=64"); \
451 builtin_define ("__mips_isa_rev=1"); \
452 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
453 } \
454 else if (ISA_MIPS64R2) \
455 { \
456 builtin_define ("__mips=64"); \
457 builtin_define ("__mips_isa_rev=2"); \
458 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
459 } \
460 \
461 switch (mips_abi) \
462 { \
463 case ABI_32: \
464 builtin_define ("_ABIO32=1"); \
465 builtin_define ("_MIPS_SIM=_ABIO32"); \
466 break; \
467 \
468 case ABI_N32: \
469 builtin_define ("_ABIN32=2"); \
470 builtin_define ("_MIPS_SIM=_ABIN32"); \
471 break; \
472 \
473 case ABI_64: \
474 builtin_define ("_ABI64=3"); \
475 builtin_define ("_MIPS_SIM=_ABI64"); \
476 break; \
477 \
478 case ABI_O64: \
479 builtin_define ("_ABIO64=4"); \
480 builtin_define ("_MIPS_SIM=_ABIO64"); \
481 break; \
482 } \
483 \
484 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
485 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
486 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
487 builtin_define_with_int_value ("_MIPS_FPSET", \
488 32 / MAX_FPRS_PER_FMT); \
489 \
490 /* These defines reflect the ABI in use, not whether the \
491 FPU is directly accessible. */ \
492 if (TARGET_NO_FLOAT) \
493 builtin_define ("__mips_no_float"); \
494 else if (TARGET_HARD_FLOAT_ABI) \
495 builtin_define ("__mips_hard_float"); \
496 else \
497 builtin_define ("__mips_soft_float"); \
498 \
499 if (TARGET_SINGLE_FLOAT) \
500 builtin_define ("__mips_single_float"); \
501 \
502 if (TARGET_PAIRED_SINGLE_FLOAT) \
503 builtin_define ("__mips_paired_single_float"); \
504 \
505 if (TARGET_BIG_ENDIAN) \
506 { \
507 builtin_define_std ("MIPSEB"); \
508 builtin_define ("_MIPSEB"); \
509 } \
510 else \
511 { \
512 builtin_define_std ("MIPSEL"); \
513 builtin_define ("_MIPSEL"); \
514 } \
515 \
516 /* Whether calls should go through $25. The separate __PIC__ \
517 macro indicates whether abicalls code might use a GOT. */ \
518 if (TARGET_ABICALLS) \
519 builtin_define ("__mips_abicalls"); \
520 \
521 /* Whether Loongson vector modes are enabled. */ \
522 if (TARGET_LOONGSON_VECTORS) \
523 builtin_define ("__mips_loongson_vector_rev"); \
524 \
525 /* Historical Octeon macro. */ \
526 if (TARGET_OCTEON) \
527 builtin_define ("__OCTEON__"); \
528 \
529 /* Macros dependent on the C dialect. */ \
530 if (preprocessing_asm_p ()) \
531 { \
532 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
533 builtin_define ("_LANGUAGE_ASSEMBLY"); \
534 } \
535 else if (c_dialect_cxx ()) \
536 { \
537 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
538 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
539 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
540 } \
541 else \
542 { \
543 builtin_define_std ("LANGUAGE_C"); \
544 builtin_define ("_LANGUAGE_C"); \
545 } \
546 if (c_dialect_objc ()) \
547 { \
548 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
549 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
550 /* Bizarre, but needed at least for Irix. */ \
551 builtin_define_std ("LANGUAGE_C"); \
552 builtin_define ("_LANGUAGE_C"); \
553 } \
554 \
555 if (mips_abi == ABI_EABI) \
556 builtin_define ("__mips_eabi"); \
557 \
558 if (TARGET_CACHE_BUILTIN) \
559 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
560 } \
561 while (0)
562
563 /* Default target_flags if no switches are specified */
564
565 #ifndef TARGET_DEFAULT
566 #define TARGET_DEFAULT 0
567 #endif
568
569 #ifndef TARGET_CPU_DEFAULT
570 #define TARGET_CPU_DEFAULT 0
571 #endif
572
573 #ifndef TARGET_ENDIAN_DEFAULT
574 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
575 #endif
576
577 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
578 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
579 #endif
580
581 #ifdef IN_LIBGCC2
582 #undef TARGET_64BIT
583 /* Make this compile time constant for libgcc2 */
584 #ifdef __mips64
585 #define TARGET_64BIT 1
586 #else
587 #define TARGET_64BIT 0
588 #endif
589 #endif /* IN_LIBGCC2 */
590
591 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
592 when compiled with hardware floating point. This is because MIPS16
593 code cannot save and restore the floating-point registers, which is
594 important if in a mixed MIPS16/non-MIPS16 environment. */
595
596 #ifdef IN_LIBGCC2
597 #if __mips_hard_float
598 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
599 #endif
600 #endif /* IN_LIBGCC2 */
601
602 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
603
604 #ifndef MULTILIB_ENDIAN_DEFAULT
605 #if TARGET_ENDIAN_DEFAULT == 0
606 #define MULTILIB_ENDIAN_DEFAULT "EL"
607 #else
608 #define MULTILIB_ENDIAN_DEFAULT "EB"
609 #endif
610 #endif
611
612 #ifndef MULTILIB_ISA_DEFAULT
613 # if MIPS_ISA_DEFAULT == 1
614 # define MULTILIB_ISA_DEFAULT "mips1"
615 # else
616 # if MIPS_ISA_DEFAULT == 2
617 # define MULTILIB_ISA_DEFAULT "mips2"
618 # else
619 # if MIPS_ISA_DEFAULT == 3
620 # define MULTILIB_ISA_DEFAULT "mips3"
621 # else
622 # if MIPS_ISA_DEFAULT == 4
623 # define MULTILIB_ISA_DEFAULT "mips4"
624 # else
625 # if MIPS_ISA_DEFAULT == 32
626 # define MULTILIB_ISA_DEFAULT "mips32"
627 # else
628 # if MIPS_ISA_DEFAULT == 33
629 # define MULTILIB_ISA_DEFAULT "mips32r2"
630 # else
631 # if MIPS_ISA_DEFAULT == 64
632 # define MULTILIB_ISA_DEFAULT "mips64"
633 # else
634 # if MIPS_ISA_DEFAULT == 65
635 # define MULTILIB_ISA_DEFAULT "mips64r2"
636 # else
637 # define MULTILIB_ISA_DEFAULT "mips1"
638 # endif
639 # endif
640 # endif
641 # endif
642 # endif
643 # endif
644 # endif
645 # endif
646 #endif
647
648 #ifndef MIPS_ABI_DEFAULT
649 #define MIPS_ABI_DEFAULT ABI_32
650 #endif
651
652 /* Use the most portable ABI flag for the ASM specs. */
653
654 #if MIPS_ABI_DEFAULT == ABI_32
655 #define MULTILIB_ABI_DEFAULT "mabi=32"
656 #endif
657
658 #if MIPS_ABI_DEFAULT == ABI_O64
659 #define MULTILIB_ABI_DEFAULT "mabi=o64"
660 #endif
661
662 #if MIPS_ABI_DEFAULT == ABI_N32
663 #define MULTILIB_ABI_DEFAULT "mabi=n32"
664 #endif
665
666 #if MIPS_ABI_DEFAULT == ABI_64
667 #define MULTILIB_ABI_DEFAULT "mabi=64"
668 #endif
669
670 #if MIPS_ABI_DEFAULT == ABI_EABI
671 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
672 #endif
673
674 #ifndef MULTILIB_DEFAULTS
675 #define MULTILIB_DEFAULTS \
676 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
677 #endif
678
679 /* We must pass -EL to the linker by default for little endian embedded
680 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
681 linker will default to using big-endian output files. The OUTPUT_FORMAT
682 line must be in the linker script, otherwise -EB/-EL will not work. */
683
684 #ifndef ENDIAN_SPEC
685 #if TARGET_ENDIAN_DEFAULT == 0
686 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
687 #else
688 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
689 #endif
690 #endif
691
692 /* A spec condition that matches all non-mips16 -mips arguments. */
693
694 #define MIPS_ISA_LEVEL_OPTION_SPEC \
695 "mips1|mips2|mips3|mips4|mips32*|mips64*"
696
697 /* A spec condition that matches all non-mips16 architecture arguments. */
698
699 #define MIPS_ARCH_OPTION_SPEC \
700 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
701
702 /* A spec that infers a -mips argument from an -march argument,
703 or injects the default if no architecture is specified. */
704
705 #define MIPS_ISA_LEVEL_SPEC \
706 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
707 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
708 %{march=mips2|march=r6000:-mips2} \
709 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
710 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
711 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
712 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
713 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
714 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
715 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
716 |march=xlr|march=loongson3a: -mips64} \
717 %{march=mips64r2|march=octeon: -mips64r2} \
718 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
719
720 /* A spec that infers a -mhard-float or -msoft-float setting from an
721 -march argument. Note that soft-float and hard-float code are not
722 link-compatible. */
723
724 #define MIPS_ARCH_FLOAT_SPEC \
725 "%{mhard-float|msoft-float|march=mips*:; \
726 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
727 |march=34kc|march=74kc|march=1004kc|march=5kc \
728 |march=octeon|march=xlr: -msoft-float; \
729 march=*: -mhard-float}"
730
731 /* A spec condition that matches 32-bit options. It only works if
732 MIPS_ISA_LEVEL_SPEC has been applied. */
733
734 #define MIPS_32BIT_OPTION_SPEC \
735 "mips1|mips2|mips32*|mgp32"
736
737 #if MIPS_ABI_DEFAULT == ABI_O64 \
738 || MIPS_ABI_DEFAULT == ABI_N32 \
739 || MIPS_ABI_DEFAULT == ABI_64
740 #define OPT_ARCH64 "mabi=32|mgp32:;"
741 #define OPT_ARCH32 "mabi=32|mgp32"
742 #else
743 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
744 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
745 #endif
746
747 /* Support for a compile-time default CPU, et cetera. The rules are:
748 --with-arch is ignored if -march is specified or a -mips is specified
749 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
750 --with-tune is ignored if -mtune is specified; likewise
751 --with-tune-32 and --with-tune-64.
752 --with-abi is ignored if -mabi is specified.
753 --with-float is ignored if -mhard-float or -msoft-float are
754 specified.
755 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
756 specified. */
757 #define OPTION_DEFAULT_SPECS \
758 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
759 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
760 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
761 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
762 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
763 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
764 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
765 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
766 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
767 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
768 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
769 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
770
771
772 /* A spec that infers the -mdsp setting from an -march argument. */
773 #define BASE_DRIVER_SELF_SPECS \
774 "%{!mno-dsp: \
775 %{march=24ke*|march=34k*|march=1004k*: -mdsp} \
776 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
777
778 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
779
780 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
781 && ISA_HAS_COND_TRAP)
782
783 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
784
785 /* True if the ABI can only work with 64-bit integer registers. We
786 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
787 otherwise floating-point registers must also be 64-bit. */
788 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
789
790 /* Likewise for 32-bit regs. */
791 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
792
793 /* True if the file format uses 64-bit symbols. At present, this is
794 only true for n64, which uses 64-bit ELF. */
795 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
796
797 /* True if symbols are 64 bits wide. This is usually determined by
798 the ABI's file format, but it can be overridden by -msym32. Note that
799 overriding the size with -msym32 changes the ABI of relocatable objects,
800 although it doesn't change the ABI of a fully-linked object. */
801 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
802 && Pmode == DImode \
803 && !TARGET_SYM32)
804
805 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
806 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
807 || ISA_MIPS4 \
808 || ISA_MIPS64 \
809 || ISA_MIPS64R2)
810
811 /* ISA has branch likely instructions (e.g. mips2). */
812 /* Disable branchlikely for tx39 until compare rewrite. They haven't
813 been generated up to this point. */
814 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
815
816 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
817 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
818 || TARGET_MIPS5400 \
819 || TARGET_MIPS5500 \
820 || TARGET_MIPS7000 \
821 || TARGET_MIPS9000 \
822 || TARGET_MAD \
823 || ISA_MIPS32 \
824 || ISA_MIPS32R2 \
825 || ISA_MIPS64 \
826 || ISA_MIPS64R2) \
827 && !TARGET_MIPS16)
828
829 /* ISA has a three-operand multiplication instruction. */
830 #define ISA_HAS_DMUL3 (TARGET_64BIT \
831 && TARGET_OCTEON \
832 && !TARGET_MIPS16)
833
834 /* ISA has the floating-point conditional move instructions introduced
835 in mips4. */
836 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
837 || ISA_MIPS32 \
838 || ISA_MIPS32R2 \
839 || ISA_MIPS64 \
840 || ISA_MIPS64R2) \
841 && !TARGET_MIPS5500 \
842 && !TARGET_MIPS16)
843
844 /* ISA has the integer conditional move instructions introduced in mips4 and
845 ST Loongson 2E/2F. */
846 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
847
848 /* ISA has LDC1 and SDC1. */
849 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
850
851 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
852 branch on CC, and move (both FP and non-FP) on CC. */
853 #define ISA_HAS_8CC (ISA_MIPS4 \
854 || ISA_MIPS32 \
855 || ISA_MIPS32R2 \
856 || ISA_MIPS64 \
857 || ISA_MIPS64R2)
858
859 /* This is a catch all for other mips4 instructions: indexed load, the
860 FP madd and msub instructions, and the FP recip and recip sqrt
861 instructions. */
862 #define ISA_HAS_FP4 ((ISA_MIPS4 \
863 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
864 || ISA_MIPS64 \
865 || ISA_MIPS64R2) \
866 && !TARGET_MIPS16)
867
868 /* ISA has paired-single instructions. */
869 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
870
871 /* ISA has conditional trap instructions. */
872 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
873 && !TARGET_MIPS16)
874
875 /* ISA has integer multiply-accumulate instructions, madd and msub. */
876 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
877 || ISA_MIPS32R2 \
878 || ISA_MIPS64 \
879 || ISA_MIPS64R2) \
880 && !TARGET_MIPS16)
881
882 /* Integer multiply-accumulate instructions should be generated. */
883 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
884
885 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
886 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
887
888 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
889 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
890
891 /* ISA has floating-point nmadd and nmsub instructions
892 'd = -((a * b) [+-] c)'. */
893 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
894 ((ISA_MIPS4 \
895 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
896 || ISA_MIPS64 \
897 || ISA_MIPS64R2) \
898 && (!TARGET_MIPS5400 || TARGET_MAD) \
899 && !TARGET_MIPS16)
900
901 /* ISA has floating-point nmadd and nmsub instructions
902 'c = -((a * b) [+-] c)'. */
903 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
904 TARGET_LOONGSON_2EF
905
906 /* ISA has count leading zeroes/ones instruction (not implemented). */
907 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
908 || ISA_MIPS32R2 \
909 || ISA_MIPS64 \
910 || ISA_MIPS64R2) \
911 && !TARGET_MIPS16)
912
913 /* ISA has three operand multiply instructions that put
914 the high part in an accumulator: mulhi or mulhiu. */
915 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
916 || TARGET_MIPS5500 \
917 || TARGET_SR71K) \
918 && !TARGET_MIPS16)
919
920 /* ISA has three operand multiply instructions that
921 negates the result and puts the result in an accumulator. */
922 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
923 || TARGET_MIPS5500 \
924 || TARGET_SR71K) \
925 && !TARGET_MIPS16)
926
927 /* ISA has three operand multiply instructions that subtracts the
928 result from a 4th operand and puts the result in an accumulator. */
929 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
930 || TARGET_MIPS5500 \
931 || TARGET_SR71K) \
932 && !TARGET_MIPS16)
933
934 /* ISA has three operand multiply instructions that the result
935 from a 4th operand and puts the result in an accumulator. */
936 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
937 || TARGET_MIPS4130 \
938 || TARGET_MIPS5400 \
939 || TARGET_MIPS5500 \
940 || TARGET_SR71K) \
941 && !TARGET_MIPS16)
942
943 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
944 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
945 || TARGET_MIPS4130) \
946 && !TARGET_MIPS16)
947
948 /* ISA has the "ror" (rotate right) instructions. */
949 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
950 || ISA_MIPS64R2 \
951 || TARGET_MIPS5400 \
952 || TARGET_MIPS5500 \
953 || TARGET_SR71K \
954 || TARGET_SMARTMIPS) \
955 && !TARGET_MIPS16)
956
957 /* ISA has data prefetch instructions. This controls use of 'pref'. */
958 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
959 || TARGET_LOONGSON_2EF \
960 || ISA_MIPS32 \
961 || ISA_MIPS32R2 \
962 || ISA_MIPS64 \
963 || ISA_MIPS64R2) \
964 && !TARGET_MIPS16)
965
966 /* ISA has data indexed prefetch instructions. This controls use of
967 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
968 (prefx is a cop1x instruction, so can only be used if FP is
969 enabled.) */
970 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
971 || ISA_MIPS32R2 \
972 || ISA_MIPS64 \
973 || ISA_MIPS64R2) \
974 && !TARGET_MIPS16)
975
976 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
977 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
978 also requires TARGET_DOUBLE_FLOAT. */
979 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
980
981 /* ISA includes the MIPS32r2 seb and seh instructions. */
982 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
983 || ISA_MIPS64R2) \
984 && !TARGET_MIPS16)
985
986 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
987 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
988 || ISA_MIPS64R2) \
989 && !TARGET_MIPS16)
990
991 /* ISA has instructions for accessing top part of 64-bit fp regs. */
992 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
993 && (ISA_MIPS32R2 \
994 || ISA_MIPS64R2))
995
996 /* ISA has lwxs instruction (load w/scaled index address. */
997 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
998
999 /* The DSP ASE is available. */
1000 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1001
1002 /* Revision 2 of the DSP ASE is available. */
1003 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1004
1005 /* True if the result of a load is not available to the next instruction.
1006 A nop will then be needed between instructions like "lw $4,..."
1007 and "addiu $4,$4,1". */
1008 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1009 && !TARGET_MIPS3900 \
1010 && !TARGET_MIPS16)
1011
1012 /* Likewise mtc1 and mfc1. */
1013 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1014 && !TARGET_LOONGSON_2EF)
1015
1016 /* Likewise floating-point comparisons. */
1017 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1018 && !TARGET_LOONGSON_2EF)
1019
1020 /* True if mflo and mfhi can be immediately followed by instructions
1021 which write to the HI and LO registers.
1022
1023 According to MIPS specifications, MIPS ISAs I, II, and III need
1024 (at least) two instructions between the reads of HI/LO and
1025 instructions which write them, and later ISAs do not. Contradicting
1026 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1027 the UM for the NEC Vr5000) document needing the instructions between
1028 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1029 MIPS64 and later ISAs to have the interlocks, plus any specific
1030 earlier-ISA CPUs for which CPU documentation declares that the
1031 instructions are really interlocked. */
1032 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1033 || ISA_MIPS32R2 \
1034 || ISA_MIPS64 \
1035 || ISA_MIPS64R2 \
1036 || TARGET_MIPS5500 \
1037 || TARGET_LOONGSON_2EF)
1038
1039 /* ISA includes synci, jr.hb and jalr.hb. */
1040 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1041 || ISA_MIPS64R2) \
1042 && !TARGET_MIPS16)
1043
1044 /* ISA includes sync. */
1045 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1046 #define GENERATE_SYNC \
1047 (target_flags_explicit & MASK_LLSC \
1048 ? TARGET_LLSC && !TARGET_MIPS16 \
1049 : ISA_HAS_SYNC)
1050
1051 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1052 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1053 instructions. */
1054 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1055 #define GENERATE_LL_SC \
1056 (target_flags_explicit & MASK_LLSC \
1057 ? TARGET_LLSC && !TARGET_MIPS16 \
1058 : ISA_HAS_LL_SC)
1059
1060 /* ISA includes the baddu instruction. */
1061 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1062
1063 /* ISA includes the bbit* instructions. */
1064 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1065
1066 /* ISA includes the cins instruction. */
1067 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1068
1069 /* ISA includes the exts instruction. */
1070 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1071
1072 /* ISA includes the seq and sne instructions. */
1073 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1074
1075 /* ISA includes the pop instruction. */
1076 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1077
1078 /* The CACHE instruction is available in non-MIPS16 code. */
1079 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1080
1081 /* The CACHE instruction is available. */
1082 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1083 \f
1084 /* Tell collect what flags to pass to nm. */
1085 #ifndef NM_FLAGS
1086 #define NM_FLAGS "-Bn"
1087 #endif
1088
1089 \f
1090 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1091 the assembler. It may be overridden by subtargets.
1092
1093 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1094 COFF debugging info. */
1095
1096 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1097 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1098 %{g} %{g0} %{g1} %{g2} %{g3} \
1099 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1100 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1101 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1102 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1103 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1104 #endif
1105
1106 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1107 overridden by subtargets. */
1108
1109 #ifndef SUBTARGET_ASM_SPEC
1110 #define SUBTARGET_ASM_SPEC ""
1111 #endif
1112
1113 #undef ASM_SPEC
1114 #define ASM_SPEC "\
1115 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1116 %{mips32*} %{mips64*} \
1117 %{mips16} %{mno-mips16:-no-mips16} \
1118 %{mips3d} %{mno-mips3d:-no-mips3d} \
1119 %{mdmx} %{mno-mdmx:-no-mdmx} \
1120 %{mdsp} %{mno-dsp} \
1121 %{mdspr2} %{mno-dspr2} \
1122 %{msmartmips} %{mno-smartmips} \
1123 %{mmt} %{mno-mt} \
1124 %{mfix-vr4120} %{mfix-vr4130} \
1125 %{mfix-24k} \
1126 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1127 %(subtarget_asm_debugging_spec) \
1128 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1129 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1130 %{mfp32} %{mfp64} \
1131 %{mshared} %{mno-shared} \
1132 %{msym32} %{mno-sym32} \
1133 %{mtune=*} \
1134 %(subtarget_asm_spec)"
1135
1136 /* Extra switches sometimes passed to the linker. */
1137
1138 #ifndef LINK_SPEC
1139 #define LINK_SPEC "\
1140 %(endian_spec) \
1141 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1142 %{shared}"
1143 #endif /* LINK_SPEC defined */
1144
1145
1146 /* Specs for the compiler proper */
1147
1148 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1149 overridden by subtargets. */
1150 #ifndef SUBTARGET_CC1_SPEC
1151 #define SUBTARGET_CC1_SPEC ""
1152 #endif
1153
1154 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1155
1156 #undef CC1_SPEC
1157 #define CC1_SPEC "\
1158 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1159 %(subtarget_cc1_spec)"
1160
1161 /* Preprocessor specs. */
1162
1163 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1164 overridden by subtargets. */
1165 #ifndef SUBTARGET_CPP_SPEC
1166 #define SUBTARGET_CPP_SPEC ""
1167 #endif
1168
1169 #define CPP_SPEC "%(subtarget_cpp_spec)"
1170
1171 /* This macro defines names of additional specifications to put in the specs
1172 that can be used in various specifications like CC1_SPEC. Its definition
1173 is an initializer with a subgrouping for each command option.
1174
1175 Each subgrouping contains a string constant, that defines the
1176 specification name, and a string constant that used by the GCC driver
1177 program.
1178
1179 Do not define this macro if it does not need to do anything. */
1180
1181 #define EXTRA_SPECS \
1182 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1183 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1184 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1185 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1186 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1187 { "endian_spec", ENDIAN_SPEC }, \
1188 SUBTARGET_EXTRA_SPECS
1189
1190 #ifndef SUBTARGET_EXTRA_SPECS
1191 #define SUBTARGET_EXTRA_SPECS
1192 #endif
1193 \f
1194 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1195 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1196
1197 #ifndef PREFERRED_DEBUGGING_TYPE
1198 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1199 #endif
1200
1201 /* The size of DWARF addresses should be the same as the size of symbols
1202 in the target file format. They shouldn't depend on things like -msym32,
1203 because many DWARF consumers do not allow the mixture of address sizes
1204 that one would then get from linking -msym32 code with -msym64 code.
1205
1206 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1207 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1208 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1209
1210 /* By default, turn on GDB extensions. */
1211 #define DEFAULT_GDB_EXTENSIONS 1
1212
1213 /* Local compiler-generated symbols must have a prefix that the assembler
1214 understands. By default, this is $, although some targets (e.g.,
1215 NetBSD-ELF) need to override this. */
1216
1217 #ifndef LOCAL_LABEL_PREFIX
1218 #define LOCAL_LABEL_PREFIX "$"
1219 #endif
1220
1221 /* By default on the mips, external symbols do not have an underscore
1222 prepended, but some targets (e.g., NetBSD) require this. */
1223
1224 #ifndef USER_LABEL_PREFIX
1225 #define USER_LABEL_PREFIX ""
1226 #endif
1227
1228 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1229 since the length can run past this up to a continuation point. */
1230 #undef DBX_CONTIN_LENGTH
1231 #define DBX_CONTIN_LENGTH 1500
1232
1233 /* How to renumber registers for dbx and gdb. */
1234 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1235
1236 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1237 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1238
1239 /* The DWARF 2 CFA column which tracks the return address. */
1240 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1241
1242 /* Before the prologue, RA lives in r31. */
1243 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1244
1245 /* Describe how we implement __builtin_eh_return. */
1246 #define EH_RETURN_DATA_REGNO(N) \
1247 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1248
1249 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1250
1251 #define EH_USES(N) mips_eh_uses (N)
1252
1253 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1254 The default for this in 64-bit mode is 8, which causes problems with
1255 SFmode register saves. */
1256 #define DWARF_CIE_DATA_ALIGNMENT -4
1257
1258 /* Correct the offset of automatic variables and arguments. Note that
1259 the MIPS debug format wants all automatic variables and arguments
1260 to be in terms of the virtual frame pointer (stack pointer before
1261 any adjustment in the function), while the MIPS 3.0 linker wants
1262 the frame pointer to be the stack pointer after the initial
1263 adjustment. */
1264
1265 #define DEBUGGER_AUTO_OFFSET(X) \
1266 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1267 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1268 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1269 \f
1270 /* Target machine storage layout */
1271
1272 #define BITS_BIG_ENDIAN 0
1273 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1274 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1275
1276 #define MAX_BITS_PER_WORD 64
1277
1278 /* Width of a word, in units (bytes). */
1279 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1280 #ifndef IN_LIBGCC2
1281 #define MIN_UNITS_PER_WORD 4
1282 #endif
1283
1284 /* For MIPS, width of a floating point register. */
1285 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1286
1287 /* The number of consecutive floating-point registers needed to store the
1288 largest format supported by the FPU. */
1289 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1290
1291 /* The number of consecutive floating-point registers needed to store the
1292 smallest format supported by the FPU. */
1293 #define MIN_FPRS_PER_FMT \
1294 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1295 ? 1 : MAX_FPRS_PER_FMT)
1296
1297 /* The largest size of value that can be held in floating-point
1298 registers and moved with a single instruction. */
1299 #define UNITS_PER_HWFPVALUE \
1300 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1301
1302 /* The largest size of value that can be held in floating-point
1303 registers. */
1304 #define UNITS_PER_FPVALUE \
1305 (TARGET_SOFT_FLOAT_ABI ? 0 \
1306 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1307 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1308
1309 /* The number of bytes in a double. */
1310 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1311
1312 /* Set the sizes of the core types. */
1313 #define SHORT_TYPE_SIZE 16
1314 #define INT_TYPE_SIZE 32
1315 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1316 #define LONG_LONG_TYPE_SIZE 64
1317
1318 #define FLOAT_TYPE_SIZE 32
1319 #define DOUBLE_TYPE_SIZE 64
1320 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1321
1322 /* Define the sizes of fixed-point types. */
1323 #define SHORT_FRACT_TYPE_SIZE 8
1324 #define FRACT_TYPE_SIZE 16
1325 #define LONG_FRACT_TYPE_SIZE 32
1326 #define LONG_LONG_FRACT_TYPE_SIZE 64
1327
1328 #define SHORT_ACCUM_TYPE_SIZE 16
1329 #define ACCUM_TYPE_SIZE 32
1330 #define LONG_ACCUM_TYPE_SIZE 64
1331 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1332 doesn't support 128-bit integers for MIPS32 currently. */
1333 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1334
1335 /* long double is not a fixed mode, but the idea is that, if we
1336 support long double, we also want a 128-bit integer type. */
1337 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1338
1339 #ifdef IN_LIBGCC2
1340 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1341 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1342 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1343 # else
1344 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1345 # endif
1346 #endif
1347
1348 /* Width in bits of a pointer. */
1349 #ifndef POINTER_SIZE
1350 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1351 #endif
1352
1353 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1354 #define PARM_BOUNDARY BITS_PER_WORD
1355
1356 /* Allocation boundary (in *bits*) for the code of a function. */
1357 #define FUNCTION_BOUNDARY 32
1358
1359 /* Alignment of field after `int : 0' in a structure. */
1360 #define EMPTY_FIELD_BOUNDARY 32
1361
1362 /* Every structure's size must be a multiple of this. */
1363 /* 8 is observed right on a DECstation and on riscos 4.02. */
1364 #define STRUCTURE_SIZE_BOUNDARY 8
1365
1366 /* There is no point aligning anything to a rounder boundary than this. */
1367 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1368
1369 /* All accesses must be aligned. */
1370 #define STRICT_ALIGNMENT 1
1371
1372 /* Define this if you wish to imitate the way many other C compilers
1373 handle alignment of bitfields and the structures that contain
1374 them.
1375
1376 The behavior is that the type written for a bit-field (`int',
1377 `short', or other integer type) imposes an alignment for the
1378 entire structure, as if the structure really did contain an
1379 ordinary field of that type. In addition, the bit-field is placed
1380 within the structure so that it would fit within such a field,
1381 not crossing a boundary for it.
1382
1383 Thus, on most machines, a bit-field whose type is written as `int'
1384 would not cross a four-byte boundary, and would force four-byte
1385 alignment for the whole structure. (The alignment used may not
1386 be four bytes; it is controlled by the other alignment
1387 parameters.)
1388
1389 If the macro is defined, its definition should be a C expression;
1390 a nonzero value for the expression enables this behavior. */
1391
1392 #define PCC_BITFIELD_TYPE_MATTERS 1
1393
1394 /* If defined, a C expression to compute the alignment given to a
1395 constant that is being placed in memory. CONSTANT is the constant
1396 and ALIGN is the alignment that the object would ordinarily have.
1397 The value of this macro is used instead of that alignment to align
1398 the object.
1399
1400 If this macro is not defined, then ALIGN is used.
1401
1402 The typical use of this macro is to increase alignment for string
1403 constants to be word aligned so that `strcpy' calls that copy
1404 constants can be done inline. */
1405
1406 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1407 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1408 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1409
1410 /* If defined, a C expression to compute the alignment for a static
1411 variable. TYPE is the data type, and ALIGN is the alignment that
1412 the object would ordinarily have. The value of this macro is used
1413 instead of that alignment to align the object.
1414
1415 If this macro is not defined, then ALIGN is used.
1416
1417 One use of this macro is to increase alignment of medium-size
1418 data to make it all fit in fewer cache lines. Another is to
1419 cause character arrays to be word-aligned so that `strcpy' calls
1420 that copy constants to character arrays can be done inline. */
1421
1422 #undef DATA_ALIGNMENT
1423 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1424 ((((ALIGN) < BITS_PER_WORD) \
1425 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1426 || TREE_CODE (TYPE) == UNION_TYPE \
1427 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1428
1429 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1430 character arrays to be word-aligned so that `strcpy' calls that copy
1431 constants to character arrays can be done inline, and 'strcmp' can be
1432 optimised to use word loads. */
1433 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1434 DATA_ALIGNMENT (TYPE, ALIGN)
1435
1436 #define PAD_VARARGS_DOWN \
1437 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1438
1439 /* Define if operations between registers always perform the operation
1440 on the full register even if a narrower mode is specified. */
1441 #define WORD_REGISTER_OPERATIONS
1442
1443 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1444 moves. All other references are zero extended. */
1445 #define LOAD_EXTEND_OP(MODE) \
1446 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1447 ? SIGN_EXTEND : ZERO_EXTEND)
1448
1449 /* Define this macro if it is advisable to hold scalars in registers
1450 in a wider mode than that declared by the program. In such cases,
1451 the value is constrained to be within the bounds of the declared
1452 type, but kept valid in the wider mode. The signedness of the
1453 extension may differ from that of the type. */
1454
1455 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1456 if (GET_MODE_CLASS (MODE) == MODE_INT \
1457 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1458 { \
1459 if ((MODE) == SImode) \
1460 (UNSIGNEDP) = 0; \
1461 (MODE) = Pmode; \
1462 }
1463
1464 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1465 Extensions of pointers to word_mode must be signed. */
1466 #define POINTERS_EXTEND_UNSIGNED false
1467
1468 /* Define if loading short immediate values into registers sign extends. */
1469 #define SHORT_IMMEDIATES_SIGN_EXTEND
1470
1471 /* The [d]clz instructions have the natural values at 0. */
1472
1473 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1474 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1475 \f
1476 /* Standard register usage. */
1477
1478 /* Number of hardware registers. We have:
1479
1480 - 32 integer registers
1481 - 32 floating point registers
1482 - 8 condition code registers
1483 - 2 accumulator registers (hi and lo)
1484 - 32 registers each for coprocessors 0, 2 and 3
1485 - 4 fake registers:
1486 - ARG_POINTER_REGNUM
1487 - FRAME_POINTER_REGNUM
1488 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1489 - CPRESTORE_SLOT_REGNUM
1490 - 2 dummy entries that were used at various times in the past.
1491 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1492 - 6 DSP control registers */
1493
1494 #define FIRST_PSEUDO_REGISTER 188
1495
1496 /* By default, fix the kernel registers ($26 and $27), the global
1497 pointer ($28) and the stack pointer ($29). This can change
1498 depending on the command-line options.
1499
1500 Regarding coprocessor registers: without evidence to the contrary,
1501 it's best to assume that each coprocessor register has a unique
1502 use. This can be overridden, in, e.g., mips_option_override or
1503 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1504 inappropriate for a particular target. */
1505
1506 #define FIXED_REGISTERS \
1507 { \
1508 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1509 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1510 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1512 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1513 /* COP0 registers */ \
1514 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1515 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1516 /* COP2 registers */ \
1517 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1518 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1519 /* COP3 registers */ \
1520 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1521 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1522 /* 6 DSP accumulator registers & 6 control registers */ \
1523 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1524 }
1525
1526
1527 /* Set up this array for o32 by default.
1528
1529 Note that we don't mark $31 as a call-clobbered register. The idea is
1530 that it's really the call instructions themselves which clobber $31.
1531 We don't care what the called function does with it afterwards.
1532
1533 This approach makes it easier to implement sibcalls. Unlike normal
1534 calls, sibcalls don't clobber $31, so the register reaches the
1535 called function in tact. EPILOGUE_USES says that $31 is useful
1536 to the called function. */
1537
1538 #define CALL_USED_REGISTERS \
1539 { \
1540 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1541 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1542 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1543 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1544 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1545 /* COP0 registers */ \
1546 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1547 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1548 /* COP2 registers */ \
1549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1551 /* COP3 registers */ \
1552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1553 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1554 /* 6 DSP accumulator registers & 6 control registers */ \
1555 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1556 }
1557
1558
1559 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1560
1561 #define CALL_REALLY_USED_REGISTERS \
1562 { /* General registers. */ \
1563 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1564 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1565 /* Floating-point registers. */ \
1566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1567 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1568 /* Others. */ \
1569 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1570 /* COP0 registers */ \
1571 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1572 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1573 /* COP2 registers */ \
1574 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1575 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1576 /* COP3 registers */ \
1577 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1578 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1579 /* 6 DSP accumulator registers & 6 control registers */ \
1580 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1581 }
1582
1583 /* Internal macros to classify a register number as to whether it's a
1584 general purpose register, a floating point register, a
1585 multiply/divide register, or a status register. */
1586
1587 #define GP_REG_FIRST 0
1588 #define GP_REG_LAST 31
1589 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1590 #define GP_DBX_FIRST 0
1591 #define K0_REG_NUM (GP_REG_FIRST + 26)
1592 #define K1_REG_NUM (GP_REG_FIRST + 27)
1593 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1594
1595 #define FP_REG_FIRST 32
1596 #define FP_REG_LAST 63
1597 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1598 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1599
1600 #define MD_REG_FIRST 64
1601 #define MD_REG_LAST 65
1602 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1603 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1604
1605 /* The DWARF 2 CFA column which tracks the return address from a
1606 signal handler context. This means that to maintain backwards
1607 compatibility, no hard register can be assigned this column if it
1608 would need to be handled by the DWARF unwinder. */
1609 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1610
1611 #define ST_REG_FIRST 67
1612 #define ST_REG_LAST 74
1613 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1614
1615
1616 /* FIXME: renumber. */
1617 #define COP0_REG_FIRST 80
1618 #define COP0_REG_LAST 111
1619 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1620
1621 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1622 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1623 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1624
1625 #define COP2_REG_FIRST 112
1626 #define COP2_REG_LAST 143
1627 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1628
1629 #define COP3_REG_FIRST 144
1630 #define COP3_REG_LAST 175
1631 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1632 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1633 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1634
1635 #define DSP_ACC_REG_FIRST 176
1636 #define DSP_ACC_REG_LAST 181
1637 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1638
1639 #define AT_REGNUM (GP_REG_FIRST + 1)
1640 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1641 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1642
1643 /* A few bitfield locations for the coprocessor registers. */
1644 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1645 the cause register for the EIC interrupt mode. */
1646 #define CAUSE_IPL 10
1647 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1648 #define SR_IPL 10
1649 /* Exception Level is at bit 1 of the status register. */
1650 #define SR_EXL 1
1651 /* Interrupt Enable is at bit 0 of the status register. */
1652 #define SR_IE 0
1653
1654 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1655 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1656 should be used instead. */
1657 #define FPSW_REGNUM ST_REG_FIRST
1658
1659 #define GP_REG_P(REGNO) \
1660 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1661 #define M16_REG_P(REGNO) \
1662 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1663 #define FP_REG_P(REGNO) \
1664 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1665 #define MD_REG_P(REGNO) \
1666 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1667 #define ST_REG_P(REGNO) \
1668 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1669 #define COP0_REG_P(REGNO) \
1670 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1671 #define COP2_REG_P(REGNO) \
1672 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1673 #define COP3_REG_P(REGNO) \
1674 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1675 #define ALL_COP_REG_P(REGNO) \
1676 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1677 /* Test if REGNO is one of the 6 new DSP accumulators. */
1678 #define DSP_ACC_REG_P(REGNO) \
1679 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1680 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1681 #define ACC_REG_P(REGNO) \
1682 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1683
1684 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1685
1686 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1687 to initialize the mips16 gp pseudo register. */
1688 #define CONST_GP_P(X) \
1689 (GET_CODE (X) == CONST \
1690 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1691 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1692
1693 /* Return coprocessor number from register number. */
1694
1695 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1696 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1697 : COP3_REG_P (REGNO) ? '3' : '?')
1698
1699
1700 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1701
1702 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1703 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1704
1705 #define MODES_TIEABLE_P mips_modes_tieable_p
1706
1707 /* Register to use for pushing function arguments. */
1708 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1709
1710 /* These two registers don't really exist: they get eliminated to either
1711 the stack or hard frame pointer. */
1712 #define ARG_POINTER_REGNUM 77
1713 #define FRAME_POINTER_REGNUM 78
1714
1715 /* $30 is not available on the mips16, so we use $17 as the frame
1716 pointer. */
1717 #define HARD_FRAME_POINTER_REGNUM \
1718 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1719
1720 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1721 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1722
1723 /* Register in which static-chain is passed to a function. */
1724 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1725
1726 /* Registers used as temporaries in prologue/epilogue code:
1727
1728 - If a MIPS16 PIC function needs access to _gp, it first loads
1729 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1730
1731 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1732 register. The register must not conflict with MIPS16_PIC_TEMP.
1733
1734 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1735 register.
1736
1737 If we're generating MIPS16 code, these registers must come from the
1738 core set of 8. The prologue registers mustn't conflict with any
1739 incoming arguments, the static chain pointer, or the frame pointer.
1740 The epilogue temporary mustn't conflict with the return registers,
1741 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1742 or the EH data registers.
1743
1744 If we're generating interrupt handlers, we use K0 as a temporary register
1745 in prologue/epilogue code. */
1746
1747 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1748 #define MIPS_PROLOGUE_TEMP_REGNUM \
1749 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1750 #define MIPS_EPILOGUE_TEMP_REGNUM \
1751 (cfun->machine->interrupt_handler_p \
1752 ? K0_REG_NUM \
1753 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1754
1755 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1756 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1757 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1758
1759 /* Define this macro if it is as good or better to call a constant
1760 function address than to call an address kept in a register. */
1761 #define NO_FUNCTION_CSE 1
1762
1763 /* The ABI-defined global pointer. Sometimes we use a different
1764 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1765 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1766
1767 /* We normally use $28 as the global pointer. However, when generating
1768 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1769 register instead. They can then avoid saving and restoring $28
1770 and perhaps avoid using a frame at all.
1771
1772 When a leaf function uses something other than $28, mips_expand_prologue
1773 will modify pic_offset_table_rtx in place. Take the register number
1774 from there after reload. */
1775 #define PIC_OFFSET_TABLE_REGNUM \
1776 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1777
1778 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1779 \f
1780 /* Define the classes of registers for register constraints in the
1781 machine description. Also define ranges of constants.
1782
1783 One of the classes must always be named ALL_REGS and include all hard regs.
1784 If there is more than one class, another class must be named NO_REGS
1785 and contain no registers.
1786
1787 The name GENERAL_REGS must be the name of a class (or an alias for
1788 another name such as ALL_REGS). This is the class of registers
1789 that is allowed by "g" or "r" in a register constraint.
1790 Also, registers outside this class are allocated only when
1791 instructions express preferences for them.
1792
1793 The classes must be numbered in nondecreasing order; that is,
1794 a larger-numbered class must never be contained completely
1795 in a smaller-numbered class.
1796
1797 For any two classes, it is very desirable that there be another
1798 class that represents their union. */
1799
1800 enum reg_class
1801 {
1802 NO_REGS, /* no registers in set */
1803 M16_REGS, /* mips16 directly accessible registers */
1804 T_REG, /* mips16 T register ($24) */
1805 M16_T_REGS, /* mips16 registers plus T register */
1806 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1807 V1_REG, /* Register $v1 ($3) used for TLS access. */
1808 LEA_REGS, /* Every GPR except $25 */
1809 GR_REGS, /* integer registers */
1810 FP_REGS, /* floating point registers */
1811 MD0_REG, /* first multiply/divide register */
1812 MD1_REG, /* second multiply/divide register */
1813 MD_REGS, /* multiply/divide registers (hi/lo) */
1814 COP0_REGS, /* generic coprocessor classes */
1815 COP2_REGS,
1816 COP3_REGS,
1817 ST_REGS, /* status registers (fp status) */
1818 DSP_ACC_REGS, /* DSP accumulator registers */
1819 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1820 FRAME_REGS, /* $arg and $frame */
1821 GR_AND_MD0_REGS, /* union classes */
1822 GR_AND_MD1_REGS,
1823 GR_AND_MD_REGS,
1824 GR_AND_ACC_REGS,
1825 ALL_REGS, /* all registers */
1826 LIM_REG_CLASSES /* max value + 1 */
1827 };
1828
1829 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1830
1831 #define GENERAL_REGS GR_REGS
1832
1833 /* An initializer containing the names of the register classes as C
1834 string constants. These names are used in writing some of the
1835 debugging dumps. */
1836
1837 #define REG_CLASS_NAMES \
1838 { \
1839 "NO_REGS", \
1840 "M16_REGS", \
1841 "T_REG", \
1842 "M16_T_REGS", \
1843 "PIC_FN_ADDR_REG", \
1844 "V1_REG", \
1845 "LEA_REGS", \
1846 "GR_REGS", \
1847 "FP_REGS", \
1848 "MD0_REG", \
1849 "MD1_REG", \
1850 "MD_REGS", \
1851 /* coprocessor registers */ \
1852 "COP0_REGS", \
1853 "COP2_REGS", \
1854 "COP3_REGS", \
1855 "ST_REGS", \
1856 "DSP_ACC_REGS", \
1857 "ACC_REGS", \
1858 "FRAME_REGS", \
1859 "GR_AND_MD0_REGS", \
1860 "GR_AND_MD1_REGS", \
1861 "GR_AND_MD_REGS", \
1862 "GR_AND_ACC_REGS", \
1863 "ALL_REGS" \
1864 }
1865
1866 /* An initializer containing the contents of the register classes,
1867 as integers which are bit masks. The Nth integer specifies the
1868 contents of class N. The way the integer MASK is interpreted is
1869 that register R is in the class if `MASK & (1 << R)' is 1.
1870
1871 When the machine has more than 32 registers, an integer does not
1872 suffice. Then the integers are replaced by sub-initializers,
1873 braced groupings containing several integers. Each
1874 sub-initializer must be suitable as an initializer for the type
1875 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1876
1877 #define REG_CLASS_CONTENTS \
1878 { \
1879 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1880 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1881 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1882 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1883 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1884 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1885 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1886 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1887 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1888 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1889 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1890 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1891 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1892 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1893 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1894 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1895 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1896 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1897 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1898 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1899 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1900 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1901 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1902 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1903 }
1904
1905
1906 /* A C expression whose value is a register class containing hard
1907 register REGNO. In general there is more that one such class;
1908 choose a class which is "minimal", meaning that no smaller class
1909 also contains the register. */
1910
1911 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1912
1913 /* A macro whose definition is the name of the class to which a
1914 valid base register must belong. A base register is one used in
1915 an address which is the register value plus a displacement. */
1916
1917 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1918
1919 /* A macro whose definition is the name of the class to which a
1920 valid index register must belong. An index register is one used
1921 in an address where its value is either multiplied by a scale
1922 factor or added to another register (as well as added to a
1923 displacement). */
1924
1925 #define INDEX_REG_CLASS NO_REGS
1926
1927 /* We generally want to put call-clobbered registers ahead of
1928 call-saved ones. (IRA expects this.) */
1929
1930 #define REG_ALLOC_ORDER \
1931 { /* Accumulator registers. When GPRs and accumulators have equal \
1932 cost, we generally prefer to use accumulators. For example, \
1933 a division of multiplication result is better allocated to LO, \
1934 so that we put the MFLO at the point of use instead of at the \
1935 point of definition. It's also needed if we're to take advantage \
1936 of the extra accumulators available with -mdspr2. In some cases, \
1937 it can also help to reduce register pressure. */ \
1938 64, 65,176,177,178,179,180,181, \
1939 /* Call-clobbered GPRs. */ \
1940 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1941 24, 25, 31, \
1942 /* The global pointer. This is call-clobbered for o32 and o64 \
1943 abicalls, call-saved for n32 and n64 abicalls, and a program \
1944 invariant otherwise. Putting it between the call-clobbered \
1945 and call-saved registers should cope with all eventualities. */ \
1946 28, \
1947 /* Call-saved GPRs. */ \
1948 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1949 /* GPRs that can never be exposed to the register allocator. */ \
1950 0, 26, 27, 29, \
1951 /* Call-clobbered FPRs. */ \
1952 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1953 48, 49, 50, 51, \
1954 /* FPRs that are usually call-saved. The odd ones are actually \
1955 call-clobbered for n32, but listing them ahead of the even \
1956 registers might encourage the register allocator to fragment \
1957 the available FPR pairs. We need paired FPRs to store long \
1958 doubles, so it isn't clear that using a different order \
1959 for n32 would be a win. */ \
1960 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1961 /* None of the remaining classes have defined call-saved \
1962 registers. */ \
1963 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1964 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1965 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1966 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1967 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1968 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1969 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1970 182,183,184,185,186,187 \
1971 }
1972
1973 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1974 to be rearranged based on a particular function. On the mips16, we
1975 want to allocate $24 (T_REG) before other registers for
1976 instructions for which it is possible. */
1977
1978 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
1979
1980 /* True if VALUE is an unsigned 6-bit number. */
1981
1982 #define UIMM6_OPERAND(VALUE) \
1983 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1984
1985 /* True if VALUE is a signed 10-bit number. */
1986
1987 #define IMM10_OPERAND(VALUE) \
1988 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1989
1990 /* True if VALUE is a signed 16-bit number. */
1991
1992 #define SMALL_OPERAND(VALUE) \
1993 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1994
1995 /* True if VALUE is an unsigned 16-bit number. */
1996
1997 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1998 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1999
2000 /* True if VALUE can be loaded into a register using LUI. */
2001
2002 #define LUI_OPERAND(VALUE) \
2003 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2004 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2005
2006 /* Return a value X with the low 16 bits clear, and such that
2007 VALUE - X is a signed 16-bit value. */
2008
2009 #define CONST_HIGH_PART(VALUE) \
2010 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2011
2012 #define CONST_LOW_PART(VALUE) \
2013 ((VALUE) - CONST_HIGH_PART (VALUE))
2014
2015 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2016 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2017 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2018
2019 /* The HI and LO registers can only be reloaded via the general
2020 registers. Condition code registers can only be loaded to the
2021 general registers, and from the floating point registers. */
2022
2023 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2024 mips_secondary_reload_class (CLASS, MODE, X, true)
2025 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2026 mips_secondary_reload_class (CLASS, MODE, X, false)
2027
2028 /* Return the maximum number of consecutive registers
2029 needed to represent mode MODE in a register of class CLASS. */
2030
2031 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2032
2033 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2034 mips_cannot_change_mode_class (FROM, TO, CLASS)
2035 \f
2036 /* Stack layout; function entry, exit and calling. */
2037
2038 #define STACK_GROWS_DOWNWARD
2039
2040 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2041
2042 /* Size of the area allocated in the frame to save the GP. */
2043
2044 #define MIPS_GP_SAVE_AREA_SIZE \
2045 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2046
2047 /* The offset of the first local variable from the frame pointer. See
2048 mips_compute_frame_info for details about the frame layout. */
2049
2050 #define STARTING_FRAME_OFFSET \
2051 (FRAME_GROWS_DOWNWARD \
2052 ? 0 \
2053 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2054
2055 #define RETURN_ADDR_RTX mips_return_addr
2056
2057 /* Mask off the MIPS16 ISA bit in unwind addresses.
2058
2059 The reason for this is a little subtle. When unwinding a call,
2060 we are given the call's return address, which on most targets
2061 is the address of the following instruction. However, what we
2062 actually want to find is the EH region for the call itself.
2063 The target-independent unwind code therefore searches for "RA - 1".
2064
2065 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2066 RA - 1 is therefore the real (even-valued) start of the return
2067 instruction. EH region labels are usually odd-valued MIPS16 symbols
2068 too, so a search for an even address within a MIPS16 region would
2069 usually work.
2070
2071 However, there is an exception. If the end of an EH region is also
2072 the end of a function, the end label is allowed to be even. This is
2073 necessary because a following non-MIPS16 function may also need EH
2074 information for its first instruction.
2075
2076 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2077 non-ISA-encoded address. This probably isn't ideal, but it is
2078 the traditional (legacy) behavior. It is therefore only safe
2079 to search MIPS EH regions for an _odd-valued_ address.
2080
2081 Masking off the ISA bit means that the target-independent code
2082 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2083 #define MASK_RETURN_ADDR GEN_INT (-2)
2084
2085
2086 /* Similarly, don't use the least-significant bit to tell pointers to
2087 code from vtable index. */
2088
2089 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2090
2091 /* The eliminations to $17 are only used for mips16 code. See the
2092 definition of HARD_FRAME_POINTER_REGNUM. */
2093
2094 #define ELIMINABLE_REGS \
2095 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2096 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2097 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2098 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2099 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2100 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2101
2102 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2103 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2104
2105 /* Allocate stack space for arguments at the beginning of each function. */
2106 #define ACCUMULATE_OUTGOING_ARGS 1
2107
2108 /* The argument pointer always points to the first argument. */
2109 #define FIRST_PARM_OFFSET(FNDECL) 0
2110
2111 /* o32 and o64 reserve stack space for all argument registers. */
2112 #define REG_PARM_STACK_SPACE(FNDECL) \
2113 (TARGET_OLDABI \
2114 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2115 : 0)
2116
2117 /* Define this if it is the responsibility of the caller to
2118 allocate the area reserved for arguments passed in registers.
2119 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2120 of this macro is to determine whether the space is included in
2121 `crtl->outgoing_args_size'. */
2122 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2123
2124 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2125 \f
2126 /* Symbolic macros for the registers used to return integer and floating
2127 point values. */
2128
2129 #define GP_RETURN (GP_REG_FIRST + 2)
2130 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2131
2132 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2133
2134 /* Symbolic macros for the first/last argument registers. */
2135
2136 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2137 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2138 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2139 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2140
2141 /* 1 if N is a possible register number for function argument passing.
2142 We have no FP argument registers when soft-float. When FP registers
2143 are 32 bits, we can't directly reference the odd numbered ones. */
2144
2145 #define FUNCTION_ARG_REGNO_P(N) \
2146 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2147 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2148 && !fixed_regs[N])
2149 \f
2150 /* This structure has to cope with two different argument allocation
2151 schemes. Most MIPS ABIs view the arguments as a structure, of which
2152 the first N words go in registers and the rest go on the stack. If I
2153 < N, the Ith word might go in Ith integer argument register or in a
2154 floating-point register. For these ABIs, we only need to remember
2155 the offset of the current argument into the structure.
2156
2157 The EABI instead allocates the integer and floating-point arguments
2158 separately. The first N words of FP arguments go in FP registers,
2159 the rest go on the stack. Likewise, the first N words of the other
2160 arguments go in integer registers, and the rest go on the stack. We
2161 need to maintain three counts: the number of integer registers used,
2162 the number of floating-point registers used, and the number of words
2163 passed on the stack.
2164
2165 We could keep separate information for the two ABIs (a word count for
2166 the standard ABIs, and three separate counts for the EABI). But it
2167 seems simpler to view the standard ABIs as forms of EABI that do not
2168 allocate floating-point registers.
2169
2170 So for the standard ABIs, the first N words are allocated to integer
2171 registers, and mips_function_arg decides on an argument-by-argument
2172 basis whether that argument should really go in an integer register,
2173 or in a floating-point one. */
2174
2175 typedef struct mips_args {
2176 /* Always true for varargs functions. Otherwise true if at least
2177 one argument has been passed in an integer register. */
2178 int gp_reg_found;
2179
2180 /* The number of arguments seen so far. */
2181 unsigned int arg_number;
2182
2183 /* The number of integer registers used so far. For all ABIs except
2184 EABI, this is the number of words that have been added to the
2185 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2186 unsigned int num_gprs;
2187
2188 /* For EABI, the number of floating-point registers used so far. */
2189 unsigned int num_fprs;
2190
2191 /* The number of words passed on the stack. */
2192 unsigned int stack_words;
2193
2194 /* On the mips16, we need to keep track of which floating point
2195 arguments were passed in general registers, but would have been
2196 passed in the FP regs if this were a 32-bit function, so that we
2197 can move them to the FP regs if we wind up calling a 32-bit
2198 function. We record this information in fp_code, encoded in base
2199 four. A zero digit means no floating point argument, a one digit
2200 means an SFmode argument, and a two digit means a DFmode argument,
2201 and a three digit is not used. The low order digit is the first
2202 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2203 an SFmode argument. ??? A more sophisticated approach will be
2204 needed if MIPS_ABI != ABI_32. */
2205 int fp_code;
2206
2207 /* True if the function has a prototype. */
2208 int prototype;
2209 } CUMULATIVE_ARGS;
2210
2211 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2212 for a call to a function whose data type is FNTYPE.
2213 For a library call, FNTYPE is 0. */
2214
2215 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2216 mips_init_cumulative_args (&CUM, FNTYPE)
2217
2218 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2219 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2220
2221 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2222 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2223
2224 /* True if using EABI and varargs can be passed in floating-point
2225 registers. Under these conditions, we need a more complex form
2226 of va_list, which tracks GPR, FPR and stack arguments separately. */
2227 #define EABI_FLOAT_VARARGS_P \
2228 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2229
2230 \f
2231 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2232
2233 /* Treat LOC as a byte offset from the stack pointer and round it up
2234 to the next fully-aligned offset. */
2235 #define MIPS_STACK_ALIGN(LOC) \
2236 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2237
2238 \f
2239 /* Output assembler code to FILE to increment profiler label # LABELNO
2240 for profiling a function entry. */
2241
2242 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2243
2244 /* The profiler preserves all interesting registers, including $31. */
2245 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2246
2247 /* No mips port has ever used the profiler counter word, so don't emit it
2248 or the label for it. */
2249
2250 #define NO_PROFILE_COUNTERS 1
2251
2252 /* Define this macro if the code for function profiling should come
2253 before the function prologue. Normally, the profiling code comes
2254 after. */
2255
2256 /* #define PROFILE_BEFORE_PROLOGUE */
2257
2258 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2259 the stack pointer does not matter. The value is tested only in
2260 functions that have frame pointers.
2261 No definition is equivalent to always zero. */
2262
2263 #define EXIT_IGNORE_STACK 1
2264
2265 \f
2266 /* Trampolines are a block of code followed by two pointers. */
2267
2268 #define TRAMPOLINE_SIZE \
2269 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2270
2271 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2272 pointers from a single LUI base. */
2273
2274 #define TRAMPOLINE_ALIGNMENT 64
2275
2276 /* mips_trampoline_init calls this library function to flush
2277 program and data caches. */
2278
2279 #ifndef CACHE_FLUSH_FUNC
2280 #define CACHE_FLUSH_FUNC "_flush_cache"
2281 #endif
2282
2283 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2284 /* Flush both caches. We need to flush the data cache in case \
2285 the system has a write-back cache. */ \
2286 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2287 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2288 GEN_INT (3), TYPE_MODE (integer_type_node))
2289
2290 \f
2291 /* Addressing modes, and classification of registers for them. */
2292
2293 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2294 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2295 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2296 \f
2297 /* Maximum number of registers that can appear in a valid memory address. */
2298
2299 #define MAX_REGS_PER_ADDRESS 1
2300
2301 /* Check for constness inline but use mips_legitimate_address_p
2302 to check whether a constant really is an address. */
2303
2304 #define CONSTANT_ADDRESS_P(X) \
2305 (CONSTANT_P (X) && memory_address_p (SImode, X))
2306
2307 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2308 'the start of the function that this code is output in'. */
2309
2310 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2311 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2312 asm_fprintf ((FILE), "%U%s", \
2313 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2314 else \
2315 asm_fprintf ((FILE), "%U%s", (NAME))
2316 \f
2317 /* Flag to mark a function decl symbol that requires a long call. */
2318 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2319 #define SYMBOL_REF_LONG_CALL_P(X) \
2320 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2321
2322 /* This flag marks functions that cannot be lazily bound. */
2323 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2324 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2325 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2326
2327 /* True if we're generating a form of MIPS16 code in which jump tables
2328 are stored in the text section and encoded as 16-bit PC-relative
2329 offsets. This is only possible when general text loads are allowed,
2330 since the table access itself will be an "lh" instruction. */
2331 /* ??? 16-bit offsets can overflow in large functions. */
2332 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2333
2334 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2335
2336 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2337
2338 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2339
2340 /* Define this as 1 if `char' should by default be signed; else as 0. */
2341 #ifndef DEFAULT_SIGNED_CHAR
2342 #define DEFAULT_SIGNED_CHAR 1
2343 #endif
2344
2345 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2346 we generally don't want to use them for copying arbitrary data.
2347 A single N-word move is usually the same cost as N single-word moves. */
2348 #define MOVE_MAX UNITS_PER_WORD
2349 #define MAX_MOVE_MAX 8
2350
2351 /* Define this macro as a C expression which is nonzero if
2352 accessing less than a word of memory (i.e. a `char' or a
2353 `short') is no faster than accessing a word of memory, i.e., if
2354 such access require more than one instruction or if there is no
2355 difference in cost between byte and (aligned) word loads.
2356
2357 On RISC machines, it tends to generate better code to define
2358 this as 1, since it avoids making a QI or HI mode register.
2359
2360 But, generating word accesses for -mips16 is generally bad as shifts
2361 (often extended) would be needed for byte accesses. */
2362 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2363
2364 /* Standard MIPS integer shifts truncate the shift amount to the
2365 width of the shifted operand. However, Loongson vector shifts
2366 do not truncate the shift amount at all. */
2367 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2368
2369 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2370 is done just by pretending it is already truncated. */
2371 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2372 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2373
2374
2375 /* Specify the machine mode that pointers have.
2376 After generation of rtl, the compiler makes no further distinction
2377 between pointers and any other objects of this machine mode. */
2378
2379 #ifndef Pmode
2380 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2381 #endif
2382
2383 /* Give call MEMs SImode since it is the "most permissive" mode
2384 for both 32-bit and 64-bit targets. */
2385
2386 #define FUNCTION_MODE SImode
2387
2388 \f
2389
2390 /* Define if copies to/from condition code registers should be avoided.
2391
2392 This is needed for the MIPS because reload_outcc is not complete;
2393 it needs to handle cases where the source is a general or another
2394 condition code register. */
2395 #define AVOID_CCMODE_COPIES
2396
2397 /* A C expression for the cost of a branch instruction. A value of
2398 1 is the default; other values are interpreted relative to that. */
2399
2400 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2401 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2402
2403 /* If defined, modifies the length assigned to instruction INSN as a
2404 function of the context in which it is used. LENGTH is an lvalue
2405 that contains the initially computed length of the insn and should
2406 be updated with the correct length of the insn. */
2407 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2408 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2409
2410 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2411 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2412 its operands. */
2413 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2414 "%*" OPCODE "%?\t" OPERANDS "%/"
2415
2416 /* Return an asm string that forces INSN to be treated as an absolute
2417 J or JAL instruction instead of an assembler macro. */
2418 #define MIPS_ABSOLUTE_JUMP(INSN) \
2419 (TARGET_ABICALLS_PIC2 \
2420 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2421 : INSN)
2422
2423 /* Return the asm template for a call. INSN is the instruction's mnemonic
2424 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2425 number of the target. SIZE_OPNO is the operand number of the argument size
2426 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2427 -1 and the call is indirect, use the function symbol from the call
2428 attributes to attach a R_MIPS_JALR relocation to the call.
2429
2430 When generating GOT code without explicit relocation operators,
2431 all calls should use assembly macros. Otherwise, all indirect
2432 calls should use "jr" or "jalr"; we will arrange to restore $gp
2433 afterwards if necessary. Finally, we can only generate direct
2434 calls for -mabicalls by temporarily switching to non-PIC mode. */
2435 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2436 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2437 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2438 : (REG_P (OPERANDS[TARGET_OPNO]) \
2439 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2440 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2441 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2442 : REG_P (OPERANDS[TARGET_OPNO]) \
2443 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2444 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2445 \f
2446 /* Control the assembler format that we output. */
2447
2448 /* Output to assembler file text saying following lines
2449 may contain character constants, extra white space, comments, etc. */
2450
2451 #ifndef ASM_APP_ON
2452 #define ASM_APP_ON " #APP\n"
2453 #endif
2454
2455 /* Output to assembler file text saying following lines
2456 no longer contain unusual constructs. */
2457
2458 #ifndef ASM_APP_OFF
2459 #define ASM_APP_OFF " #NO_APP\n"
2460 #endif
2461
2462 #define REGISTER_NAMES \
2463 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2464 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2465 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2466 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2467 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2468 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2469 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2470 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2471 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2472 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2473 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2474 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2475 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2476 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2477 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2478 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2479 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2480 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2481 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2482 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2483 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2484 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2485 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2486 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2487
2488 /* List the "software" names for each register. Also list the numerical
2489 names for $fp and $sp. */
2490
2491 #define ADDITIONAL_REGISTER_NAMES \
2492 { \
2493 { "$29", 29 + GP_REG_FIRST }, \
2494 { "$30", 30 + GP_REG_FIRST }, \
2495 { "at", 1 + GP_REG_FIRST }, \
2496 { "v0", 2 + GP_REG_FIRST }, \
2497 { "v1", 3 + GP_REG_FIRST }, \
2498 { "a0", 4 + GP_REG_FIRST }, \
2499 { "a1", 5 + GP_REG_FIRST }, \
2500 { "a2", 6 + GP_REG_FIRST }, \
2501 { "a3", 7 + GP_REG_FIRST }, \
2502 { "t0", 8 + GP_REG_FIRST }, \
2503 { "t1", 9 + GP_REG_FIRST }, \
2504 { "t2", 10 + GP_REG_FIRST }, \
2505 { "t3", 11 + GP_REG_FIRST }, \
2506 { "t4", 12 + GP_REG_FIRST }, \
2507 { "t5", 13 + GP_REG_FIRST }, \
2508 { "t6", 14 + GP_REG_FIRST }, \
2509 { "t7", 15 + GP_REG_FIRST }, \
2510 { "s0", 16 + GP_REG_FIRST }, \
2511 { "s1", 17 + GP_REG_FIRST }, \
2512 { "s2", 18 + GP_REG_FIRST }, \
2513 { "s3", 19 + GP_REG_FIRST }, \
2514 { "s4", 20 + GP_REG_FIRST }, \
2515 { "s5", 21 + GP_REG_FIRST }, \
2516 { "s6", 22 + GP_REG_FIRST }, \
2517 { "s7", 23 + GP_REG_FIRST }, \
2518 { "t8", 24 + GP_REG_FIRST }, \
2519 { "t9", 25 + GP_REG_FIRST }, \
2520 { "k0", 26 + GP_REG_FIRST }, \
2521 { "k1", 27 + GP_REG_FIRST }, \
2522 { "gp", 28 + GP_REG_FIRST }, \
2523 { "sp", 29 + GP_REG_FIRST }, \
2524 { "fp", 30 + GP_REG_FIRST }, \
2525 { "ra", 31 + GP_REG_FIRST }, \
2526 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2527 }
2528
2529 /* This is meant to be redefined in the host dependent files. It is a
2530 set of alternative names and regnums for mips coprocessors. */
2531
2532 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2533
2534 #define DBR_OUTPUT_SEQEND(STREAM) \
2535 do \
2536 { \
2537 /* Undo the effect of '%*'. */ \
2538 mips_pop_asm_switch (&mips_nomacro); \
2539 mips_pop_asm_switch (&mips_noreorder); \
2540 /* Emit a blank line after the delay slot for emphasis. */ \
2541 fputs ("\n", STREAM); \
2542 } \
2543 while (0)
2544
2545 /* Use .loc directives for SDB line numbers. */
2546 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2547 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2548
2549 /* The MIPS implementation uses some labels for its own purpose. The
2550 following lists what labels are created, and are all formed by the
2551 pattern $L[a-z].*. The machine independent portion of GCC creates
2552 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2553
2554 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2555 $Lb[0-9]+ Begin blocks for MIPS debug support
2556 $Lc[0-9]+ Label for use in s<xx> operation.
2557 $Le[0-9]+ End blocks for MIPS debug support */
2558
2559 #undef ASM_DECLARE_OBJECT_NAME
2560 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2561 mips_declare_object (STREAM, NAME, "", ":\n")
2562
2563 /* Globalizing directive for a label. */
2564 #define GLOBAL_ASM_OP "\t.globl\t"
2565
2566 /* This says how to define a global common symbol. */
2567
2568 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2569
2570 /* This says how to define a local common symbol (i.e., not visible to
2571 linker). */
2572
2573 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2574 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2575 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2576 #endif
2577
2578 /* This says how to output an external. It would be possible not to
2579 output anything and let undefined symbol become external. However
2580 the assembler uses length information on externals to allocate in
2581 data/sdata bss/sbss, thereby saving exec time. */
2582
2583 #undef ASM_OUTPUT_EXTERNAL
2584 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2585 mips_output_external(STREAM,DECL,NAME)
2586
2587 /* This is how to declare a function name. The actual work of
2588 emitting the label is moved to function_prologue, so that we can
2589 get the line number correctly emitted before the .ent directive,
2590 and after any .file directives. Define as empty so that the function
2591 is not declared before the .ent directive elsewhere. */
2592
2593 #undef ASM_DECLARE_FUNCTION_NAME
2594 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2595
2596 /* This is how to store into the string LABEL
2597 the symbol_ref name of an internal numbered label where
2598 PREFIX is the class of label and NUM is the number within the class.
2599 This is suitable for output with `assemble_name'. */
2600
2601 #undef ASM_GENERATE_INTERNAL_LABEL
2602 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2603 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2604
2605 /* Print debug labels as "foo = ." rather than "foo:" because they should
2606 represent a byte pointer rather than an ISA-encoded address. This is
2607 particularly important for code like:
2608
2609 $LFBxxx = .
2610 .cfi_startproc
2611 ...
2612 .section .gcc_except_table,...
2613 ...
2614 .uleb128 foo-$LFBxxx
2615
2616 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2617 likewise a byte pointer rather than an ISA-encoded address.
2618
2619 At the time of writing, this hook is not used for the function end
2620 label:
2621
2622 $LFExxx:
2623 .end foo
2624
2625 But this doesn't matter, because GAS doesn't treat a pre-.end label
2626 as a MIPS16 one anyway. */
2627
2628 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2629 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2630
2631 /* This is how to output an element of a case-vector that is absolute. */
2632
2633 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2634 fprintf (STREAM, "\t%s\t%sL%d\n", \
2635 ptr_mode == DImode ? ".dword" : ".word", \
2636 LOCAL_LABEL_PREFIX, \
2637 VALUE)
2638
2639 /* This is how to output an element of a case-vector. We can make the
2640 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2641 is supported. */
2642
2643 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2644 do { \
2645 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2646 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2647 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2648 else if (TARGET_GPWORD) \
2649 fprintf (STREAM, "\t%s\t%sL%d\n", \
2650 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2651 LOCAL_LABEL_PREFIX, VALUE); \
2652 else if (TARGET_RTP_PIC) \
2653 { \
2654 /* Make the entry relative to the start of the function. */ \
2655 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2656 fprintf (STREAM, "\t%s\t%sL%d-", \
2657 Pmode == DImode ? ".dword" : ".word", \
2658 LOCAL_LABEL_PREFIX, VALUE); \
2659 assemble_name (STREAM, XSTR (fnsym, 0)); \
2660 fprintf (STREAM, "\n"); \
2661 } \
2662 else \
2663 fprintf (STREAM, "\t%s\t%sL%d\n", \
2664 ptr_mode == DImode ? ".dword" : ".word", \
2665 LOCAL_LABEL_PREFIX, VALUE); \
2666 } while (0)
2667
2668 /* This is how to output an assembler line
2669 that says to advance the location counter
2670 to a multiple of 2**LOG bytes. */
2671
2672 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2673 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2674
2675 /* This is how to output an assembler line to advance the location
2676 counter by SIZE bytes. */
2677
2678 #undef ASM_OUTPUT_SKIP
2679 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2680 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2681
2682 /* This is how to output a string. */
2683 #undef ASM_OUTPUT_ASCII
2684 #define ASM_OUTPUT_ASCII mips_output_ascii
2685
2686 /* Output #ident as a in the read-only data section. */
2687 #undef ASM_OUTPUT_IDENT
2688 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2689 { \
2690 const char *p = STRING; \
2691 int size = strlen (p) + 1; \
2692 switch_to_section (readonly_data_section); \
2693 assemble_string (p, size); \
2694 }
2695 \f
2696 /* Default to -G 8 */
2697 #ifndef MIPS_DEFAULT_GVALUE
2698 #define MIPS_DEFAULT_GVALUE 8
2699 #endif
2700
2701 /* Define the strings to put out for each section in the object file. */
2702 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2703 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2704
2705 #undef READONLY_DATA_SECTION_ASM_OP
2706 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2707 \f
2708 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2709 do \
2710 { \
2711 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2712 TARGET_64BIT ? "daddiu" : "addiu", \
2713 reg_names[STACK_POINTER_REGNUM], \
2714 reg_names[STACK_POINTER_REGNUM], \
2715 TARGET_64BIT ? "sd" : "sw", \
2716 reg_names[REGNO], \
2717 reg_names[STACK_POINTER_REGNUM]); \
2718 } \
2719 while (0)
2720
2721 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2722 do \
2723 { \
2724 mips_push_asm_switch (&mips_noreorder); \
2725 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2726 TARGET_64BIT ? "ld" : "lw", \
2727 reg_names[REGNO], \
2728 reg_names[STACK_POINTER_REGNUM], \
2729 TARGET_64BIT ? "daddu" : "addu", \
2730 reg_names[STACK_POINTER_REGNUM], \
2731 reg_names[STACK_POINTER_REGNUM]); \
2732 mips_pop_asm_switch (&mips_noreorder); \
2733 } \
2734 while (0)
2735
2736 /* How to start an assembler comment.
2737 The leading space is important (the mips native assembler requires it). */
2738 #ifndef ASM_COMMENT_START
2739 #define ASM_COMMENT_START " #"
2740 #endif
2741 \f
2742 #undef SIZE_TYPE
2743 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2744
2745 #undef PTRDIFF_TYPE
2746 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2747
2748 /* The maximum number of bytes that can be copied by one iteration of
2749 a movmemsi loop; see mips_block_move_loop. */
2750 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2751 (UNITS_PER_WORD * 4)
2752
2753 /* The maximum number of bytes that can be copied by a straight-line
2754 implementation of movmemsi; see mips_block_move_straight. We want
2755 to make sure that any loop-based implementation will iterate at
2756 least twice. */
2757 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2758 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2759
2760 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2761 values were determined experimentally by benchmarking with CSiBE.
2762 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2763 for o32 where we have to restore $gp afterwards as well as make an
2764 indirect call), but in practice, bumping this up higher for
2765 TARGET_ABICALLS doesn't make much difference to code size. */
2766
2767 #define MIPS_CALL_RATIO 8
2768
2769 /* Any loop-based implementation of movmemsi will have at least
2770 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2771 moves, so allow individual copies of fewer elements.
2772
2773 When movmemsi is not available, use a value approximating
2774 the length of a memcpy call sequence, so that move_by_pieces
2775 will generate inline code if it is shorter than a function call.
2776 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2777 we'll have to generate a load/store pair for each, halve the
2778 value of MIPS_CALL_RATIO to take that into account. */
2779
2780 #define MOVE_RATIO(speed) \
2781 (HAVE_movmemsi \
2782 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2783 : MIPS_CALL_RATIO / 2)
2784
2785 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2786 mips_move_by_pieces_p (SIZE, ALIGN)
2787
2788 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2789 of the length of a memset call, but use the default otherwise. */
2790
2791 #define CLEAR_RATIO(speed)\
2792 ((speed) ? 15 : MIPS_CALL_RATIO)
2793
2794 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2795 optimizing for size adjust the ratio to account for the overhead of
2796 loading the constant and replicating it across the word. */
2797
2798 #define SET_RATIO(speed) \
2799 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2800
2801 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2802 mips_store_by_pieces_p (SIZE, ALIGN)
2803 \f
2804 #ifndef __mips16
2805 /* Since the bits of the _init and _fini function is spread across
2806 many object files, each potentially with its own GP, we must assume
2807 we need to load our GP. We don't preserve $gp or $ra, since each
2808 init/fini chunk is supposed to initialize $gp, and crti/crtn
2809 already take care of preserving $ra and, when appropriate, $gp. */
2810 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2811 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2812 asm (SECTION_OP "\n\
2813 .set noreorder\n\
2814 bal 1f\n\
2815 nop\n\
2816 1: .cpload $31\n\
2817 .set reorder\n\
2818 jal " USER_LABEL_PREFIX #FUNC "\n\
2819 " TEXT_SECTION_ASM_OP);
2820 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2821 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2822 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2823 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2824 asm (SECTION_OP "\n\
2825 .set noreorder\n\
2826 bal 1f\n\
2827 nop\n\
2828 1: .set reorder\n\
2829 .cpsetup $31, $2, 1b\n\
2830 jal " USER_LABEL_PREFIX #FUNC "\n\
2831 " TEXT_SECTION_ASM_OP);
2832 #endif
2833 #endif
2834
2835 #ifndef HAVE_AS_TLS
2836 #define HAVE_AS_TLS 0
2837 #endif
2838
2839 #ifndef USED_FOR_TARGET
2840 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2841 struct mips_asm_switch {
2842 /* The FOO in the description above. */
2843 const char *name;
2844
2845 /* The current block nesting level, or 0 if we aren't in a block. */
2846 int nesting_level;
2847 };
2848
2849 extern const enum reg_class mips_regno_to_class[];
2850 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2851 extern const char *current_function_file; /* filename current function is in */
2852 extern int num_source_filenames; /* current .file # */
2853 extern struct mips_asm_switch mips_noreorder;
2854 extern struct mips_asm_switch mips_nomacro;
2855 extern struct mips_asm_switch mips_noat;
2856 extern int mips_dbx_regno[];
2857 extern int mips_dwarf_regno[];
2858 extern bool mips_split_p[];
2859 extern bool mips_split_hi_p[];
2860 extern enum processor mips_arch; /* which cpu to codegen for */
2861 extern enum processor mips_tune; /* which cpu to schedule for */
2862 extern int mips_isa; /* architectural level */
2863 extern const struct mips_cpu_info *mips_arch_info;
2864 extern const struct mips_cpu_info *mips_tune_info;
2865 extern bool mips_base_mips16;
2866 extern GTY(()) struct target_globals *mips16_globals;
2867 #endif
2868
2869 /* Enable querying of DFA units. */
2870 #define CPU_UNITS_QUERY 1
2871
2872 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2873 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2874
2875 /* As on most targets, we want the .eh_frame section to be read-only where
2876 possible. And as on most targets, this means two things:
2877
2878 (a) Non-locally-binding pointers must have an indirect encoding,
2879 so that the addresses in the .eh_frame section itself become
2880 locally-binding.
2881
2882 (b) A shared library's .eh_frame section must encode locally-binding
2883 pointers in a relative (relocation-free) form.
2884
2885 However, MIPS has traditionally not allowed directives like:
2886
2887 .long x-.
2888
2889 in cases where "x" is in a different section, or is not defined in the
2890 same assembly file. We are therefore unable to emit the PC-relative
2891 form required by (b) at assembly time.
2892
2893 Fortunately, the linker is able to convert absolute addresses into
2894 PC-relative addresses on our behalf. Unfortunately, only certain
2895 versions of the linker know how to do this for indirect pointers,
2896 and for personality data. We must fall back on using writable
2897 .eh_frame sections for shared libraries if the linker does not
2898 support this feature. */
2899 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2900 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2901
2902 /* For switching between MIPS16 and non-MIPS16 modes. */
2903 #define SWITCHABLE_TARGET 1
2904
2905 /* Several named MIPS patterns depend on Pmode. These patterns have the
2906 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2907 Add the appropriate suffix to generator function NAME and invoke it
2908 with arguments ARGS. */
2909 #define PMODE_INSN(NAME, ARGS) \
2910 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)