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mips.h (ISA_HAS_WSBH): Define.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS64 (mips_isa == 64)
212 #define ISA_MIPS64R2 (mips_isa == 65)
213
214 /* Architecture target defines. */
215 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
216 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
217 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
218 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
219 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
220 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
221 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
222 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
223 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
224 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
225 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
226 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
227 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
228 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
229 || mips_arch == PROCESSOR_OCTEON2)
230 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
231 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
232 || mips_arch == PROCESSOR_SB1A)
233 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
234 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
235
236 /* Scheduling target defines. */
237 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
238 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
239 || mips_tune == PROCESSOR_24KF2_1 \
240 || mips_tune == PROCESSOR_24KF1_1)
241 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
242 || mips_tune == PROCESSOR_74KF2_1 \
243 || mips_tune == PROCESSOR_74KF1_1 \
244 || mips_tune == PROCESSOR_74KF3_2)
245 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
246 || mips_tune == PROCESSOR_LOONGSON_2F)
247 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
248 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
249 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
250 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
251 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
252 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
253 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
254 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
255 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
256 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
257 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
258 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
259 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
260 || mips_tune == PROCESSOR_OCTEON2)
261 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
262 || mips_tune == PROCESSOR_SB1A)
263
264 /* Whether vector modes and intrinsics for ST Microelectronics
265 Loongson-2E/2F processors should be enabled. In o32 pairs of
266 floating-point registers provide 64-bit values. */
267 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
268 && (TARGET_LOONGSON_2EF \
269 || TARGET_LOONGSON_3A))
270
271 /* True if the pre-reload scheduler should try to create chains of
272 multiply-add or multiply-subtract instructions. For example,
273 suppose we have:
274
275 t1 = a * b
276 t2 = t1 + c * d
277 t3 = e * f
278 t4 = t3 - g * h
279
280 t1 will have a higher priority than t2 and t3 will have a higher
281 priority than t4. However, before reload, there is no dependence
282 between t1 and t3, and they can often have similar priorities.
283 The scheduler will then tend to prefer:
284
285 t1 = a * b
286 t3 = e * f
287 t2 = t1 + c * d
288 t4 = t3 - g * h
289
290 which stops us from making full use of macc/madd-style instructions.
291 This sort of situation occurs frequently in Fourier transforms and
292 in unrolled loops.
293
294 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
295 queue so that chained multiply-add and multiply-subtract instructions
296 appear ahead of any other instruction that is likely to clobber lo.
297 In the example above, if t2 and t3 become ready at the same time,
298 the code ensures that t2 is scheduled first.
299
300 Multiply-accumulate instructions are a bigger win for some targets
301 than others, so this macro is defined on an opt-in basis. */
302 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
303 || TUNE_MIPS4120 \
304 || TUNE_MIPS4130 \
305 || TUNE_24K)
306
307 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
308 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
309
310 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
311 directly accessible, while the command-line options select
312 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
313 in use. */
314 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
315 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
316
317 /* False if SC acts as a memory barrier with respect to itself,
318 otherwise a SYNC will be emitted after SC for atomic operations
319 that require ordering between the SC and following loads and
320 stores. It does not tell anything about ordering of loads and
321 stores prior to and following the SC, only about the SC itself and
322 those loads and stores follow it. */
323 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
324
325 /* Define preprocessor macros for the -march and -mtune options.
326 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
327 processor. If INFO's canonical name is "foo", define PREFIX to
328 be "foo", and define an additional macro PREFIX_FOO. */
329 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
330 do \
331 { \
332 char *macro, *p; \
333 \
334 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
335 for (p = macro; *p != 0; p++) \
336 if (*p == '+') \
337 *p = 'P'; \
338 else \
339 *p = TOUPPER (*p); \
340 \
341 builtin_define (macro); \
342 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
343 free (macro); \
344 } \
345 while (0)
346
347 /* Target CPU builtins. */
348 #define TARGET_CPU_CPP_BUILTINS() \
349 do \
350 { \
351 builtin_assert ("machine=mips"); \
352 builtin_assert ("cpu=mips"); \
353 builtin_define ("__mips__"); \
354 builtin_define ("_mips"); \
355 \
356 /* We do this here because __mips is defined below and so we \
357 can't use builtin_define_std. We don't ever want to define \
358 "mips" for VxWorks because some of the VxWorks headers \
359 construct include filenames from a root directory macro, \
360 an architecture macro and a filename, where the architecture \
361 macro expands to 'mips'. If we define 'mips' to 1, the \
362 architecture macro expands to 1 as well. */ \
363 if (!flag_iso && !TARGET_VXWORKS) \
364 builtin_define ("mips"); \
365 \
366 if (TARGET_64BIT) \
367 builtin_define ("__mips64"); \
368 \
369 /* Treat _R3000 and _R4000 like register-size \
370 defines, which is how they've historically \
371 been used. */ \
372 if (TARGET_64BIT) \
373 { \
374 builtin_define_std ("R4000"); \
375 builtin_define ("_R4000"); \
376 } \
377 else \
378 { \
379 builtin_define_std ("R3000"); \
380 builtin_define ("_R3000"); \
381 } \
382 \
383 if (TARGET_FLOAT64) \
384 builtin_define ("__mips_fpr=64"); \
385 else \
386 builtin_define ("__mips_fpr=32"); \
387 \
388 if (mips_base_compression_flags & MASK_MIPS16) \
389 builtin_define ("__mips16"); \
390 \
391 if (TARGET_MIPS3D) \
392 builtin_define ("__mips3d"); \
393 \
394 if (TARGET_SMARTMIPS) \
395 builtin_define ("__mips_smartmips"); \
396 \
397 if (mips_base_compression_flags & MASK_MICROMIPS) \
398 builtin_define ("__mips_micromips"); \
399 \
400 if (TARGET_MCU) \
401 builtin_define ("__mips_mcu"); \
402 \
403 if (TARGET_EVA) \
404 builtin_define ("__mips_eva"); \
405 \
406 if (TARGET_DSP) \
407 { \
408 builtin_define ("__mips_dsp"); \
409 if (TARGET_DSPR2) \
410 { \
411 builtin_define ("__mips_dspr2"); \
412 builtin_define ("__mips_dsp_rev=2"); \
413 } \
414 else \
415 builtin_define ("__mips_dsp_rev=1"); \
416 } \
417 \
418 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
419 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
420 \
421 if (ISA_MIPS1) \
422 { \
423 builtin_define ("__mips=1"); \
424 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
425 } \
426 else if (ISA_MIPS2) \
427 { \
428 builtin_define ("__mips=2"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
430 } \
431 else if (ISA_MIPS3) \
432 { \
433 builtin_define ("__mips=3"); \
434 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
435 } \
436 else if (ISA_MIPS4) \
437 { \
438 builtin_define ("__mips=4"); \
439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
440 } \
441 else if (ISA_MIPS32) \
442 { \
443 builtin_define ("__mips=32"); \
444 builtin_define ("__mips_isa_rev=1"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
446 } \
447 else if (ISA_MIPS32R2) \
448 { \
449 builtin_define ("__mips=32"); \
450 builtin_define ("__mips_isa_rev=2"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
452 } \
453 else if (ISA_MIPS64) \
454 { \
455 builtin_define ("__mips=64"); \
456 builtin_define ("__mips_isa_rev=1"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
458 } \
459 else if (ISA_MIPS64R2) \
460 { \
461 builtin_define ("__mips=64"); \
462 builtin_define ("__mips_isa_rev=2"); \
463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
464 } \
465 \
466 switch (mips_abi) \
467 { \
468 case ABI_32: \
469 builtin_define ("_ABIO32=1"); \
470 builtin_define ("_MIPS_SIM=_ABIO32"); \
471 break; \
472 \
473 case ABI_N32: \
474 builtin_define ("_ABIN32=2"); \
475 builtin_define ("_MIPS_SIM=_ABIN32"); \
476 break; \
477 \
478 case ABI_64: \
479 builtin_define ("_ABI64=3"); \
480 builtin_define ("_MIPS_SIM=_ABI64"); \
481 break; \
482 \
483 case ABI_O64: \
484 builtin_define ("_ABIO64=4"); \
485 builtin_define ("_MIPS_SIM=_ABIO64"); \
486 break; \
487 } \
488 \
489 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
490 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
491 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
492 builtin_define_with_int_value ("_MIPS_FPSET", \
493 32 / MAX_FPRS_PER_FMT); \
494 \
495 /* These defines reflect the ABI in use, not whether the \
496 FPU is directly accessible. */ \
497 if (TARGET_NO_FLOAT) \
498 builtin_define ("__mips_no_float"); \
499 else if (TARGET_HARD_FLOAT_ABI) \
500 builtin_define ("__mips_hard_float"); \
501 else \
502 builtin_define ("__mips_soft_float"); \
503 \
504 if (TARGET_SINGLE_FLOAT) \
505 builtin_define ("__mips_single_float"); \
506 \
507 if (TARGET_PAIRED_SINGLE_FLOAT) \
508 builtin_define ("__mips_paired_single_float"); \
509 \
510 if (mips_abs == MIPS_IEEE_754_2008) \
511 builtin_define ("__mips_abs2008"); \
512 \
513 if (mips_nan == MIPS_IEEE_754_2008) \
514 builtin_define ("__mips_nan2008"); \
515 \
516 if (TARGET_BIG_ENDIAN) \
517 { \
518 builtin_define_std ("MIPSEB"); \
519 builtin_define ("_MIPSEB"); \
520 } \
521 else \
522 { \
523 builtin_define_std ("MIPSEL"); \
524 builtin_define ("_MIPSEL"); \
525 } \
526 \
527 /* Whether calls should go through $25. The separate __PIC__ \
528 macro indicates whether abicalls code might use a GOT. */ \
529 if (TARGET_ABICALLS) \
530 builtin_define ("__mips_abicalls"); \
531 \
532 /* Whether Loongson vector modes are enabled. */ \
533 if (TARGET_LOONGSON_VECTORS) \
534 builtin_define ("__mips_loongson_vector_rev"); \
535 \
536 /* Historical Octeon macro. */ \
537 if (TARGET_OCTEON) \
538 builtin_define ("__OCTEON__"); \
539 \
540 if (TARGET_SYNCI) \
541 builtin_define ("__mips_synci"); \
542 \
543 /* Macros dependent on the C dialect. */ \
544 if (preprocessing_asm_p ()) \
545 { \
546 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
547 builtin_define ("_LANGUAGE_ASSEMBLY"); \
548 } \
549 else if (c_dialect_cxx ()) \
550 { \
551 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
552 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
553 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
554 } \
555 else \
556 { \
557 builtin_define_std ("LANGUAGE_C"); \
558 builtin_define ("_LANGUAGE_C"); \
559 } \
560 if (c_dialect_objc ()) \
561 { \
562 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
563 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
564 /* Bizarre, but retained for backwards compatibility. */ \
565 builtin_define_std ("LANGUAGE_C"); \
566 builtin_define ("_LANGUAGE_C"); \
567 } \
568 \
569 if (mips_abi == ABI_EABI) \
570 builtin_define ("__mips_eabi"); \
571 \
572 if (TARGET_CACHE_BUILTIN) \
573 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
574 } \
575 while (0)
576
577 /* Default target_flags if no switches are specified */
578
579 #ifndef TARGET_DEFAULT
580 #define TARGET_DEFAULT 0
581 #endif
582
583 #ifndef TARGET_CPU_DEFAULT
584 #define TARGET_CPU_DEFAULT 0
585 #endif
586
587 #ifndef TARGET_ENDIAN_DEFAULT
588 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
589 #endif
590
591 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
592 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
593 #endif
594
595 #ifdef IN_LIBGCC2
596 #undef TARGET_64BIT
597 /* Make this compile time constant for libgcc2 */
598 #ifdef __mips64
599 #define TARGET_64BIT 1
600 #else
601 #define TARGET_64BIT 0
602 #endif
603 #endif /* IN_LIBGCC2 */
604
605 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
606 when compiled with hardware floating point. This is because MIPS16
607 code cannot save and restore the floating-point registers, which is
608 important if in a mixed MIPS16/non-MIPS16 environment. */
609
610 #ifdef IN_LIBGCC2
611 #if __mips_hard_float
612 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
613 #endif
614 #endif /* IN_LIBGCC2 */
615
616 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
617
618 #ifndef MULTILIB_ENDIAN_DEFAULT
619 #if TARGET_ENDIAN_DEFAULT == 0
620 #define MULTILIB_ENDIAN_DEFAULT "EL"
621 #else
622 #define MULTILIB_ENDIAN_DEFAULT "EB"
623 #endif
624 #endif
625
626 #ifndef MULTILIB_ISA_DEFAULT
627 #if MIPS_ISA_DEFAULT == 1
628 #define MULTILIB_ISA_DEFAULT "mips1"
629 #elif MIPS_ISA_DEFAULT == 2
630 #define MULTILIB_ISA_DEFAULT "mips2"
631 #elif MIPS_ISA_DEFAULT == 3
632 #define MULTILIB_ISA_DEFAULT "mips3"
633 #elif MIPS_ISA_DEFAULT == 4
634 #define MULTILIB_ISA_DEFAULT "mips4"
635 #elif MIPS_ISA_DEFAULT == 32
636 #define MULTILIB_ISA_DEFAULT "mips32"
637 #elif MIPS_ISA_DEFAULT == 33
638 #define MULTILIB_ISA_DEFAULT "mips32r2"
639 #elif MIPS_ISA_DEFAULT == 64
640 #define MULTILIB_ISA_DEFAULT "mips64"
641 #elif MIPS_ISA_DEFAULT == 65
642 #define MULTILIB_ISA_DEFAULT "mips64r2"
643 #else
644 #define MULTILIB_ISA_DEFAULT "mips1"
645 #endif
646 #endif
647
648 #ifndef MIPS_ABI_DEFAULT
649 #define MIPS_ABI_DEFAULT ABI_32
650 #endif
651
652 /* Use the most portable ABI flag for the ASM specs. */
653
654 #if MIPS_ABI_DEFAULT == ABI_32
655 #define MULTILIB_ABI_DEFAULT "mabi=32"
656 #elif MIPS_ABI_DEFAULT == ABI_O64
657 #define MULTILIB_ABI_DEFAULT "mabi=o64"
658 #elif MIPS_ABI_DEFAULT == ABI_N32
659 #define MULTILIB_ABI_DEFAULT "mabi=n32"
660 #elif MIPS_ABI_DEFAULT == ABI_64
661 #define MULTILIB_ABI_DEFAULT "mabi=64"
662 #elif MIPS_ABI_DEFAULT == ABI_EABI
663 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
664 #endif
665
666 #ifndef MULTILIB_DEFAULTS
667 #define MULTILIB_DEFAULTS \
668 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
669 #endif
670
671 /* We must pass -EL to the linker by default for little endian embedded
672 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
673 linker will default to using big-endian output files. The OUTPUT_FORMAT
674 line must be in the linker script, otherwise -EB/-EL will not work. */
675
676 #ifndef ENDIAN_SPEC
677 #if TARGET_ENDIAN_DEFAULT == 0
678 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
679 #else
680 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
681 #endif
682 #endif
683
684 /* A spec condition that matches all non-mips16 -mips arguments. */
685
686 #define MIPS_ISA_LEVEL_OPTION_SPEC \
687 "mips1|mips2|mips3|mips4|mips32*|mips64*"
688
689 /* A spec condition that matches all non-mips16 architecture arguments. */
690
691 #define MIPS_ARCH_OPTION_SPEC \
692 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
693
694 /* A spec that infers a -mips argument from an -march argument,
695 or injects the default if no architecture is specified. */
696
697 #define MIPS_ISA_LEVEL_SPEC \
698 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
699 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
700 %{march=mips2|march=r6000:-mips2} \
701 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
702 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
703 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
704 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
705 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
706 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
707 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
708 |march=xlr|march=loongson3a: -mips64} \
709 %{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
710 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
711
712 /* A spec that infers a -mhard-float or -msoft-float setting from an
713 -march argument. Note that soft-float and hard-float code are not
714 link-compatible. */
715
716 #define MIPS_ARCH_FLOAT_SPEC \
717 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
718 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
719 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
720 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
721 march=*: -mhard-float}"
722
723 /* A spec condition that matches 32-bit options. It only works if
724 MIPS_ISA_LEVEL_SPEC has been applied. */
725
726 #define MIPS_32BIT_OPTION_SPEC \
727 "mips1|mips2|mips32*|mgp32"
728
729 /* Infer a -msynci setting from a -mips argument, on the assumption that
730 -msynci is desired where possible. */
731 #define MIPS_ISA_SYNCI_SPEC \
732 "%{msynci|mno-synci:;:%{mips32r2|mips64r2:-msynci;:-mno-synci}}"
733
734 #if (MIPS_ABI_DEFAULT == ABI_O64 \
735 || MIPS_ABI_DEFAULT == ABI_N32 \
736 || MIPS_ABI_DEFAULT == ABI_64)
737 #define OPT_ARCH64 "mabi=32|mgp32:;"
738 #define OPT_ARCH32 "mabi=32|mgp32"
739 #else
740 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
741 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
742 #endif
743
744 /* Support for a compile-time default CPU, et cetera. The rules are:
745 --with-arch is ignored if -march is specified or a -mips is specified
746 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
747 --with-tune is ignored if -mtune is specified; likewise
748 --with-tune-32 and --with-tune-64.
749 --with-abi is ignored if -mabi is specified.
750 --with-float is ignored if -mhard-float or -msoft-float are
751 specified.
752 --with-nan is ignored if -mnan is specified.
753 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
754 specified. */
755 #define OPTION_DEFAULT_SPECS \
756 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
757 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
758 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
759 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
760 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
761 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
762 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
763 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
764 {"fpu", "%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}" }, \
765 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
766 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
767 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
768 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
769 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
770
771 /* A spec that infers the -mdsp setting from an -march argument. */
772 #define BASE_DRIVER_SELF_SPECS \
773 "%{!mno-dsp: \
774 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
775 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
776
777 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
778
779 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
780 && ISA_HAS_COND_TRAP)
781
782 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
783
784 /* True if the ABI can only work with 64-bit integer registers. We
785 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
786 otherwise floating-point registers must also be 64-bit. */
787 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
788
789 /* Likewise for 32-bit regs. */
790 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
791
792 /* True if the file format uses 64-bit symbols. At present, this is
793 only true for n64, which uses 64-bit ELF. */
794 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
795
796 /* True if symbols are 64 bits wide. This is usually determined by
797 the ABI's file format, but it can be overridden by -msym32. Note that
798 overriding the size with -msym32 changes the ABI of relocatable objects,
799 although it doesn't change the ABI of a fully-linked object. */
800 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
801 && Pmode == DImode \
802 && !TARGET_SYM32)
803
804 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
805 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
806 || ISA_MIPS4 \
807 || ISA_MIPS64 \
808 || ISA_MIPS64R2)
809
810 /* ISA has branch likely instructions (e.g. mips2). */
811 /* Disable branchlikely for tx39 until compare rewrite. They haven't
812 been generated up to this point. */
813 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
814
815 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
816 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
817 || TARGET_MIPS5400 \
818 || TARGET_MIPS5500 \
819 || TARGET_MIPS5900 \
820 || TARGET_MIPS7000 \
821 || TARGET_MIPS9000 \
822 || TARGET_MAD \
823 || ISA_MIPS32 \
824 || ISA_MIPS32R2 \
825 || ISA_MIPS64 \
826 || ISA_MIPS64R2) \
827 && !TARGET_MIPS16)
828
829 /* ISA has a three-operand multiplication instruction. */
830 #define ISA_HAS_DMUL3 (TARGET_64BIT \
831 && TARGET_OCTEON \
832 && !TARGET_MIPS16)
833
834 /* ISA supports instructions DMULT and DMULTU. */
835 #define ISA_HAS_DMULT (TARGET_64BIT && !TARGET_MIPS5900)
836
837 /* ISA supports instructions MULT and MULTU.
838 This is always true, but the macro is needed for ISA_HAS_<D>MULT
839 in mips.md. */
840 #define ISA_HAS_MULT (1)
841
842 /* ISA supports instructions DDIV and DDIVU. */
843 #define ISA_HAS_DDIV (TARGET_64BIT && !TARGET_MIPS5900)
844
845 /* ISA supports instructions DIV and DIVU.
846 This is always true, but the macro is needed for ISA_HAS_<D>DIV
847 in mips.md. */
848 #define ISA_HAS_DIV (1)
849
850 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
851 || TARGET_LOONGSON_3A) \
852 && !TARGET_MIPS16)
853
854 /* ISA has the floating-point conditional move instructions introduced
855 in mips4. */
856 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
857 || ISA_MIPS32 \
858 || ISA_MIPS32R2 \
859 || ISA_MIPS64 \
860 || ISA_MIPS64R2) \
861 && !TARGET_MIPS5500 \
862 && !TARGET_MIPS16)
863
864 /* ISA has the integer conditional move instructions introduced in mips4 and
865 ST Loongson 2E/2F. */
866 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
867 || TARGET_MIPS5900 \
868 || TARGET_LOONGSON_2EF)
869
870 /* ISA has LDC1 and SDC1. */
871 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
872 && !TARGET_MIPS5900 \
873 && !TARGET_MIPS16)
874
875 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
876 branch on CC, and move (both FP and non-FP) on CC. */
877 #define ISA_HAS_8CC (ISA_MIPS4 \
878 || ISA_MIPS32 \
879 || ISA_MIPS32R2 \
880 || ISA_MIPS64 \
881 || ISA_MIPS64R2)
882
883 /* This is a catch all for other mips4 instructions: indexed load, the
884 FP madd and msub instructions, and the FP recip and recip sqrt
885 instructions. */
886 #define ISA_HAS_FP4 ((ISA_MIPS4 \
887 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
888 || ISA_MIPS64 \
889 || ISA_MIPS64R2) \
890 && !TARGET_MIPS16)
891
892 /* ISA has paired-single instructions. */
893 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
894
895 /* ISA has conditional trap instructions. */
896 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
897 && !TARGET_MIPS16)
898
899 /* ISA has integer multiply-accumulate instructions, madd and msub. */
900 #define ISA_HAS_MADD_MSUB (ISA_MIPS32 \
901 || ISA_MIPS32R2 \
902 || ISA_MIPS64 \
903 || ISA_MIPS64R2)
904
905 /* Integer multiply-accumulate instructions should be generated. */
906 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
907
908 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
909 #define ISA_HAS_FP_MADD4_MSUB4 (ISA_HAS_FP4 \
910 || (ISA_MIPS32R2 && !TARGET_MIPS16))
911
912 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
913 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
914
915 /* ISA has floating-point nmadd and nmsub instructions
916 'd = -((a * b) [+-] c)'. */
917 #define ISA_HAS_NMADD4_NMSUB4 (ISA_HAS_FP4 \
918 || (ISA_MIPS32R2 && !TARGET_MIPS16))
919
920 /* ISA has floating-point nmadd and nmsub instructions
921 'c = -((a * b) [+-] c)'. */
922 #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF
923
924 /* ISA has count leading zeroes/ones instruction (not implemented). */
925 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
926 || ISA_MIPS32R2 \
927 || ISA_MIPS64 \
928 || ISA_MIPS64R2) \
929 && !TARGET_MIPS16)
930
931 /* ISA has three operand multiply instructions that put
932 the high part in an accumulator: mulhi or mulhiu. */
933 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
934 || TARGET_MIPS5500 \
935 || TARGET_SR71K) \
936 && !TARGET_MIPS16)
937
938 /* ISA has three operand multiply instructions that negate the
939 result and put the result in an accumulator. */
940 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
941 || TARGET_MIPS5500 \
942 || TARGET_SR71K) \
943 && !TARGET_MIPS16)
944
945 /* ISA has three operand multiply instructions that subtract the
946 result from a 4th operand and put the result in an accumulator. */
947 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
948 || TARGET_MIPS5500 \
949 || TARGET_SR71K) \
950 && !TARGET_MIPS16)
951
952 /* ISA has three operand multiply instructions that add the result
953 to a 4th operand and put the result in an accumulator. */
954 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
955 || TARGET_MIPS4130 \
956 || TARGET_MIPS5400 \
957 || TARGET_MIPS5500 \
958 || TARGET_SR71K) \
959 && !TARGET_MIPS16)
960
961 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
962 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
963 || TARGET_MIPS4130) \
964 && !TARGET_MIPS16)
965
966 /* ISA has the "ror" (rotate right) instructions. */
967 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
968 || ISA_MIPS64R2 \
969 || TARGET_MIPS5400 \
970 || TARGET_MIPS5500 \
971 || TARGET_SR71K \
972 || TARGET_SMARTMIPS) \
973 && !TARGET_MIPS16)
974
975 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
976 64-bit targets also provide DSBH and DSHD. */
977 #define ISA_HAS_WSBH ((ISA_MIPS32R2 || ISA_MIPS64R2) \
978 && !TARGET_MIPS16)
979
980 /* ISA has data prefetch instructions. This controls use of 'pref'. */
981 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
982 || TARGET_LOONGSON_2EF \
983 || TARGET_MIPS5900 \
984 || ISA_MIPS32 \
985 || ISA_MIPS32R2 \
986 || ISA_MIPS64 \
987 || ISA_MIPS64R2) \
988 && !TARGET_MIPS16)
989
990 /* ISA has data indexed prefetch instructions. This controls use of
991 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
992 (prefx is a cop1x instruction, so can only be used if FP is
993 enabled.) */
994 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
995 || ISA_MIPS32R2 \
996 || ISA_MIPS64 \
997 || ISA_MIPS64R2) \
998 && !TARGET_MIPS16)
999
1000 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1001 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1002 also requires TARGET_DOUBLE_FLOAT. */
1003 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1004
1005 /* ISA includes the MIPS32r2 seb and seh instructions. */
1006 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
1007 || ISA_MIPS64R2) \
1008 && !TARGET_MIPS16)
1009
1010 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1011 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
1012 || ISA_MIPS64R2) \
1013 && !TARGET_MIPS16)
1014
1015 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1016 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
1017 && (ISA_MIPS32R2 \
1018 || ISA_MIPS64R2))
1019
1020 /* ISA has lwxs instruction (load w/scaled index address. */
1021 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1022 && !TARGET_MIPS16)
1023
1024 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1025 #define ISA_HAS_LBX (TARGET_OCTEON2)
1026 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1027 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1028 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1029 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1030 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1031 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1032 && TARGET_64BIT)
1033
1034 /* The DSP ASE is available. */
1035 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1036
1037 /* Revision 2 of the DSP ASE is available. */
1038 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1039
1040 /* True if the result of a load is not available to the next instruction.
1041 A nop will then be needed between instructions like "lw $4,..."
1042 and "addiu $4,$4,1". */
1043 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1044 && !TARGET_MIPS3900 \
1045 && !TARGET_MIPS5900 \
1046 && !TARGET_MIPS16 \
1047 && !TARGET_MICROMIPS)
1048
1049 /* Likewise mtc1 and mfc1. */
1050 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1051 && !TARGET_MIPS5900 \
1052 && !TARGET_LOONGSON_2EF)
1053
1054 /* Likewise floating-point comparisons. */
1055 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1056 && !TARGET_MIPS5900 \
1057 && !TARGET_LOONGSON_2EF)
1058
1059 /* True if mflo and mfhi can be immediately followed by instructions
1060 which write to the HI and LO registers.
1061
1062 According to MIPS specifications, MIPS ISAs I, II, and III need
1063 (at least) two instructions between the reads of HI/LO and
1064 instructions which write them, and later ISAs do not. Contradicting
1065 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1066 the UM for the NEC Vr5000) document needing the instructions between
1067 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1068 MIPS64 and later ISAs to have the interlocks, plus any specific
1069 earlier-ISA CPUs for which CPU documentation declares that the
1070 instructions are really interlocked. */
1071 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1072 || ISA_MIPS32R2 \
1073 || ISA_MIPS64 \
1074 || ISA_MIPS64R2 \
1075 || TARGET_MIPS5500 \
1076 || TARGET_MIPS5900 \
1077 || TARGET_LOONGSON_2EF)
1078
1079 /* ISA includes synci, jr.hb and jalr.hb. */
1080 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1081 || ISA_MIPS64R2) \
1082 && !TARGET_MIPS16)
1083
1084 /* ISA includes sync. */
1085 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1086 #define GENERATE_SYNC \
1087 (target_flags_explicit & MASK_LLSC \
1088 ? TARGET_LLSC && !TARGET_MIPS16 \
1089 : ISA_HAS_SYNC)
1090
1091 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1092 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1093 instructions. */
1094 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1095 #define GENERATE_LL_SC \
1096 (target_flags_explicit & MASK_LLSC \
1097 ? TARGET_LLSC && !TARGET_MIPS16 \
1098 : ISA_HAS_LL_SC)
1099
1100 #define ISA_HAS_SWAP (TARGET_XLP)
1101 #define ISA_HAS_LDADD (TARGET_XLP)
1102
1103 /* ISA includes the baddu instruction. */
1104 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1105
1106 /* ISA includes the bbit* instructions. */
1107 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1108
1109 /* ISA includes the cins instruction. */
1110 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1111
1112 /* ISA includes the exts instruction. */
1113 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1114
1115 /* ISA includes the seq and sne instructions. */
1116 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1117
1118 /* ISA includes the pop instruction. */
1119 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1120
1121 /* The CACHE instruction is available in non-MIPS16 code. */
1122 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1123
1124 /* The CACHE instruction is available. */
1125 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1126 \f
1127 /* Tell collect what flags to pass to nm. */
1128 #ifndef NM_FLAGS
1129 #define NM_FLAGS "-Bn"
1130 #endif
1131
1132 \f
1133 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1134 the assembler. It may be overridden by subtargets.
1135
1136 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1137 COFF debugging info. */
1138
1139 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1140 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1141 %{g} %{g0} %{g1} %{g2} %{g3} \
1142 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1143 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1144 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1145 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1146 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1147 #endif
1148
1149 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1150 overridden by subtargets. */
1151
1152 #ifndef SUBTARGET_ASM_SPEC
1153 #define SUBTARGET_ASM_SPEC ""
1154 #endif
1155
1156 #undef ASM_SPEC
1157 #define ASM_SPEC "\
1158 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1159 %{mips32*} %{mips64*} \
1160 %{mips16} %{mno-mips16:-no-mips16} \
1161 %{mmicromips} %{mno-micromips} \
1162 %{mips3d} %{mno-mips3d:-no-mips3d} \
1163 %{mdmx} %{mno-mdmx:-no-mdmx} \
1164 %{mdsp} %{mno-dsp} \
1165 %{mdspr2} %{mno-dspr2} \
1166 %{mmcu} %{mno-mcu} \
1167 %{meva} %{mno-eva} \
1168 %{msmartmips} %{mno-smartmips} \
1169 %{mmt} %{mno-mt} \
1170 %{mfix-vr4120} %{mfix-vr4130} \
1171 %{mfix-24k} \
1172 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1173 %(subtarget_asm_debugging_spec) \
1174 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1175 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1176 %{mfp32} %{mfp64} %{mnan=*} \
1177 %{mshared} %{mno-shared} \
1178 %{msym32} %{mno-sym32} \
1179 %{mtune=*} \
1180 %(subtarget_asm_spec)"
1181
1182 /* Extra switches sometimes passed to the linker. */
1183
1184 #ifndef LINK_SPEC
1185 #define LINK_SPEC "\
1186 %(endian_spec) \
1187 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1188 %{shared}"
1189 #endif /* LINK_SPEC defined */
1190
1191
1192 /* Specs for the compiler proper */
1193
1194 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1195 overridden by subtargets. */
1196 #ifndef SUBTARGET_CC1_SPEC
1197 #define SUBTARGET_CC1_SPEC ""
1198 #endif
1199
1200 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1201
1202 #undef CC1_SPEC
1203 #define CC1_SPEC "\
1204 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1205 %(subtarget_cc1_spec)"
1206
1207 /* Preprocessor specs. */
1208
1209 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1210 overridden by subtargets. */
1211 #ifndef SUBTARGET_CPP_SPEC
1212 #define SUBTARGET_CPP_SPEC ""
1213 #endif
1214
1215 #define CPP_SPEC "%(subtarget_cpp_spec)"
1216
1217 /* This macro defines names of additional specifications to put in the specs
1218 that can be used in various specifications like CC1_SPEC. Its definition
1219 is an initializer with a subgrouping for each command option.
1220
1221 Each subgrouping contains a string constant, that defines the
1222 specification name, and a string constant that used by the GCC driver
1223 program.
1224
1225 Do not define this macro if it does not need to do anything. */
1226
1227 #define EXTRA_SPECS \
1228 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1229 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1230 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1231 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1232 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1233 { "endian_spec", ENDIAN_SPEC }, \
1234 SUBTARGET_EXTRA_SPECS
1235
1236 #ifndef SUBTARGET_EXTRA_SPECS
1237 #define SUBTARGET_EXTRA_SPECS
1238 #endif
1239 \f
1240 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1241 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1242
1243 #ifndef PREFERRED_DEBUGGING_TYPE
1244 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1245 #endif
1246
1247 /* The size of DWARF addresses should be the same as the size of symbols
1248 in the target file format. They shouldn't depend on things like -msym32,
1249 because many DWARF consumers do not allow the mixture of address sizes
1250 that one would then get from linking -msym32 code with -msym64 code.
1251
1252 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1253 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1254 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1255
1256 /* By default, turn on GDB extensions. */
1257 #define DEFAULT_GDB_EXTENSIONS 1
1258
1259 /* Local compiler-generated symbols must have a prefix that the assembler
1260 understands. By default, this is $, although some targets (e.g.,
1261 NetBSD-ELF) need to override this. */
1262
1263 #ifndef LOCAL_LABEL_PREFIX
1264 #define LOCAL_LABEL_PREFIX "$"
1265 #endif
1266
1267 /* By default on the mips, external symbols do not have an underscore
1268 prepended, but some targets (e.g., NetBSD) require this. */
1269
1270 #ifndef USER_LABEL_PREFIX
1271 #define USER_LABEL_PREFIX ""
1272 #endif
1273
1274 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1275 since the length can run past this up to a continuation point. */
1276 #undef DBX_CONTIN_LENGTH
1277 #define DBX_CONTIN_LENGTH 1500
1278
1279 /* How to renumber registers for dbx and gdb. */
1280 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1281
1282 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1283 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1284
1285 /* The DWARF 2 CFA column which tracks the return address. */
1286 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1287
1288 /* Before the prologue, RA lives in r31. */
1289 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1290
1291 /* Describe how we implement __builtin_eh_return. */
1292 #define EH_RETURN_DATA_REGNO(N) \
1293 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1294
1295 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1296
1297 #define EH_USES(N) mips_eh_uses (N)
1298
1299 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1300 The default for this in 64-bit mode is 8, which causes problems with
1301 SFmode register saves. */
1302 #define DWARF_CIE_DATA_ALIGNMENT -4
1303
1304 /* Correct the offset of automatic variables and arguments. Note that
1305 the MIPS debug format wants all automatic variables and arguments
1306 to be in terms of the virtual frame pointer (stack pointer before
1307 any adjustment in the function), while the MIPS 3.0 linker wants
1308 the frame pointer to be the stack pointer after the initial
1309 adjustment. */
1310
1311 #define DEBUGGER_AUTO_OFFSET(X) \
1312 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1313 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1314 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1315 \f
1316 /* Target machine storage layout */
1317
1318 #define BITS_BIG_ENDIAN 0
1319 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1320 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1321
1322 #define MAX_BITS_PER_WORD 64
1323
1324 /* Width of a word, in units (bytes). */
1325 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1326 #ifndef IN_LIBGCC2
1327 #define MIN_UNITS_PER_WORD 4
1328 #endif
1329
1330 /* For MIPS, width of a floating point register. */
1331 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1332
1333 /* The number of consecutive floating-point registers needed to store the
1334 largest format supported by the FPU. */
1335 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1336
1337 /* The number of consecutive floating-point registers needed to store the
1338 smallest format supported by the FPU. */
1339 #define MIN_FPRS_PER_FMT \
1340 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1341 ? 1 : MAX_FPRS_PER_FMT)
1342
1343 /* The largest size of value that can be held in floating-point
1344 registers and moved with a single instruction. */
1345 #define UNITS_PER_HWFPVALUE \
1346 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1347
1348 /* The largest size of value that can be held in floating-point
1349 registers. */
1350 #define UNITS_PER_FPVALUE \
1351 (TARGET_SOFT_FLOAT_ABI ? 0 \
1352 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1353 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1354
1355 /* The number of bytes in a double. */
1356 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1357
1358 /* Set the sizes of the core types. */
1359 #define SHORT_TYPE_SIZE 16
1360 #define INT_TYPE_SIZE 32
1361 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1362 #define LONG_LONG_TYPE_SIZE 64
1363
1364 #define FLOAT_TYPE_SIZE 32
1365 #define DOUBLE_TYPE_SIZE 64
1366 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1367
1368 /* Define the sizes of fixed-point types. */
1369 #define SHORT_FRACT_TYPE_SIZE 8
1370 #define FRACT_TYPE_SIZE 16
1371 #define LONG_FRACT_TYPE_SIZE 32
1372 #define LONG_LONG_FRACT_TYPE_SIZE 64
1373
1374 #define SHORT_ACCUM_TYPE_SIZE 16
1375 #define ACCUM_TYPE_SIZE 32
1376 #define LONG_ACCUM_TYPE_SIZE 64
1377 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1378 doesn't support 128-bit integers for MIPS32 currently. */
1379 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1380
1381 /* long double is not a fixed mode, but the idea is that, if we
1382 support long double, we also want a 128-bit integer type. */
1383 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1384
1385 #ifdef IN_LIBGCC2
1386 #if ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1387 || (defined _ABI64 && _MIPS_SIM == _ABI64))
1388 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1389 # else
1390 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1391 # endif
1392 #endif
1393
1394 /* Width in bits of a pointer. */
1395 #ifndef POINTER_SIZE
1396 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1397 #endif
1398
1399 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1400 #define PARM_BOUNDARY BITS_PER_WORD
1401
1402 /* Allocation boundary (in *bits*) for the code of a function. */
1403 #define FUNCTION_BOUNDARY 32
1404
1405 /* Alignment of field after `int : 0' in a structure. */
1406 #define EMPTY_FIELD_BOUNDARY 32
1407
1408 /* Every structure's size must be a multiple of this. */
1409 /* 8 is observed right on a DECstation and on riscos 4.02. */
1410 #define STRUCTURE_SIZE_BOUNDARY 8
1411
1412 /* There is no point aligning anything to a rounder boundary than this. */
1413 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1414
1415 /* All accesses must be aligned. */
1416 #define STRICT_ALIGNMENT 1
1417
1418 /* Define this if you wish to imitate the way many other C compilers
1419 handle alignment of bitfields and the structures that contain
1420 them.
1421
1422 The behavior is that the type written for a bit-field (`int',
1423 `short', or other integer type) imposes an alignment for the
1424 entire structure, as if the structure really did contain an
1425 ordinary field of that type. In addition, the bit-field is placed
1426 within the structure so that it would fit within such a field,
1427 not crossing a boundary for it.
1428
1429 Thus, on most machines, a bit-field whose type is written as `int'
1430 would not cross a four-byte boundary, and would force four-byte
1431 alignment for the whole structure. (The alignment used may not
1432 be four bytes; it is controlled by the other alignment
1433 parameters.)
1434
1435 If the macro is defined, its definition should be a C expression;
1436 a nonzero value for the expression enables this behavior. */
1437
1438 #define PCC_BITFIELD_TYPE_MATTERS 1
1439
1440 /* If defined, a C expression to compute the alignment given to a
1441 constant that is being placed in memory. CONSTANT is the constant
1442 and ALIGN is the alignment that the object would ordinarily have.
1443 The value of this macro is used instead of that alignment to align
1444 the object.
1445
1446 If this macro is not defined, then ALIGN is used.
1447
1448 The typical use of this macro is to increase alignment for string
1449 constants to be word aligned so that `strcpy' calls that copy
1450 constants can be done inline. */
1451
1452 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1453 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1454 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1455
1456 /* If defined, a C expression to compute the alignment for a static
1457 variable. TYPE is the data type, and ALIGN is the alignment that
1458 the object would ordinarily have. The value of this macro is used
1459 instead of that alignment to align the object.
1460
1461 If this macro is not defined, then ALIGN is used.
1462
1463 One use of this macro is to increase alignment of medium-size
1464 data to make it all fit in fewer cache lines. Another is to
1465 cause character arrays to be word-aligned so that `strcpy' calls
1466 that copy constants to character arrays can be done inline. */
1467
1468 #undef DATA_ALIGNMENT
1469 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1470 ((((ALIGN) < BITS_PER_WORD) \
1471 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1472 || TREE_CODE (TYPE) == UNION_TYPE \
1473 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1474
1475 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1476 character arrays to be word-aligned so that `strcpy' calls that copy
1477 constants to character arrays can be done inline, and 'strcmp' can be
1478 optimised to use word loads. */
1479 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1480 DATA_ALIGNMENT (TYPE, ALIGN)
1481
1482 #define PAD_VARARGS_DOWN \
1483 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1484
1485 /* Define if operations between registers always perform the operation
1486 on the full register even if a narrower mode is specified. */
1487 #define WORD_REGISTER_OPERATIONS
1488
1489 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1490 moves. All other references are zero extended. */
1491 #define LOAD_EXTEND_OP(MODE) \
1492 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1493 ? SIGN_EXTEND : ZERO_EXTEND)
1494
1495 /* Define this macro if it is advisable to hold scalars in registers
1496 in a wider mode than that declared by the program. In such cases,
1497 the value is constrained to be within the bounds of the declared
1498 type, but kept valid in the wider mode. The signedness of the
1499 extension may differ from that of the type. */
1500
1501 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1502 if (GET_MODE_CLASS (MODE) == MODE_INT \
1503 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1504 { \
1505 if ((MODE) == SImode) \
1506 (UNSIGNEDP) = 0; \
1507 (MODE) = Pmode; \
1508 }
1509
1510 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1511 Extensions of pointers to word_mode must be signed. */
1512 #define POINTERS_EXTEND_UNSIGNED false
1513
1514 /* Define if loading short immediate values into registers sign extends. */
1515 #define SHORT_IMMEDIATES_SIGN_EXTEND
1516
1517 /* The [d]clz instructions have the natural values at 0. */
1518
1519 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1520 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1521 \f
1522 /* Standard register usage. */
1523
1524 /* Number of hardware registers. We have:
1525
1526 - 32 integer registers
1527 - 32 floating point registers
1528 - 8 condition code registers
1529 - 2 accumulator registers (hi and lo)
1530 - 32 registers each for coprocessors 0, 2 and 3
1531 - 4 fake registers:
1532 - ARG_POINTER_REGNUM
1533 - FRAME_POINTER_REGNUM
1534 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1535 - CPRESTORE_SLOT_REGNUM
1536 - 2 dummy entries that were used at various times in the past.
1537 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1538 - 6 DSP control registers */
1539
1540 #define FIRST_PSEUDO_REGISTER 188
1541
1542 /* By default, fix the kernel registers ($26 and $27), the global
1543 pointer ($28) and the stack pointer ($29). This can change
1544 depending on the command-line options.
1545
1546 Regarding coprocessor registers: without evidence to the contrary,
1547 it's best to assume that each coprocessor register has a unique
1548 use. This can be overridden, in, e.g., mips_option_override or
1549 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1550 inappropriate for a particular target. */
1551
1552 #define FIXED_REGISTERS \
1553 { \
1554 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1555 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1556 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1557 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1558 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1559 /* COP0 registers */ \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1561 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1562 /* COP2 registers */ \
1563 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1565 /* COP3 registers */ \
1566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1567 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1568 /* 6 DSP accumulator registers & 6 control registers */ \
1569 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1570 }
1571
1572
1573 /* Set up this array for o32 by default.
1574
1575 Note that we don't mark $31 as a call-clobbered register. The idea is
1576 that it's really the call instructions themselves which clobber $31.
1577 We don't care what the called function does with it afterwards.
1578
1579 This approach makes it easier to implement sibcalls. Unlike normal
1580 calls, sibcalls don't clobber $31, so the register reaches the
1581 called function in tact. EPILOGUE_USES says that $31 is useful
1582 to the called function. */
1583
1584 #define CALL_USED_REGISTERS \
1585 { \
1586 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1587 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1588 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1589 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1590 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1591 /* COP0 registers */ \
1592 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1593 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1594 /* COP2 registers */ \
1595 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1596 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1597 /* COP3 registers */ \
1598 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1599 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1600 /* 6 DSP accumulator registers & 6 control registers */ \
1601 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1602 }
1603
1604
1605 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1606
1607 #define CALL_REALLY_USED_REGISTERS \
1608 { /* General registers. */ \
1609 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1610 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1611 /* Floating-point registers. */ \
1612 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1613 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1614 /* Others. */ \
1615 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1616 /* COP0 registers */ \
1617 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1618 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1619 /* COP2 registers */ \
1620 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1621 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1622 /* COP3 registers */ \
1623 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1624 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1625 /* 6 DSP accumulator registers & 6 control registers */ \
1626 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1627 }
1628
1629 /* Internal macros to classify a register number as to whether it's a
1630 general purpose register, a floating point register, a
1631 multiply/divide register, or a status register. */
1632
1633 #define GP_REG_FIRST 0
1634 #define GP_REG_LAST 31
1635 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1636 #define GP_DBX_FIRST 0
1637 #define K0_REG_NUM (GP_REG_FIRST + 26)
1638 #define K1_REG_NUM (GP_REG_FIRST + 27)
1639 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1640
1641 #define FP_REG_FIRST 32
1642 #define FP_REG_LAST 63
1643 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1644 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1645
1646 #define MD_REG_FIRST 64
1647 #define MD_REG_LAST 65
1648 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1649 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1650
1651 /* The DWARF 2 CFA column which tracks the return address from a
1652 signal handler context. This means that to maintain backwards
1653 compatibility, no hard register can be assigned this column if it
1654 would need to be handled by the DWARF unwinder. */
1655 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1656
1657 #define ST_REG_FIRST 67
1658 #define ST_REG_LAST 74
1659 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1660
1661
1662 /* FIXME: renumber. */
1663 #define COP0_REG_FIRST 80
1664 #define COP0_REG_LAST 111
1665 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1666
1667 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1668 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1669 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1670
1671 #define COP2_REG_FIRST 112
1672 #define COP2_REG_LAST 143
1673 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1674
1675 #define COP3_REG_FIRST 144
1676 #define COP3_REG_LAST 175
1677 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1678
1679 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1680 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1681 #define ALL_COP_REG_LAST COP3_REG_LAST
1682 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1683
1684 #define DSP_ACC_REG_FIRST 176
1685 #define DSP_ACC_REG_LAST 181
1686 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1687
1688 #define AT_REGNUM (GP_REG_FIRST + 1)
1689 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1690 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1691
1692 /* A few bitfield locations for the coprocessor registers. */
1693 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1694 the cause register for the EIC interrupt mode. */
1695 #define CAUSE_IPL 10
1696 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1697 #define SR_IPL 10
1698 /* Exception Level is at bit 1 of the status register. */
1699 #define SR_EXL 1
1700 /* Interrupt Enable is at bit 0 of the status register. */
1701 #define SR_IE 0
1702
1703 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1704 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1705 should be used instead. */
1706 #define FPSW_REGNUM ST_REG_FIRST
1707
1708 #define GP_REG_P(REGNO) \
1709 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1710 #define M16_REG_P(REGNO) \
1711 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1712 #define M16STORE_REG_P(REGNO) \
1713 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1714 #define FP_REG_P(REGNO) \
1715 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1716 #define MD_REG_P(REGNO) \
1717 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1718 #define ST_REG_P(REGNO) \
1719 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1720 #define COP0_REG_P(REGNO) \
1721 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1722 #define COP2_REG_P(REGNO) \
1723 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1724 #define COP3_REG_P(REGNO) \
1725 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1726 #define ALL_COP_REG_P(REGNO) \
1727 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1728 /* Test if REGNO is one of the 6 new DSP accumulators. */
1729 #define DSP_ACC_REG_P(REGNO) \
1730 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1731 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1732 #define ACC_REG_P(REGNO) \
1733 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1734
1735 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1736
1737 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1738 to initialize the mips16 gp pseudo register. */
1739 #define CONST_GP_P(X) \
1740 (GET_CODE (X) == CONST \
1741 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1742 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1743
1744 /* Return coprocessor number from register number. */
1745
1746 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1747 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1748 : COP3_REG_P (REGNO) ? '3' : '?')
1749
1750
1751 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1752
1753 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1754 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1755
1756 #define MODES_TIEABLE_P mips_modes_tieable_p
1757
1758 /* Register to use for pushing function arguments. */
1759 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1760
1761 /* These two registers don't really exist: they get eliminated to either
1762 the stack or hard frame pointer. */
1763 #define ARG_POINTER_REGNUM 77
1764 #define FRAME_POINTER_REGNUM 78
1765
1766 /* $30 is not available on the mips16, so we use $17 as the frame
1767 pointer. */
1768 #define HARD_FRAME_POINTER_REGNUM \
1769 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1770
1771 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1772 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1773
1774 /* Register in which static-chain is passed to a function. */
1775 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1776
1777 /* Registers used as temporaries in prologue/epilogue code:
1778
1779 - If a MIPS16 PIC function needs access to _gp, it first loads
1780 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1781
1782 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1783 register. The register must not conflict with MIPS16_PIC_TEMP.
1784
1785 - If we aren't generating MIPS16 code, the prologue can also use
1786 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1787
1788 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1789 register.
1790
1791 If we're generating MIPS16 code, these registers must come from the
1792 core set of 8. The prologue registers mustn't conflict with any
1793 incoming arguments, the static chain pointer, or the frame pointer.
1794 The epilogue temporary mustn't conflict with the return registers,
1795 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1796 or the EH data registers.
1797
1798 If we're generating interrupt handlers, we use K0 as a temporary register
1799 in prologue/epilogue code. */
1800
1801 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1802 #define MIPS_PROLOGUE_TEMP_REGNUM \
1803 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1804 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1805 (TARGET_MIPS16 \
1806 ? (gcc_unreachable (), INVALID_REGNUM) \
1807 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1808 #define MIPS_EPILOGUE_TEMP_REGNUM \
1809 (cfun->machine->interrupt_handler_p \
1810 ? K0_REG_NUM \
1811 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1812
1813 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1814 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1815 #define MIPS_PROLOGUE_TEMP2(MODE) \
1816 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1817 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1818
1819 /* Define this macro if it is as good or better to call a constant
1820 function address than to call an address kept in a register. */
1821 #define NO_FUNCTION_CSE 1
1822
1823 /* The ABI-defined global pointer. Sometimes we use a different
1824 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1825 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1826
1827 /* We normally use $28 as the global pointer. However, when generating
1828 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1829 register instead. They can then avoid saving and restoring $28
1830 and perhaps avoid using a frame at all.
1831
1832 When a leaf function uses something other than $28, mips_expand_prologue
1833 will modify pic_offset_table_rtx in place. Take the register number
1834 from there after reload. */
1835 #define PIC_OFFSET_TABLE_REGNUM \
1836 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1837 \f
1838 /* Define the classes of registers for register constraints in the
1839 machine description. Also define ranges of constants.
1840
1841 One of the classes must always be named ALL_REGS and include all hard regs.
1842 If there is more than one class, another class must be named NO_REGS
1843 and contain no registers.
1844
1845 The name GENERAL_REGS must be the name of a class (or an alias for
1846 another name such as ALL_REGS). This is the class of registers
1847 that is allowed by "g" or "r" in a register constraint.
1848 Also, registers outside this class are allocated only when
1849 instructions express preferences for them.
1850
1851 The classes must be numbered in nondecreasing order; that is,
1852 a larger-numbered class must never be contained completely
1853 in a smaller-numbered class.
1854
1855 For any two classes, it is very desirable that there be another
1856 class that represents their union. */
1857
1858 enum reg_class
1859 {
1860 NO_REGS, /* no registers in set */
1861 M16_REGS, /* mips16 directly accessible registers */
1862 T_REG, /* mips16 T register ($24) */
1863 M16_T_REGS, /* mips16 registers plus T register */
1864 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1865 V1_REG, /* Register $v1 ($3) used for TLS access. */
1866 LEA_REGS, /* Every GPR except $25 */
1867 GR_REGS, /* integer registers */
1868 FP_REGS, /* floating point registers */
1869 MD0_REG, /* first multiply/divide register */
1870 MD1_REG, /* second multiply/divide register */
1871 MD_REGS, /* multiply/divide registers (hi/lo) */
1872 COP0_REGS, /* generic coprocessor classes */
1873 COP2_REGS,
1874 COP3_REGS,
1875 ST_REGS, /* status registers (fp status) */
1876 DSP_ACC_REGS, /* DSP accumulator registers */
1877 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1878 FRAME_REGS, /* $arg and $frame */
1879 GR_AND_MD0_REGS, /* union classes */
1880 GR_AND_MD1_REGS,
1881 GR_AND_MD_REGS,
1882 GR_AND_ACC_REGS,
1883 ALL_REGS, /* all registers */
1884 LIM_REG_CLASSES /* max value + 1 */
1885 };
1886
1887 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1888
1889 #define GENERAL_REGS GR_REGS
1890
1891 /* An initializer containing the names of the register classes as C
1892 string constants. These names are used in writing some of the
1893 debugging dumps. */
1894
1895 #define REG_CLASS_NAMES \
1896 { \
1897 "NO_REGS", \
1898 "M16_REGS", \
1899 "T_REG", \
1900 "M16_T_REGS", \
1901 "PIC_FN_ADDR_REG", \
1902 "V1_REG", \
1903 "LEA_REGS", \
1904 "GR_REGS", \
1905 "FP_REGS", \
1906 "MD0_REG", \
1907 "MD1_REG", \
1908 "MD_REGS", \
1909 /* coprocessor registers */ \
1910 "COP0_REGS", \
1911 "COP2_REGS", \
1912 "COP3_REGS", \
1913 "ST_REGS", \
1914 "DSP_ACC_REGS", \
1915 "ACC_REGS", \
1916 "FRAME_REGS", \
1917 "GR_AND_MD0_REGS", \
1918 "GR_AND_MD1_REGS", \
1919 "GR_AND_MD_REGS", \
1920 "GR_AND_ACC_REGS", \
1921 "ALL_REGS" \
1922 }
1923
1924 /* An initializer containing the contents of the register classes,
1925 as integers which are bit masks. The Nth integer specifies the
1926 contents of class N. The way the integer MASK is interpreted is
1927 that register R is in the class if `MASK & (1 << R)' is 1.
1928
1929 When the machine has more than 32 registers, an integer does not
1930 suffice. Then the integers are replaced by sub-initializers,
1931 braced groupings containing several integers. Each
1932 sub-initializer must be suitable as an initializer for the type
1933 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1934
1935 #define REG_CLASS_CONTENTS \
1936 { \
1937 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1938 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1939 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1940 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1941 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1942 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1943 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1944 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1945 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1946 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1947 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1948 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1949 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1950 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1951 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1952 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1953 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1954 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1955 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1956 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1957 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1958 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1959 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1960 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1961 }
1962
1963
1964 /* A C expression whose value is a register class containing hard
1965 register REGNO. In general there is more that one such class;
1966 choose a class which is "minimal", meaning that no smaller class
1967 also contains the register. */
1968
1969 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1970
1971 /* A macro whose definition is the name of the class to which a
1972 valid base register must belong. A base register is one used in
1973 an address which is the register value plus a displacement. */
1974
1975 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1976
1977 /* A macro whose definition is the name of the class to which a
1978 valid index register must belong. An index register is one used
1979 in an address where its value is either multiplied by a scale
1980 factor or added to another register (as well as added to a
1981 displacement). */
1982
1983 #define INDEX_REG_CLASS NO_REGS
1984
1985 /* We generally want to put call-clobbered registers ahead of
1986 call-saved ones. (IRA expects this.) */
1987
1988 #define REG_ALLOC_ORDER \
1989 { /* Accumulator registers. When GPRs and accumulators have equal \
1990 cost, we generally prefer to use accumulators. For example, \
1991 a division of multiplication result is better allocated to LO, \
1992 so that we put the MFLO at the point of use instead of at the \
1993 point of definition. It's also needed if we're to take advantage \
1994 of the extra accumulators available with -mdspr2. In some cases, \
1995 it can also help to reduce register pressure. */ \
1996 64, 65,176,177,178,179,180,181, \
1997 /* Call-clobbered GPRs. */ \
1998 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1999 24, 25, 31, \
2000 /* The global pointer. This is call-clobbered for o32 and o64 \
2001 abicalls, call-saved for n32 and n64 abicalls, and a program \
2002 invariant otherwise. Putting it between the call-clobbered \
2003 and call-saved registers should cope with all eventualities. */ \
2004 28, \
2005 /* Call-saved GPRs. */ \
2006 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2007 /* GPRs that can never be exposed to the register allocator. */ \
2008 0, 26, 27, 29, \
2009 /* Call-clobbered FPRs. */ \
2010 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2011 48, 49, 50, 51, \
2012 /* FPRs that are usually call-saved. The odd ones are actually \
2013 call-clobbered for n32, but listing them ahead of the even \
2014 registers might encourage the register allocator to fragment \
2015 the available FPR pairs. We need paired FPRs to store long \
2016 doubles, so it isn't clear that using a different order \
2017 for n32 would be a win. */ \
2018 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2019 /* None of the remaining classes have defined call-saved \
2020 registers. */ \
2021 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2022 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2023 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2024 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2025 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2026 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2027 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2028 182,183,184,185,186,187 \
2029 }
2030
2031 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
2032 to be rearranged based on a particular function. On the mips16, we
2033 want to allocate $24 (T_REG) before other registers for
2034 instructions for which it is possible. */
2035
2036 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2037
2038 /* True if VALUE is an unsigned 6-bit number. */
2039
2040 #define UIMM6_OPERAND(VALUE) \
2041 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2042
2043 /* True if VALUE is a signed 10-bit number. */
2044
2045 #define IMM10_OPERAND(VALUE) \
2046 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2047
2048 /* True if VALUE is a signed 16-bit number. */
2049
2050 #define SMALL_OPERAND(VALUE) \
2051 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2052
2053 /* True if VALUE is an unsigned 16-bit number. */
2054
2055 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2056 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2057
2058 /* True if VALUE can be loaded into a register using LUI. */
2059
2060 #define LUI_OPERAND(VALUE) \
2061 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2062 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2063
2064 /* Return a value X with the low 16 bits clear, and such that
2065 VALUE - X is a signed 16-bit value. */
2066
2067 #define CONST_HIGH_PART(VALUE) \
2068 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2069
2070 #define CONST_LOW_PART(VALUE) \
2071 ((VALUE) - CONST_HIGH_PART (VALUE))
2072
2073 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2074 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2075 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2076 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2077
2078 /* The HI and LO registers can only be reloaded via the general
2079 registers. Condition code registers can only be loaded to the
2080 general registers, and from the floating point registers. */
2081
2082 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2083 mips_secondary_reload_class (CLASS, MODE, X, true)
2084 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2085 mips_secondary_reload_class (CLASS, MODE, X, false)
2086
2087 /* Return the maximum number of consecutive registers
2088 needed to represent mode MODE in a register of class CLASS. */
2089
2090 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2091
2092 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2093 mips_cannot_change_mode_class (FROM, TO, CLASS)
2094 \f
2095 /* Stack layout; function entry, exit and calling. */
2096
2097 #define STACK_GROWS_DOWNWARD
2098
2099 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2100
2101 /* Size of the area allocated in the frame to save the GP. */
2102
2103 #define MIPS_GP_SAVE_AREA_SIZE \
2104 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2105
2106 /* The offset of the first local variable from the frame pointer. See
2107 mips_compute_frame_info for details about the frame layout. */
2108
2109 #define STARTING_FRAME_OFFSET \
2110 (FRAME_GROWS_DOWNWARD \
2111 ? 0 \
2112 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2113
2114 #define RETURN_ADDR_RTX mips_return_addr
2115
2116 /* Mask off the MIPS16 ISA bit in unwind addresses.
2117
2118 The reason for this is a little subtle. When unwinding a call,
2119 we are given the call's return address, which on most targets
2120 is the address of the following instruction. However, what we
2121 actually want to find is the EH region for the call itself.
2122 The target-independent unwind code therefore searches for "RA - 1".
2123
2124 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2125 RA - 1 is therefore the real (even-valued) start of the return
2126 instruction. EH region labels are usually odd-valued MIPS16 symbols
2127 too, so a search for an even address within a MIPS16 region would
2128 usually work.
2129
2130 However, there is an exception. If the end of an EH region is also
2131 the end of a function, the end label is allowed to be even. This is
2132 necessary because a following non-MIPS16 function may also need EH
2133 information for its first instruction.
2134
2135 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2136 non-ISA-encoded address. This probably isn't ideal, but it is
2137 the traditional (legacy) behavior. It is therefore only safe
2138 to search MIPS EH regions for an _odd-valued_ address.
2139
2140 Masking off the ISA bit means that the target-independent code
2141 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2142 #define MASK_RETURN_ADDR GEN_INT (-2)
2143
2144
2145 /* Similarly, don't use the least-significant bit to tell pointers to
2146 code from vtable index. */
2147
2148 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2149
2150 /* The eliminations to $17 are only used for mips16 code. See the
2151 definition of HARD_FRAME_POINTER_REGNUM. */
2152
2153 #define ELIMINABLE_REGS \
2154 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2155 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2156 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2157 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2158 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2159 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2160
2161 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2162 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2163
2164 /* Allocate stack space for arguments at the beginning of each function. */
2165 #define ACCUMULATE_OUTGOING_ARGS 1
2166
2167 /* The argument pointer always points to the first argument. */
2168 #define FIRST_PARM_OFFSET(FNDECL) 0
2169
2170 /* o32 and o64 reserve stack space for all argument registers. */
2171 #define REG_PARM_STACK_SPACE(FNDECL) \
2172 (TARGET_OLDABI \
2173 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2174 : 0)
2175
2176 /* Define this if it is the responsibility of the caller to
2177 allocate the area reserved for arguments passed in registers.
2178 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2179 of this macro is to determine whether the space is included in
2180 `crtl->outgoing_args_size'. */
2181 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2182
2183 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2184 \f
2185 /* Symbolic macros for the registers used to return integer and floating
2186 point values. */
2187
2188 #define GP_RETURN (GP_REG_FIRST + 2)
2189 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2190
2191 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2192
2193 /* Symbolic macros for the first/last argument registers. */
2194
2195 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2196 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2197 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2198 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2199
2200 /* 1 if N is a possible register number for function argument passing.
2201 We have no FP argument registers when soft-float. When FP registers
2202 are 32 bits, we can't directly reference the odd numbered ones. */
2203
2204 #define FUNCTION_ARG_REGNO_P(N) \
2205 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2206 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2207 && !fixed_regs[N])
2208 \f
2209 /* This structure has to cope with two different argument allocation
2210 schemes. Most MIPS ABIs view the arguments as a structure, of which
2211 the first N words go in registers and the rest go on the stack. If I
2212 < N, the Ith word might go in Ith integer argument register or in a
2213 floating-point register. For these ABIs, we only need to remember
2214 the offset of the current argument into the structure.
2215
2216 The EABI instead allocates the integer and floating-point arguments
2217 separately. The first N words of FP arguments go in FP registers,
2218 the rest go on the stack. Likewise, the first N words of the other
2219 arguments go in integer registers, and the rest go on the stack. We
2220 need to maintain three counts: the number of integer registers used,
2221 the number of floating-point registers used, and the number of words
2222 passed on the stack.
2223
2224 We could keep separate information for the two ABIs (a word count for
2225 the standard ABIs, and three separate counts for the EABI). But it
2226 seems simpler to view the standard ABIs as forms of EABI that do not
2227 allocate floating-point registers.
2228
2229 So for the standard ABIs, the first N words are allocated to integer
2230 registers, and mips_function_arg decides on an argument-by-argument
2231 basis whether that argument should really go in an integer register,
2232 or in a floating-point one. */
2233
2234 typedef struct mips_args {
2235 /* Always true for varargs functions. Otherwise true if at least
2236 one argument has been passed in an integer register. */
2237 int gp_reg_found;
2238
2239 /* The number of arguments seen so far. */
2240 unsigned int arg_number;
2241
2242 /* The number of integer registers used so far. For all ABIs except
2243 EABI, this is the number of words that have been added to the
2244 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2245 unsigned int num_gprs;
2246
2247 /* For EABI, the number of floating-point registers used so far. */
2248 unsigned int num_fprs;
2249
2250 /* The number of words passed on the stack. */
2251 unsigned int stack_words;
2252
2253 /* On the mips16, we need to keep track of which floating point
2254 arguments were passed in general registers, but would have been
2255 passed in the FP regs if this were a 32-bit function, so that we
2256 can move them to the FP regs if we wind up calling a 32-bit
2257 function. We record this information in fp_code, encoded in base
2258 four. A zero digit means no floating point argument, a one digit
2259 means an SFmode argument, and a two digit means a DFmode argument,
2260 and a three digit is not used. The low order digit is the first
2261 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2262 an SFmode argument. ??? A more sophisticated approach will be
2263 needed if MIPS_ABI != ABI_32. */
2264 int fp_code;
2265
2266 /* True if the function has a prototype. */
2267 int prototype;
2268 } CUMULATIVE_ARGS;
2269
2270 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2271 for a call to a function whose data type is FNTYPE.
2272 For a library call, FNTYPE is 0. */
2273
2274 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2275 mips_init_cumulative_args (&CUM, FNTYPE)
2276
2277 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2278 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2279
2280 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2281 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2282
2283 /* True if using EABI and varargs can be passed in floating-point
2284 registers. Under these conditions, we need a more complex form
2285 of va_list, which tracks GPR, FPR and stack arguments separately. */
2286 #define EABI_FLOAT_VARARGS_P \
2287 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2288
2289 \f
2290 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2291
2292 /* Treat LOC as a byte offset from the stack pointer and round it up
2293 to the next fully-aligned offset. */
2294 #define MIPS_STACK_ALIGN(LOC) \
2295 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2296
2297 \f
2298 /* Output assembler code to FILE to increment profiler label # LABELNO
2299 for profiling a function entry. */
2300
2301 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2302
2303 /* The profiler preserves all interesting registers, including $31. */
2304 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2305
2306 /* No mips port has ever used the profiler counter word, so don't emit it
2307 or the label for it. */
2308
2309 #define NO_PROFILE_COUNTERS 1
2310
2311 /* Define this macro if the code for function profiling should come
2312 before the function prologue. Normally, the profiling code comes
2313 after. */
2314
2315 /* #define PROFILE_BEFORE_PROLOGUE */
2316
2317 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2318 the stack pointer does not matter. The value is tested only in
2319 functions that have frame pointers.
2320 No definition is equivalent to always zero. */
2321
2322 #define EXIT_IGNORE_STACK 1
2323
2324 \f
2325 /* Trampolines are a block of code followed by two pointers. */
2326
2327 #define TRAMPOLINE_SIZE \
2328 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2329
2330 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2331 pointers from a single LUI base. */
2332
2333 #define TRAMPOLINE_ALIGNMENT 64
2334
2335 /* mips_trampoline_init calls this library function to flush
2336 program and data caches. */
2337
2338 #ifndef CACHE_FLUSH_FUNC
2339 #define CACHE_FLUSH_FUNC "_flush_cache"
2340 #endif
2341
2342 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2343 /* Flush both caches. We need to flush the data cache in case \
2344 the system has a write-back cache. */ \
2345 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2346 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2347 GEN_INT (3), TYPE_MODE (integer_type_node))
2348
2349 \f
2350 /* Addressing modes, and classification of registers for them. */
2351
2352 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2353 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2354 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2355 \f
2356 /* Maximum number of registers that can appear in a valid memory address. */
2357
2358 #define MAX_REGS_PER_ADDRESS 1
2359
2360 /* Check for constness inline but use mips_legitimate_address_p
2361 to check whether a constant really is an address. */
2362
2363 #define CONSTANT_ADDRESS_P(X) \
2364 (CONSTANT_P (X) && memory_address_p (SImode, X))
2365
2366 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2367 'the start of the function that this code is output in'. */
2368
2369 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2370 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2371 asm_fprintf ((FILE), "%U%s", \
2372 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2373 else \
2374 asm_fprintf ((FILE), "%U%s", (NAME))
2375 \f
2376 /* Flag to mark a function decl symbol that requires a long call. */
2377 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2378 #define SYMBOL_REF_LONG_CALL_P(X) \
2379 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2380
2381 /* This flag marks functions that cannot be lazily bound. */
2382 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2383 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2384 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2385
2386 /* True if we're generating a form of MIPS16 code in which jump tables
2387 are stored in the text section and encoded as 16-bit PC-relative
2388 offsets. This is only possible when general text loads are allowed,
2389 since the table access itself will be an "lh" instruction. If the
2390 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2391 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2392
2393 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2394
2395 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2396
2397 /* Only use short offsets if their range will not overflow. */
2398 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2399 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2400 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2401 : SImode)
2402
2403 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2404
2405 /* Define this as 1 if `char' should by default be signed; else as 0. */
2406 #ifndef DEFAULT_SIGNED_CHAR
2407 #define DEFAULT_SIGNED_CHAR 1
2408 #endif
2409
2410 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2411 we generally don't want to use them for copying arbitrary data.
2412 A single N-word move is usually the same cost as N single-word moves. */
2413 #define MOVE_MAX UNITS_PER_WORD
2414 #define MAX_MOVE_MAX 8
2415
2416 /* Define this macro as a C expression which is nonzero if
2417 accessing less than a word of memory (i.e. a `char' or a
2418 `short') is no faster than accessing a word of memory, i.e., if
2419 such access require more than one instruction or if there is no
2420 difference in cost between byte and (aligned) word loads.
2421
2422 On RISC machines, it tends to generate better code to define
2423 this as 1, since it avoids making a QI or HI mode register.
2424
2425 But, generating word accesses for -mips16 is generally bad as shifts
2426 (often extended) would be needed for byte accesses. */
2427 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2428
2429 /* Standard MIPS integer shifts truncate the shift amount to the
2430 width of the shifted operand. However, Loongson vector shifts
2431 do not truncate the shift amount at all. */
2432 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2433
2434 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2435 is done just by pretending it is already truncated. */
2436 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2437 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2438
2439
2440 /* Specify the machine mode that pointers have.
2441 After generation of rtl, the compiler makes no further distinction
2442 between pointers and any other objects of this machine mode. */
2443
2444 #ifndef Pmode
2445 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2446 #endif
2447
2448 /* Give call MEMs SImode since it is the "most permissive" mode
2449 for both 32-bit and 64-bit targets. */
2450
2451 #define FUNCTION_MODE SImode
2452
2453 \f
2454 /* We allocate $fcc registers by hand and can't cope with moves of
2455 CCmode registers to and from pseudos (or memory). */
2456 #define AVOID_CCMODE_COPIES
2457
2458 /* A C expression for the cost of a branch instruction. A value of
2459 1 is the default; other values are interpreted relative to that. */
2460
2461 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2462 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2463
2464 /* The MIPS port has several functions that return an instruction count.
2465 Multiplying the count by this value gives the number of bytes that
2466 the instructions occupy. */
2467 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2468
2469 /* The length of a NOP in bytes. */
2470 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2471
2472 /* If defined, modifies the length assigned to instruction INSN as a
2473 function of the context in which it is used. LENGTH is an lvalue
2474 that contains the initially computed length of the insn and should
2475 be updated with the correct length of the insn. */
2476 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2477 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2478
2479 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2480 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2481 its operands. */
2482 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2483 "%*" OPCODE "%?\t" OPERANDS "%/"
2484
2485 /* Return an asm string that forces INSN to be treated as an absolute
2486 J or JAL instruction instead of an assembler macro. */
2487 #define MIPS_ABSOLUTE_JUMP(INSN) \
2488 (TARGET_ABICALLS_PIC2 \
2489 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2490 : INSN)
2491
2492 /* Return the asm template for a call. INSN is the instruction's mnemonic
2493 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2494 number of the target. SIZE_OPNO is the operand number of the argument size
2495 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2496 -1 and the call is indirect, use the function symbol from the call
2497 attributes to attach a R_MIPS_JALR relocation to the call.
2498
2499 When generating GOT code without explicit relocation operators,
2500 all calls should use assembly macros. Otherwise, all indirect
2501 calls should use "jr" or "jalr"; we will arrange to restore $gp
2502 afterwards if necessary. Finally, we can only generate direct
2503 calls for -mabicalls by temporarily switching to non-PIC mode.
2504
2505 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2506 instruction is in the delay slot of jal(r). */
2507 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2508 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2509 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2510 : REG_P (OPERANDS[TARGET_OPNO]) \
2511 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2512 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2513 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2514 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2515 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2516 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2517 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2518
2519 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2520 "jrc" when nop is in the delay slot of "jr". */
2521
2522 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2523 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2524 ? "%*j\t%" #OPNO "%/" \
2525 : REG_P (OPERANDS[OPNO]) \
2526 ? "%*jr%:\t%" #OPNO \
2527 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2528
2529 \f
2530 /* Control the assembler format that we output. */
2531
2532 /* Output to assembler file text saying following lines
2533 may contain character constants, extra white space, comments, etc. */
2534
2535 #ifndef ASM_APP_ON
2536 #define ASM_APP_ON " #APP\n"
2537 #endif
2538
2539 /* Output to assembler file text saying following lines
2540 no longer contain unusual constructs. */
2541
2542 #ifndef ASM_APP_OFF
2543 #define ASM_APP_OFF " #NO_APP\n"
2544 #endif
2545
2546 #define REGISTER_NAMES \
2547 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2548 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2549 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2550 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2551 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2552 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2553 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2554 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2555 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2556 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2557 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2558 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2559 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2560 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2561 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2562 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2563 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2564 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2565 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2566 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2567 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2568 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2569 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2570 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2571
2572 /* List the "software" names for each register. Also list the numerical
2573 names for $fp and $sp. */
2574
2575 #define ADDITIONAL_REGISTER_NAMES \
2576 { \
2577 { "$29", 29 + GP_REG_FIRST }, \
2578 { "$30", 30 + GP_REG_FIRST }, \
2579 { "at", 1 + GP_REG_FIRST }, \
2580 { "v0", 2 + GP_REG_FIRST }, \
2581 { "v1", 3 + GP_REG_FIRST }, \
2582 { "a0", 4 + GP_REG_FIRST }, \
2583 { "a1", 5 + GP_REG_FIRST }, \
2584 { "a2", 6 + GP_REG_FIRST }, \
2585 { "a3", 7 + GP_REG_FIRST }, \
2586 { "t0", 8 + GP_REG_FIRST }, \
2587 { "t1", 9 + GP_REG_FIRST }, \
2588 { "t2", 10 + GP_REG_FIRST }, \
2589 { "t3", 11 + GP_REG_FIRST }, \
2590 { "t4", 12 + GP_REG_FIRST }, \
2591 { "t5", 13 + GP_REG_FIRST }, \
2592 { "t6", 14 + GP_REG_FIRST }, \
2593 { "t7", 15 + GP_REG_FIRST }, \
2594 { "s0", 16 + GP_REG_FIRST }, \
2595 { "s1", 17 + GP_REG_FIRST }, \
2596 { "s2", 18 + GP_REG_FIRST }, \
2597 { "s3", 19 + GP_REG_FIRST }, \
2598 { "s4", 20 + GP_REG_FIRST }, \
2599 { "s5", 21 + GP_REG_FIRST }, \
2600 { "s6", 22 + GP_REG_FIRST }, \
2601 { "s7", 23 + GP_REG_FIRST }, \
2602 { "t8", 24 + GP_REG_FIRST }, \
2603 { "t9", 25 + GP_REG_FIRST }, \
2604 { "k0", 26 + GP_REG_FIRST }, \
2605 { "k1", 27 + GP_REG_FIRST }, \
2606 { "gp", 28 + GP_REG_FIRST }, \
2607 { "sp", 29 + GP_REG_FIRST }, \
2608 { "fp", 30 + GP_REG_FIRST }, \
2609 { "ra", 31 + GP_REG_FIRST } \
2610 }
2611
2612 #define DBR_OUTPUT_SEQEND(STREAM) \
2613 do \
2614 { \
2615 /* Undo the effect of '%*'. */ \
2616 mips_pop_asm_switch (&mips_nomacro); \
2617 mips_pop_asm_switch (&mips_noreorder); \
2618 /* Emit a blank line after the delay slot for emphasis. */ \
2619 fputs ("\n", STREAM); \
2620 } \
2621 while (0)
2622
2623 /* The MIPS implementation uses some labels for its own purpose. The
2624 following lists what labels are created, and are all formed by the
2625 pattern $L[a-z].*. The machine independent portion of GCC creates
2626 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2627
2628 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2629 $Lb[0-9]+ Begin blocks for MIPS debug support
2630 $Lc[0-9]+ Label for use in s<xx> operation.
2631 $Le[0-9]+ End blocks for MIPS debug support */
2632
2633 #undef ASM_DECLARE_OBJECT_NAME
2634 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2635 mips_declare_object (STREAM, NAME, "", ":\n")
2636
2637 /* Globalizing directive for a label. */
2638 #define GLOBAL_ASM_OP "\t.globl\t"
2639
2640 /* This says how to define a global common symbol. */
2641
2642 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2643
2644 /* This says how to define a local common symbol (i.e., not visible to
2645 linker). */
2646
2647 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2648 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2649 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2650 #endif
2651
2652 /* This says how to output an external. It would be possible not to
2653 output anything and let undefined symbol become external. However
2654 the assembler uses length information on externals to allocate in
2655 data/sdata bss/sbss, thereby saving exec time. */
2656
2657 #undef ASM_OUTPUT_EXTERNAL
2658 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2659 mips_output_external(STREAM,DECL,NAME)
2660
2661 /* This is how to declare a function name. The actual work of
2662 emitting the label is moved to function_prologue, so that we can
2663 get the line number correctly emitted before the .ent directive,
2664 and after any .file directives. Define as empty so that the function
2665 is not declared before the .ent directive elsewhere. */
2666
2667 #undef ASM_DECLARE_FUNCTION_NAME
2668 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2669
2670 /* This is how to store into the string LABEL
2671 the symbol_ref name of an internal numbered label where
2672 PREFIX is the class of label and NUM is the number within the class.
2673 This is suitable for output with `assemble_name'. */
2674
2675 #undef ASM_GENERATE_INTERNAL_LABEL
2676 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2677 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2678
2679 /* Print debug labels as "foo = ." rather than "foo:" because they should
2680 represent a byte pointer rather than an ISA-encoded address. This is
2681 particularly important for code like:
2682
2683 $LFBxxx = .
2684 .cfi_startproc
2685 ...
2686 .section .gcc_except_table,...
2687 ...
2688 .uleb128 foo-$LFBxxx
2689
2690 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2691 likewise a byte pointer rather than an ISA-encoded address.
2692
2693 At the time of writing, this hook is not used for the function end
2694 label:
2695
2696 $LFExxx:
2697 .end foo
2698
2699 But this doesn't matter, because GAS doesn't treat a pre-.end label
2700 as a MIPS16 one anyway. */
2701
2702 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2703 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2704
2705 /* This is how to output an element of a case-vector that is absolute. */
2706
2707 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2708 fprintf (STREAM, "\t%s\t%sL%d\n", \
2709 ptr_mode == DImode ? ".dword" : ".word", \
2710 LOCAL_LABEL_PREFIX, \
2711 VALUE)
2712
2713 /* This is how to output an element of a case-vector. We can make the
2714 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2715 is supported. */
2716
2717 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2718 do { \
2719 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2720 { \
2721 if (GET_MODE (BODY) == HImode) \
2722 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2723 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2724 else \
2725 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2726 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2727 } \
2728 else if (TARGET_GPWORD) \
2729 fprintf (STREAM, "\t%s\t%sL%d\n", \
2730 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2731 LOCAL_LABEL_PREFIX, VALUE); \
2732 else if (TARGET_RTP_PIC) \
2733 { \
2734 /* Make the entry relative to the start of the function. */ \
2735 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2736 fprintf (STREAM, "\t%s\t%sL%d-", \
2737 Pmode == DImode ? ".dword" : ".word", \
2738 LOCAL_LABEL_PREFIX, VALUE); \
2739 assemble_name (STREAM, XSTR (fnsym, 0)); \
2740 fprintf (STREAM, "\n"); \
2741 } \
2742 else \
2743 fprintf (STREAM, "\t%s\t%sL%d\n", \
2744 ptr_mode == DImode ? ".dword" : ".word", \
2745 LOCAL_LABEL_PREFIX, VALUE); \
2746 } while (0)
2747
2748 /* This is how to output an assembler line
2749 that says to advance the location counter
2750 to a multiple of 2**LOG bytes. */
2751
2752 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2753 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2754
2755 /* This is how to output an assembler line to advance the location
2756 counter by SIZE bytes. */
2757
2758 #undef ASM_OUTPUT_SKIP
2759 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2760 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2761
2762 /* This is how to output a string. */
2763 #undef ASM_OUTPUT_ASCII
2764 #define ASM_OUTPUT_ASCII mips_output_ascii
2765
2766 \f
2767 /* Default to -G 8 */
2768 #ifndef MIPS_DEFAULT_GVALUE
2769 #define MIPS_DEFAULT_GVALUE 8
2770 #endif
2771
2772 /* Define the strings to put out for each section in the object file. */
2773 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2774 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2775
2776 #undef READONLY_DATA_SECTION_ASM_OP
2777 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2778 \f
2779 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2780 do \
2781 { \
2782 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2783 TARGET_64BIT ? "daddiu" : "addiu", \
2784 reg_names[STACK_POINTER_REGNUM], \
2785 reg_names[STACK_POINTER_REGNUM], \
2786 TARGET_64BIT ? "sd" : "sw", \
2787 reg_names[REGNO], \
2788 reg_names[STACK_POINTER_REGNUM]); \
2789 } \
2790 while (0)
2791
2792 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2793 do \
2794 { \
2795 mips_push_asm_switch (&mips_noreorder); \
2796 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2797 TARGET_64BIT ? "ld" : "lw", \
2798 reg_names[REGNO], \
2799 reg_names[STACK_POINTER_REGNUM], \
2800 TARGET_64BIT ? "daddu" : "addu", \
2801 reg_names[STACK_POINTER_REGNUM], \
2802 reg_names[STACK_POINTER_REGNUM]); \
2803 mips_pop_asm_switch (&mips_noreorder); \
2804 } \
2805 while (0)
2806
2807 /* How to start an assembler comment.
2808 The leading space is important (the mips native assembler requires it). */
2809 #ifndef ASM_COMMENT_START
2810 #define ASM_COMMENT_START " #"
2811 #endif
2812 \f
2813 #undef SIZE_TYPE
2814 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2815
2816 #undef PTRDIFF_TYPE
2817 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2818
2819 /* The maximum number of bytes that can be copied by one iteration of
2820 a movmemsi loop; see mips_block_move_loop. */
2821 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2822 (UNITS_PER_WORD * 4)
2823
2824 /* The maximum number of bytes that can be copied by a straight-line
2825 implementation of movmemsi; see mips_block_move_straight. We want
2826 to make sure that any loop-based implementation will iterate at
2827 least twice. */
2828 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2829 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2830
2831 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2832 values were determined experimentally by benchmarking with CSiBE.
2833 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2834 for o32 where we have to restore $gp afterwards as well as make an
2835 indirect call), but in practice, bumping this up higher for
2836 TARGET_ABICALLS doesn't make much difference to code size. */
2837
2838 #define MIPS_CALL_RATIO 8
2839
2840 /* Any loop-based implementation of movmemsi will have at least
2841 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2842 moves, so allow individual copies of fewer elements.
2843
2844 When movmemsi is not available, use a value approximating
2845 the length of a memcpy call sequence, so that move_by_pieces
2846 will generate inline code if it is shorter than a function call.
2847 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2848 we'll have to generate a load/store pair for each, halve the
2849 value of MIPS_CALL_RATIO to take that into account. */
2850
2851 #define MOVE_RATIO(speed) \
2852 (HAVE_movmemsi \
2853 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2854 : MIPS_CALL_RATIO / 2)
2855
2856 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2857 mips_move_by_pieces_p (SIZE, ALIGN)
2858
2859 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2860 of the length of a memset call, but use the default otherwise. */
2861
2862 #define CLEAR_RATIO(speed)\
2863 ((speed) ? 15 : MIPS_CALL_RATIO)
2864
2865 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2866 optimizing for size adjust the ratio to account for the overhead of
2867 loading the constant and replicating it across the word. */
2868
2869 #define SET_RATIO(speed) \
2870 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2871
2872 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2873 mips_store_by_pieces_p (SIZE, ALIGN)
2874 \f
2875 /* Since the bits of the _init and _fini function is spread across
2876 many object files, each potentially with its own GP, we must assume
2877 we need to load our GP. We don't preserve $gp or $ra, since each
2878 init/fini chunk is supposed to initialize $gp, and crti/crtn
2879 already take care of preserving $ra and, when appropriate, $gp. */
2880 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2881 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2882 asm (SECTION_OP "\n\
2883 .set push\n\
2884 .set nomips16\n\
2885 .set noreorder\n\
2886 bal 1f\n\
2887 nop\n\
2888 1: .cpload $31\n\
2889 .set reorder\n\
2890 jal " USER_LABEL_PREFIX #FUNC "\n\
2891 .set pop\n\
2892 " TEXT_SECTION_ASM_OP);
2893 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2894 || (defined _ABI64 && _MIPS_SIM == _ABI64))
2895 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2896 asm (SECTION_OP "\n\
2897 .set push\n\
2898 .set nomips16\n\
2899 .set noreorder\n\
2900 bal 1f\n\
2901 nop\n\
2902 1: .set reorder\n\
2903 .cpsetup $31, $2, 1b\n\
2904 jal " USER_LABEL_PREFIX #FUNC "\n\
2905 .set pop\n\
2906 " TEXT_SECTION_ASM_OP);
2907 #endif
2908
2909 #ifndef HAVE_AS_TLS
2910 #define HAVE_AS_TLS 0
2911 #endif
2912
2913 #ifndef HAVE_AS_NAN
2914 #define HAVE_AS_NAN 0
2915 #endif
2916
2917 #ifndef USED_FOR_TARGET
2918 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2919 struct mips_asm_switch {
2920 /* The FOO in the description above. */
2921 const char *name;
2922
2923 /* The current block nesting level, or 0 if we aren't in a block. */
2924 int nesting_level;
2925 };
2926
2927 extern const enum reg_class mips_regno_to_class[];
2928 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2929 extern const char *current_function_file; /* filename current function is in */
2930 extern int num_source_filenames; /* current .file # */
2931 extern struct mips_asm_switch mips_noreorder;
2932 extern struct mips_asm_switch mips_nomacro;
2933 extern struct mips_asm_switch mips_noat;
2934 extern int mips_dbx_regno[];
2935 extern int mips_dwarf_regno[];
2936 extern bool mips_split_p[];
2937 extern bool mips_split_hi_p[];
2938 extern bool mips_use_pcrel_pool_p[];
2939 extern const char *mips_lo_relocs[];
2940 extern const char *mips_hi_relocs[];
2941 extern enum processor mips_arch; /* which cpu to codegen for */
2942 extern enum processor mips_tune; /* which cpu to schedule for */
2943 extern int mips_isa; /* architectural level */
2944 extern const struct mips_cpu_info *mips_arch_info;
2945 extern const struct mips_cpu_info *mips_tune_info;
2946 extern unsigned int mips_base_compression_flags;
2947 extern GTY(()) struct target_globals *mips16_globals;
2948 #endif
2949
2950 /* Enable querying of DFA units. */
2951 #define CPU_UNITS_QUERY 1
2952
2953 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2954 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2955
2956 /* As on most targets, we want the .eh_frame section to be read-only where
2957 possible. And as on most targets, this means two things:
2958
2959 (a) Non-locally-binding pointers must have an indirect encoding,
2960 so that the addresses in the .eh_frame section itself become
2961 locally-binding.
2962
2963 (b) A shared library's .eh_frame section must encode locally-binding
2964 pointers in a relative (relocation-free) form.
2965
2966 However, MIPS has traditionally not allowed directives like:
2967
2968 .long x-.
2969
2970 in cases where "x" is in a different section, or is not defined in the
2971 same assembly file. We are therefore unable to emit the PC-relative
2972 form required by (b) at assembly time.
2973
2974 Fortunately, the linker is able to convert absolute addresses into
2975 PC-relative addresses on our behalf. Unfortunately, only certain
2976 versions of the linker know how to do this for indirect pointers,
2977 and for personality data. We must fall back on using writable
2978 .eh_frame sections for shared libraries if the linker does not
2979 support this feature. */
2980 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2981 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2982
2983 /* For switching between MIPS16 and non-MIPS16 modes. */
2984 #define SWITCHABLE_TARGET 1
2985
2986 /* Several named MIPS patterns depend on Pmode. These patterns have the
2987 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2988 Add the appropriate suffix to generator function NAME and invoke it
2989 with arguments ARGS. */
2990 #define PMODE_INSN(NAME, ARGS) \
2991 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)