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gcc/
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS64 (mips_isa == 64)
212 #define ISA_MIPS64R2 (mips_isa == 65)
213
214 /* Architecture target defines. */
215 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
216 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
217 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
218 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
219 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
220 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
221 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
222 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
223 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
224 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
225 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
226 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
227 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
228 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
229 || mips_arch == PROCESSOR_OCTEON2)
230 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
231 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
232 || mips_arch == PROCESSOR_SB1A)
233 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
234 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
235
236 /* Scheduling target defines. */
237 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
238 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
239 || mips_tune == PROCESSOR_24KF2_1 \
240 || mips_tune == PROCESSOR_24KF1_1)
241 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
242 || mips_tune == PROCESSOR_74KF2_1 \
243 || mips_tune == PROCESSOR_74KF1_1 \
244 || mips_tune == PROCESSOR_74KF3_2)
245 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
246 || mips_tune == PROCESSOR_LOONGSON_2F)
247 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
248 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
249 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
250 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
251 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
252 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
253 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
254 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
255 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
256 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
257 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
258 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
259 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
260 || mips_tune == PROCESSOR_OCTEON2)
261 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
262 || mips_tune == PROCESSOR_SB1A)
263
264 /* Whether vector modes and intrinsics for ST Microelectronics
265 Loongson-2E/2F processors should be enabled. In o32 pairs of
266 floating-point registers provide 64-bit values. */
267 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
268 && (TARGET_LOONGSON_2EF \
269 || TARGET_LOONGSON_3A))
270
271 /* True if the pre-reload scheduler should try to create chains of
272 multiply-add or multiply-subtract instructions. For example,
273 suppose we have:
274
275 t1 = a * b
276 t2 = t1 + c * d
277 t3 = e * f
278 t4 = t3 - g * h
279
280 t1 will have a higher priority than t2 and t3 will have a higher
281 priority than t4. However, before reload, there is no dependence
282 between t1 and t3, and they can often have similar priorities.
283 The scheduler will then tend to prefer:
284
285 t1 = a * b
286 t3 = e * f
287 t2 = t1 + c * d
288 t4 = t3 - g * h
289
290 which stops us from making full use of macc/madd-style instructions.
291 This sort of situation occurs frequently in Fourier transforms and
292 in unrolled loops.
293
294 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
295 queue so that chained multiply-add and multiply-subtract instructions
296 appear ahead of any other instruction that is likely to clobber lo.
297 In the example above, if t2 and t3 become ready at the same time,
298 the code ensures that t2 is scheduled first.
299
300 Multiply-accumulate instructions are a bigger win for some targets
301 than others, so this macro is defined on an opt-in basis. */
302 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
303 || TUNE_MIPS4120 \
304 || TUNE_MIPS4130 \
305 || TUNE_24K)
306
307 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
308 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
309
310 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
311 directly accessible, while the command-line options select
312 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
313 in use. */
314 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
315 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
316
317 /* False if SC acts as a memory barrier with respect to itself,
318 otherwise a SYNC will be emitted after SC for atomic operations
319 that require ordering between the SC and following loads and
320 stores. It does not tell anything about ordering of loads and
321 stores prior to and following the SC, only about the SC itself and
322 those loads and stores follow it. */
323 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
324
325 /* Define preprocessor macros for the -march and -mtune options.
326 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
327 processor. If INFO's canonical name is "foo", define PREFIX to
328 be "foo", and define an additional macro PREFIX_FOO. */
329 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
330 do \
331 { \
332 char *macro, *p; \
333 \
334 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
335 for (p = macro; *p != 0; p++) \
336 if (*p == '+') \
337 *p = 'P'; \
338 else \
339 *p = TOUPPER (*p); \
340 \
341 builtin_define (macro); \
342 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
343 free (macro); \
344 } \
345 while (0)
346
347 /* Target CPU builtins. */
348 #define TARGET_CPU_CPP_BUILTINS() \
349 do \
350 { \
351 builtin_assert ("machine=mips"); \
352 builtin_assert ("cpu=mips"); \
353 builtin_define ("__mips__"); \
354 builtin_define ("_mips"); \
355 \
356 /* We do this here because __mips is defined below and so we \
357 can't use builtin_define_std. We don't ever want to define \
358 "mips" for VxWorks because some of the VxWorks headers \
359 construct include filenames from a root directory macro, \
360 an architecture macro and a filename, where the architecture \
361 macro expands to 'mips'. If we define 'mips' to 1, the \
362 architecture macro expands to 1 as well. */ \
363 if (!flag_iso && !TARGET_VXWORKS) \
364 builtin_define ("mips"); \
365 \
366 if (TARGET_64BIT) \
367 builtin_define ("__mips64"); \
368 \
369 /* Treat _R3000 and _R4000 like register-size \
370 defines, which is how they've historically \
371 been used. */ \
372 if (TARGET_64BIT) \
373 { \
374 builtin_define_std ("R4000"); \
375 builtin_define ("_R4000"); \
376 } \
377 else \
378 { \
379 builtin_define_std ("R3000"); \
380 builtin_define ("_R3000"); \
381 } \
382 \
383 if (TARGET_FLOAT64) \
384 builtin_define ("__mips_fpr=64"); \
385 else \
386 builtin_define ("__mips_fpr=32"); \
387 \
388 if (mips_base_compression_flags & MASK_MIPS16) \
389 builtin_define ("__mips16"); \
390 \
391 if (TARGET_MIPS3D) \
392 builtin_define ("__mips3d"); \
393 \
394 if (TARGET_SMARTMIPS) \
395 builtin_define ("__mips_smartmips"); \
396 \
397 if (mips_base_compression_flags & MASK_MICROMIPS) \
398 builtin_define ("__mips_micromips"); \
399 \
400 if (TARGET_MCU) \
401 builtin_define ("__mips_mcu"); \
402 \
403 if (TARGET_EVA) \
404 builtin_define ("__mips_eva"); \
405 \
406 if (TARGET_DSP) \
407 { \
408 builtin_define ("__mips_dsp"); \
409 if (TARGET_DSPR2) \
410 { \
411 builtin_define ("__mips_dspr2"); \
412 builtin_define ("__mips_dsp_rev=2"); \
413 } \
414 else \
415 builtin_define ("__mips_dsp_rev=1"); \
416 } \
417 \
418 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
419 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
420 \
421 if (ISA_MIPS1) \
422 { \
423 builtin_define ("__mips=1"); \
424 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
425 } \
426 else if (ISA_MIPS2) \
427 { \
428 builtin_define ("__mips=2"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
430 } \
431 else if (ISA_MIPS3) \
432 { \
433 builtin_define ("__mips=3"); \
434 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
435 } \
436 else if (ISA_MIPS4) \
437 { \
438 builtin_define ("__mips=4"); \
439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
440 } \
441 else if (ISA_MIPS32) \
442 { \
443 builtin_define ("__mips=32"); \
444 builtin_define ("__mips_isa_rev=1"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
446 } \
447 else if (ISA_MIPS32R2) \
448 { \
449 builtin_define ("__mips=32"); \
450 builtin_define ("__mips_isa_rev=2"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
452 } \
453 else if (ISA_MIPS64) \
454 { \
455 builtin_define ("__mips=64"); \
456 builtin_define ("__mips_isa_rev=1"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
458 } \
459 else if (ISA_MIPS64R2) \
460 { \
461 builtin_define ("__mips=64"); \
462 builtin_define ("__mips_isa_rev=2"); \
463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
464 } \
465 \
466 switch (mips_abi) \
467 { \
468 case ABI_32: \
469 builtin_define ("_ABIO32=1"); \
470 builtin_define ("_MIPS_SIM=_ABIO32"); \
471 break; \
472 \
473 case ABI_N32: \
474 builtin_define ("_ABIN32=2"); \
475 builtin_define ("_MIPS_SIM=_ABIN32"); \
476 break; \
477 \
478 case ABI_64: \
479 builtin_define ("_ABI64=3"); \
480 builtin_define ("_MIPS_SIM=_ABI64"); \
481 break; \
482 \
483 case ABI_O64: \
484 builtin_define ("_ABIO64=4"); \
485 builtin_define ("_MIPS_SIM=_ABIO64"); \
486 break; \
487 } \
488 \
489 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
490 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
491 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
492 builtin_define_with_int_value ("_MIPS_FPSET", \
493 32 / MAX_FPRS_PER_FMT); \
494 \
495 /* These defines reflect the ABI in use, not whether the \
496 FPU is directly accessible. */ \
497 if (TARGET_NO_FLOAT) \
498 builtin_define ("__mips_no_float"); \
499 else if (TARGET_HARD_FLOAT_ABI) \
500 builtin_define ("__mips_hard_float"); \
501 else \
502 builtin_define ("__mips_soft_float"); \
503 \
504 if (TARGET_SINGLE_FLOAT) \
505 builtin_define ("__mips_single_float"); \
506 \
507 if (TARGET_PAIRED_SINGLE_FLOAT) \
508 builtin_define ("__mips_paired_single_float"); \
509 \
510 if (TARGET_BIG_ENDIAN) \
511 { \
512 builtin_define_std ("MIPSEB"); \
513 builtin_define ("_MIPSEB"); \
514 } \
515 else \
516 { \
517 builtin_define_std ("MIPSEL"); \
518 builtin_define ("_MIPSEL"); \
519 } \
520 \
521 /* Whether calls should go through $25. The separate __PIC__ \
522 macro indicates whether abicalls code might use a GOT. */ \
523 if (TARGET_ABICALLS) \
524 builtin_define ("__mips_abicalls"); \
525 \
526 /* Whether Loongson vector modes are enabled. */ \
527 if (TARGET_LOONGSON_VECTORS) \
528 builtin_define ("__mips_loongson_vector_rev"); \
529 \
530 /* Historical Octeon macro. */ \
531 if (TARGET_OCTEON) \
532 builtin_define ("__OCTEON__"); \
533 \
534 if (TARGET_SYNCI) \
535 builtin_define ("__mips_synci"); \
536 \
537 /* Macros dependent on the C dialect. */ \
538 if (preprocessing_asm_p ()) \
539 { \
540 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
541 builtin_define ("_LANGUAGE_ASSEMBLY"); \
542 } \
543 else if (c_dialect_cxx ()) \
544 { \
545 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
546 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
547 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
548 } \
549 else \
550 { \
551 builtin_define_std ("LANGUAGE_C"); \
552 builtin_define ("_LANGUAGE_C"); \
553 } \
554 if (c_dialect_objc ()) \
555 { \
556 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
557 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
558 /* Bizarre, but retained for backwards compatibility. */ \
559 builtin_define_std ("LANGUAGE_C"); \
560 builtin_define ("_LANGUAGE_C"); \
561 } \
562 \
563 if (mips_abi == ABI_EABI) \
564 builtin_define ("__mips_eabi"); \
565 \
566 if (TARGET_CACHE_BUILTIN) \
567 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
568 } \
569 while (0)
570
571 /* Default target_flags if no switches are specified */
572
573 #ifndef TARGET_DEFAULT
574 #define TARGET_DEFAULT 0
575 #endif
576
577 #ifndef TARGET_CPU_DEFAULT
578 #define TARGET_CPU_DEFAULT 0
579 #endif
580
581 #ifndef TARGET_ENDIAN_DEFAULT
582 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
583 #endif
584
585 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
586 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
587 #endif
588
589 #ifdef IN_LIBGCC2
590 #undef TARGET_64BIT
591 /* Make this compile time constant for libgcc2 */
592 #ifdef __mips64
593 #define TARGET_64BIT 1
594 #else
595 #define TARGET_64BIT 0
596 #endif
597 #endif /* IN_LIBGCC2 */
598
599 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
600 when compiled with hardware floating point. This is because MIPS16
601 code cannot save and restore the floating-point registers, which is
602 important if in a mixed MIPS16/non-MIPS16 environment. */
603
604 #ifdef IN_LIBGCC2
605 #if __mips_hard_float
606 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
607 #endif
608 #endif /* IN_LIBGCC2 */
609
610 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
611
612 #ifndef MULTILIB_ENDIAN_DEFAULT
613 #if TARGET_ENDIAN_DEFAULT == 0
614 #define MULTILIB_ENDIAN_DEFAULT "EL"
615 #else
616 #define MULTILIB_ENDIAN_DEFAULT "EB"
617 #endif
618 #endif
619
620 #ifndef MULTILIB_ISA_DEFAULT
621 #if MIPS_ISA_DEFAULT == 1
622 #define MULTILIB_ISA_DEFAULT "mips1"
623 #elif MIPS_ISA_DEFAULT == 2
624 #define MULTILIB_ISA_DEFAULT "mips2"
625 #elif MIPS_ISA_DEFAULT == 3
626 #define MULTILIB_ISA_DEFAULT "mips3"
627 #elif MIPS_ISA_DEFAULT == 4
628 #define MULTILIB_ISA_DEFAULT "mips4"
629 #elif MIPS_ISA_DEFAULT == 32
630 #define MULTILIB_ISA_DEFAULT "mips32"
631 #elif MIPS_ISA_DEFAULT == 33
632 #define MULTILIB_ISA_DEFAULT "mips32r2"
633 #elif MIPS_ISA_DEFAULT == 64
634 #define MULTILIB_ISA_DEFAULT "mips64"
635 #elif MIPS_ISA_DEFAULT == 65
636 #define MULTILIB_ISA_DEFAULT "mips64r2"
637 #else
638 #define MULTILIB_ISA_DEFAULT "mips1"
639 #endif
640 #endif
641
642 #ifndef MIPS_ABI_DEFAULT
643 #define MIPS_ABI_DEFAULT ABI_32
644 #endif
645
646 /* Use the most portable ABI flag for the ASM specs. */
647
648 #if MIPS_ABI_DEFAULT == ABI_32
649 #define MULTILIB_ABI_DEFAULT "mabi=32"
650 #elif MIPS_ABI_DEFAULT == ABI_O64
651 #define MULTILIB_ABI_DEFAULT "mabi=o64"
652 #elif MIPS_ABI_DEFAULT == ABI_N32
653 #define MULTILIB_ABI_DEFAULT "mabi=n32"
654 #elif MIPS_ABI_DEFAULT == ABI_64
655 #define MULTILIB_ABI_DEFAULT "mabi=64"
656 #elif MIPS_ABI_DEFAULT == ABI_EABI
657 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
658 #endif
659
660 #ifndef MULTILIB_DEFAULTS
661 #define MULTILIB_DEFAULTS \
662 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
663 #endif
664
665 /* We must pass -EL to the linker by default for little endian embedded
666 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
667 linker will default to using big-endian output files. The OUTPUT_FORMAT
668 line must be in the linker script, otherwise -EB/-EL will not work. */
669
670 #ifndef ENDIAN_SPEC
671 #if TARGET_ENDIAN_DEFAULT == 0
672 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
673 #else
674 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
675 #endif
676 #endif
677
678 /* A spec condition that matches all non-mips16 -mips arguments. */
679
680 #define MIPS_ISA_LEVEL_OPTION_SPEC \
681 "mips1|mips2|mips3|mips4|mips32*|mips64*"
682
683 /* A spec condition that matches all non-mips16 architecture arguments. */
684
685 #define MIPS_ARCH_OPTION_SPEC \
686 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
687
688 /* A spec that infers a -mips argument from an -march argument,
689 or injects the default if no architecture is specified. */
690
691 #define MIPS_ISA_LEVEL_SPEC \
692 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
693 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
694 %{march=mips2|march=r6000:-mips2} \
695 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
696 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
697 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
698 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
699 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
700 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
701 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
702 |march=xlr|march=loongson3a: -mips64} \
703 %{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
704 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
705
706 /* A spec that infers a -mhard-float or -msoft-float setting from an
707 -march argument. Note that soft-float and hard-float code are not
708 link-compatible. */
709
710 #define MIPS_ARCH_FLOAT_SPEC \
711 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
712 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
713 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
714 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
715 march=*: -mhard-float}"
716
717 /* A spec condition that matches 32-bit options. It only works if
718 MIPS_ISA_LEVEL_SPEC has been applied. */
719
720 #define MIPS_32BIT_OPTION_SPEC \
721 "mips1|mips2|mips32*|mgp32"
722
723 /* Infer a -msynci setting from a -mips argument, on the assumption that
724 -msynci is desired where possible. */
725 #define MIPS_ISA_SYNCI_SPEC \
726 "%{msynci|mno-synci:;:%{mips32r2|mips64r2:-msynci;:-mno-synci}}"
727
728 #if (MIPS_ABI_DEFAULT == ABI_O64 \
729 || MIPS_ABI_DEFAULT == ABI_N32 \
730 || MIPS_ABI_DEFAULT == ABI_64)
731 #define OPT_ARCH64 "mabi=32|mgp32:;"
732 #define OPT_ARCH32 "mabi=32|mgp32"
733 #else
734 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
735 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
736 #endif
737
738 /* Support for a compile-time default CPU, et cetera. The rules are:
739 --with-arch is ignored if -march is specified or a -mips is specified
740 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
741 --with-tune is ignored if -mtune is specified; likewise
742 --with-tune-32 and --with-tune-64.
743 --with-abi is ignored if -mabi is specified.
744 --with-float is ignored if -mhard-float or -msoft-float are
745 specified.
746 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
747 specified. */
748 #define OPTION_DEFAULT_SPECS \
749 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
750 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
751 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
752 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
753 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
754 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
755 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
756 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
757 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
758 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
759 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
760 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
761
762 /* A spec that infers the -mdsp setting from an -march argument. */
763 #define BASE_DRIVER_SELF_SPECS \
764 "%{!mno-dsp: \
765 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
766 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
767
768 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
769
770 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
771 && ISA_HAS_COND_TRAP)
772
773 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
774
775 /* True if the ABI can only work with 64-bit integer registers. We
776 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
777 otherwise floating-point registers must also be 64-bit. */
778 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
779
780 /* Likewise for 32-bit regs. */
781 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
782
783 /* True if the file format uses 64-bit symbols. At present, this is
784 only true for n64, which uses 64-bit ELF. */
785 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
786
787 /* True if symbols are 64 bits wide. This is usually determined by
788 the ABI's file format, but it can be overridden by -msym32. Note that
789 overriding the size with -msym32 changes the ABI of relocatable objects,
790 although it doesn't change the ABI of a fully-linked object. */
791 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
792 && Pmode == DImode \
793 && !TARGET_SYM32)
794
795 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
796 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
797 || ISA_MIPS4 \
798 || ISA_MIPS64 \
799 || ISA_MIPS64R2)
800
801 /* ISA has branch likely instructions (e.g. mips2). */
802 /* Disable branchlikely for tx39 until compare rewrite. They haven't
803 been generated up to this point. */
804 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
805
806 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
807 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
808 || TARGET_MIPS5400 \
809 || TARGET_MIPS5500 \
810 || TARGET_MIPS7000 \
811 || TARGET_MIPS9000 \
812 || TARGET_MAD \
813 || ISA_MIPS32 \
814 || ISA_MIPS32R2 \
815 || ISA_MIPS64 \
816 || ISA_MIPS64R2) \
817 && !TARGET_MIPS16)
818
819 /* ISA has a three-operand multiplication instruction. */
820 #define ISA_HAS_DMUL3 (TARGET_64BIT \
821 && TARGET_OCTEON \
822 && !TARGET_MIPS16)
823
824 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
825 || TARGET_LOONGSON_3A) \
826 && !TARGET_MIPS16)
827
828 /* ISA has the floating-point conditional move instructions introduced
829 in mips4. */
830 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
831 || ISA_MIPS32 \
832 || ISA_MIPS32R2 \
833 || ISA_MIPS64 \
834 || ISA_MIPS64R2) \
835 && !TARGET_MIPS5500 \
836 && !TARGET_MIPS16)
837
838 /* ISA has the integer conditional move instructions introduced in mips4 and
839 ST Loongson 2E/2F. */
840 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
841 || TARGET_MIPS5900 \
842 || TARGET_LOONGSON_2EF)
843
844 /* ISA has LDC1 and SDC1. */
845 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
846
847 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
848 branch on CC, and move (both FP and non-FP) on CC. */
849 #define ISA_HAS_8CC (ISA_MIPS4 \
850 || ISA_MIPS32 \
851 || ISA_MIPS32R2 \
852 || ISA_MIPS64 \
853 || ISA_MIPS64R2)
854
855 /* This is a catch all for other mips4 instructions: indexed load, the
856 FP madd and msub instructions, and the FP recip and recip sqrt
857 instructions. */
858 #define ISA_HAS_FP4 ((ISA_MIPS4 \
859 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
860 || ISA_MIPS64 \
861 || ISA_MIPS64R2) \
862 && !TARGET_MIPS16)
863
864 /* ISA has paired-single instructions. */
865 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
866
867 /* ISA has conditional trap instructions. */
868 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
869 && !TARGET_MIPS16)
870
871 /* ISA has integer multiply-accumulate instructions, madd and msub. */
872 #define ISA_HAS_MADD_MSUB (ISA_MIPS32 \
873 || ISA_MIPS32R2 \
874 || ISA_MIPS64 \
875 || ISA_MIPS64R2)
876
877 /* Integer multiply-accumulate instructions should be generated. */
878 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
879
880 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
881 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
882
883 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
884 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
885
886 /* ISA has floating-point nmadd and nmsub instructions
887 'd = -((a * b) [+-] c)'. */
888 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
889 ((ISA_MIPS4 \
890 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
891 || ISA_MIPS64 \
892 || ISA_MIPS64R2) \
893 && (!TARGET_MIPS5400 || TARGET_MAD) \
894 && !TARGET_MIPS16)
895
896 /* ISA has floating-point nmadd and nmsub instructions
897 'c = -((a * b) [+-] c)'. */
898 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
899 TARGET_LOONGSON_2EF
900
901 /* ISA has count leading zeroes/ones instruction (not implemented). */
902 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
903 || ISA_MIPS32R2 \
904 || ISA_MIPS64 \
905 || ISA_MIPS64R2) \
906 && !TARGET_MIPS16)
907
908 /* ISA has three operand multiply instructions that put
909 the high part in an accumulator: mulhi or mulhiu. */
910 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
911 || TARGET_MIPS5500 \
912 || TARGET_SR71K) \
913 && !TARGET_MIPS16)
914
915 /* ISA has three operand multiply instructions that
916 negates the result and puts the result in an accumulator. */
917 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
918 || TARGET_MIPS5500 \
919 || TARGET_SR71K) \
920 && !TARGET_MIPS16)
921
922 /* ISA has three operand multiply instructions that subtracts the
923 result from a 4th operand and puts the result in an accumulator. */
924 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
925 || TARGET_MIPS5500 \
926 || TARGET_SR71K) \
927 && !TARGET_MIPS16)
928
929 /* ISA has three operand multiply instructions that the result
930 from a 4th operand and puts the result in an accumulator. */
931 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
932 || TARGET_MIPS4130 \
933 || TARGET_MIPS5400 \
934 || TARGET_MIPS5500 \
935 || TARGET_SR71K) \
936 && !TARGET_MIPS16)
937
938 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
939 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
940 || TARGET_MIPS4130) \
941 && !TARGET_MIPS16)
942
943 /* ISA has the "ror" (rotate right) instructions. */
944 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
945 || ISA_MIPS64R2 \
946 || TARGET_MIPS5400 \
947 || TARGET_MIPS5500 \
948 || TARGET_SR71K \
949 || TARGET_SMARTMIPS) \
950 && !TARGET_MIPS16)
951
952 /* ISA has data prefetch instructions. This controls use of 'pref'. */
953 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
954 || TARGET_LOONGSON_2EF \
955 || TARGET_MIPS5900 \
956 || ISA_MIPS32 \
957 || ISA_MIPS32R2 \
958 || ISA_MIPS64 \
959 || ISA_MIPS64R2) \
960 && !TARGET_MIPS16)
961
962 /* ISA has data indexed prefetch instructions. This controls use of
963 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
964 (prefx is a cop1x instruction, so can only be used if FP is
965 enabled.) */
966 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
967 || ISA_MIPS32R2 \
968 || ISA_MIPS64 \
969 || ISA_MIPS64R2) \
970 && !TARGET_MIPS16)
971
972 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
973 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
974 also requires TARGET_DOUBLE_FLOAT. */
975 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
976
977 /* ISA includes the MIPS32r2 seb and seh instructions. */
978 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
979 || ISA_MIPS64R2) \
980 && !TARGET_MIPS16)
981
982 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
983 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
984 || ISA_MIPS64R2) \
985 && !TARGET_MIPS16)
986
987 /* ISA has instructions for accessing top part of 64-bit fp regs. */
988 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
989 && (ISA_MIPS32R2 \
990 || ISA_MIPS64R2))
991
992 /* ISA has lwxs instruction (load w/scaled index address. */
993 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
994 && !TARGET_MIPS16)
995
996 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
997 #define ISA_HAS_LBX (TARGET_OCTEON2)
998 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
999 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1000 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1001 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1002 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1003 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1004 && TARGET_64BIT)
1005
1006 /* The DSP ASE is available. */
1007 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1008
1009 /* Revision 2 of the DSP ASE is available. */
1010 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1011
1012 /* True if the result of a load is not available to the next instruction.
1013 A nop will then be needed between instructions like "lw $4,..."
1014 and "addiu $4,$4,1". */
1015 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1016 && !TARGET_MIPS3900 \
1017 && !TARGET_MIPS5900 \
1018 && !TARGET_MIPS16 \
1019 && !TARGET_MICROMIPS)
1020
1021 /* Likewise mtc1 and mfc1. */
1022 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1023 && !TARGET_MIPS5900 \
1024 && !TARGET_LOONGSON_2EF)
1025
1026 /* Likewise floating-point comparisons. */
1027 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1028 && !TARGET_MIPS5900 \
1029 && !TARGET_LOONGSON_2EF)
1030
1031 /* True if mflo and mfhi can be immediately followed by instructions
1032 which write to the HI and LO registers.
1033
1034 According to MIPS specifications, MIPS ISAs I, II, and III need
1035 (at least) two instructions between the reads of HI/LO and
1036 instructions which write them, and later ISAs do not. Contradicting
1037 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1038 the UM for the NEC Vr5000) document needing the instructions between
1039 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1040 MIPS64 and later ISAs to have the interlocks, plus any specific
1041 earlier-ISA CPUs for which CPU documentation declares that the
1042 instructions are really interlocked. */
1043 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1044 || ISA_MIPS32R2 \
1045 || ISA_MIPS64 \
1046 || ISA_MIPS64R2 \
1047 || TARGET_MIPS5500 \
1048 || TARGET_MIPS5900 \
1049 || TARGET_LOONGSON_2EF)
1050
1051 /* ISA includes synci, jr.hb and jalr.hb. */
1052 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1053 || ISA_MIPS64R2) \
1054 && !TARGET_MIPS16)
1055
1056 /* ISA includes sync. */
1057 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1058 #define GENERATE_SYNC \
1059 (target_flags_explicit & MASK_LLSC \
1060 ? TARGET_LLSC && !TARGET_MIPS16 \
1061 : ISA_HAS_SYNC)
1062
1063 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1064 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1065 instructions. */
1066 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1067 #define GENERATE_LL_SC \
1068 (target_flags_explicit & MASK_LLSC \
1069 ? TARGET_LLSC && !TARGET_MIPS16 \
1070 : ISA_HAS_LL_SC)
1071
1072 #define ISA_HAS_SWAP (TARGET_XLP)
1073 #define ISA_HAS_LDADD (TARGET_XLP)
1074
1075 /* ISA includes the baddu instruction. */
1076 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1077
1078 /* ISA includes the bbit* instructions. */
1079 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1080
1081 /* ISA includes the cins instruction. */
1082 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1083
1084 /* ISA includes the exts instruction. */
1085 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1086
1087 /* ISA includes the seq and sne instructions. */
1088 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1089
1090 /* ISA includes the pop instruction. */
1091 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1092
1093 /* The CACHE instruction is available in non-MIPS16 code. */
1094 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1095
1096 /* The CACHE instruction is available. */
1097 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1098 \f
1099 /* Tell collect what flags to pass to nm. */
1100 #ifndef NM_FLAGS
1101 #define NM_FLAGS "-Bn"
1102 #endif
1103
1104 \f
1105 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1106 the assembler. It may be overridden by subtargets.
1107
1108 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1109 COFF debugging info. */
1110
1111 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1112 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1113 %{g} %{g0} %{g1} %{g2} %{g3} \
1114 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1115 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1116 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1117 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1118 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1119 #endif
1120
1121 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1122 overridden by subtargets. */
1123
1124 #ifndef SUBTARGET_ASM_SPEC
1125 #define SUBTARGET_ASM_SPEC ""
1126 #endif
1127
1128 #undef ASM_SPEC
1129 #define ASM_SPEC "\
1130 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1131 %{mips32*} %{mips64*} \
1132 %{mips16} %{mno-mips16:-no-mips16} \
1133 %{mmicromips} %{mno-micromips} \
1134 %{mips3d} %{mno-mips3d:-no-mips3d} \
1135 %{mdmx} %{mno-mdmx:-no-mdmx} \
1136 %{mdsp} %{mno-dsp} \
1137 %{mdspr2} %{mno-dspr2} \
1138 %{mmcu} %{mno-mcu} \
1139 %{meva} %{mno-eva} \
1140 %{msmartmips} %{mno-smartmips} \
1141 %{mmt} %{mno-mt} \
1142 %{mfix-vr4120} %{mfix-vr4130} \
1143 %{mfix-24k} \
1144 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1145 %(subtarget_asm_debugging_spec) \
1146 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1147 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1148 %{mfp32} %{mfp64} \
1149 %{mshared} %{mno-shared} \
1150 %{msym32} %{mno-sym32} \
1151 %{mtune=*} \
1152 %(subtarget_asm_spec)"
1153
1154 /* Extra switches sometimes passed to the linker. */
1155
1156 #ifndef LINK_SPEC
1157 #define LINK_SPEC "\
1158 %(endian_spec) \
1159 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1160 %{shared}"
1161 #endif /* LINK_SPEC defined */
1162
1163
1164 /* Specs for the compiler proper */
1165
1166 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1167 overridden by subtargets. */
1168 #ifndef SUBTARGET_CC1_SPEC
1169 #define SUBTARGET_CC1_SPEC ""
1170 #endif
1171
1172 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1173
1174 #undef CC1_SPEC
1175 #define CC1_SPEC "\
1176 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1177 %(subtarget_cc1_spec)"
1178
1179 /* Preprocessor specs. */
1180
1181 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1182 overridden by subtargets. */
1183 #ifndef SUBTARGET_CPP_SPEC
1184 #define SUBTARGET_CPP_SPEC ""
1185 #endif
1186
1187 #define CPP_SPEC "%(subtarget_cpp_spec)"
1188
1189 /* This macro defines names of additional specifications to put in the specs
1190 that can be used in various specifications like CC1_SPEC. Its definition
1191 is an initializer with a subgrouping for each command option.
1192
1193 Each subgrouping contains a string constant, that defines the
1194 specification name, and a string constant that used by the GCC driver
1195 program.
1196
1197 Do not define this macro if it does not need to do anything. */
1198
1199 #define EXTRA_SPECS \
1200 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1201 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1202 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1203 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1204 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1205 { "endian_spec", ENDIAN_SPEC }, \
1206 SUBTARGET_EXTRA_SPECS
1207
1208 #ifndef SUBTARGET_EXTRA_SPECS
1209 #define SUBTARGET_EXTRA_SPECS
1210 #endif
1211 \f
1212 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1213 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1214
1215 #ifndef PREFERRED_DEBUGGING_TYPE
1216 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1217 #endif
1218
1219 /* The size of DWARF addresses should be the same as the size of symbols
1220 in the target file format. They shouldn't depend on things like -msym32,
1221 because many DWARF consumers do not allow the mixture of address sizes
1222 that one would then get from linking -msym32 code with -msym64 code.
1223
1224 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1225 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1226 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1227
1228 /* By default, turn on GDB extensions. */
1229 #define DEFAULT_GDB_EXTENSIONS 1
1230
1231 /* Local compiler-generated symbols must have a prefix that the assembler
1232 understands. By default, this is $, although some targets (e.g.,
1233 NetBSD-ELF) need to override this. */
1234
1235 #ifndef LOCAL_LABEL_PREFIX
1236 #define LOCAL_LABEL_PREFIX "$"
1237 #endif
1238
1239 /* By default on the mips, external symbols do not have an underscore
1240 prepended, but some targets (e.g., NetBSD) require this. */
1241
1242 #ifndef USER_LABEL_PREFIX
1243 #define USER_LABEL_PREFIX ""
1244 #endif
1245
1246 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1247 since the length can run past this up to a continuation point. */
1248 #undef DBX_CONTIN_LENGTH
1249 #define DBX_CONTIN_LENGTH 1500
1250
1251 /* How to renumber registers for dbx and gdb. */
1252 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1253
1254 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1255 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1256
1257 /* The DWARF 2 CFA column which tracks the return address. */
1258 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1259
1260 /* Before the prologue, RA lives in r31. */
1261 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1262
1263 /* Describe how we implement __builtin_eh_return. */
1264 #define EH_RETURN_DATA_REGNO(N) \
1265 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1266
1267 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1268
1269 #define EH_USES(N) mips_eh_uses (N)
1270
1271 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1272 The default for this in 64-bit mode is 8, which causes problems with
1273 SFmode register saves. */
1274 #define DWARF_CIE_DATA_ALIGNMENT -4
1275
1276 /* Correct the offset of automatic variables and arguments. Note that
1277 the MIPS debug format wants all automatic variables and arguments
1278 to be in terms of the virtual frame pointer (stack pointer before
1279 any adjustment in the function), while the MIPS 3.0 linker wants
1280 the frame pointer to be the stack pointer after the initial
1281 adjustment. */
1282
1283 #define DEBUGGER_AUTO_OFFSET(X) \
1284 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1285 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1286 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1287 \f
1288 /* Target machine storage layout */
1289
1290 #define BITS_BIG_ENDIAN 0
1291 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1292 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1293
1294 #define MAX_BITS_PER_WORD 64
1295
1296 /* Width of a word, in units (bytes). */
1297 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1298 #ifndef IN_LIBGCC2
1299 #define MIN_UNITS_PER_WORD 4
1300 #endif
1301
1302 /* For MIPS, width of a floating point register. */
1303 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1304
1305 /* The number of consecutive floating-point registers needed to store the
1306 largest format supported by the FPU. */
1307 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1308
1309 /* The number of consecutive floating-point registers needed to store the
1310 smallest format supported by the FPU. */
1311 #define MIN_FPRS_PER_FMT \
1312 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1313 ? 1 : MAX_FPRS_PER_FMT)
1314
1315 /* The largest size of value that can be held in floating-point
1316 registers and moved with a single instruction. */
1317 #define UNITS_PER_HWFPVALUE \
1318 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1319
1320 /* The largest size of value that can be held in floating-point
1321 registers. */
1322 #define UNITS_PER_FPVALUE \
1323 (TARGET_SOFT_FLOAT_ABI ? 0 \
1324 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1325 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1326
1327 /* The number of bytes in a double. */
1328 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1329
1330 /* Set the sizes of the core types. */
1331 #define SHORT_TYPE_SIZE 16
1332 #define INT_TYPE_SIZE 32
1333 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1334 #define LONG_LONG_TYPE_SIZE 64
1335
1336 #define FLOAT_TYPE_SIZE 32
1337 #define DOUBLE_TYPE_SIZE 64
1338 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1339
1340 /* Define the sizes of fixed-point types. */
1341 #define SHORT_FRACT_TYPE_SIZE 8
1342 #define FRACT_TYPE_SIZE 16
1343 #define LONG_FRACT_TYPE_SIZE 32
1344 #define LONG_LONG_FRACT_TYPE_SIZE 64
1345
1346 #define SHORT_ACCUM_TYPE_SIZE 16
1347 #define ACCUM_TYPE_SIZE 32
1348 #define LONG_ACCUM_TYPE_SIZE 64
1349 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1350 doesn't support 128-bit integers for MIPS32 currently. */
1351 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1352
1353 /* long double is not a fixed mode, but the idea is that, if we
1354 support long double, we also want a 128-bit integer type. */
1355 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1356
1357 #ifdef IN_LIBGCC2
1358 #if ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1359 || (defined _ABI64 && _MIPS_SIM == _ABI64))
1360 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1361 # else
1362 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1363 # endif
1364 #endif
1365
1366 /* Width in bits of a pointer. */
1367 #ifndef POINTER_SIZE
1368 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1369 #endif
1370
1371 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1372 #define PARM_BOUNDARY BITS_PER_WORD
1373
1374 /* Allocation boundary (in *bits*) for the code of a function. */
1375 #define FUNCTION_BOUNDARY 32
1376
1377 /* Alignment of field after `int : 0' in a structure. */
1378 #define EMPTY_FIELD_BOUNDARY 32
1379
1380 /* Every structure's size must be a multiple of this. */
1381 /* 8 is observed right on a DECstation and on riscos 4.02. */
1382 #define STRUCTURE_SIZE_BOUNDARY 8
1383
1384 /* There is no point aligning anything to a rounder boundary than this. */
1385 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1386
1387 /* All accesses must be aligned. */
1388 #define STRICT_ALIGNMENT 1
1389
1390 /* Define this if you wish to imitate the way many other C compilers
1391 handle alignment of bitfields and the structures that contain
1392 them.
1393
1394 The behavior is that the type written for a bit-field (`int',
1395 `short', or other integer type) imposes an alignment for the
1396 entire structure, as if the structure really did contain an
1397 ordinary field of that type. In addition, the bit-field is placed
1398 within the structure so that it would fit within such a field,
1399 not crossing a boundary for it.
1400
1401 Thus, on most machines, a bit-field whose type is written as `int'
1402 would not cross a four-byte boundary, and would force four-byte
1403 alignment for the whole structure. (The alignment used may not
1404 be four bytes; it is controlled by the other alignment
1405 parameters.)
1406
1407 If the macro is defined, its definition should be a C expression;
1408 a nonzero value for the expression enables this behavior. */
1409
1410 #define PCC_BITFIELD_TYPE_MATTERS 1
1411
1412 /* If defined, a C expression to compute the alignment given to a
1413 constant that is being placed in memory. CONSTANT is the constant
1414 and ALIGN is the alignment that the object would ordinarily have.
1415 The value of this macro is used instead of that alignment to align
1416 the object.
1417
1418 If this macro is not defined, then ALIGN is used.
1419
1420 The typical use of this macro is to increase alignment for string
1421 constants to be word aligned so that `strcpy' calls that copy
1422 constants can be done inline. */
1423
1424 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1425 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1426 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1427
1428 /* If defined, a C expression to compute the alignment for a static
1429 variable. TYPE is the data type, and ALIGN is the alignment that
1430 the object would ordinarily have. The value of this macro is used
1431 instead of that alignment to align the object.
1432
1433 If this macro is not defined, then ALIGN is used.
1434
1435 One use of this macro is to increase alignment of medium-size
1436 data to make it all fit in fewer cache lines. Another is to
1437 cause character arrays to be word-aligned so that `strcpy' calls
1438 that copy constants to character arrays can be done inline. */
1439
1440 #undef DATA_ALIGNMENT
1441 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1442 ((((ALIGN) < BITS_PER_WORD) \
1443 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1444 || TREE_CODE (TYPE) == UNION_TYPE \
1445 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1446
1447 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1448 character arrays to be word-aligned so that `strcpy' calls that copy
1449 constants to character arrays can be done inline, and 'strcmp' can be
1450 optimised to use word loads. */
1451 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1452 DATA_ALIGNMENT (TYPE, ALIGN)
1453
1454 #define PAD_VARARGS_DOWN \
1455 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1456
1457 /* Define if operations between registers always perform the operation
1458 on the full register even if a narrower mode is specified. */
1459 #define WORD_REGISTER_OPERATIONS
1460
1461 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1462 moves. All other references are zero extended. */
1463 #define LOAD_EXTEND_OP(MODE) \
1464 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1465 ? SIGN_EXTEND : ZERO_EXTEND)
1466
1467 /* Define this macro if it is advisable to hold scalars in registers
1468 in a wider mode than that declared by the program. In such cases,
1469 the value is constrained to be within the bounds of the declared
1470 type, but kept valid in the wider mode. The signedness of the
1471 extension may differ from that of the type. */
1472
1473 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1474 if (GET_MODE_CLASS (MODE) == MODE_INT \
1475 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1476 { \
1477 if ((MODE) == SImode) \
1478 (UNSIGNEDP) = 0; \
1479 (MODE) = Pmode; \
1480 }
1481
1482 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1483 Extensions of pointers to word_mode must be signed. */
1484 #define POINTERS_EXTEND_UNSIGNED false
1485
1486 /* Define if loading short immediate values into registers sign extends. */
1487 #define SHORT_IMMEDIATES_SIGN_EXTEND
1488
1489 /* The [d]clz instructions have the natural values at 0. */
1490
1491 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1492 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1493 \f
1494 /* Standard register usage. */
1495
1496 /* Number of hardware registers. We have:
1497
1498 - 32 integer registers
1499 - 32 floating point registers
1500 - 8 condition code registers
1501 - 2 accumulator registers (hi and lo)
1502 - 32 registers each for coprocessors 0, 2 and 3
1503 - 4 fake registers:
1504 - ARG_POINTER_REGNUM
1505 - FRAME_POINTER_REGNUM
1506 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1507 - CPRESTORE_SLOT_REGNUM
1508 - 2 dummy entries that were used at various times in the past.
1509 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1510 - 6 DSP control registers */
1511
1512 #define FIRST_PSEUDO_REGISTER 188
1513
1514 /* By default, fix the kernel registers ($26 and $27), the global
1515 pointer ($28) and the stack pointer ($29). This can change
1516 depending on the command-line options.
1517
1518 Regarding coprocessor registers: without evidence to the contrary,
1519 it's best to assume that each coprocessor register has a unique
1520 use. This can be overridden, in, e.g., mips_option_override or
1521 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1522 inappropriate for a particular target. */
1523
1524 #define FIXED_REGISTERS \
1525 { \
1526 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1527 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1528 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1529 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1530 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1531 /* COP0 registers */ \
1532 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1533 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1534 /* COP2 registers */ \
1535 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1536 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1537 /* COP3 registers */ \
1538 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1539 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1540 /* 6 DSP accumulator registers & 6 control registers */ \
1541 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1542 }
1543
1544
1545 /* Set up this array for o32 by default.
1546
1547 Note that we don't mark $31 as a call-clobbered register. The idea is
1548 that it's really the call instructions themselves which clobber $31.
1549 We don't care what the called function does with it afterwards.
1550
1551 This approach makes it easier to implement sibcalls. Unlike normal
1552 calls, sibcalls don't clobber $31, so the register reaches the
1553 called function in tact. EPILOGUE_USES says that $31 is useful
1554 to the called function. */
1555
1556 #define CALL_USED_REGISTERS \
1557 { \
1558 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1559 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1561 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1562 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1563 /* COP0 registers */ \
1564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1565 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1566 /* COP2 registers */ \
1567 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1568 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1569 /* COP3 registers */ \
1570 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1571 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1572 /* 6 DSP accumulator registers & 6 control registers */ \
1573 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1574 }
1575
1576
1577 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1578
1579 #define CALL_REALLY_USED_REGISTERS \
1580 { /* General registers. */ \
1581 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1582 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1583 /* Floating-point registers. */ \
1584 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1585 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1586 /* Others. */ \
1587 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1588 /* COP0 registers */ \
1589 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1590 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1591 /* COP2 registers */ \
1592 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1594 /* COP3 registers */ \
1595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1596 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1597 /* 6 DSP accumulator registers & 6 control registers */ \
1598 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1599 }
1600
1601 /* Internal macros to classify a register number as to whether it's a
1602 general purpose register, a floating point register, a
1603 multiply/divide register, or a status register. */
1604
1605 #define GP_REG_FIRST 0
1606 #define GP_REG_LAST 31
1607 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1608 #define GP_DBX_FIRST 0
1609 #define K0_REG_NUM (GP_REG_FIRST + 26)
1610 #define K1_REG_NUM (GP_REG_FIRST + 27)
1611 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1612
1613 #define FP_REG_FIRST 32
1614 #define FP_REG_LAST 63
1615 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1616 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1617
1618 #define MD_REG_FIRST 64
1619 #define MD_REG_LAST 65
1620 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1621 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1622
1623 /* The DWARF 2 CFA column which tracks the return address from a
1624 signal handler context. This means that to maintain backwards
1625 compatibility, no hard register can be assigned this column if it
1626 would need to be handled by the DWARF unwinder. */
1627 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1628
1629 #define ST_REG_FIRST 67
1630 #define ST_REG_LAST 74
1631 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1632
1633
1634 /* FIXME: renumber. */
1635 #define COP0_REG_FIRST 80
1636 #define COP0_REG_LAST 111
1637 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1638
1639 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1640 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1641 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1642
1643 #define COP2_REG_FIRST 112
1644 #define COP2_REG_LAST 143
1645 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1646
1647 #define COP3_REG_FIRST 144
1648 #define COP3_REG_LAST 175
1649 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1650
1651 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1652 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1653 #define ALL_COP_REG_LAST COP3_REG_LAST
1654 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1655
1656 #define DSP_ACC_REG_FIRST 176
1657 #define DSP_ACC_REG_LAST 181
1658 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1659
1660 #define AT_REGNUM (GP_REG_FIRST + 1)
1661 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1662 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1663
1664 /* A few bitfield locations for the coprocessor registers. */
1665 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1666 the cause register for the EIC interrupt mode. */
1667 #define CAUSE_IPL 10
1668 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1669 #define SR_IPL 10
1670 /* Exception Level is at bit 1 of the status register. */
1671 #define SR_EXL 1
1672 /* Interrupt Enable is at bit 0 of the status register. */
1673 #define SR_IE 0
1674
1675 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1676 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1677 should be used instead. */
1678 #define FPSW_REGNUM ST_REG_FIRST
1679
1680 #define GP_REG_P(REGNO) \
1681 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1682 #define M16_REG_P(REGNO) \
1683 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1684 #define M16STORE_REG_P(REGNO) \
1685 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1686 #define FP_REG_P(REGNO) \
1687 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1688 #define MD_REG_P(REGNO) \
1689 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1690 #define ST_REG_P(REGNO) \
1691 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1692 #define COP0_REG_P(REGNO) \
1693 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1694 #define COP2_REG_P(REGNO) \
1695 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1696 #define COP3_REG_P(REGNO) \
1697 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1698 #define ALL_COP_REG_P(REGNO) \
1699 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1700 /* Test if REGNO is one of the 6 new DSP accumulators. */
1701 #define DSP_ACC_REG_P(REGNO) \
1702 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1703 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1704 #define ACC_REG_P(REGNO) \
1705 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1706
1707 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1708
1709 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1710 to initialize the mips16 gp pseudo register. */
1711 #define CONST_GP_P(X) \
1712 (GET_CODE (X) == CONST \
1713 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1714 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1715
1716 /* Return coprocessor number from register number. */
1717
1718 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1719 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1720 : COP3_REG_P (REGNO) ? '3' : '?')
1721
1722
1723 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1724
1725 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1726 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1727
1728 #define MODES_TIEABLE_P mips_modes_tieable_p
1729
1730 /* Register to use for pushing function arguments. */
1731 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1732
1733 /* These two registers don't really exist: they get eliminated to either
1734 the stack or hard frame pointer. */
1735 #define ARG_POINTER_REGNUM 77
1736 #define FRAME_POINTER_REGNUM 78
1737
1738 /* $30 is not available on the mips16, so we use $17 as the frame
1739 pointer. */
1740 #define HARD_FRAME_POINTER_REGNUM \
1741 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1742
1743 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1744 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1745
1746 /* Register in which static-chain is passed to a function. */
1747 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1748
1749 /* Registers used as temporaries in prologue/epilogue code:
1750
1751 - If a MIPS16 PIC function needs access to _gp, it first loads
1752 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1753
1754 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1755 register. The register must not conflict with MIPS16_PIC_TEMP.
1756
1757 - If we aren't generating MIPS16 code, the prologue can also use
1758 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1759
1760 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1761 register.
1762
1763 If we're generating MIPS16 code, these registers must come from the
1764 core set of 8. The prologue registers mustn't conflict with any
1765 incoming arguments, the static chain pointer, or the frame pointer.
1766 The epilogue temporary mustn't conflict with the return registers,
1767 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1768 or the EH data registers.
1769
1770 If we're generating interrupt handlers, we use K0 as a temporary register
1771 in prologue/epilogue code. */
1772
1773 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1774 #define MIPS_PROLOGUE_TEMP_REGNUM \
1775 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1776 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1777 (TARGET_MIPS16 \
1778 ? (gcc_unreachable (), INVALID_REGNUM) \
1779 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1780 #define MIPS_EPILOGUE_TEMP_REGNUM \
1781 (cfun->machine->interrupt_handler_p \
1782 ? K0_REG_NUM \
1783 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1784
1785 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1786 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1787 #define MIPS_PROLOGUE_TEMP2(MODE) \
1788 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1789 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1790
1791 /* Define this macro if it is as good or better to call a constant
1792 function address than to call an address kept in a register. */
1793 #define NO_FUNCTION_CSE 1
1794
1795 /* The ABI-defined global pointer. Sometimes we use a different
1796 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1797 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1798
1799 /* We normally use $28 as the global pointer. However, when generating
1800 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1801 register instead. They can then avoid saving and restoring $28
1802 and perhaps avoid using a frame at all.
1803
1804 When a leaf function uses something other than $28, mips_expand_prologue
1805 will modify pic_offset_table_rtx in place. Take the register number
1806 from there after reload. */
1807 #define PIC_OFFSET_TABLE_REGNUM \
1808 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1809 \f
1810 /* Define the classes of registers for register constraints in the
1811 machine description. Also define ranges of constants.
1812
1813 One of the classes must always be named ALL_REGS and include all hard regs.
1814 If there is more than one class, another class must be named NO_REGS
1815 and contain no registers.
1816
1817 The name GENERAL_REGS must be the name of a class (or an alias for
1818 another name such as ALL_REGS). This is the class of registers
1819 that is allowed by "g" or "r" in a register constraint.
1820 Also, registers outside this class are allocated only when
1821 instructions express preferences for them.
1822
1823 The classes must be numbered in nondecreasing order; that is,
1824 a larger-numbered class must never be contained completely
1825 in a smaller-numbered class.
1826
1827 For any two classes, it is very desirable that there be another
1828 class that represents their union. */
1829
1830 enum reg_class
1831 {
1832 NO_REGS, /* no registers in set */
1833 M16_REGS, /* mips16 directly accessible registers */
1834 T_REG, /* mips16 T register ($24) */
1835 M16_T_REGS, /* mips16 registers plus T register */
1836 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1837 V1_REG, /* Register $v1 ($3) used for TLS access. */
1838 LEA_REGS, /* Every GPR except $25 */
1839 GR_REGS, /* integer registers */
1840 FP_REGS, /* floating point registers */
1841 MD0_REG, /* first multiply/divide register */
1842 MD1_REG, /* second multiply/divide register */
1843 MD_REGS, /* multiply/divide registers (hi/lo) */
1844 COP0_REGS, /* generic coprocessor classes */
1845 COP2_REGS,
1846 COP3_REGS,
1847 ST_REGS, /* status registers (fp status) */
1848 DSP_ACC_REGS, /* DSP accumulator registers */
1849 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1850 FRAME_REGS, /* $arg and $frame */
1851 GR_AND_MD0_REGS, /* union classes */
1852 GR_AND_MD1_REGS,
1853 GR_AND_MD_REGS,
1854 GR_AND_ACC_REGS,
1855 ALL_REGS, /* all registers */
1856 LIM_REG_CLASSES /* max value + 1 */
1857 };
1858
1859 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1860
1861 #define GENERAL_REGS GR_REGS
1862
1863 /* An initializer containing the names of the register classes as C
1864 string constants. These names are used in writing some of the
1865 debugging dumps. */
1866
1867 #define REG_CLASS_NAMES \
1868 { \
1869 "NO_REGS", \
1870 "M16_REGS", \
1871 "T_REG", \
1872 "M16_T_REGS", \
1873 "PIC_FN_ADDR_REG", \
1874 "V1_REG", \
1875 "LEA_REGS", \
1876 "GR_REGS", \
1877 "FP_REGS", \
1878 "MD0_REG", \
1879 "MD1_REG", \
1880 "MD_REGS", \
1881 /* coprocessor registers */ \
1882 "COP0_REGS", \
1883 "COP2_REGS", \
1884 "COP3_REGS", \
1885 "ST_REGS", \
1886 "DSP_ACC_REGS", \
1887 "ACC_REGS", \
1888 "FRAME_REGS", \
1889 "GR_AND_MD0_REGS", \
1890 "GR_AND_MD1_REGS", \
1891 "GR_AND_MD_REGS", \
1892 "GR_AND_ACC_REGS", \
1893 "ALL_REGS" \
1894 }
1895
1896 /* An initializer containing the contents of the register classes,
1897 as integers which are bit masks. The Nth integer specifies the
1898 contents of class N. The way the integer MASK is interpreted is
1899 that register R is in the class if `MASK & (1 << R)' is 1.
1900
1901 When the machine has more than 32 registers, an integer does not
1902 suffice. Then the integers are replaced by sub-initializers,
1903 braced groupings containing several integers. Each
1904 sub-initializer must be suitable as an initializer for the type
1905 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1906
1907 #define REG_CLASS_CONTENTS \
1908 { \
1909 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1910 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1911 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1912 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1913 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1914 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1915 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1916 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1917 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1918 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1919 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1920 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1921 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1922 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1923 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1924 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1925 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1926 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1927 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1928 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1929 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1930 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1931 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1932 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1933 }
1934
1935
1936 /* A C expression whose value is a register class containing hard
1937 register REGNO. In general there is more that one such class;
1938 choose a class which is "minimal", meaning that no smaller class
1939 also contains the register. */
1940
1941 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1942
1943 /* A macro whose definition is the name of the class to which a
1944 valid base register must belong. A base register is one used in
1945 an address which is the register value plus a displacement. */
1946
1947 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1948
1949 /* A macro whose definition is the name of the class to which a
1950 valid index register must belong. An index register is one used
1951 in an address where its value is either multiplied by a scale
1952 factor or added to another register (as well as added to a
1953 displacement). */
1954
1955 #define INDEX_REG_CLASS NO_REGS
1956
1957 /* We generally want to put call-clobbered registers ahead of
1958 call-saved ones. (IRA expects this.) */
1959
1960 #define REG_ALLOC_ORDER \
1961 { /* Accumulator registers. When GPRs and accumulators have equal \
1962 cost, we generally prefer to use accumulators. For example, \
1963 a division of multiplication result is better allocated to LO, \
1964 so that we put the MFLO at the point of use instead of at the \
1965 point of definition. It's also needed if we're to take advantage \
1966 of the extra accumulators available with -mdspr2. In some cases, \
1967 it can also help to reduce register pressure. */ \
1968 64, 65,176,177,178,179,180,181, \
1969 /* Call-clobbered GPRs. */ \
1970 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1971 24, 25, 31, \
1972 /* The global pointer. This is call-clobbered for o32 and o64 \
1973 abicalls, call-saved for n32 and n64 abicalls, and a program \
1974 invariant otherwise. Putting it between the call-clobbered \
1975 and call-saved registers should cope with all eventualities. */ \
1976 28, \
1977 /* Call-saved GPRs. */ \
1978 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1979 /* GPRs that can never be exposed to the register allocator. */ \
1980 0, 26, 27, 29, \
1981 /* Call-clobbered FPRs. */ \
1982 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1983 48, 49, 50, 51, \
1984 /* FPRs that are usually call-saved. The odd ones are actually \
1985 call-clobbered for n32, but listing them ahead of the even \
1986 registers might encourage the register allocator to fragment \
1987 the available FPR pairs. We need paired FPRs to store long \
1988 doubles, so it isn't clear that using a different order \
1989 for n32 would be a win. */ \
1990 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1991 /* None of the remaining classes have defined call-saved \
1992 registers. */ \
1993 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1994 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1995 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1996 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1997 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1998 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1999 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2000 182,183,184,185,186,187 \
2001 }
2002
2003 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
2004 to be rearranged based on a particular function. On the mips16, we
2005 want to allocate $24 (T_REG) before other registers for
2006 instructions for which it is possible. */
2007
2008 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2009
2010 /* True if VALUE is an unsigned 6-bit number. */
2011
2012 #define UIMM6_OPERAND(VALUE) \
2013 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2014
2015 /* True if VALUE is a signed 10-bit number. */
2016
2017 #define IMM10_OPERAND(VALUE) \
2018 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2019
2020 /* True if VALUE is a signed 16-bit number. */
2021
2022 #define SMALL_OPERAND(VALUE) \
2023 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2024
2025 /* True if VALUE is an unsigned 16-bit number. */
2026
2027 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2028 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2029
2030 /* True if VALUE can be loaded into a register using LUI. */
2031
2032 #define LUI_OPERAND(VALUE) \
2033 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2034 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2035
2036 /* Return a value X with the low 16 bits clear, and such that
2037 VALUE - X is a signed 16-bit value. */
2038
2039 #define CONST_HIGH_PART(VALUE) \
2040 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2041
2042 #define CONST_LOW_PART(VALUE) \
2043 ((VALUE) - CONST_HIGH_PART (VALUE))
2044
2045 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2046 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2047 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2048 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2049
2050 /* The HI and LO registers can only be reloaded via the general
2051 registers. Condition code registers can only be loaded to the
2052 general registers, and from the floating point registers. */
2053
2054 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2055 mips_secondary_reload_class (CLASS, MODE, X, true)
2056 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2057 mips_secondary_reload_class (CLASS, MODE, X, false)
2058
2059 /* Return the maximum number of consecutive registers
2060 needed to represent mode MODE in a register of class CLASS. */
2061
2062 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2063
2064 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2065 mips_cannot_change_mode_class (FROM, TO, CLASS)
2066 \f
2067 /* Stack layout; function entry, exit and calling. */
2068
2069 #define STACK_GROWS_DOWNWARD
2070
2071 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2072
2073 /* Size of the area allocated in the frame to save the GP. */
2074
2075 #define MIPS_GP_SAVE_AREA_SIZE \
2076 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2077
2078 /* The offset of the first local variable from the frame pointer. See
2079 mips_compute_frame_info for details about the frame layout. */
2080
2081 #define STARTING_FRAME_OFFSET \
2082 (FRAME_GROWS_DOWNWARD \
2083 ? 0 \
2084 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2085
2086 #define RETURN_ADDR_RTX mips_return_addr
2087
2088 /* Mask off the MIPS16 ISA bit in unwind addresses.
2089
2090 The reason for this is a little subtle. When unwinding a call,
2091 we are given the call's return address, which on most targets
2092 is the address of the following instruction. However, what we
2093 actually want to find is the EH region for the call itself.
2094 The target-independent unwind code therefore searches for "RA - 1".
2095
2096 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2097 RA - 1 is therefore the real (even-valued) start of the return
2098 instruction. EH region labels are usually odd-valued MIPS16 symbols
2099 too, so a search for an even address within a MIPS16 region would
2100 usually work.
2101
2102 However, there is an exception. If the end of an EH region is also
2103 the end of a function, the end label is allowed to be even. This is
2104 necessary because a following non-MIPS16 function may also need EH
2105 information for its first instruction.
2106
2107 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2108 non-ISA-encoded address. This probably isn't ideal, but it is
2109 the traditional (legacy) behavior. It is therefore only safe
2110 to search MIPS EH regions for an _odd-valued_ address.
2111
2112 Masking off the ISA bit means that the target-independent code
2113 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2114 #define MASK_RETURN_ADDR GEN_INT (-2)
2115
2116
2117 /* Similarly, don't use the least-significant bit to tell pointers to
2118 code from vtable index. */
2119
2120 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2121
2122 /* The eliminations to $17 are only used for mips16 code. See the
2123 definition of HARD_FRAME_POINTER_REGNUM. */
2124
2125 #define ELIMINABLE_REGS \
2126 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2127 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2128 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2129 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2130 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2131 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2132
2133 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2134 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2135
2136 /* Allocate stack space for arguments at the beginning of each function. */
2137 #define ACCUMULATE_OUTGOING_ARGS 1
2138
2139 /* The argument pointer always points to the first argument. */
2140 #define FIRST_PARM_OFFSET(FNDECL) 0
2141
2142 /* o32 and o64 reserve stack space for all argument registers. */
2143 #define REG_PARM_STACK_SPACE(FNDECL) \
2144 (TARGET_OLDABI \
2145 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2146 : 0)
2147
2148 /* Define this if it is the responsibility of the caller to
2149 allocate the area reserved for arguments passed in registers.
2150 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2151 of this macro is to determine whether the space is included in
2152 `crtl->outgoing_args_size'. */
2153 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2154
2155 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2156 \f
2157 /* Symbolic macros for the registers used to return integer and floating
2158 point values. */
2159
2160 #define GP_RETURN (GP_REG_FIRST + 2)
2161 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2162
2163 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2164
2165 /* Symbolic macros for the first/last argument registers. */
2166
2167 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2168 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2169 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2170 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2171
2172 /* 1 if N is a possible register number for function argument passing.
2173 We have no FP argument registers when soft-float. When FP registers
2174 are 32 bits, we can't directly reference the odd numbered ones. */
2175
2176 #define FUNCTION_ARG_REGNO_P(N) \
2177 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2178 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2179 && !fixed_regs[N])
2180 \f
2181 /* This structure has to cope with two different argument allocation
2182 schemes. Most MIPS ABIs view the arguments as a structure, of which
2183 the first N words go in registers and the rest go on the stack. If I
2184 < N, the Ith word might go in Ith integer argument register or in a
2185 floating-point register. For these ABIs, we only need to remember
2186 the offset of the current argument into the structure.
2187
2188 The EABI instead allocates the integer and floating-point arguments
2189 separately. The first N words of FP arguments go in FP registers,
2190 the rest go on the stack. Likewise, the first N words of the other
2191 arguments go in integer registers, and the rest go on the stack. We
2192 need to maintain three counts: the number of integer registers used,
2193 the number of floating-point registers used, and the number of words
2194 passed on the stack.
2195
2196 We could keep separate information for the two ABIs (a word count for
2197 the standard ABIs, and three separate counts for the EABI). But it
2198 seems simpler to view the standard ABIs as forms of EABI that do not
2199 allocate floating-point registers.
2200
2201 So for the standard ABIs, the first N words are allocated to integer
2202 registers, and mips_function_arg decides on an argument-by-argument
2203 basis whether that argument should really go in an integer register,
2204 or in a floating-point one. */
2205
2206 typedef struct mips_args {
2207 /* Always true for varargs functions. Otherwise true if at least
2208 one argument has been passed in an integer register. */
2209 int gp_reg_found;
2210
2211 /* The number of arguments seen so far. */
2212 unsigned int arg_number;
2213
2214 /* The number of integer registers used so far. For all ABIs except
2215 EABI, this is the number of words that have been added to the
2216 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2217 unsigned int num_gprs;
2218
2219 /* For EABI, the number of floating-point registers used so far. */
2220 unsigned int num_fprs;
2221
2222 /* The number of words passed on the stack. */
2223 unsigned int stack_words;
2224
2225 /* On the mips16, we need to keep track of which floating point
2226 arguments were passed in general registers, but would have been
2227 passed in the FP regs if this were a 32-bit function, so that we
2228 can move them to the FP regs if we wind up calling a 32-bit
2229 function. We record this information in fp_code, encoded in base
2230 four. A zero digit means no floating point argument, a one digit
2231 means an SFmode argument, and a two digit means a DFmode argument,
2232 and a three digit is not used. The low order digit is the first
2233 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2234 an SFmode argument. ??? A more sophisticated approach will be
2235 needed if MIPS_ABI != ABI_32. */
2236 int fp_code;
2237
2238 /* True if the function has a prototype. */
2239 int prototype;
2240 } CUMULATIVE_ARGS;
2241
2242 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2243 for a call to a function whose data type is FNTYPE.
2244 For a library call, FNTYPE is 0. */
2245
2246 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2247 mips_init_cumulative_args (&CUM, FNTYPE)
2248
2249 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2250 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2251
2252 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2253 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2254
2255 /* True if using EABI and varargs can be passed in floating-point
2256 registers. Under these conditions, we need a more complex form
2257 of va_list, which tracks GPR, FPR and stack arguments separately. */
2258 #define EABI_FLOAT_VARARGS_P \
2259 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2260
2261 \f
2262 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2263
2264 /* Treat LOC as a byte offset from the stack pointer and round it up
2265 to the next fully-aligned offset. */
2266 #define MIPS_STACK_ALIGN(LOC) \
2267 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2268
2269 \f
2270 /* Output assembler code to FILE to increment profiler label # LABELNO
2271 for profiling a function entry. */
2272
2273 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2274
2275 /* The profiler preserves all interesting registers, including $31. */
2276 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2277
2278 /* No mips port has ever used the profiler counter word, so don't emit it
2279 or the label for it. */
2280
2281 #define NO_PROFILE_COUNTERS 1
2282
2283 /* Define this macro if the code for function profiling should come
2284 before the function prologue. Normally, the profiling code comes
2285 after. */
2286
2287 /* #define PROFILE_BEFORE_PROLOGUE */
2288
2289 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2290 the stack pointer does not matter. The value is tested only in
2291 functions that have frame pointers.
2292 No definition is equivalent to always zero. */
2293
2294 #define EXIT_IGNORE_STACK 1
2295
2296 \f
2297 /* Trampolines are a block of code followed by two pointers. */
2298
2299 #define TRAMPOLINE_SIZE \
2300 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2301
2302 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2303 pointers from a single LUI base. */
2304
2305 #define TRAMPOLINE_ALIGNMENT 64
2306
2307 /* mips_trampoline_init calls this library function to flush
2308 program and data caches. */
2309
2310 #ifndef CACHE_FLUSH_FUNC
2311 #define CACHE_FLUSH_FUNC "_flush_cache"
2312 #endif
2313
2314 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2315 /* Flush both caches. We need to flush the data cache in case \
2316 the system has a write-back cache. */ \
2317 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2318 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2319 GEN_INT (3), TYPE_MODE (integer_type_node))
2320
2321 \f
2322 /* Addressing modes, and classification of registers for them. */
2323
2324 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2325 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2326 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2327 \f
2328 /* Maximum number of registers that can appear in a valid memory address. */
2329
2330 #define MAX_REGS_PER_ADDRESS 1
2331
2332 /* Check for constness inline but use mips_legitimate_address_p
2333 to check whether a constant really is an address. */
2334
2335 #define CONSTANT_ADDRESS_P(X) \
2336 (CONSTANT_P (X) && memory_address_p (SImode, X))
2337
2338 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2339 'the start of the function that this code is output in'. */
2340
2341 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2342 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2343 asm_fprintf ((FILE), "%U%s", \
2344 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2345 else \
2346 asm_fprintf ((FILE), "%U%s", (NAME))
2347 \f
2348 /* Flag to mark a function decl symbol that requires a long call. */
2349 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2350 #define SYMBOL_REF_LONG_CALL_P(X) \
2351 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2352
2353 /* This flag marks functions that cannot be lazily bound. */
2354 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2355 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2356 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2357
2358 /* True if we're generating a form of MIPS16 code in which jump tables
2359 are stored in the text section and encoded as 16-bit PC-relative
2360 offsets. This is only possible when general text loads are allowed,
2361 since the table access itself will be an "lh" instruction. If the
2362 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2363 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2364
2365 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2366
2367 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2368
2369 /* Only use short offsets if their range will not overflow. */
2370 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2371 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2372 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2373 : SImode)
2374
2375 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2376
2377 /* Define this as 1 if `char' should by default be signed; else as 0. */
2378 #ifndef DEFAULT_SIGNED_CHAR
2379 #define DEFAULT_SIGNED_CHAR 1
2380 #endif
2381
2382 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2383 we generally don't want to use them for copying arbitrary data.
2384 A single N-word move is usually the same cost as N single-word moves. */
2385 #define MOVE_MAX UNITS_PER_WORD
2386 #define MAX_MOVE_MAX 8
2387
2388 /* Define this macro as a C expression which is nonzero if
2389 accessing less than a word of memory (i.e. a `char' or a
2390 `short') is no faster than accessing a word of memory, i.e., if
2391 such access require more than one instruction or if there is no
2392 difference in cost between byte and (aligned) word loads.
2393
2394 On RISC machines, it tends to generate better code to define
2395 this as 1, since it avoids making a QI or HI mode register.
2396
2397 But, generating word accesses for -mips16 is generally bad as shifts
2398 (often extended) would be needed for byte accesses. */
2399 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2400
2401 /* Standard MIPS integer shifts truncate the shift amount to the
2402 width of the shifted operand. However, Loongson vector shifts
2403 do not truncate the shift amount at all. */
2404 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2405
2406 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2407 is done just by pretending it is already truncated. */
2408 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2409 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2410
2411
2412 /* Specify the machine mode that pointers have.
2413 After generation of rtl, the compiler makes no further distinction
2414 between pointers and any other objects of this machine mode. */
2415
2416 #ifndef Pmode
2417 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2418 #endif
2419
2420 /* Give call MEMs SImode since it is the "most permissive" mode
2421 for both 32-bit and 64-bit targets. */
2422
2423 #define FUNCTION_MODE SImode
2424
2425 \f
2426 /* We allocate $fcc registers by hand and can't cope with moves of
2427 CCmode registers to and from pseudos (or memory). */
2428 #define AVOID_CCMODE_COPIES
2429
2430 /* A C expression for the cost of a branch instruction. A value of
2431 1 is the default; other values are interpreted relative to that. */
2432
2433 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2434 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2435
2436 /* The MIPS port has several functions that return an instruction count.
2437 Multiplying the count by this value gives the number of bytes that
2438 the instructions occupy. */
2439 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2440
2441 /* The length of a NOP in bytes. */
2442 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2443
2444 /* If defined, modifies the length assigned to instruction INSN as a
2445 function of the context in which it is used. LENGTH is an lvalue
2446 that contains the initially computed length of the insn and should
2447 be updated with the correct length of the insn. */
2448 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2449 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2450
2451 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2452 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2453 its operands. */
2454 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2455 "%*" OPCODE "%?\t" OPERANDS "%/"
2456
2457 /* Return an asm string that forces INSN to be treated as an absolute
2458 J or JAL instruction instead of an assembler macro. */
2459 #define MIPS_ABSOLUTE_JUMP(INSN) \
2460 (TARGET_ABICALLS_PIC2 \
2461 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2462 : INSN)
2463
2464 /* Return the asm template for a call. INSN is the instruction's mnemonic
2465 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2466 number of the target. SIZE_OPNO is the operand number of the argument size
2467 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2468 -1 and the call is indirect, use the function symbol from the call
2469 attributes to attach a R_MIPS_JALR relocation to the call.
2470
2471 When generating GOT code without explicit relocation operators,
2472 all calls should use assembly macros. Otherwise, all indirect
2473 calls should use "jr" or "jalr"; we will arrange to restore $gp
2474 afterwards if necessary. Finally, we can only generate direct
2475 calls for -mabicalls by temporarily switching to non-PIC mode.
2476
2477 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2478 instruction is in the delay slot of jal(r). */
2479 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2480 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2481 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2482 : REG_P (OPERANDS[TARGET_OPNO]) \
2483 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2484 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2485 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2486 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2487 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2488 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2489 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2490
2491 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2492 "jrc" when nop is in the delay slot of "jr". */
2493
2494 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2495 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2496 ? "%*j\t%" #OPNO "%/" \
2497 : REG_P (OPERANDS[OPNO]) \
2498 ? "%*jr%:\t%" #OPNO \
2499 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2500
2501 \f
2502 /* Control the assembler format that we output. */
2503
2504 /* Output to assembler file text saying following lines
2505 may contain character constants, extra white space, comments, etc. */
2506
2507 #ifndef ASM_APP_ON
2508 #define ASM_APP_ON " #APP\n"
2509 #endif
2510
2511 /* Output to assembler file text saying following lines
2512 no longer contain unusual constructs. */
2513
2514 #ifndef ASM_APP_OFF
2515 #define ASM_APP_OFF " #NO_APP\n"
2516 #endif
2517
2518 #define REGISTER_NAMES \
2519 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2520 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2521 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2522 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2523 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2524 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2525 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2526 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2527 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2528 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2529 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2530 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2531 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2532 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2533 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2534 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2535 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2536 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2537 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2538 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2539 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2540 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2541 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2542 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2543
2544 /* List the "software" names for each register. Also list the numerical
2545 names for $fp and $sp. */
2546
2547 #define ADDITIONAL_REGISTER_NAMES \
2548 { \
2549 { "$29", 29 + GP_REG_FIRST }, \
2550 { "$30", 30 + GP_REG_FIRST }, \
2551 { "at", 1 + GP_REG_FIRST }, \
2552 { "v0", 2 + GP_REG_FIRST }, \
2553 { "v1", 3 + GP_REG_FIRST }, \
2554 { "a0", 4 + GP_REG_FIRST }, \
2555 { "a1", 5 + GP_REG_FIRST }, \
2556 { "a2", 6 + GP_REG_FIRST }, \
2557 { "a3", 7 + GP_REG_FIRST }, \
2558 { "t0", 8 + GP_REG_FIRST }, \
2559 { "t1", 9 + GP_REG_FIRST }, \
2560 { "t2", 10 + GP_REG_FIRST }, \
2561 { "t3", 11 + GP_REG_FIRST }, \
2562 { "t4", 12 + GP_REG_FIRST }, \
2563 { "t5", 13 + GP_REG_FIRST }, \
2564 { "t6", 14 + GP_REG_FIRST }, \
2565 { "t7", 15 + GP_REG_FIRST }, \
2566 { "s0", 16 + GP_REG_FIRST }, \
2567 { "s1", 17 + GP_REG_FIRST }, \
2568 { "s2", 18 + GP_REG_FIRST }, \
2569 { "s3", 19 + GP_REG_FIRST }, \
2570 { "s4", 20 + GP_REG_FIRST }, \
2571 { "s5", 21 + GP_REG_FIRST }, \
2572 { "s6", 22 + GP_REG_FIRST }, \
2573 { "s7", 23 + GP_REG_FIRST }, \
2574 { "t8", 24 + GP_REG_FIRST }, \
2575 { "t9", 25 + GP_REG_FIRST }, \
2576 { "k0", 26 + GP_REG_FIRST }, \
2577 { "k1", 27 + GP_REG_FIRST }, \
2578 { "gp", 28 + GP_REG_FIRST }, \
2579 { "sp", 29 + GP_REG_FIRST }, \
2580 { "fp", 30 + GP_REG_FIRST }, \
2581 { "ra", 31 + GP_REG_FIRST } \
2582 }
2583
2584 #define DBR_OUTPUT_SEQEND(STREAM) \
2585 do \
2586 { \
2587 /* Undo the effect of '%*'. */ \
2588 mips_pop_asm_switch (&mips_nomacro); \
2589 mips_pop_asm_switch (&mips_noreorder); \
2590 /* Emit a blank line after the delay slot for emphasis. */ \
2591 fputs ("\n", STREAM); \
2592 } \
2593 while (0)
2594
2595 /* The MIPS implementation uses some labels for its own purpose. The
2596 following lists what labels are created, and are all formed by the
2597 pattern $L[a-z].*. The machine independent portion of GCC creates
2598 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2599
2600 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2601 $Lb[0-9]+ Begin blocks for MIPS debug support
2602 $Lc[0-9]+ Label for use in s<xx> operation.
2603 $Le[0-9]+ End blocks for MIPS debug support */
2604
2605 #undef ASM_DECLARE_OBJECT_NAME
2606 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2607 mips_declare_object (STREAM, NAME, "", ":\n")
2608
2609 /* Globalizing directive for a label. */
2610 #define GLOBAL_ASM_OP "\t.globl\t"
2611
2612 /* This says how to define a global common symbol. */
2613
2614 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2615
2616 /* This says how to define a local common symbol (i.e., not visible to
2617 linker). */
2618
2619 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2620 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2621 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2622 #endif
2623
2624 /* This says how to output an external. It would be possible not to
2625 output anything and let undefined symbol become external. However
2626 the assembler uses length information on externals to allocate in
2627 data/sdata bss/sbss, thereby saving exec time. */
2628
2629 #undef ASM_OUTPUT_EXTERNAL
2630 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2631 mips_output_external(STREAM,DECL,NAME)
2632
2633 /* This is how to declare a function name. The actual work of
2634 emitting the label is moved to function_prologue, so that we can
2635 get the line number correctly emitted before the .ent directive,
2636 and after any .file directives. Define as empty so that the function
2637 is not declared before the .ent directive elsewhere. */
2638
2639 #undef ASM_DECLARE_FUNCTION_NAME
2640 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2641
2642 /* This is how to store into the string LABEL
2643 the symbol_ref name of an internal numbered label where
2644 PREFIX is the class of label and NUM is the number within the class.
2645 This is suitable for output with `assemble_name'. */
2646
2647 #undef ASM_GENERATE_INTERNAL_LABEL
2648 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2649 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2650
2651 /* Print debug labels as "foo = ." rather than "foo:" because they should
2652 represent a byte pointer rather than an ISA-encoded address. This is
2653 particularly important for code like:
2654
2655 $LFBxxx = .
2656 .cfi_startproc
2657 ...
2658 .section .gcc_except_table,...
2659 ...
2660 .uleb128 foo-$LFBxxx
2661
2662 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2663 likewise a byte pointer rather than an ISA-encoded address.
2664
2665 At the time of writing, this hook is not used for the function end
2666 label:
2667
2668 $LFExxx:
2669 .end foo
2670
2671 But this doesn't matter, because GAS doesn't treat a pre-.end label
2672 as a MIPS16 one anyway. */
2673
2674 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2675 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2676
2677 /* This is how to output an element of a case-vector that is absolute. */
2678
2679 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2680 fprintf (STREAM, "\t%s\t%sL%d\n", \
2681 ptr_mode == DImode ? ".dword" : ".word", \
2682 LOCAL_LABEL_PREFIX, \
2683 VALUE)
2684
2685 /* This is how to output an element of a case-vector. We can make the
2686 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2687 is supported. */
2688
2689 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2690 do { \
2691 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2692 { \
2693 if (GET_MODE (BODY) == HImode) \
2694 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2695 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2696 else \
2697 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2698 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2699 } \
2700 else if (TARGET_GPWORD) \
2701 fprintf (STREAM, "\t%s\t%sL%d\n", \
2702 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2703 LOCAL_LABEL_PREFIX, VALUE); \
2704 else if (TARGET_RTP_PIC) \
2705 { \
2706 /* Make the entry relative to the start of the function. */ \
2707 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2708 fprintf (STREAM, "\t%s\t%sL%d-", \
2709 Pmode == DImode ? ".dword" : ".word", \
2710 LOCAL_LABEL_PREFIX, VALUE); \
2711 assemble_name (STREAM, XSTR (fnsym, 0)); \
2712 fprintf (STREAM, "\n"); \
2713 } \
2714 else \
2715 fprintf (STREAM, "\t%s\t%sL%d\n", \
2716 ptr_mode == DImode ? ".dword" : ".word", \
2717 LOCAL_LABEL_PREFIX, VALUE); \
2718 } while (0)
2719
2720 /* This is how to output an assembler line
2721 that says to advance the location counter
2722 to a multiple of 2**LOG bytes. */
2723
2724 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2725 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2726
2727 /* This is how to output an assembler line to advance the location
2728 counter by SIZE bytes. */
2729
2730 #undef ASM_OUTPUT_SKIP
2731 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2732 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2733
2734 /* This is how to output a string. */
2735 #undef ASM_OUTPUT_ASCII
2736 #define ASM_OUTPUT_ASCII mips_output_ascii
2737
2738 \f
2739 /* Default to -G 8 */
2740 #ifndef MIPS_DEFAULT_GVALUE
2741 #define MIPS_DEFAULT_GVALUE 8
2742 #endif
2743
2744 /* Define the strings to put out for each section in the object file. */
2745 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2746 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2747
2748 #undef READONLY_DATA_SECTION_ASM_OP
2749 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2750 \f
2751 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2752 do \
2753 { \
2754 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2755 TARGET_64BIT ? "daddiu" : "addiu", \
2756 reg_names[STACK_POINTER_REGNUM], \
2757 reg_names[STACK_POINTER_REGNUM], \
2758 TARGET_64BIT ? "sd" : "sw", \
2759 reg_names[REGNO], \
2760 reg_names[STACK_POINTER_REGNUM]); \
2761 } \
2762 while (0)
2763
2764 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2765 do \
2766 { \
2767 mips_push_asm_switch (&mips_noreorder); \
2768 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2769 TARGET_64BIT ? "ld" : "lw", \
2770 reg_names[REGNO], \
2771 reg_names[STACK_POINTER_REGNUM], \
2772 TARGET_64BIT ? "daddu" : "addu", \
2773 reg_names[STACK_POINTER_REGNUM], \
2774 reg_names[STACK_POINTER_REGNUM]); \
2775 mips_pop_asm_switch (&mips_noreorder); \
2776 } \
2777 while (0)
2778
2779 /* How to start an assembler comment.
2780 The leading space is important (the mips native assembler requires it). */
2781 #ifndef ASM_COMMENT_START
2782 #define ASM_COMMENT_START " #"
2783 #endif
2784 \f
2785 #undef SIZE_TYPE
2786 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2787
2788 #undef PTRDIFF_TYPE
2789 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2790
2791 /* The maximum number of bytes that can be copied by one iteration of
2792 a movmemsi loop; see mips_block_move_loop. */
2793 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2794 (UNITS_PER_WORD * 4)
2795
2796 /* The maximum number of bytes that can be copied by a straight-line
2797 implementation of movmemsi; see mips_block_move_straight. We want
2798 to make sure that any loop-based implementation will iterate at
2799 least twice. */
2800 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2801 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2802
2803 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2804 values were determined experimentally by benchmarking with CSiBE.
2805 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2806 for o32 where we have to restore $gp afterwards as well as make an
2807 indirect call), but in practice, bumping this up higher for
2808 TARGET_ABICALLS doesn't make much difference to code size. */
2809
2810 #define MIPS_CALL_RATIO 8
2811
2812 /* Any loop-based implementation of movmemsi will have at least
2813 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2814 moves, so allow individual copies of fewer elements.
2815
2816 When movmemsi is not available, use a value approximating
2817 the length of a memcpy call sequence, so that move_by_pieces
2818 will generate inline code if it is shorter than a function call.
2819 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2820 we'll have to generate a load/store pair for each, halve the
2821 value of MIPS_CALL_RATIO to take that into account. */
2822
2823 #define MOVE_RATIO(speed) \
2824 (HAVE_movmemsi \
2825 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2826 : MIPS_CALL_RATIO / 2)
2827
2828 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2829 mips_move_by_pieces_p (SIZE, ALIGN)
2830
2831 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2832 of the length of a memset call, but use the default otherwise. */
2833
2834 #define CLEAR_RATIO(speed)\
2835 ((speed) ? 15 : MIPS_CALL_RATIO)
2836
2837 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2838 optimizing for size adjust the ratio to account for the overhead of
2839 loading the constant and replicating it across the word. */
2840
2841 #define SET_RATIO(speed) \
2842 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2843
2844 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2845 mips_store_by_pieces_p (SIZE, ALIGN)
2846 \f
2847 /* Since the bits of the _init and _fini function is spread across
2848 many object files, each potentially with its own GP, we must assume
2849 we need to load our GP. We don't preserve $gp or $ra, since each
2850 init/fini chunk is supposed to initialize $gp, and crti/crtn
2851 already take care of preserving $ra and, when appropriate, $gp. */
2852 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2853 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2854 asm (SECTION_OP "\n\
2855 .set push\n\
2856 .set nomips16\n\
2857 .set noreorder\n\
2858 bal 1f\n\
2859 nop\n\
2860 1: .cpload $31\n\
2861 .set reorder\n\
2862 jal " USER_LABEL_PREFIX #FUNC "\n\
2863 .set pop\n\
2864 " TEXT_SECTION_ASM_OP);
2865 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2866 || (defined _ABI64 && _MIPS_SIM == _ABI64))
2867 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2868 asm (SECTION_OP "\n\
2869 .set push\n\
2870 .set nomips16\n\
2871 .set noreorder\n\
2872 bal 1f\n\
2873 nop\n\
2874 1: .set reorder\n\
2875 .cpsetup $31, $2, 1b\n\
2876 jal " USER_LABEL_PREFIX #FUNC "\n\
2877 .set pop\n\
2878 " TEXT_SECTION_ASM_OP);
2879 #endif
2880
2881 #ifndef HAVE_AS_TLS
2882 #define HAVE_AS_TLS 0
2883 #endif
2884
2885 #ifndef USED_FOR_TARGET
2886 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2887 struct mips_asm_switch {
2888 /* The FOO in the description above. */
2889 const char *name;
2890
2891 /* The current block nesting level, or 0 if we aren't in a block. */
2892 int nesting_level;
2893 };
2894
2895 extern const enum reg_class mips_regno_to_class[];
2896 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2897 extern const char *current_function_file; /* filename current function is in */
2898 extern int num_source_filenames; /* current .file # */
2899 extern struct mips_asm_switch mips_noreorder;
2900 extern struct mips_asm_switch mips_nomacro;
2901 extern struct mips_asm_switch mips_noat;
2902 extern int mips_dbx_regno[];
2903 extern int mips_dwarf_regno[];
2904 extern bool mips_split_p[];
2905 extern bool mips_split_hi_p[];
2906 extern bool mips_use_pcrel_pool_p[];
2907 extern const char *mips_lo_relocs[];
2908 extern const char *mips_hi_relocs[];
2909 extern enum processor mips_arch; /* which cpu to codegen for */
2910 extern enum processor mips_tune; /* which cpu to schedule for */
2911 extern int mips_isa; /* architectural level */
2912 extern const struct mips_cpu_info *mips_arch_info;
2913 extern const struct mips_cpu_info *mips_tune_info;
2914 extern unsigned int mips_base_compression_flags;
2915 extern GTY(()) struct target_globals *mips16_globals;
2916 #endif
2917
2918 /* Enable querying of DFA units. */
2919 #define CPU_UNITS_QUERY 1
2920
2921 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2922 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2923
2924 /* As on most targets, we want the .eh_frame section to be read-only where
2925 possible. And as on most targets, this means two things:
2926
2927 (a) Non-locally-binding pointers must have an indirect encoding,
2928 so that the addresses in the .eh_frame section itself become
2929 locally-binding.
2930
2931 (b) A shared library's .eh_frame section must encode locally-binding
2932 pointers in a relative (relocation-free) form.
2933
2934 However, MIPS has traditionally not allowed directives like:
2935
2936 .long x-.
2937
2938 in cases where "x" is in a different section, or is not defined in the
2939 same assembly file. We are therefore unable to emit the PC-relative
2940 form required by (b) at assembly time.
2941
2942 Fortunately, the linker is able to convert absolute addresses into
2943 PC-relative addresses on our behalf. Unfortunately, only certain
2944 versions of the linker know how to do this for indirect pointers,
2945 and for personality data. We must fall back on using writable
2946 .eh_frame sections for shared libraries if the linker does not
2947 support this feature. */
2948 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2949 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2950
2951 /* For switching between MIPS16 and non-MIPS16 modes. */
2952 #define SWITCHABLE_TARGET 1
2953
2954 /* Several named MIPS patterns depend on Pmode. These patterns have the
2955 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2956 Add the appropriate suffix to generator function NAME and invoke it
2957 with arguments ARGS. */
2958 #define PMODE_INSN(NAME, ARGS) \
2959 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)