projects / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
mips-cpus.def (octeon+): New CPU.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 #ifdef GENERATOR_FILE
30 /* This is used in some insn conditions, so needs to be declared, but
31 does not need to be defined. */
32 extern int target_flags_explicit;
33 #endif
34
35 /* MIPS external variables defined in mips.c. */
36
37 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
38 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
39 to work on a 64-bit machine. */
40
41 #define ABI_32 0
42 #define ABI_N32 1
43 #define ABI_64 2
44 #define ABI_EABI 3
45 #define ABI_O64 4
46
47 /* Masks that affect tuning.
48
49 PTF_AVOID_BRANCHLIKELY
50 Set if it is usually not profitable to use branch-likely instructions
51 for this target, typically because the branches are always predicted
52 taken and so incur a large overhead when not taken. */
53 #define PTF_AVOID_BRANCHLIKELY 0x1
54
55 /* Information about one recognized processor. Defined here for the
56 benefit of TARGET_CPU_CPP_BUILTINS. */
57 struct mips_cpu_info {
58 /* The 'canonical' name of the processor as far as GCC is concerned.
59 It's typically a manufacturer's prefix followed by a numerical
60 designation. It should be lowercase. */
61 const char *name;
62
63 /* The internal processor number that most closely matches this
64 entry. Several processors can have the same value, if there's no
65 difference between them from GCC's point of view. */
66 enum processor cpu;
67
68 /* The ISA level that the processor implements. */
69 int isa;
70
71 /* A mask of PTF_* values. */
72 unsigned int tune_flags;
73 };
74
75 #include "config/mips/mips-opts.h"
76
77 /* Macros to silence warnings about numbers being signed in traditional
78 C and unsigned in ISO C when compiled on 32-bit hosts. */
79
80 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
81 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
82 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
83
84 \f
85 /* Run-time compilation parameters selecting different hardware subsets. */
86
87 /* True if we are generating position-independent VxWorks RTP code. */
88 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
89
90 /* True if the output file is marked as ".abicalls; .option pic0"
91 (-call_nonpic). */
92 #define TARGET_ABICALLS_PIC0 \
93 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
94
95 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
96 #define TARGET_ABICALLS_PIC2 \
97 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
98
99 /* True if the call patterns should be split into a jalr followed by
100 an instruction to restore $gp. It is only safe to split the load
101 from the call when every use of $gp is explicit.
102
103 See mips_must_initialize_gp_p for details about how we manage the
104 global pointer. */
105
106 #define TARGET_SPLIT_CALLS \
107 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
108
109 /* True if we're generating a form of -mabicalls in which we can use
110 operators like %hi and %lo to refer to locally-binding symbols.
111 We can only do this for -mno-shared, and only then if we can use
112 relocation operations instead of assembly macros. It isn't really
113 worth using absolute sequences for 64-bit symbols because GOT
114 accesses are so much shorter. */
115
116 #define TARGET_ABSOLUTE_ABICALLS \
117 (TARGET_ABICALLS \
118 && !TARGET_SHARED \
119 && TARGET_EXPLICIT_RELOCS \
120 && !ABI_HAS_64BIT_SYMBOLS)
121
122 /* True if we can optimize sibling calls. For simplicity, we only
123 handle cases in which call_insn_operand will reject invalid
124 sibcall addresses. There are two cases in which this isn't true:
125
126 - TARGET_MIPS16. call_insn_operand accepts constant addresses
127 but there is no direct jump instruction. It isn't worth
128 using sibling calls in this case anyway; they would usually
129 be longer than normal calls.
130
131 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
132 accepts global constants, but all sibcalls must be indirect. */
133 #define TARGET_SIBCALLS \
134 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
135
136 /* True if we need to use a global offset table to access some symbols. */
137 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
138
139 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
140 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
141
142 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
143 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
144
145 /* True if we should use .cprestore to store to the cprestore slot.
146
147 We continue to use .cprestore for explicit-reloc code so that JALs
148 inside inline asms will work correctly. */
149 #define TARGET_CPRESTORE_DIRECTIVE \
150 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
151
152 /* True if we can use the J and JAL instructions. */
153 #define TARGET_ABSOLUTE_JUMPS \
154 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
155
156 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
157 This is true for both the PIC and non-PIC VxWorks RTP modes. */
158 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
159
160 /* True if .gpword or .gpdword should be used for switch tables.
161
162 Although GAS does understand .gpdword, the SGI linker mishandles
163 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
164 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
165 #define TARGET_GPWORD \
166 (TARGET_ABICALLS \
167 && !TARGET_ABSOLUTE_ABICALLS \
168 && !(mips_abi == ABI_64 && TARGET_IRIX6))
169
170 /* True if the output must have a writable .eh_frame.
171 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
172 #ifdef HAVE_LD_PERSONALITY_RELAXATION
173 #define TARGET_WRITABLE_EH_FRAME 0
174 #else
175 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
176 #endif
177
178 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
179 #ifdef HAVE_AS_DSPR1_MULT
180 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
181 #else
182 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
183 #endif
184
185 /* Generate mips16 code */
186 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
187 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
188 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
189 /* Generate mips16e register save/restore sequences. */
190 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
191
192 /* True if we're generating a form of MIPS16 code in which general
193 text loads are allowed. */
194 #define TARGET_MIPS16_TEXT_LOADS \
195 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
196
197 /* True if we're generating a form of MIPS16 code in which PC-relative
198 loads are allowed. */
199 #define TARGET_MIPS16_PCREL_LOADS \
200 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
201
202 /* Generic ISA defines. */
203 #define ISA_MIPS1 (mips_isa == 1)
204 #define ISA_MIPS2 (mips_isa == 2)
205 #define ISA_MIPS3 (mips_isa == 3)
206 #define ISA_MIPS4 (mips_isa == 4)
207 #define ISA_MIPS32 (mips_isa == 32)
208 #define ISA_MIPS32R2 (mips_isa == 33)
209 #define ISA_MIPS64 (mips_isa == 64)
210 #define ISA_MIPS64R2 (mips_isa == 65)
211
212 /* Architecture target defines. */
213 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
214 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
215 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
216 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
217 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
218 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
219 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
220 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
221 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
222 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
223 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
224 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
225 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
226 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
227 || mips_arch == PROCESSOR_SB1A)
228 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
229
230 /* Scheduling target defines. */
231 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
232 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
233 || mips_tune == PROCESSOR_24KF2_1 \
234 || mips_tune == PROCESSOR_24KF1_1)
235 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
236 || mips_tune == PROCESSOR_74KF2_1 \
237 || mips_tune == PROCESSOR_74KF1_1 \
238 || mips_tune == PROCESSOR_74KF3_2)
239 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
240 || mips_tune == PROCESSOR_LOONGSON_2F)
241 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
242 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
243 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
244 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
245 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
246 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
247 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
248 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
249 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
250 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
251 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
252 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
253 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
254 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
255 || mips_tune == PROCESSOR_SB1A)
256
257 /* Whether vector modes and intrinsics for ST Microelectronics
258 Loongson-2E/2F processors should be enabled. In o32 pairs of
259 floating-point registers provide 64-bit values. */
260 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
261 && (TARGET_LOONGSON_2EF \
262 || TARGET_LOONGSON_3A))
263
264 /* True if the pre-reload scheduler should try to create chains of
265 multiply-add or multiply-subtract instructions. For example,
266 suppose we have:
267
268 t1 = a * b
269 t2 = t1 + c * d
270 t3 = e * f
271 t4 = t3 - g * h
272
273 t1 will have a higher priority than t2 and t3 will have a higher
274 priority than t4. However, before reload, there is no dependence
275 between t1 and t3, and they can often have similar priorities.
276 The scheduler will then tend to prefer:
277
278 t1 = a * b
279 t3 = e * f
280 t2 = t1 + c * d
281 t4 = t3 - g * h
282
283 which stops us from making full use of macc/madd-style instructions.
284 This sort of situation occurs frequently in Fourier transforms and
285 in unrolled loops.
286
287 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
288 queue so that chained multiply-add and multiply-subtract instructions
289 appear ahead of any other instruction that is likely to clobber lo.
290 In the example above, if t2 and t3 become ready at the same time,
291 the code ensures that t2 is scheduled first.
292
293 Multiply-accumulate instructions are a bigger win for some targets
294 than others, so this macro is defined on an opt-in basis. */
295 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
296 || TUNE_MIPS4120 \
297 || TUNE_MIPS4130 \
298 || TUNE_24K)
299
300 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
301 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
302
303 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
304 directly accessible, while the command-line options select
305 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
306 in use. */
307 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
308 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
309
310 /* False if SC acts as a memory barrier with respect to itself,
311 otherwise a SYNC will be emitted after SC for atomic operations
312 that require ordering between the SC and following loads and
313 stores. It does not tell anything about ordering of loads and
314 stores prior to and following the SC, only about the SC itself and
315 those loads and stores follow it. */
316 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
317
318 /* IRIX specific stuff. */
319 #define TARGET_IRIX6 0
320
321 /* Define preprocessor macros for the -march and -mtune options.
322 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
323 processor. If INFO's canonical name is "foo", define PREFIX to
324 be "foo", and define an additional macro PREFIX_FOO. */
325 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
326 do \
327 { \
328 char *macro, *p; \
329 \
330 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
331 for (p = macro; *p != 0; p++) \
332 if (*p == '+') \
333 *p = 'P'; \
334 else \
335 *p = TOUPPER (*p); \
336 \
337 builtin_define (macro); \
338 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
339 free (macro); \
340 } \
341 while (0)
342
343 /* Target CPU builtins. */
344 #define TARGET_CPU_CPP_BUILTINS() \
345 do \
346 { \
347 /* Everyone but IRIX defines this to mips. */ \
348 if (!TARGET_IRIX6) \
349 builtin_assert ("machine=mips"); \
350 \
351 builtin_assert ("cpu=mips"); \
352 builtin_define ("__mips__"); \
353 builtin_define ("_mips"); \
354 \
355 /* We do this here because __mips is defined below and so we \
356 can't use builtin_define_std. We don't ever want to define \
357 "mips" for VxWorks because some of the VxWorks headers \
358 construct include filenames from a root directory macro, \
359 an architecture macro and a filename, where the architecture \
360 macro expands to 'mips'. If we define 'mips' to 1, the \
361 architecture macro expands to 1 as well. */ \
362 if (!flag_iso && !TARGET_VXWORKS) \
363 builtin_define ("mips"); \
364 \
365 if (TARGET_64BIT) \
366 builtin_define ("__mips64"); \
367 \
368 if (!TARGET_IRIX6) \
369 { \
370 /* Treat _R3000 and _R4000 like register-size \
371 defines, which is how they've historically \
372 been used. */ \
373 if (TARGET_64BIT) \
374 { \
375 builtin_define_std ("R4000"); \
376 builtin_define ("_R4000"); \
377 } \
378 else \
379 { \
380 builtin_define_std ("R3000"); \
381 builtin_define ("_R3000"); \
382 } \
383 } \
384 if (TARGET_FLOAT64) \
385 builtin_define ("__mips_fpr=64"); \
386 else \
387 builtin_define ("__mips_fpr=32"); \
388 \
389 if (mips_base_mips16) \
390 builtin_define ("__mips16"); \
391 \
392 if (TARGET_MIPS3D) \
393 builtin_define ("__mips3d"); \
394 \
395 if (TARGET_SMARTMIPS) \
396 builtin_define ("__mips_smartmips"); \
397 \
398 if (TARGET_DSP) \
399 { \
400 builtin_define ("__mips_dsp"); \
401 if (TARGET_DSPR2) \
402 { \
403 builtin_define ("__mips_dspr2"); \
404 builtin_define ("__mips_dsp_rev=2"); \
405 } \
406 else \
407 builtin_define ("__mips_dsp_rev=1"); \
408 } \
409 \
410 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
411 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
412 \
413 if (ISA_MIPS1) \
414 { \
415 builtin_define ("__mips=1"); \
416 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
417 } \
418 else if (ISA_MIPS2) \
419 { \
420 builtin_define ("__mips=2"); \
421 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
422 } \
423 else if (ISA_MIPS3) \
424 { \
425 builtin_define ("__mips=3"); \
426 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
427 } \
428 else if (ISA_MIPS4) \
429 { \
430 builtin_define ("__mips=4"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
432 } \
433 else if (ISA_MIPS32) \
434 { \
435 builtin_define ("__mips=32"); \
436 builtin_define ("__mips_isa_rev=1"); \
437 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
438 } \
439 else if (ISA_MIPS32R2) \
440 { \
441 builtin_define ("__mips=32"); \
442 builtin_define ("__mips_isa_rev=2"); \
443 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
444 } \
445 else if (ISA_MIPS64) \
446 { \
447 builtin_define ("__mips=64"); \
448 builtin_define ("__mips_isa_rev=1"); \
449 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
450 } \
451 else if (ISA_MIPS64R2) \
452 { \
453 builtin_define ("__mips=64"); \
454 builtin_define ("__mips_isa_rev=2"); \
455 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
456 } \
457 \
458 switch (mips_abi) \
459 { \
460 case ABI_32: \
461 builtin_define ("_ABIO32=1"); \
462 builtin_define ("_MIPS_SIM=_ABIO32"); \
463 break; \
464 \
465 case ABI_N32: \
466 builtin_define ("_ABIN32=2"); \
467 builtin_define ("_MIPS_SIM=_ABIN32"); \
468 break; \
469 \
470 case ABI_64: \
471 builtin_define ("_ABI64=3"); \
472 builtin_define ("_MIPS_SIM=_ABI64"); \
473 break; \
474 \
475 case ABI_O64: \
476 builtin_define ("_ABIO64=4"); \
477 builtin_define ("_MIPS_SIM=_ABIO64"); \
478 break; \
479 } \
480 \
481 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
482 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
483 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
484 builtin_define_with_int_value ("_MIPS_FPSET", \
485 32 / MAX_FPRS_PER_FMT); \
486 \
487 /* These defines reflect the ABI in use, not whether the \
488 FPU is directly accessible. */ \
489 if (TARGET_NO_FLOAT) \
490 builtin_define ("__mips_no_float"); \
491 else if (TARGET_HARD_FLOAT_ABI) \
492 builtin_define ("__mips_hard_float"); \
493 else \
494 builtin_define ("__mips_soft_float"); \
495 \
496 if (TARGET_SINGLE_FLOAT) \
497 builtin_define ("__mips_single_float"); \
498 \
499 if (TARGET_PAIRED_SINGLE_FLOAT) \
500 builtin_define ("__mips_paired_single_float"); \
501 \
502 if (TARGET_BIG_ENDIAN) \
503 { \
504 builtin_define_std ("MIPSEB"); \
505 builtin_define ("_MIPSEB"); \
506 } \
507 else \
508 { \
509 builtin_define_std ("MIPSEL"); \
510 builtin_define ("_MIPSEL"); \
511 } \
512 \
513 /* Whether calls should go through $25. The separate __PIC__ \
514 macro indicates whether abicalls code might use a GOT. */ \
515 if (TARGET_ABICALLS) \
516 builtin_define ("__mips_abicalls"); \
517 \
518 /* Whether Loongson vector modes are enabled. */ \
519 if (TARGET_LOONGSON_VECTORS) \
520 builtin_define ("__mips_loongson_vector_rev"); \
521 \
522 /* Historical Octeon macro. */ \
523 if (TARGET_OCTEON) \
524 builtin_define ("__OCTEON__"); \
525 \
526 /* Macros dependent on the C dialect. */ \
527 if (preprocessing_asm_p ()) \
528 { \
529 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
530 builtin_define ("_LANGUAGE_ASSEMBLY"); \
531 } \
532 else if (c_dialect_cxx ()) \
533 { \
534 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
535 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
536 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
537 } \
538 else \
539 { \
540 builtin_define_std ("LANGUAGE_C"); \
541 builtin_define ("_LANGUAGE_C"); \
542 } \
543 if (c_dialect_objc ()) \
544 { \
545 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
546 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
547 /* Bizarre, but needed at least for Irix. */ \
548 builtin_define_std ("LANGUAGE_C"); \
549 builtin_define ("_LANGUAGE_C"); \
550 } \
551 \
552 if (mips_abi == ABI_EABI) \
553 builtin_define ("__mips_eabi"); \
554 \
555 if (TARGET_CACHE_BUILTIN) \
556 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
557 } \
558 while (0)
559
560 /* Default target_flags if no switches are specified */
561
562 #ifndef TARGET_DEFAULT
563 #define TARGET_DEFAULT 0
564 #endif
565
566 #ifndef TARGET_CPU_DEFAULT
567 #define TARGET_CPU_DEFAULT 0
568 #endif
569
570 #ifndef TARGET_ENDIAN_DEFAULT
571 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
572 #endif
573
574 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
575 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
576 #endif
577
578 #ifdef IN_LIBGCC2
579 #undef TARGET_64BIT
580 /* Make this compile time constant for libgcc2 */
581 #ifdef __mips64
582 #define TARGET_64BIT 1
583 #else
584 #define TARGET_64BIT 0
585 #endif
586 #endif /* IN_LIBGCC2 */
587
588 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
589 when compiled with hardware floating point. This is because MIPS16
590 code cannot save and restore the floating-point registers, which is
591 important if in a mixed MIPS16/non-MIPS16 environment. */
592
593 #ifdef IN_LIBGCC2
594 #if __mips_hard_float
595 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
596 #endif
597 #endif /* IN_LIBGCC2 */
598
599 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
600
601 #ifndef MULTILIB_ENDIAN_DEFAULT
602 #if TARGET_ENDIAN_DEFAULT == 0
603 #define MULTILIB_ENDIAN_DEFAULT "EL"
604 #else
605 #define MULTILIB_ENDIAN_DEFAULT "EB"
606 #endif
607 #endif
608
609 #ifndef MULTILIB_ISA_DEFAULT
610 # if MIPS_ISA_DEFAULT == 1
611 # define MULTILIB_ISA_DEFAULT "mips1"
612 # else
613 # if MIPS_ISA_DEFAULT == 2
614 # define MULTILIB_ISA_DEFAULT "mips2"
615 # else
616 # if MIPS_ISA_DEFAULT == 3
617 # define MULTILIB_ISA_DEFAULT "mips3"
618 # else
619 # if MIPS_ISA_DEFAULT == 4
620 # define MULTILIB_ISA_DEFAULT "mips4"
621 # else
622 # if MIPS_ISA_DEFAULT == 32
623 # define MULTILIB_ISA_DEFAULT "mips32"
624 # else
625 # if MIPS_ISA_DEFAULT == 33
626 # define MULTILIB_ISA_DEFAULT "mips32r2"
627 # else
628 # if MIPS_ISA_DEFAULT == 64
629 # define MULTILIB_ISA_DEFAULT "mips64"
630 # else
631 # if MIPS_ISA_DEFAULT == 65
632 # define MULTILIB_ISA_DEFAULT "mips64r2"
633 # else
634 # define MULTILIB_ISA_DEFAULT "mips1"
635 # endif
636 # endif
637 # endif
638 # endif
639 # endif
640 # endif
641 # endif
642 # endif
643 #endif
644
645 #ifndef MIPS_ABI_DEFAULT
646 #define MIPS_ABI_DEFAULT ABI_32
647 #endif
648
649 /* Use the most portable ABI flag for the ASM specs. */
650
651 #if MIPS_ABI_DEFAULT == ABI_32
652 #define MULTILIB_ABI_DEFAULT "mabi=32"
653 #endif
654
655 #if MIPS_ABI_DEFAULT == ABI_O64
656 #define MULTILIB_ABI_DEFAULT "mabi=o64"
657 #endif
658
659 #if MIPS_ABI_DEFAULT == ABI_N32
660 #define MULTILIB_ABI_DEFAULT "mabi=n32"
661 #endif
662
663 #if MIPS_ABI_DEFAULT == ABI_64
664 #define MULTILIB_ABI_DEFAULT "mabi=64"
665 #endif
666
667 #if MIPS_ABI_DEFAULT == ABI_EABI
668 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
669 #endif
670
671 #ifndef MULTILIB_DEFAULTS
672 #define MULTILIB_DEFAULTS \
673 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
674 #endif
675
676 /* We must pass -EL to the linker by default for little endian embedded
677 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
678 linker will default to using big-endian output files. The OUTPUT_FORMAT
679 line must be in the linker script, otherwise -EB/-EL will not work. */
680
681 #ifndef ENDIAN_SPEC
682 #if TARGET_ENDIAN_DEFAULT == 0
683 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
684 #else
685 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
686 #endif
687 #endif
688
689 /* A spec condition that matches all non-mips16 -mips arguments. */
690
691 #define MIPS_ISA_LEVEL_OPTION_SPEC \
692 "mips1|mips2|mips3|mips4|mips32*|mips64*"
693
694 /* A spec condition that matches all non-mips16 architecture arguments. */
695
696 #define MIPS_ARCH_OPTION_SPEC \
697 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
698
699 /* A spec that infers a -mips argument from an -march argument,
700 or injects the default if no architecture is specified. */
701
702 #define MIPS_ISA_LEVEL_SPEC \
703 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
704 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
705 %{march=mips2|march=r6000:-mips2} \
706 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
707 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
708 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
709 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
710 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
711 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
712 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
713 |march=xlr|march=loongson3a: -mips64} \
714 %{march=mips64r2|march=octeon: -mips64r2} \
715 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
716
717 /* A spec that infers a -mhard-float or -msoft-float setting from an
718 -march argument. Note that soft-float and hard-float code are not
719 link-compatible. */
720
721 #define MIPS_ARCH_FLOAT_SPEC \
722 "%{mhard-float|msoft-float|march=mips*:; \
723 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
724 |march=34kc|march=74kc|march=1004kc|march=5kc \
725 |march=octeon|march=xlr: -msoft-float; \
726 march=*: -mhard-float}"
727
728 /* A spec condition that matches 32-bit options. It only works if
729 MIPS_ISA_LEVEL_SPEC has been applied. */
730
731 #define MIPS_32BIT_OPTION_SPEC \
732 "mips1|mips2|mips32*|mgp32"
733
734 #if MIPS_ABI_DEFAULT == ABI_O64 \
735 || MIPS_ABI_DEFAULT == ABI_N32 \
736 || MIPS_ABI_DEFAULT == ABI_64
737 #define OPT_ARCH64 "mabi=32|mgp32:;"
738 #define OPT_ARCH32 "mabi=32|mgp32"
739 #else
740 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
741 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
742 #endif
743
744 /* Support for a compile-time default CPU, et cetera. The rules are:
745 --with-arch is ignored if -march is specified or a -mips is specified
746 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
747 --with-tune is ignored if -mtune is specified; likewise
748 --with-tune-32 and --with-tune-64.
749 --with-abi is ignored if -mabi is specified.
750 --with-float is ignored if -mhard-float or -msoft-float are
751 specified.
752 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
753 specified. */
754 #define OPTION_DEFAULT_SPECS \
755 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
756 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
757 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
758 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
759 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
760 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
761 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
762 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
763 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
764 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
765 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
766 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
767
768
769 /* A spec that infers the -mdsp setting from an -march argument. */
770 #define BASE_DRIVER_SELF_SPECS \
771 "%{!mno-dsp: \
772 %{march=24ke*|march=34k*|march=1004k*: -mdsp} \
773 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
774
775 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
776
777 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
778 && ISA_HAS_COND_TRAP)
779
780 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
781
782 /* True if the ABI can only work with 64-bit integer registers. We
783 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
784 otherwise floating-point registers must also be 64-bit. */
785 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
786
787 /* Likewise for 32-bit regs. */
788 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
789
790 /* True if the file format uses 64-bit symbols. At present, this is
791 only true for n64, which uses 64-bit ELF. */
792 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
793
794 /* True if symbols are 64 bits wide. This is usually determined by
795 the ABI's file format, but it can be overridden by -msym32. Note that
796 overriding the size with -msym32 changes the ABI of relocatable objects,
797 although it doesn't change the ABI of a fully-linked object. */
798 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
799 && Pmode == DImode \
800 && !TARGET_SYM32)
801
802 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
803 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
804 || ISA_MIPS4 \
805 || ISA_MIPS64 \
806 || ISA_MIPS64R2)
807
808 /* ISA has branch likely instructions (e.g. mips2). */
809 /* Disable branchlikely for tx39 until compare rewrite. They haven't
810 been generated up to this point. */
811 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
812
813 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
814 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
815 || TARGET_MIPS5400 \
816 || TARGET_MIPS5500 \
817 || TARGET_MIPS7000 \
818 || TARGET_MIPS9000 \
819 || TARGET_MAD \
820 || ISA_MIPS32 \
821 || ISA_MIPS32R2 \
822 || ISA_MIPS64 \
823 || ISA_MIPS64R2) \
824 && !TARGET_MIPS16)
825
826 /* ISA has a three-operand multiplication instruction. */
827 #define ISA_HAS_DMUL3 (TARGET_64BIT \
828 && TARGET_OCTEON \
829 && !TARGET_MIPS16)
830
831 /* ISA has the floating-point conditional move instructions introduced
832 in mips4. */
833 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
834 || ISA_MIPS32 \
835 || ISA_MIPS32R2 \
836 || ISA_MIPS64 \
837 || ISA_MIPS64R2) \
838 && !TARGET_MIPS5500 \
839 && !TARGET_MIPS16)
840
841 /* ISA has the integer conditional move instructions introduced in mips4 and
842 ST Loongson 2E/2F. */
843 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
844
845 /* ISA has LDC1 and SDC1. */
846 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
847
848 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
849 branch on CC, and move (both FP and non-FP) on CC. */
850 #define ISA_HAS_8CC (ISA_MIPS4 \
851 || ISA_MIPS32 \
852 || ISA_MIPS32R2 \
853 || ISA_MIPS64 \
854 || ISA_MIPS64R2)
855
856 /* This is a catch all for other mips4 instructions: indexed load, the
857 FP madd and msub instructions, and the FP recip and recip sqrt
858 instructions. */
859 #define ISA_HAS_FP4 ((ISA_MIPS4 \
860 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
861 || ISA_MIPS64 \
862 || ISA_MIPS64R2) \
863 && !TARGET_MIPS16)
864
865 /* ISA has paired-single instructions. */
866 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
867
868 /* ISA has conditional trap instructions. */
869 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
870 && !TARGET_MIPS16)
871
872 /* ISA has integer multiply-accumulate instructions, madd and msub. */
873 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
874 || ISA_MIPS32R2 \
875 || ISA_MIPS64 \
876 || ISA_MIPS64R2) \
877 && !TARGET_MIPS16)
878
879 /* Integer multiply-accumulate instructions should be generated. */
880 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
881
882 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
883 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
884
885 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
886 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
887
888 /* ISA has floating-point nmadd and nmsub instructions
889 'd = -((a * b) [+-] c)'. */
890 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
891 ((ISA_MIPS4 \
892 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
893 || ISA_MIPS64 \
894 || ISA_MIPS64R2) \
895 && (!TARGET_MIPS5400 || TARGET_MAD) \
896 && !TARGET_MIPS16)
897
898 /* ISA has floating-point nmadd and nmsub instructions
899 'c = -((a * b) [+-] c)'. */
900 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
901 TARGET_LOONGSON_2EF
902
903 /* ISA has count leading zeroes/ones instruction (not implemented). */
904 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
905 || ISA_MIPS32R2 \
906 || ISA_MIPS64 \
907 || ISA_MIPS64R2) \
908 && !TARGET_MIPS16)
909
910 /* ISA has three operand multiply instructions that put
911 the high part in an accumulator: mulhi or mulhiu. */
912 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
913 || TARGET_MIPS5500 \
914 || TARGET_SR71K) \
915 && !TARGET_MIPS16)
916
917 /* ISA has three operand multiply instructions that
918 negates the result and puts the result in an accumulator. */
919 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
920 || TARGET_MIPS5500 \
921 || TARGET_SR71K) \
922 && !TARGET_MIPS16)
923
924 /* ISA has three operand multiply instructions that subtracts the
925 result from a 4th operand and puts the result in an accumulator. */
926 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
927 || TARGET_MIPS5500 \
928 || TARGET_SR71K) \
929 && !TARGET_MIPS16)
930
931 /* ISA has three operand multiply instructions that the result
932 from a 4th operand and puts the result in an accumulator. */
933 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
934 || TARGET_MIPS4130 \
935 || TARGET_MIPS5400 \
936 || TARGET_MIPS5500 \
937 || TARGET_SR71K) \
938 && !TARGET_MIPS16)
939
940 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
941 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
942 || TARGET_MIPS4130) \
943 && !TARGET_MIPS16)
944
945 /* ISA has the "ror" (rotate right) instructions. */
946 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
947 || ISA_MIPS64R2 \
948 || TARGET_MIPS5400 \
949 || TARGET_MIPS5500 \
950 || TARGET_SR71K \
951 || TARGET_SMARTMIPS) \
952 && !TARGET_MIPS16)
953
954 /* ISA has data prefetch instructions. This controls use of 'pref'. */
955 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
956 || TARGET_LOONGSON_2EF \
957 || ISA_MIPS32 \
958 || ISA_MIPS32R2 \
959 || ISA_MIPS64 \
960 || ISA_MIPS64R2) \
961 && !TARGET_MIPS16)
962
963 /* ISA has data indexed prefetch instructions. This controls use of
964 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
965 (prefx is a cop1x instruction, so can only be used if FP is
966 enabled.) */
967 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
968 || ISA_MIPS32R2 \
969 || ISA_MIPS64 \
970 || ISA_MIPS64R2) \
971 && !TARGET_MIPS16)
972
973 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
974 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
975 also requires TARGET_DOUBLE_FLOAT. */
976 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
977
978 /* ISA includes the MIPS32r2 seb and seh instructions. */
979 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
980 || ISA_MIPS64R2) \
981 && !TARGET_MIPS16)
982
983 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
984 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
985 || ISA_MIPS64R2) \
986 && !TARGET_MIPS16)
987
988 /* ISA has instructions for accessing top part of 64-bit fp regs. */
989 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
990 && (ISA_MIPS32R2 \
991 || ISA_MIPS64R2))
992
993 /* ISA has lwxs instruction (load w/scaled index address. */
994 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
995
996 /* The DSP ASE is available. */
997 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
998
999 /* Revision 2 of the DSP ASE is available. */
1000 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1001
1002 /* True if the result of a load is not available to the next instruction.
1003 A nop will then be needed between instructions like "lw $4,..."
1004 and "addiu $4,$4,1". */
1005 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1006 && !TARGET_MIPS3900 \
1007 && !TARGET_MIPS16)
1008
1009 /* Likewise mtc1 and mfc1. */
1010 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1011 && !TARGET_LOONGSON_2EF)
1012
1013 /* Likewise floating-point comparisons. */
1014 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1015 && !TARGET_LOONGSON_2EF)
1016
1017 /* True if mflo and mfhi can be immediately followed by instructions
1018 which write to the HI and LO registers.
1019
1020 According to MIPS specifications, MIPS ISAs I, II, and III need
1021 (at least) two instructions between the reads of HI/LO and
1022 instructions which write them, and later ISAs do not. Contradicting
1023 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1024 the UM for the NEC Vr5000) document needing the instructions between
1025 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1026 MIPS64 and later ISAs to have the interlocks, plus any specific
1027 earlier-ISA CPUs for which CPU documentation declares that the
1028 instructions are really interlocked. */
1029 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1030 || ISA_MIPS32R2 \
1031 || ISA_MIPS64 \
1032 || ISA_MIPS64R2 \
1033 || TARGET_MIPS5500 \
1034 || TARGET_LOONGSON_2EF)
1035
1036 /* ISA includes synci, jr.hb and jalr.hb. */
1037 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1038 || ISA_MIPS64R2) \
1039 && !TARGET_MIPS16)
1040
1041 /* ISA includes sync. */
1042 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1043 #define GENERATE_SYNC \
1044 (target_flags_explicit & MASK_LLSC \
1045 ? TARGET_LLSC && !TARGET_MIPS16 \
1046 : ISA_HAS_SYNC)
1047
1048 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1049 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1050 instructions. */
1051 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1052 #define GENERATE_LL_SC \
1053 (target_flags_explicit & MASK_LLSC \
1054 ? TARGET_LLSC && !TARGET_MIPS16 \
1055 : ISA_HAS_LL_SC)
1056
1057 /* ISA includes the baddu instruction. */
1058 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1059
1060 /* ISA includes the bbit* instructions. */
1061 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1062
1063 /* ISA includes the cins instruction. */
1064 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1065
1066 /* ISA includes the exts instruction. */
1067 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1068
1069 /* ISA includes the seq and sne instructions. */
1070 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1071
1072 /* ISA includes the pop instruction. */
1073 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1074
1075 /* The CACHE instruction is available in non-MIPS16 code. */
1076 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1077
1078 /* The CACHE instruction is available. */
1079 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1080 \f
1081 /* Tell collect what flags to pass to nm. */
1082 #ifndef NM_FLAGS
1083 #define NM_FLAGS "-Bn"
1084 #endif
1085
1086 \f
1087 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1088 the assembler. It may be overridden by subtargets.
1089
1090 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1091 COFF debugging info. */
1092
1093 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1094 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1095 %{g} %{g0} %{g1} %{g2} %{g3} \
1096 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1097 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1098 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1099 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1100 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1101 #endif
1102
1103 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1104 overridden by subtargets. */
1105
1106 #ifndef SUBTARGET_ASM_SPEC
1107 #define SUBTARGET_ASM_SPEC ""
1108 #endif
1109
1110 #undef ASM_SPEC
1111 #define ASM_SPEC "\
1112 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1113 %{mips32*} %{mips64*} \
1114 %{mips16} %{mno-mips16:-no-mips16} \
1115 %{mips3d} %{mno-mips3d:-no-mips3d} \
1116 %{mdmx} %{mno-mdmx:-no-mdmx} \
1117 %{mdsp} %{mno-dsp} \
1118 %{mdspr2} %{mno-dspr2} \
1119 %{msmartmips} %{mno-smartmips} \
1120 %{mmt} %{mno-mt} \
1121 %{mfix-vr4120} %{mfix-vr4130} \
1122 %{mfix-24k} \
1123 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1124 %(subtarget_asm_debugging_spec) \
1125 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1126 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1127 %{mfp32} %{mfp64} \
1128 %{mshared} %{mno-shared} \
1129 %{msym32} %{mno-sym32} \
1130 %{mtune=*} \
1131 %(subtarget_asm_spec)"
1132
1133 /* Extra switches sometimes passed to the linker. */
1134
1135 #ifndef LINK_SPEC
1136 #define LINK_SPEC "\
1137 %(endian_spec) \
1138 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1139 %{shared}"
1140 #endif /* LINK_SPEC defined */
1141
1142
1143 /* Specs for the compiler proper */
1144
1145 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1146 overridden by subtargets. */
1147 #ifndef SUBTARGET_CC1_SPEC
1148 #define SUBTARGET_CC1_SPEC ""
1149 #endif
1150
1151 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1152
1153 #undef CC1_SPEC
1154 #define CC1_SPEC "\
1155 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1156 %(subtarget_cc1_spec)"
1157
1158 /* Preprocessor specs. */
1159
1160 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1161 overridden by subtargets. */
1162 #ifndef SUBTARGET_CPP_SPEC
1163 #define SUBTARGET_CPP_SPEC ""
1164 #endif
1165
1166 #define CPP_SPEC "%(subtarget_cpp_spec)"
1167
1168 /* This macro defines names of additional specifications to put in the specs
1169 that can be used in various specifications like CC1_SPEC. Its definition
1170 is an initializer with a subgrouping for each command option.
1171
1172 Each subgrouping contains a string constant, that defines the
1173 specification name, and a string constant that used by the GCC driver
1174 program.
1175
1176 Do not define this macro if it does not need to do anything. */
1177
1178 #define EXTRA_SPECS \
1179 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1180 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1181 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1182 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1183 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1184 { "endian_spec", ENDIAN_SPEC }, \
1185 SUBTARGET_EXTRA_SPECS
1186
1187 #ifndef SUBTARGET_EXTRA_SPECS
1188 #define SUBTARGET_EXTRA_SPECS
1189 #endif
1190 \f
1191 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1192 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1193
1194 #ifndef PREFERRED_DEBUGGING_TYPE
1195 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1196 #endif
1197
1198 /* The size of DWARF addresses should be the same as the size of symbols
1199 in the target file format. They shouldn't depend on things like -msym32,
1200 because many DWARF consumers do not allow the mixture of address sizes
1201 that one would then get from linking -msym32 code with -msym64 code.
1202
1203 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1204 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1205 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1206
1207 /* By default, turn on GDB extensions. */
1208 #define DEFAULT_GDB_EXTENSIONS 1
1209
1210 /* Local compiler-generated symbols must have a prefix that the assembler
1211 understands. By default, this is $, although some targets (e.g.,
1212 NetBSD-ELF) need to override this. */
1213
1214 #ifndef LOCAL_LABEL_PREFIX
1215 #define LOCAL_LABEL_PREFIX "$"
1216 #endif
1217
1218 /* By default on the mips, external symbols do not have an underscore
1219 prepended, but some targets (e.g., NetBSD) require this. */
1220
1221 #ifndef USER_LABEL_PREFIX
1222 #define USER_LABEL_PREFIX ""
1223 #endif
1224
1225 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1226 since the length can run past this up to a continuation point. */
1227 #undef DBX_CONTIN_LENGTH
1228 #define DBX_CONTIN_LENGTH 1500
1229
1230 /* How to renumber registers for dbx and gdb. */
1231 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1232
1233 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1234 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1235
1236 /* The DWARF 2 CFA column which tracks the return address. */
1237 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1238
1239 /* Before the prologue, RA lives in r31. */
1240 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1241
1242 /* Describe how we implement __builtin_eh_return. */
1243 #define EH_RETURN_DATA_REGNO(N) \
1244 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1245
1246 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1247
1248 #define EH_USES(N) mips_eh_uses (N)
1249
1250 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1251 The default for this in 64-bit mode is 8, which causes problems with
1252 SFmode register saves. */
1253 #define DWARF_CIE_DATA_ALIGNMENT -4
1254
1255 /* Correct the offset of automatic variables and arguments. Note that
1256 the MIPS debug format wants all automatic variables and arguments
1257 to be in terms of the virtual frame pointer (stack pointer before
1258 any adjustment in the function), while the MIPS 3.0 linker wants
1259 the frame pointer to be the stack pointer after the initial
1260 adjustment. */
1261
1262 #define DEBUGGER_AUTO_OFFSET(X) \
1263 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1264 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1265 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1266 \f
1267 /* Target machine storage layout */
1268
1269 #define BITS_BIG_ENDIAN 0
1270 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1271 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1272
1273 #define MAX_BITS_PER_WORD 64
1274
1275 /* Width of a word, in units (bytes). */
1276 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1277 #ifndef IN_LIBGCC2
1278 #define MIN_UNITS_PER_WORD 4
1279 #endif
1280
1281 /* For MIPS, width of a floating point register. */
1282 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1283
1284 /* The number of consecutive floating-point registers needed to store the
1285 largest format supported by the FPU. */
1286 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1287
1288 /* The number of consecutive floating-point registers needed to store the
1289 smallest format supported by the FPU. */
1290 #define MIN_FPRS_PER_FMT \
1291 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1292 ? 1 : MAX_FPRS_PER_FMT)
1293
1294 /* The largest size of value that can be held in floating-point
1295 registers and moved with a single instruction. */
1296 #define UNITS_PER_HWFPVALUE \
1297 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1298
1299 /* The largest size of value that can be held in floating-point
1300 registers. */
1301 #define UNITS_PER_FPVALUE \
1302 (TARGET_SOFT_FLOAT_ABI ? 0 \
1303 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1304 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1305
1306 /* The number of bytes in a double. */
1307 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1308
1309 /* Set the sizes of the core types. */
1310 #define SHORT_TYPE_SIZE 16
1311 #define INT_TYPE_SIZE 32
1312 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1313 #define LONG_LONG_TYPE_SIZE 64
1314
1315 #define FLOAT_TYPE_SIZE 32
1316 #define DOUBLE_TYPE_SIZE 64
1317 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1318
1319 /* Define the sizes of fixed-point types. */
1320 #define SHORT_FRACT_TYPE_SIZE 8
1321 #define FRACT_TYPE_SIZE 16
1322 #define LONG_FRACT_TYPE_SIZE 32
1323 #define LONG_LONG_FRACT_TYPE_SIZE 64
1324
1325 #define SHORT_ACCUM_TYPE_SIZE 16
1326 #define ACCUM_TYPE_SIZE 32
1327 #define LONG_ACCUM_TYPE_SIZE 64
1328 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1329 doesn't support 128-bit integers for MIPS32 currently. */
1330 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1331
1332 /* long double is not a fixed mode, but the idea is that, if we
1333 support long double, we also want a 128-bit integer type. */
1334 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1335
1336 #ifdef IN_LIBGCC2
1337 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1338 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1339 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1340 # else
1341 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1342 # endif
1343 #endif
1344
1345 /* Width in bits of a pointer. */
1346 #ifndef POINTER_SIZE
1347 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1348 #endif
1349
1350 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1351 #define PARM_BOUNDARY BITS_PER_WORD
1352
1353 /* Allocation boundary (in *bits*) for the code of a function. */
1354 #define FUNCTION_BOUNDARY 32
1355
1356 /* Alignment of field after `int : 0' in a structure. */
1357 #define EMPTY_FIELD_BOUNDARY 32
1358
1359 /* Every structure's size must be a multiple of this. */
1360 /* 8 is observed right on a DECstation and on riscos 4.02. */
1361 #define STRUCTURE_SIZE_BOUNDARY 8
1362
1363 /* There is no point aligning anything to a rounder boundary than this. */
1364 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1365
1366 /* All accesses must be aligned. */
1367 #define STRICT_ALIGNMENT 1
1368
1369 /* Define this if you wish to imitate the way many other C compilers
1370 handle alignment of bitfields and the structures that contain
1371 them.
1372
1373 The behavior is that the type written for a bit-field (`int',
1374 `short', or other integer type) imposes an alignment for the
1375 entire structure, as if the structure really did contain an
1376 ordinary field of that type. In addition, the bit-field is placed
1377 within the structure so that it would fit within such a field,
1378 not crossing a boundary for it.
1379
1380 Thus, on most machines, a bit-field whose type is written as `int'
1381 would not cross a four-byte boundary, and would force four-byte
1382 alignment for the whole structure. (The alignment used may not
1383 be four bytes; it is controlled by the other alignment
1384 parameters.)
1385
1386 If the macro is defined, its definition should be a C expression;
1387 a nonzero value for the expression enables this behavior. */
1388
1389 #define PCC_BITFIELD_TYPE_MATTERS 1
1390
1391 /* If defined, a C expression to compute the alignment given to a
1392 constant that is being placed in memory. CONSTANT is the constant
1393 and ALIGN is the alignment that the object would ordinarily have.
1394 The value of this macro is used instead of that alignment to align
1395 the object.
1396
1397 If this macro is not defined, then ALIGN is used.
1398
1399 The typical use of this macro is to increase alignment for string
1400 constants to be word aligned so that `strcpy' calls that copy
1401 constants can be done inline. */
1402
1403 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1404 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1405 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1406
1407 /* If defined, a C expression to compute the alignment for a static
1408 variable. TYPE is the data type, and ALIGN is the alignment that
1409 the object would ordinarily have. The value of this macro is used
1410 instead of that alignment to align the object.
1411
1412 If this macro is not defined, then ALIGN is used.
1413
1414 One use of this macro is to increase alignment of medium-size
1415 data to make it all fit in fewer cache lines. Another is to
1416 cause character arrays to be word-aligned so that `strcpy' calls
1417 that copy constants to character arrays can be done inline. */
1418
1419 #undef DATA_ALIGNMENT
1420 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1421 ((((ALIGN) < BITS_PER_WORD) \
1422 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1423 || TREE_CODE (TYPE) == UNION_TYPE \
1424 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1425
1426 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1427 character arrays to be word-aligned so that `strcpy' calls that copy
1428 constants to character arrays can be done inline, and 'strcmp' can be
1429 optimised to use word loads. */
1430 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1431 DATA_ALIGNMENT (TYPE, ALIGN)
1432
1433 #define PAD_VARARGS_DOWN \
1434 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1435
1436 /* Define if operations between registers always perform the operation
1437 on the full register even if a narrower mode is specified. */
1438 #define WORD_REGISTER_OPERATIONS
1439
1440 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1441 moves. All other references are zero extended. */
1442 #define LOAD_EXTEND_OP(MODE) \
1443 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1444 ? SIGN_EXTEND : ZERO_EXTEND)
1445
1446 /* Define this macro if it is advisable to hold scalars in registers
1447 in a wider mode than that declared by the program. In such cases,
1448 the value is constrained to be within the bounds of the declared
1449 type, but kept valid in the wider mode. The signedness of the
1450 extension may differ from that of the type. */
1451
1452 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1453 if (GET_MODE_CLASS (MODE) == MODE_INT \
1454 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1455 { \
1456 if ((MODE) == SImode) \
1457 (UNSIGNEDP) = 0; \
1458 (MODE) = Pmode; \
1459 }
1460
1461 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1462 Extensions of pointers to word_mode must be signed. */
1463 #define POINTERS_EXTEND_UNSIGNED false
1464
1465 /* Define if loading short immediate values into registers sign extends. */
1466 #define SHORT_IMMEDIATES_SIGN_EXTEND
1467
1468 /* The [d]clz instructions have the natural values at 0. */
1469
1470 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1471 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1472 \f
1473 /* Standard register usage. */
1474
1475 /* Number of hardware registers. We have:
1476
1477 - 32 integer registers
1478 - 32 floating point registers
1479 - 8 condition code registers
1480 - 2 accumulator registers (hi and lo)
1481 - 32 registers each for coprocessors 0, 2 and 3
1482 - 4 fake registers:
1483 - ARG_POINTER_REGNUM
1484 - FRAME_POINTER_REGNUM
1485 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1486 - CPRESTORE_SLOT_REGNUM
1487 - 2 dummy entries that were used at various times in the past.
1488 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1489 - 6 DSP control registers */
1490
1491 #define FIRST_PSEUDO_REGISTER 188
1492
1493 /* By default, fix the kernel registers ($26 and $27), the global
1494 pointer ($28) and the stack pointer ($29). This can change
1495 depending on the command-line options.
1496
1497 Regarding coprocessor registers: without evidence to the contrary,
1498 it's best to assume that each coprocessor register has a unique
1499 use. This can be overridden, in, e.g., mips_option_override or
1500 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1501 inappropriate for a particular target. */
1502
1503 #define FIXED_REGISTERS \
1504 { \
1505 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1506 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1507 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1508 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1509 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1510 /* COP0 registers */ \
1511 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1512 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1513 /* COP2 registers */ \
1514 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1515 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1516 /* COP3 registers */ \
1517 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1518 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1519 /* 6 DSP accumulator registers & 6 control registers */ \
1520 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1521 }
1522
1523
1524 /* Set up this array for o32 by default.
1525
1526 Note that we don't mark $31 as a call-clobbered register. The idea is
1527 that it's really the call instructions themselves which clobber $31.
1528 We don't care what the called function does with it afterwards.
1529
1530 This approach makes it easier to implement sibcalls. Unlike normal
1531 calls, sibcalls don't clobber $31, so the register reaches the
1532 called function in tact. EPILOGUE_USES says that $31 is useful
1533 to the called function. */
1534
1535 #define CALL_USED_REGISTERS \
1536 { \
1537 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1538 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1539 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1540 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1541 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1542 /* COP0 registers */ \
1543 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1544 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1545 /* COP2 registers */ \
1546 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1547 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1548 /* COP3 registers */ \
1549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1551 /* 6 DSP accumulator registers & 6 control registers */ \
1552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1553 }
1554
1555
1556 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1557
1558 #define CALL_REALLY_USED_REGISTERS \
1559 { /* General registers. */ \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1561 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1562 /* Floating-point registers. */ \
1563 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1564 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1565 /* Others. */ \
1566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1567 /* COP0 registers */ \
1568 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1569 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1570 /* COP2 registers */ \
1571 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1572 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1573 /* COP3 registers */ \
1574 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1575 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1576 /* 6 DSP accumulator registers & 6 control registers */ \
1577 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1578 }
1579
1580 /* Internal macros to classify a register number as to whether it's a
1581 general purpose register, a floating point register, a
1582 multiply/divide register, or a status register. */
1583
1584 #define GP_REG_FIRST 0
1585 #define GP_REG_LAST 31
1586 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1587 #define GP_DBX_FIRST 0
1588 #define K0_REG_NUM (GP_REG_FIRST + 26)
1589 #define K1_REG_NUM (GP_REG_FIRST + 27)
1590 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1591
1592 #define FP_REG_FIRST 32
1593 #define FP_REG_LAST 63
1594 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1595 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1596
1597 #define MD_REG_FIRST 64
1598 #define MD_REG_LAST 65
1599 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1600 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1601
1602 /* The DWARF 2 CFA column which tracks the return address from a
1603 signal handler context. This means that to maintain backwards
1604 compatibility, no hard register can be assigned this column if it
1605 would need to be handled by the DWARF unwinder. */
1606 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1607
1608 #define ST_REG_FIRST 67
1609 #define ST_REG_LAST 74
1610 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1611
1612
1613 /* FIXME: renumber. */
1614 #define COP0_REG_FIRST 80
1615 #define COP0_REG_LAST 111
1616 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1617
1618 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1619 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1620 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1621
1622 #define COP2_REG_FIRST 112
1623 #define COP2_REG_LAST 143
1624 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1625
1626 #define COP3_REG_FIRST 144
1627 #define COP3_REG_LAST 175
1628 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1629 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1630 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1631
1632 #define DSP_ACC_REG_FIRST 176
1633 #define DSP_ACC_REG_LAST 181
1634 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1635
1636 #define AT_REGNUM (GP_REG_FIRST + 1)
1637 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1638 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1639
1640 /* A few bitfield locations for the coprocessor registers. */
1641 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1642 the cause register for the EIC interrupt mode. */
1643 #define CAUSE_IPL 10
1644 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1645 #define SR_IPL 10
1646 /* Exception Level is at bit 1 of the status register. */
1647 #define SR_EXL 1
1648 /* Interrupt Enable is at bit 0 of the status register. */
1649 #define SR_IE 0
1650
1651 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1652 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1653 should be used instead. */
1654 #define FPSW_REGNUM ST_REG_FIRST
1655
1656 #define GP_REG_P(REGNO) \
1657 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1658 #define M16_REG_P(REGNO) \
1659 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1660 #define FP_REG_P(REGNO) \
1661 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1662 #define MD_REG_P(REGNO) \
1663 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1664 #define ST_REG_P(REGNO) \
1665 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1666 #define COP0_REG_P(REGNO) \
1667 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1668 #define COP2_REG_P(REGNO) \
1669 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1670 #define COP3_REG_P(REGNO) \
1671 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1672 #define ALL_COP_REG_P(REGNO) \
1673 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1674 /* Test if REGNO is one of the 6 new DSP accumulators. */
1675 #define DSP_ACC_REG_P(REGNO) \
1676 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1677 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1678 #define ACC_REG_P(REGNO) \
1679 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1680
1681 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1682
1683 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1684 to initialize the mips16 gp pseudo register. */
1685 #define CONST_GP_P(X) \
1686 (GET_CODE (X) == CONST \
1687 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1688 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1689
1690 /* Return coprocessor number from register number. */
1691
1692 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1693 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1694 : COP3_REG_P (REGNO) ? '3' : '?')
1695
1696
1697 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1698
1699 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1700 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1701
1702 #define MODES_TIEABLE_P mips_modes_tieable_p
1703
1704 /* Register to use for pushing function arguments. */
1705 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1706
1707 /* These two registers don't really exist: they get eliminated to either
1708 the stack or hard frame pointer. */
1709 #define ARG_POINTER_REGNUM 77
1710 #define FRAME_POINTER_REGNUM 78
1711
1712 /* $30 is not available on the mips16, so we use $17 as the frame
1713 pointer. */
1714 #define HARD_FRAME_POINTER_REGNUM \
1715 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1716
1717 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1718 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1719
1720 /* Register in which static-chain is passed to a function. */
1721 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1722
1723 /* Registers used as temporaries in prologue/epilogue code:
1724
1725 - If a MIPS16 PIC function needs access to _gp, it first loads
1726 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1727
1728 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1729 register. The register must not conflict with MIPS16_PIC_TEMP.
1730
1731 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1732 register.
1733
1734 If we're generating MIPS16 code, these registers must come from the
1735 core set of 8. The prologue registers mustn't conflict with any
1736 incoming arguments, the static chain pointer, or the frame pointer.
1737 The epilogue temporary mustn't conflict with the return registers,
1738 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1739 or the EH data registers.
1740
1741 If we're generating interrupt handlers, we use K0 as a temporary register
1742 in prologue/epilogue code. */
1743
1744 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1745 #define MIPS_PROLOGUE_TEMP_REGNUM \
1746 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1747 #define MIPS_EPILOGUE_TEMP_REGNUM \
1748 (cfun->machine->interrupt_handler_p \
1749 ? K0_REG_NUM \
1750 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1751
1752 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1753 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1754 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1755
1756 /* Define this macro if it is as good or better to call a constant
1757 function address than to call an address kept in a register. */
1758 #define NO_FUNCTION_CSE 1
1759
1760 /* The ABI-defined global pointer. Sometimes we use a different
1761 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1762 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1763
1764 /* We normally use $28 as the global pointer. However, when generating
1765 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1766 register instead. They can then avoid saving and restoring $28
1767 and perhaps avoid using a frame at all.
1768
1769 When a leaf function uses something other than $28, mips_expand_prologue
1770 will modify pic_offset_table_rtx in place. Take the register number
1771 from there after reload. */
1772 #define PIC_OFFSET_TABLE_REGNUM \
1773 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1774
1775 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1776 \f
1777 /* Define the classes of registers for register constraints in the
1778 machine description. Also define ranges of constants.
1779
1780 One of the classes must always be named ALL_REGS and include all hard regs.
1781 If there is more than one class, another class must be named NO_REGS
1782 and contain no registers.
1783
1784 The name GENERAL_REGS must be the name of a class (or an alias for
1785 another name such as ALL_REGS). This is the class of registers
1786 that is allowed by "g" or "r" in a register constraint.
1787 Also, registers outside this class are allocated only when
1788 instructions express preferences for them.
1789
1790 The classes must be numbered in nondecreasing order; that is,
1791 a larger-numbered class must never be contained completely
1792 in a smaller-numbered class.
1793
1794 For any two classes, it is very desirable that there be another
1795 class that represents their union. */
1796
1797 enum reg_class
1798 {
1799 NO_REGS, /* no registers in set */
1800 M16_REGS, /* mips16 directly accessible registers */
1801 T_REG, /* mips16 T register ($24) */
1802 M16_T_REGS, /* mips16 registers plus T register */
1803 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1804 V1_REG, /* Register $v1 ($3) used for TLS access. */
1805 LEA_REGS, /* Every GPR except $25 */
1806 GR_REGS, /* integer registers */
1807 FP_REGS, /* floating point registers */
1808 MD0_REG, /* first multiply/divide register */
1809 MD1_REG, /* second multiply/divide register */
1810 MD_REGS, /* multiply/divide registers (hi/lo) */
1811 COP0_REGS, /* generic coprocessor classes */
1812 COP2_REGS,
1813 COP3_REGS,
1814 ST_REGS, /* status registers (fp status) */
1815 DSP_ACC_REGS, /* DSP accumulator registers */
1816 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1817 FRAME_REGS, /* $arg and $frame */
1818 GR_AND_MD0_REGS, /* union classes */
1819 GR_AND_MD1_REGS,
1820 GR_AND_MD_REGS,
1821 GR_AND_ACC_REGS,
1822 ALL_REGS, /* all registers */
1823 LIM_REG_CLASSES /* max value + 1 */
1824 };
1825
1826 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1827
1828 #define GENERAL_REGS GR_REGS
1829
1830 /* An initializer containing the names of the register classes as C
1831 string constants. These names are used in writing some of the
1832 debugging dumps. */
1833
1834 #define REG_CLASS_NAMES \
1835 { \
1836 "NO_REGS", \
1837 "M16_REGS", \
1838 "T_REG", \
1839 "M16_T_REGS", \
1840 "PIC_FN_ADDR_REG", \
1841 "V1_REG", \
1842 "LEA_REGS", \
1843 "GR_REGS", \
1844 "FP_REGS", \
1845 "MD0_REG", \
1846 "MD1_REG", \
1847 "MD_REGS", \
1848 /* coprocessor registers */ \
1849 "COP0_REGS", \
1850 "COP2_REGS", \
1851 "COP3_REGS", \
1852 "ST_REGS", \
1853 "DSP_ACC_REGS", \
1854 "ACC_REGS", \
1855 "FRAME_REGS", \
1856 "GR_AND_MD0_REGS", \
1857 "GR_AND_MD1_REGS", \
1858 "GR_AND_MD_REGS", \
1859 "GR_AND_ACC_REGS", \
1860 "ALL_REGS" \
1861 }
1862
1863 /* An initializer containing the contents of the register classes,
1864 as integers which are bit masks. The Nth integer specifies the
1865 contents of class N. The way the integer MASK is interpreted is
1866 that register R is in the class if `MASK & (1 << R)' is 1.
1867
1868 When the machine has more than 32 registers, an integer does not
1869 suffice. Then the integers are replaced by sub-initializers,
1870 braced groupings containing several integers. Each
1871 sub-initializer must be suitable as an initializer for the type
1872 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1873
1874 #define REG_CLASS_CONTENTS \
1875 { \
1876 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1877 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1878 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1879 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1880 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1881 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1882 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1883 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1884 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1885 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1886 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1887 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1888 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1889 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1890 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1891 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1892 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1893 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1894 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1895 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1896 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1897 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1898 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1899 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1900 }
1901
1902
1903 /* A C expression whose value is a register class containing hard
1904 register REGNO. In general there is more that one such class;
1905 choose a class which is "minimal", meaning that no smaller class
1906 also contains the register. */
1907
1908 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1909
1910 /* A macro whose definition is the name of the class to which a
1911 valid base register must belong. A base register is one used in
1912 an address which is the register value plus a displacement. */
1913
1914 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1915
1916 /* A macro whose definition is the name of the class to which a
1917 valid index register must belong. An index register is one used
1918 in an address where its value is either multiplied by a scale
1919 factor or added to another register (as well as added to a
1920 displacement). */
1921
1922 #define INDEX_REG_CLASS NO_REGS
1923
1924 /* We generally want to put call-clobbered registers ahead of
1925 call-saved ones. (IRA expects this.) */
1926
1927 #define REG_ALLOC_ORDER \
1928 { /* Accumulator registers. When GPRs and accumulators have equal \
1929 cost, we generally prefer to use accumulators. For example, \
1930 a division of multiplication result is better allocated to LO, \
1931 so that we put the MFLO at the point of use instead of at the \
1932 point of definition. It's also needed if we're to take advantage \
1933 of the extra accumulators available with -mdspr2. In some cases, \
1934 it can also help to reduce register pressure. */ \
1935 64, 65,176,177,178,179,180,181, \
1936 /* Call-clobbered GPRs. */ \
1937 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1938 24, 25, 31, \
1939 /* The global pointer. This is call-clobbered for o32 and o64 \
1940 abicalls, call-saved for n32 and n64 abicalls, and a program \
1941 invariant otherwise. Putting it between the call-clobbered \
1942 and call-saved registers should cope with all eventualities. */ \
1943 28, \
1944 /* Call-saved GPRs. */ \
1945 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1946 /* GPRs that can never be exposed to the register allocator. */ \
1947 0, 26, 27, 29, \
1948 /* Call-clobbered FPRs. */ \
1949 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1950 48, 49, 50, 51, \
1951 /* FPRs that are usually call-saved. The odd ones are actually \
1952 call-clobbered for n32, but listing them ahead of the even \
1953 registers might encourage the register allocator to fragment \
1954 the available FPR pairs. We need paired FPRs to store long \
1955 doubles, so it isn't clear that using a different order \
1956 for n32 would be a win. */ \
1957 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1958 /* None of the remaining classes have defined call-saved \
1959 registers. */ \
1960 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1961 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1962 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1963 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1964 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1965 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1966 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1967 182,183,184,185,186,187 \
1968 }
1969
1970 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1971 to be rearranged based on a particular function. On the mips16, we
1972 want to allocate $24 (T_REG) before other registers for
1973 instructions for which it is possible. */
1974
1975 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
1976
1977 /* True if VALUE is an unsigned 6-bit number. */
1978
1979 #define UIMM6_OPERAND(VALUE) \
1980 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1981
1982 /* True if VALUE is a signed 10-bit number. */
1983
1984 #define IMM10_OPERAND(VALUE) \
1985 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1986
1987 /* True if VALUE is a signed 16-bit number. */
1988
1989 #define SMALL_OPERAND(VALUE) \
1990 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1991
1992 /* True if VALUE is an unsigned 16-bit number. */
1993
1994 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1995 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1996
1997 /* True if VALUE can be loaded into a register using LUI. */
1998
1999 #define LUI_OPERAND(VALUE) \
2000 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2001 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2002
2003 /* Return a value X with the low 16 bits clear, and such that
2004 VALUE - X is a signed 16-bit value. */
2005
2006 #define CONST_HIGH_PART(VALUE) \
2007 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2008
2009 #define CONST_LOW_PART(VALUE) \
2010 ((VALUE) - CONST_HIGH_PART (VALUE))
2011
2012 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2013 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2014 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2015
2016 /* The HI and LO registers can only be reloaded via the general
2017 registers. Condition code registers can only be loaded to the
2018 general registers, and from the floating point registers. */
2019
2020 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2021 mips_secondary_reload_class (CLASS, MODE, X, true)
2022 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2023 mips_secondary_reload_class (CLASS, MODE, X, false)
2024
2025 /* Return the maximum number of consecutive registers
2026 needed to represent mode MODE in a register of class CLASS. */
2027
2028 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2029
2030 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2031 mips_cannot_change_mode_class (FROM, TO, CLASS)
2032 \f
2033 /* Stack layout; function entry, exit and calling. */
2034
2035 #define STACK_GROWS_DOWNWARD
2036
2037 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2038
2039 /* Size of the area allocated in the frame to save the GP. */
2040
2041 #define MIPS_GP_SAVE_AREA_SIZE \
2042 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2043
2044 /* The offset of the first local variable from the frame pointer. See
2045 mips_compute_frame_info for details about the frame layout. */
2046
2047 #define STARTING_FRAME_OFFSET \
2048 (FRAME_GROWS_DOWNWARD \
2049 ? 0 \
2050 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2051
2052 #define RETURN_ADDR_RTX mips_return_addr
2053
2054 /* Mask off the MIPS16 ISA bit in unwind addresses.
2055
2056 The reason for this is a little subtle. When unwinding a call,
2057 we are given the call's return address, which on most targets
2058 is the address of the following instruction. However, what we
2059 actually want to find is the EH region for the call itself.
2060 The target-independent unwind code therefore searches for "RA - 1".
2061
2062 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2063 RA - 1 is therefore the real (even-valued) start of the return
2064 instruction. EH region labels are usually odd-valued MIPS16 symbols
2065 too, so a search for an even address within a MIPS16 region would
2066 usually work.
2067
2068 However, there is an exception. If the end of an EH region is also
2069 the end of a function, the end label is allowed to be even. This is
2070 necessary because a following non-MIPS16 function may also need EH
2071 information for its first instruction.
2072
2073 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2074 non-ISA-encoded address. This probably isn't ideal, but it is
2075 the traditional (legacy) behavior. It is therefore only safe
2076 to search MIPS EH regions for an _odd-valued_ address.
2077
2078 Masking off the ISA bit means that the target-independent code
2079 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2080 #define MASK_RETURN_ADDR GEN_INT (-2)
2081
2082
2083 /* Similarly, don't use the least-significant bit to tell pointers to
2084 code from vtable index. */
2085
2086 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2087
2088 /* The eliminations to $17 are only used for mips16 code. See the
2089 definition of HARD_FRAME_POINTER_REGNUM. */
2090
2091 #define ELIMINABLE_REGS \
2092 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2093 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2094 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2095 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2096 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2097 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2098
2099 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2100 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2101
2102 /* Allocate stack space for arguments at the beginning of each function. */
2103 #define ACCUMULATE_OUTGOING_ARGS 1
2104
2105 /* The argument pointer always points to the first argument. */
2106 #define FIRST_PARM_OFFSET(FNDECL) 0
2107
2108 /* o32 and o64 reserve stack space for all argument registers. */
2109 #define REG_PARM_STACK_SPACE(FNDECL) \
2110 (TARGET_OLDABI \
2111 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2112 : 0)
2113
2114 /* Define this if it is the responsibility of the caller to
2115 allocate the area reserved for arguments passed in registers.
2116 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2117 of this macro is to determine whether the space is included in
2118 `crtl->outgoing_args_size'. */
2119 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2120
2121 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2122 \f
2123 /* Symbolic macros for the registers used to return integer and floating
2124 point values. */
2125
2126 #define GP_RETURN (GP_REG_FIRST + 2)
2127 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2128
2129 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2130
2131 /* Symbolic macros for the first/last argument registers. */
2132
2133 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2134 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2135 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2136 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2137
2138 /* 1 if N is a possible register number for function argument passing.
2139 We have no FP argument registers when soft-float. When FP registers
2140 are 32 bits, we can't directly reference the odd numbered ones. */
2141
2142 #define FUNCTION_ARG_REGNO_P(N) \
2143 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2144 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2145 && !fixed_regs[N])
2146 \f
2147 /* This structure has to cope with two different argument allocation
2148 schemes. Most MIPS ABIs view the arguments as a structure, of which
2149 the first N words go in registers and the rest go on the stack. If I
2150 < N, the Ith word might go in Ith integer argument register or in a
2151 floating-point register. For these ABIs, we only need to remember
2152 the offset of the current argument into the structure.
2153
2154 The EABI instead allocates the integer and floating-point arguments
2155 separately. The first N words of FP arguments go in FP registers,
2156 the rest go on the stack. Likewise, the first N words of the other
2157 arguments go in integer registers, and the rest go on the stack. We
2158 need to maintain three counts: the number of integer registers used,
2159 the number of floating-point registers used, and the number of words
2160 passed on the stack.
2161
2162 We could keep separate information for the two ABIs (a word count for
2163 the standard ABIs, and three separate counts for the EABI). But it
2164 seems simpler to view the standard ABIs as forms of EABI that do not
2165 allocate floating-point registers.
2166
2167 So for the standard ABIs, the first N words are allocated to integer
2168 registers, and mips_function_arg decides on an argument-by-argument
2169 basis whether that argument should really go in an integer register,
2170 or in a floating-point one. */
2171
2172 typedef struct mips_args {
2173 /* Always true for varargs functions. Otherwise true if at least
2174 one argument has been passed in an integer register. */
2175 int gp_reg_found;
2176
2177 /* The number of arguments seen so far. */
2178 unsigned int arg_number;
2179
2180 /* The number of integer registers used so far. For all ABIs except
2181 EABI, this is the number of words that have been added to the
2182 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2183 unsigned int num_gprs;
2184
2185 /* For EABI, the number of floating-point registers used so far. */
2186 unsigned int num_fprs;
2187
2188 /* The number of words passed on the stack. */
2189 unsigned int stack_words;
2190
2191 /* On the mips16, we need to keep track of which floating point
2192 arguments were passed in general registers, but would have been
2193 passed in the FP regs if this were a 32-bit function, so that we
2194 can move them to the FP regs if we wind up calling a 32-bit
2195 function. We record this information in fp_code, encoded in base
2196 four. A zero digit means no floating point argument, a one digit
2197 means an SFmode argument, and a two digit means a DFmode argument,
2198 and a three digit is not used. The low order digit is the first
2199 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2200 an SFmode argument. ??? A more sophisticated approach will be
2201 needed if MIPS_ABI != ABI_32. */
2202 int fp_code;
2203
2204 /* True if the function has a prototype. */
2205 int prototype;
2206 } CUMULATIVE_ARGS;
2207
2208 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2209 for a call to a function whose data type is FNTYPE.
2210 For a library call, FNTYPE is 0. */
2211
2212 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2213 mips_init_cumulative_args (&CUM, FNTYPE)
2214
2215 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2216 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2217
2218 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2219 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2220
2221 /* True if using EABI and varargs can be passed in floating-point
2222 registers. Under these conditions, we need a more complex form
2223 of va_list, which tracks GPR, FPR and stack arguments separately. */
2224 #define EABI_FLOAT_VARARGS_P \
2225 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2226
2227 \f
2228 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2229
2230 /* Treat LOC as a byte offset from the stack pointer and round it up
2231 to the next fully-aligned offset. */
2232 #define MIPS_STACK_ALIGN(LOC) \
2233 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2234
2235 \f
2236 /* Output assembler code to FILE to increment profiler label # LABELNO
2237 for profiling a function entry. */
2238
2239 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2240
2241 /* The profiler preserves all interesting registers, including $31. */
2242 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2243
2244 /* No mips port has ever used the profiler counter word, so don't emit it
2245 or the label for it. */
2246
2247 #define NO_PROFILE_COUNTERS 1
2248
2249 /* Define this macro if the code for function profiling should come
2250 before the function prologue. Normally, the profiling code comes
2251 after. */
2252
2253 /* #define PROFILE_BEFORE_PROLOGUE */
2254
2255 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2256 the stack pointer does not matter. The value is tested only in
2257 functions that have frame pointers.
2258 No definition is equivalent to always zero. */
2259
2260 #define EXIT_IGNORE_STACK 1
2261
2262 \f
2263 /* Trampolines are a block of code followed by two pointers. */
2264
2265 #define TRAMPOLINE_SIZE \
2266 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2267
2268 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2269 pointers from a single LUI base. */
2270
2271 #define TRAMPOLINE_ALIGNMENT 64
2272
2273 /* mips_trampoline_init calls this library function to flush
2274 program and data caches. */
2275
2276 #ifndef CACHE_FLUSH_FUNC
2277 #define CACHE_FLUSH_FUNC "_flush_cache"
2278 #endif
2279
2280 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2281 /* Flush both caches. We need to flush the data cache in case \
2282 the system has a write-back cache. */ \
2283 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2284 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2285 GEN_INT (3), TYPE_MODE (integer_type_node))
2286
2287 \f
2288 /* Addressing modes, and classification of registers for them. */
2289
2290 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2291 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2292 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2293 \f
2294 /* Maximum number of registers that can appear in a valid memory address. */
2295
2296 #define MAX_REGS_PER_ADDRESS 1
2297
2298 /* Check for constness inline but use mips_legitimate_address_p
2299 to check whether a constant really is an address. */
2300
2301 #define CONSTANT_ADDRESS_P(X) \
2302 (CONSTANT_P (X) && memory_address_p (SImode, X))
2303
2304 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2305 'the start of the function that this code is output in'. */
2306
2307 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2308 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2309 asm_fprintf ((FILE), "%U%s", \
2310 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2311 else \
2312 asm_fprintf ((FILE), "%U%s", (NAME))
2313 \f
2314 /* Flag to mark a function decl symbol that requires a long call. */
2315 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2316 #define SYMBOL_REF_LONG_CALL_P(X) \
2317 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2318
2319 /* This flag marks functions that cannot be lazily bound. */
2320 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2321 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2322 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2323
2324 /* True if we're generating a form of MIPS16 code in which jump tables
2325 are stored in the text section and encoded as 16-bit PC-relative
2326 offsets. This is only possible when general text loads are allowed,
2327 since the table access itself will be an "lh" instruction. */
2328 /* ??? 16-bit offsets can overflow in large functions. */
2329 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2330
2331 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2332
2333 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2334
2335 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2336
2337 /* Define this as 1 if `char' should by default be signed; else as 0. */
2338 #ifndef DEFAULT_SIGNED_CHAR
2339 #define DEFAULT_SIGNED_CHAR 1
2340 #endif
2341
2342 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2343 we generally don't want to use them for copying arbitrary data.
2344 A single N-word move is usually the same cost as N single-word moves. */
2345 #define MOVE_MAX UNITS_PER_WORD
2346 #define MAX_MOVE_MAX 8
2347
2348 /* Define this macro as a C expression which is nonzero if
2349 accessing less than a word of memory (i.e. a `char' or a
2350 `short') is no faster than accessing a word of memory, i.e., if
2351 such access require more than one instruction or if there is no
2352 difference in cost between byte and (aligned) word loads.
2353
2354 On RISC machines, it tends to generate better code to define
2355 this as 1, since it avoids making a QI or HI mode register.
2356
2357 But, generating word accesses for -mips16 is generally bad as shifts
2358 (often extended) would be needed for byte accesses. */
2359 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2360
2361 /* Standard MIPS integer shifts truncate the shift amount to the
2362 width of the shifted operand. However, Loongson vector shifts
2363 do not truncate the shift amount at all. */
2364 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2365
2366 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2367 is done just by pretending it is already truncated. */
2368 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2369 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2370
2371
2372 /* Specify the machine mode that pointers have.
2373 After generation of rtl, the compiler makes no further distinction
2374 between pointers and any other objects of this machine mode. */
2375
2376 #ifndef Pmode
2377 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2378 #endif
2379
2380 /* Give call MEMs SImode since it is the "most permissive" mode
2381 for both 32-bit and 64-bit targets. */
2382
2383 #define FUNCTION_MODE SImode
2384
2385 \f
2386
2387 /* Define if copies to/from condition code registers should be avoided.
2388
2389 This is needed for the MIPS because reload_outcc is not complete;
2390 it needs to handle cases where the source is a general or another
2391 condition code register. */
2392 #define AVOID_CCMODE_COPIES
2393
2394 /* A C expression for the cost of a branch instruction. A value of
2395 1 is the default; other values are interpreted relative to that. */
2396
2397 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2398 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2399
2400 /* If defined, modifies the length assigned to instruction INSN as a
2401 function of the context in which it is used. LENGTH is an lvalue
2402 that contains the initially computed length of the insn and should
2403 be updated with the correct length of the insn. */
2404 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2405 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2406
2407 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2408 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2409 its operands. */
2410 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2411 "%*" OPCODE "%?\t" OPERANDS "%/"
2412
2413 /* Return an asm string that forces INSN to be treated as an absolute
2414 J or JAL instruction instead of an assembler macro. */
2415 #define MIPS_ABSOLUTE_JUMP(INSN) \
2416 (TARGET_ABICALLS_PIC2 \
2417 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2418 : INSN)
2419
2420 /* Return the asm template for a call. INSN is the instruction's mnemonic
2421 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2422 number of the target. SIZE_OPNO is the operand number of the argument size
2423 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2424 -1 and the call is indirect, use the function symbol from the call
2425 attributes to attach a R_MIPS_JALR relocation to the call.
2426
2427 When generating GOT code without explicit relocation operators,
2428 all calls should use assembly macros. Otherwise, all indirect
2429 calls should use "jr" or "jalr"; we will arrange to restore $gp
2430 afterwards if necessary. Finally, we can only generate direct
2431 calls for -mabicalls by temporarily switching to non-PIC mode. */
2432 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2433 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2434 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2435 : (REG_P (OPERANDS[TARGET_OPNO]) \
2436 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2437 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2438 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2439 : REG_P (OPERANDS[TARGET_OPNO]) \
2440 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2441 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2442 \f
2443 /* Control the assembler format that we output. */
2444
2445 /* Output to assembler file text saying following lines
2446 may contain character constants, extra white space, comments, etc. */
2447
2448 #ifndef ASM_APP_ON
2449 #define ASM_APP_ON " #APP\n"
2450 #endif
2451
2452 /* Output to assembler file text saying following lines
2453 no longer contain unusual constructs. */
2454
2455 #ifndef ASM_APP_OFF
2456 #define ASM_APP_OFF " #NO_APP\n"
2457 #endif
2458
2459 #define REGISTER_NAMES \
2460 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2461 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2462 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2463 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2464 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2465 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2466 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2467 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2468 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2469 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2470 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2471 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2472 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2473 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2474 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2475 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2476 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2477 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2478 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2479 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2480 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2481 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2482 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2483 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2484
2485 /* List the "software" names for each register. Also list the numerical
2486 names for $fp and $sp. */
2487
2488 #define ADDITIONAL_REGISTER_NAMES \
2489 { \
2490 { "$29", 29 + GP_REG_FIRST }, \
2491 { "$30", 30 + GP_REG_FIRST }, \
2492 { "at", 1 + GP_REG_FIRST }, \
2493 { "v0", 2 + GP_REG_FIRST }, \
2494 { "v1", 3 + GP_REG_FIRST }, \
2495 { "a0", 4 + GP_REG_FIRST }, \
2496 { "a1", 5 + GP_REG_FIRST }, \
2497 { "a2", 6 + GP_REG_FIRST }, \
2498 { "a3", 7 + GP_REG_FIRST }, \
2499 { "t0", 8 + GP_REG_FIRST }, \
2500 { "t1", 9 + GP_REG_FIRST }, \
2501 { "t2", 10 + GP_REG_FIRST }, \
2502 { "t3", 11 + GP_REG_FIRST }, \
2503 { "t4", 12 + GP_REG_FIRST }, \
2504 { "t5", 13 + GP_REG_FIRST }, \
2505 { "t6", 14 + GP_REG_FIRST }, \
2506 { "t7", 15 + GP_REG_FIRST }, \
2507 { "s0", 16 + GP_REG_FIRST }, \
2508 { "s1", 17 + GP_REG_FIRST }, \
2509 { "s2", 18 + GP_REG_FIRST }, \
2510 { "s3", 19 + GP_REG_FIRST }, \
2511 { "s4", 20 + GP_REG_FIRST }, \
2512 { "s5", 21 + GP_REG_FIRST }, \
2513 { "s6", 22 + GP_REG_FIRST }, \
2514 { "s7", 23 + GP_REG_FIRST }, \
2515 { "t8", 24 + GP_REG_FIRST }, \
2516 { "t9", 25 + GP_REG_FIRST }, \
2517 { "k0", 26 + GP_REG_FIRST }, \
2518 { "k1", 27 + GP_REG_FIRST }, \
2519 { "gp", 28 + GP_REG_FIRST }, \
2520 { "sp", 29 + GP_REG_FIRST }, \
2521 { "fp", 30 + GP_REG_FIRST }, \
2522 { "ra", 31 + GP_REG_FIRST }, \
2523 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2524 }
2525
2526 /* This is meant to be redefined in the host dependent files. It is a
2527 set of alternative names and regnums for mips coprocessors. */
2528
2529 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2530
2531 #define DBR_OUTPUT_SEQEND(STREAM) \
2532 do \
2533 { \
2534 /* Undo the effect of '%*'. */ \
2535 mips_pop_asm_switch (&mips_nomacro); \
2536 mips_pop_asm_switch (&mips_noreorder); \
2537 /* Emit a blank line after the delay slot for emphasis. */ \
2538 fputs ("\n", STREAM); \
2539 } \
2540 while (0)
2541
2542 /* Use .loc directives for SDB line numbers. */
2543 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2544 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2545
2546 /* The MIPS implementation uses some labels for its own purpose. The
2547 following lists what labels are created, and are all formed by the
2548 pattern $L[a-z].*. The machine independent portion of GCC creates
2549 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2550
2551 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2552 $Lb[0-9]+ Begin blocks for MIPS debug support
2553 $Lc[0-9]+ Label for use in s<xx> operation.
2554 $Le[0-9]+ End blocks for MIPS debug support */
2555
2556 #undef ASM_DECLARE_OBJECT_NAME
2557 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2558 mips_declare_object (STREAM, NAME, "", ":\n")
2559
2560 /* Globalizing directive for a label. */
2561 #define GLOBAL_ASM_OP "\t.globl\t"
2562
2563 /* This says how to define a global common symbol. */
2564
2565 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2566
2567 /* This says how to define a local common symbol (i.e., not visible to
2568 linker). */
2569
2570 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2571 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2572 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2573 #endif
2574
2575 /* This says how to output an external. It would be possible not to
2576 output anything and let undefined symbol become external. However
2577 the assembler uses length information on externals to allocate in
2578 data/sdata bss/sbss, thereby saving exec time. */
2579
2580 #undef ASM_OUTPUT_EXTERNAL
2581 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2582 mips_output_external(STREAM,DECL,NAME)
2583
2584 /* This is how to declare a function name. The actual work of
2585 emitting the label is moved to function_prologue, so that we can
2586 get the line number correctly emitted before the .ent directive,
2587 and after any .file directives. Define as empty so that the function
2588 is not declared before the .ent directive elsewhere. */
2589
2590 #undef ASM_DECLARE_FUNCTION_NAME
2591 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2592
2593 /* This is how to store into the string LABEL
2594 the symbol_ref name of an internal numbered label where
2595 PREFIX is the class of label and NUM is the number within the class.
2596 This is suitable for output with `assemble_name'. */
2597
2598 #undef ASM_GENERATE_INTERNAL_LABEL
2599 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2600 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2601
2602 /* Print debug labels as "foo = ." rather than "foo:" because they should
2603 represent a byte pointer rather than an ISA-encoded address. This is
2604 particularly important for code like:
2605
2606 $LFBxxx = .
2607 .cfi_startproc
2608 ...
2609 .section .gcc_except_table,...
2610 ...
2611 .uleb128 foo-$LFBxxx
2612
2613 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2614 likewise a byte pointer rather than an ISA-encoded address.
2615
2616 At the time of writing, this hook is not used for the function end
2617 label:
2618
2619 $LFExxx:
2620 .end foo
2621
2622 But this doesn't matter, because GAS doesn't treat a pre-.end label
2623 as a MIPS16 one anyway. */
2624
2625 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2626 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2627
2628 /* This is how to output an element of a case-vector that is absolute. */
2629
2630 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2631 fprintf (STREAM, "\t%s\t%sL%d\n", \
2632 ptr_mode == DImode ? ".dword" : ".word", \
2633 LOCAL_LABEL_PREFIX, \
2634 VALUE)
2635
2636 /* This is how to output an element of a case-vector. We can make the
2637 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2638 is supported. */
2639
2640 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2641 do { \
2642 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2643 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2644 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2645 else if (TARGET_GPWORD) \
2646 fprintf (STREAM, "\t%s\t%sL%d\n", \
2647 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2648 LOCAL_LABEL_PREFIX, VALUE); \
2649 else if (TARGET_RTP_PIC) \
2650 { \
2651 /* Make the entry relative to the start of the function. */ \
2652 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2653 fprintf (STREAM, "\t%s\t%sL%d-", \
2654 Pmode == DImode ? ".dword" : ".word", \
2655 LOCAL_LABEL_PREFIX, VALUE); \
2656 assemble_name (STREAM, XSTR (fnsym, 0)); \
2657 fprintf (STREAM, "\n"); \
2658 } \
2659 else \
2660 fprintf (STREAM, "\t%s\t%sL%d\n", \
2661 ptr_mode == DImode ? ".dword" : ".word", \
2662 LOCAL_LABEL_PREFIX, VALUE); \
2663 } while (0)
2664
2665 /* This is how to output an assembler line
2666 that says to advance the location counter
2667 to a multiple of 2**LOG bytes. */
2668
2669 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2670 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2671
2672 /* This is how to output an assembler line to advance the location
2673 counter by SIZE bytes. */
2674
2675 #undef ASM_OUTPUT_SKIP
2676 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2677 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2678
2679 /* This is how to output a string. */
2680 #undef ASM_OUTPUT_ASCII
2681 #define ASM_OUTPUT_ASCII mips_output_ascii
2682
2683 /* Output #ident as a in the read-only data section. */
2684 #undef ASM_OUTPUT_IDENT
2685 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2686 { \
2687 const char *p = STRING; \
2688 int size = strlen (p) + 1; \
2689 switch_to_section (readonly_data_section); \
2690 assemble_string (p, size); \
2691 }
2692 \f
2693 /* Default to -G 8 */
2694 #ifndef MIPS_DEFAULT_GVALUE
2695 #define MIPS_DEFAULT_GVALUE 8
2696 #endif
2697
2698 /* Define the strings to put out for each section in the object file. */
2699 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2700 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2701
2702 #undef READONLY_DATA_SECTION_ASM_OP
2703 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2704 \f
2705 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2706 do \
2707 { \
2708 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2709 TARGET_64BIT ? "daddiu" : "addiu", \
2710 reg_names[STACK_POINTER_REGNUM], \
2711 reg_names[STACK_POINTER_REGNUM], \
2712 TARGET_64BIT ? "sd" : "sw", \
2713 reg_names[REGNO], \
2714 reg_names[STACK_POINTER_REGNUM]); \
2715 } \
2716 while (0)
2717
2718 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2719 do \
2720 { \
2721 mips_push_asm_switch (&mips_noreorder); \
2722 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2723 TARGET_64BIT ? "ld" : "lw", \
2724 reg_names[REGNO], \
2725 reg_names[STACK_POINTER_REGNUM], \
2726 TARGET_64BIT ? "daddu" : "addu", \
2727 reg_names[STACK_POINTER_REGNUM], \
2728 reg_names[STACK_POINTER_REGNUM]); \
2729 mips_pop_asm_switch (&mips_noreorder); \
2730 } \
2731 while (0)
2732
2733 /* How to start an assembler comment.
2734 The leading space is important (the mips native assembler requires it). */
2735 #ifndef ASM_COMMENT_START
2736 #define ASM_COMMENT_START " #"
2737 #endif
2738 \f
2739 #undef SIZE_TYPE
2740 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2741
2742 #undef PTRDIFF_TYPE
2743 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2744
2745 /* The maximum number of bytes that can be copied by one iteration of
2746 a movmemsi loop; see mips_block_move_loop. */
2747 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2748 (UNITS_PER_WORD * 4)
2749
2750 /* The maximum number of bytes that can be copied by a straight-line
2751 implementation of movmemsi; see mips_block_move_straight. We want
2752 to make sure that any loop-based implementation will iterate at
2753 least twice. */
2754 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2755 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2756
2757 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2758 values were determined experimentally by benchmarking with CSiBE.
2759 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2760 for o32 where we have to restore $gp afterwards as well as make an
2761 indirect call), but in practice, bumping this up higher for
2762 TARGET_ABICALLS doesn't make much difference to code size. */
2763
2764 #define MIPS_CALL_RATIO 8
2765
2766 /* Any loop-based implementation of movmemsi will have at least
2767 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2768 moves, so allow individual copies of fewer elements.
2769
2770 When movmemsi is not available, use a value approximating
2771 the length of a memcpy call sequence, so that move_by_pieces
2772 will generate inline code if it is shorter than a function call.
2773 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2774 we'll have to generate a load/store pair for each, halve the
2775 value of MIPS_CALL_RATIO to take that into account. */
2776
2777 #define MOVE_RATIO(speed) \
2778 (HAVE_movmemsi \
2779 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2780 : MIPS_CALL_RATIO / 2)
2781
2782 /* movmemsi is meant to generate code that is at least as good as
2783 move_by_pieces. However, movmemsi effectively uses a by-pieces
2784 implementation both for moves smaller than a word and for word-aligned
2785 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
2786 allow the tree-level optimisers to do such moves by pieces, as it
2787 often exposes other optimization opportunities. We might as well
2788 continue to use movmemsi at the rtl level though, as it produces
2789 better code when scheduling is disabled (such as at -O). */
2790
2791 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2792 (HAVE_movmemsi \
2793 ? (!currently_expanding_to_rtl \
2794 && ((ALIGN) < BITS_PER_WORD \
2795 ? (SIZE) < UNITS_PER_WORD \
2796 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
2797 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2798 < (unsigned int) MOVE_RATIO (false)))
2799
2800 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2801 of the length of a memset call, but use the default otherwise. */
2802
2803 #define CLEAR_RATIO(speed)\
2804 ((speed) ? 15 : MIPS_CALL_RATIO)
2805
2806 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2807 optimizing for size adjust the ratio to account for the overhead of
2808 loading the constant and replicating it across the word. */
2809
2810 #define SET_RATIO(speed) \
2811 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2812
2813 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2814 in that case each word takes 3 insns (lui, ori, sw), or more in
2815 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2816 and let the move_by_pieces code copy the string from read-only
2817 memory. In the future, this could be tuned further for multi-issue
2818 CPUs that can issue stores down one pipe and arithmetic instructions
2819 down another; in that case, the lui/ori/sw combination would be a
2820 win for long enough strings. */
2821
2822 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2823 \f
2824 #ifndef __mips16
2825 /* Since the bits of the _init and _fini function is spread across
2826 many object files, each potentially with its own GP, we must assume
2827 we need to load our GP. We don't preserve $gp or $ra, since each
2828 init/fini chunk is supposed to initialize $gp, and crti/crtn
2829 already take care of preserving $ra and, when appropriate, $gp. */
2830 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2831 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2832 asm (SECTION_OP "\n\
2833 .set noreorder\n\
2834 bal 1f\n\
2835 nop\n\
2836 1: .cpload $31\n\
2837 .set reorder\n\
2838 jal " USER_LABEL_PREFIX #FUNC "\n\
2839 " TEXT_SECTION_ASM_OP);
2840 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2841 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2842 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2843 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2844 asm (SECTION_OP "\n\
2845 .set noreorder\n\
2846 bal 1f\n\
2847 nop\n\
2848 1: .set reorder\n\
2849 .cpsetup $31, $2, 1b\n\
2850 jal " USER_LABEL_PREFIX #FUNC "\n\
2851 " TEXT_SECTION_ASM_OP);
2852 #endif
2853 #endif
2854
2855 #ifndef HAVE_AS_TLS
2856 #define HAVE_AS_TLS 0
2857 #endif
2858
2859 #ifndef USED_FOR_TARGET
2860 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2861 struct mips_asm_switch {
2862 /* The FOO in the description above. */
2863 const char *name;
2864
2865 /* The current block nesting level, or 0 if we aren't in a block. */
2866 int nesting_level;
2867 };
2868
2869 extern const enum reg_class mips_regno_to_class[];
2870 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2871 extern const char *current_function_file; /* filename current function is in */
2872 extern int num_source_filenames; /* current .file # */
2873 extern struct mips_asm_switch mips_noreorder;
2874 extern struct mips_asm_switch mips_nomacro;
2875 extern struct mips_asm_switch mips_noat;
2876 extern int mips_dbx_regno[];
2877 extern int mips_dwarf_regno[];
2878 extern bool mips_split_p[];
2879 extern bool mips_split_hi_p[];
2880 extern enum processor mips_arch; /* which cpu to codegen for */
2881 extern enum processor mips_tune; /* which cpu to schedule for */
2882 extern int mips_isa; /* architectural level */
2883 extern const struct mips_cpu_info *mips_arch_info;
2884 extern const struct mips_cpu_info *mips_tune_info;
2885 extern bool mips_base_mips16;
2886 extern GTY(()) struct target_globals *mips16_globals;
2887 #endif
2888
2889 /* Enable querying of DFA units. */
2890 #define CPU_UNITS_QUERY 1
2891
2892 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2893 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2894
2895 /* As on most targets, we want the .eh_frame section to be read-only where
2896 possible. And as on most targets, this means two things:
2897
2898 (a) Non-locally-binding pointers must have an indirect encoding,
2899 so that the addresses in the .eh_frame section itself become
2900 locally-binding.
2901
2902 (b) A shared library's .eh_frame section must encode locally-binding
2903 pointers in a relative (relocation-free) form.
2904
2905 However, MIPS has traditionally not allowed directives like:
2906
2907 .long x-.
2908
2909 in cases where "x" is in a different section, or is not defined in the
2910 same assembly file. We are therefore unable to emit the PC-relative
2911 form required by (b) at assembly time.
2912
2913 Fortunately, the linker is able to convert absolute addresses into
2914 PC-relative addresses on our behalf. Unfortunately, only certain
2915 versions of the linker know how to do this for indirect pointers,
2916 and for personality data. We must fall back on using writable
2917 .eh_frame sections for shared libraries if the linker does not
2918 support this feature. */
2919 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2920 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2921
2922 /* For switching between MIPS16 and non-MIPS16 modes. */
2923 #define SWITCHABLE_TARGET 1
2924
2925 /* Several named MIPS patterns depend on Pmode. These patterns have the
2926 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2927 Add the appropriate suffix to generator function NAME and invoke it
2928 with arguments ARGS. */
2929 #define PMODE_INSN(NAME, ARGS) \
2930 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)