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mips.h (TARGET_CPU_CPP_BUILTINS): Define __mips_synci if TARGET_SYNCI.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
4 2012
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky (lich@inria.inria.fr).
7 Changed by Michael Meissner (meissner@osf.org).
8 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
9 Brendan Eich (brendan@microunity.com).
10
11 This file is part of GCC.
12
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
16 any later version.
17
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
26
27
28 #include "config/vxworks-dummy.h"
29
30 #ifdef GENERATOR_FILE
31 /* This is used in some insn conditions, so needs to be declared, but
32 does not need to be defined. */
33 extern int target_flags_explicit;
34 #endif
35
36 /* MIPS external variables defined in mips.c. */
37
38 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
39 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
40 to work on a 64-bit machine. */
41
42 #define ABI_32 0
43 #define ABI_N32 1
44 #define ABI_64 2
45 #define ABI_EABI 3
46 #define ABI_O64 4
47
48 /* Masks that affect tuning.
49
50 PTF_AVOID_BRANCHLIKELY
51 Set if it is usually not profitable to use branch-likely instructions
52 for this target, typically because the branches are always predicted
53 taken and so incur a large overhead when not taken. */
54 #define PTF_AVOID_BRANCHLIKELY 0x1
55
56 /* Information about one recognized processor. Defined here for the
57 benefit of TARGET_CPU_CPP_BUILTINS. */
58 struct mips_cpu_info {
59 /* The 'canonical' name of the processor as far as GCC is concerned.
60 It's typically a manufacturer's prefix followed by a numerical
61 designation. It should be lowercase. */
62 const char *name;
63
64 /* The internal processor number that most closely matches this
65 entry. Several processors can have the same value, if there's no
66 difference between them from GCC's point of view. */
67 enum processor cpu;
68
69 /* The ISA level that the processor implements. */
70 int isa;
71
72 /* A mask of PTF_* values. */
73 unsigned int tune_flags;
74 };
75
76 #include "config/mips/mips-opts.h"
77
78 /* Macros to silence warnings about numbers being signed in traditional
79 C and unsigned in ISO C when compiled on 32-bit hosts. */
80
81 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
82 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
83 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
84
85 \f
86 /* Run-time compilation parameters selecting different hardware subsets. */
87
88 /* True if we are generating position-independent VxWorks RTP code. */
89 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
90
91 /* True if the output file is marked as ".abicalls; .option pic0"
92 (-call_nonpic). */
93 #define TARGET_ABICALLS_PIC0 \
94 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
95
96 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
97 #define TARGET_ABICALLS_PIC2 \
98 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
99
100 /* True if the call patterns should be split into a jalr followed by
101 an instruction to restore $gp. It is only safe to split the load
102 from the call when every use of $gp is explicit.
103
104 See mips_must_initialize_gp_p for details about how we manage the
105 global pointer. */
106
107 #define TARGET_SPLIT_CALLS \
108 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
109
110 /* True if we're generating a form of -mabicalls in which we can use
111 operators like %hi and %lo to refer to locally-binding symbols.
112 We can only do this for -mno-shared, and only then if we can use
113 relocation operations instead of assembly macros. It isn't really
114 worth using absolute sequences for 64-bit symbols because GOT
115 accesses are so much shorter. */
116
117 #define TARGET_ABSOLUTE_ABICALLS \
118 (TARGET_ABICALLS \
119 && !TARGET_SHARED \
120 && TARGET_EXPLICIT_RELOCS \
121 && !ABI_HAS_64BIT_SYMBOLS)
122
123 /* True if we can optimize sibling calls. For simplicity, we only
124 handle cases in which call_insn_operand will reject invalid
125 sibcall addresses. There are two cases in which this isn't true:
126
127 - TARGET_MIPS16. call_insn_operand accepts constant addresses
128 but there is no direct jump instruction. It isn't worth
129 using sibling calls in this case anyway; they would usually
130 be longer than normal calls.
131
132 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
133 accepts global constants, but all sibcalls must be indirect. */
134 #define TARGET_SIBCALLS \
135 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
136
137 /* True if we need to use a global offset table to access some symbols. */
138 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
139
140 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
141 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
142
143 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
144 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
145
146 /* True if we should use .cprestore to store to the cprestore slot.
147
148 We continue to use .cprestore for explicit-reloc code so that JALs
149 inside inline asms will work correctly. */
150 #define TARGET_CPRESTORE_DIRECTIVE \
151 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
152
153 /* True if we can use the J and JAL instructions. */
154 #define TARGET_ABSOLUTE_JUMPS \
155 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
156
157 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
158 This is true for both the PIC and non-PIC VxWorks RTP modes. */
159 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
160
161 /* True if .gpword or .gpdword should be used for switch tables. */
162 #define TARGET_GPWORD \
163 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
164
165 /* True if the output must have a writable .eh_frame.
166 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
167 #ifdef HAVE_LD_PERSONALITY_RELAXATION
168 #define TARGET_WRITABLE_EH_FRAME 0
169 #else
170 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
171 #endif
172
173 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
174 #ifdef HAVE_AS_DSPR1_MULT
175 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
176 #else
177 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
178 #endif
179
180 /* Generate mips16 code */
181 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
182 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
183 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
184 /* Generate mips16e register save/restore sequences. */
185 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
186
187 /* True if we're generating a form of MIPS16 code in which general
188 text loads are allowed. */
189 #define TARGET_MIPS16_TEXT_LOADS \
190 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
191
192 /* True if we're generating a form of MIPS16 code in which PC-relative
193 loads are allowed. */
194 #define TARGET_MIPS16_PCREL_LOADS \
195 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
196
197 /* Generic ISA defines. */
198 #define ISA_MIPS1 (mips_isa == 1)
199 #define ISA_MIPS2 (mips_isa == 2)
200 #define ISA_MIPS3 (mips_isa == 3)
201 #define ISA_MIPS4 (mips_isa == 4)
202 #define ISA_MIPS32 (mips_isa == 32)
203 #define ISA_MIPS32R2 (mips_isa == 33)
204 #define ISA_MIPS64 (mips_isa == 64)
205 #define ISA_MIPS64R2 (mips_isa == 65)
206
207 /* Architecture target defines. */
208 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
209 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
210 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
211 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
212 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
213 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
214 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
215 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
216 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
217 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
218 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
219 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
220 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
221 || mips_arch == PROCESSOR_OCTEON2)
222 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
223 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
224 || mips_arch == PROCESSOR_SB1A)
225 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
226 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
227
228 /* Scheduling target defines. */
229 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
230 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
231 || mips_tune == PROCESSOR_24KF2_1 \
232 || mips_tune == PROCESSOR_24KF1_1)
233 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
234 || mips_tune == PROCESSOR_74KF2_1 \
235 || mips_tune == PROCESSOR_74KF1_1 \
236 || mips_tune == PROCESSOR_74KF3_2)
237 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
238 || mips_tune == PROCESSOR_LOONGSON_2F)
239 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
240 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
241 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
242 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
243 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
244 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
245 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
246 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
247 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
248 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
249 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
250 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
251 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
252 || mips_tune == PROCESSOR_OCTEON2)
253 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
254 || mips_tune == PROCESSOR_SB1A)
255
256 /* Whether vector modes and intrinsics for ST Microelectronics
257 Loongson-2E/2F processors should be enabled. In o32 pairs of
258 floating-point registers provide 64-bit values. */
259 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
260 && (TARGET_LOONGSON_2EF \
261 || TARGET_LOONGSON_3A))
262
263 /* True if the pre-reload scheduler should try to create chains of
264 multiply-add or multiply-subtract instructions. For example,
265 suppose we have:
266
267 t1 = a * b
268 t2 = t1 + c * d
269 t3 = e * f
270 t4 = t3 - g * h
271
272 t1 will have a higher priority than t2 and t3 will have a higher
273 priority than t4. However, before reload, there is no dependence
274 between t1 and t3, and they can often have similar priorities.
275 The scheduler will then tend to prefer:
276
277 t1 = a * b
278 t3 = e * f
279 t2 = t1 + c * d
280 t4 = t3 - g * h
281
282 which stops us from making full use of macc/madd-style instructions.
283 This sort of situation occurs frequently in Fourier transforms and
284 in unrolled loops.
285
286 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
287 queue so that chained multiply-add and multiply-subtract instructions
288 appear ahead of any other instruction that is likely to clobber lo.
289 In the example above, if t2 and t3 become ready at the same time,
290 the code ensures that t2 is scheduled first.
291
292 Multiply-accumulate instructions are a bigger win for some targets
293 than others, so this macro is defined on an opt-in basis. */
294 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
295 || TUNE_MIPS4120 \
296 || TUNE_MIPS4130 \
297 || TUNE_24K)
298
299 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
300 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
301
302 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
303 directly accessible, while the command-line options select
304 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
305 in use. */
306 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
307 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
308
309 /* False if SC acts as a memory barrier with respect to itself,
310 otherwise a SYNC will be emitted after SC for atomic operations
311 that require ordering between the SC and following loads and
312 stores. It does not tell anything about ordering of loads and
313 stores prior to and following the SC, only about the SC itself and
314 those loads and stores follow it. */
315 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
316
317 /* Define preprocessor macros for the -march and -mtune options.
318 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
319 processor. If INFO's canonical name is "foo", define PREFIX to
320 be "foo", and define an additional macro PREFIX_FOO. */
321 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
322 do \
323 { \
324 char *macro, *p; \
325 \
326 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
327 for (p = macro; *p != 0; p++) \
328 if (*p == '+') \
329 *p = 'P'; \
330 else \
331 *p = TOUPPER (*p); \
332 \
333 builtin_define (macro); \
334 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
335 free (macro); \
336 } \
337 while (0)
338
339 /* Target CPU builtins. */
340 #define TARGET_CPU_CPP_BUILTINS() \
341 do \
342 { \
343 builtin_assert ("machine=mips"); \
344 builtin_assert ("cpu=mips"); \
345 builtin_define ("__mips__"); \
346 builtin_define ("_mips"); \
347 \
348 /* We do this here because __mips is defined below and so we \
349 can't use builtin_define_std. We don't ever want to define \
350 "mips" for VxWorks because some of the VxWorks headers \
351 construct include filenames from a root directory macro, \
352 an architecture macro and a filename, where the architecture \
353 macro expands to 'mips'. If we define 'mips' to 1, the \
354 architecture macro expands to 1 as well. */ \
355 if (!flag_iso && !TARGET_VXWORKS) \
356 builtin_define ("mips"); \
357 \
358 if (TARGET_64BIT) \
359 builtin_define ("__mips64"); \
360 \
361 /* Treat _R3000 and _R4000 like register-size \
362 defines, which is how they've historically \
363 been used. */ \
364 if (TARGET_64BIT) \
365 { \
366 builtin_define_std ("R4000"); \
367 builtin_define ("_R4000"); \
368 } \
369 else \
370 { \
371 builtin_define_std ("R3000"); \
372 builtin_define ("_R3000"); \
373 } \
374 \
375 if (TARGET_FLOAT64) \
376 builtin_define ("__mips_fpr=64"); \
377 else \
378 builtin_define ("__mips_fpr=32"); \
379 \
380 if (mips_base_mips16) \
381 builtin_define ("__mips16"); \
382 \
383 if (TARGET_MIPS3D) \
384 builtin_define ("__mips3d"); \
385 \
386 if (TARGET_SMARTMIPS) \
387 builtin_define ("__mips_smartmips"); \
388 \
389 if (TARGET_MCU) \
390 builtin_define ("__mips_mcu"); \
391 \
392 if (TARGET_DSP) \
393 { \
394 builtin_define ("__mips_dsp"); \
395 if (TARGET_DSPR2) \
396 { \
397 builtin_define ("__mips_dspr2"); \
398 builtin_define ("__mips_dsp_rev=2"); \
399 } \
400 else \
401 builtin_define ("__mips_dsp_rev=1"); \
402 } \
403 \
404 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
405 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
406 \
407 if (ISA_MIPS1) \
408 { \
409 builtin_define ("__mips=1"); \
410 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
411 } \
412 else if (ISA_MIPS2) \
413 { \
414 builtin_define ("__mips=2"); \
415 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
416 } \
417 else if (ISA_MIPS3) \
418 { \
419 builtin_define ("__mips=3"); \
420 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
421 } \
422 else if (ISA_MIPS4) \
423 { \
424 builtin_define ("__mips=4"); \
425 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
426 } \
427 else if (ISA_MIPS32) \
428 { \
429 builtin_define ("__mips=32"); \
430 builtin_define ("__mips_isa_rev=1"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
432 } \
433 else if (ISA_MIPS32R2) \
434 { \
435 builtin_define ("__mips=32"); \
436 builtin_define ("__mips_isa_rev=2"); \
437 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
438 } \
439 else if (ISA_MIPS64) \
440 { \
441 builtin_define ("__mips=64"); \
442 builtin_define ("__mips_isa_rev=1"); \
443 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
444 } \
445 else if (ISA_MIPS64R2) \
446 { \
447 builtin_define ("__mips=64"); \
448 builtin_define ("__mips_isa_rev=2"); \
449 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
450 } \
451 \
452 switch (mips_abi) \
453 { \
454 case ABI_32: \
455 builtin_define ("_ABIO32=1"); \
456 builtin_define ("_MIPS_SIM=_ABIO32"); \
457 break; \
458 \
459 case ABI_N32: \
460 builtin_define ("_ABIN32=2"); \
461 builtin_define ("_MIPS_SIM=_ABIN32"); \
462 break; \
463 \
464 case ABI_64: \
465 builtin_define ("_ABI64=3"); \
466 builtin_define ("_MIPS_SIM=_ABI64"); \
467 break; \
468 \
469 case ABI_O64: \
470 builtin_define ("_ABIO64=4"); \
471 builtin_define ("_MIPS_SIM=_ABIO64"); \
472 break; \
473 } \
474 \
475 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
476 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
477 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
478 builtin_define_with_int_value ("_MIPS_FPSET", \
479 32 / MAX_FPRS_PER_FMT); \
480 \
481 /* These defines reflect the ABI in use, not whether the \
482 FPU is directly accessible. */ \
483 if (TARGET_NO_FLOAT) \
484 builtin_define ("__mips_no_float"); \
485 else if (TARGET_HARD_FLOAT_ABI) \
486 builtin_define ("__mips_hard_float"); \
487 else \
488 builtin_define ("__mips_soft_float"); \
489 \
490 if (TARGET_SINGLE_FLOAT) \
491 builtin_define ("__mips_single_float"); \
492 \
493 if (TARGET_PAIRED_SINGLE_FLOAT) \
494 builtin_define ("__mips_paired_single_float"); \
495 \
496 if (TARGET_BIG_ENDIAN) \
497 { \
498 builtin_define_std ("MIPSEB"); \
499 builtin_define ("_MIPSEB"); \
500 } \
501 else \
502 { \
503 builtin_define_std ("MIPSEL"); \
504 builtin_define ("_MIPSEL"); \
505 } \
506 \
507 /* Whether calls should go through $25. The separate __PIC__ \
508 macro indicates whether abicalls code might use a GOT. */ \
509 if (TARGET_ABICALLS) \
510 builtin_define ("__mips_abicalls"); \
511 \
512 /* Whether Loongson vector modes are enabled. */ \
513 if (TARGET_LOONGSON_VECTORS) \
514 builtin_define ("__mips_loongson_vector_rev"); \
515 \
516 /* Historical Octeon macro. */ \
517 if (TARGET_OCTEON) \
518 builtin_define ("__OCTEON__"); \
519 \
520 if (TARGET_SYNCI) \
521 builtin_define ("__mips_synci"); \
522 \
523 /* Macros dependent on the C dialect. */ \
524 if (preprocessing_asm_p ()) \
525 { \
526 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
527 builtin_define ("_LANGUAGE_ASSEMBLY"); \
528 } \
529 else if (c_dialect_cxx ()) \
530 { \
531 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
532 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
533 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
534 } \
535 else \
536 { \
537 builtin_define_std ("LANGUAGE_C"); \
538 builtin_define ("_LANGUAGE_C"); \
539 } \
540 if (c_dialect_objc ()) \
541 { \
542 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
543 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
544 /* Bizarre, but retained for backwards compatibility. */ \
545 builtin_define_std ("LANGUAGE_C"); \
546 builtin_define ("_LANGUAGE_C"); \
547 } \
548 \
549 if (mips_abi == ABI_EABI) \
550 builtin_define ("__mips_eabi"); \
551 \
552 if (TARGET_CACHE_BUILTIN) \
553 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
554 } \
555 while (0)
556
557 /* Default target_flags if no switches are specified */
558
559 #ifndef TARGET_DEFAULT
560 #define TARGET_DEFAULT 0
561 #endif
562
563 #ifndef TARGET_CPU_DEFAULT
564 #define TARGET_CPU_DEFAULT 0
565 #endif
566
567 #ifndef TARGET_ENDIAN_DEFAULT
568 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
569 #endif
570
571 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
572 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
573 #endif
574
575 #ifdef IN_LIBGCC2
576 #undef TARGET_64BIT
577 /* Make this compile time constant for libgcc2 */
578 #ifdef __mips64
579 #define TARGET_64BIT 1
580 #else
581 #define TARGET_64BIT 0
582 #endif
583 #endif /* IN_LIBGCC2 */
584
585 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
586 when compiled with hardware floating point. This is because MIPS16
587 code cannot save and restore the floating-point registers, which is
588 important if in a mixed MIPS16/non-MIPS16 environment. */
589
590 #ifdef IN_LIBGCC2
591 #if __mips_hard_float
592 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
593 #endif
594 #endif /* IN_LIBGCC2 */
595
596 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
597
598 #ifndef MULTILIB_ENDIAN_DEFAULT
599 #if TARGET_ENDIAN_DEFAULT == 0
600 #define MULTILIB_ENDIAN_DEFAULT "EL"
601 #else
602 #define MULTILIB_ENDIAN_DEFAULT "EB"
603 #endif
604 #endif
605
606 #ifndef MULTILIB_ISA_DEFAULT
607 # if MIPS_ISA_DEFAULT == 1
608 # define MULTILIB_ISA_DEFAULT "mips1"
609 # else
610 # if MIPS_ISA_DEFAULT == 2
611 # define MULTILIB_ISA_DEFAULT "mips2"
612 # else
613 # if MIPS_ISA_DEFAULT == 3
614 # define MULTILIB_ISA_DEFAULT "mips3"
615 # else
616 # if MIPS_ISA_DEFAULT == 4
617 # define MULTILIB_ISA_DEFAULT "mips4"
618 # else
619 # if MIPS_ISA_DEFAULT == 32
620 # define MULTILIB_ISA_DEFAULT "mips32"
621 # else
622 # if MIPS_ISA_DEFAULT == 33
623 # define MULTILIB_ISA_DEFAULT "mips32r2"
624 # else
625 # if MIPS_ISA_DEFAULT == 64
626 # define MULTILIB_ISA_DEFAULT "mips64"
627 # else
628 # if MIPS_ISA_DEFAULT == 65
629 # define MULTILIB_ISA_DEFAULT "mips64r2"
630 # else
631 # define MULTILIB_ISA_DEFAULT "mips1"
632 # endif
633 # endif
634 # endif
635 # endif
636 # endif
637 # endif
638 # endif
639 # endif
640 #endif
641
642 #ifndef MIPS_ABI_DEFAULT
643 #define MIPS_ABI_DEFAULT ABI_32
644 #endif
645
646 /* Use the most portable ABI flag for the ASM specs. */
647
648 #if MIPS_ABI_DEFAULT == ABI_32
649 #define MULTILIB_ABI_DEFAULT "mabi=32"
650 #endif
651
652 #if MIPS_ABI_DEFAULT == ABI_O64
653 #define MULTILIB_ABI_DEFAULT "mabi=o64"
654 #endif
655
656 #if MIPS_ABI_DEFAULT == ABI_N32
657 #define MULTILIB_ABI_DEFAULT "mabi=n32"
658 #endif
659
660 #if MIPS_ABI_DEFAULT == ABI_64
661 #define MULTILIB_ABI_DEFAULT "mabi=64"
662 #endif
663
664 #if MIPS_ABI_DEFAULT == ABI_EABI
665 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
666 #endif
667
668 #ifndef MULTILIB_DEFAULTS
669 #define MULTILIB_DEFAULTS \
670 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
671 #endif
672
673 /* We must pass -EL to the linker by default for little endian embedded
674 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
675 linker will default to using big-endian output files. The OUTPUT_FORMAT
676 line must be in the linker script, otherwise -EB/-EL will not work. */
677
678 #ifndef ENDIAN_SPEC
679 #if TARGET_ENDIAN_DEFAULT == 0
680 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
681 #else
682 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
683 #endif
684 #endif
685
686 /* A spec condition that matches all non-mips16 -mips arguments. */
687
688 #define MIPS_ISA_LEVEL_OPTION_SPEC \
689 "mips1|mips2|mips3|mips4|mips32*|mips64*"
690
691 /* A spec condition that matches all non-mips16 architecture arguments. */
692
693 #define MIPS_ARCH_OPTION_SPEC \
694 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
695
696 /* A spec that infers a -mips argument from an -march argument,
697 or injects the default if no architecture is specified. */
698
699 #define MIPS_ISA_LEVEL_SPEC \
700 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
701 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
702 %{march=mips2|march=r6000:-mips2} \
703 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
704 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
705 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
706 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
707 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
708 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
709 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
710 |march=xlr|march=loongson3a: -mips64} \
711 %{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
712 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
713
714 /* A spec that infers a -mhard-float or -msoft-float setting from an
715 -march argument. Note that soft-float and hard-float code are not
716 link-compatible. */
717
718 #define MIPS_ARCH_FLOAT_SPEC \
719 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
720 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
721 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
722 |march=octeon|march=xlr: -msoft-float; \
723 march=*: -mhard-float}"
724
725 /* A spec condition that matches 32-bit options. It only works if
726 MIPS_ISA_LEVEL_SPEC has been applied. */
727
728 #define MIPS_32BIT_OPTION_SPEC \
729 "mips1|mips2|mips32*|mgp32"
730
731 #if MIPS_ABI_DEFAULT == ABI_O64 \
732 || MIPS_ABI_DEFAULT == ABI_N32 \
733 || MIPS_ABI_DEFAULT == ABI_64
734 #define OPT_ARCH64 "mabi=32|mgp32:;"
735 #define OPT_ARCH32 "mabi=32|mgp32"
736 #else
737 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
738 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
739 #endif
740
741 /* Support for a compile-time default CPU, et cetera. The rules are:
742 --with-arch is ignored if -march is specified or a -mips is specified
743 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
744 --with-tune is ignored if -mtune is specified; likewise
745 --with-tune-32 and --with-tune-64.
746 --with-abi is ignored if -mabi is specified.
747 --with-float is ignored if -mhard-float or -msoft-float are
748 specified.
749 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
750 specified. */
751 #define OPTION_DEFAULT_SPECS \
752 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
753 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
754 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
755 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
756 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
757 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
758 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
759 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
760 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
761 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
762 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
763 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
764
765
766 /* A spec that infers the -mdsp setting from an -march argument. */
767 #define BASE_DRIVER_SELF_SPECS \
768 "%{!mno-dsp: \
769 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
770 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
771
772 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
773
774 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
775 && ISA_HAS_COND_TRAP)
776
777 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
778
779 /* True if the ABI can only work with 64-bit integer registers. We
780 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
781 otherwise floating-point registers must also be 64-bit. */
782 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
783
784 /* Likewise for 32-bit regs. */
785 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
786
787 /* True if the file format uses 64-bit symbols. At present, this is
788 only true for n64, which uses 64-bit ELF. */
789 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
790
791 /* True if symbols are 64 bits wide. This is usually determined by
792 the ABI's file format, but it can be overridden by -msym32. Note that
793 overriding the size with -msym32 changes the ABI of relocatable objects,
794 although it doesn't change the ABI of a fully-linked object. */
795 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
796 && Pmode == DImode \
797 && !TARGET_SYM32)
798
799 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
800 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
801 || ISA_MIPS4 \
802 || ISA_MIPS64 \
803 || ISA_MIPS64R2)
804
805 /* ISA has branch likely instructions (e.g. mips2). */
806 /* Disable branchlikely for tx39 until compare rewrite. They haven't
807 been generated up to this point. */
808 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
809
810 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
811 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
812 || TARGET_MIPS5400 \
813 || TARGET_MIPS5500 \
814 || TARGET_MIPS7000 \
815 || TARGET_MIPS9000 \
816 || TARGET_MAD \
817 || ISA_MIPS32 \
818 || ISA_MIPS32R2 \
819 || ISA_MIPS64 \
820 || ISA_MIPS64R2) \
821 && !TARGET_MIPS16)
822
823 /* ISA has a three-operand multiplication instruction. */
824 #define ISA_HAS_DMUL3 (TARGET_64BIT \
825 && TARGET_OCTEON \
826 && !TARGET_MIPS16)
827
828 /* ISA has the floating-point conditional move instructions introduced
829 in mips4. */
830 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
831 || ISA_MIPS32 \
832 || ISA_MIPS32R2 \
833 || ISA_MIPS64 \
834 || ISA_MIPS64R2) \
835 && !TARGET_MIPS5500 \
836 && !TARGET_MIPS16)
837
838 /* ISA has the integer conditional move instructions introduced in mips4 and
839 ST Loongson 2E/2F. */
840 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
841
842 /* ISA has LDC1 and SDC1. */
843 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
844
845 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
846 branch on CC, and move (both FP and non-FP) on CC. */
847 #define ISA_HAS_8CC (ISA_MIPS4 \
848 || ISA_MIPS32 \
849 || ISA_MIPS32R2 \
850 || ISA_MIPS64 \
851 || ISA_MIPS64R2)
852
853 /* This is a catch all for other mips4 instructions: indexed load, the
854 FP madd and msub instructions, and the FP recip and recip sqrt
855 instructions. */
856 #define ISA_HAS_FP4 ((ISA_MIPS4 \
857 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
858 || ISA_MIPS64 \
859 || ISA_MIPS64R2) \
860 && !TARGET_MIPS16)
861
862 /* ISA has paired-single instructions. */
863 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
864
865 /* ISA has conditional trap instructions. */
866 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
867 && !TARGET_MIPS16)
868
869 /* ISA has integer multiply-accumulate instructions, madd and msub. */
870 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
871 || ISA_MIPS32R2 \
872 || ISA_MIPS64 \
873 || ISA_MIPS64R2) \
874 && !TARGET_MIPS16)
875
876 /* Integer multiply-accumulate instructions should be generated. */
877 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
878
879 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
880 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
881
882 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
883 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
884
885 /* ISA has floating-point nmadd and nmsub instructions
886 'd = -((a * b) [+-] c)'. */
887 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
888 ((ISA_MIPS4 \
889 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
890 || ISA_MIPS64 \
891 || ISA_MIPS64R2) \
892 && (!TARGET_MIPS5400 || TARGET_MAD) \
893 && !TARGET_MIPS16)
894
895 /* ISA has floating-point nmadd and nmsub instructions
896 'c = -((a * b) [+-] c)'. */
897 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
898 TARGET_LOONGSON_2EF
899
900 /* ISA has count leading zeroes/ones instruction (not implemented). */
901 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
902 || ISA_MIPS32R2 \
903 || ISA_MIPS64 \
904 || ISA_MIPS64R2) \
905 && !TARGET_MIPS16)
906
907 /* ISA has three operand multiply instructions that put
908 the high part in an accumulator: mulhi or mulhiu. */
909 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
910 || TARGET_MIPS5500 \
911 || TARGET_SR71K) \
912 && !TARGET_MIPS16)
913
914 /* ISA has three operand multiply instructions that
915 negates the result and puts the result in an accumulator. */
916 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
917 || TARGET_MIPS5500 \
918 || TARGET_SR71K) \
919 && !TARGET_MIPS16)
920
921 /* ISA has three operand multiply instructions that subtracts the
922 result from a 4th operand and puts the result in an accumulator. */
923 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
924 || TARGET_MIPS5500 \
925 || TARGET_SR71K) \
926 && !TARGET_MIPS16)
927
928 /* ISA has three operand multiply instructions that the result
929 from a 4th operand and puts the result in an accumulator. */
930 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
931 || TARGET_MIPS4130 \
932 || TARGET_MIPS5400 \
933 || TARGET_MIPS5500 \
934 || TARGET_SR71K) \
935 && !TARGET_MIPS16)
936
937 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
938 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
939 || TARGET_MIPS4130) \
940 && !TARGET_MIPS16)
941
942 /* ISA has the "ror" (rotate right) instructions. */
943 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
944 || ISA_MIPS64R2 \
945 || TARGET_MIPS5400 \
946 || TARGET_MIPS5500 \
947 || TARGET_SR71K \
948 || TARGET_SMARTMIPS) \
949 && !TARGET_MIPS16)
950
951 /* ISA has data prefetch instructions. This controls use of 'pref'. */
952 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
953 || TARGET_LOONGSON_2EF \
954 || ISA_MIPS32 \
955 || ISA_MIPS32R2 \
956 || ISA_MIPS64 \
957 || ISA_MIPS64R2) \
958 && !TARGET_MIPS16)
959
960 /* ISA has data indexed prefetch instructions. This controls use of
961 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
962 (prefx is a cop1x instruction, so can only be used if FP is
963 enabled.) */
964 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
965 || ISA_MIPS32R2 \
966 || ISA_MIPS64 \
967 || ISA_MIPS64R2) \
968 && !TARGET_MIPS16)
969
970 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
971 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
972 also requires TARGET_DOUBLE_FLOAT. */
973 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
974
975 /* ISA includes the MIPS32r2 seb and seh instructions. */
976 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
977 || ISA_MIPS64R2) \
978 && !TARGET_MIPS16)
979
980 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
981 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
982 || ISA_MIPS64R2) \
983 && !TARGET_MIPS16)
984
985 /* ISA has instructions for accessing top part of 64-bit fp regs. */
986 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
987 && (ISA_MIPS32R2 \
988 || ISA_MIPS64R2))
989
990 /* ISA has lwxs instruction (load w/scaled index address. */
991 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
992
993 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
994 #define ISA_HAS_LBX (TARGET_OCTEON2)
995 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
996 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
997 #define ISA_HAS_LHUX (TARGET_OCTEON2)
998 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
999 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1000 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1001 && TARGET_64BIT)
1002
1003 /* The DSP ASE is available. */
1004 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1005
1006 /* Revision 2 of the DSP ASE is available. */
1007 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1008
1009 /* True if the result of a load is not available to the next instruction.
1010 A nop will then be needed between instructions like "lw $4,..."
1011 and "addiu $4,$4,1". */
1012 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1013 && !TARGET_MIPS3900 \
1014 && !TARGET_MIPS16)
1015
1016 /* Likewise mtc1 and mfc1. */
1017 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1018 && !TARGET_LOONGSON_2EF)
1019
1020 /* Likewise floating-point comparisons. */
1021 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1022 && !TARGET_LOONGSON_2EF)
1023
1024 /* True if mflo and mfhi can be immediately followed by instructions
1025 which write to the HI and LO registers.
1026
1027 According to MIPS specifications, MIPS ISAs I, II, and III need
1028 (at least) two instructions between the reads of HI/LO and
1029 instructions which write them, and later ISAs do not. Contradicting
1030 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1031 the UM for the NEC Vr5000) document needing the instructions between
1032 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1033 MIPS64 and later ISAs to have the interlocks, plus any specific
1034 earlier-ISA CPUs for which CPU documentation declares that the
1035 instructions are really interlocked. */
1036 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1037 || ISA_MIPS32R2 \
1038 || ISA_MIPS64 \
1039 || ISA_MIPS64R2 \
1040 || TARGET_MIPS5500 \
1041 || TARGET_LOONGSON_2EF)
1042
1043 /* ISA includes synci, jr.hb and jalr.hb. */
1044 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1045 || ISA_MIPS64R2) \
1046 && !TARGET_MIPS16)
1047
1048 /* ISA includes sync. */
1049 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1050 #define GENERATE_SYNC \
1051 (target_flags_explicit & MASK_LLSC \
1052 ? TARGET_LLSC && !TARGET_MIPS16 \
1053 : ISA_HAS_SYNC)
1054
1055 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1056 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1057 instructions. */
1058 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1059 #define GENERATE_LL_SC \
1060 (target_flags_explicit & MASK_LLSC \
1061 ? TARGET_LLSC && !TARGET_MIPS16 \
1062 : ISA_HAS_LL_SC)
1063
1064 #define ISA_HAS_SWAP (TARGET_XLP)
1065 #define ISA_HAS_LDADD (TARGET_XLP)
1066
1067 /* ISA includes the baddu instruction. */
1068 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1069
1070 /* ISA includes the bbit* instructions. */
1071 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1072
1073 /* ISA includes the cins instruction. */
1074 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1075
1076 /* ISA includes the exts instruction. */
1077 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1078
1079 /* ISA includes the seq and sne instructions. */
1080 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1081
1082 /* ISA includes the pop instruction. */
1083 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1084
1085 /* The CACHE instruction is available in non-MIPS16 code. */
1086 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1087
1088 /* The CACHE instruction is available. */
1089 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1090 \f
1091 /* Tell collect what flags to pass to nm. */
1092 #ifndef NM_FLAGS
1093 #define NM_FLAGS "-Bn"
1094 #endif
1095
1096 \f
1097 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1098 the assembler. It may be overridden by subtargets.
1099
1100 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1101 COFF debugging info. */
1102
1103 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1104 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1105 %{g} %{g0} %{g1} %{g2} %{g3} \
1106 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1107 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1108 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1109 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1110 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1111 #endif
1112
1113 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1114 overridden by subtargets. */
1115
1116 #ifndef SUBTARGET_ASM_SPEC
1117 #define SUBTARGET_ASM_SPEC ""
1118 #endif
1119
1120 #undef ASM_SPEC
1121 #define ASM_SPEC "\
1122 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1123 %{mips32*} %{mips64*} \
1124 %{mips16} %{mno-mips16:-no-mips16} \
1125 %{mips3d} %{mno-mips3d:-no-mips3d} \
1126 %{mdmx} %{mno-mdmx:-no-mdmx} \
1127 %{mdsp} %{mno-dsp} \
1128 %{mdspr2} %{mno-dspr2} \
1129 %{mmcu} %{mno-mcu} \
1130 %{msmartmips} %{mno-smartmips} \
1131 %{mmt} %{mno-mt} \
1132 %{mfix-vr4120} %{mfix-vr4130} \
1133 %{mfix-24k} \
1134 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1135 %(subtarget_asm_debugging_spec) \
1136 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1137 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1138 %{mfp32} %{mfp64} \
1139 %{mshared} %{mno-shared} \
1140 %{msym32} %{mno-sym32} \
1141 %{mtune=*} \
1142 %(subtarget_asm_spec)"
1143
1144 /* Extra switches sometimes passed to the linker. */
1145
1146 #ifndef LINK_SPEC
1147 #define LINK_SPEC "\
1148 %(endian_spec) \
1149 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1150 %{shared}"
1151 #endif /* LINK_SPEC defined */
1152
1153
1154 /* Specs for the compiler proper */
1155
1156 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1157 overridden by subtargets. */
1158 #ifndef SUBTARGET_CC1_SPEC
1159 #define SUBTARGET_CC1_SPEC ""
1160 #endif
1161
1162 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1163
1164 #undef CC1_SPEC
1165 #define CC1_SPEC "\
1166 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1167 %(subtarget_cc1_spec)"
1168
1169 /* Preprocessor specs. */
1170
1171 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1172 overridden by subtargets. */
1173 #ifndef SUBTARGET_CPP_SPEC
1174 #define SUBTARGET_CPP_SPEC ""
1175 #endif
1176
1177 #define CPP_SPEC "%(subtarget_cpp_spec)"
1178
1179 /* This macro defines names of additional specifications to put in the specs
1180 that can be used in various specifications like CC1_SPEC. Its definition
1181 is an initializer with a subgrouping for each command option.
1182
1183 Each subgrouping contains a string constant, that defines the
1184 specification name, and a string constant that used by the GCC driver
1185 program.
1186
1187 Do not define this macro if it does not need to do anything. */
1188
1189 #define EXTRA_SPECS \
1190 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1191 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1192 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1193 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1194 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1195 { "endian_spec", ENDIAN_SPEC }, \
1196 SUBTARGET_EXTRA_SPECS
1197
1198 #ifndef SUBTARGET_EXTRA_SPECS
1199 #define SUBTARGET_EXTRA_SPECS
1200 #endif
1201 \f
1202 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1203 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1204
1205 #ifndef PREFERRED_DEBUGGING_TYPE
1206 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1207 #endif
1208
1209 /* The size of DWARF addresses should be the same as the size of symbols
1210 in the target file format. They shouldn't depend on things like -msym32,
1211 because many DWARF consumers do not allow the mixture of address sizes
1212 that one would then get from linking -msym32 code with -msym64 code.
1213
1214 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1215 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1216 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1217
1218 /* By default, turn on GDB extensions. */
1219 #define DEFAULT_GDB_EXTENSIONS 1
1220
1221 /* Local compiler-generated symbols must have a prefix that the assembler
1222 understands. By default, this is $, although some targets (e.g.,
1223 NetBSD-ELF) need to override this. */
1224
1225 #ifndef LOCAL_LABEL_PREFIX
1226 #define LOCAL_LABEL_PREFIX "$"
1227 #endif
1228
1229 /* By default on the mips, external symbols do not have an underscore
1230 prepended, but some targets (e.g., NetBSD) require this. */
1231
1232 #ifndef USER_LABEL_PREFIX
1233 #define USER_LABEL_PREFIX ""
1234 #endif
1235
1236 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1237 since the length can run past this up to a continuation point. */
1238 #undef DBX_CONTIN_LENGTH
1239 #define DBX_CONTIN_LENGTH 1500
1240
1241 /* How to renumber registers for dbx and gdb. */
1242 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1243
1244 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1245 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1246
1247 /* The DWARF 2 CFA column which tracks the return address. */
1248 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1249
1250 /* Before the prologue, RA lives in r31. */
1251 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1252
1253 /* Describe how we implement __builtin_eh_return. */
1254 #define EH_RETURN_DATA_REGNO(N) \
1255 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1256
1257 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1258
1259 #define EH_USES(N) mips_eh_uses (N)
1260
1261 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1262 The default for this in 64-bit mode is 8, which causes problems with
1263 SFmode register saves. */
1264 #define DWARF_CIE_DATA_ALIGNMENT -4
1265
1266 /* Correct the offset of automatic variables and arguments. Note that
1267 the MIPS debug format wants all automatic variables and arguments
1268 to be in terms of the virtual frame pointer (stack pointer before
1269 any adjustment in the function), while the MIPS 3.0 linker wants
1270 the frame pointer to be the stack pointer after the initial
1271 adjustment. */
1272
1273 #define DEBUGGER_AUTO_OFFSET(X) \
1274 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1275 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1276 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1277 \f
1278 /* Target machine storage layout */
1279
1280 #define BITS_BIG_ENDIAN 0
1281 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1282 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1283
1284 #define MAX_BITS_PER_WORD 64
1285
1286 /* Width of a word, in units (bytes). */
1287 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1288 #ifndef IN_LIBGCC2
1289 #define MIN_UNITS_PER_WORD 4
1290 #endif
1291
1292 /* For MIPS, width of a floating point register. */
1293 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1294
1295 /* The number of consecutive floating-point registers needed to store the
1296 largest format supported by the FPU. */
1297 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1298
1299 /* The number of consecutive floating-point registers needed to store the
1300 smallest format supported by the FPU. */
1301 #define MIN_FPRS_PER_FMT \
1302 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1303 ? 1 : MAX_FPRS_PER_FMT)
1304
1305 /* The largest size of value that can be held in floating-point
1306 registers and moved with a single instruction. */
1307 #define UNITS_PER_HWFPVALUE \
1308 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1309
1310 /* The largest size of value that can be held in floating-point
1311 registers. */
1312 #define UNITS_PER_FPVALUE \
1313 (TARGET_SOFT_FLOAT_ABI ? 0 \
1314 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1315 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1316
1317 /* The number of bytes in a double. */
1318 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1319
1320 /* Set the sizes of the core types. */
1321 #define SHORT_TYPE_SIZE 16
1322 #define INT_TYPE_SIZE 32
1323 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1324 #define LONG_LONG_TYPE_SIZE 64
1325
1326 #define FLOAT_TYPE_SIZE 32
1327 #define DOUBLE_TYPE_SIZE 64
1328 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1329
1330 /* Define the sizes of fixed-point types. */
1331 #define SHORT_FRACT_TYPE_SIZE 8
1332 #define FRACT_TYPE_SIZE 16
1333 #define LONG_FRACT_TYPE_SIZE 32
1334 #define LONG_LONG_FRACT_TYPE_SIZE 64
1335
1336 #define SHORT_ACCUM_TYPE_SIZE 16
1337 #define ACCUM_TYPE_SIZE 32
1338 #define LONG_ACCUM_TYPE_SIZE 64
1339 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1340 doesn't support 128-bit integers for MIPS32 currently. */
1341 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1342
1343 /* long double is not a fixed mode, but the idea is that, if we
1344 support long double, we also want a 128-bit integer type. */
1345 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1346
1347 #ifdef IN_LIBGCC2
1348 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1349 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1350 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1351 # else
1352 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1353 # endif
1354 #endif
1355
1356 /* Width in bits of a pointer. */
1357 #ifndef POINTER_SIZE
1358 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1359 #endif
1360
1361 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1362 #define PARM_BOUNDARY BITS_PER_WORD
1363
1364 /* Allocation boundary (in *bits*) for the code of a function. */
1365 #define FUNCTION_BOUNDARY 32
1366
1367 /* Alignment of field after `int : 0' in a structure. */
1368 #define EMPTY_FIELD_BOUNDARY 32
1369
1370 /* Every structure's size must be a multiple of this. */
1371 /* 8 is observed right on a DECstation and on riscos 4.02. */
1372 #define STRUCTURE_SIZE_BOUNDARY 8
1373
1374 /* There is no point aligning anything to a rounder boundary than this. */
1375 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1376
1377 /* All accesses must be aligned. */
1378 #define STRICT_ALIGNMENT 1
1379
1380 /* Define this if you wish to imitate the way many other C compilers
1381 handle alignment of bitfields and the structures that contain
1382 them.
1383
1384 The behavior is that the type written for a bit-field (`int',
1385 `short', or other integer type) imposes an alignment for the
1386 entire structure, as if the structure really did contain an
1387 ordinary field of that type. In addition, the bit-field is placed
1388 within the structure so that it would fit within such a field,
1389 not crossing a boundary for it.
1390
1391 Thus, on most machines, a bit-field whose type is written as `int'
1392 would not cross a four-byte boundary, and would force four-byte
1393 alignment for the whole structure. (The alignment used may not
1394 be four bytes; it is controlled by the other alignment
1395 parameters.)
1396
1397 If the macro is defined, its definition should be a C expression;
1398 a nonzero value for the expression enables this behavior. */
1399
1400 #define PCC_BITFIELD_TYPE_MATTERS 1
1401
1402 /* If defined, a C expression to compute the alignment given to a
1403 constant that is being placed in memory. CONSTANT is the constant
1404 and ALIGN is the alignment that the object would ordinarily have.
1405 The value of this macro is used instead of that alignment to align
1406 the object.
1407
1408 If this macro is not defined, then ALIGN is used.
1409
1410 The typical use of this macro is to increase alignment for string
1411 constants to be word aligned so that `strcpy' calls that copy
1412 constants can be done inline. */
1413
1414 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1415 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1416 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1417
1418 /* If defined, a C expression to compute the alignment for a static
1419 variable. TYPE is the data type, and ALIGN is the alignment that
1420 the object would ordinarily have. The value of this macro is used
1421 instead of that alignment to align the object.
1422
1423 If this macro is not defined, then ALIGN is used.
1424
1425 One use of this macro is to increase alignment of medium-size
1426 data to make it all fit in fewer cache lines. Another is to
1427 cause character arrays to be word-aligned so that `strcpy' calls
1428 that copy constants to character arrays can be done inline. */
1429
1430 #undef DATA_ALIGNMENT
1431 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1432 ((((ALIGN) < BITS_PER_WORD) \
1433 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1434 || TREE_CODE (TYPE) == UNION_TYPE \
1435 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1436
1437 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1438 character arrays to be word-aligned so that `strcpy' calls that copy
1439 constants to character arrays can be done inline, and 'strcmp' can be
1440 optimised to use word loads. */
1441 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1442 DATA_ALIGNMENT (TYPE, ALIGN)
1443
1444 #define PAD_VARARGS_DOWN \
1445 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1446
1447 /* Define if operations between registers always perform the operation
1448 on the full register even if a narrower mode is specified. */
1449 #define WORD_REGISTER_OPERATIONS
1450
1451 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1452 moves. All other references are zero extended. */
1453 #define LOAD_EXTEND_OP(MODE) \
1454 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1455 ? SIGN_EXTEND : ZERO_EXTEND)
1456
1457 /* Define this macro if it is advisable to hold scalars in registers
1458 in a wider mode than that declared by the program. In such cases,
1459 the value is constrained to be within the bounds of the declared
1460 type, but kept valid in the wider mode. The signedness of the
1461 extension may differ from that of the type. */
1462
1463 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1464 if (GET_MODE_CLASS (MODE) == MODE_INT \
1465 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1466 { \
1467 if ((MODE) == SImode) \
1468 (UNSIGNEDP) = 0; \
1469 (MODE) = Pmode; \
1470 }
1471
1472 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1473 Extensions of pointers to word_mode must be signed. */
1474 #define POINTERS_EXTEND_UNSIGNED false
1475
1476 /* Define if loading short immediate values into registers sign extends. */
1477 #define SHORT_IMMEDIATES_SIGN_EXTEND
1478
1479 /* The [d]clz instructions have the natural values at 0. */
1480
1481 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1482 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1483 \f
1484 /* Standard register usage. */
1485
1486 /* Number of hardware registers. We have:
1487
1488 - 32 integer registers
1489 - 32 floating point registers
1490 - 8 condition code registers
1491 - 2 accumulator registers (hi and lo)
1492 - 32 registers each for coprocessors 0, 2 and 3
1493 - 4 fake registers:
1494 - ARG_POINTER_REGNUM
1495 - FRAME_POINTER_REGNUM
1496 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1497 - CPRESTORE_SLOT_REGNUM
1498 - 2 dummy entries that were used at various times in the past.
1499 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1500 - 6 DSP control registers */
1501
1502 #define FIRST_PSEUDO_REGISTER 188
1503
1504 /* By default, fix the kernel registers ($26 and $27), the global
1505 pointer ($28) and the stack pointer ($29). This can change
1506 depending on the command-line options.
1507
1508 Regarding coprocessor registers: without evidence to the contrary,
1509 it's best to assume that each coprocessor register has a unique
1510 use. This can be overridden, in, e.g., mips_option_override or
1511 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1512 inappropriate for a particular target. */
1513
1514 #define FIXED_REGISTERS \
1515 { \
1516 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1517 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1518 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1520 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1521 /* COP0 registers */ \
1522 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1523 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1524 /* COP2 registers */ \
1525 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1526 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1527 /* COP3 registers */ \
1528 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1529 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1530 /* 6 DSP accumulator registers & 6 control registers */ \
1531 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1532 }
1533
1534
1535 /* Set up this array for o32 by default.
1536
1537 Note that we don't mark $31 as a call-clobbered register. The idea is
1538 that it's really the call instructions themselves which clobber $31.
1539 We don't care what the called function does with it afterwards.
1540
1541 This approach makes it easier to implement sibcalls. Unlike normal
1542 calls, sibcalls don't clobber $31, so the register reaches the
1543 called function in tact. EPILOGUE_USES says that $31 is useful
1544 to the called function. */
1545
1546 #define CALL_USED_REGISTERS \
1547 { \
1548 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1549 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1551 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1553 /* COP0 registers */ \
1554 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1555 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1556 /* COP2 registers */ \
1557 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1558 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1559 /* COP3 registers */ \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1561 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1562 /* 6 DSP accumulator registers & 6 control registers */ \
1563 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1564 }
1565
1566
1567 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1568
1569 #define CALL_REALLY_USED_REGISTERS \
1570 { /* General registers. */ \
1571 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1572 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1573 /* Floating-point registers. */ \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1575 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1576 /* Others. */ \
1577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1578 /* COP0 registers */ \
1579 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1580 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1581 /* COP2 registers */ \
1582 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1583 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1584 /* COP3 registers */ \
1585 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1587 /* 6 DSP accumulator registers & 6 control registers */ \
1588 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1589 }
1590
1591 /* Internal macros to classify a register number as to whether it's a
1592 general purpose register, a floating point register, a
1593 multiply/divide register, or a status register. */
1594
1595 #define GP_REG_FIRST 0
1596 #define GP_REG_LAST 31
1597 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1598 #define GP_DBX_FIRST 0
1599 #define K0_REG_NUM (GP_REG_FIRST + 26)
1600 #define K1_REG_NUM (GP_REG_FIRST + 27)
1601 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1602
1603 #define FP_REG_FIRST 32
1604 #define FP_REG_LAST 63
1605 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1606 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1607
1608 #define MD_REG_FIRST 64
1609 #define MD_REG_LAST 65
1610 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1611 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1612
1613 /* The DWARF 2 CFA column which tracks the return address from a
1614 signal handler context. This means that to maintain backwards
1615 compatibility, no hard register can be assigned this column if it
1616 would need to be handled by the DWARF unwinder. */
1617 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1618
1619 #define ST_REG_FIRST 67
1620 #define ST_REG_LAST 74
1621 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1622
1623
1624 /* FIXME: renumber. */
1625 #define COP0_REG_FIRST 80
1626 #define COP0_REG_LAST 111
1627 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1628
1629 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1630 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1631 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1632
1633 #define COP2_REG_FIRST 112
1634 #define COP2_REG_LAST 143
1635 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1636
1637 #define COP3_REG_FIRST 144
1638 #define COP3_REG_LAST 175
1639 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1640 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1641 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1642
1643 #define DSP_ACC_REG_FIRST 176
1644 #define DSP_ACC_REG_LAST 181
1645 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1646
1647 #define AT_REGNUM (GP_REG_FIRST + 1)
1648 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1649 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1650
1651 /* A few bitfield locations for the coprocessor registers. */
1652 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1653 the cause register for the EIC interrupt mode. */
1654 #define CAUSE_IPL 10
1655 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1656 #define SR_IPL 10
1657 /* Exception Level is at bit 1 of the status register. */
1658 #define SR_EXL 1
1659 /* Interrupt Enable is at bit 0 of the status register. */
1660 #define SR_IE 0
1661
1662 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1663 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1664 should be used instead. */
1665 #define FPSW_REGNUM ST_REG_FIRST
1666
1667 #define GP_REG_P(REGNO) \
1668 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1669 #define M16_REG_P(REGNO) \
1670 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1671 #define FP_REG_P(REGNO) \
1672 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1673 #define MD_REG_P(REGNO) \
1674 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1675 #define ST_REG_P(REGNO) \
1676 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1677 #define COP0_REG_P(REGNO) \
1678 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1679 #define COP2_REG_P(REGNO) \
1680 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1681 #define COP3_REG_P(REGNO) \
1682 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1683 #define ALL_COP_REG_P(REGNO) \
1684 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1685 /* Test if REGNO is one of the 6 new DSP accumulators. */
1686 #define DSP_ACC_REG_P(REGNO) \
1687 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1688 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1689 #define ACC_REG_P(REGNO) \
1690 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1691
1692 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1693
1694 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1695 to initialize the mips16 gp pseudo register. */
1696 #define CONST_GP_P(X) \
1697 (GET_CODE (X) == CONST \
1698 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1699 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1700
1701 /* Return coprocessor number from register number. */
1702
1703 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1704 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1705 : COP3_REG_P (REGNO) ? '3' : '?')
1706
1707
1708 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1709
1710 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1711 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1712
1713 #define MODES_TIEABLE_P mips_modes_tieable_p
1714
1715 /* Register to use for pushing function arguments. */
1716 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1717
1718 /* These two registers don't really exist: they get eliminated to either
1719 the stack or hard frame pointer. */
1720 #define ARG_POINTER_REGNUM 77
1721 #define FRAME_POINTER_REGNUM 78
1722
1723 /* $30 is not available on the mips16, so we use $17 as the frame
1724 pointer. */
1725 #define HARD_FRAME_POINTER_REGNUM \
1726 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1727
1728 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1729 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1730
1731 /* Register in which static-chain is passed to a function. */
1732 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1733
1734 /* Registers used as temporaries in prologue/epilogue code:
1735
1736 - If a MIPS16 PIC function needs access to _gp, it first loads
1737 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1738
1739 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1740 register. The register must not conflict with MIPS16_PIC_TEMP.
1741
1742 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1743 register.
1744
1745 If we're generating MIPS16 code, these registers must come from the
1746 core set of 8. The prologue registers mustn't conflict with any
1747 incoming arguments, the static chain pointer, or the frame pointer.
1748 The epilogue temporary mustn't conflict with the return registers,
1749 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1750 or the EH data registers.
1751
1752 If we're generating interrupt handlers, we use K0 as a temporary register
1753 in prologue/epilogue code. */
1754
1755 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1756 #define MIPS_PROLOGUE_TEMP_REGNUM \
1757 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1758 #define MIPS_EPILOGUE_TEMP_REGNUM \
1759 (cfun->machine->interrupt_handler_p \
1760 ? K0_REG_NUM \
1761 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1762
1763 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1764 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1765 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1766
1767 /* Define this macro if it is as good or better to call a constant
1768 function address than to call an address kept in a register. */
1769 #define NO_FUNCTION_CSE 1
1770
1771 /* The ABI-defined global pointer. Sometimes we use a different
1772 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1773 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1774
1775 /* We normally use $28 as the global pointer. However, when generating
1776 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1777 register instead. They can then avoid saving and restoring $28
1778 and perhaps avoid using a frame at all.
1779
1780 When a leaf function uses something other than $28, mips_expand_prologue
1781 will modify pic_offset_table_rtx in place. Take the register number
1782 from there after reload. */
1783 #define PIC_OFFSET_TABLE_REGNUM \
1784 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1785 \f
1786 /* Define the classes of registers for register constraints in the
1787 machine description. Also define ranges of constants.
1788
1789 One of the classes must always be named ALL_REGS and include all hard regs.
1790 If there is more than one class, another class must be named NO_REGS
1791 and contain no registers.
1792
1793 The name GENERAL_REGS must be the name of a class (or an alias for
1794 another name such as ALL_REGS). This is the class of registers
1795 that is allowed by "g" or "r" in a register constraint.
1796 Also, registers outside this class are allocated only when
1797 instructions express preferences for them.
1798
1799 The classes must be numbered in nondecreasing order; that is,
1800 a larger-numbered class must never be contained completely
1801 in a smaller-numbered class.
1802
1803 For any two classes, it is very desirable that there be another
1804 class that represents their union. */
1805
1806 enum reg_class
1807 {
1808 NO_REGS, /* no registers in set */
1809 M16_REGS, /* mips16 directly accessible registers */
1810 T_REG, /* mips16 T register ($24) */
1811 M16_T_REGS, /* mips16 registers plus T register */
1812 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1813 V1_REG, /* Register $v1 ($3) used for TLS access. */
1814 LEA_REGS, /* Every GPR except $25 */
1815 GR_REGS, /* integer registers */
1816 FP_REGS, /* floating point registers */
1817 MD0_REG, /* first multiply/divide register */
1818 MD1_REG, /* second multiply/divide register */
1819 MD_REGS, /* multiply/divide registers (hi/lo) */
1820 COP0_REGS, /* generic coprocessor classes */
1821 COP2_REGS,
1822 COP3_REGS,
1823 ST_REGS, /* status registers (fp status) */
1824 DSP_ACC_REGS, /* DSP accumulator registers */
1825 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1826 FRAME_REGS, /* $arg and $frame */
1827 GR_AND_MD0_REGS, /* union classes */
1828 GR_AND_MD1_REGS,
1829 GR_AND_MD_REGS,
1830 GR_AND_ACC_REGS,
1831 ALL_REGS, /* all registers */
1832 LIM_REG_CLASSES /* max value + 1 */
1833 };
1834
1835 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1836
1837 #define GENERAL_REGS GR_REGS
1838
1839 /* An initializer containing the names of the register classes as C
1840 string constants. These names are used in writing some of the
1841 debugging dumps. */
1842
1843 #define REG_CLASS_NAMES \
1844 { \
1845 "NO_REGS", \
1846 "M16_REGS", \
1847 "T_REG", \
1848 "M16_T_REGS", \
1849 "PIC_FN_ADDR_REG", \
1850 "V1_REG", \
1851 "LEA_REGS", \
1852 "GR_REGS", \
1853 "FP_REGS", \
1854 "MD0_REG", \
1855 "MD1_REG", \
1856 "MD_REGS", \
1857 /* coprocessor registers */ \
1858 "COP0_REGS", \
1859 "COP2_REGS", \
1860 "COP3_REGS", \
1861 "ST_REGS", \
1862 "DSP_ACC_REGS", \
1863 "ACC_REGS", \
1864 "FRAME_REGS", \
1865 "GR_AND_MD0_REGS", \
1866 "GR_AND_MD1_REGS", \
1867 "GR_AND_MD_REGS", \
1868 "GR_AND_ACC_REGS", \
1869 "ALL_REGS" \
1870 }
1871
1872 /* An initializer containing the contents of the register classes,
1873 as integers which are bit masks. The Nth integer specifies the
1874 contents of class N. The way the integer MASK is interpreted is
1875 that register R is in the class if `MASK & (1 << R)' is 1.
1876
1877 When the machine has more than 32 registers, an integer does not
1878 suffice. Then the integers are replaced by sub-initializers,
1879 braced groupings containing several integers. Each
1880 sub-initializer must be suitable as an initializer for the type
1881 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1882
1883 #define REG_CLASS_CONTENTS \
1884 { \
1885 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1886 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1887 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1888 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1889 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1890 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1891 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1892 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1893 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1894 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1895 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1896 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1897 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1898 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1899 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1900 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1901 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1902 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1903 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1904 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1905 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1906 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1907 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1908 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1909 }
1910
1911
1912 /* A C expression whose value is a register class containing hard
1913 register REGNO. In general there is more that one such class;
1914 choose a class which is "minimal", meaning that no smaller class
1915 also contains the register. */
1916
1917 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1918
1919 /* A macro whose definition is the name of the class to which a
1920 valid base register must belong. A base register is one used in
1921 an address which is the register value plus a displacement. */
1922
1923 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1924
1925 /* A macro whose definition is the name of the class to which a
1926 valid index register must belong. An index register is one used
1927 in an address where its value is either multiplied by a scale
1928 factor or added to another register (as well as added to a
1929 displacement). */
1930
1931 #define INDEX_REG_CLASS NO_REGS
1932
1933 /* We generally want to put call-clobbered registers ahead of
1934 call-saved ones. (IRA expects this.) */
1935
1936 #define REG_ALLOC_ORDER \
1937 { /* Accumulator registers. When GPRs and accumulators have equal \
1938 cost, we generally prefer to use accumulators. For example, \
1939 a division of multiplication result is better allocated to LO, \
1940 so that we put the MFLO at the point of use instead of at the \
1941 point of definition. It's also needed if we're to take advantage \
1942 of the extra accumulators available with -mdspr2. In some cases, \
1943 it can also help to reduce register pressure. */ \
1944 64, 65,176,177,178,179,180,181, \
1945 /* Call-clobbered GPRs. */ \
1946 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1947 24, 25, 31, \
1948 /* The global pointer. This is call-clobbered for o32 and o64 \
1949 abicalls, call-saved for n32 and n64 abicalls, and a program \
1950 invariant otherwise. Putting it between the call-clobbered \
1951 and call-saved registers should cope with all eventualities. */ \
1952 28, \
1953 /* Call-saved GPRs. */ \
1954 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1955 /* GPRs that can never be exposed to the register allocator. */ \
1956 0, 26, 27, 29, \
1957 /* Call-clobbered FPRs. */ \
1958 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1959 48, 49, 50, 51, \
1960 /* FPRs that are usually call-saved. The odd ones are actually \
1961 call-clobbered for n32, but listing them ahead of the even \
1962 registers might encourage the register allocator to fragment \
1963 the available FPR pairs. We need paired FPRs to store long \
1964 doubles, so it isn't clear that using a different order \
1965 for n32 would be a win. */ \
1966 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1967 /* None of the remaining classes have defined call-saved \
1968 registers. */ \
1969 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1970 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1971 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1972 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1973 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1974 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1975 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1976 182,183,184,185,186,187 \
1977 }
1978
1979 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1980 to be rearranged based on a particular function. On the mips16, we
1981 want to allocate $24 (T_REG) before other registers for
1982 instructions for which it is possible. */
1983
1984 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
1985
1986 /* True if VALUE is an unsigned 6-bit number. */
1987
1988 #define UIMM6_OPERAND(VALUE) \
1989 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1990
1991 /* True if VALUE is a signed 10-bit number. */
1992
1993 #define IMM10_OPERAND(VALUE) \
1994 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1995
1996 /* True if VALUE is a signed 16-bit number. */
1997
1998 #define SMALL_OPERAND(VALUE) \
1999 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2000
2001 /* True if VALUE is an unsigned 16-bit number. */
2002
2003 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2004 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2005
2006 /* True if VALUE can be loaded into a register using LUI. */
2007
2008 #define LUI_OPERAND(VALUE) \
2009 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2010 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2011
2012 /* Return a value X with the low 16 bits clear, and such that
2013 VALUE - X is a signed 16-bit value. */
2014
2015 #define CONST_HIGH_PART(VALUE) \
2016 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2017
2018 #define CONST_LOW_PART(VALUE) \
2019 ((VALUE) - CONST_HIGH_PART (VALUE))
2020
2021 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2022 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2023 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2024
2025 /* The HI and LO registers can only be reloaded via the general
2026 registers. Condition code registers can only be loaded to the
2027 general registers, and from the floating point registers. */
2028
2029 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2030 mips_secondary_reload_class (CLASS, MODE, X, true)
2031 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2032 mips_secondary_reload_class (CLASS, MODE, X, false)
2033
2034 /* Return the maximum number of consecutive registers
2035 needed to represent mode MODE in a register of class CLASS. */
2036
2037 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2038
2039 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2040 mips_cannot_change_mode_class (FROM, TO, CLASS)
2041 \f
2042 /* Stack layout; function entry, exit and calling. */
2043
2044 #define STACK_GROWS_DOWNWARD
2045
2046 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2047
2048 /* Size of the area allocated in the frame to save the GP. */
2049
2050 #define MIPS_GP_SAVE_AREA_SIZE \
2051 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2052
2053 /* The offset of the first local variable from the frame pointer. See
2054 mips_compute_frame_info for details about the frame layout. */
2055
2056 #define STARTING_FRAME_OFFSET \
2057 (FRAME_GROWS_DOWNWARD \
2058 ? 0 \
2059 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2060
2061 #define RETURN_ADDR_RTX mips_return_addr
2062
2063 /* Mask off the MIPS16 ISA bit in unwind addresses.
2064
2065 The reason for this is a little subtle. When unwinding a call,
2066 we are given the call's return address, which on most targets
2067 is the address of the following instruction. However, what we
2068 actually want to find is the EH region for the call itself.
2069 The target-independent unwind code therefore searches for "RA - 1".
2070
2071 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2072 RA - 1 is therefore the real (even-valued) start of the return
2073 instruction. EH region labels are usually odd-valued MIPS16 symbols
2074 too, so a search for an even address within a MIPS16 region would
2075 usually work.
2076
2077 However, there is an exception. If the end of an EH region is also
2078 the end of a function, the end label is allowed to be even. This is
2079 necessary because a following non-MIPS16 function may also need EH
2080 information for its first instruction.
2081
2082 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2083 non-ISA-encoded address. This probably isn't ideal, but it is
2084 the traditional (legacy) behavior. It is therefore only safe
2085 to search MIPS EH regions for an _odd-valued_ address.
2086
2087 Masking off the ISA bit means that the target-independent code
2088 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2089 #define MASK_RETURN_ADDR GEN_INT (-2)
2090
2091
2092 /* Similarly, don't use the least-significant bit to tell pointers to
2093 code from vtable index. */
2094
2095 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2096
2097 /* The eliminations to $17 are only used for mips16 code. See the
2098 definition of HARD_FRAME_POINTER_REGNUM. */
2099
2100 #define ELIMINABLE_REGS \
2101 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2102 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2103 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2104 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2105 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2106 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2107
2108 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2109 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2110
2111 /* Allocate stack space for arguments at the beginning of each function. */
2112 #define ACCUMULATE_OUTGOING_ARGS 1
2113
2114 /* The argument pointer always points to the first argument. */
2115 #define FIRST_PARM_OFFSET(FNDECL) 0
2116
2117 /* o32 and o64 reserve stack space for all argument registers. */
2118 #define REG_PARM_STACK_SPACE(FNDECL) \
2119 (TARGET_OLDABI \
2120 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2121 : 0)
2122
2123 /* Define this if it is the responsibility of the caller to
2124 allocate the area reserved for arguments passed in registers.
2125 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2126 of this macro is to determine whether the space is included in
2127 `crtl->outgoing_args_size'. */
2128 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2129
2130 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2131 \f
2132 /* Symbolic macros for the registers used to return integer and floating
2133 point values. */
2134
2135 #define GP_RETURN (GP_REG_FIRST + 2)
2136 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2137
2138 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2139
2140 /* Symbolic macros for the first/last argument registers. */
2141
2142 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2143 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2144 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2145 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2146
2147 /* 1 if N is a possible register number for function argument passing.
2148 We have no FP argument registers when soft-float. When FP registers
2149 are 32 bits, we can't directly reference the odd numbered ones. */
2150
2151 #define FUNCTION_ARG_REGNO_P(N) \
2152 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2153 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2154 && !fixed_regs[N])
2155 \f
2156 /* This structure has to cope with two different argument allocation
2157 schemes. Most MIPS ABIs view the arguments as a structure, of which
2158 the first N words go in registers and the rest go on the stack. If I
2159 < N, the Ith word might go in Ith integer argument register or in a
2160 floating-point register. For these ABIs, we only need to remember
2161 the offset of the current argument into the structure.
2162
2163 The EABI instead allocates the integer and floating-point arguments
2164 separately. The first N words of FP arguments go in FP registers,
2165 the rest go on the stack. Likewise, the first N words of the other
2166 arguments go in integer registers, and the rest go on the stack. We
2167 need to maintain three counts: the number of integer registers used,
2168 the number of floating-point registers used, and the number of words
2169 passed on the stack.
2170
2171 We could keep separate information for the two ABIs (a word count for
2172 the standard ABIs, and three separate counts for the EABI). But it
2173 seems simpler to view the standard ABIs as forms of EABI that do not
2174 allocate floating-point registers.
2175
2176 So for the standard ABIs, the first N words are allocated to integer
2177 registers, and mips_function_arg decides on an argument-by-argument
2178 basis whether that argument should really go in an integer register,
2179 or in a floating-point one. */
2180
2181 typedef struct mips_args {
2182 /* Always true for varargs functions. Otherwise true if at least
2183 one argument has been passed in an integer register. */
2184 int gp_reg_found;
2185
2186 /* The number of arguments seen so far. */
2187 unsigned int arg_number;
2188
2189 /* The number of integer registers used so far. For all ABIs except
2190 EABI, this is the number of words that have been added to the
2191 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2192 unsigned int num_gprs;
2193
2194 /* For EABI, the number of floating-point registers used so far. */
2195 unsigned int num_fprs;
2196
2197 /* The number of words passed on the stack. */
2198 unsigned int stack_words;
2199
2200 /* On the mips16, we need to keep track of which floating point
2201 arguments were passed in general registers, but would have been
2202 passed in the FP regs if this were a 32-bit function, so that we
2203 can move them to the FP regs if we wind up calling a 32-bit
2204 function. We record this information in fp_code, encoded in base
2205 four. A zero digit means no floating point argument, a one digit
2206 means an SFmode argument, and a two digit means a DFmode argument,
2207 and a three digit is not used. The low order digit is the first
2208 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2209 an SFmode argument. ??? A more sophisticated approach will be
2210 needed if MIPS_ABI != ABI_32. */
2211 int fp_code;
2212
2213 /* True if the function has a prototype. */
2214 int prototype;
2215 } CUMULATIVE_ARGS;
2216
2217 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2218 for a call to a function whose data type is FNTYPE.
2219 For a library call, FNTYPE is 0. */
2220
2221 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2222 mips_init_cumulative_args (&CUM, FNTYPE)
2223
2224 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2225 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2226
2227 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2228 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2229
2230 /* True if using EABI and varargs can be passed in floating-point
2231 registers. Under these conditions, we need a more complex form
2232 of va_list, which tracks GPR, FPR and stack arguments separately. */
2233 #define EABI_FLOAT_VARARGS_P \
2234 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2235
2236 \f
2237 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2238
2239 /* Treat LOC as a byte offset from the stack pointer and round it up
2240 to the next fully-aligned offset. */
2241 #define MIPS_STACK_ALIGN(LOC) \
2242 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2243
2244 \f
2245 /* Output assembler code to FILE to increment profiler label # LABELNO
2246 for profiling a function entry. */
2247
2248 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2249
2250 /* The profiler preserves all interesting registers, including $31. */
2251 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2252
2253 /* No mips port has ever used the profiler counter word, so don't emit it
2254 or the label for it. */
2255
2256 #define NO_PROFILE_COUNTERS 1
2257
2258 /* Define this macro if the code for function profiling should come
2259 before the function prologue. Normally, the profiling code comes
2260 after. */
2261
2262 /* #define PROFILE_BEFORE_PROLOGUE */
2263
2264 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2265 the stack pointer does not matter. The value is tested only in
2266 functions that have frame pointers.
2267 No definition is equivalent to always zero. */
2268
2269 #define EXIT_IGNORE_STACK 1
2270
2271 \f
2272 /* Trampolines are a block of code followed by two pointers. */
2273
2274 #define TRAMPOLINE_SIZE \
2275 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2276
2277 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2278 pointers from a single LUI base. */
2279
2280 #define TRAMPOLINE_ALIGNMENT 64
2281
2282 /* mips_trampoline_init calls this library function to flush
2283 program and data caches. */
2284
2285 #ifndef CACHE_FLUSH_FUNC
2286 #define CACHE_FLUSH_FUNC "_flush_cache"
2287 #endif
2288
2289 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2290 /* Flush both caches. We need to flush the data cache in case \
2291 the system has a write-back cache. */ \
2292 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2293 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2294 GEN_INT (3), TYPE_MODE (integer_type_node))
2295
2296 \f
2297 /* Addressing modes, and classification of registers for them. */
2298
2299 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2300 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2301 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2302 \f
2303 /* Maximum number of registers that can appear in a valid memory address. */
2304
2305 #define MAX_REGS_PER_ADDRESS 1
2306
2307 /* Check for constness inline but use mips_legitimate_address_p
2308 to check whether a constant really is an address. */
2309
2310 #define CONSTANT_ADDRESS_P(X) \
2311 (CONSTANT_P (X) && memory_address_p (SImode, X))
2312
2313 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2314 'the start of the function that this code is output in'. */
2315
2316 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2317 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2318 asm_fprintf ((FILE), "%U%s", \
2319 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2320 else \
2321 asm_fprintf ((FILE), "%U%s", (NAME))
2322 \f
2323 /* Flag to mark a function decl symbol that requires a long call. */
2324 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2325 #define SYMBOL_REF_LONG_CALL_P(X) \
2326 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2327
2328 /* This flag marks functions that cannot be lazily bound. */
2329 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2330 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2331 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2332
2333 /* True if we're generating a form of MIPS16 code in which jump tables
2334 are stored in the text section and encoded as 16-bit PC-relative
2335 offsets. This is only possible when general text loads are allowed,
2336 since the table access itself will be an "lh" instruction. If the
2337 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2338 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2339
2340 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2341
2342 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2343
2344 /* Only use short offsets if their range will not overflow. */
2345 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2346 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2347 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2348 : SImode)
2349
2350 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2351
2352 /* Define this as 1 if `char' should by default be signed; else as 0. */
2353 #ifndef DEFAULT_SIGNED_CHAR
2354 #define DEFAULT_SIGNED_CHAR 1
2355 #endif
2356
2357 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2358 we generally don't want to use them for copying arbitrary data.
2359 A single N-word move is usually the same cost as N single-word moves. */
2360 #define MOVE_MAX UNITS_PER_WORD
2361 #define MAX_MOVE_MAX 8
2362
2363 /* Define this macro as a C expression which is nonzero if
2364 accessing less than a word of memory (i.e. a `char' or a
2365 `short') is no faster than accessing a word of memory, i.e., if
2366 such access require more than one instruction or if there is no
2367 difference in cost between byte and (aligned) word loads.
2368
2369 On RISC machines, it tends to generate better code to define
2370 this as 1, since it avoids making a QI or HI mode register.
2371
2372 But, generating word accesses for -mips16 is generally bad as shifts
2373 (often extended) would be needed for byte accesses. */
2374 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2375
2376 /* Standard MIPS integer shifts truncate the shift amount to the
2377 width of the shifted operand. However, Loongson vector shifts
2378 do not truncate the shift amount at all. */
2379 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2380
2381 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2382 is done just by pretending it is already truncated. */
2383 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2384 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2385
2386
2387 /* Specify the machine mode that pointers have.
2388 After generation of rtl, the compiler makes no further distinction
2389 between pointers and any other objects of this machine mode. */
2390
2391 #ifndef Pmode
2392 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2393 #endif
2394
2395 /* Give call MEMs SImode since it is the "most permissive" mode
2396 for both 32-bit and 64-bit targets. */
2397
2398 #define FUNCTION_MODE SImode
2399
2400 \f
2401 /* We allocate $fcc registers by hand and can't cope with moves of
2402 CCmode registers to and from pseudos (or memory). */
2403 #define AVOID_CCMODE_COPIES
2404
2405 /* A C expression for the cost of a branch instruction. A value of
2406 1 is the default; other values are interpreted relative to that. */
2407
2408 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2409 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2410
2411 /* If defined, modifies the length assigned to instruction INSN as a
2412 function of the context in which it is used. LENGTH is an lvalue
2413 that contains the initially computed length of the insn and should
2414 be updated with the correct length of the insn. */
2415 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2416 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2417
2418 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2419 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2420 its operands. */
2421 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2422 "%*" OPCODE "%?\t" OPERANDS "%/"
2423
2424 /* Return an asm string that forces INSN to be treated as an absolute
2425 J or JAL instruction instead of an assembler macro. */
2426 #define MIPS_ABSOLUTE_JUMP(INSN) \
2427 (TARGET_ABICALLS_PIC2 \
2428 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2429 : INSN)
2430
2431 /* Return the asm template for a call. INSN is the instruction's mnemonic
2432 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2433 number of the target. SIZE_OPNO is the operand number of the argument size
2434 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2435 -1 and the call is indirect, use the function symbol from the call
2436 attributes to attach a R_MIPS_JALR relocation to the call.
2437
2438 When generating GOT code without explicit relocation operators,
2439 all calls should use assembly macros. Otherwise, all indirect
2440 calls should use "jr" or "jalr"; we will arrange to restore $gp
2441 afterwards if necessary. Finally, we can only generate direct
2442 calls for -mabicalls by temporarily switching to non-PIC mode. */
2443 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2444 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2445 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2446 : (REG_P (OPERANDS[TARGET_OPNO]) \
2447 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2448 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2449 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2450 : REG_P (OPERANDS[TARGET_OPNO]) \
2451 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2452 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2453 \f
2454 /* Control the assembler format that we output. */
2455
2456 /* Output to assembler file text saying following lines
2457 may contain character constants, extra white space, comments, etc. */
2458
2459 #ifndef ASM_APP_ON
2460 #define ASM_APP_ON " #APP\n"
2461 #endif
2462
2463 /* Output to assembler file text saying following lines
2464 no longer contain unusual constructs. */
2465
2466 #ifndef ASM_APP_OFF
2467 #define ASM_APP_OFF " #NO_APP\n"
2468 #endif
2469
2470 #define REGISTER_NAMES \
2471 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2472 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2473 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2474 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2475 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2476 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2477 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2478 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2479 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2480 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2481 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2482 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2483 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2484 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2485 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2486 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2487 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2488 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2489 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2490 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2491 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2492 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2493 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2494 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2495
2496 /* List the "software" names for each register. Also list the numerical
2497 names for $fp and $sp. */
2498
2499 #define ADDITIONAL_REGISTER_NAMES \
2500 { \
2501 { "$29", 29 + GP_REG_FIRST }, \
2502 { "$30", 30 + GP_REG_FIRST }, \
2503 { "at", 1 + GP_REG_FIRST }, \
2504 { "v0", 2 + GP_REG_FIRST }, \
2505 { "v1", 3 + GP_REG_FIRST }, \
2506 { "a0", 4 + GP_REG_FIRST }, \
2507 { "a1", 5 + GP_REG_FIRST }, \
2508 { "a2", 6 + GP_REG_FIRST }, \
2509 { "a3", 7 + GP_REG_FIRST }, \
2510 { "t0", 8 + GP_REG_FIRST }, \
2511 { "t1", 9 + GP_REG_FIRST }, \
2512 { "t2", 10 + GP_REG_FIRST }, \
2513 { "t3", 11 + GP_REG_FIRST }, \
2514 { "t4", 12 + GP_REG_FIRST }, \
2515 { "t5", 13 + GP_REG_FIRST }, \
2516 { "t6", 14 + GP_REG_FIRST }, \
2517 { "t7", 15 + GP_REG_FIRST }, \
2518 { "s0", 16 + GP_REG_FIRST }, \
2519 { "s1", 17 + GP_REG_FIRST }, \
2520 { "s2", 18 + GP_REG_FIRST }, \
2521 { "s3", 19 + GP_REG_FIRST }, \
2522 { "s4", 20 + GP_REG_FIRST }, \
2523 { "s5", 21 + GP_REG_FIRST }, \
2524 { "s6", 22 + GP_REG_FIRST }, \
2525 { "s7", 23 + GP_REG_FIRST }, \
2526 { "t8", 24 + GP_REG_FIRST }, \
2527 { "t9", 25 + GP_REG_FIRST }, \
2528 { "k0", 26 + GP_REG_FIRST }, \
2529 { "k1", 27 + GP_REG_FIRST }, \
2530 { "gp", 28 + GP_REG_FIRST }, \
2531 { "sp", 29 + GP_REG_FIRST }, \
2532 { "fp", 30 + GP_REG_FIRST }, \
2533 { "ra", 31 + GP_REG_FIRST } \
2534 }
2535
2536 #define DBR_OUTPUT_SEQEND(STREAM) \
2537 do \
2538 { \
2539 /* Undo the effect of '%*'. */ \
2540 mips_pop_asm_switch (&mips_nomacro); \
2541 mips_pop_asm_switch (&mips_noreorder); \
2542 /* Emit a blank line after the delay slot for emphasis. */ \
2543 fputs ("\n", STREAM); \
2544 } \
2545 while (0)
2546
2547 /* The MIPS implementation uses some labels for its own purpose. The
2548 following lists what labels are created, and are all formed by the
2549 pattern $L[a-z].*. The machine independent portion of GCC creates
2550 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2551
2552 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2553 $Lb[0-9]+ Begin blocks for MIPS debug support
2554 $Lc[0-9]+ Label for use in s<xx> operation.
2555 $Le[0-9]+ End blocks for MIPS debug support */
2556
2557 #undef ASM_DECLARE_OBJECT_NAME
2558 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2559 mips_declare_object (STREAM, NAME, "", ":\n")
2560
2561 /* Globalizing directive for a label. */
2562 #define GLOBAL_ASM_OP "\t.globl\t"
2563
2564 /* This says how to define a global common symbol. */
2565
2566 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2567
2568 /* This says how to define a local common symbol (i.e., not visible to
2569 linker). */
2570
2571 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2572 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2573 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2574 #endif
2575
2576 /* This says how to output an external. It would be possible not to
2577 output anything and let undefined symbol become external. However
2578 the assembler uses length information on externals to allocate in
2579 data/sdata bss/sbss, thereby saving exec time. */
2580
2581 #undef ASM_OUTPUT_EXTERNAL
2582 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2583 mips_output_external(STREAM,DECL,NAME)
2584
2585 /* This is how to declare a function name. The actual work of
2586 emitting the label is moved to function_prologue, so that we can
2587 get the line number correctly emitted before the .ent directive,
2588 and after any .file directives. Define as empty so that the function
2589 is not declared before the .ent directive elsewhere. */
2590
2591 #undef ASM_DECLARE_FUNCTION_NAME
2592 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2593
2594 /* This is how to store into the string LABEL
2595 the symbol_ref name of an internal numbered label where
2596 PREFIX is the class of label and NUM is the number within the class.
2597 This is suitable for output with `assemble_name'. */
2598
2599 #undef ASM_GENERATE_INTERNAL_LABEL
2600 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2601 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2602
2603 /* Print debug labels as "foo = ." rather than "foo:" because they should
2604 represent a byte pointer rather than an ISA-encoded address. This is
2605 particularly important for code like:
2606
2607 $LFBxxx = .
2608 .cfi_startproc
2609 ...
2610 .section .gcc_except_table,...
2611 ...
2612 .uleb128 foo-$LFBxxx
2613
2614 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2615 likewise a byte pointer rather than an ISA-encoded address.
2616
2617 At the time of writing, this hook is not used for the function end
2618 label:
2619
2620 $LFExxx:
2621 .end foo
2622
2623 But this doesn't matter, because GAS doesn't treat a pre-.end label
2624 as a MIPS16 one anyway. */
2625
2626 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2627 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2628
2629 /* This is how to output an element of a case-vector that is absolute. */
2630
2631 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2632 fprintf (STREAM, "\t%s\t%sL%d\n", \
2633 ptr_mode == DImode ? ".dword" : ".word", \
2634 LOCAL_LABEL_PREFIX, \
2635 VALUE)
2636
2637 /* This is how to output an element of a case-vector. We can make the
2638 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2639 is supported. */
2640
2641 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2642 do { \
2643 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2644 { \
2645 if (GET_MODE (BODY) == HImode) \
2646 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2647 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2648 else \
2649 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2650 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2651 } \
2652 else if (TARGET_GPWORD) \
2653 fprintf (STREAM, "\t%s\t%sL%d\n", \
2654 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2655 LOCAL_LABEL_PREFIX, VALUE); \
2656 else if (TARGET_RTP_PIC) \
2657 { \
2658 /* Make the entry relative to the start of the function. */ \
2659 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2660 fprintf (STREAM, "\t%s\t%sL%d-", \
2661 Pmode == DImode ? ".dword" : ".word", \
2662 LOCAL_LABEL_PREFIX, VALUE); \
2663 assemble_name (STREAM, XSTR (fnsym, 0)); \
2664 fprintf (STREAM, "\n"); \
2665 } \
2666 else \
2667 fprintf (STREAM, "\t%s\t%sL%d\n", \
2668 ptr_mode == DImode ? ".dword" : ".word", \
2669 LOCAL_LABEL_PREFIX, VALUE); \
2670 } while (0)
2671
2672 /* This is how to output an assembler line
2673 that says to advance the location counter
2674 to a multiple of 2**LOG bytes. */
2675
2676 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2677 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2678
2679 /* This is how to output an assembler line to advance the location
2680 counter by SIZE bytes. */
2681
2682 #undef ASM_OUTPUT_SKIP
2683 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2684 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2685
2686 /* This is how to output a string. */
2687 #undef ASM_OUTPUT_ASCII
2688 #define ASM_OUTPUT_ASCII mips_output_ascii
2689
2690 \f
2691 /* Default to -G 8 */
2692 #ifndef MIPS_DEFAULT_GVALUE
2693 #define MIPS_DEFAULT_GVALUE 8
2694 #endif
2695
2696 /* Define the strings to put out for each section in the object file. */
2697 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2698 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2699
2700 #undef READONLY_DATA_SECTION_ASM_OP
2701 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2702 \f
2703 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2704 do \
2705 { \
2706 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2707 TARGET_64BIT ? "daddiu" : "addiu", \
2708 reg_names[STACK_POINTER_REGNUM], \
2709 reg_names[STACK_POINTER_REGNUM], \
2710 TARGET_64BIT ? "sd" : "sw", \
2711 reg_names[REGNO], \
2712 reg_names[STACK_POINTER_REGNUM]); \
2713 } \
2714 while (0)
2715
2716 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2717 do \
2718 { \
2719 mips_push_asm_switch (&mips_noreorder); \
2720 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2721 TARGET_64BIT ? "ld" : "lw", \
2722 reg_names[REGNO], \
2723 reg_names[STACK_POINTER_REGNUM], \
2724 TARGET_64BIT ? "daddu" : "addu", \
2725 reg_names[STACK_POINTER_REGNUM], \
2726 reg_names[STACK_POINTER_REGNUM]); \
2727 mips_pop_asm_switch (&mips_noreorder); \
2728 } \
2729 while (0)
2730
2731 /* How to start an assembler comment.
2732 The leading space is important (the mips native assembler requires it). */
2733 #ifndef ASM_COMMENT_START
2734 #define ASM_COMMENT_START " #"
2735 #endif
2736 \f
2737 #undef SIZE_TYPE
2738 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2739
2740 #undef PTRDIFF_TYPE
2741 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2742
2743 /* The maximum number of bytes that can be copied by one iteration of
2744 a movmemsi loop; see mips_block_move_loop. */
2745 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2746 (UNITS_PER_WORD * 4)
2747
2748 /* The maximum number of bytes that can be copied by a straight-line
2749 implementation of movmemsi; see mips_block_move_straight. We want
2750 to make sure that any loop-based implementation will iterate at
2751 least twice. */
2752 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2753 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2754
2755 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2756 values were determined experimentally by benchmarking with CSiBE.
2757 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2758 for o32 where we have to restore $gp afterwards as well as make an
2759 indirect call), but in practice, bumping this up higher for
2760 TARGET_ABICALLS doesn't make much difference to code size. */
2761
2762 #define MIPS_CALL_RATIO 8
2763
2764 /* Any loop-based implementation of movmemsi will have at least
2765 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2766 moves, so allow individual copies of fewer elements.
2767
2768 When movmemsi is not available, use a value approximating
2769 the length of a memcpy call sequence, so that move_by_pieces
2770 will generate inline code if it is shorter than a function call.
2771 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2772 we'll have to generate a load/store pair for each, halve the
2773 value of MIPS_CALL_RATIO to take that into account. */
2774
2775 #define MOVE_RATIO(speed) \
2776 (HAVE_movmemsi \
2777 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2778 : MIPS_CALL_RATIO / 2)
2779
2780 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2781 mips_move_by_pieces_p (SIZE, ALIGN)
2782
2783 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2784 of the length of a memset call, but use the default otherwise. */
2785
2786 #define CLEAR_RATIO(speed)\
2787 ((speed) ? 15 : MIPS_CALL_RATIO)
2788
2789 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2790 optimizing for size adjust the ratio to account for the overhead of
2791 loading the constant and replicating it across the word. */
2792
2793 #define SET_RATIO(speed) \
2794 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2795
2796 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2797 mips_store_by_pieces_p (SIZE, ALIGN)
2798 \f
2799 /* Since the bits of the _init and _fini function is spread across
2800 many object files, each potentially with its own GP, we must assume
2801 we need to load our GP. We don't preserve $gp or $ra, since each
2802 init/fini chunk is supposed to initialize $gp, and crti/crtn
2803 already take care of preserving $ra and, when appropriate, $gp. */
2804 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2805 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2806 asm (SECTION_OP "\n\
2807 .set push\n\
2808 .set nomips16\n\
2809 .set noreorder\n\
2810 bal 1f\n\
2811 nop\n\
2812 1: .cpload $31\n\
2813 .set reorder\n\
2814 jal " USER_LABEL_PREFIX #FUNC "\n\
2815 .set pop\n\
2816 " TEXT_SECTION_ASM_OP);
2817 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2818 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2819 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2820 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2821 asm (SECTION_OP "\n\
2822 .set push\n\
2823 .set nomips16\n\
2824 .set noreorder\n\
2825 bal 1f\n\
2826 nop\n\
2827 1: .set reorder\n\
2828 .cpsetup $31, $2, 1b\n\
2829 jal " USER_LABEL_PREFIX #FUNC "\n\
2830 .set pop\n\
2831 " TEXT_SECTION_ASM_OP);
2832 #endif
2833
2834 #ifndef HAVE_AS_TLS
2835 #define HAVE_AS_TLS 0
2836 #endif
2837
2838 #ifndef USED_FOR_TARGET
2839 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2840 struct mips_asm_switch {
2841 /* The FOO in the description above. */
2842 const char *name;
2843
2844 /* The current block nesting level, or 0 if we aren't in a block. */
2845 int nesting_level;
2846 };
2847
2848 extern const enum reg_class mips_regno_to_class[];
2849 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2850 extern const char *current_function_file; /* filename current function is in */
2851 extern int num_source_filenames; /* current .file # */
2852 extern struct mips_asm_switch mips_noreorder;
2853 extern struct mips_asm_switch mips_nomacro;
2854 extern struct mips_asm_switch mips_noat;
2855 extern int mips_dbx_regno[];
2856 extern int mips_dwarf_regno[];
2857 extern bool mips_split_p[];
2858 extern bool mips_split_hi_p[];
2859 extern bool mips_use_pcrel_pool_p[];
2860 extern const char *mips_lo_relocs[];
2861 extern const char *mips_hi_relocs[];
2862 extern enum processor mips_arch; /* which cpu to codegen for */
2863 extern enum processor mips_tune; /* which cpu to schedule for */
2864 extern int mips_isa; /* architectural level */
2865 extern const struct mips_cpu_info *mips_arch_info;
2866 extern const struct mips_cpu_info *mips_tune_info;
2867 extern bool mips_base_mips16;
2868 extern GTY(()) struct target_globals *mips16_globals;
2869 #endif
2870
2871 /* Enable querying of DFA units. */
2872 #define CPU_UNITS_QUERY 1
2873
2874 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2875 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2876
2877 /* As on most targets, we want the .eh_frame section to be read-only where
2878 possible. And as on most targets, this means two things:
2879
2880 (a) Non-locally-binding pointers must have an indirect encoding,
2881 so that the addresses in the .eh_frame section itself become
2882 locally-binding.
2883
2884 (b) A shared library's .eh_frame section must encode locally-binding
2885 pointers in a relative (relocation-free) form.
2886
2887 However, MIPS has traditionally not allowed directives like:
2888
2889 .long x-.
2890
2891 in cases where "x" is in a different section, or is not defined in the
2892 same assembly file. We are therefore unable to emit the PC-relative
2893 form required by (b) at assembly time.
2894
2895 Fortunately, the linker is able to convert absolute addresses into
2896 PC-relative addresses on our behalf. Unfortunately, only certain
2897 versions of the linker know how to do this for indirect pointers,
2898 and for personality data. We must fall back on using writable
2899 .eh_frame sections for shared libraries if the linker does not
2900 support this feature. */
2901 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2902 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2903
2904 /* For switching between MIPS16 and non-MIPS16 modes. */
2905 #define SWITCHABLE_TARGET 1
2906
2907 /* Several named MIPS patterns depend on Pmode. These patterns have the
2908 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2909 Add the appropriate suffix to generator function NAME and invoke it
2910 with arguments ARGS. */
2911 #define PMODE_INSN(NAME, ARGS) \
2912 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)