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Add support for MIPS r3 and r5.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS32R3 (mips_isa == 34)
212 #define ISA_MIPS32R5 (mips_isa == 36)
213 #define ISA_MIPS64 (mips_isa == 64)
214 #define ISA_MIPS64R2 (mips_isa == 65)
215 #define ISA_MIPS64R3 (mips_isa == 66)
216 #define ISA_MIPS64R5 (mips_isa == 68)
217
218 /* Architecture target defines. */
219 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
220 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
221 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
222 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
223 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
224 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
225 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
226 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
227 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
228 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
229 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
230 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
231 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
232 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
233 || mips_arch == PROCESSOR_OCTEON2)
234 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
235 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
236 || mips_arch == PROCESSOR_SB1A)
237 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
238 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
239
240 /* Scheduling target defines. */
241 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
242 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
243 || mips_tune == PROCESSOR_24KF2_1 \
244 || mips_tune == PROCESSOR_24KF1_1)
245 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
246 || mips_tune == PROCESSOR_74KF2_1 \
247 || mips_tune == PROCESSOR_74KF1_1 \
248 || mips_tune == PROCESSOR_74KF3_2)
249 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
250 || mips_tune == PROCESSOR_LOONGSON_2F)
251 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
252 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
253 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
254 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
255 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
256 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
257 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
258 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
259 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
260 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
261 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
262 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
263 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
264 || mips_tune == PROCESSOR_OCTEON2)
265 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
266 || mips_tune == PROCESSOR_SB1A)
267
268 /* Whether vector modes and intrinsics for ST Microelectronics
269 Loongson-2E/2F processors should be enabled. In o32 pairs of
270 floating-point registers provide 64-bit values. */
271 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
272 && (TARGET_LOONGSON_2EF \
273 || TARGET_LOONGSON_3A))
274
275 /* True if the pre-reload scheduler should try to create chains of
276 multiply-add or multiply-subtract instructions. For example,
277 suppose we have:
278
279 t1 = a * b
280 t2 = t1 + c * d
281 t3 = e * f
282 t4 = t3 - g * h
283
284 t1 will have a higher priority than t2 and t3 will have a higher
285 priority than t4. However, before reload, there is no dependence
286 between t1 and t3, and they can often have similar priorities.
287 The scheduler will then tend to prefer:
288
289 t1 = a * b
290 t3 = e * f
291 t2 = t1 + c * d
292 t4 = t3 - g * h
293
294 which stops us from making full use of macc/madd-style instructions.
295 This sort of situation occurs frequently in Fourier transforms and
296 in unrolled loops.
297
298 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
299 queue so that chained multiply-add and multiply-subtract instructions
300 appear ahead of any other instruction that is likely to clobber lo.
301 In the example above, if t2 and t3 become ready at the same time,
302 the code ensures that t2 is scheduled first.
303
304 Multiply-accumulate instructions are a bigger win for some targets
305 than others, so this macro is defined on an opt-in basis. */
306 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
307 || TUNE_MIPS4120 \
308 || TUNE_MIPS4130 \
309 || TUNE_24K)
310
311 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
312 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
313
314 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
315 directly accessible, while the command-line options select
316 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
317 in use. */
318 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
319 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
320
321 /* False if SC acts as a memory barrier with respect to itself,
322 otherwise a SYNC will be emitted after SC for atomic operations
323 that require ordering between the SC and following loads and
324 stores. It does not tell anything about ordering of loads and
325 stores prior to and following the SC, only about the SC itself and
326 those loads and stores follow it. */
327 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
328
329 /* Define preprocessor macros for the -march and -mtune options.
330 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
331 processor. If INFO's canonical name is "foo", define PREFIX to
332 be "foo", and define an additional macro PREFIX_FOO. */
333 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
334 do \
335 { \
336 char *macro, *p; \
337 \
338 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
339 for (p = macro; *p != 0; p++) \
340 if (*p == '+') \
341 *p = 'P'; \
342 else \
343 *p = TOUPPER (*p); \
344 \
345 builtin_define (macro); \
346 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
347 free (macro); \
348 } \
349 while (0)
350
351 /* Target CPU builtins. */
352 #define TARGET_CPU_CPP_BUILTINS() \
353 do \
354 { \
355 builtin_assert ("machine=mips"); \
356 builtin_assert ("cpu=mips"); \
357 builtin_define ("__mips__"); \
358 builtin_define ("_mips"); \
359 \
360 /* We do this here because __mips is defined below and so we \
361 can't use builtin_define_std. We don't ever want to define \
362 "mips" for VxWorks because some of the VxWorks headers \
363 construct include filenames from a root directory macro, \
364 an architecture macro and a filename, where the architecture \
365 macro expands to 'mips'. If we define 'mips' to 1, the \
366 architecture macro expands to 1 as well. */ \
367 if (!flag_iso && !TARGET_VXWORKS) \
368 builtin_define ("mips"); \
369 \
370 if (TARGET_64BIT) \
371 builtin_define ("__mips64"); \
372 \
373 /* Treat _R3000 and _R4000 like register-size \
374 defines, which is how they've historically \
375 been used. */ \
376 if (TARGET_64BIT) \
377 { \
378 builtin_define_std ("R4000"); \
379 builtin_define ("_R4000"); \
380 } \
381 else \
382 { \
383 builtin_define_std ("R3000"); \
384 builtin_define ("_R3000"); \
385 } \
386 \
387 if (TARGET_FLOAT64) \
388 builtin_define ("__mips_fpr=64"); \
389 else \
390 builtin_define ("__mips_fpr=32"); \
391 \
392 if (mips_base_compression_flags & MASK_MIPS16) \
393 builtin_define ("__mips16"); \
394 \
395 if (TARGET_MIPS3D) \
396 builtin_define ("__mips3d"); \
397 \
398 if (TARGET_SMARTMIPS) \
399 builtin_define ("__mips_smartmips"); \
400 \
401 if (mips_base_compression_flags & MASK_MICROMIPS) \
402 builtin_define ("__mips_micromips"); \
403 \
404 if (TARGET_MCU) \
405 builtin_define ("__mips_mcu"); \
406 \
407 if (TARGET_EVA) \
408 builtin_define ("__mips_eva"); \
409 \
410 if (TARGET_DSP) \
411 { \
412 builtin_define ("__mips_dsp"); \
413 if (TARGET_DSPR2) \
414 { \
415 builtin_define ("__mips_dspr2"); \
416 builtin_define ("__mips_dsp_rev=2"); \
417 } \
418 else \
419 builtin_define ("__mips_dsp_rev=1"); \
420 } \
421 \
422 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
423 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
424 \
425 if (ISA_MIPS1) \
426 { \
427 builtin_define ("__mips=1"); \
428 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
429 } \
430 else if (ISA_MIPS2) \
431 { \
432 builtin_define ("__mips=2"); \
433 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
434 } \
435 else if (ISA_MIPS3) \
436 { \
437 builtin_define ("__mips=3"); \
438 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
439 } \
440 else if (ISA_MIPS4) \
441 { \
442 builtin_define ("__mips=4"); \
443 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
444 } \
445 else if (ISA_MIPS32) \
446 { \
447 builtin_define ("__mips=32"); \
448 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
449 } \
450 else if (ISA_MIPS32R2) \
451 { \
452 builtin_define ("__mips=32"); \
453 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
454 } \
455 else if (ISA_MIPS32R3) \
456 { \
457 builtin_define ("__mips=32"); \
458 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
459 } \
460 else if (ISA_MIPS32R5) \
461 { \
462 builtin_define ("__mips=32"); \
463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
464 } \
465 else if (ISA_MIPS64) \
466 { \
467 builtin_define ("__mips=64"); \
468 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
469 } \
470 else if (ISA_MIPS64R2) \
471 { \
472 builtin_define ("__mips=64"); \
473 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
474 } \
475 else if (ISA_MIPS64R3) \
476 { \
477 builtin_define ("__mips=64"); \
478 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
479 } \
480 else if (ISA_MIPS64R5) \
481 { \
482 builtin_define ("__mips=64"); \
483 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
484 } \
485 if (mips_isa_rev > 0) \
486 builtin_define_with_int_value ("__mips_isa_rev", \
487 mips_isa_rev); \
488 \
489 switch (mips_abi) \
490 { \
491 case ABI_32: \
492 builtin_define ("_ABIO32=1"); \
493 builtin_define ("_MIPS_SIM=_ABIO32"); \
494 break; \
495 \
496 case ABI_N32: \
497 builtin_define ("_ABIN32=2"); \
498 builtin_define ("_MIPS_SIM=_ABIN32"); \
499 break; \
500 \
501 case ABI_64: \
502 builtin_define ("_ABI64=3"); \
503 builtin_define ("_MIPS_SIM=_ABI64"); \
504 break; \
505 \
506 case ABI_O64: \
507 builtin_define ("_ABIO64=4"); \
508 builtin_define ("_MIPS_SIM=_ABIO64"); \
509 break; \
510 } \
511 \
512 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
513 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
514 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
515 builtin_define_with_int_value ("_MIPS_FPSET", \
516 32 / MAX_FPRS_PER_FMT); \
517 \
518 /* These defines reflect the ABI in use, not whether the \
519 FPU is directly accessible. */ \
520 if (TARGET_NO_FLOAT) \
521 builtin_define ("__mips_no_float"); \
522 else if (TARGET_HARD_FLOAT_ABI) \
523 builtin_define ("__mips_hard_float"); \
524 else \
525 builtin_define ("__mips_soft_float"); \
526 \
527 if (TARGET_SINGLE_FLOAT) \
528 builtin_define ("__mips_single_float"); \
529 \
530 if (TARGET_PAIRED_SINGLE_FLOAT) \
531 builtin_define ("__mips_paired_single_float"); \
532 \
533 if (mips_abs == MIPS_IEEE_754_2008) \
534 builtin_define ("__mips_abs2008"); \
535 \
536 if (mips_nan == MIPS_IEEE_754_2008) \
537 builtin_define ("__mips_nan2008"); \
538 \
539 if (TARGET_BIG_ENDIAN) \
540 { \
541 builtin_define_std ("MIPSEB"); \
542 builtin_define ("_MIPSEB"); \
543 } \
544 else \
545 { \
546 builtin_define_std ("MIPSEL"); \
547 builtin_define ("_MIPSEL"); \
548 } \
549 \
550 /* Whether calls should go through $25. The separate __PIC__ \
551 macro indicates whether abicalls code might use a GOT. */ \
552 if (TARGET_ABICALLS) \
553 builtin_define ("__mips_abicalls"); \
554 \
555 /* Whether Loongson vector modes are enabled. */ \
556 if (TARGET_LOONGSON_VECTORS) \
557 builtin_define ("__mips_loongson_vector_rev"); \
558 \
559 /* Historical Octeon macro. */ \
560 if (TARGET_OCTEON) \
561 builtin_define ("__OCTEON__"); \
562 \
563 if (TARGET_SYNCI) \
564 builtin_define ("__mips_synci"); \
565 \
566 /* Macros dependent on the C dialect. */ \
567 if (preprocessing_asm_p ()) \
568 { \
569 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
570 builtin_define ("_LANGUAGE_ASSEMBLY"); \
571 } \
572 else if (c_dialect_cxx ()) \
573 { \
574 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
575 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
576 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
577 } \
578 else \
579 { \
580 builtin_define_std ("LANGUAGE_C"); \
581 builtin_define ("_LANGUAGE_C"); \
582 } \
583 if (c_dialect_objc ()) \
584 { \
585 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
586 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
587 /* Bizarre, but retained for backwards compatibility. */ \
588 builtin_define_std ("LANGUAGE_C"); \
589 builtin_define ("_LANGUAGE_C"); \
590 } \
591 \
592 if (mips_abi == ABI_EABI) \
593 builtin_define ("__mips_eabi"); \
594 \
595 if (TARGET_CACHE_BUILTIN) \
596 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
597 } \
598 while (0)
599
600 /* Default target_flags if no switches are specified */
601
602 #ifndef TARGET_DEFAULT
603 #define TARGET_DEFAULT 0
604 #endif
605
606 #ifndef TARGET_CPU_DEFAULT
607 #define TARGET_CPU_DEFAULT 0
608 #endif
609
610 #ifndef TARGET_ENDIAN_DEFAULT
611 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
612 #endif
613
614 #ifdef IN_LIBGCC2
615 #undef TARGET_64BIT
616 /* Make this compile time constant for libgcc2 */
617 #ifdef __mips64
618 #define TARGET_64BIT 1
619 #else
620 #define TARGET_64BIT 0
621 #endif
622 #endif /* IN_LIBGCC2 */
623
624 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
625 when compiled with hardware floating point. This is because MIPS16
626 code cannot save and restore the floating-point registers, which is
627 important if in a mixed MIPS16/non-MIPS16 environment. */
628
629 #ifdef IN_LIBGCC2
630 #if __mips_hard_float
631 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
632 #endif
633 #endif /* IN_LIBGCC2 */
634
635 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
636
637 #ifndef MULTILIB_ENDIAN_DEFAULT
638 #if TARGET_ENDIAN_DEFAULT == 0
639 #define MULTILIB_ENDIAN_DEFAULT "EL"
640 #else
641 #define MULTILIB_ENDIAN_DEFAULT "EB"
642 #endif
643 #endif
644
645 #ifndef MULTILIB_ISA_DEFAULT
646 #if MIPS_ISA_DEFAULT == 1
647 #define MULTILIB_ISA_DEFAULT "mips1"
648 #elif MIPS_ISA_DEFAULT == 2
649 #define MULTILIB_ISA_DEFAULT "mips2"
650 #elif MIPS_ISA_DEFAULT == 3
651 #define MULTILIB_ISA_DEFAULT "mips3"
652 #elif MIPS_ISA_DEFAULT == 4
653 #define MULTILIB_ISA_DEFAULT "mips4"
654 #elif MIPS_ISA_DEFAULT == 32
655 #define MULTILIB_ISA_DEFAULT "mips32"
656 #elif MIPS_ISA_DEFAULT == 33
657 #define MULTILIB_ISA_DEFAULT "mips32r2"
658 #elif MIPS_ISA_DEFAULT == 64
659 #define MULTILIB_ISA_DEFAULT "mips64"
660 #elif MIPS_ISA_DEFAULT == 65
661 #define MULTILIB_ISA_DEFAULT "mips64r2"
662 #else
663 #define MULTILIB_ISA_DEFAULT "mips1"
664 #endif
665 #endif
666
667 #ifndef MIPS_ABI_DEFAULT
668 #define MIPS_ABI_DEFAULT ABI_32
669 #endif
670
671 /* Use the most portable ABI flag for the ASM specs. */
672
673 #if MIPS_ABI_DEFAULT == ABI_32
674 #define MULTILIB_ABI_DEFAULT "mabi=32"
675 #elif MIPS_ABI_DEFAULT == ABI_O64
676 #define MULTILIB_ABI_DEFAULT "mabi=o64"
677 #elif MIPS_ABI_DEFAULT == ABI_N32
678 #define MULTILIB_ABI_DEFAULT "mabi=n32"
679 #elif MIPS_ABI_DEFAULT == ABI_64
680 #define MULTILIB_ABI_DEFAULT "mabi=64"
681 #elif MIPS_ABI_DEFAULT == ABI_EABI
682 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
683 #endif
684
685 #ifndef MULTILIB_DEFAULTS
686 #define MULTILIB_DEFAULTS \
687 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
688 #endif
689
690 /* We must pass -EL to the linker by default for little endian embedded
691 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
692 linker will default to using big-endian output files. The OUTPUT_FORMAT
693 line must be in the linker script, otherwise -EB/-EL will not work. */
694
695 #ifndef ENDIAN_SPEC
696 #if TARGET_ENDIAN_DEFAULT == 0
697 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
698 #else
699 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
700 #endif
701 #endif
702
703 /* A spec condition that matches all non-mips16 -mips arguments. */
704
705 #define MIPS_ISA_LEVEL_OPTION_SPEC \
706 "mips1|mips2|mips3|mips4|mips32*|mips64*"
707
708 /* A spec condition that matches all non-mips16 architecture arguments. */
709
710 #define MIPS_ARCH_OPTION_SPEC \
711 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
712
713 /* A spec that infers a -mips argument from an -march argument,
714 or injects the default if no architecture is specified. */
715
716 #define MIPS_ISA_LEVEL_SPEC \
717 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
718 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
719 %{march=mips2|march=r6000:-mips2} \
720 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
721 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
722 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
723 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
724 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
725 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
726 %{march=mips32r3: -mips32r3} \
727 %{march=mips32r5: -mips32r5} \
728 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
729 |march=xlr: -mips64} \
730 %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
731 %{march=mips64r3: -mips64r3} \
732 %{march=mips64r5: -mips64r5} \
733 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
734
735 /* A spec that infers a -mhard-float or -msoft-float setting from an
736 -march argument. Note that soft-float and hard-float code are not
737 link-compatible. */
738
739 #define MIPS_ARCH_FLOAT_SPEC \
740 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
741 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
742 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
743 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
744 march=*: -mhard-float}"
745
746 /* A spec condition that matches 32-bit options. It only works if
747 MIPS_ISA_LEVEL_SPEC has been applied. */
748
749 #define MIPS_32BIT_OPTION_SPEC \
750 "mips1|mips2|mips32*|mgp32"
751
752 /* Infer a -msynci setting from a -mips argument, on the assumption that
753 -msynci is desired where possible. */
754 #define MIPS_ISA_SYNCI_SPEC \
755 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips64r2|mips64r3 \
756 |mips64r5:-msynci;:-mno-synci}}"
757
758 #if (MIPS_ABI_DEFAULT == ABI_O64 \
759 || MIPS_ABI_DEFAULT == ABI_N32 \
760 || MIPS_ABI_DEFAULT == ABI_64)
761 #define OPT_ARCH64 "mabi=32|mgp32:;"
762 #define OPT_ARCH32 "mabi=32|mgp32"
763 #else
764 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
765 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
766 #endif
767
768 /* Support for a compile-time default CPU, et cetera. The rules are:
769 --with-arch is ignored if -march is specified or a -mips is specified
770 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
771 --with-tune is ignored if -mtune is specified; likewise
772 --with-tune-32 and --with-tune-64.
773 --with-abi is ignored if -mabi is specified.
774 --with-float is ignored if -mhard-float or -msoft-float are
775 specified.
776 --with-nan is ignored if -mnan is specified.
777 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
778 specified. */
779 #define OPTION_DEFAULT_SPECS \
780 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
781 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
782 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
783 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
784 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
785 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
786 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
787 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
788 {"fpu", "%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}" }, \
789 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
790 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
791 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
792 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
793 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
794
795 /* A spec that infers the -mdsp setting from an -march argument. */
796 #define BASE_DRIVER_SELF_SPECS \
797 "%{!mno-dsp: \
798 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
799 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
800
801 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
802
803 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
804 && ISA_HAS_COND_TRAP)
805
806 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
807
808 /* True if the ABI can only work with 64-bit integer registers. We
809 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
810 otherwise floating-point registers must also be 64-bit. */
811 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
812
813 /* Likewise for 32-bit regs. */
814 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
815
816 /* True if the file format uses 64-bit symbols. At present, this is
817 only true for n64, which uses 64-bit ELF. */
818 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
819
820 /* True if symbols are 64 bits wide. This is usually determined by
821 the ABI's file format, but it can be overridden by -msym32. Note that
822 overriding the size with -msym32 changes the ABI of relocatable objects,
823 although it doesn't change the ABI of a fully-linked object. */
824 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
825 && Pmode == DImode \
826 && !TARGET_SYM32)
827
828 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
829 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
830 || ISA_MIPS4 \
831 || ISA_MIPS64 \
832 || ISA_MIPS64R2 \
833 || ISA_MIPS64R3 \
834 || ISA_MIPS64R5)
835
836 /* ISA has branch likely instructions (e.g. mips2). */
837 /* Disable branchlikely for tx39 until compare rewrite. They haven't
838 been generated up to this point. */
839 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
840
841 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
842 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
843 || TARGET_MIPS5400 \
844 || TARGET_MIPS5500 \
845 || TARGET_MIPS5900 \
846 || TARGET_MIPS7000 \
847 || TARGET_MIPS9000 \
848 || TARGET_MAD \
849 || mips_isa_rev >= 1) \
850 && !TARGET_MIPS16)
851
852 /* ISA has a three-operand multiplication instruction. */
853 #define ISA_HAS_DMUL3 (TARGET_64BIT \
854 && TARGET_OCTEON \
855 && !TARGET_MIPS16)
856
857 /* ISA supports instructions DMULT and DMULTU. */
858 #define ISA_HAS_DMULT (TARGET_64BIT && !TARGET_MIPS5900)
859
860 /* ISA supports instructions MULT and MULTU.
861 This is always true, but the macro is needed for ISA_HAS_<D>MULT
862 in mips.md. */
863 #define ISA_HAS_MULT (1)
864
865 /* ISA supports instructions DDIV and DDIVU. */
866 #define ISA_HAS_DDIV (TARGET_64BIT && !TARGET_MIPS5900)
867
868 /* ISA supports instructions DIV and DIVU.
869 This is always true, but the macro is needed for ISA_HAS_<D>DIV
870 in mips.md. */
871 #define ISA_HAS_DIV (1)
872
873 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
874 || TARGET_LOONGSON_3A) \
875 && !TARGET_MIPS16)
876
877 /* ISA has the floating-point conditional move instructions introduced
878 in mips4. */
879 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
880 || mips_isa_rev >= 1) \
881 && !TARGET_MIPS5500 \
882 && !TARGET_MIPS16)
883
884 /* ISA has the integer conditional move instructions introduced in mips4 and
885 ST Loongson 2E/2F. */
886 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
887 || TARGET_MIPS5900 \
888 || TARGET_LOONGSON_2EF)
889
890 /* ISA has LDC1 and SDC1. */
891 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
892 && !TARGET_MIPS5900 \
893 && !TARGET_MIPS16)
894
895 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
896 branch on CC, and move (both FP and non-FP) on CC. */
897 #define ISA_HAS_8CC (ISA_MIPS4 || mips_isa_rev >= 1)
898
899 /* This is a catch all for other mips4 instructions: indexed load, the
900 FP madd and msub instructions, and the FP recip and recip sqrt
901 instructions. Note that this macro should only be used by other
902 ISA_HAS_* macros. */
903 #define ISA_HAS_FP4 ((ISA_MIPS4 \
904 || ISA_MIPS64 \
905 || mips_isa_rev >= 2) \
906 && !TARGET_MIPS16)
907
908 /* ISA has floating-point indexed load and store instructions
909 (LWXC1, LDXC1, SWXC1 and SDXC1). */
910 #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
911
912 /* ISA has paired-single instructions. */
913 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS64 || mips_isa_rev >= 2)
914
915 /* ISA has conditional trap instructions. */
916 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
917 && !TARGET_MIPS16)
918
919 /* ISA has integer multiply-accumulate instructions, madd and msub. */
920 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1)
921
922 /* Integer multiply-accumulate instructions should be generated. */
923 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
924
925 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
926 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
927
928 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
929 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
930
931 /* ISA has floating-point nmadd and nmsub instructions
932 'd = -((a * b) [+-] c)'. */
933 #define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4
934
935 /* ISA has floating-point nmadd and nmsub instructions
936 'c = -((a * b) [+-] c)'. */
937 #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF
938
939 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
940 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
941 doubles are stored in pairs of FPRs, so for safety's sake, we apply
942 this restriction to the MIPS IV ISA too. */
943 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
944 (((ISA_HAS_FP4 \
945 && ((MODE) == SFmode \
946 || ((TARGET_FLOAT64 \
947 || mips_isa_rev >= 2) \
948 && (MODE) == DFmode))) \
949 || (TARGET_SB1 \
950 && (MODE) == V2SFmode)) \
951 && !TARGET_MIPS16)
952
953 /* ISA has count leading zeroes/ones instruction (not implemented). */
954 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
955
956 /* ISA has three operand multiply instructions that put
957 the high part in an accumulator: mulhi or mulhiu. */
958 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
959 || TARGET_MIPS5500 \
960 || TARGET_SR71K) \
961 && !TARGET_MIPS16)
962
963 /* ISA has three operand multiply instructions that negate the
964 result and put the result in an accumulator. */
965 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
966 || TARGET_MIPS5500 \
967 || TARGET_SR71K) \
968 && !TARGET_MIPS16)
969
970 /* ISA has three operand multiply instructions that subtract the
971 result from a 4th operand and put the result in an accumulator. */
972 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
973 || TARGET_MIPS5500 \
974 || TARGET_SR71K) \
975 && !TARGET_MIPS16)
976
977 /* ISA has three operand multiply instructions that add the result
978 to a 4th operand and put the result in an accumulator. */
979 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
980 || TARGET_MIPS4130 \
981 || TARGET_MIPS5400 \
982 || TARGET_MIPS5500 \
983 || TARGET_SR71K) \
984 && !TARGET_MIPS16)
985
986 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
987 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
988 || TARGET_MIPS4130) \
989 && !TARGET_MIPS16)
990
991 /* ISA has the "ror" (rotate right) instructions. */
992 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
993 || TARGET_MIPS5400 \
994 || TARGET_MIPS5500 \
995 || TARGET_SR71K \
996 || TARGET_SMARTMIPS) \
997 && !TARGET_MIPS16)
998
999 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1000 64-bit targets also provide DSBH and DSHD. */
1001 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1002
1003 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1004 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1005 || TARGET_LOONGSON_2EF \
1006 || TARGET_MIPS5900 \
1007 || mips_isa_rev >= 1) \
1008 && !TARGET_MIPS16)
1009
1010 /* ISA has data indexed prefetch instructions. This controls use of
1011 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1012 (prefx is a cop1x instruction, so can only be used if FP is
1013 enabled.) */
1014 #define ISA_HAS_PREFETCHX ISA_HAS_FP4
1015
1016 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1017 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1018 also requires TARGET_DOUBLE_FLOAT. */
1019 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1020
1021 /* ISA includes the MIPS32r2 seb and seh instructions. */
1022 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1023
1024 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1025 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1026
1027 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1028 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && mips_isa_rev >= 2)
1029
1030 /* ISA has lwxs instruction (load w/scaled index address. */
1031 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1032 && !TARGET_MIPS16)
1033
1034 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1035 #define ISA_HAS_LBX (TARGET_OCTEON2)
1036 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1037 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1038 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1039 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1040 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1041 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1042 && TARGET_64BIT)
1043
1044 /* The DSP ASE is available. */
1045 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1046
1047 /* Revision 2 of the DSP ASE is available. */
1048 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1049
1050 /* True if the result of a load is not available to the next instruction.
1051 A nop will then be needed between instructions like "lw $4,..."
1052 and "addiu $4,$4,1". */
1053 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1054 && !TARGET_MIPS3900 \
1055 && !TARGET_MIPS5900 \
1056 && !TARGET_MIPS16 \
1057 && !TARGET_MICROMIPS)
1058
1059 /* Likewise mtc1 and mfc1. */
1060 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1061 && !TARGET_MIPS5900 \
1062 && !TARGET_LOONGSON_2EF)
1063
1064 /* Likewise floating-point comparisons. */
1065 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1066 && !TARGET_MIPS5900 \
1067 && !TARGET_LOONGSON_2EF)
1068
1069 /* True if mflo and mfhi can be immediately followed by instructions
1070 which write to the HI and LO registers.
1071
1072 According to MIPS specifications, MIPS ISAs I, II, and III need
1073 (at least) two instructions between the reads of HI/LO and
1074 instructions which write them, and later ISAs do not. Contradicting
1075 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1076 the UM for the NEC Vr5000) document needing the instructions between
1077 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1078 MIPS64 and later ISAs to have the interlocks, plus any specific
1079 earlier-ISA CPUs for which CPU documentation declares that the
1080 instructions are really interlocked. */
1081 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1082 || TARGET_MIPS5500 \
1083 || TARGET_MIPS5900 \
1084 || TARGET_LOONGSON_2EF)
1085
1086 /* ISA includes synci, jr.hb and jalr.hb. */
1087 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1088
1089 /* ISA includes sync. */
1090 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1091 #define GENERATE_SYNC \
1092 (target_flags_explicit & MASK_LLSC \
1093 ? TARGET_LLSC && !TARGET_MIPS16 \
1094 : ISA_HAS_SYNC)
1095
1096 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1097 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1098 instructions. */
1099 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1100 #define GENERATE_LL_SC \
1101 (target_flags_explicit & MASK_LLSC \
1102 ? TARGET_LLSC && !TARGET_MIPS16 \
1103 : ISA_HAS_LL_SC)
1104
1105 #define ISA_HAS_SWAP (TARGET_XLP)
1106 #define ISA_HAS_LDADD (TARGET_XLP)
1107
1108 /* ISA includes the baddu instruction. */
1109 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1110
1111 /* ISA includes the bbit* instructions. */
1112 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1113
1114 /* ISA includes the cins instruction. */
1115 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1116
1117 /* ISA includes the exts instruction. */
1118 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1119
1120 /* ISA includes the seq and sne instructions. */
1121 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1122
1123 /* ISA includes the pop instruction. */
1124 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1125
1126 /* The CACHE instruction is available in non-MIPS16 code. */
1127 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1128
1129 /* The CACHE instruction is available. */
1130 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1131 \f
1132 /* Tell collect what flags to pass to nm. */
1133 #ifndef NM_FLAGS
1134 #define NM_FLAGS "-Bn"
1135 #endif
1136
1137 \f
1138 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1139 the assembler. It may be overridden by subtargets.
1140
1141 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1142 COFF debugging info. */
1143
1144 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1145 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1146 %{g} %{g0} %{g1} %{g2} %{g3} \
1147 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1148 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1149 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1150 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1151 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1152 #endif
1153
1154 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1155 overridden by subtargets. */
1156
1157 #ifndef SUBTARGET_ASM_SPEC
1158 #define SUBTARGET_ASM_SPEC ""
1159 #endif
1160
1161 #undef ASM_SPEC
1162 #define ASM_SPEC "\
1163 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1164 %{mips32*} %{mips64*} \
1165 %{mips16} %{mno-mips16:-no-mips16} \
1166 %{mmicromips} %{mno-micromips} \
1167 %{mips3d} %{mno-mips3d:-no-mips3d} \
1168 %{mdmx} %{mno-mdmx:-no-mdmx} \
1169 %{mdsp} %{mno-dsp} \
1170 %{mdspr2} %{mno-dspr2} \
1171 %{mmcu} %{mno-mcu} \
1172 %{meva} %{mno-eva} \
1173 %{mvirt} %{mno-virt} \
1174 %{mxpa} %{mno-xpa} \
1175 %{msmartmips} %{mno-smartmips} \
1176 %{mmt} %{mno-mt} \
1177 %{mfix-rm7000} %{mno-fix-rm7000} \
1178 %{mfix-vr4120} %{mfix-vr4130} \
1179 %{mfix-24k} \
1180 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1181 %(subtarget_asm_debugging_spec) \
1182 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1183 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1184 %{mfp32} %{mfp64} %{mnan=*} \
1185 %{mshared} %{mno-shared} \
1186 %{msym32} %{mno-sym32} \
1187 %{mtune=*} \
1188 %(subtarget_asm_spec)"
1189
1190 /* Extra switches sometimes passed to the linker. */
1191
1192 #ifndef LINK_SPEC
1193 #define LINK_SPEC "\
1194 %(endian_spec) \
1195 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1196 %{shared}"
1197 #endif /* LINK_SPEC defined */
1198
1199
1200 /* Specs for the compiler proper */
1201
1202 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1203 overridden by subtargets. */
1204 #ifndef SUBTARGET_CC1_SPEC
1205 #define SUBTARGET_CC1_SPEC ""
1206 #endif
1207
1208 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1209
1210 #undef CC1_SPEC
1211 #define CC1_SPEC "\
1212 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1213 %(subtarget_cc1_spec)"
1214
1215 /* Preprocessor specs. */
1216
1217 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1218 overridden by subtargets. */
1219 #ifndef SUBTARGET_CPP_SPEC
1220 #define SUBTARGET_CPP_SPEC ""
1221 #endif
1222
1223 #define CPP_SPEC "%(subtarget_cpp_spec)"
1224
1225 /* This macro defines names of additional specifications to put in the specs
1226 that can be used in various specifications like CC1_SPEC. Its definition
1227 is an initializer with a subgrouping for each command option.
1228
1229 Each subgrouping contains a string constant, that defines the
1230 specification name, and a string constant that used by the GCC driver
1231 program.
1232
1233 Do not define this macro if it does not need to do anything. */
1234
1235 #define EXTRA_SPECS \
1236 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1237 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1238 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1239 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1240 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1241 { "endian_spec", ENDIAN_SPEC }, \
1242 SUBTARGET_EXTRA_SPECS
1243
1244 #ifndef SUBTARGET_EXTRA_SPECS
1245 #define SUBTARGET_EXTRA_SPECS
1246 #endif
1247 \f
1248 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1249 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1250
1251 #ifndef PREFERRED_DEBUGGING_TYPE
1252 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1253 #endif
1254
1255 /* The size of DWARF addresses should be the same as the size of symbols
1256 in the target file format. They shouldn't depend on things like -msym32,
1257 because many DWARF consumers do not allow the mixture of address sizes
1258 that one would then get from linking -msym32 code with -msym64 code.
1259
1260 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1261 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1262 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1263
1264 /* By default, turn on GDB extensions. */
1265 #define DEFAULT_GDB_EXTENSIONS 1
1266
1267 /* Local compiler-generated symbols must have a prefix that the assembler
1268 understands. By default, this is $, although some targets (e.g.,
1269 NetBSD-ELF) need to override this. */
1270
1271 #ifndef LOCAL_LABEL_PREFIX
1272 #define LOCAL_LABEL_PREFIX "$"
1273 #endif
1274
1275 /* By default on the mips, external symbols do not have an underscore
1276 prepended, but some targets (e.g., NetBSD) require this. */
1277
1278 #ifndef USER_LABEL_PREFIX
1279 #define USER_LABEL_PREFIX ""
1280 #endif
1281
1282 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1283 since the length can run past this up to a continuation point. */
1284 #undef DBX_CONTIN_LENGTH
1285 #define DBX_CONTIN_LENGTH 1500
1286
1287 /* How to renumber registers for dbx and gdb. */
1288 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1289
1290 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1291 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1292
1293 /* The DWARF 2 CFA column which tracks the return address. */
1294 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1295
1296 /* Before the prologue, RA lives in r31. */
1297 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1298
1299 /* Describe how we implement __builtin_eh_return. */
1300 #define EH_RETURN_DATA_REGNO(N) \
1301 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1302
1303 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1304
1305 #define EH_USES(N) mips_eh_uses (N)
1306
1307 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1308 The default for this in 64-bit mode is 8, which causes problems with
1309 SFmode register saves. */
1310 #define DWARF_CIE_DATA_ALIGNMENT -4
1311
1312 /* Correct the offset of automatic variables and arguments. Note that
1313 the MIPS debug format wants all automatic variables and arguments
1314 to be in terms of the virtual frame pointer (stack pointer before
1315 any adjustment in the function), while the MIPS 3.0 linker wants
1316 the frame pointer to be the stack pointer after the initial
1317 adjustment. */
1318
1319 #define DEBUGGER_AUTO_OFFSET(X) \
1320 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1321 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1322 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1323 \f
1324 /* Target machine storage layout */
1325
1326 #define BITS_BIG_ENDIAN 0
1327 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1328 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1329
1330 #define MAX_BITS_PER_WORD 64
1331
1332 /* Width of a word, in units (bytes). */
1333 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1334 #ifndef IN_LIBGCC2
1335 #define MIN_UNITS_PER_WORD 4
1336 #endif
1337
1338 /* For MIPS, width of a floating point register. */
1339 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1340
1341 /* The number of consecutive floating-point registers needed to store the
1342 largest format supported by the FPU. */
1343 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1344
1345 /* The number of consecutive floating-point registers needed to store the
1346 smallest format supported by the FPU. */
1347 #define MIN_FPRS_PER_FMT \
1348 (mips_isa_rev >= 1 ? 1 : MAX_FPRS_PER_FMT)
1349
1350 /* The largest size of value that can be held in floating-point
1351 registers and moved with a single instruction. */
1352 #define UNITS_PER_HWFPVALUE \
1353 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1354
1355 /* The largest size of value that can be held in floating-point
1356 registers. */
1357 #define UNITS_PER_FPVALUE \
1358 (TARGET_SOFT_FLOAT_ABI ? 0 \
1359 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1360 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1361
1362 /* The number of bytes in a double. */
1363 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1364
1365 /* Set the sizes of the core types. */
1366 #define SHORT_TYPE_SIZE 16
1367 #define INT_TYPE_SIZE 32
1368 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1369 #define LONG_LONG_TYPE_SIZE 64
1370
1371 #define FLOAT_TYPE_SIZE 32
1372 #define DOUBLE_TYPE_SIZE 64
1373 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1374
1375 /* Define the sizes of fixed-point types. */
1376 #define SHORT_FRACT_TYPE_SIZE 8
1377 #define FRACT_TYPE_SIZE 16
1378 #define LONG_FRACT_TYPE_SIZE 32
1379 #define LONG_LONG_FRACT_TYPE_SIZE 64
1380
1381 #define SHORT_ACCUM_TYPE_SIZE 16
1382 #define ACCUM_TYPE_SIZE 32
1383 #define LONG_ACCUM_TYPE_SIZE 64
1384 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1385 doesn't support 128-bit integers for MIPS32 currently. */
1386 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1387
1388 /* long double is not a fixed mode, but the idea is that, if we
1389 support long double, we also want a 128-bit integer type. */
1390 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1391
1392 #ifdef IN_LIBGCC2
1393 #if ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1394 || (defined _ABI64 && _MIPS_SIM == _ABI64))
1395 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1396 # else
1397 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1398 # endif
1399 #endif
1400
1401 /* Width in bits of a pointer. */
1402 #ifndef POINTER_SIZE
1403 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1404 #endif
1405
1406 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1407 #define PARM_BOUNDARY BITS_PER_WORD
1408
1409 /* Allocation boundary (in *bits*) for the code of a function. */
1410 #define FUNCTION_BOUNDARY 32
1411
1412 /* Alignment of field after `int : 0' in a structure. */
1413 #define EMPTY_FIELD_BOUNDARY 32
1414
1415 /* Every structure's size must be a multiple of this. */
1416 /* 8 is observed right on a DECstation and on riscos 4.02. */
1417 #define STRUCTURE_SIZE_BOUNDARY 8
1418
1419 /* There is no point aligning anything to a rounder boundary than this. */
1420 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1421
1422 /* All accesses must be aligned. */
1423 #define STRICT_ALIGNMENT 1
1424
1425 /* Define this if you wish to imitate the way many other C compilers
1426 handle alignment of bitfields and the structures that contain
1427 them.
1428
1429 The behavior is that the type written for a bit-field (`int',
1430 `short', or other integer type) imposes an alignment for the
1431 entire structure, as if the structure really did contain an
1432 ordinary field of that type. In addition, the bit-field is placed
1433 within the structure so that it would fit within such a field,
1434 not crossing a boundary for it.
1435
1436 Thus, on most machines, a bit-field whose type is written as `int'
1437 would not cross a four-byte boundary, and would force four-byte
1438 alignment for the whole structure. (The alignment used may not
1439 be four bytes; it is controlled by the other alignment
1440 parameters.)
1441
1442 If the macro is defined, its definition should be a C expression;
1443 a nonzero value for the expression enables this behavior. */
1444
1445 #define PCC_BITFIELD_TYPE_MATTERS 1
1446
1447 /* If defined, a C expression to compute the alignment given to a
1448 constant that is being placed in memory. CONSTANT is the constant
1449 and ALIGN is the alignment that the object would ordinarily have.
1450 The value of this macro is used instead of that alignment to align
1451 the object.
1452
1453 If this macro is not defined, then ALIGN is used.
1454
1455 The typical use of this macro is to increase alignment for string
1456 constants to be word aligned so that `strcpy' calls that copy
1457 constants can be done inline. */
1458
1459 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1460 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1461 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1462
1463 /* If defined, a C expression to compute the alignment for a static
1464 variable. TYPE is the data type, and ALIGN is the alignment that
1465 the object would ordinarily have. The value of this macro is used
1466 instead of that alignment to align the object.
1467
1468 If this macro is not defined, then ALIGN is used.
1469
1470 One use of this macro is to increase alignment of medium-size
1471 data to make it all fit in fewer cache lines. Another is to
1472 cause character arrays to be word-aligned so that `strcpy' calls
1473 that copy constants to character arrays can be done inline. */
1474
1475 #undef DATA_ALIGNMENT
1476 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1477 ((((ALIGN) < BITS_PER_WORD) \
1478 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1479 || TREE_CODE (TYPE) == UNION_TYPE \
1480 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1481
1482 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1483 character arrays to be word-aligned so that `strcpy' calls that copy
1484 constants to character arrays can be done inline, and 'strcmp' can be
1485 optimised to use word loads. */
1486 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1487 DATA_ALIGNMENT (TYPE, ALIGN)
1488
1489 #define PAD_VARARGS_DOWN \
1490 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1491
1492 /* Define if operations between registers always perform the operation
1493 on the full register even if a narrower mode is specified. */
1494 #define WORD_REGISTER_OPERATIONS
1495
1496 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1497 moves. All other references are zero extended. */
1498 #define LOAD_EXTEND_OP(MODE) \
1499 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1500 ? SIGN_EXTEND : ZERO_EXTEND)
1501
1502 /* Define this macro if it is advisable to hold scalars in registers
1503 in a wider mode than that declared by the program. In such cases,
1504 the value is constrained to be within the bounds of the declared
1505 type, but kept valid in the wider mode. The signedness of the
1506 extension may differ from that of the type. */
1507
1508 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1509 if (GET_MODE_CLASS (MODE) == MODE_INT \
1510 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1511 { \
1512 if ((MODE) == SImode) \
1513 (UNSIGNEDP) = 0; \
1514 (MODE) = Pmode; \
1515 }
1516
1517 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1518 Extensions of pointers to word_mode must be signed. */
1519 #define POINTERS_EXTEND_UNSIGNED false
1520
1521 /* Define if loading short immediate values into registers sign extends. */
1522 #define SHORT_IMMEDIATES_SIGN_EXTEND
1523
1524 /* The [d]clz instructions have the natural values at 0. */
1525
1526 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1527 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1528 \f
1529 /* Standard register usage. */
1530
1531 /* Number of hardware registers. We have:
1532
1533 - 32 integer registers
1534 - 32 floating point registers
1535 - 8 condition code registers
1536 - 2 accumulator registers (hi and lo)
1537 - 32 registers each for coprocessors 0, 2 and 3
1538 - 4 fake registers:
1539 - ARG_POINTER_REGNUM
1540 - FRAME_POINTER_REGNUM
1541 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1542 - CPRESTORE_SLOT_REGNUM
1543 - 2 dummy entries that were used at various times in the past.
1544 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1545 - 6 DSP control registers */
1546
1547 #define FIRST_PSEUDO_REGISTER 188
1548
1549 /* By default, fix the kernel registers ($26 and $27), the global
1550 pointer ($28) and the stack pointer ($29). This can change
1551 depending on the command-line options.
1552
1553 Regarding coprocessor registers: without evidence to the contrary,
1554 it's best to assume that each coprocessor register has a unique
1555 use. This can be overridden, in, e.g., mips_option_override or
1556 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1557 inappropriate for a particular target. */
1558
1559 #define FIXED_REGISTERS \
1560 { \
1561 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1562 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1563 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1564 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1565 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1566 /* COP0 registers */ \
1567 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1568 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1569 /* COP2 registers */ \
1570 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1571 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1572 /* COP3 registers */ \
1573 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1575 /* 6 DSP accumulator registers & 6 control registers */ \
1576 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1577 }
1578
1579
1580 /* Set up this array for o32 by default.
1581
1582 Note that we don't mark $31 as a call-clobbered register. The idea is
1583 that it's really the call instructions themselves which clobber $31.
1584 We don't care what the called function does with it afterwards.
1585
1586 This approach makes it easier to implement sibcalls. Unlike normal
1587 calls, sibcalls don't clobber $31, so the register reaches the
1588 called function in tact. EPILOGUE_USES says that $31 is useful
1589 to the called function. */
1590
1591 #define CALL_USED_REGISTERS \
1592 { \
1593 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1594 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1595 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1596 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1597 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1598 /* COP0 registers */ \
1599 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1600 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1601 /* COP2 registers */ \
1602 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1603 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1604 /* COP3 registers */ \
1605 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1606 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1607 /* 6 DSP accumulator registers & 6 control registers */ \
1608 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1609 }
1610
1611
1612 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1613
1614 #define CALL_REALLY_USED_REGISTERS \
1615 { /* General registers. */ \
1616 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1617 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1618 /* Floating-point registers. */ \
1619 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1620 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1621 /* Others. */ \
1622 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1623 /* COP0 registers */ \
1624 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1625 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1626 /* COP2 registers */ \
1627 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1628 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1629 /* COP3 registers */ \
1630 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1631 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1632 /* 6 DSP accumulator registers & 6 control registers */ \
1633 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1634 }
1635
1636 /* Internal macros to classify a register number as to whether it's a
1637 general purpose register, a floating point register, a
1638 multiply/divide register, or a status register. */
1639
1640 #define GP_REG_FIRST 0
1641 #define GP_REG_LAST 31
1642 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1643 #define GP_DBX_FIRST 0
1644 #define K0_REG_NUM (GP_REG_FIRST + 26)
1645 #define K1_REG_NUM (GP_REG_FIRST + 27)
1646 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1647
1648 #define FP_REG_FIRST 32
1649 #define FP_REG_LAST 63
1650 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1651 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1652
1653 #define MD_REG_FIRST 64
1654 #define MD_REG_LAST 65
1655 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1656 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1657
1658 /* The DWARF 2 CFA column which tracks the return address from a
1659 signal handler context. This means that to maintain backwards
1660 compatibility, no hard register can be assigned this column if it
1661 would need to be handled by the DWARF unwinder. */
1662 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1663
1664 #define ST_REG_FIRST 67
1665 #define ST_REG_LAST 74
1666 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1667
1668
1669 /* FIXME: renumber. */
1670 #define COP0_REG_FIRST 80
1671 #define COP0_REG_LAST 111
1672 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1673
1674 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1675 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1676 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1677
1678 #define COP2_REG_FIRST 112
1679 #define COP2_REG_LAST 143
1680 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1681
1682 #define COP3_REG_FIRST 144
1683 #define COP3_REG_LAST 175
1684 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1685
1686 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1687 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1688 #define ALL_COP_REG_LAST COP3_REG_LAST
1689 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1690
1691 #define DSP_ACC_REG_FIRST 176
1692 #define DSP_ACC_REG_LAST 181
1693 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1694
1695 #define AT_REGNUM (GP_REG_FIRST + 1)
1696 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1697 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1698
1699 /* A few bitfield locations for the coprocessor registers. */
1700 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1701 the cause register for the EIC interrupt mode. */
1702 #define CAUSE_IPL 10
1703 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1704 #define SR_IPL 10
1705 /* Exception Level is at bit 1 of the status register. */
1706 #define SR_EXL 1
1707 /* Interrupt Enable is at bit 0 of the status register. */
1708 #define SR_IE 0
1709
1710 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1711 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1712 should be used instead. */
1713 #define FPSW_REGNUM ST_REG_FIRST
1714
1715 #define GP_REG_P(REGNO) \
1716 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1717 #define M16_REG_P(REGNO) \
1718 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1719 #define M16STORE_REG_P(REGNO) \
1720 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1721 #define FP_REG_P(REGNO) \
1722 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1723 #define MD_REG_P(REGNO) \
1724 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1725 #define ST_REG_P(REGNO) \
1726 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1727 #define COP0_REG_P(REGNO) \
1728 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1729 #define COP2_REG_P(REGNO) \
1730 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1731 #define COP3_REG_P(REGNO) \
1732 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1733 #define ALL_COP_REG_P(REGNO) \
1734 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1735 /* Test if REGNO is one of the 6 new DSP accumulators. */
1736 #define DSP_ACC_REG_P(REGNO) \
1737 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1738 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1739 #define ACC_REG_P(REGNO) \
1740 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1741
1742 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1743
1744 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1745 to initialize the mips16 gp pseudo register. */
1746 #define CONST_GP_P(X) \
1747 (GET_CODE (X) == CONST \
1748 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1749 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1750
1751 /* Return coprocessor number from register number. */
1752
1753 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1754 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1755 : COP3_REG_P (REGNO) ? '3' : '?')
1756
1757
1758 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1759
1760 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1761 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1762
1763 #define MODES_TIEABLE_P mips_modes_tieable_p
1764
1765 /* Register to use for pushing function arguments. */
1766 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1767
1768 /* These two registers don't really exist: they get eliminated to either
1769 the stack or hard frame pointer. */
1770 #define ARG_POINTER_REGNUM 77
1771 #define FRAME_POINTER_REGNUM 78
1772
1773 /* $30 is not available on the mips16, so we use $17 as the frame
1774 pointer. */
1775 #define HARD_FRAME_POINTER_REGNUM \
1776 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1777
1778 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1779 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1780
1781 /* Register in which static-chain is passed to a function. */
1782 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1783
1784 /* Registers used as temporaries in prologue/epilogue code:
1785
1786 - If a MIPS16 PIC function needs access to _gp, it first loads
1787 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1788
1789 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1790 register. The register must not conflict with MIPS16_PIC_TEMP.
1791
1792 - If we aren't generating MIPS16 code, the prologue can also use
1793 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1794
1795 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1796 register.
1797
1798 If we're generating MIPS16 code, these registers must come from the
1799 core set of 8. The prologue registers mustn't conflict with any
1800 incoming arguments, the static chain pointer, or the frame pointer.
1801 The epilogue temporary mustn't conflict with the return registers,
1802 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1803 or the EH data registers.
1804
1805 If we're generating interrupt handlers, we use K0 as a temporary register
1806 in prologue/epilogue code. */
1807
1808 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1809 #define MIPS_PROLOGUE_TEMP_REGNUM \
1810 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1811 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1812 (TARGET_MIPS16 \
1813 ? (gcc_unreachable (), INVALID_REGNUM) \
1814 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1815 #define MIPS_EPILOGUE_TEMP_REGNUM \
1816 (cfun->machine->interrupt_handler_p \
1817 ? K0_REG_NUM \
1818 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1819
1820 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1821 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1822 #define MIPS_PROLOGUE_TEMP2(MODE) \
1823 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1824 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1825
1826 /* Define this macro if it is as good or better to call a constant
1827 function address than to call an address kept in a register. */
1828 #define NO_FUNCTION_CSE 1
1829
1830 /* The ABI-defined global pointer. Sometimes we use a different
1831 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1832 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1833
1834 /* We normally use $28 as the global pointer. However, when generating
1835 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1836 register instead. They can then avoid saving and restoring $28
1837 and perhaps avoid using a frame at all.
1838
1839 When a leaf function uses something other than $28, mips_expand_prologue
1840 will modify pic_offset_table_rtx in place. Take the register number
1841 from there after reload. */
1842 #define PIC_OFFSET_TABLE_REGNUM \
1843 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1844 \f
1845 /* Define the classes of registers for register constraints in the
1846 machine description. Also define ranges of constants.
1847
1848 One of the classes must always be named ALL_REGS and include all hard regs.
1849 If there is more than one class, another class must be named NO_REGS
1850 and contain no registers.
1851
1852 The name GENERAL_REGS must be the name of a class (or an alias for
1853 another name such as ALL_REGS). This is the class of registers
1854 that is allowed by "g" or "r" in a register constraint.
1855 Also, registers outside this class are allocated only when
1856 instructions express preferences for them.
1857
1858 The classes must be numbered in nondecreasing order; that is,
1859 a larger-numbered class must never be contained completely
1860 in a smaller-numbered class.
1861
1862 For any two classes, it is very desirable that there be another
1863 class that represents their union. */
1864
1865 enum reg_class
1866 {
1867 NO_REGS, /* no registers in set */
1868 M16_STORE_REGS, /* microMIPS store registers */
1869 M16_REGS, /* mips16 directly accessible registers */
1870 T_REG, /* mips16 T register ($24) */
1871 M16_T_REGS, /* mips16 registers plus T register */
1872 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1873 V1_REG, /* Register $v1 ($3) used for TLS access. */
1874 LEA_REGS, /* Every GPR except $25 */
1875 GR_REGS, /* integer registers */
1876 FP_REGS, /* floating point registers */
1877 MD0_REG, /* first multiply/divide register */
1878 MD1_REG, /* second multiply/divide register */
1879 MD_REGS, /* multiply/divide registers (hi/lo) */
1880 COP0_REGS, /* generic coprocessor classes */
1881 COP2_REGS,
1882 COP3_REGS,
1883 ST_REGS, /* status registers (fp status) */
1884 DSP_ACC_REGS, /* DSP accumulator registers */
1885 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1886 FRAME_REGS, /* $arg and $frame */
1887 GR_AND_MD0_REGS, /* union classes */
1888 GR_AND_MD1_REGS,
1889 GR_AND_MD_REGS,
1890 GR_AND_ACC_REGS,
1891 ALL_REGS, /* all registers */
1892 LIM_REG_CLASSES /* max value + 1 */
1893 };
1894
1895 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1896
1897 #define GENERAL_REGS GR_REGS
1898
1899 /* An initializer containing the names of the register classes as C
1900 string constants. These names are used in writing some of the
1901 debugging dumps. */
1902
1903 #define REG_CLASS_NAMES \
1904 { \
1905 "NO_REGS", \
1906 "M16_STORE_REGS", \
1907 "M16_REGS", \
1908 "T_REG", \
1909 "M16_T_REGS", \
1910 "PIC_FN_ADDR_REG", \
1911 "V1_REG", \
1912 "LEA_REGS", \
1913 "GR_REGS", \
1914 "FP_REGS", \
1915 "MD0_REG", \
1916 "MD1_REG", \
1917 "MD_REGS", \
1918 /* coprocessor registers */ \
1919 "COP0_REGS", \
1920 "COP2_REGS", \
1921 "COP3_REGS", \
1922 "ST_REGS", \
1923 "DSP_ACC_REGS", \
1924 "ACC_REGS", \
1925 "FRAME_REGS", \
1926 "GR_AND_MD0_REGS", \
1927 "GR_AND_MD1_REGS", \
1928 "GR_AND_MD_REGS", \
1929 "GR_AND_ACC_REGS", \
1930 "ALL_REGS" \
1931 }
1932
1933 /* An initializer containing the contents of the register classes,
1934 as integers which are bit masks. The Nth integer specifies the
1935 contents of class N. The way the integer MASK is interpreted is
1936 that register R is in the class if `MASK & (1 << R)' is 1.
1937
1938 When the machine has more than 32 registers, an integer does not
1939 suffice. Then the integers are replaced by sub-initializers,
1940 braced groupings containing several integers. Each
1941 sub-initializer must be suitable as an initializer for the type
1942 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1943
1944 #define REG_CLASS_CONTENTS \
1945 { \
1946 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1947 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
1948 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1949 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1950 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1951 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1952 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1953 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1954 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1955 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1956 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1957 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1958 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1959 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1960 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1961 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1962 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1963 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1964 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1965 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1966 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1967 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1968 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1969 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1970 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1971 }
1972
1973
1974 /* A C expression whose value is a register class containing hard
1975 register REGNO. In general there is more that one such class;
1976 choose a class which is "minimal", meaning that no smaller class
1977 also contains the register. */
1978
1979 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1980
1981 /* A macro whose definition is the name of the class to which a
1982 valid base register must belong. A base register is one used in
1983 an address which is the register value plus a displacement. */
1984
1985 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1986
1987 /* A macro whose definition is the name of the class to which a
1988 valid index register must belong. An index register is one used
1989 in an address where its value is either multiplied by a scale
1990 factor or added to another register (as well as added to a
1991 displacement). */
1992
1993 #define INDEX_REG_CLASS NO_REGS
1994
1995 /* We generally want to put call-clobbered registers ahead of
1996 call-saved ones. (IRA expects this.) */
1997
1998 #define REG_ALLOC_ORDER \
1999 { /* Accumulator registers. When GPRs and accumulators have equal \
2000 cost, we generally prefer to use accumulators. For example, \
2001 a division of multiplication result is better allocated to LO, \
2002 so that we put the MFLO at the point of use instead of at the \
2003 point of definition. It's also needed if we're to take advantage \
2004 of the extra accumulators available with -mdspr2. In some cases, \
2005 it can also help to reduce register pressure. */ \
2006 64, 65,176,177,178,179,180,181, \
2007 /* Call-clobbered GPRs. */ \
2008 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2009 24, 25, 31, \
2010 /* The global pointer. This is call-clobbered for o32 and o64 \
2011 abicalls, call-saved for n32 and n64 abicalls, and a program \
2012 invariant otherwise. Putting it between the call-clobbered \
2013 and call-saved registers should cope with all eventualities. */ \
2014 28, \
2015 /* Call-saved GPRs. */ \
2016 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2017 /* GPRs that can never be exposed to the register allocator. */ \
2018 0, 26, 27, 29, \
2019 /* Call-clobbered FPRs. */ \
2020 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2021 48, 49, 50, 51, \
2022 /* FPRs that are usually call-saved. The odd ones are actually \
2023 call-clobbered for n32, but listing them ahead of the even \
2024 registers might encourage the register allocator to fragment \
2025 the available FPR pairs. We need paired FPRs to store long \
2026 doubles, so it isn't clear that using a different order \
2027 for n32 would be a win. */ \
2028 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2029 /* None of the remaining classes have defined call-saved \
2030 registers. */ \
2031 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2032 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2033 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2034 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2035 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2036 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2037 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2038 182,183,184,185,186,187 \
2039 }
2040
2041 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
2042 to be rearranged based on a particular function. On the mips16, we
2043 want to allocate $24 (T_REG) before other registers for
2044 instructions for which it is possible. */
2045
2046 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2047
2048 /* True if VALUE is an unsigned 6-bit number. */
2049
2050 #define UIMM6_OPERAND(VALUE) \
2051 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2052
2053 /* True if VALUE is a signed 10-bit number. */
2054
2055 #define IMM10_OPERAND(VALUE) \
2056 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2057
2058 /* True if VALUE is a signed 16-bit number. */
2059
2060 #define SMALL_OPERAND(VALUE) \
2061 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2062
2063 /* True if VALUE is an unsigned 16-bit number. */
2064
2065 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2066 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2067
2068 /* True if VALUE can be loaded into a register using LUI. */
2069
2070 #define LUI_OPERAND(VALUE) \
2071 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2072 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2073
2074 /* Return a value X with the low 16 bits clear, and such that
2075 VALUE - X is a signed 16-bit value. */
2076
2077 #define CONST_HIGH_PART(VALUE) \
2078 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2079
2080 #define CONST_LOW_PART(VALUE) \
2081 ((VALUE) - CONST_HIGH_PART (VALUE))
2082
2083 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2084 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2085 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2086 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2087
2088 /* The HI and LO registers can only be reloaded via the general
2089 registers. Condition code registers can only be loaded to the
2090 general registers, and from the floating point registers. */
2091
2092 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2093 mips_secondary_reload_class (CLASS, MODE, X, true)
2094 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2095 mips_secondary_reload_class (CLASS, MODE, X, false)
2096
2097 /* Return the maximum number of consecutive registers
2098 needed to represent mode MODE in a register of class CLASS. */
2099
2100 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2101
2102 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2103 mips_cannot_change_mode_class (FROM, TO, CLASS)
2104 \f
2105 /* Stack layout; function entry, exit and calling. */
2106
2107 #define STACK_GROWS_DOWNWARD
2108
2109 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2110
2111 /* Size of the area allocated in the frame to save the GP. */
2112
2113 #define MIPS_GP_SAVE_AREA_SIZE \
2114 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2115
2116 /* The offset of the first local variable from the frame pointer. See
2117 mips_compute_frame_info for details about the frame layout. */
2118
2119 #define STARTING_FRAME_OFFSET \
2120 (FRAME_GROWS_DOWNWARD \
2121 ? 0 \
2122 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2123
2124 #define RETURN_ADDR_RTX mips_return_addr
2125
2126 /* Mask off the MIPS16 ISA bit in unwind addresses.
2127
2128 The reason for this is a little subtle. When unwinding a call,
2129 we are given the call's return address, which on most targets
2130 is the address of the following instruction. However, what we
2131 actually want to find is the EH region for the call itself.
2132 The target-independent unwind code therefore searches for "RA - 1".
2133
2134 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2135 RA - 1 is therefore the real (even-valued) start of the return
2136 instruction. EH region labels are usually odd-valued MIPS16 symbols
2137 too, so a search for an even address within a MIPS16 region would
2138 usually work.
2139
2140 However, there is an exception. If the end of an EH region is also
2141 the end of a function, the end label is allowed to be even. This is
2142 necessary because a following non-MIPS16 function may also need EH
2143 information for its first instruction.
2144
2145 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2146 non-ISA-encoded address. This probably isn't ideal, but it is
2147 the traditional (legacy) behavior. It is therefore only safe
2148 to search MIPS EH regions for an _odd-valued_ address.
2149
2150 Masking off the ISA bit means that the target-independent code
2151 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2152 #define MASK_RETURN_ADDR GEN_INT (-2)
2153
2154
2155 /* Similarly, don't use the least-significant bit to tell pointers to
2156 code from vtable index. */
2157
2158 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2159
2160 /* The eliminations to $17 are only used for mips16 code. See the
2161 definition of HARD_FRAME_POINTER_REGNUM. */
2162
2163 #define ELIMINABLE_REGS \
2164 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2165 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2166 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2167 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2168 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2169 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2170
2171 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2172 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2173
2174 /* Allocate stack space for arguments at the beginning of each function. */
2175 #define ACCUMULATE_OUTGOING_ARGS 1
2176
2177 /* The argument pointer always points to the first argument. */
2178 #define FIRST_PARM_OFFSET(FNDECL) 0
2179
2180 /* o32 and o64 reserve stack space for all argument registers. */
2181 #define REG_PARM_STACK_SPACE(FNDECL) \
2182 (TARGET_OLDABI \
2183 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2184 : 0)
2185
2186 /* Define this if it is the responsibility of the caller to
2187 allocate the area reserved for arguments passed in registers.
2188 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2189 of this macro is to determine whether the space is included in
2190 `crtl->outgoing_args_size'. */
2191 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2192
2193 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2194 \f
2195 /* Symbolic macros for the registers used to return integer and floating
2196 point values. */
2197
2198 #define GP_RETURN (GP_REG_FIRST + 2)
2199 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2200
2201 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2202
2203 /* Symbolic macros for the first/last argument registers. */
2204
2205 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2206 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2207 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2208 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2209
2210 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2211 are used for returning complex double values in soft-float code, so $6 is the
2212 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2213 $gp itself as the temporary. */
2214 #define POST_CALL_TMP_REG \
2215 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2216
2217 /* 1 if N is a possible register number for function argument passing.
2218 We have no FP argument registers when soft-float. When FP registers
2219 are 32 bits, we can't directly reference the odd numbered ones. */
2220
2221 #define FUNCTION_ARG_REGNO_P(N) \
2222 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2223 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2224 && !fixed_regs[N])
2225 \f
2226 /* This structure has to cope with two different argument allocation
2227 schemes. Most MIPS ABIs view the arguments as a structure, of which
2228 the first N words go in registers and the rest go on the stack. If I
2229 < N, the Ith word might go in Ith integer argument register or in a
2230 floating-point register. For these ABIs, we only need to remember
2231 the offset of the current argument into the structure.
2232
2233 The EABI instead allocates the integer and floating-point arguments
2234 separately. The first N words of FP arguments go in FP registers,
2235 the rest go on the stack. Likewise, the first N words of the other
2236 arguments go in integer registers, and the rest go on the stack. We
2237 need to maintain three counts: the number of integer registers used,
2238 the number of floating-point registers used, and the number of words
2239 passed on the stack.
2240
2241 We could keep separate information for the two ABIs (a word count for
2242 the standard ABIs, and three separate counts for the EABI). But it
2243 seems simpler to view the standard ABIs as forms of EABI that do not
2244 allocate floating-point registers.
2245
2246 So for the standard ABIs, the first N words are allocated to integer
2247 registers, and mips_function_arg decides on an argument-by-argument
2248 basis whether that argument should really go in an integer register,
2249 or in a floating-point one. */
2250
2251 typedef struct mips_args {
2252 /* Always true for varargs functions. Otherwise true if at least
2253 one argument has been passed in an integer register. */
2254 int gp_reg_found;
2255
2256 /* The number of arguments seen so far. */
2257 unsigned int arg_number;
2258
2259 /* The number of integer registers used so far. For all ABIs except
2260 EABI, this is the number of words that have been added to the
2261 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2262 unsigned int num_gprs;
2263
2264 /* For EABI, the number of floating-point registers used so far. */
2265 unsigned int num_fprs;
2266
2267 /* The number of words passed on the stack. */
2268 unsigned int stack_words;
2269
2270 /* On the mips16, we need to keep track of which floating point
2271 arguments were passed in general registers, but would have been
2272 passed in the FP regs if this were a 32-bit function, so that we
2273 can move them to the FP regs if we wind up calling a 32-bit
2274 function. We record this information in fp_code, encoded in base
2275 four. A zero digit means no floating point argument, a one digit
2276 means an SFmode argument, and a two digit means a DFmode argument,
2277 and a three digit is not used. The low order digit is the first
2278 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2279 an SFmode argument. ??? A more sophisticated approach will be
2280 needed if MIPS_ABI != ABI_32. */
2281 int fp_code;
2282
2283 /* True if the function has a prototype. */
2284 int prototype;
2285 } CUMULATIVE_ARGS;
2286
2287 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2288 for a call to a function whose data type is FNTYPE.
2289 For a library call, FNTYPE is 0. */
2290
2291 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2292 mips_init_cumulative_args (&CUM, FNTYPE)
2293
2294 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2295 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2296
2297 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2298 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2299
2300 /* True if using EABI and varargs can be passed in floating-point
2301 registers. Under these conditions, we need a more complex form
2302 of va_list, which tracks GPR, FPR and stack arguments separately. */
2303 #define EABI_FLOAT_VARARGS_P \
2304 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2305
2306 \f
2307 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2308
2309 /* Treat LOC as a byte offset from the stack pointer and round it up
2310 to the next fully-aligned offset. */
2311 #define MIPS_STACK_ALIGN(LOC) \
2312 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2313
2314 \f
2315 /* Output assembler code to FILE to increment profiler label # LABELNO
2316 for profiling a function entry. */
2317
2318 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2319
2320 /* The profiler preserves all interesting registers, including $31. */
2321 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2322
2323 /* No mips port has ever used the profiler counter word, so don't emit it
2324 or the label for it. */
2325
2326 #define NO_PROFILE_COUNTERS 1
2327
2328 /* Define this macro if the code for function profiling should come
2329 before the function prologue. Normally, the profiling code comes
2330 after. */
2331
2332 /* #define PROFILE_BEFORE_PROLOGUE */
2333
2334 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2335 the stack pointer does not matter. The value is tested only in
2336 functions that have frame pointers.
2337 No definition is equivalent to always zero. */
2338
2339 #define EXIT_IGNORE_STACK 1
2340
2341 \f
2342 /* Trampolines are a block of code followed by two pointers. */
2343
2344 #define TRAMPOLINE_SIZE \
2345 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2346
2347 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2348 pointers from a single LUI base. */
2349
2350 #define TRAMPOLINE_ALIGNMENT 64
2351
2352 /* mips_trampoline_init calls this library function to flush
2353 program and data caches. */
2354
2355 #ifndef CACHE_FLUSH_FUNC
2356 #define CACHE_FLUSH_FUNC "_flush_cache"
2357 #endif
2358
2359 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2360 /* Flush both caches. We need to flush the data cache in case \
2361 the system has a write-back cache. */ \
2362 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2363 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2364 GEN_INT (3), TYPE_MODE (integer_type_node))
2365
2366 \f
2367 /* Addressing modes, and classification of registers for them. */
2368
2369 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2370 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2371 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2372 \f
2373 /* Maximum number of registers that can appear in a valid memory address. */
2374
2375 #define MAX_REGS_PER_ADDRESS 1
2376
2377 /* Check for constness inline but use mips_legitimate_address_p
2378 to check whether a constant really is an address. */
2379
2380 #define CONSTANT_ADDRESS_P(X) \
2381 (CONSTANT_P (X) && memory_address_p (SImode, X))
2382
2383 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2384 'the start of the function that this code is output in'. */
2385
2386 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2387 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2388 asm_fprintf ((FILE), "%U%s", \
2389 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2390 else \
2391 asm_fprintf ((FILE), "%U%s", (NAME))
2392 \f
2393 /* Flag to mark a function decl symbol that requires a long call. */
2394 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2395 #define SYMBOL_REF_LONG_CALL_P(X) \
2396 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2397
2398 /* This flag marks functions that cannot be lazily bound. */
2399 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2400 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2401 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2402
2403 /* True if we're generating a form of MIPS16 code in which jump tables
2404 are stored in the text section and encoded as 16-bit PC-relative
2405 offsets. This is only possible when general text loads are allowed,
2406 since the table access itself will be an "lh" instruction. If the
2407 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2408 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2409
2410 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2411
2412 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2413
2414 /* Only use short offsets if their range will not overflow. */
2415 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2416 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2417 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2418 : SImode)
2419
2420 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2421
2422 /* Define this as 1 if `char' should by default be signed; else as 0. */
2423 #ifndef DEFAULT_SIGNED_CHAR
2424 #define DEFAULT_SIGNED_CHAR 1
2425 #endif
2426
2427 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2428 we generally don't want to use them for copying arbitrary data.
2429 A single N-word move is usually the same cost as N single-word moves. */
2430 #define MOVE_MAX UNITS_PER_WORD
2431 #define MAX_MOVE_MAX 8
2432
2433 /* Define this macro as a C expression which is nonzero if
2434 accessing less than a word of memory (i.e. a `char' or a
2435 `short') is no faster than accessing a word of memory, i.e., if
2436 such access require more than one instruction or if there is no
2437 difference in cost between byte and (aligned) word loads.
2438
2439 On RISC machines, it tends to generate better code to define
2440 this as 1, since it avoids making a QI or HI mode register.
2441
2442 But, generating word accesses for -mips16 is generally bad as shifts
2443 (often extended) would be needed for byte accesses. */
2444 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2445
2446 /* Standard MIPS integer shifts truncate the shift amount to the
2447 width of the shifted operand. However, Loongson vector shifts
2448 do not truncate the shift amount at all. */
2449 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2450
2451 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2452 is done just by pretending it is already truncated. */
2453 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2454 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2455
2456
2457 /* Specify the machine mode that pointers have.
2458 After generation of rtl, the compiler makes no further distinction
2459 between pointers and any other objects of this machine mode. */
2460
2461 #ifndef Pmode
2462 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2463 #endif
2464
2465 /* Give call MEMs SImode since it is the "most permissive" mode
2466 for both 32-bit and 64-bit targets. */
2467
2468 #define FUNCTION_MODE SImode
2469
2470 \f
2471 /* We allocate $fcc registers by hand and can't cope with moves of
2472 CCmode registers to and from pseudos (or memory). */
2473 #define AVOID_CCMODE_COPIES
2474
2475 /* A C expression for the cost of a branch instruction. A value of
2476 1 is the default; other values are interpreted relative to that. */
2477
2478 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2479 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2480
2481 /* The MIPS port has several functions that return an instruction count.
2482 Multiplying the count by this value gives the number of bytes that
2483 the instructions occupy. */
2484 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2485
2486 /* The length of a NOP in bytes. */
2487 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2488
2489 /* If defined, modifies the length assigned to instruction INSN as a
2490 function of the context in which it is used. LENGTH is an lvalue
2491 that contains the initially computed length of the insn and should
2492 be updated with the correct length of the insn. */
2493 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2494 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2495
2496 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2497 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2498 its operands. */
2499 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2500 "%*" OPCODE "%?\t" OPERANDS "%/"
2501
2502 /* Return an asm string that forces INSN to be treated as an absolute
2503 J or JAL instruction instead of an assembler macro. */
2504 #define MIPS_ABSOLUTE_JUMP(INSN) \
2505 (TARGET_ABICALLS_PIC2 \
2506 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2507 : INSN)
2508
2509 /* Return the asm template for a call. INSN is the instruction's mnemonic
2510 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2511 number of the target. SIZE_OPNO is the operand number of the argument size
2512 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2513 -1 and the call is indirect, use the function symbol from the call
2514 attributes to attach a R_MIPS_JALR relocation to the call.
2515
2516 When generating GOT code without explicit relocation operators,
2517 all calls should use assembly macros. Otherwise, all indirect
2518 calls should use "jr" or "jalr"; we will arrange to restore $gp
2519 afterwards if necessary. Finally, we can only generate direct
2520 calls for -mabicalls by temporarily switching to non-PIC mode.
2521
2522 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2523 instruction is in the delay slot of jal(r). */
2524 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2525 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2526 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2527 : REG_P (OPERANDS[TARGET_OPNO]) \
2528 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2529 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2530 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2531 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2532 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2533 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2534 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2535 ? MIPS_ABSOLUTE_JUMP ("%*" INSN "%!\t%" #TARGET_OPNO "%/") \
2536 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/")) \
2537
2538 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2539 "jrc" when nop is in the delay slot of "jr". */
2540
2541 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2542 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2543 ? "%*j\t%" #OPNO "%/" \
2544 : REG_P (OPERANDS[OPNO]) \
2545 ? "%*jr%:\t%" #OPNO \
2546 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2547
2548 \f
2549 /* Control the assembler format that we output. */
2550
2551 /* Output to assembler file text saying following lines
2552 may contain character constants, extra white space, comments, etc. */
2553
2554 #ifndef ASM_APP_ON
2555 #define ASM_APP_ON " #APP\n"
2556 #endif
2557
2558 /* Output to assembler file text saying following lines
2559 no longer contain unusual constructs. */
2560
2561 #ifndef ASM_APP_OFF
2562 #define ASM_APP_OFF " #NO_APP\n"
2563 #endif
2564
2565 #define REGISTER_NAMES \
2566 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2567 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2568 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2569 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2570 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2571 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2572 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2573 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2574 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2575 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2576 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2577 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2578 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2579 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2580 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2581 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2582 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2583 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2584 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2585 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2586 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2587 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2588 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2589 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2590
2591 /* List the "software" names for each register. Also list the numerical
2592 names for $fp and $sp. */
2593
2594 #define ADDITIONAL_REGISTER_NAMES \
2595 { \
2596 { "$29", 29 + GP_REG_FIRST }, \
2597 { "$30", 30 + GP_REG_FIRST }, \
2598 { "at", 1 + GP_REG_FIRST }, \
2599 { "v0", 2 + GP_REG_FIRST }, \
2600 { "v1", 3 + GP_REG_FIRST }, \
2601 { "a0", 4 + GP_REG_FIRST }, \
2602 { "a1", 5 + GP_REG_FIRST }, \
2603 { "a2", 6 + GP_REG_FIRST }, \
2604 { "a3", 7 + GP_REG_FIRST }, \
2605 { "t0", 8 + GP_REG_FIRST }, \
2606 { "t1", 9 + GP_REG_FIRST }, \
2607 { "t2", 10 + GP_REG_FIRST }, \
2608 { "t3", 11 + GP_REG_FIRST }, \
2609 { "t4", 12 + GP_REG_FIRST }, \
2610 { "t5", 13 + GP_REG_FIRST }, \
2611 { "t6", 14 + GP_REG_FIRST }, \
2612 { "t7", 15 + GP_REG_FIRST }, \
2613 { "s0", 16 + GP_REG_FIRST }, \
2614 { "s1", 17 + GP_REG_FIRST }, \
2615 { "s2", 18 + GP_REG_FIRST }, \
2616 { "s3", 19 + GP_REG_FIRST }, \
2617 { "s4", 20 + GP_REG_FIRST }, \
2618 { "s5", 21 + GP_REG_FIRST }, \
2619 { "s6", 22 + GP_REG_FIRST }, \
2620 { "s7", 23 + GP_REG_FIRST }, \
2621 { "t8", 24 + GP_REG_FIRST }, \
2622 { "t9", 25 + GP_REG_FIRST }, \
2623 { "k0", 26 + GP_REG_FIRST }, \
2624 { "k1", 27 + GP_REG_FIRST }, \
2625 { "gp", 28 + GP_REG_FIRST }, \
2626 { "sp", 29 + GP_REG_FIRST }, \
2627 { "fp", 30 + GP_REG_FIRST }, \
2628 { "ra", 31 + GP_REG_FIRST } \
2629 }
2630
2631 #define DBR_OUTPUT_SEQEND(STREAM) \
2632 do \
2633 { \
2634 /* Undo the effect of '%*'. */ \
2635 mips_pop_asm_switch (&mips_nomacro); \
2636 mips_pop_asm_switch (&mips_noreorder); \
2637 /* Emit a blank line after the delay slot for emphasis. */ \
2638 fputs ("\n", STREAM); \
2639 } \
2640 while (0)
2641
2642 /* The MIPS implementation uses some labels for its own purpose. The
2643 following lists what labels are created, and are all formed by the
2644 pattern $L[a-z].*. The machine independent portion of GCC creates
2645 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2646
2647 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2648 $Lb[0-9]+ Begin blocks for MIPS debug support
2649 $Lc[0-9]+ Label for use in s<xx> operation.
2650 $Le[0-9]+ End blocks for MIPS debug support */
2651
2652 #undef ASM_DECLARE_OBJECT_NAME
2653 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2654 mips_declare_object (STREAM, NAME, "", ":\n")
2655
2656 /* Globalizing directive for a label. */
2657 #define GLOBAL_ASM_OP "\t.globl\t"
2658
2659 /* This says how to define a global common symbol. */
2660
2661 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2662
2663 /* This says how to define a local common symbol (i.e., not visible to
2664 linker). */
2665
2666 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2667 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2668 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2669 #endif
2670
2671 /* This says how to output an external. It would be possible not to
2672 output anything and let undefined symbol become external. However
2673 the assembler uses length information on externals to allocate in
2674 data/sdata bss/sbss, thereby saving exec time. */
2675
2676 #undef ASM_OUTPUT_EXTERNAL
2677 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2678 mips_output_external(STREAM,DECL,NAME)
2679
2680 /* This is how to declare a function name. The actual work of
2681 emitting the label is moved to function_prologue, so that we can
2682 get the line number correctly emitted before the .ent directive,
2683 and after any .file directives. Define as empty so that the function
2684 is not declared before the .ent directive elsewhere. */
2685
2686 #undef ASM_DECLARE_FUNCTION_NAME
2687 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2688
2689 /* This is how to store into the string LABEL
2690 the symbol_ref name of an internal numbered label where
2691 PREFIX is the class of label and NUM is the number within the class.
2692 This is suitable for output with `assemble_name'. */
2693
2694 #undef ASM_GENERATE_INTERNAL_LABEL
2695 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2696 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2697
2698 /* Print debug labels as "foo = ." rather than "foo:" because they should
2699 represent a byte pointer rather than an ISA-encoded address. This is
2700 particularly important for code like:
2701
2702 $LFBxxx = .
2703 .cfi_startproc
2704 ...
2705 .section .gcc_except_table,...
2706 ...
2707 .uleb128 foo-$LFBxxx
2708
2709 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2710 likewise a byte pointer rather than an ISA-encoded address.
2711
2712 At the time of writing, this hook is not used for the function end
2713 label:
2714
2715 $LFExxx:
2716 .end foo
2717
2718 But this doesn't matter, because GAS doesn't treat a pre-.end label
2719 as a MIPS16 one anyway. */
2720
2721 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2722 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2723
2724 /* This is how to output an element of a case-vector that is absolute. */
2725
2726 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2727 fprintf (STREAM, "\t%s\t%sL%d\n", \
2728 ptr_mode == DImode ? ".dword" : ".word", \
2729 LOCAL_LABEL_PREFIX, \
2730 VALUE)
2731
2732 /* This is how to output an element of a case-vector. We can make the
2733 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2734 is supported. */
2735
2736 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2737 do { \
2738 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2739 { \
2740 if (GET_MODE (BODY) == HImode) \
2741 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2742 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2743 else \
2744 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2745 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2746 } \
2747 else if (TARGET_GPWORD) \
2748 fprintf (STREAM, "\t%s\t%sL%d\n", \
2749 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2750 LOCAL_LABEL_PREFIX, VALUE); \
2751 else if (TARGET_RTP_PIC) \
2752 { \
2753 /* Make the entry relative to the start of the function. */ \
2754 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2755 fprintf (STREAM, "\t%s\t%sL%d-", \
2756 Pmode == DImode ? ".dword" : ".word", \
2757 LOCAL_LABEL_PREFIX, VALUE); \
2758 assemble_name (STREAM, XSTR (fnsym, 0)); \
2759 fprintf (STREAM, "\n"); \
2760 } \
2761 else \
2762 fprintf (STREAM, "\t%s\t%sL%d\n", \
2763 ptr_mode == DImode ? ".dword" : ".word", \
2764 LOCAL_LABEL_PREFIX, VALUE); \
2765 } while (0)
2766
2767 /* This is how to output an assembler line
2768 that says to advance the location counter
2769 to a multiple of 2**LOG bytes. */
2770
2771 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2772 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2773
2774 /* This is how to output an assembler line to advance the location
2775 counter by SIZE bytes. */
2776
2777 #undef ASM_OUTPUT_SKIP
2778 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2779 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2780
2781 /* This is how to output a string. */
2782 #undef ASM_OUTPUT_ASCII
2783 #define ASM_OUTPUT_ASCII mips_output_ascii
2784
2785 \f
2786 /* Default to -G 8 */
2787 #ifndef MIPS_DEFAULT_GVALUE
2788 #define MIPS_DEFAULT_GVALUE 8
2789 #endif
2790
2791 /* Define the strings to put out for each section in the object file. */
2792 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2793 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2794
2795 #undef READONLY_DATA_SECTION_ASM_OP
2796 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2797 \f
2798 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2799 do \
2800 { \
2801 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2802 TARGET_64BIT ? "daddiu" : "addiu", \
2803 reg_names[STACK_POINTER_REGNUM], \
2804 reg_names[STACK_POINTER_REGNUM], \
2805 TARGET_64BIT ? "sd" : "sw", \
2806 reg_names[REGNO], \
2807 reg_names[STACK_POINTER_REGNUM]); \
2808 } \
2809 while (0)
2810
2811 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2812 do \
2813 { \
2814 mips_push_asm_switch (&mips_noreorder); \
2815 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2816 TARGET_64BIT ? "ld" : "lw", \
2817 reg_names[REGNO], \
2818 reg_names[STACK_POINTER_REGNUM], \
2819 TARGET_64BIT ? "daddu" : "addu", \
2820 reg_names[STACK_POINTER_REGNUM], \
2821 reg_names[STACK_POINTER_REGNUM]); \
2822 mips_pop_asm_switch (&mips_noreorder); \
2823 } \
2824 while (0)
2825
2826 /* How to start an assembler comment.
2827 The leading space is important (the mips native assembler requires it). */
2828 #ifndef ASM_COMMENT_START
2829 #define ASM_COMMENT_START " #"
2830 #endif
2831 \f
2832 #undef SIZE_TYPE
2833 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2834
2835 #undef PTRDIFF_TYPE
2836 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2837
2838 /* The maximum number of bytes that can be copied by one iteration of
2839 a movmemsi loop; see mips_block_move_loop. */
2840 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2841 (UNITS_PER_WORD * 4)
2842
2843 /* The maximum number of bytes that can be copied by a straight-line
2844 implementation of movmemsi; see mips_block_move_straight. We want
2845 to make sure that any loop-based implementation will iterate at
2846 least twice. */
2847 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2848 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2849
2850 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2851 values were determined experimentally by benchmarking with CSiBE.
2852 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2853 for o32 where we have to restore $gp afterwards as well as make an
2854 indirect call), but in practice, bumping this up higher for
2855 TARGET_ABICALLS doesn't make much difference to code size. */
2856
2857 #define MIPS_CALL_RATIO 8
2858
2859 /* Any loop-based implementation of movmemsi will have at least
2860 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2861 moves, so allow individual copies of fewer elements.
2862
2863 When movmemsi is not available, use a value approximating
2864 the length of a memcpy call sequence, so that move_by_pieces
2865 will generate inline code if it is shorter than a function call.
2866 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2867 we'll have to generate a load/store pair for each, halve the
2868 value of MIPS_CALL_RATIO to take that into account. */
2869
2870 #define MOVE_RATIO(speed) \
2871 (HAVE_movmemsi \
2872 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2873 : MIPS_CALL_RATIO / 2)
2874
2875 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2876 mips_move_by_pieces_p (SIZE, ALIGN)
2877
2878 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2879 of the length of a memset call, but use the default otherwise. */
2880
2881 #define CLEAR_RATIO(speed)\
2882 ((speed) ? 15 : MIPS_CALL_RATIO)
2883
2884 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2885 optimizing for size adjust the ratio to account for the overhead of
2886 loading the constant and replicating it across the word. */
2887
2888 #define SET_RATIO(speed) \
2889 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2890
2891 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2892 mips_store_by_pieces_p (SIZE, ALIGN)
2893 \f
2894 /* Since the bits of the _init and _fini function is spread across
2895 many object files, each potentially with its own GP, we must assume
2896 we need to load our GP. We don't preserve $gp or $ra, since each
2897 init/fini chunk is supposed to initialize $gp, and crti/crtn
2898 already take care of preserving $ra and, when appropriate, $gp. */
2899 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2900 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2901 asm (SECTION_OP "\n\
2902 .set push\n\
2903 .set nomips16\n\
2904 .set noreorder\n\
2905 bal 1f\n\
2906 nop\n\
2907 1: .cpload $31\n\
2908 .set reorder\n\
2909 jal " USER_LABEL_PREFIX #FUNC "\n\
2910 .set pop\n\
2911 " TEXT_SECTION_ASM_OP);
2912 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2913 || (defined _ABI64 && _MIPS_SIM == _ABI64))
2914 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2915 asm (SECTION_OP "\n\
2916 .set push\n\
2917 .set nomips16\n\
2918 .set noreorder\n\
2919 bal 1f\n\
2920 nop\n\
2921 1: .set reorder\n\
2922 .cpsetup $31, $2, 1b\n\
2923 jal " USER_LABEL_PREFIX #FUNC "\n\
2924 .set pop\n\
2925 " TEXT_SECTION_ASM_OP);
2926 #endif
2927
2928 #ifndef HAVE_AS_TLS
2929 #define HAVE_AS_TLS 0
2930 #endif
2931
2932 #ifndef HAVE_AS_NAN
2933 #define HAVE_AS_NAN 0
2934 #endif
2935
2936 #ifndef USED_FOR_TARGET
2937 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2938 struct mips_asm_switch {
2939 /* The FOO in the description above. */
2940 const char *name;
2941
2942 /* The current block nesting level, or 0 if we aren't in a block. */
2943 int nesting_level;
2944 };
2945
2946 extern const enum reg_class mips_regno_to_class[];
2947 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2948 extern const char *current_function_file; /* filename current function is in */
2949 extern int num_source_filenames; /* current .file # */
2950 extern struct mips_asm_switch mips_noreorder;
2951 extern struct mips_asm_switch mips_nomacro;
2952 extern struct mips_asm_switch mips_noat;
2953 extern int mips_dbx_regno[];
2954 extern int mips_dwarf_regno[];
2955 extern bool mips_split_p[];
2956 extern bool mips_split_hi_p[];
2957 extern bool mips_use_pcrel_pool_p[];
2958 extern const char *mips_lo_relocs[];
2959 extern const char *mips_hi_relocs[];
2960 extern enum processor mips_arch; /* which cpu to codegen for */
2961 extern enum processor mips_tune; /* which cpu to schedule for */
2962 extern int mips_isa; /* architectural level */
2963 extern int mips_isa_rev;
2964 extern const struct mips_cpu_info *mips_arch_info;
2965 extern const struct mips_cpu_info *mips_tune_info;
2966 extern unsigned int mips_base_compression_flags;
2967 extern GTY(()) struct target_globals *mips16_globals;
2968 #endif
2969
2970 /* Enable querying of DFA units. */
2971 #define CPU_UNITS_QUERY 1
2972
2973 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2974 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2975
2976 /* As on most targets, we want the .eh_frame section to be read-only where
2977 possible. And as on most targets, this means two things:
2978
2979 (a) Non-locally-binding pointers must have an indirect encoding,
2980 so that the addresses in the .eh_frame section itself become
2981 locally-binding.
2982
2983 (b) A shared library's .eh_frame section must encode locally-binding
2984 pointers in a relative (relocation-free) form.
2985
2986 However, MIPS has traditionally not allowed directives like:
2987
2988 .long x-.
2989
2990 in cases where "x" is in a different section, or is not defined in the
2991 same assembly file. We are therefore unable to emit the PC-relative
2992 form required by (b) at assembly time.
2993
2994 Fortunately, the linker is able to convert absolute addresses into
2995 PC-relative addresses on our behalf. Unfortunately, only certain
2996 versions of the linker know how to do this for indirect pointers,
2997 and for personality data. We must fall back on using writable
2998 .eh_frame sections for shared libraries if the linker does not
2999 support this feature. */
3000 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3001 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3002
3003 /* For switching between MIPS16 and non-MIPS16 modes. */
3004 #define SWITCHABLE_TARGET 1
3005
3006 /* Several named MIPS patterns depend on Pmode. These patterns have the
3007 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3008 Add the appropriate suffix to generator function NAME and invoke it
3009 with arguments ARGS. */
3010 #define PMODE_INSN(NAME, ARGS) \
3011 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)