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mips.h (ASM_SPEC): Pass float options to assembler.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS32R3 (mips_isa == 34)
212 #define ISA_MIPS32R5 (mips_isa == 36)
213 #define ISA_MIPS64 (mips_isa == 64)
214 #define ISA_MIPS64R2 (mips_isa == 65)
215 #define ISA_MIPS64R3 (mips_isa == 66)
216 #define ISA_MIPS64R5 (mips_isa == 68)
217
218 /* Architecture target defines. */
219 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
220 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
221 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
222 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
223 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
224 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
225 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
226 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
227 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
228 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
229 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
230 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
231 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
232 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
233 || mips_arch == PROCESSOR_OCTEON2)
234 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
235 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
236 || mips_arch == PROCESSOR_SB1A)
237 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
238 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
239
240 /* Scheduling target defines. */
241 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
242 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
243 || mips_tune == PROCESSOR_24KF2_1 \
244 || mips_tune == PROCESSOR_24KF1_1)
245 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
246 || mips_tune == PROCESSOR_74KF2_1 \
247 || mips_tune == PROCESSOR_74KF1_1 \
248 || mips_tune == PROCESSOR_74KF3_2)
249 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
250 || mips_tune == PROCESSOR_LOONGSON_2F)
251 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
252 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
253 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
254 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
255 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
256 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
257 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
258 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
259 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
260 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
261 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
262 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
263 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
264 || mips_tune == PROCESSOR_OCTEON2)
265 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
266 || mips_tune == PROCESSOR_SB1A)
267 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
268
269 /* Whether vector modes and intrinsics for ST Microelectronics
270 Loongson-2E/2F processors should be enabled. In o32 pairs of
271 floating-point registers provide 64-bit values. */
272 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
273 && (TARGET_LOONGSON_2EF \
274 || TARGET_LOONGSON_3A))
275
276 /* True if the pre-reload scheduler should try to create chains of
277 multiply-add or multiply-subtract instructions. For example,
278 suppose we have:
279
280 t1 = a * b
281 t2 = t1 + c * d
282 t3 = e * f
283 t4 = t3 - g * h
284
285 t1 will have a higher priority than t2 and t3 will have a higher
286 priority than t4. However, before reload, there is no dependence
287 between t1 and t3, and they can often have similar priorities.
288 The scheduler will then tend to prefer:
289
290 t1 = a * b
291 t3 = e * f
292 t2 = t1 + c * d
293 t4 = t3 - g * h
294
295 which stops us from making full use of macc/madd-style instructions.
296 This sort of situation occurs frequently in Fourier transforms and
297 in unrolled loops.
298
299 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
300 queue so that chained multiply-add and multiply-subtract instructions
301 appear ahead of any other instruction that is likely to clobber lo.
302 In the example above, if t2 and t3 become ready at the same time,
303 the code ensures that t2 is scheduled first.
304
305 Multiply-accumulate instructions are a bigger win for some targets
306 than others, so this macro is defined on an opt-in basis. */
307 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
308 || TUNE_MIPS4120 \
309 || TUNE_MIPS4130 \
310 || TUNE_24K \
311 || TUNE_P5600)
312
313 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
314 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
315
316 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
317 directly accessible, while the command-line options select
318 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
319 in use. */
320 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
321 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
322
323 /* False if SC acts as a memory barrier with respect to itself,
324 otherwise a SYNC will be emitted after SC for atomic operations
325 that require ordering between the SC and following loads and
326 stores. It does not tell anything about ordering of loads and
327 stores prior to and following the SC, only about the SC itself and
328 those loads and stores follow it. */
329 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
330
331 /* Define preprocessor macros for the -march and -mtune options.
332 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
333 processor. If INFO's canonical name is "foo", define PREFIX to
334 be "foo", and define an additional macro PREFIX_FOO. */
335 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
336 do \
337 { \
338 char *macro, *p; \
339 \
340 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
341 for (p = macro; *p != 0; p++) \
342 if (*p == '+') \
343 *p = 'P'; \
344 else \
345 *p = TOUPPER (*p); \
346 \
347 builtin_define (macro); \
348 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
349 free (macro); \
350 } \
351 while (0)
352
353 /* Target CPU builtins. */
354 #define TARGET_CPU_CPP_BUILTINS() \
355 do \
356 { \
357 builtin_assert ("machine=mips"); \
358 builtin_assert ("cpu=mips"); \
359 builtin_define ("__mips__"); \
360 builtin_define ("_mips"); \
361 \
362 /* We do this here because __mips is defined below and so we \
363 can't use builtin_define_std. We don't ever want to define \
364 "mips" for VxWorks because some of the VxWorks headers \
365 construct include filenames from a root directory macro, \
366 an architecture macro and a filename, where the architecture \
367 macro expands to 'mips'. If we define 'mips' to 1, the \
368 architecture macro expands to 1 as well. */ \
369 if (!flag_iso && !TARGET_VXWORKS) \
370 builtin_define ("mips"); \
371 \
372 if (TARGET_64BIT) \
373 builtin_define ("__mips64"); \
374 \
375 /* Treat _R3000 and _R4000 like register-size \
376 defines, which is how they've historically \
377 been used. */ \
378 if (TARGET_64BIT) \
379 { \
380 builtin_define_std ("R4000"); \
381 builtin_define ("_R4000"); \
382 } \
383 else \
384 { \
385 builtin_define_std ("R3000"); \
386 builtin_define ("_R3000"); \
387 } \
388 \
389 if (TARGET_FLOAT64) \
390 builtin_define ("__mips_fpr=64"); \
391 else \
392 builtin_define ("__mips_fpr=32"); \
393 \
394 if (mips_base_compression_flags & MASK_MIPS16) \
395 builtin_define ("__mips16"); \
396 \
397 if (TARGET_MIPS3D) \
398 builtin_define ("__mips3d"); \
399 \
400 if (TARGET_SMARTMIPS) \
401 builtin_define ("__mips_smartmips"); \
402 \
403 if (mips_base_compression_flags & MASK_MICROMIPS) \
404 builtin_define ("__mips_micromips"); \
405 \
406 if (TARGET_MCU) \
407 builtin_define ("__mips_mcu"); \
408 \
409 if (TARGET_EVA) \
410 builtin_define ("__mips_eva"); \
411 \
412 if (TARGET_DSP) \
413 { \
414 builtin_define ("__mips_dsp"); \
415 if (TARGET_DSPR2) \
416 { \
417 builtin_define ("__mips_dspr2"); \
418 builtin_define ("__mips_dsp_rev=2"); \
419 } \
420 else \
421 builtin_define ("__mips_dsp_rev=1"); \
422 } \
423 \
424 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
425 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
426 \
427 if (ISA_MIPS1) \
428 { \
429 builtin_define ("__mips=1"); \
430 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
431 } \
432 else if (ISA_MIPS2) \
433 { \
434 builtin_define ("__mips=2"); \
435 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
436 } \
437 else if (ISA_MIPS3) \
438 { \
439 builtin_define ("__mips=3"); \
440 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
441 } \
442 else if (ISA_MIPS4) \
443 { \
444 builtin_define ("__mips=4"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
446 } \
447 else if (ISA_MIPS32) \
448 { \
449 builtin_define ("__mips=32"); \
450 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
451 } \
452 else if (ISA_MIPS32R2) \
453 { \
454 builtin_define ("__mips=32"); \
455 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
456 } \
457 else if (ISA_MIPS32R3) \
458 { \
459 builtin_define ("__mips=32"); \
460 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
461 } \
462 else if (ISA_MIPS32R5) \
463 { \
464 builtin_define ("__mips=32"); \
465 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
466 } \
467 else if (ISA_MIPS64) \
468 { \
469 builtin_define ("__mips=64"); \
470 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
471 } \
472 else if (ISA_MIPS64R2) \
473 { \
474 builtin_define ("__mips=64"); \
475 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
476 } \
477 else if (ISA_MIPS64R3) \
478 { \
479 builtin_define ("__mips=64"); \
480 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
481 } \
482 else if (ISA_MIPS64R5) \
483 { \
484 builtin_define ("__mips=64"); \
485 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
486 } \
487 if (mips_isa_rev > 0) \
488 builtin_define_with_int_value ("__mips_isa_rev", \
489 mips_isa_rev); \
490 \
491 switch (mips_abi) \
492 { \
493 case ABI_32: \
494 builtin_define ("_ABIO32=1"); \
495 builtin_define ("_MIPS_SIM=_ABIO32"); \
496 break; \
497 \
498 case ABI_N32: \
499 builtin_define ("_ABIN32=2"); \
500 builtin_define ("_MIPS_SIM=_ABIN32"); \
501 break; \
502 \
503 case ABI_64: \
504 builtin_define ("_ABI64=3"); \
505 builtin_define ("_MIPS_SIM=_ABI64"); \
506 break; \
507 \
508 case ABI_O64: \
509 builtin_define ("_ABIO64=4"); \
510 builtin_define ("_MIPS_SIM=_ABIO64"); \
511 break; \
512 } \
513 \
514 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
515 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
516 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
517 builtin_define_with_int_value ("_MIPS_FPSET", \
518 32 / MAX_FPRS_PER_FMT); \
519 \
520 /* These defines reflect the ABI in use, not whether the \
521 FPU is directly accessible. */ \
522 if (TARGET_NO_FLOAT) \
523 builtin_define ("__mips_no_float"); \
524 else if (TARGET_HARD_FLOAT_ABI) \
525 builtin_define ("__mips_hard_float"); \
526 else \
527 builtin_define ("__mips_soft_float"); \
528 \
529 if (TARGET_SINGLE_FLOAT) \
530 builtin_define ("__mips_single_float"); \
531 \
532 if (TARGET_PAIRED_SINGLE_FLOAT) \
533 builtin_define ("__mips_paired_single_float"); \
534 \
535 if (mips_abs == MIPS_IEEE_754_2008) \
536 builtin_define ("__mips_abs2008"); \
537 \
538 if (mips_nan == MIPS_IEEE_754_2008) \
539 builtin_define ("__mips_nan2008"); \
540 \
541 if (TARGET_BIG_ENDIAN) \
542 { \
543 builtin_define_std ("MIPSEB"); \
544 builtin_define ("_MIPSEB"); \
545 } \
546 else \
547 { \
548 builtin_define_std ("MIPSEL"); \
549 builtin_define ("_MIPSEL"); \
550 } \
551 \
552 /* Whether calls should go through $25. The separate __PIC__ \
553 macro indicates whether abicalls code might use a GOT. */ \
554 if (TARGET_ABICALLS) \
555 builtin_define ("__mips_abicalls"); \
556 \
557 /* Whether Loongson vector modes are enabled. */ \
558 if (TARGET_LOONGSON_VECTORS) \
559 builtin_define ("__mips_loongson_vector_rev"); \
560 \
561 /* Historical Octeon macro. */ \
562 if (TARGET_OCTEON) \
563 builtin_define ("__OCTEON__"); \
564 \
565 if (TARGET_SYNCI) \
566 builtin_define ("__mips_synci"); \
567 \
568 /* Macros dependent on the C dialect. */ \
569 if (preprocessing_asm_p ()) \
570 { \
571 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
572 builtin_define ("_LANGUAGE_ASSEMBLY"); \
573 } \
574 else if (c_dialect_cxx ()) \
575 { \
576 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
577 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
578 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
579 } \
580 else \
581 { \
582 builtin_define_std ("LANGUAGE_C"); \
583 builtin_define ("_LANGUAGE_C"); \
584 } \
585 if (c_dialect_objc ()) \
586 { \
587 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
588 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
589 /* Bizarre, but retained for backwards compatibility. */ \
590 builtin_define_std ("LANGUAGE_C"); \
591 builtin_define ("_LANGUAGE_C"); \
592 } \
593 \
594 if (mips_abi == ABI_EABI) \
595 builtin_define ("__mips_eabi"); \
596 \
597 if (TARGET_CACHE_BUILTIN) \
598 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
599 } \
600 while (0)
601
602 /* Default target_flags if no switches are specified */
603
604 #ifndef TARGET_DEFAULT
605 #define TARGET_DEFAULT 0
606 #endif
607
608 #ifndef TARGET_CPU_DEFAULT
609 #define TARGET_CPU_DEFAULT 0
610 #endif
611
612 #ifndef TARGET_ENDIAN_DEFAULT
613 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
614 #endif
615
616 #ifdef IN_LIBGCC2
617 #undef TARGET_64BIT
618 /* Make this compile time constant for libgcc2 */
619 #ifdef __mips64
620 #define TARGET_64BIT 1
621 #else
622 #define TARGET_64BIT 0
623 #endif
624 #endif /* IN_LIBGCC2 */
625
626 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
627 when compiled with hardware floating point. This is because MIPS16
628 code cannot save and restore the floating-point registers, which is
629 important if in a mixed MIPS16/non-MIPS16 environment. */
630
631 #ifdef IN_LIBGCC2
632 #if __mips_hard_float
633 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
634 #endif
635 #endif /* IN_LIBGCC2 */
636
637 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
638
639 #ifndef MULTILIB_ENDIAN_DEFAULT
640 #if TARGET_ENDIAN_DEFAULT == 0
641 #define MULTILIB_ENDIAN_DEFAULT "EL"
642 #else
643 #define MULTILIB_ENDIAN_DEFAULT "EB"
644 #endif
645 #endif
646
647 #ifndef MULTILIB_ISA_DEFAULT
648 #if MIPS_ISA_DEFAULT == 1
649 #define MULTILIB_ISA_DEFAULT "mips1"
650 #elif MIPS_ISA_DEFAULT == 2
651 #define MULTILIB_ISA_DEFAULT "mips2"
652 #elif MIPS_ISA_DEFAULT == 3
653 #define MULTILIB_ISA_DEFAULT "mips3"
654 #elif MIPS_ISA_DEFAULT == 4
655 #define MULTILIB_ISA_DEFAULT "mips4"
656 #elif MIPS_ISA_DEFAULT == 32
657 #define MULTILIB_ISA_DEFAULT "mips32"
658 #elif MIPS_ISA_DEFAULT == 33
659 #define MULTILIB_ISA_DEFAULT "mips32r2"
660 #elif MIPS_ISA_DEFAULT == 64
661 #define MULTILIB_ISA_DEFAULT "mips64"
662 #elif MIPS_ISA_DEFAULT == 65
663 #define MULTILIB_ISA_DEFAULT "mips64r2"
664 #else
665 #define MULTILIB_ISA_DEFAULT "mips1"
666 #endif
667 #endif
668
669 #ifndef MIPS_ABI_DEFAULT
670 #define MIPS_ABI_DEFAULT ABI_32
671 #endif
672
673 /* Use the most portable ABI flag for the ASM specs. */
674
675 #if MIPS_ABI_DEFAULT == ABI_32
676 #define MULTILIB_ABI_DEFAULT "mabi=32"
677 #elif MIPS_ABI_DEFAULT == ABI_O64
678 #define MULTILIB_ABI_DEFAULT "mabi=o64"
679 #elif MIPS_ABI_DEFAULT == ABI_N32
680 #define MULTILIB_ABI_DEFAULT "mabi=n32"
681 #elif MIPS_ABI_DEFAULT == ABI_64
682 #define MULTILIB_ABI_DEFAULT "mabi=64"
683 #elif MIPS_ABI_DEFAULT == ABI_EABI
684 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
685 #endif
686
687 #ifndef MULTILIB_DEFAULTS
688 #define MULTILIB_DEFAULTS \
689 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
690 #endif
691
692 /* We must pass -EL to the linker by default for little endian embedded
693 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
694 linker will default to using big-endian output files. The OUTPUT_FORMAT
695 line must be in the linker script, otherwise -EB/-EL will not work. */
696
697 #ifndef ENDIAN_SPEC
698 #if TARGET_ENDIAN_DEFAULT == 0
699 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
700 #else
701 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
702 #endif
703 #endif
704
705 /* A spec condition that matches all non-mips16 -mips arguments. */
706
707 #define MIPS_ISA_LEVEL_OPTION_SPEC \
708 "mips1|mips2|mips3|mips4|mips32*|mips64*"
709
710 /* A spec condition that matches all non-mips16 architecture arguments. */
711
712 #define MIPS_ARCH_OPTION_SPEC \
713 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
714
715 /* A spec that infers a -mips argument from an -march argument,
716 or injects the default if no architecture is specified. */
717
718 #define MIPS_ISA_LEVEL_SPEC \
719 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
720 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
721 %{march=mips2|march=r6000:-mips2} \
722 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
723 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
724 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
725 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
726 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
727 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
728 %{march=mips32r3: -mips32r3} \
729 %{march=mips32r5|march=p5600: -mips32r5} \
730 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
731 |march=xlr: -mips64} \
732 %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
733 %{march=mips64r3: -mips64r3} \
734 %{march=mips64r5: -mips64r5} \
735 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
736
737 /* A spec that infers a -mhard-float or -msoft-float setting from an
738 -march argument. Note that soft-float and hard-float code are not
739 link-compatible. */
740
741 #define MIPS_ARCH_FLOAT_SPEC \
742 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
743 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
744 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
745 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
746 march=*: -mhard-float}"
747
748 /* A spec condition that matches 32-bit options. It only works if
749 MIPS_ISA_LEVEL_SPEC has been applied. */
750
751 #define MIPS_32BIT_OPTION_SPEC \
752 "mips1|mips2|mips32*|mgp32"
753
754 /* Infer a -msynci setting from a -mips argument, on the assumption that
755 -msynci is desired where possible. */
756 #define MIPS_ISA_SYNCI_SPEC \
757 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips64r2|mips64r3 \
758 |mips64r5:-msynci;:-mno-synci}}"
759
760 #if (MIPS_ABI_DEFAULT == ABI_O64 \
761 || MIPS_ABI_DEFAULT == ABI_N32 \
762 || MIPS_ABI_DEFAULT == ABI_64)
763 #define OPT_ARCH64 "mabi=32|mgp32:;"
764 #define OPT_ARCH32 "mabi=32|mgp32"
765 #else
766 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
767 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
768 #endif
769
770 /* Support for a compile-time default CPU, et cetera. The rules are:
771 --with-arch is ignored if -march is specified or a -mips is specified
772 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
773 --with-tune is ignored if -mtune is specified; likewise
774 --with-tune-32 and --with-tune-64.
775 --with-abi is ignored if -mabi is specified.
776 --with-float is ignored if -mhard-float or -msoft-float are
777 specified.
778 --with-nan is ignored if -mnan is specified.
779 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
780 specified. */
781 #define OPTION_DEFAULT_SPECS \
782 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
783 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
784 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
785 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
786 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
787 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
788 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
789 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
790 {"fpu", "%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}" }, \
791 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
792 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
793 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
794 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
795 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
796
797 /* A spec that infers the -mdsp setting from an -march argument. */
798 #define BASE_DRIVER_SELF_SPECS \
799 "%{!mno-dsp: \
800 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
801 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
802
803 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
804
805 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
806 && ISA_HAS_COND_TRAP)
807
808 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
809
810 /* True if the ABI can only work with 64-bit integer registers. We
811 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
812 otherwise floating-point registers must also be 64-bit. */
813 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
814
815 /* Likewise for 32-bit regs. */
816 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
817
818 /* True if the file format uses 64-bit symbols. At present, this is
819 only true for n64, which uses 64-bit ELF. */
820 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
821
822 /* True if symbols are 64 bits wide. This is usually determined by
823 the ABI's file format, but it can be overridden by -msym32. Note that
824 overriding the size with -msym32 changes the ABI of relocatable objects,
825 although it doesn't change the ABI of a fully-linked object. */
826 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
827 && Pmode == DImode \
828 && !TARGET_SYM32)
829
830 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
831 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
832 || ISA_MIPS4 \
833 || ISA_MIPS64 \
834 || ISA_MIPS64R2 \
835 || ISA_MIPS64R3 \
836 || ISA_MIPS64R5)
837
838 /* ISA has branch likely instructions (e.g. mips2). */
839 /* Disable branchlikely for tx39 until compare rewrite. They haven't
840 been generated up to this point. */
841 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
842
843 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
844 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
845 || TARGET_MIPS5400 \
846 || TARGET_MIPS5500 \
847 || TARGET_MIPS5900 \
848 || TARGET_MIPS7000 \
849 || TARGET_MIPS9000 \
850 || TARGET_MAD \
851 || mips_isa_rev >= 1) \
852 && !TARGET_MIPS16)
853
854 /* ISA has a three-operand multiplication instruction. */
855 #define ISA_HAS_DMUL3 (TARGET_64BIT \
856 && TARGET_OCTEON \
857 && !TARGET_MIPS16)
858
859 /* ISA supports instructions DMULT and DMULTU. */
860 #define ISA_HAS_DMULT (TARGET_64BIT && !TARGET_MIPS5900)
861
862 /* ISA supports instructions MULT and MULTU.
863 This is always true, but the macro is needed for ISA_HAS_<D>MULT
864 in mips.md. */
865 #define ISA_HAS_MULT (1)
866
867 /* ISA supports instructions DDIV and DDIVU. */
868 #define ISA_HAS_DDIV (TARGET_64BIT && !TARGET_MIPS5900)
869
870 /* ISA supports instructions DIV and DIVU.
871 This is always true, but the macro is needed for ISA_HAS_<D>DIV
872 in mips.md. */
873 #define ISA_HAS_DIV (1)
874
875 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
876 || TARGET_LOONGSON_3A) \
877 && !TARGET_MIPS16)
878
879 /* ISA has the floating-point conditional move instructions introduced
880 in mips4. */
881 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
882 || mips_isa_rev >= 1) \
883 && !TARGET_MIPS5500 \
884 && !TARGET_MIPS16)
885
886 /* ISA has the integer conditional move instructions introduced in mips4 and
887 ST Loongson 2E/2F. */
888 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
889 || TARGET_MIPS5900 \
890 || TARGET_LOONGSON_2EF)
891
892 /* ISA has LDC1 and SDC1. */
893 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
894 && !TARGET_MIPS5900 \
895 && !TARGET_MIPS16)
896
897 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
898 branch on CC, and move (both FP and non-FP) on CC. */
899 #define ISA_HAS_8CC (ISA_MIPS4 || mips_isa_rev >= 1)
900
901 /* This is a catch all for other mips4 instructions: indexed load, the
902 FP madd and msub instructions, and the FP recip and recip sqrt
903 instructions. Note that this macro should only be used by other
904 ISA_HAS_* macros. */
905 #define ISA_HAS_FP4 ((ISA_MIPS4 \
906 || ISA_MIPS64 \
907 || mips_isa_rev >= 2) \
908 && !TARGET_MIPS16)
909
910 /* ISA has floating-point indexed load and store instructions
911 (LWXC1, LDXC1, SWXC1 and SDXC1). */
912 #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
913
914 /* ISA has paired-single instructions. */
915 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS64 || mips_isa_rev >= 2)
916
917 /* ISA has conditional trap instructions. */
918 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
919 && !TARGET_MIPS16)
920
921 /* ISA has integer multiply-accumulate instructions, madd and msub. */
922 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1)
923
924 /* Integer multiply-accumulate instructions should be generated. */
925 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
926
927 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
928 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
929
930 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
931 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
932
933 /* ISA has floating-point nmadd and nmsub instructions
934 'd = -((a * b) [+-] c)'. */
935 #define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4
936
937 /* ISA has floating-point nmadd and nmsub instructions
938 'c = -((a * b) [+-] c)'. */
939 #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF
940
941 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
942 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
943 doubles are stored in pairs of FPRs, so for safety's sake, we apply
944 this restriction to the MIPS IV ISA too. */
945 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
946 (((ISA_HAS_FP4 \
947 && ((MODE) == SFmode \
948 || ((TARGET_FLOAT64 \
949 || mips_isa_rev >= 2) \
950 && (MODE) == DFmode))) \
951 || (TARGET_SB1 \
952 && (MODE) == V2SFmode)) \
953 && !TARGET_MIPS16)
954
955 /* ISA has count leading zeroes/ones instruction (not implemented). */
956 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
957
958 /* ISA has three operand multiply instructions that put
959 the high part in an accumulator: mulhi or mulhiu. */
960 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
961 || TARGET_MIPS5500 \
962 || TARGET_SR71K) \
963 && !TARGET_MIPS16)
964
965 /* ISA has three operand multiply instructions that negate the
966 result and put the result in an accumulator. */
967 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
968 || TARGET_MIPS5500 \
969 || TARGET_SR71K) \
970 && !TARGET_MIPS16)
971
972 /* ISA has three operand multiply instructions that subtract the
973 result from a 4th operand and put the result in an accumulator. */
974 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
975 || TARGET_MIPS5500 \
976 || TARGET_SR71K) \
977 && !TARGET_MIPS16)
978
979 /* ISA has three operand multiply instructions that add the result
980 to a 4th operand and put the result in an accumulator. */
981 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
982 || TARGET_MIPS4130 \
983 || TARGET_MIPS5400 \
984 || TARGET_MIPS5500 \
985 || TARGET_SR71K) \
986 && !TARGET_MIPS16)
987
988 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
989 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
990 || TARGET_MIPS4130) \
991 && !TARGET_MIPS16)
992
993 /* ISA has the "ror" (rotate right) instructions. */
994 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
995 || TARGET_MIPS5400 \
996 || TARGET_MIPS5500 \
997 || TARGET_SR71K \
998 || TARGET_SMARTMIPS) \
999 && !TARGET_MIPS16)
1000
1001 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1002 64-bit targets also provide DSBH and DSHD. */
1003 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1004
1005 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1006 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1007 || TARGET_LOONGSON_2EF \
1008 || TARGET_MIPS5900 \
1009 || mips_isa_rev >= 1) \
1010 && !TARGET_MIPS16)
1011
1012 /* ISA has data indexed prefetch instructions. This controls use of
1013 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1014 (prefx is a cop1x instruction, so can only be used if FP is
1015 enabled.) */
1016 #define ISA_HAS_PREFETCHX ISA_HAS_FP4
1017
1018 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1019 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1020 also requires TARGET_DOUBLE_FLOAT. */
1021 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1022
1023 /* ISA includes the MIPS32r2 seb and seh instructions. */
1024 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1025
1026 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1027 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1028
1029 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1030 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && mips_isa_rev >= 2)
1031
1032 /* ISA has lwxs instruction (load w/scaled index address. */
1033 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1034 && !TARGET_MIPS16)
1035
1036 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1037 #define ISA_HAS_LBX (TARGET_OCTEON2)
1038 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1039 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1040 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1041 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1042 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1043 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1044 && TARGET_64BIT)
1045
1046 /* The DSP ASE is available. */
1047 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1048
1049 /* Revision 2 of the DSP ASE is available. */
1050 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1051
1052 /* True if the result of a load is not available to the next instruction.
1053 A nop will then be needed between instructions like "lw $4,..."
1054 and "addiu $4,$4,1". */
1055 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1056 && !TARGET_MIPS3900 \
1057 && !TARGET_MIPS5900 \
1058 && !TARGET_MIPS16 \
1059 && !TARGET_MICROMIPS)
1060
1061 /* Likewise mtc1 and mfc1. */
1062 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1063 && !TARGET_MIPS5900 \
1064 && !TARGET_LOONGSON_2EF)
1065
1066 /* Likewise floating-point comparisons. */
1067 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1068 && !TARGET_MIPS5900 \
1069 && !TARGET_LOONGSON_2EF)
1070
1071 /* True if mflo and mfhi can be immediately followed by instructions
1072 which write to the HI and LO registers.
1073
1074 According to MIPS specifications, MIPS ISAs I, II, and III need
1075 (at least) two instructions between the reads of HI/LO and
1076 instructions which write them, and later ISAs do not. Contradicting
1077 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1078 the UM for the NEC Vr5000) document needing the instructions between
1079 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1080 MIPS64 and later ISAs to have the interlocks, plus any specific
1081 earlier-ISA CPUs for which CPU documentation declares that the
1082 instructions are really interlocked. */
1083 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1084 || TARGET_MIPS5500 \
1085 || TARGET_MIPS5900 \
1086 || TARGET_LOONGSON_2EF)
1087
1088 /* ISA includes synci, jr.hb and jalr.hb. */
1089 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1090
1091 /* ISA includes sync. */
1092 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1093 #define GENERATE_SYNC \
1094 (target_flags_explicit & MASK_LLSC \
1095 ? TARGET_LLSC && !TARGET_MIPS16 \
1096 : ISA_HAS_SYNC)
1097
1098 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1099 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1100 instructions. */
1101 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1102 #define GENERATE_LL_SC \
1103 (target_flags_explicit & MASK_LLSC \
1104 ? TARGET_LLSC && !TARGET_MIPS16 \
1105 : ISA_HAS_LL_SC)
1106
1107 #define ISA_HAS_SWAP (TARGET_XLP)
1108 #define ISA_HAS_LDADD (TARGET_XLP)
1109
1110 /* ISA includes the baddu instruction. */
1111 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1112
1113 /* ISA includes the bbit* instructions. */
1114 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1115
1116 /* ISA includes the cins instruction. */
1117 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1118
1119 /* ISA includes the exts instruction. */
1120 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1121
1122 /* ISA includes the seq and sne instructions. */
1123 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1124
1125 /* ISA includes the pop instruction. */
1126 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1127
1128 /* The CACHE instruction is available in non-MIPS16 code. */
1129 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1130
1131 /* The CACHE instruction is available. */
1132 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1133 \f
1134 /* Tell collect what flags to pass to nm. */
1135 #ifndef NM_FLAGS
1136 #define NM_FLAGS "-Bn"
1137 #endif
1138
1139 \f
1140 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1141 the assembler. It may be overridden by subtargets.
1142
1143 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1144 COFF debugging info. */
1145
1146 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1147 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1148 %{g} %{g0} %{g1} %{g2} %{g3} \
1149 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1150 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1151 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1152 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1153 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1154 #endif
1155
1156 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1157 overridden by subtargets. */
1158
1159 #ifndef SUBTARGET_ASM_SPEC
1160 #define SUBTARGET_ASM_SPEC ""
1161 #endif
1162
1163 #undef ASM_SPEC
1164 #define ASM_SPEC "\
1165 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1166 %{mips32*} %{mips64*} \
1167 %{mips16} %{mno-mips16:-no-mips16} \
1168 %{mmicromips} %{mno-micromips} \
1169 %{mips3d} %{mno-mips3d:-no-mips3d} \
1170 %{mdmx} %{mno-mdmx:-no-mdmx} \
1171 %{mdsp} %{mno-dsp} \
1172 %{mdspr2} %{mno-dspr2} \
1173 %{mmcu} %{mno-mcu} \
1174 %{meva} %{mno-eva} \
1175 %{mvirt} %{mno-virt} \
1176 %{mxpa} %{mno-xpa} \
1177 %{msmartmips} %{mno-smartmips} \
1178 %{mmt} %{mno-mt} \
1179 %{mfix-rm7000} %{mno-fix-rm7000} \
1180 %{mfix-vr4120} %{mfix-vr4130} \
1181 %{mfix-24k} \
1182 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1183 %(subtarget_asm_debugging_spec) \
1184 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1185 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1186 %{mfp32} %{mfp64} %{mnan=*} \
1187 %{mshared} %{mno-shared} \
1188 %{msym32} %{mno-sym32} \
1189 %{mtune=*} \
1190 %{mhard-float} %{msoft-float} \
1191 %{msingle-float} %{mdouble-float} \
1192 %(subtarget_asm_spec)"
1193
1194 /* Extra switches sometimes passed to the linker. */
1195
1196 #ifndef LINK_SPEC
1197 #define LINK_SPEC "\
1198 %(endian_spec) \
1199 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1200 %{shared}"
1201 #endif /* LINK_SPEC defined */
1202
1203
1204 /* Specs for the compiler proper */
1205
1206 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1207 overridden by subtargets. */
1208 #ifndef SUBTARGET_CC1_SPEC
1209 #define SUBTARGET_CC1_SPEC ""
1210 #endif
1211
1212 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1213
1214 #undef CC1_SPEC
1215 #define CC1_SPEC "\
1216 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1217 %(subtarget_cc1_spec)"
1218
1219 /* Preprocessor specs. */
1220
1221 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1222 overridden by subtargets. */
1223 #ifndef SUBTARGET_CPP_SPEC
1224 #define SUBTARGET_CPP_SPEC ""
1225 #endif
1226
1227 #define CPP_SPEC "%(subtarget_cpp_spec)"
1228
1229 /* This macro defines names of additional specifications to put in the specs
1230 that can be used in various specifications like CC1_SPEC. Its definition
1231 is an initializer with a subgrouping for each command option.
1232
1233 Each subgrouping contains a string constant, that defines the
1234 specification name, and a string constant that used by the GCC driver
1235 program.
1236
1237 Do not define this macro if it does not need to do anything. */
1238
1239 #define EXTRA_SPECS \
1240 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1241 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1242 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1243 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1244 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1245 { "endian_spec", ENDIAN_SPEC }, \
1246 SUBTARGET_EXTRA_SPECS
1247
1248 #ifndef SUBTARGET_EXTRA_SPECS
1249 #define SUBTARGET_EXTRA_SPECS
1250 #endif
1251 \f
1252 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1253 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1254
1255 #ifndef PREFERRED_DEBUGGING_TYPE
1256 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1257 #endif
1258
1259 /* The size of DWARF addresses should be the same as the size of symbols
1260 in the target file format. They shouldn't depend on things like -msym32,
1261 because many DWARF consumers do not allow the mixture of address sizes
1262 that one would then get from linking -msym32 code with -msym64 code.
1263
1264 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1265 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1266 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1267
1268 /* By default, turn on GDB extensions. */
1269 #define DEFAULT_GDB_EXTENSIONS 1
1270
1271 /* Registers may have a prefix which can be ignored when matching
1272 user asm and register definitions. */
1273 #ifndef REGISTER_PREFIX
1274 #define REGISTER_PREFIX "$"
1275 #endif
1276
1277 /* Local compiler-generated symbols must have a prefix that the assembler
1278 understands. By default, this is $, although some targets (e.g.,
1279 NetBSD-ELF) need to override this. */
1280
1281 #ifndef LOCAL_LABEL_PREFIX
1282 #define LOCAL_LABEL_PREFIX "$"
1283 #endif
1284
1285 /* By default on the mips, external symbols do not have an underscore
1286 prepended, but some targets (e.g., NetBSD) require this. */
1287
1288 #ifndef USER_LABEL_PREFIX
1289 #define USER_LABEL_PREFIX ""
1290 #endif
1291
1292 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1293 since the length can run past this up to a continuation point. */
1294 #undef DBX_CONTIN_LENGTH
1295 #define DBX_CONTIN_LENGTH 1500
1296
1297 /* How to renumber registers for dbx and gdb. */
1298 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1299
1300 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1301 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1302
1303 /* The DWARF 2 CFA column which tracks the return address. */
1304 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1305
1306 /* Before the prologue, RA lives in r31. */
1307 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1308
1309 /* Describe how we implement __builtin_eh_return. */
1310 #define EH_RETURN_DATA_REGNO(N) \
1311 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1312
1313 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1314
1315 #define EH_USES(N) mips_eh_uses (N)
1316
1317 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1318 The default for this in 64-bit mode is 8, which causes problems with
1319 SFmode register saves. */
1320 #define DWARF_CIE_DATA_ALIGNMENT -4
1321
1322 /* Correct the offset of automatic variables and arguments. Note that
1323 the MIPS debug format wants all automatic variables and arguments
1324 to be in terms of the virtual frame pointer (stack pointer before
1325 any adjustment in the function), while the MIPS 3.0 linker wants
1326 the frame pointer to be the stack pointer after the initial
1327 adjustment. */
1328
1329 #define DEBUGGER_AUTO_OFFSET(X) \
1330 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1331 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1332 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1333 \f
1334 /* Target machine storage layout */
1335
1336 #define BITS_BIG_ENDIAN 0
1337 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1338 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1339
1340 #define MAX_BITS_PER_WORD 64
1341
1342 /* Width of a word, in units (bytes). */
1343 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1344 #ifndef IN_LIBGCC2
1345 #define MIN_UNITS_PER_WORD 4
1346 #endif
1347
1348 /* For MIPS, width of a floating point register. */
1349 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1350
1351 /* The number of consecutive floating-point registers needed to store the
1352 largest format supported by the FPU. */
1353 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1354
1355 /* The number of consecutive floating-point registers needed to store the
1356 smallest format supported by the FPU. */
1357 #define MIN_FPRS_PER_FMT \
1358 (mips_isa_rev >= 1 ? 1 : MAX_FPRS_PER_FMT)
1359
1360 /* The largest size of value that can be held in floating-point
1361 registers and moved with a single instruction. */
1362 #define UNITS_PER_HWFPVALUE \
1363 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1364
1365 /* The largest size of value that can be held in floating-point
1366 registers. */
1367 #define UNITS_PER_FPVALUE \
1368 (TARGET_SOFT_FLOAT_ABI ? 0 \
1369 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1370 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1371
1372 /* The number of bytes in a double. */
1373 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1374
1375 /* Set the sizes of the core types. */
1376 #define SHORT_TYPE_SIZE 16
1377 #define INT_TYPE_SIZE 32
1378 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1379 #define LONG_LONG_TYPE_SIZE 64
1380
1381 #define FLOAT_TYPE_SIZE 32
1382 #define DOUBLE_TYPE_SIZE 64
1383 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1384
1385 /* Define the sizes of fixed-point types. */
1386 #define SHORT_FRACT_TYPE_SIZE 8
1387 #define FRACT_TYPE_SIZE 16
1388 #define LONG_FRACT_TYPE_SIZE 32
1389 #define LONG_LONG_FRACT_TYPE_SIZE 64
1390
1391 #define SHORT_ACCUM_TYPE_SIZE 16
1392 #define ACCUM_TYPE_SIZE 32
1393 #define LONG_ACCUM_TYPE_SIZE 64
1394 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1395 doesn't support 128-bit integers for MIPS32 currently. */
1396 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1397
1398 /* long double is not a fixed mode, but the idea is that, if we
1399 support long double, we also want a 128-bit integer type. */
1400 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1401
1402 #ifdef IN_LIBGCC2
1403 #if ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1404 || (defined _ABI64 && _MIPS_SIM == _ABI64))
1405 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1406 # else
1407 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1408 # endif
1409 #endif
1410
1411 /* Width in bits of a pointer. */
1412 #ifndef POINTER_SIZE
1413 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1414 #endif
1415
1416 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1417 #define PARM_BOUNDARY BITS_PER_WORD
1418
1419 /* Allocation boundary (in *bits*) for the code of a function. */
1420 #define FUNCTION_BOUNDARY 32
1421
1422 /* Alignment of field after `int : 0' in a structure. */
1423 #define EMPTY_FIELD_BOUNDARY 32
1424
1425 /* Every structure's size must be a multiple of this. */
1426 /* 8 is observed right on a DECstation and on riscos 4.02. */
1427 #define STRUCTURE_SIZE_BOUNDARY 8
1428
1429 /* There is no point aligning anything to a rounder boundary than this. */
1430 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1431
1432 /* All accesses must be aligned. */
1433 #define STRICT_ALIGNMENT 1
1434
1435 /* Define this if you wish to imitate the way many other C compilers
1436 handle alignment of bitfields and the structures that contain
1437 them.
1438
1439 The behavior is that the type written for a bit-field (`int',
1440 `short', or other integer type) imposes an alignment for the
1441 entire structure, as if the structure really did contain an
1442 ordinary field of that type. In addition, the bit-field is placed
1443 within the structure so that it would fit within such a field,
1444 not crossing a boundary for it.
1445
1446 Thus, on most machines, a bit-field whose type is written as `int'
1447 would not cross a four-byte boundary, and would force four-byte
1448 alignment for the whole structure. (The alignment used may not
1449 be four bytes; it is controlled by the other alignment
1450 parameters.)
1451
1452 If the macro is defined, its definition should be a C expression;
1453 a nonzero value for the expression enables this behavior. */
1454
1455 #define PCC_BITFIELD_TYPE_MATTERS 1
1456
1457 /* If defined, a C expression to compute the alignment given to a
1458 constant that is being placed in memory. CONSTANT is the constant
1459 and ALIGN is the alignment that the object would ordinarily have.
1460 The value of this macro is used instead of that alignment to align
1461 the object.
1462
1463 If this macro is not defined, then ALIGN is used.
1464
1465 The typical use of this macro is to increase alignment for string
1466 constants to be word aligned so that `strcpy' calls that copy
1467 constants can be done inline. */
1468
1469 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1470 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1471 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1472
1473 /* If defined, a C expression to compute the alignment for a static
1474 variable. TYPE is the data type, and ALIGN is the alignment that
1475 the object would ordinarily have. The value of this macro is used
1476 instead of that alignment to align the object.
1477
1478 If this macro is not defined, then ALIGN is used.
1479
1480 One use of this macro is to increase alignment of medium-size
1481 data to make it all fit in fewer cache lines. Another is to
1482 cause character arrays to be word-aligned so that `strcpy' calls
1483 that copy constants to character arrays can be done inline. */
1484
1485 #undef DATA_ALIGNMENT
1486 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1487 ((((ALIGN) < BITS_PER_WORD) \
1488 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1489 || TREE_CODE (TYPE) == UNION_TYPE \
1490 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1491
1492 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1493 character arrays to be word-aligned so that `strcpy' calls that copy
1494 constants to character arrays can be done inline, and 'strcmp' can be
1495 optimised to use word loads. */
1496 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1497 DATA_ALIGNMENT (TYPE, ALIGN)
1498
1499 #define PAD_VARARGS_DOWN \
1500 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1501
1502 /* Define if operations between registers always perform the operation
1503 on the full register even if a narrower mode is specified. */
1504 #define WORD_REGISTER_OPERATIONS
1505
1506 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1507 moves. All other references are zero extended. */
1508 #define LOAD_EXTEND_OP(MODE) \
1509 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1510 ? SIGN_EXTEND : ZERO_EXTEND)
1511
1512 /* Define this macro if it is advisable to hold scalars in registers
1513 in a wider mode than that declared by the program. In such cases,
1514 the value is constrained to be within the bounds of the declared
1515 type, but kept valid in the wider mode. The signedness of the
1516 extension may differ from that of the type. */
1517
1518 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1519 if (GET_MODE_CLASS (MODE) == MODE_INT \
1520 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1521 { \
1522 if ((MODE) == SImode) \
1523 (UNSIGNEDP) = 0; \
1524 (MODE) = Pmode; \
1525 }
1526
1527 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1528 Extensions of pointers to word_mode must be signed. */
1529 #define POINTERS_EXTEND_UNSIGNED false
1530
1531 /* Define if loading short immediate values into registers sign extends. */
1532 #define SHORT_IMMEDIATES_SIGN_EXTEND
1533
1534 /* The [d]clz instructions have the natural values at 0. */
1535
1536 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1537 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1538 \f
1539 /* Standard register usage. */
1540
1541 /* Number of hardware registers. We have:
1542
1543 - 32 integer registers
1544 - 32 floating point registers
1545 - 8 condition code registers
1546 - 2 accumulator registers (hi and lo)
1547 - 32 registers each for coprocessors 0, 2 and 3
1548 - 4 fake registers:
1549 - ARG_POINTER_REGNUM
1550 - FRAME_POINTER_REGNUM
1551 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1552 - CPRESTORE_SLOT_REGNUM
1553 - 2 dummy entries that were used at various times in the past.
1554 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1555 - 6 DSP control registers */
1556
1557 #define FIRST_PSEUDO_REGISTER 188
1558
1559 /* By default, fix the kernel registers ($26 and $27), the global
1560 pointer ($28) and the stack pointer ($29). This can change
1561 depending on the command-line options.
1562
1563 Regarding coprocessor registers: without evidence to the contrary,
1564 it's best to assume that each coprocessor register has a unique
1565 use. This can be overridden, in, e.g., mips_option_override or
1566 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1567 inappropriate for a particular target. */
1568
1569 #define FIXED_REGISTERS \
1570 { \
1571 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1572 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1573 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1574 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1575 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1576 /* COP0 registers */ \
1577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1578 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1579 /* COP2 registers */ \
1580 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1581 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1582 /* COP3 registers */ \
1583 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1584 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1585 /* 6 DSP accumulator registers & 6 control registers */ \
1586 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1587 }
1588
1589
1590 /* Set up this array for o32 by default.
1591
1592 Note that we don't mark $31 as a call-clobbered register. The idea is
1593 that it's really the call instructions themselves which clobber $31.
1594 We don't care what the called function does with it afterwards.
1595
1596 This approach makes it easier to implement sibcalls. Unlike normal
1597 calls, sibcalls don't clobber $31, so the register reaches the
1598 called function in tact. EPILOGUE_USES says that $31 is useful
1599 to the called function. */
1600
1601 #define CALL_USED_REGISTERS \
1602 { \
1603 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1604 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1605 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1606 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1607 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1608 /* COP0 registers */ \
1609 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1610 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1611 /* COP2 registers */ \
1612 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1613 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1614 /* COP3 registers */ \
1615 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1616 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1617 /* 6 DSP accumulator registers & 6 control registers */ \
1618 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1619 }
1620
1621
1622 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1623
1624 #define CALL_REALLY_USED_REGISTERS \
1625 { /* General registers. */ \
1626 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1627 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1628 /* Floating-point registers. */ \
1629 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1630 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1631 /* Others. */ \
1632 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1633 /* COP0 registers */ \
1634 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1635 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1636 /* COP2 registers */ \
1637 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1638 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1639 /* COP3 registers */ \
1640 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1641 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1642 /* 6 DSP accumulator registers & 6 control registers */ \
1643 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1644 }
1645
1646 /* Internal macros to classify a register number as to whether it's a
1647 general purpose register, a floating point register, a
1648 multiply/divide register, or a status register. */
1649
1650 #define GP_REG_FIRST 0
1651 #define GP_REG_LAST 31
1652 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1653 #define GP_DBX_FIRST 0
1654 #define K0_REG_NUM (GP_REG_FIRST + 26)
1655 #define K1_REG_NUM (GP_REG_FIRST + 27)
1656 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1657
1658 #define FP_REG_FIRST 32
1659 #define FP_REG_LAST 63
1660 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1661 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1662
1663 #define MD_REG_FIRST 64
1664 #define MD_REG_LAST 65
1665 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1666 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1667
1668 /* The DWARF 2 CFA column which tracks the return address from a
1669 signal handler context. This means that to maintain backwards
1670 compatibility, no hard register can be assigned this column if it
1671 would need to be handled by the DWARF unwinder. */
1672 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1673
1674 #define ST_REG_FIRST 67
1675 #define ST_REG_LAST 74
1676 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1677
1678
1679 /* FIXME: renumber. */
1680 #define COP0_REG_FIRST 80
1681 #define COP0_REG_LAST 111
1682 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1683
1684 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1685 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1686 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1687
1688 #define COP2_REG_FIRST 112
1689 #define COP2_REG_LAST 143
1690 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1691
1692 #define COP3_REG_FIRST 144
1693 #define COP3_REG_LAST 175
1694 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1695
1696 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1697 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1698 #define ALL_COP_REG_LAST COP3_REG_LAST
1699 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1700
1701 #define DSP_ACC_REG_FIRST 176
1702 #define DSP_ACC_REG_LAST 181
1703 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1704
1705 #define AT_REGNUM (GP_REG_FIRST + 1)
1706 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1707 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1708
1709 /* A few bitfield locations for the coprocessor registers. */
1710 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1711 the cause register for the EIC interrupt mode. */
1712 #define CAUSE_IPL 10
1713 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1714 #define SR_IPL 10
1715 /* Exception Level is at bit 1 of the status register. */
1716 #define SR_EXL 1
1717 /* Interrupt Enable is at bit 0 of the status register. */
1718 #define SR_IE 0
1719
1720 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1721 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1722 should be used instead. */
1723 #define FPSW_REGNUM ST_REG_FIRST
1724
1725 #define GP_REG_P(REGNO) \
1726 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1727 #define M16_REG_P(REGNO) \
1728 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1729 #define M16STORE_REG_P(REGNO) \
1730 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1731 #define FP_REG_P(REGNO) \
1732 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1733 #define MD_REG_P(REGNO) \
1734 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1735 #define ST_REG_P(REGNO) \
1736 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1737 #define COP0_REG_P(REGNO) \
1738 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1739 #define COP2_REG_P(REGNO) \
1740 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1741 #define COP3_REG_P(REGNO) \
1742 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1743 #define ALL_COP_REG_P(REGNO) \
1744 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1745 /* Test if REGNO is one of the 6 new DSP accumulators. */
1746 #define DSP_ACC_REG_P(REGNO) \
1747 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1748 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1749 #define ACC_REG_P(REGNO) \
1750 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1751
1752 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1753
1754 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1755 to initialize the mips16 gp pseudo register. */
1756 #define CONST_GP_P(X) \
1757 (GET_CODE (X) == CONST \
1758 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1759 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1760
1761 /* Return coprocessor number from register number. */
1762
1763 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1764 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1765 : COP3_REG_P (REGNO) ? '3' : '?')
1766
1767
1768 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1769
1770 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1771 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1772
1773 #define MODES_TIEABLE_P mips_modes_tieable_p
1774
1775 /* Register to use for pushing function arguments. */
1776 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1777
1778 /* These two registers don't really exist: they get eliminated to either
1779 the stack or hard frame pointer. */
1780 #define ARG_POINTER_REGNUM 77
1781 #define FRAME_POINTER_REGNUM 78
1782
1783 /* $30 is not available on the mips16, so we use $17 as the frame
1784 pointer. */
1785 #define HARD_FRAME_POINTER_REGNUM \
1786 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1787
1788 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1789 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1790
1791 /* Register in which static-chain is passed to a function. */
1792 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1793
1794 /* Registers used as temporaries in prologue/epilogue code:
1795
1796 - If a MIPS16 PIC function needs access to _gp, it first loads
1797 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1798
1799 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1800 register. The register must not conflict with MIPS16_PIC_TEMP.
1801
1802 - If we aren't generating MIPS16 code, the prologue can also use
1803 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1804
1805 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1806 register.
1807
1808 If we're generating MIPS16 code, these registers must come from the
1809 core set of 8. The prologue registers mustn't conflict with any
1810 incoming arguments, the static chain pointer, or the frame pointer.
1811 The epilogue temporary mustn't conflict with the return registers,
1812 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1813 or the EH data registers.
1814
1815 If we're generating interrupt handlers, we use K0 as a temporary register
1816 in prologue/epilogue code. */
1817
1818 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1819 #define MIPS_PROLOGUE_TEMP_REGNUM \
1820 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1821 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1822 (TARGET_MIPS16 \
1823 ? (gcc_unreachable (), INVALID_REGNUM) \
1824 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1825 #define MIPS_EPILOGUE_TEMP_REGNUM \
1826 (cfun->machine->interrupt_handler_p \
1827 ? K0_REG_NUM \
1828 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1829
1830 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1831 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1832 #define MIPS_PROLOGUE_TEMP2(MODE) \
1833 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1834 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1835
1836 /* Define this macro if it is as good or better to call a constant
1837 function address than to call an address kept in a register. */
1838 #define NO_FUNCTION_CSE 1
1839
1840 /* The ABI-defined global pointer. Sometimes we use a different
1841 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1842 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1843
1844 /* We normally use $28 as the global pointer. However, when generating
1845 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1846 register instead. They can then avoid saving and restoring $28
1847 and perhaps avoid using a frame at all.
1848
1849 When a leaf function uses something other than $28, mips_expand_prologue
1850 will modify pic_offset_table_rtx in place. Take the register number
1851 from there after reload. */
1852 #define PIC_OFFSET_TABLE_REGNUM \
1853 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1854 \f
1855 /* Define the classes of registers for register constraints in the
1856 machine description. Also define ranges of constants.
1857
1858 One of the classes must always be named ALL_REGS and include all hard regs.
1859 If there is more than one class, another class must be named NO_REGS
1860 and contain no registers.
1861
1862 The name GENERAL_REGS must be the name of a class (or an alias for
1863 another name such as ALL_REGS). This is the class of registers
1864 that is allowed by "g" or "r" in a register constraint.
1865 Also, registers outside this class are allocated only when
1866 instructions express preferences for them.
1867
1868 The classes must be numbered in nondecreasing order; that is,
1869 a larger-numbered class must never be contained completely
1870 in a smaller-numbered class.
1871
1872 For any two classes, it is very desirable that there be another
1873 class that represents their union. */
1874
1875 enum reg_class
1876 {
1877 NO_REGS, /* no registers in set */
1878 M16_STORE_REGS, /* microMIPS store registers */
1879 M16_REGS, /* mips16 directly accessible registers */
1880 M16_SP_REGS, /* mips16 + $sp */
1881 T_REG, /* mips16 T register ($24) */
1882 M16_T_REGS, /* mips16 registers plus T register */
1883 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1884 V1_REG, /* Register $v1 ($3) used for TLS access. */
1885 SPILL_REGS, /* All but $sp and call preserved regs are in here */
1886 LEA_REGS, /* Every GPR except $25 */
1887 GR_REGS, /* integer registers */
1888 FP_REGS, /* floating point registers */
1889 MD0_REG, /* first multiply/divide register */
1890 MD1_REG, /* second multiply/divide register */
1891 MD_REGS, /* multiply/divide registers (hi/lo) */
1892 COP0_REGS, /* generic coprocessor classes */
1893 COP2_REGS,
1894 COP3_REGS,
1895 ST_REGS, /* status registers (fp status) */
1896 DSP_ACC_REGS, /* DSP accumulator registers */
1897 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1898 FRAME_REGS, /* $arg and $frame */
1899 GR_AND_MD0_REGS, /* union classes */
1900 GR_AND_MD1_REGS,
1901 GR_AND_MD_REGS,
1902 GR_AND_ACC_REGS,
1903 ALL_REGS, /* all registers */
1904 LIM_REG_CLASSES /* max value + 1 */
1905 };
1906
1907 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1908
1909 #define GENERAL_REGS GR_REGS
1910
1911 /* An initializer containing the names of the register classes as C
1912 string constants. These names are used in writing some of the
1913 debugging dumps. */
1914
1915 #define REG_CLASS_NAMES \
1916 { \
1917 "NO_REGS", \
1918 "M16_STORE_REGS", \
1919 "M16_REGS", \
1920 "M16_SP_REGS", \
1921 "T_REG", \
1922 "M16_T_REGS", \
1923 "PIC_FN_ADDR_REG", \
1924 "V1_REG", \
1925 "SPILL_REGS", \
1926 "LEA_REGS", \
1927 "GR_REGS", \
1928 "FP_REGS", \
1929 "MD0_REG", \
1930 "MD1_REG", \
1931 "MD_REGS", \
1932 /* coprocessor registers */ \
1933 "COP0_REGS", \
1934 "COP2_REGS", \
1935 "COP3_REGS", \
1936 "ST_REGS", \
1937 "DSP_ACC_REGS", \
1938 "ACC_REGS", \
1939 "FRAME_REGS", \
1940 "GR_AND_MD0_REGS", \
1941 "GR_AND_MD1_REGS", \
1942 "GR_AND_MD_REGS", \
1943 "GR_AND_ACC_REGS", \
1944 "ALL_REGS" \
1945 }
1946
1947 /* An initializer containing the contents of the register classes,
1948 as integers which are bit masks. The Nth integer specifies the
1949 contents of class N. The way the integer MASK is interpreted is
1950 that register R is in the class if `MASK & (1 << R)' is 1.
1951
1952 When the machine has more than 32 registers, an integer does not
1953 suffice. Then the integers are replaced by sub-initializers,
1954 braced groupings containing several integers. Each
1955 sub-initializer must be suitable as an initializer for the type
1956 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1957
1958 #define REG_CLASS_CONTENTS \
1959 { \
1960 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1961 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
1962 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1963 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
1964 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1965 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1966 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1967 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1968 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
1969 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1970 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1971 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1972 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1973 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1974 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1975 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1976 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1977 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1978 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1979 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1980 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1981 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1982 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1983 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1984 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1985 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1986 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1987 }
1988
1989
1990 /* A C expression whose value is a register class containing hard
1991 register REGNO. In general there is more that one such class;
1992 choose a class which is "minimal", meaning that no smaller class
1993 also contains the register. */
1994
1995 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1996
1997 /* A macro whose definition is the name of the class to which a
1998 valid base register must belong. A base register is one used in
1999 an address which is the register value plus a displacement. */
2000
2001 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
2002
2003 /* A macro whose definition is the name of the class to which a
2004 valid index register must belong. An index register is one used
2005 in an address where its value is either multiplied by a scale
2006 factor or added to another register (as well as added to a
2007 displacement). */
2008
2009 #define INDEX_REG_CLASS NO_REGS
2010
2011 /* We generally want to put call-clobbered registers ahead of
2012 call-saved ones. (IRA expects this.) */
2013
2014 #define REG_ALLOC_ORDER \
2015 { /* Accumulator registers. When GPRs and accumulators have equal \
2016 cost, we generally prefer to use accumulators. For example, \
2017 a division of multiplication result is better allocated to LO, \
2018 so that we put the MFLO at the point of use instead of at the \
2019 point of definition. It's also needed if we're to take advantage \
2020 of the extra accumulators available with -mdspr2. In some cases, \
2021 it can also help to reduce register pressure. */ \
2022 64, 65,176,177,178,179,180,181, \
2023 /* Call-clobbered GPRs. */ \
2024 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2025 24, 25, 31, \
2026 /* The global pointer. This is call-clobbered for o32 and o64 \
2027 abicalls, call-saved for n32 and n64 abicalls, and a program \
2028 invariant otherwise. Putting it between the call-clobbered \
2029 and call-saved registers should cope with all eventualities. */ \
2030 28, \
2031 /* Call-saved GPRs. */ \
2032 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2033 /* GPRs that can never be exposed to the register allocator. */ \
2034 0, 26, 27, 29, \
2035 /* Call-clobbered FPRs. */ \
2036 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2037 48, 49, 50, 51, \
2038 /* FPRs that are usually call-saved. The odd ones are actually \
2039 call-clobbered for n32, but listing them ahead of the even \
2040 registers might encourage the register allocator to fragment \
2041 the available FPR pairs. We need paired FPRs to store long \
2042 doubles, so it isn't clear that using a different order \
2043 for n32 would be a win. */ \
2044 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2045 /* None of the remaining classes have defined call-saved \
2046 registers. */ \
2047 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2048 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2049 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2050 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2051 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2052 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2053 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2054 182,183,184,185,186,187 \
2055 }
2056
2057 /* True if VALUE is an unsigned 6-bit number. */
2058
2059 #define UIMM6_OPERAND(VALUE) \
2060 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2061
2062 /* True if VALUE is a signed 10-bit number. */
2063
2064 #define IMM10_OPERAND(VALUE) \
2065 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2066
2067 /* True if VALUE is a signed 16-bit number. */
2068
2069 #define SMALL_OPERAND(VALUE) \
2070 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2071
2072 /* True if VALUE is an unsigned 16-bit number. */
2073
2074 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2075 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2076
2077 /* True if VALUE can be loaded into a register using LUI. */
2078
2079 #define LUI_OPERAND(VALUE) \
2080 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2081 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2082
2083 /* Return a value X with the low 16 bits clear, and such that
2084 VALUE - X is a signed 16-bit value. */
2085
2086 #define CONST_HIGH_PART(VALUE) \
2087 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2088
2089 #define CONST_LOW_PART(VALUE) \
2090 ((VALUE) - CONST_HIGH_PART (VALUE))
2091
2092 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2093 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2094 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2095 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2096
2097 /* The HI and LO registers can only be reloaded via the general
2098 registers. Condition code registers can only be loaded to the
2099 general registers, and from the floating point registers. */
2100
2101 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2102 mips_secondary_reload_class (CLASS, MODE, X, true)
2103 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2104 mips_secondary_reload_class (CLASS, MODE, X, false)
2105
2106 /* Return the maximum number of consecutive registers
2107 needed to represent mode MODE in a register of class CLASS. */
2108
2109 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2110
2111 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2112 mips_cannot_change_mode_class (FROM, TO, CLASS)
2113 \f
2114 /* Stack layout; function entry, exit and calling. */
2115
2116 #define STACK_GROWS_DOWNWARD
2117
2118 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2119
2120 /* Size of the area allocated in the frame to save the GP. */
2121
2122 #define MIPS_GP_SAVE_AREA_SIZE \
2123 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2124
2125 /* The offset of the first local variable from the frame pointer. See
2126 mips_compute_frame_info for details about the frame layout. */
2127
2128 #define STARTING_FRAME_OFFSET \
2129 (FRAME_GROWS_DOWNWARD \
2130 ? 0 \
2131 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2132
2133 #define RETURN_ADDR_RTX mips_return_addr
2134
2135 /* Mask off the MIPS16 ISA bit in unwind addresses.
2136
2137 The reason for this is a little subtle. When unwinding a call,
2138 we are given the call's return address, which on most targets
2139 is the address of the following instruction. However, what we
2140 actually want to find is the EH region for the call itself.
2141 The target-independent unwind code therefore searches for "RA - 1".
2142
2143 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2144 RA - 1 is therefore the real (even-valued) start of the return
2145 instruction. EH region labels are usually odd-valued MIPS16 symbols
2146 too, so a search for an even address within a MIPS16 region would
2147 usually work.
2148
2149 However, there is an exception. If the end of an EH region is also
2150 the end of a function, the end label is allowed to be even. This is
2151 necessary because a following non-MIPS16 function may also need EH
2152 information for its first instruction.
2153
2154 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2155 non-ISA-encoded address. This probably isn't ideal, but it is
2156 the traditional (legacy) behavior. It is therefore only safe
2157 to search MIPS EH regions for an _odd-valued_ address.
2158
2159 Masking off the ISA bit means that the target-independent code
2160 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2161 #define MASK_RETURN_ADDR GEN_INT (-2)
2162
2163
2164 /* Similarly, don't use the least-significant bit to tell pointers to
2165 code from vtable index. */
2166
2167 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2168
2169 /* The eliminations to $17 are only used for mips16 code. See the
2170 definition of HARD_FRAME_POINTER_REGNUM. */
2171
2172 #define ELIMINABLE_REGS \
2173 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2174 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2175 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2176 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2177 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2178 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2179
2180 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2181 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2182
2183 /* Allocate stack space for arguments at the beginning of each function. */
2184 #define ACCUMULATE_OUTGOING_ARGS 1
2185
2186 /* The argument pointer always points to the first argument. */
2187 #define FIRST_PARM_OFFSET(FNDECL) 0
2188
2189 /* o32 and o64 reserve stack space for all argument registers. */
2190 #define REG_PARM_STACK_SPACE(FNDECL) \
2191 (TARGET_OLDABI \
2192 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2193 : 0)
2194
2195 /* Define this if it is the responsibility of the caller to
2196 allocate the area reserved for arguments passed in registers.
2197 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2198 of this macro is to determine whether the space is included in
2199 `crtl->outgoing_args_size'. */
2200 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2201
2202 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2203 \f
2204 /* Symbolic macros for the registers used to return integer and floating
2205 point values. */
2206
2207 #define GP_RETURN (GP_REG_FIRST + 2)
2208 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2209
2210 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2211
2212 /* Symbolic macros for the first/last argument registers. */
2213
2214 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2215 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2216 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2217 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2218
2219 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2220 are used for returning complex double values in soft-float code, so $6 is the
2221 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2222 $gp itself as the temporary. */
2223 #define POST_CALL_TMP_REG \
2224 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2225
2226 /* 1 if N is a possible register number for function argument passing.
2227 We have no FP argument registers when soft-float. When FP registers
2228 are 32 bits, we can't directly reference the odd numbered ones. */
2229
2230 #define FUNCTION_ARG_REGNO_P(N) \
2231 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2232 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2233 && !fixed_regs[N])
2234 \f
2235 /* This structure has to cope with two different argument allocation
2236 schemes. Most MIPS ABIs view the arguments as a structure, of which
2237 the first N words go in registers and the rest go on the stack. If I
2238 < N, the Ith word might go in Ith integer argument register or in a
2239 floating-point register. For these ABIs, we only need to remember
2240 the offset of the current argument into the structure.
2241
2242 The EABI instead allocates the integer and floating-point arguments
2243 separately. The first N words of FP arguments go in FP registers,
2244 the rest go on the stack. Likewise, the first N words of the other
2245 arguments go in integer registers, and the rest go on the stack. We
2246 need to maintain three counts: the number of integer registers used,
2247 the number of floating-point registers used, and the number of words
2248 passed on the stack.
2249
2250 We could keep separate information for the two ABIs (a word count for
2251 the standard ABIs, and three separate counts for the EABI). But it
2252 seems simpler to view the standard ABIs as forms of EABI that do not
2253 allocate floating-point registers.
2254
2255 So for the standard ABIs, the first N words are allocated to integer
2256 registers, and mips_function_arg decides on an argument-by-argument
2257 basis whether that argument should really go in an integer register,
2258 or in a floating-point one. */
2259
2260 typedef struct mips_args {
2261 /* Always true for varargs functions. Otherwise true if at least
2262 one argument has been passed in an integer register. */
2263 int gp_reg_found;
2264
2265 /* The number of arguments seen so far. */
2266 unsigned int arg_number;
2267
2268 /* The number of integer registers used so far. For all ABIs except
2269 EABI, this is the number of words that have been added to the
2270 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2271 unsigned int num_gprs;
2272
2273 /* For EABI, the number of floating-point registers used so far. */
2274 unsigned int num_fprs;
2275
2276 /* The number of words passed on the stack. */
2277 unsigned int stack_words;
2278
2279 /* On the mips16, we need to keep track of which floating point
2280 arguments were passed in general registers, but would have been
2281 passed in the FP regs if this were a 32-bit function, so that we
2282 can move them to the FP regs if we wind up calling a 32-bit
2283 function. We record this information in fp_code, encoded in base
2284 four. A zero digit means no floating point argument, a one digit
2285 means an SFmode argument, and a two digit means a DFmode argument,
2286 and a three digit is not used. The low order digit is the first
2287 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2288 an SFmode argument. ??? A more sophisticated approach will be
2289 needed if MIPS_ABI != ABI_32. */
2290 int fp_code;
2291
2292 /* True if the function has a prototype. */
2293 int prototype;
2294 } CUMULATIVE_ARGS;
2295
2296 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2297 for a call to a function whose data type is FNTYPE.
2298 For a library call, FNTYPE is 0. */
2299
2300 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2301 mips_init_cumulative_args (&CUM, FNTYPE)
2302
2303 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2304 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2305
2306 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2307 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2308
2309 /* True if using EABI and varargs can be passed in floating-point
2310 registers. Under these conditions, we need a more complex form
2311 of va_list, which tracks GPR, FPR and stack arguments separately. */
2312 #define EABI_FLOAT_VARARGS_P \
2313 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2314
2315 \f
2316 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2317
2318 /* Treat LOC as a byte offset from the stack pointer and round it up
2319 to the next fully-aligned offset. */
2320 #define MIPS_STACK_ALIGN(LOC) \
2321 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2322
2323 \f
2324 /* Output assembler code to FILE to increment profiler label # LABELNO
2325 for profiling a function entry. */
2326
2327 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2328
2329 /* The profiler preserves all interesting registers, including $31. */
2330 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2331
2332 /* No mips port has ever used the profiler counter word, so don't emit it
2333 or the label for it. */
2334
2335 #define NO_PROFILE_COUNTERS 1
2336
2337 /* Define this macro if the code for function profiling should come
2338 before the function prologue. Normally, the profiling code comes
2339 after. */
2340
2341 /* #define PROFILE_BEFORE_PROLOGUE */
2342
2343 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2344 the stack pointer does not matter. The value is tested only in
2345 functions that have frame pointers.
2346 No definition is equivalent to always zero. */
2347
2348 #define EXIT_IGNORE_STACK 1
2349
2350 \f
2351 /* Trampolines are a block of code followed by two pointers. */
2352
2353 #define TRAMPOLINE_SIZE \
2354 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2355
2356 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2357 pointers from a single LUI base. */
2358
2359 #define TRAMPOLINE_ALIGNMENT 64
2360
2361 /* mips_trampoline_init calls this library function to flush
2362 program and data caches. */
2363
2364 #ifndef CACHE_FLUSH_FUNC
2365 #define CACHE_FLUSH_FUNC "_flush_cache"
2366 #endif
2367
2368 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2369 /* Flush both caches. We need to flush the data cache in case \
2370 the system has a write-back cache. */ \
2371 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2372 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2373 GEN_INT (3), TYPE_MODE (integer_type_node))
2374
2375 \f
2376 /* Addressing modes, and classification of registers for them. */
2377
2378 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2379 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2380 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2381 \f
2382 /* Maximum number of registers that can appear in a valid memory address. */
2383
2384 #define MAX_REGS_PER_ADDRESS 1
2385
2386 /* Check for constness inline but use mips_legitimate_address_p
2387 to check whether a constant really is an address. */
2388
2389 #define CONSTANT_ADDRESS_P(X) \
2390 (CONSTANT_P (X) && memory_address_p (SImode, X))
2391
2392 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2393 'the start of the function that this code is output in'. */
2394
2395 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2396 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2397 asm_fprintf ((FILE), "%U%s", \
2398 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2399 else \
2400 asm_fprintf ((FILE), "%U%s", (NAME))
2401 \f
2402 /* Flag to mark a function decl symbol that requires a long call. */
2403 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2404 #define SYMBOL_REF_LONG_CALL_P(X) \
2405 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2406
2407 /* This flag marks functions that cannot be lazily bound. */
2408 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2409 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2410 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2411
2412 /* True if we're generating a form of MIPS16 code in which jump tables
2413 are stored in the text section and encoded as 16-bit PC-relative
2414 offsets. This is only possible when general text loads are allowed,
2415 since the table access itself will be an "lh" instruction. If the
2416 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2417 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2418
2419 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2420
2421 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2422
2423 /* Only use short offsets if their range will not overflow. */
2424 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2425 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2426 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2427 : SImode)
2428
2429 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2430
2431 /* Define this as 1 if `char' should by default be signed; else as 0. */
2432 #ifndef DEFAULT_SIGNED_CHAR
2433 #define DEFAULT_SIGNED_CHAR 1
2434 #endif
2435
2436 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2437 we generally don't want to use them for copying arbitrary data.
2438 A single N-word move is usually the same cost as N single-word moves. */
2439 #define MOVE_MAX UNITS_PER_WORD
2440 #define MAX_MOVE_MAX 8
2441
2442 /* Define this macro as a C expression which is nonzero if
2443 accessing less than a word of memory (i.e. a `char' or a
2444 `short') is no faster than accessing a word of memory, i.e., if
2445 such access require more than one instruction or if there is no
2446 difference in cost between byte and (aligned) word loads.
2447
2448 On RISC machines, it tends to generate better code to define
2449 this as 1, since it avoids making a QI or HI mode register.
2450
2451 But, generating word accesses for -mips16 is generally bad as shifts
2452 (often extended) would be needed for byte accesses. */
2453 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2454
2455 /* Standard MIPS integer shifts truncate the shift amount to the
2456 width of the shifted operand. However, Loongson vector shifts
2457 do not truncate the shift amount at all. */
2458 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2459
2460 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2461 is done just by pretending it is already truncated. */
2462 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2463 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2464
2465
2466 /* Specify the machine mode that pointers have.
2467 After generation of rtl, the compiler makes no further distinction
2468 between pointers and any other objects of this machine mode. */
2469
2470 #ifndef Pmode
2471 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2472 #endif
2473
2474 /* Give call MEMs SImode since it is the "most permissive" mode
2475 for both 32-bit and 64-bit targets. */
2476
2477 #define FUNCTION_MODE SImode
2478
2479 \f
2480 /* We allocate $fcc registers by hand and can't cope with moves of
2481 CCmode registers to and from pseudos (or memory). */
2482 #define AVOID_CCMODE_COPIES
2483
2484 /* A C expression for the cost of a branch instruction. A value of
2485 1 is the default; other values are interpreted relative to that. */
2486
2487 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2488 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2489
2490 /* The MIPS port has several functions that return an instruction count.
2491 Multiplying the count by this value gives the number of bytes that
2492 the instructions occupy. */
2493 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2494
2495 /* The length of a NOP in bytes. */
2496 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2497
2498 /* If defined, modifies the length assigned to instruction INSN as a
2499 function of the context in which it is used. LENGTH is an lvalue
2500 that contains the initially computed length of the insn and should
2501 be updated with the correct length of the insn. */
2502 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2503 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2504
2505 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2506 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2507 its operands. */
2508 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2509 "%*" OPCODE "%?\t" OPERANDS "%/"
2510
2511 /* Return an asm string that forces INSN to be treated as an absolute
2512 J or JAL instruction instead of an assembler macro. */
2513 #define MIPS_ABSOLUTE_JUMP(INSN) \
2514 (TARGET_ABICALLS_PIC2 \
2515 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2516 : INSN)
2517
2518 /* Return the asm template for a call. INSN is the instruction's mnemonic
2519 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2520 number of the target. SIZE_OPNO is the operand number of the argument size
2521 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2522 -1 and the call is indirect, use the function symbol from the call
2523 attributes to attach a R_MIPS_JALR relocation to the call.
2524
2525 When generating GOT code without explicit relocation operators,
2526 all calls should use assembly macros. Otherwise, all indirect
2527 calls should use "jr" or "jalr"; we will arrange to restore $gp
2528 afterwards if necessary. Finally, we can only generate direct
2529 calls for -mabicalls by temporarily switching to non-PIC mode.
2530
2531 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2532 instruction is in the delay slot of jal(r). */
2533 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2534 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2535 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2536 : REG_P (OPERANDS[TARGET_OPNO]) \
2537 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2538 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2539 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2540 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2541 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2542 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2543 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2544 ? MIPS_ABSOLUTE_JUMP ("%*" INSN "%!\t%" #TARGET_OPNO "%/") \
2545 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/")) \
2546
2547 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2548 "jrc" when nop is in the delay slot of "jr". */
2549
2550 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2551 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2552 ? "%*j\t%" #OPNO "%/" \
2553 : REG_P (OPERANDS[OPNO]) \
2554 ? "%*jr%:\t%" #OPNO \
2555 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2556
2557 \f
2558 /* Control the assembler format that we output. */
2559
2560 /* Output to assembler file text saying following lines
2561 may contain character constants, extra white space, comments, etc. */
2562
2563 #ifndef ASM_APP_ON
2564 #define ASM_APP_ON " #APP\n"
2565 #endif
2566
2567 /* Output to assembler file text saying following lines
2568 no longer contain unusual constructs. */
2569
2570 #ifndef ASM_APP_OFF
2571 #define ASM_APP_OFF " #NO_APP\n"
2572 #endif
2573
2574 #define REGISTER_NAMES \
2575 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2576 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2577 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2578 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2579 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2580 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2581 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2582 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2583 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2584 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2585 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2586 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2587 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2588 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2589 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2590 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2591 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2592 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2593 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2594 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2595 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2596 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2597 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2598 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2599
2600 /* List the "software" names for each register. Also list the numerical
2601 names for $fp and $sp. */
2602
2603 #define ADDITIONAL_REGISTER_NAMES \
2604 { \
2605 { "$29", 29 + GP_REG_FIRST }, \
2606 { "$30", 30 + GP_REG_FIRST }, \
2607 { "at", 1 + GP_REG_FIRST }, \
2608 { "v0", 2 + GP_REG_FIRST }, \
2609 { "v1", 3 + GP_REG_FIRST }, \
2610 { "a0", 4 + GP_REG_FIRST }, \
2611 { "a1", 5 + GP_REG_FIRST }, \
2612 { "a2", 6 + GP_REG_FIRST }, \
2613 { "a3", 7 + GP_REG_FIRST }, \
2614 { "t0", 8 + GP_REG_FIRST }, \
2615 { "t1", 9 + GP_REG_FIRST }, \
2616 { "t2", 10 + GP_REG_FIRST }, \
2617 { "t3", 11 + GP_REG_FIRST }, \
2618 { "t4", 12 + GP_REG_FIRST }, \
2619 { "t5", 13 + GP_REG_FIRST }, \
2620 { "t6", 14 + GP_REG_FIRST }, \
2621 { "t7", 15 + GP_REG_FIRST }, \
2622 { "s0", 16 + GP_REG_FIRST }, \
2623 { "s1", 17 + GP_REG_FIRST }, \
2624 { "s2", 18 + GP_REG_FIRST }, \
2625 { "s3", 19 + GP_REG_FIRST }, \
2626 { "s4", 20 + GP_REG_FIRST }, \
2627 { "s5", 21 + GP_REG_FIRST }, \
2628 { "s6", 22 + GP_REG_FIRST }, \
2629 { "s7", 23 + GP_REG_FIRST }, \
2630 { "t8", 24 + GP_REG_FIRST }, \
2631 { "t9", 25 + GP_REG_FIRST }, \
2632 { "k0", 26 + GP_REG_FIRST }, \
2633 { "k1", 27 + GP_REG_FIRST }, \
2634 { "gp", 28 + GP_REG_FIRST }, \
2635 { "sp", 29 + GP_REG_FIRST }, \
2636 { "fp", 30 + GP_REG_FIRST }, \
2637 { "ra", 31 + GP_REG_FIRST } \
2638 }
2639
2640 #define DBR_OUTPUT_SEQEND(STREAM) \
2641 do \
2642 { \
2643 /* Undo the effect of '%*'. */ \
2644 mips_pop_asm_switch (&mips_nomacro); \
2645 mips_pop_asm_switch (&mips_noreorder); \
2646 /* Emit a blank line after the delay slot for emphasis. */ \
2647 fputs ("\n", STREAM); \
2648 } \
2649 while (0)
2650
2651 /* The MIPS implementation uses some labels for its own purpose. The
2652 following lists what labels are created, and are all formed by the
2653 pattern $L[a-z].*. The machine independent portion of GCC creates
2654 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2655
2656 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2657 $Lb[0-9]+ Begin blocks for MIPS debug support
2658 $Lc[0-9]+ Label for use in s<xx> operation.
2659 $Le[0-9]+ End blocks for MIPS debug support */
2660
2661 #undef ASM_DECLARE_OBJECT_NAME
2662 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2663 mips_declare_object (STREAM, NAME, "", ":\n")
2664
2665 /* Globalizing directive for a label. */
2666 #define GLOBAL_ASM_OP "\t.globl\t"
2667
2668 /* This says how to define a global common symbol. */
2669
2670 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2671
2672 /* This says how to define a local common symbol (i.e., not visible to
2673 linker). */
2674
2675 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2676 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2677 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2678 #endif
2679
2680 /* This says how to output an external. It would be possible not to
2681 output anything and let undefined symbol become external. However
2682 the assembler uses length information on externals to allocate in
2683 data/sdata bss/sbss, thereby saving exec time. */
2684
2685 #undef ASM_OUTPUT_EXTERNAL
2686 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2687 mips_output_external(STREAM,DECL,NAME)
2688
2689 /* This is how to declare a function name. The actual work of
2690 emitting the label is moved to function_prologue, so that we can
2691 get the line number correctly emitted before the .ent directive,
2692 and after any .file directives. Define as empty so that the function
2693 is not declared before the .ent directive elsewhere. */
2694
2695 #undef ASM_DECLARE_FUNCTION_NAME
2696 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2697
2698 /* This is how to store into the string LABEL
2699 the symbol_ref name of an internal numbered label where
2700 PREFIX is the class of label and NUM is the number within the class.
2701 This is suitable for output with `assemble_name'. */
2702
2703 #undef ASM_GENERATE_INTERNAL_LABEL
2704 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2705 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2706
2707 /* Print debug labels as "foo = ." rather than "foo:" because they should
2708 represent a byte pointer rather than an ISA-encoded address. This is
2709 particularly important for code like:
2710
2711 $LFBxxx = .
2712 .cfi_startproc
2713 ...
2714 .section .gcc_except_table,...
2715 ...
2716 .uleb128 foo-$LFBxxx
2717
2718 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2719 likewise a byte pointer rather than an ISA-encoded address.
2720
2721 At the time of writing, this hook is not used for the function end
2722 label:
2723
2724 $LFExxx:
2725 .end foo
2726
2727 But this doesn't matter, because GAS doesn't treat a pre-.end label
2728 as a MIPS16 one anyway. */
2729
2730 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2731 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2732
2733 /* This is how to output an element of a case-vector that is absolute. */
2734
2735 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2736 fprintf (STREAM, "\t%s\t%sL%d\n", \
2737 ptr_mode == DImode ? ".dword" : ".word", \
2738 LOCAL_LABEL_PREFIX, \
2739 VALUE)
2740
2741 /* This is how to output an element of a case-vector. We can make the
2742 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2743 is supported. */
2744
2745 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2746 do { \
2747 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2748 { \
2749 if (GET_MODE (BODY) == HImode) \
2750 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2751 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2752 else \
2753 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2754 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2755 } \
2756 else if (TARGET_GPWORD) \
2757 fprintf (STREAM, "\t%s\t%sL%d\n", \
2758 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2759 LOCAL_LABEL_PREFIX, VALUE); \
2760 else if (TARGET_RTP_PIC) \
2761 { \
2762 /* Make the entry relative to the start of the function. */ \
2763 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2764 fprintf (STREAM, "\t%s\t%sL%d-", \
2765 Pmode == DImode ? ".dword" : ".word", \
2766 LOCAL_LABEL_PREFIX, VALUE); \
2767 assemble_name (STREAM, XSTR (fnsym, 0)); \
2768 fprintf (STREAM, "\n"); \
2769 } \
2770 else \
2771 fprintf (STREAM, "\t%s\t%sL%d\n", \
2772 ptr_mode == DImode ? ".dword" : ".word", \
2773 LOCAL_LABEL_PREFIX, VALUE); \
2774 } while (0)
2775
2776 /* This is how to output an assembler line
2777 that says to advance the location counter
2778 to a multiple of 2**LOG bytes. */
2779
2780 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2781 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2782
2783 /* This is how to output an assembler line to advance the location
2784 counter by SIZE bytes. */
2785
2786 #undef ASM_OUTPUT_SKIP
2787 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2788 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2789
2790 /* This is how to output a string. */
2791 #undef ASM_OUTPUT_ASCII
2792 #define ASM_OUTPUT_ASCII mips_output_ascii
2793
2794 \f
2795 /* Default to -G 8 */
2796 #ifndef MIPS_DEFAULT_GVALUE
2797 #define MIPS_DEFAULT_GVALUE 8
2798 #endif
2799
2800 /* Define the strings to put out for each section in the object file. */
2801 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2802 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2803
2804 #undef READONLY_DATA_SECTION_ASM_OP
2805 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2806 \f
2807 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2808 do \
2809 { \
2810 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2811 TARGET_64BIT ? "daddiu" : "addiu", \
2812 reg_names[STACK_POINTER_REGNUM], \
2813 reg_names[STACK_POINTER_REGNUM], \
2814 TARGET_64BIT ? "sd" : "sw", \
2815 reg_names[REGNO], \
2816 reg_names[STACK_POINTER_REGNUM]); \
2817 } \
2818 while (0)
2819
2820 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2821 do \
2822 { \
2823 mips_push_asm_switch (&mips_noreorder); \
2824 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2825 TARGET_64BIT ? "ld" : "lw", \
2826 reg_names[REGNO], \
2827 reg_names[STACK_POINTER_REGNUM], \
2828 TARGET_64BIT ? "daddu" : "addu", \
2829 reg_names[STACK_POINTER_REGNUM], \
2830 reg_names[STACK_POINTER_REGNUM]); \
2831 mips_pop_asm_switch (&mips_noreorder); \
2832 } \
2833 while (0)
2834
2835 /* How to start an assembler comment.
2836 The leading space is important (the mips native assembler requires it). */
2837 #ifndef ASM_COMMENT_START
2838 #define ASM_COMMENT_START " #"
2839 #endif
2840 \f
2841 #undef SIZE_TYPE
2842 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2843
2844 #undef PTRDIFF_TYPE
2845 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2846
2847 /* The maximum number of bytes that can be copied by one iteration of
2848 a movmemsi loop; see mips_block_move_loop. */
2849 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2850 (UNITS_PER_WORD * 4)
2851
2852 /* The maximum number of bytes that can be copied by a straight-line
2853 implementation of movmemsi; see mips_block_move_straight. We want
2854 to make sure that any loop-based implementation will iterate at
2855 least twice. */
2856 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2857 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2858
2859 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2860 values were determined experimentally by benchmarking with CSiBE.
2861 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2862 for o32 where we have to restore $gp afterwards as well as make an
2863 indirect call), but in practice, bumping this up higher for
2864 TARGET_ABICALLS doesn't make much difference to code size. */
2865
2866 #define MIPS_CALL_RATIO 8
2867
2868 /* Any loop-based implementation of movmemsi will have at least
2869 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2870 moves, so allow individual copies of fewer elements.
2871
2872 When movmemsi is not available, use a value approximating
2873 the length of a memcpy call sequence, so that move_by_pieces
2874 will generate inline code if it is shorter than a function call.
2875 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2876 we'll have to generate a load/store pair for each, halve the
2877 value of MIPS_CALL_RATIO to take that into account. */
2878
2879 #define MOVE_RATIO(speed) \
2880 (HAVE_movmemsi \
2881 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2882 : MIPS_CALL_RATIO / 2)
2883
2884 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2885 mips_move_by_pieces_p (SIZE, ALIGN)
2886
2887 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2888 of the length of a memset call, but use the default otherwise. */
2889
2890 #define CLEAR_RATIO(speed)\
2891 ((speed) ? 15 : MIPS_CALL_RATIO)
2892
2893 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2894 optimizing for size adjust the ratio to account for the overhead of
2895 loading the constant and replicating it across the word. */
2896
2897 #define SET_RATIO(speed) \
2898 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2899
2900 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2901 mips_store_by_pieces_p (SIZE, ALIGN)
2902 \f
2903 /* Since the bits of the _init and _fini function is spread across
2904 many object files, each potentially with its own GP, we must assume
2905 we need to load our GP. We don't preserve $gp or $ra, since each
2906 init/fini chunk is supposed to initialize $gp, and crti/crtn
2907 already take care of preserving $ra and, when appropriate, $gp. */
2908 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2909 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2910 asm (SECTION_OP "\n\
2911 .set push\n\
2912 .set nomips16\n\
2913 .set noreorder\n\
2914 bal 1f\n\
2915 nop\n\
2916 1: .cpload $31\n\
2917 .set reorder\n\
2918 jal " USER_LABEL_PREFIX #FUNC "\n\
2919 .set pop\n\
2920 " TEXT_SECTION_ASM_OP);
2921 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2922 || (defined _ABI64 && _MIPS_SIM == _ABI64))
2923 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2924 asm (SECTION_OP "\n\
2925 .set push\n\
2926 .set nomips16\n\
2927 .set noreorder\n\
2928 bal 1f\n\
2929 nop\n\
2930 1: .set reorder\n\
2931 .cpsetup $31, $2, 1b\n\
2932 jal " USER_LABEL_PREFIX #FUNC "\n\
2933 .set pop\n\
2934 " TEXT_SECTION_ASM_OP);
2935 #endif
2936
2937 #ifndef HAVE_AS_TLS
2938 #define HAVE_AS_TLS 0
2939 #endif
2940
2941 #ifndef HAVE_AS_NAN
2942 #define HAVE_AS_NAN 0
2943 #endif
2944
2945 #ifndef USED_FOR_TARGET
2946 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2947 struct mips_asm_switch {
2948 /* The FOO in the description above. */
2949 const char *name;
2950
2951 /* The current block nesting level, or 0 if we aren't in a block. */
2952 int nesting_level;
2953 };
2954
2955 extern const enum reg_class mips_regno_to_class[];
2956 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2957 extern const char *current_function_file; /* filename current function is in */
2958 extern int num_source_filenames; /* current .file # */
2959 extern struct mips_asm_switch mips_noreorder;
2960 extern struct mips_asm_switch mips_nomacro;
2961 extern struct mips_asm_switch mips_noat;
2962 extern int mips_dbx_regno[];
2963 extern int mips_dwarf_regno[];
2964 extern bool mips_split_p[];
2965 extern bool mips_split_hi_p[];
2966 extern bool mips_use_pcrel_pool_p[];
2967 extern const char *mips_lo_relocs[];
2968 extern const char *mips_hi_relocs[];
2969 extern enum processor mips_arch; /* which cpu to codegen for */
2970 extern enum processor mips_tune; /* which cpu to schedule for */
2971 extern int mips_isa; /* architectural level */
2972 extern int mips_isa_rev;
2973 extern const struct mips_cpu_info *mips_arch_info;
2974 extern const struct mips_cpu_info *mips_tune_info;
2975 extern unsigned int mips_base_compression_flags;
2976 extern GTY(()) struct target_globals *mips16_globals;
2977 #endif
2978
2979 /* Enable querying of DFA units. */
2980 #define CPU_UNITS_QUERY 1
2981
2982 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2983 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2984
2985 /* As on most targets, we want the .eh_frame section to be read-only where
2986 possible. And as on most targets, this means two things:
2987
2988 (a) Non-locally-binding pointers must have an indirect encoding,
2989 so that the addresses in the .eh_frame section itself become
2990 locally-binding.
2991
2992 (b) A shared library's .eh_frame section must encode locally-binding
2993 pointers in a relative (relocation-free) form.
2994
2995 However, MIPS has traditionally not allowed directives like:
2996
2997 .long x-.
2998
2999 in cases where "x" is in a different section, or is not defined in the
3000 same assembly file. We are therefore unable to emit the PC-relative
3001 form required by (b) at assembly time.
3002
3003 Fortunately, the linker is able to convert absolute addresses into
3004 PC-relative addresses on our behalf. Unfortunately, only certain
3005 versions of the linker know how to do this for indirect pointers,
3006 and for personality data. We must fall back on using writable
3007 .eh_frame sections for shared libraries if the linker does not
3008 support this feature. */
3009 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3010 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3011
3012 /* For switching between MIPS16 and non-MIPS16 modes. */
3013 #define SWITCHABLE_TARGET 1
3014
3015 /* Several named MIPS patterns depend on Pmode. These patterns have the
3016 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3017 Add the appropriate suffix to generator function NAME and invoke it
3018 with arguments ARGS. */
3019 #define PMODE_INSN(NAME, ARGS) \
3020 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)