projects / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
microblaze.h (CC1_SPEC): Remove -gline spec.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 #ifdef GENERATOR_FILE
30 /* This is used in some insn conditions, so needs to be declared, but
31 does not need to be defined. */
32 extern int target_flags_explicit;
33 #endif
34
35 /* MIPS external variables defined in mips.c. */
36
37 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
38 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
39 to work on a 64-bit machine. */
40
41 #define ABI_32 0
42 #define ABI_N32 1
43 #define ABI_64 2
44 #define ABI_EABI 3
45 #define ABI_O64 4
46
47 /* Masks that affect tuning.
48
49 PTF_AVOID_BRANCHLIKELY
50 Set if it is usually not profitable to use branch-likely instructions
51 for this target, typically because the branches are always predicted
52 taken and so incur a large overhead when not taken. */
53 #define PTF_AVOID_BRANCHLIKELY 0x1
54
55 /* Information about one recognized processor. Defined here for the
56 benefit of TARGET_CPU_CPP_BUILTINS. */
57 struct mips_cpu_info {
58 /* The 'canonical' name of the processor as far as GCC is concerned.
59 It's typically a manufacturer's prefix followed by a numerical
60 designation. It should be lowercase. */
61 const char *name;
62
63 /* The internal processor number that most closely matches this
64 entry. Several processors can have the same value, if there's no
65 difference between them from GCC's point of view. */
66 enum processor cpu;
67
68 /* The ISA level that the processor implements. */
69 int isa;
70
71 /* A mask of PTF_* values. */
72 unsigned int tune_flags;
73 };
74
75 /* Enumerates the setting of the -mcode-readable option. */
76 enum mips_code_readable_setting {
77 CODE_READABLE_NO,
78 CODE_READABLE_PCREL,
79 CODE_READABLE_YES
80 };
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables.
166
167 Although GAS does understand .gpdword, the SGI linker mishandles
168 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
169 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
170 #define TARGET_GPWORD \
171 (TARGET_ABICALLS \
172 && !TARGET_ABSOLUTE_ABICALLS \
173 && !(mips_abi == ABI_64 && TARGET_IRIX6))
174
175 /* True if the output must have a writable .eh_frame.
176 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
177 #ifdef HAVE_LD_PERSONALITY_RELAXATION
178 #define TARGET_WRITABLE_EH_FRAME 0
179 #else
180 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
181 #endif
182
183 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
184 #ifdef HAVE_AS_DSPR1_MULT
185 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
186 #else
187 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
188 #endif
189
190 /* Generate mips16 code */
191 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
192 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
193 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
194 /* Generate mips16e register save/restore sequences. */
195 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
196
197 /* True if we're generating a form of MIPS16 code in which general
198 text loads are allowed. */
199 #define TARGET_MIPS16_TEXT_LOADS \
200 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
201
202 /* True if we're generating a form of MIPS16 code in which PC-relative
203 loads are allowed. */
204 #define TARGET_MIPS16_PCREL_LOADS \
205 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
206
207 /* Generic ISA defines. */
208 #define ISA_MIPS1 (mips_isa == 1)
209 #define ISA_MIPS2 (mips_isa == 2)
210 #define ISA_MIPS3 (mips_isa == 3)
211 #define ISA_MIPS4 (mips_isa == 4)
212 #define ISA_MIPS32 (mips_isa == 32)
213 #define ISA_MIPS32R2 (mips_isa == 33)
214 #define ISA_MIPS64 (mips_isa == 64)
215 #define ISA_MIPS64R2 (mips_isa == 65)
216
217 /* Architecture target defines. */
218 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
219 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
220 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
221 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
222 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
223 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
224 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
225 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
226 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
227 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
228 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
229 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
230 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
231 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
232 || mips_arch == PROCESSOR_SB1A)
233 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
234
235 /* Scheduling target defines. */
236 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
237 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
238 || mips_tune == PROCESSOR_24KF2_1 \
239 || mips_tune == PROCESSOR_24KF1_1)
240 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
241 || mips_tune == PROCESSOR_74KF2_1 \
242 || mips_tune == PROCESSOR_74KF1_1 \
243 || mips_tune == PROCESSOR_74KF3_2)
244 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
245 || mips_tune == PROCESSOR_LOONGSON_2F)
246 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
247 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
248 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
249 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
250 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
251 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
252 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
253 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
254 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
255 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
256 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
257 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
258 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
259 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
260 || mips_tune == PROCESSOR_SB1A)
261
262 /* Whether vector modes and intrinsics for ST Microelectronics
263 Loongson-2E/2F processors should be enabled. In o32 pairs of
264 floating-point registers provide 64-bit values. */
265 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
266 && (TARGET_LOONGSON_2EF \
267 || TARGET_LOONGSON_3A))
268
269 /* True if the pre-reload scheduler should try to create chains of
270 multiply-add or multiply-subtract instructions. For example,
271 suppose we have:
272
273 t1 = a * b
274 t2 = t1 + c * d
275 t3 = e * f
276 t4 = t3 - g * h
277
278 t1 will have a higher priority than t2 and t3 will have a higher
279 priority than t4. However, before reload, there is no dependence
280 between t1 and t3, and they can often have similar priorities.
281 The scheduler will then tend to prefer:
282
283 t1 = a * b
284 t3 = e * f
285 t2 = t1 + c * d
286 t4 = t3 - g * h
287
288 which stops us from making full use of macc/madd-style instructions.
289 This sort of situation occurs frequently in Fourier transforms and
290 in unrolled loops.
291
292 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
293 queue so that chained multiply-add and multiply-subtract instructions
294 appear ahead of any other instruction that is likely to clobber lo.
295 In the example above, if t2 and t3 become ready at the same time,
296 the code ensures that t2 is scheduled first.
297
298 Multiply-accumulate instructions are a bigger win for some targets
299 than others, so this macro is defined on an opt-in basis. */
300 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
301 || TUNE_MIPS4120 \
302 || TUNE_MIPS4130 \
303 || TUNE_24K)
304
305 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
306 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
307
308 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
309 directly accessible, while the command-line options select
310 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
311 in use. */
312 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
313 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
314
315 /* False if SC acts as a memory barrier with respect to itself,
316 otherwise a SYNC will be emitted after SC for atomic operations
317 that require ordering between the SC and following loads and
318 stores. It does not tell anything about ordering of loads and
319 stores prior to and following the SC, only about the SC itself and
320 those loads and stores follow it. */
321 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
322
323 /* IRIX specific stuff. */
324 #define TARGET_IRIX6 0
325
326 /* Define preprocessor macros for the -march and -mtune options.
327 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
328 processor. If INFO's canonical name is "foo", define PREFIX to
329 be "foo", and define an additional macro PREFIX_FOO. */
330 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
331 do \
332 { \
333 char *macro, *p; \
334 \
335 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
336 for (p = macro; *p != 0; p++) \
337 *p = TOUPPER (*p); \
338 \
339 builtin_define (macro); \
340 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
341 free (macro); \
342 } \
343 while (0)
344
345 /* Target CPU builtins. */
346 #define TARGET_CPU_CPP_BUILTINS() \
347 do \
348 { \
349 /* Everyone but IRIX defines this to mips. */ \
350 if (!TARGET_IRIX6) \
351 builtin_assert ("machine=mips"); \
352 \
353 builtin_assert ("cpu=mips"); \
354 builtin_define ("__mips__"); \
355 builtin_define ("_mips"); \
356 \
357 /* We do this here because __mips is defined below and so we \
358 can't use builtin_define_std. We don't ever want to define \
359 "mips" for VxWorks because some of the VxWorks headers \
360 construct include filenames from a root directory macro, \
361 an architecture macro and a filename, where the architecture \
362 macro expands to 'mips'. If we define 'mips' to 1, the \
363 architecture macro expands to 1 as well. */ \
364 if (!flag_iso && !TARGET_VXWORKS) \
365 builtin_define ("mips"); \
366 \
367 if (TARGET_64BIT) \
368 builtin_define ("__mips64"); \
369 \
370 if (!TARGET_IRIX6) \
371 { \
372 /* Treat _R3000 and _R4000 like register-size \
373 defines, which is how they've historically \
374 been used. */ \
375 if (TARGET_64BIT) \
376 { \
377 builtin_define_std ("R4000"); \
378 builtin_define ("_R4000"); \
379 } \
380 else \
381 { \
382 builtin_define_std ("R3000"); \
383 builtin_define ("_R3000"); \
384 } \
385 } \
386 if (TARGET_FLOAT64) \
387 builtin_define ("__mips_fpr=64"); \
388 else \
389 builtin_define ("__mips_fpr=32"); \
390 \
391 if (mips_base_mips16) \
392 builtin_define ("__mips16"); \
393 \
394 if (TARGET_MIPS3D) \
395 builtin_define ("__mips3d"); \
396 \
397 if (TARGET_SMARTMIPS) \
398 builtin_define ("__mips_smartmips"); \
399 \
400 if (TARGET_DSP) \
401 { \
402 builtin_define ("__mips_dsp"); \
403 if (TARGET_DSPR2) \
404 { \
405 builtin_define ("__mips_dspr2"); \
406 builtin_define ("__mips_dsp_rev=2"); \
407 } \
408 else \
409 builtin_define ("__mips_dsp_rev=1"); \
410 } \
411 \
412 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
413 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
414 \
415 if (ISA_MIPS1) \
416 { \
417 builtin_define ("__mips=1"); \
418 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
419 } \
420 else if (ISA_MIPS2) \
421 { \
422 builtin_define ("__mips=2"); \
423 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
424 } \
425 else if (ISA_MIPS3) \
426 { \
427 builtin_define ("__mips=3"); \
428 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
429 } \
430 else if (ISA_MIPS4) \
431 { \
432 builtin_define ("__mips=4"); \
433 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
434 } \
435 else if (ISA_MIPS32) \
436 { \
437 builtin_define ("__mips=32"); \
438 builtin_define ("__mips_isa_rev=1"); \
439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
440 } \
441 else if (ISA_MIPS32R2) \
442 { \
443 builtin_define ("__mips=32"); \
444 builtin_define ("__mips_isa_rev=2"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
446 } \
447 else if (ISA_MIPS64) \
448 { \
449 builtin_define ("__mips=64"); \
450 builtin_define ("__mips_isa_rev=1"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
452 } \
453 else if (ISA_MIPS64R2) \
454 { \
455 builtin_define ("__mips=64"); \
456 builtin_define ("__mips_isa_rev=2"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
458 } \
459 \
460 switch (mips_abi) \
461 { \
462 case ABI_32: \
463 builtin_define ("_ABIO32=1"); \
464 builtin_define ("_MIPS_SIM=_ABIO32"); \
465 break; \
466 \
467 case ABI_N32: \
468 builtin_define ("_ABIN32=2"); \
469 builtin_define ("_MIPS_SIM=_ABIN32"); \
470 break; \
471 \
472 case ABI_64: \
473 builtin_define ("_ABI64=3"); \
474 builtin_define ("_MIPS_SIM=_ABI64"); \
475 break; \
476 \
477 case ABI_O64: \
478 builtin_define ("_ABIO64=4"); \
479 builtin_define ("_MIPS_SIM=_ABIO64"); \
480 break; \
481 } \
482 \
483 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
484 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
485 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
486 builtin_define_with_int_value ("_MIPS_FPSET", \
487 32 / MAX_FPRS_PER_FMT); \
488 \
489 /* These defines reflect the ABI in use, not whether the \
490 FPU is directly accessible. */ \
491 if (TARGET_NO_FLOAT) \
492 builtin_define ("__mips_no_float"); \
493 else if (TARGET_HARD_FLOAT_ABI) \
494 builtin_define ("__mips_hard_float"); \
495 else \
496 builtin_define ("__mips_soft_float"); \
497 \
498 if (TARGET_SINGLE_FLOAT) \
499 builtin_define ("__mips_single_float"); \
500 \
501 if (TARGET_PAIRED_SINGLE_FLOAT) \
502 builtin_define ("__mips_paired_single_float"); \
503 \
504 if (TARGET_BIG_ENDIAN) \
505 { \
506 builtin_define_std ("MIPSEB"); \
507 builtin_define ("_MIPSEB"); \
508 } \
509 else \
510 { \
511 builtin_define_std ("MIPSEL"); \
512 builtin_define ("_MIPSEL"); \
513 } \
514 \
515 /* Whether calls should go through $25. The separate __PIC__ \
516 macro indicates whether abicalls code might use a GOT. */ \
517 if (TARGET_ABICALLS) \
518 builtin_define ("__mips_abicalls"); \
519 \
520 /* Whether Loongson vector modes are enabled. */ \
521 if (TARGET_LOONGSON_VECTORS) \
522 builtin_define ("__mips_loongson_vector_rev"); \
523 \
524 /* Historical Octeon macro. */ \
525 if (TARGET_OCTEON) \
526 builtin_define ("__OCTEON__"); \
527 \
528 /* Macros dependent on the C dialect. */ \
529 if (preprocessing_asm_p ()) \
530 { \
531 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
532 builtin_define ("_LANGUAGE_ASSEMBLY"); \
533 } \
534 else if (c_dialect_cxx ()) \
535 { \
536 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
537 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
538 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
539 } \
540 else \
541 { \
542 builtin_define_std ("LANGUAGE_C"); \
543 builtin_define ("_LANGUAGE_C"); \
544 } \
545 if (c_dialect_objc ()) \
546 { \
547 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
548 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
549 /* Bizarre, but needed at least for Irix. */ \
550 builtin_define_std ("LANGUAGE_C"); \
551 builtin_define ("_LANGUAGE_C"); \
552 } \
553 \
554 if (mips_abi == ABI_EABI) \
555 builtin_define ("__mips_eabi"); \
556 \
557 if (TARGET_CACHE_BUILTIN) \
558 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
559 } \
560 while (0)
561
562 /* Default target_flags if no switches are specified */
563
564 #ifndef TARGET_DEFAULT
565 #define TARGET_DEFAULT 0
566 #endif
567
568 #ifndef TARGET_CPU_DEFAULT
569 #define TARGET_CPU_DEFAULT 0
570 #endif
571
572 #ifndef TARGET_ENDIAN_DEFAULT
573 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
574 #endif
575
576 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
577 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
578 #endif
579
580 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
581 #ifndef MIPS_ISA_DEFAULT
582 #ifndef MIPS_CPU_STRING_DEFAULT
583 #define MIPS_CPU_STRING_DEFAULT "from-abi"
584 #endif
585 #endif
586
587 #ifdef IN_LIBGCC2
588 #undef TARGET_64BIT
589 /* Make this compile time constant for libgcc2 */
590 #ifdef __mips64
591 #define TARGET_64BIT 1
592 #else
593 #define TARGET_64BIT 0
594 #endif
595 #endif /* IN_LIBGCC2 */
596
597 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
598 when compiled with hardware floating point. This is because MIPS16
599 code cannot save and restore the floating-point registers, which is
600 important if in a mixed MIPS16/non-MIPS16 environment. */
601
602 #ifdef IN_LIBGCC2
603 #if __mips_hard_float
604 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
605 #endif
606 #endif /* IN_LIBGCC2 */
607
608 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
609
610 #ifndef MULTILIB_ENDIAN_DEFAULT
611 #if TARGET_ENDIAN_DEFAULT == 0
612 #define MULTILIB_ENDIAN_DEFAULT "EL"
613 #else
614 #define MULTILIB_ENDIAN_DEFAULT "EB"
615 #endif
616 #endif
617
618 #ifndef MULTILIB_ISA_DEFAULT
619 # if MIPS_ISA_DEFAULT == 1
620 # define MULTILIB_ISA_DEFAULT "mips1"
621 # else
622 # if MIPS_ISA_DEFAULT == 2
623 # define MULTILIB_ISA_DEFAULT "mips2"
624 # else
625 # if MIPS_ISA_DEFAULT == 3
626 # define MULTILIB_ISA_DEFAULT "mips3"
627 # else
628 # if MIPS_ISA_DEFAULT == 4
629 # define MULTILIB_ISA_DEFAULT "mips4"
630 # else
631 # if MIPS_ISA_DEFAULT == 32
632 # define MULTILIB_ISA_DEFAULT "mips32"
633 # else
634 # if MIPS_ISA_DEFAULT == 33
635 # define MULTILIB_ISA_DEFAULT "mips32r2"
636 # else
637 # if MIPS_ISA_DEFAULT == 64
638 # define MULTILIB_ISA_DEFAULT "mips64"
639 # else
640 # if MIPS_ISA_DEFAULT == 65
641 # define MULTILIB_ISA_DEFAULT "mips64r2"
642 # else
643 # define MULTILIB_ISA_DEFAULT "mips1"
644 # endif
645 # endif
646 # endif
647 # endif
648 # endif
649 # endif
650 # endif
651 # endif
652 #endif
653
654 #ifndef MIPS_ABI_DEFAULT
655 #define MIPS_ABI_DEFAULT ABI_32
656 #endif
657
658 /* Use the most portable ABI flag for the ASM specs. */
659
660 #if MIPS_ABI_DEFAULT == ABI_32
661 #define MULTILIB_ABI_DEFAULT "mabi=32"
662 #endif
663
664 #if MIPS_ABI_DEFAULT == ABI_O64
665 #define MULTILIB_ABI_DEFAULT "mabi=o64"
666 #endif
667
668 #if MIPS_ABI_DEFAULT == ABI_N32
669 #define MULTILIB_ABI_DEFAULT "mabi=n32"
670 #endif
671
672 #if MIPS_ABI_DEFAULT == ABI_64
673 #define MULTILIB_ABI_DEFAULT "mabi=64"
674 #endif
675
676 #if MIPS_ABI_DEFAULT == ABI_EABI
677 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
678 #endif
679
680 #ifndef MULTILIB_DEFAULTS
681 #define MULTILIB_DEFAULTS \
682 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
683 #endif
684
685 /* We must pass -EL to the linker by default for little endian embedded
686 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
687 linker will default to using big-endian output files. The OUTPUT_FORMAT
688 line must be in the linker script, otherwise -EB/-EL will not work. */
689
690 #ifndef ENDIAN_SPEC
691 #if TARGET_ENDIAN_DEFAULT == 0
692 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
693 #else
694 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
695 #endif
696 #endif
697
698 /* A spec condition that matches all non-mips16 -mips arguments. */
699
700 #define MIPS_ISA_LEVEL_OPTION_SPEC \
701 "mips1|mips2|mips3|mips4|mips32*|mips64*"
702
703 /* A spec condition that matches all non-mips16 architecture arguments. */
704
705 #define MIPS_ARCH_OPTION_SPEC \
706 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
707
708 /* A spec that infers a -mips argument from an -march argument,
709 or injects the default if no architecture is specified. */
710
711 #define MIPS_ISA_LEVEL_SPEC \
712 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
713 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
714 %{march=mips2|march=r6000:-mips2} \
715 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
716 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
717 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
718 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
719 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
720 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
721 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
722 |march=xlr|march=loongson3a: -mips64} \
723 %{march=mips64r2|march=octeon: -mips64r2} \
724 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
725
726 /* A spec that infers a -mhard-float or -msoft-float setting from an
727 -march argument. Note that soft-float and hard-float code are not
728 link-compatible. */
729
730 #define MIPS_ARCH_FLOAT_SPEC \
731 "%{mhard-float|msoft-float|march=mips*:; \
732 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
733 |march=34kc|march=74kc|march=1004kc|march=5kc \
734 |march=octeon|march=xlr: -msoft-float; \
735 march=*: -mhard-float}"
736
737 /* A spec condition that matches 32-bit options. It only works if
738 MIPS_ISA_LEVEL_SPEC has been applied. */
739
740 #define MIPS_32BIT_OPTION_SPEC \
741 "mips1|mips2|mips32*|mgp32"
742
743 #if MIPS_ABI_DEFAULT == ABI_O64 \
744 || MIPS_ABI_DEFAULT == ABI_N32 \
745 || MIPS_ABI_DEFAULT == ABI_64
746 #define OPT_ARCH64 "mabi=32|mgp32:;"
747 #define OPT_ARCH32 "mabi=32|mgp32"
748 #else
749 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
750 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
751 #endif
752
753 /* Support for a compile-time default CPU, et cetera. The rules are:
754 --with-arch is ignored if -march is specified or a -mips is specified
755 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
756 --with-tune is ignored if -mtune is specified; likewise
757 --with-tune-32 and --with-tune-64.
758 --with-abi is ignored if -mabi is specified.
759 --with-float is ignored if -mhard-float or -msoft-float are
760 specified.
761 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
762 specified. */
763 #define OPTION_DEFAULT_SPECS \
764 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
765 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
766 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
767 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
768 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
769 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
770 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
771 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
772 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
773 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
774 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
775 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
776
777
778 /* A spec that infers the -mdsp setting from an -march argument. */
779 #define BASE_DRIVER_SELF_SPECS \
780 "%{!mno-dsp: \
781 %{march=24ke*|march=34k*|march=1004k*: -mdsp} \
782 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
783
784 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
785
786 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
787 && ISA_HAS_COND_TRAP)
788
789 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
790
791 /* True if the ABI can only work with 64-bit integer registers. We
792 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
793 otherwise floating-point registers must also be 64-bit. */
794 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
795
796 /* Likewise for 32-bit regs. */
797 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
798
799 /* True if the file format uses 64-bit symbols. At present, this is
800 only true for n64, which uses 64-bit ELF. */
801 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
802
803 /* True if symbols are 64 bits wide. This is usually determined by
804 the ABI's file format, but it can be overridden by -msym32. Note that
805 overriding the size with -msym32 changes the ABI of relocatable objects,
806 although it doesn't change the ABI of a fully-linked object. */
807 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS && !TARGET_SYM32)
808
809 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
810 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
811 || ISA_MIPS4 \
812 || ISA_MIPS64 \
813 || ISA_MIPS64R2)
814
815 /* ISA has branch likely instructions (e.g. mips2). */
816 /* Disable branchlikely for tx39 until compare rewrite. They haven't
817 been generated up to this point. */
818 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
819
820 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
821 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
822 || TARGET_MIPS5400 \
823 || TARGET_MIPS5500 \
824 || TARGET_MIPS7000 \
825 || TARGET_MIPS9000 \
826 || TARGET_MAD \
827 || ISA_MIPS32 \
828 || ISA_MIPS32R2 \
829 || ISA_MIPS64 \
830 || ISA_MIPS64R2) \
831 && !TARGET_MIPS16)
832
833 /* ISA has a three-operand multiplication instruction. */
834 #define ISA_HAS_DMUL3 (TARGET_64BIT \
835 && TARGET_OCTEON \
836 && !TARGET_MIPS16)
837
838 /* ISA has the floating-point conditional move instructions introduced
839 in mips4. */
840 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
841 || ISA_MIPS32 \
842 || ISA_MIPS32R2 \
843 || ISA_MIPS64 \
844 || ISA_MIPS64R2) \
845 && !TARGET_MIPS5500 \
846 && !TARGET_MIPS16)
847
848 /* ISA has the integer conditional move instructions introduced in mips4 and
849 ST Loongson 2E/2F. */
850 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
851
852 /* ISA has LDC1 and SDC1. */
853 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
854
855 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
856 branch on CC, and move (both FP and non-FP) on CC. */
857 #define ISA_HAS_8CC (ISA_MIPS4 \
858 || ISA_MIPS32 \
859 || ISA_MIPS32R2 \
860 || ISA_MIPS64 \
861 || ISA_MIPS64R2)
862
863 /* This is a catch all for other mips4 instructions: indexed load, the
864 FP madd and msub instructions, and the FP recip and recip sqrt
865 instructions. */
866 #define ISA_HAS_FP4 ((ISA_MIPS4 \
867 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
868 || ISA_MIPS64 \
869 || ISA_MIPS64R2) \
870 && !TARGET_MIPS16)
871
872 /* ISA has paired-single instructions. */
873 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
874
875 /* ISA has conditional trap instructions. */
876 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
877 && !TARGET_MIPS16)
878
879 /* ISA has integer multiply-accumulate instructions, madd and msub. */
880 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
881 || ISA_MIPS32R2 \
882 || ISA_MIPS64 \
883 || ISA_MIPS64R2) \
884 && !TARGET_MIPS16)
885
886 /* Integer multiply-accumulate instructions should be generated. */
887 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
888
889 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
890 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
891
892 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
893 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
894
895 /* ISA has floating-point nmadd and nmsub instructions
896 'd = -((a * b) [+-] c)'. */
897 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
898 ((ISA_MIPS4 \
899 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
900 || ISA_MIPS64 \
901 || ISA_MIPS64R2) \
902 && (!TARGET_MIPS5400 || TARGET_MAD) \
903 && !TARGET_MIPS16)
904
905 /* ISA has floating-point nmadd and nmsub instructions
906 'c = -((a * b) [+-] c)'. */
907 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
908 TARGET_LOONGSON_2EF
909
910 /* ISA has count leading zeroes/ones instruction (not implemented). */
911 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
912 || ISA_MIPS32R2 \
913 || ISA_MIPS64 \
914 || ISA_MIPS64R2) \
915 && !TARGET_MIPS16)
916
917 /* ISA has three operand multiply instructions that put
918 the high part in an accumulator: mulhi or mulhiu. */
919 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
920 || TARGET_MIPS5500 \
921 || TARGET_SR71K) \
922 && !TARGET_MIPS16)
923
924 /* ISA has three operand multiply instructions that
925 negates the result and puts the result in an accumulator. */
926 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
927 || TARGET_MIPS5500 \
928 || TARGET_SR71K) \
929 && !TARGET_MIPS16)
930
931 /* ISA has three operand multiply instructions that subtracts the
932 result from a 4th operand and puts the result in an accumulator. */
933 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
934 || TARGET_MIPS5500 \
935 || TARGET_SR71K) \
936 && !TARGET_MIPS16)
937
938 /* ISA has three operand multiply instructions that the result
939 from a 4th operand and puts the result in an accumulator. */
940 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
941 || TARGET_MIPS4130 \
942 || TARGET_MIPS5400 \
943 || TARGET_MIPS5500 \
944 || TARGET_SR71K) \
945 && !TARGET_MIPS16)
946
947 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
948 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
949 || TARGET_MIPS4130) \
950 && !TARGET_MIPS16)
951
952 /* ISA has the "ror" (rotate right) instructions. */
953 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
954 || ISA_MIPS64R2 \
955 || TARGET_MIPS5400 \
956 || TARGET_MIPS5500 \
957 || TARGET_SR71K \
958 || TARGET_SMARTMIPS) \
959 && !TARGET_MIPS16)
960
961 /* ISA has data prefetch instructions. This controls use of 'pref'. */
962 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
963 || TARGET_LOONGSON_2EF \
964 || ISA_MIPS32 \
965 || ISA_MIPS32R2 \
966 || ISA_MIPS64 \
967 || ISA_MIPS64R2) \
968 && !TARGET_MIPS16)
969
970 /* ISA has data indexed prefetch instructions. This controls use of
971 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
972 (prefx is a cop1x instruction, so can only be used if FP is
973 enabled.) */
974 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
975 || ISA_MIPS32R2 \
976 || ISA_MIPS64 \
977 || ISA_MIPS64R2) \
978 && !TARGET_MIPS16)
979
980 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
981 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
982 also requires TARGET_DOUBLE_FLOAT. */
983 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
984
985 /* ISA includes the MIPS32r2 seb and seh instructions. */
986 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
987 || ISA_MIPS64R2) \
988 && !TARGET_MIPS16)
989
990 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
991 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
992 || ISA_MIPS64R2) \
993 && !TARGET_MIPS16)
994
995 /* ISA has instructions for accessing top part of 64-bit fp regs. */
996 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
997 && (ISA_MIPS32R2 \
998 || ISA_MIPS64R2))
999
1000 /* ISA has lwxs instruction (load w/scaled index address. */
1001 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
1002
1003 /* The DSP ASE is available. */
1004 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1005
1006 /* Revision 2 of the DSP ASE is available. */
1007 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1008
1009 /* True if the result of a load is not available to the next instruction.
1010 A nop will then be needed between instructions like "lw $4,..."
1011 and "addiu $4,$4,1". */
1012 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1013 && !TARGET_MIPS3900 \
1014 && !TARGET_MIPS16)
1015
1016 /* Likewise mtc1 and mfc1. */
1017 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1018 && !TARGET_LOONGSON_2EF)
1019
1020 /* Likewise floating-point comparisons. */
1021 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1022 && !TARGET_LOONGSON_2EF)
1023
1024 /* True if mflo and mfhi can be immediately followed by instructions
1025 which write to the HI and LO registers.
1026
1027 According to MIPS specifications, MIPS ISAs I, II, and III need
1028 (at least) two instructions between the reads of HI/LO and
1029 instructions which write them, and later ISAs do not. Contradicting
1030 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1031 the UM for the NEC Vr5000) document needing the instructions between
1032 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1033 MIPS64 and later ISAs to have the interlocks, plus any specific
1034 earlier-ISA CPUs for which CPU documentation declares that the
1035 instructions are really interlocked. */
1036 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1037 || ISA_MIPS32R2 \
1038 || ISA_MIPS64 \
1039 || ISA_MIPS64R2 \
1040 || TARGET_MIPS5500 \
1041 || TARGET_LOONGSON_2EF)
1042
1043 /* ISA includes synci, jr.hb and jalr.hb. */
1044 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1045 || ISA_MIPS64R2) \
1046 && !TARGET_MIPS16)
1047
1048 /* ISA includes sync. */
1049 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1050 #define GENERATE_SYNC \
1051 (target_flags_explicit & MASK_LLSC \
1052 ? TARGET_LLSC && !TARGET_MIPS16 \
1053 : ISA_HAS_SYNC)
1054
1055 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1056 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1057 instructions. */
1058 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1059 #define GENERATE_LL_SC \
1060 (target_flags_explicit & MASK_LLSC \
1061 ? TARGET_LLSC && !TARGET_MIPS16 \
1062 : ISA_HAS_LL_SC)
1063
1064 /* ISA includes the baddu instruction. */
1065 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1066
1067 /* ISA includes the bbit* instructions. */
1068 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1069
1070 /* ISA includes the cins instruction. */
1071 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1072
1073 /* ISA includes the exts instruction. */
1074 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1075
1076 /* ISA includes the seq and sne instructions. */
1077 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1078
1079 /* ISA includes the pop instruction. */
1080 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1081
1082 /* The CACHE instruction is available in non-MIPS16 code. */
1083 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1084
1085 /* The CACHE instruction is available. */
1086 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1087 \f
1088 /* Tell collect what flags to pass to nm. */
1089 #ifndef NM_FLAGS
1090 #define NM_FLAGS "-Bn"
1091 #endif
1092
1093 \f
1094 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1095 to the assembler. It may be overridden by subtargets. */
1096 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1097 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1098 %{noasmopt:-O0} \
1099 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1100 #endif
1101
1102 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1103 the assembler. It may be overridden by subtargets.
1104
1105 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1106 COFF debugging info. */
1107
1108 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1109 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1110 %{g} %{g0} %{g1} %{g2} %{g3} \
1111 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1112 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1113 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1114 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1115 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1116 #endif
1117
1118 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1119 overridden by subtargets. */
1120
1121 #ifndef SUBTARGET_ASM_SPEC
1122 #define SUBTARGET_ASM_SPEC ""
1123 #endif
1124
1125 #undef ASM_SPEC
1126 #define ASM_SPEC "\
1127 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1128 %{mips32*} %{mips64*} \
1129 %{mips16} %{mno-mips16:-no-mips16} \
1130 %{mips3d} %{mno-mips3d:-no-mips3d} \
1131 %{mdmx} %{mno-mdmx:-no-mdmx} \
1132 %{mdsp} %{mno-dsp} \
1133 %{mdspr2} %{mno-dspr2} \
1134 %{msmartmips} %{mno-smartmips} \
1135 %{mmt} %{mno-mt} \
1136 %{mfix-vr4120} %{mfix-vr4130} \
1137 %(subtarget_asm_optimizing_spec) \
1138 %(subtarget_asm_debugging_spec) \
1139 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1140 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1141 %{mfp32} %{mfp64} \
1142 %{mshared} %{mno-shared} \
1143 %{msym32} %{mno-sym32} \
1144 %{mtune=*} \
1145 %(subtarget_asm_spec)"
1146
1147 /* Extra switches sometimes passed to the linker. */
1148 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1149 will interpret it as a -b option. */
1150
1151 #ifndef LINK_SPEC
1152 #define LINK_SPEC "\
1153 %(endian_spec) \
1154 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1155 %{bestGnum} %{shared} %{non_shared}"
1156 #endif /* LINK_SPEC defined */
1157
1158
1159 /* Specs for the compiler proper */
1160
1161 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1162 overridden by subtargets. */
1163 #ifndef SUBTARGET_CC1_SPEC
1164 #define SUBTARGET_CC1_SPEC ""
1165 #endif
1166
1167 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1168
1169 #undef CC1_SPEC
1170 #define CC1_SPEC "\
1171 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1172 %(subtarget_cc1_spec)"
1173
1174 /* Preprocessor specs. */
1175
1176 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1177 overridden by subtargets. */
1178 #ifndef SUBTARGET_CPP_SPEC
1179 #define SUBTARGET_CPP_SPEC ""
1180 #endif
1181
1182 #define CPP_SPEC "%(subtarget_cpp_spec)"
1183
1184 /* This macro defines names of additional specifications to put in the specs
1185 that can be used in various specifications like CC1_SPEC. Its definition
1186 is an initializer with a subgrouping for each command option.
1187
1188 Each subgrouping contains a string constant, that defines the
1189 specification name, and a string constant that used by the GCC driver
1190 program.
1191
1192 Do not define this macro if it does not need to do anything. */
1193
1194 #define EXTRA_SPECS \
1195 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1196 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1197 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1198 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1199 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1200 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1201 { "endian_spec", ENDIAN_SPEC }, \
1202 SUBTARGET_EXTRA_SPECS
1203
1204 #ifndef SUBTARGET_EXTRA_SPECS
1205 #define SUBTARGET_EXTRA_SPECS
1206 #endif
1207 \f
1208 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1209 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1210
1211 #ifndef PREFERRED_DEBUGGING_TYPE
1212 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1213 #endif
1214
1215 /* The size of DWARF addresses should be the same as the size of symbols
1216 in the target file format. They shouldn't depend on things like -msym32,
1217 because many DWARF consumers do not allow the mixture of address sizes
1218 that one would then get from linking -msym32 code with -msym64 code.
1219
1220 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1221 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1222 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1223
1224 /* By default, turn on GDB extensions. */
1225 #define DEFAULT_GDB_EXTENSIONS 1
1226
1227 /* Local compiler-generated symbols must have a prefix that the assembler
1228 understands. By default, this is $, although some targets (e.g.,
1229 NetBSD-ELF) need to override this. */
1230
1231 #ifndef LOCAL_LABEL_PREFIX
1232 #define LOCAL_LABEL_PREFIX "$"
1233 #endif
1234
1235 /* By default on the mips, external symbols do not have an underscore
1236 prepended, but some targets (e.g., NetBSD) require this. */
1237
1238 #ifndef USER_LABEL_PREFIX
1239 #define USER_LABEL_PREFIX ""
1240 #endif
1241
1242 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1243 since the length can run past this up to a continuation point. */
1244 #undef DBX_CONTIN_LENGTH
1245 #define DBX_CONTIN_LENGTH 1500
1246
1247 /* How to renumber registers for dbx and gdb. */
1248 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1249
1250 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1251 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1252
1253 /* The DWARF 2 CFA column which tracks the return address. */
1254 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1255
1256 /* Before the prologue, RA lives in r31. */
1257 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1258
1259 /* Describe how we implement __builtin_eh_return. */
1260 #define EH_RETURN_DATA_REGNO(N) \
1261 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1262
1263 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1264
1265 #define EH_USES(N) mips_eh_uses (N)
1266
1267 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1268 The default for this in 64-bit mode is 8, which causes problems with
1269 SFmode register saves. */
1270 #define DWARF_CIE_DATA_ALIGNMENT -4
1271
1272 /* Correct the offset of automatic variables and arguments. Note that
1273 the MIPS debug format wants all automatic variables and arguments
1274 to be in terms of the virtual frame pointer (stack pointer before
1275 any adjustment in the function), while the MIPS 3.0 linker wants
1276 the frame pointer to be the stack pointer after the initial
1277 adjustment. */
1278
1279 #define DEBUGGER_AUTO_OFFSET(X) \
1280 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1281 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1282 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1283 \f
1284 /* Target machine storage layout */
1285
1286 #define BITS_BIG_ENDIAN 0
1287 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1288 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1289
1290 #define MAX_BITS_PER_WORD 64
1291
1292 /* Width of a word, in units (bytes). */
1293 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1294 #ifndef IN_LIBGCC2
1295 #define MIN_UNITS_PER_WORD 4
1296 #endif
1297
1298 /* For MIPS, width of a floating point register. */
1299 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1300
1301 /* The number of consecutive floating-point registers needed to store the
1302 largest format supported by the FPU. */
1303 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1304
1305 /* The number of consecutive floating-point registers needed to store the
1306 smallest format supported by the FPU. */
1307 #define MIN_FPRS_PER_FMT \
1308 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1309 ? 1 : MAX_FPRS_PER_FMT)
1310
1311 /* The largest size of value that can be held in floating-point
1312 registers and moved with a single instruction. */
1313 #define UNITS_PER_HWFPVALUE \
1314 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1315
1316 /* The largest size of value that can be held in floating-point
1317 registers. */
1318 #define UNITS_PER_FPVALUE \
1319 (TARGET_SOFT_FLOAT_ABI ? 0 \
1320 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1321 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1322
1323 /* The number of bytes in a double. */
1324 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1325
1326 /* Set the sizes of the core types. */
1327 #define SHORT_TYPE_SIZE 16
1328 #define INT_TYPE_SIZE 32
1329 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1330 #define LONG_LONG_TYPE_SIZE 64
1331
1332 #define FLOAT_TYPE_SIZE 32
1333 #define DOUBLE_TYPE_SIZE 64
1334 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1335
1336 /* Define the sizes of fixed-point types. */
1337 #define SHORT_FRACT_TYPE_SIZE 8
1338 #define FRACT_TYPE_SIZE 16
1339 #define LONG_FRACT_TYPE_SIZE 32
1340 #define LONG_LONG_FRACT_TYPE_SIZE 64
1341
1342 #define SHORT_ACCUM_TYPE_SIZE 16
1343 #define ACCUM_TYPE_SIZE 32
1344 #define LONG_ACCUM_TYPE_SIZE 64
1345 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1346 doesn't support 128-bit integers for MIPS32 currently. */
1347 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1348
1349 /* long double is not a fixed mode, but the idea is that, if we
1350 support long double, we also want a 128-bit integer type. */
1351 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1352
1353 #ifdef IN_LIBGCC2
1354 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1355 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1356 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1357 # else
1358 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1359 # endif
1360 #endif
1361
1362 /* Width in bits of a pointer. */
1363 #ifndef POINTER_SIZE
1364 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1365 #endif
1366
1367 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1368 #define PARM_BOUNDARY BITS_PER_WORD
1369
1370 /* Allocation boundary (in *bits*) for the code of a function. */
1371 #define FUNCTION_BOUNDARY 32
1372
1373 /* Alignment of field after `int : 0' in a structure. */
1374 #define EMPTY_FIELD_BOUNDARY 32
1375
1376 /* Every structure's size must be a multiple of this. */
1377 /* 8 is observed right on a DECstation and on riscos 4.02. */
1378 #define STRUCTURE_SIZE_BOUNDARY 8
1379
1380 /* There is no point aligning anything to a rounder boundary than this. */
1381 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1382
1383 /* All accesses must be aligned. */
1384 #define STRICT_ALIGNMENT 1
1385
1386 /* Define this if you wish to imitate the way many other C compilers
1387 handle alignment of bitfields and the structures that contain
1388 them.
1389
1390 The behavior is that the type written for a bit-field (`int',
1391 `short', or other integer type) imposes an alignment for the
1392 entire structure, as if the structure really did contain an
1393 ordinary field of that type. In addition, the bit-field is placed
1394 within the structure so that it would fit within such a field,
1395 not crossing a boundary for it.
1396
1397 Thus, on most machines, a bit-field whose type is written as `int'
1398 would not cross a four-byte boundary, and would force four-byte
1399 alignment for the whole structure. (The alignment used may not
1400 be four bytes; it is controlled by the other alignment
1401 parameters.)
1402
1403 If the macro is defined, its definition should be a C expression;
1404 a nonzero value for the expression enables this behavior. */
1405
1406 #define PCC_BITFIELD_TYPE_MATTERS 1
1407
1408 /* If defined, a C expression to compute the alignment given to a
1409 constant that is being placed in memory. CONSTANT is the constant
1410 and ALIGN is the alignment that the object would ordinarily have.
1411 The value of this macro is used instead of that alignment to align
1412 the object.
1413
1414 If this macro is not defined, then ALIGN is used.
1415
1416 The typical use of this macro is to increase alignment for string
1417 constants to be word aligned so that `strcpy' calls that copy
1418 constants can be done inline. */
1419
1420 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1421 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1422 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1423
1424 /* If defined, a C expression to compute the alignment for a static
1425 variable. TYPE is the data type, and ALIGN is the alignment that
1426 the object would ordinarily have. The value of this macro is used
1427 instead of that alignment to align the object.
1428
1429 If this macro is not defined, then ALIGN is used.
1430
1431 One use of this macro is to increase alignment of medium-size
1432 data to make it all fit in fewer cache lines. Another is to
1433 cause character arrays to be word-aligned so that `strcpy' calls
1434 that copy constants to character arrays can be done inline. */
1435
1436 #undef DATA_ALIGNMENT
1437 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1438 ((((ALIGN) < BITS_PER_WORD) \
1439 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1440 || TREE_CODE (TYPE) == UNION_TYPE \
1441 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1442
1443 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1444 character arrays to be word-aligned so that `strcpy' calls that copy
1445 constants to character arrays can be done inline, and 'strcmp' can be
1446 optimised to use word loads. */
1447 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1448 DATA_ALIGNMENT (TYPE, ALIGN)
1449
1450 #define PAD_VARARGS_DOWN \
1451 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1452
1453 /* Define if operations between registers always perform the operation
1454 on the full register even if a narrower mode is specified. */
1455 #define WORD_REGISTER_OPERATIONS
1456
1457 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1458 moves. All other references are zero extended. */
1459 #define LOAD_EXTEND_OP(MODE) \
1460 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1461 ? SIGN_EXTEND : ZERO_EXTEND)
1462
1463 /* Define this macro if it is advisable to hold scalars in registers
1464 in a wider mode than that declared by the program. In such cases,
1465 the value is constrained to be within the bounds of the declared
1466 type, but kept valid in the wider mode. The signedness of the
1467 extension may differ from that of the type. */
1468
1469 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1470 if (GET_MODE_CLASS (MODE) == MODE_INT \
1471 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1472 { \
1473 if ((MODE) == SImode) \
1474 (UNSIGNEDP) = 0; \
1475 (MODE) = Pmode; \
1476 }
1477
1478 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1479 Extensions of pointers to word_mode must be signed. */
1480 #define POINTERS_EXTEND_UNSIGNED false
1481
1482 /* Define if loading short immediate values into registers sign extends. */
1483 #define SHORT_IMMEDIATES_SIGN_EXTEND
1484
1485 /* The [d]clz instructions have the natural values at 0. */
1486
1487 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1488 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1489 \f
1490 /* Standard register usage. */
1491
1492 /* Number of hardware registers. We have:
1493
1494 - 32 integer registers
1495 - 32 floating point registers
1496 - 8 condition code registers
1497 - 2 accumulator registers (hi and lo)
1498 - 32 registers each for coprocessors 0, 2 and 3
1499 - 4 fake registers:
1500 - ARG_POINTER_REGNUM
1501 - FRAME_POINTER_REGNUM
1502 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1503 - CPRESTORE_SLOT_REGNUM
1504 - 2 dummy entries that were used at various times in the past.
1505 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1506 - 6 DSP control registers */
1507
1508 #define FIRST_PSEUDO_REGISTER 188
1509
1510 /* By default, fix the kernel registers ($26 and $27), the global
1511 pointer ($28) and the stack pointer ($29). This can change
1512 depending on the command-line options.
1513
1514 Regarding coprocessor registers: without evidence to the contrary,
1515 it's best to assume that each coprocessor register has a unique
1516 use. This can be overridden, in, e.g., mips_option_override or
1517 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1518 inappropriate for a particular target. */
1519
1520 #define FIXED_REGISTERS \
1521 { \
1522 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1523 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1524 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1525 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1526 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1527 /* COP0 registers */ \
1528 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1529 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1530 /* COP2 registers */ \
1531 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1532 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1533 /* COP3 registers */ \
1534 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1535 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1536 /* 6 DSP accumulator registers & 6 control registers */ \
1537 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1538 }
1539
1540
1541 /* Set up this array for o32 by default.
1542
1543 Note that we don't mark $31 as a call-clobbered register. The idea is
1544 that it's really the call instructions themselves which clobber $31.
1545 We don't care what the called function does with it afterwards.
1546
1547 This approach makes it easier to implement sibcalls. Unlike normal
1548 calls, sibcalls don't clobber $31, so the register reaches the
1549 called function in tact. EPILOGUE_USES says that $31 is useful
1550 to the called function. */
1551
1552 #define CALL_USED_REGISTERS \
1553 { \
1554 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1555 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1557 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1558 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1559 /* COP0 registers */ \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1561 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1562 /* COP2 registers */ \
1563 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1565 /* COP3 registers */ \
1566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1567 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1568 /* 6 DSP accumulator registers & 6 control registers */ \
1569 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1570 }
1571
1572
1573 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1574
1575 #define CALL_REALLY_USED_REGISTERS \
1576 { /* General registers. */ \
1577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1578 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1579 /* Floating-point registers. */ \
1580 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1581 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1582 /* Others. */ \
1583 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1584 /* COP0 registers */ \
1585 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1587 /* COP2 registers */ \
1588 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1589 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1590 /* COP3 registers */ \
1591 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1592 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1593 /* 6 DSP accumulator registers & 6 control registers */ \
1594 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1595 }
1596
1597 /* Internal macros to classify a register number as to whether it's a
1598 general purpose register, a floating point register, a
1599 multiply/divide register, or a status register. */
1600
1601 #define GP_REG_FIRST 0
1602 #define GP_REG_LAST 31
1603 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1604 #define GP_DBX_FIRST 0
1605 #define K0_REG_NUM (GP_REG_FIRST + 26)
1606 #define K1_REG_NUM (GP_REG_FIRST + 27)
1607 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1608
1609 #define FP_REG_FIRST 32
1610 #define FP_REG_LAST 63
1611 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1612 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1613
1614 #define MD_REG_FIRST 64
1615 #define MD_REG_LAST 65
1616 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1617 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1618
1619 /* The DWARF 2 CFA column which tracks the return address from a
1620 signal handler context. This means that to maintain backwards
1621 compatibility, no hard register can be assigned this column if it
1622 would need to be handled by the DWARF unwinder. */
1623 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1624
1625 #define ST_REG_FIRST 67
1626 #define ST_REG_LAST 74
1627 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1628
1629
1630 /* FIXME: renumber. */
1631 #define COP0_REG_FIRST 80
1632 #define COP0_REG_LAST 111
1633 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1634
1635 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1636 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1637 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1638
1639 #define COP2_REG_FIRST 112
1640 #define COP2_REG_LAST 143
1641 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1642
1643 #define COP3_REG_FIRST 144
1644 #define COP3_REG_LAST 175
1645 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1646 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1647 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1648
1649 #define DSP_ACC_REG_FIRST 176
1650 #define DSP_ACC_REG_LAST 181
1651 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1652
1653 #define AT_REGNUM (GP_REG_FIRST + 1)
1654 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1655 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1656
1657 /* A few bitfield locations for the coprocessor registers. */
1658 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1659 the cause register for the EIC interrupt mode. */
1660 #define CAUSE_IPL 10
1661 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1662 #define SR_IPL 10
1663 /* Exception Level is at bit 1 of the status register. */
1664 #define SR_EXL 1
1665 /* Interrupt Enable is at bit 0 of the status register. */
1666 #define SR_IE 0
1667
1668 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1669 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1670 should be used instead. */
1671 #define FPSW_REGNUM ST_REG_FIRST
1672
1673 #define GP_REG_P(REGNO) \
1674 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1675 #define M16_REG_P(REGNO) \
1676 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1677 #define FP_REG_P(REGNO) \
1678 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1679 #define MD_REG_P(REGNO) \
1680 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1681 #define ST_REG_P(REGNO) \
1682 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1683 #define COP0_REG_P(REGNO) \
1684 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1685 #define COP2_REG_P(REGNO) \
1686 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1687 #define COP3_REG_P(REGNO) \
1688 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1689 #define ALL_COP_REG_P(REGNO) \
1690 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1691 /* Test if REGNO is one of the 6 new DSP accumulators. */
1692 #define DSP_ACC_REG_P(REGNO) \
1693 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1694 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1695 #define ACC_REG_P(REGNO) \
1696 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1697
1698 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1699
1700 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1701 to initialize the mips16 gp pseudo register. */
1702 #define CONST_GP_P(X) \
1703 (GET_CODE (X) == CONST \
1704 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1705 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1706
1707 /* Return coprocessor number from register number. */
1708
1709 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1710 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1711 : COP3_REG_P (REGNO) ? '3' : '?')
1712
1713
1714 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1715
1716 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1717 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1718
1719 #define MODES_TIEABLE_P mips_modes_tieable_p
1720
1721 /* Register to use for pushing function arguments. */
1722 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1723
1724 /* These two registers don't really exist: they get eliminated to either
1725 the stack or hard frame pointer. */
1726 #define ARG_POINTER_REGNUM 77
1727 #define FRAME_POINTER_REGNUM 78
1728
1729 /* $30 is not available on the mips16, so we use $17 as the frame
1730 pointer. */
1731 #define HARD_FRAME_POINTER_REGNUM \
1732 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1733
1734 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1735 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1736
1737 /* Register in which static-chain is passed to a function. */
1738 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1739
1740 /* Registers used as temporaries in prologue/epilogue code:
1741
1742 - If a MIPS16 PIC function needs access to _gp, it first loads
1743 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1744
1745 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1746 register. The register must not conflict with MIPS16_PIC_TEMP.
1747
1748 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1749 register.
1750
1751 If we're generating MIPS16 code, these registers must come from the
1752 core set of 8. The prologue registers mustn't conflict with any
1753 incoming arguments, the static chain pointer, or the frame pointer.
1754 The epilogue temporary mustn't conflict with the return registers,
1755 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1756 or the EH data registers.
1757
1758 If we're generating interrupt handlers, we use K0 as a temporary register
1759 in prologue/epilogue code. */
1760
1761 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1762 #define MIPS_PROLOGUE_TEMP_REGNUM \
1763 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1764 #define MIPS_EPILOGUE_TEMP_REGNUM \
1765 (cfun->machine->interrupt_handler_p \
1766 ? K0_REG_NUM \
1767 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1768
1769 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1770 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1771 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1772
1773 /* Define this macro if it is as good or better to call a constant
1774 function address than to call an address kept in a register. */
1775 #define NO_FUNCTION_CSE 1
1776
1777 /* The ABI-defined global pointer. Sometimes we use a different
1778 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1779 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1780
1781 /* We normally use $28 as the global pointer. However, when generating
1782 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1783 register instead. They can then avoid saving and restoring $28
1784 and perhaps avoid using a frame at all.
1785
1786 When a leaf function uses something other than $28, mips_expand_prologue
1787 will modify pic_offset_table_rtx in place. Take the register number
1788 from there after reload. */
1789 #define PIC_OFFSET_TABLE_REGNUM \
1790 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1791
1792 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1793 \f
1794 /* Define the classes of registers for register constraints in the
1795 machine description. Also define ranges of constants.
1796
1797 One of the classes must always be named ALL_REGS and include all hard regs.
1798 If there is more than one class, another class must be named NO_REGS
1799 and contain no registers.
1800
1801 The name GENERAL_REGS must be the name of a class (or an alias for
1802 another name such as ALL_REGS). This is the class of registers
1803 that is allowed by "g" or "r" in a register constraint.
1804 Also, registers outside this class are allocated only when
1805 instructions express preferences for them.
1806
1807 The classes must be numbered in nondecreasing order; that is,
1808 a larger-numbered class must never be contained completely
1809 in a smaller-numbered class.
1810
1811 For any two classes, it is very desirable that there be another
1812 class that represents their union. */
1813
1814 enum reg_class
1815 {
1816 NO_REGS, /* no registers in set */
1817 M16_REGS, /* mips16 directly accessible registers */
1818 T_REG, /* mips16 T register ($24) */
1819 M16_T_REGS, /* mips16 registers plus T register */
1820 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1821 V1_REG, /* Register $v1 ($3) used for TLS access. */
1822 LEA_REGS, /* Every GPR except $25 */
1823 GR_REGS, /* integer registers */
1824 FP_REGS, /* floating point registers */
1825 MD0_REG, /* first multiply/divide register */
1826 MD1_REG, /* second multiply/divide register */
1827 MD_REGS, /* multiply/divide registers (hi/lo) */
1828 COP0_REGS, /* generic coprocessor classes */
1829 COP2_REGS,
1830 COP3_REGS,
1831 ST_REGS, /* status registers (fp status) */
1832 DSP_ACC_REGS, /* DSP accumulator registers */
1833 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1834 FRAME_REGS, /* $arg and $frame */
1835 GR_AND_MD0_REGS, /* union classes */
1836 GR_AND_MD1_REGS,
1837 GR_AND_MD_REGS,
1838 GR_AND_ACC_REGS,
1839 ALL_REGS, /* all registers */
1840 LIM_REG_CLASSES /* max value + 1 */
1841 };
1842
1843 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1844
1845 #define GENERAL_REGS GR_REGS
1846
1847 /* An initializer containing the names of the register classes as C
1848 string constants. These names are used in writing some of the
1849 debugging dumps. */
1850
1851 #define REG_CLASS_NAMES \
1852 { \
1853 "NO_REGS", \
1854 "M16_REGS", \
1855 "T_REG", \
1856 "M16_T_REGS", \
1857 "PIC_FN_ADDR_REG", \
1858 "V1_REG", \
1859 "LEA_REGS", \
1860 "GR_REGS", \
1861 "FP_REGS", \
1862 "MD0_REG", \
1863 "MD1_REG", \
1864 "MD_REGS", \
1865 /* coprocessor registers */ \
1866 "COP0_REGS", \
1867 "COP2_REGS", \
1868 "COP3_REGS", \
1869 "ST_REGS", \
1870 "DSP_ACC_REGS", \
1871 "ACC_REGS", \
1872 "FRAME_REGS", \
1873 "GR_AND_MD0_REGS", \
1874 "GR_AND_MD1_REGS", \
1875 "GR_AND_MD_REGS", \
1876 "GR_AND_ACC_REGS", \
1877 "ALL_REGS" \
1878 }
1879
1880 /* An initializer containing the contents of the register classes,
1881 as integers which are bit masks. The Nth integer specifies the
1882 contents of class N. The way the integer MASK is interpreted is
1883 that register R is in the class if `MASK & (1 << R)' is 1.
1884
1885 When the machine has more than 32 registers, an integer does not
1886 suffice. Then the integers are replaced by sub-initializers,
1887 braced groupings containing several integers. Each
1888 sub-initializer must be suitable as an initializer for the type
1889 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1890
1891 #define REG_CLASS_CONTENTS \
1892 { \
1893 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1894 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1895 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1896 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1897 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1898 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1899 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1900 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1901 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1902 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1903 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1904 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1905 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1906 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1907 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1908 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1909 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1910 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1911 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1912 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1913 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1914 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1915 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1916 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1917 }
1918
1919
1920 /* A C expression whose value is a register class containing hard
1921 register REGNO. In general there is more that one such class;
1922 choose a class which is "minimal", meaning that no smaller class
1923 also contains the register. */
1924
1925 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1926
1927 /* A macro whose definition is the name of the class to which a
1928 valid base register must belong. A base register is one used in
1929 an address which is the register value plus a displacement. */
1930
1931 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1932
1933 /* A macro whose definition is the name of the class to which a
1934 valid index register must belong. An index register is one used
1935 in an address where its value is either multiplied by a scale
1936 factor or added to another register (as well as added to a
1937 displacement). */
1938
1939 #define INDEX_REG_CLASS NO_REGS
1940
1941 /* We generally want to put call-clobbered registers ahead of
1942 call-saved ones. (IRA expects this.) */
1943
1944 #define REG_ALLOC_ORDER \
1945 { /* Accumulator registers. When GPRs and accumulators have equal \
1946 cost, we generally prefer to use accumulators. For example, \
1947 a division of multiplication result is better allocated to LO, \
1948 so that we put the MFLO at the point of use instead of at the \
1949 point of definition. It's also needed if we're to take advantage \
1950 of the extra accumulators available with -mdspr2. In some cases, \
1951 it can also help to reduce register pressure. */ \
1952 64, 65,176,177,178,179,180,181, \
1953 /* Call-clobbered GPRs. */ \
1954 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1955 24, 25, 31, \
1956 /* The global pointer. This is call-clobbered for o32 and o64 \
1957 abicalls, call-saved for n32 and n64 abicalls, and a program \
1958 invariant otherwise. Putting it between the call-clobbered \
1959 and call-saved registers should cope with all eventualities. */ \
1960 28, \
1961 /* Call-saved GPRs. */ \
1962 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1963 /* GPRs that can never be exposed to the register allocator. */ \
1964 0, 26, 27, 29, \
1965 /* Call-clobbered FPRs. */ \
1966 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1967 48, 49, 50, 51, \
1968 /* FPRs that are usually call-saved. The odd ones are actually \
1969 call-clobbered for n32, but listing them ahead of the even \
1970 registers might encourage the register allocator to fragment \
1971 the available FPR pairs. We need paired FPRs to store long \
1972 doubles, so it isn't clear that using a different order \
1973 for n32 would be a win. */ \
1974 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1975 /* None of the remaining classes have defined call-saved \
1976 registers. */ \
1977 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1978 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1979 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1980 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1981 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1982 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1983 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1984 182,183,184,185,186,187 \
1985 }
1986
1987 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1988 to be rearranged based on a particular function. On the mips16, we
1989 want to allocate $24 (T_REG) before other registers for
1990 instructions for which it is possible. */
1991
1992 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
1993
1994 /* True if VALUE is an unsigned 6-bit number. */
1995
1996 #define UIMM6_OPERAND(VALUE) \
1997 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1998
1999 /* True if VALUE is a signed 10-bit number. */
2000
2001 #define IMM10_OPERAND(VALUE) \
2002 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2003
2004 /* True if VALUE is a signed 16-bit number. */
2005
2006 #define SMALL_OPERAND(VALUE) \
2007 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2008
2009 /* True if VALUE is an unsigned 16-bit number. */
2010
2011 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2012 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2013
2014 /* True if VALUE can be loaded into a register using LUI. */
2015
2016 #define LUI_OPERAND(VALUE) \
2017 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2018 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2019
2020 /* Return a value X with the low 16 bits clear, and such that
2021 VALUE - X is a signed 16-bit value. */
2022
2023 #define CONST_HIGH_PART(VALUE) \
2024 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2025
2026 #define CONST_LOW_PART(VALUE) \
2027 ((VALUE) - CONST_HIGH_PART (VALUE))
2028
2029 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2030 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2031 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2032
2033 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2034 mips_preferred_reload_class (X, CLASS)
2035
2036 /* The HI and LO registers can only be reloaded via the general
2037 registers. Condition code registers can only be loaded to the
2038 general registers, and from the floating point registers. */
2039
2040 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2041 mips_secondary_reload_class (CLASS, MODE, X, true)
2042 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2043 mips_secondary_reload_class (CLASS, MODE, X, false)
2044
2045 /* Return the maximum number of consecutive registers
2046 needed to represent mode MODE in a register of class CLASS. */
2047
2048 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2049
2050 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2051 mips_cannot_change_mode_class (FROM, TO, CLASS)
2052 \f
2053 /* Stack layout; function entry, exit and calling. */
2054
2055 #define STACK_GROWS_DOWNWARD
2056
2057 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2058
2059 /* Size of the area allocated in the frame to save the GP. */
2060
2061 #define MIPS_GP_SAVE_AREA_SIZE \
2062 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2063
2064 /* The offset of the first local variable from the frame pointer. See
2065 mips_compute_frame_info for details about the frame layout. */
2066
2067 #define STARTING_FRAME_OFFSET \
2068 (FRAME_GROWS_DOWNWARD \
2069 ? 0 \
2070 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2071
2072 #define RETURN_ADDR_RTX mips_return_addr
2073
2074 /* Mask off the MIPS16 ISA bit in unwind addresses.
2075
2076 The reason for this is a little subtle. When unwinding a call,
2077 we are given the call's return address, which on most targets
2078 is the address of the following instruction. However, what we
2079 actually want to find is the EH region for the call itself.
2080 The target-independent unwind code therefore searches for "RA - 1".
2081
2082 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2083 RA - 1 is therefore the real (even-valued) start of the return
2084 instruction. EH region labels are usually odd-valued MIPS16 symbols
2085 too, so a search for an even address within a MIPS16 region would
2086 usually work.
2087
2088 However, there is an exception. If the end of an EH region is also
2089 the end of a function, the end label is allowed to be even. This is
2090 necessary because a following non-MIPS16 function may also need EH
2091 information for its first instruction.
2092
2093 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2094 non-ISA-encoded address. This probably isn't ideal, but it is
2095 the traditional (legacy) behavior. It is therefore only safe
2096 to search MIPS EH regions for an _odd-valued_ address.
2097
2098 Masking off the ISA bit means that the target-independent code
2099 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2100 #define MASK_RETURN_ADDR GEN_INT (-2)
2101
2102
2103 /* Similarly, don't use the least-significant bit to tell pointers to
2104 code from vtable index. */
2105
2106 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2107
2108 /* The eliminations to $17 are only used for mips16 code. See the
2109 definition of HARD_FRAME_POINTER_REGNUM. */
2110
2111 #define ELIMINABLE_REGS \
2112 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2113 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2114 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2115 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2116 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2117 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2118
2119 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2120 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2121
2122 /* Allocate stack space for arguments at the beginning of each function. */
2123 #define ACCUMULATE_OUTGOING_ARGS 1
2124
2125 /* The argument pointer always points to the first argument. */
2126 #define FIRST_PARM_OFFSET(FNDECL) 0
2127
2128 /* o32 and o64 reserve stack space for all argument registers. */
2129 #define REG_PARM_STACK_SPACE(FNDECL) \
2130 (TARGET_OLDABI \
2131 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2132 : 0)
2133
2134 /* Define this if it is the responsibility of the caller to
2135 allocate the area reserved for arguments passed in registers.
2136 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2137 of this macro is to determine whether the space is included in
2138 `crtl->outgoing_args_size'. */
2139 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2140
2141 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2142 \f
2143 /* Symbolic macros for the registers used to return integer and floating
2144 point values. */
2145
2146 #define GP_RETURN (GP_REG_FIRST + 2)
2147 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2148
2149 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2150
2151 /* Symbolic macros for the first/last argument registers. */
2152
2153 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2154 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2155 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2156 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2157
2158 #define LIBCALL_VALUE(MODE) \
2159 mips_function_value (NULL_TREE, NULL_TREE, MODE)
2160
2161 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2162 mips_function_value (VALTYPE, FUNC, VOIDmode)
2163
2164 /* 1 if N is a possible register number for a function value.
2165 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2166 Currently, R2 and F0 are only implemented here (C has no complex type) */
2167
2168 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2169 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2170 && (N) == FP_RETURN + 2))
2171
2172 /* 1 if N is a possible register number for function argument passing.
2173 We have no FP argument registers when soft-float. When FP registers
2174 are 32 bits, we can't directly reference the odd numbered ones. */
2175
2176 #define FUNCTION_ARG_REGNO_P(N) \
2177 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2178 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2179 && !fixed_regs[N])
2180 \f
2181 /* This structure has to cope with two different argument allocation
2182 schemes. Most MIPS ABIs view the arguments as a structure, of which
2183 the first N words go in registers and the rest go on the stack. If I
2184 < N, the Ith word might go in Ith integer argument register or in a
2185 floating-point register. For these ABIs, we only need to remember
2186 the offset of the current argument into the structure.
2187
2188 The EABI instead allocates the integer and floating-point arguments
2189 separately. The first N words of FP arguments go in FP registers,
2190 the rest go on the stack. Likewise, the first N words of the other
2191 arguments go in integer registers, and the rest go on the stack. We
2192 need to maintain three counts: the number of integer registers used,
2193 the number of floating-point registers used, and the number of words
2194 passed on the stack.
2195
2196 We could keep separate information for the two ABIs (a word count for
2197 the standard ABIs, and three separate counts for the EABI). But it
2198 seems simpler to view the standard ABIs as forms of EABI that do not
2199 allocate floating-point registers.
2200
2201 So for the standard ABIs, the first N words are allocated to integer
2202 registers, and mips_function_arg decides on an argument-by-argument
2203 basis whether that argument should really go in an integer register,
2204 or in a floating-point one. */
2205
2206 typedef struct mips_args {
2207 /* Always true for varargs functions. Otherwise true if at least
2208 one argument has been passed in an integer register. */
2209 int gp_reg_found;
2210
2211 /* The number of arguments seen so far. */
2212 unsigned int arg_number;
2213
2214 /* The number of integer registers used so far. For all ABIs except
2215 EABI, this is the number of words that have been added to the
2216 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2217 unsigned int num_gprs;
2218
2219 /* For EABI, the number of floating-point registers used so far. */
2220 unsigned int num_fprs;
2221
2222 /* The number of words passed on the stack. */
2223 unsigned int stack_words;
2224
2225 /* On the mips16, we need to keep track of which floating point
2226 arguments were passed in general registers, but would have been
2227 passed in the FP regs if this were a 32-bit function, so that we
2228 can move them to the FP regs if we wind up calling a 32-bit
2229 function. We record this information in fp_code, encoded in base
2230 four. A zero digit means no floating point argument, a one digit
2231 means an SFmode argument, and a two digit means a DFmode argument,
2232 and a three digit is not used. The low order digit is the first
2233 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2234 an SFmode argument. ??? A more sophisticated approach will be
2235 needed if MIPS_ABI != ABI_32. */
2236 int fp_code;
2237
2238 /* True if the function has a prototype. */
2239 int prototype;
2240 } CUMULATIVE_ARGS;
2241
2242 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2243 for a call to a function whose data type is FNTYPE.
2244 For a library call, FNTYPE is 0. */
2245
2246 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2247 mips_init_cumulative_args (&CUM, FNTYPE)
2248
2249 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2250 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2251
2252 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2253 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2254
2255 /* True if using EABI and varargs can be passed in floating-point
2256 registers. Under these conditions, we need a more complex form
2257 of va_list, which tracks GPR, FPR and stack arguments separately. */
2258 #define EABI_FLOAT_VARARGS_P \
2259 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2260
2261 \f
2262 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2263
2264 /* Treat LOC as a byte offset from the stack pointer and round it up
2265 to the next fully-aligned offset. */
2266 #define MIPS_STACK_ALIGN(LOC) \
2267 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2268
2269 \f
2270 /* Output assembler code to FILE to increment profiler label # LABELNO
2271 for profiling a function entry. */
2272
2273 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2274
2275 /* The profiler preserves all interesting registers, including $31. */
2276 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2277
2278 /* No mips port has ever used the profiler counter word, so don't emit it
2279 or the label for it. */
2280
2281 #define NO_PROFILE_COUNTERS 1
2282
2283 /* Define this macro if the code for function profiling should come
2284 before the function prologue. Normally, the profiling code comes
2285 after. */
2286
2287 /* #define PROFILE_BEFORE_PROLOGUE */
2288
2289 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2290 the stack pointer does not matter. The value is tested only in
2291 functions that have frame pointers.
2292 No definition is equivalent to always zero. */
2293
2294 #define EXIT_IGNORE_STACK 1
2295
2296 \f
2297 /* Trampolines are a block of code followed by two pointers. */
2298
2299 #define TRAMPOLINE_SIZE \
2300 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2301
2302 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2303 pointers from a single LUI base. */
2304
2305 #define TRAMPOLINE_ALIGNMENT 64
2306
2307 /* mips_trampoline_init calls this library function to flush
2308 program and data caches. */
2309
2310 #ifndef CACHE_FLUSH_FUNC
2311 #define CACHE_FLUSH_FUNC "_flush_cache"
2312 #endif
2313
2314 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2315 /* Flush both caches. We need to flush the data cache in case \
2316 the system has a write-back cache. */ \
2317 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2318 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2319 GEN_INT (3), TYPE_MODE (integer_type_node))
2320
2321 \f
2322 /* Addressing modes, and classification of registers for them. */
2323
2324 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2325 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2326 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2327
2328 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2329 and check its validity for a certain class.
2330 We have two alternate definitions for each of them.
2331 The usual definition accepts all pseudo regs; the other rejects them all.
2332 The symbol REG_OK_STRICT causes the latter definition to be used.
2333
2334 Most source files want to accept pseudo regs in the hope that
2335 they will get allocated to the class that the insn wants them to be in.
2336 Some source files that are used after register allocation
2337 need to be strict. */
2338
2339 #ifndef REG_OK_STRICT
2340 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2341 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2342 #else
2343 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2344 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2345 #endif
2346
2347 #define REG_OK_FOR_INDEX_P(X) 0
2348
2349 \f
2350 /* Maximum number of registers that can appear in a valid memory address. */
2351
2352 #define MAX_REGS_PER_ADDRESS 1
2353
2354 /* Check for constness inline but use mips_legitimate_address_p
2355 to check whether a constant really is an address. */
2356
2357 #define CONSTANT_ADDRESS_P(X) \
2358 (CONSTANT_P (X) && memory_address_p (SImode, X))
2359
2360 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2361
2362 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2363 'the start of the function that this code is output in'. */
2364
2365 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2366 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2367 asm_fprintf ((FILE), "%U%s", \
2368 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2369 else \
2370 asm_fprintf ((FILE), "%U%s", (NAME))
2371 \f
2372 /* Flag to mark a function decl symbol that requires a long call. */
2373 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2374 #define SYMBOL_REF_LONG_CALL_P(X) \
2375 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2376
2377 /* This flag marks functions that cannot be lazily bound. */
2378 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2379 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2380 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2381
2382 /* True if we're generating a form of MIPS16 code in which jump tables
2383 are stored in the text section and encoded as 16-bit PC-relative
2384 offsets. This is only possible when general text loads are allowed,
2385 since the table access itself will be an "lh" instruction. */
2386 /* ??? 16-bit offsets can overflow in large functions. */
2387 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2388
2389 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2390
2391 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2392
2393 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2394
2395 /* Define this as 1 if `char' should by default be signed; else as 0. */
2396 #ifndef DEFAULT_SIGNED_CHAR
2397 #define DEFAULT_SIGNED_CHAR 1
2398 #endif
2399
2400 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2401 we generally don't want to use them for copying arbitrary data.
2402 A single N-word move is usually the same cost as N single-word moves. */
2403 #define MOVE_MAX UNITS_PER_WORD
2404 #define MAX_MOVE_MAX 8
2405
2406 /* Define this macro as a C expression which is nonzero if
2407 accessing less than a word of memory (i.e. a `char' or a
2408 `short') is no faster than accessing a word of memory, i.e., if
2409 such access require more than one instruction or if there is no
2410 difference in cost between byte and (aligned) word loads.
2411
2412 On RISC machines, it tends to generate better code to define
2413 this as 1, since it avoids making a QI or HI mode register.
2414
2415 But, generating word accesses for -mips16 is generally bad as shifts
2416 (often extended) would be needed for byte accesses. */
2417 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2418
2419 /* Standard MIPS integer shifts truncate the shift amount to the
2420 width of the shifted operand. However, Loongson vector shifts
2421 do not truncate the shift amount at all. */
2422 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2423
2424 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2425 is done just by pretending it is already truncated. */
2426 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2427 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2428
2429
2430 /* Specify the machine mode that pointers have.
2431 After generation of rtl, the compiler makes no further distinction
2432 between pointers and any other objects of this machine mode. */
2433
2434 #ifndef Pmode
2435 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2436 #endif
2437
2438 /* Give call MEMs SImode since it is the "most permissive" mode
2439 for both 32-bit and 64-bit targets. */
2440
2441 #define FUNCTION_MODE SImode
2442
2443 \f
2444
2445 /* Define if copies to/from condition code registers should be avoided.
2446
2447 This is needed for the MIPS because reload_outcc is not complete;
2448 it needs to handle cases where the source is a general or another
2449 condition code register. */
2450 #define AVOID_CCMODE_COPIES
2451
2452 /* A C expression for the cost of a branch instruction. A value of
2453 1 is the default; other values are interpreted relative to that. */
2454
2455 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2456 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2457
2458 /* If defined, modifies the length assigned to instruction INSN as a
2459 function of the context in which it is used. LENGTH is an lvalue
2460 that contains the initially computed length of the insn and should
2461 be updated with the correct length of the insn. */
2462 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2463 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2464
2465 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2466 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2467 its operands. */
2468 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2469 "%*" OPCODE "%?\t" OPERANDS "%/"
2470
2471 /* Return an asm string that forces INSN to be treated as an absolute
2472 J or JAL instruction instead of an assembler macro. */
2473 #define MIPS_ABSOLUTE_JUMP(INSN) \
2474 (TARGET_ABICALLS_PIC2 \
2475 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2476 : INSN)
2477
2478 /* Return the asm template for a call. INSN is the instruction's mnemonic
2479 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2480 number of the target. SIZE_OPNO is the operand number of the argument size
2481 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2482 -1 and the call is indirect, use the function symbol from the call
2483 attributes to attach a R_MIPS_JALR relocation to the call.
2484
2485 When generating GOT code without explicit relocation operators,
2486 all calls should use assembly macros. Otherwise, all indirect
2487 calls should use "jr" or "jalr"; we will arrange to restore $gp
2488 afterwards if necessary. Finally, we can only generate direct
2489 calls for -mabicalls by temporarily switching to non-PIC mode. */
2490 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2491 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2492 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2493 : (REG_P (OPERANDS[TARGET_OPNO]) \
2494 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2495 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2496 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2497 : REG_P (OPERANDS[TARGET_OPNO]) \
2498 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2499 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2500 \f
2501 /* Control the assembler format that we output. */
2502
2503 /* Output to assembler file text saying following lines
2504 may contain character constants, extra white space, comments, etc. */
2505
2506 #ifndef ASM_APP_ON
2507 #define ASM_APP_ON " #APP\n"
2508 #endif
2509
2510 /* Output to assembler file text saying following lines
2511 no longer contain unusual constructs. */
2512
2513 #ifndef ASM_APP_OFF
2514 #define ASM_APP_OFF " #NO_APP\n"
2515 #endif
2516
2517 #define REGISTER_NAMES \
2518 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2519 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2520 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2521 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2522 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2523 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2524 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2525 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2526 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2527 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2528 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2529 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2530 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2531 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2532 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2533 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2534 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2535 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2536 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2537 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2538 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2539 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2540 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2541 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2542
2543 /* List the "software" names for each register. Also list the numerical
2544 names for $fp and $sp. */
2545
2546 #define ADDITIONAL_REGISTER_NAMES \
2547 { \
2548 { "$29", 29 + GP_REG_FIRST }, \
2549 { "$30", 30 + GP_REG_FIRST }, \
2550 { "at", 1 + GP_REG_FIRST }, \
2551 { "v0", 2 + GP_REG_FIRST }, \
2552 { "v1", 3 + GP_REG_FIRST }, \
2553 { "a0", 4 + GP_REG_FIRST }, \
2554 { "a1", 5 + GP_REG_FIRST }, \
2555 { "a2", 6 + GP_REG_FIRST }, \
2556 { "a3", 7 + GP_REG_FIRST }, \
2557 { "t0", 8 + GP_REG_FIRST }, \
2558 { "t1", 9 + GP_REG_FIRST }, \
2559 { "t2", 10 + GP_REG_FIRST }, \
2560 { "t3", 11 + GP_REG_FIRST }, \
2561 { "t4", 12 + GP_REG_FIRST }, \
2562 { "t5", 13 + GP_REG_FIRST }, \
2563 { "t6", 14 + GP_REG_FIRST }, \
2564 { "t7", 15 + GP_REG_FIRST }, \
2565 { "s0", 16 + GP_REG_FIRST }, \
2566 { "s1", 17 + GP_REG_FIRST }, \
2567 { "s2", 18 + GP_REG_FIRST }, \
2568 { "s3", 19 + GP_REG_FIRST }, \
2569 { "s4", 20 + GP_REG_FIRST }, \
2570 { "s5", 21 + GP_REG_FIRST }, \
2571 { "s6", 22 + GP_REG_FIRST }, \
2572 { "s7", 23 + GP_REG_FIRST }, \
2573 { "t8", 24 + GP_REG_FIRST }, \
2574 { "t9", 25 + GP_REG_FIRST }, \
2575 { "k0", 26 + GP_REG_FIRST }, \
2576 { "k1", 27 + GP_REG_FIRST }, \
2577 { "gp", 28 + GP_REG_FIRST }, \
2578 { "sp", 29 + GP_REG_FIRST }, \
2579 { "fp", 30 + GP_REG_FIRST }, \
2580 { "ra", 31 + GP_REG_FIRST }, \
2581 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2582 }
2583
2584 /* This is meant to be redefined in the host dependent files. It is a
2585 set of alternative names and regnums for mips coprocessors. */
2586
2587 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2588
2589 #define DBR_OUTPUT_SEQEND(STREAM) \
2590 do \
2591 { \
2592 /* Undo the effect of '%*'. */ \
2593 mips_pop_asm_switch (&mips_nomacro); \
2594 mips_pop_asm_switch (&mips_noreorder); \
2595 /* Emit a blank line after the delay slot for emphasis. */ \
2596 fputs ("\n", STREAM); \
2597 } \
2598 while (0)
2599
2600 /* mips-tfile does not understand .stabd directives. */
2601 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2602 dbxout_begin_stabn_sline (LINE); \
2603 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2604 } while (0)
2605
2606 /* Use .loc directives for SDB line numbers. */
2607 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2608 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2609
2610 /* The MIPS implementation uses some labels for its own purpose. The
2611 following lists what labels are created, and are all formed by the
2612 pattern $L[a-z].*. The machine independent portion of GCC creates
2613 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2614
2615 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2616 $Lb[0-9]+ Begin blocks for MIPS debug support
2617 $Lc[0-9]+ Label for use in s<xx> operation.
2618 $Le[0-9]+ End blocks for MIPS debug support */
2619
2620 #undef ASM_DECLARE_OBJECT_NAME
2621 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2622 mips_declare_object (STREAM, NAME, "", ":\n")
2623
2624 /* Globalizing directive for a label. */
2625 #define GLOBAL_ASM_OP "\t.globl\t"
2626
2627 /* This says how to define a global common symbol. */
2628
2629 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2630
2631 /* This says how to define a local common symbol (i.e., not visible to
2632 linker). */
2633
2634 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2635 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2636 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2637 #endif
2638
2639 /* This says how to output an external. It would be possible not to
2640 output anything and let undefined symbol become external. However
2641 the assembler uses length information on externals to allocate in
2642 data/sdata bss/sbss, thereby saving exec time. */
2643
2644 #undef ASM_OUTPUT_EXTERNAL
2645 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2646 mips_output_external(STREAM,DECL,NAME)
2647
2648 /* This is how to declare a function name. The actual work of
2649 emitting the label is moved to function_prologue, so that we can
2650 get the line number correctly emitted before the .ent directive,
2651 and after any .file directives. Define as empty so that the function
2652 is not declared before the .ent directive elsewhere. */
2653
2654 #undef ASM_DECLARE_FUNCTION_NAME
2655 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2656
2657 /* This is how to store into the string LABEL
2658 the symbol_ref name of an internal numbered label where
2659 PREFIX is the class of label and NUM is the number within the class.
2660 This is suitable for output with `assemble_name'. */
2661
2662 #undef ASM_GENERATE_INTERNAL_LABEL
2663 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2664 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2665
2666 /* Print debug labels as "foo = ." rather than "foo:" because they should
2667 represent a byte pointer rather than an ISA-encoded address. This is
2668 particularly important for code like:
2669
2670 $LFBxxx = .
2671 .cfi_startproc
2672 ...
2673 .section .gcc_except_table,...
2674 ...
2675 .uleb128 foo-$LFBxxx
2676
2677 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2678 likewise a byte pointer rather than an ISA-encoded address.
2679
2680 At the time of writing, this hook is not used for the function end
2681 label:
2682
2683 $LFExxx:
2684 .end foo
2685
2686 But this doesn't matter, because GAS doesn't treat a pre-.end label
2687 as a MIPS16 one anyway. */
2688
2689 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2690 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2691
2692 /* This is how to output an element of a case-vector that is absolute. */
2693
2694 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2695 fprintf (STREAM, "\t%s\t%sL%d\n", \
2696 ptr_mode == DImode ? ".dword" : ".word", \
2697 LOCAL_LABEL_PREFIX, \
2698 VALUE)
2699
2700 /* This is how to output an element of a case-vector. We can make the
2701 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2702 is supported. */
2703
2704 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2705 do { \
2706 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2707 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2708 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2709 else if (TARGET_GPWORD) \
2710 fprintf (STREAM, "\t%s\t%sL%d\n", \
2711 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2712 LOCAL_LABEL_PREFIX, VALUE); \
2713 else if (TARGET_RTP_PIC) \
2714 { \
2715 /* Make the entry relative to the start of the function. */ \
2716 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2717 fprintf (STREAM, "\t%s\t%sL%d-", \
2718 Pmode == DImode ? ".dword" : ".word", \
2719 LOCAL_LABEL_PREFIX, VALUE); \
2720 assemble_name (STREAM, XSTR (fnsym, 0)); \
2721 fprintf (STREAM, "\n"); \
2722 } \
2723 else \
2724 fprintf (STREAM, "\t%s\t%sL%d\n", \
2725 ptr_mode == DImode ? ".dword" : ".word", \
2726 LOCAL_LABEL_PREFIX, VALUE); \
2727 } while (0)
2728
2729 /* This is how to output an assembler line
2730 that says to advance the location counter
2731 to a multiple of 2**LOG bytes. */
2732
2733 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2734 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2735
2736 /* This is how to output an assembler line to advance the location
2737 counter by SIZE bytes. */
2738
2739 #undef ASM_OUTPUT_SKIP
2740 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2741 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2742
2743 /* This is how to output a string. */
2744 #undef ASM_OUTPUT_ASCII
2745 #define ASM_OUTPUT_ASCII mips_output_ascii
2746
2747 /* Output #ident as a in the read-only data section. */
2748 #undef ASM_OUTPUT_IDENT
2749 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2750 { \
2751 const char *p = STRING; \
2752 int size = strlen (p) + 1; \
2753 switch_to_section (readonly_data_section); \
2754 assemble_string (p, size); \
2755 }
2756 \f
2757 /* Default to -G 8 */
2758 #ifndef MIPS_DEFAULT_GVALUE
2759 #define MIPS_DEFAULT_GVALUE 8
2760 #endif
2761
2762 /* Define the strings to put out for each section in the object file. */
2763 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2764 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2765
2766 #undef READONLY_DATA_SECTION_ASM_OP
2767 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2768 \f
2769 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2770 do \
2771 { \
2772 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2773 TARGET_64BIT ? "daddiu" : "addiu", \
2774 reg_names[STACK_POINTER_REGNUM], \
2775 reg_names[STACK_POINTER_REGNUM], \
2776 TARGET_64BIT ? "sd" : "sw", \
2777 reg_names[REGNO], \
2778 reg_names[STACK_POINTER_REGNUM]); \
2779 } \
2780 while (0)
2781
2782 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2783 do \
2784 { \
2785 mips_push_asm_switch (&mips_noreorder); \
2786 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2787 TARGET_64BIT ? "ld" : "lw", \
2788 reg_names[REGNO], \
2789 reg_names[STACK_POINTER_REGNUM], \
2790 TARGET_64BIT ? "daddu" : "addu", \
2791 reg_names[STACK_POINTER_REGNUM], \
2792 reg_names[STACK_POINTER_REGNUM]); \
2793 mips_pop_asm_switch (&mips_noreorder); \
2794 } \
2795 while (0)
2796
2797 /* How to start an assembler comment.
2798 The leading space is important (the mips native assembler requires it). */
2799 #ifndef ASM_COMMENT_START
2800 #define ASM_COMMENT_START " #"
2801 #endif
2802 \f
2803 #undef SIZE_TYPE
2804 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2805
2806 #undef PTRDIFF_TYPE
2807 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2808
2809 /* The maximum number of bytes that can be copied by one iteration of
2810 a movmemsi loop; see mips_block_move_loop. */
2811 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2812 (UNITS_PER_WORD * 4)
2813
2814 /* The maximum number of bytes that can be copied by a straight-line
2815 implementation of movmemsi; see mips_block_move_straight. We want
2816 to make sure that any loop-based implementation will iterate at
2817 least twice. */
2818 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2819 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2820
2821 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2822 values were determined experimentally by benchmarking with CSiBE.
2823 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2824 for o32 where we have to restore $gp afterwards as well as make an
2825 indirect call), but in practice, bumping this up higher for
2826 TARGET_ABICALLS doesn't make much difference to code size. */
2827
2828 #define MIPS_CALL_RATIO 8
2829
2830 /* Any loop-based implementation of movmemsi will have at least
2831 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2832 moves, so allow individual copies of fewer elements.
2833
2834 When movmemsi is not available, use a value approximating
2835 the length of a memcpy call sequence, so that move_by_pieces
2836 will generate inline code if it is shorter than a function call.
2837 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2838 we'll have to generate a load/store pair for each, halve the
2839 value of MIPS_CALL_RATIO to take that into account. */
2840
2841 #define MOVE_RATIO(speed) \
2842 (HAVE_movmemsi \
2843 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2844 : MIPS_CALL_RATIO / 2)
2845
2846 /* movmemsi is meant to generate code that is at least as good as
2847 move_by_pieces. However, movmemsi effectively uses a by-pieces
2848 implementation both for moves smaller than a word and for word-aligned
2849 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
2850 allow the tree-level optimisers to do such moves by pieces, as it
2851 often exposes other optimization opportunities. We might as well
2852 continue to use movmemsi at the rtl level though, as it produces
2853 better code when scheduling is disabled (such as at -O). */
2854
2855 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2856 (HAVE_movmemsi \
2857 ? (!currently_expanding_to_rtl \
2858 && ((ALIGN) < BITS_PER_WORD \
2859 ? (SIZE) < UNITS_PER_WORD \
2860 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
2861 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2862 < (unsigned int) MOVE_RATIO (false)))
2863
2864 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2865 of the length of a memset call, but use the default otherwise. */
2866
2867 #define CLEAR_RATIO(speed)\
2868 ((speed) ? 15 : MIPS_CALL_RATIO)
2869
2870 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2871 optimizing for size adjust the ratio to account for the overhead of
2872 loading the constant and replicating it across the word. */
2873
2874 #define SET_RATIO(speed) \
2875 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2876
2877 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2878 in that case each word takes 3 insns (lui, ori, sw), or more in
2879 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2880 and let the move_by_pieces code copy the string from read-only
2881 memory. In the future, this could be tuned further for multi-issue
2882 CPUs that can issue stores down one pipe and arithmetic instructions
2883 down another; in that case, the lui/ori/sw combination would be a
2884 win for long enough strings. */
2885
2886 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2887 \f
2888 #ifndef __mips16
2889 /* Since the bits of the _init and _fini function is spread across
2890 many object files, each potentially with its own GP, we must assume
2891 we need to load our GP. We don't preserve $gp or $ra, since each
2892 init/fini chunk is supposed to initialize $gp, and crti/crtn
2893 already take care of preserving $ra and, when appropriate, $gp. */
2894 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2895 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2896 asm (SECTION_OP "\n\
2897 .set noreorder\n\
2898 bal 1f\n\
2899 nop\n\
2900 1: .cpload $31\n\
2901 .set reorder\n\
2902 jal " USER_LABEL_PREFIX #FUNC "\n\
2903 " TEXT_SECTION_ASM_OP);
2904 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2905 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2906 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2907 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2908 asm (SECTION_OP "\n\
2909 .set noreorder\n\
2910 bal 1f\n\
2911 nop\n\
2912 1: .set reorder\n\
2913 .cpsetup $31, $2, 1b\n\
2914 jal " USER_LABEL_PREFIX #FUNC "\n\
2915 " TEXT_SECTION_ASM_OP);
2916 #endif
2917 #endif
2918
2919 #ifndef HAVE_AS_TLS
2920 #define HAVE_AS_TLS 0
2921 #endif
2922
2923 #ifndef USED_FOR_TARGET
2924 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2925 struct mips_asm_switch {
2926 /* The FOO in the description above. */
2927 const char *name;
2928
2929 /* The current block nesting level, or 0 if we aren't in a block. */
2930 int nesting_level;
2931 };
2932
2933 extern const enum reg_class mips_regno_to_class[];
2934 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2935 extern const char *current_function_file; /* filename current function is in */
2936 extern int num_source_filenames; /* current .file # */
2937 extern struct mips_asm_switch mips_noreorder;
2938 extern struct mips_asm_switch mips_nomacro;
2939 extern struct mips_asm_switch mips_noat;
2940 extern int mips_dbx_regno[];
2941 extern int mips_dwarf_regno[];
2942 extern bool mips_split_p[];
2943 extern bool mips_split_hi_p[];
2944 extern enum processor mips_arch; /* which cpu to codegen for */
2945 extern enum processor mips_tune; /* which cpu to schedule for */
2946 extern int mips_isa; /* architectural level */
2947 extern int mips_abi; /* which ABI to use */
2948 extern const struct mips_cpu_info *mips_arch_info;
2949 extern const struct mips_cpu_info *mips_tune_info;
2950 extern bool mips_base_mips16;
2951 extern enum mips_code_readable_setting mips_code_readable;
2952 extern GTY(()) struct target_globals *mips16_globals;
2953 #endif
2954
2955 /* Enable querying of DFA units. */
2956 #define CPU_UNITS_QUERY 1
2957
2958 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2959 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2960
2961 /* As on most targets, we want the .eh_frame section to be read-only where
2962 possible. And as on most targets, this means two things:
2963
2964 (a) Non-locally-binding pointers must have an indirect encoding,
2965 so that the addresses in the .eh_frame section itself become
2966 locally-binding.
2967
2968 (b) A shared library's .eh_frame section must encode locally-binding
2969 pointers in a relative (relocation-free) form.
2970
2971 However, MIPS has traditionally not allowed directives like:
2972
2973 .long x-.
2974
2975 in cases where "x" is in a different section, or is not defined in the
2976 same assembly file. We are therefore unable to emit the PC-relative
2977 form required by (b) at assembly time.
2978
2979 Fortunately, the linker is able to convert absolute addresses into
2980 PC-relative addresses on our behalf. Unfortunately, only certain
2981 versions of the linker know how to do this for indirect pointers,
2982 and for personality data. We must fall back on using writable
2983 .eh_frame sections for shared libraries if the linker does not
2984 support this feature. */
2985 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2986 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2987
2988 /* For switching between MIPS16 and non-MIPS16 modes. */
2989 #define SWITCHABLE_TARGET 1