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Add support for the MIPS -mxpa command line option.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS64 (mips_isa == 64)
212 #define ISA_MIPS64R2 (mips_isa == 65)
213
214 /* Architecture target defines. */
215 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
216 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
217 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
218 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
219 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
220 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
221 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
222 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
223 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
224 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
225 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
226 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
227 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
228 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
229 || mips_arch == PROCESSOR_OCTEON2)
230 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
231 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
232 || mips_arch == PROCESSOR_SB1A)
233 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
234 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
235
236 /* Scheduling target defines. */
237 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
238 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
239 || mips_tune == PROCESSOR_24KF2_1 \
240 || mips_tune == PROCESSOR_24KF1_1)
241 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
242 || mips_tune == PROCESSOR_74KF2_1 \
243 || mips_tune == PROCESSOR_74KF1_1 \
244 || mips_tune == PROCESSOR_74KF3_2)
245 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
246 || mips_tune == PROCESSOR_LOONGSON_2F)
247 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
248 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
249 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
250 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
251 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
252 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
253 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
254 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
255 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
256 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
257 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
258 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
259 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
260 || mips_tune == PROCESSOR_OCTEON2)
261 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
262 || mips_tune == PROCESSOR_SB1A)
263
264 /* Whether vector modes and intrinsics for ST Microelectronics
265 Loongson-2E/2F processors should be enabled. In o32 pairs of
266 floating-point registers provide 64-bit values. */
267 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
268 && (TARGET_LOONGSON_2EF \
269 || TARGET_LOONGSON_3A))
270
271 /* True if the pre-reload scheduler should try to create chains of
272 multiply-add or multiply-subtract instructions. For example,
273 suppose we have:
274
275 t1 = a * b
276 t2 = t1 + c * d
277 t3 = e * f
278 t4 = t3 - g * h
279
280 t1 will have a higher priority than t2 and t3 will have a higher
281 priority than t4. However, before reload, there is no dependence
282 between t1 and t3, and they can often have similar priorities.
283 The scheduler will then tend to prefer:
284
285 t1 = a * b
286 t3 = e * f
287 t2 = t1 + c * d
288 t4 = t3 - g * h
289
290 which stops us from making full use of macc/madd-style instructions.
291 This sort of situation occurs frequently in Fourier transforms and
292 in unrolled loops.
293
294 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
295 queue so that chained multiply-add and multiply-subtract instructions
296 appear ahead of any other instruction that is likely to clobber lo.
297 In the example above, if t2 and t3 become ready at the same time,
298 the code ensures that t2 is scheduled first.
299
300 Multiply-accumulate instructions are a bigger win for some targets
301 than others, so this macro is defined on an opt-in basis. */
302 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
303 || TUNE_MIPS4120 \
304 || TUNE_MIPS4130 \
305 || TUNE_24K)
306
307 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
308 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
309
310 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
311 directly accessible, while the command-line options select
312 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
313 in use. */
314 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
315 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
316
317 /* False if SC acts as a memory barrier with respect to itself,
318 otherwise a SYNC will be emitted after SC for atomic operations
319 that require ordering between the SC and following loads and
320 stores. It does not tell anything about ordering of loads and
321 stores prior to and following the SC, only about the SC itself and
322 those loads and stores follow it. */
323 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
324
325 /* Define preprocessor macros for the -march and -mtune options.
326 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
327 processor. If INFO's canonical name is "foo", define PREFIX to
328 be "foo", and define an additional macro PREFIX_FOO. */
329 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
330 do \
331 { \
332 char *macro, *p; \
333 \
334 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
335 for (p = macro; *p != 0; p++) \
336 if (*p == '+') \
337 *p = 'P'; \
338 else \
339 *p = TOUPPER (*p); \
340 \
341 builtin_define (macro); \
342 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
343 free (macro); \
344 } \
345 while (0)
346
347 /* Target CPU builtins. */
348 #define TARGET_CPU_CPP_BUILTINS() \
349 do \
350 { \
351 builtin_assert ("machine=mips"); \
352 builtin_assert ("cpu=mips"); \
353 builtin_define ("__mips__"); \
354 builtin_define ("_mips"); \
355 \
356 /* We do this here because __mips is defined below and so we \
357 can't use builtin_define_std. We don't ever want to define \
358 "mips" for VxWorks because some of the VxWorks headers \
359 construct include filenames from a root directory macro, \
360 an architecture macro and a filename, where the architecture \
361 macro expands to 'mips'. If we define 'mips' to 1, the \
362 architecture macro expands to 1 as well. */ \
363 if (!flag_iso && !TARGET_VXWORKS) \
364 builtin_define ("mips"); \
365 \
366 if (TARGET_64BIT) \
367 builtin_define ("__mips64"); \
368 \
369 /* Treat _R3000 and _R4000 like register-size \
370 defines, which is how they've historically \
371 been used. */ \
372 if (TARGET_64BIT) \
373 { \
374 builtin_define_std ("R4000"); \
375 builtin_define ("_R4000"); \
376 } \
377 else \
378 { \
379 builtin_define_std ("R3000"); \
380 builtin_define ("_R3000"); \
381 } \
382 \
383 if (TARGET_FLOAT64) \
384 builtin_define ("__mips_fpr=64"); \
385 else \
386 builtin_define ("__mips_fpr=32"); \
387 \
388 if (mips_base_compression_flags & MASK_MIPS16) \
389 builtin_define ("__mips16"); \
390 \
391 if (TARGET_MIPS3D) \
392 builtin_define ("__mips3d"); \
393 \
394 if (TARGET_SMARTMIPS) \
395 builtin_define ("__mips_smartmips"); \
396 \
397 if (mips_base_compression_flags & MASK_MICROMIPS) \
398 builtin_define ("__mips_micromips"); \
399 \
400 if (TARGET_MCU) \
401 builtin_define ("__mips_mcu"); \
402 \
403 if (TARGET_EVA) \
404 builtin_define ("__mips_eva"); \
405 \
406 if (TARGET_DSP) \
407 { \
408 builtin_define ("__mips_dsp"); \
409 if (TARGET_DSPR2) \
410 { \
411 builtin_define ("__mips_dspr2"); \
412 builtin_define ("__mips_dsp_rev=2"); \
413 } \
414 else \
415 builtin_define ("__mips_dsp_rev=1"); \
416 } \
417 \
418 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
419 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
420 \
421 if (ISA_MIPS1) \
422 { \
423 builtin_define ("__mips=1"); \
424 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
425 } \
426 else if (ISA_MIPS2) \
427 { \
428 builtin_define ("__mips=2"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
430 } \
431 else if (ISA_MIPS3) \
432 { \
433 builtin_define ("__mips=3"); \
434 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
435 } \
436 else if (ISA_MIPS4) \
437 { \
438 builtin_define ("__mips=4"); \
439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
440 } \
441 else if (ISA_MIPS32) \
442 { \
443 builtin_define ("__mips=32"); \
444 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
445 } \
446 else if (ISA_MIPS32R2) \
447 { \
448 builtin_define ("__mips=32"); \
449 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
450 } \
451 else if (ISA_MIPS64) \
452 { \
453 builtin_define ("__mips=64"); \
454 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
455 } \
456 else if (ISA_MIPS64R2) \
457 { \
458 builtin_define ("__mips=64"); \
459 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
460 } \
461 if (mips_isa_rev > 0) \
462 builtin_define_with_int_value ("__mips_isa_rev", \
463 mips_isa_rev); \
464 \
465 switch (mips_abi) \
466 { \
467 case ABI_32: \
468 builtin_define ("_ABIO32=1"); \
469 builtin_define ("_MIPS_SIM=_ABIO32"); \
470 break; \
471 \
472 case ABI_N32: \
473 builtin_define ("_ABIN32=2"); \
474 builtin_define ("_MIPS_SIM=_ABIN32"); \
475 break; \
476 \
477 case ABI_64: \
478 builtin_define ("_ABI64=3"); \
479 builtin_define ("_MIPS_SIM=_ABI64"); \
480 break; \
481 \
482 case ABI_O64: \
483 builtin_define ("_ABIO64=4"); \
484 builtin_define ("_MIPS_SIM=_ABIO64"); \
485 break; \
486 } \
487 \
488 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
489 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
490 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
491 builtin_define_with_int_value ("_MIPS_FPSET", \
492 32 / MAX_FPRS_PER_FMT); \
493 \
494 /* These defines reflect the ABI in use, not whether the \
495 FPU is directly accessible. */ \
496 if (TARGET_NO_FLOAT) \
497 builtin_define ("__mips_no_float"); \
498 else if (TARGET_HARD_FLOAT_ABI) \
499 builtin_define ("__mips_hard_float"); \
500 else \
501 builtin_define ("__mips_soft_float"); \
502 \
503 if (TARGET_SINGLE_FLOAT) \
504 builtin_define ("__mips_single_float"); \
505 \
506 if (TARGET_PAIRED_SINGLE_FLOAT) \
507 builtin_define ("__mips_paired_single_float"); \
508 \
509 if (mips_abs == MIPS_IEEE_754_2008) \
510 builtin_define ("__mips_abs2008"); \
511 \
512 if (mips_nan == MIPS_IEEE_754_2008) \
513 builtin_define ("__mips_nan2008"); \
514 \
515 if (TARGET_BIG_ENDIAN) \
516 { \
517 builtin_define_std ("MIPSEB"); \
518 builtin_define ("_MIPSEB"); \
519 } \
520 else \
521 { \
522 builtin_define_std ("MIPSEL"); \
523 builtin_define ("_MIPSEL"); \
524 } \
525 \
526 /* Whether calls should go through $25. The separate __PIC__ \
527 macro indicates whether abicalls code might use a GOT. */ \
528 if (TARGET_ABICALLS) \
529 builtin_define ("__mips_abicalls"); \
530 \
531 /* Whether Loongson vector modes are enabled. */ \
532 if (TARGET_LOONGSON_VECTORS) \
533 builtin_define ("__mips_loongson_vector_rev"); \
534 \
535 /* Historical Octeon macro. */ \
536 if (TARGET_OCTEON) \
537 builtin_define ("__OCTEON__"); \
538 \
539 if (TARGET_SYNCI) \
540 builtin_define ("__mips_synci"); \
541 \
542 /* Macros dependent on the C dialect. */ \
543 if (preprocessing_asm_p ()) \
544 { \
545 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
546 builtin_define ("_LANGUAGE_ASSEMBLY"); \
547 } \
548 else if (c_dialect_cxx ()) \
549 { \
550 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
551 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
552 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
553 } \
554 else \
555 { \
556 builtin_define_std ("LANGUAGE_C"); \
557 builtin_define ("_LANGUAGE_C"); \
558 } \
559 if (c_dialect_objc ()) \
560 { \
561 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
562 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
563 /* Bizarre, but retained for backwards compatibility. */ \
564 builtin_define_std ("LANGUAGE_C"); \
565 builtin_define ("_LANGUAGE_C"); \
566 } \
567 \
568 if (mips_abi == ABI_EABI) \
569 builtin_define ("__mips_eabi"); \
570 \
571 if (TARGET_CACHE_BUILTIN) \
572 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
573 } \
574 while (0)
575
576 /* Default target_flags if no switches are specified */
577
578 #ifndef TARGET_DEFAULT
579 #define TARGET_DEFAULT 0
580 #endif
581
582 #ifndef TARGET_CPU_DEFAULT
583 #define TARGET_CPU_DEFAULT 0
584 #endif
585
586 #ifndef TARGET_ENDIAN_DEFAULT
587 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
588 #endif
589
590 #ifdef IN_LIBGCC2
591 #undef TARGET_64BIT
592 /* Make this compile time constant for libgcc2 */
593 #ifdef __mips64
594 #define TARGET_64BIT 1
595 #else
596 #define TARGET_64BIT 0
597 #endif
598 #endif /* IN_LIBGCC2 */
599
600 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
601 when compiled with hardware floating point. This is because MIPS16
602 code cannot save and restore the floating-point registers, which is
603 important if in a mixed MIPS16/non-MIPS16 environment. */
604
605 #ifdef IN_LIBGCC2
606 #if __mips_hard_float
607 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
608 #endif
609 #endif /* IN_LIBGCC2 */
610
611 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
612
613 #ifndef MULTILIB_ENDIAN_DEFAULT
614 #if TARGET_ENDIAN_DEFAULT == 0
615 #define MULTILIB_ENDIAN_DEFAULT "EL"
616 #else
617 #define MULTILIB_ENDIAN_DEFAULT "EB"
618 #endif
619 #endif
620
621 #ifndef MULTILIB_ISA_DEFAULT
622 #if MIPS_ISA_DEFAULT == 1
623 #define MULTILIB_ISA_DEFAULT "mips1"
624 #elif MIPS_ISA_DEFAULT == 2
625 #define MULTILIB_ISA_DEFAULT "mips2"
626 #elif MIPS_ISA_DEFAULT == 3
627 #define MULTILIB_ISA_DEFAULT "mips3"
628 #elif MIPS_ISA_DEFAULT == 4
629 #define MULTILIB_ISA_DEFAULT "mips4"
630 #elif MIPS_ISA_DEFAULT == 32
631 #define MULTILIB_ISA_DEFAULT "mips32"
632 #elif MIPS_ISA_DEFAULT == 33
633 #define MULTILIB_ISA_DEFAULT "mips32r2"
634 #elif MIPS_ISA_DEFAULT == 64
635 #define MULTILIB_ISA_DEFAULT "mips64"
636 #elif MIPS_ISA_DEFAULT == 65
637 #define MULTILIB_ISA_DEFAULT "mips64r2"
638 #else
639 #define MULTILIB_ISA_DEFAULT "mips1"
640 #endif
641 #endif
642
643 #ifndef MIPS_ABI_DEFAULT
644 #define MIPS_ABI_DEFAULT ABI_32
645 #endif
646
647 /* Use the most portable ABI flag for the ASM specs. */
648
649 #if MIPS_ABI_DEFAULT == ABI_32
650 #define MULTILIB_ABI_DEFAULT "mabi=32"
651 #elif MIPS_ABI_DEFAULT == ABI_O64
652 #define MULTILIB_ABI_DEFAULT "mabi=o64"
653 #elif MIPS_ABI_DEFAULT == ABI_N32
654 #define MULTILIB_ABI_DEFAULT "mabi=n32"
655 #elif MIPS_ABI_DEFAULT == ABI_64
656 #define MULTILIB_ABI_DEFAULT "mabi=64"
657 #elif MIPS_ABI_DEFAULT == ABI_EABI
658 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
659 #endif
660
661 #ifndef MULTILIB_DEFAULTS
662 #define MULTILIB_DEFAULTS \
663 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
664 #endif
665
666 /* We must pass -EL to the linker by default for little endian embedded
667 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
668 linker will default to using big-endian output files. The OUTPUT_FORMAT
669 line must be in the linker script, otherwise -EB/-EL will not work. */
670
671 #ifndef ENDIAN_SPEC
672 #if TARGET_ENDIAN_DEFAULT == 0
673 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
674 #else
675 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
676 #endif
677 #endif
678
679 /* A spec condition that matches all non-mips16 -mips arguments. */
680
681 #define MIPS_ISA_LEVEL_OPTION_SPEC \
682 "mips1|mips2|mips3|mips4|mips32*|mips64*"
683
684 /* A spec condition that matches all non-mips16 architecture arguments. */
685
686 #define MIPS_ARCH_OPTION_SPEC \
687 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
688
689 /* A spec that infers a -mips argument from an -march argument,
690 or injects the default if no architecture is specified. */
691
692 #define MIPS_ISA_LEVEL_SPEC \
693 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
694 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
695 %{march=mips2|march=r6000:-mips2} \
696 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
697 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
698 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
699 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
700 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
701 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
702 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
703 |march=xlr: -mips64} \
704 %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
705 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
706
707 /* A spec that infers a -mhard-float or -msoft-float setting from an
708 -march argument. Note that soft-float and hard-float code are not
709 link-compatible. */
710
711 #define MIPS_ARCH_FLOAT_SPEC \
712 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
713 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
714 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
715 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
716 march=*: -mhard-float}"
717
718 /* A spec condition that matches 32-bit options. It only works if
719 MIPS_ISA_LEVEL_SPEC has been applied. */
720
721 #define MIPS_32BIT_OPTION_SPEC \
722 "mips1|mips2|mips32*|mgp32"
723
724 /* Infer a -msynci setting from a -mips argument, on the assumption that
725 -msynci is desired where possible. */
726 #define MIPS_ISA_SYNCI_SPEC \
727 "%{msynci|mno-synci:;:%{mips32r2|mips64r2:-msynci;:-mno-synci}}"
728
729 #if (MIPS_ABI_DEFAULT == ABI_O64 \
730 || MIPS_ABI_DEFAULT == ABI_N32 \
731 || MIPS_ABI_DEFAULT == ABI_64)
732 #define OPT_ARCH64 "mabi=32|mgp32:;"
733 #define OPT_ARCH32 "mabi=32|mgp32"
734 #else
735 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
736 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
737 #endif
738
739 /* Support for a compile-time default CPU, et cetera. The rules are:
740 --with-arch is ignored if -march is specified or a -mips is specified
741 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
742 --with-tune is ignored if -mtune is specified; likewise
743 --with-tune-32 and --with-tune-64.
744 --with-abi is ignored if -mabi is specified.
745 --with-float is ignored if -mhard-float or -msoft-float are
746 specified.
747 --with-nan is ignored if -mnan is specified.
748 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
749 specified. */
750 #define OPTION_DEFAULT_SPECS \
751 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
752 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
753 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
754 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
755 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
756 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
757 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
758 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
759 {"fpu", "%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}" }, \
760 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
761 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
762 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
763 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
764 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
765
766 /* A spec that infers the -mdsp setting from an -march argument. */
767 #define BASE_DRIVER_SELF_SPECS \
768 "%{!mno-dsp: \
769 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
770 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
771
772 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
773
774 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
775 && ISA_HAS_COND_TRAP)
776
777 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
778
779 /* True if the ABI can only work with 64-bit integer registers. We
780 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
781 otherwise floating-point registers must also be 64-bit. */
782 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
783
784 /* Likewise for 32-bit regs. */
785 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
786
787 /* True if the file format uses 64-bit symbols. At present, this is
788 only true for n64, which uses 64-bit ELF. */
789 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
790
791 /* True if symbols are 64 bits wide. This is usually determined by
792 the ABI's file format, but it can be overridden by -msym32. Note that
793 overriding the size with -msym32 changes the ABI of relocatable objects,
794 although it doesn't change the ABI of a fully-linked object. */
795 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
796 && Pmode == DImode \
797 && !TARGET_SYM32)
798
799 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
800 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
801 || ISA_MIPS4 \
802 || ISA_MIPS64 \
803 || ISA_MIPS64R2)
804
805 /* ISA has branch likely instructions (e.g. mips2). */
806 /* Disable branchlikely for tx39 until compare rewrite. They haven't
807 been generated up to this point. */
808 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
809
810 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
811 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
812 || TARGET_MIPS5400 \
813 || TARGET_MIPS5500 \
814 || TARGET_MIPS5900 \
815 || TARGET_MIPS7000 \
816 || TARGET_MIPS9000 \
817 || TARGET_MAD \
818 || mips_isa_rev >= 1) \
819 && !TARGET_MIPS16)
820
821 /* ISA has a three-operand multiplication instruction. */
822 #define ISA_HAS_DMUL3 (TARGET_64BIT \
823 && TARGET_OCTEON \
824 && !TARGET_MIPS16)
825
826 /* ISA supports instructions DMULT and DMULTU. */
827 #define ISA_HAS_DMULT (TARGET_64BIT && !TARGET_MIPS5900)
828
829 /* ISA supports instructions MULT and MULTU.
830 This is always true, but the macro is needed for ISA_HAS_<D>MULT
831 in mips.md. */
832 #define ISA_HAS_MULT (1)
833
834 /* ISA supports instructions DDIV and DDIVU. */
835 #define ISA_HAS_DDIV (TARGET_64BIT && !TARGET_MIPS5900)
836
837 /* ISA supports instructions DIV and DIVU.
838 This is always true, but the macro is needed for ISA_HAS_<D>DIV
839 in mips.md. */
840 #define ISA_HAS_DIV (1)
841
842 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
843 || TARGET_LOONGSON_3A) \
844 && !TARGET_MIPS16)
845
846 /* ISA has the floating-point conditional move instructions introduced
847 in mips4. */
848 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
849 || mips_isa_rev >= 1) \
850 && !TARGET_MIPS5500 \
851 && !TARGET_MIPS16)
852
853 /* ISA has the integer conditional move instructions introduced in mips4 and
854 ST Loongson 2E/2F. */
855 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
856 || TARGET_MIPS5900 \
857 || TARGET_LOONGSON_2EF)
858
859 /* ISA has LDC1 and SDC1. */
860 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
861 && !TARGET_MIPS5900 \
862 && !TARGET_MIPS16)
863
864 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
865 branch on CC, and move (both FP and non-FP) on CC. */
866 #define ISA_HAS_8CC (ISA_MIPS4 || mips_isa_rev >= 1)
867
868 /* This is a catch all for other mips4 instructions: indexed load, the
869 FP madd and msub instructions, and the FP recip and recip sqrt
870 instructions. Note that this macro should only be used by other
871 ISA_HAS_* macros. */
872 #define ISA_HAS_FP4 ((ISA_MIPS4 \
873 || ISA_MIPS64 \
874 || mips_isa_rev >= 2) \
875 && !TARGET_MIPS16)
876
877 /* ISA has floating-point indexed load and store instructions
878 (LWXC1, LDXC1, SWXC1 and SDXC1). */
879 #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
880
881 /* ISA has paired-single instructions. */
882 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS64 || mips_isa_rev >= 2)
883
884 /* ISA has conditional trap instructions. */
885 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
886 && !TARGET_MIPS16)
887
888 /* ISA has integer multiply-accumulate instructions, madd and msub. */
889 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1)
890
891 /* Integer multiply-accumulate instructions should be generated. */
892 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
893
894 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
895 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
896
897 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
898 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
899
900 /* ISA has floating-point nmadd and nmsub instructions
901 'd = -((a * b) [+-] c)'. */
902 #define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4
903
904 /* ISA has floating-point nmadd and nmsub instructions
905 'c = -((a * b) [+-] c)'. */
906 #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF
907
908 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
909 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
910 doubles are stored in pairs of FPRs, so for safety's sake, we apply
911 this restriction to the MIPS IV ISA too. */
912 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
913 (((ISA_HAS_FP4 \
914 && ((MODE) == SFmode \
915 || ((TARGET_FLOAT64 \
916 || mips_isa_rev >= 2) \
917 && (MODE) == DFmode))) \
918 || (TARGET_SB1 \
919 && (MODE) == V2SFmode)) \
920 && !TARGET_MIPS16)
921
922 /* ISA has count leading zeroes/ones instruction (not implemented). */
923 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
924
925 /* ISA has three operand multiply instructions that put
926 the high part in an accumulator: mulhi or mulhiu. */
927 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
928 || TARGET_MIPS5500 \
929 || TARGET_SR71K) \
930 && !TARGET_MIPS16)
931
932 /* ISA has three operand multiply instructions that negate the
933 result and put the result in an accumulator. */
934 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
935 || TARGET_MIPS5500 \
936 || TARGET_SR71K) \
937 && !TARGET_MIPS16)
938
939 /* ISA has three operand multiply instructions that subtract the
940 result from a 4th operand and put the result in an accumulator. */
941 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
942 || TARGET_MIPS5500 \
943 || TARGET_SR71K) \
944 && !TARGET_MIPS16)
945
946 /* ISA has three operand multiply instructions that add the result
947 to a 4th operand and put the result in an accumulator. */
948 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
949 || TARGET_MIPS4130 \
950 || TARGET_MIPS5400 \
951 || TARGET_MIPS5500 \
952 || TARGET_SR71K) \
953 && !TARGET_MIPS16)
954
955 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
956 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
957 || TARGET_MIPS4130) \
958 && !TARGET_MIPS16)
959
960 /* ISA has the "ror" (rotate right) instructions. */
961 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
962 || TARGET_MIPS5400 \
963 || TARGET_MIPS5500 \
964 || TARGET_SR71K \
965 || TARGET_SMARTMIPS) \
966 && !TARGET_MIPS16)
967
968 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
969 64-bit targets also provide DSBH and DSHD. */
970 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
971
972 /* ISA has data prefetch instructions. This controls use of 'pref'. */
973 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
974 || TARGET_LOONGSON_2EF \
975 || TARGET_MIPS5900 \
976 || mips_isa_rev >= 1) \
977 && !TARGET_MIPS16)
978
979 /* ISA has data indexed prefetch instructions. This controls use of
980 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
981 (prefx is a cop1x instruction, so can only be used if FP is
982 enabled.) */
983 #define ISA_HAS_PREFETCHX ISA_HAS_FP4
984
985 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
986 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
987 also requires TARGET_DOUBLE_FLOAT. */
988 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
989
990 /* ISA includes the MIPS32r2 seb and seh instructions. */
991 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
992
993 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
994 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
995
996 /* ISA has instructions for accessing top part of 64-bit fp regs. */
997 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && mips_isa_rev >= 2)
998
999 /* ISA has lwxs instruction (load w/scaled index address. */
1000 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1001 && !TARGET_MIPS16)
1002
1003 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1004 #define ISA_HAS_LBX (TARGET_OCTEON2)
1005 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1006 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1007 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1008 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1009 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1010 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1011 && TARGET_64BIT)
1012
1013 /* The DSP ASE is available. */
1014 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1015
1016 /* Revision 2 of the DSP ASE is available. */
1017 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1018
1019 /* True if the result of a load is not available to the next instruction.
1020 A nop will then be needed between instructions like "lw $4,..."
1021 and "addiu $4,$4,1". */
1022 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1023 && !TARGET_MIPS3900 \
1024 && !TARGET_MIPS5900 \
1025 && !TARGET_MIPS16 \
1026 && !TARGET_MICROMIPS)
1027
1028 /* Likewise mtc1 and mfc1. */
1029 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1030 && !TARGET_MIPS5900 \
1031 && !TARGET_LOONGSON_2EF)
1032
1033 /* Likewise floating-point comparisons. */
1034 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1035 && !TARGET_MIPS5900 \
1036 && !TARGET_LOONGSON_2EF)
1037
1038 /* True if mflo and mfhi can be immediately followed by instructions
1039 which write to the HI and LO registers.
1040
1041 According to MIPS specifications, MIPS ISAs I, II, and III need
1042 (at least) two instructions between the reads of HI/LO and
1043 instructions which write them, and later ISAs do not. Contradicting
1044 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1045 the UM for the NEC Vr5000) document needing the instructions between
1046 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1047 MIPS64 and later ISAs to have the interlocks, plus any specific
1048 earlier-ISA CPUs for which CPU documentation declares that the
1049 instructions are really interlocked. */
1050 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1051 || TARGET_MIPS5500 \
1052 || TARGET_MIPS5900 \
1053 || TARGET_LOONGSON_2EF)
1054
1055 /* ISA includes synci, jr.hb and jalr.hb. */
1056 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1057
1058 /* ISA includes sync. */
1059 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1060 #define GENERATE_SYNC \
1061 (target_flags_explicit & MASK_LLSC \
1062 ? TARGET_LLSC && !TARGET_MIPS16 \
1063 : ISA_HAS_SYNC)
1064
1065 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1066 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1067 instructions. */
1068 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1069 #define GENERATE_LL_SC \
1070 (target_flags_explicit & MASK_LLSC \
1071 ? TARGET_LLSC && !TARGET_MIPS16 \
1072 : ISA_HAS_LL_SC)
1073
1074 #define ISA_HAS_SWAP (TARGET_XLP)
1075 #define ISA_HAS_LDADD (TARGET_XLP)
1076
1077 /* ISA includes the baddu instruction. */
1078 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1079
1080 /* ISA includes the bbit* instructions. */
1081 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1082
1083 /* ISA includes the cins instruction. */
1084 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1085
1086 /* ISA includes the exts instruction. */
1087 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1088
1089 /* ISA includes the seq and sne instructions. */
1090 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1091
1092 /* ISA includes the pop instruction. */
1093 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1094
1095 /* The CACHE instruction is available in non-MIPS16 code. */
1096 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1097
1098 /* The CACHE instruction is available. */
1099 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1100 \f
1101 /* Tell collect what flags to pass to nm. */
1102 #ifndef NM_FLAGS
1103 #define NM_FLAGS "-Bn"
1104 #endif
1105
1106 \f
1107 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1108 the assembler. It may be overridden by subtargets.
1109
1110 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1111 COFF debugging info. */
1112
1113 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1114 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1115 %{g} %{g0} %{g1} %{g2} %{g3} \
1116 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1117 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1118 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1119 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1120 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1121 #endif
1122
1123 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1124 overridden by subtargets. */
1125
1126 #ifndef SUBTARGET_ASM_SPEC
1127 #define SUBTARGET_ASM_SPEC ""
1128 #endif
1129
1130 #undef ASM_SPEC
1131 #define ASM_SPEC "\
1132 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1133 %{mips32*} %{mips64*} \
1134 %{mips16} %{mno-mips16:-no-mips16} \
1135 %{mmicromips} %{mno-micromips} \
1136 %{mips3d} %{mno-mips3d:-no-mips3d} \
1137 %{mdmx} %{mno-mdmx:-no-mdmx} \
1138 %{mdsp} %{mno-dsp} \
1139 %{mdspr2} %{mno-dspr2} \
1140 %{mmcu} %{mno-mcu} \
1141 %{meva} %{mno-eva} \
1142 %{mvirt} %{mno-virt} \
1143 %{mxpa} %{mno-xpa} \
1144 %{msmartmips} %{mno-smartmips} \
1145 %{mmt} %{mno-mt} \
1146 %{mfix-rm7000} %{mno-fix-rm7000} \
1147 %{mfix-vr4120} %{mfix-vr4130} \
1148 %{mfix-24k} \
1149 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1150 %(subtarget_asm_debugging_spec) \
1151 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1152 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1153 %{mfp32} %{mfp64} %{mnan=*} \
1154 %{mshared} %{mno-shared} \
1155 %{msym32} %{mno-sym32} \
1156 %{mtune=*} \
1157 %(subtarget_asm_spec)"
1158
1159 /* Extra switches sometimes passed to the linker. */
1160
1161 #ifndef LINK_SPEC
1162 #define LINK_SPEC "\
1163 %(endian_spec) \
1164 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1165 %{shared}"
1166 #endif /* LINK_SPEC defined */
1167
1168
1169 /* Specs for the compiler proper */
1170
1171 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1172 overridden by subtargets. */
1173 #ifndef SUBTARGET_CC1_SPEC
1174 #define SUBTARGET_CC1_SPEC ""
1175 #endif
1176
1177 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1178
1179 #undef CC1_SPEC
1180 #define CC1_SPEC "\
1181 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1182 %(subtarget_cc1_spec)"
1183
1184 /* Preprocessor specs. */
1185
1186 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1187 overridden by subtargets. */
1188 #ifndef SUBTARGET_CPP_SPEC
1189 #define SUBTARGET_CPP_SPEC ""
1190 #endif
1191
1192 #define CPP_SPEC "%(subtarget_cpp_spec)"
1193
1194 /* This macro defines names of additional specifications to put in the specs
1195 that can be used in various specifications like CC1_SPEC. Its definition
1196 is an initializer with a subgrouping for each command option.
1197
1198 Each subgrouping contains a string constant, that defines the
1199 specification name, and a string constant that used by the GCC driver
1200 program.
1201
1202 Do not define this macro if it does not need to do anything. */
1203
1204 #define EXTRA_SPECS \
1205 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1206 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1207 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1208 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1209 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1210 { "endian_spec", ENDIAN_SPEC }, \
1211 SUBTARGET_EXTRA_SPECS
1212
1213 #ifndef SUBTARGET_EXTRA_SPECS
1214 #define SUBTARGET_EXTRA_SPECS
1215 #endif
1216 \f
1217 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1218 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1219
1220 #ifndef PREFERRED_DEBUGGING_TYPE
1221 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1222 #endif
1223
1224 /* The size of DWARF addresses should be the same as the size of symbols
1225 in the target file format. They shouldn't depend on things like -msym32,
1226 because many DWARF consumers do not allow the mixture of address sizes
1227 that one would then get from linking -msym32 code with -msym64 code.
1228
1229 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1230 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1231 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1232
1233 /* By default, turn on GDB extensions. */
1234 #define DEFAULT_GDB_EXTENSIONS 1
1235
1236 /* Local compiler-generated symbols must have a prefix that the assembler
1237 understands. By default, this is $, although some targets (e.g.,
1238 NetBSD-ELF) need to override this. */
1239
1240 #ifndef LOCAL_LABEL_PREFIX
1241 #define LOCAL_LABEL_PREFIX "$"
1242 #endif
1243
1244 /* By default on the mips, external symbols do not have an underscore
1245 prepended, but some targets (e.g., NetBSD) require this. */
1246
1247 #ifndef USER_LABEL_PREFIX
1248 #define USER_LABEL_PREFIX ""
1249 #endif
1250
1251 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1252 since the length can run past this up to a continuation point. */
1253 #undef DBX_CONTIN_LENGTH
1254 #define DBX_CONTIN_LENGTH 1500
1255
1256 /* How to renumber registers for dbx and gdb. */
1257 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1258
1259 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1260 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1261
1262 /* The DWARF 2 CFA column which tracks the return address. */
1263 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1264
1265 /* Before the prologue, RA lives in r31. */
1266 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1267
1268 /* Describe how we implement __builtin_eh_return. */
1269 #define EH_RETURN_DATA_REGNO(N) \
1270 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1271
1272 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1273
1274 #define EH_USES(N) mips_eh_uses (N)
1275
1276 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1277 The default for this in 64-bit mode is 8, which causes problems with
1278 SFmode register saves. */
1279 #define DWARF_CIE_DATA_ALIGNMENT -4
1280
1281 /* Correct the offset of automatic variables and arguments. Note that
1282 the MIPS debug format wants all automatic variables and arguments
1283 to be in terms of the virtual frame pointer (stack pointer before
1284 any adjustment in the function), while the MIPS 3.0 linker wants
1285 the frame pointer to be the stack pointer after the initial
1286 adjustment. */
1287
1288 #define DEBUGGER_AUTO_OFFSET(X) \
1289 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1290 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1291 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1292 \f
1293 /* Target machine storage layout */
1294
1295 #define BITS_BIG_ENDIAN 0
1296 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1297 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1298
1299 #define MAX_BITS_PER_WORD 64
1300
1301 /* Width of a word, in units (bytes). */
1302 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1303 #ifndef IN_LIBGCC2
1304 #define MIN_UNITS_PER_WORD 4
1305 #endif
1306
1307 /* For MIPS, width of a floating point register. */
1308 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1309
1310 /* The number of consecutive floating-point registers needed to store the
1311 largest format supported by the FPU. */
1312 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1313
1314 /* The number of consecutive floating-point registers needed to store the
1315 smallest format supported by the FPU. */
1316 #define MIN_FPRS_PER_FMT \
1317 (mips_isa_rev >= 1 ? 1 : MAX_FPRS_PER_FMT)
1318
1319 /* The largest size of value that can be held in floating-point
1320 registers and moved with a single instruction. */
1321 #define UNITS_PER_HWFPVALUE \
1322 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1323
1324 /* The largest size of value that can be held in floating-point
1325 registers. */
1326 #define UNITS_PER_FPVALUE \
1327 (TARGET_SOFT_FLOAT_ABI ? 0 \
1328 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1329 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1330
1331 /* The number of bytes in a double. */
1332 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1333
1334 /* Set the sizes of the core types. */
1335 #define SHORT_TYPE_SIZE 16
1336 #define INT_TYPE_SIZE 32
1337 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1338 #define LONG_LONG_TYPE_SIZE 64
1339
1340 #define FLOAT_TYPE_SIZE 32
1341 #define DOUBLE_TYPE_SIZE 64
1342 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1343
1344 /* Define the sizes of fixed-point types. */
1345 #define SHORT_FRACT_TYPE_SIZE 8
1346 #define FRACT_TYPE_SIZE 16
1347 #define LONG_FRACT_TYPE_SIZE 32
1348 #define LONG_LONG_FRACT_TYPE_SIZE 64
1349
1350 #define SHORT_ACCUM_TYPE_SIZE 16
1351 #define ACCUM_TYPE_SIZE 32
1352 #define LONG_ACCUM_TYPE_SIZE 64
1353 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1354 doesn't support 128-bit integers for MIPS32 currently. */
1355 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1356
1357 /* long double is not a fixed mode, but the idea is that, if we
1358 support long double, we also want a 128-bit integer type. */
1359 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1360
1361 #ifdef IN_LIBGCC2
1362 #if ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1363 || (defined _ABI64 && _MIPS_SIM == _ABI64))
1364 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1365 # else
1366 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1367 # endif
1368 #endif
1369
1370 /* Width in bits of a pointer. */
1371 #ifndef POINTER_SIZE
1372 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1373 #endif
1374
1375 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1376 #define PARM_BOUNDARY BITS_PER_WORD
1377
1378 /* Allocation boundary (in *bits*) for the code of a function. */
1379 #define FUNCTION_BOUNDARY 32
1380
1381 /* Alignment of field after `int : 0' in a structure. */
1382 #define EMPTY_FIELD_BOUNDARY 32
1383
1384 /* Every structure's size must be a multiple of this. */
1385 /* 8 is observed right on a DECstation and on riscos 4.02. */
1386 #define STRUCTURE_SIZE_BOUNDARY 8
1387
1388 /* There is no point aligning anything to a rounder boundary than this. */
1389 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1390
1391 /* All accesses must be aligned. */
1392 #define STRICT_ALIGNMENT 1
1393
1394 /* Define this if you wish to imitate the way many other C compilers
1395 handle alignment of bitfields and the structures that contain
1396 them.
1397
1398 The behavior is that the type written for a bit-field (`int',
1399 `short', or other integer type) imposes an alignment for the
1400 entire structure, as if the structure really did contain an
1401 ordinary field of that type. In addition, the bit-field is placed
1402 within the structure so that it would fit within such a field,
1403 not crossing a boundary for it.
1404
1405 Thus, on most machines, a bit-field whose type is written as `int'
1406 would not cross a four-byte boundary, and would force four-byte
1407 alignment for the whole structure. (The alignment used may not
1408 be four bytes; it is controlled by the other alignment
1409 parameters.)
1410
1411 If the macro is defined, its definition should be a C expression;
1412 a nonzero value for the expression enables this behavior. */
1413
1414 #define PCC_BITFIELD_TYPE_MATTERS 1
1415
1416 /* If defined, a C expression to compute the alignment given to a
1417 constant that is being placed in memory. CONSTANT is the constant
1418 and ALIGN is the alignment that the object would ordinarily have.
1419 The value of this macro is used instead of that alignment to align
1420 the object.
1421
1422 If this macro is not defined, then ALIGN is used.
1423
1424 The typical use of this macro is to increase alignment for string
1425 constants to be word aligned so that `strcpy' calls that copy
1426 constants can be done inline. */
1427
1428 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1429 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1430 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1431
1432 /* If defined, a C expression to compute the alignment for a static
1433 variable. TYPE is the data type, and ALIGN is the alignment that
1434 the object would ordinarily have. The value of this macro is used
1435 instead of that alignment to align the object.
1436
1437 If this macro is not defined, then ALIGN is used.
1438
1439 One use of this macro is to increase alignment of medium-size
1440 data to make it all fit in fewer cache lines. Another is to
1441 cause character arrays to be word-aligned so that `strcpy' calls
1442 that copy constants to character arrays can be done inline. */
1443
1444 #undef DATA_ALIGNMENT
1445 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1446 ((((ALIGN) < BITS_PER_WORD) \
1447 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1448 || TREE_CODE (TYPE) == UNION_TYPE \
1449 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1450
1451 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1452 character arrays to be word-aligned so that `strcpy' calls that copy
1453 constants to character arrays can be done inline, and 'strcmp' can be
1454 optimised to use word loads. */
1455 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1456 DATA_ALIGNMENT (TYPE, ALIGN)
1457
1458 #define PAD_VARARGS_DOWN \
1459 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1460
1461 /* Define if operations between registers always perform the operation
1462 on the full register even if a narrower mode is specified. */
1463 #define WORD_REGISTER_OPERATIONS
1464
1465 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1466 moves. All other references are zero extended. */
1467 #define LOAD_EXTEND_OP(MODE) \
1468 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1469 ? SIGN_EXTEND : ZERO_EXTEND)
1470
1471 /* Define this macro if it is advisable to hold scalars in registers
1472 in a wider mode than that declared by the program. In such cases,
1473 the value is constrained to be within the bounds of the declared
1474 type, but kept valid in the wider mode. The signedness of the
1475 extension may differ from that of the type. */
1476
1477 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1478 if (GET_MODE_CLASS (MODE) == MODE_INT \
1479 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1480 { \
1481 if ((MODE) == SImode) \
1482 (UNSIGNEDP) = 0; \
1483 (MODE) = Pmode; \
1484 }
1485
1486 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1487 Extensions of pointers to word_mode must be signed. */
1488 #define POINTERS_EXTEND_UNSIGNED false
1489
1490 /* Define if loading short immediate values into registers sign extends. */
1491 #define SHORT_IMMEDIATES_SIGN_EXTEND
1492
1493 /* The [d]clz instructions have the natural values at 0. */
1494
1495 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1496 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1497 \f
1498 /* Standard register usage. */
1499
1500 /* Number of hardware registers. We have:
1501
1502 - 32 integer registers
1503 - 32 floating point registers
1504 - 8 condition code registers
1505 - 2 accumulator registers (hi and lo)
1506 - 32 registers each for coprocessors 0, 2 and 3
1507 - 4 fake registers:
1508 - ARG_POINTER_REGNUM
1509 - FRAME_POINTER_REGNUM
1510 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1511 - CPRESTORE_SLOT_REGNUM
1512 - 2 dummy entries that were used at various times in the past.
1513 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1514 - 6 DSP control registers */
1515
1516 #define FIRST_PSEUDO_REGISTER 188
1517
1518 /* By default, fix the kernel registers ($26 and $27), the global
1519 pointer ($28) and the stack pointer ($29). This can change
1520 depending on the command-line options.
1521
1522 Regarding coprocessor registers: without evidence to the contrary,
1523 it's best to assume that each coprocessor register has a unique
1524 use. This can be overridden, in, e.g., mips_option_override or
1525 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1526 inappropriate for a particular target. */
1527
1528 #define FIXED_REGISTERS \
1529 { \
1530 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1531 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1532 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1533 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1534 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1535 /* COP0 registers */ \
1536 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1537 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1538 /* COP2 registers */ \
1539 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1540 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1541 /* COP3 registers */ \
1542 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1543 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1544 /* 6 DSP accumulator registers & 6 control registers */ \
1545 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1546 }
1547
1548
1549 /* Set up this array for o32 by default.
1550
1551 Note that we don't mark $31 as a call-clobbered register. The idea is
1552 that it's really the call instructions themselves which clobber $31.
1553 We don't care what the called function does with it afterwards.
1554
1555 This approach makes it easier to implement sibcalls. Unlike normal
1556 calls, sibcalls don't clobber $31, so the register reaches the
1557 called function in tact. EPILOGUE_USES says that $31 is useful
1558 to the called function. */
1559
1560 #define CALL_USED_REGISTERS \
1561 { \
1562 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1563 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1565 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1567 /* COP0 registers */ \
1568 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1569 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1570 /* COP2 registers */ \
1571 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1573 /* COP3 registers */ \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1576 /* 6 DSP accumulator registers & 6 control registers */ \
1577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1578 }
1579
1580
1581 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1582
1583 #define CALL_REALLY_USED_REGISTERS \
1584 { /* General registers. */ \
1585 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1586 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1587 /* Floating-point registers. */ \
1588 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1589 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1590 /* Others. */ \
1591 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1592 /* COP0 registers */ \
1593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1595 /* COP2 registers */ \
1596 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1597 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1598 /* COP3 registers */ \
1599 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1600 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1601 /* 6 DSP accumulator registers & 6 control registers */ \
1602 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1603 }
1604
1605 /* Internal macros to classify a register number as to whether it's a
1606 general purpose register, a floating point register, a
1607 multiply/divide register, or a status register. */
1608
1609 #define GP_REG_FIRST 0
1610 #define GP_REG_LAST 31
1611 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1612 #define GP_DBX_FIRST 0
1613 #define K0_REG_NUM (GP_REG_FIRST + 26)
1614 #define K1_REG_NUM (GP_REG_FIRST + 27)
1615 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1616
1617 #define FP_REG_FIRST 32
1618 #define FP_REG_LAST 63
1619 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1620 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1621
1622 #define MD_REG_FIRST 64
1623 #define MD_REG_LAST 65
1624 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1625 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1626
1627 /* The DWARF 2 CFA column which tracks the return address from a
1628 signal handler context. This means that to maintain backwards
1629 compatibility, no hard register can be assigned this column if it
1630 would need to be handled by the DWARF unwinder. */
1631 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1632
1633 #define ST_REG_FIRST 67
1634 #define ST_REG_LAST 74
1635 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1636
1637
1638 /* FIXME: renumber. */
1639 #define COP0_REG_FIRST 80
1640 #define COP0_REG_LAST 111
1641 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1642
1643 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1644 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1645 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1646
1647 #define COP2_REG_FIRST 112
1648 #define COP2_REG_LAST 143
1649 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1650
1651 #define COP3_REG_FIRST 144
1652 #define COP3_REG_LAST 175
1653 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1654
1655 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1656 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1657 #define ALL_COP_REG_LAST COP3_REG_LAST
1658 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1659
1660 #define DSP_ACC_REG_FIRST 176
1661 #define DSP_ACC_REG_LAST 181
1662 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1663
1664 #define AT_REGNUM (GP_REG_FIRST + 1)
1665 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1666 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1667
1668 /* A few bitfield locations for the coprocessor registers. */
1669 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1670 the cause register for the EIC interrupt mode. */
1671 #define CAUSE_IPL 10
1672 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1673 #define SR_IPL 10
1674 /* Exception Level is at bit 1 of the status register. */
1675 #define SR_EXL 1
1676 /* Interrupt Enable is at bit 0 of the status register. */
1677 #define SR_IE 0
1678
1679 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1680 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1681 should be used instead. */
1682 #define FPSW_REGNUM ST_REG_FIRST
1683
1684 #define GP_REG_P(REGNO) \
1685 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1686 #define M16_REG_P(REGNO) \
1687 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1688 #define M16STORE_REG_P(REGNO) \
1689 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1690 #define FP_REG_P(REGNO) \
1691 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1692 #define MD_REG_P(REGNO) \
1693 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1694 #define ST_REG_P(REGNO) \
1695 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1696 #define COP0_REG_P(REGNO) \
1697 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1698 #define COP2_REG_P(REGNO) \
1699 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1700 #define COP3_REG_P(REGNO) \
1701 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1702 #define ALL_COP_REG_P(REGNO) \
1703 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1704 /* Test if REGNO is one of the 6 new DSP accumulators. */
1705 #define DSP_ACC_REG_P(REGNO) \
1706 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1707 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1708 #define ACC_REG_P(REGNO) \
1709 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1710
1711 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1712
1713 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1714 to initialize the mips16 gp pseudo register. */
1715 #define CONST_GP_P(X) \
1716 (GET_CODE (X) == CONST \
1717 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1718 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1719
1720 /* Return coprocessor number from register number. */
1721
1722 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1723 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1724 : COP3_REG_P (REGNO) ? '3' : '?')
1725
1726
1727 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1728
1729 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1730 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1731
1732 #define MODES_TIEABLE_P mips_modes_tieable_p
1733
1734 /* Register to use for pushing function arguments. */
1735 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1736
1737 /* These two registers don't really exist: they get eliminated to either
1738 the stack or hard frame pointer. */
1739 #define ARG_POINTER_REGNUM 77
1740 #define FRAME_POINTER_REGNUM 78
1741
1742 /* $30 is not available on the mips16, so we use $17 as the frame
1743 pointer. */
1744 #define HARD_FRAME_POINTER_REGNUM \
1745 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1746
1747 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1748 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1749
1750 /* Register in which static-chain is passed to a function. */
1751 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1752
1753 /* Registers used as temporaries in prologue/epilogue code:
1754
1755 - If a MIPS16 PIC function needs access to _gp, it first loads
1756 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1757
1758 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1759 register. The register must not conflict with MIPS16_PIC_TEMP.
1760
1761 - If we aren't generating MIPS16 code, the prologue can also use
1762 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1763
1764 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1765 register.
1766
1767 If we're generating MIPS16 code, these registers must come from the
1768 core set of 8. The prologue registers mustn't conflict with any
1769 incoming arguments, the static chain pointer, or the frame pointer.
1770 The epilogue temporary mustn't conflict with the return registers,
1771 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1772 or the EH data registers.
1773
1774 If we're generating interrupt handlers, we use K0 as a temporary register
1775 in prologue/epilogue code. */
1776
1777 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1778 #define MIPS_PROLOGUE_TEMP_REGNUM \
1779 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1780 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1781 (TARGET_MIPS16 \
1782 ? (gcc_unreachable (), INVALID_REGNUM) \
1783 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1784 #define MIPS_EPILOGUE_TEMP_REGNUM \
1785 (cfun->machine->interrupt_handler_p \
1786 ? K0_REG_NUM \
1787 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1788
1789 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1790 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1791 #define MIPS_PROLOGUE_TEMP2(MODE) \
1792 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1793 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1794
1795 /* Define this macro if it is as good or better to call a constant
1796 function address than to call an address kept in a register. */
1797 #define NO_FUNCTION_CSE 1
1798
1799 /* The ABI-defined global pointer. Sometimes we use a different
1800 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1801 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1802
1803 /* We normally use $28 as the global pointer. However, when generating
1804 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1805 register instead. They can then avoid saving and restoring $28
1806 and perhaps avoid using a frame at all.
1807
1808 When a leaf function uses something other than $28, mips_expand_prologue
1809 will modify pic_offset_table_rtx in place. Take the register number
1810 from there after reload. */
1811 #define PIC_OFFSET_TABLE_REGNUM \
1812 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1813 \f
1814 /* Define the classes of registers for register constraints in the
1815 machine description. Also define ranges of constants.
1816
1817 One of the classes must always be named ALL_REGS and include all hard regs.
1818 If there is more than one class, another class must be named NO_REGS
1819 and contain no registers.
1820
1821 The name GENERAL_REGS must be the name of a class (or an alias for
1822 another name such as ALL_REGS). This is the class of registers
1823 that is allowed by "g" or "r" in a register constraint.
1824 Also, registers outside this class are allocated only when
1825 instructions express preferences for them.
1826
1827 The classes must be numbered in nondecreasing order; that is,
1828 a larger-numbered class must never be contained completely
1829 in a smaller-numbered class.
1830
1831 For any two classes, it is very desirable that there be another
1832 class that represents their union. */
1833
1834 enum reg_class
1835 {
1836 NO_REGS, /* no registers in set */
1837 M16_STORE_REGS, /* microMIPS store registers */
1838 M16_REGS, /* mips16 directly accessible registers */
1839 T_REG, /* mips16 T register ($24) */
1840 M16_T_REGS, /* mips16 registers plus T register */
1841 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1842 V1_REG, /* Register $v1 ($3) used for TLS access. */
1843 LEA_REGS, /* Every GPR except $25 */
1844 GR_REGS, /* integer registers */
1845 FP_REGS, /* floating point registers */
1846 MD0_REG, /* first multiply/divide register */
1847 MD1_REG, /* second multiply/divide register */
1848 MD_REGS, /* multiply/divide registers (hi/lo) */
1849 COP0_REGS, /* generic coprocessor classes */
1850 COP2_REGS,
1851 COP3_REGS,
1852 ST_REGS, /* status registers (fp status) */
1853 DSP_ACC_REGS, /* DSP accumulator registers */
1854 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1855 FRAME_REGS, /* $arg and $frame */
1856 GR_AND_MD0_REGS, /* union classes */
1857 GR_AND_MD1_REGS,
1858 GR_AND_MD_REGS,
1859 GR_AND_ACC_REGS,
1860 ALL_REGS, /* all registers */
1861 LIM_REG_CLASSES /* max value + 1 */
1862 };
1863
1864 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1865
1866 #define GENERAL_REGS GR_REGS
1867
1868 /* An initializer containing the names of the register classes as C
1869 string constants. These names are used in writing some of the
1870 debugging dumps. */
1871
1872 #define REG_CLASS_NAMES \
1873 { \
1874 "NO_REGS", \
1875 "M16_STORE_REGS", \
1876 "M16_REGS", \
1877 "T_REG", \
1878 "M16_T_REGS", \
1879 "PIC_FN_ADDR_REG", \
1880 "V1_REG", \
1881 "LEA_REGS", \
1882 "GR_REGS", \
1883 "FP_REGS", \
1884 "MD0_REG", \
1885 "MD1_REG", \
1886 "MD_REGS", \
1887 /* coprocessor registers */ \
1888 "COP0_REGS", \
1889 "COP2_REGS", \
1890 "COP3_REGS", \
1891 "ST_REGS", \
1892 "DSP_ACC_REGS", \
1893 "ACC_REGS", \
1894 "FRAME_REGS", \
1895 "GR_AND_MD0_REGS", \
1896 "GR_AND_MD1_REGS", \
1897 "GR_AND_MD_REGS", \
1898 "GR_AND_ACC_REGS", \
1899 "ALL_REGS" \
1900 }
1901
1902 /* An initializer containing the contents of the register classes,
1903 as integers which are bit masks. The Nth integer specifies the
1904 contents of class N. The way the integer MASK is interpreted is
1905 that register R is in the class if `MASK & (1 << R)' is 1.
1906
1907 When the machine has more than 32 registers, an integer does not
1908 suffice. Then the integers are replaced by sub-initializers,
1909 braced groupings containing several integers. Each
1910 sub-initializer must be suitable as an initializer for the type
1911 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1912
1913 #define REG_CLASS_CONTENTS \
1914 { \
1915 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1916 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
1917 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1918 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1919 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1920 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1921 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1922 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1923 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1924 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1925 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1926 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1927 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1928 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1929 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1930 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1931 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1932 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1933 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1934 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1935 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1936 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1937 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1938 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1939 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1940 }
1941
1942
1943 /* A C expression whose value is a register class containing hard
1944 register REGNO. In general there is more that one such class;
1945 choose a class which is "minimal", meaning that no smaller class
1946 also contains the register. */
1947
1948 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1949
1950 /* A macro whose definition is the name of the class to which a
1951 valid base register must belong. A base register is one used in
1952 an address which is the register value plus a displacement. */
1953
1954 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1955
1956 /* A macro whose definition is the name of the class to which a
1957 valid index register must belong. An index register is one used
1958 in an address where its value is either multiplied by a scale
1959 factor or added to another register (as well as added to a
1960 displacement). */
1961
1962 #define INDEX_REG_CLASS NO_REGS
1963
1964 /* We generally want to put call-clobbered registers ahead of
1965 call-saved ones. (IRA expects this.) */
1966
1967 #define REG_ALLOC_ORDER \
1968 { /* Accumulator registers. When GPRs and accumulators have equal \
1969 cost, we generally prefer to use accumulators. For example, \
1970 a division of multiplication result is better allocated to LO, \
1971 so that we put the MFLO at the point of use instead of at the \
1972 point of definition. It's also needed if we're to take advantage \
1973 of the extra accumulators available with -mdspr2. In some cases, \
1974 it can also help to reduce register pressure. */ \
1975 64, 65,176,177,178,179,180,181, \
1976 /* Call-clobbered GPRs. */ \
1977 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1978 24, 25, 31, \
1979 /* The global pointer. This is call-clobbered for o32 and o64 \
1980 abicalls, call-saved for n32 and n64 abicalls, and a program \
1981 invariant otherwise. Putting it between the call-clobbered \
1982 and call-saved registers should cope with all eventualities. */ \
1983 28, \
1984 /* Call-saved GPRs. */ \
1985 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1986 /* GPRs that can never be exposed to the register allocator. */ \
1987 0, 26, 27, 29, \
1988 /* Call-clobbered FPRs. */ \
1989 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1990 48, 49, 50, 51, \
1991 /* FPRs that are usually call-saved. The odd ones are actually \
1992 call-clobbered for n32, but listing them ahead of the even \
1993 registers might encourage the register allocator to fragment \
1994 the available FPR pairs. We need paired FPRs to store long \
1995 doubles, so it isn't clear that using a different order \
1996 for n32 would be a win. */ \
1997 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1998 /* None of the remaining classes have defined call-saved \
1999 registers. */ \
2000 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2001 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2002 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2003 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2004 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2005 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2006 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2007 182,183,184,185,186,187 \
2008 }
2009
2010 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
2011 to be rearranged based on a particular function. On the mips16, we
2012 want to allocate $24 (T_REG) before other registers for
2013 instructions for which it is possible. */
2014
2015 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2016
2017 /* True if VALUE is an unsigned 6-bit number. */
2018
2019 #define UIMM6_OPERAND(VALUE) \
2020 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2021
2022 /* True if VALUE is a signed 10-bit number. */
2023
2024 #define IMM10_OPERAND(VALUE) \
2025 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2026
2027 /* True if VALUE is a signed 16-bit number. */
2028
2029 #define SMALL_OPERAND(VALUE) \
2030 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2031
2032 /* True if VALUE is an unsigned 16-bit number. */
2033
2034 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2035 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2036
2037 /* True if VALUE can be loaded into a register using LUI. */
2038
2039 #define LUI_OPERAND(VALUE) \
2040 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2041 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2042
2043 /* Return a value X with the low 16 bits clear, and such that
2044 VALUE - X is a signed 16-bit value. */
2045
2046 #define CONST_HIGH_PART(VALUE) \
2047 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2048
2049 #define CONST_LOW_PART(VALUE) \
2050 ((VALUE) - CONST_HIGH_PART (VALUE))
2051
2052 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2053 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2054 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2055 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2056
2057 /* The HI and LO registers can only be reloaded via the general
2058 registers. Condition code registers can only be loaded to the
2059 general registers, and from the floating point registers. */
2060
2061 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2062 mips_secondary_reload_class (CLASS, MODE, X, true)
2063 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2064 mips_secondary_reload_class (CLASS, MODE, X, false)
2065
2066 /* Return the maximum number of consecutive registers
2067 needed to represent mode MODE in a register of class CLASS. */
2068
2069 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2070
2071 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2072 mips_cannot_change_mode_class (FROM, TO, CLASS)
2073 \f
2074 /* Stack layout; function entry, exit and calling. */
2075
2076 #define STACK_GROWS_DOWNWARD
2077
2078 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2079
2080 /* Size of the area allocated in the frame to save the GP. */
2081
2082 #define MIPS_GP_SAVE_AREA_SIZE \
2083 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2084
2085 /* The offset of the first local variable from the frame pointer. See
2086 mips_compute_frame_info for details about the frame layout. */
2087
2088 #define STARTING_FRAME_OFFSET \
2089 (FRAME_GROWS_DOWNWARD \
2090 ? 0 \
2091 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2092
2093 #define RETURN_ADDR_RTX mips_return_addr
2094
2095 /* Mask off the MIPS16 ISA bit in unwind addresses.
2096
2097 The reason for this is a little subtle. When unwinding a call,
2098 we are given the call's return address, which on most targets
2099 is the address of the following instruction. However, what we
2100 actually want to find is the EH region for the call itself.
2101 The target-independent unwind code therefore searches for "RA - 1".
2102
2103 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2104 RA - 1 is therefore the real (even-valued) start of the return
2105 instruction. EH region labels are usually odd-valued MIPS16 symbols
2106 too, so a search for an even address within a MIPS16 region would
2107 usually work.
2108
2109 However, there is an exception. If the end of an EH region is also
2110 the end of a function, the end label is allowed to be even. This is
2111 necessary because a following non-MIPS16 function may also need EH
2112 information for its first instruction.
2113
2114 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2115 non-ISA-encoded address. This probably isn't ideal, but it is
2116 the traditional (legacy) behavior. It is therefore only safe
2117 to search MIPS EH regions for an _odd-valued_ address.
2118
2119 Masking off the ISA bit means that the target-independent code
2120 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2121 #define MASK_RETURN_ADDR GEN_INT (-2)
2122
2123
2124 /* Similarly, don't use the least-significant bit to tell pointers to
2125 code from vtable index. */
2126
2127 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2128
2129 /* The eliminations to $17 are only used for mips16 code. See the
2130 definition of HARD_FRAME_POINTER_REGNUM. */
2131
2132 #define ELIMINABLE_REGS \
2133 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2134 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2135 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2136 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2137 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2138 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2139
2140 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2141 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2142
2143 /* Allocate stack space for arguments at the beginning of each function. */
2144 #define ACCUMULATE_OUTGOING_ARGS 1
2145
2146 /* The argument pointer always points to the first argument. */
2147 #define FIRST_PARM_OFFSET(FNDECL) 0
2148
2149 /* o32 and o64 reserve stack space for all argument registers. */
2150 #define REG_PARM_STACK_SPACE(FNDECL) \
2151 (TARGET_OLDABI \
2152 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2153 : 0)
2154
2155 /* Define this if it is the responsibility of the caller to
2156 allocate the area reserved for arguments passed in registers.
2157 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2158 of this macro is to determine whether the space is included in
2159 `crtl->outgoing_args_size'. */
2160 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2161
2162 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2163 \f
2164 /* Symbolic macros for the registers used to return integer and floating
2165 point values. */
2166
2167 #define GP_RETURN (GP_REG_FIRST + 2)
2168 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2169
2170 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2171
2172 /* Symbolic macros for the first/last argument registers. */
2173
2174 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2175 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2176 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2177 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2178
2179 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2180 are used for returning complex double values in soft-float code, so $6 is the
2181 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2182 $gp itself as the temporary. */
2183 #define POST_CALL_TMP_REG \
2184 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2185
2186 /* 1 if N is a possible register number for function argument passing.
2187 We have no FP argument registers when soft-float. When FP registers
2188 are 32 bits, we can't directly reference the odd numbered ones. */
2189
2190 #define FUNCTION_ARG_REGNO_P(N) \
2191 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2192 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2193 && !fixed_regs[N])
2194 \f
2195 /* This structure has to cope with two different argument allocation
2196 schemes. Most MIPS ABIs view the arguments as a structure, of which
2197 the first N words go in registers and the rest go on the stack. If I
2198 < N, the Ith word might go in Ith integer argument register or in a
2199 floating-point register. For these ABIs, we only need to remember
2200 the offset of the current argument into the structure.
2201
2202 The EABI instead allocates the integer and floating-point arguments
2203 separately. The first N words of FP arguments go in FP registers,
2204 the rest go on the stack. Likewise, the first N words of the other
2205 arguments go in integer registers, and the rest go on the stack. We
2206 need to maintain three counts: the number of integer registers used,
2207 the number of floating-point registers used, and the number of words
2208 passed on the stack.
2209
2210 We could keep separate information for the two ABIs (a word count for
2211 the standard ABIs, and three separate counts for the EABI). But it
2212 seems simpler to view the standard ABIs as forms of EABI that do not
2213 allocate floating-point registers.
2214
2215 So for the standard ABIs, the first N words are allocated to integer
2216 registers, and mips_function_arg decides on an argument-by-argument
2217 basis whether that argument should really go in an integer register,
2218 or in a floating-point one. */
2219
2220 typedef struct mips_args {
2221 /* Always true for varargs functions. Otherwise true if at least
2222 one argument has been passed in an integer register. */
2223 int gp_reg_found;
2224
2225 /* The number of arguments seen so far. */
2226 unsigned int arg_number;
2227
2228 /* The number of integer registers used so far. For all ABIs except
2229 EABI, this is the number of words that have been added to the
2230 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2231 unsigned int num_gprs;
2232
2233 /* For EABI, the number of floating-point registers used so far. */
2234 unsigned int num_fprs;
2235
2236 /* The number of words passed on the stack. */
2237 unsigned int stack_words;
2238
2239 /* On the mips16, we need to keep track of which floating point
2240 arguments were passed in general registers, but would have been
2241 passed in the FP regs if this were a 32-bit function, so that we
2242 can move them to the FP regs if we wind up calling a 32-bit
2243 function. We record this information in fp_code, encoded in base
2244 four. A zero digit means no floating point argument, a one digit
2245 means an SFmode argument, and a two digit means a DFmode argument,
2246 and a three digit is not used. The low order digit is the first
2247 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2248 an SFmode argument. ??? A more sophisticated approach will be
2249 needed if MIPS_ABI != ABI_32. */
2250 int fp_code;
2251
2252 /* True if the function has a prototype. */
2253 int prototype;
2254 } CUMULATIVE_ARGS;
2255
2256 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2257 for a call to a function whose data type is FNTYPE.
2258 For a library call, FNTYPE is 0. */
2259
2260 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2261 mips_init_cumulative_args (&CUM, FNTYPE)
2262
2263 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2264 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2265
2266 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2267 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2268
2269 /* True if using EABI and varargs can be passed in floating-point
2270 registers. Under these conditions, we need a more complex form
2271 of va_list, which tracks GPR, FPR and stack arguments separately. */
2272 #define EABI_FLOAT_VARARGS_P \
2273 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2274
2275 \f
2276 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2277
2278 /* Treat LOC as a byte offset from the stack pointer and round it up
2279 to the next fully-aligned offset. */
2280 #define MIPS_STACK_ALIGN(LOC) \
2281 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2282
2283 \f
2284 /* Output assembler code to FILE to increment profiler label # LABELNO
2285 for profiling a function entry. */
2286
2287 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2288
2289 /* The profiler preserves all interesting registers, including $31. */
2290 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2291
2292 /* No mips port has ever used the profiler counter word, so don't emit it
2293 or the label for it. */
2294
2295 #define NO_PROFILE_COUNTERS 1
2296
2297 /* Define this macro if the code for function profiling should come
2298 before the function prologue. Normally, the profiling code comes
2299 after. */
2300
2301 /* #define PROFILE_BEFORE_PROLOGUE */
2302
2303 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2304 the stack pointer does not matter. The value is tested only in
2305 functions that have frame pointers.
2306 No definition is equivalent to always zero. */
2307
2308 #define EXIT_IGNORE_STACK 1
2309
2310 \f
2311 /* Trampolines are a block of code followed by two pointers. */
2312
2313 #define TRAMPOLINE_SIZE \
2314 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2315
2316 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2317 pointers from a single LUI base. */
2318
2319 #define TRAMPOLINE_ALIGNMENT 64
2320
2321 /* mips_trampoline_init calls this library function to flush
2322 program and data caches. */
2323
2324 #ifndef CACHE_FLUSH_FUNC
2325 #define CACHE_FLUSH_FUNC "_flush_cache"
2326 #endif
2327
2328 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2329 /* Flush both caches. We need to flush the data cache in case \
2330 the system has a write-back cache. */ \
2331 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2332 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2333 GEN_INT (3), TYPE_MODE (integer_type_node))
2334
2335 \f
2336 /* Addressing modes, and classification of registers for them. */
2337
2338 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2339 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2340 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2341 \f
2342 /* Maximum number of registers that can appear in a valid memory address. */
2343
2344 #define MAX_REGS_PER_ADDRESS 1
2345
2346 /* Check for constness inline but use mips_legitimate_address_p
2347 to check whether a constant really is an address. */
2348
2349 #define CONSTANT_ADDRESS_P(X) \
2350 (CONSTANT_P (X) && memory_address_p (SImode, X))
2351
2352 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2353 'the start of the function that this code is output in'. */
2354
2355 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2356 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2357 asm_fprintf ((FILE), "%U%s", \
2358 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2359 else \
2360 asm_fprintf ((FILE), "%U%s", (NAME))
2361 \f
2362 /* Flag to mark a function decl symbol that requires a long call. */
2363 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2364 #define SYMBOL_REF_LONG_CALL_P(X) \
2365 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2366
2367 /* This flag marks functions that cannot be lazily bound. */
2368 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2369 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2370 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2371
2372 /* True if we're generating a form of MIPS16 code in which jump tables
2373 are stored in the text section and encoded as 16-bit PC-relative
2374 offsets. This is only possible when general text loads are allowed,
2375 since the table access itself will be an "lh" instruction. If the
2376 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2377 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2378
2379 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2380
2381 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2382
2383 /* Only use short offsets if their range will not overflow. */
2384 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2385 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2386 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2387 : SImode)
2388
2389 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2390
2391 /* Define this as 1 if `char' should by default be signed; else as 0. */
2392 #ifndef DEFAULT_SIGNED_CHAR
2393 #define DEFAULT_SIGNED_CHAR 1
2394 #endif
2395
2396 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2397 we generally don't want to use them for copying arbitrary data.
2398 A single N-word move is usually the same cost as N single-word moves. */
2399 #define MOVE_MAX UNITS_PER_WORD
2400 #define MAX_MOVE_MAX 8
2401
2402 /* Define this macro as a C expression which is nonzero if
2403 accessing less than a word of memory (i.e. a `char' or a
2404 `short') is no faster than accessing a word of memory, i.e., if
2405 such access require more than one instruction or if there is no
2406 difference in cost between byte and (aligned) word loads.
2407
2408 On RISC machines, it tends to generate better code to define
2409 this as 1, since it avoids making a QI or HI mode register.
2410
2411 But, generating word accesses for -mips16 is generally bad as shifts
2412 (often extended) would be needed for byte accesses. */
2413 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2414
2415 /* Standard MIPS integer shifts truncate the shift amount to the
2416 width of the shifted operand. However, Loongson vector shifts
2417 do not truncate the shift amount at all. */
2418 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2419
2420 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2421 is done just by pretending it is already truncated. */
2422 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2423 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2424
2425
2426 /* Specify the machine mode that pointers have.
2427 After generation of rtl, the compiler makes no further distinction
2428 between pointers and any other objects of this machine mode. */
2429
2430 #ifndef Pmode
2431 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2432 #endif
2433
2434 /* Give call MEMs SImode since it is the "most permissive" mode
2435 for both 32-bit and 64-bit targets. */
2436
2437 #define FUNCTION_MODE SImode
2438
2439 \f
2440 /* We allocate $fcc registers by hand and can't cope with moves of
2441 CCmode registers to and from pseudos (or memory). */
2442 #define AVOID_CCMODE_COPIES
2443
2444 /* A C expression for the cost of a branch instruction. A value of
2445 1 is the default; other values are interpreted relative to that. */
2446
2447 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2448 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2449
2450 /* The MIPS port has several functions that return an instruction count.
2451 Multiplying the count by this value gives the number of bytes that
2452 the instructions occupy. */
2453 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2454
2455 /* The length of a NOP in bytes. */
2456 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2457
2458 /* If defined, modifies the length assigned to instruction INSN as a
2459 function of the context in which it is used. LENGTH is an lvalue
2460 that contains the initially computed length of the insn and should
2461 be updated with the correct length of the insn. */
2462 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2463 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2464
2465 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2466 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2467 its operands. */
2468 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2469 "%*" OPCODE "%?\t" OPERANDS "%/"
2470
2471 /* Return an asm string that forces INSN to be treated as an absolute
2472 J or JAL instruction instead of an assembler macro. */
2473 #define MIPS_ABSOLUTE_JUMP(INSN) \
2474 (TARGET_ABICALLS_PIC2 \
2475 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2476 : INSN)
2477
2478 /* Return the asm template for a call. INSN is the instruction's mnemonic
2479 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2480 number of the target. SIZE_OPNO is the operand number of the argument size
2481 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2482 -1 and the call is indirect, use the function symbol from the call
2483 attributes to attach a R_MIPS_JALR relocation to the call.
2484
2485 When generating GOT code without explicit relocation operators,
2486 all calls should use assembly macros. Otherwise, all indirect
2487 calls should use "jr" or "jalr"; we will arrange to restore $gp
2488 afterwards if necessary. Finally, we can only generate direct
2489 calls for -mabicalls by temporarily switching to non-PIC mode.
2490
2491 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2492 instruction is in the delay slot of jal(r). */
2493 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2494 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2495 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2496 : REG_P (OPERANDS[TARGET_OPNO]) \
2497 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2498 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2499 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2500 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2501 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2502 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2503 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2504 ? MIPS_ABSOLUTE_JUMP ("%*" INSN "%!\t%" #TARGET_OPNO "%/") \
2505 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/")) \
2506
2507 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2508 "jrc" when nop is in the delay slot of "jr". */
2509
2510 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2511 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2512 ? "%*j\t%" #OPNO "%/" \
2513 : REG_P (OPERANDS[OPNO]) \
2514 ? "%*jr%:\t%" #OPNO \
2515 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2516
2517 \f
2518 /* Control the assembler format that we output. */
2519
2520 /* Output to assembler file text saying following lines
2521 may contain character constants, extra white space, comments, etc. */
2522
2523 #ifndef ASM_APP_ON
2524 #define ASM_APP_ON " #APP\n"
2525 #endif
2526
2527 /* Output to assembler file text saying following lines
2528 no longer contain unusual constructs. */
2529
2530 #ifndef ASM_APP_OFF
2531 #define ASM_APP_OFF " #NO_APP\n"
2532 #endif
2533
2534 #define REGISTER_NAMES \
2535 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2536 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2537 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2538 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2539 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2540 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2541 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2542 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2543 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2544 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2545 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2546 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2547 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2548 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2549 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2550 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2551 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2552 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2553 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2554 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2555 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2556 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2557 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2558 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2559
2560 /* List the "software" names for each register. Also list the numerical
2561 names for $fp and $sp. */
2562
2563 #define ADDITIONAL_REGISTER_NAMES \
2564 { \
2565 { "$29", 29 + GP_REG_FIRST }, \
2566 { "$30", 30 + GP_REG_FIRST }, \
2567 { "at", 1 + GP_REG_FIRST }, \
2568 { "v0", 2 + GP_REG_FIRST }, \
2569 { "v1", 3 + GP_REG_FIRST }, \
2570 { "a0", 4 + GP_REG_FIRST }, \
2571 { "a1", 5 + GP_REG_FIRST }, \
2572 { "a2", 6 + GP_REG_FIRST }, \
2573 { "a3", 7 + GP_REG_FIRST }, \
2574 { "t0", 8 + GP_REG_FIRST }, \
2575 { "t1", 9 + GP_REG_FIRST }, \
2576 { "t2", 10 + GP_REG_FIRST }, \
2577 { "t3", 11 + GP_REG_FIRST }, \
2578 { "t4", 12 + GP_REG_FIRST }, \
2579 { "t5", 13 + GP_REG_FIRST }, \
2580 { "t6", 14 + GP_REG_FIRST }, \
2581 { "t7", 15 + GP_REG_FIRST }, \
2582 { "s0", 16 + GP_REG_FIRST }, \
2583 { "s1", 17 + GP_REG_FIRST }, \
2584 { "s2", 18 + GP_REG_FIRST }, \
2585 { "s3", 19 + GP_REG_FIRST }, \
2586 { "s4", 20 + GP_REG_FIRST }, \
2587 { "s5", 21 + GP_REG_FIRST }, \
2588 { "s6", 22 + GP_REG_FIRST }, \
2589 { "s7", 23 + GP_REG_FIRST }, \
2590 { "t8", 24 + GP_REG_FIRST }, \
2591 { "t9", 25 + GP_REG_FIRST }, \
2592 { "k0", 26 + GP_REG_FIRST }, \
2593 { "k1", 27 + GP_REG_FIRST }, \
2594 { "gp", 28 + GP_REG_FIRST }, \
2595 { "sp", 29 + GP_REG_FIRST }, \
2596 { "fp", 30 + GP_REG_FIRST }, \
2597 { "ra", 31 + GP_REG_FIRST } \
2598 }
2599
2600 #define DBR_OUTPUT_SEQEND(STREAM) \
2601 do \
2602 { \
2603 /* Undo the effect of '%*'. */ \
2604 mips_pop_asm_switch (&mips_nomacro); \
2605 mips_pop_asm_switch (&mips_noreorder); \
2606 /* Emit a blank line after the delay slot for emphasis. */ \
2607 fputs ("\n", STREAM); \
2608 } \
2609 while (0)
2610
2611 /* The MIPS implementation uses some labels for its own purpose. The
2612 following lists what labels are created, and are all formed by the
2613 pattern $L[a-z].*. The machine independent portion of GCC creates
2614 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2615
2616 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2617 $Lb[0-9]+ Begin blocks for MIPS debug support
2618 $Lc[0-9]+ Label for use in s<xx> operation.
2619 $Le[0-9]+ End blocks for MIPS debug support */
2620
2621 #undef ASM_DECLARE_OBJECT_NAME
2622 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2623 mips_declare_object (STREAM, NAME, "", ":\n")
2624
2625 /* Globalizing directive for a label. */
2626 #define GLOBAL_ASM_OP "\t.globl\t"
2627
2628 /* This says how to define a global common symbol. */
2629
2630 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2631
2632 /* This says how to define a local common symbol (i.e., not visible to
2633 linker). */
2634
2635 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2636 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2637 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2638 #endif
2639
2640 /* This says how to output an external. It would be possible not to
2641 output anything and let undefined symbol become external. However
2642 the assembler uses length information on externals to allocate in
2643 data/sdata bss/sbss, thereby saving exec time. */
2644
2645 #undef ASM_OUTPUT_EXTERNAL
2646 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2647 mips_output_external(STREAM,DECL,NAME)
2648
2649 /* This is how to declare a function name. The actual work of
2650 emitting the label is moved to function_prologue, so that we can
2651 get the line number correctly emitted before the .ent directive,
2652 and after any .file directives. Define as empty so that the function
2653 is not declared before the .ent directive elsewhere. */
2654
2655 #undef ASM_DECLARE_FUNCTION_NAME
2656 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2657
2658 /* This is how to store into the string LABEL
2659 the symbol_ref name of an internal numbered label where
2660 PREFIX is the class of label and NUM is the number within the class.
2661 This is suitable for output with `assemble_name'. */
2662
2663 #undef ASM_GENERATE_INTERNAL_LABEL
2664 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2665 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2666
2667 /* Print debug labels as "foo = ." rather than "foo:" because they should
2668 represent a byte pointer rather than an ISA-encoded address. This is
2669 particularly important for code like:
2670
2671 $LFBxxx = .
2672 .cfi_startproc
2673 ...
2674 .section .gcc_except_table,...
2675 ...
2676 .uleb128 foo-$LFBxxx
2677
2678 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2679 likewise a byte pointer rather than an ISA-encoded address.
2680
2681 At the time of writing, this hook is not used for the function end
2682 label:
2683
2684 $LFExxx:
2685 .end foo
2686
2687 But this doesn't matter, because GAS doesn't treat a pre-.end label
2688 as a MIPS16 one anyway. */
2689
2690 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2691 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2692
2693 /* This is how to output an element of a case-vector that is absolute. */
2694
2695 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2696 fprintf (STREAM, "\t%s\t%sL%d\n", \
2697 ptr_mode == DImode ? ".dword" : ".word", \
2698 LOCAL_LABEL_PREFIX, \
2699 VALUE)
2700
2701 /* This is how to output an element of a case-vector. We can make the
2702 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2703 is supported. */
2704
2705 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2706 do { \
2707 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2708 { \
2709 if (GET_MODE (BODY) == HImode) \
2710 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2711 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2712 else \
2713 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2714 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2715 } \
2716 else if (TARGET_GPWORD) \
2717 fprintf (STREAM, "\t%s\t%sL%d\n", \
2718 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2719 LOCAL_LABEL_PREFIX, VALUE); \
2720 else if (TARGET_RTP_PIC) \
2721 { \
2722 /* Make the entry relative to the start of the function. */ \
2723 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2724 fprintf (STREAM, "\t%s\t%sL%d-", \
2725 Pmode == DImode ? ".dword" : ".word", \
2726 LOCAL_LABEL_PREFIX, VALUE); \
2727 assemble_name (STREAM, XSTR (fnsym, 0)); \
2728 fprintf (STREAM, "\n"); \
2729 } \
2730 else \
2731 fprintf (STREAM, "\t%s\t%sL%d\n", \
2732 ptr_mode == DImode ? ".dword" : ".word", \
2733 LOCAL_LABEL_PREFIX, VALUE); \
2734 } while (0)
2735
2736 /* This is how to output an assembler line
2737 that says to advance the location counter
2738 to a multiple of 2**LOG bytes. */
2739
2740 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2741 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2742
2743 /* This is how to output an assembler line to advance the location
2744 counter by SIZE bytes. */
2745
2746 #undef ASM_OUTPUT_SKIP
2747 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2748 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2749
2750 /* This is how to output a string. */
2751 #undef ASM_OUTPUT_ASCII
2752 #define ASM_OUTPUT_ASCII mips_output_ascii
2753
2754 \f
2755 /* Default to -G 8 */
2756 #ifndef MIPS_DEFAULT_GVALUE
2757 #define MIPS_DEFAULT_GVALUE 8
2758 #endif
2759
2760 /* Define the strings to put out for each section in the object file. */
2761 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2762 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2763
2764 #undef READONLY_DATA_SECTION_ASM_OP
2765 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2766 \f
2767 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2768 do \
2769 { \
2770 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2771 TARGET_64BIT ? "daddiu" : "addiu", \
2772 reg_names[STACK_POINTER_REGNUM], \
2773 reg_names[STACK_POINTER_REGNUM], \
2774 TARGET_64BIT ? "sd" : "sw", \
2775 reg_names[REGNO], \
2776 reg_names[STACK_POINTER_REGNUM]); \
2777 } \
2778 while (0)
2779
2780 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2781 do \
2782 { \
2783 mips_push_asm_switch (&mips_noreorder); \
2784 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2785 TARGET_64BIT ? "ld" : "lw", \
2786 reg_names[REGNO], \
2787 reg_names[STACK_POINTER_REGNUM], \
2788 TARGET_64BIT ? "daddu" : "addu", \
2789 reg_names[STACK_POINTER_REGNUM], \
2790 reg_names[STACK_POINTER_REGNUM]); \
2791 mips_pop_asm_switch (&mips_noreorder); \
2792 } \
2793 while (0)
2794
2795 /* How to start an assembler comment.
2796 The leading space is important (the mips native assembler requires it). */
2797 #ifndef ASM_COMMENT_START
2798 #define ASM_COMMENT_START " #"
2799 #endif
2800 \f
2801 #undef SIZE_TYPE
2802 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2803
2804 #undef PTRDIFF_TYPE
2805 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2806
2807 /* The maximum number of bytes that can be copied by one iteration of
2808 a movmemsi loop; see mips_block_move_loop. */
2809 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2810 (UNITS_PER_WORD * 4)
2811
2812 /* The maximum number of bytes that can be copied by a straight-line
2813 implementation of movmemsi; see mips_block_move_straight. We want
2814 to make sure that any loop-based implementation will iterate at
2815 least twice. */
2816 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2817 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2818
2819 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2820 values were determined experimentally by benchmarking with CSiBE.
2821 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2822 for o32 where we have to restore $gp afterwards as well as make an
2823 indirect call), but in practice, bumping this up higher for
2824 TARGET_ABICALLS doesn't make much difference to code size. */
2825
2826 #define MIPS_CALL_RATIO 8
2827
2828 /* Any loop-based implementation of movmemsi will have at least
2829 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2830 moves, so allow individual copies of fewer elements.
2831
2832 When movmemsi is not available, use a value approximating
2833 the length of a memcpy call sequence, so that move_by_pieces
2834 will generate inline code if it is shorter than a function call.
2835 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2836 we'll have to generate a load/store pair for each, halve the
2837 value of MIPS_CALL_RATIO to take that into account. */
2838
2839 #define MOVE_RATIO(speed) \
2840 (HAVE_movmemsi \
2841 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2842 : MIPS_CALL_RATIO / 2)
2843
2844 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2845 mips_move_by_pieces_p (SIZE, ALIGN)
2846
2847 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2848 of the length of a memset call, but use the default otherwise. */
2849
2850 #define CLEAR_RATIO(speed)\
2851 ((speed) ? 15 : MIPS_CALL_RATIO)
2852
2853 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2854 optimizing for size adjust the ratio to account for the overhead of
2855 loading the constant and replicating it across the word. */
2856
2857 #define SET_RATIO(speed) \
2858 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2859
2860 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2861 mips_store_by_pieces_p (SIZE, ALIGN)
2862 \f
2863 /* Since the bits of the _init and _fini function is spread across
2864 many object files, each potentially with its own GP, we must assume
2865 we need to load our GP. We don't preserve $gp or $ra, since each
2866 init/fini chunk is supposed to initialize $gp, and crti/crtn
2867 already take care of preserving $ra and, when appropriate, $gp. */
2868 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2869 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2870 asm (SECTION_OP "\n\
2871 .set push\n\
2872 .set nomips16\n\
2873 .set noreorder\n\
2874 bal 1f\n\
2875 nop\n\
2876 1: .cpload $31\n\
2877 .set reorder\n\
2878 jal " USER_LABEL_PREFIX #FUNC "\n\
2879 .set pop\n\
2880 " TEXT_SECTION_ASM_OP);
2881 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2882 || (defined _ABI64 && _MIPS_SIM == _ABI64))
2883 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2884 asm (SECTION_OP "\n\
2885 .set push\n\
2886 .set nomips16\n\
2887 .set noreorder\n\
2888 bal 1f\n\
2889 nop\n\
2890 1: .set reorder\n\
2891 .cpsetup $31, $2, 1b\n\
2892 jal " USER_LABEL_PREFIX #FUNC "\n\
2893 .set pop\n\
2894 " TEXT_SECTION_ASM_OP);
2895 #endif
2896
2897 #ifndef HAVE_AS_TLS
2898 #define HAVE_AS_TLS 0
2899 #endif
2900
2901 #ifndef HAVE_AS_NAN
2902 #define HAVE_AS_NAN 0
2903 #endif
2904
2905 #ifndef USED_FOR_TARGET
2906 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2907 struct mips_asm_switch {
2908 /* The FOO in the description above. */
2909 const char *name;
2910
2911 /* The current block nesting level, or 0 if we aren't in a block. */
2912 int nesting_level;
2913 };
2914
2915 extern const enum reg_class mips_regno_to_class[];
2916 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2917 extern const char *current_function_file; /* filename current function is in */
2918 extern int num_source_filenames; /* current .file # */
2919 extern struct mips_asm_switch mips_noreorder;
2920 extern struct mips_asm_switch mips_nomacro;
2921 extern struct mips_asm_switch mips_noat;
2922 extern int mips_dbx_regno[];
2923 extern int mips_dwarf_regno[];
2924 extern bool mips_split_p[];
2925 extern bool mips_split_hi_p[];
2926 extern bool mips_use_pcrel_pool_p[];
2927 extern const char *mips_lo_relocs[];
2928 extern const char *mips_hi_relocs[];
2929 extern enum processor mips_arch; /* which cpu to codegen for */
2930 extern enum processor mips_tune; /* which cpu to schedule for */
2931 extern int mips_isa; /* architectural level */
2932 extern int mips_isa_rev;
2933 extern const struct mips_cpu_info *mips_arch_info;
2934 extern const struct mips_cpu_info *mips_tune_info;
2935 extern unsigned int mips_base_compression_flags;
2936 extern GTY(()) struct target_globals *mips16_globals;
2937 #endif
2938
2939 /* Enable querying of DFA units. */
2940 #define CPU_UNITS_QUERY 1
2941
2942 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2943 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2944
2945 /* As on most targets, we want the .eh_frame section to be read-only where
2946 possible. And as on most targets, this means two things:
2947
2948 (a) Non-locally-binding pointers must have an indirect encoding,
2949 so that the addresses in the .eh_frame section itself become
2950 locally-binding.
2951
2952 (b) A shared library's .eh_frame section must encode locally-binding
2953 pointers in a relative (relocation-free) form.
2954
2955 However, MIPS has traditionally not allowed directives like:
2956
2957 .long x-.
2958
2959 in cases where "x" is in a different section, or is not defined in the
2960 same assembly file. We are therefore unable to emit the PC-relative
2961 form required by (b) at assembly time.
2962
2963 Fortunately, the linker is able to convert absolute addresses into
2964 PC-relative addresses on our behalf. Unfortunately, only certain
2965 versions of the linker know how to do this for indirect pointers,
2966 and for personality data. We must fall back on using writable
2967 .eh_frame sections for shared libraries if the linker does not
2968 support this feature. */
2969 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2970 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2971
2972 /* For switching between MIPS16 and non-MIPS16 modes. */
2973 #define SWITCHABLE_TARGET 1
2974
2975 /* Several named MIPS patterns depend on Pmode. These patterns have the
2976 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2977 Add the appropriate suffix to generator function NAME and invoke it
2978 with arguments ARGS. */
2979 #define PMODE_INSN(NAME, ARGS) \
2980 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)