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mips.opt (meva): New.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS64 (mips_isa == 64)
212 #define ISA_MIPS64R2 (mips_isa == 65)
213
214 /* Architecture target defines. */
215 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
216 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
217 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
218 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
219 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
220 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
221 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
222 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
223 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
224 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
225 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
226 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
227 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
228 || mips_arch == PROCESSOR_OCTEON2)
229 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
230 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
231 || mips_arch == PROCESSOR_SB1A)
232 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
233 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
234
235 /* Scheduling target defines. */
236 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
237 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
238 || mips_tune == PROCESSOR_24KF2_1 \
239 || mips_tune == PROCESSOR_24KF1_1)
240 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
241 || mips_tune == PROCESSOR_74KF2_1 \
242 || mips_tune == PROCESSOR_74KF1_1 \
243 || mips_tune == PROCESSOR_74KF3_2)
244 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
245 || mips_tune == PROCESSOR_LOONGSON_2F)
246 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
247 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
248 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
249 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
250 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
251 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
252 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
253 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
254 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
255 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
256 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
257 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
258 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
259 || mips_tune == PROCESSOR_OCTEON2)
260 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
261 || mips_tune == PROCESSOR_SB1A)
262
263 /* Whether vector modes and intrinsics for ST Microelectronics
264 Loongson-2E/2F processors should be enabled. In o32 pairs of
265 floating-point registers provide 64-bit values. */
266 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
267 && (TARGET_LOONGSON_2EF \
268 || TARGET_LOONGSON_3A))
269
270 /* True if the pre-reload scheduler should try to create chains of
271 multiply-add or multiply-subtract instructions. For example,
272 suppose we have:
273
274 t1 = a * b
275 t2 = t1 + c * d
276 t3 = e * f
277 t4 = t3 - g * h
278
279 t1 will have a higher priority than t2 and t3 will have a higher
280 priority than t4. However, before reload, there is no dependence
281 between t1 and t3, and they can often have similar priorities.
282 The scheduler will then tend to prefer:
283
284 t1 = a * b
285 t3 = e * f
286 t2 = t1 + c * d
287 t4 = t3 - g * h
288
289 which stops us from making full use of macc/madd-style instructions.
290 This sort of situation occurs frequently in Fourier transforms and
291 in unrolled loops.
292
293 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
294 queue so that chained multiply-add and multiply-subtract instructions
295 appear ahead of any other instruction that is likely to clobber lo.
296 In the example above, if t2 and t3 become ready at the same time,
297 the code ensures that t2 is scheduled first.
298
299 Multiply-accumulate instructions are a bigger win for some targets
300 than others, so this macro is defined on an opt-in basis. */
301 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
302 || TUNE_MIPS4120 \
303 || TUNE_MIPS4130 \
304 || TUNE_24K)
305
306 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
307 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
308
309 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
310 directly accessible, while the command-line options select
311 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
312 in use. */
313 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
314 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
315
316 /* False if SC acts as a memory barrier with respect to itself,
317 otherwise a SYNC will be emitted after SC for atomic operations
318 that require ordering between the SC and following loads and
319 stores. It does not tell anything about ordering of loads and
320 stores prior to and following the SC, only about the SC itself and
321 those loads and stores follow it. */
322 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
323
324 /* Define preprocessor macros for the -march and -mtune options.
325 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
326 processor. If INFO's canonical name is "foo", define PREFIX to
327 be "foo", and define an additional macro PREFIX_FOO. */
328 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
329 do \
330 { \
331 char *macro, *p; \
332 \
333 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
334 for (p = macro; *p != 0; p++) \
335 if (*p == '+') \
336 *p = 'P'; \
337 else \
338 *p = TOUPPER (*p); \
339 \
340 builtin_define (macro); \
341 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
342 free (macro); \
343 } \
344 while (0)
345
346 /* Target CPU builtins. */
347 #define TARGET_CPU_CPP_BUILTINS() \
348 do \
349 { \
350 builtin_assert ("machine=mips"); \
351 builtin_assert ("cpu=mips"); \
352 builtin_define ("__mips__"); \
353 builtin_define ("_mips"); \
354 \
355 /* We do this here because __mips is defined below and so we \
356 can't use builtin_define_std. We don't ever want to define \
357 "mips" for VxWorks because some of the VxWorks headers \
358 construct include filenames from a root directory macro, \
359 an architecture macro and a filename, where the architecture \
360 macro expands to 'mips'. If we define 'mips' to 1, the \
361 architecture macro expands to 1 as well. */ \
362 if (!flag_iso && !TARGET_VXWORKS) \
363 builtin_define ("mips"); \
364 \
365 if (TARGET_64BIT) \
366 builtin_define ("__mips64"); \
367 \
368 /* Treat _R3000 and _R4000 like register-size \
369 defines, which is how they've historically \
370 been used. */ \
371 if (TARGET_64BIT) \
372 { \
373 builtin_define_std ("R4000"); \
374 builtin_define ("_R4000"); \
375 } \
376 else \
377 { \
378 builtin_define_std ("R3000"); \
379 builtin_define ("_R3000"); \
380 } \
381 \
382 if (TARGET_FLOAT64) \
383 builtin_define ("__mips_fpr=64"); \
384 else \
385 builtin_define ("__mips_fpr=32"); \
386 \
387 if (mips_base_compression_flags & MASK_MIPS16) \
388 builtin_define ("__mips16"); \
389 \
390 if (TARGET_MIPS3D) \
391 builtin_define ("__mips3d"); \
392 \
393 if (TARGET_SMARTMIPS) \
394 builtin_define ("__mips_smartmips"); \
395 \
396 if (mips_base_compression_flags & MASK_MICROMIPS) \
397 builtin_define ("__mips_micromips"); \
398 \
399 if (TARGET_MCU) \
400 builtin_define ("__mips_mcu"); \
401 \
402 if (TARGET_EVA) \
403 builtin_define ("__mips_eva"); \
404 \
405 if (TARGET_DSP) \
406 { \
407 builtin_define ("__mips_dsp"); \
408 if (TARGET_DSPR2) \
409 { \
410 builtin_define ("__mips_dspr2"); \
411 builtin_define ("__mips_dsp_rev=2"); \
412 } \
413 else \
414 builtin_define ("__mips_dsp_rev=1"); \
415 } \
416 \
417 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
418 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
419 \
420 if (ISA_MIPS1) \
421 { \
422 builtin_define ("__mips=1"); \
423 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
424 } \
425 else if (ISA_MIPS2) \
426 { \
427 builtin_define ("__mips=2"); \
428 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
429 } \
430 else if (ISA_MIPS3) \
431 { \
432 builtin_define ("__mips=3"); \
433 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
434 } \
435 else if (ISA_MIPS4) \
436 { \
437 builtin_define ("__mips=4"); \
438 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
439 } \
440 else if (ISA_MIPS32) \
441 { \
442 builtin_define ("__mips=32"); \
443 builtin_define ("__mips_isa_rev=1"); \
444 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
445 } \
446 else if (ISA_MIPS32R2) \
447 { \
448 builtin_define ("__mips=32"); \
449 builtin_define ("__mips_isa_rev=2"); \
450 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
451 } \
452 else if (ISA_MIPS64) \
453 { \
454 builtin_define ("__mips=64"); \
455 builtin_define ("__mips_isa_rev=1"); \
456 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
457 } \
458 else if (ISA_MIPS64R2) \
459 { \
460 builtin_define ("__mips=64"); \
461 builtin_define ("__mips_isa_rev=2"); \
462 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
463 } \
464 \
465 switch (mips_abi) \
466 { \
467 case ABI_32: \
468 builtin_define ("_ABIO32=1"); \
469 builtin_define ("_MIPS_SIM=_ABIO32"); \
470 break; \
471 \
472 case ABI_N32: \
473 builtin_define ("_ABIN32=2"); \
474 builtin_define ("_MIPS_SIM=_ABIN32"); \
475 break; \
476 \
477 case ABI_64: \
478 builtin_define ("_ABI64=3"); \
479 builtin_define ("_MIPS_SIM=_ABI64"); \
480 break; \
481 \
482 case ABI_O64: \
483 builtin_define ("_ABIO64=4"); \
484 builtin_define ("_MIPS_SIM=_ABIO64"); \
485 break; \
486 } \
487 \
488 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
489 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
490 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
491 builtin_define_with_int_value ("_MIPS_FPSET", \
492 32 / MAX_FPRS_PER_FMT); \
493 \
494 /* These defines reflect the ABI in use, not whether the \
495 FPU is directly accessible. */ \
496 if (TARGET_NO_FLOAT) \
497 builtin_define ("__mips_no_float"); \
498 else if (TARGET_HARD_FLOAT_ABI) \
499 builtin_define ("__mips_hard_float"); \
500 else \
501 builtin_define ("__mips_soft_float"); \
502 \
503 if (TARGET_SINGLE_FLOAT) \
504 builtin_define ("__mips_single_float"); \
505 \
506 if (TARGET_PAIRED_SINGLE_FLOAT) \
507 builtin_define ("__mips_paired_single_float"); \
508 \
509 if (TARGET_BIG_ENDIAN) \
510 { \
511 builtin_define_std ("MIPSEB"); \
512 builtin_define ("_MIPSEB"); \
513 } \
514 else \
515 { \
516 builtin_define_std ("MIPSEL"); \
517 builtin_define ("_MIPSEL"); \
518 } \
519 \
520 /* Whether calls should go through $25. The separate __PIC__ \
521 macro indicates whether abicalls code might use a GOT. */ \
522 if (TARGET_ABICALLS) \
523 builtin_define ("__mips_abicalls"); \
524 \
525 /* Whether Loongson vector modes are enabled. */ \
526 if (TARGET_LOONGSON_VECTORS) \
527 builtin_define ("__mips_loongson_vector_rev"); \
528 \
529 /* Historical Octeon macro. */ \
530 if (TARGET_OCTEON) \
531 builtin_define ("__OCTEON__"); \
532 \
533 if (TARGET_SYNCI) \
534 builtin_define ("__mips_synci"); \
535 \
536 /* Macros dependent on the C dialect. */ \
537 if (preprocessing_asm_p ()) \
538 { \
539 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
540 builtin_define ("_LANGUAGE_ASSEMBLY"); \
541 } \
542 else if (c_dialect_cxx ()) \
543 { \
544 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
545 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
546 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
547 } \
548 else \
549 { \
550 builtin_define_std ("LANGUAGE_C"); \
551 builtin_define ("_LANGUAGE_C"); \
552 } \
553 if (c_dialect_objc ()) \
554 { \
555 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
556 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
557 /* Bizarre, but retained for backwards compatibility. */ \
558 builtin_define_std ("LANGUAGE_C"); \
559 builtin_define ("_LANGUAGE_C"); \
560 } \
561 \
562 if (mips_abi == ABI_EABI) \
563 builtin_define ("__mips_eabi"); \
564 \
565 if (TARGET_CACHE_BUILTIN) \
566 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
567 } \
568 while (0)
569
570 /* Default target_flags if no switches are specified */
571
572 #ifndef TARGET_DEFAULT
573 #define TARGET_DEFAULT 0
574 #endif
575
576 #ifndef TARGET_CPU_DEFAULT
577 #define TARGET_CPU_DEFAULT 0
578 #endif
579
580 #ifndef TARGET_ENDIAN_DEFAULT
581 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
582 #endif
583
584 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
585 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
586 #endif
587
588 #ifdef IN_LIBGCC2
589 #undef TARGET_64BIT
590 /* Make this compile time constant for libgcc2 */
591 #ifdef __mips64
592 #define TARGET_64BIT 1
593 #else
594 #define TARGET_64BIT 0
595 #endif
596 #endif /* IN_LIBGCC2 */
597
598 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
599 when compiled with hardware floating point. This is because MIPS16
600 code cannot save and restore the floating-point registers, which is
601 important if in a mixed MIPS16/non-MIPS16 environment. */
602
603 #ifdef IN_LIBGCC2
604 #if __mips_hard_float
605 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
606 #endif
607 #endif /* IN_LIBGCC2 */
608
609 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
610
611 #ifndef MULTILIB_ENDIAN_DEFAULT
612 #if TARGET_ENDIAN_DEFAULT == 0
613 #define MULTILIB_ENDIAN_DEFAULT "EL"
614 #else
615 #define MULTILIB_ENDIAN_DEFAULT "EB"
616 #endif
617 #endif
618
619 #ifndef MULTILIB_ISA_DEFAULT
620 #if MIPS_ISA_DEFAULT == 1
621 #define MULTILIB_ISA_DEFAULT "mips1"
622 #elif MIPS_ISA_DEFAULT == 2
623 #define MULTILIB_ISA_DEFAULT "mips2"
624 #elif MIPS_ISA_DEFAULT == 3
625 #define MULTILIB_ISA_DEFAULT "mips3"
626 #elif MIPS_ISA_DEFAULT == 4
627 #define MULTILIB_ISA_DEFAULT "mips4"
628 #elif MIPS_ISA_DEFAULT == 32
629 #define MULTILIB_ISA_DEFAULT "mips32"
630 #elif MIPS_ISA_DEFAULT == 33
631 #define MULTILIB_ISA_DEFAULT "mips32r2"
632 #elif MIPS_ISA_DEFAULT == 64
633 #define MULTILIB_ISA_DEFAULT "mips64"
634 #elif MIPS_ISA_DEFAULT == 65
635 #define MULTILIB_ISA_DEFAULT "mips64r2"
636 #else
637 #define MULTILIB_ISA_DEFAULT "mips1"
638 #endif
639 #endif
640
641 #ifndef MIPS_ABI_DEFAULT
642 #define MIPS_ABI_DEFAULT ABI_32
643 #endif
644
645 /* Use the most portable ABI flag for the ASM specs. */
646
647 #if MIPS_ABI_DEFAULT == ABI_32
648 #define MULTILIB_ABI_DEFAULT "mabi=32"
649 #elif MIPS_ABI_DEFAULT == ABI_O64
650 #define MULTILIB_ABI_DEFAULT "mabi=o64"
651 #elif MIPS_ABI_DEFAULT == ABI_N32
652 #define MULTILIB_ABI_DEFAULT "mabi=n32"
653 #elif MIPS_ABI_DEFAULT == ABI_64
654 #define MULTILIB_ABI_DEFAULT "mabi=64"
655 #elif MIPS_ABI_DEFAULT == ABI_EABI
656 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
657 #endif
658
659 #ifndef MULTILIB_DEFAULTS
660 #define MULTILIB_DEFAULTS \
661 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
662 #endif
663
664 /* We must pass -EL to the linker by default for little endian embedded
665 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
666 linker will default to using big-endian output files. The OUTPUT_FORMAT
667 line must be in the linker script, otherwise -EB/-EL will not work. */
668
669 #ifndef ENDIAN_SPEC
670 #if TARGET_ENDIAN_DEFAULT == 0
671 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
672 #else
673 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
674 #endif
675 #endif
676
677 /* A spec condition that matches all non-mips16 -mips arguments. */
678
679 #define MIPS_ISA_LEVEL_OPTION_SPEC \
680 "mips1|mips2|mips3|mips4|mips32*|mips64*"
681
682 /* A spec condition that matches all non-mips16 architecture arguments. */
683
684 #define MIPS_ARCH_OPTION_SPEC \
685 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
686
687 /* A spec that infers a -mips argument from an -march argument,
688 or injects the default if no architecture is specified. */
689
690 #define MIPS_ISA_LEVEL_SPEC \
691 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
692 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
693 %{march=mips2|march=r6000:-mips2} \
694 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
695 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
696 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
697 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
698 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
699 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
700 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
701 |march=xlr|march=loongson3a: -mips64} \
702 %{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
703 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
704
705 /* A spec that infers a -mhard-float or -msoft-float setting from an
706 -march argument. Note that soft-float and hard-float code are not
707 link-compatible. */
708
709 #define MIPS_ARCH_FLOAT_SPEC \
710 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
711 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
712 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
713 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
714 march=*: -mhard-float}"
715
716 /* A spec condition that matches 32-bit options. It only works if
717 MIPS_ISA_LEVEL_SPEC has been applied. */
718
719 #define MIPS_32BIT_OPTION_SPEC \
720 "mips1|mips2|mips32*|mgp32"
721
722 /* Infer a -msynci setting from a -mips argument, on the assumption that
723 -msynci is desired where possible. */
724 #define MIPS_ISA_SYNCI_SPEC \
725 "%{msynci|mno-synci:;:%{mips32r2|mips64r2:-msynci;:-mno-synci}}"
726
727 #if (MIPS_ABI_DEFAULT == ABI_O64 \
728 || MIPS_ABI_DEFAULT == ABI_N32 \
729 || MIPS_ABI_DEFAULT == ABI_64)
730 #define OPT_ARCH64 "mabi=32|mgp32:;"
731 #define OPT_ARCH32 "mabi=32|mgp32"
732 #else
733 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
734 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
735 #endif
736
737 /* Support for a compile-time default CPU, et cetera. The rules are:
738 --with-arch is ignored if -march is specified or a -mips is specified
739 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
740 --with-tune is ignored if -mtune is specified; likewise
741 --with-tune-32 and --with-tune-64.
742 --with-abi is ignored if -mabi is specified.
743 --with-float is ignored if -mhard-float or -msoft-float are
744 specified.
745 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
746 specified. */
747 #define OPTION_DEFAULT_SPECS \
748 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
749 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
750 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
751 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
752 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
753 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
754 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
755 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
756 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
757 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
758 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
759 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
760
761 /* A spec that infers the -mdsp setting from an -march argument. */
762 #define BASE_DRIVER_SELF_SPECS \
763 "%{!mno-dsp: \
764 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
765 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
766
767 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
768
769 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
770 && ISA_HAS_COND_TRAP)
771
772 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
773
774 /* True if the ABI can only work with 64-bit integer registers. We
775 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
776 otherwise floating-point registers must also be 64-bit. */
777 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
778
779 /* Likewise for 32-bit regs. */
780 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
781
782 /* True if the file format uses 64-bit symbols. At present, this is
783 only true for n64, which uses 64-bit ELF. */
784 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
785
786 /* True if symbols are 64 bits wide. This is usually determined by
787 the ABI's file format, but it can be overridden by -msym32. Note that
788 overriding the size with -msym32 changes the ABI of relocatable objects,
789 although it doesn't change the ABI of a fully-linked object. */
790 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
791 && Pmode == DImode \
792 && !TARGET_SYM32)
793
794 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
795 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
796 || ISA_MIPS4 \
797 || ISA_MIPS64 \
798 || ISA_MIPS64R2)
799
800 /* ISA has branch likely instructions (e.g. mips2). */
801 /* Disable branchlikely for tx39 until compare rewrite. They haven't
802 been generated up to this point. */
803 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
804
805 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
806 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
807 || TARGET_MIPS5400 \
808 || TARGET_MIPS5500 \
809 || TARGET_MIPS7000 \
810 || TARGET_MIPS9000 \
811 || TARGET_MAD \
812 || ISA_MIPS32 \
813 || ISA_MIPS32R2 \
814 || ISA_MIPS64 \
815 || ISA_MIPS64R2) \
816 && !TARGET_MIPS16)
817
818 /* ISA has a three-operand multiplication instruction. */
819 #define ISA_HAS_DMUL3 (TARGET_64BIT \
820 && TARGET_OCTEON \
821 && !TARGET_MIPS16)
822
823 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
824 || TARGET_LOONGSON_3A) \
825 && !TARGET_MIPS16)
826
827 /* ISA has the floating-point conditional move instructions introduced
828 in mips4. */
829 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
830 || ISA_MIPS32 \
831 || ISA_MIPS32R2 \
832 || ISA_MIPS64 \
833 || ISA_MIPS64R2) \
834 && !TARGET_MIPS5500 \
835 && !TARGET_MIPS16)
836
837 /* ISA has the integer conditional move instructions introduced in mips4 and
838 ST Loongson 2E/2F. */
839 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
840
841 /* ISA has LDC1 and SDC1. */
842 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
843
844 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
845 branch on CC, and move (both FP and non-FP) on CC. */
846 #define ISA_HAS_8CC (ISA_MIPS4 \
847 || ISA_MIPS32 \
848 || ISA_MIPS32R2 \
849 || ISA_MIPS64 \
850 || ISA_MIPS64R2)
851
852 /* This is a catch all for other mips4 instructions: indexed load, the
853 FP madd and msub instructions, and the FP recip and recip sqrt
854 instructions. */
855 #define ISA_HAS_FP4 ((ISA_MIPS4 \
856 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
857 || ISA_MIPS64 \
858 || ISA_MIPS64R2) \
859 && !TARGET_MIPS16)
860
861 /* ISA has paired-single instructions. */
862 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
863
864 /* ISA has conditional trap instructions. */
865 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
866 && !TARGET_MIPS16)
867
868 /* ISA has integer multiply-accumulate instructions, madd and msub. */
869 #define ISA_HAS_MADD_MSUB (ISA_MIPS32 \
870 || ISA_MIPS32R2 \
871 || ISA_MIPS64 \
872 || ISA_MIPS64R2)
873
874 /* Integer multiply-accumulate instructions should be generated. */
875 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
876
877 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
878 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
879
880 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
881 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
882
883 /* ISA has floating-point nmadd and nmsub instructions
884 'd = -((a * b) [+-] c)'. */
885 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
886 ((ISA_MIPS4 \
887 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
888 || ISA_MIPS64 \
889 || ISA_MIPS64R2) \
890 && (!TARGET_MIPS5400 || TARGET_MAD) \
891 && !TARGET_MIPS16)
892
893 /* ISA has floating-point nmadd and nmsub instructions
894 'c = -((a * b) [+-] c)'. */
895 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
896 TARGET_LOONGSON_2EF
897
898 /* ISA has count leading zeroes/ones instruction (not implemented). */
899 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
900 || ISA_MIPS32R2 \
901 || ISA_MIPS64 \
902 || ISA_MIPS64R2) \
903 && !TARGET_MIPS16)
904
905 /* ISA has three operand multiply instructions that put
906 the high part in an accumulator: mulhi or mulhiu. */
907 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
908 || TARGET_MIPS5500 \
909 || TARGET_SR71K) \
910 && !TARGET_MIPS16)
911
912 /* ISA has three operand multiply instructions that
913 negates the result and puts the result in an accumulator. */
914 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
915 || TARGET_MIPS5500 \
916 || TARGET_SR71K) \
917 && !TARGET_MIPS16)
918
919 /* ISA has three operand multiply instructions that subtracts the
920 result from a 4th operand and puts the result in an accumulator. */
921 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
922 || TARGET_MIPS5500 \
923 || TARGET_SR71K) \
924 && !TARGET_MIPS16)
925
926 /* ISA has three operand multiply instructions that the result
927 from a 4th operand and puts the result in an accumulator. */
928 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
929 || TARGET_MIPS4130 \
930 || TARGET_MIPS5400 \
931 || TARGET_MIPS5500 \
932 || TARGET_SR71K) \
933 && !TARGET_MIPS16)
934
935 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
936 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
937 || TARGET_MIPS4130) \
938 && !TARGET_MIPS16)
939
940 /* ISA has the "ror" (rotate right) instructions. */
941 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
942 || ISA_MIPS64R2 \
943 || TARGET_MIPS5400 \
944 || TARGET_MIPS5500 \
945 || TARGET_SR71K \
946 || TARGET_SMARTMIPS) \
947 && !TARGET_MIPS16)
948
949 /* ISA has data prefetch instructions. This controls use of 'pref'. */
950 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
951 || TARGET_LOONGSON_2EF \
952 || ISA_MIPS32 \
953 || ISA_MIPS32R2 \
954 || ISA_MIPS64 \
955 || ISA_MIPS64R2) \
956 && !TARGET_MIPS16)
957
958 /* ISA has data indexed prefetch instructions. This controls use of
959 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
960 (prefx is a cop1x instruction, so can only be used if FP is
961 enabled.) */
962 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
963 || ISA_MIPS32R2 \
964 || ISA_MIPS64 \
965 || ISA_MIPS64R2) \
966 && !TARGET_MIPS16)
967
968 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
969 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
970 also requires TARGET_DOUBLE_FLOAT. */
971 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
972
973 /* ISA includes the MIPS32r2 seb and seh instructions. */
974 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
975 || ISA_MIPS64R2) \
976 && !TARGET_MIPS16)
977
978 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
979 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
980 || ISA_MIPS64R2) \
981 && !TARGET_MIPS16)
982
983 /* ISA has instructions for accessing top part of 64-bit fp regs. */
984 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
985 && (ISA_MIPS32R2 \
986 || ISA_MIPS64R2))
987
988 /* ISA has lwxs instruction (load w/scaled index address. */
989 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
990 && !TARGET_MIPS16)
991
992 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
993 #define ISA_HAS_LBX (TARGET_OCTEON2)
994 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
995 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
996 #define ISA_HAS_LHUX (TARGET_OCTEON2)
997 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
998 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
999 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1000 && TARGET_64BIT)
1001
1002 /* The DSP ASE is available. */
1003 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1004
1005 /* Revision 2 of the DSP ASE is available. */
1006 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1007
1008 /* True if the result of a load is not available to the next instruction.
1009 A nop will then be needed between instructions like "lw $4,..."
1010 and "addiu $4,$4,1". */
1011 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1012 && !TARGET_MIPS3900 \
1013 && !TARGET_MIPS16 \
1014 && !TARGET_MICROMIPS)
1015
1016 /* Likewise mtc1 and mfc1. */
1017 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1018 && !TARGET_LOONGSON_2EF)
1019
1020 /* Likewise floating-point comparisons. */
1021 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1022 && !TARGET_LOONGSON_2EF)
1023
1024 /* True if mflo and mfhi can be immediately followed by instructions
1025 which write to the HI and LO registers.
1026
1027 According to MIPS specifications, MIPS ISAs I, II, and III need
1028 (at least) two instructions between the reads of HI/LO and
1029 instructions which write them, and later ISAs do not. Contradicting
1030 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1031 the UM for the NEC Vr5000) document needing the instructions between
1032 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1033 MIPS64 and later ISAs to have the interlocks, plus any specific
1034 earlier-ISA CPUs for which CPU documentation declares that the
1035 instructions are really interlocked. */
1036 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1037 || ISA_MIPS32R2 \
1038 || ISA_MIPS64 \
1039 || ISA_MIPS64R2 \
1040 || TARGET_MIPS5500 \
1041 || TARGET_LOONGSON_2EF)
1042
1043 /* ISA includes synci, jr.hb and jalr.hb. */
1044 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1045 || ISA_MIPS64R2) \
1046 && !TARGET_MIPS16)
1047
1048 /* ISA includes sync. */
1049 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1050 #define GENERATE_SYNC \
1051 (target_flags_explicit & MASK_LLSC \
1052 ? TARGET_LLSC && !TARGET_MIPS16 \
1053 : ISA_HAS_SYNC)
1054
1055 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1056 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1057 instructions. */
1058 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1059 #define GENERATE_LL_SC \
1060 (target_flags_explicit & MASK_LLSC \
1061 ? TARGET_LLSC && !TARGET_MIPS16 \
1062 : ISA_HAS_LL_SC)
1063
1064 #define ISA_HAS_SWAP (TARGET_XLP)
1065 #define ISA_HAS_LDADD (TARGET_XLP)
1066
1067 /* ISA includes the baddu instruction. */
1068 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1069
1070 /* ISA includes the bbit* instructions. */
1071 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1072
1073 /* ISA includes the cins instruction. */
1074 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1075
1076 /* ISA includes the exts instruction. */
1077 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1078
1079 /* ISA includes the seq and sne instructions. */
1080 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1081
1082 /* ISA includes the pop instruction. */
1083 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1084
1085 /* The CACHE instruction is available in non-MIPS16 code. */
1086 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1087
1088 /* The CACHE instruction is available. */
1089 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1090 \f
1091 /* Tell collect what flags to pass to nm. */
1092 #ifndef NM_FLAGS
1093 #define NM_FLAGS "-Bn"
1094 #endif
1095
1096 \f
1097 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1098 the assembler. It may be overridden by subtargets.
1099
1100 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1101 COFF debugging info. */
1102
1103 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1104 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1105 %{g} %{g0} %{g1} %{g2} %{g3} \
1106 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1107 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1108 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1109 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1110 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1111 #endif
1112
1113 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1114 overridden by subtargets. */
1115
1116 #ifndef SUBTARGET_ASM_SPEC
1117 #define SUBTARGET_ASM_SPEC ""
1118 #endif
1119
1120 #undef ASM_SPEC
1121 #define ASM_SPEC "\
1122 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1123 %{mips32*} %{mips64*} \
1124 %{mips16} %{mno-mips16:-no-mips16} \
1125 %{mmicromips} %{mno-micromips} \
1126 %{mips3d} %{mno-mips3d:-no-mips3d} \
1127 %{mdmx} %{mno-mdmx:-no-mdmx} \
1128 %{mdsp} %{mno-dsp} \
1129 %{mdspr2} %{mno-dspr2} \
1130 %{mmcu} %{mno-mcu} \
1131 %{meva} %{mno-eva} \
1132 %{msmartmips} %{mno-smartmips} \
1133 %{mmt} %{mno-mt} \
1134 %{mfix-vr4120} %{mfix-vr4130} \
1135 %{mfix-24k} \
1136 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1137 %(subtarget_asm_debugging_spec) \
1138 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1139 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1140 %{mfp32} %{mfp64} \
1141 %{mshared} %{mno-shared} \
1142 %{msym32} %{mno-sym32} \
1143 %{mtune=*} \
1144 %(subtarget_asm_spec)"
1145
1146 /* Extra switches sometimes passed to the linker. */
1147
1148 #ifndef LINK_SPEC
1149 #define LINK_SPEC "\
1150 %(endian_spec) \
1151 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1152 %{shared}"
1153 #endif /* LINK_SPEC defined */
1154
1155
1156 /* Specs for the compiler proper */
1157
1158 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1159 overridden by subtargets. */
1160 #ifndef SUBTARGET_CC1_SPEC
1161 #define SUBTARGET_CC1_SPEC ""
1162 #endif
1163
1164 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1165
1166 #undef CC1_SPEC
1167 #define CC1_SPEC "\
1168 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1169 %(subtarget_cc1_spec)"
1170
1171 /* Preprocessor specs. */
1172
1173 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1174 overridden by subtargets. */
1175 #ifndef SUBTARGET_CPP_SPEC
1176 #define SUBTARGET_CPP_SPEC ""
1177 #endif
1178
1179 #define CPP_SPEC "%(subtarget_cpp_spec)"
1180
1181 /* This macro defines names of additional specifications to put in the specs
1182 that can be used in various specifications like CC1_SPEC. Its definition
1183 is an initializer with a subgrouping for each command option.
1184
1185 Each subgrouping contains a string constant, that defines the
1186 specification name, and a string constant that used by the GCC driver
1187 program.
1188
1189 Do not define this macro if it does not need to do anything. */
1190
1191 #define EXTRA_SPECS \
1192 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1193 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1194 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1195 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1196 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1197 { "endian_spec", ENDIAN_SPEC }, \
1198 SUBTARGET_EXTRA_SPECS
1199
1200 #ifndef SUBTARGET_EXTRA_SPECS
1201 #define SUBTARGET_EXTRA_SPECS
1202 #endif
1203 \f
1204 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1205 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1206
1207 #ifndef PREFERRED_DEBUGGING_TYPE
1208 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1209 #endif
1210
1211 /* The size of DWARF addresses should be the same as the size of symbols
1212 in the target file format. They shouldn't depend on things like -msym32,
1213 because many DWARF consumers do not allow the mixture of address sizes
1214 that one would then get from linking -msym32 code with -msym64 code.
1215
1216 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1217 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1218 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1219
1220 /* By default, turn on GDB extensions. */
1221 #define DEFAULT_GDB_EXTENSIONS 1
1222
1223 /* Local compiler-generated symbols must have a prefix that the assembler
1224 understands. By default, this is $, although some targets (e.g.,
1225 NetBSD-ELF) need to override this. */
1226
1227 #ifndef LOCAL_LABEL_PREFIX
1228 #define LOCAL_LABEL_PREFIX "$"
1229 #endif
1230
1231 /* By default on the mips, external symbols do not have an underscore
1232 prepended, but some targets (e.g., NetBSD) require this. */
1233
1234 #ifndef USER_LABEL_PREFIX
1235 #define USER_LABEL_PREFIX ""
1236 #endif
1237
1238 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1239 since the length can run past this up to a continuation point. */
1240 #undef DBX_CONTIN_LENGTH
1241 #define DBX_CONTIN_LENGTH 1500
1242
1243 /* How to renumber registers for dbx and gdb. */
1244 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1245
1246 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1247 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1248
1249 /* The DWARF 2 CFA column which tracks the return address. */
1250 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1251
1252 /* Before the prologue, RA lives in r31. */
1253 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1254
1255 /* Describe how we implement __builtin_eh_return. */
1256 #define EH_RETURN_DATA_REGNO(N) \
1257 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1258
1259 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1260
1261 #define EH_USES(N) mips_eh_uses (N)
1262
1263 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1264 The default for this in 64-bit mode is 8, which causes problems with
1265 SFmode register saves. */
1266 #define DWARF_CIE_DATA_ALIGNMENT -4
1267
1268 /* Correct the offset of automatic variables and arguments. Note that
1269 the MIPS debug format wants all automatic variables and arguments
1270 to be in terms of the virtual frame pointer (stack pointer before
1271 any adjustment in the function), while the MIPS 3.0 linker wants
1272 the frame pointer to be the stack pointer after the initial
1273 adjustment. */
1274
1275 #define DEBUGGER_AUTO_OFFSET(X) \
1276 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1277 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1278 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1279 \f
1280 /* Target machine storage layout */
1281
1282 #define BITS_BIG_ENDIAN 0
1283 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1284 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1285
1286 #define MAX_BITS_PER_WORD 64
1287
1288 /* Width of a word, in units (bytes). */
1289 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1290 #ifndef IN_LIBGCC2
1291 #define MIN_UNITS_PER_WORD 4
1292 #endif
1293
1294 /* For MIPS, width of a floating point register. */
1295 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1296
1297 /* The number of consecutive floating-point registers needed to store the
1298 largest format supported by the FPU. */
1299 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1300
1301 /* The number of consecutive floating-point registers needed to store the
1302 smallest format supported by the FPU. */
1303 #define MIN_FPRS_PER_FMT \
1304 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1305 ? 1 : MAX_FPRS_PER_FMT)
1306
1307 /* The largest size of value that can be held in floating-point
1308 registers and moved with a single instruction. */
1309 #define UNITS_PER_HWFPVALUE \
1310 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1311
1312 /* The largest size of value that can be held in floating-point
1313 registers. */
1314 #define UNITS_PER_FPVALUE \
1315 (TARGET_SOFT_FLOAT_ABI ? 0 \
1316 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1317 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1318
1319 /* The number of bytes in a double. */
1320 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1321
1322 /* Set the sizes of the core types. */
1323 #define SHORT_TYPE_SIZE 16
1324 #define INT_TYPE_SIZE 32
1325 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1326 #define LONG_LONG_TYPE_SIZE 64
1327
1328 #define FLOAT_TYPE_SIZE 32
1329 #define DOUBLE_TYPE_SIZE 64
1330 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1331
1332 /* Define the sizes of fixed-point types. */
1333 #define SHORT_FRACT_TYPE_SIZE 8
1334 #define FRACT_TYPE_SIZE 16
1335 #define LONG_FRACT_TYPE_SIZE 32
1336 #define LONG_LONG_FRACT_TYPE_SIZE 64
1337
1338 #define SHORT_ACCUM_TYPE_SIZE 16
1339 #define ACCUM_TYPE_SIZE 32
1340 #define LONG_ACCUM_TYPE_SIZE 64
1341 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1342 doesn't support 128-bit integers for MIPS32 currently. */
1343 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1344
1345 /* long double is not a fixed mode, but the idea is that, if we
1346 support long double, we also want a 128-bit integer type. */
1347 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1348
1349 #ifdef IN_LIBGCC2
1350 #if ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1351 || (defined _ABI64 && _MIPS_SIM == _ABI64))
1352 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1353 # else
1354 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1355 # endif
1356 #endif
1357
1358 /* Width in bits of a pointer. */
1359 #ifndef POINTER_SIZE
1360 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1361 #endif
1362
1363 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1364 #define PARM_BOUNDARY BITS_PER_WORD
1365
1366 /* Allocation boundary (in *bits*) for the code of a function. */
1367 #define FUNCTION_BOUNDARY 32
1368
1369 /* Alignment of field after `int : 0' in a structure. */
1370 #define EMPTY_FIELD_BOUNDARY 32
1371
1372 /* Every structure's size must be a multiple of this. */
1373 /* 8 is observed right on a DECstation and on riscos 4.02. */
1374 #define STRUCTURE_SIZE_BOUNDARY 8
1375
1376 /* There is no point aligning anything to a rounder boundary than this. */
1377 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1378
1379 /* All accesses must be aligned. */
1380 #define STRICT_ALIGNMENT 1
1381
1382 /* Define this if you wish to imitate the way many other C compilers
1383 handle alignment of bitfields and the structures that contain
1384 them.
1385
1386 The behavior is that the type written for a bit-field (`int',
1387 `short', or other integer type) imposes an alignment for the
1388 entire structure, as if the structure really did contain an
1389 ordinary field of that type. In addition, the bit-field is placed
1390 within the structure so that it would fit within such a field,
1391 not crossing a boundary for it.
1392
1393 Thus, on most machines, a bit-field whose type is written as `int'
1394 would not cross a four-byte boundary, and would force four-byte
1395 alignment for the whole structure. (The alignment used may not
1396 be four bytes; it is controlled by the other alignment
1397 parameters.)
1398
1399 If the macro is defined, its definition should be a C expression;
1400 a nonzero value for the expression enables this behavior. */
1401
1402 #define PCC_BITFIELD_TYPE_MATTERS 1
1403
1404 /* If defined, a C expression to compute the alignment given to a
1405 constant that is being placed in memory. CONSTANT is the constant
1406 and ALIGN is the alignment that the object would ordinarily have.
1407 The value of this macro is used instead of that alignment to align
1408 the object.
1409
1410 If this macro is not defined, then ALIGN is used.
1411
1412 The typical use of this macro is to increase alignment for string
1413 constants to be word aligned so that `strcpy' calls that copy
1414 constants can be done inline. */
1415
1416 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1417 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1418 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1419
1420 /* If defined, a C expression to compute the alignment for a static
1421 variable. TYPE is the data type, and ALIGN is the alignment that
1422 the object would ordinarily have. The value of this macro is used
1423 instead of that alignment to align the object.
1424
1425 If this macro is not defined, then ALIGN is used.
1426
1427 One use of this macro is to increase alignment of medium-size
1428 data to make it all fit in fewer cache lines. Another is to
1429 cause character arrays to be word-aligned so that `strcpy' calls
1430 that copy constants to character arrays can be done inline. */
1431
1432 #undef DATA_ALIGNMENT
1433 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1434 ((((ALIGN) < BITS_PER_WORD) \
1435 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1436 || TREE_CODE (TYPE) == UNION_TYPE \
1437 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1438
1439 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1440 character arrays to be word-aligned so that `strcpy' calls that copy
1441 constants to character arrays can be done inline, and 'strcmp' can be
1442 optimised to use word loads. */
1443 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1444 DATA_ALIGNMENT (TYPE, ALIGN)
1445
1446 #define PAD_VARARGS_DOWN \
1447 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1448
1449 /* Define if operations between registers always perform the operation
1450 on the full register even if a narrower mode is specified. */
1451 #define WORD_REGISTER_OPERATIONS
1452
1453 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1454 moves. All other references are zero extended. */
1455 #define LOAD_EXTEND_OP(MODE) \
1456 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1457 ? SIGN_EXTEND : ZERO_EXTEND)
1458
1459 /* Define this macro if it is advisable to hold scalars in registers
1460 in a wider mode than that declared by the program. In such cases,
1461 the value is constrained to be within the bounds of the declared
1462 type, but kept valid in the wider mode. The signedness of the
1463 extension may differ from that of the type. */
1464
1465 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1466 if (GET_MODE_CLASS (MODE) == MODE_INT \
1467 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1468 { \
1469 if ((MODE) == SImode) \
1470 (UNSIGNEDP) = 0; \
1471 (MODE) = Pmode; \
1472 }
1473
1474 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1475 Extensions of pointers to word_mode must be signed. */
1476 #define POINTERS_EXTEND_UNSIGNED false
1477
1478 /* Define if loading short immediate values into registers sign extends. */
1479 #define SHORT_IMMEDIATES_SIGN_EXTEND
1480
1481 /* The [d]clz instructions have the natural values at 0. */
1482
1483 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1484 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1485 \f
1486 /* Standard register usage. */
1487
1488 /* Number of hardware registers. We have:
1489
1490 - 32 integer registers
1491 - 32 floating point registers
1492 - 8 condition code registers
1493 - 2 accumulator registers (hi and lo)
1494 - 32 registers each for coprocessors 0, 2 and 3
1495 - 4 fake registers:
1496 - ARG_POINTER_REGNUM
1497 - FRAME_POINTER_REGNUM
1498 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1499 - CPRESTORE_SLOT_REGNUM
1500 - 2 dummy entries that were used at various times in the past.
1501 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1502 - 6 DSP control registers */
1503
1504 #define FIRST_PSEUDO_REGISTER 188
1505
1506 /* By default, fix the kernel registers ($26 and $27), the global
1507 pointer ($28) and the stack pointer ($29). This can change
1508 depending on the command-line options.
1509
1510 Regarding coprocessor registers: without evidence to the contrary,
1511 it's best to assume that each coprocessor register has a unique
1512 use. This can be overridden, in, e.g., mips_option_override or
1513 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1514 inappropriate for a particular target. */
1515
1516 #define FIXED_REGISTERS \
1517 { \
1518 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1520 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1521 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1522 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1523 /* COP0 registers */ \
1524 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1525 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1526 /* COP2 registers */ \
1527 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1528 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1529 /* COP3 registers */ \
1530 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1531 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1532 /* 6 DSP accumulator registers & 6 control registers */ \
1533 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1534 }
1535
1536
1537 /* Set up this array for o32 by default.
1538
1539 Note that we don't mark $31 as a call-clobbered register. The idea is
1540 that it's really the call instructions themselves which clobber $31.
1541 We don't care what the called function does with it afterwards.
1542
1543 This approach makes it easier to implement sibcalls. Unlike normal
1544 calls, sibcalls don't clobber $31, so the register reaches the
1545 called function in tact. EPILOGUE_USES says that $31 is useful
1546 to the called function. */
1547
1548 #define CALL_USED_REGISTERS \
1549 { \
1550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1551 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1553 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1554 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1555 /* COP0 registers */ \
1556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1557 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1558 /* COP2 registers */ \
1559 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1561 /* COP3 registers */ \
1562 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1563 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1564 /* 6 DSP accumulator registers & 6 control registers */ \
1565 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1566 }
1567
1568
1569 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1570
1571 #define CALL_REALLY_USED_REGISTERS \
1572 { /* General registers. */ \
1573 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1574 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1575 /* Floating-point registers. */ \
1576 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1577 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1578 /* Others. */ \
1579 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1580 /* COP0 registers */ \
1581 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1582 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1583 /* COP2 registers */ \
1584 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1585 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1586 /* COP3 registers */ \
1587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1588 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1589 /* 6 DSP accumulator registers & 6 control registers */ \
1590 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1591 }
1592
1593 /* Internal macros to classify a register number as to whether it's a
1594 general purpose register, a floating point register, a
1595 multiply/divide register, or a status register. */
1596
1597 #define GP_REG_FIRST 0
1598 #define GP_REG_LAST 31
1599 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1600 #define GP_DBX_FIRST 0
1601 #define K0_REG_NUM (GP_REG_FIRST + 26)
1602 #define K1_REG_NUM (GP_REG_FIRST + 27)
1603 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1604
1605 #define FP_REG_FIRST 32
1606 #define FP_REG_LAST 63
1607 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1608 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1609
1610 #define MD_REG_FIRST 64
1611 #define MD_REG_LAST 65
1612 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1613 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1614
1615 /* The DWARF 2 CFA column which tracks the return address from a
1616 signal handler context. This means that to maintain backwards
1617 compatibility, no hard register can be assigned this column if it
1618 would need to be handled by the DWARF unwinder. */
1619 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1620
1621 #define ST_REG_FIRST 67
1622 #define ST_REG_LAST 74
1623 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1624
1625
1626 /* FIXME: renumber. */
1627 #define COP0_REG_FIRST 80
1628 #define COP0_REG_LAST 111
1629 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1630
1631 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1632 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1633 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1634
1635 #define COP2_REG_FIRST 112
1636 #define COP2_REG_LAST 143
1637 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1638
1639 #define COP3_REG_FIRST 144
1640 #define COP3_REG_LAST 175
1641 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1642
1643 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1644 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1645 #define ALL_COP_REG_LAST COP3_REG_LAST
1646 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1647
1648 #define DSP_ACC_REG_FIRST 176
1649 #define DSP_ACC_REG_LAST 181
1650 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1651
1652 #define AT_REGNUM (GP_REG_FIRST + 1)
1653 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1654 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1655
1656 /* A few bitfield locations for the coprocessor registers. */
1657 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1658 the cause register for the EIC interrupt mode. */
1659 #define CAUSE_IPL 10
1660 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1661 #define SR_IPL 10
1662 /* Exception Level is at bit 1 of the status register. */
1663 #define SR_EXL 1
1664 /* Interrupt Enable is at bit 0 of the status register. */
1665 #define SR_IE 0
1666
1667 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1668 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1669 should be used instead. */
1670 #define FPSW_REGNUM ST_REG_FIRST
1671
1672 #define GP_REG_P(REGNO) \
1673 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1674 #define M16_REG_P(REGNO) \
1675 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1676 #define M16STORE_REG_P(REGNO) \
1677 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1678 #define FP_REG_P(REGNO) \
1679 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1680 #define MD_REG_P(REGNO) \
1681 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1682 #define ST_REG_P(REGNO) \
1683 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1684 #define COP0_REG_P(REGNO) \
1685 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1686 #define COP2_REG_P(REGNO) \
1687 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1688 #define COP3_REG_P(REGNO) \
1689 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1690 #define ALL_COP_REG_P(REGNO) \
1691 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1692 /* Test if REGNO is one of the 6 new DSP accumulators. */
1693 #define DSP_ACC_REG_P(REGNO) \
1694 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1695 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1696 #define ACC_REG_P(REGNO) \
1697 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1698
1699 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1700
1701 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1702 to initialize the mips16 gp pseudo register. */
1703 #define CONST_GP_P(X) \
1704 (GET_CODE (X) == CONST \
1705 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1706 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1707
1708 /* Return coprocessor number from register number. */
1709
1710 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1711 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1712 : COP3_REG_P (REGNO) ? '3' : '?')
1713
1714
1715 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1716
1717 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1718 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1719
1720 #define MODES_TIEABLE_P mips_modes_tieable_p
1721
1722 /* Register to use for pushing function arguments. */
1723 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1724
1725 /* These two registers don't really exist: they get eliminated to either
1726 the stack or hard frame pointer. */
1727 #define ARG_POINTER_REGNUM 77
1728 #define FRAME_POINTER_REGNUM 78
1729
1730 /* $30 is not available on the mips16, so we use $17 as the frame
1731 pointer. */
1732 #define HARD_FRAME_POINTER_REGNUM \
1733 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1734
1735 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1736 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1737
1738 /* Register in which static-chain is passed to a function. */
1739 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1740
1741 /* Registers used as temporaries in prologue/epilogue code:
1742
1743 - If a MIPS16 PIC function needs access to _gp, it first loads
1744 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1745
1746 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1747 register. The register must not conflict with MIPS16_PIC_TEMP.
1748
1749 - If we aren't generating MIPS16 code, the prologue can also use
1750 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1751
1752 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1753 register.
1754
1755 If we're generating MIPS16 code, these registers must come from the
1756 core set of 8. The prologue registers mustn't conflict with any
1757 incoming arguments, the static chain pointer, or the frame pointer.
1758 The epilogue temporary mustn't conflict with the return registers,
1759 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1760 or the EH data registers.
1761
1762 If we're generating interrupt handlers, we use K0 as a temporary register
1763 in prologue/epilogue code. */
1764
1765 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1766 #define MIPS_PROLOGUE_TEMP_REGNUM \
1767 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1768 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1769 (TARGET_MIPS16 \
1770 ? (gcc_unreachable (), INVALID_REGNUM) \
1771 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1772 #define MIPS_EPILOGUE_TEMP_REGNUM \
1773 (cfun->machine->interrupt_handler_p \
1774 ? K0_REG_NUM \
1775 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1776
1777 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1778 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1779 #define MIPS_PROLOGUE_TEMP2(MODE) \
1780 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1781 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1782
1783 /* Define this macro if it is as good or better to call a constant
1784 function address than to call an address kept in a register. */
1785 #define NO_FUNCTION_CSE 1
1786
1787 /* The ABI-defined global pointer. Sometimes we use a different
1788 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1789 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1790
1791 /* We normally use $28 as the global pointer. However, when generating
1792 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1793 register instead. They can then avoid saving and restoring $28
1794 and perhaps avoid using a frame at all.
1795
1796 When a leaf function uses something other than $28, mips_expand_prologue
1797 will modify pic_offset_table_rtx in place. Take the register number
1798 from there after reload. */
1799 #define PIC_OFFSET_TABLE_REGNUM \
1800 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1801 \f
1802 /* Define the classes of registers for register constraints in the
1803 machine description. Also define ranges of constants.
1804
1805 One of the classes must always be named ALL_REGS and include all hard regs.
1806 If there is more than one class, another class must be named NO_REGS
1807 and contain no registers.
1808
1809 The name GENERAL_REGS must be the name of a class (or an alias for
1810 another name such as ALL_REGS). This is the class of registers
1811 that is allowed by "g" or "r" in a register constraint.
1812 Also, registers outside this class are allocated only when
1813 instructions express preferences for them.
1814
1815 The classes must be numbered in nondecreasing order; that is,
1816 a larger-numbered class must never be contained completely
1817 in a smaller-numbered class.
1818
1819 For any two classes, it is very desirable that there be another
1820 class that represents their union. */
1821
1822 enum reg_class
1823 {
1824 NO_REGS, /* no registers in set */
1825 M16_REGS, /* mips16 directly accessible registers */
1826 T_REG, /* mips16 T register ($24) */
1827 M16_T_REGS, /* mips16 registers plus T register */
1828 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1829 V1_REG, /* Register $v1 ($3) used for TLS access. */
1830 LEA_REGS, /* Every GPR except $25 */
1831 GR_REGS, /* integer registers */
1832 FP_REGS, /* floating point registers */
1833 MD0_REG, /* first multiply/divide register */
1834 MD1_REG, /* second multiply/divide register */
1835 MD_REGS, /* multiply/divide registers (hi/lo) */
1836 COP0_REGS, /* generic coprocessor classes */
1837 COP2_REGS,
1838 COP3_REGS,
1839 ST_REGS, /* status registers (fp status) */
1840 DSP_ACC_REGS, /* DSP accumulator registers */
1841 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1842 FRAME_REGS, /* $arg and $frame */
1843 GR_AND_MD0_REGS, /* union classes */
1844 GR_AND_MD1_REGS,
1845 GR_AND_MD_REGS,
1846 GR_AND_ACC_REGS,
1847 ALL_REGS, /* all registers */
1848 LIM_REG_CLASSES /* max value + 1 */
1849 };
1850
1851 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1852
1853 #define GENERAL_REGS GR_REGS
1854
1855 /* An initializer containing the names of the register classes as C
1856 string constants. These names are used in writing some of the
1857 debugging dumps. */
1858
1859 #define REG_CLASS_NAMES \
1860 { \
1861 "NO_REGS", \
1862 "M16_REGS", \
1863 "T_REG", \
1864 "M16_T_REGS", \
1865 "PIC_FN_ADDR_REG", \
1866 "V1_REG", \
1867 "LEA_REGS", \
1868 "GR_REGS", \
1869 "FP_REGS", \
1870 "MD0_REG", \
1871 "MD1_REG", \
1872 "MD_REGS", \
1873 /* coprocessor registers */ \
1874 "COP0_REGS", \
1875 "COP2_REGS", \
1876 "COP3_REGS", \
1877 "ST_REGS", \
1878 "DSP_ACC_REGS", \
1879 "ACC_REGS", \
1880 "FRAME_REGS", \
1881 "GR_AND_MD0_REGS", \
1882 "GR_AND_MD1_REGS", \
1883 "GR_AND_MD_REGS", \
1884 "GR_AND_ACC_REGS", \
1885 "ALL_REGS" \
1886 }
1887
1888 /* An initializer containing the contents of the register classes,
1889 as integers which are bit masks. The Nth integer specifies the
1890 contents of class N. The way the integer MASK is interpreted is
1891 that register R is in the class if `MASK & (1 << R)' is 1.
1892
1893 When the machine has more than 32 registers, an integer does not
1894 suffice. Then the integers are replaced by sub-initializers,
1895 braced groupings containing several integers. Each
1896 sub-initializer must be suitable as an initializer for the type
1897 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1898
1899 #define REG_CLASS_CONTENTS \
1900 { \
1901 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1902 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1903 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1904 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1905 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1906 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1907 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1908 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1909 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1910 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1911 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1912 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1913 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1914 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1915 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1916 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1917 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1918 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1919 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1920 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1921 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1922 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1923 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1924 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1925 }
1926
1927
1928 /* A C expression whose value is a register class containing hard
1929 register REGNO. In general there is more that one such class;
1930 choose a class which is "minimal", meaning that no smaller class
1931 also contains the register. */
1932
1933 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1934
1935 /* A macro whose definition is the name of the class to which a
1936 valid base register must belong. A base register is one used in
1937 an address which is the register value plus a displacement. */
1938
1939 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1940
1941 /* A macro whose definition is the name of the class to which a
1942 valid index register must belong. An index register is one used
1943 in an address where its value is either multiplied by a scale
1944 factor or added to another register (as well as added to a
1945 displacement). */
1946
1947 #define INDEX_REG_CLASS NO_REGS
1948
1949 /* We generally want to put call-clobbered registers ahead of
1950 call-saved ones. (IRA expects this.) */
1951
1952 #define REG_ALLOC_ORDER \
1953 { /* Accumulator registers. When GPRs and accumulators have equal \
1954 cost, we generally prefer to use accumulators. For example, \
1955 a division of multiplication result is better allocated to LO, \
1956 so that we put the MFLO at the point of use instead of at the \
1957 point of definition. It's also needed if we're to take advantage \
1958 of the extra accumulators available with -mdspr2. In some cases, \
1959 it can also help to reduce register pressure. */ \
1960 64, 65,176,177,178,179,180,181, \
1961 /* Call-clobbered GPRs. */ \
1962 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1963 24, 25, 31, \
1964 /* The global pointer. This is call-clobbered for o32 and o64 \
1965 abicalls, call-saved for n32 and n64 abicalls, and a program \
1966 invariant otherwise. Putting it between the call-clobbered \
1967 and call-saved registers should cope with all eventualities. */ \
1968 28, \
1969 /* Call-saved GPRs. */ \
1970 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1971 /* GPRs that can never be exposed to the register allocator. */ \
1972 0, 26, 27, 29, \
1973 /* Call-clobbered FPRs. */ \
1974 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1975 48, 49, 50, 51, \
1976 /* FPRs that are usually call-saved. The odd ones are actually \
1977 call-clobbered for n32, but listing them ahead of the even \
1978 registers might encourage the register allocator to fragment \
1979 the available FPR pairs. We need paired FPRs to store long \
1980 doubles, so it isn't clear that using a different order \
1981 for n32 would be a win. */ \
1982 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1983 /* None of the remaining classes have defined call-saved \
1984 registers. */ \
1985 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1986 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1987 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1988 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1989 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1990 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1991 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1992 182,183,184,185,186,187 \
1993 }
1994
1995 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1996 to be rearranged based on a particular function. On the mips16, we
1997 want to allocate $24 (T_REG) before other registers for
1998 instructions for which it is possible. */
1999
2000 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2001
2002 /* True if VALUE is an unsigned 6-bit number. */
2003
2004 #define UIMM6_OPERAND(VALUE) \
2005 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2006
2007 /* True if VALUE is a signed 10-bit number. */
2008
2009 #define IMM10_OPERAND(VALUE) \
2010 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2011
2012 /* True if VALUE is a signed 16-bit number. */
2013
2014 #define SMALL_OPERAND(VALUE) \
2015 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2016
2017 /* True if VALUE is an unsigned 16-bit number. */
2018
2019 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2020 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2021
2022 /* True if VALUE can be loaded into a register using LUI. */
2023
2024 #define LUI_OPERAND(VALUE) \
2025 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2026 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2027
2028 /* Return a value X with the low 16 bits clear, and such that
2029 VALUE - X is a signed 16-bit value. */
2030
2031 #define CONST_HIGH_PART(VALUE) \
2032 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2033
2034 #define CONST_LOW_PART(VALUE) \
2035 ((VALUE) - CONST_HIGH_PART (VALUE))
2036
2037 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2038 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2039 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2040 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2041
2042 /* The HI and LO registers can only be reloaded via the general
2043 registers. Condition code registers can only be loaded to the
2044 general registers, and from the floating point registers. */
2045
2046 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2047 mips_secondary_reload_class (CLASS, MODE, X, true)
2048 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2049 mips_secondary_reload_class (CLASS, MODE, X, false)
2050
2051 /* Return the maximum number of consecutive registers
2052 needed to represent mode MODE in a register of class CLASS. */
2053
2054 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2055
2056 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2057 mips_cannot_change_mode_class (FROM, TO, CLASS)
2058 \f
2059 /* Stack layout; function entry, exit and calling. */
2060
2061 #define STACK_GROWS_DOWNWARD
2062
2063 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2064
2065 /* Size of the area allocated in the frame to save the GP. */
2066
2067 #define MIPS_GP_SAVE_AREA_SIZE \
2068 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2069
2070 /* The offset of the first local variable from the frame pointer. See
2071 mips_compute_frame_info for details about the frame layout. */
2072
2073 #define STARTING_FRAME_OFFSET \
2074 (FRAME_GROWS_DOWNWARD \
2075 ? 0 \
2076 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2077
2078 #define RETURN_ADDR_RTX mips_return_addr
2079
2080 /* Mask off the MIPS16 ISA bit in unwind addresses.
2081
2082 The reason for this is a little subtle. When unwinding a call,
2083 we are given the call's return address, which on most targets
2084 is the address of the following instruction. However, what we
2085 actually want to find is the EH region for the call itself.
2086 The target-independent unwind code therefore searches for "RA - 1".
2087
2088 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2089 RA - 1 is therefore the real (even-valued) start of the return
2090 instruction. EH region labels are usually odd-valued MIPS16 symbols
2091 too, so a search for an even address within a MIPS16 region would
2092 usually work.
2093
2094 However, there is an exception. If the end of an EH region is also
2095 the end of a function, the end label is allowed to be even. This is
2096 necessary because a following non-MIPS16 function may also need EH
2097 information for its first instruction.
2098
2099 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2100 non-ISA-encoded address. This probably isn't ideal, but it is
2101 the traditional (legacy) behavior. It is therefore only safe
2102 to search MIPS EH regions for an _odd-valued_ address.
2103
2104 Masking off the ISA bit means that the target-independent code
2105 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2106 #define MASK_RETURN_ADDR GEN_INT (-2)
2107
2108
2109 /* Similarly, don't use the least-significant bit to tell pointers to
2110 code from vtable index. */
2111
2112 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2113
2114 /* The eliminations to $17 are only used for mips16 code. See the
2115 definition of HARD_FRAME_POINTER_REGNUM. */
2116
2117 #define ELIMINABLE_REGS \
2118 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2119 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2120 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2121 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2122 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2123 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2124
2125 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2126 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2127
2128 /* Allocate stack space for arguments at the beginning of each function. */
2129 #define ACCUMULATE_OUTGOING_ARGS 1
2130
2131 /* The argument pointer always points to the first argument. */
2132 #define FIRST_PARM_OFFSET(FNDECL) 0
2133
2134 /* o32 and o64 reserve stack space for all argument registers. */
2135 #define REG_PARM_STACK_SPACE(FNDECL) \
2136 (TARGET_OLDABI \
2137 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2138 : 0)
2139
2140 /* Define this if it is the responsibility of the caller to
2141 allocate the area reserved for arguments passed in registers.
2142 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2143 of this macro is to determine whether the space is included in
2144 `crtl->outgoing_args_size'. */
2145 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2146
2147 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2148 \f
2149 /* Symbolic macros for the registers used to return integer and floating
2150 point values. */
2151
2152 #define GP_RETURN (GP_REG_FIRST + 2)
2153 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2154
2155 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2156
2157 /* Symbolic macros for the first/last argument registers. */
2158
2159 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2160 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2161 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2162 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2163
2164 /* 1 if N is a possible register number for function argument passing.
2165 We have no FP argument registers when soft-float. When FP registers
2166 are 32 bits, we can't directly reference the odd numbered ones. */
2167
2168 #define FUNCTION_ARG_REGNO_P(N) \
2169 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2170 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2171 && !fixed_regs[N])
2172 \f
2173 /* This structure has to cope with two different argument allocation
2174 schemes. Most MIPS ABIs view the arguments as a structure, of which
2175 the first N words go in registers and the rest go on the stack. If I
2176 < N, the Ith word might go in Ith integer argument register or in a
2177 floating-point register. For these ABIs, we only need to remember
2178 the offset of the current argument into the structure.
2179
2180 The EABI instead allocates the integer and floating-point arguments
2181 separately. The first N words of FP arguments go in FP registers,
2182 the rest go on the stack. Likewise, the first N words of the other
2183 arguments go in integer registers, and the rest go on the stack. We
2184 need to maintain three counts: the number of integer registers used,
2185 the number of floating-point registers used, and the number of words
2186 passed on the stack.
2187
2188 We could keep separate information for the two ABIs (a word count for
2189 the standard ABIs, and three separate counts for the EABI). But it
2190 seems simpler to view the standard ABIs as forms of EABI that do not
2191 allocate floating-point registers.
2192
2193 So for the standard ABIs, the first N words are allocated to integer
2194 registers, and mips_function_arg decides on an argument-by-argument
2195 basis whether that argument should really go in an integer register,
2196 or in a floating-point one. */
2197
2198 typedef struct mips_args {
2199 /* Always true for varargs functions. Otherwise true if at least
2200 one argument has been passed in an integer register. */
2201 int gp_reg_found;
2202
2203 /* The number of arguments seen so far. */
2204 unsigned int arg_number;
2205
2206 /* The number of integer registers used so far. For all ABIs except
2207 EABI, this is the number of words that have been added to the
2208 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2209 unsigned int num_gprs;
2210
2211 /* For EABI, the number of floating-point registers used so far. */
2212 unsigned int num_fprs;
2213
2214 /* The number of words passed on the stack. */
2215 unsigned int stack_words;
2216
2217 /* On the mips16, we need to keep track of which floating point
2218 arguments were passed in general registers, but would have been
2219 passed in the FP regs if this were a 32-bit function, so that we
2220 can move them to the FP regs if we wind up calling a 32-bit
2221 function. We record this information in fp_code, encoded in base
2222 four. A zero digit means no floating point argument, a one digit
2223 means an SFmode argument, and a two digit means a DFmode argument,
2224 and a three digit is not used. The low order digit is the first
2225 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2226 an SFmode argument. ??? A more sophisticated approach will be
2227 needed if MIPS_ABI != ABI_32. */
2228 int fp_code;
2229
2230 /* True if the function has a prototype. */
2231 int prototype;
2232 } CUMULATIVE_ARGS;
2233
2234 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2235 for a call to a function whose data type is FNTYPE.
2236 For a library call, FNTYPE is 0. */
2237
2238 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2239 mips_init_cumulative_args (&CUM, FNTYPE)
2240
2241 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2242 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2243
2244 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2245 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2246
2247 /* True if using EABI and varargs can be passed in floating-point
2248 registers. Under these conditions, we need a more complex form
2249 of va_list, which tracks GPR, FPR and stack arguments separately. */
2250 #define EABI_FLOAT_VARARGS_P \
2251 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2252
2253 \f
2254 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2255
2256 /* Treat LOC as a byte offset from the stack pointer and round it up
2257 to the next fully-aligned offset. */
2258 #define MIPS_STACK_ALIGN(LOC) \
2259 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2260
2261 \f
2262 /* Output assembler code to FILE to increment profiler label # LABELNO
2263 for profiling a function entry. */
2264
2265 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2266
2267 /* The profiler preserves all interesting registers, including $31. */
2268 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2269
2270 /* No mips port has ever used the profiler counter word, so don't emit it
2271 or the label for it. */
2272
2273 #define NO_PROFILE_COUNTERS 1
2274
2275 /* Define this macro if the code for function profiling should come
2276 before the function prologue. Normally, the profiling code comes
2277 after. */
2278
2279 /* #define PROFILE_BEFORE_PROLOGUE */
2280
2281 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2282 the stack pointer does not matter. The value is tested only in
2283 functions that have frame pointers.
2284 No definition is equivalent to always zero. */
2285
2286 #define EXIT_IGNORE_STACK 1
2287
2288 \f
2289 /* Trampolines are a block of code followed by two pointers. */
2290
2291 #define TRAMPOLINE_SIZE \
2292 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2293
2294 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2295 pointers from a single LUI base. */
2296
2297 #define TRAMPOLINE_ALIGNMENT 64
2298
2299 /* mips_trampoline_init calls this library function to flush
2300 program and data caches. */
2301
2302 #ifndef CACHE_FLUSH_FUNC
2303 #define CACHE_FLUSH_FUNC "_flush_cache"
2304 #endif
2305
2306 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2307 /* Flush both caches. We need to flush the data cache in case \
2308 the system has a write-back cache. */ \
2309 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2310 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2311 GEN_INT (3), TYPE_MODE (integer_type_node))
2312
2313 \f
2314 /* Addressing modes, and classification of registers for them. */
2315
2316 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2317 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2318 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2319 \f
2320 /* Maximum number of registers that can appear in a valid memory address. */
2321
2322 #define MAX_REGS_PER_ADDRESS 1
2323
2324 /* Check for constness inline but use mips_legitimate_address_p
2325 to check whether a constant really is an address. */
2326
2327 #define CONSTANT_ADDRESS_P(X) \
2328 (CONSTANT_P (X) && memory_address_p (SImode, X))
2329
2330 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2331 'the start of the function that this code is output in'. */
2332
2333 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2334 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2335 asm_fprintf ((FILE), "%U%s", \
2336 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2337 else \
2338 asm_fprintf ((FILE), "%U%s", (NAME))
2339 \f
2340 /* Flag to mark a function decl symbol that requires a long call. */
2341 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2342 #define SYMBOL_REF_LONG_CALL_P(X) \
2343 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2344
2345 /* This flag marks functions that cannot be lazily bound. */
2346 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2347 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2348 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2349
2350 /* True if we're generating a form of MIPS16 code in which jump tables
2351 are stored in the text section and encoded as 16-bit PC-relative
2352 offsets. This is only possible when general text loads are allowed,
2353 since the table access itself will be an "lh" instruction. If the
2354 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2355 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2356
2357 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2358
2359 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2360
2361 /* Only use short offsets if their range will not overflow. */
2362 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2363 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2364 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2365 : SImode)
2366
2367 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2368
2369 /* Define this as 1 if `char' should by default be signed; else as 0. */
2370 #ifndef DEFAULT_SIGNED_CHAR
2371 #define DEFAULT_SIGNED_CHAR 1
2372 #endif
2373
2374 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2375 we generally don't want to use them for copying arbitrary data.
2376 A single N-word move is usually the same cost as N single-word moves. */
2377 #define MOVE_MAX UNITS_PER_WORD
2378 #define MAX_MOVE_MAX 8
2379
2380 /* Define this macro as a C expression which is nonzero if
2381 accessing less than a word of memory (i.e. a `char' or a
2382 `short') is no faster than accessing a word of memory, i.e., if
2383 such access require more than one instruction or if there is no
2384 difference in cost between byte and (aligned) word loads.
2385
2386 On RISC machines, it tends to generate better code to define
2387 this as 1, since it avoids making a QI or HI mode register.
2388
2389 But, generating word accesses for -mips16 is generally bad as shifts
2390 (often extended) would be needed for byte accesses. */
2391 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2392
2393 /* Standard MIPS integer shifts truncate the shift amount to the
2394 width of the shifted operand. However, Loongson vector shifts
2395 do not truncate the shift amount at all. */
2396 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2397
2398 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2399 is done just by pretending it is already truncated. */
2400 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2401 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2402
2403
2404 /* Specify the machine mode that pointers have.
2405 After generation of rtl, the compiler makes no further distinction
2406 between pointers and any other objects of this machine mode. */
2407
2408 #ifndef Pmode
2409 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2410 #endif
2411
2412 /* Give call MEMs SImode since it is the "most permissive" mode
2413 for both 32-bit and 64-bit targets. */
2414
2415 #define FUNCTION_MODE SImode
2416
2417 \f
2418 /* We allocate $fcc registers by hand and can't cope with moves of
2419 CCmode registers to and from pseudos (or memory). */
2420 #define AVOID_CCMODE_COPIES
2421
2422 /* A C expression for the cost of a branch instruction. A value of
2423 1 is the default; other values are interpreted relative to that. */
2424
2425 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2426 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2427
2428 /* The MIPS port has several functions that return an instruction count.
2429 Multiplying the count by this value gives the number of bytes that
2430 the instructions occupy. */
2431 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2432
2433 /* The length of a NOP in bytes. */
2434 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2435
2436 /* If defined, modifies the length assigned to instruction INSN as a
2437 function of the context in which it is used. LENGTH is an lvalue
2438 that contains the initially computed length of the insn and should
2439 be updated with the correct length of the insn. */
2440 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2441 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2442
2443 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2444 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2445 its operands. */
2446 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2447 "%*" OPCODE "%?\t" OPERANDS "%/"
2448
2449 /* Return an asm string that forces INSN to be treated as an absolute
2450 J or JAL instruction instead of an assembler macro. */
2451 #define MIPS_ABSOLUTE_JUMP(INSN) \
2452 (TARGET_ABICALLS_PIC2 \
2453 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2454 : INSN)
2455
2456 /* Return the asm template for a call. INSN is the instruction's mnemonic
2457 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2458 number of the target. SIZE_OPNO is the operand number of the argument size
2459 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2460 -1 and the call is indirect, use the function symbol from the call
2461 attributes to attach a R_MIPS_JALR relocation to the call.
2462
2463 When generating GOT code without explicit relocation operators,
2464 all calls should use assembly macros. Otherwise, all indirect
2465 calls should use "jr" or "jalr"; we will arrange to restore $gp
2466 afterwards if necessary. Finally, we can only generate direct
2467 calls for -mabicalls by temporarily switching to non-PIC mode.
2468
2469 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2470 instruction is in the delay slot of jal(r). */
2471 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2472 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2473 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2474 : REG_P (OPERANDS[TARGET_OPNO]) \
2475 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2476 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2477 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2478 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2479 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2480 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2481 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2482
2483 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2484 "jrc" when nop is in the delay slot of "jr". */
2485
2486 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2487 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2488 ? "%*j\t%" #OPNO "%/" \
2489 : REG_P (OPERANDS[OPNO]) \
2490 ? "%*jr%:\t%" #OPNO \
2491 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2492
2493 \f
2494 /* Control the assembler format that we output. */
2495
2496 /* Output to assembler file text saying following lines
2497 may contain character constants, extra white space, comments, etc. */
2498
2499 #ifndef ASM_APP_ON
2500 #define ASM_APP_ON " #APP\n"
2501 #endif
2502
2503 /* Output to assembler file text saying following lines
2504 no longer contain unusual constructs. */
2505
2506 #ifndef ASM_APP_OFF
2507 #define ASM_APP_OFF " #NO_APP\n"
2508 #endif
2509
2510 #define REGISTER_NAMES \
2511 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2512 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2513 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2514 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2515 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2516 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2517 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2518 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2519 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2520 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2521 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2522 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2523 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2524 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2525 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2526 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2527 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2528 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2529 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2530 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2531 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2532 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2533 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2534 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2535
2536 /* List the "software" names for each register. Also list the numerical
2537 names for $fp and $sp. */
2538
2539 #define ADDITIONAL_REGISTER_NAMES \
2540 { \
2541 { "$29", 29 + GP_REG_FIRST }, \
2542 { "$30", 30 + GP_REG_FIRST }, \
2543 { "at", 1 + GP_REG_FIRST }, \
2544 { "v0", 2 + GP_REG_FIRST }, \
2545 { "v1", 3 + GP_REG_FIRST }, \
2546 { "a0", 4 + GP_REG_FIRST }, \
2547 { "a1", 5 + GP_REG_FIRST }, \
2548 { "a2", 6 + GP_REG_FIRST }, \
2549 { "a3", 7 + GP_REG_FIRST }, \
2550 { "t0", 8 + GP_REG_FIRST }, \
2551 { "t1", 9 + GP_REG_FIRST }, \
2552 { "t2", 10 + GP_REG_FIRST }, \
2553 { "t3", 11 + GP_REG_FIRST }, \
2554 { "t4", 12 + GP_REG_FIRST }, \
2555 { "t5", 13 + GP_REG_FIRST }, \
2556 { "t6", 14 + GP_REG_FIRST }, \
2557 { "t7", 15 + GP_REG_FIRST }, \
2558 { "s0", 16 + GP_REG_FIRST }, \
2559 { "s1", 17 + GP_REG_FIRST }, \
2560 { "s2", 18 + GP_REG_FIRST }, \
2561 { "s3", 19 + GP_REG_FIRST }, \
2562 { "s4", 20 + GP_REG_FIRST }, \
2563 { "s5", 21 + GP_REG_FIRST }, \
2564 { "s6", 22 + GP_REG_FIRST }, \
2565 { "s7", 23 + GP_REG_FIRST }, \
2566 { "t8", 24 + GP_REG_FIRST }, \
2567 { "t9", 25 + GP_REG_FIRST }, \
2568 { "k0", 26 + GP_REG_FIRST }, \
2569 { "k1", 27 + GP_REG_FIRST }, \
2570 { "gp", 28 + GP_REG_FIRST }, \
2571 { "sp", 29 + GP_REG_FIRST }, \
2572 { "fp", 30 + GP_REG_FIRST }, \
2573 { "ra", 31 + GP_REG_FIRST } \
2574 }
2575
2576 #define DBR_OUTPUT_SEQEND(STREAM) \
2577 do \
2578 { \
2579 /* Undo the effect of '%*'. */ \
2580 mips_pop_asm_switch (&mips_nomacro); \
2581 mips_pop_asm_switch (&mips_noreorder); \
2582 /* Emit a blank line after the delay slot for emphasis. */ \
2583 fputs ("\n", STREAM); \
2584 } \
2585 while (0)
2586
2587 /* The MIPS implementation uses some labels for its own purpose. The
2588 following lists what labels are created, and are all formed by the
2589 pattern $L[a-z].*. The machine independent portion of GCC creates
2590 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2591
2592 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2593 $Lb[0-9]+ Begin blocks for MIPS debug support
2594 $Lc[0-9]+ Label for use in s<xx> operation.
2595 $Le[0-9]+ End blocks for MIPS debug support */
2596
2597 #undef ASM_DECLARE_OBJECT_NAME
2598 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2599 mips_declare_object (STREAM, NAME, "", ":\n")
2600
2601 /* Globalizing directive for a label. */
2602 #define GLOBAL_ASM_OP "\t.globl\t"
2603
2604 /* This says how to define a global common symbol. */
2605
2606 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2607
2608 /* This says how to define a local common symbol (i.e., not visible to
2609 linker). */
2610
2611 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2612 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2613 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2614 #endif
2615
2616 /* This says how to output an external. It would be possible not to
2617 output anything and let undefined symbol become external. However
2618 the assembler uses length information on externals to allocate in
2619 data/sdata bss/sbss, thereby saving exec time. */
2620
2621 #undef ASM_OUTPUT_EXTERNAL
2622 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2623 mips_output_external(STREAM,DECL,NAME)
2624
2625 /* This is how to declare a function name. The actual work of
2626 emitting the label is moved to function_prologue, so that we can
2627 get the line number correctly emitted before the .ent directive,
2628 and after any .file directives. Define as empty so that the function
2629 is not declared before the .ent directive elsewhere. */
2630
2631 #undef ASM_DECLARE_FUNCTION_NAME
2632 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2633
2634 /* This is how to store into the string LABEL
2635 the symbol_ref name of an internal numbered label where
2636 PREFIX is the class of label and NUM is the number within the class.
2637 This is suitable for output with `assemble_name'. */
2638
2639 #undef ASM_GENERATE_INTERNAL_LABEL
2640 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2641 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2642
2643 /* Print debug labels as "foo = ." rather than "foo:" because they should
2644 represent a byte pointer rather than an ISA-encoded address. This is
2645 particularly important for code like:
2646
2647 $LFBxxx = .
2648 .cfi_startproc
2649 ...
2650 .section .gcc_except_table,...
2651 ...
2652 .uleb128 foo-$LFBxxx
2653
2654 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2655 likewise a byte pointer rather than an ISA-encoded address.
2656
2657 At the time of writing, this hook is not used for the function end
2658 label:
2659
2660 $LFExxx:
2661 .end foo
2662
2663 But this doesn't matter, because GAS doesn't treat a pre-.end label
2664 as a MIPS16 one anyway. */
2665
2666 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2667 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2668
2669 /* This is how to output an element of a case-vector that is absolute. */
2670
2671 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2672 fprintf (STREAM, "\t%s\t%sL%d\n", \
2673 ptr_mode == DImode ? ".dword" : ".word", \
2674 LOCAL_LABEL_PREFIX, \
2675 VALUE)
2676
2677 /* This is how to output an element of a case-vector. We can make the
2678 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2679 is supported. */
2680
2681 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2682 do { \
2683 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2684 { \
2685 if (GET_MODE (BODY) == HImode) \
2686 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2687 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2688 else \
2689 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2690 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2691 } \
2692 else if (TARGET_GPWORD) \
2693 fprintf (STREAM, "\t%s\t%sL%d\n", \
2694 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2695 LOCAL_LABEL_PREFIX, VALUE); \
2696 else if (TARGET_RTP_PIC) \
2697 { \
2698 /* Make the entry relative to the start of the function. */ \
2699 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2700 fprintf (STREAM, "\t%s\t%sL%d-", \
2701 Pmode == DImode ? ".dword" : ".word", \
2702 LOCAL_LABEL_PREFIX, VALUE); \
2703 assemble_name (STREAM, XSTR (fnsym, 0)); \
2704 fprintf (STREAM, "\n"); \
2705 } \
2706 else \
2707 fprintf (STREAM, "\t%s\t%sL%d\n", \
2708 ptr_mode == DImode ? ".dword" : ".word", \
2709 LOCAL_LABEL_PREFIX, VALUE); \
2710 } while (0)
2711
2712 /* This is how to output an assembler line
2713 that says to advance the location counter
2714 to a multiple of 2**LOG bytes. */
2715
2716 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2717 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2718
2719 /* This is how to output an assembler line to advance the location
2720 counter by SIZE bytes. */
2721
2722 #undef ASM_OUTPUT_SKIP
2723 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2724 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2725
2726 /* This is how to output a string. */
2727 #undef ASM_OUTPUT_ASCII
2728 #define ASM_OUTPUT_ASCII mips_output_ascii
2729
2730 \f
2731 /* Default to -G 8 */
2732 #ifndef MIPS_DEFAULT_GVALUE
2733 #define MIPS_DEFAULT_GVALUE 8
2734 #endif
2735
2736 /* Define the strings to put out for each section in the object file. */
2737 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2738 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2739
2740 #undef READONLY_DATA_SECTION_ASM_OP
2741 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2742 \f
2743 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2744 do \
2745 { \
2746 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2747 TARGET_64BIT ? "daddiu" : "addiu", \
2748 reg_names[STACK_POINTER_REGNUM], \
2749 reg_names[STACK_POINTER_REGNUM], \
2750 TARGET_64BIT ? "sd" : "sw", \
2751 reg_names[REGNO], \
2752 reg_names[STACK_POINTER_REGNUM]); \
2753 } \
2754 while (0)
2755
2756 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2757 do \
2758 { \
2759 mips_push_asm_switch (&mips_noreorder); \
2760 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2761 TARGET_64BIT ? "ld" : "lw", \
2762 reg_names[REGNO], \
2763 reg_names[STACK_POINTER_REGNUM], \
2764 TARGET_64BIT ? "daddu" : "addu", \
2765 reg_names[STACK_POINTER_REGNUM], \
2766 reg_names[STACK_POINTER_REGNUM]); \
2767 mips_pop_asm_switch (&mips_noreorder); \
2768 } \
2769 while (0)
2770
2771 /* How to start an assembler comment.
2772 The leading space is important (the mips native assembler requires it). */
2773 #ifndef ASM_COMMENT_START
2774 #define ASM_COMMENT_START " #"
2775 #endif
2776 \f
2777 #undef SIZE_TYPE
2778 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2779
2780 #undef PTRDIFF_TYPE
2781 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2782
2783 /* The maximum number of bytes that can be copied by one iteration of
2784 a movmemsi loop; see mips_block_move_loop. */
2785 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2786 (UNITS_PER_WORD * 4)
2787
2788 /* The maximum number of bytes that can be copied by a straight-line
2789 implementation of movmemsi; see mips_block_move_straight. We want
2790 to make sure that any loop-based implementation will iterate at
2791 least twice. */
2792 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2793 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2794
2795 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2796 values were determined experimentally by benchmarking with CSiBE.
2797 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2798 for o32 where we have to restore $gp afterwards as well as make an
2799 indirect call), but in practice, bumping this up higher for
2800 TARGET_ABICALLS doesn't make much difference to code size. */
2801
2802 #define MIPS_CALL_RATIO 8
2803
2804 /* Any loop-based implementation of movmemsi will have at least
2805 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2806 moves, so allow individual copies of fewer elements.
2807
2808 When movmemsi is not available, use a value approximating
2809 the length of a memcpy call sequence, so that move_by_pieces
2810 will generate inline code if it is shorter than a function call.
2811 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2812 we'll have to generate a load/store pair for each, halve the
2813 value of MIPS_CALL_RATIO to take that into account. */
2814
2815 #define MOVE_RATIO(speed) \
2816 (HAVE_movmemsi \
2817 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2818 : MIPS_CALL_RATIO / 2)
2819
2820 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2821 mips_move_by_pieces_p (SIZE, ALIGN)
2822
2823 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2824 of the length of a memset call, but use the default otherwise. */
2825
2826 #define CLEAR_RATIO(speed)\
2827 ((speed) ? 15 : MIPS_CALL_RATIO)
2828
2829 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2830 optimizing for size adjust the ratio to account for the overhead of
2831 loading the constant and replicating it across the word. */
2832
2833 #define SET_RATIO(speed) \
2834 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2835
2836 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2837 mips_store_by_pieces_p (SIZE, ALIGN)
2838 \f
2839 /* Since the bits of the _init and _fini function is spread across
2840 many object files, each potentially with its own GP, we must assume
2841 we need to load our GP. We don't preserve $gp or $ra, since each
2842 init/fini chunk is supposed to initialize $gp, and crti/crtn
2843 already take care of preserving $ra and, when appropriate, $gp. */
2844 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2845 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2846 asm (SECTION_OP "\n\
2847 .set push\n\
2848 .set nomips16\n\
2849 .set noreorder\n\
2850 bal 1f\n\
2851 nop\n\
2852 1: .cpload $31\n\
2853 .set reorder\n\
2854 jal " USER_LABEL_PREFIX #FUNC "\n\
2855 .set pop\n\
2856 " TEXT_SECTION_ASM_OP);
2857 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2858 || (defined _ABI64 && _MIPS_SIM == _ABI64))
2859 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2860 asm (SECTION_OP "\n\
2861 .set push\n\
2862 .set nomips16\n\
2863 .set noreorder\n\
2864 bal 1f\n\
2865 nop\n\
2866 1: .set reorder\n\
2867 .cpsetup $31, $2, 1b\n\
2868 jal " USER_LABEL_PREFIX #FUNC "\n\
2869 .set pop\n\
2870 " TEXT_SECTION_ASM_OP);
2871 #endif
2872
2873 #ifndef HAVE_AS_TLS
2874 #define HAVE_AS_TLS 0
2875 #endif
2876
2877 #ifndef USED_FOR_TARGET
2878 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2879 struct mips_asm_switch {
2880 /* The FOO in the description above. */
2881 const char *name;
2882
2883 /* The current block nesting level, or 0 if we aren't in a block. */
2884 int nesting_level;
2885 };
2886
2887 extern const enum reg_class mips_regno_to_class[];
2888 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2889 extern const char *current_function_file; /* filename current function is in */
2890 extern int num_source_filenames; /* current .file # */
2891 extern struct mips_asm_switch mips_noreorder;
2892 extern struct mips_asm_switch mips_nomacro;
2893 extern struct mips_asm_switch mips_noat;
2894 extern int mips_dbx_regno[];
2895 extern int mips_dwarf_regno[];
2896 extern bool mips_split_p[];
2897 extern bool mips_split_hi_p[];
2898 extern bool mips_use_pcrel_pool_p[];
2899 extern const char *mips_lo_relocs[];
2900 extern const char *mips_hi_relocs[];
2901 extern enum processor mips_arch; /* which cpu to codegen for */
2902 extern enum processor mips_tune; /* which cpu to schedule for */
2903 extern int mips_isa; /* architectural level */
2904 extern const struct mips_cpu_info *mips_arch_info;
2905 extern const struct mips_cpu_info *mips_tune_info;
2906 extern unsigned int mips_base_compression_flags;
2907 extern GTY(()) struct target_globals *mips16_globals;
2908 #endif
2909
2910 /* Enable querying of DFA units. */
2911 #define CPU_UNITS_QUERY 1
2912
2913 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2914 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2915
2916 /* As on most targets, we want the .eh_frame section to be read-only where
2917 possible. And as on most targets, this means two things:
2918
2919 (a) Non-locally-binding pointers must have an indirect encoding,
2920 so that the addresses in the .eh_frame section itself become
2921 locally-binding.
2922
2923 (b) A shared library's .eh_frame section must encode locally-binding
2924 pointers in a relative (relocation-free) form.
2925
2926 However, MIPS has traditionally not allowed directives like:
2927
2928 .long x-.
2929
2930 in cases where "x" is in a different section, or is not defined in the
2931 same assembly file. We are therefore unable to emit the PC-relative
2932 form required by (b) at assembly time.
2933
2934 Fortunately, the linker is able to convert absolute addresses into
2935 PC-relative addresses on our behalf. Unfortunately, only certain
2936 versions of the linker know how to do this for indirect pointers,
2937 and for personality data. We must fall back on using writable
2938 .eh_frame sections for shared libraries if the linker does not
2939 support this feature. */
2940 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2941 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2942
2943 /* For switching between MIPS16 and non-MIPS16 modes. */
2944 #define SWITCHABLE_TARGET 1
2945
2946 /* Several named MIPS patterns depend on Pmode. These patterns have the
2947 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2948 Add the appropriate suffix to generator function NAME and invoke it
2949 with arguments ARGS. */
2950 #define PMODE_INSN(NAME, ARGS) \
2951 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)