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configure.ac (gcc_cv_ld_mips_personality_relaxation): New feature check.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF2_1,
45 PROCESSOR_24KF1_1,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF2_1,
48 PROCESSOR_74KF1_1,
49 PROCESSOR_74KF3_2,
50 PROCESSOR_LOONGSON_2E,
51 PROCESSOR_LOONGSON_2F,
52 PROCESSOR_M4K,
53 PROCESSOR_OCTEON,
54 PROCESSOR_R3900,
55 PROCESSOR_R6000,
56 PROCESSOR_R4000,
57 PROCESSOR_R4100,
58 PROCESSOR_R4111,
59 PROCESSOR_R4120,
60 PROCESSOR_R4130,
61 PROCESSOR_R4300,
62 PROCESSOR_R4600,
63 PROCESSOR_R4650,
64 PROCESSOR_R5000,
65 PROCESSOR_R5400,
66 PROCESSOR_R5500,
67 PROCESSOR_R7000,
68 PROCESSOR_R8000,
69 PROCESSOR_R9000,
70 PROCESSOR_R10000,
71 PROCESSOR_SB1,
72 PROCESSOR_SB1A,
73 PROCESSOR_SR71000,
74 PROCESSOR_XLR,
75 PROCESSOR_MAX
76 };
77
78 /* Costs of various operations on the different architectures. */
79
80 struct mips_rtx_cost_data
81 {
82 unsigned short fp_add;
83 unsigned short fp_mult_sf;
84 unsigned short fp_mult_df;
85 unsigned short fp_div_sf;
86 unsigned short fp_div_df;
87 unsigned short int_mult_si;
88 unsigned short int_mult_di;
89 unsigned short int_div_si;
90 unsigned short int_div_di;
91 unsigned short branch_cost;
92 unsigned short memory_latency;
93 };
94
95 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
96 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
97 to work on a 64-bit machine. */
98
99 #define ABI_32 0
100 #define ABI_N32 1
101 #define ABI_64 2
102 #define ABI_EABI 3
103 #define ABI_O64 4
104
105 /* Masks that affect tuning.
106
107 PTF_AVOID_BRANCHLIKELY
108 Set if it is usually not profitable to use branch-likely instructions
109 for this target, typically because the branches are always predicted
110 taken and so incur a large overhead when not taken. */
111 #define PTF_AVOID_BRANCHLIKELY 0x1
112
113 /* Information about one recognized processor. Defined here for the
114 benefit of TARGET_CPU_CPP_BUILTINS. */
115 struct mips_cpu_info {
116 /* The 'canonical' name of the processor as far as GCC is concerned.
117 It's typically a manufacturer's prefix followed by a numerical
118 designation. It should be lowercase. */
119 const char *name;
120
121 /* The internal processor number that most closely matches this
122 entry. Several processors can have the same value, if there's no
123 difference between them from GCC's point of view. */
124 enum processor_type cpu;
125
126 /* The ISA level that the processor implements. */
127 int isa;
128
129 /* A mask of PTF_* values. */
130 unsigned int tune_flags;
131 };
132
133 /* Enumerates the setting of the -mcode-readable option. */
134 enum mips_code_readable_setting {
135 CODE_READABLE_NO,
136 CODE_READABLE_PCREL,
137 CODE_READABLE_YES
138 };
139
140 /* Macros to silence warnings about numbers being signed in traditional
141 C and unsigned in ISO C when compiled on 32-bit hosts. */
142
143 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
144 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
145 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
146
147 \f
148 /* Run-time compilation parameters selecting different hardware subsets. */
149
150 /* True if we are generating position-independent VxWorks RTP code. */
151 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
152
153 /* True if the output file is marked as ".abicalls; .option pic0"
154 (-call_nonpic). */
155 #define TARGET_ABICALLS_PIC0 \
156 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
157
158 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
159 #define TARGET_ABICALLS_PIC2 \
160 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
161
162 /* True if the call patterns should be split into a jalr followed by
163 an instruction to restore $gp. It is only safe to split the load
164 from the call when every use of $gp is explicit.
165
166 See mips_must_initialize_gp_p for details about how we manage the
167 global pointer. */
168
169 #define TARGET_SPLIT_CALLS \
170 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
171
172 /* True if we're generating a form of -mabicalls in which we can use
173 operators like %hi and %lo to refer to locally-binding symbols.
174 We can only do this for -mno-shared, and only then if we can use
175 relocation operations instead of assembly macros. It isn't really
176 worth using absolute sequences for 64-bit symbols because GOT
177 accesses are so much shorter. */
178
179 #define TARGET_ABSOLUTE_ABICALLS \
180 (TARGET_ABICALLS \
181 && !TARGET_SHARED \
182 && TARGET_EXPLICIT_RELOCS \
183 && !ABI_HAS_64BIT_SYMBOLS)
184
185 /* True if we can optimize sibling calls. For simplicity, we only
186 handle cases in which call_insn_operand will reject invalid
187 sibcall addresses. There are two cases in which this isn't true:
188
189 - TARGET_MIPS16. call_insn_operand accepts constant addresses
190 but there is no direct jump instruction. It isn't worth
191 using sibling calls in this case anyway; they would usually
192 be longer than normal calls.
193
194 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
195 accepts global constants, but all sibcalls must be indirect. */
196 #define TARGET_SIBCALLS \
197 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
198
199 /* True if we need to use a global offset table to access some symbols. */
200 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
201
202 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
203 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
204
205 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
206 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
207
208 /* True if we should use .cprestore to store to the cprestore slot.
209
210 We continue to use .cprestore for explicit-reloc code so that JALs
211 inside inline asms will work correctly. */
212 #define TARGET_CPRESTORE_DIRECTIVE \
213 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
214
215 /* True if we can use the J and JAL instructions. */
216 #define TARGET_ABSOLUTE_JUMPS \
217 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
218
219 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
220 This is true for both the PIC and non-PIC VxWorks RTP modes. */
221 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
222
223 /* True if .gpword or .gpdword should be used for switch tables.
224
225 Although GAS does understand .gpdword, the SGI linker mishandles
226 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
227 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
228 #define TARGET_GPWORD \
229 (TARGET_ABICALLS \
230 && !TARGET_ABSOLUTE_ABICALLS \
231 && !(mips_abi == ABI_64 && TARGET_IRIX))
232
233 /* True if the output must have a writable .eh_frame.
234 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
235 #ifdef HAVE_LD_PERSONALITY_RELAXATION
236 #define TARGET_WRITABLE_EH_FRAME 0
237 #else
238 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
239 #endif
240
241 /* Generate mips16 code */
242 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
243 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
244 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
245 /* Generate mips16e register save/restore sequences. */
246 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
247
248 /* True if we're generating a form of MIPS16 code in which general
249 text loads are allowed. */
250 #define TARGET_MIPS16_TEXT_LOADS \
251 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
252
253 /* True if we're generating a form of MIPS16 code in which PC-relative
254 loads are allowed. */
255 #define TARGET_MIPS16_PCREL_LOADS \
256 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
257
258 /* Generic ISA defines. */
259 #define ISA_MIPS1 (mips_isa == 1)
260 #define ISA_MIPS2 (mips_isa == 2)
261 #define ISA_MIPS3 (mips_isa == 3)
262 #define ISA_MIPS4 (mips_isa == 4)
263 #define ISA_MIPS32 (mips_isa == 32)
264 #define ISA_MIPS32R2 (mips_isa == 33)
265 #define ISA_MIPS64 (mips_isa == 64)
266 #define ISA_MIPS64R2 (mips_isa == 65)
267
268 /* Architecture target defines. */
269 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
270 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
271 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
272 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
273 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
274 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
275 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
276 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
277 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
278 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
279 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
280 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
281 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
282 || mips_arch == PROCESSOR_SB1A)
283 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
284
285 /* Scheduling target defines. */
286 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
287 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
288 || mips_tune == PROCESSOR_24KF2_1 \
289 || mips_tune == PROCESSOR_24KF1_1)
290 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
291 || mips_tune == PROCESSOR_74KF2_1 \
292 || mips_tune == PROCESSOR_74KF1_1 \
293 || mips_tune == PROCESSOR_74KF3_2)
294 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
295 || mips_tune == PROCESSOR_LOONGSON_2F)
296 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
297 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
298 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
299 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
300 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
301 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
302 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
303 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
304 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
305 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
306 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
307 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
308 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
309 || mips_tune == PROCESSOR_SB1A)
310
311 /* Whether vector modes and intrinsics for ST Microelectronics
312 Loongson-2E/2F processors should be enabled. In o32 pairs of
313 floating-point registers provide 64-bit values. */
314 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
315 && TARGET_LOONGSON_2EF)
316
317 /* True if the pre-reload scheduler should try to create chains of
318 multiply-add or multiply-subtract instructions. For example,
319 suppose we have:
320
321 t1 = a * b
322 t2 = t1 + c * d
323 t3 = e * f
324 t4 = t3 - g * h
325
326 t1 will have a higher priority than t2 and t3 will have a higher
327 priority than t4. However, before reload, there is no dependence
328 between t1 and t3, and they can often have similar priorities.
329 The scheduler will then tend to prefer:
330
331 t1 = a * b
332 t3 = e * f
333 t2 = t1 + c * d
334 t4 = t3 - g * h
335
336 which stops us from making full use of macc/madd-style instructions.
337 This sort of situation occurs frequently in Fourier transforms and
338 in unrolled loops.
339
340 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
341 queue so that chained multiply-add and multiply-subtract instructions
342 appear ahead of any other instruction that is likely to clobber lo.
343 In the example above, if t2 and t3 become ready at the same time,
344 the code ensures that t2 is scheduled first.
345
346 Multiply-accumulate instructions are a bigger win for some targets
347 than others, so this macro is defined on an opt-in basis. */
348 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
349 || TUNE_MIPS4120 \
350 || TUNE_MIPS4130 \
351 || TUNE_24K)
352
353 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
354 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
355
356 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
357 directly accessible, while the command-line options select
358 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
359 in use. */
360 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
361 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
362
363 /* False if SC acts as a memory barrier with respect to itself,
364 otherwise a SYNC will be emitted after SC for atomic operations
365 that require ordering between the SC and following loads and
366 stores. It does not tell anything about ordering of loads and
367 stores prior to and following the SC, only about the SC itself and
368 those loads and stores follow it. */
369 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
370
371 /* IRIX specific stuff. */
372 #define TARGET_IRIX 0
373 #define TARGET_IRIX6 0
374
375 /* Define preprocessor macros for the -march and -mtune options.
376 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
377 processor. If INFO's canonical name is "foo", define PREFIX to
378 be "foo", and define an additional macro PREFIX_FOO. */
379 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
380 do \
381 { \
382 char *macro, *p; \
383 \
384 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
385 for (p = macro; *p != 0; p++) \
386 *p = TOUPPER (*p); \
387 \
388 builtin_define (macro); \
389 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
390 free (macro); \
391 } \
392 while (0)
393
394 /* Target CPU builtins. */
395 #define TARGET_CPU_CPP_BUILTINS() \
396 do \
397 { \
398 /* Everyone but IRIX defines this to mips. */ \
399 if (!TARGET_IRIX) \
400 builtin_assert ("machine=mips"); \
401 \
402 builtin_assert ("cpu=mips"); \
403 builtin_define ("__mips__"); \
404 builtin_define ("_mips"); \
405 \
406 /* We do this here because __mips is defined below and so we \
407 can't use builtin_define_std. We don't ever want to define \
408 "mips" for VxWorks because some of the VxWorks headers \
409 construct include filenames from a root directory macro, \
410 an architecture macro and a filename, where the architecture \
411 macro expands to 'mips'. If we define 'mips' to 1, the \
412 architecture macro expands to 1 as well. */ \
413 if (!flag_iso && !TARGET_VXWORKS) \
414 builtin_define ("mips"); \
415 \
416 if (TARGET_64BIT) \
417 builtin_define ("__mips64"); \
418 \
419 if (!TARGET_IRIX) \
420 { \
421 /* Treat _R3000 and _R4000 like register-size \
422 defines, which is how they've historically \
423 been used. */ \
424 if (TARGET_64BIT) \
425 { \
426 builtin_define_std ("R4000"); \
427 builtin_define ("_R4000"); \
428 } \
429 else \
430 { \
431 builtin_define_std ("R3000"); \
432 builtin_define ("_R3000"); \
433 } \
434 } \
435 if (TARGET_FLOAT64) \
436 builtin_define ("__mips_fpr=64"); \
437 else \
438 builtin_define ("__mips_fpr=32"); \
439 \
440 if (mips_base_mips16) \
441 builtin_define ("__mips16"); \
442 \
443 if (TARGET_MIPS3D) \
444 builtin_define ("__mips3d"); \
445 \
446 if (TARGET_SMARTMIPS) \
447 builtin_define ("__mips_smartmips"); \
448 \
449 if (TARGET_DSP) \
450 { \
451 builtin_define ("__mips_dsp"); \
452 if (TARGET_DSPR2) \
453 { \
454 builtin_define ("__mips_dspr2"); \
455 builtin_define ("__mips_dsp_rev=2"); \
456 } \
457 else \
458 builtin_define ("__mips_dsp_rev=1"); \
459 } \
460 \
461 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
462 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
463 \
464 if (ISA_MIPS1) \
465 { \
466 builtin_define ("__mips=1"); \
467 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
468 } \
469 else if (ISA_MIPS2) \
470 { \
471 builtin_define ("__mips=2"); \
472 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
473 } \
474 else if (ISA_MIPS3) \
475 { \
476 builtin_define ("__mips=3"); \
477 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
478 } \
479 else if (ISA_MIPS4) \
480 { \
481 builtin_define ("__mips=4"); \
482 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
483 } \
484 else if (ISA_MIPS32) \
485 { \
486 builtin_define ("__mips=32"); \
487 builtin_define ("__mips_isa_rev=1"); \
488 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
489 } \
490 else if (ISA_MIPS32R2) \
491 { \
492 builtin_define ("__mips=32"); \
493 builtin_define ("__mips_isa_rev=2"); \
494 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
495 } \
496 else if (ISA_MIPS64) \
497 { \
498 builtin_define ("__mips=64"); \
499 builtin_define ("__mips_isa_rev=1"); \
500 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
501 } \
502 else if (ISA_MIPS64R2) \
503 { \
504 builtin_define ("__mips=64"); \
505 builtin_define ("__mips_isa_rev=2"); \
506 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
507 } \
508 \
509 switch (mips_abi) \
510 { \
511 case ABI_32: \
512 builtin_define ("_ABIO32=1"); \
513 builtin_define ("_MIPS_SIM=_ABIO32"); \
514 break; \
515 \
516 case ABI_N32: \
517 builtin_define ("_ABIN32=2"); \
518 builtin_define ("_MIPS_SIM=_ABIN32"); \
519 break; \
520 \
521 case ABI_64: \
522 builtin_define ("_ABI64=3"); \
523 builtin_define ("_MIPS_SIM=_ABI64"); \
524 break; \
525 \
526 case ABI_O64: \
527 builtin_define ("_ABIO64=4"); \
528 builtin_define ("_MIPS_SIM=_ABIO64"); \
529 break; \
530 } \
531 \
532 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
533 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
534 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
535 builtin_define_with_int_value ("_MIPS_FPSET", \
536 32 / MAX_FPRS_PER_FMT); \
537 \
538 /* These defines reflect the ABI in use, not whether the \
539 FPU is directly accessible. */ \
540 if (TARGET_HARD_FLOAT_ABI) \
541 builtin_define ("__mips_hard_float"); \
542 else \
543 builtin_define ("__mips_soft_float"); \
544 \
545 if (TARGET_SINGLE_FLOAT) \
546 builtin_define ("__mips_single_float"); \
547 \
548 if (TARGET_PAIRED_SINGLE_FLOAT) \
549 builtin_define ("__mips_paired_single_float"); \
550 \
551 if (TARGET_BIG_ENDIAN) \
552 { \
553 builtin_define_std ("MIPSEB"); \
554 builtin_define ("_MIPSEB"); \
555 } \
556 else \
557 { \
558 builtin_define_std ("MIPSEL"); \
559 builtin_define ("_MIPSEL"); \
560 } \
561 \
562 /* Whether calls should go through $25. The separate __PIC__ \
563 macro indicates whether abicalls code might use a GOT. */ \
564 if (TARGET_ABICALLS) \
565 builtin_define ("__mips_abicalls"); \
566 \
567 /* Whether Loongson vector modes are enabled. */ \
568 if (TARGET_LOONGSON_VECTORS) \
569 builtin_define ("__mips_loongson_vector_rev"); \
570 \
571 /* Historical Octeon macro. */ \
572 if (TARGET_OCTEON) \
573 builtin_define ("__OCTEON__"); \
574 \
575 /* Macros dependent on the C dialect. */ \
576 if (preprocessing_asm_p ()) \
577 { \
578 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
579 builtin_define ("_LANGUAGE_ASSEMBLY"); \
580 } \
581 else if (c_dialect_cxx ()) \
582 { \
583 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
584 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
585 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
586 } \
587 else \
588 { \
589 builtin_define_std ("LANGUAGE_C"); \
590 builtin_define ("_LANGUAGE_C"); \
591 } \
592 if (c_dialect_objc ()) \
593 { \
594 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
595 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
596 /* Bizarre, but needed at least for Irix. */ \
597 builtin_define_std ("LANGUAGE_C"); \
598 builtin_define ("_LANGUAGE_C"); \
599 } \
600 \
601 if (mips_abi == ABI_EABI) \
602 builtin_define ("__mips_eabi"); \
603 \
604 if (TARGET_CACHE_BUILTIN) \
605 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
606 } \
607 while (0)
608
609 /* Default target_flags if no switches are specified */
610
611 #ifndef TARGET_DEFAULT
612 #define TARGET_DEFAULT 0
613 #endif
614
615 #ifndef TARGET_CPU_DEFAULT
616 #define TARGET_CPU_DEFAULT 0
617 #endif
618
619 #ifndef TARGET_ENDIAN_DEFAULT
620 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
621 #endif
622
623 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
624 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
625 #endif
626
627 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
628 #ifndef MIPS_ISA_DEFAULT
629 #ifndef MIPS_CPU_STRING_DEFAULT
630 #define MIPS_CPU_STRING_DEFAULT "from-abi"
631 #endif
632 #endif
633
634 #ifdef IN_LIBGCC2
635 #undef TARGET_64BIT
636 /* Make this compile time constant for libgcc2 */
637 #ifdef __mips64
638 #define TARGET_64BIT 1
639 #else
640 #define TARGET_64BIT 0
641 #endif
642 #endif /* IN_LIBGCC2 */
643
644 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
645 when compiled with hardware floating point. This is because MIPS16
646 code cannot save and restore the floating-point registers, which is
647 important if in a mixed MIPS16/non-MIPS16 environment. */
648
649 #ifdef IN_LIBGCC2
650 #if __mips_hard_float
651 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
652 #endif
653 #endif /* IN_LIBGCC2 */
654
655 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
656
657 #ifndef MULTILIB_ENDIAN_DEFAULT
658 #if TARGET_ENDIAN_DEFAULT == 0
659 #define MULTILIB_ENDIAN_DEFAULT "EL"
660 #else
661 #define MULTILIB_ENDIAN_DEFAULT "EB"
662 #endif
663 #endif
664
665 #ifndef MULTILIB_ISA_DEFAULT
666 # if MIPS_ISA_DEFAULT == 1
667 # define MULTILIB_ISA_DEFAULT "mips1"
668 # else
669 # if MIPS_ISA_DEFAULT == 2
670 # define MULTILIB_ISA_DEFAULT "mips2"
671 # else
672 # if MIPS_ISA_DEFAULT == 3
673 # define MULTILIB_ISA_DEFAULT "mips3"
674 # else
675 # if MIPS_ISA_DEFAULT == 4
676 # define MULTILIB_ISA_DEFAULT "mips4"
677 # else
678 # if MIPS_ISA_DEFAULT == 32
679 # define MULTILIB_ISA_DEFAULT "mips32"
680 # else
681 # if MIPS_ISA_DEFAULT == 33
682 # define MULTILIB_ISA_DEFAULT "mips32r2"
683 # else
684 # if MIPS_ISA_DEFAULT == 64
685 # define MULTILIB_ISA_DEFAULT "mips64"
686 # else
687 # if MIPS_ISA_DEFAULT == 65
688 # define MULTILIB_ISA_DEFAULT "mips64r2"
689 # else
690 # define MULTILIB_ISA_DEFAULT "mips1"
691 # endif
692 # endif
693 # endif
694 # endif
695 # endif
696 # endif
697 # endif
698 # endif
699 #endif
700
701 #ifndef MIPS_ABI_DEFAULT
702 #define MIPS_ABI_DEFAULT ABI_32
703 #endif
704
705 /* Use the most portable ABI flag for the ASM specs. */
706
707 #if MIPS_ABI_DEFAULT == ABI_32
708 #define MULTILIB_ABI_DEFAULT "mabi=32"
709 #endif
710
711 #if MIPS_ABI_DEFAULT == ABI_O64
712 #define MULTILIB_ABI_DEFAULT "mabi=o64"
713 #endif
714
715 #if MIPS_ABI_DEFAULT == ABI_N32
716 #define MULTILIB_ABI_DEFAULT "mabi=n32"
717 #endif
718
719 #if MIPS_ABI_DEFAULT == ABI_64
720 #define MULTILIB_ABI_DEFAULT "mabi=64"
721 #endif
722
723 #if MIPS_ABI_DEFAULT == ABI_EABI
724 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
725 #endif
726
727 #ifndef MULTILIB_DEFAULTS
728 #define MULTILIB_DEFAULTS \
729 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
730 #endif
731
732 /* We must pass -EL to the linker by default for little endian embedded
733 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
734 linker will default to using big-endian output files. The OUTPUT_FORMAT
735 line must be in the linker script, otherwise -EB/-EL will not work. */
736
737 #ifndef ENDIAN_SPEC
738 #if TARGET_ENDIAN_DEFAULT == 0
739 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
740 #else
741 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
742 #endif
743 #endif
744
745 /* A spec condition that matches all non-mips16 -mips arguments. */
746
747 #define MIPS_ISA_LEVEL_OPTION_SPEC \
748 "mips1|mips2|mips3|mips4|mips32*|mips64*"
749
750 /* A spec condition that matches all non-mips16 architecture arguments. */
751
752 #define MIPS_ARCH_OPTION_SPEC \
753 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
754
755 /* A spec that infers a -mips argument from an -march argument,
756 or injects the default if no architecture is specified. */
757
758 #define MIPS_ISA_LEVEL_SPEC \
759 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
760 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
761 %{march=mips2|march=r6000:-mips2} \
762 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
763 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
764 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
765 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
766 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
767 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
768 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
769 |march=xlr: -mips64} \
770 %{march=mips64r2|march=octeon: -mips64r2} \
771 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
772
773 /* A spec that infers a -mhard-float or -msoft-float setting from an
774 -march argument. Note that soft-float and hard-float code are not
775 link-compatible. */
776
777 #define MIPS_ARCH_FLOAT_SPEC \
778 "%{mhard-float|msoft-float|march=mips*:; \
779 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
780 |march=34kc|march=74kc|march=1004kc|march=5kc \
781 |march=octeon|march=xlr: -msoft-float; \
782 march=*: -mhard-float}"
783
784 /* A spec condition that matches 32-bit options. It only works if
785 MIPS_ISA_LEVEL_SPEC has been applied. */
786
787 #define MIPS_32BIT_OPTION_SPEC \
788 "mips1|mips2|mips32*|mgp32"
789
790 #if MIPS_ABI_DEFAULT == ABI_O64 \
791 || MIPS_ABI_DEFAULT == ABI_N32 \
792 || MIPS_ABI_DEFAULT == ABI_64
793 #define OPT_ARCH64 "mabi=32|mgp32:;"
794 #define OPT_ARCH32 "mabi=32|mgp32"
795 #else
796 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
797 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
798 #endif
799
800 /* Support for a compile-time default CPU, et cetera. The rules are:
801 --with-arch is ignored if -march is specified or a -mips is specified
802 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
803 --with-tune is ignored if -mtune is specified; likewise
804 --with-tune-32 and --with-tune-64.
805 --with-abi is ignored if -mabi is specified.
806 --with-float is ignored if -mhard-float or -msoft-float are
807 specified.
808 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
809 specified. */
810 #define OPTION_DEFAULT_SPECS \
811 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
812 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
813 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
814 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
815 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
816 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
817 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
818 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
819 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
820 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
821 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
822 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
823
824
825 /* A spec that infers the -mdsp setting from an -march argument. */
826 #define BASE_DRIVER_SELF_SPECS \
827 "%{!mno-dsp:%{march=24ke*|march=34k*|march=74k*|march=1004k*: -mdsp}}"
828
829 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
830
831 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
832 && ISA_HAS_COND_TRAP)
833
834 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
835
836 /* True if the ABI can only work with 64-bit integer registers. We
837 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
838 otherwise floating-point registers must also be 64-bit. */
839 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
840
841 /* Likewise for 32-bit regs. */
842 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
843
844 /* True if the file format uses 64-bit symbols. At present, this is
845 only true for n64, which uses 64-bit ELF. */
846 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
847
848 /* True if symbols are 64 bits wide. This is usually determined by
849 the ABI's file format, but it can be overridden by -msym32. Note that
850 overriding the size with -msym32 changes the ABI of relocatable objects,
851 although it doesn't change the ABI of a fully-linked object. */
852 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS && !TARGET_SYM32)
853
854 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
855 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
856 || ISA_MIPS4 \
857 || ISA_MIPS64 \
858 || ISA_MIPS64R2)
859
860 /* ISA has branch likely instructions (e.g. mips2). */
861 /* Disable branchlikely for tx39 until compare rewrite. They haven't
862 been generated up to this point. */
863 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
864
865 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
866 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
867 || TARGET_MIPS5400 \
868 || TARGET_MIPS5500 \
869 || TARGET_MIPS7000 \
870 || TARGET_MIPS9000 \
871 || TARGET_MAD \
872 || ISA_MIPS32 \
873 || ISA_MIPS32R2 \
874 || ISA_MIPS64 \
875 || ISA_MIPS64R2) \
876 && !TARGET_MIPS16)
877
878 /* ISA has a three-operand multiplication instruction. */
879 #define ISA_HAS_DMUL3 (TARGET_64BIT \
880 && TARGET_OCTEON \
881 && !TARGET_MIPS16)
882
883 /* ISA has the floating-point conditional move instructions introduced
884 in mips4. */
885 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
886 || ISA_MIPS32 \
887 || ISA_MIPS32R2 \
888 || ISA_MIPS64 \
889 || ISA_MIPS64R2) \
890 && !TARGET_MIPS5500 \
891 && !TARGET_MIPS16)
892
893 /* ISA has the integer conditional move instructions introduced in mips4 and
894 ST Loongson 2E/2F. */
895 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
896
897 /* ISA has LDC1 and SDC1. */
898 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
899
900 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
901 branch on CC, and move (both FP and non-FP) on CC. */
902 #define ISA_HAS_8CC (ISA_MIPS4 \
903 || ISA_MIPS32 \
904 || ISA_MIPS32R2 \
905 || ISA_MIPS64 \
906 || ISA_MIPS64R2)
907
908 /* This is a catch all for other mips4 instructions: indexed load, the
909 FP madd and msub instructions, and the FP recip and recip sqrt
910 instructions. */
911 #define ISA_HAS_FP4 ((ISA_MIPS4 \
912 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
913 || ISA_MIPS64 \
914 || ISA_MIPS64R2) \
915 && !TARGET_MIPS16)
916
917 /* ISA has paired-single instructions. */
918 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
919
920 /* ISA has conditional trap instructions. */
921 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
922 && !TARGET_MIPS16)
923
924 /* ISA has integer multiply-accumulate instructions, madd and msub. */
925 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
926 || ISA_MIPS32R2 \
927 || ISA_MIPS64 \
928 || ISA_MIPS64R2) \
929 && !TARGET_MIPS16)
930
931 /* Integer multiply-accumulate instructions should be generated. */
932 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
933
934 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
935 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
936
937 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
938 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
939
940 /* ISA has floating-point nmadd and nmsub instructions
941 'd = -((a * b) [+-] c)'. */
942 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
943 ((ISA_MIPS4 \
944 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
945 || ISA_MIPS64 \
946 || ISA_MIPS64R2) \
947 && (!TARGET_MIPS5400 || TARGET_MAD) \
948 && !TARGET_MIPS16)
949
950 /* ISA has floating-point nmadd and nmsub instructions
951 'c = -((a * b) [+-] c)'. */
952 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
953 TARGET_LOONGSON_2EF
954
955 /* ISA has count leading zeroes/ones instruction (not implemented). */
956 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
957 || ISA_MIPS32R2 \
958 || ISA_MIPS64 \
959 || ISA_MIPS64R2) \
960 && !TARGET_MIPS16)
961
962 /* ISA has three operand multiply instructions that put
963 the high part in an accumulator: mulhi or mulhiu. */
964 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
965 || TARGET_MIPS5500 \
966 || TARGET_SR71K) \
967 && !TARGET_MIPS16)
968
969 /* ISA has three operand multiply instructions that
970 negates the result and puts the result in an accumulator. */
971 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
972 || TARGET_MIPS5500 \
973 || TARGET_SR71K) \
974 && !TARGET_MIPS16)
975
976 /* ISA has three operand multiply instructions that subtracts the
977 result from a 4th operand and puts the result in an accumulator. */
978 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
979 || TARGET_MIPS5500 \
980 || TARGET_SR71K) \
981 && !TARGET_MIPS16)
982
983 /* ISA has three operand multiply instructions that the result
984 from a 4th operand and puts the result in an accumulator. */
985 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
986 || TARGET_MIPS4130 \
987 || TARGET_MIPS5400 \
988 || TARGET_MIPS5500 \
989 || TARGET_SR71K) \
990 && !TARGET_MIPS16)
991
992 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
993 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
994 || TARGET_MIPS4130) \
995 && !TARGET_MIPS16)
996
997 /* ISA has the "ror" (rotate right) instructions. */
998 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
999 || ISA_MIPS64R2 \
1000 || TARGET_MIPS5400 \
1001 || TARGET_MIPS5500 \
1002 || TARGET_SR71K \
1003 || TARGET_SMARTMIPS) \
1004 && !TARGET_MIPS16)
1005
1006 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1007 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1008 || TARGET_LOONGSON_2EF \
1009 || ISA_MIPS32 \
1010 || ISA_MIPS32R2 \
1011 || ISA_MIPS64 \
1012 || ISA_MIPS64R2) \
1013 && !TARGET_MIPS16)
1014
1015 /* ISA has data indexed prefetch instructions. This controls use of
1016 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1017 (prefx is a cop1x instruction, so can only be used if FP is
1018 enabled.) */
1019 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
1020 || ISA_MIPS32R2 \
1021 || ISA_MIPS64 \
1022 || ISA_MIPS64R2) \
1023 && !TARGET_MIPS16)
1024
1025 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1026 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1027 also requires TARGET_DOUBLE_FLOAT. */
1028 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1029
1030 /* ISA includes the MIPS32r2 seb and seh instructions. */
1031 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
1032 || ISA_MIPS64R2) \
1033 && !TARGET_MIPS16)
1034
1035 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1036 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
1037 || ISA_MIPS64R2) \
1038 && !TARGET_MIPS16)
1039
1040 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1041 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
1042 && (ISA_MIPS32R2 \
1043 || ISA_MIPS64R2))
1044
1045 /* ISA has lwxs instruction (load w/scaled index address. */
1046 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
1047
1048 /* The DSP ASE is available. */
1049 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1050
1051 /* Revision 2 of the DSP ASE is available. */
1052 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1053
1054 /* True if the result of a load is not available to the next instruction.
1055 A nop will then be needed between instructions like "lw $4,..."
1056 and "addiu $4,$4,1". */
1057 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1058 && !TARGET_MIPS3900 \
1059 && !TARGET_MIPS16)
1060
1061 /* Likewise mtc1 and mfc1. */
1062 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1063 && !TARGET_LOONGSON_2EF)
1064
1065 /* Likewise floating-point comparisons. */
1066 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1067 && !TARGET_LOONGSON_2EF)
1068
1069 /* True if mflo and mfhi can be immediately followed by instructions
1070 which write to the HI and LO registers.
1071
1072 According to MIPS specifications, MIPS ISAs I, II, and III need
1073 (at least) two instructions between the reads of HI/LO and
1074 instructions which write them, and later ISAs do not. Contradicting
1075 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1076 the UM for the NEC Vr5000) document needing the instructions between
1077 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1078 MIPS64 and later ISAs to have the interlocks, plus any specific
1079 earlier-ISA CPUs for which CPU documentation declares that the
1080 instructions are really interlocked. */
1081 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1082 || ISA_MIPS32R2 \
1083 || ISA_MIPS64 \
1084 || ISA_MIPS64R2 \
1085 || TARGET_MIPS5500 \
1086 || TARGET_LOONGSON_2EF)
1087
1088 /* ISA includes synci, jr.hb and jalr.hb. */
1089 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1090 || ISA_MIPS64R2) \
1091 && !TARGET_MIPS16)
1092
1093 /* ISA includes sync. */
1094 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1095 #define GENERATE_SYNC \
1096 (target_flags_explicit & MASK_LLSC \
1097 ? TARGET_LLSC && !TARGET_MIPS16 \
1098 : ISA_HAS_SYNC)
1099
1100 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1101 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1102 instructions. */
1103 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1104 #define GENERATE_LL_SC \
1105 (target_flags_explicit & MASK_LLSC \
1106 ? TARGET_LLSC && !TARGET_MIPS16 \
1107 : ISA_HAS_LL_SC)
1108
1109 /* ISA includes the baddu instruction. */
1110 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1111
1112 /* ISA includes the bbit* instructions. */
1113 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1114
1115 /* ISA includes the cins instruction. */
1116 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1117
1118 /* ISA includes the exts instruction. */
1119 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1120
1121 /* ISA includes the seq and sne instructions. */
1122 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1123
1124 /* ISA includes the pop instruction. */
1125 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1126
1127 /* The CACHE instruction is available in non-MIPS16 code. */
1128 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1129
1130 /* The CACHE instruction is available. */
1131 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1132 \f
1133 /* Add -G xx support. */
1134
1135 #undef SWITCH_TAKES_ARG
1136 #define SWITCH_TAKES_ARG(CHAR) \
1137 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1138
1139 #define OVERRIDE_OPTIONS mips_override_options ()
1140
1141 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1142
1143 /* Show we can debug even without a frame pointer. */
1144 #define CAN_DEBUG_WITHOUT_FP
1145 \f
1146 /* Tell collect what flags to pass to nm. */
1147 #ifndef NM_FLAGS
1148 #define NM_FLAGS "-Bn"
1149 #endif
1150
1151 \f
1152 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1153 to the assembler. It may be overridden by subtargets. */
1154 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1155 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1156 %{noasmopt:-O0} \
1157 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1158 #endif
1159
1160 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1161 the assembler. It may be overridden by subtargets.
1162
1163 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1164 COFF debugging info. */
1165
1166 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1167 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1168 %{g} %{g0} %{g1} %{g2} %{g3} \
1169 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1170 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1171 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1172 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1173 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1174 #endif
1175
1176 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1177 overridden by subtargets. */
1178
1179 #ifndef SUBTARGET_ASM_SPEC
1180 #define SUBTARGET_ASM_SPEC ""
1181 #endif
1182
1183 #undef ASM_SPEC
1184 #define ASM_SPEC "\
1185 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1186 %{mips32*} %{mips64*} \
1187 %{mips16} %{mno-mips16:-no-mips16} \
1188 %{mips3d} %{mno-mips3d:-no-mips3d} \
1189 %{mdmx} %{mno-mdmx:-no-mdmx} \
1190 %{mdsp} %{mno-dsp} \
1191 %{mdspr2} %{mno-dspr2} \
1192 %{msmartmips} %{mno-smartmips} \
1193 %{mmt} %{mno-mt} \
1194 %{mfix-vr4120} %{mfix-vr4130} \
1195 %(subtarget_asm_optimizing_spec) \
1196 %(subtarget_asm_debugging_spec) \
1197 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1198 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1199 %{mfp32} %{mfp64} \
1200 %{mshared} %{mno-shared} \
1201 %{msym32} %{mno-sym32} \
1202 %{mtune=*} %{v} \
1203 %(subtarget_asm_spec)"
1204
1205 /* Extra switches sometimes passed to the linker. */
1206 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1207 will interpret it as a -b option. */
1208
1209 #ifndef LINK_SPEC
1210 #define LINK_SPEC "\
1211 %(endian_spec) \
1212 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1213 %{bestGnum} %{shared} %{non_shared}"
1214 #endif /* LINK_SPEC defined */
1215
1216
1217 /* Specs for the compiler proper */
1218
1219 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1220 overridden by subtargets. */
1221 #ifndef SUBTARGET_CC1_SPEC
1222 #define SUBTARGET_CC1_SPEC ""
1223 #endif
1224
1225 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1226
1227 #undef CC1_SPEC
1228 #define CC1_SPEC "\
1229 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1230 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1231 %{save-temps: } \
1232 %(subtarget_cc1_spec)"
1233
1234 /* Preprocessor specs. */
1235
1236 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1237 overridden by subtargets. */
1238 #ifndef SUBTARGET_CPP_SPEC
1239 #define SUBTARGET_CPP_SPEC ""
1240 #endif
1241
1242 #define CPP_SPEC "%(subtarget_cpp_spec)"
1243
1244 /* This macro defines names of additional specifications to put in the specs
1245 that can be used in various specifications like CC1_SPEC. Its definition
1246 is an initializer with a subgrouping for each command option.
1247
1248 Each subgrouping contains a string constant, that defines the
1249 specification name, and a string constant that used by the GCC driver
1250 program.
1251
1252 Do not define this macro if it does not need to do anything. */
1253
1254 #define EXTRA_SPECS \
1255 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1256 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1257 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1258 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1259 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1260 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1261 { "endian_spec", ENDIAN_SPEC }, \
1262 SUBTARGET_EXTRA_SPECS
1263
1264 #ifndef SUBTARGET_EXTRA_SPECS
1265 #define SUBTARGET_EXTRA_SPECS
1266 #endif
1267 \f
1268 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1269 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1270
1271 #ifndef PREFERRED_DEBUGGING_TYPE
1272 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1273 #endif
1274
1275 /* The size of DWARF addresses should be the same as the size of symbols
1276 in the target file format. They shouldn't depend on things like -msym32,
1277 because many DWARF consumers do not allow the mixture of address sizes
1278 that one would then get from linking -msym32 code with -msym64 code.
1279
1280 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1281 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1282 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1283
1284 /* By default, turn on GDB extensions. */
1285 #define DEFAULT_GDB_EXTENSIONS 1
1286
1287 /* Local compiler-generated symbols must have a prefix that the assembler
1288 understands. By default, this is $, although some targets (e.g.,
1289 NetBSD-ELF) need to override this. */
1290
1291 #ifndef LOCAL_LABEL_PREFIX
1292 #define LOCAL_LABEL_PREFIX "$"
1293 #endif
1294
1295 /* By default on the mips, external symbols do not have an underscore
1296 prepended, but some targets (e.g., NetBSD) require this. */
1297
1298 #ifndef USER_LABEL_PREFIX
1299 #define USER_LABEL_PREFIX ""
1300 #endif
1301
1302 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1303 since the length can run past this up to a continuation point. */
1304 #undef DBX_CONTIN_LENGTH
1305 #define DBX_CONTIN_LENGTH 1500
1306
1307 /* How to renumber registers for dbx and gdb. */
1308 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1309
1310 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1311 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1312
1313 /* The DWARF 2 CFA column which tracks the return address. */
1314 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1315
1316 /* Before the prologue, RA lives in r31. */
1317 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1318
1319 /* Describe how we implement __builtin_eh_return. */
1320 #define EH_RETURN_DATA_REGNO(N) \
1321 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1322
1323 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1324
1325 #define EH_USES(N) mips_eh_uses (N)
1326
1327 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1328 The default for this in 64-bit mode is 8, which causes problems with
1329 SFmode register saves. */
1330 #define DWARF_CIE_DATA_ALIGNMENT -4
1331
1332 /* Correct the offset of automatic variables and arguments. Note that
1333 the MIPS debug format wants all automatic variables and arguments
1334 to be in terms of the virtual frame pointer (stack pointer before
1335 any adjustment in the function), while the MIPS 3.0 linker wants
1336 the frame pointer to be the stack pointer after the initial
1337 adjustment. */
1338
1339 #define DEBUGGER_AUTO_OFFSET(X) \
1340 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1341 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1342 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1343 \f
1344 /* Target machine storage layout */
1345
1346 #define BITS_BIG_ENDIAN 0
1347 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1348 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1349
1350 /* Define this to set the endianness to use in libgcc2.c, which can
1351 not depend on target_flags. */
1352 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1353 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1354 #else
1355 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1356 #endif
1357
1358 #define MAX_BITS_PER_WORD 64
1359
1360 /* Width of a word, in units (bytes). */
1361 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1362 #ifndef IN_LIBGCC2
1363 #define MIN_UNITS_PER_WORD 4
1364 #endif
1365
1366 /* For MIPS, width of a floating point register. */
1367 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1368
1369 /* The number of consecutive floating-point registers needed to store the
1370 largest format supported by the FPU. */
1371 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1372
1373 /* The number of consecutive floating-point registers needed to store the
1374 smallest format supported by the FPU. */
1375 #define MIN_FPRS_PER_FMT \
1376 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1377 ? 1 : MAX_FPRS_PER_FMT)
1378
1379 /* The largest size of value that can be held in floating-point
1380 registers and moved with a single instruction. */
1381 #define UNITS_PER_HWFPVALUE \
1382 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1383
1384 /* The largest size of value that can be held in floating-point
1385 registers. */
1386 #define UNITS_PER_FPVALUE \
1387 (TARGET_SOFT_FLOAT_ABI ? 0 \
1388 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1389 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1390
1391 /* The number of bytes in a double. */
1392 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1393
1394 #define UNITS_PER_SIMD_WORD(MODE) \
1395 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1396
1397 /* Set the sizes of the core types. */
1398 #define SHORT_TYPE_SIZE 16
1399 #define INT_TYPE_SIZE 32
1400 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1401 #define LONG_LONG_TYPE_SIZE 64
1402
1403 #define FLOAT_TYPE_SIZE 32
1404 #define DOUBLE_TYPE_SIZE 64
1405 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1406
1407 /* Define the sizes of fixed-point types. */
1408 #define SHORT_FRACT_TYPE_SIZE 8
1409 #define FRACT_TYPE_SIZE 16
1410 #define LONG_FRACT_TYPE_SIZE 32
1411 #define LONG_LONG_FRACT_TYPE_SIZE 64
1412
1413 #define SHORT_ACCUM_TYPE_SIZE 16
1414 #define ACCUM_TYPE_SIZE 32
1415 #define LONG_ACCUM_TYPE_SIZE 64
1416 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1417 doesn't support 128-bit integers for MIPS32 currently. */
1418 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1419
1420 /* long double is not a fixed mode, but the idea is that, if we
1421 support long double, we also want a 128-bit integer type. */
1422 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1423
1424 #ifdef IN_LIBGCC2
1425 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1426 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1427 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1428 # else
1429 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1430 # endif
1431 #endif
1432
1433 /* Width in bits of a pointer. */
1434 #ifndef POINTER_SIZE
1435 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1436 #endif
1437
1438 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1439 #define PARM_BOUNDARY BITS_PER_WORD
1440
1441 /* Allocation boundary (in *bits*) for the code of a function. */
1442 #define FUNCTION_BOUNDARY 32
1443
1444 /* Alignment of field after `int : 0' in a structure. */
1445 #define EMPTY_FIELD_BOUNDARY 32
1446
1447 /* Every structure's size must be a multiple of this. */
1448 /* 8 is observed right on a DECstation and on riscos 4.02. */
1449 #define STRUCTURE_SIZE_BOUNDARY 8
1450
1451 /* There is no point aligning anything to a rounder boundary than this. */
1452 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1453
1454 /* All accesses must be aligned. */
1455 #define STRICT_ALIGNMENT 1
1456
1457 /* Define this if you wish to imitate the way many other C compilers
1458 handle alignment of bitfields and the structures that contain
1459 them.
1460
1461 The behavior is that the type written for a bit-field (`int',
1462 `short', or other integer type) imposes an alignment for the
1463 entire structure, as if the structure really did contain an
1464 ordinary field of that type. In addition, the bit-field is placed
1465 within the structure so that it would fit within such a field,
1466 not crossing a boundary for it.
1467
1468 Thus, on most machines, a bit-field whose type is written as `int'
1469 would not cross a four-byte boundary, and would force four-byte
1470 alignment for the whole structure. (The alignment used may not
1471 be four bytes; it is controlled by the other alignment
1472 parameters.)
1473
1474 If the macro is defined, its definition should be a C expression;
1475 a nonzero value for the expression enables this behavior. */
1476
1477 #define PCC_BITFIELD_TYPE_MATTERS 1
1478
1479 /* If defined, a C expression to compute the alignment given to a
1480 constant that is being placed in memory. CONSTANT is the constant
1481 and ALIGN is the alignment that the object would ordinarily have.
1482 The value of this macro is used instead of that alignment to align
1483 the object.
1484
1485 If this macro is not defined, then ALIGN is used.
1486
1487 The typical use of this macro is to increase alignment for string
1488 constants to be word aligned so that `strcpy' calls that copy
1489 constants can be done inline. */
1490
1491 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1492 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1493 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1494
1495 /* If defined, a C expression to compute the alignment for a static
1496 variable. TYPE is the data type, and ALIGN is the alignment that
1497 the object would ordinarily have. The value of this macro is used
1498 instead of that alignment to align the object.
1499
1500 If this macro is not defined, then ALIGN is used.
1501
1502 One use of this macro is to increase alignment of medium-size
1503 data to make it all fit in fewer cache lines. Another is to
1504 cause character arrays to be word-aligned so that `strcpy' calls
1505 that copy constants to character arrays can be done inline. */
1506
1507 #undef DATA_ALIGNMENT
1508 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1509 ((((ALIGN) < BITS_PER_WORD) \
1510 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1511 || TREE_CODE (TYPE) == UNION_TYPE \
1512 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1513
1514 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1515 character arrays to be word-aligned so that `strcpy' calls that copy
1516 constants to character arrays can be done inline, and 'strcmp' can be
1517 optimised to use word loads. */
1518 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1519 DATA_ALIGNMENT (TYPE, ALIGN)
1520
1521 #define PAD_VARARGS_DOWN \
1522 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1523
1524 /* Define if operations between registers always perform the operation
1525 on the full register even if a narrower mode is specified. */
1526 #define WORD_REGISTER_OPERATIONS
1527
1528 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1529 moves. All other references are zero extended. */
1530 #define LOAD_EXTEND_OP(MODE) \
1531 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1532 ? SIGN_EXTEND : ZERO_EXTEND)
1533
1534 /* Define this macro if it is advisable to hold scalars in registers
1535 in a wider mode than that declared by the program. In such cases,
1536 the value is constrained to be within the bounds of the declared
1537 type, but kept valid in the wider mode. The signedness of the
1538 extension may differ from that of the type. */
1539
1540 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1541 if (GET_MODE_CLASS (MODE) == MODE_INT \
1542 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1543 { \
1544 if ((MODE) == SImode) \
1545 (UNSIGNEDP) = 0; \
1546 (MODE) = Pmode; \
1547 }
1548
1549 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1550 Extensions of pointers to word_mode must be signed. */
1551 #define POINTERS_EXTEND_UNSIGNED false
1552
1553 /* Define if loading short immediate values into registers sign extends. */
1554 #define SHORT_IMMEDIATES_SIGN_EXTEND
1555
1556 /* The [d]clz instructions have the natural values at 0. */
1557
1558 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1559 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1560 \f
1561 /* Standard register usage. */
1562
1563 /* Number of hardware registers. We have:
1564
1565 - 32 integer registers
1566 - 32 floating point registers
1567 - 8 condition code registers
1568 - 2 accumulator registers (hi and lo)
1569 - 32 registers each for coprocessors 0, 2 and 3
1570 - 4 fake registers:
1571 - ARG_POINTER_REGNUM
1572 - FRAME_POINTER_REGNUM
1573 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1574 - CPRESTORE_SLOT_REGNUM
1575 - 2 dummy entries that were used at various times in the past.
1576 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1577 - 6 DSP control registers */
1578
1579 #define FIRST_PSEUDO_REGISTER 188
1580
1581 /* By default, fix the kernel registers ($26 and $27), the global
1582 pointer ($28) and the stack pointer ($29). This can change
1583 depending on the command-line options.
1584
1585 Regarding coprocessor registers: without evidence to the contrary,
1586 it's best to assume that each coprocessor register has a unique
1587 use. This can be overridden, in, e.g., mips_override_options or
1588 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1589 for a particular target. */
1590
1591 #define FIXED_REGISTERS \
1592 { \
1593 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1596 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1597 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1598 /* COP0 registers */ \
1599 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1600 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1601 /* COP2 registers */ \
1602 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1603 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1604 /* COP3 registers */ \
1605 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1606 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1607 /* 6 DSP accumulator registers & 6 control registers */ \
1608 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1609 }
1610
1611
1612 /* Set up this array for o32 by default.
1613
1614 Note that we don't mark $31 as a call-clobbered register. The idea is
1615 that it's really the call instructions themselves which clobber $31.
1616 We don't care what the called function does with it afterwards.
1617
1618 This approach makes it easier to implement sibcalls. Unlike normal
1619 calls, sibcalls don't clobber $31, so the register reaches the
1620 called function in tact. EPILOGUE_USES says that $31 is useful
1621 to the called function. */
1622
1623 #define CALL_USED_REGISTERS \
1624 { \
1625 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1626 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1627 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1628 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1629 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1630 /* COP0 registers */ \
1631 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1632 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1633 /* COP2 registers */ \
1634 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1635 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1636 /* COP3 registers */ \
1637 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1638 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1639 /* 6 DSP accumulator registers & 6 control registers */ \
1640 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1641 }
1642
1643
1644 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1645
1646 #define CALL_REALLY_USED_REGISTERS \
1647 { /* General registers. */ \
1648 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1649 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1650 /* Floating-point registers. */ \
1651 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1652 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1653 /* Others. */ \
1654 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1655 /* COP0 registers */ \
1656 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1657 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1658 /* COP2 registers */ \
1659 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1660 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1661 /* COP3 registers */ \
1662 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1663 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1664 /* 6 DSP accumulator registers & 6 control registers */ \
1665 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1666 }
1667
1668 /* Internal macros to classify a register number as to whether it's a
1669 general purpose register, a floating point register, a
1670 multiply/divide register, or a status register. */
1671
1672 #define GP_REG_FIRST 0
1673 #define GP_REG_LAST 31
1674 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1675 #define GP_DBX_FIRST 0
1676 #define K0_REG_NUM (GP_REG_FIRST + 26)
1677 #define K1_REG_NUM (GP_REG_FIRST + 27)
1678 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1679
1680 #define FP_REG_FIRST 32
1681 #define FP_REG_LAST 63
1682 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1683 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1684
1685 #define MD_REG_FIRST 64
1686 #define MD_REG_LAST 65
1687 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1688 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1689
1690 /* The DWARF 2 CFA column which tracks the return address from a
1691 signal handler context. This means that to maintain backwards
1692 compatibility, no hard register can be assigned this column if it
1693 would need to be handled by the DWARF unwinder. */
1694 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1695
1696 #define ST_REG_FIRST 67
1697 #define ST_REG_LAST 74
1698 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1699
1700
1701 /* FIXME: renumber. */
1702 #define COP0_REG_FIRST 80
1703 #define COP0_REG_LAST 111
1704 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1705
1706 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1707 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1708 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1709
1710 #define COP2_REG_FIRST 112
1711 #define COP2_REG_LAST 143
1712 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1713
1714 #define COP3_REG_FIRST 144
1715 #define COP3_REG_LAST 175
1716 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1717 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1718 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1719
1720 #define DSP_ACC_REG_FIRST 176
1721 #define DSP_ACC_REG_LAST 181
1722 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1723
1724 #define AT_REGNUM (GP_REG_FIRST + 1)
1725 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1726 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1727
1728 /* A few bitfield locations for the coprocessor registers. */
1729 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1730 the cause register for the EIC interrupt mode. */
1731 #define CAUSE_IPL 10
1732 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1733 #define SR_IPL 10
1734 /* Exception Level is at bit 1 of the status register. */
1735 #define SR_EXL 1
1736 /* Interrupt Enable is at bit 0 of the status register. */
1737 #define SR_IE 0
1738
1739 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1740 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1741 should be used instead. */
1742 #define FPSW_REGNUM ST_REG_FIRST
1743
1744 #define GP_REG_P(REGNO) \
1745 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1746 #define M16_REG_P(REGNO) \
1747 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1748 #define FP_REG_P(REGNO) \
1749 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1750 #define MD_REG_P(REGNO) \
1751 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1752 #define ST_REG_P(REGNO) \
1753 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1754 #define COP0_REG_P(REGNO) \
1755 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1756 #define COP2_REG_P(REGNO) \
1757 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1758 #define COP3_REG_P(REGNO) \
1759 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1760 #define ALL_COP_REG_P(REGNO) \
1761 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1762 /* Test if REGNO is one of the 6 new DSP accumulators. */
1763 #define DSP_ACC_REG_P(REGNO) \
1764 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1765 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1766 #define ACC_REG_P(REGNO) \
1767 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1768
1769 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1770
1771 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1772 to initialize the mips16 gp pseudo register. */
1773 #define CONST_GP_P(X) \
1774 (GET_CODE (X) == CONST \
1775 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1776 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1777
1778 /* Return coprocessor number from register number. */
1779
1780 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1781 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1782 : COP3_REG_P (REGNO) ? '3' : '?')
1783
1784
1785 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1786
1787 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1788 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1789
1790 #define MODES_TIEABLE_P mips_modes_tieable_p
1791
1792 /* Register to use for pushing function arguments. */
1793 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1794
1795 /* These two registers don't really exist: they get eliminated to either
1796 the stack or hard frame pointer. */
1797 #define ARG_POINTER_REGNUM 77
1798 #define FRAME_POINTER_REGNUM 78
1799
1800 /* $30 is not available on the mips16, so we use $17 as the frame
1801 pointer. */
1802 #define HARD_FRAME_POINTER_REGNUM \
1803 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1804
1805 /* Register in which static-chain is passed to a function. */
1806 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1807
1808 /* Registers used as temporaries in prologue/epilogue code:
1809
1810 - If a MIPS16 PIC function needs access to _gp, it first loads
1811 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1812
1813 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1814 register. The register must not conflict with MIPS16_PIC_TEMP.
1815
1816 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1817 register.
1818
1819 If we're generating MIPS16 code, these registers must come from the
1820 core set of 8. The prologue registers mustn't conflict with any
1821 incoming arguments, the static chain pointer, or the frame pointer.
1822 The epilogue temporary mustn't conflict with the return registers,
1823 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1824 or the EH data registers.
1825
1826 If we're generating interrupt handlers, we use K0 as a temporary register
1827 in prologue/epilogue code. */
1828
1829 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1830 #define MIPS_PROLOGUE_TEMP_REGNUM \
1831 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1832 #define MIPS_EPILOGUE_TEMP_REGNUM \
1833 (cfun->machine->interrupt_handler_p \
1834 ? K0_REG_NUM \
1835 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1836
1837 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1838 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1839 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1840
1841 /* Define this macro if it is as good or better to call a constant
1842 function address than to call an address kept in a register. */
1843 #define NO_FUNCTION_CSE 1
1844
1845 /* The ABI-defined global pointer. Sometimes we use a different
1846 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1847 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1848
1849 /* We normally use $28 as the global pointer. However, when generating
1850 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1851 register instead. They can then avoid saving and restoring $28
1852 and perhaps avoid using a frame at all.
1853
1854 When a leaf function uses something other than $28, mips_expand_prologue
1855 will modify pic_offset_table_rtx in place. Take the register number
1856 from there after reload. */
1857 #define PIC_OFFSET_TABLE_REGNUM \
1858 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1859
1860 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1861 \f
1862 /* Define the classes of registers for register constraints in the
1863 machine description. Also define ranges of constants.
1864
1865 One of the classes must always be named ALL_REGS and include all hard regs.
1866 If there is more than one class, another class must be named NO_REGS
1867 and contain no registers.
1868
1869 The name GENERAL_REGS must be the name of a class (or an alias for
1870 another name such as ALL_REGS). This is the class of registers
1871 that is allowed by "g" or "r" in a register constraint.
1872 Also, registers outside this class are allocated only when
1873 instructions express preferences for them.
1874
1875 The classes must be numbered in nondecreasing order; that is,
1876 a larger-numbered class must never be contained completely
1877 in a smaller-numbered class.
1878
1879 For any two classes, it is very desirable that there be another
1880 class that represents their union. */
1881
1882 enum reg_class
1883 {
1884 NO_REGS, /* no registers in set */
1885 M16_REGS, /* mips16 directly accessible registers */
1886 T_REG, /* mips16 T register ($24) */
1887 M16_T_REGS, /* mips16 registers plus T register */
1888 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1889 V1_REG, /* Register $v1 ($3) used for TLS access. */
1890 LEA_REGS, /* Every GPR except $25 */
1891 GR_REGS, /* integer registers */
1892 FP_REGS, /* floating point registers */
1893 MD0_REG, /* first multiply/divide register */
1894 MD1_REG, /* second multiply/divide register */
1895 MD_REGS, /* multiply/divide registers (hi/lo) */
1896 COP0_REGS, /* generic coprocessor classes */
1897 COP2_REGS,
1898 COP3_REGS,
1899 ST_REGS, /* status registers (fp status) */
1900 DSP_ACC_REGS, /* DSP accumulator registers */
1901 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1902 FRAME_REGS, /* $arg and $frame */
1903 GR_AND_MD0_REGS, /* union classes */
1904 GR_AND_MD1_REGS,
1905 GR_AND_MD_REGS,
1906 GR_AND_ACC_REGS,
1907 ALL_REGS, /* all registers */
1908 LIM_REG_CLASSES /* max value + 1 */
1909 };
1910
1911 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1912
1913 #define GENERAL_REGS GR_REGS
1914
1915 /* An initializer containing the names of the register classes as C
1916 string constants. These names are used in writing some of the
1917 debugging dumps. */
1918
1919 #define REG_CLASS_NAMES \
1920 { \
1921 "NO_REGS", \
1922 "M16_REGS", \
1923 "T_REG", \
1924 "M16_T_REGS", \
1925 "PIC_FN_ADDR_REG", \
1926 "V1_REG", \
1927 "LEA_REGS", \
1928 "GR_REGS", \
1929 "FP_REGS", \
1930 "MD0_REG", \
1931 "MD1_REG", \
1932 "MD_REGS", \
1933 /* coprocessor registers */ \
1934 "COP0_REGS", \
1935 "COP2_REGS", \
1936 "COP3_REGS", \
1937 "ST_REGS", \
1938 "DSP_ACC_REGS", \
1939 "ACC_REGS", \
1940 "FRAME_REGS", \
1941 "GR_AND_MD0_REGS", \
1942 "GR_AND_MD1_REGS", \
1943 "GR_AND_MD_REGS", \
1944 "GR_AND_ACC_REGS", \
1945 "ALL_REGS" \
1946 }
1947
1948 /* An initializer containing the contents of the register classes,
1949 as integers which are bit masks. The Nth integer specifies the
1950 contents of class N. The way the integer MASK is interpreted is
1951 that register R is in the class if `MASK & (1 << R)' is 1.
1952
1953 When the machine has more than 32 registers, an integer does not
1954 suffice. Then the integers are replaced by sub-initializers,
1955 braced groupings containing several integers. Each
1956 sub-initializer must be suitable as an initializer for the type
1957 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1958
1959 #define REG_CLASS_CONTENTS \
1960 { \
1961 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1962 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1963 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1964 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1965 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1966 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1967 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1968 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1969 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1970 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1971 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1972 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1973 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1974 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1975 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1976 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1977 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1978 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1979 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1980 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1981 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1982 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1983 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1984 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1985 }
1986
1987
1988 /* A C expression whose value is a register class containing hard
1989 register REGNO. In general there is more that one such class;
1990 choose a class which is "minimal", meaning that no smaller class
1991 also contains the register. */
1992
1993 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1994
1995 /* A macro whose definition is the name of the class to which a
1996 valid base register must belong. A base register is one used in
1997 an address which is the register value plus a displacement. */
1998
1999 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2000
2001 /* A macro whose definition is the name of the class to which a
2002 valid index register must belong. An index register is one used
2003 in an address where its value is either multiplied by a scale
2004 factor or added to another register (as well as added to a
2005 displacement). */
2006
2007 #define INDEX_REG_CLASS NO_REGS
2008
2009 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2010 registers explicitly used in the rtl to be used as spill registers
2011 but prevents the compiler from extending the lifetime of these
2012 registers. */
2013
2014 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2015
2016 /* We generally want to put call-clobbered registers ahead of
2017 call-saved ones. (IRA expects this.) */
2018
2019 #define REG_ALLOC_ORDER \
2020 { /* Accumulator registers. When GPRs and accumulators have equal \
2021 cost, we generally prefer to use accumulators. For example, \
2022 a division of multiplication result is better allocated to LO, \
2023 so that we put the MFLO at the point of use instead of at the \
2024 point of definition. It's also needed if we're to take advantage \
2025 of the extra accumulators available with -mdspr2. In some cases, \
2026 it can also help to reduce register pressure. */ \
2027 64, 65,176,177,178,179,180,181, \
2028 /* Call-clobbered GPRs. */ \
2029 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2030 24, 25, 31, \
2031 /* The global pointer. This is call-clobbered for o32 and o64 \
2032 abicalls, call-saved for n32 and n64 abicalls, and a program \
2033 invariant otherwise. Putting it between the call-clobbered \
2034 and call-saved registers should cope with all eventualities. */ \
2035 28, \
2036 /* Call-saved GPRs. */ \
2037 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2038 /* GPRs that can never be exposed to the register allocator. */ \
2039 0, 26, 27, 29, \
2040 /* Call-clobbered FPRs. */ \
2041 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2042 48, 49, 50, 51, \
2043 /* FPRs that are usually call-saved. The odd ones are actually \
2044 call-clobbered for n32, but listing them ahead of the even \
2045 registers might encourage the register allocator to fragment \
2046 the available FPR pairs. We need paired FPRs to store long \
2047 doubles, so it isn't clear that using a different order \
2048 for n32 would be a win. */ \
2049 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2050 /* None of the remaining classes have defined call-saved \
2051 registers. */ \
2052 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2053 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2054 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2055 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2056 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2057 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2058 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2059 182,183,184,185,186,187 \
2060 }
2061
2062 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2063 to be rearranged based on a particular function. On the mips16, we
2064 want to allocate $24 (T_REG) before other registers for
2065 instructions for which it is possible. */
2066
2067 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2068
2069 /* True if VALUE is an unsigned 6-bit number. */
2070
2071 #define UIMM6_OPERAND(VALUE) \
2072 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2073
2074 /* True if VALUE is a signed 10-bit number. */
2075
2076 #define IMM10_OPERAND(VALUE) \
2077 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2078
2079 /* True if VALUE is a signed 16-bit number. */
2080
2081 #define SMALL_OPERAND(VALUE) \
2082 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2083
2084 /* True if VALUE is an unsigned 16-bit number. */
2085
2086 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2087 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2088
2089 /* True if VALUE can be loaded into a register using LUI. */
2090
2091 #define LUI_OPERAND(VALUE) \
2092 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2093 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2094
2095 /* Return a value X with the low 16 bits clear, and such that
2096 VALUE - X is a signed 16-bit value. */
2097
2098 #define CONST_HIGH_PART(VALUE) \
2099 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2100
2101 #define CONST_LOW_PART(VALUE) \
2102 ((VALUE) - CONST_HIGH_PART (VALUE))
2103
2104 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2105 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2106 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2107
2108 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2109 mips_preferred_reload_class (X, CLASS)
2110
2111 /* The HI and LO registers can only be reloaded via the general
2112 registers. Condition code registers can only be loaded to the
2113 general registers, and from the floating point registers. */
2114
2115 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2116 mips_secondary_reload_class (CLASS, MODE, X, true)
2117 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2118 mips_secondary_reload_class (CLASS, MODE, X, false)
2119
2120 /* Return the maximum number of consecutive registers
2121 needed to represent mode MODE in a register of class CLASS. */
2122
2123 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2124
2125 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2126 mips_cannot_change_mode_class (FROM, TO, CLASS)
2127 \f
2128 /* Stack layout; function entry, exit and calling. */
2129
2130 #define STACK_GROWS_DOWNWARD
2131
2132 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2133
2134 /* Size of the area allocated in the frame to save the GP. */
2135
2136 #define MIPS_GP_SAVE_AREA_SIZE \
2137 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2138
2139 /* The offset of the first local variable from the frame pointer. See
2140 mips_compute_frame_info for details about the frame layout. */
2141
2142 #define STARTING_FRAME_OFFSET \
2143 (FRAME_GROWS_DOWNWARD \
2144 ? 0 \
2145 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2146
2147 #define RETURN_ADDR_RTX mips_return_addr
2148
2149 /* Mask off the MIPS16 ISA bit in unwind addresses.
2150
2151 The reason for this is a little subtle. When unwinding a call,
2152 we are given the call's return address, which on most targets
2153 is the address of the following instruction. However, what we
2154 actually want to find is the EH region for the call itself.
2155 The target-independent unwind code therefore searches for "RA - 1".
2156
2157 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2158 RA - 1 is therefore the real (even-valued) start of the return
2159 instruction. EH region labels are usually odd-valued MIPS16 symbols
2160 too, so a search for an even address within a MIPS16 region would
2161 usually work.
2162
2163 However, there is an exception. If the end of an EH region is also
2164 the end of a function, the end label is allowed to be even. This is
2165 necessary because a following non-MIPS16 function may also need EH
2166 information for its first instruction.
2167
2168 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2169 non-ISA-encoded address. This probably isn't ideal, but it is
2170 the traditional (legacy) behavior. It is therefore only safe
2171 to search MIPS EH regions for an _odd-valued_ address.
2172
2173 Masking off the ISA bit means that the target-independent code
2174 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2175 #define MASK_RETURN_ADDR GEN_INT (-2)
2176
2177
2178 /* Similarly, don't use the least-significant bit to tell pointers to
2179 code from vtable index. */
2180
2181 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2182
2183 /* The eliminations to $17 are only used for mips16 code. See the
2184 definition of HARD_FRAME_POINTER_REGNUM. */
2185
2186 #define ELIMINABLE_REGS \
2187 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2188 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2189 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2190 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2191 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2192 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2193
2194 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2195 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2196
2197 /* Allocate stack space for arguments at the beginning of each function. */
2198 #define ACCUMULATE_OUTGOING_ARGS 1
2199
2200 /* The argument pointer always points to the first argument. */
2201 #define FIRST_PARM_OFFSET(FNDECL) 0
2202
2203 /* o32 and o64 reserve stack space for all argument registers. */
2204 #define REG_PARM_STACK_SPACE(FNDECL) \
2205 (TARGET_OLDABI \
2206 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2207 : 0)
2208
2209 /* Define this if it is the responsibility of the caller to
2210 allocate the area reserved for arguments passed in registers.
2211 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2212 of this macro is to determine whether the space is included in
2213 `crtl->outgoing_args_size'. */
2214 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2215
2216 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2217 \f
2218 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2219
2220 /* Symbolic macros for the registers used to return integer and floating
2221 point values. */
2222
2223 #define GP_RETURN (GP_REG_FIRST + 2)
2224 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2225
2226 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2227
2228 /* Symbolic macros for the first/last argument registers. */
2229
2230 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2231 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2232 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2233 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2234
2235 #define LIBCALL_VALUE(MODE) \
2236 mips_function_value (NULL_TREE, NULL_TREE, MODE)
2237
2238 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2239 mips_function_value (VALTYPE, FUNC, VOIDmode)
2240
2241 /* 1 if N is a possible register number for a function value.
2242 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2243 Currently, R2 and F0 are only implemented here (C has no complex type) */
2244
2245 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2246 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2247 && (N) == FP_RETURN + 2))
2248
2249 /* 1 if N is a possible register number for function argument passing.
2250 We have no FP argument registers when soft-float. When FP registers
2251 are 32 bits, we can't directly reference the odd numbered ones. */
2252
2253 #define FUNCTION_ARG_REGNO_P(N) \
2254 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2255 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2256 && !fixed_regs[N])
2257 \f
2258 /* This structure has to cope with two different argument allocation
2259 schemes. Most MIPS ABIs view the arguments as a structure, of which
2260 the first N words go in registers and the rest go on the stack. If I
2261 < N, the Ith word might go in Ith integer argument register or in a
2262 floating-point register. For these ABIs, we only need to remember
2263 the offset of the current argument into the structure.
2264
2265 The EABI instead allocates the integer and floating-point arguments
2266 separately. The first N words of FP arguments go in FP registers,
2267 the rest go on the stack. Likewise, the first N words of the other
2268 arguments go in integer registers, and the rest go on the stack. We
2269 need to maintain three counts: the number of integer registers used,
2270 the number of floating-point registers used, and the number of words
2271 passed on the stack.
2272
2273 We could keep separate information for the two ABIs (a word count for
2274 the standard ABIs, and three separate counts for the EABI). But it
2275 seems simpler to view the standard ABIs as forms of EABI that do not
2276 allocate floating-point registers.
2277
2278 So for the standard ABIs, the first N words are allocated to integer
2279 registers, and mips_function_arg decides on an argument-by-argument
2280 basis whether that argument should really go in an integer register,
2281 or in a floating-point one. */
2282
2283 typedef struct mips_args {
2284 /* Always true for varargs functions. Otherwise true if at least
2285 one argument has been passed in an integer register. */
2286 int gp_reg_found;
2287
2288 /* The number of arguments seen so far. */
2289 unsigned int arg_number;
2290
2291 /* The number of integer registers used so far. For all ABIs except
2292 EABI, this is the number of words that have been added to the
2293 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2294 unsigned int num_gprs;
2295
2296 /* For EABI, the number of floating-point registers used so far. */
2297 unsigned int num_fprs;
2298
2299 /* The number of words passed on the stack. */
2300 unsigned int stack_words;
2301
2302 /* On the mips16, we need to keep track of which floating point
2303 arguments were passed in general registers, but would have been
2304 passed in the FP regs if this were a 32-bit function, so that we
2305 can move them to the FP regs if we wind up calling a 32-bit
2306 function. We record this information in fp_code, encoded in base
2307 four. A zero digit means no floating point argument, a one digit
2308 means an SFmode argument, and a two digit means a DFmode argument,
2309 and a three digit is not used. The low order digit is the first
2310 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2311 an SFmode argument. ??? A more sophisticated approach will be
2312 needed if MIPS_ABI != ABI_32. */
2313 int fp_code;
2314
2315 /* True if the function has a prototype. */
2316 int prototype;
2317 } CUMULATIVE_ARGS;
2318
2319 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2320 for a call to a function whose data type is FNTYPE.
2321 For a library call, FNTYPE is 0. */
2322
2323 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2324 mips_init_cumulative_args (&CUM, FNTYPE)
2325
2326 /* Update the data in CUM to advance over an argument
2327 of mode MODE and data type TYPE.
2328 (TYPE is null for libcalls where that information may not be available.) */
2329
2330 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2331 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
2332
2333 /* Determine where to put an argument to a function.
2334 Value is zero to push the argument on the stack,
2335 or a hard register in which to store the argument.
2336
2337 MODE is the argument's machine mode.
2338 TYPE is the data type of the argument (as a tree).
2339 This is null for libcalls where that information may
2340 not be available.
2341 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2342 the preceding args and about the function being called.
2343 NAMED is nonzero if this argument is a named parameter
2344 (otherwise it is an extra parameter matching an ellipsis). */
2345
2346 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2347 mips_function_arg (&CUM, MODE, TYPE, NAMED)
2348
2349 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2350
2351 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2352 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2353
2354 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2355 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2356
2357 /* True if using EABI and varargs can be passed in floating-point
2358 registers. Under these conditions, we need a more complex form
2359 of va_list, which tracks GPR, FPR and stack arguments separately. */
2360 #define EABI_FLOAT_VARARGS_P \
2361 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2362
2363 \f
2364 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2365
2366 /* Treat LOC as a byte offset from the stack pointer and round it up
2367 to the next fully-aligned offset. */
2368 #define MIPS_STACK_ALIGN(LOC) \
2369 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2370
2371 \f
2372 /* Output assembler code to FILE to increment profiler label # LABELNO
2373 for profiling a function entry. */
2374
2375 #define FUNCTION_PROFILER(FILE, LABELNO) \
2376 { \
2377 if (TARGET_MIPS16) \
2378 sorry ("mips16 function profiling"); \
2379 if (TARGET_LONG_CALLS) \
2380 { \
2381 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */ \
2382 if (Pmode == DImode) \
2383 fprintf (FILE, "\tdla\t%s,_mcount\n", reg_names[GP_REG_FIRST + 3]); \
2384 else \
2385 fprintf (FILE, "\tla\t%s,_mcount\n", reg_names[GP_REG_FIRST + 3]); \
2386 } \
2387 mips_push_asm_switch (&mips_noat); \
2388 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2389 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2390 /* _mcount treats $2 as the static chain register. */ \
2391 if (cfun->static_chain_decl != NULL) \
2392 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[2], \
2393 reg_names[STATIC_CHAIN_REGNUM]); \
2394 if (!TARGET_NEWABI) \
2395 { \
2396 fprintf (FILE, \
2397 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2398 TARGET_64BIT ? "dsubu" : "subu", \
2399 reg_names[STACK_POINTER_REGNUM], \
2400 reg_names[STACK_POINTER_REGNUM], \
2401 Pmode == DImode ? 16 : 8); \
2402 } \
2403 if (TARGET_LONG_CALLS) \
2404 fprintf (FILE, "\tjalr\t%s\n", reg_names[GP_REG_FIRST + 3]); \
2405 else \
2406 fprintf (FILE, "\tjal\t_mcount\n"); \
2407 mips_pop_asm_switch (&mips_noat); \
2408 /* _mcount treats $2 as the static chain register. */ \
2409 if (cfun->static_chain_decl != NULL) \
2410 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], \
2411 reg_names[2]); \
2412 }
2413
2414 /* The profiler preserves all interesting registers, including $31. */
2415 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2416
2417 /* No mips port has ever used the profiler counter word, so don't emit it
2418 or the label for it. */
2419
2420 #define NO_PROFILE_COUNTERS 1
2421
2422 /* Define this macro if the code for function profiling should come
2423 before the function prologue. Normally, the profiling code comes
2424 after. */
2425
2426 /* #define PROFILE_BEFORE_PROLOGUE */
2427
2428 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2429 the stack pointer does not matter. The value is tested only in
2430 functions that have frame pointers.
2431 No definition is equivalent to always zero. */
2432
2433 #define EXIT_IGNORE_STACK 1
2434
2435 \f
2436 /* A C statement to output, on the stream FILE, assembler code for a
2437 block of data that contains the constant parts of a trampoline.
2438 This code should not include a label--the label is taken care of
2439 automatically. */
2440
2441 #define TRAMPOLINE_TEMPLATE(STREAM) \
2442 { \
2443 if (ptr_mode == DImode) \
2444 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2445 else \
2446 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2447 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2448 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2449 if (ptr_mode == DImode) \
2450 { \
2451 fprintf (STREAM, "\t.word\t0xdff90014\t\t# ld $25,20($31)\n"); \
2452 fprintf (STREAM, "\t.word\t0xdfef001c\t\t# ld $15,28($31)\n"); \
2453 } \
2454 else \
2455 { \
2456 fprintf (STREAM, "\t.word\t0x8ff90010\t\t# lw $25,16($31)\n"); \
2457 fprintf (STREAM, "\t.word\t0x8fef0014\t\t# lw $15,20($31)\n"); \
2458 } \
2459 fprintf (STREAM, "\t.word\t0x03200008\t\t# jr $25\n"); \
2460 if (ptr_mode == DImode) \
2461 { \
2462 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2463 fprintf (STREAM, "\t.word\t0x00000000\t\t# <padding>\n"); \
2464 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2465 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2466 } \
2467 else \
2468 { \
2469 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2470 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2471 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2472 } \
2473 }
2474
2475 /* A C expression for the size in bytes of the trampoline, as an
2476 integer. */
2477
2478 #define TRAMPOLINE_SIZE (ptr_mode == DImode ? 48 : 36)
2479
2480 /* Alignment required for trampolines, in bits. */
2481
2482 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2483
2484 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2485 program and data caches. */
2486
2487 #ifndef CACHE_FLUSH_FUNC
2488 #define CACHE_FLUSH_FUNC "_flush_cache"
2489 #endif
2490
2491 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2492 /* Flush both caches. We need to flush the data cache in case \
2493 the system has a write-back cache. */ \
2494 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2495 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2496 GEN_INT (3), TYPE_MODE (integer_type_node))
2497
2498 /* A C statement to initialize the variable parts of a trampoline.
2499 ADDR is an RTX for the address of the trampoline; FNADDR is an
2500 RTX for the address of the nested function; STATIC_CHAIN is an
2501 RTX for the static chain value that should be passed to the
2502 function when it is called. */
2503
2504 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2505 { \
2506 rtx func_addr, chain_addr, end_addr; \
2507 \
2508 func_addr = plus_constant (ADDR, ptr_mode == DImode ? 32 : 28); \
2509 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2510 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2511 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2512 end_addr = gen_reg_rtx (Pmode); \
2513 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2514 GEN_INT (TRAMPOLINE_SIZE))); \
2515 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2516 }
2517 \f
2518 /* Addressing modes, and classification of registers for them. */
2519
2520 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2521 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2522 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2523
2524 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2525 and check its validity for a certain class.
2526 We have two alternate definitions for each of them.
2527 The usual definition accepts all pseudo regs; the other rejects them all.
2528 The symbol REG_OK_STRICT causes the latter definition to be used.
2529
2530 Most source files want to accept pseudo regs in the hope that
2531 they will get allocated to the class that the insn wants them to be in.
2532 Some source files that are used after register allocation
2533 need to be strict. */
2534
2535 #ifndef REG_OK_STRICT
2536 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2537 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2538 #else
2539 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2540 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2541 #endif
2542
2543 #define REG_OK_FOR_INDEX_P(X) 0
2544
2545 \f
2546 /* Maximum number of registers that can appear in a valid memory address. */
2547
2548 #define MAX_REGS_PER_ADDRESS 1
2549
2550 /* Check for constness inline but use mips_legitimate_address_p
2551 to check whether a constant really is an address. */
2552
2553 #define CONSTANT_ADDRESS_P(X) \
2554 (CONSTANT_P (X) && memory_address_p (SImode, X))
2555
2556 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2557
2558 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2559 'the start of the function that this code is output in'. */
2560
2561 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2562 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2563 asm_fprintf ((FILE), "%U%s", \
2564 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2565 else \
2566 asm_fprintf ((FILE), "%U%s", (NAME))
2567 \f
2568 /* Flag to mark a function decl symbol that requires a long call. */
2569 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2570 #define SYMBOL_REF_LONG_CALL_P(X) \
2571 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2572
2573 /* This flag marks functions that cannot be lazily bound. */
2574 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2575 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2576 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2577
2578 /* True if we're generating a form of MIPS16 code in which jump tables
2579 are stored in the text section and encoded as 16-bit PC-relative
2580 offsets. This is only possible when general text loads are allowed,
2581 since the table access itself will be an "lh" instruction. */
2582 /* ??? 16-bit offsets can overflow in large functions. */
2583 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2584
2585 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2586
2587 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2588
2589 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2590
2591 /* Define this as 1 if `char' should by default be signed; else as 0. */
2592 #ifndef DEFAULT_SIGNED_CHAR
2593 #define DEFAULT_SIGNED_CHAR 1
2594 #endif
2595
2596 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2597 we generally don't want to use them for copying arbitrary data.
2598 A single N-word move is usually the same cost as N single-word moves. */
2599 #define MOVE_MAX UNITS_PER_WORD
2600 #define MAX_MOVE_MAX 8
2601
2602 /* Define this macro as a C expression which is nonzero if
2603 accessing less than a word of memory (i.e. a `char' or a
2604 `short') is no faster than accessing a word of memory, i.e., if
2605 such access require more than one instruction or if there is no
2606 difference in cost between byte and (aligned) word loads.
2607
2608 On RISC machines, it tends to generate better code to define
2609 this as 1, since it avoids making a QI or HI mode register.
2610
2611 But, generating word accesses for -mips16 is generally bad as shifts
2612 (often extended) would be needed for byte accesses. */
2613 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2614
2615 /* Define this to be nonzero if shift instructions ignore all but the low-order
2616 few bits. */
2617 #define SHIFT_COUNT_TRUNCATED 1
2618
2619 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2620 is done just by pretending it is already truncated. */
2621 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2622 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2623
2624
2625 /* Specify the machine mode that pointers have.
2626 After generation of rtl, the compiler makes no further distinction
2627 between pointers and any other objects of this machine mode. */
2628
2629 #ifndef Pmode
2630 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2631 #endif
2632
2633 /* Give call MEMs SImode since it is the "most permissive" mode
2634 for both 32-bit and 64-bit targets. */
2635
2636 #define FUNCTION_MODE SImode
2637
2638 \f
2639 /* A C expression for the cost of moving data from a register in
2640 class FROM to one in class TO. The classes are expressed using
2641 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2642 the default; other values are interpreted relative to that.
2643
2644 It is not required that the cost always equal 2 when FROM is the
2645 same as TO; on some machines it is expensive to move between
2646 registers if they are not general registers.
2647
2648 If reload sees an insn consisting of a single `set' between two
2649 hard registers, and if `REGISTER_MOVE_COST' applied to their
2650 classes returns a value of 2, reload does not check to ensure
2651 that the constraints of the insn are met. Setting a cost of
2652 other than 2 will allow reload to verify that the constraints are
2653 met. You should do this if the `movM' pattern's constraints do
2654 not allow such copying. */
2655
2656 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2657 mips_register_move_cost (MODE, FROM, TO)
2658
2659 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2660 (mips_cost->memory_latency \
2661 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2662
2663 /* Define if copies to/from condition code registers should be avoided.
2664
2665 This is needed for the MIPS because reload_outcc is not complete;
2666 it needs to handle cases where the source is a general or another
2667 condition code register. */
2668 #define AVOID_CCMODE_COPIES
2669
2670 /* A C expression for the cost of a branch instruction. A value of
2671 1 is the default; other values are interpreted relative to that. */
2672
2673 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2674 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2675
2676 /* If defined, modifies the length assigned to instruction INSN as a
2677 function of the context in which it is used. LENGTH is an lvalue
2678 that contains the initially computed length of the insn and should
2679 be updated with the correct length of the insn. */
2680 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2681 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2682
2683 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2684 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2685 its operands. */
2686 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2687 "%*" OPCODE "%?\t" OPERANDS "%/"
2688
2689 /* Return an asm string that forces INSN to be treated as an absolute
2690 J or JAL instruction instead of an assembler macro. */
2691 #define MIPS_ABSOLUTE_JUMP(INSN) \
2692 (TARGET_ABICALLS_PIC2 \
2693 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2694 : INSN)
2695
2696 /* Return the asm template for a call. INSN is the instruction's mnemonic
2697 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2698 number of the target. SIZE_OPNO is the operand number of the argument size
2699 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2700 -1 and the call is indirect, use the function symbol from the call
2701 attributes to attach a R_MIPS_JALR relocation to the call.
2702
2703 When generating GOT code without explicit relocation operators,
2704 all calls should use assembly macros. Otherwise, all indirect
2705 calls should use "jr" or "jalr"; we will arrange to restore $gp
2706 afterwards if necessary. Finally, we can only generate direct
2707 calls for -mabicalls by temporarily switching to non-PIC mode. */
2708 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2709 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2710 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2711 : (REG_P (OPERANDS[TARGET_OPNO]) \
2712 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2713 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2714 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2715 : REG_P (OPERANDS[TARGET_OPNO]) \
2716 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2717 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2718 \f
2719 /* Control the assembler format that we output. */
2720
2721 /* Output to assembler file text saying following lines
2722 may contain character constants, extra white space, comments, etc. */
2723
2724 #ifndef ASM_APP_ON
2725 #define ASM_APP_ON " #APP\n"
2726 #endif
2727
2728 /* Output to assembler file text saying following lines
2729 no longer contain unusual constructs. */
2730
2731 #ifndef ASM_APP_OFF
2732 #define ASM_APP_OFF " #NO_APP\n"
2733 #endif
2734
2735 #define REGISTER_NAMES \
2736 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2737 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2738 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2739 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2740 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2741 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2742 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2743 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2744 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2745 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2746 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2747 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2748 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2749 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2750 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2751 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2752 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2753 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2754 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2755 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2756 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2757 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2758 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2759 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2760
2761 /* List the "software" names for each register. Also list the numerical
2762 names for $fp and $sp. */
2763
2764 #define ADDITIONAL_REGISTER_NAMES \
2765 { \
2766 { "$29", 29 + GP_REG_FIRST }, \
2767 { "$30", 30 + GP_REG_FIRST }, \
2768 { "at", 1 + GP_REG_FIRST }, \
2769 { "v0", 2 + GP_REG_FIRST }, \
2770 { "v1", 3 + GP_REG_FIRST }, \
2771 { "a0", 4 + GP_REG_FIRST }, \
2772 { "a1", 5 + GP_REG_FIRST }, \
2773 { "a2", 6 + GP_REG_FIRST }, \
2774 { "a3", 7 + GP_REG_FIRST }, \
2775 { "t0", 8 + GP_REG_FIRST }, \
2776 { "t1", 9 + GP_REG_FIRST }, \
2777 { "t2", 10 + GP_REG_FIRST }, \
2778 { "t3", 11 + GP_REG_FIRST }, \
2779 { "t4", 12 + GP_REG_FIRST }, \
2780 { "t5", 13 + GP_REG_FIRST }, \
2781 { "t6", 14 + GP_REG_FIRST }, \
2782 { "t7", 15 + GP_REG_FIRST }, \
2783 { "s0", 16 + GP_REG_FIRST }, \
2784 { "s1", 17 + GP_REG_FIRST }, \
2785 { "s2", 18 + GP_REG_FIRST }, \
2786 { "s3", 19 + GP_REG_FIRST }, \
2787 { "s4", 20 + GP_REG_FIRST }, \
2788 { "s5", 21 + GP_REG_FIRST }, \
2789 { "s6", 22 + GP_REG_FIRST }, \
2790 { "s7", 23 + GP_REG_FIRST }, \
2791 { "t8", 24 + GP_REG_FIRST }, \
2792 { "t9", 25 + GP_REG_FIRST }, \
2793 { "k0", 26 + GP_REG_FIRST }, \
2794 { "k1", 27 + GP_REG_FIRST }, \
2795 { "gp", 28 + GP_REG_FIRST }, \
2796 { "sp", 29 + GP_REG_FIRST }, \
2797 { "fp", 30 + GP_REG_FIRST }, \
2798 { "ra", 31 + GP_REG_FIRST }, \
2799 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2800 }
2801
2802 /* This is meant to be redefined in the host dependent files. It is a
2803 set of alternative names and regnums for mips coprocessors. */
2804
2805 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2806
2807 #define PRINT_OPERAND mips_print_operand
2808 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2809 #define PRINT_OPERAND_ADDRESS mips_print_operand_address
2810
2811 #define DBR_OUTPUT_SEQEND(STREAM) \
2812 do \
2813 { \
2814 /* Undo the effect of '%*'. */ \
2815 mips_pop_asm_switch (&mips_nomacro); \
2816 mips_pop_asm_switch (&mips_noreorder); \
2817 /* Emit a blank line after the delay slot for emphasis. */ \
2818 fputs ("\n", STREAM); \
2819 } \
2820 while (0)
2821
2822 /* How to tell the debugger about changes of source files. */
2823 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
2824
2825 /* mips-tfile does not understand .stabd directives. */
2826 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2827 dbxout_begin_stabn_sline (LINE); \
2828 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2829 } while (0)
2830
2831 /* Use .loc directives for SDB line numbers. */
2832 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2833 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2834
2835 /* The MIPS implementation uses some labels for its own purpose. The
2836 following lists what labels are created, and are all formed by the
2837 pattern $L[a-z].*. The machine independent portion of GCC creates
2838 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2839
2840 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2841 $Lb[0-9]+ Begin blocks for MIPS debug support
2842 $Lc[0-9]+ Label for use in s<xx> operation.
2843 $Le[0-9]+ End blocks for MIPS debug support */
2844
2845 #undef ASM_DECLARE_OBJECT_NAME
2846 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2847 mips_declare_object (STREAM, NAME, "", ":\n")
2848
2849 /* Globalizing directive for a label. */
2850 #define GLOBAL_ASM_OP "\t.globl\t"
2851
2852 /* This says how to define a global common symbol. */
2853
2854 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2855
2856 /* This says how to define a local common symbol (i.e., not visible to
2857 linker). */
2858
2859 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2860 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2861 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2862 #endif
2863
2864 /* This says how to output an external. It would be possible not to
2865 output anything and let undefined symbol become external. However
2866 the assembler uses length information on externals to allocate in
2867 data/sdata bss/sbss, thereby saving exec time. */
2868
2869 #undef ASM_OUTPUT_EXTERNAL
2870 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2871 mips_output_external(STREAM,DECL,NAME)
2872
2873 /* This is how to declare a function name. The actual work of
2874 emitting the label is moved to function_prologue, so that we can
2875 get the line number correctly emitted before the .ent directive,
2876 and after any .file directives. Define as empty so that the function
2877 is not declared before the .ent directive elsewhere. */
2878
2879 #undef ASM_DECLARE_FUNCTION_NAME
2880 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2881
2882 /* This is how to store into the string LABEL
2883 the symbol_ref name of an internal numbered label where
2884 PREFIX is the class of label and NUM is the number within the class.
2885 This is suitable for output with `assemble_name'. */
2886
2887 #undef ASM_GENERATE_INTERNAL_LABEL
2888 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2889 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2890
2891 /* Print debug labels as "foo = ." rather than "foo:" because they should
2892 represent a byte pointer rather than an ISA-encoded address. This is
2893 particularly important for code like:
2894
2895 $LFBxxx = .
2896 .cfi_startproc
2897 ...
2898 .section .gcc_except_table,...
2899 ...
2900 .uleb128 foo-$LFBxxx
2901
2902 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2903 likewise a byte pointer rather than an ISA-encoded address.
2904
2905 At the time of writing, this hook is not used for the function end
2906 label:
2907
2908 $LFExxx:
2909 .end foo
2910
2911 But this doesn't matter, because GAS doesn't treat a pre-.end label
2912 as a MIPS16 one anyway. */
2913
2914 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2915 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2916
2917 /* This is how to output an element of a case-vector that is absolute. */
2918
2919 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2920 fprintf (STREAM, "\t%s\t%sL%d\n", \
2921 ptr_mode == DImode ? ".dword" : ".word", \
2922 LOCAL_LABEL_PREFIX, \
2923 VALUE)
2924
2925 /* This is how to output an element of a case-vector. We can make the
2926 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2927 is supported. */
2928
2929 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2930 do { \
2931 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2932 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2933 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2934 else if (TARGET_GPWORD) \
2935 fprintf (STREAM, "\t%s\t%sL%d\n", \
2936 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2937 LOCAL_LABEL_PREFIX, VALUE); \
2938 else if (TARGET_RTP_PIC) \
2939 { \
2940 /* Make the entry relative to the start of the function. */ \
2941 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2942 fprintf (STREAM, "\t%s\t%sL%d-", \
2943 Pmode == DImode ? ".dword" : ".word", \
2944 LOCAL_LABEL_PREFIX, VALUE); \
2945 assemble_name (STREAM, XSTR (fnsym, 0)); \
2946 fprintf (STREAM, "\n"); \
2947 } \
2948 else \
2949 fprintf (STREAM, "\t%s\t%sL%d\n", \
2950 ptr_mode == DImode ? ".dword" : ".word", \
2951 LOCAL_LABEL_PREFIX, VALUE); \
2952 } while (0)
2953
2954 /* This is how to output an assembler line
2955 that says to advance the location counter
2956 to a multiple of 2**LOG bytes. */
2957
2958 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2959 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2960
2961 /* This is how to output an assembler line to advance the location
2962 counter by SIZE bytes. */
2963
2964 #undef ASM_OUTPUT_SKIP
2965 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2966 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2967
2968 /* This is how to output a string. */
2969 #undef ASM_OUTPUT_ASCII
2970 #define ASM_OUTPUT_ASCII mips_output_ascii
2971
2972 /* Output #ident as a in the read-only data section. */
2973 #undef ASM_OUTPUT_IDENT
2974 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2975 { \
2976 const char *p = STRING; \
2977 int size = strlen (p) + 1; \
2978 switch_to_section (readonly_data_section); \
2979 assemble_string (p, size); \
2980 }
2981 \f
2982 /* Default to -G 8 */
2983 #ifndef MIPS_DEFAULT_GVALUE
2984 #define MIPS_DEFAULT_GVALUE 8
2985 #endif
2986
2987 /* Define the strings to put out for each section in the object file. */
2988 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2989 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2990
2991 #undef READONLY_DATA_SECTION_ASM_OP
2992 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2993 \f
2994 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2995 do \
2996 { \
2997 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2998 TARGET_64BIT ? "daddiu" : "addiu", \
2999 reg_names[STACK_POINTER_REGNUM], \
3000 reg_names[STACK_POINTER_REGNUM], \
3001 TARGET_64BIT ? "sd" : "sw", \
3002 reg_names[REGNO], \
3003 reg_names[STACK_POINTER_REGNUM]); \
3004 } \
3005 while (0)
3006
3007 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3008 do \
3009 { \
3010 mips_push_asm_switch (&mips_noreorder); \
3011 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3012 TARGET_64BIT ? "ld" : "lw", \
3013 reg_names[REGNO], \
3014 reg_names[STACK_POINTER_REGNUM], \
3015 TARGET_64BIT ? "daddu" : "addu", \
3016 reg_names[STACK_POINTER_REGNUM], \
3017 reg_names[STACK_POINTER_REGNUM]); \
3018 mips_pop_asm_switch (&mips_noreorder); \
3019 } \
3020 while (0)
3021
3022 /* How to start an assembler comment.
3023 The leading space is important (the mips native assembler requires it). */
3024 #ifndef ASM_COMMENT_START
3025 #define ASM_COMMENT_START " #"
3026 #endif
3027 \f
3028 /* Default definitions for size_t and ptrdiff_t. We must override the
3029 definitions from ../svr4.h on mips-*-linux-gnu. */
3030
3031 #undef SIZE_TYPE
3032 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3033
3034 #undef PTRDIFF_TYPE
3035 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3036
3037 /* The maximum number of bytes that can be copied by one iteration of
3038 a movmemsi loop; see mips_block_move_loop. */
3039 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
3040 (UNITS_PER_WORD * 4)
3041
3042 /* The maximum number of bytes that can be copied by a straight-line
3043 implementation of movmemsi; see mips_block_move_straight. We want
3044 to make sure that any loop-based implementation will iterate at
3045 least twice. */
3046 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
3047 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
3048
3049 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
3050 values were determined experimentally by benchmarking with CSiBE.
3051 In theory, the call overhead is higher for TARGET_ABICALLS (especially
3052 for o32 where we have to restore $gp afterwards as well as make an
3053 indirect call), but in practice, bumping this up higher for
3054 TARGET_ABICALLS doesn't make much difference to code size. */
3055
3056 #define MIPS_CALL_RATIO 8
3057
3058 /* Any loop-based implementation of movmemsi will have at least
3059 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
3060 moves, so allow individual copies of fewer elements.
3061
3062 When movmemsi is not available, use a value approximating
3063 the length of a memcpy call sequence, so that move_by_pieces
3064 will generate inline code if it is shorter than a function call.
3065 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3066 we'll have to generate a load/store pair for each, halve the
3067 value of MIPS_CALL_RATIO to take that into account. */
3068
3069 #define MOVE_RATIO(speed) \
3070 (HAVE_movmemsi \
3071 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3072 : MIPS_CALL_RATIO / 2)
3073
3074 /* movmemsi is meant to generate code that is at least as good as
3075 move_by_pieces. However, movmemsi effectively uses a by-pieces
3076 implementation both for moves smaller than a word and for word-aligned
3077 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
3078 allow the tree-level optimisers to do such moves by pieces, as it
3079 often exposes other optimization opportunities. We might as well
3080 continue to use movmemsi at the rtl level though, as it produces
3081 better code when scheduling is disabled (such as at -O). */
3082
3083 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
3084 (HAVE_movmemsi \
3085 ? (!currently_expanding_to_rtl \
3086 && ((ALIGN) < BITS_PER_WORD \
3087 ? (SIZE) < UNITS_PER_WORD \
3088 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
3089 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
3090 < (unsigned int) MOVE_RATIO (false)))
3091
3092 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
3093 of the length of a memset call, but use the default otherwise. */
3094
3095 #define CLEAR_RATIO(speed)\
3096 ((speed) ? 15 : MIPS_CALL_RATIO)
3097
3098 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3099 optimizing for size adjust the ratio to account for the overhead of
3100 loading the constant and replicating it across the word. */
3101
3102 #define SET_RATIO(speed) \
3103 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3104
3105 /* STORE_BY_PIECES_P can be used when copying a constant string, but
3106 in that case each word takes 3 insns (lui, ori, sw), or more in
3107 64-bit mode, instead of 2 (lw, sw). For now we always fail this
3108 and let the move_by_pieces code copy the string from read-only
3109 memory. In the future, this could be tuned further for multi-issue
3110 CPUs that can issue stores down one pipe and arithmetic instructions
3111 down another; in that case, the lui/ori/sw combination would be a
3112 win for long enough strings. */
3113
3114 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
3115 \f
3116 #ifndef __mips16
3117 /* Since the bits of the _init and _fini function is spread across
3118 many object files, each potentially with its own GP, we must assume
3119 we need to load our GP. We don't preserve $gp or $ra, since each
3120 init/fini chunk is supposed to initialize $gp, and crti/crtn
3121 already take care of preserving $ra and, when appropriate, $gp. */
3122 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3123 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3124 asm (SECTION_OP "\n\
3125 .set noreorder\n\
3126 bal 1f\n\
3127 nop\n\
3128 1: .cpload $31\n\
3129 .set reorder\n\
3130 jal " USER_LABEL_PREFIX #FUNC "\n\
3131 " TEXT_SECTION_ASM_OP);
3132 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3133 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3134 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3135 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3136 asm (SECTION_OP "\n\
3137 .set noreorder\n\
3138 bal 1f\n\
3139 nop\n\
3140 1: .set reorder\n\
3141 .cpsetup $31, $2, 1b\n\
3142 jal " USER_LABEL_PREFIX #FUNC "\n\
3143 " TEXT_SECTION_ASM_OP);
3144 #endif
3145 #endif
3146
3147 #ifndef HAVE_AS_TLS
3148 #define HAVE_AS_TLS 0
3149 #endif
3150
3151 #ifndef USED_FOR_TARGET
3152 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3153 struct mips_asm_switch {
3154 /* The FOO in the description above. */
3155 const char *name;
3156
3157 /* The current block nesting level, or 0 if we aren't in a block. */
3158 int nesting_level;
3159 };
3160
3161 extern const enum reg_class mips_regno_to_class[];
3162 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3163 extern bool mips_print_operand_punct[256];
3164 extern const char *current_function_file; /* filename current function is in */
3165 extern int num_source_filenames; /* current .file # */
3166 extern struct mips_asm_switch mips_noreorder;
3167 extern struct mips_asm_switch mips_nomacro;
3168 extern struct mips_asm_switch mips_noat;
3169 extern int mips_dbx_regno[];
3170 extern int mips_dwarf_regno[];
3171 extern bool mips_split_p[];
3172 extern bool mips_split_hi_p[];
3173 extern enum processor_type mips_arch; /* which cpu to codegen for */
3174 extern enum processor_type mips_tune; /* which cpu to schedule for */
3175 extern int mips_isa; /* architectural level */
3176 extern int mips_abi; /* which ABI to use */
3177 extern const struct mips_cpu_info *mips_arch_info;
3178 extern const struct mips_cpu_info *mips_tune_info;
3179 extern const struct mips_rtx_cost_data *mips_cost;
3180 extern bool mips_base_mips16;
3181 extern enum mips_code_readable_setting mips_code_readable;
3182 #endif
3183
3184 /* Enable querying of DFA units. */
3185 #define CPU_UNITS_QUERY 1
3186
3187 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3188 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3189
3190 /* This is necessary to avoid a warning about comparing different enum
3191 types. */
3192 #define mips_tune_attr ((enum attr_cpu) mips_tune)
3193
3194 /* As on most targets, we want the .eh_frame section to be read-only where
3195 possible. And as on most targets, this means two things:
3196
3197 (a) Non-locally-binding pointers must have an indirect encoding,
3198 so that the addresses in the .eh_frame section itself become
3199 locally-binding.
3200
3201 (b) A shared library's .eh_frame section must encode locally-binding
3202 pointers in a relative (relocation-free) form.
3203
3204 However, MIPS has traditionally not allowed directives like:
3205
3206 .long x-.
3207
3208 in cases where "x" is in a different section, or is not defined in the
3209 same assembly file. We are therefore unable to emit the PC-relative
3210 form required by (b) at assembly time.
3211
3212 Fortunately, the linker is able to convert absolute addresses into
3213 PC-relative addresses on our behalf. Unfortunately, only certain
3214 versions of the linker know how to do this for indirect pointers,
3215 and for personality data. We must fall back on using writable
3216 .eh_frame sections for shared libraries if the linker does not
3217 support this feature. */
3218 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3219 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)