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Add support for the R6 LSA and DLSA instructions
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* ISA has LSA available. */
185 #define ISA_HAS_LSA (mips_isa_rev >= 6)
186
187 /* ISA has DLSA available. */
188 #define ISA_HAS_DLSA (TARGET_64BIT && mips_isa_rev >= 6)
189
190 /* The ISA compression flags that are currently in effect. */
191 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
192
193 /* Generate mips16 code */
194 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
195 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
196 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
197 /* Generate mips16e register save/restore sequences. */
198 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
199
200 /* True if we're generating a form of MIPS16 code in which general
201 text loads are allowed. */
202 #define TARGET_MIPS16_TEXT_LOADS \
203 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
204
205 /* True if we're generating a form of MIPS16 code in which PC-relative
206 loads are allowed. */
207 #define TARGET_MIPS16_PCREL_LOADS \
208 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
209
210 /* Generic ISA defines. */
211 #define ISA_MIPS1 (mips_isa == 1)
212 #define ISA_MIPS2 (mips_isa == 2)
213 #define ISA_MIPS3 (mips_isa == 3)
214 #define ISA_MIPS4 (mips_isa == 4)
215 #define ISA_MIPS32 (mips_isa == 32)
216 #define ISA_MIPS32R2 (mips_isa == 33)
217 #define ISA_MIPS32R3 (mips_isa == 34)
218 #define ISA_MIPS32R5 (mips_isa == 36)
219 #define ISA_MIPS32R6 (mips_isa == 37)
220 #define ISA_MIPS64 (mips_isa == 64)
221 #define ISA_MIPS64R2 (mips_isa == 65)
222 #define ISA_MIPS64R3 (mips_isa == 66)
223 #define ISA_MIPS64R5 (mips_isa == 68)
224 #define ISA_MIPS64R6 (mips_isa == 69)
225
226 /* Architecture target defines. */
227 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
228 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
229 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
230 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
231 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
232 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
233 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
234 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
235 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
236 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
237 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
238 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
239 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
240 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
241 || mips_arch == PROCESSOR_OCTEON2 \
242 || mips_arch == PROCESSOR_OCTEON3)
243 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
244 || mips_arch == PROCESSOR_OCTEON3)
245 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
246 || mips_arch == PROCESSOR_SB1A)
247 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
248 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
249
250 /* Scheduling target defines. */
251 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
252 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
253 || mips_tune == PROCESSOR_24KF2_1 \
254 || mips_tune == PROCESSOR_24KF1_1)
255 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
256 || mips_tune == PROCESSOR_74KF2_1 \
257 || mips_tune == PROCESSOR_74KF1_1 \
258 || mips_tune == PROCESSOR_74KF3_2)
259 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
260 || mips_tune == PROCESSOR_LOONGSON_2F)
261 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
262 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
263 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
264 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
265 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
266 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
267 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
268 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
269 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
270 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
271 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
272 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
273 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
274 || mips_tune == PROCESSOR_OCTEON2 \
275 || mips_tune == PROCESSOR_OCTEON3)
276 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
277 || mips_tune == PROCESSOR_SB1A)
278 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
279
280 /* Whether vector modes and intrinsics for ST Microelectronics
281 Loongson-2E/2F processors should be enabled. In o32 pairs of
282 floating-point registers provide 64-bit values. */
283 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
284 && (TARGET_LOONGSON_2EF \
285 || TARGET_LOONGSON_3A))
286
287 /* True if the pre-reload scheduler should try to create chains of
288 multiply-add or multiply-subtract instructions. For example,
289 suppose we have:
290
291 t1 = a * b
292 t2 = t1 + c * d
293 t3 = e * f
294 t4 = t3 - g * h
295
296 t1 will have a higher priority than t2 and t3 will have a higher
297 priority than t4. However, before reload, there is no dependence
298 between t1 and t3, and they can often have similar priorities.
299 The scheduler will then tend to prefer:
300
301 t1 = a * b
302 t3 = e * f
303 t2 = t1 + c * d
304 t4 = t3 - g * h
305
306 which stops us from making full use of macc/madd-style instructions.
307 This sort of situation occurs frequently in Fourier transforms and
308 in unrolled loops.
309
310 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
311 queue so that chained multiply-add and multiply-subtract instructions
312 appear ahead of any other instruction that is likely to clobber lo.
313 In the example above, if t2 and t3 become ready at the same time,
314 the code ensures that t2 is scheduled first.
315
316 Multiply-accumulate instructions are a bigger win for some targets
317 than others, so this macro is defined on an opt-in basis. */
318 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
319 || TUNE_MIPS4120 \
320 || TUNE_MIPS4130 \
321 || TUNE_24K \
322 || TUNE_P5600)
323
324 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
325 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
326
327 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
328 directly accessible, while the command-line options select
329 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
330 in use. */
331 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
332 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
333
334 /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents
335 -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */
336 #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX)
337
338 /* TARGET_O32_FP64A_ABI represents all the conditions that form the
339 o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */
340 #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \
341 && !TARGET_ODD_SPREG)
342
343 /* False if SC acts as a memory barrier with respect to itself,
344 otherwise a SYNC will be emitted after SC for atomic operations
345 that require ordering between the SC and following loads and
346 stores. It does not tell anything about ordering of loads and
347 stores prior to and following the SC, only about the SC itself and
348 those loads and stores follow it. */
349 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
350
351 /* Define preprocessor macros for the -march and -mtune options.
352 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
353 processor. If INFO's canonical name is "foo", define PREFIX to
354 be "foo", and define an additional macro PREFIX_FOO. */
355 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
356 do \
357 { \
358 char *macro, *p; \
359 \
360 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
361 for (p = macro; *p != 0; p++) \
362 if (*p == '+') \
363 *p = 'P'; \
364 else \
365 *p = TOUPPER (*p); \
366 \
367 builtin_define (macro); \
368 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
369 free (macro); \
370 } \
371 while (0)
372
373 /* Target CPU builtins. */
374 #define TARGET_CPU_CPP_BUILTINS() \
375 do \
376 { \
377 builtin_assert ("machine=mips"); \
378 builtin_assert ("cpu=mips"); \
379 builtin_define ("__mips__"); \
380 builtin_define ("_mips"); \
381 \
382 /* We do this here because __mips is defined below and so we \
383 can't use builtin_define_std. We don't ever want to define \
384 "mips" for VxWorks because some of the VxWorks headers \
385 construct include filenames from a root directory macro, \
386 an architecture macro and a filename, where the architecture \
387 macro expands to 'mips'. If we define 'mips' to 1, the \
388 architecture macro expands to 1 as well. */ \
389 if (!flag_iso && !TARGET_VXWORKS) \
390 builtin_define ("mips"); \
391 \
392 if (TARGET_64BIT) \
393 builtin_define ("__mips64"); \
394 \
395 /* Treat _R3000 and _R4000 like register-size \
396 defines, which is how they've historically \
397 been used. */ \
398 if (TARGET_64BIT) \
399 { \
400 builtin_define_std ("R4000"); \
401 builtin_define ("_R4000"); \
402 } \
403 else \
404 { \
405 builtin_define_std ("R3000"); \
406 builtin_define ("_R3000"); \
407 } \
408 \
409 if (TARGET_FLOAT64) \
410 builtin_define ("__mips_fpr=64"); \
411 else if (TARGET_FLOATXX) \
412 builtin_define ("__mips_fpr=0"); \
413 else \
414 builtin_define ("__mips_fpr=32"); \
415 \
416 if (mips_base_compression_flags & MASK_MIPS16) \
417 builtin_define ("__mips16"); \
418 \
419 if (TARGET_MIPS3D) \
420 builtin_define ("__mips3d"); \
421 \
422 if (TARGET_SMARTMIPS) \
423 builtin_define ("__mips_smartmips"); \
424 \
425 if (mips_base_compression_flags & MASK_MICROMIPS) \
426 builtin_define ("__mips_micromips"); \
427 \
428 if (TARGET_MCU) \
429 builtin_define ("__mips_mcu"); \
430 \
431 if (TARGET_EVA) \
432 builtin_define ("__mips_eva"); \
433 \
434 if (TARGET_DSP) \
435 { \
436 builtin_define ("__mips_dsp"); \
437 if (TARGET_DSPR2) \
438 { \
439 builtin_define ("__mips_dspr2"); \
440 builtin_define ("__mips_dsp_rev=2"); \
441 } \
442 else \
443 builtin_define ("__mips_dsp_rev=1"); \
444 } \
445 \
446 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
447 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
448 \
449 if (ISA_MIPS1) \
450 { \
451 builtin_define ("__mips=1"); \
452 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
453 } \
454 else if (ISA_MIPS2) \
455 { \
456 builtin_define ("__mips=2"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
458 } \
459 else if (ISA_MIPS3) \
460 { \
461 builtin_define ("__mips=3"); \
462 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
463 } \
464 else if (ISA_MIPS4) \
465 { \
466 builtin_define ("__mips=4"); \
467 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
468 } \
469 else if (mips_isa >= 32 && mips_isa < 64) \
470 { \
471 builtin_define ("__mips=32"); \
472 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
473 } \
474 else if (mips_isa >= 64) \
475 { \
476 builtin_define ("__mips=64"); \
477 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
478 } \
479 if (mips_isa_rev > 0) \
480 builtin_define_with_int_value ("__mips_isa_rev", \
481 mips_isa_rev); \
482 \
483 switch (mips_abi) \
484 { \
485 case ABI_32: \
486 builtin_define ("_ABIO32=1"); \
487 builtin_define ("_MIPS_SIM=_ABIO32"); \
488 break; \
489 \
490 case ABI_N32: \
491 builtin_define ("_ABIN32=2"); \
492 builtin_define ("_MIPS_SIM=_ABIN32"); \
493 break; \
494 \
495 case ABI_64: \
496 builtin_define ("_ABI64=3"); \
497 builtin_define ("_MIPS_SIM=_ABI64"); \
498 break; \
499 \
500 case ABI_O64: \
501 builtin_define ("_ABIO64=4"); \
502 builtin_define ("_MIPS_SIM=_ABIO64"); \
503 break; \
504 } \
505 \
506 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
507 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
508 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
509 builtin_define_with_int_value ("_MIPS_FPSET", \
510 32 / MAX_FPRS_PER_FMT); \
511 builtin_define_with_int_value ("_MIPS_SPFPSET", \
512 TARGET_ODD_SPREG ? 32 : 16); \
513 \
514 /* These defines reflect the ABI in use, not whether the \
515 FPU is directly accessible. */ \
516 if (TARGET_NO_FLOAT) \
517 builtin_define ("__mips_no_float"); \
518 else if (TARGET_HARD_FLOAT_ABI) \
519 builtin_define ("__mips_hard_float"); \
520 else \
521 builtin_define ("__mips_soft_float"); \
522 \
523 if (TARGET_SINGLE_FLOAT) \
524 builtin_define ("__mips_single_float"); \
525 \
526 if (TARGET_PAIRED_SINGLE_FLOAT) \
527 builtin_define ("__mips_paired_single_float"); \
528 \
529 if (mips_abs == MIPS_IEEE_754_2008) \
530 builtin_define ("__mips_abs2008"); \
531 \
532 if (mips_nan == MIPS_IEEE_754_2008) \
533 builtin_define ("__mips_nan2008"); \
534 \
535 if (TARGET_BIG_ENDIAN) \
536 { \
537 builtin_define_std ("MIPSEB"); \
538 builtin_define ("_MIPSEB"); \
539 } \
540 else \
541 { \
542 builtin_define_std ("MIPSEL"); \
543 builtin_define ("_MIPSEL"); \
544 } \
545 \
546 /* Whether calls should go through $25. The separate __PIC__ \
547 macro indicates whether abicalls code might use a GOT. */ \
548 if (TARGET_ABICALLS) \
549 builtin_define ("__mips_abicalls"); \
550 \
551 /* Whether Loongson vector modes are enabled. */ \
552 if (TARGET_LOONGSON_VECTORS) \
553 builtin_define ("__mips_loongson_vector_rev"); \
554 \
555 /* Historical Octeon macro. */ \
556 if (TARGET_OCTEON) \
557 builtin_define ("__OCTEON__"); \
558 \
559 if (TARGET_SYNCI) \
560 builtin_define ("__mips_synci"); \
561 \
562 /* Macros dependent on the C dialect. */ \
563 if (preprocessing_asm_p ()) \
564 { \
565 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
566 builtin_define ("_LANGUAGE_ASSEMBLY"); \
567 } \
568 else if (c_dialect_cxx ()) \
569 { \
570 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
571 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
572 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
573 } \
574 else \
575 { \
576 builtin_define_std ("LANGUAGE_C"); \
577 builtin_define ("_LANGUAGE_C"); \
578 } \
579 if (c_dialect_objc ()) \
580 { \
581 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
582 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
583 /* Bizarre, but retained for backwards compatibility. */ \
584 builtin_define_std ("LANGUAGE_C"); \
585 builtin_define ("_LANGUAGE_C"); \
586 } \
587 \
588 if (mips_abi == ABI_EABI) \
589 builtin_define ("__mips_eabi"); \
590 \
591 if (TARGET_CACHE_BUILTIN) \
592 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
593 } \
594 while (0)
595
596 /* Default target_flags if no switches are specified */
597
598 #ifndef TARGET_DEFAULT
599 #define TARGET_DEFAULT 0
600 #endif
601
602 #ifndef TARGET_CPU_DEFAULT
603 #define TARGET_CPU_DEFAULT 0
604 #endif
605
606 #ifndef TARGET_ENDIAN_DEFAULT
607 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
608 #endif
609
610 #ifdef IN_LIBGCC2
611 #undef TARGET_64BIT
612 /* Make this compile time constant for libgcc2 */
613 #ifdef __mips64
614 #define TARGET_64BIT 1
615 #else
616 #define TARGET_64BIT 0
617 #endif
618 #endif /* IN_LIBGCC2 */
619
620 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
621 when compiled with hardware floating point. This is because MIPS16
622 code cannot save and restore the floating-point registers, which is
623 important if in a mixed MIPS16/non-MIPS16 environment. */
624
625 #ifdef IN_LIBGCC2
626 #if __mips_hard_float
627 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
628 #endif
629 #endif /* IN_LIBGCC2 */
630
631 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
632
633 #ifndef MULTILIB_ENDIAN_DEFAULT
634 #if TARGET_ENDIAN_DEFAULT == 0
635 #define MULTILIB_ENDIAN_DEFAULT "EL"
636 #else
637 #define MULTILIB_ENDIAN_DEFAULT "EB"
638 #endif
639 #endif
640
641 #ifndef MULTILIB_ISA_DEFAULT
642 #if MIPS_ISA_DEFAULT == 1
643 #define MULTILIB_ISA_DEFAULT "mips1"
644 #elif MIPS_ISA_DEFAULT == 2
645 #define MULTILIB_ISA_DEFAULT "mips2"
646 #elif MIPS_ISA_DEFAULT == 3
647 #define MULTILIB_ISA_DEFAULT "mips3"
648 #elif MIPS_ISA_DEFAULT == 4
649 #define MULTILIB_ISA_DEFAULT "mips4"
650 #elif MIPS_ISA_DEFAULT == 32
651 #define MULTILIB_ISA_DEFAULT "mips32"
652 #elif MIPS_ISA_DEFAULT == 33
653 #define MULTILIB_ISA_DEFAULT "mips32r2"
654 #elif MIPS_ISA_DEFAULT == 37
655 #define MULTILIB_ISA_DEFAULT "mips32r6"
656 #elif MIPS_ISA_DEFAULT == 64
657 #define MULTILIB_ISA_DEFAULT "mips64"
658 #elif MIPS_ISA_DEFAULT == 65
659 #define MULTILIB_ISA_DEFAULT "mips64r2"
660 #elif MIPS_ISA_DEFAULT == 69
661 #define MULTILIB_ISA_DEFAULT "mips64r6"
662 #else
663 #define MULTILIB_ISA_DEFAULT "mips1"
664 #endif
665 #endif
666
667 #ifndef MIPS_ABI_DEFAULT
668 #define MIPS_ABI_DEFAULT ABI_32
669 #endif
670
671 /* Use the most portable ABI flag for the ASM specs. */
672
673 #if MIPS_ABI_DEFAULT == ABI_32
674 #define MULTILIB_ABI_DEFAULT "mabi=32"
675 #elif MIPS_ABI_DEFAULT == ABI_O64
676 #define MULTILIB_ABI_DEFAULT "mabi=o64"
677 #elif MIPS_ABI_DEFAULT == ABI_N32
678 #define MULTILIB_ABI_DEFAULT "mabi=n32"
679 #elif MIPS_ABI_DEFAULT == ABI_64
680 #define MULTILIB_ABI_DEFAULT "mabi=64"
681 #elif MIPS_ABI_DEFAULT == ABI_EABI
682 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
683 #endif
684
685 #ifndef MULTILIB_DEFAULTS
686 #define MULTILIB_DEFAULTS \
687 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
688 #endif
689
690 /* We must pass -EL to the linker by default for little endian embedded
691 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
692 linker will default to using big-endian output files. The OUTPUT_FORMAT
693 line must be in the linker script, otherwise -EB/-EL will not work. */
694
695 #ifndef ENDIAN_SPEC
696 #if TARGET_ENDIAN_DEFAULT == 0
697 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
698 #else
699 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
700 #endif
701 #endif
702
703 /* A spec condition that matches all non-mips16 -mips arguments. */
704
705 #define MIPS_ISA_LEVEL_OPTION_SPEC \
706 "mips1|mips2|mips3|mips4|mips32*|mips64*"
707
708 /* A spec condition that matches all non-mips16 architecture arguments. */
709
710 #define MIPS_ARCH_OPTION_SPEC \
711 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
712
713 /* A spec that infers a -mips argument from an -march argument. */
714
715 #define MIPS_ISA_LEVEL_SPEC \
716 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
717 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
718 %{march=mips2|march=r6000:-mips2} \
719 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
720 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
721 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
722 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
723 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
724 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
725 %{march=mips32r3: -mips32r3} \
726 %{march=mips32r5|march=p5600: -mips32r5} \
727 %{march=mips32r6: -mips32r6} \
728 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
729 |march=xlr: -mips64} \
730 %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
731 %{march=mips64r3: -mips64r3} \
732 %{march=mips64r5: -mips64r5} \
733 %{march=mips64r6: -mips64r6}}"
734
735 /* A spec that injects the default multilib ISA if no architecture is
736 specified. */
737
738 #define MIPS_DEFAULT_ISA_LEVEL_SPEC \
739 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
740 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
741
742 /* A spec that infers a -mhard-float or -msoft-float setting from an
743 -march argument. Note that soft-float and hard-float code are not
744 link-compatible. */
745
746 #define MIPS_ARCH_FLOAT_SPEC \
747 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
748 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
749 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
750 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
751 march=*: -mhard-float}"
752
753 /* A spec condition that matches 32-bit options. It only works if
754 MIPS_ISA_LEVEL_SPEC has been applied. */
755
756 #define MIPS_32BIT_OPTION_SPEC \
757 "mips1|mips2|mips32*|mgp32"
758
759 /* A spec condition that matches architectures should be targeted with
760 o32 FPXX for compatibility reasons. */
761 #define MIPS_FPXX_OPTION_SPEC \
762 "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \
763 mips64|mips64r2|mips64r3|mips64r5"
764
765 /* Infer a -msynci setting from a -mips argument, on the assumption that
766 -msynci is desired where possible. */
767 #define MIPS_ISA_SYNCI_SPEC \
768 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \
769 |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}"
770
771 /* Infer a -mnan=2008 setting from a -mips argument. */
772 #define MIPS_ISA_NAN2008_SPEC \
773 "%{mnan*:;mips32r6|mips64r6:-mnan=2008}"
774
775 #if (MIPS_ABI_DEFAULT == ABI_O64 \
776 || MIPS_ABI_DEFAULT == ABI_N32 \
777 || MIPS_ABI_DEFAULT == ABI_64)
778 #define OPT_ARCH64 "mabi=32|mgp32:;"
779 #define OPT_ARCH32 "mabi=32|mgp32"
780 #else
781 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
782 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
783 #endif
784
785 /* Support for a compile-time default CPU, et cetera. The rules are:
786 --with-arch is ignored if -march is specified or a -mips is specified
787 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
788 --with-tune is ignored if -mtune is specified; likewise
789 --with-tune-32 and --with-tune-64.
790 --with-abi is ignored if -mabi is specified.
791 --with-float is ignored if -mhard-float or -msoft-float are
792 specified.
793 --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are
794 specified.
795 --with-nan is ignored if -mnan is specified.
796 --with-fp-32 is ignored if -msoft-float, -msingle-float or -mfp are specified.
797 --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg
798 or -mno-odd-spreg are specified.
799 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
800 specified. */
801 #define OPTION_DEFAULT_SPECS \
802 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
803 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
804 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
805 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
806 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
807 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
808 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
809 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
810 {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \
811 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
812 {"fp_32", "%{" OPT_ARCH32 \
813 ":%{!msoft-float:%{!msingle-float:%{!mfp*:-mfp%(VALUE)}}}}" }, \
814 {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \
815 "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \
816 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
817 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
818 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
819 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
820
821 /* A spec that infers the:
822 -mnan=2008 setting from a -mips argument,
823 -mdsp setting from a -march argument. */
824 #define BASE_DRIVER_SELF_SPECS \
825 MIPS_ISA_NAN2008_SPEC, \
826 "%{!mno-dsp: \
827 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
828 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
829
830 #define DRIVER_SELF_SPECS \
831 MIPS_ISA_LEVEL_SPEC, \
832 BASE_DRIVER_SELF_SPECS
833
834 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
835 && ISA_HAS_COND_TRAP)
836
837 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
838
839 /* True if the ABI can only work with 64-bit integer registers. We
840 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
841 otherwise floating-point registers must also be 64-bit. */
842 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
843
844 /* Likewise for 32-bit regs. */
845 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
846
847 /* True if the file format uses 64-bit symbols. At present, this is
848 only true for n64, which uses 64-bit ELF. */
849 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
850
851 /* True if symbols are 64 bits wide. This is usually determined by
852 the ABI's file format, but it can be overridden by -msym32. Note that
853 overriding the size with -msym32 changes the ABI of relocatable objects,
854 although it doesn't change the ABI of a fully-linked object. */
855 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
856 && Pmode == DImode \
857 && !TARGET_SYM32)
858
859 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
860 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
861 || ISA_MIPS4 \
862 || ISA_MIPS64 \
863 || ISA_MIPS64R2 \
864 || ISA_MIPS64R3 \
865 || ISA_MIPS64R5 \
866 || ISA_MIPS64R6)
867
868 #define ISA_HAS_JR (mips_isa_rev <= 5)
869
870 /* ISA has branch likely instructions (e.g. mips2). */
871 /* Disable branchlikely for tx39 until compare rewrite. They haven't
872 been generated up to this point. */
873 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5)
874
875 /* ISA has 32 single-precision registers. */
876 #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \
877 && !TARGET_LOONGSON_3A) \
878 || TARGET_FLOAT64 \
879 || TARGET_MIPS5900)
880
881 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
882 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
883 || TARGET_MIPS5400 \
884 || TARGET_MIPS5500 \
885 || TARGET_MIPS5900 \
886 || TARGET_MIPS7000 \
887 || TARGET_MIPS9000 \
888 || TARGET_MAD \
889 || (mips_isa_rev >= 1 \
890 && mips_isa_rev <= 5)) \
891 && !TARGET_MIPS16)
892
893 /* ISA has a three-operand multiplication instruction. */
894 #define ISA_HAS_DMUL3 (TARGET_64BIT \
895 && TARGET_OCTEON \
896 && !TARGET_MIPS16)
897
898 /* ISA has HI and LO registers. */
899 #define ISA_HAS_HILO (mips_isa_rev <= 5)
900
901 /* ISA supports instructions DMULT and DMULTU. */
902 #define ISA_HAS_DMULT (TARGET_64BIT \
903 && !TARGET_MIPS5900 \
904 && mips_isa_rev <= 5)
905
906 /* ISA supports instructions MULT and MULTU. */
907 #define ISA_HAS_MULT (mips_isa_rev <= 5)
908
909 /* ISA supports instructions MUL, MULU, MUH, MUHU. */
910 #define ISA_HAS_R6MUL (mips_isa_rev >= 6)
911
912 /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */
913 #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6)
914
915 /* ISA supports instructions DDIV and DDIVU. */
916 #define ISA_HAS_DDIV (TARGET_64BIT \
917 && !TARGET_MIPS5900 \
918 && mips_isa_rev <= 5)
919
920 /* ISA supports instructions DIV and DIVU.
921 This is always true, but the macro is needed for ISA_HAS_<D>DIV
922 in mips.md. */
923 #define ISA_HAS_DIV (mips_isa_rev <= 5)
924
925 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
926 || TARGET_LOONGSON_3A) \
927 && !TARGET_MIPS16)
928
929 /* ISA supports instructions DIV, DIVU, MOD and MODU. */
930 #define ISA_HAS_R6DIV (mips_isa_rev >= 6)
931
932 /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */
933 #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6)
934
935 /* ISA has the floating-point conditional move instructions introduced
936 in mips4. */
937 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
938 || (mips_isa_rev >= 1 \
939 && mips_isa_rev <= 5)) \
940 && !TARGET_MIPS5500 \
941 && !TARGET_MIPS16)
942
943 /* ISA has the integer conditional move instructions introduced in mips4 and
944 ST Loongson 2E/2F. */
945 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
946 || TARGET_MIPS5900 \
947 || TARGET_LOONGSON_2EF)
948
949 /* ISA has LDC1 and SDC1. */
950 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
951 && !TARGET_MIPS5900 \
952 && !TARGET_MIPS16)
953
954 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
955 branch on CC, and move (both FP and non-FP) on CC. */
956 #define ISA_HAS_8CC (ISA_MIPS4 \
957 || (mips_isa_rev >= 1 \
958 && mips_isa_rev <= 5))
959
960 /* ISA has the FP condition code instructions that store the flag in an
961 FP register. */
962 #define ISA_HAS_CCF (mips_isa_rev >= 6)
963
964 #define ISA_HAS_SEL (mips_isa_rev >= 6)
965
966 /* This is a catch all for other mips4 instructions: indexed load, the
967 FP madd and msub instructions, and the FP recip and recip sqrt
968 instructions. Note that this macro should only be used by other
969 ISA_HAS_* macros. */
970 #define ISA_HAS_FP4 ((ISA_MIPS4 \
971 || ISA_MIPS64 \
972 || (mips_isa_rev >= 2 \
973 && mips_isa_rev <= 5)) \
974 && !TARGET_MIPS16)
975
976 /* ISA has floating-point indexed load and store instructions
977 (LWXC1, LDXC1, SWXC1 and SDXC1). */
978 #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
979
980 /* ISA has paired-single instructions. */
981 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS64 \
982 || (mips_isa_rev >= 2 \
983 && mips_isa_rev <= 5))
984
985 /* ISA has conditional trap instructions. */
986 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
987 && !TARGET_MIPS16)
988
989 /* ISA has conditional trap with immediate instructions. */
990 #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \
991 && mips_isa_rev <= 5 \
992 && !TARGET_MIPS16)
993
994 /* ISA has integer multiply-accumulate instructions, madd and msub. */
995 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \
996 && mips_isa_rev <= 5)
997
998 /* Integer multiply-accumulate instructions should be generated. */
999 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
1000
1001 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
1002 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
1003
1004 /* ISA has floating-point MADDF and MSUBF instructions 'd = d [+-] a * b'. */
1005 #define ISA_HAS_FP_MADDF_MSUBF (mips_isa_rev >= 6)
1006
1007 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
1008 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
1009
1010 /* ISA has floating-point nmadd and nmsub instructions
1011 'd = -((a * b) [+-] c)'. */
1012 #define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4
1013
1014 /* ISA has floating-point nmadd and nmsub instructions
1015 'c = -((a * b) [+-] c)'. */
1016 #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF
1017
1018 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
1019 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
1020 doubles are stored in pairs of FPRs, so for safety's sake, we apply
1021 this restriction to the MIPS IV ISA too. */
1022 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
1023 (((ISA_HAS_FP4 \
1024 && ((MODE) == SFmode \
1025 || ((TARGET_FLOAT64 \
1026 || mips_isa_rev >= 2) \
1027 && (MODE) == DFmode))) \
1028 || (((MODE) == SFmode \
1029 || (MODE) == DFmode) \
1030 && (mips_isa_rev >= 6)) \
1031 || (TARGET_SB1 \
1032 && (MODE) == V2SFmode)) \
1033 && !TARGET_MIPS16)
1034
1035 #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16)
1036
1037 #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5)
1038
1039 #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2)
1040
1041 /* ISA has count leading zeroes/ones instruction (not implemented). */
1042 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
1043
1044 /* ISA has three operand multiply instructions that put
1045 the high part in an accumulator: mulhi or mulhiu. */
1046 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
1047 || TARGET_MIPS5500 \
1048 || TARGET_SR71K) \
1049 && !TARGET_MIPS16)
1050
1051 /* ISA has three operand multiply instructions that negate the
1052 result and put the result in an accumulator. */
1053 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
1054 || TARGET_MIPS5500 \
1055 || TARGET_SR71K) \
1056 && !TARGET_MIPS16)
1057
1058 /* ISA has three operand multiply instructions that subtract the
1059 result from a 4th operand and put the result in an accumulator. */
1060 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
1061 || TARGET_MIPS5500 \
1062 || TARGET_SR71K) \
1063 && !TARGET_MIPS16)
1064
1065 /* ISA has three operand multiply instructions that add the result
1066 to a 4th operand and put the result in an accumulator. */
1067 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
1068 || TARGET_MIPS4130 \
1069 || TARGET_MIPS5400 \
1070 || TARGET_MIPS5500 \
1071 || TARGET_SR71K) \
1072 && !TARGET_MIPS16)
1073
1074 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
1075 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
1076 || TARGET_MIPS4130) \
1077 && !TARGET_MIPS16)
1078
1079 /* ISA has the "ror" (rotate right) instructions. */
1080 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
1081 || TARGET_MIPS5400 \
1082 || TARGET_MIPS5500 \
1083 || TARGET_SR71K \
1084 || TARGET_SMARTMIPS) \
1085 && !TARGET_MIPS16)
1086
1087 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1088 64-bit targets also provide DSBH and DSHD. */
1089 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1090
1091 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1092 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1093 || TARGET_LOONGSON_2EF \
1094 || TARGET_MIPS5900 \
1095 || mips_isa_rev >= 1) \
1096 && !TARGET_MIPS16)
1097
1098 /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */
1099 #define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6)
1100
1101 /* ISA has data indexed prefetch instructions. This controls use of
1102 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1103 (prefx is a cop1x instruction, so can only be used if FP is
1104 enabled.) */
1105 #define ISA_HAS_PREFETCHX ISA_HAS_FP4
1106
1107 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1108 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1109 also requires TARGET_DOUBLE_FLOAT. */
1110 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1111
1112 /* ISA includes the MIPS32r2 seb and seh instructions. */
1113 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1114
1115 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1116 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1117
1118 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1119 #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \
1120 && mips_isa_rev >= 2)
1121
1122 /* ISA has lwxs instruction (load w/scaled index address. */
1123 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1124 && !TARGET_MIPS16)
1125
1126 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1127 #define ISA_HAS_LBX (TARGET_OCTEON2)
1128 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1129 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1130 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1131 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1132 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1133 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1134 && TARGET_64BIT)
1135
1136 /* The DSP ASE is available. */
1137 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1138
1139 /* Revision 2 of the DSP ASE is available. */
1140 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1141
1142 /* True if the result of a load is not available to the next instruction.
1143 A nop will then be needed between instructions like "lw $4,..."
1144 and "addiu $4,$4,1". */
1145 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1146 && !TARGET_MIPS3900 \
1147 && !TARGET_MIPS5900 \
1148 && !TARGET_MIPS16 \
1149 && !TARGET_MICROMIPS)
1150
1151 /* Likewise mtc1 and mfc1. */
1152 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1153 && !TARGET_MIPS5900 \
1154 && !TARGET_LOONGSON_2EF)
1155
1156 /* Likewise floating-point comparisons. */
1157 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1158 && !TARGET_MIPS5900 \
1159 && !TARGET_LOONGSON_2EF)
1160
1161 /* True if mflo and mfhi can be immediately followed by instructions
1162 which write to the HI and LO registers.
1163
1164 According to MIPS specifications, MIPS ISAs I, II, and III need
1165 (at least) two instructions between the reads of HI/LO and
1166 instructions which write them, and later ISAs do not. Contradicting
1167 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1168 the UM for the NEC Vr5000) document needing the instructions between
1169 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1170 MIPS64 and later ISAs to have the interlocks, plus any specific
1171 earlier-ISA CPUs for which CPU documentation declares that the
1172 instructions are really interlocked. */
1173 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1174 || TARGET_MIPS5500 \
1175 || TARGET_MIPS5900 \
1176 || TARGET_LOONGSON_2EF)
1177
1178 /* ISA includes synci, jr.hb and jalr.hb. */
1179 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1180
1181 /* ISA includes sync. */
1182 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1183 #define GENERATE_SYNC \
1184 (target_flags_explicit & MASK_LLSC \
1185 ? TARGET_LLSC && !TARGET_MIPS16 \
1186 : ISA_HAS_SYNC)
1187
1188 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1189 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1190 instructions. */
1191 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1192 #define GENERATE_LL_SC \
1193 (target_flags_explicit & MASK_LLSC \
1194 ? TARGET_LLSC && !TARGET_MIPS16 \
1195 : ISA_HAS_LL_SC)
1196
1197 #define ISA_HAS_SWAP (TARGET_XLP)
1198 #define ISA_HAS_LDADD (TARGET_XLP)
1199
1200 /* ISA includes the baddu instruction. */
1201 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1202
1203 /* ISA includes the bbit* instructions. */
1204 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1205
1206 /* ISA includes the cins instruction. */
1207 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1208
1209 /* ISA includes the exts instruction. */
1210 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1211
1212 /* ISA includes the seq and sne instructions. */
1213 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1214
1215 /* ISA includes the pop instruction. */
1216 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1217
1218 /* The CACHE instruction is available in non-MIPS16 code. */
1219 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1220
1221 /* The CACHE instruction is available. */
1222 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1223 \f
1224 /* Tell collect what flags to pass to nm. */
1225 #ifndef NM_FLAGS
1226 #define NM_FLAGS "-Bn"
1227 #endif
1228
1229 \f
1230 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1231 the assembler. It may be overridden by subtargets.
1232
1233 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1234 COFF debugging info. */
1235
1236 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1237 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1238 %{g} %{g0} %{g1} %{g2} %{g3} \
1239 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1240 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1241 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1242 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1243 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1244 #endif
1245
1246 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1247 overridden by subtargets. */
1248
1249 #ifndef SUBTARGET_ASM_SPEC
1250 #define SUBTARGET_ASM_SPEC ""
1251 #endif
1252
1253 #undef ASM_SPEC
1254 #define ASM_SPEC "\
1255 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1256 %{mips32*} %{mips64*} \
1257 %{mips16} %{mno-mips16:-no-mips16} \
1258 %{mmicromips} %{mno-micromips} \
1259 %{mips3d} %{mno-mips3d:-no-mips3d} \
1260 %{mdmx} %{mno-mdmx:-no-mdmx} \
1261 %{mdsp} %{mno-dsp} \
1262 %{mdspr2} %{mno-dspr2} \
1263 %{mmcu} %{mno-mcu} \
1264 %{meva} %{mno-eva} \
1265 %{mvirt} %{mno-virt} \
1266 %{mxpa} %{mno-xpa} \
1267 %{msmartmips} %{mno-smartmips} \
1268 %{mmt} %{mno-mt} \
1269 %{mfix-rm7000} %{mno-fix-rm7000} \
1270 %{mfix-vr4120} %{mfix-vr4130} \
1271 %{mfix-24k} \
1272 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1273 %(subtarget_asm_debugging_spec) \
1274 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1275 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1276 %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \
1277 %{modd-spreg} %{mno-odd-spreg} \
1278 %{mshared} %{mno-shared} \
1279 %{msym32} %{mno-sym32} \
1280 %{mtune=*} \
1281 %{mhard-float} %{msoft-float} \
1282 %{msingle-float} %{mdouble-float} \
1283 %(subtarget_asm_spec)"
1284
1285 /* Extra switches sometimes passed to the linker. */
1286
1287 #ifndef LINK_SPEC
1288 #define LINK_SPEC "\
1289 %(endian_spec) \
1290 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1291 %{shared}"
1292 #endif /* LINK_SPEC defined */
1293
1294
1295 /* Specs for the compiler proper */
1296
1297 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1298 overridden by subtargets. */
1299 #ifndef SUBTARGET_CC1_SPEC
1300 #define SUBTARGET_CC1_SPEC ""
1301 #endif
1302
1303 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1304
1305 #undef CC1_SPEC
1306 #define CC1_SPEC "\
1307 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1308 %(subtarget_cc1_spec)"
1309
1310 /* Preprocessor specs. */
1311
1312 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1313 overridden by subtargets. */
1314 #ifndef SUBTARGET_CPP_SPEC
1315 #define SUBTARGET_CPP_SPEC ""
1316 #endif
1317
1318 #define CPP_SPEC "%(subtarget_cpp_spec)"
1319
1320 /* This macro defines names of additional specifications to put in the specs
1321 that can be used in various specifications like CC1_SPEC. Its definition
1322 is an initializer with a subgrouping for each command option.
1323
1324 Each subgrouping contains a string constant, that defines the
1325 specification name, and a string constant that used by the GCC driver
1326 program.
1327
1328 Do not define this macro if it does not need to do anything. */
1329
1330 #define EXTRA_SPECS \
1331 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1332 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1333 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1334 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1335 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1336 { "endian_spec", ENDIAN_SPEC }, \
1337 SUBTARGET_EXTRA_SPECS
1338
1339 #ifndef SUBTARGET_EXTRA_SPECS
1340 #define SUBTARGET_EXTRA_SPECS
1341 #endif
1342 \f
1343 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1344 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1345
1346 #ifndef PREFERRED_DEBUGGING_TYPE
1347 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1348 #endif
1349
1350 /* The size of DWARF addresses should be the same as the size of symbols
1351 in the target file format. They shouldn't depend on things like -msym32,
1352 because many DWARF consumers do not allow the mixture of address sizes
1353 that one would then get from linking -msym32 code with -msym64 code.
1354
1355 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1356 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1357 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1358
1359 /* By default, turn on GDB extensions. */
1360 #define DEFAULT_GDB_EXTENSIONS 1
1361
1362 /* Registers may have a prefix which can be ignored when matching
1363 user asm and register definitions. */
1364 #ifndef REGISTER_PREFIX
1365 #define REGISTER_PREFIX "$"
1366 #endif
1367
1368 /* Local compiler-generated symbols must have a prefix that the assembler
1369 understands. By default, this is $, although some targets (e.g.,
1370 NetBSD-ELF) need to override this. */
1371
1372 #ifndef LOCAL_LABEL_PREFIX
1373 #define LOCAL_LABEL_PREFIX "$"
1374 #endif
1375
1376 /* By default on the mips, external symbols do not have an underscore
1377 prepended, but some targets (e.g., NetBSD) require this. */
1378
1379 #ifndef USER_LABEL_PREFIX
1380 #define USER_LABEL_PREFIX ""
1381 #endif
1382
1383 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1384 since the length can run past this up to a continuation point. */
1385 #undef DBX_CONTIN_LENGTH
1386 #define DBX_CONTIN_LENGTH 1500
1387
1388 /* How to renumber registers for dbx and gdb. */
1389 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1390
1391 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1392 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1393
1394 /* The DWARF 2 CFA column which tracks the return address. */
1395 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1396
1397 /* Before the prologue, RA lives in r31. */
1398 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1399
1400 /* Describe how we implement __builtin_eh_return. */
1401 #define EH_RETURN_DATA_REGNO(N) \
1402 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1403
1404 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1405
1406 #define EH_USES(N) mips_eh_uses (N)
1407
1408 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1409 The default for this in 64-bit mode is 8, which causes problems with
1410 SFmode register saves. */
1411 #define DWARF_CIE_DATA_ALIGNMENT -4
1412
1413 /* Correct the offset of automatic variables and arguments. Note that
1414 the MIPS debug format wants all automatic variables and arguments
1415 to be in terms of the virtual frame pointer (stack pointer before
1416 any adjustment in the function), while the MIPS 3.0 linker wants
1417 the frame pointer to be the stack pointer after the initial
1418 adjustment. */
1419
1420 #define DEBUGGER_AUTO_OFFSET(X) \
1421 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1422 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1423 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1424 \f
1425 /* Target machine storage layout */
1426
1427 #define BITS_BIG_ENDIAN 0
1428 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1429 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1430
1431 #define MAX_BITS_PER_WORD 64
1432
1433 /* Width of a word, in units (bytes). */
1434 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1435 #ifndef IN_LIBGCC2
1436 #define MIN_UNITS_PER_WORD 4
1437 #endif
1438
1439 /* For MIPS, width of a floating point register. */
1440 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1441
1442 /* The number of consecutive floating-point registers needed to store the
1443 largest format supported by the FPU. */
1444 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1445
1446 /* The number of consecutive floating-point registers needed to store the
1447 smallest format supported by the FPU. */
1448 #define MIN_FPRS_PER_FMT \
1449 (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT)
1450
1451 /* The largest size of value that can be held in floating-point
1452 registers and moved with a single instruction. */
1453 #define UNITS_PER_HWFPVALUE \
1454 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1455
1456 /* The largest size of value that can be held in floating-point
1457 registers. */
1458 #define UNITS_PER_FPVALUE \
1459 (TARGET_SOFT_FLOAT_ABI ? 0 \
1460 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1461 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1462
1463 /* The number of bytes in a double. */
1464 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1465
1466 /* Set the sizes of the core types. */
1467 #define SHORT_TYPE_SIZE 16
1468 #define INT_TYPE_SIZE 32
1469 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1470 #define LONG_LONG_TYPE_SIZE 64
1471
1472 #define FLOAT_TYPE_SIZE 32
1473 #define DOUBLE_TYPE_SIZE 64
1474 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1475
1476 /* Define the sizes of fixed-point types. */
1477 #define SHORT_FRACT_TYPE_SIZE 8
1478 #define FRACT_TYPE_SIZE 16
1479 #define LONG_FRACT_TYPE_SIZE 32
1480 #define LONG_LONG_FRACT_TYPE_SIZE 64
1481
1482 #define SHORT_ACCUM_TYPE_SIZE 16
1483 #define ACCUM_TYPE_SIZE 32
1484 #define LONG_ACCUM_TYPE_SIZE 64
1485 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1486 doesn't support 128-bit integers for MIPS32 currently. */
1487 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1488
1489 /* long double is not a fixed mode, but the idea is that, if we
1490 support long double, we also want a 128-bit integer type. */
1491 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1492
1493 /* Width in bits of a pointer. */
1494 #ifndef POINTER_SIZE
1495 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1496 #endif
1497
1498 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1499 #define PARM_BOUNDARY BITS_PER_WORD
1500
1501 /* Allocation boundary (in *bits*) for the code of a function. */
1502 #define FUNCTION_BOUNDARY 32
1503
1504 /* Alignment of field after `int : 0' in a structure. */
1505 #define EMPTY_FIELD_BOUNDARY 32
1506
1507 /* Every structure's size must be a multiple of this. */
1508 /* 8 is observed right on a DECstation and on riscos 4.02. */
1509 #define STRUCTURE_SIZE_BOUNDARY 8
1510
1511 /* There is no point aligning anything to a rounder boundary than this. */
1512 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1513
1514 /* All accesses must be aligned. */
1515 #define STRICT_ALIGNMENT 1
1516
1517 /* Define this if you wish to imitate the way many other C compilers
1518 handle alignment of bitfields and the structures that contain
1519 them.
1520
1521 The behavior is that the type written for a bit-field (`int',
1522 `short', or other integer type) imposes an alignment for the
1523 entire structure, as if the structure really did contain an
1524 ordinary field of that type. In addition, the bit-field is placed
1525 within the structure so that it would fit within such a field,
1526 not crossing a boundary for it.
1527
1528 Thus, on most machines, a bit-field whose type is written as `int'
1529 would not cross a four-byte boundary, and would force four-byte
1530 alignment for the whole structure. (The alignment used may not
1531 be four bytes; it is controlled by the other alignment
1532 parameters.)
1533
1534 If the macro is defined, its definition should be a C expression;
1535 a nonzero value for the expression enables this behavior. */
1536
1537 #define PCC_BITFIELD_TYPE_MATTERS 1
1538
1539 /* If defined, a C expression to compute the alignment given to a
1540 constant that is being placed in memory. CONSTANT is the constant
1541 and ALIGN is the alignment that the object would ordinarily have.
1542 The value of this macro is used instead of that alignment to align
1543 the object.
1544
1545 If this macro is not defined, then ALIGN is used.
1546
1547 The typical use of this macro is to increase alignment for string
1548 constants to be word aligned so that `strcpy' calls that copy
1549 constants can be done inline. */
1550
1551 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1552 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1553 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1554
1555 /* If defined, a C expression to compute the alignment for a static
1556 variable. TYPE is the data type, and ALIGN is the alignment that
1557 the object would ordinarily have. The value of this macro is used
1558 instead of that alignment to align the object.
1559
1560 If this macro is not defined, then ALIGN is used.
1561
1562 One use of this macro is to increase alignment of medium-size
1563 data to make it all fit in fewer cache lines. Another is to
1564 cause character arrays to be word-aligned so that `strcpy' calls
1565 that copy constants to character arrays can be done inline. */
1566
1567 #undef DATA_ALIGNMENT
1568 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1569 ((((ALIGN) < BITS_PER_WORD) \
1570 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1571 || TREE_CODE (TYPE) == UNION_TYPE \
1572 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1573
1574 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1575 character arrays to be word-aligned so that `strcpy' calls that copy
1576 constants to character arrays can be done inline, and 'strcmp' can be
1577 optimised to use word loads. */
1578 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1579 DATA_ALIGNMENT (TYPE, ALIGN)
1580
1581 #define PAD_VARARGS_DOWN \
1582 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1583
1584 /* Define if operations between registers always perform the operation
1585 on the full register even if a narrower mode is specified. */
1586 #define WORD_REGISTER_OPERATIONS
1587
1588 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1589 moves. All other references are zero extended. */
1590 #define LOAD_EXTEND_OP(MODE) \
1591 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1592 ? SIGN_EXTEND : ZERO_EXTEND)
1593
1594 /* Define this macro if it is advisable to hold scalars in registers
1595 in a wider mode than that declared by the program. In such cases,
1596 the value is constrained to be within the bounds of the declared
1597 type, but kept valid in the wider mode. The signedness of the
1598 extension may differ from that of the type. */
1599
1600 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1601 if (GET_MODE_CLASS (MODE) == MODE_INT \
1602 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1603 { \
1604 if ((MODE) == SImode) \
1605 (UNSIGNEDP) = 0; \
1606 (MODE) = Pmode; \
1607 }
1608
1609 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1610 Extensions of pointers to word_mode must be signed. */
1611 #define POINTERS_EXTEND_UNSIGNED false
1612
1613 /* Define if loading short immediate values into registers sign extends. */
1614 #define SHORT_IMMEDIATES_SIGN_EXTEND
1615
1616 /* The [d]clz instructions have the natural values at 0. */
1617
1618 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1619 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1620 \f
1621 /* Standard register usage. */
1622
1623 /* Number of hardware registers. We have:
1624
1625 - 32 integer registers
1626 - 32 floating point registers
1627 - 8 condition code registers
1628 - 2 accumulator registers (hi and lo)
1629 - 32 registers each for coprocessors 0, 2 and 3
1630 - 4 fake registers:
1631 - ARG_POINTER_REGNUM
1632 - FRAME_POINTER_REGNUM
1633 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1634 - CPRESTORE_SLOT_REGNUM
1635 - 2 dummy entries that were used at various times in the past.
1636 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1637 - 6 DSP control registers */
1638
1639 #define FIRST_PSEUDO_REGISTER 188
1640
1641 /* By default, fix the kernel registers ($26 and $27), the global
1642 pointer ($28) and the stack pointer ($29). This can change
1643 depending on the command-line options.
1644
1645 Regarding coprocessor registers: without evidence to the contrary,
1646 it's best to assume that each coprocessor register has a unique
1647 use. This can be overridden, in, e.g., mips_option_override or
1648 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1649 inappropriate for a particular target. */
1650
1651 #define FIXED_REGISTERS \
1652 { \
1653 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1654 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1655 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1656 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1657 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1658 /* COP0 registers */ \
1659 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1660 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1661 /* COP2 registers */ \
1662 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1663 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1664 /* COP3 registers */ \
1665 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1666 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1667 /* 6 DSP accumulator registers & 6 control registers */ \
1668 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1669 }
1670
1671
1672 /* Set up this array for o32 by default.
1673
1674 Note that we don't mark $31 as a call-clobbered register. The idea is
1675 that it's really the call instructions themselves which clobber $31.
1676 We don't care what the called function does with it afterwards.
1677
1678 This approach makes it easier to implement sibcalls. Unlike normal
1679 calls, sibcalls don't clobber $31, so the register reaches the
1680 called function in tact. EPILOGUE_USES says that $31 is useful
1681 to the called function. */
1682
1683 #define CALL_USED_REGISTERS \
1684 { \
1685 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1686 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1687 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1688 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1689 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1690 /* COP0 registers */ \
1691 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1692 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1693 /* COP2 registers */ \
1694 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1695 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1696 /* COP3 registers */ \
1697 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1698 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1699 /* 6 DSP accumulator registers & 6 control registers */ \
1700 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1701 }
1702
1703
1704 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1705
1706 #define CALL_REALLY_USED_REGISTERS \
1707 { /* General registers. */ \
1708 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1709 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1710 /* Floating-point registers. */ \
1711 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1712 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1713 /* Others. */ \
1714 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1715 /* COP0 registers */ \
1716 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1717 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1718 /* COP2 registers */ \
1719 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1720 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1721 /* COP3 registers */ \
1722 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1723 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1724 /* 6 DSP accumulator registers & 6 control registers */ \
1725 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1726 }
1727
1728 /* Internal macros to classify a register number as to whether it's a
1729 general purpose register, a floating point register, a
1730 multiply/divide register, or a status register. */
1731
1732 #define GP_REG_FIRST 0
1733 #define GP_REG_LAST 31
1734 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1735 #define GP_DBX_FIRST 0
1736 #define K0_REG_NUM (GP_REG_FIRST + 26)
1737 #define K1_REG_NUM (GP_REG_FIRST + 27)
1738 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1739
1740 #define FP_REG_FIRST 32
1741 #define FP_REG_LAST 63
1742 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1743 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1744
1745 #define MD_REG_FIRST 64
1746 #define MD_REG_LAST 65
1747 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1748 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1749
1750 /* The DWARF 2 CFA column which tracks the return address from a
1751 signal handler context. This means that to maintain backwards
1752 compatibility, no hard register can be assigned this column if it
1753 would need to be handled by the DWARF unwinder. */
1754 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1755
1756 #define ST_REG_FIRST 67
1757 #define ST_REG_LAST 74
1758 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1759
1760
1761 /* FIXME: renumber. */
1762 #define COP0_REG_FIRST 80
1763 #define COP0_REG_LAST 111
1764 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1765
1766 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1767 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1768 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1769
1770 #define COP2_REG_FIRST 112
1771 #define COP2_REG_LAST 143
1772 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1773
1774 #define COP3_REG_FIRST 144
1775 #define COP3_REG_LAST 175
1776 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1777
1778 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1779 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1780 #define ALL_COP_REG_LAST COP3_REG_LAST
1781 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1782
1783 #define DSP_ACC_REG_FIRST 176
1784 #define DSP_ACC_REG_LAST 181
1785 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1786
1787 #define AT_REGNUM (GP_REG_FIRST + 1)
1788 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1789 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1790
1791 /* A few bitfield locations for the coprocessor registers. */
1792 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1793 the cause register for the EIC interrupt mode. */
1794 #define CAUSE_IPL 10
1795 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1796 #define SR_IPL 10
1797 /* Exception Level is at bit 1 of the status register. */
1798 #define SR_EXL 1
1799 /* Interrupt Enable is at bit 0 of the status register. */
1800 #define SR_IE 0
1801
1802 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1803 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1804 should be used instead. */
1805 #define FPSW_REGNUM ST_REG_FIRST
1806
1807 #define GP_REG_P(REGNO) \
1808 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1809 #define M16_REG_P(REGNO) \
1810 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1811 #define M16STORE_REG_P(REGNO) \
1812 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1813 #define FP_REG_P(REGNO) \
1814 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1815 #define MD_REG_P(REGNO) \
1816 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1817 #define ST_REG_P(REGNO) \
1818 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1819 #define COP0_REG_P(REGNO) \
1820 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1821 #define COP2_REG_P(REGNO) \
1822 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1823 #define COP3_REG_P(REGNO) \
1824 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1825 #define ALL_COP_REG_P(REGNO) \
1826 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1827 /* Test if REGNO is one of the 6 new DSP accumulators. */
1828 #define DSP_ACC_REG_P(REGNO) \
1829 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1830 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1831 #define ACC_REG_P(REGNO) \
1832 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1833
1834 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1835
1836 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1837 to initialize the mips16 gp pseudo register. */
1838 #define CONST_GP_P(X) \
1839 (GET_CODE (X) == CONST \
1840 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1841 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1842
1843 /* Return coprocessor number from register number. */
1844
1845 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1846 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1847 : COP3_REG_P (REGNO) ? '3' : '?')
1848
1849
1850 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1851
1852 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1853 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1854
1855 /* Select a register mode required for caller save of hard regno REGNO. */
1856 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1857 mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE)
1858
1859 /* Odd-numbered single-precision registers are not considered callee-saved
1860 for o32 FPXX as they will be clobbered when run on an FR=1 FPU. */
1861 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1862 (TARGET_FLOATXX && hard_regno_nregs[REGNO][MODE] == 1 \
1863 && FP_REG_P (REGNO) && ((REGNO) & 1))
1864
1865 #define MODES_TIEABLE_P mips_modes_tieable_p
1866
1867 /* Register to use for pushing function arguments. */
1868 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1869
1870 /* These two registers don't really exist: they get eliminated to either
1871 the stack or hard frame pointer. */
1872 #define ARG_POINTER_REGNUM 77
1873 #define FRAME_POINTER_REGNUM 78
1874
1875 /* $30 is not available on the mips16, so we use $17 as the frame
1876 pointer. */
1877 #define HARD_FRAME_POINTER_REGNUM \
1878 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1879
1880 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1881 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1882
1883 /* Register in which static-chain is passed to a function. */
1884 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1885
1886 /* Registers used as temporaries in prologue/epilogue code:
1887
1888 - If a MIPS16 PIC function needs access to _gp, it first loads
1889 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1890
1891 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1892 register. The register must not conflict with MIPS16_PIC_TEMP.
1893
1894 - If we aren't generating MIPS16 code, the prologue can also use
1895 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1896
1897 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1898 register.
1899
1900 If we're generating MIPS16 code, these registers must come from the
1901 core set of 8. The prologue registers mustn't conflict with any
1902 incoming arguments, the static chain pointer, or the frame pointer.
1903 The epilogue temporary mustn't conflict with the return registers,
1904 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1905 or the EH data registers.
1906
1907 If we're generating interrupt handlers, we use K0 as a temporary register
1908 in prologue/epilogue code. */
1909
1910 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1911 #define MIPS_PROLOGUE_TEMP_REGNUM \
1912 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1913 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1914 (TARGET_MIPS16 \
1915 ? (gcc_unreachable (), INVALID_REGNUM) \
1916 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1917 #define MIPS_EPILOGUE_TEMP_REGNUM \
1918 (cfun->machine->interrupt_handler_p \
1919 ? K0_REG_NUM \
1920 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1921
1922 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1923 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1924 #define MIPS_PROLOGUE_TEMP2(MODE) \
1925 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1926 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1927
1928 /* Define this macro if it is as good or better to call a constant
1929 function address than to call an address kept in a register. */
1930 #define NO_FUNCTION_CSE 1
1931
1932 /* The ABI-defined global pointer. Sometimes we use a different
1933 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1934 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1935
1936 /* We normally use $28 as the global pointer. However, when generating
1937 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1938 register instead. They can then avoid saving and restoring $28
1939 and perhaps avoid using a frame at all.
1940
1941 When a leaf function uses something other than $28, mips_expand_prologue
1942 will modify pic_offset_table_rtx in place. Take the register number
1943 from there after reload. */
1944 #define PIC_OFFSET_TABLE_REGNUM \
1945 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1946 \f
1947 /* Define the classes of registers for register constraints in the
1948 machine description. Also define ranges of constants.
1949
1950 One of the classes must always be named ALL_REGS and include all hard regs.
1951 If there is more than one class, another class must be named NO_REGS
1952 and contain no registers.
1953
1954 The name GENERAL_REGS must be the name of a class (or an alias for
1955 another name such as ALL_REGS). This is the class of registers
1956 that is allowed by "g" or "r" in a register constraint.
1957 Also, registers outside this class are allocated only when
1958 instructions express preferences for them.
1959
1960 The classes must be numbered in nondecreasing order; that is,
1961 a larger-numbered class must never be contained completely
1962 in a smaller-numbered class.
1963
1964 For any two classes, it is very desirable that there be another
1965 class that represents their union. */
1966
1967 enum reg_class
1968 {
1969 NO_REGS, /* no registers in set */
1970 M16_STORE_REGS, /* microMIPS store registers */
1971 M16_REGS, /* mips16 directly accessible registers */
1972 M16_SP_REGS, /* mips16 + $sp */
1973 T_REG, /* mips16 T register ($24) */
1974 M16_T_REGS, /* mips16 registers plus T register */
1975 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1976 V1_REG, /* Register $v1 ($3) used for TLS access. */
1977 SPILL_REGS, /* All but $sp and call preserved regs are in here */
1978 LEA_REGS, /* Every GPR except $25 */
1979 GR_REGS, /* integer registers */
1980 FP_REGS, /* floating point registers */
1981 MD0_REG, /* first multiply/divide register */
1982 MD1_REG, /* second multiply/divide register */
1983 MD_REGS, /* multiply/divide registers (hi/lo) */
1984 COP0_REGS, /* generic coprocessor classes */
1985 COP2_REGS,
1986 COP3_REGS,
1987 ST_REGS, /* status registers (fp status) */
1988 DSP_ACC_REGS, /* DSP accumulator registers */
1989 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1990 FRAME_REGS, /* $arg and $frame */
1991 GR_AND_MD0_REGS, /* union classes */
1992 GR_AND_MD1_REGS,
1993 GR_AND_MD_REGS,
1994 GR_AND_ACC_REGS,
1995 ALL_REGS, /* all registers */
1996 LIM_REG_CLASSES /* max value + 1 */
1997 };
1998
1999 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2000
2001 #define GENERAL_REGS GR_REGS
2002
2003 /* An initializer containing the names of the register classes as C
2004 string constants. These names are used in writing some of the
2005 debugging dumps. */
2006
2007 #define REG_CLASS_NAMES \
2008 { \
2009 "NO_REGS", \
2010 "M16_STORE_REGS", \
2011 "M16_REGS", \
2012 "M16_SP_REGS", \
2013 "T_REG", \
2014 "M16_T_REGS", \
2015 "PIC_FN_ADDR_REG", \
2016 "V1_REG", \
2017 "SPILL_REGS", \
2018 "LEA_REGS", \
2019 "GR_REGS", \
2020 "FP_REGS", \
2021 "MD0_REG", \
2022 "MD1_REG", \
2023 "MD_REGS", \
2024 /* coprocessor registers */ \
2025 "COP0_REGS", \
2026 "COP2_REGS", \
2027 "COP3_REGS", \
2028 "ST_REGS", \
2029 "DSP_ACC_REGS", \
2030 "ACC_REGS", \
2031 "FRAME_REGS", \
2032 "GR_AND_MD0_REGS", \
2033 "GR_AND_MD1_REGS", \
2034 "GR_AND_MD_REGS", \
2035 "GR_AND_ACC_REGS", \
2036 "ALL_REGS" \
2037 }
2038
2039 /* An initializer containing the contents of the register classes,
2040 as integers which are bit masks. The Nth integer specifies the
2041 contents of class N. The way the integer MASK is interpreted is
2042 that register R is in the class if `MASK & (1 << R)' is 1.
2043
2044 When the machine has more than 32 registers, an integer does not
2045 suffice. Then the integers are replaced by sub-initializers,
2046 braced groupings containing several integers. Each
2047 sub-initializer must be suitable as an initializer for the type
2048 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2049
2050 #define REG_CLASS_CONTENTS \
2051 { \
2052 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
2053 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
2054 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
2055 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
2056 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
2057 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
2058 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
2059 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
2060 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
2061 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
2062 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
2063 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
2064 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
2065 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
2066 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
2067 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
2068 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
2069 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
2070 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
2071 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
2072 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
2073 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
2074 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
2075 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
2076 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
2077 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
2078 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
2079 }
2080
2081
2082 /* A C expression whose value is a register class containing hard
2083 register REGNO. In general there is more that one such class;
2084 choose a class which is "minimal", meaning that no smaller class
2085 also contains the register. */
2086
2087 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2088
2089 /* A macro whose definition is the name of the class to which a
2090 valid base register must belong. A base register is one used in
2091 an address which is the register value plus a displacement. */
2092
2093 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
2094
2095 /* A macro whose definition is the name of the class to which a
2096 valid index register must belong. An index register is one used
2097 in an address where its value is either multiplied by a scale
2098 factor or added to another register (as well as added to a
2099 displacement). */
2100
2101 #define INDEX_REG_CLASS NO_REGS
2102
2103 /* We generally want to put call-clobbered registers ahead of
2104 call-saved ones. (IRA expects this.) */
2105
2106 #define REG_ALLOC_ORDER \
2107 { /* Accumulator registers. When GPRs and accumulators have equal \
2108 cost, we generally prefer to use accumulators. For example, \
2109 a division of multiplication result is better allocated to LO, \
2110 so that we put the MFLO at the point of use instead of at the \
2111 point of definition. It's also needed if we're to take advantage \
2112 of the extra accumulators available with -mdspr2. In some cases, \
2113 it can also help to reduce register pressure. */ \
2114 64, 65,176,177,178,179,180,181, \
2115 /* Call-clobbered GPRs. */ \
2116 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2117 24, 25, 31, \
2118 /* The global pointer. This is call-clobbered for o32 and o64 \
2119 abicalls, call-saved for n32 and n64 abicalls, and a program \
2120 invariant otherwise. Putting it between the call-clobbered \
2121 and call-saved registers should cope with all eventualities. */ \
2122 28, \
2123 /* Call-saved GPRs. */ \
2124 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2125 /* GPRs that can never be exposed to the register allocator. */ \
2126 0, 26, 27, 29, \
2127 /* Call-clobbered FPRs. */ \
2128 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2129 48, 49, 50, 51, \
2130 /* FPRs that are usually call-saved. The odd ones are actually \
2131 call-clobbered for n32, but listing them ahead of the even \
2132 registers might encourage the register allocator to fragment \
2133 the available FPR pairs. We need paired FPRs to store long \
2134 doubles, so it isn't clear that using a different order \
2135 for n32 would be a win. */ \
2136 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2137 /* None of the remaining classes have defined call-saved \
2138 registers. */ \
2139 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2140 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2141 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2142 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2143 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2144 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2145 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2146 182,183,184,185,186,187 \
2147 }
2148
2149 /* True if VALUE is an unsigned 6-bit number. */
2150
2151 #define UIMM6_OPERAND(VALUE) \
2152 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2153
2154 /* True if VALUE is a signed 10-bit number. */
2155
2156 #define IMM10_OPERAND(VALUE) \
2157 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2158
2159 /* True if VALUE is a signed 16-bit number. */
2160
2161 #define SMALL_OPERAND(VALUE) \
2162 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2163
2164 /* True if VALUE is an unsigned 16-bit number. */
2165
2166 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2167 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2168
2169 /* True if VALUE can be loaded into a register using LUI. */
2170
2171 #define LUI_OPERAND(VALUE) \
2172 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2173 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2174
2175 /* Return a value X with the low 16 bits clear, and such that
2176 VALUE - X is a signed 16-bit value. */
2177
2178 #define CONST_HIGH_PART(VALUE) \
2179 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2180
2181 #define CONST_LOW_PART(VALUE) \
2182 ((VALUE) - CONST_HIGH_PART (VALUE))
2183
2184 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2185 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2186 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2187 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2188 #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255))
2189
2190 /* The HI and LO registers can only be reloaded via the general
2191 registers. Condition code registers can only be loaded to the
2192 general registers, and from the floating point registers. */
2193
2194 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2195 mips_secondary_reload_class (CLASS, MODE, X, true)
2196 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2197 mips_secondary_reload_class (CLASS, MODE, X, false)
2198
2199 /* When targeting the o32 FPXX ABI, all moves with a length of doubleword
2200 or greater must be performed by FR-mode-aware instructions.
2201 This can be achieved using MFHC1/MTHC1 when these instructions are
2202 available but otherwise moves must go via memory.
2203 For the o32 FP64A ABI, all odd-numbered moves with a length of
2204 doubleword or greater are required to use memory. Using MTC1/MFC1
2205 to access the lower-half of these registers would require a forbidden
2206 single-precision access. We require all double-word moves to use
2207 memory because adding even and odd floating-point registers classes
2208 would have a significant impact on the backend. */
2209 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2210 mips_secondary_memory_needed ((CLASS1), (CLASS2), (MODE))
2211
2212 /* Return the maximum number of consecutive registers
2213 needed to represent mode MODE in a register of class CLASS. */
2214
2215 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2216
2217 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2218 mips_cannot_change_mode_class (FROM, TO, CLASS)
2219 \f
2220 /* Stack layout; function entry, exit and calling. */
2221
2222 #define STACK_GROWS_DOWNWARD
2223
2224 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2225
2226 /* Size of the area allocated in the frame to save the GP. */
2227
2228 #define MIPS_GP_SAVE_AREA_SIZE \
2229 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2230
2231 /* The offset of the first local variable from the frame pointer. See
2232 mips_compute_frame_info for details about the frame layout. */
2233
2234 #define STARTING_FRAME_OFFSET \
2235 (FRAME_GROWS_DOWNWARD \
2236 ? 0 \
2237 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2238
2239 #define RETURN_ADDR_RTX mips_return_addr
2240
2241 /* Mask off the MIPS16 ISA bit in unwind addresses.
2242
2243 The reason for this is a little subtle. When unwinding a call,
2244 we are given the call's return address, which on most targets
2245 is the address of the following instruction. However, what we
2246 actually want to find is the EH region for the call itself.
2247 The target-independent unwind code therefore searches for "RA - 1".
2248
2249 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2250 RA - 1 is therefore the real (even-valued) start of the return
2251 instruction. EH region labels are usually odd-valued MIPS16 symbols
2252 too, so a search for an even address within a MIPS16 region would
2253 usually work.
2254
2255 However, there is an exception. If the end of an EH region is also
2256 the end of a function, the end label is allowed to be even. This is
2257 necessary because a following non-MIPS16 function may also need EH
2258 information for its first instruction.
2259
2260 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2261 non-ISA-encoded address. This probably isn't ideal, but it is
2262 the traditional (legacy) behavior. It is therefore only safe
2263 to search MIPS EH regions for an _odd-valued_ address.
2264
2265 Masking off the ISA bit means that the target-independent code
2266 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2267 #define MASK_RETURN_ADDR GEN_INT (-2)
2268
2269
2270 /* Similarly, don't use the least-significant bit to tell pointers to
2271 code from vtable index. */
2272
2273 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2274
2275 /* The eliminations to $17 are only used for mips16 code. See the
2276 definition of HARD_FRAME_POINTER_REGNUM. */
2277
2278 #define ELIMINABLE_REGS \
2279 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2280 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2281 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2282 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2283 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2284 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2285
2286 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2287 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2288
2289 /* Allocate stack space for arguments at the beginning of each function. */
2290 #define ACCUMULATE_OUTGOING_ARGS 1
2291
2292 /* The argument pointer always points to the first argument. */
2293 #define FIRST_PARM_OFFSET(FNDECL) 0
2294
2295 /* o32 and o64 reserve stack space for all argument registers. */
2296 #define REG_PARM_STACK_SPACE(FNDECL) \
2297 (TARGET_OLDABI \
2298 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2299 : 0)
2300
2301 /* Define this if it is the responsibility of the caller to
2302 allocate the area reserved for arguments passed in registers.
2303 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2304 of this macro is to determine whether the space is included in
2305 `crtl->outgoing_args_size'. */
2306 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2307
2308 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2309 \f
2310 /* Symbolic macros for the registers used to return integer and floating
2311 point values. */
2312
2313 #define GP_RETURN (GP_REG_FIRST + 2)
2314 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2315
2316 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2317
2318 /* Symbolic macros for the first/last argument registers. */
2319
2320 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2321 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2322 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2323 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2324
2325 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2326 are used for returning complex double values in soft-float code, so $6 is the
2327 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2328 $gp itself as the temporary. */
2329 #define POST_CALL_TMP_REG \
2330 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2331
2332 /* 1 if N is a possible register number for function argument passing.
2333 We have no FP argument registers when soft-float. Special handling
2334 is required for O32 where only even numbered registers are used for
2335 O32-FPXX and O32-FP64. */
2336
2337 #define FUNCTION_ARG_REGNO_P(N) \
2338 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2339 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2340 && (mips_abi != ABI_32 \
2341 || TARGET_FLOAT32 \
2342 || ((N) % 2 == 0)))) \
2343 && !fixed_regs[N])
2344 \f
2345 /* This structure has to cope with two different argument allocation
2346 schemes. Most MIPS ABIs view the arguments as a structure, of which
2347 the first N words go in registers and the rest go on the stack. If I
2348 < N, the Ith word might go in Ith integer argument register or in a
2349 floating-point register. For these ABIs, we only need to remember
2350 the offset of the current argument into the structure.
2351
2352 The EABI instead allocates the integer and floating-point arguments
2353 separately. The first N words of FP arguments go in FP registers,
2354 the rest go on the stack. Likewise, the first N words of the other
2355 arguments go in integer registers, and the rest go on the stack. We
2356 need to maintain three counts: the number of integer registers used,
2357 the number of floating-point registers used, and the number of words
2358 passed on the stack.
2359
2360 We could keep separate information for the two ABIs (a word count for
2361 the standard ABIs, and three separate counts for the EABI). But it
2362 seems simpler to view the standard ABIs as forms of EABI that do not
2363 allocate floating-point registers.
2364
2365 So for the standard ABIs, the first N words are allocated to integer
2366 registers, and mips_function_arg decides on an argument-by-argument
2367 basis whether that argument should really go in an integer register,
2368 or in a floating-point one. */
2369
2370 typedef struct mips_args {
2371 /* Always true for varargs functions. Otherwise true if at least
2372 one argument has been passed in an integer register. */
2373 int gp_reg_found;
2374
2375 /* The number of arguments seen so far. */
2376 unsigned int arg_number;
2377
2378 /* The number of integer registers used so far. For all ABIs except
2379 EABI, this is the number of words that have been added to the
2380 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2381 unsigned int num_gprs;
2382
2383 /* For EABI, the number of floating-point registers used so far. */
2384 unsigned int num_fprs;
2385
2386 /* The number of words passed on the stack. */
2387 unsigned int stack_words;
2388
2389 /* On the mips16, we need to keep track of which floating point
2390 arguments were passed in general registers, but would have been
2391 passed in the FP regs if this were a 32-bit function, so that we
2392 can move them to the FP regs if we wind up calling a 32-bit
2393 function. We record this information in fp_code, encoded in base
2394 four. A zero digit means no floating point argument, a one digit
2395 means an SFmode argument, and a two digit means a DFmode argument,
2396 and a three digit is not used. The low order digit is the first
2397 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2398 an SFmode argument. ??? A more sophisticated approach will be
2399 needed if MIPS_ABI != ABI_32. */
2400 int fp_code;
2401
2402 /* True if the function has a prototype. */
2403 int prototype;
2404 } CUMULATIVE_ARGS;
2405
2406 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2407 for a call to a function whose data type is FNTYPE.
2408 For a library call, FNTYPE is 0. */
2409
2410 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2411 mips_init_cumulative_args (&CUM, FNTYPE)
2412
2413 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2414 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2415
2416 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2417 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2418
2419 /* True if using EABI and varargs can be passed in floating-point
2420 registers. Under these conditions, we need a more complex form
2421 of va_list, which tracks GPR, FPR and stack arguments separately. */
2422 #define EABI_FLOAT_VARARGS_P \
2423 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2424
2425 \f
2426 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2427
2428 /* Treat LOC as a byte offset from the stack pointer and round it up
2429 to the next fully-aligned offset. */
2430 #define MIPS_STACK_ALIGN(LOC) \
2431 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2432
2433 \f
2434 /* Output assembler code to FILE to increment profiler label # LABELNO
2435 for profiling a function entry. */
2436
2437 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2438
2439 /* The profiler preserves all interesting registers, including $31. */
2440 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2441
2442 /* No mips port has ever used the profiler counter word, so don't emit it
2443 or the label for it. */
2444
2445 #define NO_PROFILE_COUNTERS 1
2446
2447 /* Define this macro if the code for function profiling should come
2448 before the function prologue. Normally, the profiling code comes
2449 after. */
2450
2451 /* #define PROFILE_BEFORE_PROLOGUE */
2452
2453 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2454 the stack pointer does not matter. The value is tested only in
2455 functions that have frame pointers.
2456 No definition is equivalent to always zero. */
2457
2458 #define EXIT_IGNORE_STACK 1
2459
2460 \f
2461 /* Trampolines are a block of code followed by two pointers. */
2462
2463 #define TRAMPOLINE_SIZE \
2464 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2465
2466 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2467 pointers from a single LUI base. */
2468
2469 #define TRAMPOLINE_ALIGNMENT 64
2470
2471 /* mips_trampoline_init calls this library function to flush
2472 program and data caches. */
2473
2474 #ifndef CACHE_FLUSH_FUNC
2475 #define CACHE_FLUSH_FUNC "_flush_cache"
2476 #endif
2477
2478 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2479 /* Flush both caches. We need to flush the data cache in case \
2480 the system has a write-back cache. */ \
2481 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2482 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2483 GEN_INT (3), TYPE_MODE (integer_type_node))
2484
2485 \f
2486 /* Addressing modes, and classification of registers for them. */
2487
2488 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2489 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2490 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2491 \f
2492 /* Maximum number of registers that can appear in a valid memory address. */
2493
2494 #define MAX_REGS_PER_ADDRESS 1
2495
2496 /* Check for constness inline but use mips_legitimate_address_p
2497 to check whether a constant really is an address. */
2498
2499 #define CONSTANT_ADDRESS_P(X) \
2500 (CONSTANT_P (X) && memory_address_p (SImode, X))
2501
2502 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2503 'the start of the function that this code is output in'. */
2504
2505 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2506 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2507 asm_fprintf ((FILE), "%U%s", \
2508 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2509 else \
2510 asm_fprintf ((FILE), "%U%s", (NAME))
2511 \f
2512 /* Flag to mark a function decl symbol that requires a long call. */
2513 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2514 #define SYMBOL_REF_LONG_CALL_P(X) \
2515 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2516
2517 /* This flag marks functions that cannot be lazily bound. */
2518 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2519 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2520 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2521
2522 /* True if we're generating a form of MIPS16 code in which jump tables
2523 are stored in the text section and encoded as 16-bit PC-relative
2524 offsets. This is only possible when general text loads are allowed,
2525 since the table access itself will be an "lh" instruction. If the
2526 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2527 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2528
2529 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2530
2531 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2532
2533 /* Only use short offsets if their range will not overflow. */
2534 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2535 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2536 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2537 : SImode)
2538
2539 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2540
2541 /* Define this as 1 if `char' should by default be signed; else as 0. */
2542 #ifndef DEFAULT_SIGNED_CHAR
2543 #define DEFAULT_SIGNED_CHAR 1
2544 #endif
2545
2546 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2547 we generally don't want to use them for copying arbitrary data.
2548 A single N-word move is usually the same cost as N single-word moves. */
2549 #define MOVE_MAX UNITS_PER_WORD
2550 #define MAX_MOVE_MAX 8
2551
2552 /* Define this macro as a C expression which is nonzero if
2553 accessing less than a word of memory (i.e. a `char' or a
2554 `short') is no faster than accessing a word of memory, i.e., if
2555 such access require more than one instruction or if there is no
2556 difference in cost between byte and (aligned) word loads.
2557
2558 On RISC machines, it tends to generate better code to define
2559 this as 1, since it avoids making a QI or HI mode register.
2560
2561 But, generating word accesses for -mips16 is generally bad as shifts
2562 (often extended) would be needed for byte accesses. */
2563 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2564
2565 /* Standard MIPS integer shifts truncate the shift amount to the
2566 width of the shifted operand. However, Loongson vector shifts
2567 do not truncate the shift amount at all. */
2568 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2569
2570 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2571 is done just by pretending it is already truncated. */
2572 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2573 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2574
2575
2576 /* Specify the machine mode that pointers have.
2577 After generation of rtl, the compiler makes no further distinction
2578 between pointers and any other objects of this machine mode. */
2579
2580 #ifndef Pmode
2581 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2582 #endif
2583
2584 /* Give call MEMs SImode since it is the "most permissive" mode
2585 for both 32-bit and 64-bit targets. */
2586
2587 #define FUNCTION_MODE SImode
2588
2589 \f
2590 /* We allocate $fcc registers by hand and can't cope with moves of
2591 CCmode registers to and from pseudos (or memory). */
2592 #define AVOID_CCMODE_COPIES
2593
2594 /* A C expression for the cost of a branch instruction. A value of
2595 1 is the default; other values are interpreted relative to that. */
2596
2597 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2598 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2599
2600 /* The MIPS port has several functions that return an instruction count.
2601 Multiplying the count by this value gives the number of bytes that
2602 the instructions occupy. */
2603 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2604
2605 /* The length of a NOP in bytes. */
2606 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2607
2608 /* If defined, modifies the length assigned to instruction INSN as a
2609 function of the context in which it is used. LENGTH is an lvalue
2610 that contains the initially computed length of the insn and should
2611 be updated with the correct length of the insn. */
2612 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2613 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2614
2615 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2616 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2617 its operands. */
2618 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2619 "%*" OPCODE "%?\t" OPERANDS "%/"
2620
2621 /* Return an asm string that forces INSN to be treated as an absolute
2622 J or JAL instruction instead of an assembler macro. */
2623 #define MIPS_ABSOLUTE_JUMP(INSN) \
2624 (TARGET_ABICALLS_PIC2 \
2625 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2626 : INSN)
2627
2628 /* Return the asm template for a call. INSN is the instruction's mnemonic
2629 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2630 number of the target. SIZE_OPNO is the operand number of the argument size
2631 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2632 -1 and the call is indirect, use the function symbol from the call
2633 attributes to attach a R_MIPS_JALR relocation to the call.
2634
2635 When generating GOT code without explicit relocation operators,
2636 all calls should use assembly macros. Otherwise, all indirect
2637 calls should use "jr" or "jalr"; we will arrange to restore $gp
2638 afterwards if necessary. Finally, we can only generate direct
2639 calls for -mabicalls by temporarily switching to non-PIC mode.
2640
2641 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2642 instruction is in the delay slot of jal(r). */
2643 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2644 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2645 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2646 : REG_P (OPERANDS[TARGET_OPNO]) \
2647 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2648 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2649 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2650 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2651 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2652 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2653 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2654 ? MIPS_ABSOLUTE_JUMP ("%*" INSN "%!\t%" #TARGET_OPNO "%/") \
2655 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/")) \
2656
2657 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2658 "jrc" when nop is in the delay slot of "jr". */
2659
2660 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2661 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2662 ? "%*j\t%" #OPNO "%/" \
2663 : REG_P (OPERANDS[OPNO]) \
2664 ? "%*jr%:\t%" #OPNO \
2665 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2666
2667 \f
2668 /* Control the assembler format that we output. */
2669
2670 /* Output to assembler file text saying following lines
2671 may contain character constants, extra white space, comments, etc. */
2672
2673 #ifndef ASM_APP_ON
2674 #define ASM_APP_ON " #APP\n"
2675 #endif
2676
2677 /* Output to assembler file text saying following lines
2678 no longer contain unusual constructs. */
2679
2680 #ifndef ASM_APP_OFF
2681 #define ASM_APP_OFF " #NO_APP\n"
2682 #endif
2683
2684 #define REGISTER_NAMES \
2685 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2686 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2687 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2688 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2689 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2690 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2691 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2692 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2693 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2694 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2695 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2696 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2697 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2698 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2699 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2700 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2701 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2702 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2703 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2704 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2705 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2706 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2707 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2708 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2709
2710 /* List the "software" names for each register. Also list the numerical
2711 names for $fp and $sp. */
2712
2713 #define ADDITIONAL_REGISTER_NAMES \
2714 { \
2715 { "$29", 29 + GP_REG_FIRST }, \
2716 { "$30", 30 + GP_REG_FIRST }, \
2717 { "at", 1 + GP_REG_FIRST }, \
2718 { "v0", 2 + GP_REG_FIRST }, \
2719 { "v1", 3 + GP_REG_FIRST }, \
2720 { "a0", 4 + GP_REG_FIRST }, \
2721 { "a1", 5 + GP_REG_FIRST }, \
2722 { "a2", 6 + GP_REG_FIRST }, \
2723 { "a3", 7 + GP_REG_FIRST }, \
2724 { "t0", 8 + GP_REG_FIRST }, \
2725 { "t1", 9 + GP_REG_FIRST }, \
2726 { "t2", 10 + GP_REG_FIRST }, \
2727 { "t3", 11 + GP_REG_FIRST }, \
2728 { "t4", 12 + GP_REG_FIRST }, \
2729 { "t5", 13 + GP_REG_FIRST }, \
2730 { "t6", 14 + GP_REG_FIRST }, \
2731 { "t7", 15 + GP_REG_FIRST }, \
2732 { "s0", 16 + GP_REG_FIRST }, \
2733 { "s1", 17 + GP_REG_FIRST }, \
2734 { "s2", 18 + GP_REG_FIRST }, \
2735 { "s3", 19 + GP_REG_FIRST }, \
2736 { "s4", 20 + GP_REG_FIRST }, \
2737 { "s5", 21 + GP_REG_FIRST }, \
2738 { "s6", 22 + GP_REG_FIRST }, \
2739 { "s7", 23 + GP_REG_FIRST }, \
2740 { "t8", 24 + GP_REG_FIRST }, \
2741 { "t9", 25 + GP_REG_FIRST }, \
2742 { "k0", 26 + GP_REG_FIRST }, \
2743 { "k1", 27 + GP_REG_FIRST }, \
2744 { "gp", 28 + GP_REG_FIRST }, \
2745 { "sp", 29 + GP_REG_FIRST }, \
2746 { "fp", 30 + GP_REG_FIRST }, \
2747 { "ra", 31 + GP_REG_FIRST } \
2748 }
2749
2750 #define DBR_OUTPUT_SEQEND(STREAM) \
2751 do \
2752 { \
2753 /* Undo the effect of '%*'. */ \
2754 mips_pop_asm_switch (&mips_nomacro); \
2755 mips_pop_asm_switch (&mips_noreorder); \
2756 /* Emit a blank line after the delay slot for emphasis. */ \
2757 fputs ("\n", STREAM); \
2758 } \
2759 while (0)
2760
2761 /* The MIPS implementation uses some labels for its own purpose. The
2762 following lists what labels are created, and are all formed by the
2763 pattern $L[a-z].*. The machine independent portion of GCC creates
2764 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2765
2766 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2767 $Lb[0-9]+ Begin blocks for MIPS debug support
2768 $Lc[0-9]+ Label for use in s<xx> operation.
2769 $Le[0-9]+ End blocks for MIPS debug support */
2770
2771 #undef ASM_DECLARE_OBJECT_NAME
2772 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2773 mips_declare_object (STREAM, NAME, "", ":\n")
2774
2775 /* Globalizing directive for a label. */
2776 #define GLOBAL_ASM_OP "\t.globl\t"
2777
2778 /* This says how to define a global common symbol. */
2779
2780 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2781
2782 /* This says how to define a local common symbol (i.e., not visible to
2783 linker). */
2784
2785 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2786 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2787 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2788 #endif
2789
2790 /* This says how to output an external. It would be possible not to
2791 output anything and let undefined symbol become external. However
2792 the assembler uses length information on externals to allocate in
2793 data/sdata bss/sbss, thereby saving exec time. */
2794
2795 #undef ASM_OUTPUT_EXTERNAL
2796 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2797 mips_output_external(STREAM,DECL,NAME)
2798
2799 /* This is how to declare a function name. The actual work of
2800 emitting the label is moved to function_prologue, so that we can
2801 get the line number correctly emitted before the .ent directive,
2802 and after any .file directives. Define as empty so that the function
2803 is not declared before the .ent directive elsewhere. */
2804
2805 #undef ASM_DECLARE_FUNCTION_NAME
2806 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2807
2808 /* This is how to store into the string LABEL
2809 the symbol_ref name of an internal numbered label where
2810 PREFIX is the class of label and NUM is the number within the class.
2811 This is suitable for output with `assemble_name'. */
2812
2813 #undef ASM_GENERATE_INTERNAL_LABEL
2814 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2815 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2816
2817 /* Print debug labels as "foo = ." rather than "foo:" because they should
2818 represent a byte pointer rather than an ISA-encoded address. This is
2819 particularly important for code like:
2820
2821 $LFBxxx = .
2822 .cfi_startproc
2823 ...
2824 .section .gcc_except_table,...
2825 ...
2826 .uleb128 foo-$LFBxxx
2827
2828 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2829 likewise a byte pointer rather than an ISA-encoded address.
2830
2831 At the time of writing, this hook is not used for the function end
2832 label:
2833
2834 $LFExxx:
2835 .end foo
2836
2837 But this doesn't matter, because GAS doesn't treat a pre-.end label
2838 as a MIPS16 one anyway. */
2839
2840 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2841 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2842
2843 /* This is how to output an element of a case-vector that is absolute. */
2844
2845 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2846 fprintf (STREAM, "\t%s\t%sL%d\n", \
2847 ptr_mode == DImode ? ".dword" : ".word", \
2848 LOCAL_LABEL_PREFIX, \
2849 VALUE)
2850
2851 /* This is how to output an element of a case-vector. We can make the
2852 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2853 is supported. */
2854
2855 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2856 do { \
2857 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2858 { \
2859 if (GET_MODE (BODY) == HImode) \
2860 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2861 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2862 else \
2863 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2864 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2865 } \
2866 else if (TARGET_GPWORD) \
2867 fprintf (STREAM, "\t%s\t%sL%d\n", \
2868 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2869 LOCAL_LABEL_PREFIX, VALUE); \
2870 else if (TARGET_RTP_PIC) \
2871 { \
2872 /* Make the entry relative to the start of the function. */ \
2873 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2874 fprintf (STREAM, "\t%s\t%sL%d-", \
2875 Pmode == DImode ? ".dword" : ".word", \
2876 LOCAL_LABEL_PREFIX, VALUE); \
2877 assemble_name (STREAM, XSTR (fnsym, 0)); \
2878 fprintf (STREAM, "\n"); \
2879 } \
2880 else \
2881 fprintf (STREAM, "\t%s\t%sL%d\n", \
2882 ptr_mode == DImode ? ".dword" : ".word", \
2883 LOCAL_LABEL_PREFIX, VALUE); \
2884 } while (0)
2885
2886 /* This is how to output an assembler line
2887 that says to advance the location counter
2888 to a multiple of 2**LOG bytes. */
2889
2890 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2891 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2892
2893 /* This is how to output an assembler line to advance the location
2894 counter by SIZE bytes. */
2895
2896 #undef ASM_OUTPUT_SKIP
2897 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2898 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2899
2900 /* This is how to output a string. */
2901 #undef ASM_OUTPUT_ASCII
2902 #define ASM_OUTPUT_ASCII mips_output_ascii
2903
2904 \f
2905 /* Default to -G 8 */
2906 #ifndef MIPS_DEFAULT_GVALUE
2907 #define MIPS_DEFAULT_GVALUE 8
2908 #endif
2909
2910 /* Define the strings to put out for each section in the object file. */
2911 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2912 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2913
2914 #undef READONLY_DATA_SECTION_ASM_OP
2915 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2916 \f
2917 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2918 do \
2919 { \
2920 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2921 TARGET_64BIT ? "daddiu" : "addiu", \
2922 reg_names[STACK_POINTER_REGNUM], \
2923 reg_names[STACK_POINTER_REGNUM], \
2924 TARGET_64BIT ? "sd" : "sw", \
2925 reg_names[REGNO], \
2926 reg_names[STACK_POINTER_REGNUM]); \
2927 } \
2928 while (0)
2929
2930 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2931 do \
2932 { \
2933 mips_push_asm_switch (&mips_noreorder); \
2934 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2935 TARGET_64BIT ? "ld" : "lw", \
2936 reg_names[REGNO], \
2937 reg_names[STACK_POINTER_REGNUM], \
2938 TARGET_64BIT ? "daddu" : "addu", \
2939 reg_names[STACK_POINTER_REGNUM], \
2940 reg_names[STACK_POINTER_REGNUM]); \
2941 mips_pop_asm_switch (&mips_noreorder); \
2942 } \
2943 while (0)
2944
2945 /* How to start an assembler comment.
2946 The leading space is important (the mips native assembler requires it). */
2947 #ifndef ASM_COMMENT_START
2948 #define ASM_COMMENT_START " #"
2949 #endif
2950 \f
2951 #undef SIZE_TYPE
2952 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2953
2954 #undef PTRDIFF_TYPE
2955 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2956
2957 /* The maximum number of bytes that can be copied by one iteration of
2958 a movmemsi loop; see mips_block_move_loop. */
2959 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2960 (UNITS_PER_WORD * 4)
2961
2962 /* The maximum number of bytes that can be copied by a straight-line
2963 implementation of movmemsi; see mips_block_move_straight. We want
2964 to make sure that any loop-based implementation will iterate at
2965 least twice. */
2966 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2967 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2968
2969 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2970 values were determined experimentally by benchmarking with CSiBE.
2971 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2972 for o32 where we have to restore $gp afterwards as well as make an
2973 indirect call), but in practice, bumping this up higher for
2974 TARGET_ABICALLS doesn't make much difference to code size. */
2975
2976 #define MIPS_CALL_RATIO 8
2977
2978 /* Any loop-based implementation of movmemsi will have at least
2979 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2980 moves, so allow individual copies of fewer elements.
2981
2982 When movmemsi is not available, use a value approximating
2983 the length of a memcpy call sequence, so that move_by_pieces
2984 will generate inline code if it is shorter than a function call.
2985 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2986 we'll have to generate a load/store pair for each, halve the
2987 value of MIPS_CALL_RATIO to take that into account. */
2988
2989 #define MOVE_RATIO(speed) \
2990 (HAVE_movmemsi \
2991 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2992 : MIPS_CALL_RATIO / 2)
2993
2994 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2995 of the length of a memset call, but use the default otherwise. */
2996
2997 #define CLEAR_RATIO(speed)\
2998 ((speed) ? 15 : MIPS_CALL_RATIO)
2999
3000 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3001 optimizing for size adjust the ratio to account for the overhead of
3002 loading the constant and replicating it across the word. */
3003
3004 #define SET_RATIO(speed) \
3005 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3006 \f
3007 /* Since the bits of the _init and _fini function is spread across
3008 many object files, each potentially with its own GP, we must assume
3009 we need to load our GP. We don't preserve $gp or $ra, since each
3010 init/fini chunk is supposed to initialize $gp, and crti/crtn
3011 already take care of preserving $ra and, when appropriate, $gp. */
3012 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3013 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3014 asm (SECTION_OP "\n\
3015 .set push\n\
3016 .set nomips16\n\
3017 .set noreorder\n\
3018 bal 1f\n\
3019 nop\n\
3020 1: .cpload $31\n\
3021 .set reorder\n\
3022 jal " USER_LABEL_PREFIX #FUNC "\n\
3023 .set pop\n\
3024 " TEXT_SECTION_ASM_OP);
3025 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3026 || (defined _ABI64 && _MIPS_SIM == _ABI64))
3027 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3028 asm (SECTION_OP "\n\
3029 .set push\n\
3030 .set nomips16\n\
3031 .set noreorder\n\
3032 bal 1f\n\
3033 nop\n\
3034 1: .set reorder\n\
3035 .cpsetup $31, $2, 1b\n\
3036 jal " USER_LABEL_PREFIX #FUNC "\n\
3037 .set pop\n\
3038 " TEXT_SECTION_ASM_OP);
3039 #endif
3040
3041 #ifndef HAVE_AS_TLS
3042 #define HAVE_AS_TLS 0
3043 #endif
3044
3045 #ifndef HAVE_AS_NAN
3046 #define HAVE_AS_NAN 0
3047 #endif
3048
3049 #ifndef USED_FOR_TARGET
3050 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3051 struct mips_asm_switch {
3052 /* The FOO in the description above. */
3053 const char *name;
3054
3055 /* The current block nesting level, or 0 if we aren't in a block. */
3056 int nesting_level;
3057 };
3058
3059 extern const enum reg_class mips_regno_to_class[];
3060 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3061 extern const char *current_function_file; /* filename current function is in */
3062 extern int num_source_filenames; /* current .file # */
3063 extern struct mips_asm_switch mips_noreorder;
3064 extern struct mips_asm_switch mips_nomacro;
3065 extern struct mips_asm_switch mips_noat;
3066 extern int mips_dbx_regno[];
3067 extern int mips_dwarf_regno[];
3068 extern bool mips_split_p[];
3069 extern bool mips_split_hi_p[];
3070 extern bool mips_use_pcrel_pool_p[];
3071 extern const char *mips_lo_relocs[];
3072 extern const char *mips_hi_relocs[];
3073 extern enum processor mips_arch; /* which cpu to codegen for */
3074 extern enum processor mips_tune; /* which cpu to schedule for */
3075 extern int mips_isa; /* architectural level */
3076 extern int mips_isa_rev;
3077 extern const struct mips_cpu_info *mips_arch_info;
3078 extern const struct mips_cpu_info *mips_tune_info;
3079 extern unsigned int mips_base_compression_flags;
3080 extern GTY(()) struct target_globals *mips16_globals;
3081 #endif
3082
3083 /* Enable querying of DFA units. */
3084 #define CPU_UNITS_QUERY 1
3085
3086 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3087 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3088
3089 /* As on most targets, we want the .eh_frame section to be read-only where
3090 possible. And as on most targets, this means two things:
3091
3092 (a) Non-locally-binding pointers must have an indirect encoding,
3093 so that the addresses in the .eh_frame section itself become
3094 locally-binding.
3095
3096 (b) A shared library's .eh_frame section must encode locally-binding
3097 pointers in a relative (relocation-free) form.
3098
3099 However, MIPS has traditionally not allowed directives like:
3100
3101 .long x-.
3102
3103 in cases where "x" is in a different section, or is not defined in the
3104 same assembly file. We are therefore unable to emit the PC-relative
3105 form required by (b) at assembly time.
3106
3107 Fortunately, the linker is able to convert absolute addresses into
3108 PC-relative addresses on our behalf. Unfortunately, only certain
3109 versions of the linker know how to do this for indirect pointers,
3110 and for personality data. We must fall back on using writable
3111 .eh_frame sections for shared libraries if the linker does not
3112 support this feature. */
3113 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3114 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3115
3116 /* For switching between MIPS16 and non-MIPS16 modes. */
3117 #define SWITCHABLE_TARGET 1
3118
3119 /* Several named MIPS patterns depend on Pmode. These patterns have the
3120 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3121 Add the appropriate suffix to generator function NAME and invoke it
3122 with arguments ARGS. */
3123 #define PMODE_INSN(NAME, ARGS) \
3124 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
3125
3126 /* If we are *not* using multilibs and the default ABI is not ABI_32 we
3127 need to change these from /lib and /usr/lib. */
3128 #if MIPS_ABI_DEFAULT == ABI_N32
3129 #define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
3130 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
3131 #elif MIPS_ABI_DEFAULT == ABI_64
3132 #define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
3133 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
3134 #endif