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config.gcc: Removed mips-sgi-irix5*, mips-sgi-irix6.[0-4]* from list of obsolete...
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF2_1,
45 PROCESSOR_24KF1_1,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF2_1,
48 PROCESSOR_74KF1_1,
49 PROCESSOR_74KF3_2,
50 PROCESSOR_LOONGSON_2E,
51 PROCESSOR_LOONGSON_2F,
52 PROCESSOR_M4K,
53 PROCESSOR_OCTEON,
54 PROCESSOR_R3900,
55 PROCESSOR_R6000,
56 PROCESSOR_R4000,
57 PROCESSOR_R4100,
58 PROCESSOR_R4111,
59 PROCESSOR_R4120,
60 PROCESSOR_R4130,
61 PROCESSOR_R4300,
62 PROCESSOR_R4600,
63 PROCESSOR_R4650,
64 PROCESSOR_R5000,
65 PROCESSOR_R5400,
66 PROCESSOR_R5500,
67 PROCESSOR_R7000,
68 PROCESSOR_R8000,
69 PROCESSOR_R9000,
70 PROCESSOR_R10000,
71 PROCESSOR_SB1,
72 PROCESSOR_SB1A,
73 PROCESSOR_SR71000,
74 PROCESSOR_XLR,
75 PROCESSOR_MAX
76 };
77
78 /* Costs of various operations on the different architectures. */
79
80 struct mips_rtx_cost_data
81 {
82 unsigned short fp_add;
83 unsigned short fp_mult_sf;
84 unsigned short fp_mult_df;
85 unsigned short fp_div_sf;
86 unsigned short fp_div_df;
87 unsigned short int_mult_si;
88 unsigned short int_mult_di;
89 unsigned short int_div_si;
90 unsigned short int_div_di;
91 unsigned short branch_cost;
92 unsigned short memory_latency;
93 };
94
95 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
96 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
97 to work on a 64-bit machine. */
98
99 #define ABI_32 0
100 #define ABI_N32 1
101 #define ABI_64 2
102 #define ABI_EABI 3
103 #define ABI_O64 4
104
105 /* Masks that affect tuning.
106
107 PTF_AVOID_BRANCHLIKELY
108 Set if it is usually not profitable to use branch-likely instructions
109 for this target, typically because the branches are always predicted
110 taken and so incur a large overhead when not taken. */
111 #define PTF_AVOID_BRANCHLIKELY 0x1
112
113 /* Information about one recognized processor. Defined here for the
114 benefit of TARGET_CPU_CPP_BUILTINS. */
115 struct mips_cpu_info {
116 /* The 'canonical' name of the processor as far as GCC is concerned.
117 It's typically a manufacturer's prefix followed by a numerical
118 designation. It should be lowercase. */
119 const char *name;
120
121 /* The internal processor number that most closely matches this
122 entry. Several processors can have the same value, if there's no
123 difference between them from GCC's point of view. */
124 enum processor_type cpu;
125
126 /* The ISA level that the processor implements. */
127 int isa;
128
129 /* A mask of PTF_* values. */
130 unsigned int tune_flags;
131 };
132
133 /* Enumerates the setting of the -mcode-readable option. */
134 enum mips_code_readable_setting {
135 CODE_READABLE_NO,
136 CODE_READABLE_PCREL,
137 CODE_READABLE_YES
138 };
139
140 /* Macros to silence warnings about numbers being signed in traditional
141 C and unsigned in ISO C when compiled on 32-bit hosts. */
142
143 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
144 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
145 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
146
147 \f
148 /* Run-time compilation parameters selecting different hardware subsets. */
149
150 /* True if we are generating position-independent VxWorks RTP code. */
151 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
152
153 /* True if the output file is marked as ".abicalls; .option pic0"
154 (-call_nonpic). */
155 #define TARGET_ABICALLS_PIC0 \
156 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
157
158 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
159 #define TARGET_ABICALLS_PIC2 \
160 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
161
162 /* True if the call patterns should be split into a jalr followed by
163 an instruction to restore $gp. It is only safe to split the load
164 from the call when every use of $gp is explicit.
165
166 See mips_must_initialize_gp_p for details about how we manage the
167 global pointer. */
168
169 #define TARGET_SPLIT_CALLS \
170 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
171
172 /* True if we're generating a form of -mabicalls in which we can use
173 operators like %hi and %lo to refer to locally-binding symbols.
174 We can only do this for -mno-shared, and only then if we can use
175 relocation operations instead of assembly macros. It isn't really
176 worth using absolute sequences for 64-bit symbols because GOT
177 accesses are so much shorter. */
178
179 #define TARGET_ABSOLUTE_ABICALLS \
180 (TARGET_ABICALLS \
181 && !TARGET_SHARED \
182 && TARGET_EXPLICIT_RELOCS \
183 && !ABI_HAS_64BIT_SYMBOLS)
184
185 /* True if we can optimize sibling calls. For simplicity, we only
186 handle cases in which call_insn_operand will reject invalid
187 sibcall addresses. There are two cases in which this isn't true:
188
189 - TARGET_MIPS16. call_insn_operand accepts constant addresses
190 but there is no direct jump instruction. It isn't worth
191 using sibling calls in this case anyway; they would usually
192 be longer than normal calls.
193
194 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
195 accepts global constants, but all sibcalls must be indirect. */
196 #define TARGET_SIBCALLS \
197 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
198
199 /* True if we need to use a global offset table to access some symbols. */
200 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
201
202 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
203 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
204
205 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
206 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
207
208 /* True if we should use .cprestore to store to the cprestore slot.
209
210 We continue to use .cprestore for explicit-reloc code so that JALs
211 inside inline asms will work correctly. */
212 #define TARGET_CPRESTORE_DIRECTIVE \
213 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
214
215 /* True if we can use the J and JAL instructions. */
216 #define TARGET_ABSOLUTE_JUMPS \
217 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
218
219 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
220 This is true for both the PIC and non-PIC VxWorks RTP modes. */
221 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
222
223 /* True if .gpword or .gpdword should be used for switch tables.
224
225 Although GAS does understand .gpdword, the SGI linker mishandles
226 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
227 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
228 #define TARGET_GPWORD \
229 (TARGET_ABICALLS \
230 && !TARGET_ABSOLUTE_ABICALLS \
231 && !(mips_abi == ABI_64 && TARGET_IRIX6))
232
233 /* True if the output must have a writable .eh_frame.
234 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
235 #ifdef HAVE_LD_PERSONALITY_RELAXATION
236 #define TARGET_WRITABLE_EH_FRAME 0
237 #else
238 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
239 #endif
240
241 /* Generate mips16 code */
242 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
243 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
244 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
245 /* Generate mips16e register save/restore sequences. */
246 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
247
248 /* True if we're generating a form of MIPS16 code in which general
249 text loads are allowed. */
250 #define TARGET_MIPS16_TEXT_LOADS \
251 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
252
253 /* True if we're generating a form of MIPS16 code in which PC-relative
254 loads are allowed. */
255 #define TARGET_MIPS16_PCREL_LOADS \
256 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
257
258 /* Generic ISA defines. */
259 #define ISA_MIPS1 (mips_isa == 1)
260 #define ISA_MIPS2 (mips_isa == 2)
261 #define ISA_MIPS3 (mips_isa == 3)
262 #define ISA_MIPS4 (mips_isa == 4)
263 #define ISA_MIPS32 (mips_isa == 32)
264 #define ISA_MIPS32R2 (mips_isa == 33)
265 #define ISA_MIPS64 (mips_isa == 64)
266 #define ISA_MIPS64R2 (mips_isa == 65)
267
268 /* Architecture target defines. */
269 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
270 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
271 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
272 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
273 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
274 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
275 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
276 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
277 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
278 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
279 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
280 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
281 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
282 || mips_arch == PROCESSOR_SB1A)
283 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
284
285 /* Scheduling target defines. */
286 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
287 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
288 || mips_tune == PROCESSOR_24KF2_1 \
289 || mips_tune == PROCESSOR_24KF1_1)
290 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
291 || mips_tune == PROCESSOR_74KF2_1 \
292 || mips_tune == PROCESSOR_74KF1_1 \
293 || mips_tune == PROCESSOR_74KF3_2)
294 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
295 || mips_tune == PROCESSOR_LOONGSON_2F)
296 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
297 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
298 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
299 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
300 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
301 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
302 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
303 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
304 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
305 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
306 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
307 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
308 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
309 || mips_tune == PROCESSOR_SB1A)
310
311 /* Whether vector modes and intrinsics for ST Microelectronics
312 Loongson-2E/2F processors should be enabled. In o32 pairs of
313 floating-point registers provide 64-bit values. */
314 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
315 && TARGET_LOONGSON_2EF)
316
317 /* True if the pre-reload scheduler should try to create chains of
318 multiply-add or multiply-subtract instructions. For example,
319 suppose we have:
320
321 t1 = a * b
322 t2 = t1 + c * d
323 t3 = e * f
324 t4 = t3 - g * h
325
326 t1 will have a higher priority than t2 and t3 will have a higher
327 priority than t4. However, before reload, there is no dependence
328 between t1 and t3, and they can often have similar priorities.
329 The scheduler will then tend to prefer:
330
331 t1 = a * b
332 t3 = e * f
333 t2 = t1 + c * d
334 t4 = t3 - g * h
335
336 which stops us from making full use of macc/madd-style instructions.
337 This sort of situation occurs frequently in Fourier transforms and
338 in unrolled loops.
339
340 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
341 queue so that chained multiply-add and multiply-subtract instructions
342 appear ahead of any other instruction that is likely to clobber lo.
343 In the example above, if t2 and t3 become ready at the same time,
344 the code ensures that t2 is scheduled first.
345
346 Multiply-accumulate instructions are a bigger win for some targets
347 than others, so this macro is defined on an opt-in basis. */
348 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
349 || TUNE_MIPS4120 \
350 || TUNE_MIPS4130 \
351 || TUNE_24K)
352
353 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
354 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
355
356 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
357 directly accessible, while the command-line options select
358 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
359 in use. */
360 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
361 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
362
363 /* False if SC acts as a memory barrier with respect to itself,
364 otherwise a SYNC will be emitted after SC for atomic operations
365 that require ordering between the SC and following loads and
366 stores. It does not tell anything about ordering of loads and
367 stores prior to and following the SC, only about the SC itself and
368 those loads and stores follow it. */
369 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
370
371 /* IRIX specific stuff. */
372 #define TARGET_IRIX6 0
373
374 /* Define preprocessor macros for the -march and -mtune options.
375 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
376 processor. If INFO's canonical name is "foo", define PREFIX to
377 be "foo", and define an additional macro PREFIX_FOO. */
378 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
379 do \
380 { \
381 char *macro, *p; \
382 \
383 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
384 for (p = macro; *p != 0; p++) \
385 *p = TOUPPER (*p); \
386 \
387 builtin_define (macro); \
388 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
389 free (macro); \
390 } \
391 while (0)
392
393 /* Target CPU builtins. */
394 #define TARGET_CPU_CPP_BUILTINS() \
395 do \
396 { \
397 /* Everyone but IRIX defines this to mips. */ \
398 if (!TARGET_IRIX6) \
399 builtin_assert ("machine=mips"); \
400 \
401 builtin_assert ("cpu=mips"); \
402 builtin_define ("__mips__"); \
403 builtin_define ("_mips"); \
404 \
405 /* We do this here because __mips is defined below and so we \
406 can't use builtin_define_std. We don't ever want to define \
407 "mips" for VxWorks because some of the VxWorks headers \
408 construct include filenames from a root directory macro, \
409 an architecture macro and a filename, where the architecture \
410 macro expands to 'mips'. If we define 'mips' to 1, the \
411 architecture macro expands to 1 as well. */ \
412 if (!flag_iso && !TARGET_VXWORKS) \
413 builtin_define ("mips"); \
414 \
415 if (TARGET_64BIT) \
416 builtin_define ("__mips64"); \
417 \
418 if (!TARGET_IRIX6) \
419 { \
420 /* Treat _R3000 and _R4000 like register-size \
421 defines, which is how they've historically \
422 been used. */ \
423 if (TARGET_64BIT) \
424 { \
425 builtin_define_std ("R4000"); \
426 builtin_define ("_R4000"); \
427 } \
428 else \
429 { \
430 builtin_define_std ("R3000"); \
431 builtin_define ("_R3000"); \
432 } \
433 } \
434 if (TARGET_FLOAT64) \
435 builtin_define ("__mips_fpr=64"); \
436 else \
437 builtin_define ("__mips_fpr=32"); \
438 \
439 if (mips_base_mips16) \
440 builtin_define ("__mips16"); \
441 \
442 if (TARGET_MIPS3D) \
443 builtin_define ("__mips3d"); \
444 \
445 if (TARGET_SMARTMIPS) \
446 builtin_define ("__mips_smartmips"); \
447 \
448 if (TARGET_DSP) \
449 { \
450 builtin_define ("__mips_dsp"); \
451 if (TARGET_DSPR2) \
452 { \
453 builtin_define ("__mips_dspr2"); \
454 builtin_define ("__mips_dsp_rev=2"); \
455 } \
456 else \
457 builtin_define ("__mips_dsp_rev=1"); \
458 } \
459 \
460 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
461 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
462 \
463 if (ISA_MIPS1) \
464 { \
465 builtin_define ("__mips=1"); \
466 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
467 } \
468 else if (ISA_MIPS2) \
469 { \
470 builtin_define ("__mips=2"); \
471 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
472 } \
473 else if (ISA_MIPS3) \
474 { \
475 builtin_define ("__mips=3"); \
476 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
477 } \
478 else if (ISA_MIPS4) \
479 { \
480 builtin_define ("__mips=4"); \
481 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
482 } \
483 else if (ISA_MIPS32) \
484 { \
485 builtin_define ("__mips=32"); \
486 builtin_define ("__mips_isa_rev=1"); \
487 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
488 } \
489 else if (ISA_MIPS32R2) \
490 { \
491 builtin_define ("__mips=32"); \
492 builtin_define ("__mips_isa_rev=2"); \
493 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
494 } \
495 else if (ISA_MIPS64) \
496 { \
497 builtin_define ("__mips=64"); \
498 builtin_define ("__mips_isa_rev=1"); \
499 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
500 } \
501 else if (ISA_MIPS64R2) \
502 { \
503 builtin_define ("__mips=64"); \
504 builtin_define ("__mips_isa_rev=2"); \
505 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
506 } \
507 \
508 switch (mips_abi) \
509 { \
510 case ABI_32: \
511 builtin_define ("_ABIO32=1"); \
512 builtin_define ("_MIPS_SIM=_ABIO32"); \
513 break; \
514 \
515 case ABI_N32: \
516 builtin_define ("_ABIN32=2"); \
517 builtin_define ("_MIPS_SIM=_ABIN32"); \
518 break; \
519 \
520 case ABI_64: \
521 builtin_define ("_ABI64=3"); \
522 builtin_define ("_MIPS_SIM=_ABI64"); \
523 break; \
524 \
525 case ABI_O64: \
526 builtin_define ("_ABIO64=4"); \
527 builtin_define ("_MIPS_SIM=_ABIO64"); \
528 break; \
529 } \
530 \
531 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
532 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
533 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
534 builtin_define_with_int_value ("_MIPS_FPSET", \
535 32 / MAX_FPRS_PER_FMT); \
536 \
537 /* These defines reflect the ABI in use, not whether the \
538 FPU is directly accessible. */ \
539 if (TARGET_HARD_FLOAT_ABI) \
540 builtin_define ("__mips_hard_float"); \
541 else \
542 builtin_define ("__mips_soft_float"); \
543 \
544 if (TARGET_SINGLE_FLOAT) \
545 builtin_define ("__mips_single_float"); \
546 \
547 if (TARGET_PAIRED_SINGLE_FLOAT) \
548 builtin_define ("__mips_paired_single_float"); \
549 \
550 if (TARGET_BIG_ENDIAN) \
551 { \
552 builtin_define_std ("MIPSEB"); \
553 builtin_define ("_MIPSEB"); \
554 } \
555 else \
556 { \
557 builtin_define_std ("MIPSEL"); \
558 builtin_define ("_MIPSEL"); \
559 } \
560 \
561 /* Whether calls should go through $25. The separate __PIC__ \
562 macro indicates whether abicalls code might use a GOT. */ \
563 if (TARGET_ABICALLS) \
564 builtin_define ("__mips_abicalls"); \
565 \
566 /* Whether Loongson vector modes are enabled. */ \
567 if (TARGET_LOONGSON_VECTORS) \
568 builtin_define ("__mips_loongson_vector_rev"); \
569 \
570 /* Historical Octeon macro. */ \
571 if (TARGET_OCTEON) \
572 builtin_define ("__OCTEON__"); \
573 \
574 /* Macros dependent on the C dialect. */ \
575 if (preprocessing_asm_p ()) \
576 { \
577 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
578 builtin_define ("_LANGUAGE_ASSEMBLY"); \
579 } \
580 else if (c_dialect_cxx ()) \
581 { \
582 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
583 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
584 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
585 } \
586 else \
587 { \
588 builtin_define_std ("LANGUAGE_C"); \
589 builtin_define ("_LANGUAGE_C"); \
590 } \
591 if (c_dialect_objc ()) \
592 { \
593 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
594 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
595 /* Bizarre, but needed at least for Irix. */ \
596 builtin_define_std ("LANGUAGE_C"); \
597 builtin_define ("_LANGUAGE_C"); \
598 } \
599 \
600 if (mips_abi == ABI_EABI) \
601 builtin_define ("__mips_eabi"); \
602 \
603 if (TARGET_CACHE_BUILTIN) \
604 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
605 } \
606 while (0)
607
608 /* Default target_flags if no switches are specified */
609
610 #ifndef TARGET_DEFAULT
611 #define TARGET_DEFAULT 0
612 #endif
613
614 #ifndef TARGET_CPU_DEFAULT
615 #define TARGET_CPU_DEFAULT 0
616 #endif
617
618 #ifndef TARGET_ENDIAN_DEFAULT
619 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
620 #endif
621
622 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
623 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
624 #endif
625
626 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
627 #ifndef MIPS_ISA_DEFAULT
628 #ifndef MIPS_CPU_STRING_DEFAULT
629 #define MIPS_CPU_STRING_DEFAULT "from-abi"
630 #endif
631 #endif
632
633 #ifdef IN_LIBGCC2
634 #undef TARGET_64BIT
635 /* Make this compile time constant for libgcc2 */
636 #ifdef __mips64
637 #define TARGET_64BIT 1
638 #else
639 #define TARGET_64BIT 0
640 #endif
641 #endif /* IN_LIBGCC2 */
642
643 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
644 when compiled with hardware floating point. This is because MIPS16
645 code cannot save and restore the floating-point registers, which is
646 important if in a mixed MIPS16/non-MIPS16 environment. */
647
648 #ifdef IN_LIBGCC2
649 #if __mips_hard_float
650 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
651 #endif
652 #endif /* IN_LIBGCC2 */
653
654 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
655
656 #ifndef MULTILIB_ENDIAN_DEFAULT
657 #if TARGET_ENDIAN_DEFAULT == 0
658 #define MULTILIB_ENDIAN_DEFAULT "EL"
659 #else
660 #define MULTILIB_ENDIAN_DEFAULT "EB"
661 #endif
662 #endif
663
664 #ifndef MULTILIB_ISA_DEFAULT
665 # if MIPS_ISA_DEFAULT == 1
666 # define MULTILIB_ISA_DEFAULT "mips1"
667 # else
668 # if MIPS_ISA_DEFAULT == 2
669 # define MULTILIB_ISA_DEFAULT "mips2"
670 # else
671 # if MIPS_ISA_DEFAULT == 3
672 # define MULTILIB_ISA_DEFAULT "mips3"
673 # else
674 # if MIPS_ISA_DEFAULT == 4
675 # define MULTILIB_ISA_DEFAULT "mips4"
676 # else
677 # if MIPS_ISA_DEFAULT == 32
678 # define MULTILIB_ISA_DEFAULT "mips32"
679 # else
680 # if MIPS_ISA_DEFAULT == 33
681 # define MULTILIB_ISA_DEFAULT "mips32r2"
682 # else
683 # if MIPS_ISA_DEFAULT == 64
684 # define MULTILIB_ISA_DEFAULT "mips64"
685 # else
686 # if MIPS_ISA_DEFAULT == 65
687 # define MULTILIB_ISA_DEFAULT "mips64r2"
688 # else
689 # define MULTILIB_ISA_DEFAULT "mips1"
690 # endif
691 # endif
692 # endif
693 # endif
694 # endif
695 # endif
696 # endif
697 # endif
698 #endif
699
700 #ifndef MIPS_ABI_DEFAULT
701 #define MIPS_ABI_DEFAULT ABI_32
702 #endif
703
704 /* Use the most portable ABI flag for the ASM specs. */
705
706 #if MIPS_ABI_DEFAULT == ABI_32
707 #define MULTILIB_ABI_DEFAULT "mabi=32"
708 #endif
709
710 #if MIPS_ABI_DEFAULT == ABI_O64
711 #define MULTILIB_ABI_DEFAULT "mabi=o64"
712 #endif
713
714 #if MIPS_ABI_DEFAULT == ABI_N32
715 #define MULTILIB_ABI_DEFAULT "mabi=n32"
716 #endif
717
718 #if MIPS_ABI_DEFAULT == ABI_64
719 #define MULTILIB_ABI_DEFAULT "mabi=64"
720 #endif
721
722 #if MIPS_ABI_DEFAULT == ABI_EABI
723 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
724 #endif
725
726 #ifndef MULTILIB_DEFAULTS
727 #define MULTILIB_DEFAULTS \
728 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
729 #endif
730
731 /* We must pass -EL to the linker by default for little endian embedded
732 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
733 linker will default to using big-endian output files. The OUTPUT_FORMAT
734 line must be in the linker script, otherwise -EB/-EL will not work. */
735
736 #ifndef ENDIAN_SPEC
737 #if TARGET_ENDIAN_DEFAULT == 0
738 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
739 #else
740 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
741 #endif
742 #endif
743
744 /* A spec condition that matches all non-mips16 -mips arguments. */
745
746 #define MIPS_ISA_LEVEL_OPTION_SPEC \
747 "mips1|mips2|mips3|mips4|mips32*|mips64*"
748
749 /* A spec condition that matches all non-mips16 architecture arguments. */
750
751 #define MIPS_ARCH_OPTION_SPEC \
752 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
753
754 /* A spec that infers a -mips argument from an -march argument,
755 or injects the default if no architecture is specified. */
756
757 #define MIPS_ISA_LEVEL_SPEC \
758 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
759 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
760 %{march=mips2|march=r6000:-mips2} \
761 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
762 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
763 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
764 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
765 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
766 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
767 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
768 |march=xlr: -mips64} \
769 %{march=mips64r2|march=octeon: -mips64r2} \
770 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
771
772 /* A spec that infers a -mhard-float or -msoft-float setting from an
773 -march argument. Note that soft-float and hard-float code are not
774 link-compatible. */
775
776 #define MIPS_ARCH_FLOAT_SPEC \
777 "%{mhard-float|msoft-float|march=mips*:; \
778 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
779 |march=34kc|march=74kc|march=1004kc|march=5kc \
780 |march=octeon|march=xlr: -msoft-float; \
781 march=*: -mhard-float}"
782
783 /* A spec condition that matches 32-bit options. It only works if
784 MIPS_ISA_LEVEL_SPEC has been applied. */
785
786 #define MIPS_32BIT_OPTION_SPEC \
787 "mips1|mips2|mips32*|mgp32"
788
789 #if MIPS_ABI_DEFAULT == ABI_O64 \
790 || MIPS_ABI_DEFAULT == ABI_N32 \
791 || MIPS_ABI_DEFAULT == ABI_64
792 #define OPT_ARCH64 "mabi=32|mgp32:;"
793 #define OPT_ARCH32 "mabi=32|mgp32"
794 #else
795 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
796 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
797 #endif
798
799 /* Support for a compile-time default CPU, et cetera. The rules are:
800 --with-arch is ignored if -march is specified or a -mips is specified
801 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
802 --with-tune is ignored if -mtune is specified; likewise
803 --with-tune-32 and --with-tune-64.
804 --with-abi is ignored if -mabi is specified.
805 --with-float is ignored if -mhard-float or -msoft-float are
806 specified.
807 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
808 specified. */
809 #define OPTION_DEFAULT_SPECS \
810 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
811 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
812 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
813 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
814 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
815 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
816 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
817 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
818 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
819 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
820 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
821 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
822
823
824 /* A spec that infers the -mdsp setting from an -march argument. */
825 #define BASE_DRIVER_SELF_SPECS \
826 "%{!mno-dsp:%{march=24ke*|march=34k*|march=74k*|march=1004k*: -mdsp}}"
827
828 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
829
830 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
831 && ISA_HAS_COND_TRAP)
832
833 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
834
835 /* True if the ABI can only work with 64-bit integer registers. We
836 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
837 otherwise floating-point registers must also be 64-bit. */
838 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
839
840 /* Likewise for 32-bit regs. */
841 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
842
843 /* True if the file format uses 64-bit symbols. At present, this is
844 only true for n64, which uses 64-bit ELF. */
845 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
846
847 /* True if symbols are 64 bits wide. This is usually determined by
848 the ABI's file format, but it can be overridden by -msym32. Note that
849 overriding the size with -msym32 changes the ABI of relocatable objects,
850 although it doesn't change the ABI of a fully-linked object. */
851 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS && !TARGET_SYM32)
852
853 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
854 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
855 || ISA_MIPS4 \
856 || ISA_MIPS64 \
857 || ISA_MIPS64R2)
858
859 /* ISA has branch likely instructions (e.g. mips2). */
860 /* Disable branchlikely for tx39 until compare rewrite. They haven't
861 been generated up to this point. */
862 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
863
864 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
865 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
866 || TARGET_MIPS5400 \
867 || TARGET_MIPS5500 \
868 || TARGET_MIPS7000 \
869 || TARGET_MIPS9000 \
870 || TARGET_MAD \
871 || ISA_MIPS32 \
872 || ISA_MIPS32R2 \
873 || ISA_MIPS64 \
874 || ISA_MIPS64R2) \
875 && !TARGET_MIPS16)
876
877 /* ISA has a three-operand multiplication instruction. */
878 #define ISA_HAS_DMUL3 (TARGET_64BIT \
879 && TARGET_OCTEON \
880 && !TARGET_MIPS16)
881
882 /* ISA has the floating-point conditional move instructions introduced
883 in mips4. */
884 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
885 || ISA_MIPS32 \
886 || ISA_MIPS32R2 \
887 || ISA_MIPS64 \
888 || ISA_MIPS64R2) \
889 && !TARGET_MIPS5500 \
890 && !TARGET_MIPS16)
891
892 /* ISA has the integer conditional move instructions introduced in mips4 and
893 ST Loongson 2E/2F. */
894 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
895
896 /* ISA has LDC1 and SDC1. */
897 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
898
899 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
900 branch on CC, and move (both FP and non-FP) on CC. */
901 #define ISA_HAS_8CC (ISA_MIPS4 \
902 || ISA_MIPS32 \
903 || ISA_MIPS32R2 \
904 || ISA_MIPS64 \
905 || ISA_MIPS64R2)
906
907 /* This is a catch all for other mips4 instructions: indexed load, the
908 FP madd and msub instructions, and the FP recip and recip sqrt
909 instructions. */
910 #define ISA_HAS_FP4 ((ISA_MIPS4 \
911 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
912 || ISA_MIPS64 \
913 || ISA_MIPS64R2) \
914 && !TARGET_MIPS16)
915
916 /* ISA has paired-single instructions. */
917 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
918
919 /* ISA has conditional trap instructions. */
920 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
921 && !TARGET_MIPS16)
922
923 /* ISA has integer multiply-accumulate instructions, madd and msub. */
924 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
925 || ISA_MIPS32R2 \
926 || ISA_MIPS64 \
927 || ISA_MIPS64R2) \
928 && !TARGET_MIPS16)
929
930 /* Integer multiply-accumulate instructions should be generated. */
931 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
932
933 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
934 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
935
936 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
937 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
938
939 /* ISA has floating-point nmadd and nmsub instructions
940 'd = -((a * b) [+-] c)'. */
941 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
942 ((ISA_MIPS4 \
943 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
944 || ISA_MIPS64 \
945 || ISA_MIPS64R2) \
946 && (!TARGET_MIPS5400 || TARGET_MAD) \
947 && !TARGET_MIPS16)
948
949 /* ISA has floating-point nmadd and nmsub instructions
950 'c = -((a * b) [+-] c)'. */
951 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
952 TARGET_LOONGSON_2EF
953
954 /* ISA has count leading zeroes/ones instruction (not implemented). */
955 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
956 || ISA_MIPS32R2 \
957 || ISA_MIPS64 \
958 || ISA_MIPS64R2) \
959 && !TARGET_MIPS16)
960
961 /* ISA has three operand multiply instructions that put
962 the high part in an accumulator: mulhi or mulhiu. */
963 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
964 || TARGET_MIPS5500 \
965 || TARGET_SR71K) \
966 && !TARGET_MIPS16)
967
968 /* ISA has three operand multiply instructions that
969 negates the result and puts the result in an accumulator. */
970 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
971 || TARGET_MIPS5500 \
972 || TARGET_SR71K) \
973 && !TARGET_MIPS16)
974
975 /* ISA has three operand multiply instructions that subtracts the
976 result from a 4th operand and puts the result in an accumulator. */
977 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
978 || TARGET_MIPS5500 \
979 || TARGET_SR71K) \
980 && !TARGET_MIPS16)
981
982 /* ISA has three operand multiply instructions that the result
983 from a 4th operand and puts the result in an accumulator. */
984 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
985 || TARGET_MIPS4130 \
986 || TARGET_MIPS5400 \
987 || TARGET_MIPS5500 \
988 || TARGET_SR71K) \
989 && !TARGET_MIPS16)
990
991 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
992 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
993 || TARGET_MIPS4130) \
994 && !TARGET_MIPS16)
995
996 /* ISA has the "ror" (rotate right) instructions. */
997 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
998 || ISA_MIPS64R2 \
999 || TARGET_MIPS5400 \
1000 || TARGET_MIPS5500 \
1001 || TARGET_SR71K \
1002 || TARGET_SMARTMIPS) \
1003 && !TARGET_MIPS16)
1004
1005 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1006 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1007 || TARGET_LOONGSON_2EF \
1008 || ISA_MIPS32 \
1009 || ISA_MIPS32R2 \
1010 || ISA_MIPS64 \
1011 || ISA_MIPS64R2) \
1012 && !TARGET_MIPS16)
1013
1014 /* ISA has data indexed prefetch instructions. This controls use of
1015 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1016 (prefx is a cop1x instruction, so can only be used if FP is
1017 enabled.) */
1018 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
1019 || ISA_MIPS32R2 \
1020 || ISA_MIPS64 \
1021 || ISA_MIPS64R2) \
1022 && !TARGET_MIPS16)
1023
1024 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1025 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1026 also requires TARGET_DOUBLE_FLOAT. */
1027 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1028
1029 /* ISA includes the MIPS32r2 seb and seh instructions. */
1030 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
1031 || ISA_MIPS64R2) \
1032 && !TARGET_MIPS16)
1033
1034 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1035 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
1036 || ISA_MIPS64R2) \
1037 && !TARGET_MIPS16)
1038
1039 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1040 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
1041 && (ISA_MIPS32R2 \
1042 || ISA_MIPS64R2))
1043
1044 /* ISA has lwxs instruction (load w/scaled index address. */
1045 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
1046
1047 /* The DSP ASE is available. */
1048 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1049
1050 /* Revision 2 of the DSP ASE is available. */
1051 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1052
1053 /* True if the result of a load is not available to the next instruction.
1054 A nop will then be needed between instructions like "lw $4,..."
1055 and "addiu $4,$4,1". */
1056 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1057 && !TARGET_MIPS3900 \
1058 && !TARGET_MIPS16)
1059
1060 /* Likewise mtc1 and mfc1. */
1061 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1062 && !TARGET_LOONGSON_2EF)
1063
1064 /* Likewise floating-point comparisons. */
1065 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1066 && !TARGET_LOONGSON_2EF)
1067
1068 /* True if mflo and mfhi can be immediately followed by instructions
1069 which write to the HI and LO registers.
1070
1071 According to MIPS specifications, MIPS ISAs I, II, and III need
1072 (at least) two instructions between the reads of HI/LO and
1073 instructions which write them, and later ISAs do not. Contradicting
1074 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1075 the UM for the NEC Vr5000) document needing the instructions between
1076 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1077 MIPS64 and later ISAs to have the interlocks, plus any specific
1078 earlier-ISA CPUs for which CPU documentation declares that the
1079 instructions are really interlocked. */
1080 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1081 || ISA_MIPS32R2 \
1082 || ISA_MIPS64 \
1083 || ISA_MIPS64R2 \
1084 || TARGET_MIPS5500 \
1085 || TARGET_LOONGSON_2EF)
1086
1087 /* ISA includes synci, jr.hb and jalr.hb. */
1088 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1089 || ISA_MIPS64R2) \
1090 && !TARGET_MIPS16)
1091
1092 /* ISA includes sync. */
1093 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1094 #define GENERATE_SYNC \
1095 (target_flags_explicit & MASK_LLSC \
1096 ? TARGET_LLSC && !TARGET_MIPS16 \
1097 : ISA_HAS_SYNC)
1098
1099 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1100 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1101 instructions. */
1102 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1103 #define GENERATE_LL_SC \
1104 (target_flags_explicit & MASK_LLSC \
1105 ? TARGET_LLSC && !TARGET_MIPS16 \
1106 : ISA_HAS_LL_SC)
1107
1108 /* ISA includes the baddu instruction. */
1109 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1110
1111 /* ISA includes the bbit* instructions. */
1112 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1113
1114 /* ISA includes the cins instruction. */
1115 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1116
1117 /* ISA includes the exts instruction. */
1118 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1119
1120 /* ISA includes the seq and sne instructions. */
1121 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1122
1123 /* ISA includes the pop instruction. */
1124 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1125
1126 /* The CACHE instruction is available in non-MIPS16 code. */
1127 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1128
1129 /* The CACHE instruction is available. */
1130 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1131 \f
1132 /* Add -G xx support. */
1133
1134 #undef SWITCH_TAKES_ARG
1135 #define SWITCH_TAKES_ARG(CHAR) \
1136 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1137
1138 #define OVERRIDE_OPTIONS mips_override_options ()
1139
1140 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1141
1142 /* Show we can debug even without a frame pointer. */
1143 #define CAN_DEBUG_WITHOUT_FP
1144 \f
1145 /* Tell collect what flags to pass to nm. */
1146 #ifndef NM_FLAGS
1147 #define NM_FLAGS "-Bn"
1148 #endif
1149
1150 \f
1151 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1152 to the assembler. It may be overridden by subtargets. */
1153 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1154 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1155 %{noasmopt:-O0} \
1156 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1157 #endif
1158
1159 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1160 the assembler. It may be overridden by subtargets.
1161
1162 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1163 COFF debugging info. */
1164
1165 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1166 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1167 %{g} %{g0} %{g1} %{g2} %{g3} \
1168 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1169 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1170 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1171 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1172 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1173 #endif
1174
1175 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1176 overridden by subtargets. */
1177
1178 #ifndef SUBTARGET_ASM_SPEC
1179 #define SUBTARGET_ASM_SPEC ""
1180 #endif
1181
1182 #undef ASM_SPEC
1183 #define ASM_SPEC "\
1184 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1185 %{mips32*} %{mips64*} \
1186 %{mips16} %{mno-mips16:-no-mips16} \
1187 %{mips3d} %{mno-mips3d:-no-mips3d} \
1188 %{mdmx} %{mno-mdmx:-no-mdmx} \
1189 %{mdsp} %{mno-dsp} \
1190 %{mdspr2} %{mno-dspr2} \
1191 %{msmartmips} %{mno-smartmips} \
1192 %{mmt} %{mno-mt} \
1193 %{mfix-vr4120} %{mfix-vr4130} \
1194 %(subtarget_asm_optimizing_spec) \
1195 %(subtarget_asm_debugging_spec) \
1196 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1197 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1198 %{mfp32} %{mfp64} \
1199 %{mshared} %{mno-shared} \
1200 %{msym32} %{mno-sym32} \
1201 %{mtune=*} %{v} \
1202 %(subtarget_asm_spec)"
1203
1204 /* Extra switches sometimes passed to the linker. */
1205 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1206 will interpret it as a -b option. */
1207
1208 #ifndef LINK_SPEC
1209 #define LINK_SPEC "\
1210 %(endian_spec) \
1211 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1212 %{bestGnum} %{shared} %{non_shared}"
1213 #endif /* LINK_SPEC defined */
1214
1215
1216 /* Specs for the compiler proper */
1217
1218 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1219 overridden by subtargets. */
1220 #ifndef SUBTARGET_CC1_SPEC
1221 #define SUBTARGET_CC1_SPEC ""
1222 #endif
1223
1224 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1225
1226 #undef CC1_SPEC
1227 #define CC1_SPEC "\
1228 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1229 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1230 %{save-temps: } \
1231 %(subtarget_cc1_spec)"
1232
1233 /* Preprocessor specs. */
1234
1235 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1236 overridden by subtargets. */
1237 #ifndef SUBTARGET_CPP_SPEC
1238 #define SUBTARGET_CPP_SPEC ""
1239 #endif
1240
1241 #define CPP_SPEC "%(subtarget_cpp_spec)"
1242
1243 /* This macro defines names of additional specifications to put in the specs
1244 that can be used in various specifications like CC1_SPEC. Its definition
1245 is an initializer with a subgrouping for each command option.
1246
1247 Each subgrouping contains a string constant, that defines the
1248 specification name, and a string constant that used by the GCC driver
1249 program.
1250
1251 Do not define this macro if it does not need to do anything. */
1252
1253 #define EXTRA_SPECS \
1254 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1255 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1256 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1257 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1258 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1259 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1260 { "endian_spec", ENDIAN_SPEC }, \
1261 SUBTARGET_EXTRA_SPECS
1262
1263 #ifndef SUBTARGET_EXTRA_SPECS
1264 #define SUBTARGET_EXTRA_SPECS
1265 #endif
1266 \f
1267 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1268 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1269
1270 #ifndef PREFERRED_DEBUGGING_TYPE
1271 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1272 #endif
1273
1274 /* The size of DWARF addresses should be the same as the size of symbols
1275 in the target file format. They shouldn't depend on things like -msym32,
1276 because many DWARF consumers do not allow the mixture of address sizes
1277 that one would then get from linking -msym32 code with -msym64 code.
1278
1279 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1280 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1281 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1282
1283 /* By default, turn on GDB extensions. */
1284 #define DEFAULT_GDB_EXTENSIONS 1
1285
1286 /* Local compiler-generated symbols must have a prefix that the assembler
1287 understands. By default, this is $, although some targets (e.g.,
1288 NetBSD-ELF) need to override this. */
1289
1290 #ifndef LOCAL_LABEL_PREFIX
1291 #define LOCAL_LABEL_PREFIX "$"
1292 #endif
1293
1294 /* By default on the mips, external symbols do not have an underscore
1295 prepended, but some targets (e.g., NetBSD) require this. */
1296
1297 #ifndef USER_LABEL_PREFIX
1298 #define USER_LABEL_PREFIX ""
1299 #endif
1300
1301 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1302 since the length can run past this up to a continuation point. */
1303 #undef DBX_CONTIN_LENGTH
1304 #define DBX_CONTIN_LENGTH 1500
1305
1306 /* How to renumber registers for dbx and gdb. */
1307 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1308
1309 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1310 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1311
1312 /* The DWARF 2 CFA column which tracks the return address. */
1313 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1314
1315 /* Before the prologue, RA lives in r31. */
1316 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1317
1318 /* Describe how we implement __builtin_eh_return. */
1319 #define EH_RETURN_DATA_REGNO(N) \
1320 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1321
1322 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1323
1324 #define EH_USES(N) mips_eh_uses (N)
1325
1326 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1327 The default for this in 64-bit mode is 8, which causes problems with
1328 SFmode register saves. */
1329 #define DWARF_CIE_DATA_ALIGNMENT -4
1330
1331 /* Correct the offset of automatic variables and arguments. Note that
1332 the MIPS debug format wants all automatic variables and arguments
1333 to be in terms of the virtual frame pointer (stack pointer before
1334 any adjustment in the function), while the MIPS 3.0 linker wants
1335 the frame pointer to be the stack pointer after the initial
1336 adjustment. */
1337
1338 #define DEBUGGER_AUTO_OFFSET(X) \
1339 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1340 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1341 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1342 \f
1343 /* Target machine storage layout */
1344
1345 #define BITS_BIG_ENDIAN 0
1346 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1347 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1348
1349 /* Define this to set the endianness to use in libgcc2.c, which can
1350 not depend on target_flags. */
1351 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1352 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1353 #else
1354 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1355 #endif
1356
1357 #define MAX_BITS_PER_WORD 64
1358
1359 /* Width of a word, in units (bytes). */
1360 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1361 #ifndef IN_LIBGCC2
1362 #define MIN_UNITS_PER_WORD 4
1363 #endif
1364
1365 /* For MIPS, width of a floating point register. */
1366 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1367
1368 /* The number of consecutive floating-point registers needed to store the
1369 largest format supported by the FPU. */
1370 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1371
1372 /* The number of consecutive floating-point registers needed to store the
1373 smallest format supported by the FPU. */
1374 #define MIN_FPRS_PER_FMT \
1375 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1376 ? 1 : MAX_FPRS_PER_FMT)
1377
1378 /* The largest size of value that can be held in floating-point
1379 registers and moved with a single instruction. */
1380 #define UNITS_PER_HWFPVALUE \
1381 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1382
1383 /* The largest size of value that can be held in floating-point
1384 registers. */
1385 #define UNITS_PER_FPVALUE \
1386 (TARGET_SOFT_FLOAT_ABI ? 0 \
1387 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1388 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1389
1390 /* The number of bytes in a double. */
1391 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1392
1393 #define UNITS_PER_SIMD_WORD(MODE) \
1394 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1395
1396 /* Set the sizes of the core types. */
1397 #define SHORT_TYPE_SIZE 16
1398 #define INT_TYPE_SIZE 32
1399 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1400 #define LONG_LONG_TYPE_SIZE 64
1401
1402 #define FLOAT_TYPE_SIZE 32
1403 #define DOUBLE_TYPE_SIZE 64
1404 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1405
1406 /* Define the sizes of fixed-point types. */
1407 #define SHORT_FRACT_TYPE_SIZE 8
1408 #define FRACT_TYPE_SIZE 16
1409 #define LONG_FRACT_TYPE_SIZE 32
1410 #define LONG_LONG_FRACT_TYPE_SIZE 64
1411
1412 #define SHORT_ACCUM_TYPE_SIZE 16
1413 #define ACCUM_TYPE_SIZE 32
1414 #define LONG_ACCUM_TYPE_SIZE 64
1415 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1416 doesn't support 128-bit integers for MIPS32 currently. */
1417 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1418
1419 /* long double is not a fixed mode, but the idea is that, if we
1420 support long double, we also want a 128-bit integer type. */
1421 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1422
1423 #ifdef IN_LIBGCC2
1424 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1425 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1426 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1427 # else
1428 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1429 # endif
1430 #endif
1431
1432 /* Width in bits of a pointer. */
1433 #ifndef POINTER_SIZE
1434 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1435 #endif
1436
1437 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1438 #define PARM_BOUNDARY BITS_PER_WORD
1439
1440 /* Allocation boundary (in *bits*) for the code of a function. */
1441 #define FUNCTION_BOUNDARY 32
1442
1443 /* Alignment of field after `int : 0' in a structure. */
1444 #define EMPTY_FIELD_BOUNDARY 32
1445
1446 /* Every structure's size must be a multiple of this. */
1447 /* 8 is observed right on a DECstation and on riscos 4.02. */
1448 #define STRUCTURE_SIZE_BOUNDARY 8
1449
1450 /* There is no point aligning anything to a rounder boundary than this. */
1451 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1452
1453 /* All accesses must be aligned. */
1454 #define STRICT_ALIGNMENT 1
1455
1456 /* Define this if you wish to imitate the way many other C compilers
1457 handle alignment of bitfields and the structures that contain
1458 them.
1459
1460 The behavior is that the type written for a bit-field (`int',
1461 `short', or other integer type) imposes an alignment for the
1462 entire structure, as if the structure really did contain an
1463 ordinary field of that type. In addition, the bit-field is placed
1464 within the structure so that it would fit within such a field,
1465 not crossing a boundary for it.
1466
1467 Thus, on most machines, a bit-field whose type is written as `int'
1468 would not cross a four-byte boundary, and would force four-byte
1469 alignment for the whole structure. (The alignment used may not
1470 be four bytes; it is controlled by the other alignment
1471 parameters.)
1472
1473 If the macro is defined, its definition should be a C expression;
1474 a nonzero value for the expression enables this behavior. */
1475
1476 #define PCC_BITFIELD_TYPE_MATTERS 1
1477
1478 /* If defined, a C expression to compute the alignment given to a
1479 constant that is being placed in memory. CONSTANT is the constant
1480 and ALIGN is the alignment that the object would ordinarily have.
1481 The value of this macro is used instead of that alignment to align
1482 the object.
1483
1484 If this macro is not defined, then ALIGN is used.
1485
1486 The typical use of this macro is to increase alignment for string
1487 constants to be word aligned so that `strcpy' calls that copy
1488 constants can be done inline. */
1489
1490 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1491 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1492 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1493
1494 /* If defined, a C expression to compute the alignment for a static
1495 variable. TYPE is the data type, and ALIGN is the alignment that
1496 the object would ordinarily have. The value of this macro is used
1497 instead of that alignment to align the object.
1498
1499 If this macro is not defined, then ALIGN is used.
1500
1501 One use of this macro is to increase alignment of medium-size
1502 data to make it all fit in fewer cache lines. Another is to
1503 cause character arrays to be word-aligned so that `strcpy' calls
1504 that copy constants to character arrays can be done inline. */
1505
1506 #undef DATA_ALIGNMENT
1507 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1508 ((((ALIGN) < BITS_PER_WORD) \
1509 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1510 || TREE_CODE (TYPE) == UNION_TYPE \
1511 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1512
1513 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1514 character arrays to be word-aligned so that `strcpy' calls that copy
1515 constants to character arrays can be done inline, and 'strcmp' can be
1516 optimised to use word loads. */
1517 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1518 DATA_ALIGNMENT (TYPE, ALIGN)
1519
1520 #define PAD_VARARGS_DOWN \
1521 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1522
1523 /* Define if operations between registers always perform the operation
1524 on the full register even if a narrower mode is specified. */
1525 #define WORD_REGISTER_OPERATIONS
1526
1527 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1528 moves. All other references are zero extended. */
1529 #define LOAD_EXTEND_OP(MODE) \
1530 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1531 ? SIGN_EXTEND : ZERO_EXTEND)
1532
1533 /* Define this macro if it is advisable to hold scalars in registers
1534 in a wider mode than that declared by the program. In such cases,
1535 the value is constrained to be within the bounds of the declared
1536 type, but kept valid in the wider mode. The signedness of the
1537 extension may differ from that of the type. */
1538
1539 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1540 if (GET_MODE_CLASS (MODE) == MODE_INT \
1541 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1542 { \
1543 if ((MODE) == SImode) \
1544 (UNSIGNEDP) = 0; \
1545 (MODE) = Pmode; \
1546 }
1547
1548 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1549 Extensions of pointers to word_mode must be signed. */
1550 #define POINTERS_EXTEND_UNSIGNED false
1551
1552 /* Define if loading short immediate values into registers sign extends. */
1553 #define SHORT_IMMEDIATES_SIGN_EXTEND
1554
1555 /* The [d]clz instructions have the natural values at 0. */
1556
1557 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1558 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1559 \f
1560 /* Standard register usage. */
1561
1562 /* Number of hardware registers. We have:
1563
1564 - 32 integer registers
1565 - 32 floating point registers
1566 - 8 condition code registers
1567 - 2 accumulator registers (hi and lo)
1568 - 32 registers each for coprocessors 0, 2 and 3
1569 - 4 fake registers:
1570 - ARG_POINTER_REGNUM
1571 - FRAME_POINTER_REGNUM
1572 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1573 - CPRESTORE_SLOT_REGNUM
1574 - 2 dummy entries that were used at various times in the past.
1575 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1576 - 6 DSP control registers */
1577
1578 #define FIRST_PSEUDO_REGISTER 188
1579
1580 /* By default, fix the kernel registers ($26 and $27), the global
1581 pointer ($28) and the stack pointer ($29). This can change
1582 depending on the command-line options.
1583
1584 Regarding coprocessor registers: without evidence to the contrary,
1585 it's best to assume that each coprocessor register has a unique
1586 use. This can be overridden, in, e.g., mips_override_options or
1587 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1588 for a particular target. */
1589
1590 #define FIXED_REGISTERS \
1591 { \
1592 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1596 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1597 /* COP0 registers */ \
1598 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1599 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1600 /* COP2 registers */ \
1601 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1602 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1603 /* COP3 registers */ \
1604 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1605 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1606 /* 6 DSP accumulator registers & 6 control registers */ \
1607 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1608 }
1609
1610
1611 /* Set up this array for o32 by default.
1612
1613 Note that we don't mark $31 as a call-clobbered register. The idea is
1614 that it's really the call instructions themselves which clobber $31.
1615 We don't care what the called function does with it afterwards.
1616
1617 This approach makes it easier to implement sibcalls. Unlike normal
1618 calls, sibcalls don't clobber $31, so the register reaches the
1619 called function in tact. EPILOGUE_USES says that $31 is useful
1620 to the called function. */
1621
1622 #define CALL_USED_REGISTERS \
1623 { \
1624 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1625 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1626 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1627 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1628 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1629 /* COP0 registers */ \
1630 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1631 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1632 /* COP2 registers */ \
1633 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1634 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1635 /* COP3 registers */ \
1636 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1637 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1638 /* 6 DSP accumulator registers & 6 control registers */ \
1639 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1640 }
1641
1642
1643 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1644
1645 #define CALL_REALLY_USED_REGISTERS \
1646 { /* General registers. */ \
1647 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1648 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1649 /* Floating-point registers. */ \
1650 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1651 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1652 /* Others. */ \
1653 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1654 /* COP0 registers */ \
1655 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1656 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1657 /* COP2 registers */ \
1658 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1659 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1660 /* COP3 registers */ \
1661 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1662 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1663 /* 6 DSP accumulator registers & 6 control registers */ \
1664 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1665 }
1666
1667 /* Internal macros to classify a register number as to whether it's a
1668 general purpose register, a floating point register, a
1669 multiply/divide register, or a status register. */
1670
1671 #define GP_REG_FIRST 0
1672 #define GP_REG_LAST 31
1673 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1674 #define GP_DBX_FIRST 0
1675 #define K0_REG_NUM (GP_REG_FIRST + 26)
1676 #define K1_REG_NUM (GP_REG_FIRST + 27)
1677 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1678
1679 #define FP_REG_FIRST 32
1680 #define FP_REG_LAST 63
1681 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1682 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1683
1684 #define MD_REG_FIRST 64
1685 #define MD_REG_LAST 65
1686 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1687 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1688
1689 /* The DWARF 2 CFA column which tracks the return address from a
1690 signal handler context. This means that to maintain backwards
1691 compatibility, no hard register can be assigned this column if it
1692 would need to be handled by the DWARF unwinder. */
1693 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1694
1695 #define ST_REG_FIRST 67
1696 #define ST_REG_LAST 74
1697 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1698
1699
1700 /* FIXME: renumber. */
1701 #define COP0_REG_FIRST 80
1702 #define COP0_REG_LAST 111
1703 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1704
1705 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1706 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1707 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1708
1709 #define COP2_REG_FIRST 112
1710 #define COP2_REG_LAST 143
1711 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1712
1713 #define COP3_REG_FIRST 144
1714 #define COP3_REG_LAST 175
1715 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1716 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1717 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1718
1719 #define DSP_ACC_REG_FIRST 176
1720 #define DSP_ACC_REG_LAST 181
1721 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1722
1723 #define AT_REGNUM (GP_REG_FIRST + 1)
1724 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1725 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1726
1727 /* A few bitfield locations for the coprocessor registers. */
1728 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1729 the cause register for the EIC interrupt mode. */
1730 #define CAUSE_IPL 10
1731 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1732 #define SR_IPL 10
1733 /* Exception Level is at bit 1 of the status register. */
1734 #define SR_EXL 1
1735 /* Interrupt Enable is at bit 0 of the status register. */
1736 #define SR_IE 0
1737
1738 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1739 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1740 should be used instead. */
1741 #define FPSW_REGNUM ST_REG_FIRST
1742
1743 #define GP_REG_P(REGNO) \
1744 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1745 #define M16_REG_P(REGNO) \
1746 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1747 #define FP_REG_P(REGNO) \
1748 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1749 #define MD_REG_P(REGNO) \
1750 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1751 #define ST_REG_P(REGNO) \
1752 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1753 #define COP0_REG_P(REGNO) \
1754 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1755 #define COP2_REG_P(REGNO) \
1756 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1757 #define COP3_REG_P(REGNO) \
1758 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1759 #define ALL_COP_REG_P(REGNO) \
1760 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1761 /* Test if REGNO is one of the 6 new DSP accumulators. */
1762 #define DSP_ACC_REG_P(REGNO) \
1763 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1764 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1765 #define ACC_REG_P(REGNO) \
1766 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1767
1768 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1769
1770 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1771 to initialize the mips16 gp pseudo register. */
1772 #define CONST_GP_P(X) \
1773 (GET_CODE (X) == CONST \
1774 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1775 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1776
1777 /* Return coprocessor number from register number. */
1778
1779 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1780 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1781 : COP3_REG_P (REGNO) ? '3' : '?')
1782
1783
1784 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1785
1786 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1787 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1788
1789 #define MODES_TIEABLE_P mips_modes_tieable_p
1790
1791 /* Register to use for pushing function arguments. */
1792 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1793
1794 /* These two registers don't really exist: they get eliminated to either
1795 the stack or hard frame pointer. */
1796 #define ARG_POINTER_REGNUM 77
1797 #define FRAME_POINTER_REGNUM 78
1798
1799 /* $30 is not available on the mips16, so we use $17 as the frame
1800 pointer. */
1801 #define HARD_FRAME_POINTER_REGNUM \
1802 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1803
1804 /* Register in which static-chain is passed to a function. */
1805 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1806
1807 /* Registers used as temporaries in prologue/epilogue code:
1808
1809 - If a MIPS16 PIC function needs access to _gp, it first loads
1810 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1811
1812 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1813 register. The register must not conflict with MIPS16_PIC_TEMP.
1814
1815 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1816 register.
1817
1818 If we're generating MIPS16 code, these registers must come from the
1819 core set of 8. The prologue registers mustn't conflict with any
1820 incoming arguments, the static chain pointer, or the frame pointer.
1821 The epilogue temporary mustn't conflict with the return registers,
1822 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1823 or the EH data registers.
1824
1825 If we're generating interrupt handlers, we use K0 as a temporary register
1826 in prologue/epilogue code. */
1827
1828 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1829 #define MIPS_PROLOGUE_TEMP_REGNUM \
1830 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1831 #define MIPS_EPILOGUE_TEMP_REGNUM \
1832 (cfun->machine->interrupt_handler_p \
1833 ? K0_REG_NUM \
1834 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1835
1836 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1837 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1838 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1839
1840 /* Define this macro if it is as good or better to call a constant
1841 function address than to call an address kept in a register. */
1842 #define NO_FUNCTION_CSE 1
1843
1844 /* The ABI-defined global pointer. Sometimes we use a different
1845 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1846 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1847
1848 /* We normally use $28 as the global pointer. However, when generating
1849 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1850 register instead. They can then avoid saving and restoring $28
1851 and perhaps avoid using a frame at all.
1852
1853 When a leaf function uses something other than $28, mips_expand_prologue
1854 will modify pic_offset_table_rtx in place. Take the register number
1855 from there after reload. */
1856 #define PIC_OFFSET_TABLE_REGNUM \
1857 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1858
1859 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1860 \f
1861 /* Define the classes of registers for register constraints in the
1862 machine description. Also define ranges of constants.
1863
1864 One of the classes must always be named ALL_REGS and include all hard regs.
1865 If there is more than one class, another class must be named NO_REGS
1866 and contain no registers.
1867
1868 The name GENERAL_REGS must be the name of a class (or an alias for
1869 another name such as ALL_REGS). This is the class of registers
1870 that is allowed by "g" or "r" in a register constraint.
1871 Also, registers outside this class are allocated only when
1872 instructions express preferences for them.
1873
1874 The classes must be numbered in nondecreasing order; that is,
1875 a larger-numbered class must never be contained completely
1876 in a smaller-numbered class.
1877
1878 For any two classes, it is very desirable that there be another
1879 class that represents their union. */
1880
1881 enum reg_class
1882 {
1883 NO_REGS, /* no registers in set */
1884 M16_REGS, /* mips16 directly accessible registers */
1885 T_REG, /* mips16 T register ($24) */
1886 M16_T_REGS, /* mips16 registers plus T register */
1887 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1888 V1_REG, /* Register $v1 ($3) used for TLS access. */
1889 LEA_REGS, /* Every GPR except $25 */
1890 GR_REGS, /* integer registers */
1891 FP_REGS, /* floating point registers */
1892 MD0_REG, /* first multiply/divide register */
1893 MD1_REG, /* second multiply/divide register */
1894 MD_REGS, /* multiply/divide registers (hi/lo) */
1895 COP0_REGS, /* generic coprocessor classes */
1896 COP2_REGS,
1897 COP3_REGS,
1898 ST_REGS, /* status registers (fp status) */
1899 DSP_ACC_REGS, /* DSP accumulator registers */
1900 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1901 FRAME_REGS, /* $arg and $frame */
1902 GR_AND_MD0_REGS, /* union classes */
1903 GR_AND_MD1_REGS,
1904 GR_AND_MD_REGS,
1905 GR_AND_ACC_REGS,
1906 ALL_REGS, /* all registers */
1907 LIM_REG_CLASSES /* max value + 1 */
1908 };
1909
1910 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1911
1912 #define GENERAL_REGS GR_REGS
1913
1914 /* An initializer containing the names of the register classes as C
1915 string constants. These names are used in writing some of the
1916 debugging dumps. */
1917
1918 #define REG_CLASS_NAMES \
1919 { \
1920 "NO_REGS", \
1921 "M16_REGS", \
1922 "T_REG", \
1923 "M16_T_REGS", \
1924 "PIC_FN_ADDR_REG", \
1925 "V1_REG", \
1926 "LEA_REGS", \
1927 "GR_REGS", \
1928 "FP_REGS", \
1929 "MD0_REG", \
1930 "MD1_REG", \
1931 "MD_REGS", \
1932 /* coprocessor registers */ \
1933 "COP0_REGS", \
1934 "COP2_REGS", \
1935 "COP3_REGS", \
1936 "ST_REGS", \
1937 "DSP_ACC_REGS", \
1938 "ACC_REGS", \
1939 "FRAME_REGS", \
1940 "GR_AND_MD0_REGS", \
1941 "GR_AND_MD1_REGS", \
1942 "GR_AND_MD_REGS", \
1943 "GR_AND_ACC_REGS", \
1944 "ALL_REGS" \
1945 }
1946
1947 /* An initializer containing the contents of the register classes,
1948 as integers which are bit masks. The Nth integer specifies the
1949 contents of class N. The way the integer MASK is interpreted is
1950 that register R is in the class if `MASK & (1 << R)' is 1.
1951
1952 When the machine has more than 32 registers, an integer does not
1953 suffice. Then the integers are replaced by sub-initializers,
1954 braced groupings containing several integers. Each
1955 sub-initializer must be suitable as an initializer for the type
1956 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1957
1958 #define REG_CLASS_CONTENTS \
1959 { \
1960 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1961 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1962 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1963 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1964 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1965 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1966 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1967 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1968 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1969 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1970 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1971 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1972 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1973 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1974 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1975 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1976 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1977 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1978 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1979 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1980 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1981 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1982 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1983 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1984 }
1985
1986
1987 /* A C expression whose value is a register class containing hard
1988 register REGNO. In general there is more that one such class;
1989 choose a class which is "minimal", meaning that no smaller class
1990 also contains the register. */
1991
1992 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1993
1994 /* A macro whose definition is the name of the class to which a
1995 valid base register must belong. A base register is one used in
1996 an address which is the register value plus a displacement. */
1997
1998 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1999
2000 /* A macro whose definition is the name of the class to which a
2001 valid index register must belong. An index register is one used
2002 in an address where its value is either multiplied by a scale
2003 factor or added to another register (as well as added to a
2004 displacement). */
2005
2006 #define INDEX_REG_CLASS NO_REGS
2007
2008 /* We generally want to put call-clobbered registers ahead of
2009 call-saved ones. (IRA expects this.) */
2010
2011 #define REG_ALLOC_ORDER \
2012 { /* Accumulator registers. When GPRs and accumulators have equal \
2013 cost, we generally prefer to use accumulators. For example, \
2014 a division of multiplication result is better allocated to LO, \
2015 so that we put the MFLO at the point of use instead of at the \
2016 point of definition. It's also needed if we're to take advantage \
2017 of the extra accumulators available with -mdspr2. In some cases, \
2018 it can also help to reduce register pressure. */ \
2019 64, 65,176,177,178,179,180,181, \
2020 /* Call-clobbered GPRs. */ \
2021 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2022 24, 25, 31, \
2023 /* The global pointer. This is call-clobbered for o32 and o64 \
2024 abicalls, call-saved for n32 and n64 abicalls, and a program \
2025 invariant otherwise. Putting it between the call-clobbered \
2026 and call-saved registers should cope with all eventualities. */ \
2027 28, \
2028 /* Call-saved GPRs. */ \
2029 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2030 /* GPRs that can never be exposed to the register allocator. */ \
2031 0, 26, 27, 29, \
2032 /* Call-clobbered FPRs. */ \
2033 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2034 48, 49, 50, 51, \
2035 /* FPRs that are usually call-saved. The odd ones are actually \
2036 call-clobbered for n32, but listing them ahead of the even \
2037 registers might encourage the register allocator to fragment \
2038 the available FPR pairs. We need paired FPRs to store long \
2039 doubles, so it isn't clear that using a different order \
2040 for n32 would be a win. */ \
2041 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2042 /* None of the remaining classes have defined call-saved \
2043 registers. */ \
2044 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2045 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2046 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2047 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2048 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2049 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2050 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2051 182,183,184,185,186,187 \
2052 }
2053
2054 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
2055 to be rearranged based on a particular function. On the mips16, we
2056 want to allocate $24 (T_REG) before other registers for
2057 instructions for which it is possible. */
2058
2059 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2060
2061 /* True if VALUE is an unsigned 6-bit number. */
2062
2063 #define UIMM6_OPERAND(VALUE) \
2064 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2065
2066 /* True if VALUE is a signed 10-bit number. */
2067
2068 #define IMM10_OPERAND(VALUE) \
2069 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2070
2071 /* True if VALUE is a signed 16-bit number. */
2072
2073 #define SMALL_OPERAND(VALUE) \
2074 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2075
2076 /* True if VALUE is an unsigned 16-bit number. */
2077
2078 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2079 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2080
2081 /* True if VALUE can be loaded into a register using LUI. */
2082
2083 #define LUI_OPERAND(VALUE) \
2084 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2085 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2086
2087 /* Return a value X with the low 16 bits clear, and such that
2088 VALUE - X is a signed 16-bit value. */
2089
2090 #define CONST_HIGH_PART(VALUE) \
2091 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2092
2093 #define CONST_LOW_PART(VALUE) \
2094 ((VALUE) - CONST_HIGH_PART (VALUE))
2095
2096 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2097 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2098 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2099
2100 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2101 mips_preferred_reload_class (X, CLASS)
2102
2103 /* The HI and LO registers can only be reloaded via the general
2104 registers. Condition code registers can only be loaded to the
2105 general registers, and from the floating point registers. */
2106
2107 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2108 mips_secondary_reload_class (CLASS, MODE, X, true)
2109 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2110 mips_secondary_reload_class (CLASS, MODE, X, false)
2111
2112 /* Return the maximum number of consecutive registers
2113 needed to represent mode MODE in a register of class CLASS. */
2114
2115 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2116
2117 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2118 mips_cannot_change_mode_class (FROM, TO, CLASS)
2119 \f
2120 /* Stack layout; function entry, exit and calling. */
2121
2122 #define STACK_GROWS_DOWNWARD
2123
2124 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2125
2126 /* Size of the area allocated in the frame to save the GP. */
2127
2128 #define MIPS_GP_SAVE_AREA_SIZE \
2129 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2130
2131 /* The offset of the first local variable from the frame pointer. See
2132 mips_compute_frame_info for details about the frame layout. */
2133
2134 #define STARTING_FRAME_OFFSET \
2135 (FRAME_GROWS_DOWNWARD \
2136 ? 0 \
2137 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2138
2139 #define RETURN_ADDR_RTX mips_return_addr
2140
2141 /* Mask off the MIPS16 ISA bit in unwind addresses.
2142
2143 The reason for this is a little subtle. When unwinding a call,
2144 we are given the call's return address, which on most targets
2145 is the address of the following instruction. However, what we
2146 actually want to find is the EH region for the call itself.
2147 The target-independent unwind code therefore searches for "RA - 1".
2148
2149 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2150 RA - 1 is therefore the real (even-valued) start of the return
2151 instruction. EH region labels are usually odd-valued MIPS16 symbols
2152 too, so a search for an even address within a MIPS16 region would
2153 usually work.
2154
2155 However, there is an exception. If the end of an EH region is also
2156 the end of a function, the end label is allowed to be even. This is
2157 necessary because a following non-MIPS16 function may also need EH
2158 information for its first instruction.
2159
2160 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2161 non-ISA-encoded address. This probably isn't ideal, but it is
2162 the traditional (legacy) behavior. It is therefore only safe
2163 to search MIPS EH regions for an _odd-valued_ address.
2164
2165 Masking off the ISA bit means that the target-independent code
2166 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2167 #define MASK_RETURN_ADDR GEN_INT (-2)
2168
2169
2170 /* Similarly, don't use the least-significant bit to tell pointers to
2171 code from vtable index. */
2172
2173 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2174
2175 /* The eliminations to $17 are only used for mips16 code. See the
2176 definition of HARD_FRAME_POINTER_REGNUM. */
2177
2178 #define ELIMINABLE_REGS \
2179 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2180 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2181 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2182 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2183 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2184 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2185
2186 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2187 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2188
2189 /* Allocate stack space for arguments at the beginning of each function. */
2190 #define ACCUMULATE_OUTGOING_ARGS 1
2191
2192 /* The argument pointer always points to the first argument. */
2193 #define FIRST_PARM_OFFSET(FNDECL) 0
2194
2195 /* o32 and o64 reserve stack space for all argument registers. */
2196 #define REG_PARM_STACK_SPACE(FNDECL) \
2197 (TARGET_OLDABI \
2198 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2199 : 0)
2200
2201 /* Define this if it is the responsibility of the caller to
2202 allocate the area reserved for arguments passed in registers.
2203 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2204 of this macro is to determine whether the space is included in
2205 `crtl->outgoing_args_size'. */
2206 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2207
2208 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2209 \f
2210 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2211
2212 /* Symbolic macros for the registers used to return integer and floating
2213 point values. */
2214
2215 #define GP_RETURN (GP_REG_FIRST + 2)
2216 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2217
2218 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2219
2220 /* Symbolic macros for the first/last argument registers. */
2221
2222 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2223 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2224 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2225 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2226
2227 #define LIBCALL_VALUE(MODE) \
2228 mips_function_value (NULL_TREE, NULL_TREE, MODE)
2229
2230 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2231 mips_function_value (VALTYPE, FUNC, VOIDmode)
2232
2233 /* 1 if N is a possible register number for a function value.
2234 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2235 Currently, R2 and F0 are only implemented here (C has no complex type) */
2236
2237 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2238 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2239 && (N) == FP_RETURN + 2))
2240
2241 /* 1 if N is a possible register number for function argument passing.
2242 We have no FP argument registers when soft-float. When FP registers
2243 are 32 bits, we can't directly reference the odd numbered ones. */
2244
2245 #define FUNCTION_ARG_REGNO_P(N) \
2246 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2247 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2248 && !fixed_regs[N])
2249 \f
2250 /* This structure has to cope with two different argument allocation
2251 schemes. Most MIPS ABIs view the arguments as a structure, of which
2252 the first N words go in registers and the rest go on the stack. If I
2253 < N, the Ith word might go in Ith integer argument register or in a
2254 floating-point register. For these ABIs, we only need to remember
2255 the offset of the current argument into the structure.
2256
2257 The EABI instead allocates the integer and floating-point arguments
2258 separately. The first N words of FP arguments go in FP registers,
2259 the rest go on the stack. Likewise, the first N words of the other
2260 arguments go in integer registers, and the rest go on the stack. We
2261 need to maintain three counts: the number of integer registers used,
2262 the number of floating-point registers used, and the number of words
2263 passed on the stack.
2264
2265 We could keep separate information for the two ABIs (a word count for
2266 the standard ABIs, and three separate counts for the EABI). But it
2267 seems simpler to view the standard ABIs as forms of EABI that do not
2268 allocate floating-point registers.
2269
2270 So for the standard ABIs, the first N words are allocated to integer
2271 registers, and mips_function_arg decides on an argument-by-argument
2272 basis whether that argument should really go in an integer register,
2273 or in a floating-point one. */
2274
2275 typedef struct mips_args {
2276 /* Always true for varargs functions. Otherwise true if at least
2277 one argument has been passed in an integer register. */
2278 int gp_reg_found;
2279
2280 /* The number of arguments seen so far. */
2281 unsigned int arg_number;
2282
2283 /* The number of integer registers used so far. For all ABIs except
2284 EABI, this is the number of words that have been added to the
2285 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2286 unsigned int num_gprs;
2287
2288 /* For EABI, the number of floating-point registers used so far. */
2289 unsigned int num_fprs;
2290
2291 /* The number of words passed on the stack. */
2292 unsigned int stack_words;
2293
2294 /* On the mips16, we need to keep track of which floating point
2295 arguments were passed in general registers, but would have been
2296 passed in the FP regs if this were a 32-bit function, so that we
2297 can move them to the FP regs if we wind up calling a 32-bit
2298 function. We record this information in fp_code, encoded in base
2299 four. A zero digit means no floating point argument, a one digit
2300 means an SFmode argument, and a two digit means a DFmode argument,
2301 and a three digit is not used. The low order digit is the first
2302 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2303 an SFmode argument. ??? A more sophisticated approach will be
2304 needed if MIPS_ABI != ABI_32. */
2305 int fp_code;
2306
2307 /* True if the function has a prototype. */
2308 int prototype;
2309 } CUMULATIVE_ARGS;
2310
2311 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2312 for a call to a function whose data type is FNTYPE.
2313 For a library call, FNTYPE is 0. */
2314
2315 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2316 mips_init_cumulative_args (&CUM, FNTYPE)
2317
2318 /* Update the data in CUM to advance over an argument
2319 of mode MODE and data type TYPE.
2320 (TYPE is null for libcalls where that information may not be available.) */
2321
2322 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2323 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
2324
2325 /* Determine where to put an argument to a function.
2326 Value is zero to push the argument on the stack,
2327 or a hard register in which to store the argument.
2328
2329 MODE is the argument's machine mode.
2330 TYPE is the data type of the argument (as a tree).
2331 This is null for libcalls where that information may
2332 not be available.
2333 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2334 the preceding args and about the function being called.
2335 NAMED is nonzero if this argument is a named parameter
2336 (otherwise it is an extra parameter matching an ellipsis). */
2337
2338 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2339 mips_function_arg (&CUM, MODE, TYPE, NAMED)
2340
2341 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2342
2343 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2344 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2345
2346 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2347 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2348
2349 /* True if using EABI and varargs can be passed in floating-point
2350 registers. Under these conditions, we need a more complex form
2351 of va_list, which tracks GPR, FPR and stack arguments separately. */
2352 #define EABI_FLOAT_VARARGS_P \
2353 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2354
2355 \f
2356 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2357
2358 /* Treat LOC as a byte offset from the stack pointer and round it up
2359 to the next fully-aligned offset. */
2360 #define MIPS_STACK_ALIGN(LOC) \
2361 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2362
2363 \f
2364 /* Output assembler code to FILE to increment profiler label # LABELNO
2365 for profiling a function entry. */
2366
2367 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2368
2369 /* The profiler preserves all interesting registers, including $31. */
2370 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2371
2372 /* No mips port has ever used the profiler counter word, so don't emit it
2373 or the label for it. */
2374
2375 #define NO_PROFILE_COUNTERS 1
2376
2377 /* Define this macro if the code for function profiling should come
2378 before the function prologue. Normally, the profiling code comes
2379 after. */
2380
2381 /* #define PROFILE_BEFORE_PROLOGUE */
2382
2383 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2384 the stack pointer does not matter. The value is tested only in
2385 functions that have frame pointers.
2386 No definition is equivalent to always zero. */
2387
2388 #define EXIT_IGNORE_STACK 1
2389
2390 \f
2391 /* Trampolines are a block of code followed by two pointers. */
2392
2393 #define TRAMPOLINE_SIZE \
2394 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2395
2396 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2397 pointers from a single LUI base. */
2398
2399 #define TRAMPOLINE_ALIGNMENT 64
2400
2401 /* mips_trampoline_init calls this library function to flush
2402 program and data caches. */
2403
2404 #ifndef CACHE_FLUSH_FUNC
2405 #define CACHE_FLUSH_FUNC "_flush_cache"
2406 #endif
2407
2408 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2409 /* Flush both caches. We need to flush the data cache in case \
2410 the system has a write-back cache. */ \
2411 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2412 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2413 GEN_INT (3), TYPE_MODE (integer_type_node))
2414
2415 \f
2416 /* Addressing modes, and classification of registers for them. */
2417
2418 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2419 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2420 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2421
2422 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2423 and check its validity for a certain class.
2424 We have two alternate definitions for each of them.
2425 The usual definition accepts all pseudo regs; the other rejects them all.
2426 The symbol REG_OK_STRICT causes the latter definition to be used.
2427
2428 Most source files want to accept pseudo regs in the hope that
2429 they will get allocated to the class that the insn wants them to be in.
2430 Some source files that are used after register allocation
2431 need to be strict. */
2432
2433 #ifndef REG_OK_STRICT
2434 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2435 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2436 #else
2437 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2438 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2439 #endif
2440
2441 #define REG_OK_FOR_INDEX_P(X) 0
2442
2443 \f
2444 /* Maximum number of registers that can appear in a valid memory address. */
2445
2446 #define MAX_REGS_PER_ADDRESS 1
2447
2448 /* Check for constness inline but use mips_legitimate_address_p
2449 to check whether a constant really is an address. */
2450
2451 #define CONSTANT_ADDRESS_P(X) \
2452 (CONSTANT_P (X) && memory_address_p (SImode, X))
2453
2454 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2455
2456 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2457 'the start of the function that this code is output in'. */
2458
2459 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2460 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2461 asm_fprintf ((FILE), "%U%s", \
2462 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2463 else \
2464 asm_fprintf ((FILE), "%U%s", (NAME))
2465 \f
2466 /* Flag to mark a function decl symbol that requires a long call. */
2467 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2468 #define SYMBOL_REF_LONG_CALL_P(X) \
2469 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2470
2471 /* This flag marks functions that cannot be lazily bound. */
2472 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2473 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2474 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2475
2476 /* True if we're generating a form of MIPS16 code in which jump tables
2477 are stored in the text section and encoded as 16-bit PC-relative
2478 offsets. This is only possible when general text loads are allowed,
2479 since the table access itself will be an "lh" instruction. */
2480 /* ??? 16-bit offsets can overflow in large functions. */
2481 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2482
2483 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2484
2485 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2486
2487 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2488
2489 /* Define this as 1 if `char' should by default be signed; else as 0. */
2490 #ifndef DEFAULT_SIGNED_CHAR
2491 #define DEFAULT_SIGNED_CHAR 1
2492 #endif
2493
2494 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2495 we generally don't want to use them for copying arbitrary data.
2496 A single N-word move is usually the same cost as N single-word moves. */
2497 #define MOVE_MAX UNITS_PER_WORD
2498 #define MAX_MOVE_MAX 8
2499
2500 /* Define this macro as a C expression which is nonzero if
2501 accessing less than a word of memory (i.e. a `char' or a
2502 `short') is no faster than accessing a word of memory, i.e., if
2503 such access require more than one instruction or if there is no
2504 difference in cost between byte and (aligned) word loads.
2505
2506 On RISC machines, it tends to generate better code to define
2507 this as 1, since it avoids making a QI or HI mode register.
2508
2509 But, generating word accesses for -mips16 is generally bad as shifts
2510 (often extended) would be needed for byte accesses. */
2511 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2512
2513 /* Define this to be nonzero if shift instructions ignore all but the low-order
2514 few bits. */
2515 #define SHIFT_COUNT_TRUNCATED 1
2516
2517 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2518 is done just by pretending it is already truncated. */
2519 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2520 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2521
2522
2523 /* Specify the machine mode that pointers have.
2524 After generation of rtl, the compiler makes no further distinction
2525 between pointers and any other objects of this machine mode. */
2526
2527 #ifndef Pmode
2528 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2529 #endif
2530
2531 /* Give call MEMs SImode since it is the "most permissive" mode
2532 for both 32-bit and 64-bit targets. */
2533
2534 #define FUNCTION_MODE SImode
2535
2536 \f
2537 /* A C expression for the cost of moving data from a register in
2538 class FROM to one in class TO. The classes are expressed using
2539 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2540 the default; other values are interpreted relative to that.
2541
2542 It is not required that the cost always equal 2 when FROM is the
2543 same as TO; on some machines it is expensive to move between
2544 registers if they are not general registers.
2545
2546 If reload sees an insn consisting of a single `set' between two
2547 hard registers, and if `REGISTER_MOVE_COST' applied to their
2548 classes returns a value of 2, reload does not check to ensure
2549 that the constraints of the insn are met. Setting a cost of
2550 other than 2 will allow reload to verify that the constraints are
2551 met. You should do this if the `movM' pattern's constraints do
2552 not allow such copying. */
2553
2554 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2555 mips_register_move_cost (MODE, FROM, TO)
2556
2557 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2558 (mips_cost->memory_latency \
2559 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2560
2561 /* Define if copies to/from condition code registers should be avoided.
2562
2563 This is needed for the MIPS because reload_outcc is not complete;
2564 it needs to handle cases where the source is a general or another
2565 condition code register. */
2566 #define AVOID_CCMODE_COPIES
2567
2568 /* A C expression for the cost of a branch instruction. A value of
2569 1 is the default; other values are interpreted relative to that. */
2570
2571 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2572 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2573
2574 /* If defined, modifies the length assigned to instruction INSN as a
2575 function of the context in which it is used. LENGTH is an lvalue
2576 that contains the initially computed length of the insn and should
2577 be updated with the correct length of the insn. */
2578 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2579 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2580
2581 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2582 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2583 its operands. */
2584 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2585 "%*" OPCODE "%?\t" OPERANDS "%/"
2586
2587 /* Return an asm string that forces INSN to be treated as an absolute
2588 J or JAL instruction instead of an assembler macro. */
2589 #define MIPS_ABSOLUTE_JUMP(INSN) \
2590 (TARGET_ABICALLS_PIC2 \
2591 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2592 : INSN)
2593
2594 /* Return the asm template for a call. INSN is the instruction's mnemonic
2595 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2596 number of the target. SIZE_OPNO is the operand number of the argument size
2597 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2598 -1 and the call is indirect, use the function symbol from the call
2599 attributes to attach a R_MIPS_JALR relocation to the call.
2600
2601 When generating GOT code without explicit relocation operators,
2602 all calls should use assembly macros. Otherwise, all indirect
2603 calls should use "jr" or "jalr"; we will arrange to restore $gp
2604 afterwards if necessary. Finally, we can only generate direct
2605 calls for -mabicalls by temporarily switching to non-PIC mode. */
2606 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2607 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2608 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2609 : (REG_P (OPERANDS[TARGET_OPNO]) \
2610 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2611 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2612 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2613 : REG_P (OPERANDS[TARGET_OPNO]) \
2614 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2615 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2616 \f
2617 /* Control the assembler format that we output. */
2618
2619 /* Output to assembler file text saying following lines
2620 may contain character constants, extra white space, comments, etc. */
2621
2622 #ifndef ASM_APP_ON
2623 #define ASM_APP_ON " #APP\n"
2624 #endif
2625
2626 /* Output to assembler file text saying following lines
2627 no longer contain unusual constructs. */
2628
2629 #ifndef ASM_APP_OFF
2630 #define ASM_APP_OFF " #NO_APP\n"
2631 #endif
2632
2633 #define REGISTER_NAMES \
2634 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2635 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2636 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2637 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2638 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2639 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2640 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2641 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2642 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2643 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2644 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2645 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2646 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2647 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2648 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2649 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2650 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2651 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2652 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2653 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2654 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2655 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2656 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2657 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2658
2659 /* List the "software" names for each register. Also list the numerical
2660 names for $fp and $sp. */
2661
2662 #define ADDITIONAL_REGISTER_NAMES \
2663 { \
2664 { "$29", 29 + GP_REG_FIRST }, \
2665 { "$30", 30 + GP_REG_FIRST }, \
2666 { "at", 1 + GP_REG_FIRST }, \
2667 { "v0", 2 + GP_REG_FIRST }, \
2668 { "v1", 3 + GP_REG_FIRST }, \
2669 { "a0", 4 + GP_REG_FIRST }, \
2670 { "a1", 5 + GP_REG_FIRST }, \
2671 { "a2", 6 + GP_REG_FIRST }, \
2672 { "a3", 7 + GP_REG_FIRST }, \
2673 { "t0", 8 + GP_REG_FIRST }, \
2674 { "t1", 9 + GP_REG_FIRST }, \
2675 { "t2", 10 + GP_REG_FIRST }, \
2676 { "t3", 11 + GP_REG_FIRST }, \
2677 { "t4", 12 + GP_REG_FIRST }, \
2678 { "t5", 13 + GP_REG_FIRST }, \
2679 { "t6", 14 + GP_REG_FIRST }, \
2680 { "t7", 15 + GP_REG_FIRST }, \
2681 { "s0", 16 + GP_REG_FIRST }, \
2682 { "s1", 17 + GP_REG_FIRST }, \
2683 { "s2", 18 + GP_REG_FIRST }, \
2684 { "s3", 19 + GP_REG_FIRST }, \
2685 { "s4", 20 + GP_REG_FIRST }, \
2686 { "s5", 21 + GP_REG_FIRST }, \
2687 { "s6", 22 + GP_REG_FIRST }, \
2688 { "s7", 23 + GP_REG_FIRST }, \
2689 { "t8", 24 + GP_REG_FIRST }, \
2690 { "t9", 25 + GP_REG_FIRST }, \
2691 { "k0", 26 + GP_REG_FIRST }, \
2692 { "k1", 27 + GP_REG_FIRST }, \
2693 { "gp", 28 + GP_REG_FIRST }, \
2694 { "sp", 29 + GP_REG_FIRST }, \
2695 { "fp", 30 + GP_REG_FIRST }, \
2696 { "ra", 31 + GP_REG_FIRST }, \
2697 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2698 }
2699
2700 /* This is meant to be redefined in the host dependent files. It is a
2701 set of alternative names and regnums for mips coprocessors. */
2702
2703 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2704
2705 #define PRINT_OPERAND mips_print_operand
2706 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2707 #define PRINT_OPERAND_ADDRESS mips_print_operand_address
2708
2709 #define DBR_OUTPUT_SEQEND(STREAM) \
2710 do \
2711 { \
2712 /* Undo the effect of '%*'. */ \
2713 mips_pop_asm_switch (&mips_nomacro); \
2714 mips_pop_asm_switch (&mips_noreorder); \
2715 /* Emit a blank line after the delay slot for emphasis. */ \
2716 fputs ("\n", STREAM); \
2717 } \
2718 while (0)
2719
2720 /* How to tell the debugger about changes of source files. */
2721 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
2722
2723 /* mips-tfile does not understand .stabd directives. */
2724 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2725 dbxout_begin_stabn_sline (LINE); \
2726 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2727 } while (0)
2728
2729 /* Use .loc directives for SDB line numbers. */
2730 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2731 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2732
2733 /* The MIPS implementation uses some labels for its own purpose. The
2734 following lists what labels are created, and are all formed by the
2735 pattern $L[a-z].*. The machine independent portion of GCC creates
2736 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2737
2738 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2739 $Lb[0-9]+ Begin blocks for MIPS debug support
2740 $Lc[0-9]+ Label for use in s<xx> operation.
2741 $Le[0-9]+ End blocks for MIPS debug support */
2742
2743 #undef ASM_DECLARE_OBJECT_NAME
2744 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2745 mips_declare_object (STREAM, NAME, "", ":\n")
2746
2747 /* Globalizing directive for a label. */
2748 #define GLOBAL_ASM_OP "\t.globl\t"
2749
2750 /* This says how to define a global common symbol. */
2751
2752 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2753
2754 /* This says how to define a local common symbol (i.e., not visible to
2755 linker). */
2756
2757 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2758 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2759 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2760 #endif
2761
2762 /* This says how to output an external. It would be possible not to
2763 output anything and let undefined symbol become external. However
2764 the assembler uses length information on externals to allocate in
2765 data/sdata bss/sbss, thereby saving exec time. */
2766
2767 #undef ASM_OUTPUT_EXTERNAL
2768 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2769 mips_output_external(STREAM,DECL,NAME)
2770
2771 /* This is how to declare a function name. The actual work of
2772 emitting the label is moved to function_prologue, so that we can
2773 get the line number correctly emitted before the .ent directive,
2774 and after any .file directives. Define as empty so that the function
2775 is not declared before the .ent directive elsewhere. */
2776
2777 #undef ASM_DECLARE_FUNCTION_NAME
2778 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2779
2780 /* This is how to store into the string LABEL
2781 the symbol_ref name of an internal numbered label where
2782 PREFIX is the class of label and NUM is the number within the class.
2783 This is suitable for output with `assemble_name'. */
2784
2785 #undef ASM_GENERATE_INTERNAL_LABEL
2786 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2787 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2788
2789 /* Print debug labels as "foo = ." rather than "foo:" because they should
2790 represent a byte pointer rather than an ISA-encoded address. This is
2791 particularly important for code like:
2792
2793 $LFBxxx = .
2794 .cfi_startproc
2795 ...
2796 .section .gcc_except_table,...
2797 ...
2798 .uleb128 foo-$LFBxxx
2799
2800 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2801 likewise a byte pointer rather than an ISA-encoded address.
2802
2803 At the time of writing, this hook is not used for the function end
2804 label:
2805
2806 $LFExxx:
2807 .end foo
2808
2809 But this doesn't matter, because GAS doesn't treat a pre-.end label
2810 as a MIPS16 one anyway. */
2811
2812 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2813 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2814
2815 /* This is how to output an element of a case-vector that is absolute. */
2816
2817 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2818 fprintf (STREAM, "\t%s\t%sL%d\n", \
2819 ptr_mode == DImode ? ".dword" : ".word", \
2820 LOCAL_LABEL_PREFIX, \
2821 VALUE)
2822
2823 /* This is how to output an element of a case-vector. We can make the
2824 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2825 is supported. */
2826
2827 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2828 do { \
2829 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2830 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2831 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2832 else if (TARGET_GPWORD) \
2833 fprintf (STREAM, "\t%s\t%sL%d\n", \
2834 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2835 LOCAL_LABEL_PREFIX, VALUE); \
2836 else if (TARGET_RTP_PIC) \
2837 { \
2838 /* Make the entry relative to the start of the function. */ \
2839 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2840 fprintf (STREAM, "\t%s\t%sL%d-", \
2841 Pmode == DImode ? ".dword" : ".word", \
2842 LOCAL_LABEL_PREFIX, VALUE); \
2843 assemble_name (STREAM, XSTR (fnsym, 0)); \
2844 fprintf (STREAM, "\n"); \
2845 } \
2846 else \
2847 fprintf (STREAM, "\t%s\t%sL%d\n", \
2848 ptr_mode == DImode ? ".dword" : ".word", \
2849 LOCAL_LABEL_PREFIX, VALUE); \
2850 } while (0)
2851
2852 /* This is how to output an assembler line
2853 that says to advance the location counter
2854 to a multiple of 2**LOG bytes. */
2855
2856 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2857 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2858
2859 /* This is how to output an assembler line to advance the location
2860 counter by SIZE bytes. */
2861
2862 #undef ASM_OUTPUT_SKIP
2863 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2864 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2865
2866 /* This is how to output a string. */
2867 #undef ASM_OUTPUT_ASCII
2868 #define ASM_OUTPUT_ASCII mips_output_ascii
2869
2870 /* Output #ident as a in the read-only data section. */
2871 #undef ASM_OUTPUT_IDENT
2872 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2873 { \
2874 const char *p = STRING; \
2875 int size = strlen (p) + 1; \
2876 switch_to_section (readonly_data_section); \
2877 assemble_string (p, size); \
2878 }
2879 \f
2880 /* Default to -G 8 */
2881 #ifndef MIPS_DEFAULT_GVALUE
2882 #define MIPS_DEFAULT_GVALUE 8
2883 #endif
2884
2885 /* Define the strings to put out for each section in the object file. */
2886 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2887 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2888
2889 #undef READONLY_DATA_SECTION_ASM_OP
2890 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2891 \f
2892 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2893 do \
2894 { \
2895 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2896 TARGET_64BIT ? "daddiu" : "addiu", \
2897 reg_names[STACK_POINTER_REGNUM], \
2898 reg_names[STACK_POINTER_REGNUM], \
2899 TARGET_64BIT ? "sd" : "sw", \
2900 reg_names[REGNO], \
2901 reg_names[STACK_POINTER_REGNUM]); \
2902 } \
2903 while (0)
2904
2905 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2906 do \
2907 { \
2908 mips_push_asm_switch (&mips_noreorder); \
2909 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2910 TARGET_64BIT ? "ld" : "lw", \
2911 reg_names[REGNO], \
2912 reg_names[STACK_POINTER_REGNUM], \
2913 TARGET_64BIT ? "daddu" : "addu", \
2914 reg_names[STACK_POINTER_REGNUM], \
2915 reg_names[STACK_POINTER_REGNUM]); \
2916 mips_pop_asm_switch (&mips_noreorder); \
2917 } \
2918 while (0)
2919
2920 /* How to start an assembler comment.
2921 The leading space is important (the mips native assembler requires it). */
2922 #ifndef ASM_COMMENT_START
2923 #define ASM_COMMENT_START " #"
2924 #endif
2925 \f
2926 /* Default definitions for size_t and ptrdiff_t. We must override the
2927 definitions from ../svr4.h on mips-*-linux-gnu. */
2928
2929 #undef SIZE_TYPE
2930 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2931
2932 #undef PTRDIFF_TYPE
2933 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2934
2935 /* The maximum number of bytes that can be copied by one iteration of
2936 a movmemsi loop; see mips_block_move_loop. */
2937 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2938 (UNITS_PER_WORD * 4)
2939
2940 /* The maximum number of bytes that can be copied by a straight-line
2941 implementation of movmemsi; see mips_block_move_straight. We want
2942 to make sure that any loop-based implementation will iterate at
2943 least twice. */
2944 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2945 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2946
2947 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2948 values were determined experimentally by benchmarking with CSiBE.
2949 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2950 for o32 where we have to restore $gp afterwards as well as make an
2951 indirect call), but in practice, bumping this up higher for
2952 TARGET_ABICALLS doesn't make much difference to code size. */
2953
2954 #define MIPS_CALL_RATIO 8
2955
2956 /* Any loop-based implementation of movmemsi will have at least
2957 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2958 moves, so allow individual copies of fewer elements.
2959
2960 When movmemsi is not available, use a value approximating
2961 the length of a memcpy call sequence, so that move_by_pieces
2962 will generate inline code if it is shorter than a function call.
2963 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2964 we'll have to generate a load/store pair for each, halve the
2965 value of MIPS_CALL_RATIO to take that into account. */
2966
2967 #define MOVE_RATIO(speed) \
2968 (HAVE_movmemsi \
2969 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2970 : MIPS_CALL_RATIO / 2)
2971
2972 /* movmemsi is meant to generate code that is at least as good as
2973 move_by_pieces. However, movmemsi effectively uses a by-pieces
2974 implementation both for moves smaller than a word and for word-aligned
2975 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
2976 allow the tree-level optimisers to do such moves by pieces, as it
2977 often exposes other optimization opportunities. We might as well
2978 continue to use movmemsi at the rtl level though, as it produces
2979 better code when scheduling is disabled (such as at -O). */
2980
2981 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2982 (HAVE_movmemsi \
2983 ? (!currently_expanding_to_rtl \
2984 && ((ALIGN) < BITS_PER_WORD \
2985 ? (SIZE) < UNITS_PER_WORD \
2986 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
2987 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2988 < (unsigned int) MOVE_RATIO (false)))
2989
2990 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2991 of the length of a memset call, but use the default otherwise. */
2992
2993 #define CLEAR_RATIO(speed)\
2994 ((speed) ? 15 : MIPS_CALL_RATIO)
2995
2996 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2997 optimizing for size adjust the ratio to account for the overhead of
2998 loading the constant and replicating it across the word. */
2999
3000 #define SET_RATIO(speed) \
3001 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3002
3003 /* STORE_BY_PIECES_P can be used when copying a constant string, but
3004 in that case each word takes 3 insns (lui, ori, sw), or more in
3005 64-bit mode, instead of 2 (lw, sw). For now we always fail this
3006 and let the move_by_pieces code copy the string from read-only
3007 memory. In the future, this could be tuned further for multi-issue
3008 CPUs that can issue stores down one pipe and arithmetic instructions
3009 down another; in that case, the lui/ori/sw combination would be a
3010 win for long enough strings. */
3011
3012 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
3013 \f
3014 #ifndef __mips16
3015 /* Since the bits of the _init and _fini function is spread across
3016 many object files, each potentially with its own GP, we must assume
3017 we need to load our GP. We don't preserve $gp or $ra, since each
3018 init/fini chunk is supposed to initialize $gp, and crti/crtn
3019 already take care of preserving $ra and, when appropriate, $gp. */
3020 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3021 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3022 asm (SECTION_OP "\n\
3023 .set noreorder\n\
3024 bal 1f\n\
3025 nop\n\
3026 1: .cpload $31\n\
3027 .set reorder\n\
3028 jal " USER_LABEL_PREFIX #FUNC "\n\
3029 " TEXT_SECTION_ASM_OP);
3030 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3031 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3032 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3033 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3034 asm (SECTION_OP "\n\
3035 .set noreorder\n\
3036 bal 1f\n\
3037 nop\n\
3038 1: .set reorder\n\
3039 .cpsetup $31, $2, 1b\n\
3040 jal " USER_LABEL_PREFIX #FUNC "\n\
3041 " TEXT_SECTION_ASM_OP);
3042 #endif
3043 #endif
3044
3045 #ifndef HAVE_AS_TLS
3046 #define HAVE_AS_TLS 0
3047 #endif
3048
3049 #ifndef USED_FOR_TARGET
3050 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3051 struct mips_asm_switch {
3052 /* The FOO in the description above. */
3053 const char *name;
3054
3055 /* The current block nesting level, or 0 if we aren't in a block. */
3056 int nesting_level;
3057 };
3058
3059 extern const enum reg_class mips_regno_to_class[];
3060 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3061 extern bool mips_print_operand_punct[256];
3062 extern const char *current_function_file; /* filename current function is in */
3063 extern int num_source_filenames; /* current .file # */
3064 extern struct mips_asm_switch mips_noreorder;
3065 extern struct mips_asm_switch mips_nomacro;
3066 extern struct mips_asm_switch mips_noat;
3067 extern int mips_dbx_regno[];
3068 extern int mips_dwarf_regno[];
3069 extern bool mips_split_p[];
3070 extern bool mips_split_hi_p[];
3071 extern enum processor_type mips_arch; /* which cpu to codegen for */
3072 extern enum processor_type mips_tune; /* which cpu to schedule for */
3073 extern int mips_isa; /* architectural level */
3074 extern int mips_abi; /* which ABI to use */
3075 extern const struct mips_cpu_info *mips_arch_info;
3076 extern const struct mips_cpu_info *mips_tune_info;
3077 extern const struct mips_rtx_cost_data *mips_cost;
3078 extern bool mips_base_mips16;
3079 extern enum mips_code_readable_setting mips_code_readable;
3080 #endif
3081
3082 /* Enable querying of DFA units. */
3083 #define CPU_UNITS_QUERY 1
3084
3085 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3086 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3087
3088 /* This is necessary to avoid a warning about comparing different enum
3089 types. */
3090 #define mips_tune_attr ((enum attr_cpu) mips_tune)
3091
3092 /* As on most targets, we want the .eh_frame section to be read-only where
3093 possible. And as on most targets, this means two things:
3094
3095 (a) Non-locally-binding pointers must have an indirect encoding,
3096 so that the addresses in the .eh_frame section itself become
3097 locally-binding.
3098
3099 (b) A shared library's .eh_frame section must encode locally-binding
3100 pointers in a relative (relocation-free) form.
3101
3102 However, MIPS has traditionally not allowed directives like:
3103
3104 .long x-.
3105
3106 in cases where "x" is in a different section, or is not defined in the
3107 same assembly file. We are therefore unable to emit the PC-relative
3108 form required by (b) at assembly time.
3109
3110 Fortunately, the linker is able to convert absolute addresses into
3111 PC-relative addresses on our behalf. Unfortunately, only certain
3112 versions of the linker know how to do this for indirect pointers,
3113 and for personality data. We must fall back on using writable
3114 .eh_frame sections for shared libraries if the linker does not
3115 support this feature. */
3116 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3117 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)