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mips-common.c (TARGET_DEFAULT_TARGET_FLAGS): Remove TARGET_FP_EXCEPTIONS_DEFAULT...
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS64 (mips_isa == 64)
212 #define ISA_MIPS64R2 (mips_isa == 65)
213
214 /* Architecture target defines. */
215 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
216 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
217 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
218 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
219 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
220 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
221 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
222 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
223 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
224 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
225 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
226 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
227 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
228 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
229 || mips_arch == PROCESSOR_OCTEON2)
230 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
231 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
232 || mips_arch == PROCESSOR_SB1A)
233 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
234 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
235
236 /* Scheduling target defines. */
237 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
238 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
239 || mips_tune == PROCESSOR_24KF2_1 \
240 || mips_tune == PROCESSOR_24KF1_1)
241 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
242 || mips_tune == PROCESSOR_74KF2_1 \
243 || mips_tune == PROCESSOR_74KF1_1 \
244 || mips_tune == PROCESSOR_74KF3_2)
245 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
246 || mips_tune == PROCESSOR_LOONGSON_2F)
247 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
248 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
249 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
250 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
251 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
252 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
253 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
254 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
255 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
256 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
257 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
258 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
259 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
260 || mips_tune == PROCESSOR_OCTEON2)
261 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
262 || mips_tune == PROCESSOR_SB1A)
263
264 /* Whether vector modes and intrinsics for ST Microelectronics
265 Loongson-2E/2F processors should be enabled. In o32 pairs of
266 floating-point registers provide 64-bit values. */
267 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
268 && (TARGET_LOONGSON_2EF \
269 || TARGET_LOONGSON_3A))
270
271 /* True if the pre-reload scheduler should try to create chains of
272 multiply-add or multiply-subtract instructions. For example,
273 suppose we have:
274
275 t1 = a * b
276 t2 = t1 + c * d
277 t3 = e * f
278 t4 = t3 - g * h
279
280 t1 will have a higher priority than t2 and t3 will have a higher
281 priority than t4. However, before reload, there is no dependence
282 between t1 and t3, and they can often have similar priorities.
283 The scheduler will then tend to prefer:
284
285 t1 = a * b
286 t3 = e * f
287 t2 = t1 + c * d
288 t4 = t3 - g * h
289
290 which stops us from making full use of macc/madd-style instructions.
291 This sort of situation occurs frequently in Fourier transforms and
292 in unrolled loops.
293
294 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
295 queue so that chained multiply-add and multiply-subtract instructions
296 appear ahead of any other instruction that is likely to clobber lo.
297 In the example above, if t2 and t3 become ready at the same time,
298 the code ensures that t2 is scheduled first.
299
300 Multiply-accumulate instructions are a bigger win for some targets
301 than others, so this macro is defined on an opt-in basis. */
302 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
303 || TUNE_MIPS4120 \
304 || TUNE_MIPS4130 \
305 || TUNE_24K)
306
307 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
308 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
309
310 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
311 directly accessible, while the command-line options select
312 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
313 in use. */
314 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
315 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
316
317 /* False if SC acts as a memory barrier with respect to itself,
318 otherwise a SYNC will be emitted after SC for atomic operations
319 that require ordering between the SC and following loads and
320 stores. It does not tell anything about ordering of loads and
321 stores prior to and following the SC, only about the SC itself and
322 those loads and stores follow it. */
323 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
324
325 /* Define preprocessor macros for the -march and -mtune options.
326 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
327 processor. If INFO's canonical name is "foo", define PREFIX to
328 be "foo", and define an additional macro PREFIX_FOO. */
329 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
330 do \
331 { \
332 char *macro, *p; \
333 \
334 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
335 for (p = macro; *p != 0; p++) \
336 if (*p == '+') \
337 *p = 'P'; \
338 else \
339 *p = TOUPPER (*p); \
340 \
341 builtin_define (macro); \
342 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
343 free (macro); \
344 } \
345 while (0)
346
347 /* Target CPU builtins. */
348 #define TARGET_CPU_CPP_BUILTINS() \
349 do \
350 { \
351 builtin_assert ("machine=mips"); \
352 builtin_assert ("cpu=mips"); \
353 builtin_define ("__mips__"); \
354 builtin_define ("_mips"); \
355 \
356 /* We do this here because __mips is defined below and so we \
357 can't use builtin_define_std. We don't ever want to define \
358 "mips" for VxWorks because some of the VxWorks headers \
359 construct include filenames from a root directory macro, \
360 an architecture macro and a filename, where the architecture \
361 macro expands to 'mips'. If we define 'mips' to 1, the \
362 architecture macro expands to 1 as well. */ \
363 if (!flag_iso && !TARGET_VXWORKS) \
364 builtin_define ("mips"); \
365 \
366 if (TARGET_64BIT) \
367 builtin_define ("__mips64"); \
368 \
369 /* Treat _R3000 and _R4000 like register-size \
370 defines, which is how they've historically \
371 been used. */ \
372 if (TARGET_64BIT) \
373 { \
374 builtin_define_std ("R4000"); \
375 builtin_define ("_R4000"); \
376 } \
377 else \
378 { \
379 builtin_define_std ("R3000"); \
380 builtin_define ("_R3000"); \
381 } \
382 \
383 if (TARGET_FLOAT64) \
384 builtin_define ("__mips_fpr=64"); \
385 else \
386 builtin_define ("__mips_fpr=32"); \
387 \
388 if (mips_base_compression_flags & MASK_MIPS16) \
389 builtin_define ("__mips16"); \
390 \
391 if (TARGET_MIPS3D) \
392 builtin_define ("__mips3d"); \
393 \
394 if (TARGET_SMARTMIPS) \
395 builtin_define ("__mips_smartmips"); \
396 \
397 if (mips_base_compression_flags & MASK_MICROMIPS) \
398 builtin_define ("__mips_micromips"); \
399 \
400 if (TARGET_MCU) \
401 builtin_define ("__mips_mcu"); \
402 \
403 if (TARGET_EVA) \
404 builtin_define ("__mips_eva"); \
405 \
406 if (TARGET_DSP) \
407 { \
408 builtin_define ("__mips_dsp"); \
409 if (TARGET_DSPR2) \
410 { \
411 builtin_define ("__mips_dspr2"); \
412 builtin_define ("__mips_dsp_rev=2"); \
413 } \
414 else \
415 builtin_define ("__mips_dsp_rev=1"); \
416 } \
417 \
418 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
419 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
420 \
421 if (ISA_MIPS1) \
422 { \
423 builtin_define ("__mips=1"); \
424 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
425 } \
426 else if (ISA_MIPS2) \
427 { \
428 builtin_define ("__mips=2"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
430 } \
431 else if (ISA_MIPS3) \
432 { \
433 builtin_define ("__mips=3"); \
434 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
435 } \
436 else if (ISA_MIPS4) \
437 { \
438 builtin_define ("__mips=4"); \
439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
440 } \
441 else if (ISA_MIPS32) \
442 { \
443 builtin_define ("__mips=32"); \
444 builtin_define ("__mips_isa_rev=1"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
446 } \
447 else if (ISA_MIPS32R2) \
448 { \
449 builtin_define ("__mips=32"); \
450 builtin_define ("__mips_isa_rev=2"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
452 } \
453 else if (ISA_MIPS64) \
454 { \
455 builtin_define ("__mips=64"); \
456 builtin_define ("__mips_isa_rev=1"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
458 } \
459 else if (ISA_MIPS64R2) \
460 { \
461 builtin_define ("__mips=64"); \
462 builtin_define ("__mips_isa_rev=2"); \
463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
464 } \
465 \
466 switch (mips_abi) \
467 { \
468 case ABI_32: \
469 builtin_define ("_ABIO32=1"); \
470 builtin_define ("_MIPS_SIM=_ABIO32"); \
471 break; \
472 \
473 case ABI_N32: \
474 builtin_define ("_ABIN32=2"); \
475 builtin_define ("_MIPS_SIM=_ABIN32"); \
476 break; \
477 \
478 case ABI_64: \
479 builtin_define ("_ABI64=3"); \
480 builtin_define ("_MIPS_SIM=_ABI64"); \
481 break; \
482 \
483 case ABI_O64: \
484 builtin_define ("_ABIO64=4"); \
485 builtin_define ("_MIPS_SIM=_ABIO64"); \
486 break; \
487 } \
488 \
489 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
490 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
491 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
492 builtin_define_with_int_value ("_MIPS_FPSET", \
493 32 / MAX_FPRS_PER_FMT); \
494 \
495 /* These defines reflect the ABI in use, not whether the \
496 FPU is directly accessible. */ \
497 if (TARGET_NO_FLOAT) \
498 builtin_define ("__mips_no_float"); \
499 else if (TARGET_HARD_FLOAT_ABI) \
500 builtin_define ("__mips_hard_float"); \
501 else \
502 builtin_define ("__mips_soft_float"); \
503 \
504 if (TARGET_SINGLE_FLOAT) \
505 builtin_define ("__mips_single_float"); \
506 \
507 if (TARGET_PAIRED_SINGLE_FLOAT) \
508 builtin_define ("__mips_paired_single_float"); \
509 \
510 if (mips_abs == MIPS_IEEE_754_2008) \
511 builtin_define ("__mips_abs2008"); \
512 \
513 if (mips_nan == MIPS_IEEE_754_2008) \
514 builtin_define ("__mips_nan2008"); \
515 \
516 if (TARGET_BIG_ENDIAN) \
517 { \
518 builtin_define_std ("MIPSEB"); \
519 builtin_define ("_MIPSEB"); \
520 } \
521 else \
522 { \
523 builtin_define_std ("MIPSEL"); \
524 builtin_define ("_MIPSEL"); \
525 } \
526 \
527 /* Whether calls should go through $25. The separate __PIC__ \
528 macro indicates whether abicalls code might use a GOT. */ \
529 if (TARGET_ABICALLS) \
530 builtin_define ("__mips_abicalls"); \
531 \
532 /* Whether Loongson vector modes are enabled. */ \
533 if (TARGET_LOONGSON_VECTORS) \
534 builtin_define ("__mips_loongson_vector_rev"); \
535 \
536 /* Historical Octeon macro. */ \
537 if (TARGET_OCTEON) \
538 builtin_define ("__OCTEON__"); \
539 \
540 if (TARGET_SYNCI) \
541 builtin_define ("__mips_synci"); \
542 \
543 /* Macros dependent on the C dialect. */ \
544 if (preprocessing_asm_p ()) \
545 { \
546 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
547 builtin_define ("_LANGUAGE_ASSEMBLY"); \
548 } \
549 else if (c_dialect_cxx ()) \
550 { \
551 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
552 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
553 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
554 } \
555 else \
556 { \
557 builtin_define_std ("LANGUAGE_C"); \
558 builtin_define ("_LANGUAGE_C"); \
559 } \
560 if (c_dialect_objc ()) \
561 { \
562 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
563 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
564 /* Bizarre, but retained for backwards compatibility. */ \
565 builtin_define_std ("LANGUAGE_C"); \
566 builtin_define ("_LANGUAGE_C"); \
567 } \
568 \
569 if (mips_abi == ABI_EABI) \
570 builtin_define ("__mips_eabi"); \
571 \
572 if (TARGET_CACHE_BUILTIN) \
573 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
574 } \
575 while (0)
576
577 /* Default target_flags if no switches are specified */
578
579 #ifndef TARGET_DEFAULT
580 #define TARGET_DEFAULT 0
581 #endif
582
583 #ifndef TARGET_CPU_DEFAULT
584 #define TARGET_CPU_DEFAULT 0
585 #endif
586
587 #ifndef TARGET_ENDIAN_DEFAULT
588 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
589 #endif
590
591 #ifdef IN_LIBGCC2
592 #undef TARGET_64BIT
593 /* Make this compile time constant for libgcc2 */
594 #ifdef __mips64
595 #define TARGET_64BIT 1
596 #else
597 #define TARGET_64BIT 0
598 #endif
599 #endif /* IN_LIBGCC2 */
600
601 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
602 when compiled with hardware floating point. This is because MIPS16
603 code cannot save and restore the floating-point registers, which is
604 important if in a mixed MIPS16/non-MIPS16 environment. */
605
606 #ifdef IN_LIBGCC2
607 #if __mips_hard_float
608 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
609 #endif
610 #endif /* IN_LIBGCC2 */
611
612 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
613
614 #ifndef MULTILIB_ENDIAN_DEFAULT
615 #if TARGET_ENDIAN_DEFAULT == 0
616 #define MULTILIB_ENDIAN_DEFAULT "EL"
617 #else
618 #define MULTILIB_ENDIAN_DEFAULT "EB"
619 #endif
620 #endif
621
622 #ifndef MULTILIB_ISA_DEFAULT
623 #if MIPS_ISA_DEFAULT == 1
624 #define MULTILIB_ISA_DEFAULT "mips1"
625 #elif MIPS_ISA_DEFAULT == 2
626 #define MULTILIB_ISA_DEFAULT "mips2"
627 #elif MIPS_ISA_DEFAULT == 3
628 #define MULTILIB_ISA_DEFAULT "mips3"
629 #elif MIPS_ISA_DEFAULT == 4
630 #define MULTILIB_ISA_DEFAULT "mips4"
631 #elif MIPS_ISA_DEFAULT == 32
632 #define MULTILIB_ISA_DEFAULT "mips32"
633 #elif MIPS_ISA_DEFAULT == 33
634 #define MULTILIB_ISA_DEFAULT "mips32r2"
635 #elif MIPS_ISA_DEFAULT == 64
636 #define MULTILIB_ISA_DEFAULT "mips64"
637 #elif MIPS_ISA_DEFAULT == 65
638 #define MULTILIB_ISA_DEFAULT "mips64r2"
639 #else
640 #define MULTILIB_ISA_DEFAULT "mips1"
641 #endif
642 #endif
643
644 #ifndef MIPS_ABI_DEFAULT
645 #define MIPS_ABI_DEFAULT ABI_32
646 #endif
647
648 /* Use the most portable ABI flag for the ASM specs. */
649
650 #if MIPS_ABI_DEFAULT == ABI_32
651 #define MULTILIB_ABI_DEFAULT "mabi=32"
652 #elif MIPS_ABI_DEFAULT == ABI_O64
653 #define MULTILIB_ABI_DEFAULT "mabi=o64"
654 #elif MIPS_ABI_DEFAULT == ABI_N32
655 #define MULTILIB_ABI_DEFAULT "mabi=n32"
656 #elif MIPS_ABI_DEFAULT == ABI_64
657 #define MULTILIB_ABI_DEFAULT "mabi=64"
658 #elif MIPS_ABI_DEFAULT == ABI_EABI
659 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
660 #endif
661
662 #ifndef MULTILIB_DEFAULTS
663 #define MULTILIB_DEFAULTS \
664 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
665 #endif
666
667 /* We must pass -EL to the linker by default for little endian embedded
668 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
669 linker will default to using big-endian output files. The OUTPUT_FORMAT
670 line must be in the linker script, otherwise -EB/-EL will not work. */
671
672 #ifndef ENDIAN_SPEC
673 #if TARGET_ENDIAN_DEFAULT == 0
674 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
675 #else
676 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
677 #endif
678 #endif
679
680 /* A spec condition that matches all non-mips16 -mips arguments. */
681
682 #define MIPS_ISA_LEVEL_OPTION_SPEC \
683 "mips1|mips2|mips3|mips4|mips32*|mips64*"
684
685 /* A spec condition that matches all non-mips16 architecture arguments. */
686
687 #define MIPS_ARCH_OPTION_SPEC \
688 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
689
690 /* A spec that infers a -mips argument from an -march argument,
691 or injects the default if no architecture is specified. */
692
693 #define MIPS_ISA_LEVEL_SPEC \
694 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
695 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
696 %{march=mips2|march=r6000:-mips2} \
697 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
698 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
699 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
700 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
701 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
702 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
703 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
704 |march=xlr|march=loongson3a: -mips64} \
705 %{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
706 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
707
708 /* A spec that infers a -mhard-float or -msoft-float setting from an
709 -march argument. Note that soft-float and hard-float code are not
710 link-compatible. */
711
712 #define MIPS_ARCH_FLOAT_SPEC \
713 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
714 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
715 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
716 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
717 march=*: -mhard-float}"
718
719 /* A spec condition that matches 32-bit options. It only works if
720 MIPS_ISA_LEVEL_SPEC has been applied. */
721
722 #define MIPS_32BIT_OPTION_SPEC \
723 "mips1|mips2|mips32*|mgp32"
724
725 /* Infer a -msynci setting from a -mips argument, on the assumption that
726 -msynci is desired where possible. */
727 #define MIPS_ISA_SYNCI_SPEC \
728 "%{msynci|mno-synci:;:%{mips32r2|mips64r2:-msynci;:-mno-synci}}"
729
730 #if (MIPS_ABI_DEFAULT == ABI_O64 \
731 || MIPS_ABI_DEFAULT == ABI_N32 \
732 || MIPS_ABI_DEFAULT == ABI_64)
733 #define OPT_ARCH64 "mabi=32|mgp32:;"
734 #define OPT_ARCH32 "mabi=32|mgp32"
735 #else
736 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
737 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
738 #endif
739
740 /* Support for a compile-time default CPU, et cetera. The rules are:
741 --with-arch is ignored if -march is specified or a -mips is specified
742 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
743 --with-tune is ignored if -mtune is specified; likewise
744 --with-tune-32 and --with-tune-64.
745 --with-abi is ignored if -mabi is specified.
746 --with-float is ignored if -mhard-float or -msoft-float are
747 specified.
748 --with-nan is ignored if -mnan is specified.
749 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
750 specified. */
751 #define OPTION_DEFAULT_SPECS \
752 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
753 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
754 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
755 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
756 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
757 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
758 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
759 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
760 {"fpu", "%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}" }, \
761 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
762 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
763 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
764 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
765 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
766
767 /* A spec that infers the -mdsp setting from an -march argument. */
768 #define BASE_DRIVER_SELF_SPECS \
769 "%{!mno-dsp: \
770 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
771 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
772
773 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
774
775 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
776 && ISA_HAS_COND_TRAP)
777
778 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
779
780 /* True if the ABI can only work with 64-bit integer registers. We
781 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
782 otherwise floating-point registers must also be 64-bit. */
783 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
784
785 /* Likewise for 32-bit regs. */
786 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
787
788 /* True if the file format uses 64-bit symbols. At present, this is
789 only true for n64, which uses 64-bit ELF. */
790 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
791
792 /* True if symbols are 64 bits wide. This is usually determined by
793 the ABI's file format, but it can be overridden by -msym32. Note that
794 overriding the size with -msym32 changes the ABI of relocatable objects,
795 although it doesn't change the ABI of a fully-linked object. */
796 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
797 && Pmode == DImode \
798 && !TARGET_SYM32)
799
800 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
801 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
802 || ISA_MIPS4 \
803 || ISA_MIPS64 \
804 || ISA_MIPS64R2)
805
806 /* ISA has branch likely instructions (e.g. mips2). */
807 /* Disable branchlikely for tx39 until compare rewrite. They haven't
808 been generated up to this point. */
809 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
810
811 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
812 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
813 || TARGET_MIPS5400 \
814 || TARGET_MIPS5500 \
815 || TARGET_MIPS5900 \
816 || TARGET_MIPS7000 \
817 || TARGET_MIPS9000 \
818 || TARGET_MAD \
819 || ISA_MIPS32 \
820 || ISA_MIPS32R2 \
821 || ISA_MIPS64 \
822 || ISA_MIPS64R2) \
823 && !TARGET_MIPS16)
824
825 /* ISA has a three-operand multiplication instruction. */
826 #define ISA_HAS_DMUL3 (TARGET_64BIT \
827 && TARGET_OCTEON \
828 && !TARGET_MIPS16)
829
830 /* ISA supports instructions DMULT and DMULTU. */
831 #define ISA_HAS_DMULT (TARGET_64BIT && !TARGET_MIPS5900)
832
833 /* ISA supports instructions MULT and MULTU.
834 This is always true, but the macro is needed for ISA_HAS_<D>MULT
835 in mips.md. */
836 #define ISA_HAS_MULT (1)
837
838 /* ISA supports instructions DDIV and DDIVU. */
839 #define ISA_HAS_DDIV (TARGET_64BIT && !TARGET_MIPS5900)
840
841 /* ISA supports instructions DIV and DIVU.
842 This is always true, but the macro is needed for ISA_HAS_<D>DIV
843 in mips.md. */
844 #define ISA_HAS_DIV (1)
845
846 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
847 || TARGET_LOONGSON_3A) \
848 && !TARGET_MIPS16)
849
850 /* ISA has the floating-point conditional move instructions introduced
851 in mips4. */
852 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
853 || ISA_MIPS32 \
854 || ISA_MIPS32R2 \
855 || ISA_MIPS64 \
856 || ISA_MIPS64R2) \
857 && !TARGET_MIPS5500 \
858 && !TARGET_MIPS16)
859
860 /* ISA has the integer conditional move instructions introduced in mips4 and
861 ST Loongson 2E/2F. */
862 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
863 || TARGET_MIPS5900 \
864 || TARGET_LOONGSON_2EF)
865
866 /* ISA has LDC1 and SDC1. */
867 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
868 && !TARGET_MIPS5900 \
869 && !TARGET_MIPS16)
870
871 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
872 branch on CC, and move (both FP and non-FP) on CC. */
873 #define ISA_HAS_8CC (ISA_MIPS4 \
874 || ISA_MIPS32 \
875 || ISA_MIPS32R2 \
876 || ISA_MIPS64 \
877 || ISA_MIPS64R2)
878
879 /* This is a catch all for other mips4 instructions: indexed load, the
880 FP madd and msub instructions, and the FP recip and recip sqrt
881 instructions. Note that this macro should only be used by other
882 ISA_HAS_* macros. */
883 #define ISA_HAS_FP4 ((ISA_MIPS4 \
884 || ISA_MIPS32R2 \
885 || ISA_MIPS64 \
886 || ISA_MIPS64R2) \
887 && !TARGET_MIPS16)
888
889 /* ISA has floating-point indexed load and store instructions
890 (LWXC1, LDXC1, SWXC1 and SDXC1). */
891 #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
892
893 /* ISA has paired-single instructions. */
894 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
895
896 /* ISA has conditional trap instructions. */
897 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
898 && !TARGET_MIPS16)
899
900 /* ISA has integer multiply-accumulate instructions, madd and msub. */
901 #define ISA_HAS_MADD_MSUB (ISA_MIPS32 \
902 || ISA_MIPS32R2 \
903 || ISA_MIPS64 \
904 || ISA_MIPS64R2)
905
906 /* Integer multiply-accumulate instructions should be generated. */
907 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
908
909 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
910 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
911
912 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
913 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
914
915 /* ISA has floating-point nmadd and nmsub instructions
916 'd = -((a * b) [+-] c)'. */
917 #define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4
918
919 /* ISA has floating-point nmadd and nmsub instructions
920 'c = -((a * b) [+-] c)'. */
921 #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF
922
923 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
924 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
925 doubles are stored in pairs of FPRs, so for safety's sake, we apply
926 this restriction to the MIPS IV ISA too. */
927 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
928 (((ISA_HAS_FP4 \
929 && ((MODE) == SFmode \
930 || ((TARGET_FLOAT64 \
931 || ISA_MIPS32R2 \
932 || ISA_MIPS64R2) \
933 && (MODE) == DFmode))) \
934 || (TARGET_SB1 \
935 && (MODE) == V2SFmode)) \
936 && !TARGET_MIPS16)
937
938 /* ISA has count leading zeroes/ones instruction (not implemented). */
939 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
940 || ISA_MIPS32R2 \
941 || ISA_MIPS64 \
942 || ISA_MIPS64R2) \
943 && !TARGET_MIPS16)
944
945 /* ISA has three operand multiply instructions that put
946 the high part in an accumulator: mulhi or mulhiu. */
947 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
948 || TARGET_MIPS5500 \
949 || TARGET_SR71K) \
950 && !TARGET_MIPS16)
951
952 /* ISA has three operand multiply instructions that negate the
953 result and put the result in an accumulator. */
954 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
955 || TARGET_MIPS5500 \
956 || TARGET_SR71K) \
957 && !TARGET_MIPS16)
958
959 /* ISA has three operand multiply instructions that subtract the
960 result from a 4th operand and put the result in an accumulator. */
961 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
962 || TARGET_MIPS5500 \
963 || TARGET_SR71K) \
964 && !TARGET_MIPS16)
965
966 /* ISA has three operand multiply instructions that add the result
967 to a 4th operand and put the result in an accumulator. */
968 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
969 || TARGET_MIPS4130 \
970 || TARGET_MIPS5400 \
971 || TARGET_MIPS5500 \
972 || TARGET_SR71K) \
973 && !TARGET_MIPS16)
974
975 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
976 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
977 || TARGET_MIPS4130) \
978 && !TARGET_MIPS16)
979
980 /* ISA has the "ror" (rotate right) instructions. */
981 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
982 || ISA_MIPS64R2 \
983 || TARGET_MIPS5400 \
984 || TARGET_MIPS5500 \
985 || TARGET_SR71K \
986 || TARGET_SMARTMIPS) \
987 && !TARGET_MIPS16)
988
989 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
990 64-bit targets also provide DSBH and DSHD. */
991 #define ISA_HAS_WSBH ((ISA_MIPS32R2 || ISA_MIPS64R2) \
992 && !TARGET_MIPS16)
993
994 /* ISA has data prefetch instructions. This controls use of 'pref'. */
995 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
996 || TARGET_LOONGSON_2EF \
997 || TARGET_MIPS5900 \
998 || ISA_MIPS32 \
999 || ISA_MIPS32R2 \
1000 || ISA_MIPS64 \
1001 || ISA_MIPS64R2) \
1002 && !TARGET_MIPS16)
1003
1004 /* ISA has data indexed prefetch instructions. This controls use of
1005 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1006 (prefx is a cop1x instruction, so can only be used if FP is
1007 enabled.) */
1008 #define ISA_HAS_PREFETCHX ISA_HAS_FP4
1009
1010 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1011 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1012 also requires TARGET_DOUBLE_FLOAT. */
1013 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1014
1015 /* ISA includes the MIPS32r2 seb and seh instructions. */
1016 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
1017 || ISA_MIPS64R2) \
1018 && !TARGET_MIPS16)
1019
1020 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1021 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
1022 || ISA_MIPS64R2) \
1023 && !TARGET_MIPS16)
1024
1025 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1026 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
1027 && (ISA_MIPS32R2 \
1028 || ISA_MIPS64R2))
1029
1030 /* ISA has lwxs instruction (load w/scaled index address. */
1031 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1032 && !TARGET_MIPS16)
1033
1034 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1035 #define ISA_HAS_LBX (TARGET_OCTEON2)
1036 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1037 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1038 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1039 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1040 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1041 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1042 && TARGET_64BIT)
1043
1044 /* The DSP ASE is available. */
1045 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1046
1047 /* Revision 2 of the DSP ASE is available. */
1048 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1049
1050 /* True if the result of a load is not available to the next instruction.
1051 A nop will then be needed between instructions like "lw $4,..."
1052 and "addiu $4,$4,1". */
1053 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1054 && !TARGET_MIPS3900 \
1055 && !TARGET_MIPS5900 \
1056 && !TARGET_MIPS16 \
1057 && !TARGET_MICROMIPS)
1058
1059 /* Likewise mtc1 and mfc1. */
1060 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1061 && !TARGET_MIPS5900 \
1062 && !TARGET_LOONGSON_2EF)
1063
1064 /* Likewise floating-point comparisons. */
1065 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1066 && !TARGET_MIPS5900 \
1067 && !TARGET_LOONGSON_2EF)
1068
1069 /* True if mflo and mfhi can be immediately followed by instructions
1070 which write to the HI and LO registers.
1071
1072 According to MIPS specifications, MIPS ISAs I, II, and III need
1073 (at least) two instructions between the reads of HI/LO and
1074 instructions which write them, and later ISAs do not. Contradicting
1075 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1076 the UM for the NEC Vr5000) document needing the instructions between
1077 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1078 MIPS64 and later ISAs to have the interlocks, plus any specific
1079 earlier-ISA CPUs for which CPU documentation declares that the
1080 instructions are really interlocked. */
1081 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1082 || ISA_MIPS32R2 \
1083 || ISA_MIPS64 \
1084 || ISA_MIPS64R2 \
1085 || TARGET_MIPS5500 \
1086 || TARGET_MIPS5900 \
1087 || TARGET_LOONGSON_2EF)
1088
1089 /* ISA includes synci, jr.hb and jalr.hb. */
1090 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1091 || ISA_MIPS64R2) \
1092 && !TARGET_MIPS16)
1093
1094 /* ISA includes sync. */
1095 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1096 #define GENERATE_SYNC \
1097 (target_flags_explicit & MASK_LLSC \
1098 ? TARGET_LLSC && !TARGET_MIPS16 \
1099 : ISA_HAS_SYNC)
1100
1101 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1102 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1103 instructions. */
1104 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1105 #define GENERATE_LL_SC \
1106 (target_flags_explicit & MASK_LLSC \
1107 ? TARGET_LLSC && !TARGET_MIPS16 \
1108 : ISA_HAS_LL_SC)
1109
1110 #define ISA_HAS_SWAP (TARGET_XLP)
1111 #define ISA_HAS_LDADD (TARGET_XLP)
1112
1113 /* ISA includes the baddu instruction. */
1114 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1115
1116 /* ISA includes the bbit* instructions. */
1117 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1118
1119 /* ISA includes the cins instruction. */
1120 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1121
1122 /* ISA includes the exts instruction. */
1123 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1124
1125 /* ISA includes the seq and sne instructions. */
1126 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1127
1128 /* ISA includes the pop instruction. */
1129 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1130
1131 /* The CACHE instruction is available in non-MIPS16 code. */
1132 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1133
1134 /* The CACHE instruction is available. */
1135 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1136 \f
1137 /* Tell collect what flags to pass to nm. */
1138 #ifndef NM_FLAGS
1139 #define NM_FLAGS "-Bn"
1140 #endif
1141
1142 \f
1143 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1144 the assembler. It may be overridden by subtargets.
1145
1146 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1147 COFF debugging info. */
1148
1149 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1150 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1151 %{g} %{g0} %{g1} %{g2} %{g3} \
1152 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1153 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1154 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1155 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1156 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1157 #endif
1158
1159 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1160 overridden by subtargets. */
1161
1162 #ifndef SUBTARGET_ASM_SPEC
1163 #define SUBTARGET_ASM_SPEC ""
1164 #endif
1165
1166 #undef ASM_SPEC
1167 #define ASM_SPEC "\
1168 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1169 %{mips32*} %{mips64*} \
1170 %{mips16} %{mno-mips16:-no-mips16} \
1171 %{mmicromips} %{mno-micromips} \
1172 %{mips3d} %{mno-mips3d:-no-mips3d} \
1173 %{mdmx} %{mno-mdmx:-no-mdmx} \
1174 %{mdsp} %{mno-dsp} \
1175 %{mdspr2} %{mno-dspr2} \
1176 %{mmcu} %{mno-mcu} \
1177 %{meva} %{mno-eva} \
1178 %{msmartmips} %{mno-smartmips} \
1179 %{mmt} %{mno-mt} \
1180 %{mfix-rm7000} %{mno-fix-rm7000} \
1181 %{mfix-vr4120} %{mfix-vr4130} \
1182 %{mfix-24k} \
1183 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1184 %(subtarget_asm_debugging_spec) \
1185 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1186 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1187 %{mfp32} %{mfp64} %{mnan=*} \
1188 %{mshared} %{mno-shared} \
1189 %{msym32} %{mno-sym32} \
1190 %{mtune=*} \
1191 %(subtarget_asm_spec)"
1192
1193 /* Extra switches sometimes passed to the linker. */
1194
1195 #ifndef LINK_SPEC
1196 #define LINK_SPEC "\
1197 %(endian_spec) \
1198 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1199 %{shared}"
1200 #endif /* LINK_SPEC defined */
1201
1202
1203 /* Specs for the compiler proper */
1204
1205 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1206 overridden by subtargets. */
1207 #ifndef SUBTARGET_CC1_SPEC
1208 #define SUBTARGET_CC1_SPEC ""
1209 #endif
1210
1211 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1212
1213 #undef CC1_SPEC
1214 #define CC1_SPEC "\
1215 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1216 %(subtarget_cc1_spec)"
1217
1218 /* Preprocessor specs. */
1219
1220 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1221 overridden by subtargets. */
1222 #ifndef SUBTARGET_CPP_SPEC
1223 #define SUBTARGET_CPP_SPEC ""
1224 #endif
1225
1226 #define CPP_SPEC "%(subtarget_cpp_spec)"
1227
1228 /* This macro defines names of additional specifications to put in the specs
1229 that can be used in various specifications like CC1_SPEC. Its definition
1230 is an initializer with a subgrouping for each command option.
1231
1232 Each subgrouping contains a string constant, that defines the
1233 specification name, and a string constant that used by the GCC driver
1234 program.
1235
1236 Do not define this macro if it does not need to do anything. */
1237
1238 #define EXTRA_SPECS \
1239 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1240 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1241 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1242 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1243 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1244 { "endian_spec", ENDIAN_SPEC }, \
1245 SUBTARGET_EXTRA_SPECS
1246
1247 #ifndef SUBTARGET_EXTRA_SPECS
1248 #define SUBTARGET_EXTRA_SPECS
1249 #endif
1250 \f
1251 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1252 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1253
1254 #ifndef PREFERRED_DEBUGGING_TYPE
1255 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1256 #endif
1257
1258 /* The size of DWARF addresses should be the same as the size of symbols
1259 in the target file format. They shouldn't depend on things like -msym32,
1260 because many DWARF consumers do not allow the mixture of address sizes
1261 that one would then get from linking -msym32 code with -msym64 code.
1262
1263 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1264 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1265 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1266
1267 /* By default, turn on GDB extensions. */
1268 #define DEFAULT_GDB_EXTENSIONS 1
1269
1270 /* Local compiler-generated symbols must have a prefix that the assembler
1271 understands. By default, this is $, although some targets (e.g.,
1272 NetBSD-ELF) need to override this. */
1273
1274 #ifndef LOCAL_LABEL_PREFIX
1275 #define LOCAL_LABEL_PREFIX "$"
1276 #endif
1277
1278 /* By default on the mips, external symbols do not have an underscore
1279 prepended, but some targets (e.g., NetBSD) require this. */
1280
1281 #ifndef USER_LABEL_PREFIX
1282 #define USER_LABEL_PREFIX ""
1283 #endif
1284
1285 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1286 since the length can run past this up to a continuation point. */
1287 #undef DBX_CONTIN_LENGTH
1288 #define DBX_CONTIN_LENGTH 1500
1289
1290 /* How to renumber registers for dbx and gdb. */
1291 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1292
1293 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1294 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1295
1296 /* The DWARF 2 CFA column which tracks the return address. */
1297 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1298
1299 /* Before the prologue, RA lives in r31. */
1300 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1301
1302 /* Describe how we implement __builtin_eh_return. */
1303 #define EH_RETURN_DATA_REGNO(N) \
1304 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1305
1306 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1307
1308 #define EH_USES(N) mips_eh_uses (N)
1309
1310 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1311 The default for this in 64-bit mode is 8, which causes problems with
1312 SFmode register saves. */
1313 #define DWARF_CIE_DATA_ALIGNMENT -4
1314
1315 /* Correct the offset of automatic variables and arguments. Note that
1316 the MIPS debug format wants all automatic variables and arguments
1317 to be in terms of the virtual frame pointer (stack pointer before
1318 any adjustment in the function), while the MIPS 3.0 linker wants
1319 the frame pointer to be the stack pointer after the initial
1320 adjustment. */
1321
1322 #define DEBUGGER_AUTO_OFFSET(X) \
1323 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1324 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1325 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1326 \f
1327 /* Target machine storage layout */
1328
1329 #define BITS_BIG_ENDIAN 0
1330 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1331 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1332
1333 #define MAX_BITS_PER_WORD 64
1334
1335 /* Width of a word, in units (bytes). */
1336 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1337 #ifndef IN_LIBGCC2
1338 #define MIN_UNITS_PER_WORD 4
1339 #endif
1340
1341 /* For MIPS, width of a floating point register. */
1342 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1343
1344 /* The number of consecutive floating-point registers needed to store the
1345 largest format supported by the FPU. */
1346 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1347
1348 /* The number of consecutive floating-point registers needed to store the
1349 smallest format supported by the FPU. */
1350 #define MIN_FPRS_PER_FMT \
1351 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1352 ? 1 : MAX_FPRS_PER_FMT)
1353
1354 /* The largest size of value that can be held in floating-point
1355 registers and moved with a single instruction. */
1356 #define UNITS_PER_HWFPVALUE \
1357 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1358
1359 /* The largest size of value that can be held in floating-point
1360 registers. */
1361 #define UNITS_PER_FPVALUE \
1362 (TARGET_SOFT_FLOAT_ABI ? 0 \
1363 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1364 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1365
1366 /* The number of bytes in a double. */
1367 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1368
1369 /* Set the sizes of the core types. */
1370 #define SHORT_TYPE_SIZE 16
1371 #define INT_TYPE_SIZE 32
1372 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1373 #define LONG_LONG_TYPE_SIZE 64
1374
1375 #define FLOAT_TYPE_SIZE 32
1376 #define DOUBLE_TYPE_SIZE 64
1377 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1378
1379 /* Define the sizes of fixed-point types. */
1380 #define SHORT_FRACT_TYPE_SIZE 8
1381 #define FRACT_TYPE_SIZE 16
1382 #define LONG_FRACT_TYPE_SIZE 32
1383 #define LONG_LONG_FRACT_TYPE_SIZE 64
1384
1385 #define SHORT_ACCUM_TYPE_SIZE 16
1386 #define ACCUM_TYPE_SIZE 32
1387 #define LONG_ACCUM_TYPE_SIZE 64
1388 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1389 doesn't support 128-bit integers for MIPS32 currently. */
1390 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1391
1392 /* long double is not a fixed mode, but the idea is that, if we
1393 support long double, we also want a 128-bit integer type. */
1394 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1395
1396 #ifdef IN_LIBGCC2
1397 #if ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1398 || (defined _ABI64 && _MIPS_SIM == _ABI64))
1399 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1400 # else
1401 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1402 # endif
1403 #endif
1404
1405 /* Width in bits of a pointer. */
1406 #ifndef POINTER_SIZE
1407 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1408 #endif
1409
1410 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1411 #define PARM_BOUNDARY BITS_PER_WORD
1412
1413 /* Allocation boundary (in *bits*) for the code of a function. */
1414 #define FUNCTION_BOUNDARY 32
1415
1416 /* Alignment of field after `int : 0' in a structure. */
1417 #define EMPTY_FIELD_BOUNDARY 32
1418
1419 /* Every structure's size must be a multiple of this. */
1420 /* 8 is observed right on a DECstation and on riscos 4.02. */
1421 #define STRUCTURE_SIZE_BOUNDARY 8
1422
1423 /* There is no point aligning anything to a rounder boundary than this. */
1424 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1425
1426 /* All accesses must be aligned. */
1427 #define STRICT_ALIGNMENT 1
1428
1429 /* Define this if you wish to imitate the way many other C compilers
1430 handle alignment of bitfields and the structures that contain
1431 them.
1432
1433 The behavior is that the type written for a bit-field (`int',
1434 `short', or other integer type) imposes an alignment for the
1435 entire structure, as if the structure really did contain an
1436 ordinary field of that type. In addition, the bit-field is placed
1437 within the structure so that it would fit within such a field,
1438 not crossing a boundary for it.
1439
1440 Thus, on most machines, a bit-field whose type is written as `int'
1441 would not cross a four-byte boundary, and would force four-byte
1442 alignment for the whole structure. (The alignment used may not
1443 be four bytes; it is controlled by the other alignment
1444 parameters.)
1445
1446 If the macro is defined, its definition should be a C expression;
1447 a nonzero value for the expression enables this behavior. */
1448
1449 #define PCC_BITFIELD_TYPE_MATTERS 1
1450
1451 /* If defined, a C expression to compute the alignment given to a
1452 constant that is being placed in memory. CONSTANT is the constant
1453 and ALIGN is the alignment that the object would ordinarily have.
1454 The value of this macro is used instead of that alignment to align
1455 the object.
1456
1457 If this macro is not defined, then ALIGN is used.
1458
1459 The typical use of this macro is to increase alignment for string
1460 constants to be word aligned so that `strcpy' calls that copy
1461 constants can be done inline. */
1462
1463 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1464 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1465 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1466
1467 /* If defined, a C expression to compute the alignment for a static
1468 variable. TYPE is the data type, and ALIGN is the alignment that
1469 the object would ordinarily have. The value of this macro is used
1470 instead of that alignment to align the object.
1471
1472 If this macro is not defined, then ALIGN is used.
1473
1474 One use of this macro is to increase alignment of medium-size
1475 data to make it all fit in fewer cache lines. Another is to
1476 cause character arrays to be word-aligned so that `strcpy' calls
1477 that copy constants to character arrays can be done inline. */
1478
1479 #undef DATA_ALIGNMENT
1480 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1481 ((((ALIGN) < BITS_PER_WORD) \
1482 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1483 || TREE_CODE (TYPE) == UNION_TYPE \
1484 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1485
1486 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1487 character arrays to be word-aligned so that `strcpy' calls that copy
1488 constants to character arrays can be done inline, and 'strcmp' can be
1489 optimised to use word loads. */
1490 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1491 DATA_ALIGNMENT (TYPE, ALIGN)
1492
1493 #define PAD_VARARGS_DOWN \
1494 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1495
1496 /* Define if operations between registers always perform the operation
1497 on the full register even if a narrower mode is specified. */
1498 #define WORD_REGISTER_OPERATIONS
1499
1500 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1501 moves. All other references are zero extended. */
1502 #define LOAD_EXTEND_OP(MODE) \
1503 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1504 ? SIGN_EXTEND : ZERO_EXTEND)
1505
1506 /* Define this macro if it is advisable to hold scalars in registers
1507 in a wider mode than that declared by the program. In such cases,
1508 the value is constrained to be within the bounds of the declared
1509 type, but kept valid in the wider mode. The signedness of the
1510 extension may differ from that of the type. */
1511
1512 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1513 if (GET_MODE_CLASS (MODE) == MODE_INT \
1514 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1515 { \
1516 if ((MODE) == SImode) \
1517 (UNSIGNEDP) = 0; \
1518 (MODE) = Pmode; \
1519 }
1520
1521 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1522 Extensions of pointers to word_mode must be signed. */
1523 #define POINTERS_EXTEND_UNSIGNED false
1524
1525 /* Define if loading short immediate values into registers sign extends. */
1526 #define SHORT_IMMEDIATES_SIGN_EXTEND
1527
1528 /* The [d]clz instructions have the natural values at 0. */
1529
1530 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1531 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1532 \f
1533 /* Standard register usage. */
1534
1535 /* Number of hardware registers. We have:
1536
1537 - 32 integer registers
1538 - 32 floating point registers
1539 - 8 condition code registers
1540 - 2 accumulator registers (hi and lo)
1541 - 32 registers each for coprocessors 0, 2 and 3
1542 - 4 fake registers:
1543 - ARG_POINTER_REGNUM
1544 - FRAME_POINTER_REGNUM
1545 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1546 - CPRESTORE_SLOT_REGNUM
1547 - 2 dummy entries that were used at various times in the past.
1548 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1549 - 6 DSP control registers */
1550
1551 #define FIRST_PSEUDO_REGISTER 188
1552
1553 /* By default, fix the kernel registers ($26 and $27), the global
1554 pointer ($28) and the stack pointer ($29). This can change
1555 depending on the command-line options.
1556
1557 Regarding coprocessor registers: without evidence to the contrary,
1558 it's best to assume that each coprocessor register has a unique
1559 use. This can be overridden, in, e.g., mips_option_override or
1560 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1561 inappropriate for a particular target. */
1562
1563 #define FIXED_REGISTERS \
1564 { \
1565 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1566 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1567 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1568 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1569 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1570 /* COP0 registers */ \
1571 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1573 /* COP2 registers */ \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1576 /* COP3 registers */ \
1577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1578 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1579 /* 6 DSP accumulator registers & 6 control registers */ \
1580 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1581 }
1582
1583
1584 /* Set up this array for o32 by default.
1585
1586 Note that we don't mark $31 as a call-clobbered register. The idea is
1587 that it's really the call instructions themselves which clobber $31.
1588 We don't care what the called function does with it afterwards.
1589
1590 This approach makes it easier to implement sibcalls. Unlike normal
1591 calls, sibcalls don't clobber $31, so the register reaches the
1592 called function in tact. EPILOGUE_USES says that $31 is useful
1593 to the called function. */
1594
1595 #define CALL_USED_REGISTERS \
1596 { \
1597 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1598 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1599 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1600 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1601 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1602 /* COP0 registers */ \
1603 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1604 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1605 /* COP2 registers */ \
1606 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1607 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1608 /* COP3 registers */ \
1609 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1610 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1611 /* 6 DSP accumulator registers & 6 control registers */ \
1612 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1613 }
1614
1615
1616 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1617
1618 #define CALL_REALLY_USED_REGISTERS \
1619 { /* General registers. */ \
1620 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1621 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1622 /* Floating-point registers. */ \
1623 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1624 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1625 /* Others. */ \
1626 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1627 /* COP0 registers */ \
1628 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1629 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1630 /* COP2 registers */ \
1631 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1632 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1633 /* COP3 registers */ \
1634 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1635 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1636 /* 6 DSP accumulator registers & 6 control registers */ \
1637 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1638 }
1639
1640 /* Internal macros to classify a register number as to whether it's a
1641 general purpose register, a floating point register, a
1642 multiply/divide register, or a status register. */
1643
1644 #define GP_REG_FIRST 0
1645 #define GP_REG_LAST 31
1646 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1647 #define GP_DBX_FIRST 0
1648 #define K0_REG_NUM (GP_REG_FIRST + 26)
1649 #define K1_REG_NUM (GP_REG_FIRST + 27)
1650 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1651
1652 #define FP_REG_FIRST 32
1653 #define FP_REG_LAST 63
1654 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1655 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1656
1657 #define MD_REG_FIRST 64
1658 #define MD_REG_LAST 65
1659 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1660 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1661
1662 /* The DWARF 2 CFA column which tracks the return address from a
1663 signal handler context. This means that to maintain backwards
1664 compatibility, no hard register can be assigned this column if it
1665 would need to be handled by the DWARF unwinder. */
1666 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1667
1668 #define ST_REG_FIRST 67
1669 #define ST_REG_LAST 74
1670 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1671
1672
1673 /* FIXME: renumber. */
1674 #define COP0_REG_FIRST 80
1675 #define COP0_REG_LAST 111
1676 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1677
1678 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1679 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1680 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1681
1682 #define COP2_REG_FIRST 112
1683 #define COP2_REG_LAST 143
1684 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1685
1686 #define COP3_REG_FIRST 144
1687 #define COP3_REG_LAST 175
1688 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1689
1690 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1691 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1692 #define ALL_COP_REG_LAST COP3_REG_LAST
1693 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1694
1695 #define DSP_ACC_REG_FIRST 176
1696 #define DSP_ACC_REG_LAST 181
1697 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1698
1699 #define AT_REGNUM (GP_REG_FIRST + 1)
1700 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1701 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1702
1703 /* A few bitfield locations for the coprocessor registers. */
1704 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1705 the cause register for the EIC interrupt mode. */
1706 #define CAUSE_IPL 10
1707 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1708 #define SR_IPL 10
1709 /* Exception Level is at bit 1 of the status register. */
1710 #define SR_EXL 1
1711 /* Interrupt Enable is at bit 0 of the status register. */
1712 #define SR_IE 0
1713
1714 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1715 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1716 should be used instead. */
1717 #define FPSW_REGNUM ST_REG_FIRST
1718
1719 #define GP_REG_P(REGNO) \
1720 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1721 #define M16_REG_P(REGNO) \
1722 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1723 #define M16STORE_REG_P(REGNO) \
1724 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1725 #define FP_REG_P(REGNO) \
1726 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1727 #define MD_REG_P(REGNO) \
1728 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1729 #define ST_REG_P(REGNO) \
1730 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1731 #define COP0_REG_P(REGNO) \
1732 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1733 #define COP2_REG_P(REGNO) \
1734 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1735 #define COP3_REG_P(REGNO) \
1736 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1737 #define ALL_COP_REG_P(REGNO) \
1738 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1739 /* Test if REGNO is one of the 6 new DSP accumulators. */
1740 #define DSP_ACC_REG_P(REGNO) \
1741 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1742 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1743 #define ACC_REG_P(REGNO) \
1744 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1745
1746 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1747
1748 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1749 to initialize the mips16 gp pseudo register. */
1750 #define CONST_GP_P(X) \
1751 (GET_CODE (X) == CONST \
1752 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1753 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1754
1755 /* Return coprocessor number from register number. */
1756
1757 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1758 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1759 : COP3_REG_P (REGNO) ? '3' : '?')
1760
1761
1762 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1763
1764 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1765 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1766
1767 #define MODES_TIEABLE_P mips_modes_tieable_p
1768
1769 /* Register to use for pushing function arguments. */
1770 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1771
1772 /* These two registers don't really exist: they get eliminated to either
1773 the stack or hard frame pointer. */
1774 #define ARG_POINTER_REGNUM 77
1775 #define FRAME_POINTER_REGNUM 78
1776
1777 /* $30 is not available on the mips16, so we use $17 as the frame
1778 pointer. */
1779 #define HARD_FRAME_POINTER_REGNUM \
1780 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1781
1782 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1783 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1784
1785 /* Register in which static-chain is passed to a function. */
1786 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1787
1788 /* Registers used as temporaries in prologue/epilogue code:
1789
1790 - If a MIPS16 PIC function needs access to _gp, it first loads
1791 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1792
1793 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1794 register. The register must not conflict with MIPS16_PIC_TEMP.
1795
1796 - If we aren't generating MIPS16 code, the prologue can also use
1797 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1798
1799 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1800 register.
1801
1802 If we're generating MIPS16 code, these registers must come from the
1803 core set of 8. The prologue registers mustn't conflict with any
1804 incoming arguments, the static chain pointer, or the frame pointer.
1805 The epilogue temporary mustn't conflict with the return registers,
1806 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1807 or the EH data registers.
1808
1809 If we're generating interrupt handlers, we use K0 as a temporary register
1810 in prologue/epilogue code. */
1811
1812 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1813 #define MIPS_PROLOGUE_TEMP_REGNUM \
1814 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1815 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1816 (TARGET_MIPS16 \
1817 ? (gcc_unreachable (), INVALID_REGNUM) \
1818 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1819 #define MIPS_EPILOGUE_TEMP_REGNUM \
1820 (cfun->machine->interrupt_handler_p \
1821 ? K0_REG_NUM \
1822 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1823
1824 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1825 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1826 #define MIPS_PROLOGUE_TEMP2(MODE) \
1827 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1828 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1829
1830 /* Define this macro if it is as good or better to call a constant
1831 function address than to call an address kept in a register. */
1832 #define NO_FUNCTION_CSE 1
1833
1834 /* The ABI-defined global pointer. Sometimes we use a different
1835 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1836 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1837
1838 /* We normally use $28 as the global pointer. However, when generating
1839 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1840 register instead. They can then avoid saving and restoring $28
1841 and perhaps avoid using a frame at all.
1842
1843 When a leaf function uses something other than $28, mips_expand_prologue
1844 will modify pic_offset_table_rtx in place. Take the register number
1845 from there after reload. */
1846 #define PIC_OFFSET_TABLE_REGNUM \
1847 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1848 \f
1849 /* Define the classes of registers for register constraints in the
1850 machine description. Also define ranges of constants.
1851
1852 One of the classes must always be named ALL_REGS and include all hard regs.
1853 If there is more than one class, another class must be named NO_REGS
1854 and contain no registers.
1855
1856 The name GENERAL_REGS must be the name of a class (or an alias for
1857 another name such as ALL_REGS). This is the class of registers
1858 that is allowed by "g" or "r" in a register constraint.
1859 Also, registers outside this class are allocated only when
1860 instructions express preferences for them.
1861
1862 The classes must be numbered in nondecreasing order; that is,
1863 a larger-numbered class must never be contained completely
1864 in a smaller-numbered class.
1865
1866 For any two classes, it is very desirable that there be another
1867 class that represents their union. */
1868
1869 enum reg_class
1870 {
1871 NO_REGS, /* no registers in set */
1872 M16_REGS, /* mips16 directly accessible registers */
1873 T_REG, /* mips16 T register ($24) */
1874 M16_T_REGS, /* mips16 registers plus T register */
1875 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1876 V1_REG, /* Register $v1 ($3) used for TLS access. */
1877 LEA_REGS, /* Every GPR except $25 */
1878 GR_REGS, /* integer registers */
1879 FP_REGS, /* floating point registers */
1880 MD0_REG, /* first multiply/divide register */
1881 MD1_REG, /* second multiply/divide register */
1882 MD_REGS, /* multiply/divide registers (hi/lo) */
1883 COP0_REGS, /* generic coprocessor classes */
1884 COP2_REGS,
1885 COP3_REGS,
1886 ST_REGS, /* status registers (fp status) */
1887 DSP_ACC_REGS, /* DSP accumulator registers */
1888 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1889 FRAME_REGS, /* $arg and $frame */
1890 GR_AND_MD0_REGS, /* union classes */
1891 GR_AND_MD1_REGS,
1892 GR_AND_MD_REGS,
1893 GR_AND_ACC_REGS,
1894 ALL_REGS, /* all registers */
1895 LIM_REG_CLASSES /* max value + 1 */
1896 };
1897
1898 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1899
1900 #define GENERAL_REGS GR_REGS
1901
1902 /* An initializer containing the names of the register classes as C
1903 string constants. These names are used in writing some of the
1904 debugging dumps. */
1905
1906 #define REG_CLASS_NAMES \
1907 { \
1908 "NO_REGS", \
1909 "M16_REGS", \
1910 "T_REG", \
1911 "M16_T_REGS", \
1912 "PIC_FN_ADDR_REG", \
1913 "V1_REG", \
1914 "LEA_REGS", \
1915 "GR_REGS", \
1916 "FP_REGS", \
1917 "MD0_REG", \
1918 "MD1_REG", \
1919 "MD_REGS", \
1920 /* coprocessor registers */ \
1921 "COP0_REGS", \
1922 "COP2_REGS", \
1923 "COP3_REGS", \
1924 "ST_REGS", \
1925 "DSP_ACC_REGS", \
1926 "ACC_REGS", \
1927 "FRAME_REGS", \
1928 "GR_AND_MD0_REGS", \
1929 "GR_AND_MD1_REGS", \
1930 "GR_AND_MD_REGS", \
1931 "GR_AND_ACC_REGS", \
1932 "ALL_REGS" \
1933 }
1934
1935 /* An initializer containing the contents of the register classes,
1936 as integers which are bit masks. The Nth integer specifies the
1937 contents of class N. The way the integer MASK is interpreted is
1938 that register R is in the class if `MASK & (1 << R)' is 1.
1939
1940 When the machine has more than 32 registers, an integer does not
1941 suffice. Then the integers are replaced by sub-initializers,
1942 braced groupings containing several integers. Each
1943 sub-initializer must be suitable as an initializer for the type
1944 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1945
1946 #define REG_CLASS_CONTENTS \
1947 { \
1948 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1949 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1950 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1951 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1952 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1953 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1954 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1955 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1956 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1957 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1958 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1959 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1960 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1961 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1962 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1963 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1964 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1965 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1966 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1967 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1968 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1969 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1970 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1971 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1972 }
1973
1974
1975 /* A C expression whose value is a register class containing hard
1976 register REGNO. In general there is more that one such class;
1977 choose a class which is "minimal", meaning that no smaller class
1978 also contains the register. */
1979
1980 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1981
1982 /* A macro whose definition is the name of the class to which a
1983 valid base register must belong. A base register is one used in
1984 an address which is the register value plus a displacement. */
1985
1986 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1987
1988 /* A macro whose definition is the name of the class to which a
1989 valid index register must belong. An index register is one used
1990 in an address where its value is either multiplied by a scale
1991 factor or added to another register (as well as added to a
1992 displacement). */
1993
1994 #define INDEX_REG_CLASS NO_REGS
1995
1996 /* We generally want to put call-clobbered registers ahead of
1997 call-saved ones. (IRA expects this.) */
1998
1999 #define REG_ALLOC_ORDER \
2000 { /* Accumulator registers. When GPRs and accumulators have equal \
2001 cost, we generally prefer to use accumulators. For example, \
2002 a division of multiplication result is better allocated to LO, \
2003 so that we put the MFLO at the point of use instead of at the \
2004 point of definition. It's also needed if we're to take advantage \
2005 of the extra accumulators available with -mdspr2. In some cases, \
2006 it can also help to reduce register pressure. */ \
2007 64, 65,176,177,178,179,180,181, \
2008 /* Call-clobbered GPRs. */ \
2009 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2010 24, 25, 31, \
2011 /* The global pointer. This is call-clobbered for o32 and o64 \
2012 abicalls, call-saved for n32 and n64 abicalls, and a program \
2013 invariant otherwise. Putting it between the call-clobbered \
2014 and call-saved registers should cope with all eventualities. */ \
2015 28, \
2016 /* Call-saved GPRs. */ \
2017 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2018 /* GPRs that can never be exposed to the register allocator. */ \
2019 0, 26, 27, 29, \
2020 /* Call-clobbered FPRs. */ \
2021 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2022 48, 49, 50, 51, \
2023 /* FPRs that are usually call-saved. The odd ones are actually \
2024 call-clobbered for n32, but listing them ahead of the even \
2025 registers might encourage the register allocator to fragment \
2026 the available FPR pairs. We need paired FPRs to store long \
2027 doubles, so it isn't clear that using a different order \
2028 for n32 would be a win. */ \
2029 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2030 /* None of the remaining classes have defined call-saved \
2031 registers. */ \
2032 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2033 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2034 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2035 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2036 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2037 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2038 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2039 182,183,184,185,186,187 \
2040 }
2041
2042 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
2043 to be rearranged based on a particular function. On the mips16, we
2044 want to allocate $24 (T_REG) before other registers for
2045 instructions for which it is possible. */
2046
2047 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2048
2049 /* True if VALUE is an unsigned 6-bit number. */
2050
2051 #define UIMM6_OPERAND(VALUE) \
2052 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2053
2054 /* True if VALUE is a signed 10-bit number. */
2055
2056 #define IMM10_OPERAND(VALUE) \
2057 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2058
2059 /* True if VALUE is a signed 16-bit number. */
2060
2061 #define SMALL_OPERAND(VALUE) \
2062 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2063
2064 /* True if VALUE is an unsigned 16-bit number. */
2065
2066 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2067 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2068
2069 /* True if VALUE can be loaded into a register using LUI. */
2070
2071 #define LUI_OPERAND(VALUE) \
2072 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2073 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2074
2075 /* Return a value X with the low 16 bits clear, and such that
2076 VALUE - X is a signed 16-bit value. */
2077
2078 #define CONST_HIGH_PART(VALUE) \
2079 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2080
2081 #define CONST_LOW_PART(VALUE) \
2082 ((VALUE) - CONST_HIGH_PART (VALUE))
2083
2084 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2085 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2086 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2087 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2088
2089 /* The HI and LO registers can only be reloaded via the general
2090 registers. Condition code registers can only be loaded to the
2091 general registers, and from the floating point registers. */
2092
2093 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2094 mips_secondary_reload_class (CLASS, MODE, X, true)
2095 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2096 mips_secondary_reload_class (CLASS, MODE, X, false)
2097
2098 /* Return the maximum number of consecutive registers
2099 needed to represent mode MODE in a register of class CLASS. */
2100
2101 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2102
2103 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2104 mips_cannot_change_mode_class (FROM, TO, CLASS)
2105 \f
2106 /* Stack layout; function entry, exit and calling. */
2107
2108 #define STACK_GROWS_DOWNWARD
2109
2110 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2111
2112 /* Size of the area allocated in the frame to save the GP. */
2113
2114 #define MIPS_GP_SAVE_AREA_SIZE \
2115 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2116
2117 /* The offset of the first local variable from the frame pointer. See
2118 mips_compute_frame_info for details about the frame layout. */
2119
2120 #define STARTING_FRAME_OFFSET \
2121 (FRAME_GROWS_DOWNWARD \
2122 ? 0 \
2123 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2124
2125 #define RETURN_ADDR_RTX mips_return_addr
2126
2127 /* Mask off the MIPS16 ISA bit in unwind addresses.
2128
2129 The reason for this is a little subtle. When unwinding a call,
2130 we are given the call's return address, which on most targets
2131 is the address of the following instruction. However, what we
2132 actually want to find is the EH region for the call itself.
2133 The target-independent unwind code therefore searches for "RA - 1".
2134
2135 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2136 RA - 1 is therefore the real (even-valued) start of the return
2137 instruction. EH region labels are usually odd-valued MIPS16 symbols
2138 too, so a search for an even address within a MIPS16 region would
2139 usually work.
2140
2141 However, there is an exception. If the end of an EH region is also
2142 the end of a function, the end label is allowed to be even. This is
2143 necessary because a following non-MIPS16 function may also need EH
2144 information for its first instruction.
2145
2146 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2147 non-ISA-encoded address. This probably isn't ideal, but it is
2148 the traditional (legacy) behavior. It is therefore only safe
2149 to search MIPS EH regions for an _odd-valued_ address.
2150
2151 Masking off the ISA bit means that the target-independent code
2152 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2153 #define MASK_RETURN_ADDR GEN_INT (-2)
2154
2155
2156 /* Similarly, don't use the least-significant bit to tell pointers to
2157 code from vtable index. */
2158
2159 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2160
2161 /* The eliminations to $17 are only used for mips16 code. See the
2162 definition of HARD_FRAME_POINTER_REGNUM. */
2163
2164 #define ELIMINABLE_REGS \
2165 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2166 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2167 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2168 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2169 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2170 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2171
2172 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2173 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2174
2175 /* Allocate stack space for arguments at the beginning of each function. */
2176 #define ACCUMULATE_OUTGOING_ARGS 1
2177
2178 /* The argument pointer always points to the first argument. */
2179 #define FIRST_PARM_OFFSET(FNDECL) 0
2180
2181 /* o32 and o64 reserve stack space for all argument registers. */
2182 #define REG_PARM_STACK_SPACE(FNDECL) \
2183 (TARGET_OLDABI \
2184 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2185 : 0)
2186
2187 /* Define this if it is the responsibility of the caller to
2188 allocate the area reserved for arguments passed in registers.
2189 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2190 of this macro is to determine whether the space is included in
2191 `crtl->outgoing_args_size'. */
2192 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2193
2194 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2195 \f
2196 /* Symbolic macros for the registers used to return integer and floating
2197 point values. */
2198
2199 #define GP_RETURN (GP_REG_FIRST + 2)
2200 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2201
2202 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2203
2204 /* Symbolic macros for the first/last argument registers. */
2205
2206 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2207 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2208 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2209 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2210
2211 /* 1 if N is a possible register number for function argument passing.
2212 We have no FP argument registers when soft-float. When FP registers
2213 are 32 bits, we can't directly reference the odd numbered ones. */
2214
2215 #define FUNCTION_ARG_REGNO_P(N) \
2216 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2217 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2218 && !fixed_regs[N])
2219 \f
2220 /* This structure has to cope with two different argument allocation
2221 schemes. Most MIPS ABIs view the arguments as a structure, of which
2222 the first N words go in registers and the rest go on the stack. If I
2223 < N, the Ith word might go in Ith integer argument register or in a
2224 floating-point register. For these ABIs, we only need to remember
2225 the offset of the current argument into the structure.
2226
2227 The EABI instead allocates the integer and floating-point arguments
2228 separately. The first N words of FP arguments go in FP registers,
2229 the rest go on the stack. Likewise, the first N words of the other
2230 arguments go in integer registers, and the rest go on the stack. We
2231 need to maintain three counts: the number of integer registers used,
2232 the number of floating-point registers used, and the number of words
2233 passed on the stack.
2234
2235 We could keep separate information for the two ABIs (a word count for
2236 the standard ABIs, and three separate counts for the EABI). But it
2237 seems simpler to view the standard ABIs as forms of EABI that do not
2238 allocate floating-point registers.
2239
2240 So for the standard ABIs, the first N words are allocated to integer
2241 registers, and mips_function_arg decides on an argument-by-argument
2242 basis whether that argument should really go in an integer register,
2243 or in a floating-point one. */
2244
2245 typedef struct mips_args {
2246 /* Always true for varargs functions. Otherwise true if at least
2247 one argument has been passed in an integer register. */
2248 int gp_reg_found;
2249
2250 /* The number of arguments seen so far. */
2251 unsigned int arg_number;
2252
2253 /* The number of integer registers used so far. For all ABIs except
2254 EABI, this is the number of words that have been added to the
2255 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2256 unsigned int num_gprs;
2257
2258 /* For EABI, the number of floating-point registers used so far. */
2259 unsigned int num_fprs;
2260
2261 /* The number of words passed on the stack. */
2262 unsigned int stack_words;
2263
2264 /* On the mips16, we need to keep track of which floating point
2265 arguments were passed in general registers, but would have been
2266 passed in the FP regs if this were a 32-bit function, so that we
2267 can move them to the FP regs if we wind up calling a 32-bit
2268 function. We record this information in fp_code, encoded in base
2269 four. A zero digit means no floating point argument, a one digit
2270 means an SFmode argument, and a two digit means a DFmode argument,
2271 and a three digit is not used. The low order digit is the first
2272 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2273 an SFmode argument. ??? A more sophisticated approach will be
2274 needed if MIPS_ABI != ABI_32. */
2275 int fp_code;
2276
2277 /* True if the function has a prototype. */
2278 int prototype;
2279 } CUMULATIVE_ARGS;
2280
2281 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2282 for a call to a function whose data type is FNTYPE.
2283 For a library call, FNTYPE is 0. */
2284
2285 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2286 mips_init_cumulative_args (&CUM, FNTYPE)
2287
2288 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2289 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2290
2291 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2292 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2293
2294 /* True if using EABI and varargs can be passed in floating-point
2295 registers. Under these conditions, we need a more complex form
2296 of va_list, which tracks GPR, FPR and stack arguments separately. */
2297 #define EABI_FLOAT_VARARGS_P \
2298 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2299
2300 \f
2301 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2302
2303 /* Treat LOC as a byte offset from the stack pointer and round it up
2304 to the next fully-aligned offset. */
2305 #define MIPS_STACK_ALIGN(LOC) \
2306 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2307
2308 \f
2309 /* Output assembler code to FILE to increment profiler label # LABELNO
2310 for profiling a function entry. */
2311
2312 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2313
2314 /* The profiler preserves all interesting registers, including $31. */
2315 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2316
2317 /* No mips port has ever used the profiler counter word, so don't emit it
2318 or the label for it. */
2319
2320 #define NO_PROFILE_COUNTERS 1
2321
2322 /* Define this macro if the code for function profiling should come
2323 before the function prologue. Normally, the profiling code comes
2324 after. */
2325
2326 /* #define PROFILE_BEFORE_PROLOGUE */
2327
2328 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2329 the stack pointer does not matter. The value is tested only in
2330 functions that have frame pointers.
2331 No definition is equivalent to always zero. */
2332
2333 #define EXIT_IGNORE_STACK 1
2334
2335 \f
2336 /* Trampolines are a block of code followed by two pointers. */
2337
2338 #define TRAMPOLINE_SIZE \
2339 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2340
2341 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2342 pointers from a single LUI base. */
2343
2344 #define TRAMPOLINE_ALIGNMENT 64
2345
2346 /* mips_trampoline_init calls this library function to flush
2347 program and data caches. */
2348
2349 #ifndef CACHE_FLUSH_FUNC
2350 #define CACHE_FLUSH_FUNC "_flush_cache"
2351 #endif
2352
2353 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2354 /* Flush both caches. We need to flush the data cache in case \
2355 the system has a write-back cache. */ \
2356 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2357 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2358 GEN_INT (3), TYPE_MODE (integer_type_node))
2359
2360 \f
2361 /* Addressing modes, and classification of registers for them. */
2362
2363 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2364 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2365 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2366 \f
2367 /* Maximum number of registers that can appear in a valid memory address. */
2368
2369 #define MAX_REGS_PER_ADDRESS 1
2370
2371 /* Check for constness inline but use mips_legitimate_address_p
2372 to check whether a constant really is an address. */
2373
2374 #define CONSTANT_ADDRESS_P(X) \
2375 (CONSTANT_P (X) && memory_address_p (SImode, X))
2376
2377 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2378 'the start of the function that this code is output in'. */
2379
2380 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2381 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2382 asm_fprintf ((FILE), "%U%s", \
2383 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2384 else \
2385 asm_fprintf ((FILE), "%U%s", (NAME))
2386 \f
2387 /* Flag to mark a function decl symbol that requires a long call. */
2388 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2389 #define SYMBOL_REF_LONG_CALL_P(X) \
2390 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2391
2392 /* This flag marks functions that cannot be lazily bound. */
2393 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2394 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2395 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2396
2397 /* True if we're generating a form of MIPS16 code in which jump tables
2398 are stored in the text section and encoded as 16-bit PC-relative
2399 offsets. This is only possible when general text loads are allowed,
2400 since the table access itself will be an "lh" instruction. If the
2401 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2402 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2403
2404 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2405
2406 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2407
2408 /* Only use short offsets if their range will not overflow. */
2409 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2410 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2411 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2412 : SImode)
2413
2414 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2415
2416 /* Define this as 1 if `char' should by default be signed; else as 0. */
2417 #ifndef DEFAULT_SIGNED_CHAR
2418 #define DEFAULT_SIGNED_CHAR 1
2419 #endif
2420
2421 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2422 we generally don't want to use them for copying arbitrary data.
2423 A single N-word move is usually the same cost as N single-word moves. */
2424 #define MOVE_MAX UNITS_PER_WORD
2425 #define MAX_MOVE_MAX 8
2426
2427 /* Define this macro as a C expression which is nonzero if
2428 accessing less than a word of memory (i.e. a `char' or a
2429 `short') is no faster than accessing a word of memory, i.e., if
2430 such access require more than one instruction or if there is no
2431 difference in cost between byte and (aligned) word loads.
2432
2433 On RISC machines, it tends to generate better code to define
2434 this as 1, since it avoids making a QI or HI mode register.
2435
2436 But, generating word accesses for -mips16 is generally bad as shifts
2437 (often extended) would be needed for byte accesses. */
2438 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2439
2440 /* Standard MIPS integer shifts truncate the shift amount to the
2441 width of the shifted operand. However, Loongson vector shifts
2442 do not truncate the shift amount at all. */
2443 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2444
2445 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2446 is done just by pretending it is already truncated. */
2447 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2448 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2449
2450
2451 /* Specify the machine mode that pointers have.
2452 After generation of rtl, the compiler makes no further distinction
2453 between pointers and any other objects of this machine mode. */
2454
2455 #ifndef Pmode
2456 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2457 #endif
2458
2459 /* Give call MEMs SImode since it is the "most permissive" mode
2460 for both 32-bit and 64-bit targets. */
2461
2462 #define FUNCTION_MODE SImode
2463
2464 \f
2465 /* We allocate $fcc registers by hand and can't cope with moves of
2466 CCmode registers to and from pseudos (or memory). */
2467 #define AVOID_CCMODE_COPIES
2468
2469 /* A C expression for the cost of a branch instruction. A value of
2470 1 is the default; other values are interpreted relative to that. */
2471
2472 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2473 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2474
2475 /* The MIPS port has several functions that return an instruction count.
2476 Multiplying the count by this value gives the number of bytes that
2477 the instructions occupy. */
2478 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2479
2480 /* The length of a NOP in bytes. */
2481 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2482
2483 /* If defined, modifies the length assigned to instruction INSN as a
2484 function of the context in which it is used. LENGTH is an lvalue
2485 that contains the initially computed length of the insn and should
2486 be updated with the correct length of the insn. */
2487 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2488 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2489
2490 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2491 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2492 its operands. */
2493 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2494 "%*" OPCODE "%?\t" OPERANDS "%/"
2495
2496 /* Return an asm string that forces INSN to be treated as an absolute
2497 J or JAL instruction instead of an assembler macro. */
2498 #define MIPS_ABSOLUTE_JUMP(INSN) \
2499 (TARGET_ABICALLS_PIC2 \
2500 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2501 : INSN)
2502
2503 /* Return the asm template for a call. INSN is the instruction's mnemonic
2504 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2505 number of the target. SIZE_OPNO is the operand number of the argument size
2506 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2507 -1 and the call is indirect, use the function symbol from the call
2508 attributes to attach a R_MIPS_JALR relocation to the call.
2509
2510 When generating GOT code without explicit relocation operators,
2511 all calls should use assembly macros. Otherwise, all indirect
2512 calls should use "jr" or "jalr"; we will arrange to restore $gp
2513 afterwards if necessary. Finally, we can only generate direct
2514 calls for -mabicalls by temporarily switching to non-PIC mode.
2515
2516 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2517 instruction is in the delay slot of jal(r). */
2518 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2519 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2520 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2521 : REG_P (OPERANDS[TARGET_OPNO]) \
2522 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2523 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2524 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2525 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2526 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2527 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2528 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2529 ? MIPS_ABSOLUTE_JUMP ("%*" INSN "%!\t%" #TARGET_OPNO "%/") \
2530 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/")) \
2531
2532 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2533 "jrc" when nop is in the delay slot of "jr". */
2534
2535 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2536 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2537 ? "%*j\t%" #OPNO "%/" \
2538 : REG_P (OPERANDS[OPNO]) \
2539 ? "%*jr%:\t%" #OPNO \
2540 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2541
2542 \f
2543 /* Control the assembler format that we output. */
2544
2545 /* Output to assembler file text saying following lines
2546 may contain character constants, extra white space, comments, etc. */
2547
2548 #ifndef ASM_APP_ON
2549 #define ASM_APP_ON " #APP\n"
2550 #endif
2551
2552 /* Output to assembler file text saying following lines
2553 no longer contain unusual constructs. */
2554
2555 #ifndef ASM_APP_OFF
2556 #define ASM_APP_OFF " #NO_APP\n"
2557 #endif
2558
2559 #define REGISTER_NAMES \
2560 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2561 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2562 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2563 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2564 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2565 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2566 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2567 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2568 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2569 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2570 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2571 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2572 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2573 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2574 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2575 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2576 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2577 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2578 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2579 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2580 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2581 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2582 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2583 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2584
2585 /* List the "software" names for each register. Also list the numerical
2586 names for $fp and $sp. */
2587
2588 #define ADDITIONAL_REGISTER_NAMES \
2589 { \
2590 { "$29", 29 + GP_REG_FIRST }, \
2591 { "$30", 30 + GP_REG_FIRST }, \
2592 { "at", 1 + GP_REG_FIRST }, \
2593 { "v0", 2 + GP_REG_FIRST }, \
2594 { "v1", 3 + GP_REG_FIRST }, \
2595 { "a0", 4 + GP_REG_FIRST }, \
2596 { "a1", 5 + GP_REG_FIRST }, \
2597 { "a2", 6 + GP_REG_FIRST }, \
2598 { "a3", 7 + GP_REG_FIRST }, \
2599 { "t0", 8 + GP_REG_FIRST }, \
2600 { "t1", 9 + GP_REG_FIRST }, \
2601 { "t2", 10 + GP_REG_FIRST }, \
2602 { "t3", 11 + GP_REG_FIRST }, \
2603 { "t4", 12 + GP_REG_FIRST }, \
2604 { "t5", 13 + GP_REG_FIRST }, \
2605 { "t6", 14 + GP_REG_FIRST }, \
2606 { "t7", 15 + GP_REG_FIRST }, \
2607 { "s0", 16 + GP_REG_FIRST }, \
2608 { "s1", 17 + GP_REG_FIRST }, \
2609 { "s2", 18 + GP_REG_FIRST }, \
2610 { "s3", 19 + GP_REG_FIRST }, \
2611 { "s4", 20 + GP_REG_FIRST }, \
2612 { "s5", 21 + GP_REG_FIRST }, \
2613 { "s6", 22 + GP_REG_FIRST }, \
2614 { "s7", 23 + GP_REG_FIRST }, \
2615 { "t8", 24 + GP_REG_FIRST }, \
2616 { "t9", 25 + GP_REG_FIRST }, \
2617 { "k0", 26 + GP_REG_FIRST }, \
2618 { "k1", 27 + GP_REG_FIRST }, \
2619 { "gp", 28 + GP_REG_FIRST }, \
2620 { "sp", 29 + GP_REG_FIRST }, \
2621 { "fp", 30 + GP_REG_FIRST }, \
2622 { "ra", 31 + GP_REG_FIRST } \
2623 }
2624
2625 #define DBR_OUTPUT_SEQEND(STREAM) \
2626 do \
2627 { \
2628 /* Undo the effect of '%*'. */ \
2629 mips_pop_asm_switch (&mips_nomacro); \
2630 mips_pop_asm_switch (&mips_noreorder); \
2631 /* Emit a blank line after the delay slot for emphasis. */ \
2632 fputs ("\n", STREAM); \
2633 } \
2634 while (0)
2635
2636 /* The MIPS implementation uses some labels for its own purpose. The
2637 following lists what labels are created, and are all formed by the
2638 pattern $L[a-z].*. The machine independent portion of GCC creates
2639 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2640
2641 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2642 $Lb[0-9]+ Begin blocks for MIPS debug support
2643 $Lc[0-9]+ Label for use in s<xx> operation.
2644 $Le[0-9]+ End blocks for MIPS debug support */
2645
2646 #undef ASM_DECLARE_OBJECT_NAME
2647 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2648 mips_declare_object (STREAM, NAME, "", ":\n")
2649
2650 /* Globalizing directive for a label. */
2651 #define GLOBAL_ASM_OP "\t.globl\t"
2652
2653 /* This says how to define a global common symbol. */
2654
2655 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2656
2657 /* This says how to define a local common symbol (i.e., not visible to
2658 linker). */
2659
2660 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2661 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2662 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2663 #endif
2664
2665 /* This says how to output an external. It would be possible not to
2666 output anything and let undefined symbol become external. However
2667 the assembler uses length information on externals to allocate in
2668 data/sdata bss/sbss, thereby saving exec time. */
2669
2670 #undef ASM_OUTPUT_EXTERNAL
2671 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2672 mips_output_external(STREAM,DECL,NAME)
2673
2674 /* This is how to declare a function name. The actual work of
2675 emitting the label is moved to function_prologue, so that we can
2676 get the line number correctly emitted before the .ent directive,
2677 and after any .file directives. Define as empty so that the function
2678 is not declared before the .ent directive elsewhere. */
2679
2680 #undef ASM_DECLARE_FUNCTION_NAME
2681 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2682
2683 /* This is how to store into the string LABEL
2684 the symbol_ref name of an internal numbered label where
2685 PREFIX is the class of label and NUM is the number within the class.
2686 This is suitable for output with `assemble_name'. */
2687
2688 #undef ASM_GENERATE_INTERNAL_LABEL
2689 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2690 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2691
2692 /* Print debug labels as "foo = ." rather than "foo:" because they should
2693 represent a byte pointer rather than an ISA-encoded address. This is
2694 particularly important for code like:
2695
2696 $LFBxxx = .
2697 .cfi_startproc
2698 ...
2699 .section .gcc_except_table,...
2700 ...
2701 .uleb128 foo-$LFBxxx
2702
2703 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2704 likewise a byte pointer rather than an ISA-encoded address.
2705
2706 At the time of writing, this hook is not used for the function end
2707 label:
2708
2709 $LFExxx:
2710 .end foo
2711
2712 But this doesn't matter, because GAS doesn't treat a pre-.end label
2713 as a MIPS16 one anyway. */
2714
2715 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2716 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2717
2718 /* This is how to output an element of a case-vector that is absolute. */
2719
2720 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2721 fprintf (STREAM, "\t%s\t%sL%d\n", \
2722 ptr_mode == DImode ? ".dword" : ".word", \
2723 LOCAL_LABEL_PREFIX, \
2724 VALUE)
2725
2726 /* This is how to output an element of a case-vector. We can make the
2727 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2728 is supported. */
2729
2730 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2731 do { \
2732 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2733 { \
2734 if (GET_MODE (BODY) == HImode) \
2735 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2736 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2737 else \
2738 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2739 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2740 } \
2741 else if (TARGET_GPWORD) \
2742 fprintf (STREAM, "\t%s\t%sL%d\n", \
2743 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2744 LOCAL_LABEL_PREFIX, VALUE); \
2745 else if (TARGET_RTP_PIC) \
2746 { \
2747 /* Make the entry relative to the start of the function. */ \
2748 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2749 fprintf (STREAM, "\t%s\t%sL%d-", \
2750 Pmode == DImode ? ".dword" : ".word", \
2751 LOCAL_LABEL_PREFIX, VALUE); \
2752 assemble_name (STREAM, XSTR (fnsym, 0)); \
2753 fprintf (STREAM, "\n"); \
2754 } \
2755 else \
2756 fprintf (STREAM, "\t%s\t%sL%d\n", \
2757 ptr_mode == DImode ? ".dword" : ".word", \
2758 LOCAL_LABEL_PREFIX, VALUE); \
2759 } while (0)
2760
2761 /* This is how to output an assembler line
2762 that says to advance the location counter
2763 to a multiple of 2**LOG bytes. */
2764
2765 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2766 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2767
2768 /* This is how to output an assembler line to advance the location
2769 counter by SIZE bytes. */
2770
2771 #undef ASM_OUTPUT_SKIP
2772 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2773 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2774
2775 /* This is how to output a string. */
2776 #undef ASM_OUTPUT_ASCII
2777 #define ASM_OUTPUT_ASCII mips_output_ascii
2778
2779 \f
2780 /* Default to -G 8 */
2781 #ifndef MIPS_DEFAULT_GVALUE
2782 #define MIPS_DEFAULT_GVALUE 8
2783 #endif
2784
2785 /* Define the strings to put out for each section in the object file. */
2786 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2787 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2788
2789 #undef READONLY_DATA_SECTION_ASM_OP
2790 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2791 \f
2792 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2793 do \
2794 { \
2795 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2796 TARGET_64BIT ? "daddiu" : "addiu", \
2797 reg_names[STACK_POINTER_REGNUM], \
2798 reg_names[STACK_POINTER_REGNUM], \
2799 TARGET_64BIT ? "sd" : "sw", \
2800 reg_names[REGNO], \
2801 reg_names[STACK_POINTER_REGNUM]); \
2802 } \
2803 while (0)
2804
2805 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2806 do \
2807 { \
2808 mips_push_asm_switch (&mips_noreorder); \
2809 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2810 TARGET_64BIT ? "ld" : "lw", \
2811 reg_names[REGNO], \
2812 reg_names[STACK_POINTER_REGNUM], \
2813 TARGET_64BIT ? "daddu" : "addu", \
2814 reg_names[STACK_POINTER_REGNUM], \
2815 reg_names[STACK_POINTER_REGNUM]); \
2816 mips_pop_asm_switch (&mips_noreorder); \
2817 } \
2818 while (0)
2819
2820 /* How to start an assembler comment.
2821 The leading space is important (the mips native assembler requires it). */
2822 #ifndef ASM_COMMENT_START
2823 #define ASM_COMMENT_START " #"
2824 #endif
2825 \f
2826 #undef SIZE_TYPE
2827 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2828
2829 #undef PTRDIFF_TYPE
2830 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2831
2832 /* The maximum number of bytes that can be copied by one iteration of
2833 a movmemsi loop; see mips_block_move_loop. */
2834 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2835 (UNITS_PER_WORD * 4)
2836
2837 /* The maximum number of bytes that can be copied by a straight-line
2838 implementation of movmemsi; see mips_block_move_straight. We want
2839 to make sure that any loop-based implementation will iterate at
2840 least twice. */
2841 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2842 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2843
2844 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2845 values were determined experimentally by benchmarking with CSiBE.
2846 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2847 for o32 where we have to restore $gp afterwards as well as make an
2848 indirect call), but in practice, bumping this up higher for
2849 TARGET_ABICALLS doesn't make much difference to code size. */
2850
2851 #define MIPS_CALL_RATIO 8
2852
2853 /* Any loop-based implementation of movmemsi will have at least
2854 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2855 moves, so allow individual copies of fewer elements.
2856
2857 When movmemsi is not available, use a value approximating
2858 the length of a memcpy call sequence, so that move_by_pieces
2859 will generate inline code if it is shorter than a function call.
2860 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2861 we'll have to generate a load/store pair for each, halve the
2862 value of MIPS_CALL_RATIO to take that into account. */
2863
2864 #define MOVE_RATIO(speed) \
2865 (HAVE_movmemsi \
2866 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2867 : MIPS_CALL_RATIO / 2)
2868
2869 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2870 mips_move_by_pieces_p (SIZE, ALIGN)
2871
2872 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2873 of the length of a memset call, but use the default otherwise. */
2874
2875 #define CLEAR_RATIO(speed)\
2876 ((speed) ? 15 : MIPS_CALL_RATIO)
2877
2878 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2879 optimizing for size adjust the ratio to account for the overhead of
2880 loading the constant and replicating it across the word. */
2881
2882 #define SET_RATIO(speed) \
2883 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2884
2885 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2886 mips_store_by_pieces_p (SIZE, ALIGN)
2887 \f
2888 /* Since the bits of the _init and _fini function is spread across
2889 many object files, each potentially with its own GP, we must assume
2890 we need to load our GP. We don't preserve $gp or $ra, since each
2891 init/fini chunk is supposed to initialize $gp, and crti/crtn
2892 already take care of preserving $ra and, when appropriate, $gp. */
2893 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2894 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2895 asm (SECTION_OP "\n\
2896 .set push\n\
2897 .set nomips16\n\
2898 .set noreorder\n\
2899 bal 1f\n\
2900 nop\n\
2901 1: .cpload $31\n\
2902 .set reorder\n\
2903 jal " USER_LABEL_PREFIX #FUNC "\n\
2904 .set pop\n\
2905 " TEXT_SECTION_ASM_OP);
2906 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2907 || (defined _ABI64 && _MIPS_SIM == _ABI64))
2908 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2909 asm (SECTION_OP "\n\
2910 .set push\n\
2911 .set nomips16\n\
2912 .set noreorder\n\
2913 bal 1f\n\
2914 nop\n\
2915 1: .set reorder\n\
2916 .cpsetup $31, $2, 1b\n\
2917 jal " USER_LABEL_PREFIX #FUNC "\n\
2918 .set pop\n\
2919 " TEXT_SECTION_ASM_OP);
2920 #endif
2921
2922 #ifndef HAVE_AS_TLS
2923 #define HAVE_AS_TLS 0
2924 #endif
2925
2926 #ifndef HAVE_AS_NAN
2927 #define HAVE_AS_NAN 0
2928 #endif
2929
2930 #ifndef USED_FOR_TARGET
2931 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2932 struct mips_asm_switch {
2933 /* The FOO in the description above. */
2934 const char *name;
2935
2936 /* The current block nesting level, or 0 if we aren't in a block. */
2937 int nesting_level;
2938 };
2939
2940 extern const enum reg_class mips_regno_to_class[];
2941 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2942 extern const char *current_function_file; /* filename current function is in */
2943 extern int num_source_filenames; /* current .file # */
2944 extern struct mips_asm_switch mips_noreorder;
2945 extern struct mips_asm_switch mips_nomacro;
2946 extern struct mips_asm_switch mips_noat;
2947 extern int mips_dbx_regno[];
2948 extern int mips_dwarf_regno[];
2949 extern bool mips_split_p[];
2950 extern bool mips_split_hi_p[];
2951 extern bool mips_use_pcrel_pool_p[];
2952 extern const char *mips_lo_relocs[];
2953 extern const char *mips_hi_relocs[];
2954 extern enum processor mips_arch; /* which cpu to codegen for */
2955 extern enum processor mips_tune; /* which cpu to schedule for */
2956 extern int mips_isa; /* architectural level */
2957 extern const struct mips_cpu_info *mips_arch_info;
2958 extern const struct mips_cpu_info *mips_tune_info;
2959 extern unsigned int mips_base_compression_flags;
2960 extern GTY(()) struct target_globals *mips16_globals;
2961 #endif
2962
2963 /* Enable querying of DFA units. */
2964 #define CPU_UNITS_QUERY 1
2965
2966 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2967 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2968
2969 /* As on most targets, we want the .eh_frame section to be read-only where
2970 possible. And as on most targets, this means two things:
2971
2972 (a) Non-locally-binding pointers must have an indirect encoding,
2973 so that the addresses in the .eh_frame section itself become
2974 locally-binding.
2975
2976 (b) A shared library's .eh_frame section must encode locally-binding
2977 pointers in a relative (relocation-free) form.
2978
2979 However, MIPS has traditionally not allowed directives like:
2980
2981 .long x-.
2982
2983 in cases where "x" is in a different section, or is not defined in the
2984 same assembly file. We are therefore unable to emit the PC-relative
2985 form required by (b) at assembly time.
2986
2987 Fortunately, the linker is able to convert absolute addresses into
2988 PC-relative addresses on our behalf. Unfortunately, only certain
2989 versions of the linker know how to do this for indirect pointers,
2990 and for personality data. We must fall back on using writable
2991 .eh_frame sections for shared libraries if the linker does not
2992 support this feature. */
2993 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2994 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2995
2996 /* For switching between MIPS16 and non-MIPS16 modes. */
2997 #define SWITCHABLE_TARGET 1
2998
2999 /* Several named MIPS patterns depend on Pmode. These patterns have the
3000 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3001 Add the appropriate suffix to generator function NAME and invoke it
3002 with arguments ARGS. */
3003 #define PMODE_INSN(NAME, ARGS) \
3004 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)