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Remove obsolete IRIX 6.5 support
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
4 2012
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky (lich@inria.inria.fr).
7 Changed by Michael Meissner (meissner@osf.org).
8 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
9 Brendan Eich (brendan@microunity.com).
10
11 This file is part of GCC.
12
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
16 any later version.
17
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
26
27
28 #include "config/vxworks-dummy.h"
29
30 #ifdef GENERATOR_FILE
31 /* This is used in some insn conditions, so needs to be declared, but
32 does not need to be defined. */
33 extern int target_flags_explicit;
34 #endif
35
36 /* MIPS external variables defined in mips.c. */
37
38 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
39 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
40 to work on a 64-bit machine. */
41
42 #define ABI_32 0
43 #define ABI_N32 1
44 #define ABI_64 2
45 #define ABI_EABI 3
46 #define ABI_O64 4
47
48 /* Masks that affect tuning.
49
50 PTF_AVOID_BRANCHLIKELY
51 Set if it is usually not profitable to use branch-likely instructions
52 for this target, typically because the branches are always predicted
53 taken and so incur a large overhead when not taken. */
54 #define PTF_AVOID_BRANCHLIKELY 0x1
55
56 /* Information about one recognized processor. Defined here for the
57 benefit of TARGET_CPU_CPP_BUILTINS. */
58 struct mips_cpu_info {
59 /* The 'canonical' name of the processor as far as GCC is concerned.
60 It's typically a manufacturer's prefix followed by a numerical
61 designation. It should be lowercase. */
62 const char *name;
63
64 /* The internal processor number that most closely matches this
65 entry. Several processors can have the same value, if there's no
66 difference between them from GCC's point of view. */
67 enum processor cpu;
68
69 /* The ISA level that the processor implements. */
70 int isa;
71
72 /* A mask of PTF_* values. */
73 unsigned int tune_flags;
74 };
75
76 #include "config/mips/mips-opts.h"
77
78 /* Macros to silence warnings about numbers being signed in traditional
79 C and unsigned in ISO C when compiled on 32-bit hosts. */
80
81 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
82 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
83 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
84
85 \f
86 /* Run-time compilation parameters selecting different hardware subsets. */
87
88 /* True if we are generating position-independent VxWorks RTP code. */
89 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
90
91 /* True if the output file is marked as ".abicalls; .option pic0"
92 (-call_nonpic). */
93 #define TARGET_ABICALLS_PIC0 \
94 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
95
96 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
97 #define TARGET_ABICALLS_PIC2 \
98 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
99
100 /* True if the call patterns should be split into a jalr followed by
101 an instruction to restore $gp. It is only safe to split the load
102 from the call when every use of $gp is explicit.
103
104 See mips_must_initialize_gp_p for details about how we manage the
105 global pointer. */
106
107 #define TARGET_SPLIT_CALLS \
108 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
109
110 /* True if we're generating a form of -mabicalls in which we can use
111 operators like %hi and %lo to refer to locally-binding symbols.
112 We can only do this for -mno-shared, and only then if we can use
113 relocation operations instead of assembly macros. It isn't really
114 worth using absolute sequences for 64-bit symbols because GOT
115 accesses are so much shorter. */
116
117 #define TARGET_ABSOLUTE_ABICALLS \
118 (TARGET_ABICALLS \
119 && !TARGET_SHARED \
120 && TARGET_EXPLICIT_RELOCS \
121 && !ABI_HAS_64BIT_SYMBOLS)
122
123 /* True if we can optimize sibling calls. For simplicity, we only
124 handle cases in which call_insn_operand will reject invalid
125 sibcall addresses. There are two cases in which this isn't true:
126
127 - TARGET_MIPS16. call_insn_operand accepts constant addresses
128 but there is no direct jump instruction. It isn't worth
129 using sibling calls in this case anyway; they would usually
130 be longer than normal calls.
131
132 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
133 accepts global constants, but all sibcalls must be indirect. */
134 #define TARGET_SIBCALLS \
135 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
136
137 /* True if we need to use a global offset table to access some symbols. */
138 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
139
140 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
141 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
142
143 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
144 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
145
146 /* True if we should use .cprestore to store to the cprestore slot.
147
148 We continue to use .cprestore for explicit-reloc code so that JALs
149 inside inline asms will work correctly. */
150 #define TARGET_CPRESTORE_DIRECTIVE \
151 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
152
153 /* True if we can use the J and JAL instructions. */
154 #define TARGET_ABSOLUTE_JUMPS \
155 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
156
157 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
158 This is true for both the PIC and non-PIC VxWorks RTP modes. */
159 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
160
161 /* True if .gpword or .gpdword should be used for switch tables. */
162 #define TARGET_GPWORD \
163 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
164
165 /* True if the output must have a writable .eh_frame.
166 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
167 #ifdef HAVE_LD_PERSONALITY_RELAXATION
168 #define TARGET_WRITABLE_EH_FRAME 0
169 #else
170 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
171 #endif
172
173 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
174 #ifdef HAVE_AS_DSPR1_MULT
175 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
176 #else
177 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
178 #endif
179
180 /* Generate mips16 code */
181 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
182 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
183 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
184 /* Generate mips16e register save/restore sequences. */
185 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
186
187 /* True if we're generating a form of MIPS16 code in which general
188 text loads are allowed. */
189 #define TARGET_MIPS16_TEXT_LOADS \
190 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
191
192 /* True if we're generating a form of MIPS16 code in which PC-relative
193 loads are allowed. */
194 #define TARGET_MIPS16_PCREL_LOADS \
195 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
196
197 /* Generic ISA defines. */
198 #define ISA_MIPS1 (mips_isa == 1)
199 #define ISA_MIPS2 (mips_isa == 2)
200 #define ISA_MIPS3 (mips_isa == 3)
201 #define ISA_MIPS4 (mips_isa == 4)
202 #define ISA_MIPS32 (mips_isa == 32)
203 #define ISA_MIPS32R2 (mips_isa == 33)
204 #define ISA_MIPS64 (mips_isa == 64)
205 #define ISA_MIPS64R2 (mips_isa == 65)
206
207 /* Architecture target defines. */
208 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
209 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
210 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
211 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
212 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
213 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
214 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
215 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
216 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
217 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
218 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
219 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
220 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
221 || mips_arch == PROCESSOR_OCTEON2)
222 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
223 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
224 || mips_arch == PROCESSOR_SB1A)
225 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
226
227 /* Scheduling target defines. */
228 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
229 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
230 || mips_tune == PROCESSOR_24KF2_1 \
231 || mips_tune == PROCESSOR_24KF1_1)
232 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
233 || mips_tune == PROCESSOR_74KF2_1 \
234 || mips_tune == PROCESSOR_74KF1_1 \
235 || mips_tune == PROCESSOR_74KF3_2)
236 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
237 || mips_tune == PROCESSOR_LOONGSON_2F)
238 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
239 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
240 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
241 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
242 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
243 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
244 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
245 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
246 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
247 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
248 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
249 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
250 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
251 || mips_tune == PROCESSOR_OCTEON2)
252 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
253 || mips_tune == PROCESSOR_SB1A)
254
255 /* Whether vector modes and intrinsics for ST Microelectronics
256 Loongson-2E/2F processors should be enabled. In o32 pairs of
257 floating-point registers provide 64-bit values. */
258 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
259 && (TARGET_LOONGSON_2EF \
260 || TARGET_LOONGSON_3A))
261
262 /* True if the pre-reload scheduler should try to create chains of
263 multiply-add or multiply-subtract instructions. For example,
264 suppose we have:
265
266 t1 = a * b
267 t2 = t1 + c * d
268 t3 = e * f
269 t4 = t3 - g * h
270
271 t1 will have a higher priority than t2 and t3 will have a higher
272 priority than t4. However, before reload, there is no dependence
273 between t1 and t3, and they can often have similar priorities.
274 The scheduler will then tend to prefer:
275
276 t1 = a * b
277 t3 = e * f
278 t2 = t1 + c * d
279 t4 = t3 - g * h
280
281 which stops us from making full use of macc/madd-style instructions.
282 This sort of situation occurs frequently in Fourier transforms and
283 in unrolled loops.
284
285 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
286 queue so that chained multiply-add and multiply-subtract instructions
287 appear ahead of any other instruction that is likely to clobber lo.
288 In the example above, if t2 and t3 become ready at the same time,
289 the code ensures that t2 is scheduled first.
290
291 Multiply-accumulate instructions are a bigger win for some targets
292 than others, so this macro is defined on an opt-in basis. */
293 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
294 || TUNE_MIPS4120 \
295 || TUNE_MIPS4130 \
296 || TUNE_24K)
297
298 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
299 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
300
301 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
302 directly accessible, while the command-line options select
303 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
304 in use. */
305 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
306 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
307
308 /* False if SC acts as a memory barrier with respect to itself,
309 otherwise a SYNC will be emitted after SC for atomic operations
310 that require ordering between the SC and following loads and
311 stores. It does not tell anything about ordering of loads and
312 stores prior to and following the SC, only about the SC itself and
313 those loads and stores follow it. */
314 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
315
316 /* Define preprocessor macros for the -march and -mtune options.
317 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
318 processor. If INFO's canonical name is "foo", define PREFIX to
319 be "foo", and define an additional macro PREFIX_FOO. */
320 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
321 do \
322 { \
323 char *macro, *p; \
324 \
325 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
326 for (p = macro; *p != 0; p++) \
327 if (*p == '+') \
328 *p = 'P'; \
329 else \
330 *p = TOUPPER (*p); \
331 \
332 builtin_define (macro); \
333 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
334 free (macro); \
335 } \
336 while (0)
337
338 /* Target CPU builtins. */
339 #define TARGET_CPU_CPP_BUILTINS() \
340 do \
341 { \
342 builtin_assert ("machine=mips"); \
343 builtin_assert ("cpu=mips"); \
344 builtin_define ("__mips__"); \
345 builtin_define ("_mips"); \
346 \
347 /* We do this here because __mips is defined below and so we \
348 can't use builtin_define_std. We don't ever want to define \
349 "mips" for VxWorks because some of the VxWorks headers \
350 construct include filenames from a root directory macro, \
351 an architecture macro and a filename, where the architecture \
352 macro expands to 'mips'. If we define 'mips' to 1, the \
353 architecture macro expands to 1 as well. */ \
354 if (!flag_iso && !TARGET_VXWORKS) \
355 builtin_define ("mips"); \
356 \
357 if (TARGET_64BIT) \
358 builtin_define ("__mips64"); \
359 \
360 /* Treat _R3000 and _R4000 like register-size \
361 defines, which is how they've historically \
362 been used. */ \
363 if (TARGET_64BIT) \
364 { \
365 builtin_define_std ("R4000"); \
366 builtin_define ("_R4000"); \
367 } \
368 else \
369 { \
370 builtin_define_std ("R3000"); \
371 builtin_define ("_R3000"); \
372 } \
373 \
374 if (TARGET_FLOAT64) \
375 builtin_define ("__mips_fpr=64"); \
376 else \
377 builtin_define ("__mips_fpr=32"); \
378 \
379 if (mips_base_mips16) \
380 builtin_define ("__mips16"); \
381 \
382 if (TARGET_MIPS3D) \
383 builtin_define ("__mips3d"); \
384 \
385 if (TARGET_SMARTMIPS) \
386 builtin_define ("__mips_smartmips"); \
387 \
388 if (TARGET_DSP) \
389 { \
390 builtin_define ("__mips_dsp"); \
391 if (TARGET_DSPR2) \
392 { \
393 builtin_define ("__mips_dspr2"); \
394 builtin_define ("__mips_dsp_rev=2"); \
395 } \
396 else \
397 builtin_define ("__mips_dsp_rev=1"); \
398 } \
399 \
400 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
401 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
402 \
403 if (ISA_MIPS1) \
404 { \
405 builtin_define ("__mips=1"); \
406 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
407 } \
408 else if (ISA_MIPS2) \
409 { \
410 builtin_define ("__mips=2"); \
411 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
412 } \
413 else if (ISA_MIPS3) \
414 { \
415 builtin_define ("__mips=3"); \
416 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
417 } \
418 else if (ISA_MIPS4) \
419 { \
420 builtin_define ("__mips=4"); \
421 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
422 } \
423 else if (ISA_MIPS32) \
424 { \
425 builtin_define ("__mips=32"); \
426 builtin_define ("__mips_isa_rev=1"); \
427 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
428 } \
429 else if (ISA_MIPS32R2) \
430 { \
431 builtin_define ("__mips=32"); \
432 builtin_define ("__mips_isa_rev=2"); \
433 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
434 } \
435 else if (ISA_MIPS64) \
436 { \
437 builtin_define ("__mips=64"); \
438 builtin_define ("__mips_isa_rev=1"); \
439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
440 } \
441 else if (ISA_MIPS64R2) \
442 { \
443 builtin_define ("__mips=64"); \
444 builtin_define ("__mips_isa_rev=2"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
446 } \
447 \
448 switch (mips_abi) \
449 { \
450 case ABI_32: \
451 builtin_define ("_ABIO32=1"); \
452 builtin_define ("_MIPS_SIM=_ABIO32"); \
453 break; \
454 \
455 case ABI_N32: \
456 builtin_define ("_ABIN32=2"); \
457 builtin_define ("_MIPS_SIM=_ABIN32"); \
458 break; \
459 \
460 case ABI_64: \
461 builtin_define ("_ABI64=3"); \
462 builtin_define ("_MIPS_SIM=_ABI64"); \
463 break; \
464 \
465 case ABI_O64: \
466 builtin_define ("_ABIO64=4"); \
467 builtin_define ("_MIPS_SIM=_ABIO64"); \
468 break; \
469 } \
470 \
471 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
472 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
473 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
474 builtin_define_with_int_value ("_MIPS_FPSET", \
475 32 / MAX_FPRS_PER_FMT); \
476 \
477 /* These defines reflect the ABI in use, not whether the \
478 FPU is directly accessible. */ \
479 if (TARGET_NO_FLOAT) \
480 builtin_define ("__mips_no_float"); \
481 else if (TARGET_HARD_FLOAT_ABI) \
482 builtin_define ("__mips_hard_float"); \
483 else \
484 builtin_define ("__mips_soft_float"); \
485 \
486 if (TARGET_SINGLE_FLOAT) \
487 builtin_define ("__mips_single_float"); \
488 \
489 if (TARGET_PAIRED_SINGLE_FLOAT) \
490 builtin_define ("__mips_paired_single_float"); \
491 \
492 if (TARGET_BIG_ENDIAN) \
493 { \
494 builtin_define_std ("MIPSEB"); \
495 builtin_define ("_MIPSEB"); \
496 } \
497 else \
498 { \
499 builtin_define_std ("MIPSEL"); \
500 builtin_define ("_MIPSEL"); \
501 } \
502 \
503 /* Whether calls should go through $25. The separate __PIC__ \
504 macro indicates whether abicalls code might use a GOT. */ \
505 if (TARGET_ABICALLS) \
506 builtin_define ("__mips_abicalls"); \
507 \
508 /* Whether Loongson vector modes are enabled. */ \
509 if (TARGET_LOONGSON_VECTORS) \
510 builtin_define ("__mips_loongson_vector_rev"); \
511 \
512 /* Historical Octeon macro. */ \
513 if (TARGET_OCTEON) \
514 builtin_define ("__OCTEON__"); \
515 \
516 /* Macros dependent on the C dialect. */ \
517 if (preprocessing_asm_p ()) \
518 { \
519 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
520 builtin_define ("_LANGUAGE_ASSEMBLY"); \
521 } \
522 else if (c_dialect_cxx ()) \
523 { \
524 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
525 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
526 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
527 } \
528 else \
529 { \
530 builtin_define_std ("LANGUAGE_C"); \
531 builtin_define ("_LANGUAGE_C"); \
532 } \
533 if (c_dialect_objc ()) \
534 { \
535 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
536 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
537 /* Bizarre, but retained for backwards compatibility. */ \
538 builtin_define_std ("LANGUAGE_C"); \
539 builtin_define ("_LANGUAGE_C"); \
540 } \
541 \
542 if (mips_abi == ABI_EABI) \
543 builtin_define ("__mips_eabi"); \
544 \
545 if (TARGET_CACHE_BUILTIN) \
546 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
547 } \
548 while (0)
549
550 /* Default target_flags if no switches are specified */
551
552 #ifndef TARGET_DEFAULT
553 #define TARGET_DEFAULT 0
554 #endif
555
556 #ifndef TARGET_CPU_DEFAULT
557 #define TARGET_CPU_DEFAULT 0
558 #endif
559
560 #ifndef TARGET_ENDIAN_DEFAULT
561 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
562 #endif
563
564 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
565 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
566 #endif
567
568 #ifdef IN_LIBGCC2
569 #undef TARGET_64BIT
570 /* Make this compile time constant for libgcc2 */
571 #ifdef __mips64
572 #define TARGET_64BIT 1
573 #else
574 #define TARGET_64BIT 0
575 #endif
576 #endif /* IN_LIBGCC2 */
577
578 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
579 when compiled with hardware floating point. This is because MIPS16
580 code cannot save and restore the floating-point registers, which is
581 important if in a mixed MIPS16/non-MIPS16 environment. */
582
583 #ifdef IN_LIBGCC2
584 #if __mips_hard_float
585 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
586 #endif
587 #endif /* IN_LIBGCC2 */
588
589 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
590
591 #ifndef MULTILIB_ENDIAN_DEFAULT
592 #if TARGET_ENDIAN_DEFAULT == 0
593 #define MULTILIB_ENDIAN_DEFAULT "EL"
594 #else
595 #define MULTILIB_ENDIAN_DEFAULT "EB"
596 #endif
597 #endif
598
599 #ifndef MULTILIB_ISA_DEFAULT
600 # if MIPS_ISA_DEFAULT == 1
601 # define MULTILIB_ISA_DEFAULT "mips1"
602 # else
603 # if MIPS_ISA_DEFAULT == 2
604 # define MULTILIB_ISA_DEFAULT "mips2"
605 # else
606 # if MIPS_ISA_DEFAULT == 3
607 # define MULTILIB_ISA_DEFAULT "mips3"
608 # else
609 # if MIPS_ISA_DEFAULT == 4
610 # define MULTILIB_ISA_DEFAULT "mips4"
611 # else
612 # if MIPS_ISA_DEFAULT == 32
613 # define MULTILIB_ISA_DEFAULT "mips32"
614 # else
615 # if MIPS_ISA_DEFAULT == 33
616 # define MULTILIB_ISA_DEFAULT "mips32r2"
617 # else
618 # if MIPS_ISA_DEFAULT == 64
619 # define MULTILIB_ISA_DEFAULT "mips64"
620 # else
621 # if MIPS_ISA_DEFAULT == 65
622 # define MULTILIB_ISA_DEFAULT "mips64r2"
623 # else
624 # define MULTILIB_ISA_DEFAULT "mips1"
625 # endif
626 # endif
627 # endif
628 # endif
629 # endif
630 # endif
631 # endif
632 # endif
633 #endif
634
635 #ifndef MIPS_ABI_DEFAULT
636 #define MIPS_ABI_DEFAULT ABI_32
637 #endif
638
639 /* Use the most portable ABI flag for the ASM specs. */
640
641 #if MIPS_ABI_DEFAULT == ABI_32
642 #define MULTILIB_ABI_DEFAULT "mabi=32"
643 #endif
644
645 #if MIPS_ABI_DEFAULT == ABI_O64
646 #define MULTILIB_ABI_DEFAULT "mabi=o64"
647 #endif
648
649 #if MIPS_ABI_DEFAULT == ABI_N32
650 #define MULTILIB_ABI_DEFAULT "mabi=n32"
651 #endif
652
653 #if MIPS_ABI_DEFAULT == ABI_64
654 #define MULTILIB_ABI_DEFAULT "mabi=64"
655 #endif
656
657 #if MIPS_ABI_DEFAULT == ABI_EABI
658 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
659 #endif
660
661 #ifndef MULTILIB_DEFAULTS
662 #define MULTILIB_DEFAULTS \
663 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
664 #endif
665
666 /* We must pass -EL to the linker by default for little endian embedded
667 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
668 linker will default to using big-endian output files. The OUTPUT_FORMAT
669 line must be in the linker script, otherwise -EB/-EL will not work. */
670
671 #ifndef ENDIAN_SPEC
672 #if TARGET_ENDIAN_DEFAULT == 0
673 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
674 #else
675 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
676 #endif
677 #endif
678
679 /* A spec condition that matches all non-mips16 -mips arguments. */
680
681 #define MIPS_ISA_LEVEL_OPTION_SPEC \
682 "mips1|mips2|mips3|mips4|mips32*|mips64*"
683
684 /* A spec condition that matches all non-mips16 architecture arguments. */
685
686 #define MIPS_ARCH_OPTION_SPEC \
687 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
688
689 /* A spec that infers a -mips argument from an -march argument,
690 or injects the default if no architecture is specified. */
691
692 #define MIPS_ISA_LEVEL_SPEC \
693 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
694 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
695 %{march=mips2|march=r6000:-mips2} \
696 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
697 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
698 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
699 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
700 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
701 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
702 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
703 |march=xlr|march=loongson3a: -mips64} \
704 %{march=mips64r2|march=octeon: -mips64r2} \
705 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
706
707 /* A spec that infers a -mhard-float or -msoft-float setting from an
708 -march argument. Note that soft-float and hard-float code are not
709 link-compatible. */
710
711 #define MIPS_ARCH_FLOAT_SPEC \
712 "%{mhard-float|msoft-float|march=mips*:; \
713 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
714 |march=34kc|march=74kc|march=1004kc|march=5kc \
715 |march=octeon|march=xlr: -msoft-float; \
716 march=*: -mhard-float}"
717
718 /* A spec condition that matches 32-bit options. It only works if
719 MIPS_ISA_LEVEL_SPEC has been applied. */
720
721 #define MIPS_32BIT_OPTION_SPEC \
722 "mips1|mips2|mips32*|mgp32"
723
724 #if MIPS_ABI_DEFAULT == ABI_O64 \
725 || MIPS_ABI_DEFAULT == ABI_N32 \
726 || MIPS_ABI_DEFAULT == ABI_64
727 #define OPT_ARCH64 "mabi=32|mgp32:;"
728 #define OPT_ARCH32 "mabi=32|mgp32"
729 #else
730 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
731 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
732 #endif
733
734 /* Support for a compile-time default CPU, et cetera. The rules are:
735 --with-arch is ignored if -march is specified or a -mips is specified
736 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
737 --with-tune is ignored if -mtune is specified; likewise
738 --with-tune-32 and --with-tune-64.
739 --with-abi is ignored if -mabi is specified.
740 --with-float is ignored if -mhard-float or -msoft-float are
741 specified.
742 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
743 specified. */
744 #define OPTION_DEFAULT_SPECS \
745 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
746 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
747 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
748 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
749 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
750 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
751 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
752 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
753 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
754 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
755 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
756 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
757
758
759 /* A spec that infers the -mdsp setting from an -march argument. */
760 #define BASE_DRIVER_SELF_SPECS \
761 "%{!mno-dsp: \
762 %{march=24ke*|march=34k*|march=1004k*: -mdsp} \
763 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
764
765 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
766
767 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
768 && ISA_HAS_COND_TRAP)
769
770 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
771
772 /* True if the ABI can only work with 64-bit integer registers. We
773 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
774 otherwise floating-point registers must also be 64-bit. */
775 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
776
777 /* Likewise for 32-bit regs. */
778 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
779
780 /* True if the file format uses 64-bit symbols. At present, this is
781 only true for n64, which uses 64-bit ELF. */
782 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
783
784 /* True if symbols are 64 bits wide. This is usually determined by
785 the ABI's file format, but it can be overridden by -msym32. Note that
786 overriding the size with -msym32 changes the ABI of relocatable objects,
787 although it doesn't change the ABI of a fully-linked object. */
788 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
789 && Pmode == DImode \
790 && !TARGET_SYM32)
791
792 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
793 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
794 || ISA_MIPS4 \
795 || ISA_MIPS64 \
796 || ISA_MIPS64R2)
797
798 /* ISA has branch likely instructions (e.g. mips2). */
799 /* Disable branchlikely for tx39 until compare rewrite. They haven't
800 been generated up to this point. */
801 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
802
803 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
804 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
805 || TARGET_MIPS5400 \
806 || TARGET_MIPS5500 \
807 || TARGET_MIPS7000 \
808 || TARGET_MIPS9000 \
809 || TARGET_MAD \
810 || ISA_MIPS32 \
811 || ISA_MIPS32R2 \
812 || ISA_MIPS64 \
813 || ISA_MIPS64R2) \
814 && !TARGET_MIPS16)
815
816 /* ISA has a three-operand multiplication instruction. */
817 #define ISA_HAS_DMUL3 (TARGET_64BIT \
818 && TARGET_OCTEON \
819 && !TARGET_MIPS16)
820
821 /* ISA has the floating-point conditional move instructions introduced
822 in mips4. */
823 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
824 || ISA_MIPS32 \
825 || ISA_MIPS32R2 \
826 || ISA_MIPS64 \
827 || ISA_MIPS64R2) \
828 && !TARGET_MIPS5500 \
829 && !TARGET_MIPS16)
830
831 /* ISA has the integer conditional move instructions introduced in mips4 and
832 ST Loongson 2E/2F. */
833 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
834
835 /* ISA has LDC1 and SDC1. */
836 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
837
838 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
839 branch on CC, and move (both FP and non-FP) on CC. */
840 #define ISA_HAS_8CC (ISA_MIPS4 \
841 || ISA_MIPS32 \
842 || ISA_MIPS32R2 \
843 || ISA_MIPS64 \
844 || ISA_MIPS64R2)
845
846 /* This is a catch all for other mips4 instructions: indexed load, the
847 FP madd and msub instructions, and the FP recip and recip sqrt
848 instructions. */
849 #define ISA_HAS_FP4 ((ISA_MIPS4 \
850 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
851 || ISA_MIPS64 \
852 || ISA_MIPS64R2) \
853 && !TARGET_MIPS16)
854
855 /* ISA has paired-single instructions. */
856 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
857
858 /* ISA has conditional trap instructions. */
859 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
860 && !TARGET_MIPS16)
861
862 /* ISA has integer multiply-accumulate instructions, madd and msub. */
863 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
864 || ISA_MIPS32R2 \
865 || ISA_MIPS64 \
866 || ISA_MIPS64R2) \
867 && !TARGET_MIPS16)
868
869 /* Integer multiply-accumulate instructions should be generated. */
870 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
871
872 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
873 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
874
875 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
876 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
877
878 /* ISA has floating-point nmadd and nmsub instructions
879 'd = -((a * b) [+-] c)'. */
880 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
881 ((ISA_MIPS4 \
882 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
883 || ISA_MIPS64 \
884 || ISA_MIPS64R2) \
885 && (!TARGET_MIPS5400 || TARGET_MAD) \
886 && !TARGET_MIPS16)
887
888 /* ISA has floating-point nmadd and nmsub instructions
889 'c = -((a * b) [+-] c)'. */
890 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
891 TARGET_LOONGSON_2EF
892
893 /* ISA has count leading zeroes/ones instruction (not implemented). */
894 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
895 || ISA_MIPS32R2 \
896 || ISA_MIPS64 \
897 || ISA_MIPS64R2) \
898 && !TARGET_MIPS16)
899
900 /* ISA has three operand multiply instructions that put
901 the high part in an accumulator: mulhi or mulhiu. */
902 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
903 || TARGET_MIPS5500 \
904 || TARGET_SR71K) \
905 && !TARGET_MIPS16)
906
907 /* ISA has three operand multiply instructions that
908 negates the result and puts the result in an accumulator. */
909 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
910 || TARGET_MIPS5500 \
911 || TARGET_SR71K) \
912 && !TARGET_MIPS16)
913
914 /* ISA has three operand multiply instructions that subtracts the
915 result from a 4th operand and puts the result in an accumulator. */
916 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
917 || TARGET_MIPS5500 \
918 || TARGET_SR71K) \
919 && !TARGET_MIPS16)
920
921 /* ISA has three operand multiply instructions that the result
922 from a 4th operand and puts the result in an accumulator. */
923 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
924 || TARGET_MIPS4130 \
925 || TARGET_MIPS5400 \
926 || TARGET_MIPS5500 \
927 || TARGET_SR71K) \
928 && !TARGET_MIPS16)
929
930 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
931 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
932 || TARGET_MIPS4130) \
933 && !TARGET_MIPS16)
934
935 /* ISA has the "ror" (rotate right) instructions. */
936 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
937 || ISA_MIPS64R2 \
938 || TARGET_MIPS5400 \
939 || TARGET_MIPS5500 \
940 || TARGET_SR71K \
941 || TARGET_SMARTMIPS) \
942 && !TARGET_MIPS16)
943
944 /* ISA has data prefetch instructions. This controls use of 'pref'. */
945 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
946 || TARGET_LOONGSON_2EF \
947 || ISA_MIPS32 \
948 || ISA_MIPS32R2 \
949 || ISA_MIPS64 \
950 || ISA_MIPS64R2) \
951 && !TARGET_MIPS16)
952
953 /* ISA has data indexed prefetch instructions. This controls use of
954 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
955 (prefx is a cop1x instruction, so can only be used if FP is
956 enabled.) */
957 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
958 || ISA_MIPS32R2 \
959 || ISA_MIPS64 \
960 || ISA_MIPS64R2) \
961 && !TARGET_MIPS16)
962
963 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
964 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
965 also requires TARGET_DOUBLE_FLOAT. */
966 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
967
968 /* ISA includes the MIPS32r2 seb and seh instructions. */
969 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
970 || ISA_MIPS64R2) \
971 && !TARGET_MIPS16)
972
973 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
974 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
975 || ISA_MIPS64R2) \
976 && !TARGET_MIPS16)
977
978 /* ISA has instructions for accessing top part of 64-bit fp regs. */
979 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
980 && (ISA_MIPS32R2 \
981 || ISA_MIPS64R2))
982
983 /* ISA has lwxs instruction (load w/scaled index address. */
984 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
985
986 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
987 #define ISA_HAS_LBX (TARGET_OCTEON2)
988 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
989 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
990 #define ISA_HAS_LHUX (TARGET_OCTEON2)
991 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
992 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
993 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
994 && TARGET_64BIT)
995
996 /* The DSP ASE is available. */
997 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
998
999 /* Revision 2 of the DSP ASE is available. */
1000 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1001
1002 /* True if the result of a load is not available to the next instruction.
1003 A nop will then be needed between instructions like "lw $4,..."
1004 and "addiu $4,$4,1". */
1005 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1006 && !TARGET_MIPS3900 \
1007 && !TARGET_MIPS16)
1008
1009 /* Likewise mtc1 and mfc1. */
1010 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1011 && !TARGET_LOONGSON_2EF)
1012
1013 /* Likewise floating-point comparisons. */
1014 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1015 && !TARGET_LOONGSON_2EF)
1016
1017 /* True if mflo and mfhi can be immediately followed by instructions
1018 which write to the HI and LO registers.
1019
1020 According to MIPS specifications, MIPS ISAs I, II, and III need
1021 (at least) two instructions between the reads of HI/LO and
1022 instructions which write them, and later ISAs do not. Contradicting
1023 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1024 the UM for the NEC Vr5000) document needing the instructions between
1025 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1026 MIPS64 and later ISAs to have the interlocks, plus any specific
1027 earlier-ISA CPUs for which CPU documentation declares that the
1028 instructions are really interlocked. */
1029 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1030 || ISA_MIPS32R2 \
1031 || ISA_MIPS64 \
1032 || ISA_MIPS64R2 \
1033 || TARGET_MIPS5500 \
1034 || TARGET_LOONGSON_2EF)
1035
1036 /* ISA includes synci, jr.hb and jalr.hb. */
1037 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1038 || ISA_MIPS64R2) \
1039 && !TARGET_MIPS16)
1040
1041 /* ISA includes sync. */
1042 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1043 #define GENERATE_SYNC \
1044 (target_flags_explicit & MASK_LLSC \
1045 ? TARGET_LLSC && !TARGET_MIPS16 \
1046 : ISA_HAS_SYNC)
1047
1048 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1049 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1050 instructions. */
1051 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1052 #define GENERATE_LL_SC \
1053 (target_flags_explicit & MASK_LLSC \
1054 ? TARGET_LLSC && !TARGET_MIPS16 \
1055 : ISA_HAS_LL_SC)
1056
1057 /* ISA includes the baddu instruction. */
1058 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1059
1060 /* ISA includes the bbit* instructions. */
1061 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1062
1063 /* ISA includes the cins instruction. */
1064 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1065
1066 /* ISA includes the exts instruction. */
1067 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1068
1069 /* ISA includes the seq and sne instructions. */
1070 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1071
1072 /* ISA includes the pop instruction. */
1073 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1074
1075 /* The CACHE instruction is available in non-MIPS16 code. */
1076 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1077
1078 /* The CACHE instruction is available. */
1079 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1080 \f
1081 /* Tell collect what flags to pass to nm. */
1082 #ifndef NM_FLAGS
1083 #define NM_FLAGS "-Bn"
1084 #endif
1085
1086 \f
1087 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1088 the assembler. It may be overridden by subtargets.
1089
1090 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1091 COFF debugging info. */
1092
1093 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1094 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1095 %{g} %{g0} %{g1} %{g2} %{g3} \
1096 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1097 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1098 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1099 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1100 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1101 #endif
1102
1103 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1104 overridden by subtargets. */
1105
1106 #ifndef SUBTARGET_ASM_SPEC
1107 #define SUBTARGET_ASM_SPEC ""
1108 #endif
1109
1110 #undef ASM_SPEC
1111 #define ASM_SPEC "\
1112 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1113 %{mips32*} %{mips64*} \
1114 %{mips16} %{mno-mips16:-no-mips16} \
1115 %{mips3d} %{mno-mips3d:-no-mips3d} \
1116 %{mdmx} %{mno-mdmx:-no-mdmx} \
1117 %{mdsp} %{mno-dsp} \
1118 %{mdspr2} %{mno-dspr2} \
1119 %{msmartmips} %{mno-smartmips} \
1120 %{mmt} %{mno-mt} \
1121 %{mfix-vr4120} %{mfix-vr4130} \
1122 %{mfix-24k} \
1123 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1124 %(subtarget_asm_debugging_spec) \
1125 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1126 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1127 %{mfp32} %{mfp64} \
1128 %{mshared} %{mno-shared} \
1129 %{msym32} %{mno-sym32} \
1130 %{mtune=*} \
1131 %(subtarget_asm_spec)"
1132
1133 /* Extra switches sometimes passed to the linker. */
1134
1135 #ifndef LINK_SPEC
1136 #define LINK_SPEC "\
1137 %(endian_spec) \
1138 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1139 %{shared}"
1140 #endif /* LINK_SPEC defined */
1141
1142
1143 /* Specs for the compiler proper */
1144
1145 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1146 overridden by subtargets. */
1147 #ifndef SUBTARGET_CC1_SPEC
1148 #define SUBTARGET_CC1_SPEC ""
1149 #endif
1150
1151 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1152
1153 #undef CC1_SPEC
1154 #define CC1_SPEC "\
1155 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1156 %(subtarget_cc1_spec)"
1157
1158 /* Preprocessor specs. */
1159
1160 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1161 overridden by subtargets. */
1162 #ifndef SUBTARGET_CPP_SPEC
1163 #define SUBTARGET_CPP_SPEC ""
1164 #endif
1165
1166 #define CPP_SPEC "%(subtarget_cpp_spec)"
1167
1168 /* This macro defines names of additional specifications to put in the specs
1169 that can be used in various specifications like CC1_SPEC. Its definition
1170 is an initializer with a subgrouping for each command option.
1171
1172 Each subgrouping contains a string constant, that defines the
1173 specification name, and a string constant that used by the GCC driver
1174 program.
1175
1176 Do not define this macro if it does not need to do anything. */
1177
1178 #define EXTRA_SPECS \
1179 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1180 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1181 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1182 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1183 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1184 { "endian_spec", ENDIAN_SPEC }, \
1185 SUBTARGET_EXTRA_SPECS
1186
1187 #ifndef SUBTARGET_EXTRA_SPECS
1188 #define SUBTARGET_EXTRA_SPECS
1189 #endif
1190 \f
1191 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1192 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1193
1194 #ifndef PREFERRED_DEBUGGING_TYPE
1195 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1196 #endif
1197
1198 /* The size of DWARF addresses should be the same as the size of symbols
1199 in the target file format. They shouldn't depend on things like -msym32,
1200 because many DWARF consumers do not allow the mixture of address sizes
1201 that one would then get from linking -msym32 code with -msym64 code.
1202
1203 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1204 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1205 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1206
1207 /* By default, turn on GDB extensions. */
1208 #define DEFAULT_GDB_EXTENSIONS 1
1209
1210 /* Local compiler-generated symbols must have a prefix that the assembler
1211 understands. By default, this is $, although some targets (e.g.,
1212 NetBSD-ELF) need to override this. */
1213
1214 #ifndef LOCAL_LABEL_PREFIX
1215 #define LOCAL_LABEL_PREFIX "$"
1216 #endif
1217
1218 /* By default on the mips, external symbols do not have an underscore
1219 prepended, but some targets (e.g., NetBSD) require this. */
1220
1221 #ifndef USER_LABEL_PREFIX
1222 #define USER_LABEL_PREFIX ""
1223 #endif
1224
1225 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1226 since the length can run past this up to a continuation point. */
1227 #undef DBX_CONTIN_LENGTH
1228 #define DBX_CONTIN_LENGTH 1500
1229
1230 /* How to renumber registers for dbx and gdb. */
1231 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1232
1233 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1234 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1235
1236 /* The DWARF 2 CFA column which tracks the return address. */
1237 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1238
1239 /* Before the prologue, RA lives in r31. */
1240 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1241
1242 /* Describe how we implement __builtin_eh_return. */
1243 #define EH_RETURN_DATA_REGNO(N) \
1244 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1245
1246 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1247
1248 #define EH_USES(N) mips_eh_uses (N)
1249
1250 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1251 The default for this in 64-bit mode is 8, which causes problems with
1252 SFmode register saves. */
1253 #define DWARF_CIE_DATA_ALIGNMENT -4
1254
1255 /* Correct the offset of automatic variables and arguments. Note that
1256 the MIPS debug format wants all automatic variables and arguments
1257 to be in terms of the virtual frame pointer (stack pointer before
1258 any adjustment in the function), while the MIPS 3.0 linker wants
1259 the frame pointer to be the stack pointer after the initial
1260 adjustment. */
1261
1262 #define DEBUGGER_AUTO_OFFSET(X) \
1263 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1264 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1265 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1266 \f
1267 /* Target machine storage layout */
1268
1269 #define BITS_BIG_ENDIAN 0
1270 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1271 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1272
1273 #define MAX_BITS_PER_WORD 64
1274
1275 /* Width of a word, in units (bytes). */
1276 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1277 #ifndef IN_LIBGCC2
1278 #define MIN_UNITS_PER_WORD 4
1279 #endif
1280
1281 /* For MIPS, width of a floating point register. */
1282 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1283
1284 /* The number of consecutive floating-point registers needed to store the
1285 largest format supported by the FPU. */
1286 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1287
1288 /* The number of consecutive floating-point registers needed to store the
1289 smallest format supported by the FPU. */
1290 #define MIN_FPRS_PER_FMT \
1291 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1292 ? 1 : MAX_FPRS_PER_FMT)
1293
1294 /* The largest size of value that can be held in floating-point
1295 registers and moved with a single instruction. */
1296 #define UNITS_PER_HWFPVALUE \
1297 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1298
1299 /* The largest size of value that can be held in floating-point
1300 registers. */
1301 #define UNITS_PER_FPVALUE \
1302 (TARGET_SOFT_FLOAT_ABI ? 0 \
1303 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1304 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1305
1306 /* The number of bytes in a double. */
1307 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1308
1309 /* Set the sizes of the core types. */
1310 #define SHORT_TYPE_SIZE 16
1311 #define INT_TYPE_SIZE 32
1312 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1313 #define LONG_LONG_TYPE_SIZE 64
1314
1315 #define FLOAT_TYPE_SIZE 32
1316 #define DOUBLE_TYPE_SIZE 64
1317 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1318
1319 /* Define the sizes of fixed-point types. */
1320 #define SHORT_FRACT_TYPE_SIZE 8
1321 #define FRACT_TYPE_SIZE 16
1322 #define LONG_FRACT_TYPE_SIZE 32
1323 #define LONG_LONG_FRACT_TYPE_SIZE 64
1324
1325 #define SHORT_ACCUM_TYPE_SIZE 16
1326 #define ACCUM_TYPE_SIZE 32
1327 #define LONG_ACCUM_TYPE_SIZE 64
1328 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1329 doesn't support 128-bit integers for MIPS32 currently. */
1330 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1331
1332 /* long double is not a fixed mode, but the idea is that, if we
1333 support long double, we also want a 128-bit integer type. */
1334 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1335
1336 #ifdef IN_LIBGCC2
1337 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1338 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1339 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1340 # else
1341 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1342 # endif
1343 #endif
1344
1345 /* Width in bits of a pointer. */
1346 #ifndef POINTER_SIZE
1347 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1348 #endif
1349
1350 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1351 #define PARM_BOUNDARY BITS_PER_WORD
1352
1353 /* Allocation boundary (in *bits*) for the code of a function. */
1354 #define FUNCTION_BOUNDARY 32
1355
1356 /* Alignment of field after `int : 0' in a structure. */
1357 #define EMPTY_FIELD_BOUNDARY 32
1358
1359 /* Every structure's size must be a multiple of this. */
1360 /* 8 is observed right on a DECstation and on riscos 4.02. */
1361 #define STRUCTURE_SIZE_BOUNDARY 8
1362
1363 /* There is no point aligning anything to a rounder boundary than this. */
1364 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1365
1366 /* All accesses must be aligned. */
1367 #define STRICT_ALIGNMENT 1
1368
1369 /* Define this if you wish to imitate the way many other C compilers
1370 handle alignment of bitfields and the structures that contain
1371 them.
1372
1373 The behavior is that the type written for a bit-field (`int',
1374 `short', or other integer type) imposes an alignment for the
1375 entire structure, as if the structure really did contain an
1376 ordinary field of that type. In addition, the bit-field is placed
1377 within the structure so that it would fit within such a field,
1378 not crossing a boundary for it.
1379
1380 Thus, on most machines, a bit-field whose type is written as `int'
1381 would not cross a four-byte boundary, and would force four-byte
1382 alignment for the whole structure. (The alignment used may not
1383 be four bytes; it is controlled by the other alignment
1384 parameters.)
1385
1386 If the macro is defined, its definition should be a C expression;
1387 a nonzero value for the expression enables this behavior. */
1388
1389 #define PCC_BITFIELD_TYPE_MATTERS 1
1390
1391 /* If defined, a C expression to compute the alignment given to a
1392 constant that is being placed in memory. CONSTANT is the constant
1393 and ALIGN is the alignment that the object would ordinarily have.
1394 The value of this macro is used instead of that alignment to align
1395 the object.
1396
1397 If this macro is not defined, then ALIGN is used.
1398
1399 The typical use of this macro is to increase alignment for string
1400 constants to be word aligned so that `strcpy' calls that copy
1401 constants can be done inline. */
1402
1403 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1404 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1405 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1406
1407 /* If defined, a C expression to compute the alignment for a static
1408 variable. TYPE is the data type, and ALIGN is the alignment that
1409 the object would ordinarily have. The value of this macro is used
1410 instead of that alignment to align the object.
1411
1412 If this macro is not defined, then ALIGN is used.
1413
1414 One use of this macro is to increase alignment of medium-size
1415 data to make it all fit in fewer cache lines. Another is to
1416 cause character arrays to be word-aligned so that `strcpy' calls
1417 that copy constants to character arrays can be done inline. */
1418
1419 #undef DATA_ALIGNMENT
1420 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1421 ((((ALIGN) < BITS_PER_WORD) \
1422 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1423 || TREE_CODE (TYPE) == UNION_TYPE \
1424 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1425
1426 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1427 character arrays to be word-aligned so that `strcpy' calls that copy
1428 constants to character arrays can be done inline, and 'strcmp' can be
1429 optimised to use word loads. */
1430 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1431 DATA_ALIGNMENT (TYPE, ALIGN)
1432
1433 #define PAD_VARARGS_DOWN \
1434 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1435
1436 /* Define if operations between registers always perform the operation
1437 on the full register even if a narrower mode is specified. */
1438 #define WORD_REGISTER_OPERATIONS
1439
1440 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1441 moves. All other references are zero extended. */
1442 #define LOAD_EXTEND_OP(MODE) \
1443 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1444 ? SIGN_EXTEND : ZERO_EXTEND)
1445
1446 /* Define this macro if it is advisable to hold scalars in registers
1447 in a wider mode than that declared by the program. In such cases,
1448 the value is constrained to be within the bounds of the declared
1449 type, but kept valid in the wider mode. The signedness of the
1450 extension may differ from that of the type. */
1451
1452 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1453 if (GET_MODE_CLASS (MODE) == MODE_INT \
1454 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1455 { \
1456 if ((MODE) == SImode) \
1457 (UNSIGNEDP) = 0; \
1458 (MODE) = Pmode; \
1459 }
1460
1461 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1462 Extensions of pointers to word_mode must be signed. */
1463 #define POINTERS_EXTEND_UNSIGNED false
1464
1465 /* Define if loading short immediate values into registers sign extends. */
1466 #define SHORT_IMMEDIATES_SIGN_EXTEND
1467
1468 /* The [d]clz instructions have the natural values at 0. */
1469
1470 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1471 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1472 \f
1473 /* Standard register usage. */
1474
1475 /* Number of hardware registers. We have:
1476
1477 - 32 integer registers
1478 - 32 floating point registers
1479 - 8 condition code registers
1480 - 2 accumulator registers (hi and lo)
1481 - 32 registers each for coprocessors 0, 2 and 3
1482 - 4 fake registers:
1483 - ARG_POINTER_REGNUM
1484 - FRAME_POINTER_REGNUM
1485 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1486 - CPRESTORE_SLOT_REGNUM
1487 - 2 dummy entries that were used at various times in the past.
1488 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1489 - 6 DSP control registers */
1490
1491 #define FIRST_PSEUDO_REGISTER 188
1492
1493 /* By default, fix the kernel registers ($26 and $27), the global
1494 pointer ($28) and the stack pointer ($29). This can change
1495 depending on the command-line options.
1496
1497 Regarding coprocessor registers: without evidence to the contrary,
1498 it's best to assume that each coprocessor register has a unique
1499 use. This can be overridden, in, e.g., mips_option_override or
1500 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1501 inappropriate for a particular target. */
1502
1503 #define FIXED_REGISTERS \
1504 { \
1505 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1506 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1507 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1508 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1509 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1510 /* COP0 registers */ \
1511 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1512 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1513 /* COP2 registers */ \
1514 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1515 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1516 /* COP3 registers */ \
1517 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1518 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1519 /* 6 DSP accumulator registers & 6 control registers */ \
1520 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1521 }
1522
1523
1524 /* Set up this array for o32 by default.
1525
1526 Note that we don't mark $31 as a call-clobbered register. The idea is
1527 that it's really the call instructions themselves which clobber $31.
1528 We don't care what the called function does with it afterwards.
1529
1530 This approach makes it easier to implement sibcalls. Unlike normal
1531 calls, sibcalls don't clobber $31, so the register reaches the
1532 called function in tact. EPILOGUE_USES says that $31 is useful
1533 to the called function. */
1534
1535 #define CALL_USED_REGISTERS \
1536 { \
1537 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1538 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1539 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1540 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1541 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1542 /* COP0 registers */ \
1543 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1544 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1545 /* COP2 registers */ \
1546 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1547 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1548 /* COP3 registers */ \
1549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1551 /* 6 DSP accumulator registers & 6 control registers */ \
1552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1553 }
1554
1555
1556 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1557
1558 #define CALL_REALLY_USED_REGISTERS \
1559 { /* General registers. */ \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1561 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1562 /* Floating-point registers. */ \
1563 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1564 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1565 /* Others. */ \
1566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1567 /* COP0 registers */ \
1568 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1569 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1570 /* COP2 registers */ \
1571 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1572 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1573 /* COP3 registers */ \
1574 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1575 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1576 /* 6 DSP accumulator registers & 6 control registers */ \
1577 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1578 }
1579
1580 /* Internal macros to classify a register number as to whether it's a
1581 general purpose register, a floating point register, a
1582 multiply/divide register, or a status register. */
1583
1584 #define GP_REG_FIRST 0
1585 #define GP_REG_LAST 31
1586 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1587 #define GP_DBX_FIRST 0
1588 #define K0_REG_NUM (GP_REG_FIRST + 26)
1589 #define K1_REG_NUM (GP_REG_FIRST + 27)
1590 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1591
1592 #define FP_REG_FIRST 32
1593 #define FP_REG_LAST 63
1594 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1595 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1596
1597 #define MD_REG_FIRST 64
1598 #define MD_REG_LAST 65
1599 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1600 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1601
1602 /* The DWARF 2 CFA column which tracks the return address from a
1603 signal handler context. This means that to maintain backwards
1604 compatibility, no hard register can be assigned this column if it
1605 would need to be handled by the DWARF unwinder. */
1606 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1607
1608 #define ST_REG_FIRST 67
1609 #define ST_REG_LAST 74
1610 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1611
1612
1613 /* FIXME: renumber. */
1614 #define COP0_REG_FIRST 80
1615 #define COP0_REG_LAST 111
1616 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1617
1618 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1619 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1620 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1621
1622 #define COP2_REG_FIRST 112
1623 #define COP2_REG_LAST 143
1624 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1625
1626 #define COP3_REG_FIRST 144
1627 #define COP3_REG_LAST 175
1628 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1629 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1630 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1631
1632 #define DSP_ACC_REG_FIRST 176
1633 #define DSP_ACC_REG_LAST 181
1634 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1635
1636 #define AT_REGNUM (GP_REG_FIRST + 1)
1637 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1638 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1639
1640 /* A few bitfield locations for the coprocessor registers. */
1641 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1642 the cause register for the EIC interrupt mode. */
1643 #define CAUSE_IPL 10
1644 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1645 #define SR_IPL 10
1646 /* Exception Level is at bit 1 of the status register. */
1647 #define SR_EXL 1
1648 /* Interrupt Enable is at bit 0 of the status register. */
1649 #define SR_IE 0
1650
1651 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1652 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1653 should be used instead. */
1654 #define FPSW_REGNUM ST_REG_FIRST
1655
1656 #define GP_REG_P(REGNO) \
1657 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1658 #define M16_REG_P(REGNO) \
1659 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1660 #define FP_REG_P(REGNO) \
1661 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1662 #define MD_REG_P(REGNO) \
1663 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1664 #define ST_REG_P(REGNO) \
1665 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1666 #define COP0_REG_P(REGNO) \
1667 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1668 #define COP2_REG_P(REGNO) \
1669 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1670 #define COP3_REG_P(REGNO) \
1671 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1672 #define ALL_COP_REG_P(REGNO) \
1673 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1674 /* Test if REGNO is one of the 6 new DSP accumulators. */
1675 #define DSP_ACC_REG_P(REGNO) \
1676 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1677 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1678 #define ACC_REG_P(REGNO) \
1679 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1680
1681 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1682
1683 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1684 to initialize the mips16 gp pseudo register. */
1685 #define CONST_GP_P(X) \
1686 (GET_CODE (X) == CONST \
1687 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1688 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1689
1690 /* Return coprocessor number from register number. */
1691
1692 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1693 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1694 : COP3_REG_P (REGNO) ? '3' : '?')
1695
1696
1697 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1698
1699 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1700 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1701
1702 #define MODES_TIEABLE_P mips_modes_tieable_p
1703
1704 /* Register to use for pushing function arguments. */
1705 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1706
1707 /* These two registers don't really exist: they get eliminated to either
1708 the stack or hard frame pointer. */
1709 #define ARG_POINTER_REGNUM 77
1710 #define FRAME_POINTER_REGNUM 78
1711
1712 /* $30 is not available on the mips16, so we use $17 as the frame
1713 pointer. */
1714 #define HARD_FRAME_POINTER_REGNUM \
1715 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1716
1717 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1718 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1719
1720 /* Register in which static-chain is passed to a function. */
1721 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1722
1723 /* Registers used as temporaries in prologue/epilogue code:
1724
1725 - If a MIPS16 PIC function needs access to _gp, it first loads
1726 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1727
1728 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1729 register. The register must not conflict with MIPS16_PIC_TEMP.
1730
1731 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1732 register.
1733
1734 If we're generating MIPS16 code, these registers must come from the
1735 core set of 8. The prologue registers mustn't conflict with any
1736 incoming arguments, the static chain pointer, or the frame pointer.
1737 The epilogue temporary mustn't conflict with the return registers,
1738 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1739 or the EH data registers.
1740
1741 If we're generating interrupt handlers, we use K0 as a temporary register
1742 in prologue/epilogue code. */
1743
1744 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1745 #define MIPS_PROLOGUE_TEMP_REGNUM \
1746 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1747 #define MIPS_EPILOGUE_TEMP_REGNUM \
1748 (cfun->machine->interrupt_handler_p \
1749 ? K0_REG_NUM \
1750 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1751
1752 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1753 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1754 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1755
1756 /* Define this macro if it is as good or better to call a constant
1757 function address than to call an address kept in a register. */
1758 #define NO_FUNCTION_CSE 1
1759
1760 /* The ABI-defined global pointer. Sometimes we use a different
1761 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1762 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1763
1764 /* We normally use $28 as the global pointer. However, when generating
1765 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1766 register instead. They can then avoid saving and restoring $28
1767 and perhaps avoid using a frame at all.
1768
1769 When a leaf function uses something other than $28, mips_expand_prologue
1770 will modify pic_offset_table_rtx in place. Take the register number
1771 from there after reload. */
1772 #define PIC_OFFSET_TABLE_REGNUM \
1773 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1774 \f
1775 /* Define the classes of registers for register constraints in the
1776 machine description. Also define ranges of constants.
1777
1778 One of the classes must always be named ALL_REGS and include all hard regs.
1779 If there is more than one class, another class must be named NO_REGS
1780 and contain no registers.
1781
1782 The name GENERAL_REGS must be the name of a class (or an alias for
1783 another name such as ALL_REGS). This is the class of registers
1784 that is allowed by "g" or "r" in a register constraint.
1785 Also, registers outside this class are allocated only when
1786 instructions express preferences for them.
1787
1788 The classes must be numbered in nondecreasing order; that is,
1789 a larger-numbered class must never be contained completely
1790 in a smaller-numbered class.
1791
1792 For any two classes, it is very desirable that there be another
1793 class that represents their union. */
1794
1795 enum reg_class
1796 {
1797 NO_REGS, /* no registers in set */
1798 M16_REGS, /* mips16 directly accessible registers */
1799 T_REG, /* mips16 T register ($24) */
1800 M16_T_REGS, /* mips16 registers plus T register */
1801 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1802 V1_REG, /* Register $v1 ($3) used for TLS access. */
1803 LEA_REGS, /* Every GPR except $25 */
1804 GR_REGS, /* integer registers */
1805 FP_REGS, /* floating point registers */
1806 MD0_REG, /* first multiply/divide register */
1807 MD1_REG, /* second multiply/divide register */
1808 MD_REGS, /* multiply/divide registers (hi/lo) */
1809 COP0_REGS, /* generic coprocessor classes */
1810 COP2_REGS,
1811 COP3_REGS,
1812 ST_REGS, /* status registers (fp status) */
1813 DSP_ACC_REGS, /* DSP accumulator registers */
1814 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1815 FRAME_REGS, /* $arg and $frame */
1816 GR_AND_MD0_REGS, /* union classes */
1817 GR_AND_MD1_REGS,
1818 GR_AND_MD_REGS,
1819 GR_AND_ACC_REGS,
1820 ALL_REGS, /* all registers */
1821 LIM_REG_CLASSES /* max value + 1 */
1822 };
1823
1824 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1825
1826 #define GENERAL_REGS GR_REGS
1827
1828 /* An initializer containing the names of the register classes as C
1829 string constants. These names are used in writing some of the
1830 debugging dumps. */
1831
1832 #define REG_CLASS_NAMES \
1833 { \
1834 "NO_REGS", \
1835 "M16_REGS", \
1836 "T_REG", \
1837 "M16_T_REGS", \
1838 "PIC_FN_ADDR_REG", \
1839 "V1_REG", \
1840 "LEA_REGS", \
1841 "GR_REGS", \
1842 "FP_REGS", \
1843 "MD0_REG", \
1844 "MD1_REG", \
1845 "MD_REGS", \
1846 /* coprocessor registers */ \
1847 "COP0_REGS", \
1848 "COP2_REGS", \
1849 "COP3_REGS", \
1850 "ST_REGS", \
1851 "DSP_ACC_REGS", \
1852 "ACC_REGS", \
1853 "FRAME_REGS", \
1854 "GR_AND_MD0_REGS", \
1855 "GR_AND_MD1_REGS", \
1856 "GR_AND_MD_REGS", \
1857 "GR_AND_ACC_REGS", \
1858 "ALL_REGS" \
1859 }
1860
1861 /* An initializer containing the contents of the register classes,
1862 as integers which are bit masks. The Nth integer specifies the
1863 contents of class N. The way the integer MASK is interpreted is
1864 that register R is in the class if `MASK & (1 << R)' is 1.
1865
1866 When the machine has more than 32 registers, an integer does not
1867 suffice. Then the integers are replaced by sub-initializers,
1868 braced groupings containing several integers. Each
1869 sub-initializer must be suitable as an initializer for the type
1870 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1871
1872 #define REG_CLASS_CONTENTS \
1873 { \
1874 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1875 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1876 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1877 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1878 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1879 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1880 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1881 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1882 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1883 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1884 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1885 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1886 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1887 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1888 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1889 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1890 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1891 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1892 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1893 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1894 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1895 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1896 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1897 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1898 }
1899
1900
1901 /* A C expression whose value is a register class containing hard
1902 register REGNO. In general there is more that one such class;
1903 choose a class which is "minimal", meaning that no smaller class
1904 also contains the register. */
1905
1906 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1907
1908 /* A macro whose definition is the name of the class to which a
1909 valid base register must belong. A base register is one used in
1910 an address which is the register value plus a displacement. */
1911
1912 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1913
1914 /* A macro whose definition is the name of the class to which a
1915 valid index register must belong. An index register is one used
1916 in an address where its value is either multiplied by a scale
1917 factor or added to another register (as well as added to a
1918 displacement). */
1919
1920 #define INDEX_REG_CLASS NO_REGS
1921
1922 /* We generally want to put call-clobbered registers ahead of
1923 call-saved ones. (IRA expects this.) */
1924
1925 #define REG_ALLOC_ORDER \
1926 { /* Accumulator registers. When GPRs and accumulators have equal \
1927 cost, we generally prefer to use accumulators. For example, \
1928 a division of multiplication result is better allocated to LO, \
1929 so that we put the MFLO at the point of use instead of at the \
1930 point of definition. It's also needed if we're to take advantage \
1931 of the extra accumulators available with -mdspr2. In some cases, \
1932 it can also help to reduce register pressure. */ \
1933 64, 65,176,177,178,179,180,181, \
1934 /* Call-clobbered GPRs. */ \
1935 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1936 24, 25, 31, \
1937 /* The global pointer. This is call-clobbered for o32 and o64 \
1938 abicalls, call-saved for n32 and n64 abicalls, and a program \
1939 invariant otherwise. Putting it between the call-clobbered \
1940 and call-saved registers should cope with all eventualities. */ \
1941 28, \
1942 /* Call-saved GPRs. */ \
1943 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1944 /* GPRs that can never be exposed to the register allocator. */ \
1945 0, 26, 27, 29, \
1946 /* Call-clobbered FPRs. */ \
1947 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1948 48, 49, 50, 51, \
1949 /* FPRs that are usually call-saved. The odd ones are actually \
1950 call-clobbered for n32, but listing them ahead of the even \
1951 registers might encourage the register allocator to fragment \
1952 the available FPR pairs. We need paired FPRs to store long \
1953 doubles, so it isn't clear that using a different order \
1954 for n32 would be a win. */ \
1955 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1956 /* None of the remaining classes have defined call-saved \
1957 registers. */ \
1958 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1959 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1960 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1961 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1962 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1963 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1964 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1965 182,183,184,185,186,187 \
1966 }
1967
1968 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1969 to be rearranged based on a particular function. On the mips16, we
1970 want to allocate $24 (T_REG) before other registers for
1971 instructions for which it is possible. */
1972
1973 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
1974
1975 /* True if VALUE is an unsigned 6-bit number. */
1976
1977 #define UIMM6_OPERAND(VALUE) \
1978 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1979
1980 /* True if VALUE is a signed 10-bit number. */
1981
1982 #define IMM10_OPERAND(VALUE) \
1983 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1984
1985 /* True if VALUE is a signed 16-bit number. */
1986
1987 #define SMALL_OPERAND(VALUE) \
1988 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1989
1990 /* True if VALUE is an unsigned 16-bit number. */
1991
1992 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1993 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1994
1995 /* True if VALUE can be loaded into a register using LUI. */
1996
1997 #define LUI_OPERAND(VALUE) \
1998 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1999 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2000
2001 /* Return a value X with the low 16 bits clear, and such that
2002 VALUE - X is a signed 16-bit value. */
2003
2004 #define CONST_HIGH_PART(VALUE) \
2005 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2006
2007 #define CONST_LOW_PART(VALUE) \
2008 ((VALUE) - CONST_HIGH_PART (VALUE))
2009
2010 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2011 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2012 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2013
2014 /* The HI and LO registers can only be reloaded via the general
2015 registers. Condition code registers can only be loaded to the
2016 general registers, and from the floating point registers. */
2017
2018 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2019 mips_secondary_reload_class (CLASS, MODE, X, true)
2020 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2021 mips_secondary_reload_class (CLASS, MODE, X, false)
2022
2023 /* Return the maximum number of consecutive registers
2024 needed to represent mode MODE in a register of class CLASS. */
2025
2026 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2027
2028 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2029 mips_cannot_change_mode_class (FROM, TO, CLASS)
2030 \f
2031 /* Stack layout; function entry, exit and calling. */
2032
2033 #define STACK_GROWS_DOWNWARD
2034
2035 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2036
2037 /* Size of the area allocated in the frame to save the GP. */
2038
2039 #define MIPS_GP_SAVE_AREA_SIZE \
2040 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2041
2042 /* The offset of the first local variable from the frame pointer. See
2043 mips_compute_frame_info for details about the frame layout. */
2044
2045 #define STARTING_FRAME_OFFSET \
2046 (FRAME_GROWS_DOWNWARD \
2047 ? 0 \
2048 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2049
2050 #define RETURN_ADDR_RTX mips_return_addr
2051
2052 /* Mask off the MIPS16 ISA bit in unwind addresses.
2053
2054 The reason for this is a little subtle. When unwinding a call,
2055 we are given the call's return address, which on most targets
2056 is the address of the following instruction. However, what we
2057 actually want to find is the EH region for the call itself.
2058 The target-independent unwind code therefore searches for "RA - 1".
2059
2060 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2061 RA - 1 is therefore the real (even-valued) start of the return
2062 instruction. EH region labels are usually odd-valued MIPS16 symbols
2063 too, so a search for an even address within a MIPS16 region would
2064 usually work.
2065
2066 However, there is an exception. If the end of an EH region is also
2067 the end of a function, the end label is allowed to be even. This is
2068 necessary because a following non-MIPS16 function may also need EH
2069 information for its first instruction.
2070
2071 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2072 non-ISA-encoded address. This probably isn't ideal, but it is
2073 the traditional (legacy) behavior. It is therefore only safe
2074 to search MIPS EH regions for an _odd-valued_ address.
2075
2076 Masking off the ISA bit means that the target-independent code
2077 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2078 #define MASK_RETURN_ADDR GEN_INT (-2)
2079
2080
2081 /* Similarly, don't use the least-significant bit to tell pointers to
2082 code from vtable index. */
2083
2084 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2085
2086 /* The eliminations to $17 are only used for mips16 code. See the
2087 definition of HARD_FRAME_POINTER_REGNUM. */
2088
2089 #define ELIMINABLE_REGS \
2090 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2091 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2092 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2093 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2094 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2095 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2096
2097 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2098 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2099
2100 /* Allocate stack space for arguments at the beginning of each function. */
2101 #define ACCUMULATE_OUTGOING_ARGS 1
2102
2103 /* The argument pointer always points to the first argument. */
2104 #define FIRST_PARM_OFFSET(FNDECL) 0
2105
2106 /* o32 and o64 reserve stack space for all argument registers. */
2107 #define REG_PARM_STACK_SPACE(FNDECL) \
2108 (TARGET_OLDABI \
2109 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2110 : 0)
2111
2112 /* Define this if it is the responsibility of the caller to
2113 allocate the area reserved for arguments passed in registers.
2114 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2115 of this macro is to determine whether the space is included in
2116 `crtl->outgoing_args_size'. */
2117 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2118
2119 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2120 \f
2121 /* Symbolic macros for the registers used to return integer and floating
2122 point values. */
2123
2124 #define GP_RETURN (GP_REG_FIRST + 2)
2125 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2126
2127 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2128
2129 /* Symbolic macros for the first/last argument registers. */
2130
2131 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2132 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2133 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2134 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2135
2136 /* 1 if N is a possible register number for function argument passing.
2137 We have no FP argument registers when soft-float. When FP registers
2138 are 32 bits, we can't directly reference the odd numbered ones. */
2139
2140 #define FUNCTION_ARG_REGNO_P(N) \
2141 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2142 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2143 && !fixed_regs[N])
2144 \f
2145 /* This structure has to cope with two different argument allocation
2146 schemes. Most MIPS ABIs view the arguments as a structure, of which
2147 the first N words go in registers and the rest go on the stack. If I
2148 < N, the Ith word might go in Ith integer argument register or in a
2149 floating-point register. For these ABIs, we only need to remember
2150 the offset of the current argument into the structure.
2151
2152 The EABI instead allocates the integer and floating-point arguments
2153 separately. The first N words of FP arguments go in FP registers,
2154 the rest go on the stack. Likewise, the first N words of the other
2155 arguments go in integer registers, and the rest go on the stack. We
2156 need to maintain three counts: the number of integer registers used,
2157 the number of floating-point registers used, and the number of words
2158 passed on the stack.
2159
2160 We could keep separate information for the two ABIs (a word count for
2161 the standard ABIs, and three separate counts for the EABI). But it
2162 seems simpler to view the standard ABIs as forms of EABI that do not
2163 allocate floating-point registers.
2164
2165 So for the standard ABIs, the first N words are allocated to integer
2166 registers, and mips_function_arg decides on an argument-by-argument
2167 basis whether that argument should really go in an integer register,
2168 or in a floating-point one. */
2169
2170 typedef struct mips_args {
2171 /* Always true for varargs functions. Otherwise true if at least
2172 one argument has been passed in an integer register. */
2173 int gp_reg_found;
2174
2175 /* The number of arguments seen so far. */
2176 unsigned int arg_number;
2177
2178 /* The number of integer registers used so far. For all ABIs except
2179 EABI, this is the number of words that have been added to the
2180 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2181 unsigned int num_gprs;
2182
2183 /* For EABI, the number of floating-point registers used so far. */
2184 unsigned int num_fprs;
2185
2186 /* The number of words passed on the stack. */
2187 unsigned int stack_words;
2188
2189 /* On the mips16, we need to keep track of which floating point
2190 arguments were passed in general registers, but would have been
2191 passed in the FP regs if this were a 32-bit function, so that we
2192 can move them to the FP regs if we wind up calling a 32-bit
2193 function. We record this information in fp_code, encoded in base
2194 four. A zero digit means no floating point argument, a one digit
2195 means an SFmode argument, and a two digit means a DFmode argument,
2196 and a three digit is not used. The low order digit is the first
2197 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2198 an SFmode argument. ??? A more sophisticated approach will be
2199 needed if MIPS_ABI != ABI_32. */
2200 int fp_code;
2201
2202 /* True if the function has a prototype. */
2203 int prototype;
2204 } CUMULATIVE_ARGS;
2205
2206 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2207 for a call to a function whose data type is FNTYPE.
2208 For a library call, FNTYPE is 0. */
2209
2210 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2211 mips_init_cumulative_args (&CUM, FNTYPE)
2212
2213 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2214 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2215
2216 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2217 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2218
2219 /* True if using EABI and varargs can be passed in floating-point
2220 registers. Under these conditions, we need a more complex form
2221 of va_list, which tracks GPR, FPR and stack arguments separately. */
2222 #define EABI_FLOAT_VARARGS_P \
2223 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2224
2225 \f
2226 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2227
2228 /* Treat LOC as a byte offset from the stack pointer and round it up
2229 to the next fully-aligned offset. */
2230 #define MIPS_STACK_ALIGN(LOC) \
2231 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2232
2233 \f
2234 /* Output assembler code to FILE to increment profiler label # LABELNO
2235 for profiling a function entry. */
2236
2237 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2238
2239 /* The profiler preserves all interesting registers, including $31. */
2240 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2241
2242 /* No mips port has ever used the profiler counter word, so don't emit it
2243 or the label for it. */
2244
2245 #define NO_PROFILE_COUNTERS 1
2246
2247 /* Define this macro if the code for function profiling should come
2248 before the function prologue. Normally, the profiling code comes
2249 after. */
2250
2251 /* #define PROFILE_BEFORE_PROLOGUE */
2252
2253 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2254 the stack pointer does not matter. The value is tested only in
2255 functions that have frame pointers.
2256 No definition is equivalent to always zero. */
2257
2258 #define EXIT_IGNORE_STACK 1
2259
2260 \f
2261 /* Trampolines are a block of code followed by two pointers. */
2262
2263 #define TRAMPOLINE_SIZE \
2264 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2265
2266 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2267 pointers from a single LUI base. */
2268
2269 #define TRAMPOLINE_ALIGNMENT 64
2270
2271 /* mips_trampoline_init calls this library function to flush
2272 program and data caches. */
2273
2274 #ifndef CACHE_FLUSH_FUNC
2275 #define CACHE_FLUSH_FUNC "_flush_cache"
2276 #endif
2277
2278 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2279 /* Flush both caches. We need to flush the data cache in case \
2280 the system has a write-back cache. */ \
2281 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2282 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2283 GEN_INT (3), TYPE_MODE (integer_type_node))
2284
2285 \f
2286 /* Addressing modes, and classification of registers for them. */
2287
2288 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2289 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2290 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2291 \f
2292 /* Maximum number of registers that can appear in a valid memory address. */
2293
2294 #define MAX_REGS_PER_ADDRESS 1
2295
2296 /* Check for constness inline but use mips_legitimate_address_p
2297 to check whether a constant really is an address. */
2298
2299 #define CONSTANT_ADDRESS_P(X) \
2300 (CONSTANT_P (X) && memory_address_p (SImode, X))
2301
2302 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2303 'the start of the function that this code is output in'. */
2304
2305 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2306 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2307 asm_fprintf ((FILE), "%U%s", \
2308 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2309 else \
2310 asm_fprintf ((FILE), "%U%s", (NAME))
2311 \f
2312 /* Flag to mark a function decl symbol that requires a long call. */
2313 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2314 #define SYMBOL_REF_LONG_CALL_P(X) \
2315 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2316
2317 /* This flag marks functions that cannot be lazily bound. */
2318 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2319 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2320 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2321
2322 /* True if we're generating a form of MIPS16 code in which jump tables
2323 are stored in the text section and encoded as 16-bit PC-relative
2324 offsets. This is only possible when general text loads are allowed,
2325 since the table access itself will be an "lh" instruction. */
2326 /* ??? 16-bit offsets can overflow in large functions. */
2327 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2328
2329 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2330
2331 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2332
2333 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2334
2335 /* Define this as 1 if `char' should by default be signed; else as 0. */
2336 #ifndef DEFAULT_SIGNED_CHAR
2337 #define DEFAULT_SIGNED_CHAR 1
2338 #endif
2339
2340 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2341 we generally don't want to use them for copying arbitrary data.
2342 A single N-word move is usually the same cost as N single-word moves. */
2343 #define MOVE_MAX UNITS_PER_WORD
2344 #define MAX_MOVE_MAX 8
2345
2346 /* Define this macro as a C expression which is nonzero if
2347 accessing less than a word of memory (i.e. a `char' or a
2348 `short') is no faster than accessing a word of memory, i.e., if
2349 such access require more than one instruction or if there is no
2350 difference in cost between byte and (aligned) word loads.
2351
2352 On RISC machines, it tends to generate better code to define
2353 this as 1, since it avoids making a QI or HI mode register.
2354
2355 But, generating word accesses for -mips16 is generally bad as shifts
2356 (often extended) would be needed for byte accesses. */
2357 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2358
2359 /* Standard MIPS integer shifts truncate the shift amount to the
2360 width of the shifted operand. However, Loongson vector shifts
2361 do not truncate the shift amount at all. */
2362 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2363
2364 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2365 is done just by pretending it is already truncated. */
2366 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2367 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2368
2369
2370 /* Specify the machine mode that pointers have.
2371 After generation of rtl, the compiler makes no further distinction
2372 between pointers and any other objects of this machine mode. */
2373
2374 #ifndef Pmode
2375 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2376 #endif
2377
2378 /* Give call MEMs SImode since it is the "most permissive" mode
2379 for both 32-bit and 64-bit targets. */
2380
2381 #define FUNCTION_MODE SImode
2382
2383 \f
2384
2385 /* Define if copies to/from condition code registers should be avoided.
2386
2387 This is needed for the MIPS because reload_outcc is not complete;
2388 it needs to handle cases where the source is a general or another
2389 condition code register. */
2390 #define AVOID_CCMODE_COPIES
2391
2392 /* A C expression for the cost of a branch instruction. A value of
2393 1 is the default; other values are interpreted relative to that. */
2394
2395 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2396 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2397
2398 /* If defined, modifies the length assigned to instruction INSN as a
2399 function of the context in which it is used. LENGTH is an lvalue
2400 that contains the initially computed length of the insn and should
2401 be updated with the correct length of the insn. */
2402 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2403 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2404
2405 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2406 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2407 its operands. */
2408 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2409 "%*" OPCODE "%?\t" OPERANDS "%/"
2410
2411 /* Return an asm string that forces INSN to be treated as an absolute
2412 J or JAL instruction instead of an assembler macro. */
2413 #define MIPS_ABSOLUTE_JUMP(INSN) \
2414 (TARGET_ABICALLS_PIC2 \
2415 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2416 : INSN)
2417
2418 /* Return the asm template for a call. INSN is the instruction's mnemonic
2419 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2420 number of the target. SIZE_OPNO is the operand number of the argument size
2421 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2422 -1 and the call is indirect, use the function symbol from the call
2423 attributes to attach a R_MIPS_JALR relocation to the call.
2424
2425 When generating GOT code without explicit relocation operators,
2426 all calls should use assembly macros. Otherwise, all indirect
2427 calls should use "jr" or "jalr"; we will arrange to restore $gp
2428 afterwards if necessary. Finally, we can only generate direct
2429 calls for -mabicalls by temporarily switching to non-PIC mode. */
2430 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2431 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2432 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2433 : (REG_P (OPERANDS[TARGET_OPNO]) \
2434 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2435 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2436 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2437 : REG_P (OPERANDS[TARGET_OPNO]) \
2438 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2439 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2440 \f
2441 /* Control the assembler format that we output. */
2442
2443 /* Output to assembler file text saying following lines
2444 may contain character constants, extra white space, comments, etc. */
2445
2446 #ifndef ASM_APP_ON
2447 #define ASM_APP_ON " #APP\n"
2448 #endif
2449
2450 /* Output to assembler file text saying following lines
2451 no longer contain unusual constructs. */
2452
2453 #ifndef ASM_APP_OFF
2454 #define ASM_APP_OFF " #NO_APP\n"
2455 #endif
2456
2457 #define REGISTER_NAMES \
2458 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2459 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2460 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2461 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2462 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2463 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2464 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2465 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2466 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2467 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2468 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2469 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2470 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2471 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2472 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2473 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2474 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2475 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2476 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2477 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2478 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2479 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2480 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2481 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2482
2483 /* List the "software" names for each register. Also list the numerical
2484 names for $fp and $sp. */
2485
2486 #define ADDITIONAL_REGISTER_NAMES \
2487 { \
2488 { "$29", 29 + GP_REG_FIRST }, \
2489 { "$30", 30 + GP_REG_FIRST }, \
2490 { "at", 1 + GP_REG_FIRST }, \
2491 { "v0", 2 + GP_REG_FIRST }, \
2492 { "v1", 3 + GP_REG_FIRST }, \
2493 { "a0", 4 + GP_REG_FIRST }, \
2494 { "a1", 5 + GP_REG_FIRST }, \
2495 { "a2", 6 + GP_REG_FIRST }, \
2496 { "a3", 7 + GP_REG_FIRST }, \
2497 { "t0", 8 + GP_REG_FIRST }, \
2498 { "t1", 9 + GP_REG_FIRST }, \
2499 { "t2", 10 + GP_REG_FIRST }, \
2500 { "t3", 11 + GP_REG_FIRST }, \
2501 { "t4", 12 + GP_REG_FIRST }, \
2502 { "t5", 13 + GP_REG_FIRST }, \
2503 { "t6", 14 + GP_REG_FIRST }, \
2504 { "t7", 15 + GP_REG_FIRST }, \
2505 { "s0", 16 + GP_REG_FIRST }, \
2506 { "s1", 17 + GP_REG_FIRST }, \
2507 { "s2", 18 + GP_REG_FIRST }, \
2508 { "s3", 19 + GP_REG_FIRST }, \
2509 { "s4", 20 + GP_REG_FIRST }, \
2510 { "s5", 21 + GP_REG_FIRST }, \
2511 { "s6", 22 + GP_REG_FIRST }, \
2512 { "s7", 23 + GP_REG_FIRST }, \
2513 { "t8", 24 + GP_REG_FIRST }, \
2514 { "t9", 25 + GP_REG_FIRST }, \
2515 { "k0", 26 + GP_REG_FIRST }, \
2516 { "k1", 27 + GP_REG_FIRST }, \
2517 { "gp", 28 + GP_REG_FIRST }, \
2518 { "sp", 29 + GP_REG_FIRST }, \
2519 { "fp", 30 + GP_REG_FIRST }, \
2520 { "ra", 31 + GP_REG_FIRST }, \
2521 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2522 }
2523
2524 /* This is meant to be redefined in the host dependent files. It is a
2525 set of alternative names and regnums for mips coprocessors. */
2526
2527 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2528
2529 #define DBR_OUTPUT_SEQEND(STREAM) \
2530 do \
2531 { \
2532 /* Undo the effect of '%*'. */ \
2533 mips_pop_asm_switch (&mips_nomacro); \
2534 mips_pop_asm_switch (&mips_noreorder); \
2535 /* Emit a blank line after the delay slot for emphasis. */ \
2536 fputs ("\n", STREAM); \
2537 } \
2538 while (0)
2539
2540 /* The MIPS implementation uses some labels for its own purpose. The
2541 following lists what labels are created, and are all formed by the
2542 pattern $L[a-z].*. The machine independent portion of GCC creates
2543 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2544
2545 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2546 $Lb[0-9]+ Begin blocks for MIPS debug support
2547 $Lc[0-9]+ Label for use in s<xx> operation.
2548 $Le[0-9]+ End blocks for MIPS debug support */
2549
2550 #undef ASM_DECLARE_OBJECT_NAME
2551 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2552 mips_declare_object (STREAM, NAME, "", ":\n")
2553
2554 /* Globalizing directive for a label. */
2555 #define GLOBAL_ASM_OP "\t.globl\t"
2556
2557 /* This says how to define a global common symbol. */
2558
2559 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2560
2561 /* This says how to define a local common symbol (i.e., not visible to
2562 linker). */
2563
2564 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2565 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2566 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2567 #endif
2568
2569 /* This says how to output an external. It would be possible not to
2570 output anything and let undefined symbol become external. However
2571 the assembler uses length information on externals to allocate in
2572 data/sdata bss/sbss, thereby saving exec time. */
2573
2574 #undef ASM_OUTPUT_EXTERNAL
2575 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2576 mips_output_external(STREAM,DECL,NAME)
2577
2578 /* This is how to declare a function name. The actual work of
2579 emitting the label is moved to function_prologue, so that we can
2580 get the line number correctly emitted before the .ent directive,
2581 and after any .file directives. Define as empty so that the function
2582 is not declared before the .ent directive elsewhere. */
2583
2584 #undef ASM_DECLARE_FUNCTION_NAME
2585 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2586
2587 /* This is how to store into the string LABEL
2588 the symbol_ref name of an internal numbered label where
2589 PREFIX is the class of label and NUM is the number within the class.
2590 This is suitable for output with `assemble_name'. */
2591
2592 #undef ASM_GENERATE_INTERNAL_LABEL
2593 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2594 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2595
2596 /* Print debug labels as "foo = ." rather than "foo:" because they should
2597 represent a byte pointer rather than an ISA-encoded address. This is
2598 particularly important for code like:
2599
2600 $LFBxxx = .
2601 .cfi_startproc
2602 ...
2603 .section .gcc_except_table,...
2604 ...
2605 .uleb128 foo-$LFBxxx
2606
2607 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2608 likewise a byte pointer rather than an ISA-encoded address.
2609
2610 At the time of writing, this hook is not used for the function end
2611 label:
2612
2613 $LFExxx:
2614 .end foo
2615
2616 But this doesn't matter, because GAS doesn't treat a pre-.end label
2617 as a MIPS16 one anyway. */
2618
2619 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2620 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2621
2622 /* This is how to output an element of a case-vector that is absolute. */
2623
2624 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2625 fprintf (STREAM, "\t%s\t%sL%d\n", \
2626 ptr_mode == DImode ? ".dword" : ".word", \
2627 LOCAL_LABEL_PREFIX, \
2628 VALUE)
2629
2630 /* This is how to output an element of a case-vector. We can make the
2631 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2632 is supported. */
2633
2634 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2635 do { \
2636 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2637 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2638 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2639 else if (TARGET_GPWORD) \
2640 fprintf (STREAM, "\t%s\t%sL%d\n", \
2641 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2642 LOCAL_LABEL_PREFIX, VALUE); \
2643 else if (TARGET_RTP_PIC) \
2644 { \
2645 /* Make the entry relative to the start of the function. */ \
2646 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2647 fprintf (STREAM, "\t%s\t%sL%d-", \
2648 Pmode == DImode ? ".dword" : ".word", \
2649 LOCAL_LABEL_PREFIX, VALUE); \
2650 assemble_name (STREAM, XSTR (fnsym, 0)); \
2651 fprintf (STREAM, "\n"); \
2652 } \
2653 else \
2654 fprintf (STREAM, "\t%s\t%sL%d\n", \
2655 ptr_mode == DImode ? ".dword" : ".word", \
2656 LOCAL_LABEL_PREFIX, VALUE); \
2657 } while (0)
2658
2659 /* This is how to output an assembler line
2660 that says to advance the location counter
2661 to a multiple of 2**LOG bytes. */
2662
2663 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2664 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2665
2666 /* This is how to output an assembler line to advance the location
2667 counter by SIZE bytes. */
2668
2669 #undef ASM_OUTPUT_SKIP
2670 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2671 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2672
2673 /* This is how to output a string. */
2674 #undef ASM_OUTPUT_ASCII
2675 #define ASM_OUTPUT_ASCII mips_output_ascii
2676
2677 /* Output #ident as a in the read-only data section. */
2678 #undef ASM_OUTPUT_IDENT
2679 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2680 { \
2681 const char *p = STRING; \
2682 int size = strlen (p) + 1; \
2683 switch_to_section (readonly_data_section); \
2684 assemble_string (p, size); \
2685 }
2686 \f
2687 /* Default to -G 8 */
2688 #ifndef MIPS_DEFAULT_GVALUE
2689 #define MIPS_DEFAULT_GVALUE 8
2690 #endif
2691
2692 /* Define the strings to put out for each section in the object file. */
2693 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2694 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2695
2696 #undef READONLY_DATA_SECTION_ASM_OP
2697 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2698 \f
2699 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2700 do \
2701 { \
2702 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2703 TARGET_64BIT ? "daddiu" : "addiu", \
2704 reg_names[STACK_POINTER_REGNUM], \
2705 reg_names[STACK_POINTER_REGNUM], \
2706 TARGET_64BIT ? "sd" : "sw", \
2707 reg_names[REGNO], \
2708 reg_names[STACK_POINTER_REGNUM]); \
2709 } \
2710 while (0)
2711
2712 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2713 do \
2714 { \
2715 mips_push_asm_switch (&mips_noreorder); \
2716 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2717 TARGET_64BIT ? "ld" : "lw", \
2718 reg_names[REGNO], \
2719 reg_names[STACK_POINTER_REGNUM], \
2720 TARGET_64BIT ? "daddu" : "addu", \
2721 reg_names[STACK_POINTER_REGNUM], \
2722 reg_names[STACK_POINTER_REGNUM]); \
2723 mips_pop_asm_switch (&mips_noreorder); \
2724 } \
2725 while (0)
2726
2727 /* How to start an assembler comment.
2728 The leading space is important (the mips native assembler requires it). */
2729 #ifndef ASM_COMMENT_START
2730 #define ASM_COMMENT_START " #"
2731 #endif
2732 \f
2733 #undef SIZE_TYPE
2734 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2735
2736 #undef PTRDIFF_TYPE
2737 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2738
2739 /* The maximum number of bytes that can be copied by one iteration of
2740 a movmemsi loop; see mips_block_move_loop. */
2741 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2742 (UNITS_PER_WORD * 4)
2743
2744 /* The maximum number of bytes that can be copied by a straight-line
2745 implementation of movmemsi; see mips_block_move_straight. We want
2746 to make sure that any loop-based implementation will iterate at
2747 least twice. */
2748 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2749 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2750
2751 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2752 values were determined experimentally by benchmarking with CSiBE.
2753 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2754 for o32 where we have to restore $gp afterwards as well as make an
2755 indirect call), but in practice, bumping this up higher for
2756 TARGET_ABICALLS doesn't make much difference to code size. */
2757
2758 #define MIPS_CALL_RATIO 8
2759
2760 /* Any loop-based implementation of movmemsi will have at least
2761 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2762 moves, so allow individual copies of fewer elements.
2763
2764 When movmemsi is not available, use a value approximating
2765 the length of a memcpy call sequence, so that move_by_pieces
2766 will generate inline code if it is shorter than a function call.
2767 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2768 we'll have to generate a load/store pair for each, halve the
2769 value of MIPS_CALL_RATIO to take that into account. */
2770
2771 #define MOVE_RATIO(speed) \
2772 (HAVE_movmemsi \
2773 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2774 : MIPS_CALL_RATIO / 2)
2775
2776 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2777 mips_move_by_pieces_p (SIZE, ALIGN)
2778
2779 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2780 of the length of a memset call, but use the default otherwise. */
2781
2782 #define CLEAR_RATIO(speed)\
2783 ((speed) ? 15 : MIPS_CALL_RATIO)
2784
2785 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2786 optimizing for size adjust the ratio to account for the overhead of
2787 loading the constant and replicating it across the word. */
2788
2789 #define SET_RATIO(speed) \
2790 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2791
2792 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2793 mips_store_by_pieces_p (SIZE, ALIGN)
2794 \f
2795 #ifndef __mips16
2796 /* Since the bits of the _init and _fini function is spread across
2797 many object files, each potentially with its own GP, we must assume
2798 we need to load our GP. We don't preserve $gp or $ra, since each
2799 init/fini chunk is supposed to initialize $gp, and crti/crtn
2800 already take care of preserving $ra and, when appropriate, $gp. */
2801 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2802 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2803 asm (SECTION_OP "\n\
2804 .set noreorder\n\
2805 bal 1f\n\
2806 nop\n\
2807 1: .cpload $31\n\
2808 .set reorder\n\
2809 jal " USER_LABEL_PREFIX #FUNC "\n\
2810 " TEXT_SECTION_ASM_OP);
2811 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2812 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2813 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2814 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2815 asm (SECTION_OP "\n\
2816 .set noreorder\n\
2817 bal 1f\n\
2818 nop\n\
2819 1: .set reorder\n\
2820 .cpsetup $31, $2, 1b\n\
2821 jal " USER_LABEL_PREFIX #FUNC "\n\
2822 " TEXT_SECTION_ASM_OP);
2823 #endif
2824 #endif
2825
2826 #ifndef HAVE_AS_TLS
2827 #define HAVE_AS_TLS 0
2828 #endif
2829
2830 #ifndef USED_FOR_TARGET
2831 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2832 struct mips_asm_switch {
2833 /* The FOO in the description above. */
2834 const char *name;
2835
2836 /* The current block nesting level, or 0 if we aren't in a block. */
2837 int nesting_level;
2838 };
2839
2840 extern const enum reg_class mips_regno_to_class[];
2841 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2842 extern const char *current_function_file; /* filename current function is in */
2843 extern int num_source_filenames; /* current .file # */
2844 extern struct mips_asm_switch mips_noreorder;
2845 extern struct mips_asm_switch mips_nomacro;
2846 extern struct mips_asm_switch mips_noat;
2847 extern int mips_dbx_regno[];
2848 extern int mips_dwarf_regno[];
2849 extern bool mips_split_p[];
2850 extern bool mips_split_hi_p[];
2851 extern bool mips_use_pcrel_pool_p[];
2852 extern const char *mips_lo_relocs[];
2853 extern const char *mips_hi_relocs[];
2854 extern enum processor mips_arch; /* which cpu to codegen for */
2855 extern enum processor mips_tune; /* which cpu to schedule for */
2856 extern int mips_isa; /* architectural level */
2857 extern const struct mips_cpu_info *mips_arch_info;
2858 extern const struct mips_cpu_info *mips_tune_info;
2859 extern bool mips_base_mips16;
2860 extern GTY(()) struct target_globals *mips16_globals;
2861 #endif
2862
2863 /* Enable querying of DFA units. */
2864 #define CPU_UNITS_QUERY 1
2865
2866 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2867 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2868
2869 /* As on most targets, we want the .eh_frame section to be read-only where
2870 possible. And as on most targets, this means two things:
2871
2872 (a) Non-locally-binding pointers must have an indirect encoding,
2873 so that the addresses in the .eh_frame section itself become
2874 locally-binding.
2875
2876 (b) A shared library's .eh_frame section must encode locally-binding
2877 pointers in a relative (relocation-free) form.
2878
2879 However, MIPS has traditionally not allowed directives like:
2880
2881 .long x-.
2882
2883 in cases where "x" is in a different section, or is not defined in the
2884 same assembly file. We are therefore unable to emit the PC-relative
2885 form required by (b) at assembly time.
2886
2887 Fortunately, the linker is able to convert absolute addresses into
2888 PC-relative addresses on our behalf. Unfortunately, only certain
2889 versions of the linker know how to do this for indirect pointers,
2890 and for personality data. We must fall back on using writable
2891 .eh_frame sections for shared libraries if the linker does not
2892 support this feature. */
2893 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2894 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2895
2896 /* For switching between MIPS16 and non-MIPS16 modes. */
2897 #define SWITCHABLE_TARGET 1
2898
2899 /* Several named MIPS patterns depend on Pmode. These patterns have the
2900 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2901 Add the appropriate suffix to generator function NAME and invoke it
2902 with arguments ARGS. */
2903 #define PMODE_INSN(NAME, ARGS) \
2904 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)