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mips-protos.h (mips_function_arg_advance): Delete
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
32 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
33 to work on a 64-bit machine. */
34
35 #define ABI_32 0
36 #define ABI_N32 1
37 #define ABI_64 2
38 #define ABI_EABI 3
39 #define ABI_O64 4
40
41 /* Masks that affect tuning.
42
43 PTF_AVOID_BRANCHLIKELY
44 Set if it is usually not profitable to use branch-likely instructions
45 for this target, typically because the branches are always predicted
46 taken and so incur a large overhead when not taken. */
47 #define PTF_AVOID_BRANCHLIKELY 0x1
48
49 /* Information about one recognized processor. Defined here for the
50 benefit of TARGET_CPU_CPP_BUILTINS. */
51 struct mips_cpu_info {
52 /* The 'canonical' name of the processor as far as GCC is concerned.
53 It's typically a manufacturer's prefix followed by a numerical
54 designation. It should be lowercase. */
55 const char *name;
56
57 /* The internal processor number that most closely matches this
58 entry. Several processors can have the same value, if there's no
59 difference between them from GCC's point of view. */
60 enum processor cpu;
61
62 /* The ISA level that the processor implements. */
63 int isa;
64
65 /* A mask of PTF_* values. */
66 unsigned int tune_flags;
67 };
68
69 /* Enumerates the setting of the -mcode-readable option. */
70 enum mips_code_readable_setting {
71 CODE_READABLE_NO,
72 CODE_READABLE_PCREL,
73 CODE_READABLE_YES
74 };
75
76 /* Macros to silence warnings about numbers being signed in traditional
77 C and unsigned in ISO C when compiled on 32-bit hosts. */
78
79 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
80 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
81 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
82
83 \f
84 /* Run-time compilation parameters selecting different hardware subsets. */
85
86 /* True if we are generating position-independent VxWorks RTP code. */
87 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
88
89 /* True if the output file is marked as ".abicalls; .option pic0"
90 (-call_nonpic). */
91 #define TARGET_ABICALLS_PIC0 \
92 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
93
94 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
95 #define TARGET_ABICALLS_PIC2 \
96 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
97
98 /* True if the call patterns should be split into a jalr followed by
99 an instruction to restore $gp. It is only safe to split the load
100 from the call when every use of $gp is explicit.
101
102 See mips_must_initialize_gp_p for details about how we manage the
103 global pointer. */
104
105 #define TARGET_SPLIT_CALLS \
106 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
107
108 /* True if we're generating a form of -mabicalls in which we can use
109 operators like %hi and %lo to refer to locally-binding symbols.
110 We can only do this for -mno-shared, and only then if we can use
111 relocation operations instead of assembly macros. It isn't really
112 worth using absolute sequences for 64-bit symbols because GOT
113 accesses are so much shorter. */
114
115 #define TARGET_ABSOLUTE_ABICALLS \
116 (TARGET_ABICALLS \
117 && !TARGET_SHARED \
118 && TARGET_EXPLICIT_RELOCS \
119 && !ABI_HAS_64BIT_SYMBOLS)
120
121 /* True if we can optimize sibling calls. For simplicity, we only
122 handle cases in which call_insn_operand will reject invalid
123 sibcall addresses. There are two cases in which this isn't true:
124
125 - TARGET_MIPS16. call_insn_operand accepts constant addresses
126 but there is no direct jump instruction. It isn't worth
127 using sibling calls in this case anyway; they would usually
128 be longer than normal calls.
129
130 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
131 accepts global constants, but all sibcalls must be indirect. */
132 #define TARGET_SIBCALLS \
133 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
134
135 /* True if we need to use a global offset table to access some symbols. */
136 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
137
138 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
139 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
140
141 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
142 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
143
144 /* True if we should use .cprestore to store to the cprestore slot.
145
146 We continue to use .cprestore for explicit-reloc code so that JALs
147 inside inline asms will work correctly. */
148 #define TARGET_CPRESTORE_DIRECTIVE \
149 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
150
151 /* True if we can use the J and JAL instructions. */
152 #define TARGET_ABSOLUTE_JUMPS \
153 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
154
155 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
156 This is true for both the PIC and non-PIC VxWorks RTP modes. */
157 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
158
159 /* True if .gpword or .gpdword should be used for switch tables.
160
161 Although GAS does understand .gpdword, the SGI linker mishandles
162 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
163 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
164 #define TARGET_GPWORD \
165 (TARGET_ABICALLS \
166 && !TARGET_ABSOLUTE_ABICALLS \
167 && !(mips_abi == ABI_64 && TARGET_IRIX6))
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Generate mips16 code */
178 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
179 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
180 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
181 /* Generate mips16e register save/restore sequences. */
182 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
183
184 /* True if we're generating a form of MIPS16 code in which general
185 text loads are allowed. */
186 #define TARGET_MIPS16_TEXT_LOADS \
187 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
188
189 /* True if we're generating a form of MIPS16 code in which PC-relative
190 loads are allowed. */
191 #define TARGET_MIPS16_PCREL_LOADS \
192 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
193
194 /* Generic ISA defines. */
195 #define ISA_MIPS1 (mips_isa == 1)
196 #define ISA_MIPS2 (mips_isa == 2)
197 #define ISA_MIPS3 (mips_isa == 3)
198 #define ISA_MIPS4 (mips_isa == 4)
199 #define ISA_MIPS32 (mips_isa == 32)
200 #define ISA_MIPS32R2 (mips_isa == 33)
201 #define ISA_MIPS64 (mips_isa == 64)
202 #define ISA_MIPS64R2 (mips_isa == 65)
203
204 /* Architecture target defines. */
205 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
206 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
207 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
208 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
209 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
210 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
211 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
212 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
213 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
214 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
215 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
216 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
217 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
218 || mips_arch == PROCESSOR_SB1A)
219 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
220
221 /* Scheduling target defines. */
222 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
223 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
224 || mips_tune == PROCESSOR_24KF2_1 \
225 || mips_tune == PROCESSOR_24KF1_1)
226 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
227 || mips_tune == PROCESSOR_74KF2_1 \
228 || mips_tune == PROCESSOR_74KF1_1 \
229 || mips_tune == PROCESSOR_74KF3_2)
230 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
231 || mips_tune == PROCESSOR_LOONGSON_2F)
232 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
233 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
234 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
235 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
236 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
237 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
238 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
239 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
240 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
241 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
242 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
243 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
244 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
245 || mips_tune == PROCESSOR_SB1A)
246
247 /* Whether vector modes and intrinsics for ST Microelectronics
248 Loongson-2E/2F processors should be enabled. In o32 pairs of
249 floating-point registers provide 64-bit values. */
250 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
251 && TARGET_LOONGSON_2EF)
252
253 /* True if the pre-reload scheduler should try to create chains of
254 multiply-add or multiply-subtract instructions. For example,
255 suppose we have:
256
257 t1 = a * b
258 t2 = t1 + c * d
259 t3 = e * f
260 t4 = t3 - g * h
261
262 t1 will have a higher priority than t2 and t3 will have a higher
263 priority than t4. However, before reload, there is no dependence
264 between t1 and t3, and they can often have similar priorities.
265 The scheduler will then tend to prefer:
266
267 t1 = a * b
268 t3 = e * f
269 t2 = t1 + c * d
270 t4 = t3 - g * h
271
272 which stops us from making full use of macc/madd-style instructions.
273 This sort of situation occurs frequently in Fourier transforms and
274 in unrolled loops.
275
276 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
277 queue so that chained multiply-add and multiply-subtract instructions
278 appear ahead of any other instruction that is likely to clobber lo.
279 In the example above, if t2 and t3 become ready at the same time,
280 the code ensures that t2 is scheduled first.
281
282 Multiply-accumulate instructions are a bigger win for some targets
283 than others, so this macro is defined on an opt-in basis. */
284 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
285 || TUNE_MIPS4120 \
286 || TUNE_MIPS4130 \
287 || TUNE_24K)
288
289 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
290 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
291
292 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
293 directly accessible, while the command-line options select
294 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
295 in use. */
296 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
297 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
298
299 /* False if SC acts as a memory barrier with respect to itself,
300 otherwise a SYNC will be emitted after SC for atomic operations
301 that require ordering between the SC and following loads and
302 stores. It does not tell anything about ordering of loads and
303 stores prior to and following the SC, only about the SC itself and
304 those loads and stores follow it. */
305 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
306
307 /* IRIX specific stuff. */
308 #define TARGET_IRIX6 0
309
310 /* Define preprocessor macros for the -march and -mtune options.
311 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
312 processor. If INFO's canonical name is "foo", define PREFIX to
313 be "foo", and define an additional macro PREFIX_FOO. */
314 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
315 do \
316 { \
317 char *macro, *p; \
318 \
319 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
320 for (p = macro; *p != 0; p++) \
321 *p = TOUPPER (*p); \
322 \
323 builtin_define (macro); \
324 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
325 free (macro); \
326 } \
327 while (0)
328
329 /* Target CPU builtins. */
330 #define TARGET_CPU_CPP_BUILTINS() \
331 do \
332 { \
333 /* Everyone but IRIX defines this to mips. */ \
334 if (!TARGET_IRIX6) \
335 builtin_assert ("machine=mips"); \
336 \
337 builtin_assert ("cpu=mips"); \
338 builtin_define ("__mips__"); \
339 builtin_define ("_mips"); \
340 \
341 /* We do this here because __mips is defined below and so we \
342 can't use builtin_define_std. We don't ever want to define \
343 "mips" for VxWorks because some of the VxWorks headers \
344 construct include filenames from a root directory macro, \
345 an architecture macro and a filename, where the architecture \
346 macro expands to 'mips'. If we define 'mips' to 1, the \
347 architecture macro expands to 1 as well. */ \
348 if (!flag_iso && !TARGET_VXWORKS) \
349 builtin_define ("mips"); \
350 \
351 if (TARGET_64BIT) \
352 builtin_define ("__mips64"); \
353 \
354 if (!TARGET_IRIX6) \
355 { \
356 /* Treat _R3000 and _R4000 like register-size \
357 defines, which is how they've historically \
358 been used. */ \
359 if (TARGET_64BIT) \
360 { \
361 builtin_define_std ("R4000"); \
362 builtin_define ("_R4000"); \
363 } \
364 else \
365 { \
366 builtin_define_std ("R3000"); \
367 builtin_define ("_R3000"); \
368 } \
369 } \
370 if (TARGET_FLOAT64) \
371 builtin_define ("__mips_fpr=64"); \
372 else \
373 builtin_define ("__mips_fpr=32"); \
374 \
375 if (mips_base_mips16) \
376 builtin_define ("__mips16"); \
377 \
378 if (TARGET_MIPS3D) \
379 builtin_define ("__mips3d"); \
380 \
381 if (TARGET_SMARTMIPS) \
382 builtin_define ("__mips_smartmips"); \
383 \
384 if (TARGET_DSP) \
385 { \
386 builtin_define ("__mips_dsp"); \
387 if (TARGET_DSPR2) \
388 { \
389 builtin_define ("__mips_dspr2"); \
390 builtin_define ("__mips_dsp_rev=2"); \
391 } \
392 else \
393 builtin_define ("__mips_dsp_rev=1"); \
394 } \
395 \
396 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
397 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
398 \
399 if (ISA_MIPS1) \
400 { \
401 builtin_define ("__mips=1"); \
402 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
403 } \
404 else if (ISA_MIPS2) \
405 { \
406 builtin_define ("__mips=2"); \
407 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
408 } \
409 else if (ISA_MIPS3) \
410 { \
411 builtin_define ("__mips=3"); \
412 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
413 } \
414 else if (ISA_MIPS4) \
415 { \
416 builtin_define ("__mips=4"); \
417 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
418 } \
419 else if (ISA_MIPS32) \
420 { \
421 builtin_define ("__mips=32"); \
422 builtin_define ("__mips_isa_rev=1"); \
423 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
424 } \
425 else if (ISA_MIPS32R2) \
426 { \
427 builtin_define ("__mips=32"); \
428 builtin_define ("__mips_isa_rev=2"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
430 } \
431 else if (ISA_MIPS64) \
432 { \
433 builtin_define ("__mips=64"); \
434 builtin_define ("__mips_isa_rev=1"); \
435 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
436 } \
437 else if (ISA_MIPS64R2) \
438 { \
439 builtin_define ("__mips=64"); \
440 builtin_define ("__mips_isa_rev=2"); \
441 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
442 } \
443 \
444 switch (mips_abi) \
445 { \
446 case ABI_32: \
447 builtin_define ("_ABIO32=1"); \
448 builtin_define ("_MIPS_SIM=_ABIO32"); \
449 break; \
450 \
451 case ABI_N32: \
452 builtin_define ("_ABIN32=2"); \
453 builtin_define ("_MIPS_SIM=_ABIN32"); \
454 break; \
455 \
456 case ABI_64: \
457 builtin_define ("_ABI64=3"); \
458 builtin_define ("_MIPS_SIM=_ABI64"); \
459 break; \
460 \
461 case ABI_O64: \
462 builtin_define ("_ABIO64=4"); \
463 builtin_define ("_MIPS_SIM=_ABIO64"); \
464 break; \
465 } \
466 \
467 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
468 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
469 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
470 builtin_define_with_int_value ("_MIPS_FPSET", \
471 32 / MAX_FPRS_PER_FMT); \
472 \
473 /* These defines reflect the ABI in use, not whether the \
474 FPU is directly accessible. */ \
475 if (TARGET_NO_FLOAT) \
476 builtin_define ("__mips_no_float"); \
477 else if (TARGET_HARD_FLOAT_ABI) \
478 builtin_define ("__mips_hard_float"); \
479 else \
480 builtin_define ("__mips_soft_float"); \
481 \
482 if (TARGET_SINGLE_FLOAT) \
483 builtin_define ("__mips_single_float"); \
484 \
485 if (TARGET_PAIRED_SINGLE_FLOAT) \
486 builtin_define ("__mips_paired_single_float"); \
487 \
488 if (TARGET_BIG_ENDIAN) \
489 { \
490 builtin_define_std ("MIPSEB"); \
491 builtin_define ("_MIPSEB"); \
492 } \
493 else \
494 { \
495 builtin_define_std ("MIPSEL"); \
496 builtin_define ("_MIPSEL"); \
497 } \
498 \
499 /* Whether calls should go through $25. The separate __PIC__ \
500 macro indicates whether abicalls code might use a GOT. */ \
501 if (TARGET_ABICALLS) \
502 builtin_define ("__mips_abicalls"); \
503 \
504 /* Whether Loongson vector modes are enabled. */ \
505 if (TARGET_LOONGSON_VECTORS) \
506 builtin_define ("__mips_loongson_vector_rev"); \
507 \
508 /* Historical Octeon macro. */ \
509 if (TARGET_OCTEON) \
510 builtin_define ("__OCTEON__"); \
511 \
512 /* Macros dependent on the C dialect. */ \
513 if (preprocessing_asm_p ()) \
514 { \
515 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
516 builtin_define ("_LANGUAGE_ASSEMBLY"); \
517 } \
518 else if (c_dialect_cxx ()) \
519 { \
520 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
521 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
522 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
523 } \
524 else \
525 { \
526 builtin_define_std ("LANGUAGE_C"); \
527 builtin_define ("_LANGUAGE_C"); \
528 } \
529 if (c_dialect_objc ()) \
530 { \
531 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
532 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
533 /* Bizarre, but needed at least for Irix. */ \
534 builtin_define_std ("LANGUAGE_C"); \
535 builtin_define ("_LANGUAGE_C"); \
536 } \
537 \
538 if (mips_abi == ABI_EABI) \
539 builtin_define ("__mips_eabi"); \
540 \
541 if (TARGET_CACHE_BUILTIN) \
542 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
543 } \
544 while (0)
545
546 /* Default target_flags if no switches are specified */
547
548 #ifndef TARGET_DEFAULT
549 #define TARGET_DEFAULT 0
550 #endif
551
552 #ifndef TARGET_CPU_DEFAULT
553 #define TARGET_CPU_DEFAULT 0
554 #endif
555
556 #ifndef TARGET_ENDIAN_DEFAULT
557 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
558 #endif
559
560 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
561 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
562 #endif
563
564 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
565 #ifndef MIPS_ISA_DEFAULT
566 #ifndef MIPS_CPU_STRING_DEFAULT
567 #define MIPS_CPU_STRING_DEFAULT "from-abi"
568 #endif
569 #endif
570
571 #ifdef IN_LIBGCC2
572 #undef TARGET_64BIT
573 /* Make this compile time constant for libgcc2 */
574 #ifdef __mips64
575 #define TARGET_64BIT 1
576 #else
577 #define TARGET_64BIT 0
578 #endif
579 #endif /* IN_LIBGCC2 */
580
581 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
582 when compiled with hardware floating point. This is because MIPS16
583 code cannot save and restore the floating-point registers, which is
584 important if in a mixed MIPS16/non-MIPS16 environment. */
585
586 #ifdef IN_LIBGCC2
587 #if __mips_hard_float
588 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
589 #endif
590 #endif /* IN_LIBGCC2 */
591
592 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
593
594 #ifndef MULTILIB_ENDIAN_DEFAULT
595 #if TARGET_ENDIAN_DEFAULT == 0
596 #define MULTILIB_ENDIAN_DEFAULT "EL"
597 #else
598 #define MULTILIB_ENDIAN_DEFAULT "EB"
599 #endif
600 #endif
601
602 #ifndef MULTILIB_ISA_DEFAULT
603 # if MIPS_ISA_DEFAULT == 1
604 # define MULTILIB_ISA_DEFAULT "mips1"
605 # else
606 # if MIPS_ISA_DEFAULT == 2
607 # define MULTILIB_ISA_DEFAULT "mips2"
608 # else
609 # if MIPS_ISA_DEFAULT == 3
610 # define MULTILIB_ISA_DEFAULT "mips3"
611 # else
612 # if MIPS_ISA_DEFAULT == 4
613 # define MULTILIB_ISA_DEFAULT "mips4"
614 # else
615 # if MIPS_ISA_DEFAULT == 32
616 # define MULTILIB_ISA_DEFAULT "mips32"
617 # else
618 # if MIPS_ISA_DEFAULT == 33
619 # define MULTILIB_ISA_DEFAULT "mips32r2"
620 # else
621 # if MIPS_ISA_DEFAULT == 64
622 # define MULTILIB_ISA_DEFAULT "mips64"
623 # else
624 # if MIPS_ISA_DEFAULT == 65
625 # define MULTILIB_ISA_DEFAULT "mips64r2"
626 # else
627 # define MULTILIB_ISA_DEFAULT "mips1"
628 # endif
629 # endif
630 # endif
631 # endif
632 # endif
633 # endif
634 # endif
635 # endif
636 #endif
637
638 #ifndef MIPS_ABI_DEFAULT
639 #define MIPS_ABI_DEFAULT ABI_32
640 #endif
641
642 /* Use the most portable ABI flag for the ASM specs. */
643
644 #if MIPS_ABI_DEFAULT == ABI_32
645 #define MULTILIB_ABI_DEFAULT "mabi=32"
646 #endif
647
648 #if MIPS_ABI_DEFAULT == ABI_O64
649 #define MULTILIB_ABI_DEFAULT "mabi=o64"
650 #endif
651
652 #if MIPS_ABI_DEFAULT == ABI_N32
653 #define MULTILIB_ABI_DEFAULT "mabi=n32"
654 #endif
655
656 #if MIPS_ABI_DEFAULT == ABI_64
657 #define MULTILIB_ABI_DEFAULT "mabi=64"
658 #endif
659
660 #if MIPS_ABI_DEFAULT == ABI_EABI
661 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
662 #endif
663
664 #ifndef MULTILIB_DEFAULTS
665 #define MULTILIB_DEFAULTS \
666 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
667 #endif
668
669 /* We must pass -EL to the linker by default for little endian embedded
670 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
671 linker will default to using big-endian output files. The OUTPUT_FORMAT
672 line must be in the linker script, otherwise -EB/-EL will not work. */
673
674 #ifndef ENDIAN_SPEC
675 #if TARGET_ENDIAN_DEFAULT == 0
676 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
677 #else
678 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
679 #endif
680 #endif
681
682 /* A spec condition that matches all non-mips16 -mips arguments. */
683
684 #define MIPS_ISA_LEVEL_OPTION_SPEC \
685 "mips1|mips2|mips3|mips4|mips32*|mips64*"
686
687 /* A spec condition that matches all non-mips16 architecture arguments. */
688
689 #define MIPS_ARCH_OPTION_SPEC \
690 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
691
692 /* A spec that infers a -mips argument from an -march argument,
693 or injects the default if no architecture is specified. */
694
695 #define MIPS_ISA_LEVEL_SPEC \
696 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
697 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
698 %{march=mips2|march=r6000:-mips2} \
699 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
700 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
701 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
702 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
703 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
704 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
705 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
706 |march=xlr: -mips64} \
707 %{march=mips64r2|march=octeon: -mips64r2} \
708 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
709
710 /* A spec that infers a -mhard-float or -msoft-float setting from an
711 -march argument. Note that soft-float and hard-float code are not
712 link-compatible. */
713
714 #define MIPS_ARCH_FLOAT_SPEC \
715 "%{mhard-float|msoft-float|march=mips*:; \
716 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
717 |march=34kc|march=74kc|march=1004kc|march=5kc \
718 |march=octeon|march=xlr: -msoft-float; \
719 march=*: -mhard-float}"
720
721 /* A spec condition that matches 32-bit options. It only works if
722 MIPS_ISA_LEVEL_SPEC has been applied. */
723
724 #define MIPS_32BIT_OPTION_SPEC \
725 "mips1|mips2|mips32*|mgp32"
726
727 #if MIPS_ABI_DEFAULT == ABI_O64 \
728 || MIPS_ABI_DEFAULT == ABI_N32 \
729 || MIPS_ABI_DEFAULT == ABI_64
730 #define OPT_ARCH64 "mabi=32|mgp32:;"
731 #define OPT_ARCH32 "mabi=32|mgp32"
732 #else
733 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
734 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
735 #endif
736
737 /* Support for a compile-time default CPU, et cetera. The rules are:
738 --with-arch is ignored if -march is specified or a -mips is specified
739 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
740 --with-tune is ignored if -mtune is specified; likewise
741 --with-tune-32 and --with-tune-64.
742 --with-abi is ignored if -mabi is specified.
743 --with-float is ignored if -mhard-float or -msoft-float are
744 specified.
745 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
746 specified. */
747 #define OPTION_DEFAULT_SPECS \
748 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
749 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
750 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
751 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
752 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
753 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
754 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
755 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
756 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
757 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
758 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
759 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
760
761
762 /* A spec that infers the -mdsp setting from an -march argument. */
763 #define BASE_DRIVER_SELF_SPECS \
764 "%{!mno-dsp:%{march=24ke*|march=34k*|march=74k*|march=1004k*: -mdsp}}"
765
766 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
767
768 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
769 && ISA_HAS_COND_TRAP)
770
771 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
772
773 /* True if the ABI can only work with 64-bit integer registers. We
774 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
775 otherwise floating-point registers must also be 64-bit. */
776 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
777
778 /* Likewise for 32-bit regs. */
779 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
780
781 /* True if the file format uses 64-bit symbols. At present, this is
782 only true for n64, which uses 64-bit ELF. */
783 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
784
785 /* True if symbols are 64 bits wide. This is usually determined by
786 the ABI's file format, but it can be overridden by -msym32. Note that
787 overriding the size with -msym32 changes the ABI of relocatable objects,
788 although it doesn't change the ABI of a fully-linked object. */
789 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS && !TARGET_SYM32)
790
791 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
792 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
793 || ISA_MIPS4 \
794 || ISA_MIPS64 \
795 || ISA_MIPS64R2)
796
797 /* ISA has branch likely instructions (e.g. mips2). */
798 /* Disable branchlikely for tx39 until compare rewrite. They haven't
799 been generated up to this point. */
800 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
801
802 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
803 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
804 || TARGET_MIPS5400 \
805 || TARGET_MIPS5500 \
806 || TARGET_MIPS7000 \
807 || TARGET_MIPS9000 \
808 || TARGET_MAD \
809 || ISA_MIPS32 \
810 || ISA_MIPS32R2 \
811 || ISA_MIPS64 \
812 || ISA_MIPS64R2) \
813 && !TARGET_MIPS16)
814
815 /* ISA has a three-operand multiplication instruction. */
816 #define ISA_HAS_DMUL3 (TARGET_64BIT \
817 && TARGET_OCTEON \
818 && !TARGET_MIPS16)
819
820 /* ISA has the floating-point conditional move instructions introduced
821 in mips4. */
822 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
823 || ISA_MIPS32 \
824 || ISA_MIPS32R2 \
825 || ISA_MIPS64 \
826 || ISA_MIPS64R2) \
827 && !TARGET_MIPS5500 \
828 && !TARGET_MIPS16)
829
830 /* ISA has the integer conditional move instructions introduced in mips4 and
831 ST Loongson 2E/2F. */
832 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
833
834 /* ISA has LDC1 and SDC1. */
835 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
836
837 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
838 branch on CC, and move (both FP and non-FP) on CC. */
839 #define ISA_HAS_8CC (ISA_MIPS4 \
840 || ISA_MIPS32 \
841 || ISA_MIPS32R2 \
842 || ISA_MIPS64 \
843 || ISA_MIPS64R2)
844
845 /* This is a catch all for other mips4 instructions: indexed load, the
846 FP madd and msub instructions, and the FP recip and recip sqrt
847 instructions. */
848 #define ISA_HAS_FP4 ((ISA_MIPS4 \
849 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
850 || ISA_MIPS64 \
851 || ISA_MIPS64R2) \
852 && !TARGET_MIPS16)
853
854 /* ISA has paired-single instructions. */
855 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
856
857 /* ISA has conditional trap instructions. */
858 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
859 && !TARGET_MIPS16)
860
861 /* ISA has integer multiply-accumulate instructions, madd and msub. */
862 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
863 || ISA_MIPS32R2 \
864 || ISA_MIPS64 \
865 || ISA_MIPS64R2) \
866 && !TARGET_MIPS16)
867
868 /* Integer multiply-accumulate instructions should be generated. */
869 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
870
871 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
872 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
873
874 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
875 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
876
877 /* ISA has floating-point nmadd and nmsub instructions
878 'd = -((a * b) [+-] c)'. */
879 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
880 ((ISA_MIPS4 \
881 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
882 || ISA_MIPS64 \
883 || ISA_MIPS64R2) \
884 && (!TARGET_MIPS5400 || TARGET_MAD) \
885 && !TARGET_MIPS16)
886
887 /* ISA has floating-point nmadd and nmsub instructions
888 'c = -((a * b) [+-] c)'. */
889 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
890 TARGET_LOONGSON_2EF
891
892 /* ISA has count leading zeroes/ones instruction (not implemented). */
893 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
894 || ISA_MIPS32R2 \
895 || ISA_MIPS64 \
896 || ISA_MIPS64R2) \
897 && !TARGET_MIPS16)
898
899 /* ISA has three operand multiply instructions that put
900 the high part in an accumulator: mulhi or mulhiu. */
901 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
902 || TARGET_MIPS5500 \
903 || TARGET_SR71K) \
904 && !TARGET_MIPS16)
905
906 /* ISA has three operand multiply instructions that
907 negates the result and puts the result in an accumulator. */
908 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
909 || TARGET_MIPS5500 \
910 || TARGET_SR71K) \
911 && !TARGET_MIPS16)
912
913 /* ISA has three operand multiply instructions that subtracts the
914 result from a 4th operand and puts the result in an accumulator. */
915 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
916 || TARGET_MIPS5500 \
917 || TARGET_SR71K) \
918 && !TARGET_MIPS16)
919
920 /* ISA has three operand multiply instructions that the result
921 from a 4th operand and puts the result in an accumulator. */
922 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
923 || TARGET_MIPS4130 \
924 || TARGET_MIPS5400 \
925 || TARGET_MIPS5500 \
926 || TARGET_SR71K) \
927 && !TARGET_MIPS16)
928
929 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
930 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
931 || TARGET_MIPS4130) \
932 && !TARGET_MIPS16)
933
934 /* ISA has the "ror" (rotate right) instructions. */
935 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
936 || ISA_MIPS64R2 \
937 || TARGET_MIPS5400 \
938 || TARGET_MIPS5500 \
939 || TARGET_SR71K \
940 || TARGET_SMARTMIPS) \
941 && !TARGET_MIPS16)
942
943 /* ISA has data prefetch instructions. This controls use of 'pref'. */
944 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
945 || TARGET_LOONGSON_2EF \
946 || ISA_MIPS32 \
947 || ISA_MIPS32R2 \
948 || ISA_MIPS64 \
949 || ISA_MIPS64R2) \
950 && !TARGET_MIPS16)
951
952 /* ISA has data indexed prefetch instructions. This controls use of
953 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
954 (prefx is a cop1x instruction, so can only be used if FP is
955 enabled.) */
956 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
957 || ISA_MIPS32R2 \
958 || ISA_MIPS64 \
959 || ISA_MIPS64R2) \
960 && !TARGET_MIPS16)
961
962 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
963 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
964 also requires TARGET_DOUBLE_FLOAT. */
965 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
966
967 /* ISA includes the MIPS32r2 seb and seh instructions. */
968 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
969 || ISA_MIPS64R2) \
970 && !TARGET_MIPS16)
971
972 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
973 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
974 || ISA_MIPS64R2) \
975 && !TARGET_MIPS16)
976
977 /* ISA has instructions for accessing top part of 64-bit fp regs. */
978 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
979 && (ISA_MIPS32R2 \
980 || ISA_MIPS64R2))
981
982 /* ISA has lwxs instruction (load w/scaled index address. */
983 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
984
985 /* The DSP ASE is available. */
986 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
987
988 /* Revision 2 of the DSP ASE is available. */
989 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
990
991 /* True if the result of a load is not available to the next instruction.
992 A nop will then be needed between instructions like "lw $4,..."
993 and "addiu $4,$4,1". */
994 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
995 && !TARGET_MIPS3900 \
996 && !TARGET_MIPS16)
997
998 /* Likewise mtc1 and mfc1. */
999 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1000 && !TARGET_LOONGSON_2EF)
1001
1002 /* Likewise floating-point comparisons. */
1003 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1004 && !TARGET_LOONGSON_2EF)
1005
1006 /* True if mflo and mfhi can be immediately followed by instructions
1007 which write to the HI and LO registers.
1008
1009 According to MIPS specifications, MIPS ISAs I, II, and III need
1010 (at least) two instructions between the reads of HI/LO and
1011 instructions which write them, and later ISAs do not. Contradicting
1012 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1013 the UM for the NEC Vr5000) document needing the instructions between
1014 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1015 MIPS64 and later ISAs to have the interlocks, plus any specific
1016 earlier-ISA CPUs for which CPU documentation declares that the
1017 instructions are really interlocked. */
1018 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1019 || ISA_MIPS32R2 \
1020 || ISA_MIPS64 \
1021 || ISA_MIPS64R2 \
1022 || TARGET_MIPS5500 \
1023 || TARGET_LOONGSON_2EF)
1024
1025 /* ISA includes synci, jr.hb and jalr.hb. */
1026 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1027 || ISA_MIPS64R2) \
1028 && !TARGET_MIPS16)
1029
1030 /* ISA includes sync. */
1031 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1032 #define GENERATE_SYNC \
1033 (target_flags_explicit & MASK_LLSC \
1034 ? TARGET_LLSC && !TARGET_MIPS16 \
1035 : ISA_HAS_SYNC)
1036
1037 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1038 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1039 instructions. */
1040 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1041 #define GENERATE_LL_SC \
1042 (target_flags_explicit & MASK_LLSC \
1043 ? TARGET_LLSC && !TARGET_MIPS16 \
1044 : ISA_HAS_LL_SC)
1045
1046 /* ISA includes the baddu instruction. */
1047 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1048
1049 /* ISA includes the bbit* instructions. */
1050 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1051
1052 /* ISA includes the cins instruction. */
1053 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1054
1055 /* ISA includes the exts instruction. */
1056 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1057
1058 /* ISA includes the seq and sne instructions. */
1059 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1060
1061 /* ISA includes the pop instruction. */
1062 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1063
1064 /* The CACHE instruction is available in non-MIPS16 code. */
1065 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1066
1067 /* The CACHE instruction is available. */
1068 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1069 \f
1070 /* Add -G xx support. */
1071
1072 #undef SWITCH_TAKES_ARG
1073 #define SWITCH_TAKES_ARG(CHAR) \
1074 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1075
1076 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1077
1078 /* Show we can debug even without a frame pointer. */
1079 #define CAN_DEBUG_WITHOUT_FP
1080 \f
1081 /* Tell collect what flags to pass to nm. */
1082 #ifndef NM_FLAGS
1083 #define NM_FLAGS "-Bn"
1084 #endif
1085
1086 \f
1087 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1088 to the assembler. It may be overridden by subtargets. */
1089 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1090 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1091 %{noasmopt:-O0} \
1092 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1093 #endif
1094
1095 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1096 the assembler. It may be overridden by subtargets.
1097
1098 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1099 COFF debugging info. */
1100
1101 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1102 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1103 %{g} %{g0} %{g1} %{g2} %{g3} \
1104 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1105 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1106 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1107 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1108 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1109 #endif
1110
1111 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1112 overridden by subtargets. */
1113
1114 #ifndef SUBTARGET_ASM_SPEC
1115 #define SUBTARGET_ASM_SPEC ""
1116 #endif
1117
1118 #undef ASM_SPEC
1119 #define ASM_SPEC "\
1120 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1121 %{mips32*} %{mips64*} \
1122 %{mips16} %{mno-mips16:-no-mips16} \
1123 %{mips3d} %{mno-mips3d:-no-mips3d} \
1124 %{mdmx} %{mno-mdmx:-no-mdmx} \
1125 %{mdsp} %{mno-dsp} \
1126 %{mdspr2} %{mno-dspr2} \
1127 %{msmartmips} %{mno-smartmips} \
1128 %{mmt} %{mno-mt} \
1129 %{mfix-vr4120} %{mfix-vr4130} \
1130 %(subtarget_asm_optimizing_spec) \
1131 %(subtarget_asm_debugging_spec) \
1132 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1133 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1134 %{mfp32} %{mfp64} \
1135 %{mshared} %{mno-shared} \
1136 %{msym32} %{mno-sym32} \
1137 %{mtune=*} %{v} \
1138 %(subtarget_asm_spec)"
1139
1140 /* Extra switches sometimes passed to the linker. */
1141 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1142 will interpret it as a -b option. */
1143
1144 #ifndef LINK_SPEC
1145 #define LINK_SPEC "\
1146 %(endian_spec) \
1147 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1148 %{bestGnum} %{shared} %{non_shared}"
1149 #endif /* LINK_SPEC defined */
1150
1151
1152 /* Specs for the compiler proper */
1153
1154 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1155 overridden by subtargets. */
1156 #ifndef SUBTARGET_CC1_SPEC
1157 #define SUBTARGET_CC1_SPEC ""
1158 #endif
1159
1160 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1161
1162 #undef CC1_SPEC
1163 #define CC1_SPEC "\
1164 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1165 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1166 %{save-temps: } \
1167 %(subtarget_cc1_spec)"
1168
1169 /* Preprocessor specs. */
1170
1171 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1172 overridden by subtargets. */
1173 #ifndef SUBTARGET_CPP_SPEC
1174 #define SUBTARGET_CPP_SPEC ""
1175 #endif
1176
1177 #define CPP_SPEC "%(subtarget_cpp_spec)"
1178
1179 /* This macro defines names of additional specifications to put in the specs
1180 that can be used in various specifications like CC1_SPEC. Its definition
1181 is an initializer with a subgrouping for each command option.
1182
1183 Each subgrouping contains a string constant, that defines the
1184 specification name, and a string constant that used by the GCC driver
1185 program.
1186
1187 Do not define this macro if it does not need to do anything. */
1188
1189 #define EXTRA_SPECS \
1190 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1191 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1192 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1193 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1194 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1195 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1196 { "endian_spec", ENDIAN_SPEC }, \
1197 SUBTARGET_EXTRA_SPECS
1198
1199 #ifndef SUBTARGET_EXTRA_SPECS
1200 #define SUBTARGET_EXTRA_SPECS
1201 #endif
1202 \f
1203 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1204 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1205
1206 #ifndef PREFERRED_DEBUGGING_TYPE
1207 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1208 #endif
1209
1210 /* The size of DWARF addresses should be the same as the size of symbols
1211 in the target file format. They shouldn't depend on things like -msym32,
1212 because many DWARF consumers do not allow the mixture of address sizes
1213 that one would then get from linking -msym32 code with -msym64 code.
1214
1215 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1216 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1217 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1218
1219 /* By default, turn on GDB extensions. */
1220 #define DEFAULT_GDB_EXTENSIONS 1
1221
1222 /* Local compiler-generated symbols must have a prefix that the assembler
1223 understands. By default, this is $, although some targets (e.g.,
1224 NetBSD-ELF) need to override this. */
1225
1226 #ifndef LOCAL_LABEL_PREFIX
1227 #define LOCAL_LABEL_PREFIX "$"
1228 #endif
1229
1230 /* By default on the mips, external symbols do not have an underscore
1231 prepended, but some targets (e.g., NetBSD) require this. */
1232
1233 #ifndef USER_LABEL_PREFIX
1234 #define USER_LABEL_PREFIX ""
1235 #endif
1236
1237 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1238 since the length can run past this up to a continuation point. */
1239 #undef DBX_CONTIN_LENGTH
1240 #define DBX_CONTIN_LENGTH 1500
1241
1242 /* How to renumber registers for dbx and gdb. */
1243 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1244
1245 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1246 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1247
1248 /* The DWARF 2 CFA column which tracks the return address. */
1249 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1250
1251 /* Before the prologue, RA lives in r31. */
1252 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1253
1254 /* Describe how we implement __builtin_eh_return. */
1255 #define EH_RETURN_DATA_REGNO(N) \
1256 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1257
1258 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1259
1260 #define EH_USES(N) mips_eh_uses (N)
1261
1262 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1263 The default for this in 64-bit mode is 8, which causes problems with
1264 SFmode register saves. */
1265 #define DWARF_CIE_DATA_ALIGNMENT -4
1266
1267 /* Correct the offset of automatic variables and arguments. Note that
1268 the MIPS debug format wants all automatic variables and arguments
1269 to be in terms of the virtual frame pointer (stack pointer before
1270 any adjustment in the function), while the MIPS 3.0 linker wants
1271 the frame pointer to be the stack pointer after the initial
1272 adjustment. */
1273
1274 #define DEBUGGER_AUTO_OFFSET(X) \
1275 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1276 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1277 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1278 \f
1279 /* Target machine storage layout */
1280
1281 #define BITS_BIG_ENDIAN 0
1282 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1283 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1284
1285 /* Define this to set the endianness to use in libgcc2.c, which can
1286 not depend on target_flags. */
1287 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1288 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1289 #else
1290 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1291 #endif
1292
1293 #define MAX_BITS_PER_WORD 64
1294
1295 /* Width of a word, in units (bytes). */
1296 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1297 #ifndef IN_LIBGCC2
1298 #define MIN_UNITS_PER_WORD 4
1299 #endif
1300
1301 /* For MIPS, width of a floating point register. */
1302 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1303
1304 /* The number of consecutive floating-point registers needed to store the
1305 largest format supported by the FPU. */
1306 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1307
1308 /* The number of consecutive floating-point registers needed to store the
1309 smallest format supported by the FPU. */
1310 #define MIN_FPRS_PER_FMT \
1311 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1312 ? 1 : MAX_FPRS_PER_FMT)
1313
1314 /* The largest size of value that can be held in floating-point
1315 registers and moved with a single instruction. */
1316 #define UNITS_PER_HWFPVALUE \
1317 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1318
1319 /* The largest size of value that can be held in floating-point
1320 registers. */
1321 #define UNITS_PER_FPVALUE \
1322 (TARGET_SOFT_FLOAT_ABI ? 0 \
1323 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1324 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1325
1326 /* The number of bytes in a double. */
1327 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1328
1329 #define UNITS_PER_SIMD_WORD(MODE) \
1330 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1331
1332 /* Set the sizes of the core types. */
1333 #define SHORT_TYPE_SIZE 16
1334 #define INT_TYPE_SIZE 32
1335 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1336 #define LONG_LONG_TYPE_SIZE 64
1337
1338 #define FLOAT_TYPE_SIZE 32
1339 #define DOUBLE_TYPE_SIZE 64
1340 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1341
1342 /* Define the sizes of fixed-point types. */
1343 #define SHORT_FRACT_TYPE_SIZE 8
1344 #define FRACT_TYPE_SIZE 16
1345 #define LONG_FRACT_TYPE_SIZE 32
1346 #define LONG_LONG_FRACT_TYPE_SIZE 64
1347
1348 #define SHORT_ACCUM_TYPE_SIZE 16
1349 #define ACCUM_TYPE_SIZE 32
1350 #define LONG_ACCUM_TYPE_SIZE 64
1351 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1352 doesn't support 128-bit integers for MIPS32 currently. */
1353 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1354
1355 /* long double is not a fixed mode, but the idea is that, if we
1356 support long double, we also want a 128-bit integer type. */
1357 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1358
1359 #ifdef IN_LIBGCC2
1360 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1361 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1362 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1363 # else
1364 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1365 # endif
1366 #endif
1367
1368 /* Width in bits of a pointer. */
1369 #ifndef POINTER_SIZE
1370 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1371 #endif
1372
1373 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1374 #define PARM_BOUNDARY BITS_PER_WORD
1375
1376 /* Allocation boundary (in *bits*) for the code of a function. */
1377 #define FUNCTION_BOUNDARY 32
1378
1379 /* Alignment of field after `int : 0' in a structure. */
1380 #define EMPTY_FIELD_BOUNDARY 32
1381
1382 /* Every structure's size must be a multiple of this. */
1383 /* 8 is observed right on a DECstation and on riscos 4.02. */
1384 #define STRUCTURE_SIZE_BOUNDARY 8
1385
1386 /* There is no point aligning anything to a rounder boundary than this. */
1387 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1388
1389 /* All accesses must be aligned. */
1390 #define STRICT_ALIGNMENT 1
1391
1392 /* Define this if you wish to imitate the way many other C compilers
1393 handle alignment of bitfields and the structures that contain
1394 them.
1395
1396 The behavior is that the type written for a bit-field (`int',
1397 `short', or other integer type) imposes an alignment for the
1398 entire structure, as if the structure really did contain an
1399 ordinary field of that type. In addition, the bit-field is placed
1400 within the structure so that it would fit within such a field,
1401 not crossing a boundary for it.
1402
1403 Thus, on most machines, a bit-field whose type is written as `int'
1404 would not cross a four-byte boundary, and would force four-byte
1405 alignment for the whole structure. (The alignment used may not
1406 be four bytes; it is controlled by the other alignment
1407 parameters.)
1408
1409 If the macro is defined, its definition should be a C expression;
1410 a nonzero value for the expression enables this behavior. */
1411
1412 #define PCC_BITFIELD_TYPE_MATTERS 1
1413
1414 /* If defined, a C expression to compute the alignment given to a
1415 constant that is being placed in memory. CONSTANT is the constant
1416 and ALIGN is the alignment that the object would ordinarily have.
1417 The value of this macro is used instead of that alignment to align
1418 the object.
1419
1420 If this macro is not defined, then ALIGN is used.
1421
1422 The typical use of this macro is to increase alignment for string
1423 constants to be word aligned so that `strcpy' calls that copy
1424 constants can be done inline. */
1425
1426 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1427 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1428 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1429
1430 /* If defined, a C expression to compute the alignment for a static
1431 variable. TYPE is the data type, and ALIGN is the alignment that
1432 the object would ordinarily have. The value of this macro is used
1433 instead of that alignment to align the object.
1434
1435 If this macro is not defined, then ALIGN is used.
1436
1437 One use of this macro is to increase alignment of medium-size
1438 data to make it all fit in fewer cache lines. Another is to
1439 cause character arrays to be word-aligned so that `strcpy' calls
1440 that copy constants to character arrays can be done inline. */
1441
1442 #undef DATA_ALIGNMENT
1443 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1444 ((((ALIGN) < BITS_PER_WORD) \
1445 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1446 || TREE_CODE (TYPE) == UNION_TYPE \
1447 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1448
1449 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1450 character arrays to be word-aligned so that `strcpy' calls that copy
1451 constants to character arrays can be done inline, and 'strcmp' can be
1452 optimised to use word loads. */
1453 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1454 DATA_ALIGNMENT (TYPE, ALIGN)
1455
1456 #define PAD_VARARGS_DOWN \
1457 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1458
1459 /* Define if operations between registers always perform the operation
1460 on the full register even if a narrower mode is specified. */
1461 #define WORD_REGISTER_OPERATIONS
1462
1463 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1464 moves. All other references are zero extended. */
1465 #define LOAD_EXTEND_OP(MODE) \
1466 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1467 ? SIGN_EXTEND : ZERO_EXTEND)
1468
1469 /* Define this macro if it is advisable to hold scalars in registers
1470 in a wider mode than that declared by the program. In such cases,
1471 the value is constrained to be within the bounds of the declared
1472 type, but kept valid in the wider mode. The signedness of the
1473 extension may differ from that of the type. */
1474
1475 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1476 if (GET_MODE_CLASS (MODE) == MODE_INT \
1477 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1478 { \
1479 if ((MODE) == SImode) \
1480 (UNSIGNEDP) = 0; \
1481 (MODE) = Pmode; \
1482 }
1483
1484 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1485 Extensions of pointers to word_mode must be signed. */
1486 #define POINTERS_EXTEND_UNSIGNED false
1487
1488 /* Define if loading short immediate values into registers sign extends. */
1489 #define SHORT_IMMEDIATES_SIGN_EXTEND
1490
1491 /* The [d]clz instructions have the natural values at 0. */
1492
1493 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1494 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1495 \f
1496 /* Standard register usage. */
1497
1498 /* Number of hardware registers. We have:
1499
1500 - 32 integer registers
1501 - 32 floating point registers
1502 - 8 condition code registers
1503 - 2 accumulator registers (hi and lo)
1504 - 32 registers each for coprocessors 0, 2 and 3
1505 - 4 fake registers:
1506 - ARG_POINTER_REGNUM
1507 - FRAME_POINTER_REGNUM
1508 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1509 - CPRESTORE_SLOT_REGNUM
1510 - 2 dummy entries that were used at various times in the past.
1511 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1512 - 6 DSP control registers */
1513
1514 #define FIRST_PSEUDO_REGISTER 188
1515
1516 /* By default, fix the kernel registers ($26 and $27), the global
1517 pointer ($28) and the stack pointer ($29). This can change
1518 depending on the command-line options.
1519
1520 Regarding coprocessor registers: without evidence to the contrary,
1521 it's best to assume that each coprocessor register has a unique
1522 use. This can be overridden, in, e.g., mips_option_override or
1523 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1524 for a particular target. */
1525
1526 #define FIXED_REGISTERS \
1527 { \
1528 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1529 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1530 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1531 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1532 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1533 /* COP0 registers */ \
1534 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1535 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1536 /* COP2 registers */ \
1537 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1538 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1539 /* COP3 registers */ \
1540 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1541 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1542 /* 6 DSP accumulator registers & 6 control registers */ \
1543 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1544 }
1545
1546
1547 /* Set up this array for o32 by default.
1548
1549 Note that we don't mark $31 as a call-clobbered register. The idea is
1550 that it's really the call instructions themselves which clobber $31.
1551 We don't care what the called function does with it afterwards.
1552
1553 This approach makes it easier to implement sibcalls. Unlike normal
1554 calls, sibcalls don't clobber $31, so the register reaches the
1555 called function in tact. EPILOGUE_USES says that $31 is useful
1556 to the called function. */
1557
1558 #define CALL_USED_REGISTERS \
1559 { \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1561 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1562 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1563 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1565 /* COP0 registers */ \
1566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1567 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1568 /* COP2 registers */ \
1569 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1570 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1571 /* COP3 registers */ \
1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1573 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1574 /* 6 DSP accumulator registers & 6 control registers */ \
1575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1576 }
1577
1578
1579 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1580
1581 #define CALL_REALLY_USED_REGISTERS \
1582 { /* General registers. */ \
1583 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1584 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1585 /* Floating-point registers. */ \
1586 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1587 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1588 /* Others. */ \
1589 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1590 /* COP0 registers */ \
1591 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1592 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1593 /* COP2 registers */ \
1594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1596 /* COP3 registers */ \
1597 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1598 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1599 /* 6 DSP accumulator registers & 6 control registers */ \
1600 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1601 }
1602
1603 /* Internal macros to classify a register number as to whether it's a
1604 general purpose register, a floating point register, a
1605 multiply/divide register, or a status register. */
1606
1607 #define GP_REG_FIRST 0
1608 #define GP_REG_LAST 31
1609 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1610 #define GP_DBX_FIRST 0
1611 #define K0_REG_NUM (GP_REG_FIRST + 26)
1612 #define K1_REG_NUM (GP_REG_FIRST + 27)
1613 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1614
1615 #define FP_REG_FIRST 32
1616 #define FP_REG_LAST 63
1617 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1618 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1619
1620 #define MD_REG_FIRST 64
1621 #define MD_REG_LAST 65
1622 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1623 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1624
1625 /* The DWARF 2 CFA column which tracks the return address from a
1626 signal handler context. This means that to maintain backwards
1627 compatibility, no hard register can be assigned this column if it
1628 would need to be handled by the DWARF unwinder. */
1629 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1630
1631 #define ST_REG_FIRST 67
1632 #define ST_REG_LAST 74
1633 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1634
1635
1636 /* FIXME: renumber. */
1637 #define COP0_REG_FIRST 80
1638 #define COP0_REG_LAST 111
1639 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1640
1641 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1642 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1643 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1644
1645 #define COP2_REG_FIRST 112
1646 #define COP2_REG_LAST 143
1647 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1648
1649 #define COP3_REG_FIRST 144
1650 #define COP3_REG_LAST 175
1651 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1652 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1653 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1654
1655 #define DSP_ACC_REG_FIRST 176
1656 #define DSP_ACC_REG_LAST 181
1657 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1658
1659 #define AT_REGNUM (GP_REG_FIRST + 1)
1660 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1661 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1662
1663 /* A few bitfield locations for the coprocessor registers. */
1664 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1665 the cause register for the EIC interrupt mode. */
1666 #define CAUSE_IPL 10
1667 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1668 #define SR_IPL 10
1669 /* Exception Level is at bit 1 of the status register. */
1670 #define SR_EXL 1
1671 /* Interrupt Enable is at bit 0 of the status register. */
1672 #define SR_IE 0
1673
1674 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1675 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1676 should be used instead. */
1677 #define FPSW_REGNUM ST_REG_FIRST
1678
1679 #define GP_REG_P(REGNO) \
1680 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1681 #define M16_REG_P(REGNO) \
1682 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1683 #define FP_REG_P(REGNO) \
1684 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1685 #define MD_REG_P(REGNO) \
1686 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1687 #define ST_REG_P(REGNO) \
1688 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1689 #define COP0_REG_P(REGNO) \
1690 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1691 #define COP2_REG_P(REGNO) \
1692 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1693 #define COP3_REG_P(REGNO) \
1694 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1695 #define ALL_COP_REG_P(REGNO) \
1696 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1697 /* Test if REGNO is one of the 6 new DSP accumulators. */
1698 #define DSP_ACC_REG_P(REGNO) \
1699 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1700 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1701 #define ACC_REG_P(REGNO) \
1702 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1703
1704 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1705
1706 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1707 to initialize the mips16 gp pseudo register. */
1708 #define CONST_GP_P(X) \
1709 (GET_CODE (X) == CONST \
1710 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1711 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1712
1713 /* Return coprocessor number from register number. */
1714
1715 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1716 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1717 : COP3_REG_P (REGNO) ? '3' : '?')
1718
1719
1720 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1721
1722 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1723 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1724
1725 #define MODES_TIEABLE_P mips_modes_tieable_p
1726
1727 /* Register to use for pushing function arguments. */
1728 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1729
1730 /* These two registers don't really exist: they get eliminated to either
1731 the stack or hard frame pointer. */
1732 #define ARG_POINTER_REGNUM 77
1733 #define FRAME_POINTER_REGNUM 78
1734
1735 /* $30 is not available on the mips16, so we use $17 as the frame
1736 pointer. */
1737 #define HARD_FRAME_POINTER_REGNUM \
1738 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1739
1740 /* Register in which static-chain is passed to a function. */
1741 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1742
1743 /* Registers used as temporaries in prologue/epilogue code:
1744
1745 - If a MIPS16 PIC function needs access to _gp, it first loads
1746 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1747
1748 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1749 register. The register must not conflict with MIPS16_PIC_TEMP.
1750
1751 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1752 register.
1753
1754 If we're generating MIPS16 code, these registers must come from the
1755 core set of 8. The prologue registers mustn't conflict with any
1756 incoming arguments, the static chain pointer, or the frame pointer.
1757 The epilogue temporary mustn't conflict with the return registers,
1758 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1759 or the EH data registers.
1760
1761 If we're generating interrupt handlers, we use K0 as a temporary register
1762 in prologue/epilogue code. */
1763
1764 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1765 #define MIPS_PROLOGUE_TEMP_REGNUM \
1766 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1767 #define MIPS_EPILOGUE_TEMP_REGNUM \
1768 (cfun->machine->interrupt_handler_p \
1769 ? K0_REG_NUM \
1770 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1771
1772 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1773 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1774 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1775
1776 /* Define this macro if it is as good or better to call a constant
1777 function address than to call an address kept in a register. */
1778 #define NO_FUNCTION_CSE 1
1779
1780 /* The ABI-defined global pointer. Sometimes we use a different
1781 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1782 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1783
1784 /* We normally use $28 as the global pointer. However, when generating
1785 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1786 register instead. They can then avoid saving and restoring $28
1787 and perhaps avoid using a frame at all.
1788
1789 When a leaf function uses something other than $28, mips_expand_prologue
1790 will modify pic_offset_table_rtx in place. Take the register number
1791 from there after reload. */
1792 #define PIC_OFFSET_TABLE_REGNUM \
1793 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1794
1795 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1796 \f
1797 /* Define the classes of registers for register constraints in the
1798 machine description. Also define ranges of constants.
1799
1800 One of the classes must always be named ALL_REGS and include all hard regs.
1801 If there is more than one class, another class must be named NO_REGS
1802 and contain no registers.
1803
1804 The name GENERAL_REGS must be the name of a class (or an alias for
1805 another name such as ALL_REGS). This is the class of registers
1806 that is allowed by "g" or "r" in a register constraint.
1807 Also, registers outside this class are allocated only when
1808 instructions express preferences for them.
1809
1810 The classes must be numbered in nondecreasing order; that is,
1811 a larger-numbered class must never be contained completely
1812 in a smaller-numbered class.
1813
1814 For any two classes, it is very desirable that there be another
1815 class that represents their union. */
1816
1817 enum reg_class
1818 {
1819 NO_REGS, /* no registers in set */
1820 M16_REGS, /* mips16 directly accessible registers */
1821 T_REG, /* mips16 T register ($24) */
1822 M16_T_REGS, /* mips16 registers plus T register */
1823 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1824 V1_REG, /* Register $v1 ($3) used for TLS access. */
1825 LEA_REGS, /* Every GPR except $25 */
1826 GR_REGS, /* integer registers */
1827 FP_REGS, /* floating point registers */
1828 MD0_REG, /* first multiply/divide register */
1829 MD1_REG, /* second multiply/divide register */
1830 MD_REGS, /* multiply/divide registers (hi/lo) */
1831 COP0_REGS, /* generic coprocessor classes */
1832 COP2_REGS,
1833 COP3_REGS,
1834 ST_REGS, /* status registers (fp status) */
1835 DSP_ACC_REGS, /* DSP accumulator registers */
1836 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1837 FRAME_REGS, /* $arg and $frame */
1838 GR_AND_MD0_REGS, /* union classes */
1839 GR_AND_MD1_REGS,
1840 GR_AND_MD_REGS,
1841 GR_AND_ACC_REGS,
1842 ALL_REGS, /* all registers */
1843 LIM_REG_CLASSES /* max value + 1 */
1844 };
1845
1846 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1847
1848 #define GENERAL_REGS GR_REGS
1849
1850 /* An initializer containing the names of the register classes as C
1851 string constants. These names are used in writing some of the
1852 debugging dumps. */
1853
1854 #define REG_CLASS_NAMES \
1855 { \
1856 "NO_REGS", \
1857 "M16_REGS", \
1858 "T_REG", \
1859 "M16_T_REGS", \
1860 "PIC_FN_ADDR_REG", \
1861 "V1_REG", \
1862 "LEA_REGS", \
1863 "GR_REGS", \
1864 "FP_REGS", \
1865 "MD0_REG", \
1866 "MD1_REG", \
1867 "MD_REGS", \
1868 /* coprocessor registers */ \
1869 "COP0_REGS", \
1870 "COP2_REGS", \
1871 "COP3_REGS", \
1872 "ST_REGS", \
1873 "DSP_ACC_REGS", \
1874 "ACC_REGS", \
1875 "FRAME_REGS", \
1876 "GR_AND_MD0_REGS", \
1877 "GR_AND_MD1_REGS", \
1878 "GR_AND_MD_REGS", \
1879 "GR_AND_ACC_REGS", \
1880 "ALL_REGS" \
1881 }
1882
1883 /* An initializer containing the contents of the register classes,
1884 as integers which are bit masks. The Nth integer specifies the
1885 contents of class N. The way the integer MASK is interpreted is
1886 that register R is in the class if `MASK & (1 << R)' is 1.
1887
1888 When the machine has more than 32 registers, an integer does not
1889 suffice. Then the integers are replaced by sub-initializers,
1890 braced groupings containing several integers. Each
1891 sub-initializer must be suitable as an initializer for the type
1892 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1893
1894 #define REG_CLASS_CONTENTS \
1895 { \
1896 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1897 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1898 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1899 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1900 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1901 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1902 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1903 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1904 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1905 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1906 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1907 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1908 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1909 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1910 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1911 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1912 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1913 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1914 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1915 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1916 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1917 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1918 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1919 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1920 }
1921
1922
1923 /* A C expression whose value is a register class containing hard
1924 register REGNO. In general there is more that one such class;
1925 choose a class which is "minimal", meaning that no smaller class
1926 also contains the register. */
1927
1928 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1929
1930 /* A macro whose definition is the name of the class to which a
1931 valid base register must belong. A base register is one used in
1932 an address which is the register value plus a displacement. */
1933
1934 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1935
1936 /* A macro whose definition is the name of the class to which a
1937 valid index register must belong. An index register is one used
1938 in an address where its value is either multiplied by a scale
1939 factor or added to another register (as well as added to a
1940 displacement). */
1941
1942 #define INDEX_REG_CLASS NO_REGS
1943
1944 /* We generally want to put call-clobbered registers ahead of
1945 call-saved ones. (IRA expects this.) */
1946
1947 #define REG_ALLOC_ORDER \
1948 { /* Accumulator registers. When GPRs and accumulators have equal \
1949 cost, we generally prefer to use accumulators. For example, \
1950 a division of multiplication result is better allocated to LO, \
1951 so that we put the MFLO at the point of use instead of at the \
1952 point of definition. It's also needed if we're to take advantage \
1953 of the extra accumulators available with -mdspr2. In some cases, \
1954 it can also help to reduce register pressure. */ \
1955 64, 65,176,177,178,179,180,181, \
1956 /* Call-clobbered GPRs. */ \
1957 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1958 24, 25, 31, \
1959 /* The global pointer. This is call-clobbered for o32 and o64 \
1960 abicalls, call-saved for n32 and n64 abicalls, and a program \
1961 invariant otherwise. Putting it between the call-clobbered \
1962 and call-saved registers should cope with all eventualities. */ \
1963 28, \
1964 /* Call-saved GPRs. */ \
1965 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1966 /* GPRs that can never be exposed to the register allocator. */ \
1967 0, 26, 27, 29, \
1968 /* Call-clobbered FPRs. */ \
1969 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1970 48, 49, 50, 51, \
1971 /* FPRs that are usually call-saved. The odd ones are actually \
1972 call-clobbered for n32, but listing them ahead of the even \
1973 registers might encourage the register allocator to fragment \
1974 the available FPR pairs. We need paired FPRs to store long \
1975 doubles, so it isn't clear that using a different order \
1976 for n32 would be a win. */ \
1977 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1978 /* None of the remaining classes have defined call-saved \
1979 registers. */ \
1980 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1981 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1982 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1983 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1984 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1985 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1986 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1987 182,183,184,185,186,187 \
1988 }
1989
1990 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1991 to be rearranged based on a particular function. On the mips16, we
1992 want to allocate $24 (T_REG) before other registers for
1993 instructions for which it is possible. */
1994
1995 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
1996
1997 /* True if VALUE is an unsigned 6-bit number. */
1998
1999 #define UIMM6_OPERAND(VALUE) \
2000 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2001
2002 /* True if VALUE is a signed 10-bit number. */
2003
2004 #define IMM10_OPERAND(VALUE) \
2005 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2006
2007 /* True if VALUE is a signed 16-bit number. */
2008
2009 #define SMALL_OPERAND(VALUE) \
2010 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2011
2012 /* True if VALUE is an unsigned 16-bit number. */
2013
2014 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2015 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2016
2017 /* True if VALUE can be loaded into a register using LUI. */
2018
2019 #define LUI_OPERAND(VALUE) \
2020 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2021 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2022
2023 /* Return a value X with the low 16 bits clear, and such that
2024 VALUE - X is a signed 16-bit value. */
2025
2026 #define CONST_HIGH_PART(VALUE) \
2027 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2028
2029 #define CONST_LOW_PART(VALUE) \
2030 ((VALUE) - CONST_HIGH_PART (VALUE))
2031
2032 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2033 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2034 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2035
2036 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2037 mips_preferred_reload_class (X, CLASS)
2038
2039 /* The HI and LO registers can only be reloaded via the general
2040 registers. Condition code registers can only be loaded to the
2041 general registers, and from the floating point registers. */
2042
2043 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2044 mips_secondary_reload_class (CLASS, MODE, X, true)
2045 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2046 mips_secondary_reload_class (CLASS, MODE, X, false)
2047
2048 /* Return the maximum number of consecutive registers
2049 needed to represent mode MODE in a register of class CLASS. */
2050
2051 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2052
2053 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2054 mips_cannot_change_mode_class (FROM, TO, CLASS)
2055 \f
2056 /* Stack layout; function entry, exit and calling. */
2057
2058 #define STACK_GROWS_DOWNWARD
2059
2060 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2061
2062 /* Size of the area allocated in the frame to save the GP. */
2063
2064 #define MIPS_GP_SAVE_AREA_SIZE \
2065 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2066
2067 /* The offset of the first local variable from the frame pointer. See
2068 mips_compute_frame_info for details about the frame layout. */
2069
2070 #define STARTING_FRAME_OFFSET \
2071 (FRAME_GROWS_DOWNWARD \
2072 ? 0 \
2073 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2074
2075 #define RETURN_ADDR_RTX mips_return_addr
2076
2077 /* Mask off the MIPS16 ISA bit in unwind addresses.
2078
2079 The reason for this is a little subtle. When unwinding a call,
2080 we are given the call's return address, which on most targets
2081 is the address of the following instruction. However, what we
2082 actually want to find is the EH region for the call itself.
2083 The target-independent unwind code therefore searches for "RA - 1".
2084
2085 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2086 RA - 1 is therefore the real (even-valued) start of the return
2087 instruction. EH region labels are usually odd-valued MIPS16 symbols
2088 too, so a search for an even address within a MIPS16 region would
2089 usually work.
2090
2091 However, there is an exception. If the end of an EH region is also
2092 the end of a function, the end label is allowed to be even. This is
2093 necessary because a following non-MIPS16 function may also need EH
2094 information for its first instruction.
2095
2096 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2097 non-ISA-encoded address. This probably isn't ideal, but it is
2098 the traditional (legacy) behavior. It is therefore only safe
2099 to search MIPS EH regions for an _odd-valued_ address.
2100
2101 Masking off the ISA bit means that the target-independent code
2102 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2103 #define MASK_RETURN_ADDR GEN_INT (-2)
2104
2105
2106 /* Similarly, don't use the least-significant bit to tell pointers to
2107 code from vtable index. */
2108
2109 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2110
2111 /* The eliminations to $17 are only used for mips16 code. See the
2112 definition of HARD_FRAME_POINTER_REGNUM. */
2113
2114 #define ELIMINABLE_REGS \
2115 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2116 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2117 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2118 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2119 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2120 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2121
2122 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2123 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2124
2125 /* Allocate stack space for arguments at the beginning of each function. */
2126 #define ACCUMULATE_OUTGOING_ARGS 1
2127
2128 /* The argument pointer always points to the first argument. */
2129 #define FIRST_PARM_OFFSET(FNDECL) 0
2130
2131 /* o32 and o64 reserve stack space for all argument registers. */
2132 #define REG_PARM_STACK_SPACE(FNDECL) \
2133 (TARGET_OLDABI \
2134 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2135 : 0)
2136
2137 /* Define this if it is the responsibility of the caller to
2138 allocate the area reserved for arguments passed in registers.
2139 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2140 of this macro is to determine whether the space is included in
2141 `crtl->outgoing_args_size'. */
2142 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2143
2144 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2145 \f
2146 /* Symbolic macros for the registers used to return integer and floating
2147 point values. */
2148
2149 #define GP_RETURN (GP_REG_FIRST + 2)
2150 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2151
2152 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2153
2154 /* Symbolic macros for the first/last argument registers. */
2155
2156 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2157 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2158 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2159 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2160
2161 #define LIBCALL_VALUE(MODE) \
2162 mips_function_value (NULL_TREE, NULL_TREE, MODE)
2163
2164 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2165 mips_function_value (VALTYPE, FUNC, VOIDmode)
2166
2167 /* 1 if N is a possible register number for a function value.
2168 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2169 Currently, R2 and F0 are only implemented here (C has no complex type) */
2170
2171 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2172 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2173 && (N) == FP_RETURN + 2))
2174
2175 /* 1 if N is a possible register number for function argument passing.
2176 We have no FP argument registers when soft-float. When FP registers
2177 are 32 bits, we can't directly reference the odd numbered ones. */
2178
2179 #define FUNCTION_ARG_REGNO_P(N) \
2180 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2181 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2182 && !fixed_regs[N])
2183 \f
2184 /* This structure has to cope with two different argument allocation
2185 schemes. Most MIPS ABIs view the arguments as a structure, of which
2186 the first N words go in registers and the rest go on the stack. If I
2187 < N, the Ith word might go in Ith integer argument register or in a
2188 floating-point register. For these ABIs, we only need to remember
2189 the offset of the current argument into the structure.
2190
2191 The EABI instead allocates the integer and floating-point arguments
2192 separately. The first N words of FP arguments go in FP registers,
2193 the rest go on the stack. Likewise, the first N words of the other
2194 arguments go in integer registers, and the rest go on the stack. We
2195 need to maintain three counts: the number of integer registers used,
2196 the number of floating-point registers used, and the number of words
2197 passed on the stack.
2198
2199 We could keep separate information for the two ABIs (a word count for
2200 the standard ABIs, and three separate counts for the EABI). But it
2201 seems simpler to view the standard ABIs as forms of EABI that do not
2202 allocate floating-point registers.
2203
2204 So for the standard ABIs, the first N words are allocated to integer
2205 registers, and mips_function_arg decides on an argument-by-argument
2206 basis whether that argument should really go in an integer register,
2207 or in a floating-point one. */
2208
2209 typedef struct mips_args {
2210 /* Always true for varargs functions. Otherwise true if at least
2211 one argument has been passed in an integer register. */
2212 int gp_reg_found;
2213
2214 /* The number of arguments seen so far. */
2215 unsigned int arg_number;
2216
2217 /* The number of integer registers used so far. For all ABIs except
2218 EABI, this is the number of words that have been added to the
2219 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2220 unsigned int num_gprs;
2221
2222 /* For EABI, the number of floating-point registers used so far. */
2223 unsigned int num_fprs;
2224
2225 /* The number of words passed on the stack. */
2226 unsigned int stack_words;
2227
2228 /* On the mips16, we need to keep track of which floating point
2229 arguments were passed in general registers, but would have been
2230 passed in the FP regs if this were a 32-bit function, so that we
2231 can move them to the FP regs if we wind up calling a 32-bit
2232 function. We record this information in fp_code, encoded in base
2233 four. A zero digit means no floating point argument, a one digit
2234 means an SFmode argument, and a two digit means a DFmode argument,
2235 and a three digit is not used. The low order digit is the first
2236 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2237 an SFmode argument. ??? A more sophisticated approach will be
2238 needed if MIPS_ABI != ABI_32. */
2239 int fp_code;
2240
2241 /* True if the function has a prototype. */
2242 int prototype;
2243 } CUMULATIVE_ARGS;
2244
2245 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2246 for a call to a function whose data type is FNTYPE.
2247 For a library call, FNTYPE is 0. */
2248
2249 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2250 mips_init_cumulative_args (&CUM, FNTYPE)
2251
2252 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2253
2254 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2255 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2256
2257 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2258 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2259
2260 /* True if using EABI and varargs can be passed in floating-point
2261 registers. Under these conditions, we need a more complex form
2262 of va_list, which tracks GPR, FPR and stack arguments separately. */
2263 #define EABI_FLOAT_VARARGS_P \
2264 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2265
2266 \f
2267 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2268
2269 /* Treat LOC as a byte offset from the stack pointer and round it up
2270 to the next fully-aligned offset. */
2271 #define MIPS_STACK_ALIGN(LOC) \
2272 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2273
2274 \f
2275 /* Output assembler code to FILE to increment profiler label # LABELNO
2276 for profiling a function entry. */
2277
2278 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2279
2280 /* The profiler preserves all interesting registers, including $31. */
2281 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2282
2283 /* No mips port has ever used the profiler counter word, so don't emit it
2284 or the label for it. */
2285
2286 #define NO_PROFILE_COUNTERS 1
2287
2288 /* Define this macro if the code for function profiling should come
2289 before the function prologue. Normally, the profiling code comes
2290 after. */
2291
2292 /* #define PROFILE_BEFORE_PROLOGUE */
2293
2294 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2295 the stack pointer does not matter. The value is tested only in
2296 functions that have frame pointers.
2297 No definition is equivalent to always zero. */
2298
2299 #define EXIT_IGNORE_STACK 1
2300
2301 \f
2302 /* Trampolines are a block of code followed by two pointers. */
2303
2304 #define TRAMPOLINE_SIZE \
2305 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2306
2307 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2308 pointers from a single LUI base. */
2309
2310 #define TRAMPOLINE_ALIGNMENT 64
2311
2312 /* mips_trampoline_init calls this library function to flush
2313 program and data caches. */
2314
2315 #ifndef CACHE_FLUSH_FUNC
2316 #define CACHE_FLUSH_FUNC "_flush_cache"
2317 #endif
2318
2319 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2320 /* Flush both caches. We need to flush the data cache in case \
2321 the system has a write-back cache. */ \
2322 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2323 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2324 GEN_INT (3), TYPE_MODE (integer_type_node))
2325
2326 \f
2327 /* Addressing modes, and classification of registers for them. */
2328
2329 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2330 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2331 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2332
2333 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2334 and check its validity for a certain class.
2335 We have two alternate definitions for each of them.
2336 The usual definition accepts all pseudo regs; the other rejects them all.
2337 The symbol REG_OK_STRICT causes the latter definition to be used.
2338
2339 Most source files want to accept pseudo regs in the hope that
2340 they will get allocated to the class that the insn wants them to be in.
2341 Some source files that are used after register allocation
2342 need to be strict. */
2343
2344 #ifndef REG_OK_STRICT
2345 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2346 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2347 #else
2348 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2349 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2350 #endif
2351
2352 #define REG_OK_FOR_INDEX_P(X) 0
2353
2354 \f
2355 /* Maximum number of registers that can appear in a valid memory address. */
2356
2357 #define MAX_REGS_PER_ADDRESS 1
2358
2359 /* Check for constness inline but use mips_legitimate_address_p
2360 to check whether a constant really is an address. */
2361
2362 #define CONSTANT_ADDRESS_P(X) \
2363 (CONSTANT_P (X) && memory_address_p (SImode, X))
2364
2365 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2366
2367 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2368 'the start of the function that this code is output in'. */
2369
2370 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2371 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2372 asm_fprintf ((FILE), "%U%s", \
2373 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2374 else \
2375 asm_fprintf ((FILE), "%U%s", (NAME))
2376 \f
2377 /* Flag to mark a function decl symbol that requires a long call. */
2378 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2379 #define SYMBOL_REF_LONG_CALL_P(X) \
2380 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2381
2382 /* This flag marks functions that cannot be lazily bound. */
2383 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2384 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2385 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2386
2387 /* True if we're generating a form of MIPS16 code in which jump tables
2388 are stored in the text section and encoded as 16-bit PC-relative
2389 offsets. This is only possible when general text loads are allowed,
2390 since the table access itself will be an "lh" instruction. */
2391 /* ??? 16-bit offsets can overflow in large functions. */
2392 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2393
2394 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2395
2396 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2397
2398 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2399
2400 /* Define this as 1 if `char' should by default be signed; else as 0. */
2401 #ifndef DEFAULT_SIGNED_CHAR
2402 #define DEFAULT_SIGNED_CHAR 1
2403 #endif
2404
2405 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2406 we generally don't want to use them for copying arbitrary data.
2407 A single N-word move is usually the same cost as N single-word moves. */
2408 #define MOVE_MAX UNITS_PER_WORD
2409 #define MAX_MOVE_MAX 8
2410
2411 /* Define this macro as a C expression which is nonzero if
2412 accessing less than a word of memory (i.e. a `char' or a
2413 `short') is no faster than accessing a word of memory, i.e., if
2414 such access require more than one instruction or if there is no
2415 difference in cost between byte and (aligned) word loads.
2416
2417 On RISC machines, it tends to generate better code to define
2418 this as 1, since it avoids making a QI or HI mode register.
2419
2420 But, generating word accesses for -mips16 is generally bad as shifts
2421 (often extended) would be needed for byte accesses. */
2422 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2423
2424 /* Define this to be nonzero if shift instructions ignore all but the low-order
2425 few bits. */
2426 #define SHIFT_COUNT_TRUNCATED 1
2427
2428 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2429 is done just by pretending it is already truncated. */
2430 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2431 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2432
2433
2434 /* Specify the machine mode that pointers have.
2435 After generation of rtl, the compiler makes no further distinction
2436 between pointers and any other objects of this machine mode. */
2437
2438 #ifndef Pmode
2439 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2440 #endif
2441
2442 /* Give call MEMs SImode since it is the "most permissive" mode
2443 for both 32-bit and 64-bit targets. */
2444
2445 #define FUNCTION_MODE SImode
2446
2447 \f
2448
2449 /* Define if copies to/from condition code registers should be avoided.
2450
2451 This is needed for the MIPS because reload_outcc is not complete;
2452 it needs to handle cases where the source is a general or another
2453 condition code register. */
2454 #define AVOID_CCMODE_COPIES
2455
2456 /* A C expression for the cost of a branch instruction. A value of
2457 1 is the default; other values are interpreted relative to that. */
2458
2459 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2460 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2461
2462 /* If defined, modifies the length assigned to instruction INSN as a
2463 function of the context in which it is used. LENGTH is an lvalue
2464 that contains the initially computed length of the insn and should
2465 be updated with the correct length of the insn. */
2466 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2467 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2468
2469 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2470 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2471 its operands. */
2472 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2473 "%*" OPCODE "%?\t" OPERANDS "%/"
2474
2475 /* Return an asm string that forces INSN to be treated as an absolute
2476 J or JAL instruction instead of an assembler macro. */
2477 #define MIPS_ABSOLUTE_JUMP(INSN) \
2478 (TARGET_ABICALLS_PIC2 \
2479 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2480 : INSN)
2481
2482 /* Return the asm template for a call. INSN is the instruction's mnemonic
2483 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2484 number of the target. SIZE_OPNO is the operand number of the argument size
2485 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2486 -1 and the call is indirect, use the function symbol from the call
2487 attributes to attach a R_MIPS_JALR relocation to the call.
2488
2489 When generating GOT code without explicit relocation operators,
2490 all calls should use assembly macros. Otherwise, all indirect
2491 calls should use "jr" or "jalr"; we will arrange to restore $gp
2492 afterwards if necessary. Finally, we can only generate direct
2493 calls for -mabicalls by temporarily switching to non-PIC mode. */
2494 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2495 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2496 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2497 : (REG_P (OPERANDS[TARGET_OPNO]) \
2498 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2499 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2500 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2501 : REG_P (OPERANDS[TARGET_OPNO]) \
2502 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2503 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2504 \f
2505 /* Control the assembler format that we output. */
2506
2507 /* Output to assembler file text saying following lines
2508 may contain character constants, extra white space, comments, etc. */
2509
2510 #ifndef ASM_APP_ON
2511 #define ASM_APP_ON " #APP\n"
2512 #endif
2513
2514 /* Output to assembler file text saying following lines
2515 no longer contain unusual constructs. */
2516
2517 #ifndef ASM_APP_OFF
2518 #define ASM_APP_OFF " #NO_APP\n"
2519 #endif
2520
2521 #define REGISTER_NAMES \
2522 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2523 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2524 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2525 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2526 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2527 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2528 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2529 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2530 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2531 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2532 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2533 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2534 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2535 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2536 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2537 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2538 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2539 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2540 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2541 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2542 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2543 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2544 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2545 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2546
2547 /* List the "software" names for each register. Also list the numerical
2548 names for $fp and $sp. */
2549
2550 #define ADDITIONAL_REGISTER_NAMES \
2551 { \
2552 { "$29", 29 + GP_REG_FIRST }, \
2553 { "$30", 30 + GP_REG_FIRST }, \
2554 { "at", 1 + GP_REG_FIRST }, \
2555 { "v0", 2 + GP_REG_FIRST }, \
2556 { "v1", 3 + GP_REG_FIRST }, \
2557 { "a0", 4 + GP_REG_FIRST }, \
2558 { "a1", 5 + GP_REG_FIRST }, \
2559 { "a2", 6 + GP_REG_FIRST }, \
2560 { "a3", 7 + GP_REG_FIRST }, \
2561 { "t0", 8 + GP_REG_FIRST }, \
2562 { "t1", 9 + GP_REG_FIRST }, \
2563 { "t2", 10 + GP_REG_FIRST }, \
2564 { "t3", 11 + GP_REG_FIRST }, \
2565 { "t4", 12 + GP_REG_FIRST }, \
2566 { "t5", 13 + GP_REG_FIRST }, \
2567 { "t6", 14 + GP_REG_FIRST }, \
2568 { "t7", 15 + GP_REG_FIRST }, \
2569 { "s0", 16 + GP_REG_FIRST }, \
2570 { "s1", 17 + GP_REG_FIRST }, \
2571 { "s2", 18 + GP_REG_FIRST }, \
2572 { "s3", 19 + GP_REG_FIRST }, \
2573 { "s4", 20 + GP_REG_FIRST }, \
2574 { "s5", 21 + GP_REG_FIRST }, \
2575 { "s6", 22 + GP_REG_FIRST }, \
2576 { "s7", 23 + GP_REG_FIRST }, \
2577 { "t8", 24 + GP_REG_FIRST }, \
2578 { "t9", 25 + GP_REG_FIRST }, \
2579 { "k0", 26 + GP_REG_FIRST }, \
2580 { "k1", 27 + GP_REG_FIRST }, \
2581 { "gp", 28 + GP_REG_FIRST }, \
2582 { "sp", 29 + GP_REG_FIRST }, \
2583 { "fp", 30 + GP_REG_FIRST }, \
2584 { "ra", 31 + GP_REG_FIRST }, \
2585 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2586 }
2587
2588 /* This is meant to be redefined in the host dependent files. It is a
2589 set of alternative names and regnums for mips coprocessors. */
2590
2591 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2592
2593 #define DBR_OUTPUT_SEQEND(STREAM) \
2594 do \
2595 { \
2596 /* Undo the effect of '%*'. */ \
2597 mips_pop_asm_switch (&mips_nomacro); \
2598 mips_pop_asm_switch (&mips_noreorder); \
2599 /* Emit a blank line after the delay slot for emphasis. */ \
2600 fputs ("\n", STREAM); \
2601 } \
2602 while (0)
2603
2604 /* mips-tfile does not understand .stabd directives. */
2605 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2606 dbxout_begin_stabn_sline (LINE); \
2607 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2608 } while (0)
2609
2610 /* Use .loc directives for SDB line numbers. */
2611 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2612 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2613
2614 /* The MIPS implementation uses some labels for its own purpose. The
2615 following lists what labels are created, and are all formed by the
2616 pattern $L[a-z].*. The machine independent portion of GCC creates
2617 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2618
2619 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2620 $Lb[0-9]+ Begin blocks for MIPS debug support
2621 $Lc[0-9]+ Label for use in s<xx> operation.
2622 $Le[0-9]+ End blocks for MIPS debug support */
2623
2624 #undef ASM_DECLARE_OBJECT_NAME
2625 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2626 mips_declare_object (STREAM, NAME, "", ":\n")
2627
2628 /* Globalizing directive for a label. */
2629 #define GLOBAL_ASM_OP "\t.globl\t"
2630
2631 /* This says how to define a global common symbol. */
2632
2633 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2634
2635 /* This says how to define a local common symbol (i.e., not visible to
2636 linker). */
2637
2638 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2639 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2640 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2641 #endif
2642
2643 /* This says how to output an external. It would be possible not to
2644 output anything and let undefined symbol become external. However
2645 the assembler uses length information on externals to allocate in
2646 data/sdata bss/sbss, thereby saving exec time. */
2647
2648 #undef ASM_OUTPUT_EXTERNAL
2649 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2650 mips_output_external(STREAM,DECL,NAME)
2651
2652 /* This is how to declare a function name. The actual work of
2653 emitting the label is moved to function_prologue, so that we can
2654 get the line number correctly emitted before the .ent directive,
2655 and after any .file directives. Define as empty so that the function
2656 is not declared before the .ent directive elsewhere. */
2657
2658 #undef ASM_DECLARE_FUNCTION_NAME
2659 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2660
2661 /* This is how to store into the string LABEL
2662 the symbol_ref name of an internal numbered label where
2663 PREFIX is the class of label and NUM is the number within the class.
2664 This is suitable for output with `assemble_name'. */
2665
2666 #undef ASM_GENERATE_INTERNAL_LABEL
2667 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2668 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2669
2670 /* Print debug labels as "foo = ." rather than "foo:" because they should
2671 represent a byte pointer rather than an ISA-encoded address. This is
2672 particularly important for code like:
2673
2674 $LFBxxx = .
2675 .cfi_startproc
2676 ...
2677 .section .gcc_except_table,...
2678 ...
2679 .uleb128 foo-$LFBxxx
2680
2681 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2682 likewise a byte pointer rather than an ISA-encoded address.
2683
2684 At the time of writing, this hook is not used for the function end
2685 label:
2686
2687 $LFExxx:
2688 .end foo
2689
2690 But this doesn't matter, because GAS doesn't treat a pre-.end label
2691 as a MIPS16 one anyway. */
2692
2693 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2694 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2695
2696 /* This is how to output an element of a case-vector that is absolute. */
2697
2698 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2699 fprintf (STREAM, "\t%s\t%sL%d\n", \
2700 ptr_mode == DImode ? ".dword" : ".word", \
2701 LOCAL_LABEL_PREFIX, \
2702 VALUE)
2703
2704 /* This is how to output an element of a case-vector. We can make the
2705 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2706 is supported. */
2707
2708 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2709 do { \
2710 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2711 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2712 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2713 else if (TARGET_GPWORD) \
2714 fprintf (STREAM, "\t%s\t%sL%d\n", \
2715 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2716 LOCAL_LABEL_PREFIX, VALUE); \
2717 else if (TARGET_RTP_PIC) \
2718 { \
2719 /* Make the entry relative to the start of the function. */ \
2720 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2721 fprintf (STREAM, "\t%s\t%sL%d-", \
2722 Pmode == DImode ? ".dword" : ".word", \
2723 LOCAL_LABEL_PREFIX, VALUE); \
2724 assemble_name (STREAM, XSTR (fnsym, 0)); \
2725 fprintf (STREAM, "\n"); \
2726 } \
2727 else \
2728 fprintf (STREAM, "\t%s\t%sL%d\n", \
2729 ptr_mode == DImode ? ".dword" : ".word", \
2730 LOCAL_LABEL_PREFIX, VALUE); \
2731 } while (0)
2732
2733 /* This is how to output an assembler line
2734 that says to advance the location counter
2735 to a multiple of 2**LOG bytes. */
2736
2737 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2738 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2739
2740 /* This is how to output an assembler line to advance the location
2741 counter by SIZE bytes. */
2742
2743 #undef ASM_OUTPUT_SKIP
2744 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2745 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2746
2747 /* This is how to output a string. */
2748 #undef ASM_OUTPUT_ASCII
2749 #define ASM_OUTPUT_ASCII mips_output_ascii
2750
2751 /* Output #ident as a in the read-only data section. */
2752 #undef ASM_OUTPUT_IDENT
2753 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2754 { \
2755 const char *p = STRING; \
2756 int size = strlen (p) + 1; \
2757 switch_to_section (readonly_data_section); \
2758 assemble_string (p, size); \
2759 }
2760 \f
2761 /* Default to -G 8 */
2762 #ifndef MIPS_DEFAULT_GVALUE
2763 #define MIPS_DEFAULT_GVALUE 8
2764 #endif
2765
2766 /* Define the strings to put out for each section in the object file. */
2767 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2768 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2769
2770 #undef READONLY_DATA_SECTION_ASM_OP
2771 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2772 \f
2773 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2774 do \
2775 { \
2776 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2777 TARGET_64BIT ? "daddiu" : "addiu", \
2778 reg_names[STACK_POINTER_REGNUM], \
2779 reg_names[STACK_POINTER_REGNUM], \
2780 TARGET_64BIT ? "sd" : "sw", \
2781 reg_names[REGNO], \
2782 reg_names[STACK_POINTER_REGNUM]); \
2783 } \
2784 while (0)
2785
2786 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2787 do \
2788 { \
2789 mips_push_asm_switch (&mips_noreorder); \
2790 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2791 TARGET_64BIT ? "ld" : "lw", \
2792 reg_names[REGNO], \
2793 reg_names[STACK_POINTER_REGNUM], \
2794 TARGET_64BIT ? "daddu" : "addu", \
2795 reg_names[STACK_POINTER_REGNUM], \
2796 reg_names[STACK_POINTER_REGNUM]); \
2797 mips_pop_asm_switch (&mips_noreorder); \
2798 } \
2799 while (0)
2800
2801 /* How to start an assembler comment.
2802 The leading space is important (the mips native assembler requires it). */
2803 #ifndef ASM_COMMENT_START
2804 #define ASM_COMMENT_START " #"
2805 #endif
2806 \f
2807 /* Default definitions for size_t and ptrdiff_t. We must override the
2808 definitions from ../svr4.h on mips-*-linux-gnu. */
2809
2810 #undef SIZE_TYPE
2811 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2812
2813 #undef PTRDIFF_TYPE
2814 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2815
2816 /* The maximum number of bytes that can be copied by one iteration of
2817 a movmemsi loop; see mips_block_move_loop. */
2818 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2819 (UNITS_PER_WORD * 4)
2820
2821 /* The maximum number of bytes that can be copied by a straight-line
2822 implementation of movmemsi; see mips_block_move_straight. We want
2823 to make sure that any loop-based implementation will iterate at
2824 least twice. */
2825 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2826 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2827
2828 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2829 values were determined experimentally by benchmarking with CSiBE.
2830 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2831 for o32 where we have to restore $gp afterwards as well as make an
2832 indirect call), but in practice, bumping this up higher for
2833 TARGET_ABICALLS doesn't make much difference to code size. */
2834
2835 #define MIPS_CALL_RATIO 8
2836
2837 /* Any loop-based implementation of movmemsi will have at least
2838 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2839 moves, so allow individual copies of fewer elements.
2840
2841 When movmemsi is not available, use a value approximating
2842 the length of a memcpy call sequence, so that move_by_pieces
2843 will generate inline code if it is shorter than a function call.
2844 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2845 we'll have to generate a load/store pair for each, halve the
2846 value of MIPS_CALL_RATIO to take that into account. */
2847
2848 #define MOVE_RATIO(speed) \
2849 (HAVE_movmemsi \
2850 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2851 : MIPS_CALL_RATIO / 2)
2852
2853 /* movmemsi is meant to generate code that is at least as good as
2854 move_by_pieces. However, movmemsi effectively uses a by-pieces
2855 implementation both for moves smaller than a word and for word-aligned
2856 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
2857 allow the tree-level optimisers to do such moves by pieces, as it
2858 often exposes other optimization opportunities. We might as well
2859 continue to use movmemsi at the rtl level though, as it produces
2860 better code when scheduling is disabled (such as at -O). */
2861
2862 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2863 (HAVE_movmemsi \
2864 ? (!currently_expanding_to_rtl \
2865 && ((ALIGN) < BITS_PER_WORD \
2866 ? (SIZE) < UNITS_PER_WORD \
2867 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
2868 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2869 < (unsigned int) MOVE_RATIO (false)))
2870
2871 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2872 of the length of a memset call, but use the default otherwise. */
2873
2874 #define CLEAR_RATIO(speed)\
2875 ((speed) ? 15 : MIPS_CALL_RATIO)
2876
2877 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2878 optimizing for size adjust the ratio to account for the overhead of
2879 loading the constant and replicating it across the word. */
2880
2881 #define SET_RATIO(speed) \
2882 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2883
2884 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2885 in that case each word takes 3 insns (lui, ori, sw), or more in
2886 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2887 and let the move_by_pieces code copy the string from read-only
2888 memory. In the future, this could be tuned further for multi-issue
2889 CPUs that can issue stores down one pipe and arithmetic instructions
2890 down another; in that case, the lui/ori/sw combination would be a
2891 win for long enough strings. */
2892
2893 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2894 \f
2895 #ifndef __mips16
2896 /* Since the bits of the _init and _fini function is spread across
2897 many object files, each potentially with its own GP, we must assume
2898 we need to load our GP. We don't preserve $gp or $ra, since each
2899 init/fini chunk is supposed to initialize $gp, and crti/crtn
2900 already take care of preserving $ra and, when appropriate, $gp. */
2901 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2902 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2903 asm (SECTION_OP "\n\
2904 .set noreorder\n\
2905 bal 1f\n\
2906 nop\n\
2907 1: .cpload $31\n\
2908 .set reorder\n\
2909 jal " USER_LABEL_PREFIX #FUNC "\n\
2910 " TEXT_SECTION_ASM_OP);
2911 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2912 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2913 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2914 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2915 asm (SECTION_OP "\n\
2916 .set noreorder\n\
2917 bal 1f\n\
2918 nop\n\
2919 1: .set reorder\n\
2920 .cpsetup $31, $2, 1b\n\
2921 jal " USER_LABEL_PREFIX #FUNC "\n\
2922 " TEXT_SECTION_ASM_OP);
2923 #endif
2924 #endif
2925
2926 #ifndef HAVE_AS_TLS
2927 #define HAVE_AS_TLS 0
2928 #endif
2929
2930 #ifndef USED_FOR_TARGET
2931 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2932 struct mips_asm_switch {
2933 /* The FOO in the description above. */
2934 const char *name;
2935
2936 /* The current block nesting level, or 0 if we aren't in a block. */
2937 int nesting_level;
2938 };
2939
2940 extern const enum reg_class mips_regno_to_class[];
2941 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2942 extern const char *current_function_file; /* filename current function is in */
2943 extern int num_source_filenames; /* current .file # */
2944 extern struct mips_asm_switch mips_noreorder;
2945 extern struct mips_asm_switch mips_nomacro;
2946 extern struct mips_asm_switch mips_noat;
2947 extern int mips_dbx_regno[];
2948 extern int mips_dwarf_regno[];
2949 extern bool mips_split_p[];
2950 extern bool mips_split_hi_p[];
2951 extern enum processor mips_arch; /* which cpu to codegen for */
2952 extern enum processor mips_tune; /* which cpu to schedule for */
2953 extern int mips_isa; /* architectural level */
2954 extern int mips_abi; /* which ABI to use */
2955 extern const struct mips_cpu_info *mips_arch_info;
2956 extern const struct mips_cpu_info *mips_tune_info;
2957 extern bool mips_base_mips16;
2958 extern enum mips_code_readable_setting mips_code_readable;
2959 extern GTY(()) struct target_globals *mips16_globals;
2960 #endif
2961
2962 /* Enable querying of DFA units. */
2963 #define CPU_UNITS_QUERY 1
2964
2965 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2966 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2967
2968 /* As on most targets, we want the .eh_frame section to be read-only where
2969 possible. And as on most targets, this means two things:
2970
2971 (a) Non-locally-binding pointers must have an indirect encoding,
2972 so that the addresses in the .eh_frame section itself become
2973 locally-binding.
2974
2975 (b) A shared library's .eh_frame section must encode locally-binding
2976 pointers in a relative (relocation-free) form.
2977
2978 However, MIPS has traditionally not allowed directives like:
2979
2980 .long x-.
2981
2982 in cases where "x" is in a different section, or is not defined in the
2983 same assembly file. We are therefore unable to emit the PC-relative
2984 form required by (b) at assembly time.
2985
2986 Fortunately, the linker is able to convert absolute addresses into
2987 PC-relative addresses on our behalf. Unfortunately, only certain
2988 versions of the linker know how to do this for indirect pointers,
2989 and for personality data. We must fall back on using writable
2990 .eh_frame sections for shared libraries if the linker does not
2991 support this feature. */
2992 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2993 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2994
2995 /* For switching between MIPS16 and non-MIPS16 modes. */
2996 #define SWITCHABLE_TARGET 1