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[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken. */
51 #define PTF_AVOID_BRANCHLIKELY 0x1
52
53 /* Information about one recognized processor. Defined here for the
54 benefit of TARGET_CPU_CPP_BUILTINS. */
55 struct mips_cpu_info {
56 /* The 'canonical' name of the processor as far as GCC is concerned.
57 It's typically a manufacturer's prefix followed by a numerical
58 designation. It should be lowercase. */
59 const char *name;
60
61 /* The internal processor number that most closely matches this
62 entry. Several processors can have the same value, if there's no
63 difference between them from GCC's point of view. */
64 enum processor cpu;
65
66 /* The ISA level that the processor implements. */
67 int isa;
68
69 /* A mask of PTF_* values. */
70 unsigned int tune_flags;
71 };
72
73 #include "config/mips/mips-opts.h"
74
75 /* Macros to silence warnings about numbers being signed in traditional
76 C and unsigned in ISO C when compiled on 32-bit hosts. */
77
78 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
79 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
80 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
81
82 \f
83 /* Run-time compilation parameters selecting different hardware subsets. */
84
85 /* True if we are generating position-independent VxWorks RTP code. */
86 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
87
88 /* True if the output file is marked as ".abicalls; .option pic0"
89 (-call_nonpic). */
90 #define TARGET_ABICALLS_PIC0 \
91 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
92
93 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
94 #define TARGET_ABICALLS_PIC2 \
95 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
96
97 /* True if the call patterns should be split into a jalr followed by
98 an instruction to restore $gp. It is only safe to split the load
99 from the call when every use of $gp is explicit.
100
101 See mips_must_initialize_gp_p for details about how we manage the
102 global pointer. */
103
104 #define TARGET_SPLIT_CALLS \
105 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
106
107 /* True if we're generating a form of -mabicalls in which we can use
108 operators like %hi and %lo to refer to locally-binding symbols.
109 We can only do this for -mno-shared, and only then if we can use
110 relocation operations instead of assembly macros. It isn't really
111 worth using absolute sequences for 64-bit symbols because GOT
112 accesses are so much shorter. */
113
114 #define TARGET_ABSOLUTE_ABICALLS \
115 (TARGET_ABICALLS \
116 && !TARGET_SHARED \
117 && TARGET_EXPLICIT_RELOCS \
118 && !ABI_HAS_64BIT_SYMBOLS)
119
120 /* True if we can optimize sibling calls. For simplicity, we only
121 handle cases in which call_insn_operand will reject invalid
122 sibcall addresses. There are two cases in which this isn't true:
123
124 - TARGET_MIPS16. call_insn_operand accepts constant addresses
125 but there is no direct jump instruction. It isn't worth
126 using sibling calls in this case anyway; they would usually
127 be longer than normal calls.
128
129 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
130 accepts global constants, but all sibcalls must be indirect. */
131 #define TARGET_SIBCALLS \
132 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
133
134 /* True if we need to use a global offset table to access some symbols. */
135 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
136
137 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
138 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
139
140 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
141 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
142
143 /* True if we should use .cprestore to store to the cprestore slot.
144
145 We continue to use .cprestore for explicit-reloc code so that JALs
146 inside inline asms will work correctly. */
147 #define TARGET_CPRESTORE_DIRECTIVE \
148 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
149
150 /* True if we can use the J and JAL instructions. */
151 #define TARGET_ABSOLUTE_JUMPS \
152 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
153
154 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
155 This is true for both the PIC and non-PIC VxWorks RTP modes. */
156 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
157
158 /* True if .gpword or .gpdword should be used for switch tables. */
159 #define TARGET_GPWORD \
160 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
161
162 /* True if the output must have a writable .eh_frame.
163 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
164 #ifdef HAVE_LD_PERSONALITY_RELAXATION
165 #define TARGET_WRITABLE_EH_FRAME 0
166 #else
167 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
168 #endif
169
170 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
171 #ifdef HAVE_AS_DSPR1_MULT
172 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
173 #else
174 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
175 #endif
176
177 /* Generate mips16 code */
178 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
179 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
180 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
181 /* Generate mips16e register save/restore sequences. */
182 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
183
184 /* True if we're generating a form of MIPS16 code in which general
185 text loads are allowed. */
186 #define TARGET_MIPS16_TEXT_LOADS \
187 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
188
189 /* True if we're generating a form of MIPS16 code in which PC-relative
190 loads are allowed. */
191 #define TARGET_MIPS16_PCREL_LOADS \
192 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
193
194 /* Generic ISA defines. */
195 #define ISA_MIPS1 (mips_isa == 1)
196 #define ISA_MIPS2 (mips_isa == 2)
197 #define ISA_MIPS3 (mips_isa == 3)
198 #define ISA_MIPS4 (mips_isa == 4)
199 #define ISA_MIPS32 (mips_isa == 32)
200 #define ISA_MIPS32R2 (mips_isa == 33)
201 #define ISA_MIPS64 (mips_isa == 64)
202 #define ISA_MIPS64R2 (mips_isa == 65)
203
204 /* Architecture target defines. */
205 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
206 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
207 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
208 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
209 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
210 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
211 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
212 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
213 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
214 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
215 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
216 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
217 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
218 || mips_arch == PROCESSOR_OCTEON2)
219 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
220 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
221 || mips_arch == PROCESSOR_SB1A)
222 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
223 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
224
225 /* Scheduling target defines. */
226 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
227 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
228 || mips_tune == PROCESSOR_24KF2_1 \
229 || mips_tune == PROCESSOR_24KF1_1)
230 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
231 || mips_tune == PROCESSOR_74KF2_1 \
232 || mips_tune == PROCESSOR_74KF1_1 \
233 || mips_tune == PROCESSOR_74KF3_2)
234 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
235 || mips_tune == PROCESSOR_LOONGSON_2F)
236 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
237 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
238 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
239 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
240 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
241 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
242 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
243 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
244 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
245 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
246 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
247 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
248 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
249 || mips_tune == PROCESSOR_OCTEON2)
250 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
251 || mips_tune == PROCESSOR_SB1A)
252
253 /* Whether vector modes and intrinsics for ST Microelectronics
254 Loongson-2E/2F processors should be enabled. In o32 pairs of
255 floating-point registers provide 64-bit values. */
256 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
257 && (TARGET_LOONGSON_2EF \
258 || TARGET_LOONGSON_3A))
259
260 /* True if the pre-reload scheduler should try to create chains of
261 multiply-add or multiply-subtract instructions. For example,
262 suppose we have:
263
264 t1 = a * b
265 t2 = t1 + c * d
266 t3 = e * f
267 t4 = t3 - g * h
268
269 t1 will have a higher priority than t2 and t3 will have a higher
270 priority than t4. However, before reload, there is no dependence
271 between t1 and t3, and they can often have similar priorities.
272 The scheduler will then tend to prefer:
273
274 t1 = a * b
275 t3 = e * f
276 t2 = t1 + c * d
277 t4 = t3 - g * h
278
279 which stops us from making full use of macc/madd-style instructions.
280 This sort of situation occurs frequently in Fourier transforms and
281 in unrolled loops.
282
283 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
284 queue so that chained multiply-add and multiply-subtract instructions
285 appear ahead of any other instruction that is likely to clobber lo.
286 In the example above, if t2 and t3 become ready at the same time,
287 the code ensures that t2 is scheduled first.
288
289 Multiply-accumulate instructions are a bigger win for some targets
290 than others, so this macro is defined on an opt-in basis. */
291 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
292 || TUNE_MIPS4120 \
293 || TUNE_MIPS4130 \
294 || TUNE_24K)
295
296 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
297 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
298
299 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
300 directly accessible, while the command-line options select
301 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
302 in use. */
303 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
304 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
305
306 /* False if SC acts as a memory barrier with respect to itself,
307 otherwise a SYNC will be emitted after SC for atomic operations
308 that require ordering between the SC and following loads and
309 stores. It does not tell anything about ordering of loads and
310 stores prior to and following the SC, only about the SC itself and
311 those loads and stores follow it. */
312 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
313
314 /* Define preprocessor macros for the -march and -mtune options.
315 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
316 processor. If INFO's canonical name is "foo", define PREFIX to
317 be "foo", and define an additional macro PREFIX_FOO. */
318 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
319 do \
320 { \
321 char *macro, *p; \
322 \
323 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
324 for (p = macro; *p != 0; p++) \
325 if (*p == '+') \
326 *p = 'P'; \
327 else \
328 *p = TOUPPER (*p); \
329 \
330 builtin_define (macro); \
331 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
332 free (macro); \
333 } \
334 while (0)
335
336 /* Target CPU builtins. */
337 #define TARGET_CPU_CPP_BUILTINS() \
338 do \
339 { \
340 builtin_assert ("machine=mips"); \
341 builtin_assert ("cpu=mips"); \
342 builtin_define ("__mips__"); \
343 builtin_define ("_mips"); \
344 \
345 /* We do this here because __mips is defined below and so we \
346 can't use builtin_define_std. We don't ever want to define \
347 "mips" for VxWorks because some of the VxWorks headers \
348 construct include filenames from a root directory macro, \
349 an architecture macro and a filename, where the architecture \
350 macro expands to 'mips'. If we define 'mips' to 1, the \
351 architecture macro expands to 1 as well. */ \
352 if (!flag_iso && !TARGET_VXWORKS) \
353 builtin_define ("mips"); \
354 \
355 if (TARGET_64BIT) \
356 builtin_define ("__mips64"); \
357 \
358 /* Treat _R3000 and _R4000 like register-size \
359 defines, which is how they've historically \
360 been used. */ \
361 if (TARGET_64BIT) \
362 { \
363 builtin_define_std ("R4000"); \
364 builtin_define ("_R4000"); \
365 } \
366 else \
367 { \
368 builtin_define_std ("R3000"); \
369 builtin_define ("_R3000"); \
370 } \
371 \
372 if (TARGET_FLOAT64) \
373 builtin_define ("__mips_fpr=64"); \
374 else \
375 builtin_define ("__mips_fpr=32"); \
376 \
377 if (mips_base_mips16) \
378 builtin_define ("__mips16"); \
379 \
380 if (TARGET_MIPS3D) \
381 builtin_define ("__mips3d"); \
382 \
383 if (TARGET_SMARTMIPS) \
384 builtin_define ("__mips_smartmips"); \
385 \
386 if (TARGET_MCU) \
387 builtin_define ("__mips_mcu"); \
388 \
389 if (TARGET_DSP) \
390 { \
391 builtin_define ("__mips_dsp"); \
392 if (TARGET_DSPR2) \
393 { \
394 builtin_define ("__mips_dspr2"); \
395 builtin_define ("__mips_dsp_rev=2"); \
396 } \
397 else \
398 builtin_define ("__mips_dsp_rev=1"); \
399 } \
400 \
401 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
402 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
403 \
404 if (ISA_MIPS1) \
405 { \
406 builtin_define ("__mips=1"); \
407 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
408 } \
409 else if (ISA_MIPS2) \
410 { \
411 builtin_define ("__mips=2"); \
412 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
413 } \
414 else if (ISA_MIPS3) \
415 { \
416 builtin_define ("__mips=3"); \
417 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
418 } \
419 else if (ISA_MIPS4) \
420 { \
421 builtin_define ("__mips=4"); \
422 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
423 } \
424 else if (ISA_MIPS32) \
425 { \
426 builtin_define ("__mips=32"); \
427 builtin_define ("__mips_isa_rev=1"); \
428 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
429 } \
430 else if (ISA_MIPS32R2) \
431 { \
432 builtin_define ("__mips=32"); \
433 builtin_define ("__mips_isa_rev=2"); \
434 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
435 } \
436 else if (ISA_MIPS64) \
437 { \
438 builtin_define ("__mips=64"); \
439 builtin_define ("__mips_isa_rev=1"); \
440 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
441 } \
442 else if (ISA_MIPS64R2) \
443 { \
444 builtin_define ("__mips=64"); \
445 builtin_define ("__mips_isa_rev=2"); \
446 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
447 } \
448 \
449 switch (mips_abi) \
450 { \
451 case ABI_32: \
452 builtin_define ("_ABIO32=1"); \
453 builtin_define ("_MIPS_SIM=_ABIO32"); \
454 break; \
455 \
456 case ABI_N32: \
457 builtin_define ("_ABIN32=2"); \
458 builtin_define ("_MIPS_SIM=_ABIN32"); \
459 break; \
460 \
461 case ABI_64: \
462 builtin_define ("_ABI64=3"); \
463 builtin_define ("_MIPS_SIM=_ABI64"); \
464 break; \
465 \
466 case ABI_O64: \
467 builtin_define ("_ABIO64=4"); \
468 builtin_define ("_MIPS_SIM=_ABIO64"); \
469 break; \
470 } \
471 \
472 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
473 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
474 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
475 builtin_define_with_int_value ("_MIPS_FPSET", \
476 32 / MAX_FPRS_PER_FMT); \
477 \
478 /* These defines reflect the ABI in use, not whether the \
479 FPU is directly accessible. */ \
480 if (TARGET_NO_FLOAT) \
481 builtin_define ("__mips_no_float"); \
482 else if (TARGET_HARD_FLOAT_ABI) \
483 builtin_define ("__mips_hard_float"); \
484 else \
485 builtin_define ("__mips_soft_float"); \
486 \
487 if (TARGET_SINGLE_FLOAT) \
488 builtin_define ("__mips_single_float"); \
489 \
490 if (TARGET_PAIRED_SINGLE_FLOAT) \
491 builtin_define ("__mips_paired_single_float"); \
492 \
493 if (TARGET_BIG_ENDIAN) \
494 { \
495 builtin_define_std ("MIPSEB"); \
496 builtin_define ("_MIPSEB"); \
497 } \
498 else \
499 { \
500 builtin_define_std ("MIPSEL"); \
501 builtin_define ("_MIPSEL"); \
502 } \
503 \
504 /* Whether calls should go through $25. The separate __PIC__ \
505 macro indicates whether abicalls code might use a GOT. */ \
506 if (TARGET_ABICALLS) \
507 builtin_define ("__mips_abicalls"); \
508 \
509 /* Whether Loongson vector modes are enabled. */ \
510 if (TARGET_LOONGSON_VECTORS) \
511 builtin_define ("__mips_loongson_vector_rev"); \
512 \
513 /* Historical Octeon macro. */ \
514 if (TARGET_OCTEON) \
515 builtin_define ("__OCTEON__"); \
516 \
517 if (TARGET_SYNCI) \
518 builtin_define ("__mips_synci"); \
519 \
520 /* Macros dependent on the C dialect. */ \
521 if (preprocessing_asm_p ()) \
522 { \
523 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
524 builtin_define ("_LANGUAGE_ASSEMBLY"); \
525 } \
526 else if (c_dialect_cxx ()) \
527 { \
528 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
529 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
530 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
531 } \
532 else \
533 { \
534 builtin_define_std ("LANGUAGE_C"); \
535 builtin_define ("_LANGUAGE_C"); \
536 } \
537 if (c_dialect_objc ()) \
538 { \
539 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
540 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
541 /* Bizarre, but retained for backwards compatibility. */ \
542 builtin_define_std ("LANGUAGE_C"); \
543 builtin_define ("_LANGUAGE_C"); \
544 } \
545 \
546 if (mips_abi == ABI_EABI) \
547 builtin_define ("__mips_eabi"); \
548 \
549 if (TARGET_CACHE_BUILTIN) \
550 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
551 } \
552 while (0)
553
554 /* Default target_flags if no switches are specified */
555
556 #ifndef TARGET_DEFAULT
557 #define TARGET_DEFAULT 0
558 #endif
559
560 #ifndef TARGET_CPU_DEFAULT
561 #define TARGET_CPU_DEFAULT 0
562 #endif
563
564 #ifndef TARGET_ENDIAN_DEFAULT
565 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
566 #endif
567
568 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
569 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
570 #endif
571
572 #ifdef IN_LIBGCC2
573 #undef TARGET_64BIT
574 /* Make this compile time constant for libgcc2 */
575 #ifdef __mips64
576 #define TARGET_64BIT 1
577 #else
578 #define TARGET_64BIT 0
579 #endif
580 #endif /* IN_LIBGCC2 */
581
582 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
583 when compiled with hardware floating point. This is because MIPS16
584 code cannot save and restore the floating-point registers, which is
585 important if in a mixed MIPS16/non-MIPS16 environment. */
586
587 #ifdef IN_LIBGCC2
588 #if __mips_hard_float
589 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
590 #endif
591 #endif /* IN_LIBGCC2 */
592
593 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
594
595 #ifndef MULTILIB_ENDIAN_DEFAULT
596 #if TARGET_ENDIAN_DEFAULT == 0
597 #define MULTILIB_ENDIAN_DEFAULT "EL"
598 #else
599 #define MULTILIB_ENDIAN_DEFAULT "EB"
600 #endif
601 #endif
602
603 #ifndef MULTILIB_ISA_DEFAULT
604 # if MIPS_ISA_DEFAULT == 1
605 # define MULTILIB_ISA_DEFAULT "mips1"
606 # else
607 # if MIPS_ISA_DEFAULT == 2
608 # define MULTILIB_ISA_DEFAULT "mips2"
609 # else
610 # if MIPS_ISA_DEFAULT == 3
611 # define MULTILIB_ISA_DEFAULT "mips3"
612 # else
613 # if MIPS_ISA_DEFAULT == 4
614 # define MULTILIB_ISA_DEFAULT "mips4"
615 # else
616 # if MIPS_ISA_DEFAULT == 32
617 # define MULTILIB_ISA_DEFAULT "mips32"
618 # else
619 # if MIPS_ISA_DEFAULT == 33
620 # define MULTILIB_ISA_DEFAULT "mips32r2"
621 # else
622 # if MIPS_ISA_DEFAULT == 64
623 # define MULTILIB_ISA_DEFAULT "mips64"
624 # else
625 # if MIPS_ISA_DEFAULT == 65
626 # define MULTILIB_ISA_DEFAULT "mips64r2"
627 # else
628 # define MULTILIB_ISA_DEFAULT "mips1"
629 # endif
630 # endif
631 # endif
632 # endif
633 # endif
634 # endif
635 # endif
636 # endif
637 #endif
638
639 #ifndef MIPS_ABI_DEFAULT
640 #define MIPS_ABI_DEFAULT ABI_32
641 #endif
642
643 /* Use the most portable ABI flag for the ASM specs. */
644
645 #if MIPS_ABI_DEFAULT == ABI_32
646 #define MULTILIB_ABI_DEFAULT "mabi=32"
647 #endif
648
649 #if MIPS_ABI_DEFAULT == ABI_O64
650 #define MULTILIB_ABI_DEFAULT "mabi=o64"
651 #endif
652
653 #if MIPS_ABI_DEFAULT == ABI_N32
654 #define MULTILIB_ABI_DEFAULT "mabi=n32"
655 #endif
656
657 #if MIPS_ABI_DEFAULT == ABI_64
658 #define MULTILIB_ABI_DEFAULT "mabi=64"
659 #endif
660
661 #if MIPS_ABI_DEFAULT == ABI_EABI
662 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
663 #endif
664
665 #ifndef MULTILIB_DEFAULTS
666 #define MULTILIB_DEFAULTS \
667 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
668 #endif
669
670 /* We must pass -EL to the linker by default for little endian embedded
671 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
672 linker will default to using big-endian output files. The OUTPUT_FORMAT
673 line must be in the linker script, otherwise -EB/-EL will not work. */
674
675 #ifndef ENDIAN_SPEC
676 #if TARGET_ENDIAN_DEFAULT == 0
677 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
678 #else
679 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
680 #endif
681 #endif
682
683 /* A spec condition that matches all non-mips16 -mips arguments. */
684
685 #define MIPS_ISA_LEVEL_OPTION_SPEC \
686 "mips1|mips2|mips3|mips4|mips32*|mips64*"
687
688 /* A spec condition that matches all non-mips16 architecture arguments. */
689
690 #define MIPS_ARCH_OPTION_SPEC \
691 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
692
693 /* A spec that infers a -mips argument from an -march argument,
694 or injects the default if no architecture is specified. */
695
696 #define MIPS_ISA_LEVEL_SPEC \
697 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
698 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
699 %{march=mips2|march=r6000:-mips2} \
700 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
701 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
702 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
703 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
704 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
705 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
706 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
707 |march=xlr|march=loongson3a: -mips64} \
708 %{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
709 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
710
711 /* A spec that infers a -mhard-float or -msoft-float setting from an
712 -march argument. Note that soft-float and hard-float code are not
713 link-compatible. */
714
715 #define MIPS_ARCH_FLOAT_SPEC \
716 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
717 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
718 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
719 |march=octeon|march=xlr: -msoft-float; \
720 march=*: -mhard-float}"
721
722 /* A spec condition that matches 32-bit options. It only works if
723 MIPS_ISA_LEVEL_SPEC has been applied. */
724
725 #define MIPS_32BIT_OPTION_SPEC \
726 "mips1|mips2|mips32*|mgp32"
727
728 /* Infer a -msynci setting from a -mips argument, on the assumption that
729 -msynci is desired where possible. */
730 #define MIPS_ISA_SYNCI_SPEC \
731 "%{msynci|mno-synci:;:%{mips32r2|mips64r2:-msynci;:-mno-synci}}"
732
733 #if MIPS_ABI_DEFAULT == ABI_O64 \
734 || MIPS_ABI_DEFAULT == ABI_N32 \
735 || MIPS_ABI_DEFAULT == ABI_64
736 #define OPT_ARCH64 "mabi=32|mgp32:;"
737 #define OPT_ARCH32 "mabi=32|mgp32"
738 #else
739 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
740 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
741 #endif
742
743 /* Support for a compile-time default CPU, et cetera. The rules are:
744 --with-arch is ignored if -march is specified or a -mips is specified
745 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
746 --with-tune is ignored if -mtune is specified; likewise
747 --with-tune-32 and --with-tune-64.
748 --with-abi is ignored if -mabi is specified.
749 --with-float is ignored if -mhard-float or -msoft-float are
750 specified.
751 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
752 specified. */
753 #define OPTION_DEFAULT_SPECS \
754 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
755 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
756 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
757 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
758 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
759 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
760 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
761 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
762 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
763 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
764 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
765 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
766
767 /* A spec that infers the -mdsp setting from an -march argument. */
768 #define BASE_DRIVER_SELF_SPECS \
769 "%{!mno-dsp: \
770 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
771 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
772
773 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
774
775 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
776 && ISA_HAS_COND_TRAP)
777
778 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
779
780 /* True if the ABI can only work with 64-bit integer registers. We
781 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
782 otherwise floating-point registers must also be 64-bit. */
783 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
784
785 /* Likewise for 32-bit regs. */
786 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
787
788 /* True if the file format uses 64-bit symbols. At present, this is
789 only true for n64, which uses 64-bit ELF. */
790 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
791
792 /* True if symbols are 64 bits wide. This is usually determined by
793 the ABI's file format, but it can be overridden by -msym32. Note that
794 overriding the size with -msym32 changes the ABI of relocatable objects,
795 although it doesn't change the ABI of a fully-linked object. */
796 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
797 && Pmode == DImode \
798 && !TARGET_SYM32)
799
800 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
801 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
802 || ISA_MIPS4 \
803 || ISA_MIPS64 \
804 || ISA_MIPS64R2)
805
806 /* ISA has branch likely instructions (e.g. mips2). */
807 /* Disable branchlikely for tx39 until compare rewrite. They haven't
808 been generated up to this point. */
809 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
810
811 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
812 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
813 || TARGET_MIPS5400 \
814 || TARGET_MIPS5500 \
815 || TARGET_MIPS7000 \
816 || TARGET_MIPS9000 \
817 || TARGET_MAD \
818 || ISA_MIPS32 \
819 || ISA_MIPS32R2 \
820 || ISA_MIPS64 \
821 || ISA_MIPS64R2) \
822 && !TARGET_MIPS16)
823
824 /* ISA has a three-operand multiplication instruction. */
825 #define ISA_HAS_DMUL3 (TARGET_64BIT \
826 && TARGET_OCTEON \
827 && !TARGET_MIPS16)
828
829 /* ISA has the floating-point conditional move instructions introduced
830 in mips4. */
831 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
832 || ISA_MIPS32 \
833 || ISA_MIPS32R2 \
834 || ISA_MIPS64 \
835 || ISA_MIPS64R2) \
836 && !TARGET_MIPS5500 \
837 && !TARGET_MIPS16)
838
839 /* ISA has the integer conditional move instructions introduced in mips4 and
840 ST Loongson 2E/2F. */
841 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
842
843 /* ISA has LDC1 and SDC1. */
844 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
845
846 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
847 branch on CC, and move (both FP and non-FP) on CC. */
848 #define ISA_HAS_8CC (ISA_MIPS4 \
849 || ISA_MIPS32 \
850 || ISA_MIPS32R2 \
851 || ISA_MIPS64 \
852 || ISA_MIPS64R2)
853
854 /* This is a catch all for other mips4 instructions: indexed load, the
855 FP madd and msub instructions, and the FP recip and recip sqrt
856 instructions. */
857 #define ISA_HAS_FP4 ((ISA_MIPS4 \
858 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
859 || ISA_MIPS64 \
860 || ISA_MIPS64R2) \
861 && !TARGET_MIPS16)
862
863 /* ISA has paired-single instructions. */
864 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
865
866 /* ISA has conditional trap instructions. */
867 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
868 && !TARGET_MIPS16)
869
870 /* ISA has integer multiply-accumulate instructions, madd and msub. */
871 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
872 || ISA_MIPS32R2 \
873 || ISA_MIPS64 \
874 || ISA_MIPS64R2) \
875 && !TARGET_MIPS16)
876
877 /* Integer multiply-accumulate instructions should be generated. */
878 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
879
880 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
881 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
882
883 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
884 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
885
886 /* ISA has floating-point nmadd and nmsub instructions
887 'd = -((a * b) [+-] c)'. */
888 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
889 ((ISA_MIPS4 \
890 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
891 || ISA_MIPS64 \
892 || ISA_MIPS64R2) \
893 && (!TARGET_MIPS5400 || TARGET_MAD) \
894 && !TARGET_MIPS16)
895
896 /* ISA has floating-point nmadd and nmsub instructions
897 'c = -((a * b) [+-] c)'. */
898 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
899 TARGET_LOONGSON_2EF
900
901 /* ISA has count leading zeroes/ones instruction (not implemented). */
902 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
903 || ISA_MIPS32R2 \
904 || ISA_MIPS64 \
905 || ISA_MIPS64R2) \
906 && !TARGET_MIPS16)
907
908 /* ISA has three operand multiply instructions that put
909 the high part in an accumulator: mulhi or mulhiu. */
910 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
911 || TARGET_MIPS5500 \
912 || TARGET_SR71K) \
913 && !TARGET_MIPS16)
914
915 /* ISA has three operand multiply instructions that
916 negates the result and puts the result in an accumulator. */
917 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
918 || TARGET_MIPS5500 \
919 || TARGET_SR71K) \
920 && !TARGET_MIPS16)
921
922 /* ISA has three operand multiply instructions that subtracts the
923 result from a 4th operand and puts the result in an accumulator. */
924 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
925 || TARGET_MIPS5500 \
926 || TARGET_SR71K) \
927 && !TARGET_MIPS16)
928
929 /* ISA has three operand multiply instructions that the result
930 from a 4th operand and puts the result in an accumulator. */
931 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
932 || TARGET_MIPS4130 \
933 || TARGET_MIPS5400 \
934 || TARGET_MIPS5500 \
935 || TARGET_SR71K) \
936 && !TARGET_MIPS16)
937
938 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
939 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
940 || TARGET_MIPS4130) \
941 && !TARGET_MIPS16)
942
943 /* ISA has the "ror" (rotate right) instructions. */
944 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
945 || ISA_MIPS64R2 \
946 || TARGET_MIPS5400 \
947 || TARGET_MIPS5500 \
948 || TARGET_SR71K \
949 || TARGET_SMARTMIPS) \
950 && !TARGET_MIPS16)
951
952 /* ISA has data prefetch instructions. This controls use of 'pref'. */
953 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
954 || TARGET_LOONGSON_2EF \
955 || ISA_MIPS32 \
956 || ISA_MIPS32R2 \
957 || ISA_MIPS64 \
958 || ISA_MIPS64R2) \
959 && !TARGET_MIPS16)
960
961 /* ISA has data indexed prefetch instructions. This controls use of
962 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
963 (prefx is a cop1x instruction, so can only be used if FP is
964 enabled.) */
965 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
966 || ISA_MIPS32R2 \
967 || ISA_MIPS64 \
968 || ISA_MIPS64R2) \
969 && !TARGET_MIPS16)
970
971 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
972 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
973 also requires TARGET_DOUBLE_FLOAT. */
974 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
975
976 /* ISA includes the MIPS32r2 seb and seh instructions. */
977 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
978 || ISA_MIPS64R2) \
979 && !TARGET_MIPS16)
980
981 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
982 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
983 || ISA_MIPS64R2) \
984 && !TARGET_MIPS16)
985
986 /* ISA has instructions for accessing top part of 64-bit fp regs. */
987 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
988 && (ISA_MIPS32R2 \
989 || ISA_MIPS64R2))
990
991 /* ISA has lwxs instruction (load w/scaled index address. */
992 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
993
994 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
995 #define ISA_HAS_LBX (TARGET_OCTEON2)
996 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
997 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
998 #define ISA_HAS_LHUX (TARGET_OCTEON2)
999 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1000 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1001 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1002 && TARGET_64BIT)
1003
1004 /* The DSP ASE is available. */
1005 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1006
1007 /* Revision 2 of the DSP ASE is available. */
1008 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1009
1010 /* True if the result of a load is not available to the next instruction.
1011 A nop will then be needed between instructions like "lw $4,..."
1012 and "addiu $4,$4,1". */
1013 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1014 && !TARGET_MIPS3900 \
1015 && !TARGET_MIPS16)
1016
1017 /* Likewise mtc1 and mfc1. */
1018 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1019 && !TARGET_LOONGSON_2EF)
1020
1021 /* Likewise floating-point comparisons. */
1022 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1023 && !TARGET_LOONGSON_2EF)
1024
1025 /* True if mflo and mfhi can be immediately followed by instructions
1026 which write to the HI and LO registers.
1027
1028 According to MIPS specifications, MIPS ISAs I, II, and III need
1029 (at least) two instructions between the reads of HI/LO and
1030 instructions which write them, and later ISAs do not. Contradicting
1031 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1032 the UM for the NEC Vr5000) document needing the instructions between
1033 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1034 MIPS64 and later ISAs to have the interlocks, plus any specific
1035 earlier-ISA CPUs for which CPU documentation declares that the
1036 instructions are really interlocked. */
1037 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1038 || ISA_MIPS32R2 \
1039 || ISA_MIPS64 \
1040 || ISA_MIPS64R2 \
1041 || TARGET_MIPS5500 \
1042 || TARGET_LOONGSON_2EF)
1043
1044 /* ISA includes synci, jr.hb and jalr.hb. */
1045 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1046 || ISA_MIPS64R2) \
1047 && !TARGET_MIPS16)
1048
1049 /* ISA includes sync. */
1050 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1051 #define GENERATE_SYNC \
1052 (target_flags_explicit & MASK_LLSC \
1053 ? TARGET_LLSC && !TARGET_MIPS16 \
1054 : ISA_HAS_SYNC)
1055
1056 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1057 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1058 instructions. */
1059 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1060 #define GENERATE_LL_SC \
1061 (target_flags_explicit & MASK_LLSC \
1062 ? TARGET_LLSC && !TARGET_MIPS16 \
1063 : ISA_HAS_LL_SC)
1064
1065 #define ISA_HAS_SWAP (TARGET_XLP)
1066 #define ISA_HAS_LDADD (TARGET_XLP)
1067
1068 /* ISA includes the baddu instruction. */
1069 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1070
1071 /* ISA includes the bbit* instructions. */
1072 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1073
1074 /* ISA includes the cins instruction. */
1075 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1076
1077 /* ISA includes the exts instruction. */
1078 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1079
1080 /* ISA includes the seq and sne instructions. */
1081 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1082
1083 /* ISA includes the pop instruction. */
1084 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1085
1086 /* The CACHE instruction is available in non-MIPS16 code. */
1087 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1088
1089 /* The CACHE instruction is available. */
1090 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1091 \f
1092 /* Tell collect what flags to pass to nm. */
1093 #ifndef NM_FLAGS
1094 #define NM_FLAGS "-Bn"
1095 #endif
1096
1097 \f
1098 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1099 the assembler. It may be overridden by subtargets.
1100
1101 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1102 COFF debugging info. */
1103
1104 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1105 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1106 %{g} %{g0} %{g1} %{g2} %{g3} \
1107 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1108 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1109 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1110 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1111 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1112 #endif
1113
1114 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1115 overridden by subtargets. */
1116
1117 #ifndef SUBTARGET_ASM_SPEC
1118 #define SUBTARGET_ASM_SPEC ""
1119 #endif
1120
1121 #undef ASM_SPEC
1122 #define ASM_SPEC "\
1123 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1124 %{mips32*} %{mips64*} \
1125 %{mips16} %{mno-mips16:-no-mips16} \
1126 %{mips3d} %{mno-mips3d:-no-mips3d} \
1127 %{mdmx} %{mno-mdmx:-no-mdmx} \
1128 %{mdsp} %{mno-dsp} \
1129 %{mdspr2} %{mno-dspr2} \
1130 %{mmcu} %{mno-mcu} \
1131 %{msmartmips} %{mno-smartmips} \
1132 %{mmt} %{mno-mt} \
1133 %{mfix-vr4120} %{mfix-vr4130} \
1134 %{mfix-24k} \
1135 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1136 %(subtarget_asm_debugging_spec) \
1137 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1138 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1139 %{mfp32} %{mfp64} \
1140 %{mshared} %{mno-shared} \
1141 %{msym32} %{mno-sym32} \
1142 %{mtune=*} \
1143 %(subtarget_asm_spec)"
1144
1145 /* Extra switches sometimes passed to the linker. */
1146
1147 #ifndef LINK_SPEC
1148 #define LINK_SPEC "\
1149 %(endian_spec) \
1150 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1151 %{shared}"
1152 #endif /* LINK_SPEC defined */
1153
1154
1155 /* Specs for the compiler proper */
1156
1157 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1158 overridden by subtargets. */
1159 #ifndef SUBTARGET_CC1_SPEC
1160 #define SUBTARGET_CC1_SPEC ""
1161 #endif
1162
1163 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1164
1165 #undef CC1_SPEC
1166 #define CC1_SPEC "\
1167 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1168 %(subtarget_cc1_spec)"
1169
1170 /* Preprocessor specs. */
1171
1172 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1173 overridden by subtargets. */
1174 #ifndef SUBTARGET_CPP_SPEC
1175 #define SUBTARGET_CPP_SPEC ""
1176 #endif
1177
1178 #define CPP_SPEC "%(subtarget_cpp_spec)"
1179
1180 /* This macro defines names of additional specifications to put in the specs
1181 that can be used in various specifications like CC1_SPEC. Its definition
1182 is an initializer with a subgrouping for each command option.
1183
1184 Each subgrouping contains a string constant, that defines the
1185 specification name, and a string constant that used by the GCC driver
1186 program.
1187
1188 Do not define this macro if it does not need to do anything. */
1189
1190 #define EXTRA_SPECS \
1191 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1192 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1193 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1194 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1195 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1196 { "endian_spec", ENDIAN_SPEC }, \
1197 SUBTARGET_EXTRA_SPECS
1198
1199 #ifndef SUBTARGET_EXTRA_SPECS
1200 #define SUBTARGET_EXTRA_SPECS
1201 #endif
1202 \f
1203 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1204 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1205
1206 #ifndef PREFERRED_DEBUGGING_TYPE
1207 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1208 #endif
1209
1210 /* The size of DWARF addresses should be the same as the size of symbols
1211 in the target file format. They shouldn't depend on things like -msym32,
1212 because many DWARF consumers do not allow the mixture of address sizes
1213 that one would then get from linking -msym32 code with -msym64 code.
1214
1215 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1216 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1217 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1218
1219 /* By default, turn on GDB extensions. */
1220 #define DEFAULT_GDB_EXTENSIONS 1
1221
1222 /* Local compiler-generated symbols must have a prefix that the assembler
1223 understands. By default, this is $, although some targets (e.g.,
1224 NetBSD-ELF) need to override this. */
1225
1226 #ifndef LOCAL_LABEL_PREFIX
1227 #define LOCAL_LABEL_PREFIX "$"
1228 #endif
1229
1230 /* By default on the mips, external symbols do not have an underscore
1231 prepended, but some targets (e.g., NetBSD) require this. */
1232
1233 #ifndef USER_LABEL_PREFIX
1234 #define USER_LABEL_PREFIX ""
1235 #endif
1236
1237 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1238 since the length can run past this up to a continuation point. */
1239 #undef DBX_CONTIN_LENGTH
1240 #define DBX_CONTIN_LENGTH 1500
1241
1242 /* How to renumber registers for dbx and gdb. */
1243 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1244
1245 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1246 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1247
1248 /* The DWARF 2 CFA column which tracks the return address. */
1249 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1250
1251 /* Before the prologue, RA lives in r31. */
1252 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1253
1254 /* Describe how we implement __builtin_eh_return. */
1255 #define EH_RETURN_DATA_REGNO(N) \
1256 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1257
1258 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1259
1260 #define EH_USES(N) mips_eh_uses (N)
1261
1262 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1263 The default for this in 64-bit mode is 8, which causes problems with
1264 SFmode register saves. */
1265 #define DWARF_CIE_DATA_ALIGNMENT -4
1266
1267 /* Correct the offset of automatic variables and arguments. Note that
1268 the MIPS debug format wants all automatic variables and arguments
1269 to be in terms of the virtual frame pointer (stack pointer before
1270 any adjustment in the function), while the MIPS 3.0 linker wants
1271 the frame pointer to be the stack pointer after the initial
1272 adjustment. */
1273
1274 #define DEBUGGER_AUTO_OFFSET(X) \
1275 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1276 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1277 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1278 \f
1279 /* Target machine storage layout */
1280
1281 #define BITS_BIG_ENDIAN 0
1282 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1283 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1284
1285 #define MAX_BITS_PER_WORD 64
1286
1287 /* Width of a word, in units (bytes). */
1288 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1289 #ifndef IN_LIBGCC2
1290 #define MIN_UNITS_PER_WORD 4
1291 #endif
1292
1293 /* For MIPS, width of a floating point register. */
1294 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1295
1296 /* The number of consecutive floating-point registers needed to store the
1297 largest format supported by the FPU. */
1298 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1299
1300 /* The number of consecutive floating-point registers needed to store the
1301 smallest format supported by the FPU. */
1302 #define MIN_FPRS_PER_FMT \
1303 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1304 ? 1 : MAX_FPRS_PER_FMT)
1305
1306 /* The largest size of value that can be held in floating-point
1307 registers and moved with a single instruction. */
1308 #define UNITS_PER_HWFPVALUE \
1309 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1310
1311 /* The largest size of value that can be held in floating-point
1312 registers. */
1313 #define UNITS_PER_FPVALUE \
1314 (TARGET_SOFT_FLOAT_ABI ? 0 \
1315 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1316 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1317
1318 /* The number of bytes in a double. */
1319 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1320
1321 /* Set the sizes of the core types. */
1322 #define SHORT_TYPE_SIZE 16
1323 #define INT_TYPE_SIZE 32
1324 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1325 #define LONG_LONG_TYPE_SIZE 64
1326
1327 #define FLOAT_TYPE_SIZE 32
1328 #define DOUBLE_TYPE_SIZE 64
1329 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1330
1331 /* Define the sizes of fixed-point types. */
1332 #define SHORT_FRACT_TYPE_SIZE 8
1333 #define FRACT_TYPE_SIZE 16
1334 #define LONG_FRACT_TYPE_SIZE 32
1335 #define LONG_LONG_FRACT_TYPE_SIZE 64
1336
1337 #define SHORT_ACCUM_TYPE_SIZE 16
1338 #define ACCUM_TYPE_SIZE 32
1339 #define LONG_ACCUM_TYPE_SIZE 64
1340 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1341 doesn't support 128-bit integers for MIPS32 currently. */
1342 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1343
1344 /* long double is not a fixed mode, but the idea is that, if we
1345 support long double, we also want a 128-bit integer type. */
1346 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1347
1348 #ifdef IN_LIBGCC2
1349 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1350 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1351 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1352 # else
1353 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1354 # endif
1355 #endif
1356
1357 /* Width in bits of a pointer. */
1358 #ifndef POINTER_SIZE
1359 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1360 #endif
1361
1362 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1363 #define PARM_BOUNDARY BITS_PER_WORD
1364
1365 /* Allocation boundary (in *bits*) for the code of a function. */
1366 #define FUNCTION_BOUNDARY 32
1367
1368 /* Alignment of field after `int : 0' in a structure. */
1369 #define EMPTY_FIELD_BOUNDARY 32
1370
1371 /* Every structure's size must be a multiple of this. */
1372 /* 8 is observed right on a DECstation and on riscos 4.02. */
1373 #define STRUCTURE_SIZE_BOUNDARY 8
1374
1375 /* There is no point aligning anything to a rounder boundary than this. */
1376 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1377
1378 /* All accesses must be aligned. */
1379 #define STRICT_ALIGNMENT 1
1380
1381 /* Define this if you wish to imitate the way many other C compilers
1382 handle alignment of bitfields and the structures that contain
1383 them.
1384
1385 The behavior is that the type written for a bit-field (`int',
1386 `short', or other integer type) imposes an alignment for the
1387 entire structure, as if the structure really did contain an
1388 ordinary field of that type. In addition, the bit-field is placed
1389 within the structure so that it would fit within such a field,
1390 not crossing a boundary for it.
1391
1392 Thus, on most machines, a bit-field whose type is written as `int'
1393 would not cross a four-byte boundary, and would force four-byte
1394 alignment for the whole structure. (The alignment used may not
1395 be four bytes; it is controlled by the other alignment
1396 parameters.)
1397
1398 If the macro is defined, its definition should be a C expression;
1399 a nonzero value for the expression enables this behavior. */
1400
1401 #define PCC_BITFIELD_TYPE_MATTERS 1
1402
1403 /* If defined, a C expression to compute the alignment given to a
1404 constant that is being placed in memory. CONSTANT is the constant
1405 and ALIGN is the alignment that the object would ordinarily have.
1406 The value of this macro is used instead of that alignment to align
1407 the object.
1408
1409 If this macro is not defined, then ALIGN is used.
1410
1411 The typical use of this macro is to increase alignment for string
1412 constants to be word aligned so that `strcpy' calls that copy
1413 constants can be done inline. */
1414
1415 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1416 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1417 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1418
1419 /* If defined, a C expression to compute the alignment for a static
1420 variable. TYPE is the data type, and ALIGN is the alignment that
1421 the object would ordinarily have. The value of this macro is used
1422 instead of that alignment to align the object.
1423
1424 If this macro is not defined, then ALIGN is used.
1425
1426 One use of this macro is to increase alignment of medium-size
1427 data to make it all fit in fewer cache lines. Another is to
1428 cause character arrays to be word-aligned so that `strcpy' calls
1429 that copy constants to character arrays can be done inline. */
1430
1431 #undef DATA_ALIGNMENT
1432 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1433 ((((ALIGN) < BITS_PER_WORD) \
1434 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1435 || TREE_CODE (TYPE) == UNION_TYPE \
1436 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1437
1438 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1439 character arrays to be word-aligned so that `strcpy' calls that copy
1440 constants to character arrays can be done inline, and 'strcmp' can be
1441 optimised to use word loads. */
1442 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1443 DATA_ALIGNMENT (TYPE, ALIGN)
1444
1445 #define PAD_VARARGS_DOWN \
1446 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1447
1448 /* Define if operations between registers always perform the operation
1449 on the full register even if a narrower mode is specified. */
1450 #define WORD_REGISTER_OPERATIONS
1451
1452 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1453 moves. All other references are zero extended. */
1454 #define LOAD_EXTEND_OP(MODE) \
1455 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1456 ? SIGN_EXTEND : ZERO_EXTEND)
1457
1458 /* Define this macro if it is advisable to hold scalars in registers
1459 in a wider mode than that declared by the program. In such cases,
1460 the value is constrained to be within the bounds of the declared
1461 type, but kept valid in the wider mode. The signedness of the
1462 extension may differ from that of the type. */
1463
1464 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1465 if (GET_MODE_CLASS (MODE) == MODE_INT \
1466 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1467 { \
1468 if ((MODE) == SImode) \
1469 (UNSIGNEDP) = 0; \
1470 (MODE) = Pmode; \
1471 }
1472
1473 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1474 Extensions of pointers to word_mode must be signed. */
1475 #define POINTERS_EXTEND_UNSIGNED false
1476
1477 /* Define if loading short immediate values into registers sign extends. */
1478 #define SHORT_IMMEDIATES_SIGN_EXTEND
1479
1480 /* The [d]clz instructions have the natural values at 0. */
1481
1482 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1483 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1484 \f
1485 /* Standard register usage. */
1486
1487 /* Number of hardware registers. We have:
1488
1489 - 32 integer registers
1490 - 32 floating point registers
1491 - 8 condition code registers
1492 - 2 accumulator registers (hi and lo)
1493 - 32 registers each for coprocessors 0, 2 and 3
1494 - 4 fake registers:
1495 - ARG_POINTER_REGNUM
1496 - FRAME_POINTER_REGNUM
1497 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1498 - CPRESTORE_SLOT_REGNUM
1499 - 2 dummy entries that were used at various times in the past.
1500 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1501 - 6 DSP control registers */
1502
1503 #define FIRST_PSEUDO_REGISTER 188
1504
1505 /* By default, fix the kernel registers ($26 and $27), the global
1506 pointer ($28) and the stack pointer ($29). This can change
1507 depending on the command-line options.
1508
1509 Regarding coprocessor registers: without evidence to the contrary,
1510 it's best to assume that each coprocessor register has a unique
1511 use. This can be overridden, in, e.g., mips_option_override or
1512 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1513 inappropriate for a particular target. */
1514
1515 #define FIXED_REGISTERS \
1516 { \
1517 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1518 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1520 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1521 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1522 /* COP0 registers */ \
1523 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1524 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1525 /* COP2 registers */ \
1526 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1527 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1528 /* COP3 registers */ \
1529 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1530 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1531 /* 6 DSP accumulator registers & 6 control registers */ \
1532 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1533 }
1534
1535
1536 /* Set up this array for o32 by default.
1537
1538 Note that we don't mark $31 as a call-clobbered register. The idea is
1539 that it's really the call instructions themselves which clobber $31.
1540 We don't care what the called function does with it afterwards.
1541
1542 This approach makes it easier to implement sibcalls. Unlike normal
1543 calls, sibcalls don't clobber $31, so the register reaches the
1544 called function in tact. EPILOGUE_USES says that $31 is useful
1545 to the called function. */
1546
1547 #define CALL_USED_REGISTERS \
1548 { \
1549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1550 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1551 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1552 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1553 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1554 /* COP0 registers */ \
1555 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1557 /* COP2 registers */ \
1558 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1559 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1560 /* COP3 registers */ \
1561 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1562 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1563 /* 6 DSP accumulator registers & 6 control registers */ \
1564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1565 }
1566
1567
1568 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1569
1570 #define CALL_REALLY_USED_REGISTERS \
1571 { /* General registers. */ \
1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1573 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1574 /* Floating-point registers. */ \
1575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1576 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1577 /* Others. */ \
1578 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1579 /* COP0 registers */ \
1580 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1581 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1582 /* COP2 registers */ \
1583 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1584 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1585 /* COP3 registers */ \
1586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1588 /* 6 DSP accumulator registers & 6 control registers */ \
1589 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1590 }
1591
1592 /* Internal macros to classify a register number as to whether it's a
1593 general purpose register, a floating point register, a
1594 multiply/divide register, or a status register. */
1595
1596 #define GP_REG_FIRST 0
1597 #define GP_REG_LAST 31
1598 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1599 #define GP_DBX_FIRST 0
1600 #define K0_REG_NUM (GP_REG_FIRST + 26)
1601 #define K1_REG_NUM (GP_REG_FIRST + 27)
1602 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1603
1604 #define FP_REG_FIRST 32
1605 #define FP_REG_LAST 63
1606 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1607 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1608
1609 #define MD_REG_FIRST 64
1610 #define MD_REG_LAST 65
1611 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1612 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1613
1614 /* The DWARF 2 CFA column which tracks the return address from a
1615 signal handler context. This means that to maintain backwards
1616 compatibility, no hard register can be assigned this column if it
1617 would need to be handled by the DWARF unwinder. */
1618 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1619
1620 #define ST_REG_FIRST 67
1621 #define ST_REG_LAST 74
1622 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1623
1624
1625 /* FIXME: renumber. */
1626 #define COP0_REG_FIRST 80
1627 #define COP0_REG_LAST 111
1628 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1629
1630 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1631 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1632 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1633
1634 #define COP2_REG_FIRST 112
1635 #define COP2_REG_LAST 143
1636 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1637
1638 #define COP3_REG_FIRST 144
1639 #define COP3_REG_LAST 175
1640 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1641
1642 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1643 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1644 #define ALL_COP_REG_LAST COP3_REG_LAST
1645 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1646
1647 #define DSP_ACC_REG_FIRST 176
1648 #define DSP_ACC_REG_LAST 181
1649 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1650
1651 #define AT_REGNUM (GP_REG_FIRST + 1)
1652 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1653 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1654
1655 /* A few bitfield locations for the coprocessor registers. */
1656 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1657 the cause register for the EIC interrupt mode. */
1658 #define CAUSE_IPL 10
1659 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1660 #define SR_IPL 10
1661 /* Exception Level is at bit 1 of the status register. */
1662 #define SR_EXL 1
1663 /* Interrupt Enable is at bit 0 of the status register. */
1664 #define SR_IE 0
1665
1666 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1667 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1668 should be used instead. */
1669 #define FPSW_REGNUM ST_REG_FIRST
1670
1671 #define GP_REG_P(REGNO) \
1672 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1673 #define M16_REG_P(REGNO) \
1674 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1675 #define FP_REG_P(REGNO) \
1676 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1677 #define MD_REG_P(REGNO) \
1678 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1679 #define ST_REG_P(REGNO) \
1680 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1681 #define COP0_REG_P(REGNO) \
1682 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1683 #define COP2_REG_P(REGNO) \
1684 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1685 #define COP3_REG_P(REGNO) \
1686 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1687 #define ALL_COP_REG_P(REGNO) \
1688 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1689 /* Test if REGNO is one of the 6 new DSP accumulators. */
1690 #define DSP_ACC_REG_P(REGNO) \
1691 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1692 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1693 #define ACC_REG_P(REGNO) \
1694 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1695
1696 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1697
1698 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1699 to initialize the mips16 gp pseudo register. */
1700 #define CONST_GP_P(X) \
1701 (GET_CODE (X) == CONST \
1702 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1703 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1704
1705 /* Return coprocessor number from register number. */
1706
1707 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1708 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1709 : COP3_REG_P (REGNO) ? '3' : '?')
1710
1711
1712 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1713
1714 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1715 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1716
1717 #define MODES_TIEABLE_P mips_modes_tieable_p
1718
1719 /* Register to use for pushing function arguments. */
1720 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1721
1722 /* These two registers don't really exist: they get eliminated to either
1723 the stack or hard frame pointer. */
1724 #define ARG_POINTER_REGNUM 77
1725 #define FRAME_POINTER_REGNUM 78
1726
1727 /* $30 is not available on the mips16, so we use $17 as the frame
1728 pointer. */
1729 #define HARD_FRAME_POINTER_REGNUM \
1730 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1731
1732 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1733 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1734
1735 /* Register in which static-chain is passed to a function. */
1736 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1737
1738 /* Registers used as temporaries in prologue/epilogue code:
1739
1740 - If a MIPS16 PIC function needs access to _gp, it first loads
1741 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1742
1743 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1744 register. The register must not conflict with MIPS16_PIC_TEMP.
1745
1746 - If we aren't generating MIPS16 code, the prologue can also use
1747 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1748
1749 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1750 register.
1751
1752 If we're generating MIPS16 code, these registers must come from the
1753 core set of 8. The prologue registers mustn't conflict with any
1754 incoming arguments, the static chain pointer, or the frame pointer.
1755 The epilogue temporary mustn't conflict with the return registers,
1756 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1757 or the EH data registers.
1758
1759 If we're generating interrupt handlers, we use K0 as a temporary register
1760 in prologue/epilogue code. */
1761
1762 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1763 #define MIPS_PROLOGUE_TEMP_REGNUM \
1764 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1765 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1766 (TARGET_MIPS16 \
1767 ? (gcc_unreachable (), INVALID_REGNUM) \
1768 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1769 #define MIPS_EPILOGUE_TEMP_REGNUM \
1770 (cfun->machine->interrupt_handler_p \
1771 ? K0_REG_NUM \
1772 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1773
1774 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1775 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1776 #define MIPS_PROLOGUE_TEMP2(MODE) \
1777 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1778 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1779
1780 /* Define this macro if it is as good or better to call a constant
1781 function address than to call an address kept in a register. */
1782 #define NO_FUNCTION_CSE 1
1783
1784 /* The ABI-defined global pointer. Sometimes we use a different
1785 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1786 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1787
1788 /* We normally use $28 as the global pointer. However, when generating
1789 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1790 register instead. They can then avoid saving and restoring $28
1791 and perhaps avoid using a frame at all.
1792
1793 When a leaf function uses something other than $28, mips_expand_prologue
1794 will modify pic_offset_table_rtx in place. Take the register number
1795 from there after reload. */
1796 #define PIC_OFFSET_TABLE_REGNUM \
1797 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1798 \f
1799 /* Define the classes of registers for register constraints in the
1800 machine description. Also define ranges of constants.
1801
1802 One of the classes must always be named ALL_REGS and include all hard regs.
1803 If there is more than one class, another class must be named NO_REGS
1804 and contain no registers.
1805
1806 The name GENERAL_REGS must be the name of a class (or an alias for
1807 another name such as ALL_REGS). This is the class of registers
1808 that is allowed by "g" or "r" in a register constraint.
1809 Also, registers outside this class are allocated only when
1810 instructions express preferences for them.
1811
1812 The classes must be numbered in nondecreasing order; that is,
1813 a larger-numbered class must never be contained completely
1814 in a smaller-numbered class.
1815
1816 For any two classes, it is very desirable that there be another
1817 class that represents their union. */
1818
1819 enum reg_class
1820 {
1821 NO_REGS, /* no registers in set */
1822 M16_REGS, /* mips16 directly accessible registers */
1823 T_REG, /* mips16 T register ($24) */
1824 M16_T_REGS, /* mips16 registers plus T register */
1825 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1826 V1_REG, /* Register $v1 ($3) used for TLS access. */
1827 LEA_REGS, /* Every GPR except $25 */
1828 GR_REGS, /* integer registers */
1829 FP_REGS, /* floating point registers */
1830 MD0_REG, /* first multiply/divide register */
1831 MD1_REG, /* second multiply/divide register */
1832 MD_REGS, /* multiply/divide registers (hi/lo) */
1833 COP0_REGS, /* generic coprocessor classes */
1834 COP2_REGS,
1835 COP3_REGS,
1836 ST_REGS, /* status registers (fp status) */
1837 DSP_ACC_REGS, /* DSP accumulator registers */
1838 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1839 FRAME_REGS, /* $arg and $frame */
1840 GR_AND_MD0_REGS, /* union classes */
1841 GR_AND_MD1_REGS,
1842 GR_AND_MD_REGS,
1843 GR_AND_ACC_REGS,
1844 ALL_REGS, /* all registers */
1845 LIM_REG_CLASSES /* max value + 1 */
1846 };
1847
1848 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1849
1850 #define GENERAL_REGS GR_REGS
1851
1852 /* An initializer containing the names of the register classes as C
1853 string constants. These names are used in writing some of the
1854 debugging dumps. */
1855
1856 #define REG_CLASS_NAMES \
1857 { \
1858 "NO_REGS", \
1859 "M16_REGS", \
1860 "T_REG", \
1861 "M16_T_REGS", \
1862 "PIC_FN_ADDR_REG", \
1863 "V1_REG", \
1864 "LEA_REGS", \
1865 "GR_REGS", \
1866 "FP_REGS", \
1867 "MD0_REG", \
1868 "MD1_REG", \
1869 "MD_REGS", \
1870 /* coprocessor registers */ \
1871 "COP0_REGS", \
1872 "COP2_REGS", \
1873 "COP3_REGS", \
1874 "ST_REGS", \
1875 "DSP_ACC_REGS", \
1876 "ACC_REGS", \
1877 "FRAME_REGS", \
1878 "GR_AND_MD0_REGS", \
1879 "GR_AND_MD1_REGS", \
1880 "GR_AND_MD_REGS", \
1881 "GR_AND_ACC_REGS", \
1882 "ALL_REGS" \
1883 }
1884
1885 /* An initializer containing the contents of the register classes,
1886 as integers which are bit masks. The Nth integer specifies the
1887 contents of class N. The way the integer MASK is interpreted is
1888 that register R is in the class if `MASK & (1 << R)' is 1.
1889
1890 When the machine has more than 32 registers, an integer does not
1891 suffice. Then the integers are replaced by sub-initializers,
1892 braced groupings containing several integers. Each
1893 sub-initializer must be suitable as an initializer for the type
1894 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1895
1896 #define REG_CLASS_CONTENTS \
1897 { \
1898 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1899 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1900 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1901 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1902 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1903 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1904 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1905 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1906 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1907 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1908 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1909 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1910 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1911 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1912 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1913 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1914 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1915 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1916 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1917 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1918 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1919 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1920 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1921 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1922 }
1923
1924
1925 /* A C expression whose value is a register class containing hard
1926 register REGNO. In general there is more that one such class;
1927 choose a class which is "minimal", meaning that no smaller class
1928 also contains the register. */
1929
1930 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1931
1932 /* A macro whose definition is the name of the class to which a
1933 valid base register must belong. A base register is one used in
1934 an address which is the register value plus a displacement. */
1935
1936 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1937
1938 /* A macro whose definition is the name of the class to which a
1939 valid index register must belong. An index register is one used
1940 in an address where its value is either multiplied by a scale
1941 factor or added to another register (as well as added to a
1942 displacement). */
1943
1944 #define INDEX_REG_CLASS NO_REGS
1945
1946 /* We generally want to put call-clobbered registers ahead of
1947 call-saved ones. (IRA expects this.) */
1948
1949 #define REG_ALLOC_ORDER \
1950 { /* Accumulator registers. When GPRs and accumulators have equal \
1951 cost, we generally prefer to use accumulators. For example, \
1952 a division of multiplication result is better allocated to LO, \
1953 so that we put the MFLO at the point of use instead of at the \
1954 point of definition. It's also needed if we're to take advantage \
1955 of the extra accumulators available with -mdspr2. In some cases, \
1956 it can also help to reduce register pressure. */ \
1957 64, 65,176,177,178,179,180,181, \
1958 /* Call-clobbered GPRs. */ \
1959 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1960 24, 25, 31, \
1961 /* The global pointer. This is call-clobbered for o32 and o64 \
1962 abicalls, call-saved for n32 and n64 abicalls, and a program \
1963 invariant otherwise. Putting it between the call-clobbered \
1964 and call-saved registers should cope with all eventualities. */ \
1965 28, \
1966 /* Call-saved GPRs. */ \
1967 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1968 /* GPRs that can never be exposed to the register allocator. */ \
1969 0, 26, 27, 29, \
1970 /* Call-clobbered FPRs. */ \
1971 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1972 48, 49, 50, 51, \
1973 /* FPRs that are usually call-saved. The odd ones are actually \
1974 call-clobbered for n32, but listing them ahead of the even \
1975 registers might encourage the register allocator to fragment \
1976 the available FPR pairs. We need paired FPRs to store long \
1977 doubles, so it isn't clear that using a different order \
1978 for n32 would be a win. */ \
1979 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1980 /* None of the remaining classes have defined call-saved \
1981 registers. */ \
1982 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1983 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1984 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1985 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1986 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1987 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1988 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1989 182,183,184,185,186,187 \
1990 }
1991
1992 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1993 to be rearranged based on a particular function. On the mips16, we
1994 want to allocate $24 (T_REG) before other registers for
1995 instructions for which it is possible. */
1996
1997 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
1998
1999 /* True if VALUE is an unsigned 6-bit number. */
2000
2001 #define UIMM6_OPERAND(VALUE) \
2002 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2003
2004 /* True if VALUE is a signed 10-bit number. */
2005
2006 #define IMM10_OPERAND(VALUE) \
2007 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2008
2009 /* True if VALUE is a signed 16-bit number. */
2010
2011 #define SMALL_OPERAND(VALUE) \
2012 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2013
2014 /* True if VALUE is an unsigned 16-bit number. */
2015
2016 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2017 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2018
2019 /* True if VALUE can be loaded into a register using LUI. */
2020
2021 #define LUI_OPERAND(VALUE) \
2022 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2023 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2024
2025 /* Return a value X with the low 16 bits clear, and such that
2026 VALUE - X is a signed 16-bit value. */
2027
2028 #define CONST_HIGH_PART(VALUE) \
2029 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2030
2031 #define CONST_LOW_PART(VALUE) \
2032 ((VALUE) - CONST_HIGH_PART (VALUE))
2033
2034 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2035 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2036 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2037
2038 /* The HI and LO registers can only be reloaded via the general
2039 registers. Condition code registers can only be loaded to the
2040 general registers, and from the floating point registers. */
2041
2042 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2043 mips_secondary_reload_class (CLASS, MODE, X, true)
2044 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2045 mips_secondary_reload_class (CLASS, MODE, X, false)
2046
2047 /* Return the maximum number of consecutive registers
2048 needed to represent mode MODE in a register of class CLASS. */
2049
2050 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2051
2052 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2053 mips_cannot_change_mode_class (FROM, TO, CLASS)
2054 \f
2055 /* Stack layout; function entry, exit and calling. */
2056
2057 #define STACK_GROWS_DOWNWARD
2058
2059 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2060
2061 /* Size of the area allocated in the frame to save the GP. */
2062
2063 #define MIPS_GP_SAVE_AREA_SIZE \
2064 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2065
2066 /* The offset of the first local variable from the frame pointer. See
2067 mips_compute_frame_info for details about the frame layout. */
2068
2069 #define STARTING_FRAME_OFFSET \
2070 (FRAME_GROWS_DOWNWARD \
2071 ? 0 \
2072 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2073
2074 #define RETURN_ADDR_RTX mips_return_addr
2075
2076 /* Mask off the MIPS16 ISA bit in unwind addresses.
2077
2078 The reason for this is a little subtle. When unwinding a call,
2079 we are given the call's return address, which on most targets
2080 is the address of the following instruction. However, what we
2081 actually want to find is the EH region for the call itself.
2082 The target-independent unwind code therefore searches for "RA - 1".
2083
2084 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2085 RA - 1 is therefore the real (even-valued) start of the return
2086 instruction. EH region labels are usually odd-valued MIPS16 symbols
2087 too, so a search for an even address within a MIPS16 region would
2088 usually work.
2089
2090 However, there is an exception. If the end of an EH region is also
2091 the end of a function, the end label is allowed to be even. This is
2092 necessary because a following non-MIPS16 function may also need EH
2093 information for its first instruction.
2094
2095 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2096 non-ISA-encoded address. This probably isn't ideal, but it is
2097 the traditional (legacy) behavior. It is therefore only safe
2098 to search MIPS EH regions for an _odd-valued_ address.
2099
2100 Masking off the ISA bit means that the target-independent code
2101 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2102 #define MASK_RETURN_ADDR GEN_INT (-2)
2103
2104
2105 /* Similarly, don't use the least-significant bit to tell pointers to
2106 code from vtable index. */
2107
2108 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2109
2110 /* The eliminations to $17 are only used for mips16 code. See the
2111 definition of HARD_FRAME_POINTER_REGNUM. */
2112
2113 #define ELIMINABLE_REGS \
2114 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2115 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2116 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2117 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2118 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2119 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2120
2121 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2122 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2123
2124 /* Allocate stack space for arguments at the beginning of each function. */
2125 #define ACCUMULATE_OUTGOING_ARGS 1
2126
2127 /* The argument pointer always points to the first argument. */
2128 #define FIRST_PARM_OFFSET(FNDECL) 0
2129
2130 /* o32 and o64 reserve stack space for all argument registers. */
2131 #define REG_PARM_STACK_SPACE(FNDECL) \
2132 (TARGET_OLDABI \
2133 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2134 : 0)
2135
2136 /* Define this if it is the responsibility of the caller to
2137 allocate the area reserved for arguments passed in registers.
2138 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2139 of this macro is to determine whether the space is included in
2140 `crtl->outgoing_args_size'. */
2141 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2142
2143 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2144 \f
2145 /* Symbolic macros for the registers used to return integer and floating
2146 point values. */
2147
2148 #define GP_RETURN (GP_REG_FIRST + 2)
2149 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2150
2151 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2152
2153 /* Symbolic macros for the first/last argument registers. */
2154
2155 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2156 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2157 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2158 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2159
2160 /* 1 if N is a possible register number for function argument passing.
2161 We have no FP argument registers when soft-float. When FP registers
2162 are 32 bits, we can't directly reference the odd numbered ones. */
2163
2164 #define FUNCTION_ARG_REGNO_P(N) \
2165 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2166 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2167 && !fixed_regs[N])
2168 \f
2169 /* This structure has to cope with two different argument allocation
2170 schemes. Most MIPS ABIs view the arguments as a structure, of which
2171 the first N words go in registers and the rest go on the stack. If I
2172 < N, the Ith word might go in Ith integer argument register or in a
2173 floating-point register. For these ABIs, we only need to remember
2174 the offset of the current argument into the structure.
2175
2176 The EABI instead allocates the integer and floating-point arguments
2177 separately. The first N words of FP arguments go in FP registers,
2178 the rest go on the stack. Likewise, the first N words of the other
2179 arguments go in integer registers, and the rest go on the stack. We
2180 need to maintain three counts: the number of integer registers used,
2181 the number of floating-point registers used, and the number of words
2182 passed on the stack.
2183
2184 We could keep separate information for the two ABIs (a word count for
2185 the standard ABIs, and three separate counts for the EABI). But it
2186 seems simpler to view the standard ABIs as forms of EABI that do not
2187 allocate floating-point registers.
2188
2189 So for the standard ABIs, the first N words are allocated to integer
2190 registers, and mips_function_arg decides on an argument-by-argument
2191 basis whether that argument should really go in an integer register,
2192 or in a floating-point one. */
2193
2194 typedef struct mips_args {
2195 /* Always true for varargs functions. Otherwise true if at least
2196 one argument has been passed in an integer register. */
2197 int gp_reg_found;
2198
2199 /* The number of arguments seen so far. */
2200 unsigned int arg_number;
2201
2202 /* The number of integer registers used so far. For all ABIs except
2203 EABI, this is the number of words that have been added to the
2204 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2205 unsigned int num_gprs;
2206
2207 /* For EABI, the number of floating-point registers used so far. */
2208 unsigned int num_fprs;
2209
2210 /* The number of words passed on the stack. */
2211 unsigned int stack_words;
2212
2213 /* On the mips16, we need to keep track of which floating point
2214 arguments were passed in general registers, but would have been
2215 passed in the FP regs if this were a 32-bit function, so that we
2216 can move them to the FP regs if we wind up calling a 32-bit
2217 function. We record this information in fp_code, encoded in base
2218 four. A zero digit means no floating point argument, a one digit
2219 means an SFmode argument, and a two digit means a DFmode argument,
2220 and a three digit is not used. The low order digit is the first
2221 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2222 an SFmode argument. ??? A more sophisticated approach will be
2223 needed if MIPS_ABI != ABI_32. */
2224 int fp_code;
2225
2226 /* True if the function has a prototype. */
2227 int prototype;
2228 } CUMULATIVE_ARGS;
2229
2230 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2231 for a call to a function whose data type is FNTYPE.
2232 For a library call, FNTYPE is 0. */
2233
2234 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2235 mips_init_cumulative_args (&CUM, FNTYPE)
2236
2237 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2238 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2239
2240 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2241 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2242
2243 /* True if using EABI and varargs can be passed in floating-point
2244 registers. Under these conditions, we need a more complex form
2245 of va_list, which tracks GPR, FPR and stack arguments separately. */
2246 #define EABI_FLOAT_VARARGS_P \
2247 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2248
2249 \f
2250 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2251
2252 /* Treat LOC as a byte offset from the stack pointer and round it up
2253 to the next fully-aligned offset. */
2254 #define MIPS_STACK_ALIGN(LOC) \
2255 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2256
2257 \f
2258 /* Output assembler code to FILE to increment profiler label # LABELNO
2259 for profiling a function entry. */
2260
2261 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2262
2263 /* The profiler preserves all interesting registers, including $31. */
2264 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2265
2266 /* No mips port has ever used the profiler counter word, so don't emit it
2267 or the label for it. */
2268
2269 #define NO_PROFILE_COUNTERS 1
2270
2271 /* Define this macro if the code for function profiling should come
2272 before the function prologue. Normally, the profiling code comes
2273 after. */
2274
2275 /* #define PROFILE_BEFORE_PROLOGUE */
2276
2277 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2278 the stack pointer does not matter. The value is tested only in
2279 functions that have frame pointers.
2280 No definition is equivalent to always zero. */
2281
2282 #define EXIT_IGNORE_STACK 1
2283
2284 \f
2285 /* Trampolines are a block of code followed by two pointers. */
2286
2287 #define TRAMPOLINE_SIZE \
2288 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2289
2290 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2291 pointers from a single LUI base. */
2292
2293 #define TRAMPOLINE_ALIGNMENT 64
2294
2295 /* mips_trampoline_init calls this library function to flush
2296 program and data caches. */
2297
2298 #ifndef CACHE_FLUSH_FUNC
2299 #define CACHE_FLUSH_FUNC "_flush_cache"
2300 #endif
2301
2302 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2303 /* Flush both caches. We need to flush the data cache in case \
2304 the system has a write-back cache. */ \
2305 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2306 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2307 GEN_INT (3), TYPE_MODE (integer_type_node))
2308
2309 \f
2310 /* Addressing modes, and classification of registers for them. */
2311
2312 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2313 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2314 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2315 \f
2316 /* Maximum number of registers that can appear in a valid memory address. */
2317
2318 #define MAX_REGS_PER_ADDRESS 1
2319
2320 /* Check for constness inline but use mips_legitimate_address_p
2321 to check whether a constant really is an address. */
2322
2323 #define CONSTANT_ADDRESS_P(X) \
2324 (CONSTANT_P (X) && memory_address_p (SImode, X))
2325
2326 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2327 'the start of the function that this code is output in'. */
2328
2329 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2330 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2331 asm_fprintf ((FILE), "%U%s", \
2332 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2333 else \
2334 asm_fprintf ((FILE), "%U%s", (NAME))
2335 \f
2336 /* Flag to mark a function decl symbol that requires a long call. */
2337 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2338 #define SYMBOL_REF_LONG_CALL_P(X) \
2339 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2340
2341 /* This flag marks functions that cannot be lazily bound. */
2342 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2343 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2344 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2345
2346 /* True if we're generating a form of MIPS16 code in which jump tables
2347 are stored in the text section and encoded as 16-bit PC-relative
2348 offsets. This is only possible when general text loads are allowed,
2349 since the table access itself will be an "lh" instruction. If the
2350 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2351 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2352
2353 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2354
2355 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2356
2357 /* Only use short offsets if their range will not overflow. */
2358 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2359 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2360 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2361 : SImode)
2362
2363 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2364
2365 /* Define this as 1 if `char' should by default be signed; else as 0. */
2366 #ifndef DEFAULT_SIGNED_CHAR
2367 #define DEFAULT_SIGNED_CHAR 1
2368 #endif
2369
2370 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2371 we generally don't want to use them for copying arbitrary data.
2372 A single N-word move is usually the same cost as N single-word moves. */
2373 #define MOVE_MAX UNITS_PER_WORD
2374 #define MAX_MOVE_MAX 8
2375
2376 /* Define this macro as a C expression which is nonzero if
2377 accessing less than a word of memory (i.e. a `char' or a
2378 `short') is no faster than accessing a word of memory, i.e., if
2379 such access require more than one instruction or if there is no
2380 difference in cost between byte and (aligned) word loads.
2381
2382 On RISC machines, it tends to generate better code to define
2383 this as 1, since it avoids making a QI or HI mode register.
2384
2385 But, generating word accesses for -mips16 is generally bad as shifts
2386 (often extended) would be needed for byte accesses. */
2387 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2388
2389 /* Standard MIPS integer shifts truncate the shift amount to the
2390 width of the shifted operand. However, Loongson vector shifts
2391 do not truncate the shift amount at all. */
2392 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2393
2394 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2395 is done just by pretending it is already truncated. */
2396 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2397 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2398
2399
2400 /* Specify the machine mode that pointers have.
2401 After generation of rtl, the compiler makes no further distinction
2402 between pointers and any other objects of this machine mode. */
2403
2404 #ifndef Pmode
2405 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2406 #endif
2407
2408 /* Give call MEMs SImode since it is the "most permissive" mode
2409 for both 32-bit and 64-bit targets. */
2410
2411 #define FUNCTION_MODE SImode
2412
2413 \f
2414 /* We allocate $fcc registers by hand and can't cope with moves of
2415 CCmode registers to and from pseudos (or memory). */
2416 #define AVOID_CCMODE_COPIES
2417
2418 /* A C expression for the cost of a branch instruction. A value of
2419 1 is the default; other values are interpreted relative to that. */
2420
2421 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2422 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2423
2424 /* If defined, modifies the length assigned to instruction INSN as a
2425 function of the context in which it is used. LENGTH is an lvalue
2426 that contains the initially computed length of the insn and should
2427 be updated with the correct length of the insn. */
2428 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2429 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2430
2431 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2432 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2433 its operands. */
2434 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2435 "%*" OPCODE "%?\t" OPERANDS "%/"
2436
2437 /* Return an asm string that forces INSN to be treated as an absolute
2438 J or JAL instruction instead of an assembler macro. */
2439 #define MIPS_ABSOLUTE_JUMP(INSN) \
2440 (TARGET_ABICALLS_PIC2 \
2441 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2442 : INSN)
2443
2444 /* Return the asm template for a call. INSN is the instruction's mnemonic
2445 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2446 number of the target. SIZE_OPNO is the operand number of the argument size
2447 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2448 -1 and the call is indirect, use the function symbol from the call
2449 attributes to attach a R_MIPS_JALR relocation to the call.
2450
2451 When generating GOT code without explicit relocation operators,
2452 all calls should use assembly macros. Otherwise, all indirect
2453 calls should use "jr" or "jalr"; we will arrange to restore $gp
2454 afterwards if necessary. Finally, we can only generate direct
2455 calls for -mabicalls by temporarily switching to non-PIC mode. */
2456 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2457 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2458 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2459 : (REG_P (OPERANDS[TARGET_OPNO]) \
2460 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2461 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2462 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2463 : REG_P (OPERANDS[TARGET_OPNO]) \
2464 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2465 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2466 \f
2467 /* Control the assembler format that we output. */
2468
2469 /* Output to assembler file text saying following lines
2470 may contain character constants, extra white space, comments, etc. */
2471
2472 #ifndef ASM_APP_ON
2473 #define ASM_APP_ON " #APP\n"
2474 #endif
2475
2476 /* Output to assembler file text saying following lines
2477 no longer contain unusual constructs. */
2478
2479 #ifndef ASM_APP_OFF
2480 #define ASM_APP_OFF " #NO_APP\n"
2481 #endif
2482
2483 #define REGISTER_NAMES \
2484 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2485 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2486 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2487 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2488 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2489 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2490 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2491 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2492 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2493 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2494 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2495 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2496 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2497 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2498 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2499 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2500 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2501 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2502 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2503 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2504 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2505 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2506 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2507 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2508
2509 /* List the "software" names for each register. Also list the numerical
2510 names for $fp and $sp. */
2511
2512 #define ADDITIONAL_REGISTER_NAMES \
2513 { \
2514 { "$29", 29 + GP_REG_FIRST }, \
2515 { "$30", 30 + GP_REG_FIRST }, \
2516 { "at", 1 + GP_REG_FIRST }, \
2517 { "v0", 2 + GP_REG_FIRST }, \
2518 { "v1", 3 + GP_REG_FIRST }, \
2519 { "a0", 4 + GP_REG_FIRST }, \
2520 { "a1", 5 + GP_REG_FIRST }, \
2521 { "a2", 6 + GP_REG_FIRST }, \
2522 { "a3", 7 + GP_REG_FIRST }, \
2523 { "t0", 8 + GP_REG_FIRST }, \
2524 { "t1", 9 + GP_REG_FIRST }, \
2525 { "t2", 10 + GP_REG_FIRST }, \
2526 { "t3", 11 + GP_REG_FIRST }, \
2527 { "t4", 12 + GP_REG_FIRST }, \
2528 { "t5", 13 + GP_REG_FIRST }, \
2529 { "t6", 14 + GP_REG_FIRST }, \
2530 { "t7", 15 + GP_REG_FIRST }, \
2531 { "s0", 16 + GP_REG_FIRST }, \
2532 { "s1", 17 + GP_REG_FIRST }, \
2533 { "s2", 18 + GP_REG_FIRST }, \
2534 { "s3", 19 + GP_REG_FIRST }, \
2535 { "s4", 20 + GP_REG_FIRST }, \
2536 { "s5", 21 + GP_REG_FIRST }, \
2537 { "s6", 22 + GP_REG_FIRST }, \
2538 { "s7", 23 + GP_REG_FIRST }, \
2539 { "t8", 24 + GP_REG_FIRST }, \
2540 { "t9", 25 + GP_REG_FIRST }, \
2541 { "k0", 26 + GP_REG_FIRST }, \
2542 { "k1", 27 + GP_REG_FIRST }, \
2543 { "gp", 28 + GP_REG_FIRST }, \
2544 { "sp", 29 + GP_REG_FIRST }, \
2545 { "fp", 30 + GP_REG_FIRST }, \
2546 { "ra", 31 + GP_REG_FIRST } \
2547 }
2548
2549 #define DBR_OUTPUT_SEQEND(STREAM) \
2550 do \
2551 { \
2552 /* Undo the effect of '%*'. */ \
2553 mips_pop_asm_switch (&mips_nomacro); \
2554 mips_pop_asm_switch (&mips_noreorder); \
2555 /* Emit a blank line after the delay slot for emphasis. */ \
2556 fputs ("\n", STREAM); \
2557 } \
2558 while (0)
2559
2560 /* The MIPS implementation uses some labels for its own purpose. The
2561 following lists what labels are created, and are all formed by the
2562 pattern $L[a-z].*. The machine independent portion of GCC creates
2563 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2564
2565 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2566 $Lb[0-9]+ Begin blocks for MIPS debug support
2567 $Lc[0-9]+ Label for use in s<xx> operation.
2568 $Le[0-9]+ End blocks for MIPS debug support */
2569
2570 #undef ASM_DECLARE_OBJECT_NAME
2571 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2572 mips_declare_object (STREAM, NAME, "", ":\n")
2573
2574 /* Globalizing directive for a label. */
2575 #define GLOBAL_ASM_OP "\t.globl\t"
2576
2577 /* This says how to define a global common symbol. */
2578
2579 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2580
2581 /* This says how to define a local common symbol (i.e., not visible to
2582 linker). */
2583
2584 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2585 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2586 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2587 #endif
2588
2589 /* This says how to output an external. It would be possible not to
2590 output anything and let undefined symbol become external. However
2591 the assembler uses length information on externals to allocate in
2592 data/sdata bss/sbss, thereby saving exec time. */
2593
2594 #undef ASM_OUTPUT_EXTERNAL
2595 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2596 mips_output_external(STREAM,DECL,NAME)
2597
2598 /* This is how to declare a function name. The actual work of
2599 emitting the label is moved to function_prologue, so that we can
2600 get the line number correctly emitted before the .ent directive,
2601 and after any .file directives. Define as empty so that the function
2602 is not declared before the .ent directive elsewhere. */
2603
2604 #undef ASM_DECLARE_FUNCTION_NAME
2605 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2606
2607 /* This is how to store into the string LABEL
2608 the symbol_ref name of an internal numbered label where
2609 PREFIX is the class of label and NUM is the number within the class.
2610 This is suitable for output with `assemble_name'. */
2611
2612 #undef ASM_GENERATE_INTERNAL_LABEL
2613 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2614 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2615
2616 /* Print debug labels as "foo = ." rather than "foo:" because they should
2617 represent a byte pointer rather than an ISA-encoded address. This is
2618 particularly important for code like:
2619
2620 $LFBxxx = .
2621 .cfi_startproc
2622 ...
2623 .section .gcc_except_table,...
2624 ...
2625 .uleb128 foo-$LFBxxx
2626
2627 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2628 likewise a byte pointer rather than an ISA-encoded address.
2629
2630 At the time of writing, this hook is not used for the function end
2631 label:
2632
2633 $LFExxx:
2634 .end foo
2635
2636 But this doesn't matter, because GAS doesn't treat a pre-.end label
2637 as a MIPS16 one anyway. */
2638
2639 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2640 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2641
2642 /* This is how to output an element of a case-vector that is absolute. */
2643
2644 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2645 fprintf (STREAM, "\t%s\t%sL%d\n", \
2646 ptr_mode == DImode ? ".dword" : ".word", \
2647 LOCAL_LABEL_PREFIX, \
2648 VALUE)
2649
2650 /* This is how to output an element of a case-vector. We can make the
2651 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2652 is supported. */
2653
2654 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2655 do { \
2656 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2657 { \
2658 if (GET_MODE (BODY) == HImode) \
2659 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2660 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2661 else \
2662 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2663 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2664 } \
2665 else if (TARGET_GPWORD) \
2666 fprintf (STREAM, "\t%s\t%sL%d\n", \
2667 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2668 LOCAL_LABEL_PREFIX, VALUE); \
2669 else if (TARGET_RTP_PIC) \
2670 { \
2671 /* Make the entry relative to the start of the function. */ \
2672 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2673 fprintf (STREAM, "\t%s\t%sL%d-", \
2674 Pmode == DImode ? ".dword" : ".word", \
2675 LOCAL_LABEL_PREFIX, VALUE); \
2676 assemble_name (STREAM, XSTR (fnsym, 0)); \
2677 fprintf (STREAM, "\n"); \
2678 } \
2679 else \
2680 fprintf (STREAM, "\t%s\t%sL%d\n", \
2681 ptr_mode == DImode ? ".dword" : ".word", \
2682 LOCAL_LABEL_PREFIX, VALUE); \
2683 } while (0)
2684
2685 /* This is how to output an assembler line
2686 that says to advance the location counter
2687 to a multiple of 2**LOG bytes. */
2688
2689 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2690 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2691
2692 /* This is how to output an assembler line to advance the location
2693 counter by SIZE bytes. */
2694
2695 #undef ASM_OUTPUT_SKIP
2696 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2697 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2698
2699 /* This is how to output a string. */
2700 #undef ASM_OUTPUT_ASCII
2701 #define ASM_OUTPUT_ASCII mips_output_ascii
2702
2703 \f
2704 /* Default to -G 8 */
2705 #ifndef MIPS_DEFAULT_GVALUE
2706 #define MIPS_DEFAULT_GVALUE 8
2707 #endif
2708
2709 /* Define the strings to put out for each section in the object file. */
2710 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2711 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2712
2713 #undef READONLY_DATA_SECTION_ASM_OP
2714 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2715 \f
2716 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2717 do \
2718 { \
2719 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2720 TARGET_64BIT ? "daddiu" : "addiu", \
2721 reg_names[STACK_POINTER_REGNUM], \
2722 reg_names[STACK_POINTER_REGNUM], \
2723 TARGET_64BIT ? "sd" : "sw", \
2724 reg_names[REGNO], \
2725 reg_names[STACK_POINTER_REGNUM]); \
2726 } \
2727 while (0)
2728
2729 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2730 do \
2731 { \
2732 mips_push_asm_switch (&mips_noreorder); \
2733 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2734 TARGET_64BIT ? "ld" : "lw", \
2735 reg_names[REGNO], \
2736 reg_names[STACK_POINTER_REGNUM], \
2737 TARGET_64BIT ? "daddu" : "addu", \
2738 reg_names[STACK_POINTER_REGNUM], \
2739 reg_names[STACK_POINTER_REGNUM]); \
2740 mips_pop_asm_switch (&mips_noreorder); \
2741 } \
2742 while (0)
2743
2744 /* How to start an assembler comment.
2745 The leading space is important (the mips native assembler requires it). */
2746 #ifndef ASM_COMMENT_START
2747 #define ASM_COMMENT_START " #"
2748 #endif
2749 \f
2750 #undef SIZE_TYPE
2751 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2752
2753 #undef PTRDIFF_TYPE
2754 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2755
2756 /* The maximum number of bytes that can be copied by one iteration of
2757 a movmemsi loop; see mips_block_move_loop. */
2758 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2759 (UNITS_PER_WORD * 4)
2760
2761 /* The maximum number of bytes that can be copied by a straight-line
2762 implementation of movmemsi; see mips_block_move_straight. We want
2763 to make sure that any loop-based implementation will iterate at
2764 least twice. */
2765 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2766 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2767
2768 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2769 values were determined experimentally by benchmarking with CSiBE.
2770 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2771 for o32 where we have to restore $gp afterwards as well as make an
2772 indirect call), but in practice, bumping this up higher for
2773 TARGET_ABICALLS doesn't make much difference to code size. */
2774
2775 #define MIPS_CALL_RATIO 8
2776
2777 /* Any loop-based implementation of movmemsi will have at least
2778 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2779 moves, so allow individual copies of fewer elements.
2780
2781 When movmemsi is not available, use a value approximating
2782 the length of a memcpy call sequence, so that move_by_pieces
2783 will generate inline code if it is shorter than a function call.
2784 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2785 we'll have to generate a load/store pair for each, halve the
2786 value of MIPS_CALL_RATIO to take that into account. */
2787
2788 #define MOVE_RATIO(speed) \
2789 (HAVE_movmemsi \
2790 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2791 : MIPS_CALL_RATIO / 2)
2792
2793 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2794 mips_move_by_pieces_p (SIZE, ALIGN)
2795
2796 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2797 of the length of a memset call, but use the default otherwise. */
2798
2799 #define CLEAR_RATIO(speed)\
2800 ((speed) ? 15 : MIPS_CALL_RATIO)
2801
2802 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2803 optimizing for size adjust the ratio to account for the overhead of
2804 loading the constant and replicating it across the word. */
2805
2806 #define SET_RATIO(speed) \
2807 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2808
2809 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2810 mips_store_by_pieces_p (SIZE, ALIGN)
2811 \f
2812 /* Since the bits of the _init and _fini function is spread across
2813 many object files, each potentially with its own GP, we must assume
2814 we need to load our GP. We don't preserve $gp or $ra, since each
2815 init/fini chunk is supposed to initialize $gp, and crti/crtn
2816 already take care of preserving $ra and, when appropriate, $gp. */
2817 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2818 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2819 asm (SECTION_OP "\n\
2820 .set push\n\
2821 .set nomips16\n\
2822 .set noreorder\n\
2823 bal 1f\n\
2824 nop\n\
2825 1: .cpload $31\n\
2826 .set reorder\n\
2827 jal " USER_LABEL_PREFIX #FUNC "\n\
2828 .set pop\n\
2829 " TEXT_SECTION_ASM_OP);
2830 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2831 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2832 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2833 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2834 asm (SECTION_OP "\n\
2835 .set push\n\
2836 .set nomips16\n\
2837 .set noreorder\n\
2838 bal 1f\n\
2839 nop\n\
2840 1: .set reorder\n\
2841 .cpsetup $31, $2, 1b\n\
2842 jal " USER_LABEL_PREFIX #FUNC "\n\
2843 .set pop\n\
2844 " TEXT_SECTION_ASM_OP);
2845 #endif
2846
2847 #ifndef HAVE_AS_TLS
2848 #define HAVE_AS_TLS 0
2849 #endif
2850
2851 #ifndef USED_FOR_TARGET
2852 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2853 struct mips_asm_switch {
2854 /* The FOO in the description above. */
2855 const char *name;
2856
2857 /* The current block nesting level, or 0 if we aren't in a block. */
2858 int nesting_level;
2859 };
2860
2861 extern const enum reg_class mips_regno_to_class[];
2862 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2863 extern const char *current_function_file; /* filename current function is in */
2864 extern int num_source_filenames; /* current .file # */
2865 extern struct mips_asm_switch mips_noreorder;
2866 extern struct mips_asm_switch mips_nomacro;
2867 extern struct mips_asm_switch mips_noat;
2868 extern int mips_dbx_regno[];
2869 extern int mips_dwarf_regno[];
2870 extern bool mips_split_p[];
2871 extern bool mips_split_hi_p[];
2872 extern bool mips_use_pcrel_pool_p[];
2873 extern const char *mips_lo_relocs[];
2874 extern const char *mips_hi_relocs[];
2875 extern enum processor mips_arch; /* which cpu to codegen for */
2876 extern enum processor mips_tune; /* which cpu to schedule for */
2877 extern int mips_isa; /* architectural level */
2878 extern const struct mips_cpu_info *mips_arch_info;
2879 extern const struct mips_cpu_info *mips_tune_info;
2880 extern bool mips_base_mips16;
2881 extern GTY(()) struct target_globals *mips16_globals;
2882 #endif
2883
2884 /* Enable querying of DFA units. */
2885 #define CPU_UNITS_QUERY 1
2886
2887 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2888 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2889
2890 /* As on most targets, we want the .eh_frame section to be read-only where
2891 possible. And as on most targets, this means two things:
2892
2893 (a) Non-locally-binding pointers must have an indirect encoding,
2894 so that the addresses in the .eh_frame section itself become
2895 locally-binding.
2896
2897 (b) A shared library's .eh_frame section must encode locally-binding
2898 pointers in a relative (relocation-free) form.
2899
2900 However, MIPS has traditionally not allowed directives like:
2901
2902 .long x-.
2903
2904 in cases where "x" is in a different section, or is not defined in the
2905 same assembly file. We are therefore unable to emit the PC-relative
2906 form required by (b) at assembly time.
2907
2908 Fortunately, the linker is able to convert absolute addresses into
2909 PC-relative addresses on our behalf. Unfortunately, only certain
2910 versions of the linker know how to do this for indirect pointers,
2911 and for personality data. We must fall back on using writable
2912 .eh_frame sections for shared libraries if the linker does not
2913 support this feature. */
2914 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2915 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2916
2917 /* For switching between MIPS16 and non-MIPS16 modes. */
2918 #define SWITCHABLE_TARGET 1
2919
2920 /* Several named MIPS patterns depend on Pmode. These patterns have the
2921 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2922 Add the appropriate suffix to generator function NAME and invoke it
2923 with arguments ARGS. */
2924 #define PMODE_INSN(NAME, ARGS) \
2925 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)