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gcc_update (gcc/config/mips/mips-tables.opt): New dependencies.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 #ifdef GENERATOR_FILE
30 /* This is used in some insn conditions, so needs to be declared, but
31 does not need to be defined. */
32 extern int target_flags_explicit;
33 #endif
34
35 /* MIPS external variables defined in mips.c. */
36
37 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
38 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
39 to work on a 64-bit machine. */
40
41 #define ABI_32 0
42 #define ABI_N32 1
43 #define ABI_64 2
44 #define ABI_EABI 3
45 #define ABI_O64 4
46
47 /* Masks that affect tuning.
48
49 PTF_AVOID_BRANCHLIKELY
50 Set if it is usually not profitable to use branch-likely instructions
51 for this target, typically because the branches are always predicted
52 taken and so incur a large overhead when not taken. */
53 #define PTF_AVOID_BRANCHLIKELY 0x1
54
55 /* Information about one recognized processor. Defined here for the
56 benefit of TARGET_CPU_CPP_BUILTINS. */
57 struct mips_cpu_info {
58 /* The 'canonical' name of the processor as far as GCC is concerned.
59 It's typically a manufacturer's prefix followed by a numerical
60 designation. It should be lowercase. */
61 const char *name;
62
63 /* The internal processor number that most closely matches this
64 entry. Several processors can have the same value, if there's no
65 difference between them from GCC's point of view. */
66 enum processor cpu;
67
68 /* The ISA level that the processor implements. */
69 int isa;
70
71 /* A mask of PTF_* values. */
72 unsigned int tune_flags;
73 };
74
75 #include "config/mips/mips-opts.h"
76
77 /* Macros to silence warnings about numbers being signed in traditional
78 C and unsigned in ISO C when compiled on 32-bit hosts. */
79
80 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
81 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
82 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
83
84 \f
85 /* Run-time compilation parameters selecting different hardware subsets. */
86
87 /* True if we are generating position-independent VxWorks RTP code. */
88 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
89
90 /* True if the output file is marked as ".abicalls; .option pic0"
91 (-call_nonpic). */
92 #define TARGET_ABICALLS_PIC0 \
93 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
94
95 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
96 #define TARGET_ABICALLS_PIC2 \
97 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
98
99 /* True if the call patterns should be split into a jalr followed by
100 an instruction to restore $gp. It is only safe to split the load
101 from the call when every use of $gp is explicit.
102
103 See mips_must_initialize_gp_p for details about how we manage the
104 global pointer. */
105
106 #define TARGET_SPLIT_CALLS \
107 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
108
109 /* True if we're generating a form of -mabicalls in which we can use
110 operators like %hi and %lo to refer to locally-binding symbols.
111 We can only do this for -mno-shared, and only then if we can use
112 relocation operations instead of assembly macros. It isn't really
113 worth using absolute sequences for 64-bit symbols because GOT
114 accesses are so much shorter. */
115
116 #define TARGET_ABSOLUTE_ABICALLS \
117 (TARGET_ABICALLS \
118 && !TARGET_SHARED \
119 && TARGET_EXPLICIT_RELOCS \
120 && !ABI_HAS_64BIT_SYMBOLS)
121
122 /* True if we can optimize sibling calls. For simplicity, we only
123 handle cases in which call_insn_operand will reject invalid
124 sibcall addresses. There are two cases in which this isn't true:
125
126 - TARGET_MIPS16. call_insn_operand accepts constant addresses
127 but there is no direct jump instruction. It isn't worth
128 using sibling calls in this case anyway; they would usually
129 be longer than normal calls.
130
131 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
132 accepts global constants, but all sibcalls must be indirect. */
133 #define TARGET_SIBCALLS \
134 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
135
136 /* True if we need to use a global offset table to access some symbols. */
137 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
138
139 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
140 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
141
142 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
143 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
144
145 /* True if we should use .cprestore to store to the cprestore slot.
146
147 We continue to use .cprestore for explicit-reloc code so that JALs
148 inside inline asms will work correctly. */
149 #define TARGET_CPRESTORE_DIRECTIVE \
150 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
151
152 /* True if we can use the J and JAL instructions. */
153 #define TARGET_ABSOLUTE_JUMPS \
154 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
155
156 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
157 This is true for both the PIC and non-PIC VxWorks RTP modes. */
158 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
159
160 /* True if .gpword or .gpdword should be used for switch tables.
161
162 Although GAS does understand .gpdword, the SGI linker mishandles
163 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
164 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
165 #define TARGET_GPWORD \
166 (TARGET_ABICALLS \
167 && !TARGET_ABSOLUTE_ABICALLS \
168 && !(mips_abi == ABI_64 && TARGET_IRIX6))
169
170 /* True if the output must have a writable .eh_frame.
171 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
172 #ifdef HAVE_LD_PERSONALITY_RELAXATION
173 #define TARGET_WRITABLE_EH_FRAME 0
174 #else
175 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
176 #endif
177
178 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
179 #ifdef HAVE_AS_DSPR1_MULT
180 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
181 #else
182 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
183 #endif
184
185 /* Generate mips16 code */
186 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
187 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
188 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
189 /* Generate mips16e register save/restore sequences. */
190 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
191
192 /* True if we're generating a form of MIPS16 code in which general
193 text loads are allowed. */
194 #define TARGET_MIPS16_TEXT_LOADS \
195 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
196
197 /* True if we're generating a form of MIPS16 code in which PC-relative
198 loads are allowed. */
199 #define TARGET_MIPS16_PCREL_LOADS \
200 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
201
202 /* Generic ISA defines. */
203 #define ISA_MIPS1 (mips_isa == 1)
204 #define ISA_MIPS2 (mips_isa == 2)
205 #define ISA_MIPS3 (mips_isa == 3)
206 #define ISA_MIPS4 (mips_isa == 4)
207 #define ISA_MIPS32 (mips_isa == 32)
208 #define ISA_MIPS32R2 (mips_isa == 33)
209 #define ISA_MIPS64 (mips_isa == 64)
210 #define ISA_MIPS64R2 (mips_isa == 65)
211
212 /* Architecture target defines. */
213 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
214 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
215 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
216 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
217 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
218 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
219 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
220 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
221 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
222 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
223 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
224 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
225 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
226 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
227 || mips_arch == PROCESSOR_SB1A)
228 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
229
230 /* Scheduling target defines. */
231 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
232 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
233 || mips_tune == PROCESSOR_24KF2_1 \
234 || mips_tune == PROCESSOR_24KF1_1)
235 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
236 || mips_tune == PROCESSOR_74KF2_1 \
237 || mips_tune == PROCESSOR_74KF1_1 \
238 || mips_tune == PROCESSOR_74KF3_2)
239 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
240 || mips_tune == PROCESSOR_LOONGSON_2F)
241 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
242 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
243 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
244 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
245 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
246 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
247 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
248 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
249 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
250 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
251 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
252 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
253 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
254 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
255 || mips_tune == PROCESSOR_SB1A)
256
257 /* Whether vector modes and intrinsics for ST Microelectronics
258 Loongson-2E/2F processors should be enabled. In o32 pairs of
259 floating-point registers provide 64-bit values. */
260 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
261 && (TARGET_LOONGSON_2EF \
262 || TARGET_LOONGSON_3A))
263
264 /* True if the pre-reload scheduler should try to create chains of
265 multiply-add or multiply-subtract instructions. For example,
266 suppose we have:
267
268 t1 = a * b
269 t2 = t1 + c * d
270 t3 = e * f
271 t4 = t3 - g * h
272
273 t1 will have a higher priority than t2 and t3 will have a higher
274 priority than t4. However, before reload, there is no dependence
275 between t1 and t3, and they can often have similar priorities.
276 The scheduler will then tend to prefer:
277
278 t1 = a * b
279 t3 = e * f
280 t2 = t1 + c * d
281 t4 = t3 - g * h
282
283 which stops us from making full use of macc/madd-style instructions.
284 This sort of situation occurs frequently in Fourier transforms and
285 in unrolled loops.
286
287 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
288 queue so that chained multiply-add and multiply-subtract instructions
289 appear ahead of any other instruction that is likely to clobber lo.
290 In the example above, if t2 and t3 become ready at the same time,
291 the code ensures that t2 is scheduled first.
292
293 Multiply-accumulate instructions are a bigger win for some targets
294 than others, so this macro is defined on an opt-in basis. */
295 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
296 || TUNE_MIPS4120 \
297 || TUNE_MIPS4130 \
298 || TUNE_24K)
299
300 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
301 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
302
303 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
304 directly accessible, while the command-line options select
305 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
306 in use. */
307 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
308 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
309
310 /* False if SC acts as a memory barrier with respect to itself,
311 otherwise a SYNC will be emitted after SC for atomic operations
312 that require ordering between the SC and following loads and
313 stores. It does not tell anything about ordering of loads and
314 stores prior to and following the SC, only about the SC itself and
315 those loads and stores follow it. */
316 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
317
318 /* IRIX specific stuff. */
319 #define TARGET_IRIX6 0
320
321 /* Define preprocessor macros for the -march and -mtune options.
322 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
323 processor. If INFO's canonical name is "foo", define PREFIX to
324 be "foo", and define an additional macro PREFIX_FOO. */
325 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
326 do \
327 { \
328 char *macro, *p; \
329 \
330 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
331 for (p = macro; *p != 0; p++) \
332 *p = TOUPPER (*p); \
333 \
334 builtin_define (macro); \
335 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
336 free (macro); \
337 } \
338 while (0)
339
340 /* Target CPU builtins. */
341 #define TARGET_CPU_CPP_BUILTINS() \
342 do \
343 { \
344 /* Everyone but IRIX defines this to mips. */ \
345 if (!TARGET_IRIX6) \
346 builtin_assert ("machine=mips"); \
347 \
348 builtin_assert ("cpu=mips"); \
349 builtin_define ("__mips__"); \
350 builtin_define ("_mips"); \
351 \
352 /* We do this here because __mips is defined below and so we \
353 can't use builtin_define_std. We don't ever want to define \
354 "mips" for VxWorks because some of the VxWorks headers \
355 construct include filenames from a root directory macro, \
356 an architecture macro and a filename, where the architecture \
357 macro expands to 'mips'. If we define 'mips' to 1, the \
358 architecture macro expands to 1 as well. */ \
359 if (!flag_iso && !TARGET_VXWORKS) \
360 builtin_define ("mips"); \
361 \
362 if (TARGET_64BIT) \
363 builtin_define ("__mips64"); \
364 \
365 if (!TARGET_IRIX6) \
366 { \
367 /* Treat _R3000 and _R4000 like register-size \
368 defines, which is how they've historically \
369 been used. */ \
370 if (TARGET_64BIT) \
371 { \
372 builtin_define_std ("R4000"); \
373 builtin_define ("_R4000"); \
374 } \
375 else \
376 { \
377 builtin_define_std ("R3000"); \
378 builtin_define ("_R3000"); \
379 } \
380 } \
381 if (TARGET_FLOAT64) \
382 builtin_define ("__mips_fpr=64"); \
383 else \
384 builtin_define ("__mips_fpr=32"); \
385 \
386 if (mips_base_mips16) \
387 builtin_define ("__mips16"); \
388 \
389 if (TARGET_MIPS3D) \
390 builtin_define ("__mips3d"); \
391 \
392 if (TARGET_SMARTMIPS) \
393 builtin_define ("__mips_smartmips"); \
394 \
395 if (TARGET_DSP) \
396 { \
397 builtin_define ("__mips_dsp"); \
398 if (TARGET_DSPR2) \
399 { \
400 builtin_define ("__mips_dspr2"); \
401 builtin_define ("__mips_dsp_rev=2"); \
402 } \
403 else \
404 builtin_define ("__mips_dsp_rev=1"); \
405 } \
406 \
407 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
408 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
409 \
410 if (ISA_MIPS1) \
411 { \
412 builtin_define ("__mips=1"); \
413 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
414 } \
415 else if (ISA_MIPS2) \
416 { \
417 builtin_define ("__mips=2"); \
418 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
419 } \
420 else if (ISA_MIPS3) \
421 { \
422 builtin_define ("__mips=3"); \
423 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
424 } \
425 else if (ISA_MIPS4) \
426 { \
427 builtin_define ("__mips=4"); \
428 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
429 } \
430 else if (ISA_MIPS32) \
431 { \
432 builtin_define ("__mips=32"); \
433 builtin_define ("__mips_isa_rev=1"); \
434 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
435 } \
436 else if (ISA_MIPS32R2) \
437 { \
438 builtin_define ("__mips=32"); \
439 builtin_define ("__mips_isa_rev=2"); \
440 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
441 } \
442 else if (ISA_MIPS64) \
443 { \
444 builtin_define ("__mips=64"); \
445 builtin_define ("__mips_isa_rev=1"); \
446 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
447 } \
448 else if (ISA_MIPS64R2) \
449 { \
450 builtin_define ("__mips=64"); \
451 builtin_define ("__mips_isa_rev=2"); \
452 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
453 } \
454 \
455 switch (mips_abi) \
456 { \
457 case ABI_32: \
458 builtin_define ("_ABIO32=1"); \
459 builtin_define ("_MIPS_SIM=_ABIO32"); \
460 break; \
461 \
462 case ABI_N32: \
463 builtin_define ("_ABIN32=2"); \
464 builtin_define ("_MIPS_SIM=_ABIN32"); \
465 break; \
466 \
467 case ABI_64: \
468 builtin_define ("_ABI64=3"); \
469 builtin_define ("_MIPS_SIM=_ABI64"); \
470 break; \
471 \
472 case ABI_O64: \
473 builtin_define ("_ABIO64=4"); \
474 builtin_define ("_MIPS_SIM=_ABIO64"); \
475 break; \
476 } \
477 \
478 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
479 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
480 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
481 builtin_define_with_int_value ("_MIPS_FPSET", \
482 32 / MAX_FPRS_PER_FMT); \
483 \
484 /* These defines reflect the ABI in use, not whether the \
485 FPU is directly accessible. */ \
486 if (TARGET_NO_FLOAT) \
487 builtin_define ("__mips_no_float"); \
488 else if (TARGET_HARD_FLOAT_ABI) \
489 builtin_define ("__mips_hard_float"); \
490 else \
491 builtin_define ("__mips_soft_float"); \
492 \
493 if (TARGET_SINGLE_FLOAT) \
494 builtin_define ("__mips_single_float"); \
495 \
496 if (TARGET_PAIRED_SINGLE_FLOAT) \
497 builtin_define ("__mips_paired_single_float"); \
498 \
499 if (TARGET_BIG_ENDIAN) \
500 { \
501 builtin_define_std ("MIPSEB"); \
502 builtin_define ("_MIPSEB"); \
503 } \
504 else \
505 { \
506 builtin_define_std ("MIPSEL"); \
507 builtin_define ("_MIPSEL"); \
508 } \
509 \
510 /* Whether calls should go through $25. The separate __PIC__ \
511 macro indicates whether abicalls code might use a GOT. */ \
512 if (TARGET_ABICALLS) \
513 builtin_define ("__mips_abicalls"); \
514 \
515 /* Whether Loongson vector modes are enabled. */ \
516 if (TARGET_LOONGSON_VECTORS) \
517 builtin_define ("__mips_loongson_vector_rev"); \
518 \
519 /* Historical Octeon macro. */ \
520 if (TARGET_OCTEON) \
521 builtin_define ("__OCTEON__"); \
522 \
523 /* Macros dependent on the C dialect. */ \
524 if (preprocessing_asm_p ()) \
525 { \
526 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
527 builtin_define ("_LANGUAGE_ASSEMBLY"); \
528 } \
529 else if (c_dialect_cxx ()) \
530 { \
531 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
532 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
533 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
534 } \
535 else \
536 { \
537 builtin_define_std ("LANGUAGE_C"); \
538 builtin_define ("_LANGUAGE_C"); \
539 } \
540 if (c_dialect_objc ()) \
541 { \
542 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
543 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
544 /* Bizarre, but needed at least for Irix. */ \
545 builtin_define_std ("LANGUAGE_C"); \
546 builtin_define ("_LANGUAGE_C"); \
547 } \
548 \
549 if (mips_abi == ABI_EABI) \
550 builtin_define ("__mips_eabi"); \
551 \
552 if (TARGET_CACHE_BUILTIN) \
553 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
554 } \
555 while (0)
556
557 /* Default target_flags if no switches are specified */
558
559 #ifndef TARGET_DEFAULT
560 #define TARGET_DEFAULT 0
561 #endif
562
563 #ifndef TARGET_CPU_DEFAULT
564 #define TARGET_CPU_DEFAULT 0
565 #endif
566
567 #ifndef TARGET_ENDIAN_DEFAULT
568 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
569 #endif
570
571 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
572 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
573 #endif
574
575 #ifdef IN_LIBGCC2
576 #undef TARGET_64BIT
577 /* Make this compile time constant for libgcc2 */
578 #ifdef __mips64
579 #define TARGET_64BIT 1
580 #else
581 #define TARGET_64BIT 0
582 #endif
583 #endif /* IN_LIBGCC2 */
584
585 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
586 when compiled with hardware floating point. This is because MIPS16
587 code cannot save and restore the floating-point registers, which is
588 important if in a mixed MIPS16/non-MIPS16 environment. */
589
590 #ifdef IN_LIBGCC2
591 #if __mips_hard_float
592 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
593 #endif
594 #endif /* IN_LIBGCC2 */
595
596 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
597
598 #ifndef MULTILIB_ENDIAN_DEFAULT
599 #if TARGET_ENDIAN_DEFAULT == 0
600 #define MULTILIB_ENDIAN_DEFAULT "EL"
601 #else
602 #define MULTILIB_ENDIAN_DEFAULT "EB"
603 #endif
604 #endif
605
606 #ifndef MULTILIB_ISA_DEFAULT
607 # if MIPS_ISA_DEFAULT == 1
608 # define MULTILIB_ISA_DEFAULT "mips1"
609 # else
610 # if MIPS_ISA_DEFAULT == 2
611 # define MULTILIB_ISA_DEFAULT "mips2"
612 # else
613 # if MIPS_ISA_DEFAULT == 3
614 # define MULTILIB_ISA_DEFAULT "mips3"
615 # else
616 # if MIPS_ISA_DEFAULT == 4
617 # define MULTILIB_ISA_DEFAULT "mips4"
618 # else
619 # if MIPS_ISA_DEFAULT == 32
620 # define MULTILIB_ISA_DEFAULT "mips32"
621 # else
622 # if MIPS_ISA_DEFAULT == 33
623 # define MULTILIB_ISA_DEFAULT "mips32r2"
624 # else
625 # if MIPS_ISA_DEFAULT == 64
626 # define MULTILIB_ISA_DEFAULT "mips64"
627 # else
628 # if MIPS_ISA_DEFAULT == 65
629 # define MULTILIB_ISA_DEFAULT "mips64r2"
630 # else
631 # define MULTILIB_ISA_DEFAULT "mips1"
632 # endif
633 # endif
634 # endif
635 # endif
636 # endif
637 # endif
638 # endif
639 # endif
640 #endif
641
642 #ifndef MIPS_ABI_DEFAULT
643 #define MIPS_ABI_DEFAULT ABI_32
644 #endif
645
646 /* Use the most portable ABI flag for the ASM specs. */
647
648 #if MIPS_ABI_DEFAULT == ABI_32
649 #define MULTILIB_ABI_DEFAULT "mabi=32"
650 #endif
651
652 #if MIPS_ABI_DEFAULT == ABI_O64
653 #define MULTILIB_ABI_DEFAULT "mabi=o64"
654 #endif
655
656 #if MIPS_ABI_DEFAULT == ABI_N32
657 #define MULTILIB_ABI_DEFAULT "mabi=n32"
658 #endif
659
660 #if MIPS_ABI_DEFAULT == ABI_64
661 #define MULTILIB_ABI_DEFAULT "mabi=64"
662 #endif
663
664 #if MIPS_ABI_DEFAULT == ABI_EABI
665 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
666 #endif
667
668 #ifndef MULTILIB_DEFAULTS
669 #define MULTILIB_DEFAULTS \
670 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
671 #endif
672
673 /* We must pass -EL to the linker by default for little endian embedded
674 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
675 linker will default to using big-endian output files. The OUTPUT_FORMAT
676 line must be in the linker script, otherwise -EB/-EL will not work. */
677
678 #ifndef ENDIAN_SPEC
679 #if TARGET_ENDIAN_DEFAULT == 0
680 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
681 #else
682 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
683 #endif
684 #endif
685
686 /* A spec condition that matches all non-mips16 -mips arguments. */
687
688 #define MIPS_ISA_LEVEL_OPTION_SPEC \
689 "mips1|mips2|mips3|mips4|mips32*|mips64*"
690
691 /* A spec condition that matches all non-mips16 architecture arguments. */
692
693 #define MIPS_ARCH_OPTION_SPEC \
694 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
695
696 /* A spec that infers a -mips argument from an -march argument,
697 or injects the default if no architecture is specified. */
698
699 #define MIPS_ISA_LEVEL_SPEC \
700 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
701 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
702 %{march=mips2|march=r6000:-mips2} \
703 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
704 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
705 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
706 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
707 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
708 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
709 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
710 |march=xlr|march=loongson3a: -mips64} \
711 %{march=mips64r2|march=octeon: -mips64r2} \
712 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
713
714 /* A spec that infers a -mhard-float or -msoft-float setting from an
715 -march argument. Note that soft-float and hard-float code are not
716 link-compatible. */
717
718 #define MIPS_ARCH_FLOAT_SPEC \
719 "%{mhard-float|msoft-float|march=mips*:; \
720 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
721 |march=34kc|march=74kc|march=1004kc|march=5kc \
722 |march=octeon|march=xlr: -msoft-float; \
723 march=*: -mhard-float}"
724
725 /* A spec condition that matches 32-bit options. It only works if
726 MIPS_ISA_LEVEL_SPEC has been applied. */
727
728 #define MIPS_32BIT_OPTION_SPEC \
729 "mips1|mips2|mips32*|mgp32"
730
731 #if MIPS_ABI_DEFAULT == ABI_O64 \
732 || MIPS_ABI_DEFAULT == ABI_N32 \
733 || MIPS_ABI_DEFAULT == ABI_64
734 #define OPT_ARCH64 "mabi=32|mgp32:;"
735 #define OPT_ARCH32 "mabi=32|mgp32"
736 #else
737 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
738 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
739 #endif
740
741 /* Support for a compile-time default CPU, et cetera. The rules are:
742 --with-arch is ignored if -march is specified or a -mips is specified
743 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
744 --with-tune is ignored if -mtune is specified; likewise
745 --with-tune-32 and --with-tune-64.
746 --with-abi is ignored if -mabi is specified.
747 --with-float is ignored if -mhard-float or -msoft-float are
748 specified.
749 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
750 specified. */
751 #define OPTION_DEFAULT_SPECS \
752 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
753 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
754 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
755 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
756 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
757 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
758 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
759 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
760 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
761 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
762 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
763 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
764
765
766 /* A spec that infers the -mdsp setting from an -march argument. */
767 #define BASE_DRIVER_SELF_SPECS \
768 "%{!mno-dsp: \
769 %{march=24ke*|march=34k*|march=1004k*: -mdsp} \
770 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
771
772 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
773
774 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
775 && ISA_HAS_COND_TRAP)
776
777 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
778
779 /* True if the ABI can only work with 64-bit integer registers. We
780 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
781 otherwise floating-point registers must also be 64-bit. */
782 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
783
784 /* Likewise for 32-bit regs. */
785 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
786
787 /* True if the file format uses 64-bit symbols. At present, this is
788 only true for n64, which uses 64-bit ELF. */
789 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
790
791 /* True if symbols are 64 bits wide. This is usually determined by
792 the ABI's file format, but it can be overridden by -msym32. Note that
793 overriding the size with -msym32 changes the ABI of relocatable objects,
794 although it doesn't change the ABI of a fully-linked object. */
795 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS && !TARGET_SYM32)
796
797 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
798 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
799 || ISA_MIPS4 \
800 || ISA_MIPS64 \
801 || ISA_MIPS64R2)
802
803 /* ISA has branch likely instructions (e.g. mips2). */
804 /* Disable branchlikely for tx39 until compare rewrite. They haven't
805 been generated up to this point. */
806 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
807
808 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
809 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
810 || TARGET_MIPS5400 \
811 || TARGET_MIPS5500 \
812 || TARGET_MIPS7000 \
813 || TARGET_MIPS9000 \
814 || TARGET_MAD \
815 || ISA_MIPS32 \
816 || ISA_MIPS32R2 \
817 || ISA_MIPS64 \
818 || ISA_MIPS64R2) \
819 && !TARGET_MIPS16)
820
821 /* ISA has a three-operand multiplication instruction. */
822 #define ISA_HAS_DMUL3 (TARGET_64BIT \
823 && TARGET_OCTEON \
824 && !TARGET_MIPS16)
825
826 /* ISA has the floating-point conditional move instructions introduced
827 in mips4. */
828 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
829 || ISA_MIPS32 \
830 || ISA_MIPS32R2 \
831 || ISA_MIPS64 \
832 || ISA_MIPS64R2) \
833 && !TARGET_MIPS5500 \
834 && !TARGET_MIPS16)
835
836 /* ISA has the integer conditional move instructions introduced in mips4 and
837 ST Loongson 2E/2F. */
838 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
839
840 /* ISA has LDC1 and SDC1. */
841 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
842
843 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
844 branch on CC, and move (both FP and non-FP) on CC. */
845 #define ISA_HAS_8CC (ISA_MIPS4 \
846 || ISA_MIPS32 \
847 || ISA_MIPS32R2 \
848 || ISA_MIPS64 \
849 || ISA_MIPS64R2)
850
851 /* This is a catch all for other mips4 instructions: indexed load, the
852 FP madd and msub instructions, and the FP recip and recip sqrt
853 instructions. */
854 #define ISA_HAS_FP4 ((ISA_MIPS4 \
855 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
856 || ISA_MIPS64 \
857 || ISA_MIPS64R2) \
858 && !TARGET_MIPS16)
859
860 /* ISA has paired-single instructions. */
861 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
862
863 /* ISA has conditional trap instructions. */
864 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
865 && !TARGET_MIPS16)
866
867 /* ISA has integer multiply-accumulate instructions, madd and msub. */
868 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
869 || ISA_MIPS32R2 \
870 || ISA_MIPS64 \
871 || ISA_MIPS64R2) \
872 && !TARGET_MIPS16)
873
874 /* Integer multiply-accumulate instructions should be generated. */
875 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
876
877 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
878 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
879
880 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
881 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
882
883 /* ISA has floating-point nmadd and nmsub instructions
884 'd = -((a * b) [+-] c)'. */
885 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
886 ((ISA_MIPS4 \
887 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
888 || ISA_MIPS64 \
889 || ISA_MIPS64R2) \
890 && (!TARGET_MIPS5400 || TARGET_MAD) \
891 && !TARGET_MIPS16)
892
893 /* ISA has floating-point nmadd and nmsub instructions
894 'c = -((a * b) [+-] c)'. */
895 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
896 TARGET_LOONGSON_2EF
897
898 /* ISA has count leading zeroes/ones instruction (not implemented). */
899 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
900 || ISA_MIPS32R2 \
901 || ISA_MIPS64 \
902 || ISA_MIPS64R2) \
903 && !TARGET_MIPS16)
904
905 /* ISA has three operand multiply instructions that put
906 the high part in an accumulator: mulhi or mulhiu. */
907 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
908 || TARGET_MIPS5500 \
909 || TARGET_SR71K) \
910 && !TARGET_MIPS16)
911
912 /* ISA has three operand multiply instructions that
913 negates the result and puts the result in an accumulator. */
914 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
915 || TARGET_MIPS5500 \
916 || TARGET_SR71K) \
917 && !TARGET_MIPS16)
918
919 /* ISA has three operand multiply instructions that subtracts the
920 result from a 4th operand and puts the result in an accumulator. */
921 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
922 || TARGET_MIPS5500 \
923 || TARGET_SR71K) \
924 && !TARGET_MIPS16)
925
926 /* ISA has three operand multiply instructions that the result
927 from a 4th operand and puts the result in an accumulator. */
928 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
929 || TARGET_MIPS4130 \
930 || TARGET_MIPS5400 \
931 || TARGET_MIPS5500 \
932 || TARGET_SR71K) \
933 && !TARGET_MIPS16)
934
935 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
936 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
937 || TARGET_MIPS4130) \
938 && !TARGET_MIPS16)
939
940 /* ISA has the "ror" (rotate right) instructions. */
941 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
942 || ISA_MIPS64R2 \
943 || TARGET_MIPS5400 \
944 || TARGET_MIPS5500 \
945 || TARGET_SR71K \
946 || TARGET_SMARTMIPS) \
947 && !TARGET_MIPS16)
948
949 /* ISA has data prefetch instructions. This controls use of 'pref'. */
950 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
951 || TARGET_LOONGSON_2EF \
952 || ISA_MIPS32 \
953 || ISA_MIPS32R2 \
954 || ISA_MIPS64 \
955 || ISA_MIPS64R2) \
956 && !TARGET_MIPS16)
957
958 /* ISA has data indexed prefetch instructions. This controls use of
959 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
960 (prefx is a cop1x instruction, so can only be used if FP is
961 enabled.) */
962 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
963 || ISA_MIPS32R2 \
964 || ISA_MIPS64 \
965 || ISA_MIPS64R2) \
966 && !TARGET_MIPS16)
967
968 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
969 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
970 also requires TARGET_DOUBLE_FLOAT. */
971 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
972
973 /* ISA includes the MIPS32r2 seb and seh instructions. */
974 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
975 || ISA_MIPS64R2) \
976 && !TARGET_MIPS16)
977
978 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
979 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
980 || ISA_MIPS64R2) \
981 && !TARGET_MIPS16)
982
983 /* ISA has instructions for accessing top part of 64-bit fp regs. */
984 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
985 && (ISA_MIPS32R2 \
986 || ISA_MIPS64R2))
987
988 /* ISA has lwxs instruction (load w/scaled index address. */
989 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
990
991 /* The DSP ASE is available. */
992 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
993
994 /* Revision 2 of the DSP ASE is available. */
995 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
996
997 /* True if the result of a load is not available to the next instruction.
998 A nop will then be needed between instructions like "lw $4,..."
999 and "addiu $4,$4,1". */
1000 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1001 && !TARGET_MIPS3900 \
1002 && !TARGET_MIPS16)
1003
1004 /* Likewise mtc1 and mfc1. */
1005 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1006 && !TARGET_LOONGSON_2EF)
1007
1008 /* Likewise floating-point comparisons. */
1009 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1010 && !TARGET_LOONGSON_2EF)
1011
1012 /* True if mflo and mfhi can be immediately followed by instructions
1013 which write to the HI and LO registers.
1014
1015 According to MIPS specifications, MIPS ISAs I, II, and III need
1016 (at least) two instructions between the reads of HI/LO and
1017 instructions which write them, and later ISAs do not. Contradicting
1018 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1019 the UM for the NEC Vr5000) document needing the instructions between
1020 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1021 MIPS64 and later ISAs to have the interlocks, plus any specific
1022 earlier-ISA CPUs for which CPU documentation declares that the
1023 instructions are really interlocked. */
1024 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1025 || ISA_MIPS32R2 \
1026 || ISA_MIPS64 \
1027 || ISA_MIPS64R2 \
1028 || TARGET_MIPS5500 \
1029 || TARGET_LOONGSON_2EF)
1030
1031 /* ISA includes synci, jr.hb and jalr.hb. */
1032 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1033 || ISA_MIPS64R2) \
1034 && !TARGET_MIPS16)
1035
1036 /* ISA includes sync. */
1037 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1038 #define GENERATE_SYNC \
1039 (target_flags_explicit & MASK_LLSC \
1040 ? TARGET_LLSC && !TARGET_MIPS16 \
1041 : ISA_HAS_SYNC)
1042
1043 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1044 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1045 instructions. */
1046 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1047 #define GENERATE_LL_SC \
1048 (target_flags_explicit & MASK_LLSC \
1049 ? TARGET_LLSC && !TARGET_MIPS16 \
1050 : ISA_HAS_LL_SC)
1051
1052 /* ISA includes the baddu instruction. */
1053 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1054
1055 /* ISA includes the bbit* instructions. */
1056 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1057
1058 /* ISA includes the cins instruction. */
1059 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1060
1061 /* ISA includes the exts instruction. */
1062 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1063
1064 /* ISA includes the seq and sne instructions. */
1065 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1066
1067 /* ISA includes the pop instruction. */
1068 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1069
1070 /* The CACHE instruction is available in non-MIPS16 code. */
1071 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1072
1073 /* The CACHE instruction is available. */
1074 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1075 \f
1076 /* Tell collect what flags to pass to nm. */
1077 #ifndef NM_FLAGS
1078 #define NM_FLAGS "-Bn"
1079 #endif
1080
1081 \f
1082 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1083 to the assembler. It may be overridden by subtargets. */
1084 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1085 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1086 %{noasmopt:-O0} \
1087 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1088 #endif
1089
1090 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1091 the assembler. It may be overridden by subtargets.
1092
1093 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1094 COFF debugging info. */
1095
1096 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1097 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1098 %{g} %{g0} %{g1} %{g2} %{g3} \
1099 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1100 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1101 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1102 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1103 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1104 #endif
1105
1106 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1107 overridden by subtargets. */
1108
1109 #ifndef SUBTARGET_ASM_SPEC
1110 #define SUBTARGET_ASM_SPEC ""
1111 #endif
1112
1113 #undef ASM_SPEC
1114 #define ASM_SPEC "\
1115 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1116 %{mips32*} %{mips64*} \
1117 %{mips16} %{mno-mips16:-no-mips16} \
1118 %{mips3d} %{mno-mips3d:-no-mips3d} \
1119 %{mdmx} %{mno-mdmx:-no-mdmx} \
1120 %{mdsp} %{mno-dsp} \
1121 %{mdspr2} %{mno-dspr2} \
1122 %{msmartmips} %{mno-smartmips} \
1123 %{mmt} %{mno-mt} \
1124 %{mfix-vr4120} %{mfix-vr4130} \
1125 %{mfix-24k} \
1126 %(subtarget_asm_optimizing_spec) \
1127 %(subtarget_asm_debugging_spec) \
1128 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1129 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1130 %{mfp32} %{mfp64} \
1131 %{mshared} %{mno-shared} \
1132 %{msym32} %{mno-sym32} \
1133 %{mtune=*} \
1134 %(subtarget_asm_spec)"
1135
1136 /* Extra switches sometimes passed to the linker. */
1137
1138 #ifndef LINK_SPEC
1139 #define LINK_SPEC "\
1140 %(endian_spec) \
1141 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1142 %{shared}"
1143 #endif /* LINK_SPEC defined */
1144
1145
1146 /* Specs for the compiler proper */
1147
1148 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1149 overridden by subtargets. */
1150 #ifndef SUBTARGET_CC1_SPEC
1151 #define SUBTARGET_CC1_SPEC ""
1152 #endif
1153
1154 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1155
1156 #undef CC1_SPEC
1157 #define CC1_SPEC "\
1158 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1159 %(subtarget_cc1_spec)"
1160
1161 /* Preprocessor specs. */
1162
1163 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1164 overridden by subtargets. */
1165 #ifndef SUBTARGET_CPP_SPEC
1166 #define SUBTARGET_CPP_SPEC ""
1167 #endif
1168
1169 #define CPP_SPEC "%(subtarget_cpp_spec)"
1170
1171 /* This macro defines names of additional specifications to put in the specs
1172 that can be used in various specifications like CC1_SPEC. Its definition
1173 is an initializer with a subgrouping for each command option.
1174
1175 Each subgrouping contains a string constant, that defines the
1176 specification name, and a string constant that used by the GCC driver
1177 program.
1178
1179 Do not define this macro if it does not need to do anything. */
1180
1181 #define EXTRA_SPECS \
1182 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1183 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1184 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1185 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1186 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1187 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1188 { "endian_spec", ENDIAN_SPEC }, \
1189 SUBTARGET_EXTRA_SPECS
1190
1191 #ifndef SUBTARGET_EXTRA_SPECS
1192 #define SUBTARGET_EXTRA_SPECS
1193 #endif
1194 \f
1195 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1196 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1197
1198 #ifndef PREFERRED_DEBUGGING_TYPE
1199 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1200 #endif
1201
1202 /* The size of DWARF addresses should be the same as the size of symbols
1203 in the target file format. They shouldn't depend on things like -msym32,
1204 because many DWARF consumers do not allow the mixture of address sizes
1205 that one would then get from linking -msym32 code with -msym64 code.
1206
1207 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1208 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1209 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1210
1211 /* By default, turn on GDB extensions. */
1212 #define DEFAULT_GDB_EXTENSIONS 1
1213
1214 /* Local compiler-generated symbols must have a prefix that the assembler
1215 understands. By default, this is $, although some targets (e.g.,
1216 NetBSD-ELF) need to override this. */
1217
1218 #ifndef LOCAL_LABEL_PREFIX
1219 #define LOCAL_LABEL_PREFIX "$"
1220 #endif
1221
1222 /* By default on the mips, external symbols do not have an underscore
1223 prepended, but some targets (e.g., NetBSD) require this. */
1224
1225 #ifndef USER_LABEL_PREFIX
1226 #define USER_LABEL_PREFIX ""
1227 #endif
1228
1229 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1230 since the length can run past this up to a continuation point. */
1231 #undef DBX_CONTIN_LENGTH
1232 #define DBX_CONTIN_LENGTH 1500
1233
1234 /* How to renumber registers for dbx and gdb. */
1235 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1236
1237 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1238 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1239
1240 /* The DWARF 2 CFA column which tracks the return address. */
1241 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1242
1243 /* Before the prologue, RA lives in r31. */
1244 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1245
1246 /* Describe how we implement __builtin_eh_return. */
1247 #define EH_RETURN_DATA_REGNO(N) \
1248 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1249
1250 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1251
1252 #define EH_USES(N) mips_eh_uses (N)
1253
1254 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1255 The default for this in 64-bit mode is 8, which causes problems with
1256 SFmode register saves. */
1257 #define DWARF_CIE_DATA_ALIGNMENT -4
1258
1259 /* Correct the offset of automatic variables and arguments. Note that
1260 the MIPS debug format wants all automatic variables and arguments
1261 to be in terms of the virtual frame pointer (stack pointer before
1262 any adjustment in the function), while the MIPS 3.0 linker wants
1263 the frame pointer to be the stack pointer after the initial
1264 adjustment. */
1265
1266 #define DEBUGGER_AUTO_OFFSET(X) \
1267 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1268 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1269 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1270 \f
1271 /* Target machine storage layout */
1272
1273 #define BITS_BIG_ENDIAN 0
1274 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1275 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1276
1277 #define MAX_BITS_PER_WORD 64
1278
1279 /* Width of a word, in units (bytes). */
1280 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1281 #ifndef IN_LIBGCC2
1282 #define MIN_UNITS_PER_WORD 4
1283 #endif
1284
1285 /* For MIPS, width of a floating point register. */
1286 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1287
1288 /* The number of consecutive floating-point registers needed to store the
1289 largest format supported by the FPU. */
1290 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1291
1292 /* The number of consecutive floating-point registers needed to store the
1293 smallest format supported by the FPU. */
1294 #define MIN_FPRS_PER_FMT \
1295 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1296 ? 1 : MAX_FPRS_PER_FMT)
1297
1298 /* The largest size of value that can be held in floating-point
1299 registers and moved with a single instruction. */
1300 #define UNITS_PER_HWFPVALUE \
1301 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1302
1303 /* The largest size of value that can be held in floating-point
1304 registers. */
1305 #define UNITS_PER_FPVALUE \
1306 (TARGET_SOFT_FLOAT_ABI ? 0 \
1307 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1308 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1309
1310 /* The number of bytes in a double. */
1311 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1312
1313 /* Set the sizes of the core types. */
1314 #define SHORT_TYPE_SIZE 16
1315 #define INT_TYPE_SIZE 32
1316 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1317 #define LONG_LONG_TYPE_SIZE 64
1318
1319 #define FLOAT_TYPE_SIZE 32
1320 #define DOUBLE_TYPE_SIZE 64
1321 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1322
1323 /* Define the sizes of fixed-point types. */
1324 #define SHORT_FRACT_TYPE_SIZE 8
1325 #define FRACT_TYPE_SIZE 16
1326 #define LONG_FRACT_TYPE_SIZE 32
1327 #define LONG_LONG_FRACT_TYPE_SIZE 64
1328
1329 #define SHORT_ACCUM_TYPE_SIZE 16
1330 #define ACCUM_TYPE_SIZE 32
1331 #define LONG_ACCUM_TYPE_SIZE 64
1332 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1333 doesn't support 128-bit integers for MIPS32 currently. */
1334 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1335
1336 /* long double is not a fixed mode, but the idea is that, if we
1337 support long double, we also want a 128-bit integer type. */
1338 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1339
1340 #ifdef IN_LIBGCC2
1341 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1342 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1343 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1344 # else
1345 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1346 # endif
1347 #endif
1348
1349 /* Width in bits of a pointer. */
1350 #ifndef POINTER_SIZE
1351 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1352 #endif
1353
1354 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1355 #define PARM_BOUNDARY BITS_PER_WORD
1356
1357 /* Allocation boundary (in *bits*) for the code of a function. */
1358 #define FUNCTION_BOUNDARY 32
1359
1360 /* Alignment of field after `int : 0' in a structure. */
1361 #define EMPTY_FIELD_BOUNDARY 32
1362
1363 /* Every structure's size must be a multiple of this. */
1364 /* 8 is observed right on a DECstation and on riscos 4.02. */
1365 #define STRUCTURE_SIZE_BOUNDARY 8
1366
1367 /* There is no point aligning anything to a rounder boundary than this. */
1368 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1369
1370 /* All accesses must be aligned. */
1371 #define STRICT_ALIGNMENT 1
1372
1373 /* Define this if you wish to imitate the way many other C compilers
1374 handle alignment of bitfields and the structures that contain
1375 them.
1376
1377 The behavior is that the type written for a bit-field (`int',
1378 `short', or other integer type) imposes an alignment for the
1379 entire structure, as if the structure really did contain an
1380 ordinary field of that type. In addition, the bit-field is placed
1381 within the structure so that it would fit within such a field,
1382 not crossing a boundary for it.
1383
1384 Thus, on most machines, a bit-field whose type is written as `int'
1385 would not cross a four-byte boundary, and would force four-byte
1386 alignment for the whole structure. (The alignment used may not
1387 be four bytes; it is controlled by the other alignment
1388 parameters.)
1389
1390 If the macro is defined, its definition should be a C expression;
1391 a nonzero value for the expression enables this behavior. */
1392
1393 #define PCC_BITFIELD_TYPE_MATTERS 1
1394
1395 /* If defined, a C expression to compute the alignment given to a
1396 constant that is being placed in memory. CONSTANT is the constant
1397 and ALIGN is the alignment that the object would ordinarily have.
1398 The value of this macro is used instead of that alignment to align
1399 the object.
1400
1401 If this macro is not defined, then ALIGN is used.
1402
1403 The typical use of this macro is to increase alignment for string
1404 constants to be word aligned so that `strcpy' calls that copy
1405 constants can be done inline. */
1406
1407 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1408 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1409 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1410
1411 /* If defined, a C expression to compute the alignment for a static
1412 variable. TYPE is the data type, and ALIGN is the alignment that
1413 the object would ordinarily have. The value of this macro is used
1414 instead of that alignment to align the object.
1415
1416 If this macro is not defined, then ALIGN is used.
1417
1418 One use of this macro is to increase alignment of medium-size
1419 data to make it all fit in fewer cache lines. Another is to
1420 cause character arrays to be word-aligned so that `strcpy' calls
1421 that copy constants to character arrays can be done inline. */
1422
1423 #undef DATA_ALIGNMENT
1424 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1425 ((((ALIGN) < BITS_PER_WORD) \
1426 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1427 || TREE_CODE (TYPE) == UNION_TYPE \
1428 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1429
1430 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1431 character arrays to be word-aligned so that `strcpy' calls that copy
1432 constants to character arrays can be done inline, and 'strcmp' can be
1433 optimised to use word loads. */
1434 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1435 DATA_ALIGNMENT (TYPE, ALIGN)
1436
1437 #define PAD_VARARGS_DOWN \
1438 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1439
1440 /* Define if operations between registers always perform the operation
1441 on the full register even if a narrower mode is specified. */
1442 #define WORD_REGISTER_OPERATIONS
1443
1444 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1445 moves. All other references are zero extended. */
1446 #define LOAD_EXTEND_OP(MODE) \
1447 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1448 ? SIGN_EXTEND : ZERO_EXTEND)
1449
1450 /* Define this macro if it is advisable to hold scalars in registers
1451 in a wider mode than that declared by the program. In such cases,
1452 the value is constrained to be within the bounds of the declared
1453 type, but kept valid in the wider mode. The signedness of the
1454 extension may differ from that of the type. */
1455
1456 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1457 if (GET_MODE_CLASS (MODE) == MODE_INT \
1458 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1459 { \
1460 if ((MODE) == SImode) \
1461 (UNSIGNEDP) = 0; \
1462 (MODE) = Pmode; \
1463 }
1464
1465 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1466 Extensions of pointers to word_mode must be signed. */
1467 #define POINTERS_EXTEND_UNSIGNED false
1468
1469 /* Define if loading short immediate values into registers sign extends. */
1470 #define SHORT_IMMEDIATES_SIGN_EXTEND
1471
1472 /* The [d]clz instructions have the natural values at 0. */
1473
1474 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1475 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1476 \f
1477 /* Standard register usage. */
1478
1479 /* Number of hardware registers. We have:
1480
1481 - 32 integer registers
1482 - 32 floating point registers
1483 - 8 condition code registers
1484 - 2 accumulator registers (hi and lo)
1485 - 32 registers each for coprocessors 0, 2 and 3
1486 - 4 fake registers:
1487 - ARG_POINTER_REGNUM
1488 - FRAME_POINTER_REGNUM
1489 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1490 - CPRESTORE_SLOT_REGNUM
1491 - 2 dummy entries that were used at various times in the past.
1492 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1493 - 6 DSP control registers */
1494
1495 #define FIRST_PSEUDO_REGISTER 188
1496
1497 /* By default, fix the kernel registers ($26 and $27), the global
1498 pointer ($28) and the stack pointer ($29). This can change
1499 depending on the command-line options.
1500
1501 Regarding coprocessor registers: without evidence to the contrary,
1502 it's best to assume that each coprocessor register has a unique
1503 use. This can be overridden, in, e.g., mips_option_override or
1504 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1505 inappropriate for a particular target. */
1506
1507 #define FIXED_REGISTERS \
1508 { \
1509 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1510 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1512 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1513 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1514 /* COP0 registers */ \
1515 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1516 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1517 /* COP2 registers */ \
1518 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1519 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1520 /* COP3 registers */ \
1521 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1522 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1523 /* 6 DSP accumulator registers & 6 control registers */ \
1524 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1525 }
1526
1527
1528 /* Set up this array for o32 by default.
1529
1530 Note that we don't mark $31 as a call-clobbered register. The idea is
1531 that it's really the call instructions themselves which clobber $31.
1532 We don't care what the called function does with it afterwards.
1533
1534 This approach makes it easier to implement sibcalls. Unlike normal
1535 calls, sibcalls don't clobber $31, so the register reaches the
1536 called function in tact. EPILOGUE_USES says that $31 is useful
1537 to the called function. */
1538
1539 #define CALL_USED_REGISTERS \
1540 { \
1541 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1542 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1543 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1544 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1545 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1546 /* COP0 registers */ \
1547 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1548 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1549 /* COP2 registers */ \
1550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1551 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1552 /* COP3 registers */ \
1553 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1554 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1555 /* 6 DSP accumulator registers & 6 control registers */ \
1556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1557 }
1558
1559
1560 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1561
1562 #define CALL_REALLY_USED_REGISTERS \
1563 { /* General registers. */ \
1564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1565 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1566 /* Floating-point registers. */ \
1567 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1568 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1569 /* Others. */ \
1570 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1571 /* COP0 registers */ \
1572 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1573 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1574 /* COP2 registers */ \
1575 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1576 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1577 /* COP3 registers */ \
1578 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1579 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1580 /* 6 DSP accumulator registers & 6 control registers */ \
1581 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1582 }
1583
1584 /* Internal macros to classify a register number as to whether it's a
1585 general purpose register, a floating point register, a
1586 multiply/divide register, or a status register. */
1587
1588 #define GP_REG_FIRST 0
1589 #define GP_REG_LAST 31
1590 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1591 #define GP_DBX_FIRST 0
1592 #define K0_REG_NUM (GP_REG_FIRST + 26)
1593 #define K1_REG_NUM (GP_REG_FIRST + 27)
1594 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1595
1596 #define FP_REG_FIRST 32
1597 #define FP_REG_LAST 63
1598 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1599 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1600
1601 #define MD_REG_FIRST 64
1602 #define MD_REG_LAST 65
1603 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1604 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1605
1606 /* The DWARF 2 CFA column which tracks the return address from a
1607 signal handler context. This means that to maintain backwards
1608 compatibility, no hard register can be assigned this column if it
1609 would need to be handled by the DWARF unwinder. */
1610 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1611
1612 #define ST_REG_FIRST 67
1613 #define ST_REG_LAST 74
1614 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1615
1616
1617 /* FIXME: renumber. */
1618 #define COP0_REG_FIRST 80
1619 #define COP0_REG_LAST 111
1620 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1621
1622 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1623 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1624 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1625
1626 #define COP2_REG_FIRST 112
1627 #define COP2_REG_LAST 143
1628 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1629
1630 #define COP3_REG_FIRST 144
1631 #define COP3_REG_LAST 175
1632 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1633 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1634 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1635
1636 #define DSP_ACC_REG_FIRST 176
1637 #define DSP_ACC_REG_LAST 181
1638 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1639
1640 #define AT_REGNUM (GP_REG_FIRST + 1)
1641 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1642 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1643
1644 /* A few bitfield locations for the coprocessor registers. */
1645 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1646 the cause register for the EIC interrupt mode. */
1647 #define CAUSE_IPL 10
1648 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1649 #define SR_IPL 10
1650 /* Exception Level is at bit 1 of the status register. */
1651 #define SR_EXL 1
1652 /* Interrupt Enable is at bit 0 of the status register. */
1653 #define SR_IE 0
1654
1655 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1656 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1657 should be used instead. */
1658 #define FPSW_REGNUM ST_REG_FIRST
1659
1660 #define GP_REG_P(REGNO) \
1661 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1662 #define M16_REG_P(REGNO) \
1663 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1664 #define FP_REG_P(REGNO) \
1665 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1666 #define MD_REG_P(REGNO) \
1667 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1668 #define ST_REG_P(REGNO) \
1669 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1670 #define COP0_REG_P(REGNO) \
1671 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1672 #define COP2_REG_P(REGNO) \
1673 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1674 #define COP3_REG_P(REGNO) \
1675 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1676 #define ALL_COP_REG_P(REGNO) \
1677 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1678 /* Test if REGNO is one of the 6 new DSP accumulators. */
1679 #define DSP_ACC_REG_P(REGNO) \
1680 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1681 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1682 #define ACC_REG_P(REGNO) \
1683 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1684
1685 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1686
1687 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1688 to initialize the mips16 gp pseudo register. */
1689 #define CONST_GP_P(X) \
1690 (GET_CODE (X) == CONST \
1691 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1692 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1693
1694 /* Return coprocessor number from register number. */
1695
1696 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1697 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1698 : COP3_REG_P (REGNO) ? '3' : '?')
1699
1700
1701 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1702
1703 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1704 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1705
1706 #define MODES_TIEABLE_P mips_modes_tieable_p
1707
1708 /* Register to use for pushing function arguments. */
1709 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1710
1711 /* These two registers don't really exist: they get eliminated to either
1712 the stack or hard frame pointer. */
1713 #define ARG_POINTER_REGNUM 77
1714 #define FRAME_POINTER_REGNUM 78
1715
1716 /* $30 is not available on the mips16, so we use $17 as the frame
1717 pointer. */
1718 #define HARD_FRAME_POINTER_REGNUM \
1719 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1720
1721 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1722 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1723
1724 /* Register in which static-chain is passed to a function. */
1725 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1726
1727 /* Registers used as temporaries in prologue/epilogue code:
1728
1729 - If a MIPS16 PIC function needs access to _gp, it first loads
1730 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1731
1732 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1733 register. The register must not conflict with MIPS16_PIC_TEMP.
1734
1735 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1736 register.
1737
1738 If we're generating MIPS16 code, these registers must come from the
1739 core set of 8. The prologue registers mustn't conflict with any
1740 incoming arguments, the static chain pointer, or the frame pointer.
1741 The epilogue temporary mustn't conflict with the return registers,
1742 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1743 or the EH data registers.
1744
1745 If we're generating interrupt handlers, we use K0 as a temporary register
1746 in prologue/epilogue code. */
1747
1748 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1749 #define MIPS_PROLOGUE_TEMP_REGNUM \
1750 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1751 #define MIPS_EPILOGUE_TEMP_REGNUM \
1752 (cfun->machine->interrupt_handler_p \
1753 ? K0_REG_NUM \
1754 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1755
1756 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1757 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1758 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1759
1760 /* Define this macro if it is as good or better to call a constant
1761 function address than to call an address kept in a register. */
1762 #define NO_FUNCTION_CSE 1
1763
1764 /* The ABI-defined global pointer. Sometimes we use a different
1765 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1766 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1767
1768 /* We normally use $28 as the global pointer. However, when generating
1769 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1770 register instead. They can then avoid saving and restoring $28
1771 and perhaps avoid using a frame at all.
1772
1773 When a leaf function uses something other than $28, mips_expand_prologue
1774 will modify pic_offset_table_rtx in place. Take the register number
1775 from there after reload. */
1776 #define PIC_OFFSET_TABLE_REGNUM \
1777 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1778
1779 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1780 \f
1781 /* Define the classes of registers for register constraints in the
1782 machine description. Also define ranges of constants.
1783
1784 One of the classes must always be named ALL_REGS and include all hard regs.
1785 If there is more than one class, another class must be named NO_REGS
1786 and contain no registers.
1787
1788 The name GENERAL_REGS must be the name of a class (or an alias for
1789 another name such as ALL_REGS). This is the class of registers
1790 that is allowed by "g" or "r" in a register constraint.
1791 Also, registers outside this class are allocated only when
1792 instructions express preferences for them.
1793
1794 The classes must be numbered in nondecreasing order; that is,
1795 a larger-numbered class must never be contained completely
1796 in a smaller-numbered class.
1797
1798 For any two classes, it is very desirable that there be another
1799 class that represents their union. */
1800
1801 enum reg_class
1802 {
1803 NO_REGS, /* no registers in set */
1804 M16_REGS, /* mips16 directly accessible registers */
1805 T_REG, /* mips16 T register ($24) */
1806 M16_T_REGS, /* mips16 registers plus T register */
1807 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1808 V1_REG, /* Register $v1 ($3) used for TLS access. */
1809 LEA_REGS, /* Every GPR except $25 */
1810 GR_REGS, /* integer registers */
1811 FP_REGS, /* floating point registers */
1812 MD0_REG, /* first multiply/divide register */
1813 MD1_REG, /* second multiply/divide register */
1814 MD_REGS, /* multiply/divide registers (hi/lo) */
1815 COP0_REGS, /* generic coprocessor classes */
1816 COP2_REGS,
1817 COP3_REGS,
1818 ST_REGS, /* status registers (fp status) */
1819 DSP_ACC_REGS, /* DSP accumulator registers */
1820 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1821 FRAME_REGS, /* $arg and $frame */
1822 GR_AND_MD0_REGS, /* union classes */
1823 GR_AND_MD1_REGS,
1824 GR_AND_MD_REGS,
1825 GR_AND_ACC_REGS,
1826 ALL_REGS, /* all registers */
1827 LIM_REG_CLASSES /* max value + 1 */
1828 };
1829
1830 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1831
1832 #define GENERAL_REGS GR_REGS
1833
1834 /* An initializer containing the names of the register classes as C
1835 string constants. These names are used in writing some of the
1836 debugging dumps. */
1837
1838 #define REG_CLASS_NAMES \
1839 { \
1840 "NO_REGS", \
1841 "M16_REGS", \
1842 "T_REG", \
1843 "M16_T_REGS", \
1844 "PIC_FN_ADDR_REG", \
1845 "V1_REG", \
1846 "LEA_REGS", \
1847 "GR_REGS", \
1848 "FP_REGS", \
1849 "MD0_REG", \
1850 "MD1_REG", \
1851 "MD_REGS", \
1852 /* coprocessor registers */ \
1853 "COP0_REGS", \
1854 "COP2_REGS", \
1855 "COP3_REGS", \
1856 "ST_REGS", \
1857 "DSP_ACC_REGS", \
1858 "ACC_REGS", \
1859 "FRAME_REGS", \
1860 "GR_AND_MD0_REGS", \
1861 "GR_AND_MD1_REGS", \
1862 "GR_AND_MD_REGS", \
1863 "GR_AND_ACC_REGS", \
1864 "ALL_REGS" \
1865 }
1866
1867 /* An initializer containing the contents of the register classes,
1868 as integers which are bit masks. The Nth integer specifies the
1869 contents of class N. The way the integer MASK is interpreted is
1870 that register R is in the class if `MASK & (1 << R)' is 1.
1871
1872 When the machine has more than 32 registers, an integer does not
1873 suffice. Then the integers are replaced by sub-initializers,
1874 braced groupings containing several integers. Each
1875 sub-initializer must be suitable as an initializer for the type
1876 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1877
1878 #define REG_CLASS_CONTENTS \
1879 { \
1880 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1881 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1882 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1883 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1884 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1885 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1886 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1887 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1888 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1889 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1890 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1891 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1892 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1893 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1894 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1895 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1896 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1897 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1898 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1899 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1900 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1901 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1902 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1903 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1904 }
1905
1906
1907 /* A C expression whose value is a register class containing hard
1908 register REGNO. In general there is more that one such class;
1909 choose a class which is "minimal", meaning that no smaller class
1910 also contains the register. */
1911
1912 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1913
1914 /* A macro whose definition is the name of the class to which a
1915 valid base register must belong. A base register is one used in
1916 an address which is the register value plus a displacement. */
1917
1918 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1919
1920 /* A macro whose definition is the name of the class to which a
1921 valid index register must belong. An index register is one used
1922 in an address where its value is either multiplied by a scale
1923 factor or added to another register (as well as added to a
1924 displacement). */
1925
1926 #define INDEX_REG_CLASS NO_REGS
1927
1928 /* We generally want to put call-clobbered registers ahead of
1929 call-saved ones. (IRA expects this.) */
1930
1931 #define REG_ALLOC_ORDER \
1932 { /* Accumulator registers. When GPRs and accumulators have equal \
1933 cost, we generally prefer to use accumulators. For example, \
1934 a division of multiplication result is better allocated to LO, \
1935 so that we put the MFLO at the point of use instead of at the \
1936 point of definition. It's also needed if we're to take advantage \
1937 of the extra accumulators available with -mdspr2. In some cases, \
1938 it can also help to reduce register pressure. */ \
1939 64, 65,176,177,178,179,180,181, \
1940 /* Call-clobbered GPRs. */ \
1941 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1942 24, 25, 31, \
1943 /* The global pointer. This is call-clobbered for o32 and o64 \
1944 abicalls, call-saved for n32 and n64 abicalls, and a program \
1945 invariant otherwise. Putting it between the call-clobbered \
1946 and call-saved registers should cope with all eventualities. */ \
1947 28, \
1948 /* Call-saved GPRs. */ \
1949 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1950 /* GPRs that can never be exposed to the register allocator. */ \
1951 0, 26, 27, 29, \
1952 /* Call-clobbered FPRs. */ \
1953 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1954 48, 49, 50, 51, \
1955 /* FPRs that are usually call-saved. The odd ones are actually \
1956 call-clobbered for n32, but listing them ahead of the even \
1957 registers might encourage the register allocator to fragment \
1958 the available FPR pairs. We need paired FPRs to store long \
1959 doubles, so it isn't clear that using a different order \
1960 for n32 would be a win. */ \
1961 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1962 /* None of the remaining classes have defined call-saved \
1963 registers. */ \
1964 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1965 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1966 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1967 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1968 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1969 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1970 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1971 182,183,184,185,186,187 \
1972 }
1973
1974 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1975 to be rearranged based on a particular function. On the mips16, we
1976 want to allocate $24 (T_REG) before other registers for
1977 instructions for which it is possible. */
1978
1979 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
1980
1981 /* True if VALUE is an unsigned 6-bit number. */
1982
1983 #define UIMM6_OPERAND(VALUE) \
1984 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1985
1986 /* True if VALUE is a signed 10-bit number. */
1987
1988 #define IMM10_OPERAND(VALUE) \
1989 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1990
1991 /* True if VALUE is a signed 16-bit number. */
1992
1993 #define SMALL_OPERAND(VALUE) \
1994 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1995
1996 /* True if VALUE is an unsigned 16-bit number. */
1997
1998 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1999 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2000
2001 /* True if VALUE can be loaded into a register using LUI. */
2002
2003 #define LUI_OPERAND(VALUE) \
2004 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2005 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2006
2007 /* Return a value X with the low 16 bits clear, and such that
2008 VALUE - X is a signed 16-bit value. */
2009
2010 #define CONST_HIGH_PART(VALUE) \
2011 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2012
2013 #define CONST_LOW_PART(VALUE) \
2014 ((VALUE) - CONST_HIGH_PART (VALUE))
2015
2016 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2017 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2018 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2019
2020 /* The HI and LO registers can only be reloaded via the general
2021 registers. Condition code registers can only be loaded to the
2022 general registers, and from the floating point registers. */
2023
2024 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2025 mips_secondary_reload_class (CLASS, MODE, X, true)
2026 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2027 mips_secondary_reload_class (CLASS, MODE, X, false)
2028
2029 /* Return the maximum number of consecutive registers
2030 needed to represent mode MODE in a register of class CLASS. */
2031
2032 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2033
2034 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2035 mips_cannot_change_mode_class (FROM, TO, CLASS)
2036 \f
2037 /* Stack layout; function entry, exit and calling. */
2038
2039 #define STACK_GROWS_DOWNWARD
2040
2041 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2042
2043 /* Size of the area allocated in the frame to save the GP. */
2044
2045 #define MIPS_GP_SAVE_AREA_SIZE \
2046 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2047
2048 /* The offset of the first local variable from the frame pointer. See
2049 mips_compute_frame_info for details about the frame layout. */
2050
2051 #define STARTING_FRAME_OFFSET \
2052 (FRAME_GROWS_DOWNWARD \
2053 ? 0 \
2054 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2055
2056 #define RETURN_ADDR_RTX mips_return_addr
2057
2058 /* Mask off the MIPS16 ISA bit in unwind addresses.
2059
2060 The reason for this is a little subtle. When unwinding a call,
2061 we are given the call's return address, which on most targets
2062 is the address of the following instruction. However, what we
2063 actually want to find is the EH region for the call itself.
2064 The target-independent unwind code therefore searches for "RA - 1".
2065
2066 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2067 RA - 1 is therefore the real (even-valued) start of the return
2068 instruction. EH region labels are usually odd-valued MIPS16 symbols
2069 too, so a search for an even address within a MIPS16 region would
2070 usually work.
2071
2072 However, there is an exception. If the end of an EH region is also
2073 the end of a function, the end label is allowed to be even. This is
2074 necessary because a following non-MIPS16 function may also need EH
2075 information for its first instruction.
2076
2077 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2078 non-ISA-encoded address. This probably isn't ideal, but it is
2079 the traditional (legacy) behavior. It is therefore only safe
2080 to search MIPS EH regions for an _odd-valued_ address.
2081
2082 Masking off the ISA bit means that the target-independent code
2083 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2084 #define MASK_RETURN_ADDR GEN_INT (-2)
2085
2086
2087 /* Similarly, don't use the least-significant bit to tell pointers to
2088 code from vtable index. */
2089
2090 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2091
2092 /* The eliminations to $17 are only used for mips16 code. See the
2093 definition of HARD_FRAME_POINTER_REGNUM. */
2094
2095 #define ELIMINABLE_REGS \
2096 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2097 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2098 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2099 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2100 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2101 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2102
2103 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2104 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2105
2106 /* Allocate stack space for arguments at the beginning of each function. */
2107 #define ACCUMULATE_OUTGOING_ARGS 1
2108
2109 /* The argument pointer always points to the first argument. */
2110 #define FIRST_PARM_OFFSET(FNDECL) 0
2111
2112 /* o32 and o64 reserve stack space for all argument registers. */
2113 #define REG_PARM_STACK_SPACE(FNDECL) \
2114 (TARGET_OLDABI \
2115 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2116 : 0)
2117
2118 /* Define this if it is the responsibility of the caller to
2119 allocate the area reserved for arguments passed in registers.
2120 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2121 of this macro is to determine whether the space is included in
2122 `crtl->outgoing_args_size'. */
2123 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2124
2125 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2126 \f
2127 /* Symbolic macros for the registers used to return integer and floating
2128 point values. */
2129
2130 #define GP_RETURN (GP_REG_FIRST + 2)
2131 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2132
2133 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2134
2135 /* Symbolic macros for the first/last argument registers. */
2136
2137 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2138 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2139 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2140 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2141
2142 /* 1 if N is a possible register number for function argument passing.
2143 We have no FP argument registers when soft-float. When FP registers
2144 are 32 bits, we can't directly reference the odd numbered ones. */
2145
2146 #define FUNCTION_ARG_REGNO_P(N) \
2147 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2148 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2149 && !fixed_regs[N])
2150 \f
2151 /* This structure has to cope with two different argument allocation
2152 schemes. Most MIPS ABIs view the arguments as a structure, of which
2153 the first N words go in registers and the rest go on the stack. If I
2154 < N, the Ith word might go in Ith integer argument register or in a
2155 floating-point register. For these ABIs, we only need to remember
2156 the offset of the current argument into the structure.
2157
2158 The EABI instead allocates the integer and floating-point arguments
2159 separately. The first N words of FP arguments go in FP registers,
2160 the rest go on the stack. Likewise, the first N words of the other
2161 arguments go in integer registers, and the rest go on the stack. We
2162 need to maintain three counts: the number of integer registers used,
2163 the number of floating-point registers used, and the number of words
2164 passed on the stack.
2165
2166 We could keep separate information for the two ABIs (a word count for
2167 the standard ABIs, and three separate counts for the EABI). But it
2168 seems simpler to view the standard ABIs as forms of EABI that do not
2169 allocate floating-point registers.
2170
2171 So for the standard ABIs, the first N words are allocated to integer
2172 registers, and mips_function_arg decides on an argument-by-argument
2173 basis whether that argument should really go in an integer register,
2174 or in a floating-point one. */
2175
2176 typedef struct mips_args {
2177 /* Always true for varargs functions. Otherwise true if at least
2178 one argument has been passed in an integer register. */
2179 int gp_reg_found;
2180
2181 /* The number of arguments seen so far. */
2182 unsigned int arg_number;
2183
2184 /* The number of integer registers used so far. For all ABIs except
2185 EABI, this is the number of words that have been added to the
2186 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2187 unsigned int num_gprs;
2188
2189 /* For EABI, the number of floating-point registers used so far. */
2190 unsigned int num_fprs;
2191
2192 /* The number of words passed on the stack. */
2193 unsigned int stack_words;
2194
2195 /* On the mips16, we need to keep track of which floating point
2196 arguments were passed in general registers, but would have been
2197 passed in the FP regs if this were a 32-bit function, so that we
2198 can move them to the FP regs if we wind up calling a 32-bit
2199 function. We record this information in fp_code, encoded in base
2200 four. A zero digit means no floating point argument, a one digit
2201 means an SFmode argument, and a two digit means a DFmode argument,
2202 and a three digit is not used. The low order digit is the first
2203 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2204 an SFmode argument. ??? A more sophisticated approach will be
2205 needed if MIPS_ABI != ABI_32. */
2206 int fp_code;
2207
2208 /* True if the function has a prototype. */
2209 int prototype;
2210 } CUMULATIVE_ARGS;
2211
2212 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2213 for a call to a function whose data type is FNTYPE.
2214 For a library call, FNTYPE is 0. */
2215
2216 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2217 mips_init_cumulative_args (&CUM, FNTYPE)
2218
2219 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2220 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2221
2222 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2223 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2224
2225 /* True if using EABI and varargs can be passed in floating-point
2226 registers. Under these conditions, we need a more complex form
2227 of va_list, which tracks GPR, FPR and stack arguments separately. */
2228 #define EABI_FLOAT_VARARGS_P \
2229 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2230
2231 \f
2232 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2233
2234 /* Treat LOC as a byte offset from the stack pointer and round it up
2235 to the next fully-aligned offset. */
2236 #define MIPS_STACK_ALIGN(LOC) \
2237 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2238
2239 \f
2240 /* Output assembler code to FILE to increment profiler label # LABELNO
2241 for profiling a function entry. */
2242
2243 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2244
2245 /* The profiler preserves all interesting registers, including $31. */
2246 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2247
2248 /* No mips port has ever used the profiler counter word, so don't emit it
2249 or the label for it. */
2250
2251 #define NO_PROFILE_COUNTERS 1
2252
2253 /* Define this macro if the code for function profiling should come
2254 before the function prologue. Normally, the profiling code comes
2255 after. */
2256
2257 /* #define PROFILE_BEFORE_PROLOGUE */
2258
2259 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2260 the stack pointer does not matter. The value is tested only in
2261 functions that have frame pointers.
2262 No definition is equivalent to always zero. */
2263
2264 #define EXIT_IGNORE_STACK 1
2265
2266 \f
2267 /* Trampolines are a block of code followed by two pointers. */
2268
2269 #define TRAMPOLINE_SIZE \
2270 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2271
2272 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2273 pointers from a single LUI base. */
2274
2275 #define TRAMPOLINE_ALIGNMENT 64
2276
2277 /* mips_trampoline_init calls this library function to flush
2278 program and data caches. */
2279
2280 #ifndef CACHE_FLUSH_FUNC
2281 #define CACHE_FLUSH_FUNC "_flush_cache"
2282 #endif
2283
2284 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2285 /* Flush both caches. We need to flush the data cache in case \
2286 the system has a write-back cache. */ \
2287 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2288 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2289 GEN_INT (3), TYPE_MODE (integer_type_node))
2290
2291 \f
2292 /* Addressing modes, and classification of registers for them. */
2293
2294 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2295 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2296 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2297 \f
2298 /* Maximum number of registers that can appear in a valid memory address. */
2299
2300 #define MAX_REGS_PER_ADDRESS 1
2301
2302 /* Check for constness inline but use mips_legitimate_address_p
2303 to check whether a constant really is an address. */
2304
2305 #define CONSTANT_ADDRESS_P(X) \
2306 (CONSTANT_P (X) && memory_address_p (SImode, X))
2307
2308 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2309 'the start of the function that this code is output in'. */
2310
2311 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2312 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2313 asm_fprintf ((FILE), "%U%s", \
2314 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2315 else \
2316 asm_fprintf ((FILE), "%U%s", (NAME))
2317 \f
2318 /* Flag to mark a function decl symbol that requires a long call. */
2319 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2320 #define SYMBOL_REF_LONG_CALL_P(X) \
2321 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2322
2323 /* This flag marks functions that cannot be lazily bound. */
2324 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2325 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2326 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2327
2328 /* True if we're generating a form of MIPS16 code in which jump tables
2329 are stored in the text section and encoded as 16-bit PC-relative
2330 offsets. This is only possible when general text loads are allowed,
2331 since the table access itself will be an "lh" instruction. */
2332 /* ??? 16-bit offsets can overflow in large functions. */
2333 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2334
2335 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2336
2337 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2338
2339 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2340
2341 /* Define this as 1 if `char' should by default be signed; else as 0. */
2342 #ifndef DEFAULT_SIGNED_CHAR
2343 #define DEFAULT_SIGNED_CHAR 1
2344 #endif
2345
2346 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2347 we generally don't want to use them for copying arbitrary data.
2348 A single N-word move is usually the same cost as N single-word moves. */
2349 #define MOVE_MAX UNITS_PER_WORD
2350 #define MAX_MOVE_MAX 8
2351
2352 /* Define this macro as a C expression which is nonzero if
2353 accessing less than a word of memory (i.e. a `char' or a
2354 `short') is no faster than accessing a word of memory, i.e., if
2355 such access require more than one instruction or if there is no
2356 difference in cost between byte and (aligned) word loads.
2357
2358 On RISC machines, it tends to generate better code to define
2359 this as 1, since it avoids making a QI or HI mode register.
2360
2361 But, generating word accesses for -mips16 is generally bad as shifts
2362 (often extended) would be needed for byte accesses. */
2363 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2364
2365 /* Standard MIPS integer shifts truncate the shift amount to the
2366 width of the shifted operand. However, Loongson vector shifts
2367 do not truncate the shift amount at all. */
2368 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2369
2370 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2371 is done just by pretending it is already truncated. */
2372 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2373 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2374
2375
2376 /* Specify the machine mode that pointers have.
2377 After generation of rtl, the compiler makes no further distinction
2378 between pointers and any other objects of this machine mode. */
2379
2380 #ifndef Pmode
2381 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2382 #endif
2383
2384 /* Give call MEMs SImode since it is the "most permissive" mode
2385 for both 32-bit and 64-bit targets. */
2386
2387 #define FUNCTION_MODE SImode
2388
2389 \f
2390
2391 /* Define if copies to/from condition code registers should be avoided.
2392
2393 This is needed for the MIPS because reload_outcc is not complete;
2394 it needs to handle cases where the source is a general or another
2395 condition code register. */
2396 #define AVOID_CCMODE_COPIES
2397
2398 /* A C expression for the cost of a branch instruction. A value of
2399 1 is the default; other values are interpreted relative to that. */
2400
2401 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2402 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2403
2404 /* If defined, modifies the length assigned to instruction INSN as a
2405 function of the context in which it is used. LENGTH is an lvalue
2406 that contains the initially computed length of the insn and should
2407 be updated with the correct length of the insn. */
2408 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2409 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2410
2411 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2412 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2413 its operands. */
2414 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2415 "%*" OPCODE "%?\t" OPERANDS "%/"
2416
2417 /* Return an asm string that forces INSN to be treated as an absolute
2418 J or JAL instruction instead of an assembler macro. */
2419 #define MIPS_ABSOLUTE_JUMP(INSN) \
2420 (TARGET_ABICALLS_PIC2 \
2421 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2422 : INSN)
2423
2424 /* Return the asm template for a call. INSN is the instruction's mnemonic
2425 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2426 number of the target. SIZE_OPNO is the operand number of the argument size
2427 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2428 -1 and the call is indirect, use the function symbol from the call
2429 attributes to attach a R_MIPS_JALR relocation to the call.
2430
2431 When generating GOT code without explicit relocation operators,
2432 all calls should use assembly macros. Otherwise, all indirect
2433 calls should use "jr" or "jalr"; we will arrange to restore $gp
2434 afterwards if necessary. Finally, we can only generate direct
2435 calls for -mabicalls by temporarily switching to non-PIC mode. */
2436 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2437 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2438 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2439 : (REG_P (OPERANDS[TARGET_OPNO]) \
2440 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2441 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2442 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2443 : REG_P (OPERANDS[TARGET_OPNO]) \
2444 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2445 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2446 \f
2447 /* Control the assembler format that we output. */
2448
2449 /* Output to assembler file text saying following lines
2450 may contain character constants, extra white space, comments, etc. */
2451
2452 #ifndef ASM_APP_ON
2453 #define ASM_APP_ON " #APP\n"
2454 #endif
2455
2456 /* Output to assembler file text saying following lines
2457 no longer contain unusual constructs. */
2458
2459 #ifndef ASM_APP_OFF
2460 #define ASM_APP_OFF " #NO_APP\n"
2461 #endif
2462
2463 #define REGISTER_NAMES \
2464 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2465 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2466 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2467 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2468 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2469 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2470 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2471 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2472 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2473 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2474 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2475 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2476 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2477 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2478 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2479 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2480 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2481 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2482 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2483 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2484 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2485 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2486 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2487 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2488
2489 /* List the "software" names for each register. Also list the numerical
2490 names for $fp and $sp. */
2491
2492 #define ADDITIONAL_REGISTER_NAMES \
2493 { \
2494 { "$29", 29 + GP_REG_FIRST }, \
2495 { "$30", 30 + GP_REG_FIRST }, \
2496 { "at", 1 + GP_REG_FIRST }, \
2497 { "v0", 2 + GP_REG_FIRST }, \
2498 { "v1", 3 + GP_REG_FIRST }, \
2499 { "a0", 4 + GP_REG_FIRST }, \
2500 { "a1", 5 + GP_REG_FIRST }, \
2501 { "a2", 6 + GP_REG_FIRST }, \
2502 { "a3", 7 + GP_REG_FIRST }, \
2503 { "t0", 8 + GP_REG_FIRST }, \
2504 { "t1", 9 + GP_REG_FIRST }, \
2505 { "t2", 10 + GP_REG_FIRST }, \
2506 { "t3", 11 + GP_REG_FIRST }, \
2507 { "t4", 12 + GP_REG_FIRST }, \
2508 { "t5", 13 + GP_REG_FIRST }, \
2509 { "t6", 14 + GP_REG_FIRST }, \
2510 { "t7", 15 + GP_REG_FIRST }, \
2511 { "s0", 16 + GP_REG_FIRST }, \
2512 { "s1", 17 + GP_REG_FIRST }, \
2513 { "s2", 18 + GP_REG_FIRST }, \
2514 { "s3", 19 + GP_REG_FIRST }, \
2515 { "s4", 20 + GP_REG_FIRST }, \
2516 { "s5", 21 + GP_REG_FIRST }, \
2517 { "s6", 22 + GP_REG_FIRST }, \
2518 { "s7", 23 + GP_REG_FIRST }, \
2519 { "t8", 24 + GP_REG_FIRST }, \
2520 { "t9", 25 + GP_REG_FIRST }, \
2521 { "k0", 26 + GP_REG_FIRST }, \
2522 { "k1", 27 + GP_REG_FIRST }, \
2523 { "gp", 28 + GP_REG_FIRST }, \
2524 { "sp", 29 + GP_REG_FIRST }, \
2525 { "fp", 30 + GP_REG_FIRST }, \
2526 { "ra", 31 + GP_REG_FIRST }, \
2527 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2528 }
2529
2530 /* This is meant to be redefined in the host dependent files. It is a
2531 set of alternative names and regnums for mips coprocessors. */
2532
2533 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2534
2535 #define DBR_OUTPUT_SEQEND(STREAM) \
2536 do \
2537 { \
2538 /* Undo the effect of '%*'. */ \
2539 mips_pop_asm_switch (&mips_nomacro); \
2540 mips_pop_asm_switch (&mips_noreorder); \
2541 /* Emit a blank line after the delay slot for emphasis. */ \
2542 fputs ("\n", STREAM); \
2543 } \
2544 while (0)
2545
2546 /* Use .loc directives for SDB line numbers. */
2547 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2548 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2549
2550 /* The MIPS implementation uses some labels for its own purpose. The
2551 following lists what labels are created, and are all formed by the
2552 pattern $L[a-z].*. The machine independent portion of GCC creates
2553 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2554
2555 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2556 $Lb[0-9]+ Begin blocks for MIPS debug support
2557 $Lc[0-9]+ Label for use in s<xx> operation.
2558 $Le[0-9]+ End blocks for MIPS debug support */
2559
2560 #undef ASM_DECLARE_OBJECT_NAME
2561 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2562 mips_declare_object (STREAM, NAME, "", ":\n")
2563
2564 /* Globalizing directive for a label. */
2565 #define GLOBAL_ASM_OP "\t.globl\t"
2566
2567 /* This says how to define a global common symbol. */
2568
2569 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2570
2571 /* This says how to define a local common symbol (i.e., not visible to
2572 linker). */
2573
2574 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2575 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2576 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2577 #endif
2578
2579 /* This says how to output an external. It would be possible not to
2580 output anything and let undefined symbol become external. However
2581 the assembler uses length information on externals to allocate in
2582 data/sdata bss/sbss, thereby saving exec time. */
2583
2584 #undef ASM_OUTPUT_EXTERNAL
2585 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2586 mips_output_external(STREAM,DECL,NAME)
2587
2588 /* This is how to declare a function name. The actual work of
2589 emitting the label is moved to function_prologue, so that we can
2590 get the line number correctly emitted before the .ent directive,
2591 and after any .file directives. Define as empty so that the function
2592 is not declared before the .ent directive elsewhere. */
2593
2594 #undef ASM_DECLARE_FUNCTION_NAME
2595 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2596
2597 /* This is how to store into the string LABEL
2598 the symbol_ref name of an internal numbered label where
2599 PREFIX is the class of label and NUM is the number within the class.
2600 This is suitable for output with `assemble_name'. */
2601
2602 #undef ASM_GENERATE_INTERNAL_LABEL
2603 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2604 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2605
2606 /* Print debug labels as "foo = ." rather than "foo:" because they should
2607 represent a byte pointer rather than an ISA-encoded address. This is
2608 particularly important for code like:
2609
2610 $LFBxxx = .
2611 .cfi_startproc
2612 ...
2613 .section .gcc_except_table,...
2614 ...
2615 .uleb128 foo-$LFBxxx
2616
2617 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2618 likewise a byte pointer rather than an ISA-encoded address.
2619
2620 At the time of writing, this hook is not used for the function end
2621 label:
2622
2623 $LFExxx:
2624 .end foo
2625
2626 But this doesn't matter, because GAS doesn't treat a pre-.end label
2627 as a MIPS16 one anyway. */
2628
2629 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2630 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2631
2632 /* This is how to output an element of a case-vector that is absolute. */
2633
2634 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2635 fprintf (STREAM, "\t%s\t%sL%d\n", \
2636 ptr_mode == DImode ? ".dword" : ".word", \
2637 LOCAL_LABEL_PREFIX, \
2638 VALUE)
2639
2640 /* This is how to output an element of a case-vector. We can make the
2641 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2642 is supported. */
2643
2644 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2645 do { \
2646 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2647 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2648 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2649 else if (TARGET_GPWORD) \
2650 fprintf (STREAM, "\t%s\t%sL%d\n", \
2651 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2652 LOCAL_LABEL_PREFIX, VALUE); \
2653 else if (TARGET_RTP_PIC) \
2654 { \
2655 /* Make the entry relative to the start of the function. */ \
2656 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2657 fprintf (STREAM, "\t%s\t%sL%d-", \
2658 Pmode == DImode ? ".dword" : ".word", \
2659 LOCAL_LABEL_PREFIX, VALUE); \
2660 assemble_name (STREAM, XSTR (fnsym, 0)); \
2661 fprintf (STREAM, "\n"); \
2662 } \
2663 else \
2664 fprintf (STREAM, "\t%s\t%sL%d\n", \
2665 ptr_mode == DImode ? ".dword" : ".word", \
2666 LOCAL_LABEL_PREFIX, VALUE); \
2667 } while (0)
2668
2669 /* This is how to output an assembler line
2670 that says to advance the location counter
2671 to a multiple of 2**LOG bytes. */
2672
2673 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2674 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2675
2676 /* This is how to output an assembler line to advance the location
2677 counter by SIZE bytes. */
2678
2679 #undef ASM_OUTPUT_SKIP
2680 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2681 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2682
2683 /* This is how to output a string. */
2684 #undef ASM_OUTPUT_ASCII
2685 #define ASM_OUTPUT_ASCII mips_output_ascii
2686
2687 /* Output #ident as a in the read-only data section. */
2688 #undef ASM_OUTPUT_IDENT
2689 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2690 { \
2691 const char *p = STRING; \
2692 int size = strlen (p) + 1; \
2693 switch_to_section (readonly_data_section); \
2694 assemble_string (p, size); \
2695 }
2696 \f
2697 /* Default to -G 8 */
2698 #ifndef MIPS_DEFAULT_GVALUE
2699 #define MIPS_DEFAULT_GVALUE 8
2700 #endif
2701
2702 /* Define the strings to put out for each section in the object file. */
2703 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2704 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2705
2706 #undef READONLY_DATA_SECTION_ASM_OP
2707 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2708 \f
2709 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2710 do \
2711 { \
2712 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2713 TARGET_64BIT ? "daddiu" : "addiu", \
2714 reg_names[STACK_POINTER_REGNUM], \
2715 reg_names[STACK_POINTER_REGNUM], \
2716 TARGET_64BIT ? "sd" : "sw", \
2717 reg_names[REGNO], \
2718 reg_names[STACK_POINTER_REGNUM]); \
2719 } \
2720 while (0)
2721
2722 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2723 do \
2724 { \
2725 mips_push_asm_switch (&mips_noreorder); \
2726 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2727 TARGET_64BIT ? "ld" : "lw", \
2728 reg_names[REGNO], \
2729 reg_names[STACK_POINTER_REGNUM], \
2730 TARGET_64BIT ? "daddu" : "addu", \
2731 reg_names[STACK_POINTER_REGNUM], \
2732 reg_names[STACK_POINTER_REGNUM]); \
2733 mips_pop_asm_switch (&mips_noreorder); \
2734 } \
2735 while (0)
2736
2737 /* How to start an assembler comment.
2738 The leading space is important (the mips native assembler requires it). */
2739 #ifndef ASM_COMMENT_START
2740 #define ASM_COMMENT_START " #"
2741 #endif
2742 \f
2743 #undef SIZE_TYPE
2744 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2745
2746 #undef PTRDIFF_TYPE
2747 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2748
2749 /* The maximum number of bytes that can be copied by one iteration of
2750 a movmemsi loop; see mips_block_move_loop. */
2751 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2752 (UNITS_PER_WORD * 4)
2753
2754 /* The maximum number of bytes that can be copied by a straight-line
2755 implementation of movmemsi; see mips_block_move_straight. We want
2756 to make sure that any loop-based implementation will iterate at
2757 least twice. */
2758 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2759 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2760
2761 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2762 values were determined experimentally by benchmarking with CSiBE.
2763 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2764 for o32 where we have to restore $gp afterwards as well as make an
2765 indirect call), but in practice, bumping this up higher for
2766 TARGET_ABICALLS doesn't make much difference to code size. */
2767
2768 #define MIPS_CALL_RATIO 8
2769
2770 /* Any loop-based implementation of movmemsi will have at least
2771 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2772 moves, so allow individual copies of fewer elements.
2773
2774 When movmemsi is not available, use a value approximating
2775 the length of a memcpy call sequence, so that move_by_pieces
2776 will generate inline code if it is shorter than a function call.
2777 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2778 we'll have to generate a load/store pair for each, halve the
2779 value of MIPS_CALL_RATIO to take that into account. */
2780
2781 #define MOVE_RATIO(speed) \
2782 (HAVE_movmemsi \
2783 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2784 : MIPS_CALL_RATIO / 2)
2785
2786 /* movmemsi is meant to generate code that is at least as good as
2787 move_by_pieces. However, movmemsi effectively uses a by-pieces
2788 implementation both for moves smaller than a word and for word-aligned
2789 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
2790 allow the tree-level optimisers to do such moves by pieces, as it
2791 often exposes other optimization opportunities. We might as well
2792 continue to use movmemsi at the rtl level though, as it produces
2793 better code when scheduling is disabled (such as at -O). */
2794
2795 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2796 (HAVE_movmemsi \
2797 ? (!currently_expanding_to_rtl \
2798 && ((ALIGN) < BITS_PER_WORD \
2799 ? (SIZE) < UNITS_PER_WORD \
2800 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
2801 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2802 < (unsigned int) MOVE_RATIO (false)))
2803
2804 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2805 of the length of a memset call, but use the default otherwise. */
2806
2807 #define CLEAR_RATIO(speed)\
2808 ((speed) ? 15 : MIPS_CALL_RATIO)
2809
2810 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2811 optimizing for size adjust the ratio to account for the overhead of
2812 loading the constant and replicating it across the word. */
2813
2814 #define SET_RATIO(speed) \
2815 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2816
2817 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2818 in that case each word takes 3 insns (lui, ori, sw), or more in
2819 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2820 and let the move_by_pieces code copy the string from read-only
2821 memory. In the future, this could be tuned further for multi-issue
2822 CPUs that can issue stores down one pipe and arithmetic instructions
2823 down another; in that case, the lui/ori/sw combination would be a
2824 win for long enough strings. */
2825
2826 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2827 \f
2828 #ifndef __mips16
2829 /* Since the bits of the _init and _fini function is spread across
2830 many object files, each potentially with its own GP, we must assume
2831 we need to load our GP. We don't preserve $gp or $ra, since each
2832 init/fini chunk is supposed to initialize $gp, and crti/crtn
2833 already take care of preserving $ra and, when appropriate, $gp. */
2834 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2835 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2836 asm (SECTION_OP "\n\
2837 .set noreorder\n\
2838 bal 1f\n\
2839 nop\n\
2840 1: .cpload $31\n\
2841 .set reorder\n\
2842 jal " USER_LABEL_PREFIX #FUNC "\n\
2843 " TEXT_SECTION_ASM_OP);
2844 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2845 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2846 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2847 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2848 asm (SECTION_OP "\n\
2849 .set noreorder\n\
2850 bal 1f\n\
2851 nop\n\
2852 1: .set reorder\n\
2853 .cpsetup $31, $2, 1b\n\
2854 jal " USER_LABEL_PREFIX #FUNC "\n\
2855 " TEXT_SECTION_ASM_OP);
2856 #endif
2857 #endif
2858
2859 #ifndef HAVE_AS_TLS
2860 #define HAVE_AS_TLS 0
2861 #endif
2862
2863 #ifndef USED_FOR_TARGET
2864 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2865 struct mips_asm_switch {
2866 /* The FOO in the description above. */
2867 const char *name;
2868
2869 /* The current block nesting level, or 0 if we aren't in a block. */
2870 int nesting_level;
2871 };
2872
2873 extern const enum reg_class mips_regno_to_class[];
2874 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2875 extern const char *current_function_file; /* filename current function is in */
2876 extern int num_source_filenames; /* current .file # */
2877 extern struct mips_asm_switch mips_noreorder;
2878 extern struct mips_asm_switch mips_nomacro;
2879 extern struct mips_asm_switch mips_noat;
2880 extern int mips_dbx_regno[];
2881 extern int mips_dwarf_regno[];
2882 extern bool mips_split_p[];
2883 extern bool mips_split_hi_p[];
2884 extern enum processor mips_arch; /* which cpu to codegen for */
2885 extern enum processor mips_tune; /* which cpu to schedule for */
2886 extern int mips_isa; /* architectural level */
2887 extern const struct mips_cpu_info *mips_arch_info;
2888 extern const struct mips_cpu_info *mips_tune_info;
2889 extern bool mips_base_mips16;
2890 extern GTY(()) struct target_globals *mips16_globals;
2891 #endif
2892
2893 /* Enable querying of DFA units. */
2894 #define CPU_UNITS_QUERY 1
2895
2896 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2897 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2898
2899 /* As on most targets, we want the .eh_frame section to be read-only where
2900 possible. And as on most targets, this means two things:
2901
2902 (a) Non-locally-binding pointers must have an indirect encoding,
2903 so that the addresses in the .eh_frame section itself become
2904 locally-binding.
2905
2906 (b) A shared library's .eh_frame section must encode locally-binding
2907 pointers in a relative (relocation-free) form.
2908
2909 However, MIPS has traditionally not allowed directives like:
2910
2911 .long x-.
2912
2913 in cases where "x" is in a different section, or is not defined in the
2914 same assembly file. We are therefore unable to emit the PC-relative
2915 form required by (b) at assembly time.
2916
2917 Fortunately, the linker is able to convert absolute addresses into
2918 PC-relative addresses on our behalf. Unfortunately, only certain
2919 versions of the linker know how to do this for indirect pointers,
2920 and for personality data. We must fall back on using writable
2921 .eh_frame sections for shared libraries if the linker does not
2922 support this feature. */
2923 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2924 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2925
2926 /* For switching between MIPS16 and non-MIPS16 modes. */
2927 #define SWITCHABLE_TARGET 1