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mips.h (ISA_HAS_NMADD4_NMSUB4): Remove TARGET_MIPS5400 checking.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS64 (mips_isa == 64)
212 #define ISA_MIPS64R2 (mips_isa == 65)
213
214 /* Architecture target defines. */
215 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
216 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
217 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
218 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
219 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
220 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
221 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
222 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
223 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
224 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
225 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
226 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
227 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
228 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
229 || mips_arch == PROCESSOR_OCTEON2)
230 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
231 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
232 || mips_arch == PROCESSOR_SB1A)
233 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
234 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
235
236 /* Scheduling target defines. */
237 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
238 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
239 || mips_tune == PROCESSOR_24KF2_1 \
240 || mips_tune == PROCESSOR_24KF1_1)
241 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
242 || mips_tune == PROCESSOR_74KF2_1 \
243 || mips_tune == PROCESSOR_74KF1_1 \
244 || mips_tune == PROCESSOR_74KF3_2)
245 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
246 || mips_tune == PROCESSOR_LOONGSON_2F)
247 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
248 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
249 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
250 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
251 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
252 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
253 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
254 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
255 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
256 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
257 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
258 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
259 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
260 || mips_tune == PROCESSOR_OCTEON2)
261 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
262 || mips_tune == PROCESSOR_SB1A)
263
264 /* Whether vector modes and intrinsics for ST Microelectronics
265 Loongson-2E/2F processors should be enabled. In o32 pairs of
266 floating-point registers provide 64-bit values. */
267 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
268 && (TARGET_LOONGSON_2EF \
269 || TARGET_LOONGSON_3A))
270
271 /* True if the pre-reload scheduler should try to create chains of
272 multiply-add or multiply-subtract instructions. For example,
273 suppose we have:
274
275 t1 = a * b
276 t2 = t1 + c * d
277 t3 = e * f
278 t4 = t3 - g * h
279
280 t1 will have a higher priority than t2 and t3 will have a higher
281 priority than t4. However, before reload, there is no dependence
282 between t1 and t3, and they can often have similar priorities.
283 The scheduler will then tend to prefer:
284
285 t1 = a * b
286 t3 = e * f
287 t2 = t1 + c * d
288 t4 = t3 - g * h
289
290 which stops us from making full use of macc/madd-style instructions.
291 This sort of situation occurs frequently in Fourier transforms and
292 in unrolled loops.
293
294 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
295 queue so that chained multiply-add and multiply-subtract instructions
296 appear ahead of any other instruction that is likely to clobber lo.
297 In the example above, if t2 and t3 become ready at the same time,
298 the code ensures that t2 is scheduled first.
299
300 Multiply-accumulate instructions are a bigger win for some targets
301 than others, so this macro is defined on an opt-in basis. */
302 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
303 || TUNE_MIPS4120 \
304 || TUNE_MIPS4130 \
305 || TUNE_24K)
306
307 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
308 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
309
310 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
311 directly accessible, while the command-line options select
312 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
313 in use. */
314 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
315 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
316
317 /* False if SC acts as a memory barrier with respect to itself,
318 otherwise a SYNC will be emitted after SC for atomic operations
319 that require ordering between the SC and following loads and
320 stores. It does not tell anything about ordering of loads and
321 stores prior to and following the SC, only about the SC itself and
322 those loads and stores follow it. */
323 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
324
325 /* Define preprocessor macros for the -march and -mtune options.
326 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
327 processor. If INFO's canonical name is "foo", define PREFIX to
328 be "foo", and define an additional macro PREFIX_FOO. */
329 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
330 do \
331 { \
332 char *macro, *p; \
333 \
334 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
335 for (p = macro; *p != 0; p++) \
336 if (*p == '+') \
337 *p = 'P'; \
338 else \
339 *p = TOUPPER (*p); \
340 \
341 builtin_define (macro); \
342 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
343 free (macro); \
344 } \
345 while (0)
346
347 /* Target CPU builtins. */
348 #define TARGET_CPU_CPP_BUILTINS() \
349 do \
350 { \
351 builtin_assert ("machine=mips"); \
352 builtin_assert ("cpu=mips"); \
353 builtin_define ("__mips__"); \
354 builtin_define ("_mips"); \
355 \
356 /* We do this here because __mips is defined below and so we \
357 can't use builtin_define_std. We don't ever want to define \
358 "mips" for VxWorks because some of the VxWorks headers \
359 construct include filenames from a root directory macro, \
360 an architecture macro and a filename, where the architecture \
361 macro expands to 'mips'. If we define 'mips' to 1, the \
362 architecture macro expands to 1 as well. */ \
363 if (!flag_iso && !TARGET_VXWORKS) \
364 builtin_define ("mips"); \
365 \
366 if (TARGET_64BIT) \
367 builtin_define ("__mips64"); \
368 \
369 /* Treat _R3000 and _R4000 like register-size \
370 defines, which is how they've historically \
371 been used. */ \
372 if (TARGET_64BIT) \
373 { \
374 builtin_define_std ("R4000"); \
375 builtin_define ("_R4000"); \
376 } \
377 else \
378 { \
379 builtin_define_std ("R3000"); \
380 builtin_define ("_R3000"); \
381 } \
382 \
383 if (TARGET_FLOAT64) \
384 builtin_define ("__mips_fpr=64"); \
385 else \
386 builtin_define ("__mips_fpr=32"); \
387 \
388 if (mips_base_compression_flags & MASK_MIPS16) \
389 builtin_define ("__mips16"); \
390 \
391 if (TARGET_MIPS3D) \
392 builtin_define ("__mips3d"); \
393 \
394 if (TARGET_SMARTMIPS) \
395 builtin_define ("__mips_smartmips"); \
396 \
397 if (mips_base_compression_flags & MASK_MICROMIPS) \
398 builtin_define ("__mips_micromips"); \
399 \
400 if (TARGET_MCU) \
401 builtin_define ("__mips_mcu"); \
402 \
403 if (TARGET_EVA) \
404 builtin_define ("__mips_eva"); \
405 \
406 if (TARGET_DSP) \
407 { \
408 builtin_define ("__mips_dsp"); \
409 if (TARGET_DSPR2) \
410 { \
411 builtin_define ("__mips_dspr2"); \
412 builtin_define ("__mips_dsp_rev=2"); \
413 } \
414 else \
415 builtin_define ("__mips_dsp_rev=1"); \
416 } \
417 \
418 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
419 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
420 \
421 if (ISA_MIPS1) \
422 { \
423 builtin_define ("__mips=1"); \
424 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
425 } \
426 else if (ISA_MIPS2) \
427 { \
428 builtin_define ("__mips=2"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
430 } \
431 else if (ISA_MIPS3) \
432 { \
433 builtin_define ("__mips=3"); \
434 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
435 } \
436 else if (ISA_MIPS4) \
437 { \
438 builtin_define ("__mips=4"); \
439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
440 } \
441 else if (ISA_MIPS32) \
442 { \
443 builtin_define ("__mips=32"); \
444 builtin_define ("__mips_isa_rev=1"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
446 } \
447 else if (ISA_MIPS32R2) \
448 { \
449 builtin_define ("__mips=32"); \
450 builtin_define ("__mips_isa_rev=2"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
452 } \
453 else if (ISA_MIPS64) \
454 { \
455 builtin_define ("__mips=64"); \
456 builtin_define ("__mips_isa_rev=1"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
458 } \
459 else if (ISA_MIPS64R2) \
460 { \
461 builtin_define ("__mips=64"); \
462 builtin_define ("__mips_isa_rev=2"); \
463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
464 } \
465 \
466 switch (mips_abi) \
467 { \
468 case ABI_32: \
469 builtin_define ("_ABIO32=1"); \
470 builtin_define ("_MIPS_SIM=_ABIO32"); \
471 break; \
472 \
473 case ABI_N32: \
474 builtin_define ("_ABIN32=2"); \
475 builtin_define ("_MIPS_SIM=_ABIN32"); \
476 break; \
477 \
478 case ABI_64: \
479 builtin_define ("_ABI64=3"); \
480 builtin_define ("_MIPS_SIM=_ABI64"); \
481 break; \
482 \
483 case ABI_O64: \
484 builtin_define ("_ABIO64=4"); \
485 builtin_define ("_MIPS_SIM=_ABIO64"); \
486 break; \
487 } \
488 \
489 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
490 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
491 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
492 builtin_define_with_int_value ("_MIPS_FPSET", \
493 32 / MAX_FPRS_PER_FMT); \
494 \
495 /* These defines reflect the ABI in use, not whether the \
496 FPU is directly accessible. */ \
497 if (TARGET_NO_FLOAT) \
498 builtin_define ("__mips_no_float"); \
499 else if (TARGET_HARD_FLOAT_ABI) \
500 builtin_define ("__mips_hard_float"); \
501 else \
502 builtin_define ("__mips_soft_float"); \
503 \
504 if (TARGET_SINGLE_FLOAT) \
505 builtin_define ("__mips_single_float"); \
506 \
507 if (TARGET_PAIRED_SINGLE_FLOAT) \
508 builtin_define ("__mips_paired_single_float"); \
509 \
510 if (TARGET_BIG_ENDIAN) \
511 { \
512 builtin_define_std ("MIPSEB"); \
513 builtin_define ("_MIPSEB"); \
514 } \
515 else \
516 { \
517 builtin_define_std ("MIPSEL"); \
518 builtin_define ("_MIPSEL"); \
519 } \
520 \
521 /* Whether calls should go through $25. The separate __PIC__ \
522 macro indicates whether abicalls code might use a GOT. */ \
523 if (TARGET_ABICALLS) \
524 builtin_define ("__mips_abicalls"); \
525 \
526 /* Whether Loongson vector modes are enabled. */ \
527 if (TARGET_LOONGSON_VECTORS) \
528 builtin_define ("__mips_loongson_vector_rev"); \
529 \
530 /* Historical Octeon macro. */ \
531 if (TARGET_OCTEON) \
532 builtin_define ("__OCTEON__"); \
533 \
534 if (TARGET_SYNCI) \
535 builtin_define ("__mips_synci"); \
536 \
537 /* Macros dependent on the C dialect. */ \
538 if (preprocessing_asm_p ()) \
539 { \
540 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
541 builtin_define ("_LANGUAGE_ASSEMBLY"); \
542 } \
543 else if (c_dialect_cxx ()) \
544 { \
545 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
546 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
547 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
548 } \
549 else \
550 { \
551 builtin_define_std ("LANGUAGE_C"); \
552 builtin_define ("_LANGUAGE_C"); \
553 } \
554 if (c_dialect_objc ()) \
555 { \
556 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
557 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
558 /* Bizarre, but retained for backwards compatibility. */ \
559 builtin_define_std ("LANGUAGE_C"); \
560 builtin_define ("_LANGUAGE_C"); \
561 } \
562 \
563 if (mips_abi == ABI_EABI) \
564 builtin_define ("__mips_eabi"); \
565 \
566 if (TARGET_CACHE_BUILTIN) \
567 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
568 } \
569 while (0)
570
571 /* Default target_flags if no switches are specified */
572
573 #ifndef TARGET_DEFAULT
574 #define TARGET_DEFAULT 0
575 #endif
576
577 #ifndef TARGET_CPU_DEFAULT
578 #define TARGET_CPU_DEFAULT 0
579 #endif
580
581 #ifndef TARGET_ENDIAN_DEFAULT
582 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
583 #endif
584
585 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
586 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
587 #endif
588
589 #ifdef IN_LIBGCC2
590 #undef TARGET_64BIT
591 /* Make this compile time constant for libgcc2 */
592 #ifdef __mips64
593 #define TARGET_64BIT 1
594 #else
595 #define TARGET_64BIT 0
596 #endif
597 #endif /* IN_LIBGCC2 */
598
599 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
600 when compiled with hardware floating point. This is because MIPS16
601 code cannot save and restore the floating-point registers, which is
602 important if in a mixed MIPS16/non-MIPS16 environment. */
603
604 #ifdef IN_LIBGCC2
605 #if __mips_hard_float
606 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
607 #endif
608 #endif /* IN_LIBGCC2 */
609
610 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
611
612 #ifndef MULTILIB_ENDIAN_DEFAULT
613 #if TARGET_ENDIAN_DEFAULT == 0
614 #define MULTILIB_ENDIAN_DEFAULT "EL"
615 #else
616 #define MULTILIB_ENDIAN_DEFAULT "EB"
617 #endif
618 #endif
619
620 #ifndef MULTILIB_ISA_DEFAULT
621 #if MIPS_ISA_DEFAULT == 1
622 #define MULTILIB_ISA_DEFAULT "mips1"
623 #elif MIPS_ISA_DEFAULT == 2
624 #define MULTILIB_ISA_DEFAULT "mips2"
625 #elif MIPS_ISA_DEFAULT == 3
626 #define MULTILIB_ISA_DEFAULT "mips3"
627 #elif MIPS_ISA_DEFAULT == 4
628 #define MULTILIB_ISA_DEFAULT "mips4"
629 #elif MIPS_ISA_DEFAULT == 32
630 #define MULTILIB_ISA_DEFAULT "mips32"
631 #elif MIPS_ISA_DEFAULT == 33
632 #define MULTILIB_ISA_DEFAULT "mips32r2"
633 #elif MIPS_ISA_DEFAULT == 64
634 #define MULTILIB_ISA_DEFAULT "mips64"
635 #elif MIPS_ISA_DEFAULT == 65
636 #define MULTILIB_ISA_DEFAULT "mips64r2"
637 #else
638 #define MULTILIB_ISA_DEFAULT "mips1"
639 #endif
640 #endif
641
642 #ifndef MIPS_ABI_DEFAULT
643 #define MIPS_ABI_DEFAULT ABI_32
644 #endif
645
646 /* Use the most portable ABI flag for the ASM specs. */
647
648 #if MIPS_ABI_DEFAULT == ABI_32
649 #define MULTILIB_ABI_DEFAULT "mabi=32"
650 #elif MIPS_ABI_DEFAULT == ABI_O64
651 #define MULTILIB_ABI_DEFAULT "mabi=o64"
652 #elif MIPS_ABI_DEFAULT == ABI_N32
653 #define MULTILIB_ABI_DEFAULT "mabi=n32"
654 #elif MIPS_ABI_DEFAULT == ABI_64
655 #define MULTILIB_ABI_DEFAULT "mabi=64"
656 #elif MIPS_ABI_DEFAULT == ABI_EABI
657 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
658 #endif
659
660 #ifndef MULTILIB_DEFAULTS
661 #define MULTILIB_DEFAULTS \
662 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
663 #endif
664
665 /* We must pass -EL to the linker by default for little endian embedded
666 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
667 linker will default to using big-endian output files. The OUTPUT_FORMAT
668 line must be in the linker script, otherwise -EB/-EL will not work. */
669
670 #ifndef ENDIAN_SPEC
671 #if TARGET_ENDIAN_DEFAULT == 0
672 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
673 #else
674 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
675 #endif
676 #endif
677
678 /* A spec condition that matches all non-mips16 -mips arguments. */
679
680 #define MIPS_ISA_LEVEL_OPTION_SPEC \
681 "mips1|mips2|mips3|mips4|mips32*|mips64*"
682
683 /* A spec condition that matches all non-mips16 architecture arguments. */
684
685 #define MIPS_ARCH_OPTION_SPEC \
686 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
687
688 /* A spec that infers a -mips argument from an -march argument,
689 or injects the default if no architecture is specified. */
690
691 #define MIPS_ISA_LEVEL_SPEC \
692 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
693 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
694 %{march=mips2|march=r6000:-mips2} \
695 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
696 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
697 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
698 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
699 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
700 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
701 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
702 |march=xlr|march=loongson3a: -mips64} \
703 %{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
704 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
705
706 /* A spec that infers a -mhard-float or -msoft-float setting from an
707 -march argument. Note that soft-float and hard-float code are not
708 link-compatible. */
709
710 #define MIPS_ARCH_FLOAT_SPEC \
711 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
712 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
713 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
714 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
715 march=*: -mhard-float}"
716
717 /* A spec condition that matches 32-bit options. It only works if
718 MIPS_ISA_LEVEL_SPEC has been applied. */
719
720 #define MIPS_32BIT_OPTION_SPEC \
721 "mips1|mips2|mips32*|mgp32"
722
723 /* Infer a -msynci setting from a -mips argument, on the assumption that
724 -msynci is desired where possible. */
725 #define MIPS_ISA_SYNCI_SPEC \
726 "%{msynci|mno-synci:;:%{mips32r2|mips64r2:-msynci;:-mno-synci}}"
727
728 #if (MIPS_ABI_DEFAULT == ABI_O64 \
729 || MIPS_ABI_DEFAULT == ABI_N32 \
730 || MIPS_ABI_DEFAULT == ABI_64)
731 #define OPT_ARCH64 "mabi=32|mgp32:;"
732 #define OPT_ARCH32 "mabi=32|mgp32"
733 #else
734 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
735 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
736 #endif
737
738 /* Support for a compile-time default CPU, et cetera. The rules are:
739 --with-arch is ignored if -march is specified or a -mips is specified
740 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
741 --with-tune is ignored if -mtune is specified; likewise
742 --with-tune-32 and --with-tune-64.
743 --with-abi is ignored if -mabi is specified.
744 --with-float is ignored if -mhard-float or -msoft-float are
745 specified.
746 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
747 specified. */
748 #define OPTION_DEFAULT_SPECS \
749 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
750 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
751 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
752 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
753 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
754 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
755 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
756 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
757 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
758 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
759 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
760 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
761
762 /* A spec that infers the -mdsp setting from an -march argument. */
763 #define BASE_DRIVER_SELF_SPECS \
764 "%{!mno-dsp: \
765 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
766 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
767
768 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
769
770 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
771 && ISA_HAS_COND_TRAP)
772
773 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
774
775 /* True if the ABI can only work with 64-bit integer registers. We
776 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
777 otherwise floating-point registers must also be 64-bit. */
778 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
779
780 /* Likewise for 32-bit regs. */
781 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
782
783 /* True if the file format uses 64-bit symbols. At present, this is
784 only true for n64, which uses 64-bit ELF. */
785 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
786
787 /* True if symbols are 64 bits wide. This is usually determined by
788 the ABI's file format, but it can be overridden by -msym32. Note that
789 overriding the size with -msym32 changes the ABI of relocatable objects,
790 although it doesn't change the ABI of a fully-linked object. */
791 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
792 && Pmode == DImode \
793 && !TARGET_SYM32)
794
795 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
796 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
797 || ISA_MIPS4 \
798 || ISA_MIPS64 \
799 || ISA_MIPS64R2)
800
801 /* ISA has branch likely instructions (e.g. mips2). */
802 /* Disable branchlikely for tx39 until compare rewrite. They haven't
803 been generated up to this point. */
804 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
805
806 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
807 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
808 || TARGET_MIPS5400 \
809 || TARGET_MIPS5500 \
810 || TARGET_MIPS5900 \
811 || TARGET_MIPS7000 \
812 || TARGET_MIPS9000 \
813 || TARGET_MAD \
814 || ISA_MIPS32 \
815 || ISA_MIPS32R2 \
816 || ISA_MIPS64 \
817 || ISA_MIPS64R2) \
818 && !TARGET_MIPS16)
819
820 /* ISA has a three-operand multiplication instruction. */
821 #define ISA_HAS_DMUL3 (TARGET_64BIT \
822 && TARGET_OCTEON \
823 && !TARGET_MIPS16)
824
825 /* ISA supports instructions DMULT and DMULTU. */
826 #define ISA_HAS_DMULT (TARGET_64BIT && !TARGET_MIPS5900)
827
828 /* ISA supports instructions MULT and MULTU.
829 This is always true, but the macro is needed for ISA_HAS_<D>MULT
830 in mips.md. */
831 #define ISA_HAS_MULT (1)
832
833 /* ISA supports instructions DDIV and DDIVU. */
834 #define ISA_HAS_DDIV (TARGET_64BIT && !TARGET_MIPS5900)
835
836 /* ISA supports instructions DIV and DIVU.
837 This is always true, but the macro is needed for ISA_HAS_<D>DIV
838 in mips.md. */
839 #define ISA_HAS_DIV (1)
840
841 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
842 || TARGET_LOONGSON_3A) \
843 && !TARGET_MIPS16)
844
845 /* ISA has the floating-point conditional move instructions introduced
846 in mips4. */
847 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
848 || ISA_MIPS32 \
849 || ISA_MIPS32R2 \
850 || ISA_MIPS64 \
851 || ISA_MIPS64R2) \
852 && !TARGET_MIPS5500 \
853 && !TARGET_MIPS16)
854
855 /* ISA has the integer conditional move instructions introduced in mips4 and
856 ST Loongson 2E/2F. */
857 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
858 || TARGET_MIPS5900 \
859 || TARGET_LOONGSON_2EF)
860
861 /* ISA has LDC1 and SDC1. */
862 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
863
864 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
865 branch on CC, and move (both FP and non-FP) on CC. */
866 #define ISA_HAS_8CC (ISA_MIPS4 \
867 || ISA_MIPS32 \
868 || ISA_MIPS32R2 \
869 || ISA_MIPS64 \
870 || ISA_MIPS64R2)
871
872 /* This is a catch all for other mips4 instructions: indexed load, the
873 FP madd and msub instructions, and the FP recip and recip sqrt
874 instructions. */
875 #define ISA_HAS_FP4 ((ISA_MIPS4 \
876 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
877 || ISA_MIPS64 \
878 || ISA_MIPS64R2) \
879 && !TARGET_MIPS16)
880
881 /* ISA has paired-single instructions. */
882 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
883
884 /* ISA has conditional trap instructions. */
885 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
886 && !TARGET_MIPS16)
887
888 /* ISA has integer multiply-accumulate instructions, madd and msub. */
889 #define ISA_HAS_MADD_MSUB (ISA_MIPS32 \
890 || ISA_MIPS32R2 \
891 || ISA_MIPS64 \
892 || ISA_MIPS64R2)
893
894 /* Integer multiply-accumulate instructions should be generated. */
895 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
896
897 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
898 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
899
900 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
901 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
902
903 /* ISA has floating-point nmadd and nmsub instructions
904 'd = -((a * b) [+-] c)'. */
905 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
906 ((ISA_MIPS4 \
907 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
908 || ISA_MIPS64 \
909 || ISA_MIPS64R2) \
910 && !TARGET_MIPS16)
911
912 /* ISA has floating-point nmadd and nmsub instructions
913 'c = -((a * b) [+-] c)'. */
914 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
915 TARGET_LOONGSON_2EF
916
917 /* ISA has count leading zeroes/ones instruction (not implemented). */
918 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
919 || ISA_MIPS32R2 \
920 || ISA_MIPS64 \
921 || ISA_MIPS64R2) \
922 && !TARGET_MIPS16)
923
924 /* ISA has three operand multiply instructions that put
925 the high part in an accumulator: mulhi or mulhiu. */
926 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
927 || TARGET_MIPS5500 \
928 || TARGET_SR71K) \
929 && !TARGET_MIPS16)
930
931 /* ISA has three operand multiply instructions that negate the
932 result and put the result in an accumulator. */
933 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
934 || TARGET_MIPS5500 \
935 || TARGET_SR71K) \
936 && !TARGET_MIPS16)
937
938 /* ISA has three operand multiply instructions that subtract the
939 result from a 4th operand and put the result in an accumulator. */
940 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
941 || TARGET_MIPS5500 \
942 || TARGET_SR71K) \
943 && !TARGET_MIPS16)
944
945 /* ISA has three operand multiply instructions that add the result
946 to a 4th operand and put the result in an accumulator. */
947 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
948 || TARGET_MIPS4130 \
949 || TARGET_MIPS5400 \
950 || TARGET_MIPS5500 \
951 || TARGET_SR71K) \
952 && !TARGET_MIPS16)
953
954 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
955 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
956 || TARGET_MIPS4130) \
957 && !TARGET_MIPS16)
958
959 /* ISA has the "ror" (rotate right) instructions. */
960 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
961 || ISA_MIPS64R2 \
962 || TARGET_MIPS5400 \
963 || TARGET_MIPS5500 \
964 || TARGET_SR71K \
965 || TARGET_SMARTMIPS) \
966 && !TARGET_MIPS16)
967
968 /* ISA has data prefetch instructions. This controls use of 'pref'. */
969 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
970 || TARGET_LOONGSON_2EF \
971 || TARGET_MIPS5900 \
972 || ISA_MIPS32 \
973 || ISA_MIPS32R2 \
974 || ISA_MIPS64 \
975 || ISA_MIPS64R2) \
976 && !TARGET_MIPS16)
977
978 /* ISA has data indexed prefetch instructions. This controls use of
979 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
980 (prefx is a cop1x instruction, so can only be used if FP is
981 enabled.) */
982 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
983 || ISA_MIPS32R2 \
984 || ISA_MIPS64 \
985 || ISA_MIPS64R2) \
986 && !TARGET_MIPS16)
987
988 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
989 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
990 also requires TARGET_DOUBLE_FLOAT. */
991 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
992
993 /* ISA includes the MIPS32r2 seb and seh instructions. */
994 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
995 || ISA_MIPS64R2) \
996 && !TARGET_MIPS16)
997
998 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
999 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
1000 || ISA_MIPS64R2) \
1001 && !TARGET_MIPS16)
1002
1003 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1004 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
1005 && (ISA_MIPS32R2 \
1006 || ISA_MIPS64R2))
1007
1008 /* ISA has lwxs instruction (load w/scaled index address. */
1009 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1010 && !TARGET_MIPS16)
1011
1012 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1013 #define ISA_HAS_LBX (TARGET_OCTEON2)
1014 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1015 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1016 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1017 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1018 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1019 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1020 && TARGET_64BIT)
1021
1022 /* The DSP ASE is available. */
1023 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1024
1025 /* Revision 2 of the DSP ASE is available. */
1026 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1027
1028 /* True if the result of a load is not available to the next instruction.
1029 A nop will then be needed between instructions like "lw $4,..."
1030 and "addiu $4,$4,1". */
1031 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1032 && !TARGET_MIPS3900 \
1033 && !TARGET_MIPS5900 \
1034 && !TARGET_MIPS16 \
1035 && !TARGET_MICROMIPS)
1036
1037 /* Likewise mtc1 and mfc1. */
1038 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1039 && !TARGET_MIPS5900 \
1040 && !TARGET_LOONGSON_2EF)
1041
1042 /* Likewise floating-point comparisons. */
1043 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1044 && !TARGET_MIPS5900 \
1045 && !TARGET_LOONGSON_2EF)
1046
1047 /* True if mflo and mfhi can be immediately followed by instructions
1048 which write to the HI and LO registers.
1049
1050 According to MIPS specifications, MIPS ISAs I, II, and III need
1051 (at least) two instructions between the reads of HI/LO and
1052 instructions which write them, and later ISAs do not. Contradicting
1053 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1054 the UM for the NEC Vr5000) document needing the instructions between
1055 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1056 MIPS64 and later ISAs to have the interlocks, plus any specific
1057 earlier-ISA CPUs for which CPU documentation declares that the
1058 instructions are really interlocked. */
1059 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1060 || ISA_MIPS32R2 \
1061 || ISA_MIPS64 \
1062 || ISA_MIPS64R2 \
1063 || TARGET_MIPS5500 \
1064 || TARGET_MIPS5900 \
1065 || TARGET_LOONGSON_2EF)
1066
1067 /* ISA includes synci, jr.hb and jalr.hb. */
1068 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1069 || ISA_MIPS64R2) \
1070 && !TARGET_MIPS16)
1071
1072 /* ISA includes sync. */
1073 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1074 #define GENERATE_SYNC \
1075 (target_flags_explicit & MASK_LLSC \
1076 ? TARGET_LLSC && !TARGET_MIPS16 \
1077 : ISA_HAS_SYNC)
1078
1079 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1080 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1081 instructions. */
1082 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1083 #define GENERATE_LL_SC \
1084 (target_flags_explicit & MASK_LLSC \
1085 ? TARGET_LLSC && !TARGET_MIPS16 \
1086 : ISA_HAS_LL_SC)
1087
1088 #define ISA_HAS_SWAP (TARGET_XLP)
1089 #define ISA_HAS_LDADD (TARGET_XLP)
1090
1091 /* ISA includes the baddu instruction. */
1092 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1093
1094 /* ISA includes the bbit* instructions. */
1095 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1096
1097 /* ISA includes the cins instruction. */
1098 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1099
1100 /* ISA includes the exts instruction. */
1101 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1102
1103 /* ISA includes the seq and sne instructions. */
1104 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1105
1106 /* ISA includes the pop instruction. */
1107 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1108
1109 /* The CACHE instruction is available in non-MIPS16 code. */
1110 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1111
1112 /* The CACHE instruction is available. */
1113 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1114 \f
1115 /* Tell collect what flags to pass to nm. */
1116 #ifndef NM_FLAGS
1117 #define NM_FLAGS "-Bn"
1118 #endif
1119
1120 \f
1121 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1122 the assembler. It may be overridden by subtargets.
1123
1124 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1125 COFF debugging info. */
1126
1127 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1128 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1129 %{g} %{g0} %{g1} %{g2} %{g3} \
1130 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1131 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1132 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1133 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1134 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1135 #endif
1136
1137 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1138 overridden by subtargets. */
1139
1140 #ifndef SUBTARGET_ASM_SPEC
1141 #define SUBTARGET_ASM_SPEC ""
1142 #endif
1143
1144 #undef ASM_SPEC
1145 #define ASM_SPEC "\
1146 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1147 %{mips32*} %{mips64*} \
1148 %{mips16} %{mno-mips16:-no-mips16} \
1149 %{mmicromips} %{mno-micromips} \
1150 %{mips3d} %{mno-mips3d:-no-mips3d} \
1151 %{mdmx} %{mno-mdmx:-no-mdmx} \
1152 %{mdsp} %{mno-dsp} \
1153 %{mdspr2} %{mno-dspr2} \
1154 %{mmcu} %{mno-mcu} \
1155 %{meva} %{mno-eva} \
1156 %{msmartmips} %{mno-smartmips} \
1157 %{mmt} %{mno-mt} \
1158 %{mfix-vr4120} %{mfix-vr4130} \
1159 %{mfix-24k} \
1160 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1161 %(subtarget_asm_debugging_spec) \
1162 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1163 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1164 %{mfp32} %{mfp64} \
1165 %{mshared} %{mno-shared} \
1166 %{msym32} %{mno-sym32} \
1167 %{mtune=*} \
1168 %(subtarget_asm_spec)"
1169
1170 /* Extra switches sometimes passed to the linker. */
1171
1172 #ifndef LINK_SPEC
1173 #define LINK_SPEC "\
1174 %(endian_spec) \
1175 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1176 %{shared}"
1177 #endif /* LINK_SPEC defined */
1178
1179
1180 /* Specs for the compiler proper */
1181
1182 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1183 overridden by subtargets. */
1184 #ifndef SUBTARGET_CC1_SPEC
1185 #define SUBTARGET_CC1_SPEC ""
1186 #endif
1187
1188 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1189
1190 #undef CC1_SPEC
1191 #define CC1_SPEC "\
1192 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1193 %(subtarget_cc1_spec)"
1194
1195 /* Preprocessor specs. */
1196
1197 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1198 overridden by subtargets. */
1199 #ifndef SUBTARGET_CPP_SPEC
1200 #define SUBTARGET_CPP_SPEC ""
1201 #endif
1202
1203 #define CPP_SPEC "%(subtarget_cpp_spec)"
1204
1205 /* This macro defines names of additional specifications to put in the specs
1206 that can be used in various specifications like CC1_SPEC. Its definition
1207 is an initializer with a subgrouping for each command option.
1208
1209 Each subgrouping contains a string constant, that defines the
1210 specification name, and a string constant that used by the GCC driver
1211 program.
1212
1213 Do not define this macro if it does not need to do anything. */
1214
1215 #define EXTRA_SPECS \
1216 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1217 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1218 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1219 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1220 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1221 { "endian_spec", ENDIAN_SPEC }, \
1222 SUBTARGET_EXTRA_SPECS
1223
1224 #ifndef SUBTARGET_EXTRA_SPECS
1225 #define SUBTARGET_EXTRA_SPECS
1226 #endif
1227 \f
1228 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1229 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1230
1231 #ifndef PREFERRED_DEBUGGING_TYPE
1232 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1233 #endif
1234
1235 /* The size of DWARF addresses should be the same as the size of symbols
1236 in the target file format. They shouldn't depend on things like -msym32,
1237 because many DWARF consumers do not allow the mixture of address sizes
1238 that one would then get from linking -msym32 code with -msym64 code.
1239
1240 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1241 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1242 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1243
1244 /* By default, turn on GDB extensions. */
1245 #define DEFAULT_GDB_EXTENSIONS 1
1246
1247 /* Local compiler-generated symbols must have a prefix that the assembler
1248 understands. By default, this is $, although some targets (e.g.,
1249 NetBSD-ELF) need to override this. */
1250
1251 #ifndef LOCAL_LABEL_PREFIX
1252 #define LOCAL_LABEL_PREFIX "$"
1253 #endif
1254
1255 /* By default on the mips, external symbols do not have an underscore
1256 prepended, but some targets (e.g., NetBSD) require this. */
1257
1258 #ifndef USER_LABEL_PREFIX
1259 #define USER_LABEL_PREFIX ""
1260 #endif
1261
1262 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1263 since the length can run past this up to a continuation point. */
1264 #undef DBX_CONTIN_LENGTH
1265 #define DBX_CONTIN_LENGTH 1500
1266
1267 /* How to renumber registers for dbx and gdb. */
1268 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1269
1270 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1271 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1272
1273 /* The DWARF 2 CFA column which tracks the return address. */
1274 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1275
1276 /* Before the prologue, RA lives in r31. */
1277 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1278
1279 /* Describe how we implement __builtin_eh_return. */
1280 #define EH_RETURN_DATA_REGNO(N) \
1281 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1282
1283 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1284
1285 #define EH_USES(N) mips_eh_uses (N)
1286
1287 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1288 The default for this in 64-bit mode is 8, which causes problems with
1289 SFmode register saves. */
1290 #define DWARF_CIE_DATA_ALIGNMENT -4
1291
1292 /* Correct the offset of automatic variables and arguments. Note that
1293 the MIPS debug format wants all automatic variables and arguments
1294 to be in terms of the virtual frame pointer (stack pointer before
1295 any adjustment in the function), while the MIPS 3.0 linker wants
1296 the frame pointer to be the stack pointer after the initial
1297 adjustment. */
1298
1299 #define DEBUGGER_AUTO_OFFSET(X) \
1300 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1301 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1302 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1303 \f
1304 /* Target machine storage layout */
1305
1306 #define BITS_BIG_ENDIAN 0
1307 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1308 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1309
1310 #define MAX_BITS_PER_WORD 64
1311
1312 /* Width of a word, in units (bytes). */
1313 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1314 #ifndef IN_LIBGCC2
1315 #define MIN_UNITS_PER_WORD 4
1316 #endif
1317
1318 /* For MIPS, width of a floating point register. */
1319 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1320
1321 /* The number of consecutive floating-point registers needed to store the
1322 largest format supported by the FPU. */
1323 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1324
1325 /* The number of consecutive floating-point registers needed to store the
1326 smallest format supported by the FPU. */
1327 #define MIN_FPRS_PER_FMT \
1328 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1329 ? 1 : MAX_FPRS_PER_FMT)
1330
1331 /* The largest size of value that can be held in floating-point
1332 registers and moved with a single instruction. */
1333 #define UNITS_PER_HWFPVALUE \
1334 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1335
1336 /* The largest size of value that can be held in floating-point
1337 registers. */
1338 #define UNITS_PER_FPVALUE \
1339 (TARGET_SOFT_FLOAT_ABI ? 0 \
1340 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1341 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1342
1343 /* The number of bytes in a double. */
1344 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1345
1346 /* Set the sizes of the core types. */
1347 #define SHORT_TYPE_SIZE 16
1348 #define INT_TYPE_SIZE 32
1349 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1350 #define LONG_LONG_TYPE_SIZE 64
1351
1352 #define FLOAT_TYPE_SIZE 32
1353 #define DOUBLE_TYPE_SIZE 64
1354 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1355
1356 /* Define the sizes of fixed-point types. */
1357 #define SHORT_FRACT_TYPE_SIZE 8
1358 #define FRACT_TYPE_SIZE 16
1359 #define LONG_FRACT_TYPE_SIZE 32
1360 #define LONG_LONG_FRACT_TYPE_SIZE 64
1361
1362 #define SHORT_ACCUM_TYPE_SIZE 16
1363 #define ACCUM_TYPE_SIZE 32
1364 #define LONG_ACCUM_TYPE_SIZE 64
1365 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1366 doesn't support 128-bit integers for MIPS32 currently. */
1367 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1368
1369 /* long double is not a fixed mode, but the idea is that, if we
1370 support long double, we also want a 128-bit integer type. */
1371 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1372
1373 #ifdef IN_LIBGCC2
1374 #if ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1375 || (defined _ABI64 && _MIPS_SIM == _ABI64))
1376 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1377 # else
1378 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1379 # endif
1380 #endif
1381
1382 /* Width in bits of a pointer. */
1383 #ifndef POINTER_SIZE
1384 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1385 #endif
1386
1387 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1388 #define PARM_BOUNDARY BITS_PER_WORD
1389
1390 /* Allocation boundary (in *bits*) for the code of a function. */
1391 #define FUNCTION_BOUNDARY 32
1392
1393 /* Alignment of field after `int : 0' in a structure. */
1394 #define EMPTY_FIELD_BOUNDARY 32
1395
1396 /* Every structure's size must be a multiple of this. */
1397 /* 8 is observed right on a DECstation and on riscos 4.02. */
1398 #define STRUCTURE_SIZE_BOUNDARY 8
1399
1400 /* There is no point aligning anything to a rounder boundary than this. */
1401 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1402
1403 /* All accesses must be aligned. */
1404 #define STRICT_ALIGNMENT 1
1405
1406 /* Define this if you wish to imitate the way many other C compilers
1407 handle alignment of bitfields and the structures that contain
1408 them.
1409
1410 The behavior is that the type written for a bit-field (`int',
1411 `short', or other integer type) imposes an alignment for the
1412 entire structure, as if the structure really did contain an
1413 ordinary field of that type. In addition, the bit-field is placed
1414 within the structure so that it would fit within such a field,
1415 not crossing a boundary for it.
1416
1417 Thus, on most machines, a bit-field whose type is written as `int'
1418 would not cross a four-byte boundary, and would force four-byte
1419 alignment for the whole structure. (The alignment used may not
1420 be four bytes; it is controlled by the other alignment
1421 parameters.)
1422
1423 If the macro is defined, its definition should be a C expression;
1424 a nonzero value for the expression enables this behavior. */
1425
1426 #define PCC_BITFIELD_TYPE_MATTERS 1
1427
1428 /* If defined, a C expression to compute the alignment given to a
1429 constant that is being placed in memory. CONSTANT is the constant
1430 and ALIGN is the alignment that the object would ordinarily have.
1431 The value of this macro is used instead of that alignment to align
1432 the object.
1433
1434 If this macro is not defined, then ALIGN is used.
1435
1436 The typical use of this macro is to increase alignment for string
1437 constants to be word aligned so that `strcpy' calls that copy
1438 constants can be done inline. */
1439
1440 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1441 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1442 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1443
1444 /* If defined, a C expression to compute the alignment for a static
1445 variable. TYPE is the data type, and ALIGN is the alignment that
1446 the object would ordinarily have. The value of this macro is used
1447 instead of that alignment to align the object.
1448
1449 If this macro is not defined, then ALIGN is used.
1450
1451 One use of this macro is to increase alignment of medium-size
1452 data to make it all fit in fewer cache lines. Another is to
1453 cause character arrays to be word-aligned so that `strcpy' calls
1454 that copy constants to character arrays can be done inline. */
1455
1456 #undef DATA_ALIGNMENT
1457 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1458 ((((ALIGN) < BITS_PER_WORD) \
1459 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1460 || TREE_CODE (TYPE) == UNION_TYPE \
1461 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1462
1463 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1464 character arrays to be word-aligned so that `strcpy' calls that copy
1465 constants to character arrays can be done inline, and 'strcmp' can be
1466 optimised to use word loads. */
1467 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1468 DATA_ALIGNMENT (TYPE, ALIGN)
1469
1470 #define PAD_VARARGS_DOWN \
1471 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1472
1473 /* Define if operations between registers always perform the operation
1474 on the full register even if a narrower mode is specified. */
1475 #define WORD_REGISTER_OPERATIONS
1476
1477 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1478 moves. All other references are zero extended. */
1479 #define LOAD_EXTEND_OP(MODE) \
1480 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1481 ? SIGN_EXTEND : ZERO_EXTEND)
1482
1483 /* Define this macro if it is advisable to hold scalars in registers
1484 in a wider mode than that declared by the program. In such cases,
1485 the value is constrained to be within the bounds of the declared
1486 type, but kept valid in the wider mode. The signedness of the
1487 extension may differ from that of the type. */
1488
1489 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1490 if (GET_MODE_CLASS (MODE) == MODE_INT \
1491 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1492 { \
1493 if ((MODE) == SImode) \
1494 (UNSIGNEDP) = 0; \
1495 (MODE) = Pmode; \
1496 }
1497
1498 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1499 Extensions of pointers to word_mode must be signed. */
1500 #define POINTERS_EXTEND_UNSIGNED false
1501
1502 /* Define if loading short immediate values into registers sign extends. */
1503 #define SHORT_IMMEDIATES_SIGN_EXTEND
1504
1505 /* The [d]clz instructions have the natural values at 0. */
1506
1507 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1508 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1509 \f
1510 /* Standard register usage. */
1511
1512 /* Number of hardware registers. We have:
1513
1514 - 32 integer registers
1515 - 32 floating point registers
1516 - 8 condition code registers
1517 - 2 accumulator registers (hi and lo)
1518 - 32 registers each for coprocessors 0, 2 and 3
1519 - 4 fake registers:
1520 - ARG_POINTER_REGNUM
1521 - FRAME_POINTER_REGNUM
1522 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1523 - CPRESTORE_SLOT_REGNUM
1524 - 2 dummy entries that were used at various times in the past.
1525 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1526 - 6 DSP control registers */
1527
1528 #define FIRST_PSEUDO_REGISTER 188
1529
1530 /* By default, fix the kernel registers ($26 and $27), the global
1531 pointer ($28) and the stack pointer ($29). This can change
1532 depending on the command-line options.
1533
1534 Regarding coprocessor registers: without evidence to the contrary,
1535 it's best to assume that each coprocessor register has a unique
1536 use. This can be overridden, in, e.g., mips_option_override or
1537 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1538 inappropriate for a particular target. */
1539
1540 #define FIXED_REGISTERS \
1541 { \
1542 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1543 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1544 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1545 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1546 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1547 /* COP0 registers */ \
1548 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1550 /* COP2 registers */ \
1551 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1553 /* COP3 registers */ \
1554 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1555 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1556 /* 6 DSP accumulator registers & 6 control registers */ \
1557 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1558 }
1559
1560
1561 /* Set up this array for o32 by default.
1562
1563 Note that we don't mark $31 as a call-clobbered register. The idea is
1564 that it's really the call instructions themselves which clobber $31.
1565 We don't care what the called function does with it afterwards.
1566
1567 This approach makes it easier to implement sibcalls. Unlike normal
1568 calls, sibcalls don't clobber $31, so the register reaches the
1569 called function in tact. EPILOGUE_USES says that $31 is useful
1570 to the called function. */
1571
1572 #define CALL_USED_REGISTERS \
1573 { \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1575 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1576 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1577 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1578 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1579 /* COP0 registers */ \
1580 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1581 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1582 /* COP2 registers */ \
1583 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1584 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1585 /* COP3 registers */ \
1586 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1587 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1588 /* 6 DSP accumulator registers & 6 control registers */ \
1589 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1590 }
1591
1592
1593 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1594
1595 #define CALL_REALLY_USED_REGISTERS \
1596 { /* General registers. */ \
1597 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1598 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1599 /* Floating-point registers. */ \
1600 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1601 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1602 /* Others. */ \
1603 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1604 /* COP0 registers */ \
1605 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1606 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1607 /* COP2 registers */ \
1608 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1609 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1610 /* COP3 registers */ \
1611 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1612 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1613 /* 6 DSP accumulator registers & 6 control registers */ \
1614 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1615 }
1616
1617 /* Internal macros to classify a register number as to whether it's a
1618 general purpose register, a floating point register, a
1619 multiply/divide register, or a status register. */
1620
1621 #define GP_REG_FIRST 0
1622 #define GP_REG_LAST 31
1623 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1624 #define GP_DBX_FIRST 0
1625 #define K0_REG_NUM (GP_REG_FIRST + 26)
1626 #define K1_REG_NUM (GP_REG_FIRST + 27)
1627 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1628
1629 #define FP_REG_FIRST 32
1630 #define FP_REG_LAST 63
1631 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1632 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1633
1634 #define MD_REG_FIRST 64
1635 #define MD_REG_LAST 65
1636 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1637 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1638
1639 /* The DWARF 2 CFA column which tracks the return address from a
1640 signal handler context. This means that to maintain backwards
1641 compatibility, no hard register can be assigned this column if it
1642 would need to be handled by the DWARF unwinder. */
1643 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1644
1645 #define ST_REG_FIRST 67
1646 #define ST_REG_LAST 74
1647 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1648
1649
1650 /* FIXME: renumber. */
1651 #define COP0_REG_FIRST 80
1652 #define COP0_REG_LAST 111
1653 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1654
1655 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1656 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1657 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1658
1659 #define COP2_REG_FIRST 112
1660 #define COP2_REG_LAST 143
1661 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1662
1663 #define COP3_REG_FIRST 144
1664 #define COP3_REG_LAST 175
1665 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1666
1667 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1668 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1669 #define ALL_COP_REG_LAST COP3_REG_LAST
1670 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1671
1672 #define DSP_ACC_REG_FIRST 176
1673 #define DSP_ACC_REG_LAST 181
1674 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1675
1676 #define AT_REGNUM (GP_REG_FIRST + 1)
1677 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1678 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1679
1680 /* A few bitfield locations for the coprocessor registers. */
1681 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1682 the cause register for the EIC interrupt mode. */
1683 #define CAUSE_IPL 10
1684 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1685 #define SR_IPL 10
1686 /* Exception Level is at bit 1 of the status register. */
1687 #define SR_EXL 1
1688 /* Interrupt Enable is at bit 0 of the status register. */
1689 #define SR_IE 0
1690
1691 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1692 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1693 should be used instead. */
1694 #define FPSW_REGNUM ST_REG_FIRST
1695
1696 #define GP_REG_P(REGNO) \
1697 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1698 #define M16_REG_P(REGNO) \
1699 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1700 #define M16STORE_REG_P(REGNO) \
1701 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1702 #define FP_REG_P(REGNO) \
1703 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1704 #define MD_REG_P(REGNO) \
1705 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1706 #define ST_REG_P(REGNO) \
1707 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1708 #define COP0_REG_P(REGNO) \
1709 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1710 #define COP2_REG_P(REGNO) \
1711 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1712 #define COP3_REG_P(REGNO) \
1713 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1714 #define ALL_COP_REG_P(REGNO) \
1715 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1716 /* Test if REGNO is one of the 6 new DSP accumulators. */
1717 #define DSP_ACC_REG_P(REGNO) \
1718 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1719 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1720 #define ACC_REG_P(REGNO) \
1721 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1722
1723 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1724
1725 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1726 to initialize the mips16 gp pseudo register. */
1727 #define CONST_GP_P(X) \
1728 (GET_CODE (X) == CONST \
1729 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1730 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1731
1732 /* Return coprocessor number from register number. */
1733
1734 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1735 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1736 : COP3_REG_P (REGNO) ? '3' : '?')
1737
1738
1739 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1740
1741 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1742 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1743
1744 #define MODES_TIEABLE_P mips_modes_tieable_p
1745
1746 /* Register to use for pushing function arguments. */
1747 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1748
1749 /* These two registers don't really exist: they get eliminated to either
1750 the stack or hard frame pointer. */
1751 #define ARG_POINTER_REGNUM 77
1752 #define FRAME_POINTER_REGNUM 78
1753
1754 /* $30 is not available on the mips16, so we use $17 as the frame
1755 pointer. */
1756 #define HARD_FRAME_POINTER_REGNUM \
1757 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1758
1759 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1760 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1761
1762 /* Register in which static-chain is passed to a function. */
1763 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1764
1765 /* Registers used as temporaries in prologue/epilogue code:
1766
1767 - If a MIPS16 PIC function needs access to _gp, it first loads
1768 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1769
1770 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1771 register. The register must not conflict with MIPS16_PIC_TEMP.
1772
1773 - If we aren't generating MIPS16 code, the prologue can also use
1774 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1775
1776 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1777 register.
1778
1779 If we're generating MIPS16 code, these registers must come from the
1780 core set of 8. The prologue registers mustn't conflict with any
1781 incoming arguments, the static chain pointer, or the frame pointer.
1782 The epilogue temporary mustn't conflict with the return registers,
1783 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1784 or the EH data registers.
1785
1786 If we're generating interrupt handlers, we use K0 as a temporary register
1787 in prologue/epilogue code. */
1788
1789 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1790 #define MIPS_PROLOGUE_TEMP_REGNUM \
1791 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1792 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1793 (TARGET_MIPS16 \
1794 ? (gcc_unreachable (), INVALID_REGNUM) \
1795 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1796 #define MIPS_EPILOGUE_TEMP_REGNUM \
1797 (cfun->machine->interrupt_handler_p \
1798 ? K0_REG_NUM \
1799 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1800
1801 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1802 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1803 #define MIPS_PROLOGUE_TEMP2(MODE) \
1804 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1805 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1806
1807 /* Define this macro if it is as good or better to call a constant
1808 function address than to call an address kept in a register. */
1809 #define NO_FUNCTION_CSE 1
1810
1811 /* The ABI-defined global pointer. Sometimes we use a different
1812 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1813 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1814
1815 /* We normally use $28 as the global pointer. However, when generating
1816 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1817 register instead. They can then avoid saving and restoring $28
1818 and perhaps avoid using a frame at all.
1819
1820 When a leaf function uses something other than $28, mips_expand_prologue
1821 will modify pic_offset_table_rtx in place. Take the register number
1822 from there after reload. */
1823 #define PIC_OFFSET_TABLE_REGNUM \
1824 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1825 \f
1826 /* Define the classes of registers for register constraints in the
1827 machine description. Also define ranges of constants.
1828
1829 One of the classes must always be named ALL_REGS and include all hard regs.
1830 If there is more than one class, another class must be named NO_REGS
1831 and contain no registers.
1832
1833 The name GENERAL_REGS must be the name of a class (or an alias for
1834 another name such as ALL_REGS). This is the class of registers
1835 that is allowed by "g" or "r" in a register constraint.
1836 Also, registers outside this class are allocated only when
1837 instructions express preferences for them.
1838
1839 The classes must be numbered in nondecreasing order; that is,
1840 a larger-numbered class must never be contained completely
1841 in a smaller-numbered class.
1842
1843 For any two classes, it is very desirable that there be another
1844 class that represents their union. */
1845
1846 enum reg_class
1847 {
1848 NO_REGS, /* no registers in set */
1849 M16_REGS, /* mips16 directly accessible registers */
1850 T_REG, /* mips16 T register ($24) */
1851 M16_T_REGS, /* mips16 registers plus T register */
1852 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1853 V1_REG, /* Register $v1 ($3) used for TLS access. */
1854 LEA_REGS, /* Every GPR except $25 */
1855 GR_REGS, /* integer registers */
1856 FP_REGS, /* floating point registers */
1857 MD0_REG, /* first multiply/divide register */
1858 MD1_REG, /* second multiply/divide register */
1859 MD_REGS, /* multiply/divide registers (hi/lo) */
1860 COP0_REGS, /* generic coprocessor classes */
1861 COP2_REGS,
1862 COP3_REGS,
1863 ST_REGS, /* status registers (fp status) */
1864 DSP_ACC_REGS, /* DSP accumulator registers */
1865 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1866 FRAME_REGS, /* $arg and $frame */
1867 GR_AND_MD0_REGS, /* union classes */
1868 GR_AND_MD1_REGS,
1869 GR_AND_MD_REGS,
1870 GR_AND_ACC_REGS,
1871 ALL_REGS, /* all registers */
1872 LIM_REG_CLASSES /* max value + 1 */
1873 };
1874
1875 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1876
1877 #define GENERAL_REGS GR_REGS
1878
1879 /* An initializer containing the names of the register classes as C
1880 string constants. These names are used in writing some of the
1881 debugging dumps. */
1882
1883 #define REG_CLASS_NAMES \
1884 { \
1885 "NO_REGS", \
1886 "M16_REGS", \
1887 "T_REG", \
1888 "M16_T_REGS", \
1889 "PIC_FN_ADDR_REG", \
1890 "V1_REG", \
1891 "LEA_REGS", \
1892 "GR_REGS", \
1893 "FP_REGS", \
1894 "MD0_REG", \
1895 "MD1_REG", \
1896 "MD_REGS", \
1897 /* coprocessor registers */ \
1898 "COP0_REGS", \
1899 "COP2_REGS", \
1900 "COP3_REGS", \
1901 "ST_REGS", \
1902 "DSP_ACC_REGS", \
1903 "ACC_REGS", \
1904 "FRAME_REGS", \
1905 "GR_AND_MD0_REGS", \
1906 "GR_AND_MD1_REGS", \
1907 "GR_AND_MD_REGS", \
1908 "GR_AND_ACC_REGS", \
1909 "ALL_REGS" \
1910 }
1911
1912 /* An initializer containing the contents of the register classes,
1913 as integers which are bit masks. The Nth integer specifies the
1914 contents of class N. The way the integer MASK is interpreted is
1915 that register R is in the class if `MASK & (1 << R)' is 1.
1916
1917 When the machine has more than 32 registers, an integer does not
1918 suffice. Then the integers are replaced by sub-initializers,
1919 braced groupings containing several integers. Each
1920 sub-initializer must be suitable as an initializer for the type
1921 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1922
1923 #define REG_CLASS_CONTENTS \
1924 { \
1925 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1926 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1927 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1928 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1929 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1930 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1931 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1932 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1933 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1934 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1935 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1936 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1937 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1938 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1939 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1940 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1941 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1942 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1943 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1944 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1945 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1946 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1947 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1948 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1949 }
1950
1951
1952 /* A C expression whose value is a register class containing hard
1953 register REGNO. In general there is more that one such class;
1954 choose a class which is "minimal", meaning that no smaller class
1955 also contains the register. */
1956
1957 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1958
1959 /* A macro whose definition is the name of the class to which a
1960 valid base register must belong. A base register is one used in
1961 an address which is the register value plus a displacement. */
1962
1963 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1964
1965 /* A macro whose definition is the name of the class to which a
1966 valid index register must belong. An index register is one used
1967 in an address where its value is either multiplied by a scale
1968 factor or added to another register (as well as added to a
1969 displacement). */
1970
1971 #define INDEX_REG_CLASS NO_REGS
1972
1973 /* We generally want to put call-clobbered registers ahead of
1974 call-saved ones. (IRA expects this.) */
1975
1976 #define REG_ALLOC_ORDER \
1977 { /* Accumulator registers. When GPRs and accumulators have equal \
1978 cost, we generally prefer to use accumulators. For example, \
1979 a division of multiplication result is better allocated to LO, \
1980 so that we put the MFLO at the point of use instead of at the \
1981 point of definition. It's also needed if we're to take advantage \
1982 of the extra accumulators available with -mdspr2. In some cases, \
1983 it can also help to reduce register pressure. */ \
1984 64, 65,176,177,178,179,180,181, \
1985 /* Call-clobbered GPRs. */ \
1986 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1987 24, 25, 31, \
1988 /* The global pointer. This is call-clobbered for o32 and o64 \
1989 abicalls, call-saved for n32 and n64 abicalls, and a program \
1990 invariant otherwise. Putting it between the call-clobbered \
1991 and call-saved registers should cope with all eventualities. */ \
1992 28, \
1993 /* Call-saved GPRs. */ \
1994 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1995 /* GPRs that can never be exposed to the register allocator. */ \
1996 0, 26, 27, 29, \
1997 /* Call-clobbered FPRs. */ \
1998 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1999 48, 49, 50, 51, \
2000 /* FPRs that are usually call-saved. The odd ones are actually \
2001 call-clobbered for n32, but listing them ahead of the even \
2002 registers might encourage the register allocator to fragment \
2003 the available FPR pairs. We need paired FPRs to store long \
2004 doubles, so it isn't clear that using a different order \
2005 for n32 would be a win. */ \
2006 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2007 /* None of the remaining classes have defined call-saved \
2008 registers. */ \
2009 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2010 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2011 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2012 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2013 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2014 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2015 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2016 182,183,184,185,186,187 \
2017 }
2018
2019 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
2020 to be rearranged based on a particular function. On the mips16, we
2021 want to allocate $24 (T_REG) before other registers for
2022 instructions for which it is possible. */
2023
2024 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2025
2026 /* True if VALUE is an unsigned 6-bit number. */
2027
2028 #define UIMM6_OPERAND(VALUE) \
2029 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2030
2031 /* True if VALUE is a signed 10-bit number. */
2032
2033 #define IMM10_OPERAND(VALUE) \
2034 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2035
2036 /* True if VALUE is a signed 16-bit number. */
2037
2038 #define SMALL_OPERAND(VALUE) \
2039 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2040
2041 /* True if VALUE is an unsigned 16-bit number. */
2042
2043 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2044 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2045
2046 /* True if VALUE can be loaded into a register using LUI. */
2047
2048 #define LUI_OPERAND(VALUE) \
2049 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2050 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2051
2052 /* Return a value X with the low 16 bits clear, and such that
2053 VALUE - X is a signed 16-bit value. */
2054
2055 #define CONST_HIGH_PART(VALUE) \
2056 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2057
2058 #define CONST_LOW_PART(VALUE) \
2059 ((VALUE) - CONST_HIGH_PART (VALUE))
2060
2061 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2062 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2063 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2064 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2065
2066 /* The HI and LO registers can only be reloaded via the general
2067 registers. Condition code registers can only be loaded to the
2068 general registers, and from the floating point registers. */
2069
2070 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2071 mips_secondary_reload_class (CLASS, MODE, X, true)
2072 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2073 mips_secondary_reload_class (CLASS, MODE, X, false)
2074
2075 /* Return the maximum number of consecutive registers
2076 needed to represent mode MODE in a register of class CLASS. */
2077
2078 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2079
2080 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2081 mips_cannot_change_mode_class (FROM, TO, CLASS)
2082 \f
2083 /* Stack layout; function entry, exit and calling. */
2084
2085 #define STACK_GROWS_DOWNWARD
2086
2087 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2088
2089 /* Size of the area allocated in the frame to save the GP. */
2090
2091 #define MIPS_GP_SAVE_AREA_SIZE \
2092 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2093
2094 /* The offset of the first local variable from the frame pointer. See
2095 mips_compute_frame_info for details about the frame layout. */
2096
2097 #define STARTING_FRAME_OFFSET \
2098 (FRAME_GROWS_DOWNWARD \
2099 ? 0 \
2100 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2101
2102 #define RETURN_ADDR_RTX mips_return_addr
2103
2104 /* Mask off the MIPS16 ISA bit in unwind addresses.
2105
2106 The reason for this is a little subtle. When unwinding a call,
2107 we are given the call's return address, which on most targets
2108 is the address of the following instruction. However, what we
2109 actually want to find is the EH region for the call itself.
2110 The target-independent unwind code therefore searches for "RA - 1".
2111
2112 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2113 RA - 1 is therefore the real (even-valued) start of the return
2114 instruction. EH region labels are usually odd-valued MIPS16 symbols
2115 too, so a search for an even address within a MIPS16 region would
2116 usually work.
2117
2118 However, there is an exception. If the end of an EH region is also
2119 the end of a function, the end label is allowed to be even. This is
2120 necessary because a following non-MIPS16 function may also need EH
2121 information for its first instruction.
2122
2123 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2124 non-ISA-encoded address. This probably isn't ideal, but it is
2125 the traditional (legacy) behavior. It is therefore only safe
2126 to search MIPS EH regions for an _odd-valued_ address.
2127
2128 Masking off the ISA bit means that the target-independent code
2129 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2130 #define MASK_RETURN_ADDR GEN_INT (-2)
2131
2132
2133 /* Similarly, don't use the least-significant bit to tell pointers to
2134 code from vtable index. */
2135
2136 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2137
2138 /* The eliminations to $17 are only used for mips16 code. See the
2139 definition of HARD_FRAME_POINTER_REGNUM. */
2140
2141 #define ELIMINABLE_REGS \
2142 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2143 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2144 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2145 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2146 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2147 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2148
2149 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2150 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2151
2152 /* Allocate stack space for arguments at the beginning of each function. */
2153 #define ACCUMULATE_OUTGOING_ARGS 1
2154
2155 /* The argument pointer always points to the first argument. */
2156 #define FIRST_PARM_OFFSET(FNDECL) 0
2157
2158 /* o32 and o64 reserve stack space for all argument registers. */
2159 #define REG_PARM_STACK_SPACE(FNDECL) \
2160 (TARGET_OLDABI \
2161 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2162 : 0)
2163
2164 /* Define this if it is the responsibility of the caller to
2165 allocate the area reserved for arguments passed in registers.
2166 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2167 of this macro is to determine whether the space is included in
2168 `crtl->outgoing_args_size'. */
2169 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2170
2171 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2172 \f
2173 /* Symbolic macros for the registers used to return integer and floating
2174 point values. */
2175
2176 #define GP_RETURN (GP_REG_FIRST + 2)
2177 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2178
2179 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2180
2181 /* Symbolic macros for the first/last argument registers. */
2182
2183 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2184 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2185 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2186 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2187
2188 /* 1 if N is a possible register number for function argument passing.
2189 We have no FP argument registers when soft-float. When FP registers
2190 are 32 bits, we can't directly reference the odd numbered ones. */
2191
2192 #define FUNCTION_ARG_REGNO_P(N) \
2193 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2194 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2195 && !fixed_regs[N])
2196 \f
2197 /* This structure has to cope with two different argument allocation
2198 schemes. Most MIPS ABIs view the arguments as a structure, of which
2199 the first N words go in registers and the rest go on the stack. If I
2200 < N, the Ith word might go in Ith integer argument register or in a
2201 floating-point register. For these ABIs, we only need to remember
2202 the offset of the current argument into the structure.
2203
2204 The EABI instead allocates the integer and floating-point arguments
2205 separately. The first N words of FP arguments go in FP registers,
2206 the rest go on the stack. Likewise, the first N words of the other
2207 arguments go in integer registers, and the rest go on the stack. We
2208 need to maintain three counts: the number of integer registers used,
2209 the number of floating-point registers used, and the number of words
2210 passed on the stack.
2211
2212 We could keep separate information for the two ABIs (a word count for
2213 the standard ABIs, and three separate counts for the EABI). But it
2214 seems simpler to view the standard ABIs as forms of EABI that do not
2215 allocate floating-point registers.
2216
2217 So for the standard ABIs, the first N words are allocated to integer
2218 registers, and mips_function_arg decides on an argument-by-argument
2219 basis whether that argument should really go in an integer register,
2220 or in a floating-point one. */
2221
2222 typedef struct mips_args {
2223 /* Always true for varargs functions. Otherwise true if at least
2224 one argument has been passed in an integer register. */
2225 int gp_reg_found;
2226
2227 /* The number of arguments seen so far. */
2228 unsigned int arg_number;
2229
2230 /* The number of integer registers used so far. For all ABIs except
2231 EABI, this is the number of words that have been added to the
2232 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2233 unsigned int num_gprs;
2234
2235 /* For EABI, the number of floating-point registers used so far. */
2236 unsigned int num_fprs;
2237
2238 /* The number of words passed on the stack. */
2239 unsigned int stack_words;
2240
2241 /* On the mips16, we need to keep track of which floating point
2242 arguments were passed in general registers, but would have been
2243 passed in the FP regs if this were a 32-bit function, so that we
2244 can move them to the FP regs if we wind up calling a 32-bit
2245 function. We record this information in fp_code, encoded in base
2246 four. A zero digit means no floating point argument, a one digit
2247 means an SFmode argument, and a two digit means a DFmode argument,
2248 and a three digit is not used. The low order digit is the first
2249 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2250 an SFmode argument. ??? A more sophisticated approach will be
2251 needed if MIPS_ABI != ABI_32. */
2252 int fp_code;
2253
2254 /* True if the function has a prototype. */
2255 int prototype;
2256 } CUMULATIVE_ARGS;
2257
2258 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2259 for a call to a function whose data type is FNTYPE.
2260 For a library call, FNTYPE is 0. */
2261
2262 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2263 mips_init_cumulative_args (&CUM, FNTYPE)
2264
2265 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2266 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2267
2268 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2269 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2270
2271 /* True if using EABI and varargs can be passed in floating-point
2272 registers. Under these conditions, we need a more complex form
2273 of va_list, which tracks GPR, FPR and stack arguments separately. */
2274 #define EABI_FLOAT_VARARGS_P \
2275 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2276
2277 \f
2278 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2279
2280 /* Treat LOC as a byte offset from the stack pointer and round it up
2281 to the next fully-aligned offset. */
2282 #define MIPS_STACK_ALIGN(LOC) \
2283 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2284
2285 \f
2286 /* Output assembler code to FILE to increment profiler label # LABELNO
2287 for profiling a function entry. */
2288
2289 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2290
2291 /* The profiler preserves all interesting registers, including $31. */
2292 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2293
2294 /* No mips port has ever used the profiler counter word, so don't emit it
2295 or the label for it. */
2296
2297 #define NO_PROFILE_COUNTERS 1
2298
2299 /* Define this macro if the code for function profiling should come
2300 before the function prologue. Normally, the profiling code comes
2301 after. */
2302
2303 /* #define PROFILE_BEFORE_PROLOGUE */
2304
2305 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2306 the stack pointer does not matter. The value is tested only in
2307 functions that have frame pointers.
2308 No definition is equivalent to always zero. */
2309
2310 #define EXIT_IGNORE_STACK 1
2311
2312 \f
2313 /* Trampolines are a block of code followed by two pointers. */
2314
2315 #define TRAMPOLINE_SIZE \
2316 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2317
2318 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2319 pointers from a single LUI base. */
2320
2321 #define TRAMPOLINE_ALIGNMENT 64
2322
2323 /* mips_trampoline_init calls this library function to flush
2324 program and data caches. */
2325
2326 #ifndef CACHE_FLUSH_FUNC
2327 #define CACHE_FLUSH_FUNC "_flush_cache"
2328 #endif
2329
2330 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2331 /* Flush both caches. We need to flush the data cache in case \
2332 the system has a write-back cache. */ \
2333 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2334 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2335 GEN_INT (3), TYPE_MODE (integer_type_node))
2336
2337 \f
2338 /* Addressing modes, and classification of registers for them. */
2339
2340 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2341 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2342 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2343 \f
2344 /* Maximum number of registers that can appear in a valid memory address. */
2345
2346 #define MAX_REGS_PER_ADDRESS 1
2347
2348 /* Check for constness inline but use mips_legitimate_address_p
2349 to check whether a constant really is an address. */
2350
2351 #define CONSTANT_ADDRESS_P(X) \
2352 (CONSTANT_P (X) && memory_address_p (SImode, X))
2353
2354 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2355 'the start of the function that this code is output in'. */
2356
2357 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2358 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2359 asm_fprintf ((FILE), "%U%s", \
2360 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2361 else \
2362 asm_fprintf ((FILE), "%U%s", (NAME))
2363 \f
2364 /* Flag to mark a function decl symbol that requires a long call. */
2365 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2366 #define SYMBOL_REF_LONG_CALL_P(X) \
2367 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2368
2369 /* This flag marks functions that cannot be lazily bound. */
2370 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2371 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2372 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2373
2374 /* True if we're generating a form of MIPS16 code in which jump tables
2375 are stored in the text section and encoded as 16-bit PC-relative
2376 offsets. This is only possible when general text loads are allowed,
2377 since the table access itself will be an "lh" instruction. If the
2378 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2379 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2380
2381 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2382
2383 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2384
2385 /* Only use short offsets if their range will not overflow. */
2386 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2387 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2388 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2389 : SImode)
2390
2391 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2392
2393 /* Define this as 1 if `char' should by default be signed; else as 0. */
2394 #ifndef DEFAULT_SIGNED_CHAR
2395 #define DEFAULT_SIGNED_CHAR 1
2396 #endif
2397
2398 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2399 we generally don't want to use them for copying arbitrary data.
2400 A single N-word move is usually the same cost as N single-word moves. */
2401 #define MOVE_MAX UNITS_PER_WORD
2402 #define MAX_MOVE_MAX 8
2403
2404 /* Define this macro as a C expression which is nonzero if
2405 accessing less than a word of memory (i.e. a `char' or a
2406 `short') is no faster than accessing a word of memory, i.e., if
2407 such access require more than one instruction or if there is no
2408 difference in cost between byte and (aligned) word loads.
2409
2410 On RISC machines, it tends to generate better code to define
2411 this as 1, since it avoids making a QI or HI mode register.
2412
2413 But, generating word accesses for -mips16 is generally bad as shifts
2414 (often extended) would be needed for byte accesses. */
2415 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2416
2417 /* Standard MIPS integer shifts truncate the shift amount to the
2418 width of the shifted operand. However, Loongson vector shifts
2419 do not truncate the shift amount at all. */
2420 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2421
2422 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2423 is done just by pretending it is already truncated. */
2424 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2425 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2426
2427
2428 /* Specify the machine mode that pointers have.
2429 After generation of rtl, the compiler makes no further distinction
2430 between pointers and any other objects of this machine mode. */
2431
2432 #ifndef Pmode
2433 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2434 #endif
2435
2436 /* Give call MEMs SImode since it is the "most permissive" mode
2437 for both 32-bit and 64-bit targets. */
2438
2439 #define FUNCTION_MODE SImode
2440
2441 \f
2442 /* We allocate $fcc registers by hand and can't cope with moves of
2443 CCmode registers to and from pseudos (or memory). */
2444 #define AVOID_CCMODE_COPIES
2445
2446 /* A C expression for the cost of a branch instruction. A value of
2447 1 is the default; other values are interpreted relative to that. */
2448
2449 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2450 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2451
2452 /* The MIPS port has several functions that return an instruction count.
2453 Multiplying the count by this value gives the number of bytes that
2454 the instructions occupy. */
2455 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2456
2457 /* The length of a NOP in bytes. */
2458 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2459
2460 /* If defined, modifies the length assigned to instruction INSN as a
2461 function of the context in which it is used. LENGTH is an lvalue
2462 that contains the initially computed length of the insn and should
2463 be updated with the correct length of the insn. */
2464 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2465 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2466
2467 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2468 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2469 its operands. */
2470 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2471 "%*" OPCODE "%?\t" OPERANDS "%/"
2472
2473 /* Return an asm string that forces INSN to be treated as an absolute
2474 J or JAL instruction instead of an assembler macro. */
2475 #define MIPS_ABSOLUTE_JUMP(INSN) \
2476 (TARGET_ABICALLS_PIC2 \
2477 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2478 : INSN)
2479
2480 /* Return the asm template for a call. INSN is the instruction's mnemonic
2481 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2482 number of the target. SIZE_OPNO is the operand number of the argument size
2483 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2484 -1 and the call is indirect, use the function symbol from the call
2485 attributes to attach a R_MIPS_JALR relocation to the call.
2486
2487 When generating GOT code without explicit relocation operators,
2488 all calls should use assembly macros. Otherwise, all indirect
2489 calls should use "jr" or "jalr"; we will arrange to restore $gp
2490 afterwards if necessary. Finally, we can only generate direct
2491 calls for -mabicalls by temporarily switching to non-PIC mode.
2492
2493 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2494 instruction is in the delay slot of jal(r). */
2495 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2496 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2497 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2498 : REG_P (OPERANDS[TARGET_OPNO]) \
2499 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2500 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2501 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2502 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2503 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2504 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2505 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2506
2507 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2508 "jrc" when nop is in the delay slot of "jr". */
2509
2510 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2511 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2512 ? "%*j\t%" #OPNO "%/" \
2513 : REG_P (OPERANDS[OPNO]) \
2514 ? "%*jr%:\t%" #OPNO \
2515 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2516
2517 \f
2518 /* Control the assembler format that we output. */
2519
2520 /* Output to assembler file text saying following lines
2521 may contain character constants, extra white space, comments, etc. */
2522
2523 #ifndef ASM_APP_ON
2524 #define ASM_APP_ON " #APP\n"
2525 #endif
2526
2527 /* Output to assembler file text saying following lines
2528 no longer contain unusual constructs. */
2529
2530 #ifndef ASM_APP_OFF
2531 #define ASM_APP_OFF " #NO_APP\n"
2532 #endif
2533
2534 #define REGISTER_NAMES \
2535 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2536 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2537 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2538 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2539 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2540 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2541 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2542 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2543 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2544 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2545 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2546 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2547 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2548 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2549 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2550 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2551 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2552 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2553 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2554 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2555 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2556 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2557 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2558 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2559
2560 /* List the "software" names for each register. Also list the numerical
2561 names for $fp and $sp. */
2562
2563 #define ADDITIONAL_REGISTER_NAMES \
2564 { \
2565 { "$29", 29 + GP_REG_FIRST }, \
2566 { "$30", 30 + GP_REG_FIRST }, \
2567 { "at", 1 + GP_REG_FIRST }, \
2568 { "v0", 2 + GP_REG_FIRST }, \
2569 { "v1", 3 + GP_REG_FIRST }, \
2570 { "a0", 4 + GP_REG_FIRST }, \
2571 { "a1", 5 + GP_REG_FIRST }, \
2572 { "a2", 6 + GP_REG_FIRST }, \
2573 { "a3", 7 + GP_REG_FIRST }, \
2574 { "t0", 8 + GP_REG_FIRST }, \
2575 { "t1", 9 + GP_REG_FIRST }, \
2576 { "t2", 10 + GP_REG_FIRST }, \
2577 { "t3", 11 + GP_REG_FIRST }, \
2578 { "t4", 12 + GP_REG_FIRST }, \
2579 { "t5", 13 + GP_REG_FIRST }, \
2580 { "t6", 14 + GP_REG_FIRST }, \
2581 { "t7", 15 + GP_REG_FIRST }, \
2582 { "s0", 16 + GP_REG_FIRST }, \
2583 { "s1", 17 + GP_REG_FIRST }, \
2584 { "s2", 18 + GP_REG_FIRST }, \
2585 { "s3", 19 + GP_REG_FIRST }, \
2586 { "s4", 20 + GP_REG_FIRST }, \
2587 { "s5", 21 + GP_REG_FIRST }, \
2588 { "s6", 22 + GP_REG_FIRST }, \
2589 { "s7", 23 + GP_REG_FIRST }, \
2590 { "t8", 24 + GP_REG_FIRST }, \
2591 { "t9", 25 + GP_REG_FIRST }, \
2592 { "k0", 26 + GP_REG_FIRST }, \
2593 { "k1", 27 + GP_REG_FIRST }, \
2594 { "gp", 28 + GP_REG_FIRST }, \
2595 { "sp", 29 + GP_REG_FIRST }, \
2596 { "fp", 30 + GP_REG_FIRST }, \
2597 { "ra", 31 + GP_REG_FIRST } \
2598 }
2599
2600 #define DBR_OUTPUT_SEQEND(STREAM) \
2601 do \
2602 { \
2603 /* Undo the effect of '%*'. */ \
2604 mips_pop_asm_switch (&mips_nomacro); \
2605 mips_pop_asm_switch (&mips_noreorder); \
2606 /* Emit a blank line after the delay slot for emphasis. */ \
2607 fputs ("\n", STREAM); \
2608 } \
2609 while (0)
2610
2611 /* The MIPS implementation uses some labels for its own purpose. The
2612 following lists what labels are created, and are all formed by the
2613 pattern $L[a-z].*. The machine independent portion of GCC creates
2614 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2615
2616 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2617 $Lb[0-9]+ Begin blocks for MIPS debug support
2618 $Lc[0-9]+ Label for use in s<xx> operation.
2619 $Le[0-9]+ End blocks for MIPS debug support */
2620
2621 #undef ASM_DECLARE_OBJECT_NAME
2622 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2623 mips_declare_object (STREAM, NAME, "", ":\n")
2624
2625 /* Globalizing directive for a label. */
2626 #define GLOBAL_ASM_OP "\t.globl\t"
2627
2628 /* This says how to define a global common symbol. */
2629
2630 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2631
2632 /* This says how to define a local common symbol (i.e., not visible to
2633 linker). */
2634
2635 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2636 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2637 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2638 #endif
2639
2640 /* This says how to output an external. It would be possible not to
2641 output anything and let undefined symbol become external. However
2642 the assembler uses length information on externals to allocate in
2643 data/sdata bss/sbss, thereby saving exec time. */
2644
2645 #undef ASM_OUTPUT_EXTERNAL
2646 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2647 mips_output_external(STREAM,DECL,NAME)
2648
2649 /* This is how to declare a function name. The actual work of
2650 emitting the label is moved to function_prologue, so that we can
2651 get the line number correctly emitted before the .ent directive,
2652 and after any .file directives. Define as empty so that the function
2653 is not declared before the .ent directive elsewhere. */
2654
2655 #undef ASM_DECLARE_FUNCTION_NAME
2656 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2657
2658 /* This is how to store into the string LABEL
2659 the symbol_ref name of an internal numbered label where
2660 PREFIX is the class of label and NUM is the number within the class.
2661 This is suitable for output with `assemble_name'. */
2662
2663 #undef ASM_GENERATE_INTERNAL_LABEL
2664 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2665 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2666
2667 /* Print debug labels as "foo = ." rather than "foo:" because they should
2668 represent a byte pointer rather than an ISA-encoded address. This is
2669 particularly important for code like:
2670
2671 $LFBxxx = .
2672 .cfi_startproc
2673 ...
2674 .section .gcc_except_table,...
2675 ...
2676 .uleb128 foo-$LFBxxx
2677
2678 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2679 likewise a byte pointer rather than an ISA-encoded address.
2680
2681 At the time of writing, this hook is not used for the function end
2682 label:
2683
2684 $LFExxx:
2685 .end foo
2686
2687 But this doesn't matter, because GAS doesn't treat a pre-.end label
2688 as a MIPS16 one anyway. */
2689
2690 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2691 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2692
2693 /* This is how to output an element of a case-vector that is absolute. */
2694
2695 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2696 fprintf (STREAM, "\t%s\t%sL%d\n", \
2697 ptr_mode == DImode ? ".dword" : ".word", \
2698 LOCAL_LABEL_PREFIX, \
2699 VALUE)
2700
2701 /* This is how to output an element of a case-vector. We can make the
2702 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2703 is supported. */
2704
2705 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2706 do { \
2707 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2708 { \
2709 if (GET_MODE (BODY) == HImode) \
2710 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2711 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2712 else \
2713 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2714 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2715 } \
2716 else if (TARGET_GPWORD) \
2717 fprintf (STREAM, "\t%s\t%sL%d\n", \
2718 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2719 LOCAL_LABEL_PREFIX, VALUE); \
2720 else if (TARGET_RTP_PIC) \
2721 { \
2722 /* Make the entry relative to the start of the function. */ \
2723 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2724 fprintf (STREAM, "\t%s\t%sL%d-", \
2725 Pmode == DImode ? ".dword" : ".word", \
2726 LOCAL_LABEL_PREFIX, VALUE); \
2727 assemble_name (STREAM, XSTR (fnsym, 0)); \
2728 fprintf (STREAM, "\n"); \
2729 } \
2730 else \
2731 fprintf (STREAM, "\t%s\t%sL%d\n", \
2732 ptr_mode == DImode ? ".dword" : ".word", \
2733 LOCAL_LABEL_PREFIX, VALUE); \
2734 } while (0)
2735
2736 /* This is how to output an assembler line
2737 that says to advance the location counter
2738 to a multiple of 2**LOG bytes. */
2739
2740 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2741 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2742
2743 /* This is how to output an assembler line to advance the location
2744 counter by SIZE bytes. */
2745
2746 #undef ASM_OUTPUT_SKIP
2747 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2748 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2749
2750 /* This is how to output a string. */
2751 #undef ASM_OUTPUT_ASCII
2752 #define ASM_OUTPUT_ASCII mips_output_ascii
2753
2754 \f
2755 /* Default to -G 8 */
2756 #ifndef MIPS_DEFAULT_GVALUE
2757 #define MIPS_DEFAULT_GVALUE 8
2758 #endif
2759
2760 /* Define the strings to put out for each section in the object file. */
2761 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2762 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2763
2764 #undef READONLY_DATA_SECTION_ASM_OP
2765 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2766 \f
2767 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2768 do \
2769 { \
2770 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2771 TARGET_64BIT ? "daddiu" : "addiu", \
2772 reg_names[STACK_POINTER_REGNUM], \
2773 reg_names[STACK_POINTER_REGNUM], \
2774 TARGET_64BIT ? "sd" : "sw", \
2775 reg_names[REGNO], \
2776 reg_names[STACK_POINTER_REGNUM]); \
2777 } \
2778 while (0)
2779
2780 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2781 do \
2782 { \
2783 mips_push_asm_switch (&mips_noreorder); \
2784 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2785 TARGET_64BIT ? "ld" : "lw", \
2786 reg_names[REGNO], \
2787 reg_names[STACK_POINTER_REGNUM], \
2788 TARGET_64BIT ? "daddu" : "addu", \
2789 reg_names[STACK_POINTER_REGNUM], \
2790 reg_names[STACK_POINTER_REGNUM]); \
2791 mips_pop_asm_switch (&mips_noreorder); \
2792 } \
2793 while (0)
2794
2795 /* How to start an assembler comment.
2796 The leading space is important (the mips native assembler requires it). */
2797 #ifndef ASM_COMMENT_START
2798 #define ASM_COMMENT_START " #"
2799 #endif
2800 \f
2801 #undef SIZE_TYPE
2802 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2803
2804 #undef PTRDIFF_TYPE
2805 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2806
2807 /* The maximum number of bytes that can be copied by one iteration of
2808 a movmemsi loop; see mips_block_move_loop. */
2809 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2810 (UNITS_PER_WORD * 4)
2811
2812 /* The maximum number of bytes that can be copied by a straight-line
2813 implementation of movmemsi; see mips_block_move_straight. We want
2814 to make sure that any loop-based implementation will iterate at
2815 least twice. */
2816 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2817 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2818
2819 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2820 values were determined experimentally by benchmarking with CSiBE.
2821 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2822 for o32 where we have to restore $gp afterwards as well as make an
2823 indirect call), but in practice, bumping this up higher for
2824 TARGET_ABICALLS doesn't make much difference to code size. */
2825
2826 #define MIPS_CALL_RATIO 8
2827
2828 /* Any loop-based implementation of movmemsi will have at least
2829 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2830 moves, so allow individual copies of fewer elements.
2831
2832 When movmemsi is not available, use a value approximating
2833 the length of a memcpy call sequence, so that move_by_pieces
2834 will generate inline code if it is shorter than a function call.
2835 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2836 we'll have to generate a load/store pair for each, halve the
2837 value of MIPS_CALL_RATIO to take that into account. */
2838
2839 #define MOVE_RATIO(speed) \
2840 (HAVE_movmemsi \
2841 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2842 : MIPS_CALL_RATIO / 2)
2843
2844 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2845 mips_move_by_pieces_p (SIZE, ALIGN)
2846
2847 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2848 of the length of a memset call, but use the default otherwise. */
2849
2850 #define CLEAR_RATIO(speed)\
2851 ((speed) ? 15 : MIPS_CALL_RATIO)
2852
2853 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2854 optimizing for size adjust the ratio to account for the overhead of
2855 loading the constant and replicating it across the word. */
2856
2857 #define SET_RATIO(speed) \
2858 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2859
2860 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2861 mips_store_by_pieces_p (SIZE, ALIGN)
2862 \f
2863 /* Since the bits of the _init and _fini function is spread across
2864 many object files, each potentially with its own GP, we must assume
2865 we need to load our GP. We don't preserve $gp or $ra, since each
2866 init/fini chunk is supposed to initialize $gp, and crti/crtn
2867 already take care of preserving $ra and, when appropriate, $gp. */
2868 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2869 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2870 asm (SECTION_OP "\n\
2871 .set push\n\
2872 .set nomips16\n\
2873 .set noreorder\n\
2874 bal 1f\n\
2875 nop\n\
2876 1: .cpload $31\n\
2877 .set reorder\n\
2878 jal " USER_LABEL_PREFIX #FUNC "\n\
2879 .set pop\n\
2880 " TEXT_SECTION_ASM_OP);
2881 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2882 || (defined _ABI64 && _MIPS_SIM == _ABI64))
2883 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2884 asm (SECTION_OP "\n\
2885 .set push\n\
2886 .set nomips16\n\
2887 .set noreorder\n\
2888 bal 1f\n\
2889 nop\n\
2890 1: .set reorder\n\
2891 .cpsetup $31, $2, 1b\n\
2892 jal " USER_LABEL_PREFIX #FUNC "\n\
2893 .set pop\n\
2894 " TEXT_SECTION_ASM_OP);
2895 #endif
2896
2897 #ifndef HAVE_AS_TLS
2898 #define HAVE_AS_TLS 0
2899 #endif
2900
2901 #ifndef USED_FOR_TARGET
2902 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2903 struct mips_asm_switch {
2904 /* The FOO in the description above. */
2905 const char *name;
2906
2907 /* The current block nesting level, or 0 if we aren't in a block. */
2908 int nesting_level;
2909 };
2910
2911 extern const enum reg_class mips_regno_to_class[];
2912 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2913 extern const char *current_function_file; /* filename current function is in */
2914 extern int num_source_filenames; /* current .file # */
2915 extern struct mips_asm_switch mips_noreorder;
2916 extern struct mips_asm_switch mips_nomacro;
2917 extern struct mips_asm_switch mips_noat;
2918 extern int mips_dbx_regno[];
2919 extern int mips_dwarf_regno[];
2920 extern bool mips_split_p[];
2921 extern bool mips_split_hi_p[];
2922 extern bool mips_use_pcrel_pool_p[];
2923 extern const char *mips_lo_relocs[];
2924 extern const char *mips_hi_relocs[];
2925 extern enum processor mips_arch; /* which cpu to codegen for */
2926 extern enum processor mips_tune; /* which cpu to schedule for */
2927 extern int mips_isa; /* architectural level */
2928 extern const struct mips_cpu_info *mips_arch_info;
2929 extern const struct mips_cpu_info *mips_tune_info;
2930 extern unsigned int mips_base_compression_flags;
2931 extern GTY(()) struct target_globals *mips16_globals;
2932 #endif
2933
2934 /* Enable querying of DFA units. */
2935 #define CPU_UNITS_QUERY 1
2936
2937 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2938 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2939
2940 /* As on most targets, we want the .eh_frame section to be read-only where
2941 possible. And as on most targets, this means two things:
2942
2943 (a) Non-locally-binding pointers must have an indirect encoding,
2944 so that the addresses in the .eh_frame section itself become
2945 locally-binding.
2946
2947 (b) A shared library's .eh_frame section must encode locally-binding
2948 pointers in a relative (relocation-free) form.
2949
2950 However, MIPS has traditionally not allowed directives like:
2951
2952 .long x-.
2953
2954 in cases where "x" is in a different section, or is not defined in the
2955 same assembly file. We are therefore unable to emit the PC-relative
2956 form required by (b) at assembly time.
2957
2958 Fortunately, the linker is able to convert absolute addresses into
2959 PC-relative addresses on our behalf. Unfortunately, only certain
2960 versions of the linker know how to do this for indirect pointers,
2961 and for personality data. We must fall back on using writable
2962 .eh_frame sections for shared libraries if the linker does not
2963 support this feature. */
2964 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2965 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2966
2967 /* For switching between MIPS16 and non-MIPS16 modes. */
2968 #define SWITCHABLE_TARGET 1
2969
2970 /* Several named MIPS patterns depend on Pmode. These patterns have the
2971 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2972 Add the appropriate suffix to generator function NAME and invoke it
2973 with arguments ARGS. */
2974 #define PMODE_INSN(NAME, ARGS) \
2975 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)