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mips.h (BASE_INSN_LENGTH, [...]): New macros.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS64 (mips_isa == 64)
212 #define ISA_MIPS64R2 (mips_isa == 65)
213
214 /* Architecture target defines. */
215 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
216 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
217 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
218 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
219 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
220 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
221 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
222 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
223 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
224 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
225 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
226 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
227 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
228 || mips_arch == PROCESSOR_OCTEON2)
229 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
230 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
231 || mips_arch == PROCESSOR_SB1A)
232 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
233 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
234
235 /* Scheduling target defines. */
236 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
237 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
238 || mips_tune == PROCESSOR_24KF2_1 \
239 || mips_tune == PROCESSOR_24KF1_1)
240 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
241 || mips_tune == PROCESSOR_74KF2_1 \
242 || mips_tune == PROCESSOR_74KF1_1 \
243 || mips_tune == PROCESSOR_74KF3_2)
244 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
245 || mips_tune == PROCESSOR_LOONGSON_2F)
246 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
247 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
248 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
249 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
250 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
251 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
252 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
253 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
254 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
255 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
256 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
257 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
258 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
259 || mips_tune == PROCESSOR_OCTEON2)
260 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
261 || mips_tune == PROCESSOR_SB1A)
262
263 /* Whether vector modes and intrinsics for ST Microelectronics
264 Loongson-2E/2F processors should be enabled. In o32 pairs of
265 floating-point registers provide 64-bit values. */
266 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
267 && (TARGET_LOONGSON_2EF \
268 || TARGET_LOONGSON_3A))
269
270 /* True if the pre-reload scheduler should try to create chains of
271 multiply-add or multiply-subtract instructions. For example,
272 suppose we have:
273
274 t1 = a * b
275 t2 = t1 + c * d
276 t3 = e * f
277 t4 = t3 - g * h
278
279 t1 will have a higher priority than t2 and t3 will have a higher
280 priority than t4. However, before reload, there is no dependence
281 between t1 and t3, and they can often have similar priorities.
282 The scheduler will then tend to prefer:
283
284 t1 = a * b
285 t3 = e * f
286 t2 = t1 + c * d
287 t4 = t3 - g * h
288
289 which stops us from making full use of macc/madd-style instructions.
290 This sort of situation occurs frequently in Fourier transforms and
291 in unrolled loops.
292
293 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
294 queue so that chained multiply-add and multiply-subtract instructions
295 appear ahead of any other instruction that is likely to clobber lo.
296 In the example above, if t2 and t3 become ready at the same time,
297 the code ensures that t2 is scheduled first.
298
299 Multiply-accumulate instructions are a bigger win for some targets
300 than others, so this macro is defined on an opt-in basis. */
301 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
302 || TUNE_MIPS4120 \
303 || TUNE_MIPS4130 \
304 || TUNE_24K)
305
306 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
307 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
308
309 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
310 directly accessible, while the command-line options select
311 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
312 in use. */
313 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
314 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
315
316 /* False if SC acts as a memory barrier with respect to itself,
317 otherwise a SYNC will be emitted after SC for atomic operations
318 that require ordering between the SC and following loads and
319 stores. It does not tell anything about ordering of loads and
320 stores prior to and following the SC, only about the SC itself and
321 those loads and stores follow it. */
322 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
323
324 /* Define preprocessor macros for the -march and -mtune options.
325 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
326 processor. If INFO's canonical name is "foo", define PREFIX to
327 be "foo", and define an additional macro PREFIX_FOO. */
328 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
329 do \
330 { \
331 char *macro, *p; \
332 \
333 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
334 for (p = macro; *p != 0; p++) \
335 if (*p == '+') \
336 *p = 'P'; \
337 else \
338 *p = TOUPPER (*p); \
339 \
340 builtin_define (macro); \
341 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
342 free (macro); \
343 } \
344 while (0)
345
346 /* Target CPU builtins. */
347 #define TARGET_CPU_CPP_BUILTINS() \
348 do \
349 { \
350 builtin_assert ("machine=mips"); \
351 builtin_assert ("cpu=mips"); \
352 builtin_define ("__mips__"); \
353 builtin_define ("_mips"); \
354 \
355 /* We do this here because __mips is defined below and so we \
356 can't use builtin_define_std. We don't ever want to define \
357 "mips" for VxWorks because some of the VxWorks headers \
358 construct include filenames from a root directory macro, \
359 an architecture macro and a filename, where the architecture \
360 macro expands to 'mips'. If we define 'mips' to 1, the \
361 architecture macro expands to 1 as well. */ \
362 if (!flag_iso && !TARGET_VXWORKS) \
363 builtin_define ("mips"); \
364 \
365 if (TARGET_64BIT) \
366 builtin_define ("__mips64"); \
367 \
368 /* Treat _R3000 and _R4000 like register-size \
369 defines, which is how they've historically \
370 been used. */ \
371 if (TARGET_64BIT) \
372 { \
373 builtin_define_std ("R4000"); \
374 builtin_define ("_R4000"); \
375 } \
376 else \
377 { \
378 builtin_define_std ("R3000"); \
379 builtin_define ("_R3000"); \
380 } \
381 \
382 if (TARGET_FLOAT64) \
383 builtin_define ("__mips_fpr=64"); \
384 else \
385 builtin_define ("__mips_fpr=32"); \
386 \
387 if (mips_base_compression_flags & MASK_MIPS16) \
388 builtin_define ("__mips16"); \
389 \
390 if (TARGET_MIPS3D) \
391 builtin_define ("__mips3d"); \
392 \
393 if (TARGET_SMARTMIPS) \
394 builtin_define ("__mips_smartmips"); \
395 \
396 if (mips_base_compression_flags & MASK_MICROMIPS) \
397 builtin_define ("__mips_micromips"); \
398 \
399 if (TARGET_MCU) \
400 builtin_define ("__mips_mcu"); \
401 \
402 if (TARGET_DSP) \
403 { \
404 builtin_define ("__mips_dsp"); \
405 if (TARGET_DSPR2) \
406 { \
407 builtin_define ("__mips_dspr2"); \
408 builtin_define ("__mips_dsp_rev=2"); \
409 } \
410 else \
411 builtin_define ("__mips_dsp_rev=1"); \
412 } \
413 \
414 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
415 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
416 \
417 if (ISA_MIPS1) \
418 { \
419 builtin_define ("__mips=1"); \
420 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
421 } \
422 else if (ISA_MIPS2) \
423 { \
424 builtin_define ("__mips=2"); \
425 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
426 } \
427 else if (ISA_MIPS3) \
428 { \
429 builtin_define ("__mips=3"); \
430 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
431 } \
432 else if (ISA_MIPS4) \
433 { \
434 builtin_define ("__mips=4"); \
435 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
436 } \
437 else if (ISA_MIPS32) \
438 { \
439 builtin_define ("__mips=32"); \
440 builtin_define ("__mips_isa_rev=1"); \
441 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
442 } \
443 else if (ISA_MIPS32R2) \
444 { \
445 builtin_define ("__mips=32"); \
446 builtin_define ("__mips_isa_rev=2"); \
447 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
448 } \
449 else if (ISA_MIPS64) \
450 { \
451 builtin_define ("__mips=64"); \
452 builtin_define ("__mips_isa_rev=1"); \
453 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
454 } \
455 else if (ISA_MIPS64R2) \
456 { \
457 builtin_define ("__mips=64"); \
458 builtin_define ("__mips_isa_rev=2"); \
459 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
460 } \
461 \
462 switch (mips_abi) \
463 { \
464 case ABI_32: \
465 builtin_define ("_ABIO32=1"); \
466 builtin_define ("_MIPS_SIM=_ABIO32"); \
467 break; \
468 \
469 case ABI_N32: \
470 builtin_define ("_ABIN32=2"); \
471 builtin_define ("_MIPS_SIM=_ABIN32"); \
472 break; \
473 \
474 case ABI_64: \
475 builtin_define ("_ABI64=3"); \
476 builtin_define ("_MIPS_SIM=_ABI64"); \
477 break; \
478 \
479 case ABI_O64: \
480 builtin_define ("_ABIO64=4"); \
481 builtin_define ("_MIPS_SIM=_ABIO64"); \
482 break; \
483 } \
484 \
485 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
486 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
487 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
488 builtin_define_with_int_value ("_MIPS_FPSET", \
489 32 / MAX_FPRS_PER_FMT); \
490 \
491 /* These defines reflect the ABI in use, not whether the \
492 FPU is directly accessible. */ \
493 if (TARGET_NO_FLOAT) \
494 builtin_define ("__mips_no_float"); \
495 else if (TARGET_HARD_FLOAT_ABI) \
496 builtin_define ("__mips_hard_float"); \
497 else \
498 builtin_define ("__mips_soft_float"); \
499 \
500 if (TARGET_SINGLE_FLOAT) \
501 builtin_define ("__mips_single_float"); \
502 \
503 if (TARGET_PAIRED_SINGLE_FLOAT) \
504 builtin_define ("__mips_paired_single_float"); \
505 \
506 if (TARGET_BIG_ENDIAN) \
507 { \
508 builtin_define_std ("MIPSEB"); \
509 builtin_define ("_MIPSEB"); \
510 } \
511 else \
512 { \
513 builtin_define_std ("MIPSEL"); \
514 builtin_define ("_MIPSEL"); \
515 } \
516 \
517 /* Whether calls should go through $25. The separate __PIC__ \
518 macro indicates whether abicalls code might use a GOT. */ \
519 if (TARGET_ABICALLS) \
520 builtin_define ("__mips_abicalls"); \
521 \
522 /* Whether Loongson vector modes are enabled. */ \
523 if (TARGET_LOONGSON_VECTORS) \
524 builtin_define ("__mips_loongson_vector_rev"); \
525 \
526 /* Historical Octeon macro. */ \
527 if (TARGET_OCTEON) \
528 builtin_define ("__OCTEON__"); \
529 \
530 if (TARGET_SYNCI) \
531 builtin_define ("__mips_synci"); \
532 \
533 /* Macros dependent on the C dialect. */ \
534 if (preprocessing_asm_p ()) \
535 { \
536 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
537 builtin_define ("_LANGUAGE_ASSEMBLY"); \
538 } \
539 else if (c_dialect_cxx ()) \
540 { \
541 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
542 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
543 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
544 } \
545 else \
546 { \
547 builtin_define_std ("LANGUAGE_C"); \
548 builtin_define ("_LANGUAGE_C"); \
549 } \
550 if (c_dialect_objc ()) \
551 { \
552 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
553 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
554 /* Bizarre, but retained for backwards compatibility. */ \
555 builtin_define_std ("LANGUAGE_C"); \
556 builtin_define ("_LANGUAGE_C"); \
557 } \
558 \
559 if (mips_abi == ABI_EABI) \
560 builtin_define ("__mips_eabi"); \
561 \
562 if (TARGET_CACHE_BUILTIN) \
563 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
564 } \
565 while (0)
566
567 /* Default target_flags if no switches are specified */
568
569 #ifndef TARGET_DEFAULT
570 #define TARGET_DEFAULT 0
571 #endif
572
573 #ifndef TARGET_CPU_DEFAULT
574 #define TARGET_CPU_DEFAULT 0
575 #endif
576
577 #ifndef TARGET_ENDIAN_DEFAULT
578 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
579 #endif
580
581 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
582 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
583 #endif
584
585 #ifdef IN_LIBGCC2
586 #undef TARGET_64BIT
587 /* Make this compile time constant for libgcc2 */
588 #ifdef __mips64
589 #define TARGET_64BIT 1
590 #else
591 #define TARGET_64BIT 0
592 #endif
593 #endif /* IN_LIBGCC2 */
594
595 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
596 when compiled with hardware floating point. This is because MIPS16
597 code cannot save and restore the floating-point registers, which is
598 important if in a mixed MIPS16/non-MIPS16 environment. */
599
600 #ifdef IN_LIBGCC2
601 #if __mips_hard_float
602 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
603 #endif
604 #endif /* IN_LIBGCC2 */
605
606 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
607
608 #ifndef MULTILIB_ENDIAN_DEFAULT
609 #if TARGET_ENDIAN_DEFAULT == 0
610 #define MULTILIB_ENDIAN_DEFAULT "EL"
611 #else
612 #define MULTILIB_ENDIAN_DEFAULT "EB"
613 #endif
614 #endif
615
616 #ifndef MULTILIB_ISA_DEFAULT
617 # if MIPS_ISA_DEFAULT == 1
618 # define MULTILIB_ISA_DEFAULT "mips1"
619 # else
620 # if MIPS_ISA_DEFAULT == 2
621 # define MULTILIB_ISA_DEFAULT "mips2"
622 # else
623 # if MIPS_ISA_DEFAULT == 3
624 # define MULTILIB_ISA_DEFAULT "mips3"
625 # else
626 # if MIPS_ISA_DEFAULT == 4
627 # define MULTILIB_ISA_DEFAULT "mips4"
628 # else
629 # if MIPS_ISA_DEFAULT == 32
630 # define MULTILIB_ISA_DEFAULT "mips32"
631 # else
632 # if MIPS_ISA_DEFAULT == 33
633 # define MULTILIB_ISA_DEFAULT "mips32r2"
634 # else
635 # if MIPS_ISA_DEFAULT == 64
636 # define MULTILIB_ISA_DEFAULT "mips64"
637 # else
638 # if MIPS_ISA_DEFAULT == 65
639 # define MULTILIB_ISA_DEFAULT "mips64r2"
640 # else
641 # define MULTILIB_ISA_DEFAULT "mips1"
642 # endif
643 # endif
644 # endif
645 # endif
646 # endif
647 # endif
648 # endif
649 # endif
650 #endif
651
652 #ifndef MIPS_ABI_DEFAULT
653 #define MIPS_ABI_DEFAULT ABI_32
654 #endif
655
656 /* Use the most portable ABI flag for the ASM specs. */
657
658 #if MIPS_ABI_DEFAULT == ABI_32
659 #define MULTILIB_ABI_DEFAULT "mabi=32"
660 #endif
661
662 #if MIPS_ABI_DEFAULT == ABI_O64
663 #define MULTILIB_ABI_DEFAULT "mabi=o64"
664 #endif
665
666 #if MIPS_ABI_DEFAULT == ABI_N32
667 #define MULTILIB_ABI_DEFAULT "mabi=n32"
668 #endif
669
670 #if MIPS_ABI_DEFAULT == ABI_64
671 #define MULTILIB_ABI_DEFAULT "mabi=64"
672 #endif
673
674 #if MIPS_ABI_DEFAULT == ABI_EABI
675 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
676 #endif
677
678 #ifndef MULTILIB_DEFAULTS
679 #define MULTILIB_DEFAULTS \
680 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
681 #endif
682
683 /* We must pass -EL to the linker by default for little endian embedded
684 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
685 linker will default to using big-endian output files. The OUTPUT_FORMAT
686 line must be in the linker script, otherwise -EB/-EL will not work. */
687
688 #ifndef ENDIAN_SPEC
689 #if TARGET_ENDIAN_DEFAULT == 0
690 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
691 #else
692 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
693 #endif
694 #endif
695
696 /* A spec condition that matches all non-mips16 -mips arguments. */
697
698 #define MIPS_ISA_LEVEL_OPTION_SPEC \
699 "mips1|mips2|mips3|mips4|mips32*|mips64*"
700
701 /* A spec condition that matches all non-mips16 architecture arguments. */
702
703 #define MIPS_ARCH_OPTION_SPEC \
704 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
705
706 /* A spec that infers a -mips argument from an -march argument,
707 or injects the default if no architecture is specified. */
708
709 #define MIPS_ISA_LEVEL_SPEC \
710 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
711 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
712 %{march=mips2|march=r6000:-mips2} \
713 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
714 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
715 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
716 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
717 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
718 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
719 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
720 |march=xlr|march=loongson3a: -mips64} \
721 %{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
722 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
723
724 /* A spec that infers a -mhard-float or -msoft-float setting from an
725 -march argument. Note that soft-float and hard-float code are not
726 link-compatible. */
727
728 #define MIPS_ARCH_FLOAT_SPEC \
729 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
730 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
731 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
732 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
733 march=*: -mhard-float}"
734
735 /* A spec condition that matches 32-bit options. It only works if
736 MIPS_ISA_LEVEL_SPEC has been applied. */
737
738 #define MIPS_32BIT_OPTION_SPEC \
739 "mips1|mips2|mips32*|mgp32"
740
741 /* Infer a -msynci setting from a -mips argument, on the assumption that
742 -msynci is desired where possible. */
743 #define MIPS_ISA_SYNCI_SPEC \
744 "%{msynci|mno-synci:;:%{mips32r2|mips64r2:-msynci;:-mno-synci}}"
745
746 #if MIPS_ABI_DEFAULT == ABI_O64 \
747 || MIPS_ABI_DEFAULT == ABI_N32 \
748 || MIPS_ABI_DEFAULT == ABI_64
749 #define OPT_ARCH64 "mabi=32|mgp32:;"
750 #define OPT_ARCH32 "mabi=32|mgp32"
751 #else
752 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
753 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
754 #endif
755
756 /* Support for a compile-time default CPU, et cetera. The rules are:
757 --with-arch is ignored if -march is specified or a -mips is specified
758 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
759 --with-tune is ignored if -mtune is specified; likewise
760 --with-tune-32 and --with-tune-64.
761 --with-abi is ignored if -mabi is specified.
762 --with-float is ignored if -mhard-float or -msoft-float are
763 specified.
764 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
765 specified. */
766 #define OPTION_DEFAULT_SPECS \
767 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
768 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
769 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
770 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
771 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
772 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
773 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
774 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
775 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
776 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
777 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
778 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
779
780 /* A spec that infers the -mdsp setting from an -march argument. */
781 #define BASE_DRIVER_SELF_SPECS \
782 "%{!mno-dsp: \
783 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
784 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
785
786 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
787
788 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
789 && ISA_HAS_COND_TRAP)
790
791 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
792
793 /* True if the ABI can only work with 64-bit integer registers. We
794 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
795 otherwise floating-point registers must also be 64-bit. */
796 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
797
798 /* Likewise for 32-bit regs. */
799 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
800
801 /* True if the file format uses 64-bit symbols. At present, this is
802 only true for n64, which uses 64-bit ELF. */
803 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
804
805 /* True if symbols are 64 bits wide. This is usually determined by
806 the ABI's file format, but it can be overridden by -msym32. Note that
807 overriding the size with -msym32 changes the ABI of relocatable objects,
808 although it doesn't change the ABI of a fully-linked object. */
809 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
810 && Pmode == DImode \
811 && !TARGET_SYM32)
812
813 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
814 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
815 || ISA_MIPS4 \
816 || ISA_MIPS64 \
817 || ISA_MIPS64R2)
818
819 /* ISA has branch likely instructions (e.g. mips2). */
820 /* Disable branchlikely for tx39 until compare rewrite. They haven't
821 been generated up to this point. */
822 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
823
824 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
825 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
826 || TARGET_MIPS5400 \
827 || TARGET_MIPS5500 \
828 || TARGET_MIPS7000 \
829 || TARGET_MIPS9000 \
830 || TARGET_MAD \
831 || ISA_MIPS32 \
832 || ISA_MIPS32R2 \
833 || ISA_MIPS64 \
834 || ISA_MIPS64R2) \
835 && !TARGET_MIPS16)
836
837 /* ISA has a three-operand multiplication instruction. */
838 #define ISA_HAS_DMUL3 (TARGET_64BIT \
839 && TARGET_OCTEON \
840 && !TARGET_MIPS16)
841
842 /* ISA has the floating-point conditional move instructions introduced
843 in mips4. */
844 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
845 || ISA_MIPS32 \
846 || ISA_MIPS32R2 \
847 || ISA_MIPS64 \
848 || ISA_MIPS64R2) \
849 && !TARGET_MIPS5500 \
850 && !TARGET_MIPS16)
851
852 /* ISA has the integer conditional move instructions introduced in mips4 and
853 ST Loongson 2E/2F. */
854 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
855
856 /* ISA has LDC1 and SDC1. */
857 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
858
859 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
860 branch on CC, and move (both FP and non-FP) on CC. */
861 #define ISA_HAS_8CC (ISA_MIPS4 \
862 || ISA_MIPS32 \
863 || ISA_MIPS32R2 \
864 || ISA_MIPS64 \
865 || ISA_MIPS64R2)
866
867 /* This is a catch all for other mips4 instructions: indexed load, the
868 FP madd and msub instructions, and the FP recip and recip sqrt
869 instructions. */
870 #define ISA_HAS_FP4 ((ISA_MIPS4 \
871 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
872 || ISA_MIPS64 \
873 || ISA_MIPS64R2) \
874 && !TARGET_MIPS16)
875
876 /* ISA has paired-single instructions. */
877 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
878
879 /* ISA has conditional trap instructions. */
880 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
881 && !TARGET_MIPS16)
882
883 /* ISA has integer multiply-accumulate instructions, madd and msub. */
884 #define ISA_HAS_MADD_MSUB (ISA_MIPS32 \
885 || ISA_MIPS32R2 \
886 || ISA_MIPS64 \
887 || ISA_MIPS64R2)
888
889 /* Integer multiply-accumulate instructions should be generated. */
890 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
891
892 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
893 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
894
895 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
896 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
897
898 /* ISA has floating-point nmadd and nmsub instructions
899 'd = -((a * b) [+-] c)'. */
900 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
901 ((ISA_MIPS4 \
902 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
903 || ISA_MIPS64 \
904 || ISA_MIPS64R2) \
905 && (!TARGET_MIPS5400 || TARGET_MAD) \
906 && !TARGET_MIPS16)
907
908 /* ISA has floating-point nmadd and nmsub instructions
909 'c = -((a * b) [+-] c)'. */
910 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
911 TARGET_LOONGSON_2EF
912
913 /* ISA has count leading zeroes/ones instruction (not implemented). */
914 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
915 || ISA_MIPS32R2 \
916 || ISA_MIPS64 \
917 || ISA_MIPS64R2) \
918 && !TARGET_MIPS16)
919
920 /* ISA has three operand multiply instructions that put
921 the high part in an accumulator: mulhi or mulhiu. */
922 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
923 || TARGET_MIPS5500 \
924 || TARGET_SR71K) \
925 && !TARGET_MIPS16)
926
927 /* ISA has three operand multiply instructions that
928 negates the result and puts the result in an accumulator. */
929 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
930 || TARGET_MIPS5500 \
931 || TARGET_SR71K) \
932 && !TARGET_MIPS16)
933
934 /* ISA has three operand multiply instructions that subtracts the
935 result from a 4th operand and puts the result in an accumulator. */
936 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
937 || TARGET_MIPS5500 \
938 || TARGET_SR71K) \
939 && !TARGET_MIPS16)
940
941 /* ISA has three operand multiply instructions that the result
942 from a 4th operand and puts the result in an accumulator. */
943 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
944 || TARGET_MIPS4130 \
945 || TARGET_MIPS5400 \
946 || TARGET_MIPS5500 \
947 || TARGET_SR71K) \
948 && !TARGET_MIPS16)
949
950 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
951 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
952 || TARGET_MIPS4130) \
953 && !TARGET_MIPS16)
954
955 /* ISA has the "ror" (rotate right) instructions. */
956 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
957 || ISA_MIPS64R2 \
958 || TARGET_MIPS5400 \
959 || TARGET_MIPS5500 \
960 || TARGET_SR71K \
961 || TARGET_SMARTMIPS) \
962 && !TARGET_MIPS16)
963
964 /* ISA has data prefetch instructions. This controls use of 'pref'. */
965 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
966 || TARGET_LOONGSON_2EF \
967 || ISA_MIPS32 \
968 || ISA_MIPS32R2 \
969 || ISA_MIPS64 \
970 || ISA_MIPS64R2) \
971 && !TARGET_MIPS16)
972
973 /* ISA has data indexed prefetch instructions. This controls use of
974 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
975 (prefx is a cop1x instruction, so can only be used if FP is
976 enabled.) */
977 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
978 || ISA_MIPS32R2 \
979 || ISA_MIPS64 \
980 || ISA_MIPS64R2) \
981 && !TARGET_MIPS16)
982
983 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
984 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
985 also requires TARGET_DOUBLE_FLOAT. */
986 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
987
988 /* ISA includes the MIPS32r2 seb and seh instructions. */
989 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
990 || ISA_MIPS64R2) \
991 && !TARGET_MIPS16)
992
993 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
994 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
995 || ISA_MIPS64R2) \
996 && !TARGET_MIPS16)
997
998 /* ISA has instructions for accessing top part of 64-bit fp regs. */
999 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
1000 && (ISA_MIPS32R2 \
1001 || ISA_MIPS64R2))
1002
1003 /* ISA has lwxs instruction (load w/scaled index address. */
1004 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1005 && !TARGET_MIPS16)
1006
1007 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1008 #define ISA_HAS_LBX (TARGET_OCTEON2)
1009 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1010 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1011 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1012 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1013 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1014 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1015 && TARGET_64BIT)
1016
1017 /* The DSP ASE is available. */
1018 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1019
1020 /* Revision 2 of the DSP ASE is available. */
1021 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1022
1023 /* True if the result of a load is not available to the next instruction.
1024 A nop will then be needed between instructions like "lw $4,..."
1025 and "addiu $4,$4,1". */
1026 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1027 && !TARGET_MIPS3900 \
1028 && !TARGET_MIPS16 \
1029 && !TARGET_MICROMIPS)
1030
1031 /* Likewise mtc1 and mfc1. */
1032 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1033 && !TARGET_LOONGSON_2EF)
1034
1035 /* Likewise floating-point comparisons. */
1036 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1037 && !TARGET_LOONGSON_2EF)
1038
1039 /* True if mflo and mfhi can be immediately followed by instructions
1040 which write to the HI and LO registers.
1041
1042 According to MIPS specifications, MIPS ISAs I, II, and III need
1043 (at least) two instructions between the reads of HI/LO and
1044 instructions which write them, and later ISAs do not. Contradicting
1045 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1046 the UM for the NEC Vr5000) document needing the instructions between
1047 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1048 MIPS64 and later ISAs to have the interlocks, plus any specific
1049 earlier-ISA CPUs for which CPU documentation declares that the
1050 instructions are really interlocked. */
1051 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1052 || ISA_MIPS32R2 \
1053 || ISA_MIPS64 \
1054 || ISA_MIPS64R2 \
1055 || TARGET_MIPS5500 \
1056 || TARGET_LOONGSON_2EF)
1057
1058 /* ISA includes synci, jr.hb and jalr.hb. */
1059 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1060 || ISA_MIPS64R2) \
1061 && !TARGET_MIPS16)
1062
1063 /* ISA includes sync. */
1064 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1065 #define GENERATE_SYNC \
1066 (target_flags_explicit & MASK_LLSC \
1067 ? TARGET_LLSC && !TARGET_MIPS16 \
1068 : ISA_HAS_SYNC)
1069
1070 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1071 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1072 instructions. */
1073 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1074 #define GENERATE_LL_SC \
1075 (target_flags_explicit & MASK_LLSC \
1076 ? TARGET_LLSC && !TARGET_MIPS16 \
1077 : ISA_HAS_LL_SC)
1078
1079 #define ISA_HAS_SWAP (TARGET_XLP)
1080 #define ISA_HAS_LDADD (TARGET_XLP)
1081
1082 /* ISA includes the baddu instruction. */
1083 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1084
1085 /* ISA includes the bbit* instructions. */
1086 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1087
1088 /* ISA includes the cins instruction. */
1089 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1090
1091 /* ISA includes the exts instruction. */
1092 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1093
1094 /* ISA includes the seq and sne instructions. */
1095 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1096
1097 /* ISA includes the pop instruction. */
1098 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1099
1100 /* The CACHE instruction is available in non-MIPS16 code. */
1101 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1102
1103 /* The CACHE instruction is available. */
1104 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1105 \f
1106 /* Tell collect what flags to pass to nm. */
1107 #ifndef NM_FLAGS
1108 #define NM_FLAGS "-Bn"
1109 #endif
1110
1111 \f
1112 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1113 the assembler. It may be overridden by subtargets.
1114
1115 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1116 COFF debugging info. */
1117
1118 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1119 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1120 %{g} %{g0} %{g1} %{g2} %{g3} \
1121 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1122 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1123 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1124 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1125 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1126 #endif
1127
1128 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1129 overridden by subtargets. */
1130
1131 #ifndef SUBTARGET_ASM_SPEC
1132 #define SUBTARGET_ASM_SPEC ""
1133 #endif
1134
1135 #undef ASM_SPEC
1136 #define ASM_SPEC "\
1137 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1138 %{mips32*} %{mips64*} \
1139 %{mips16} %{mno-mips16:-no-mips16} \
1140 %{mmicromips} %{mno-micromips} \
1141 %{mips3d} %{mno-mips3d:-no-mips3d} \
1142 %{mdmx} %{mno-mdmx:-no-mdmx} \
1143 %{mdsp} %{mno-dsp} \
1144 %{mdspr2} %{mno-dspr2} \
1145 %{mmcu} %{mno-mcu} \
1146 %{msmartmips} %{mno-smartmips} \
1147 %{mmt} %{mno-mt} \
1148 %{mfix-vr4120} %{mfix-vr4130} \
1149 %{mfix-24k} \
1150 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1151 %(subtarget_asm_debugging_spec) \
1152 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1153 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1154 %{mfp32} %{mfp64} \
1155 %{mshared} %{mno-shared} \
1156 %{msym32} %{mno-sym32} \
1157 %{mtune=*} \
1158 %(subtarget_asm_spec)"
1159
1160 /* Extra switches sometimes passed to the linker. */
1161
1162 #ifndef LINK_SPEC
1163 #define LINK_SPEC "\
1164 %(endian_spec) \
1165 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1166 %{shared}"
1167 #endif /* LINK_SPEC defined */
1168
1169
1170 /* Specs for the compiler proper */
1171
1172 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1173 overridden by subtargets. */
1174 #ifndef SUBTARGET_CC1_SPEC
1175 #define SUBTARGET_CC1_SPEC ""
1176 #endif
1177
1178 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1179
1180 #undef CC1_SPEC
1181 #define CC1_SPEC "\
1182 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1183 %(subtarget_cc1_spec)"
1184
1185 /* Preprocessor specs. */
1186
1187 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1188 overridden by subtargets. */
1189 #ifndef SUBTARGET_CPP_SPEC
1190 #define SUBTARGET_CPP_SPEC ""
1191 #endif
1192
1193 #define CPP_SPEC "%(subtarget_cpp_spec)"
1194
1195 /* This macro defines names of additional specifications to put in the specs
1196 that can be used in various specifications like CC1_SPEC. Its definition
1197 is an initializer with a subgrouping for each command option.
1198
1199 Each subgrouping contains a string constant, that defines the
1200 specification name, and a string constant that used by the GCC driver
1201 program.
1202
1203 Do not define this macro if it does not need to do anything. */
1204
1205 #define EXTRA_SPECS \
1206 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1207 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1208 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1209 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1210 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1211 { "endian_spec", ENDIAN_SPEC }, \
1212 SUBTARGET_EXTRA_SPECS
1213
1214 #ifndef SUBTARGET_EXTRA_SPECS
1215 #define SUBTARGET_EXTRA_SPECS
1216 #endif
1217 \f
1218 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1219 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1220
1221 #ifndef PREFERRED_DEBUGGING_TYPE
1222 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1223 #endif
1224
1225 /* The size of DWARF addresses should be the same as the size of symbols
1226 in the target file format. They shouldn't depend on things like -msym32,
1227 because many DWARF consumers do not allow the mixture of address sizes
1228 that one would then get from linking -msym32 code with -msym64 code.
1229
1230 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1231 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1232 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1233
1234 /* By default, turn on GDB extensions. */
1235 #define DEFAULT_GDB_EXTENSIONS 1
1236
1237 /* Local compiler-generated symbols must have a prefix that the assembler
1238 understands. By default, this is $, although some targets (e.g.,
1239 NetBSD-ELF) need to override this. */
1240
1241 #ifndef LOCAL_LABEL_PREFIX
1242 #define LOCAL_LABEL_PREFIX "$"
1243 #endif
1244
1245 /* By default on the mips, external symbols do not have an underscore
1246 prepended, but some targets (e.g., NetBSD) require this. */
1247
1248 #ifndef USER_LABEL_PREFIX
1249 #define USER_LABEL_PREFIX ""
1250 #endif
1251
1252 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1253 since the length can run past this up to a continuation point. */
1254 #undef DBX_CONTIN_LENGTH
1255 #define DBX_CONTIN_LENGTH 1500
1256
1257 /* How to renumber registers for dbx and gdb. */
1258 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1259
1260 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1261 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1262
1263 /* The DWARF 2 CFA column which tracks the return address. */
1264 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1265
1266 /* Before the prologue, RA lives in r31. */
1267 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1268
1269 /* Describe how we implement __builtin_eh_return. */
1270 #define EH_RETURN_DATA_REGNO(N) \
1271 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1272
1273 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1274
1275 #define EH_USES(N) mips_eh_uses (N)
1276
1277 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1278 The default for this in 64-bit mode is 8, which causes problems with
1279 SFmode register saves. */
1280 #define DWARF_CIE_DATA_ALIGNMENT -4
1281
1282 /* Correct the offset of automatic variables and arguments. Note that
1283 the MIPS debug format wants all automatic variables and arguments
1284 to be in terms of the virtual frame pointer (stack pointer before
1285 any adjustment in the function), while the MIPS 3.0 linker wants
1286 the frame pointer to be the stack pointer after the initial
1287 adjustment. */
1288
1289 #define DEBUGGER_AUTO_OFFSET(X) \
1290 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1291 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1292 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1293 \f
1294 /* Target machine storage layout */
1295
1296 #define BITS_BIG_ENDIAN 0
1297 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1298 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1299
1300 #define MAX_BITS_PER_WORD 64
1301
1302 /* Width of a word, in units (bytes). */
1303 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1304 #ifndef IN_LIBGCC2
1305 #define MIN_UNITS_PER_WORD 4
1306 #endif
1307
1308 /* For MIPS, width of a floating point register. */
1309 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1310
1311 /* The number of consecutive floating-point registers needed to store the
1312 largest format supported by the FPU. */
1313 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1314
1315 /* The number of consecutive floating-point registers needed to store the
1316 smallest format supported by the FPU. */
1317 #define MIN_FPRS_PER_FMT \
1318 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1319 ? 1 : MAX_FPRS_PER_FMT)
1320
1321 /* The largest size of value that can be held in floating-point
1322 registers and moved with a single instruction. */
1323 #define UNITS_PER_HWFPVALUE \
1324 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1325
1326 /* The largest size of value that can be held in floating-point
1327 registers. */
1328 #define UNITS_PER_FPVALUE \
1329 (TARGET_SOFT_FLOAT_ABI ? 0 \
1330 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1331 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1332
1333 /* The number of bytes in a double. */
1334 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1335
1336 /* Set the sizes of the core types. */
1337 #define SHORT_TYPE_SIZE 16
1338 #define INT_TYPE_SIZE 32
1339 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1340 #define LONG_LONG_TYPE_SIZE 64
1341
1342 #define FLOAT_TYPE_SIZE 32
1343 #define DOUBLE_TYPE_SIZE 64
1344 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1345
1346 /* Define the sizes of fixed-point types. */
1347 #define SHORT_FRACT_TYPE_SIZE 8
1348 #define FRACT_TYPE_SIZE 16
1349 #define LONG_FRACT_TYPE_SIZE 32
1350 #define LONG_LONG_FRACT_TYPE_SIZE 64
1351
1352 #define SHORT_ACCUM_TYPE_SIZE 16
1353 #define ACCUM_TYPE_SIZE 32
1354 #define LONG_ACCUM_TYPE_SIZE 64
1355 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1356 doesn't support 128-bit integers for MIPS32 currently. */
1357 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1358
1359 /* long double is not a fixed mode, but the idea is that, if we
1360 support long double, we also want a 128-bit integer type. */
1361 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1362
1363 #ifdef IN_LIBGCC2
1364 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1365 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1366 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1367 # else
1368 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1369 # endif
1370 #endif
1371
1372 /* Width in bits of a pointer. */
1373 #ifndef POINTER_SIZE
1374 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1375 #endif
1376
1377 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1378 #define PARM_BOUNDARY BITS_PER_WORD
1379
1380 /* Allocation boundary (in *bits*) for the code of a function. */
1381 #define FUNCTION_BOUNDARY 32
1382
1383 /* Alignment of field after `int : 0' in a structure. */
1384 #define EMPTY_FIELD_BOUNDARY 32
1385
1386 /* Every structure's size must be a multiple of this. */
1387 /* 8 is observed right on a DECstation and on riscos 4.02. */
1388 #define STRUCTURE_SIZE_BOUNDARY 8
1389
1390 /* There is no point aligning anything to a rounder boundary than this. */
1391 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1392
1393 /* All accesses must be aligned. */
1394 #define STRICT_ALIGNMENT 1
1395
1396 /* Define this if you wish to imitate the way many other C compilers
1397 handle alignment of bitfields and the structures that contain
1398 them.
1399
1400 The behavior is that the type written for a bit-field (`int',
1401 `short', or other integer type) imposes an alignment for the
1402 entire structure, as if the structure really did contain an
1403 ordinary field of that type. In addition, the bit-field is placed
1404 within the structure so that it would fit within such a field,
1405 not crossing a boundary for it.
1406
1407 Thus, on most machines, a bit-field whose type is written as `int'
1408 would not cross a four-byte boundary, and would force four-byte
1409 alignment for the whole structure. (The alignment used may not
1410 be four bytes; it is controlled by the other alignment
1411 parameters.)
1412
1413 If the macro is defined, its definition should be a C expression;
1414 a nonzero value for the expression enables this behavior. */
1415
1416 #define PCC_BITFIELD_TYPE_MATTERS 1
1417
1418 /* If defined, a C expression to compute the alignment given to a
1419 constant that is being placed in memory. CONSTANT is the constant
1420 and ALIGN is the alignment that the object would ordinarily have.
1421 The value of this macro is used instead of that alignment to align
1422 the object.
1423
1424 If this macro is not defined, then ALIGN is used.
1425
1426 The typical use of this macro is to increase alignment for string
1427 constants to be word aligned so that `strcpy' calls that copy
1428 constants can be done inline. */
1429
1430 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1431 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1432 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1433
1434 /* If defined, a C expression to compute the alignment for a static
1435 variable. TYPE is the data type, and ALIGN is the alignment that
1436 the object would ordinarily have. The value of this macro is used
1437 instead of that alignment to align the object.
1438
1439 If this macro is not defined, then ALIGN is used.
1440
1441 One use of this macro is to increase alignment of medium-size
1442 data to make it all fit in fewer cache lines. Another is to
1443 cause character arrays to be word-aligned so that `strcpy' calls
1444 that copy constants to character arrays can be done inline. */
1445
1446 #undef DATA_ALIGNMENT
1447 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1448 ((((ALIGN) < BITS_PER_WORD) \
1449 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1450 || TREE_CODE (TYPE) == UNION_TYPE \
1451 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1452
1453 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1454 character arrays to be word-aligned so that `strcpy' calls that copy
1455 constants to character arrays can be done inline, and 'strcmp' can be
1456 optimised to use word loads. */
1457 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1458 DATA_ALIGNMENT (TYPE, ALIGN)
1459
1460 #define PAD_VARARGS_DOWN \
1461 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1462
1463 /* Define if operations between registers always perform the operation
1464 on the full register even if a narrower mode is specified. */
1465 #define WORD_REGISTER_OPERATIONS
1466
1467 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1468 moves. All other references are zero extended. */
1469 #define LOAD_EXTEND_OP(MODE) \
1470 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1471 ? SIGN_EXTEND : ZERO_EXTEND)
1472
1473 /* Define this macro if it is advisable to hold scalars in registers
1474 in a wider mode than that declared by the program. In such cases,
1475 the value is constrained to be within the bounds of the declared
1476 type, but kept valid in the wider mode. The signedness of the
1477 extension may differ from that of the type. */
1478
1479 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1480 if (GET_MODE_CLASS (MODE) == MODE_INT \
1481 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1482 { \
1483 if ((MODE) == SImode) \
1484 (UNSIGNEDP) = 0; \
1485 (MODE) = Pmode; \
1486 }
1487
1488 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1489 Extensions of pointers to word_mode must be signed. */
1490 #define POINTERS_EXTEND_UNSIGNED false
1491
1492 /* Define if loading short immediate values into registers sign extends. */
1493 #define SHORT_IMMEDIATES_SIGN_EXTEND
1494
1495 /* The [d]clz instructions have the natural values at 0. */
1496
1497 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1498 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1499 \f
1500 /* Standard register usage. */
1501
1502 /* Number of hardware registers. We have:
1503
1504 - 32 integer registers
1505 - 32 floating point registers
1506 - 8 condition code registers
1507 - 2 accumulator registers (hi and lo)
1508 - 32 registers each for coprocessors 0, 2 and 3
1509 - 4 fake registers:
1510 - ARG_POINTER_REGNUM
1511 - FRAME_POINTER_REGNUM
1512 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1513 - CPRESTORE_SLOT_REGNUM
1514 - 2 dummy entries that were used at various times in the past.
1515 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1516 - 6 DSP control registers */
1517
1518 #define FIRST_PSEUDO_REGISTER 188
1519
1520 /* By default, fix the kernel registers ($26 and $27), the global
1521 pointer ($28) and the stack pointer ($29). This can change
1522 depending on the command-line options.
1523
1524 Regarding coprocessor registers: without evidence to the contrary,
1525 it's best to assume that each coprocessor register has a unique
1526 use. This can be overridden, in, e.g., mips_option_override or
1527 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1528 inappropriate for a particular target. */
1529
1530 #define FIXED_REGISTERS \
1531 { \
1532 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1533 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1534 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1535 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1536 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1537 /* COP0 registers */ \
1538 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1539 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1540 /* COP2 registers */ \
1541 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1542 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1543 /* COP3 registers */ \
1544 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1545 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1546 /* 6 DSP accumulator registers & 6 control registers */ \
1547 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1548 }
1549
1550
1551 /* Set up this array for o32 by default.
1552
1553 Note that we don't mark $31 as a call-clobbered register. The idea is
1554 that it's really the call instructions themselves which clobber $31.
1555 We don't care what the called function does with it afterwards.
1556
1557 This approach makes it easier to implement sibcalls. Unlike normal
1558 calls, sibcalls don't clobber $31, so the register reaches the
1559 called function in tact. EPILOGUE_USES says that $31 is useful
1560 to the called function. */
1561
1562 #define CALL_USED_REGISTERS \
1563 { \
1564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1565 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1567 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1568 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1569 /* COP0 registers */ \
1570 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1571 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1572 /* COP2 registers */ \
1573 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1575 /* COP3 registers */ \
1576 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1578 /* 6 DSP accumulator registers & 6 control registers */ \
1579 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1580 }
1581
1582
1583 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1584
1585 #define CALL_REALLY_USED_REGISTERS \
1586 { /* General registers. */ \
1587 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1588 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1589 /* Floating-point registers. */ \
1590 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1591 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1592 /* Others. */ \
1593 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1594 /* COP0 registers */ \
1595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1596 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1597 /* COP2 registers */ \
1598 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1599 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1600 /* COP3 registers */ \
1601 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1602 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1603 /* 6 DSP accumulator registers & 6 control registers */ \
1604 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1605 }
1606
1607 /* Internal macros to classify a register number as to whether it's a
1608 general purpose register, a floating point register, a
1609 multiply/divide register, or a status register. */
1610
1611 #define GP_REG_FIRST 0
1612 #define GP_REG_LAST 31
1613 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1614 #define GP_DBX_FIRST 0
1615 #define K0_REG_NUM (GP_REG_FIRST + 26)
1616 #define K1_REG_NUM (GP_REG_FIRST + 27)
1617 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1618
1619 #define FP_REG_FIRST 32
1620 #define FP_REG_LAST 63
1621 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1622 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1623
1624 #define MD_REG_FIRST 64
1625 #define MD_REG_LAST 65
1626 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1627 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1628
1629 /* The DWARF 2 CFA column which tracks the return address from a
1630 signal handler context. This means that to maintain backwards
1631 compatibility, no hard register can be assigned this column if it
1632 would need to be handled by the DWARF unwinder. */
1633 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1634
1635 #define ST_REG_FIRST 67
1636 #define ST_REG_LAST 74
1637 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1638
1639
1640 /* FIXME: renumber. */
1641 #define COP0_REG_FIRST 80
1642 #define COP0_REG_LAST 111
1643 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1644
1645 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1646 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1647 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1648
1649 #define COP2_REG_FIRST 112
1650 #define COP2_REG_LAST 143
1651 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1652
1653 #define COP3_REG_FIRST 144
1654 #define COP3_REG_LAST 175
1655 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1656
1657 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1658 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1659 #define ALL_COP_REG_LAST COP3_REG_LAST
1660 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1661
1662 #define DSP_ACC_REG_FIRST 176
1663 #define DSP_ACC_REG_LAST 181
1664 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1665
1666 #define AT_REGNUM (GP_REG_FIRST + 1)
1667 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1668 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1669
1670 /* A few bitfield locations for the coprocessor registers. */
1671 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1672 the cause register for the EIC interrupt mode. */
1673 #define CAUSE_IPL 10
1674 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1675 #define SR_IPL 10
1676 /* Exception Level is at bit 1 of the status register. */
1677 #define SR_EXL 1
1678 /* Interrupt Enable is at bit 0 of the status register. */
1679 #define SR_IE 0
1680
1681 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1682 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1683 should be used instead. */
1684 #define FPSW_REGNUM ST_REG_FIRST
1685
1686 #define GP_REG_P(REGNO) \
1687 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1688 #define M16_REG_P(REGNO) \
1689 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1690 #define M16STORE_REG_P(REGNO) \
1691 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1692 #define FP_REG_P(REGNO) \
1693 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1694 #define MD_REG_P(REGNO) \
1695 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1696 #define ST_REG_P(REGNO) \
1697 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1698 #define COP0_REG_P(REGNO) \
1699 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1700 #define COP2_REG_P(REGNO) \
1701 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1702 #define COP3_REG_P(REGNO) \
1703 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1704 #define ALL_COP_REG_P(REGNO) \
1705 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1706 /* Test if REGNO is one of the 6 new DSP accumulators. */
1707 #define DSP_ACC_REG_P(REGNO) \
1708 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1709 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1710 #define ACC_REG_P(REGNO) \
1711 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1712
1713 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1714
1715 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1716 to initialize the mips16 gp pseudo register. */
1717 #define CONST_GP_P(X) \
1718 (GET_CODE (X) == CONST \
1719 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1720 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1721
1722 /* Return coprocessor number from register number. */
1723
1724 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1725 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1726 : COP3_REG_P (REGNO) ? '3' : '?')
1727
1728
1729 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1730
1731 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1732 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1733
1734 #define MODES_TIEABLE_P mips_modes_tieable_p
1735
1736 /* Register to use for pushing function arguments. */
1737 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1738
1739 /* These two registers don't really exist: they get eliminated to either
1740 the stack or hard frame pointer. */
1741 #define ARG_POINTER_REGNUM 77
1742 #define FRAME_POINTER_REGNUM 78
1743
1744 /* $30 is not available on the mips16, so we use $17 as the frame
1745 pointer. */
1746 #define HARD_FRAME_POINTER_REGNUM \
1747 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1748
1749 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1750 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1751
1752 /* Register in which static-chain is passed to a function. */
1753 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1754
1755 /* Registers used as temporaries in prologue/epilogue code:
1756
1757 - If a MIPS16 PIC function needs access to _gp, it first loads
1758 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1759
1760 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1761 register. The register must not conflict with MIPS16_PIC_TEMP.
1762
1763 - If we aren't generating MIPS16 code, the prologue can also use
1764 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1765
1766 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1767 register.
1768
1769 If we're generating MIPS16 code, these registers must come from the
1770 core set of 8. The prologue registers mustn't conflict with any
1771 incoming arguments, the static chain pointer, or the frame pointer.
1772 The epilogue temporary mustn't conflict with the return registers,
1773 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1774 or the EH data registers.
1775
1776 If we're generating interrupt handlers, we use K0 as a temporary register
1777 in prologue/epilogue code. */
1778
1779 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1780 #define MIPS_PROLOGUE_TEMP_REGNUM \
1781 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1782 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1783 (TARGET_MIPS16 \
1784 ? (gcc_unreachable (), INVALID_REGNUM) \
1785 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1786 #define MIPS_EPILOGUE_TEMP_REGNUM \
1787 (cfun->machine->interrupt_handler_p \
1788 ? K0_REG_NUM \
1789 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1790
1791 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1792 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1793 #define MIPS_PROLOGUE_TEMP2(MODE) \
1794 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1795 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1796
1797 /* Define this macro if it is as good or better to call a constant
1798 function address than to call an address kept in a register. */
1799 #define NO_FUNCTION_CSE 1
1800
1801 /* The ABI-defined global pointer. Sometimes we use a different
1802 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1803 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1804
1805 /* We normally use $28 as the global pointer. However, when generating
1806 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1807 register instead. They can then avoid saving and restoring $28
1808 and perhaps avoid using a frame at all.
1809
1810 When a leaf function uses something other than $28, mips_expand_prologue
1811 will modify pic_offset_table_rtx in place. Take the register number
1812 from there after reload. */
1813 #define PIC_OFFSET_TABLE_REGNUM \
1814 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1815 \f
1816 /* Define the classes of registers for register constraints in the
1817 machine description. Also define ranges of constants.
1818
1819 One of the classes must always be named ALL_REGS and include all hard regs.
1820 If there is more than one class, another class must be named NO_REGS
1821 and contain no registers.
1822
1823 The name GENERAL_REGS must be the name of a class (or an alias for
1824 another name such as ALL_REGS). This is the class of registers
1825 that is allowed by "g" or "r" in a register constraint.
1826 Also, registers outside this class are allocated only when
1827 instructions express preferences for them.
1828
1829 The classes must be numbered in nondecreasing order; that is,
1830 a larger-numbered class must never be contained completely
1831 in a smaller-numbered class.
1832
1833 For any two classes, it is very desirable that there be another
1834 class that represents their union. */
1835
1836 enum reg_class
1837 {
1838 NO_REGS, /* no registers in set */
1839 M16_REGS, /* mips16 directly accessible registers */
1840 T_REG, /* mips16 T register ($24) */
1841 M16_T_REGS, /* mips16 registers plus T register */
1842 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1843 V1_REG, /* Register $v1 ($3) used for TLS access. */
1844 LEA_REGS, /* Every GPR except $25 */
1845 GR_REGS, /* integer registers */
1846 FP_REGS, /* floating point registers */
1847 MD0_REG, /* first multiply/divide register */
1848 MD1_REG, /* second multiply/divide register */
1849 MD_REGS, /* multiply/divide registers (hi/lo) */
1850 COP0_REGS, /* generic coprocessor classes */
1851 COP2_REGS,
1852 COP3_REGS,
1853 ST_REGS, /* status registers (fp status) */
1854 DSP_ACC_REGS, /* DSP accumulator registers */
1855 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1856 FRAME_REGS, /* $arg and $frame */
1857 GR_AND_MD0_REGS, /* union classes */
1858 GR_AND_MD1_REGS,
1859 GR_AND_MD_REGS,
1860 GR_AND_ACC_REGS,
1861 ALL_REGS, /* all registers */
1862 LIM_REG_CLASSES /* max value + 1 */
1863 };
1864
1865 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1866
1867 #define GENERAL_REGS GR_REGS
1868
1869 /* An initializer containing the names of the register classes as C
1870 string constants. These names are used in writing some of the
1871 debugging dumps. */
1872
1873 #define REG_CLASS_NAMES \
1874 { \
1875 "NO_REGS", \
1876 "M16_REGS", \
1877 "T_REG", \
1878 "M16_T_REGS", \
1879 "PIC_FN_ADDR_REG", \
1880 "V1_REG", \
1881 "LEA_REGS", \
1882 "GR_REGS", \
1883 "FP_REGS", \
1884 "MD0_REG", \
1885 "MD1_REG", \
1886 "MD_REGS", \
1887 /* coprocessor registers */ \
1888 "COP0_REGS", \
1889 "COP2_REGS", \
1890 "COP3_REGS", \
1891 "ST_REGS", \
1892 "DSP_ACC_REGS", \
1893 "ACC_REGS", \
1894 "FRAME_REGS", \
1895 "GR_AND_MD0_REGS", \
1896 "GR_AND_MD1_REGS", \
1897 "GR_AND_MD_REGS", \
1898 "GR_AND_ACC_REGS", \
1899 "ALL_REGS" \
1900 }
1901
1902 /* An initializer containing the contents of the register classes,
1903 as integers which are bit masks. The Nth integer specifies the
1904 contents of class N. The way the integer MASK is interpreted is
1905 that register R is in the class if `MASK & (1 << R)' is 1.
1906
1907 When the machine has more than 32 registers, an integer does not
1908 suffice. Then the integers are replaced by sub-initializers,
1909 braced groupings containing several integers. Each
1910 sub-initializer must be suitable as an initializer for the type
1911 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1912
1913 #define REG_CLASS_CONTENTS \
1914 { \
1915 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1916 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1917 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1918 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1919 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1920 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1921 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1922 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1923 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1924 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1925 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1926 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1927 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1928 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1929 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1930 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1931 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1932 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1933 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1934 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1935 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1936 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1937 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1938 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1939 }
1940
1941
1942 /* A C expression whose value is a register class containing hard
1943 register REGNO. In general there is more that one such class;
1944 choose a class which is "minimal", meaning that no smaller class
1945 also contains the register. */
1946
1947 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1948
1949 /* A macro whose definition is the name of the class to which a
1950 valid base register must belong. A base register is one used in
1951 an address which is the register value plus a displacement. */
1952
1953 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1954
1955 /* A macro whose definition is the name of the class to which a
1956 valid index register must belong. An index register is one used
1957 in an address where its value is either multiplied by a scale
1958 factor or added to another register (as well as added to a
1959 displacement). */
1960
1961 #define INDEX_REG_CLASS NO_REGS
1962
1963 /* We generally want to put call-clobbered registers ahead of
1964 call-saved ones. (IRA expects this.) */
1965
1966 #define REG_ALLOC_ORDER \
1967 { /* Accumulator registers. When GPRs and accumulators have equal \
1968 cost, we generally prefer to use accumulators. For example, \
1969 a division of multiplication result is better allocated to LO, \
1970 so that we put the MFLO at the point of use instead of at the \
1971 point of definition. It's also needed if we're to take advantage \
1972 of the extra accumulators available with -mdspr2. In some cases, \
1973 it can also help to reduce register pressure. */ \
1974 64, 65,176,177,178,179,180,181, \
1975 /* Call-clobbered GPRs. */ \
1976 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1977 24, 25, 31, \
1978 /* The global pointer. This is call-clobbered for o32 and o64 \
1979 abicalls, call-saved for n32 and n64 abicalls, and a program \
1980 invariant otherwise. Putting it between the call-clobbered \
1981 and call-saved registers should cope with all eventualities. */ \
1982 28, \
1983 /* Call-saved GPRs. */ \
1984 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1985 /* GPRs that can never be exposed to the register allocator. */ \
1986 0, 26, 27, 29, \
1987 /* Call-clobbered FPRs. */ \
1988 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1989 48, 49, 50, 51, \
1990 /* FPRs that are usually call-saved. The odd ones are actually \
1991 call-clobbered for n32, but listing them ahead of the even \
1992 registers might encourage the register allocator to fragment \
1993 the available FPR pairs. We need paired FPRs to store long \
1994 doubles, so it isn't clear that using a different order \
1995 for n32 would be a win. */ \
1996 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1997 /* None of the remaining classes have defined call-saved \
1998 registers. */ \
1999 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2000 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2001 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2002 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2003 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2004 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2005 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2006 182,183,184,185,186,187 \
2007 }
2008
2009 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
2010 to be rearranged based on a particular function. On the mips16, we
2011 want to allocate $24 (T_REG) before other registers for
2012 instructions for which it is possible. */
2013
2014 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2015
2016 /* True if VALUE is an unsigned 6-bit number. */
2017
2018 #define UIMM6_OPERAND(VALUE) \
2019 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2020
2021 /* True if VALUE is a signed 10-bit number. */
2022
2023 #define IMM10_OPERAND(VALUE) \
2024 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2025
2026 /* True if VALUE is a signed 16-bit number. */
2027
2028 #define SMALL_OPERAND(VALUE) \
2029 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2030
2031 /* True if VALUE is an unsigned 16-bit number. */
2032
2033 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2034 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2035
2036 /* True if VALUE can be loaded into a register using LUI. */
2037
2038 #define LUI_OPERAND(VALUE) \
2039 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2040 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2041
2042 /* Return a value X with the low 16 bits clear, and such that
2043 VALUE - X is a signed 16-bit value. */
2044
2045 #define CONST_HIGH_PART(VALUE) \
2046 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2047
2048 #define CONST_LOW_PART(VALUE) \
2049 ((VALUE) - CONST_HIGH_PART (VALUE))
2050
2051 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2052 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2053 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2054 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2055
2056 /* The HI and LO registers can only be reloaded via the general
2057 registers. Condition code registers can only be loaded to the
2058 general registers, and from the floating point registers. */
2059
2060 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2061 mips_secondary_reload_class (CLASS, MODE, X, true)
2062 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2063 mips_secondary_reload_class (CLASS, MODE, X, false)
2064
2065 /* Return the maximum number of consecutive registers
2066 needed to represent mode MODE in a register of class CLASS. */
2067
2068 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2069
2070 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2071 mips_cannot_change_mode_class (FROM, TO, CLASS)
2072 \f
2073 /* Stack layout; function entry, exit and calling. */
2074
2075 #define STACK_GROWS_DOWNWARD
2076
2077 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2078
2079 /* Size of the area allocated in the frame to save the GP. */
2080
2081 #define MIPS_GP_SAVE_AREA_SIZE \
2082 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2083
2084 /* The offset of the first local variable from the frame pointer. See
2085 mips_compute_frame_info for details about the frame layout. */
2086
2087 #define STARTING_FRAME_OFFSET \
2088 (FRAME_GROWS_DOWNWARD \
2089 ? 0 \
2090 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2091
2092 #define RETURN_ADDR_RTX mips_return_addr
2093
2094 /* Mask off the MIPS16 ISA bit in unwind addresses.
2095
2096 The reason for this is a little subtle. When unwinding a call,
2097 we are given the call's return address, which on most targets
2098 is the address of the following instruction. However, what we
2099 actually want to find is the EH region for the call itself.
2100 The target-independent unwind code therefore searches for "RA - 1".
2101
2102 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2103 RA - 1 is therefore the real (even-valued) start of the return
2104 instruction. EH region labels are usually odd-valued MIPS16 symbols
2105 too, so a search for an even address within a MIPS16 region would
2106 usually work.
2107
2108 However, there is an exception. If the end of an EH region is also
2109 the end of a function, the end label is allowed to be even. This is
2110 necessary because a following non-MIPS16 function may also need EH
2111 information for its first instruction.
2112
2113 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2114 non-ISA-encoded address. This probably isn't ideal, but it is
2115 the traditional (legacy) behavior. It is therefore only safe
2116 to search MIPS EH regions for an _odd-valued_ address.
2117
2118 Masking off the ISA bit means that the target-independent code
2119 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2120 #define MASK_RETURN_ADDR GEN_INT (-2)
2121
2122
2123 /* Similarly, don't use the least-significant bit to tell pointers to
2124 code from vtable index. */
2125
2126 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2127
2128 /* The eliminations to $17 are only used for mips16 code. See the
2129 definition of HARD_FRAME_POINTER_REGNUM. */
2130
2131 #define ELIMINABLE_REGS \
2132 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2133 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2134 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2135 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2136 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2137 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2138
2139 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2140 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2141
2142 /* Allocate stack space for arguments at the beginning of each function. */
2143 #define ACCUMULATE_OUTGOING_ARGS 1
2144
2145 /* The argument pointer always points to the first argument. */
2146 #define FIRST_PARM_OFFSET(FNDECL) 0
2147
2148 /* o32 and o64 reserve stack space for all argument registers. */
2149 #define REG_PARM_STACK_SPACE(FNDECL) \
2150 (TARGET_OLDABI \
2151 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2152 : 0)
2153
2154 /* Define this if it is the responsibility of the caller to
2155 allocate the area reserved for arguments passed in registers.
2156 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2157 of this macro is to determine whether the space is included in
2158 `crtl->outgoing_args_size'. */
2159 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2160
2161 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2162 \f
2163 /* Symbolic macros for the registers used to return integer and floating
2164 point values. */
2165
2166 #define GP_RETURN (GP_REG_FIRST + 2)
2167 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2168
2169 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2170
2171 /* Symbolic macros for the first/last argument registers. */
2172
2173 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2174 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2175 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2176 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2177
2178 /* 1 if N is a possible register number for function argument passing.
2179 We have no FP argument registers when soft-float. When FP registers
2180 are 32 bits, we can't directly reference the odd numbered ones. */
2181
2182 #define FUNCTION_ARG_REGNO_P(N) \
2183 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2184 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2185 && !fixed_regs[N])
2186 \f
2187 /* This structure has to cope with two different argument allocation
2188 schemes. Most MIPS ABIs view the arguments as a structure, of which
2189 the first N words go in registers and the rest go on the stack. If I
2190 < N, the Ith word might go in Ith integer argument register or in a
2191 floating-point register. For these ABIs, we only need to remember
2192 the offset of the current argument into the structure.
2193
2194 The EABI instead allocates the integer and floating-point arguments
2195 separately. The first N words of FP arguments go in FP registers,
2196 the rest go on the stack. Likewise, the first N words of the other
2197 arguments go in integer registers, and the rest go on the stack. We
2198 need to maintain three counts: the number of integer registers used,
2199 the number of floating-point registers used, and the number of words
2200 passed on the stack.
2201
2202 We could keep separate information for the two ABIs (a word count for
2203 the standard ABIs, and three separate counts for the EABI). But it
2204 seems simpler to view the standard ABIs as forms of EABI that do not
2205 allocate floating-point registers.
2206
2207 So for the standard ABIs, the first N words are allocated to integer
2208 registers, and mips_function_arg decides on an argument-by-argument
2209 basis whether that argument should really go in an integer register,
2210 or in a floating-point one. */
2211
2212 typedef struct mips_args {
2213 /* Always true for varargs functions. Otherwise true if at least
2214 one argument has been passed in an integer register. */
2215 int gp_reg_found;
2216
2217 /* The number of arguments seen so far. */
2218 unsigned int arg_number;
2219
2220 /* The number of integer registers used so far. For all ABIs except
2221 EABI, this is the number of words that have been added to the
2222 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2223 unsigned int num_gprs;
2224
2225 /* For EABI, the number of floating-point registers used so far. */
2226 unsigned int num_fprs;
2227
2228 /* The number of words passed on the stack. */
2229 unsigned int stack_words;
2230
2231 /* On the mips16, we need to keep track of which floating point
2232 arguments were passed in general registers, but would have been
2233 passed in the FP regs if this were a 32-bit function, so that we
2234 can move them to the FP regs if we wind up calling a 32-bit
2235 function. We record this information in fp_code, encoded in base
2236 four. A zero digit means no floating point argument, a one digit
2237 means an SFmode argument, and a two digit means a DFmode argument,
2238 and a three digit is not used. The low order digit is the first
2239 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2240 an SFmode argument. ??? A more sophisticated approach will be
2241 needed if MIPS_ABI != ABI_32. */
2242 int fp_code;
2243
2244 /* True if the function has a prototype. */
2245 int prototype;
2246 } CUMULATIVE_ARGS;
2247
2248 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2249 for a call to a function whose data type is FNTYPE.
2250 For a library call, FNTYPE is 0. */
2251
2252 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2253 mips_init_cumulative_args (&CUM, FNTYPE)
2254
2255 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2256 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2257
2258 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2259 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2260
2261 /* True if using EABI and varargs can be passed in floating-point
2262 registers. Under these conditions, we need a more complex form
2263 of va_list, which tracks GPR, FPR and stack arguments separately. */
2264 #define EABI_FLOAT_VARARGS_P \
2265 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2266
2267 \f
2268 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2269
2270 /* Treat LOC as a byte offset from the stack pointer and round it up
2271 to the next fully-aligned offset. */
2272 #define MIPS_STACK_ALIGN(LOC) \
2273 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2274
2275 \f
2276 /* Output assembler code to FILE to increment profiler label # LABELNO
2277 for profiling a function entry. */
2278
2279 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2280
2281 /* The profiler preserves all interesting registers, including $31. */
2282 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2283
2284 /* No mips port has ever used the profiler counter word, so don't emit it
2285 or the label for it. */
2286
2287 #define NO_PROFILE_COUNTERS 1
2288
2289 /* Define this macro if the code for function profiling should come
2290 before the function prologue. Normally, the profiling code comes
2291 after. */
2292
2293 /* #define PROFILE_BEFORE_PROLOGUE */
2294
2295 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2296 the stack pointer does not matter. The value is tested only in
2297 functions that have frame pointers.
2298 No definition is equivalent to always zero. */
2299
2300 #define EXIT_IGNORE_STACK 1
2301
2302 \f
2303 /* Trampolines are a block of code followed by two pointers. */
2304
2305 #define TRAMPOLINE_SIZE \
2306 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2307
2308 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2309 pointers from a single LUI base. */
2310
2311 #define TRAMPOLINE_ALIGNMENT 64
2312
2313 /* mips_trampoline_init calls this library function to flush
2314 program and data caches. */
2315
2316 #ifndef CACHE_FLUSH_FUNC
2317 #define CACHE_FLUSH_FUNC "_flush_cache"
2318 #endif
2319
2320 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2321 /* Flush both caches. We need to flush the data cache in case \
2322 the system has a write-back cache. */ \
2323 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2324 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2325 GEN_INT (3), TYPE_MODE (integer_type_node))
2326
2327 \f
2328 /* Addressing modes, and classification of registers for them. */
2329
2330 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2331 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2332 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2333 \f
2334 /* Maximum number of registers that can appear in a valid memory address. */
2335
2336 #define MAX_REGS_PER_ADDRESS 1
2337
2338 /* Check for constness inline but use mips_legitimate_address_p
2339 to check whether a constant really is an address. */
2340
2341 #define CONSTANT_ADDRESS_P(X) \
2342 (CONSTANT_P (X) && memory_address_p (SImode, X))
2343
2344 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2345 'the start of the function that this code is output in'. */
2346
2347 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2348 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2349 asm_fprintf ((FILE), "%U%s", \
2350 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2351 else \
2352 asm_fprintf ((FILE), "%U%s", (NAME))
2353 \f
2354 /* Flag to mark a function decl symbol that requires a long call. */
2355 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2356 #define SYMBOL_REF_LONG_CALL_P(X) \
2357 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2358
2359 /* This flag marks functions that cannot be lazily bound. */
2360 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2361 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2362 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2363
2364 /* True if we're generating a form of MIPS16 code in which jump tables
2365 are stored in the text section and encoded as 16-bit PC-relative
2366 offsets. This is only possible when general text loads are allowed,
2367 since the table access itself will be an "lh" instruction. If the
2368 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2369 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2370
2371 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2372
2373 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2374
2375 /* Only use short offsets if their range will not overflow. */
2376 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2377 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2378 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2379 : SImode)
2380
2381 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2382
2383 /* Define this as 1 if `char' should by default be signed; else as 0. */
2384 #ifndef DEFAULT_SIGNED_CHAR
2385 #define DEFAULT_SIGNED_CHAR 1
2386 #endif
2387
2388 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2389 we generally don't want to use them for copying arbitrary data.
2390 A single N-word move is usually the same cost as N single-word moves. */
2391 #define MOVE_MAX UNITS_PER_WORD
2392 #define MAX_MOVE_MAX 8
2393
2394 /* Define this macro as a C expression which is nonzero if
2395 accessing less than a word of memory (i.e. a `char' or a
2396 `short') is no faster than accessing a word of memory, i.e., if
2397 such access require more than one instruction or if there is no
2398 difference in cost between byte and (aligned) word loads.
2399
2400 On RISC machines, it tends to generate better code to define
2401 this as 1, since it avoids making a QI or HI mode register.
2402
2403 But, generating word accesses for -mips16 is generally bad as shifts
2404 (often extended) would be needed for byte accesses. */
2405 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2406
2407 /* Standard MIPS integer shifts truncate the shift amount to the
2408 width of the shifted operand. However, Loongson vector shifts
2409 do not truncate the shift amount at all. */
2410 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2411
2412 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2413 is done just by pretending it is already truncated. */
2414 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2415 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2416
2417
2418 /* Specify the machine mode that pointers have.
2419 After generation of rtl, the compiler makes no further distinction
2420 between pointers and any other objects of this machine mode. */
2421
2422 #ifndef Pmode
2423 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2424 #endif
2425
2426 /* Give call MEMs SImode since it is the "most permissive" mode
2427 for both 32-bit and 64-bit targets. */
2428
2429 #define FUNCTION_MODE SImode
2430
2431 \f
2432 /* We allocate $fcc registers by hand and can't cope with moves of
2433 CCmode registers to and from pseudos (or memory). */
2434 #define AVOID_CCMODE_COPIES
2435
2436 /* A C expression for the cost of a branch instruction. A value of
2437 1 is the default; other values are interpreted relative to that. */
2438
2439 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2440 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2441
2442 /* The MIPS port has several functions that return an instruction count.
2443 Multiplying the count by this value gives the number of bytes that
2444 the instructions occupy. */
2445 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2446
2447 /* The length of a NOP in bytes. */
2448 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2449
2450 /* If defined, modifies the length assigned to instruction INSN as a
2451 function of the context in which it is used. LENGTH is an lvalue
2452 that contains the initially computed length of the insn and should
2453 be updated with the correct length of the insn. */
2454 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2455 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2456
2457 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2458 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2459 its operands. */
2460 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2461 "%*" OPCODE "%?\t" OPERANDS "%/"
2462
2463 /* Return an asm string that forces INSN to be treated as an absolute
2464 J or JAL instruction instead of an assembler macro. */
2465 #define MIPS_ABSOLUTE_JUMP(INSN) \
2466 (TARGET_ABICALLS_PIC2 \
2467 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2468 : INSN)
2469
2470 /* Return the asm template for a call. INSN is the instruction's mnemonic
2471 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2472 number of the target. SIZE_OPNO is the operand number of the argument size
2473 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2474 -1 and the call is indirect, use the function symbol from the call
2475 attributes to attach a R_MIPS_JALR relocation to the call.
2476
2477 When generating GOT code without explicit relocation operators,
2478 all calls should use assembly macros. Otherwise, all indirect
2479 calls should use "jr" or "jalr"; we will arrange to restore $gp
2480 afterwards if necessary. Finally, we can only generate direct
2481 calls for -mabicalls by temporarily switching to non-PIC mode.
2482
2483 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2484 instruction is in the delay slot of jal(r). */
2485 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2486 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2487 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2488 : REG_P (OPERANDS[TARGET_OPNO]) \
2489 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2490 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2491 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2492 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2493 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2494 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2495 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2496
2497 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2498 "jrc" when nop is in the delay slot of "jr". */
2499
2500 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2501 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2502 ? "%*j\t%" #OPNO "%/" \
2503 : REG_P (OPERANDS[OPNO]) \
2504 ? "%*jr%:\t%" #OPNO \
2505 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2506
2507 \f
2508 /* Control the assembler format that we output. */
2509
2510 /* Output to assembler file text saying following lines
2511 may contain character constants, extra white space, comments, etc. */
2512
2513 #ifndef ASM_APP_ON
2514 #define ASM_APP_ON " #APP\n"
2515 #endif
2516
2517 /* Output to assembler file text saying following lines
2518 no longer contain unusual constructs. */
2519
2520 #ifndef ASM_APP_OFF
2521 #define ASM_APP_OFF " #NO_APP\n"
2522 #endif
2523
2524 #define REGISTER_NAMES \
2525 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2526 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2527 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2528 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2529 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2530 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2531 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2532 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2533 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2534 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2535 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2536 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2537 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2538 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2539 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2540 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2541 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2542 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2543 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2544 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2545 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2546 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2547 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2548 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2549
2550 /* List the "software" names for each register. Also list the numerical
2551 names for $fp and $sp. */
2552
2553 #define ADDITIONAL_REGISTER_NAMES \
2554 { \
2555 { "$29", 29 + GP_REG_FIRST }, \
2556 { "$30", 30 + GP_REG_FIRST }, \
2557 { "at", 1 + GP_REG_FIRST }, \
2558 { "v0", 2 + GP_REG_FIRST }, \
2559 { "v1", 3 + GP_REG_FIRST }, \
2560 { "a0", 4 + GP_REG_FIRST }, \
2561 { "a1", 5 + GP_REG_FIRST }, \
2562 { "a2", 6 + GP_REG_FIRST }, \
2563 { "a3", 7 + GP_REG_FIRST }, \
2564 { "t0", 8 + GP_REG_FIRST }, \
2565 { "t1", 9 + GP_REG_FIRST }, \
2566 { "t2", 10 + GP_REG_FIRST }, \
2567 { "t3", 11 + GP_REG_FIRST }, \
2568 { "t4", 12 + GP_REG_FIRST }, \
2569 { "t5", 13 + GP_REG_FIRST }, \
2570 { "t6", 14 + GP_REG_FIRST }, \
2571 { "t7", 15 + GP_REG_FIRST }, \
2572 { "s0", 16 + GP_REG_FIRST }, \
2573 { "s1", 17 + GP_REG_FIRST }, \
2574 { "s2", 18 + GP_REG_FIRST }, \
2575 { "s3", 19 + GP_REG_FIRST }, \
2576 { "s4", 20 + GP_REG_FIRST }, \
2577 { "s5", 21 + GP_REG_FIRST }, \
2578 { "s6", 22 + GP_REG_FIRST }, \
2579 { "s7", 23 + GP_REG_FIRST }, \
2580 { "t8", 24 + GP_REG_FIRST }, \
2581 { "t9", 25 + GP_REG_FIRST }, \
2582 { "k0", 26 + GP_REG_FIRST }, \
2583 { "k1", 27 + GP_REG_FIRST }, \
2584 { "gp", 28 + GP_REG_FIRST }, \
2585 { "sp", 29 + GP_REG_FIRST }, \
2586 { "fp", 30 + GP_REG_FIRST }, \
2587 { "ra", 31 + GP_REG_FIRST } \
2588 }
2589
2590 #define DBR_OUTPUT_SEQEND(STREAM) \
2591 do \
2592 { \
2593 /* Undo the effect of '%*'. */ \
2594 mips_pop_asm_switch (&mips_nomacro); \
2595 mips_pop_asm_switch (&mips_noreorder); \
2596 /* Emit a blank line after the delay slot for emphasis. */ \
2597 fputs ("\n", STREAM); \
2598 } \
2599 while (0)
2600
2601 /* The MIPS implementation uses some labels for its own purpose. The
2602 following lists what labels are created, and are all formed by the
2603 pattern $L[a-z].*. The machine independent portion of GCC creates
2604 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2605
2606 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2607 $Lb[0-9]+ Begin blocks for MIPS debug support
2608 $Lc[0-9]+ Label for use in s<xx> operation.
2609 $Le[0-9]+ End blocks for MIPS debug support */
2610
2611 #undef ASM_DECLARE_OBJECT_NAME
2612 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2613 mips_declare_object (STREAM, NAME, "", ":\n")
2614
2615 /* Globalizing directive for a label. */
2616 #define GLOBAL_ASM_OP "\t.globl\t"
2617
2618 /* This says how to define a global common symbol. */
2619
2620 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2621
2622 /* This says how to define a local common symbol (i.e., not visible to
2623 linker). */
2624
2625 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2626 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2627 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2628 #endif
2629
2630 /* This says how to output an external. It would be possible not to
2631 output anything and let undefined symbol become external. However
2632 the assembler uses length information on externals to allocate in
2633 data/sdata bss/sbss, thereby saving exec time. */
2634
2635 #undef ASM_OUTPUT_EXTERNAL
2636 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2637 mips_output_external(STREAM,DECL,NAME)
2638
2639 /* This is how to declare a function name. The actual work of
2640 emitting the label is moved to function_prologue, so that we can
2641 get the line number correctly emitted before the .ent directive,
2642 and after any .file directives. Define as empty so that the function
2643 is not declared before the .ent directive elsewhere. */
2644
2645 #undef ASM_DECLARE_FUNCTION_NAME
2646 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2647
2648 /* This is how to store into the string LABEL
2649 the symbol_ref name of an internal numbered label where
2650 PREFIX is the class of label and NUM is the number within the class.
2651 This is suitable for output with `assemble_name'. */
2652
2653 #undef ASM_GENERATE_INTERNAL_LABEL
2654 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2655 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2656
2657 /* Print debug labels as "foo = ." rather than "foo:" because they should
2658 represent a byte pointer rather than an ISA-encoded address. This is
2659 particularly important for code like:
2660
2661 $LFBxxx = .
2662 .cfi_startproc
2663 ...
2664 .section .gcc_except_table,...
2665 ...
2666 .uleb128 foo-$LFBxxx
2667
2668 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2669 likewise a byte pointer rather than an ISA-encoded address.
2670
2671 At the time of writing, this hook is not used for the function end
2672 label:
2673
2674 $LFExxx:
2675 .end foo
2676
2677 But this doesn't matter, because GAS doesn't treat a pre-.end label
2678 as a MIPS16 one anyway. */
2679
2680 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2681 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2682
2683 /* This is how to output an element of a case-vector that is absolute. */
2684
2685 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2686 fprintf (STREAM, "\t%s\t%sL%d\n", \
2687 ptr_mode == DImode ? ".dword" : ".word", \
2688 LOCAL_LABEL_PREFIX, \
2689 VALUE)
2690
2691 /* This is how to output an element of a case-vector. We can make the
2692 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2693 is supported. */
2694
2695 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2696 do { \
2697 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2698 { \
2699 if (GET_MODE (BODY) == HImode) \
2700 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2701 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2702 else \
2703 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2704 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2705 } \
2706 else if (TARGET_GPWORD) \
2707 fprintf (STREAM, "\t%s\t%sL%d\n", \
2708 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2709 LOCAL_LABEL_PREFIX, VALUE); \
2710 else if (TARGET_RTP_PIC) \
2711 { \
2712 /* Make the entry relative to the start of the function. */ \
2713 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2714 fprintf (STREAM, "\t%s\t%sL%d-", \
2715 Pmode == DImode ? ".dword" : ".word", \
2716 LOCAL_LABEL_PREFIX, VALUE); \
2717 assemble_name (STREAM, XSTR (fnsym, 0)); \
2718 fprintf (STREAM, "\n"); \
2719 } \
2720 else \
2721 fprintf (STREAM, "\t%s\t%sL%d\n", \
2722 ptr_mode == DImode ? ".dword" : ".word", \
2723 LOCAL_LABEL_PREFIX, VALUE); \
2724 } while (0)
2725
2726 /* This is how to output an assembler line
2727 that says to advance the location counter
2728 to a multiple of 2**LOG bytes. */
2729
2730 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2731 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2732
2733 /* This is how to output an assembler line to advance the location
2734 counter by SIZE bytes. */
2735
2736 #undef ASM_OUTPUT_SKIP
2737 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2738 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2739
2740 /* This is how to output a string. */
2741 #undef ASM_OUTPUT_ASCII
2742 #define ASM_OUTPUT_ASCII mips_output_ascii
2743
2744 \f
2745 /* Default to -G 8 */
2746 #ifndef MIPS_DEFAULT_GVALUE
2747 #define MIPS_DEFAULT_GVALUE 8
2748 #endif
2749
2750 /* Define the strings to put out for each section in the object file. */
2751 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2752 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2753
2754 #undef READONLY_DATA_SECTION_ASM_OP
2755 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2756 \f
2757 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2758 do \
2759 { \
2760 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2761 TARGET_64BIT ? "daddiu" : "addiu", \
2762 reg_names[STACK_POINTER_REGNUM], \
2763 reg_names[STACK_POINTER_REGNUM], \
2764 TARGET_64BIT ? "sd" : "sw", \
2765 reg_names[REGNO], \
2766 reg_names[STACK_POINTER_REGNUM]); \
2767 } \
2768 while (0)
2769
2770 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2771 do \
2772 { \
2773 mips_push_asm_switch (&mips_noreorder); \
2774 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2775 TARGET_64BIT ? "ld" : "lw", \
2776 reg_names[REGNO], \
2777 reg_names[STACK_POINTER_REGNUM], \
2778 TARGET_64BIT ? "daddu" : "addu", \
2779 reg_names[STACK_POINTER_REGNUM], \
2780 reg_names[STACK_POINTER_REGNUM]); \
2781 mips_pop_asm_switch (&mips_noreorder); \
2782 } \
2783 while (0)
2784
2785 /* How to start an assembler comment.
2786 The leading space is important (the mips native assembler requires it). */
2787 #ifndef ASM_COMMENT_START
2788 #define ASM_COMMENT_START " #"
2789 #endif
2790 \f
2791 #undef SIZE_TYPE
2792 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2793
2794 #undef PTRDIFF_TYPE
2795 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2796
2797 /* The maximum number of bytes that can be copied by one iteration of
2798 a movmemsi loop; see mips_block_move_loop. */
2799 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2800 (UNITS_PER_WORD * 4)
2801
2802 /* The maximum number of bytes that can be copied by a straight-line
2803 implementation of movmemsi; see mips_block_move_straight. We want
2804 to make sure that any loop-based implementation will iterate at
2805 least twice. */
2806 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2807 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2808
2809 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2810 values were determined experimentally by benchmarking with CSiBE.
2811 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2812 for o32 where we have to restore $gp afterwards as well as make an
2813 indirect call), but in practice, bumping this up higher for
2814 TARGET_ABICALLS doesn't make much difference to code size. */
2815
2816 #define MIPS_CALL_RATIO 8
2817
2818 /* Any loop-based implementation of movmemsi will have at least
2819 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2820 moves, so allow individual copies of fewer elements.
2821
2822 When movmemsi is not available, use a value approximating
2823 the length of a memcpy call sequence, so that move_by_pieces
2824 will generate inline code if it is shorter than a function call.
2825 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2826 we'll have to generate a load/store pair for each, halve the
2827 value of MIPS_CALL_RATIO to take that into account. */
2828
2829 #define MOVE_RATIO(speed) \
2830 (HAVE_movmemsi \
2831 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2832 : MIPS_CALL_RATIO / 2)
2833
2834 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2835 mips_move_by_pieces_p (SIZE, ALIGN)
2836
2837 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2838 of the length of a memset call, but use the default otherwise. */
2839
2840 #define CLEAR_RATIO(speed)\
2841 ((speed) ? 15 : MIPS_CALL_RATIO)
2842
2843 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2844 optimizing for size adjust the ratio to account for the overhead of
2845 loading the constant and replicating it across the word. */
2846
2847 #define SET_RATIO(speed) \
2848 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2849
2850 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2851 mips_store_by_pieces_p (SIZE, ALIGN)
2852 \f
2853 /* Since the bits of the _init and _fini function is spread across
2854 many object files, each potentially with its own GP, we must assume
2855 we need to load our GP. We don't preserve $gp or $ra, since each
2856 init/fini chunk is supposed to initialize $gp, and crti/crtn
2857 already take care of preserving $ra and, when appropriate, $gp. */
2858 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2859 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2860 asm (SECTION_OP "\n\
2861 .set push\n\
2862 .set nomips16\n\
2863 .set noreorder\n\
2864 bal 1f\n\
2865 nop\n\
2866 1: .cpload $31\n\
2867 .set reorder\n\
2868 jal " USER_LABEL_PREFIX #FUNC "\n\
2869 .set pop\n\
2870 " TEXT_SECTION_ASM_OP);
2871 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2872 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2873 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2874 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2875 asm (SECTION_OP "\n\
2876 .set push\n\
2877 .set nomips16\n\
2878 .set noreorder\n\
2879 bal 1f\n\
2880 nop\n\
2881 1: .set reorder\n\
2882 .cpsetup $31, $2, 1b\n\
2883 jal " USER_LABEL_PREFIX #FUNC "\n\
2884 .set pop\n\
2885 " TEXT_SECTION_ASM_OP);
2886 #endif
2887
2888 #ifndef HAVE_AS_TLS
2889 #define HAVE_AS_TLS 0
2890 #endif
2891
2892 #ifndef USED_FOR_TARGET
2893 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2894 struct mips_asm_switch {
2895 /* The FOO in the description above. */
2896 const char *name;
2897
2898 /* The current block nesting level, or 0 if we aren't in a block. */
2899 int nesting_level;
2900 };
2901
2902 extern const enum reg_class mips_regno_to_class[];
2903 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2904 extern const char *current_function_file; /* filename current function is in */
2905 extern int num_source_filenames; /* current .file # */
2906 extern struct mips_asm_switch mips_noreorder;
2907 extern struct mips_asm_switch mips_nomacro;
2908 extern struct mips_asm_switch mips_noat;
2909 extern int mips_dbx_regno[];
2910 extern int mips_dwarf_regno[];
2911 extern bool mips_split_p[];
2912 extern bool mips_split_hi_p[];
2913 extern bool mips_use_pcrel_pool_p[];
2914 extern const char *mips_lo_relocs[];
2915 extern const char *mips_hi_relocs[];
2916 extern enum processor mips_arch; /* which cpu to codegen for */
2917 extern enum processor mips_tune; /* which cpu to schedule for */
2918 extern int mips_isa; /* architectural level */
2919 extern const struct mips_cpu_info *mips_arch_info;
2920 extern const struct mips_cpu_info *mips_tune_info;
2921 extern unsigned int mips_base_compression_flags;
2922 extern GTY(()) struct target_globals *mips16_globals;
2923 #endif
2924
2925 /* Enable querying of DFA units. */
2926 #define CPU_UNITS_QUERY 1
2927
2928 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2929 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2930
2931 /* As on most targets, we want the .eh_frame section to be read-only where
2932 possible. And as on most targets, this means two things:
2933
2934 (a) Non-locally-binding pointers must have an indirect encoding,
2935 so that the addresses in the .eh_frame section itself become
2936 locally-binding.
2937
2938 (b) A shared library's .eh_frame section must encode locally-binding
2939 pointers in a relative (relocation-free) form.
2940
2941 However, MIPS has traditionally not allowed directives like:
2942
2943 .long x-.
2944
2945 in cases where "x" is in a different section, or is not defined in the
2946 same assembly file. We are therefore unable to emit the PC-relative
2947 form required by (b) at assembly time.
2948
2949 Fortunately, the linker is able to convert absolute addresses into
2950 PC-relative addresses on our behalf. Unfortunately, only certain
2951 versions of the linker know how to do this for indirect pointers,
2952 and for personality data. We must fall back on using writable
2953 .eh_frame sections for shared libraries if the linker does not
2954 support this feature. */
2955 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2956 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2957
2958 /* For switching between MIPS16 and non-MIPS16 modes. */
2959 #define SWITCHABLE_TARGET 1
2960
2961 /* Several named MIPS patterns depend on Pmode. These patterns have the
2962 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2963 Add the appropriate suffix to generator function NAME and invoke it
2964 with arguments ARGS. */
2965 #define PMODE_INSN(NAME, ARGS) \
2966 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)