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mips.c (mips_order_regs_for_local_alloc): Delete.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS32R3 (mips_isa == 34)
212 #define ISA_MIPS32R5 (mips_isa == 36)
213 #define ISA_MIPS64 (mips_isa == 64)
214 #define ISA_MIPS64R2 (mips_isa == 65)
215 #define ISA_MIPS64R3 (mips_isa == 66)
216 #define ISA_MIPS64R5 (mips_isa == 68)
217
218 /* Architecture target defines. */
219 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
220 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
221 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
222 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
223 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
224 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
225 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
226 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
227 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
228 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
229 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
230 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
231 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
232 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
233 || mips_arch == PROCESSOR_OCTEON2)
234 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
235 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
236 || mips_arch == PROCESSOR_SB1A)
237 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
238 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
239
240 /* Scheduling target defines. */
241 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
242 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
243 || mips_tune == PROCESSOR_24KF2_1 \
244 || mips_tune == PROCESSOR_24KF1_1)
245 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
246 || mips_tune == PROCESSOR_74KF2_1 \
247 || mips_tune == PROCESSOR_74KF1_1 \
248 || mips_tune == PROCESSOR_74KF3_2)
249 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
250 || mips_tune == PROCESSOR_LOONGSON_2F)
251 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
252 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
253 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
254 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
255 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
256 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
257 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
258 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
259 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
260 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
261 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
262 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
263 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
264 || mips_tune == PROCESSOR_OCTEON2)
265 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
266 || mips_tune == PROCESSOR_SB1A)
267 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
268
269 /* Whether vector modes and intrinsics for ST Microelectronics
270 Loongson-2E/2F processors should be enabled. In o32 pairs of
271 floating-point registers provide 64-bit values. */
272 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
273 && (TARGET_LOONGSON_2EF \
274 || TARGET_LOONGSON_3A))
275
276 /* True if the pre-reload scheduler should try to create chains of
277 multiply-add or multiply-subtract instructions. For example,
278 suppose we have:
279
280 t1 = a * b
281 t2 = t1 + c * d
282 t3 = e * f
283 t4 = t3 - g * h
284
285 t1 will have a higher priority than t2 and t3 will have a higher
286 priority than t4. However, before reload, there is no dependence
287 between t1 and t3, and they can often have similar priorities.
288 The scheduler will then tend to prefer:
289
290 t1 = a * b
291 t3 = e * f
292 t2 = t1 + c * d
293 t4 = t3 - g * h
294
295 which stops us from making full use of macc/madd-style instructions.
296 This sort of situation occurs frequently in Fourier transforms and
297 in unrolled loops.
298
299 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
300 queue so that chained multiply-add and multiply-subtract instructions
301 appear ahead of any other instruction that is likely to clobber lo.
302 In the example above, if t2 and t3 become ready at the same time,
303 the code ensures that t2 is scheduled first.
304
305 Multiply-accumulate instructions are a bigger win for some targets
306 than others, so this macro is defined on an opt-in basis. */
307 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
308 || TUNE_MIPS4120 \
309 || TUNE_MIPS4130 \
310 || TUNE_24K \
311 || TUNE_P5600)
312
313 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
314 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
315
316 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
317 directly accessible, while the command-line options select
318 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
319 in use. */
320 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
321 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
322
323 /* False if SC acts as a memory barrier with respect to itself,
324 otherwise a SYNC will be emitted after SC for atomic operations
325 that require ordering between the SC and following loads and
326 stores. It does not tell anything about ordering of loads and
327 stores prior to and following the SC, only about the SC itself and
328 those loads and stores follow it. */
329 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
330
331 /* Define preprocessor macros for the -march and -mtune options.
332 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
333 processor. If INFO's canonical name is "foo", define PREFIX to
334 be "foo", and define an additional macro PREFIX_FOO. */
335 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
336 do \
337 { \
338 char *macro, *p; \
339 \
340 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
341 for (p = macro; *p != 0; p++) \
342 if (*p == '+') \
343 *p = 'P'; \
344 else \
345 *p = TOUPPER (*p); \
346 \
347 builtin_define (macro); \
348 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
349 free (macro); \
350 } \
351 while (0)
352
353 /* Target CPU builtins. */
354 #define TARGET_CPU_CPP_BUILTINS() \
355 do \
356 { \
357 builtin_assert ("machine=mips"); \
358 builtin_assert ("cpu=mips"); \
359 builtin_define ("__mips__"); \
360 builtin_define ("_mips"); \
361 \
362 /* We do this here because __mips is defined below and so we \
363 can't use builtin_define_std. We don't ever want to define \
364 "mips" for VxWorks because some of the VxWorks headers \
365 construct include filenames from a root directory macro, \
366 an architecture macro and a filename, where the architecture \
367 macro expands to 'mips'. If we define 'mips' to 1, the \
368 architecture macro expands to 1 as well. */ \
369 if (!flag_iso && !TARGET_VXWORKS) \
370 builtin_define ("mips"); \
371 \
372 if (TARGET_64BIT) \
373 builtin_define ("__mips64"); \
374 \
375 /* Treat _R3000 and _R4000 like register-size \
376 defines, which is how they've historically \
377 been used. */ \
378 if (TARGET_64BIT) \
379 { \
380 builtin_define_std ("R4000"); \
381 builtin_define ("_R4000"); \
382 } \
383 else \
384 { \
385 builtin_define_std ("R3000"); \
386 builtin_define ("_R3000"); \
387 } \
388 \
389 if (TARGET_FLOAT64) \
390 builtin_define ("__mips_fpr=64"); \
391 else \
392 builtin_define ("__mips_fpr=32"); \
393 \
394 if (mips_base_compression_flags & MASK_MIPS16) \
395 builtin_define ("__mips16"); \
396 \
397 if (TARGET_MIPS3D) \
398 builtin_define ("__mips3d"); \
399 \
400 if (TARGET_SMARTMIPS) \
401 builtin_define ("__mips_smartmips"); \
402 \
403 if (mips_base_compression_flags & MASK_MICROMIPS) \
404 builtin_define ("__mips_micromips"); \
405 \
406 if (TARGET_MCU) \
407 builtin_define ("__mips_mcu"); \
408 \
409 if (TARGET_EVA) \
410 builtin_define ("__mips_eva"); \
411 \
412 if (TARGET_DSP) \
413 { \
414 builtin_define ("__mips_dsp"); \
415 if (TARGET_DSPR2) \
416 { \
417 builtin_define ("__mips_dspr2"); \
418 builtin_define ("__mips_dsp_rev=2"); \
419 } \
420 else \
421 builtin_define ("__mips_dsp_rev=1"); \
422 } \
423 \
424 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
425 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
426 \
427 if (ISA_MIPS1) \
428 { \
429 builtin_define ("__mips=1"); \
430 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
431 } \
432 else if (ISA_MIPS2) \
433 { \
434 builtin_define ("__mips=2"); \
435 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
436 } \
437 else if (ISA_MIPS3) \
438 { \
439 builtin_define ("__mips=3"); \
440 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
441 } \
442 else if (ISA_MIPS4) \
443 { \
444 builtin_define ("__mips=4"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
446 } \
447 else if (ISA_MIPS32) \
448 { \
449 builtin_define ("__mips=32"); \
450 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
451 } \
452 else if (ISA_MIPS32R2) \
453 { \
454 builtin_define ("__mips=32"); \
455 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
456 } \
457 else if (ISA_MIPS32R3) \
458 { \
459 builtin_define ("__mips=32"); \
460 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
461 } \
462 else if (ISA_MIPS32R5) \
463 { \
464 builtin_define ("__mips=32"); \
465 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
466 } \
467 else if (ISA_MIPS64) \
468 { \
469 builtin_define ("__mips=64"); \
470 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
471 } \
472 else if (ISA_MIPS64R2) \
473 { \
474 builtin_define ("__mips=64"); \
475 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
476 } \
477 else if (ISA_MIPS64R3) \
478 { \
479 builtin_define ("__mips=64"); \
480 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
481 } \
482 else if (ISA_MIPS64R5) \
483 { \
484 builtin_define ("__mips=64"); \
485 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
486 } \
487 if (mips_isa_rev > 0) \
488 builtin_define_with_int_value ("__mips_isa_rev", \
489 mips_isa_rev); \
490 \
491 switch (mips_abi) \
492 { \
493 case ABI_32: \
494 builtin_define ("_ABIO32=1"); \
495 builtin_define ("_MIPS_SIM=_ABIO32"); \
496 break; \
497 \
498 case ABI_N32: \
499 builtin_define ("_ABIN32=2"); \
500 builtin_define ("_MIPS_SIM=_ABIN32"); \
501 break; \
502 \
503 case ABI_64: \
504 builtin_define ("_ABI64=3"); \
505 builtin_define ("_MIPS_SIM=_ABI64"); \
506 break; \
507 \
508 case ABI_O64: \
509 builtin_define ("_ABIO64=4"); \
510 builtin_define ("_MIPS_SIM=_ABIO64"); \
511 break; \
512 } \
513 \
514 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
515 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
516 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
517 builtin_define_with_int_value ("_MIPS_FPSET", \
518 32 / MAX_FPRS_PER_FMT); \
519 \
520 /* These defines reflect the ABI in use, not whether the \
521 FPU is directly accessible. */ \
522 if (TARGET_NO_FLOAT) \
523 builtin_define ("__mips_no_float"); \
524 else if (TARGET_HARD_FLOAT_ABI) \
525 builtin_define ("__mips_hard_float"); \
526 else \
527 builtin_define ("__mips_soft_float"); \
528 \
529 if (TARGET_SINGLE_FLOAT) \
530 builtin_define ("__mips_single_float"); \
531 \
532 if (TARGET_PAIRED_SINGLE_FLOAT) \
533 builtin_define ("__mips_paired_single_float"); \
534 \
535 if (mips_abs == MIPS_IEEE_754_2008) \
536 builtin_define ("__mips_abs2008"); \
537 \
538 if (mips_nan == MIPS_IEEE_754_2008) \
539 builtin_define ("__mips_nan2008"); \
540 \
541 if (TARGET_BIG_ENDIAN) \
542 { \
543 builtin_define_std ("MIPSEB"); \
544 builtin_define ("_MIPSEB"); \
545 } \
546 else \
547 { \
548 builtin_define_std ("MIPSEL"); \
549 builtin_define ("_MIPSEL"); \
550 } \
551 \
552 /* Whether calls should go through $25. The separate __PIC__ \
553 macro indicates whether abicalls code might use a GOT. */ \
554 if (TARGET_ABICALLS) \
555 builtin_define ("__mips_abicalls"); \
556 \
557 /* Whether Loongson vector modes are enabled. */ \
558 if (TARGET_LOONGSON_VECTORS) \
559 builtin_define ("__mips_loongson_vector_rev"); \
560 \
561 /* Historical Octeon macro. */ \
562 if (TARGET_OCTEON) \
563 builtin_define ("__OCTEON__"); \
564 \
565 if (TARGET_SYNCI) \
566 builtin_define ("__mips_synci"); \
567 \
568 /* Macros dependent on the C dialect. */ \
569 if (preprocessing_asm_p ()) \
570 { \
571 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
572 builtin_define ("_LANGUAGE_ASSEMBLY"); \
573 } \
574 else if (c_dialect_cxx ()) \
575 { \
576 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
577 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
578 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
579 } \
580 else \
581 { \
582 builtin_define_std ("LANGUAGE_C"); \
583 builtin_define ("_LANGUAGE_C"); \
584 } \
585 if (c_dialect_objc ()) \
586 { \
587 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
588 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
589 /* Bizarre, but retained for backwards compatibility. */ \
590 builtin_define_std ("LANGUAGE_C"); \
591 builtin_define ("_LANGUAGE_C"); \
592 } \
593 \
594 if (mips_abi == ABI_EABI) \
595 builtin_define ("__mips_eabi"); \
596 \
597 if (TARGET_CACHE_BUILTIN) \
598 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
599 } \
600 while (0)
601
602 /* Default target_flags if no switches are specified */
603
604 #ifndef TARGET_DEFAULT
605 #define TARGET_DEFAULT 0
606 #endif
607
608 #ifndef TARGET_CPU_DEFAULT
609 #define TARGET_CPU_DEFAULT 0
610 #endif
611
612 #ifndef TARGET_ENDIAN_DEFAULT
613 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
614 #endif
615
616 #ifdef IN_LIBGCC2
617 #undef TARGET_64BIT
618 /* Make this compile time constant for libgcc2 */
619 #ifdef __mips64
620 #define TARGET_64BIT 1
621 #else
622 #define TARGET_64BIT 0
623 #endif
624 #endif /* IN_LIBGCC2 */
625
626 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
627 when compiled with hardware floating point. This is because MIPS16
628 code cannot save and restore the floating-point registers, which is
629 important if in a mixed MIPS16/non-MIPS16 environment. */
630
631 #ifdef IN_LIBGCC2
632 #if __mips_hard_float
633 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
634 #endif
635 #endif /* IN_LIBGCC2 */
636
637 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
638
639 #ifndef MULTILIB_ENDIAN_DEFAULT
640 #if TARGET_ENDIAN_DEFAULT == 0
641 #define MULTILIB_ENDIAN_DEFAULT "EL"
642 #else
643 #define MULTILIB_ENDIAN_DEFAULT "EB"
644 #endif
645 #endif
646
647 #ifndef MULTILIB_ISA_DEFAULT
648 #if MIPS_ISA_DEFAULT == 1
649 #define MULTILIB_ISA_DEFAULT "mips1"
650 #elif MIPS_ISA_DEFAULT == 2
651 #define MULTILIB_ISA_DEFAULT "mips2"
652 #elif MIPS_ISA_DEFAULT == 3
653 #define MULTILIB_ISA_DEFAULT "mips3"
654 #elif MIPS_ISA_DEFAULT == 4
655 #define MULTILIB_ISA_DEFAULT "mips4"
656 #elif MIPS_ISA_DEFAULT == 32
657 #define MULTILIB_ISA_DEFAULT "mips32"
658 #elif MIPS_ISA_DEFAULT == 33
659 #define MULTILIB_ISA_DEFAULT "mips32r2"
660 #elif MIPS_ISA_DEFAULT == 64
661 #define MULTILIB_ISA_DEFAULT "mips64"
662 #elif MIPS_ISA_DEFAULT == 65
663 #define MULTILIB_ISA_DEFAULT "mips64r2"
664 #else
665 #define MULTILIB_ISA_DEFAULT "mips1"
666 #endif
667 #endif
668
669 #ifndef MIPS_ABI_DEFAULT
670 #define MIPS_ABI_DEFAULT ABI_32
671 #endif
672
673 /* Use the most portable ABI flag for the ASM specs. */
674
675 #if MIPS_ABI_DEFAULT == ABI_32
676 #define MULTILIB_ABI_DEFAULT "mabi=32"
677 #elif MIPS_ABI_DEFAULT == ABI_O64
678 #define MULTILIB_ABI_DEFAULT "mabi=o64"
679 #elif MIPS_ABI_DEFAULT == ABI_N32
680 #define MULTILIB_ABI_DEFAULT "mabi=n32"
681 #elif MIPS_ABI_DEFAULT == ABI_64
682 #define MULTILIB_ABI_DEFAULT "mabi=64"
683 #elif MIPS_ABI_DEFAULT == ABI_EABI
684 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
685 #endif
686
687 #ifndef MULTILIB_DEFAULTS
688 #define MULTILIB_DEFAULTS \
689 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
690 #endif
691
692 /* We must pass -EL to the linker by default for little endian embedded
693 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
694 linker will default to using big-endian output files. The OUTPUT_FORMAT
695 line must be in the linker script, otherwise -EB/-EL will not work. */
696
697 #ifndef ENDIAN_SPEC
698 #if TARGET_ENDIAN_DEFAULT == 0
699 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
700 #else
701 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
702 #endif
703 #endif
704
705 /* A spec condition that matches all non-mips16 -mips arguments. */
706
707 #define MIPS_ISA_LEVEL_OPTION_SPEC \
708 "mips1|mips2|mips3|mips4|mips32*|mips64*"
709
710 /* A spec condition that matches all non-mips16 architecture arguments. */
711
712 #define MIPS_ARCH_OPTION_SPEC \
713 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
714
715 /* A spec that infers a -mips argument from an -march argument,
716 or injects the default if no architecture is specified. */
717
718 #define MIPS_ISA_LEVEL_SPEC \
719 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
720 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
721 %{march=mips2|march=r6000:-mips2} \
722 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
723 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
724 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
725 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
726 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
727 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
728 %{march=mips32r3: -mips32r3} \
729 %{march=mips32r5|march=p5600: -mips32r5} \
730 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
731 |march=xlr: -mips64} \
732 %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
733 %{march=mips64r3: -mips64r3} \
734 %{march=mips64r5: -mips64r5} \
735 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
736
737 /* A spec that infers a -mhard-float or -msoft-float setting from an
738 -march argument. Note that soft-float and hard-float code are not
739 link-compatible. */
740
741 #define MIPS_ARCH_FLOAT_SPEC \
742 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
743 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
744 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
745 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
746 march=*: -mhard-float}"
747
748 /* A spec condition that matches 32-bit options. It only works if
749 MIPS_ISA_LEVEL_SPEC has been applied. */
750
751 #define MIPS_32BIT_OPTION_SPEC \
752 "mips1|mips2|mips32*|mgp32"
753
754 /* Infer a -msynci setting from a -mips argument, on the assumption that
755 -msynci is desired where possible. */
756 #define MIPS_ISA_SYNCI_SPEC \
757 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips64r2|mips64r3 \
758 |mips64r5:-msynci;:-mno-synci}}"
759
760 #if (MIPS_ABI_DEFAULT == ABI_O64 \
761 || MIPS_ABI_DEFAULT == ABI_N32 \
762 || MIPS_ABI_DEFAULT == ABI_64)
763 #define OPT_ARCH64 "mabi=32|mgp32:;"
764 #define OPT_ARCH32 "mabi=32|mgp32"
765 #else
766 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
767 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
768 #endif
769
770 /* Support for a compile-time default CPU, et cetera. The rules are:
771 --with-arch is ignored if -march is specified or a -mips is specified
772 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
773 --with-tune is ignored if -mtune is specified; likewise
774 --with-tune-32 and --with-tune-64.
775 --with-abi is ignored if -mabi is specified.
776 --with-float is ignored if -mhard-float or -msoft-float are
777 specified.
778 --with-nan is ignored if -mnan is specified.
779 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
780 specified. */
781 #define OPTION_DEFAULT_SPECS \
782 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
783 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
784 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
785 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
786 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
787 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
788 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
789 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
790 {"fpu", "%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}" }, \
791 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
792 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
793 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
794 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
795 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
796
797 /* A spec that infers the -mdsp setting from an -march argument. */
798 #define BASE_DRIVER_SELF_SPECS \
799 "%{!mno-dsp: \
800 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
801 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
802
803 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
804
805 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
806 && ISA_HAS_COND_TRAP)
807
808 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
809
810 /* True if the ABI can only work with 64-bit integer registers. We
811 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
812 otherwise floating-point registers must also be 64-bit. */
813 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
814
815 /* Likewise for 32-bit regs. */
816 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
817
818 /* True if the file format uses 64-bit symbols. At present, this is
819 only true for n64, which uses 64-bit ELF. */
820 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
821
822 /* True if symbols are 64 bits wide. This is usually determined by
823 the ABI's file format, but it can be overridden by -msym32. Note that
824 overriding the size with -msym32 changes the ABI of relocatable objects,
825 although it doesn't change the ABI of a fully-linked object. */
826 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
827 && Pmode == DImode \
828 && !TARGET_SYM32)
829
830 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
831 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
832 || ISA_MIPS4 \
833 || ISA_MIPS64 \
834 || ISA_MIPS64R2 \
835 || ISA_MIPS64R3 \
836 || ISA_MIPS64R5)
837
838 /* ISA has branch likely instructions (e.g. mips2). */
839 /* Disable branchlikely for tx39 until compare rewrite. They haven't
840 been generated up to this point. */
841 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
842
843 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
844 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
845 || TARGET_MIPS5400 \
846 || TARGET_MIPS5500 \
847 || TARGET_MIPS5900 \
848 || TARGET_MIPS7000 \
849 || TARGET_MIPS9000 \
850 || TARGET_MAD \
851 || mips_isa_rev >= 1) \
852 && !TARGET_MIPS16)
853
854 /* ISA has a three-operand multiplication instruction. */
855 #define ISA_HAS_DMUL3 (TARGET_64BIT \
856 && TARGET_OCTEON \
857 && !TARGET_MIPS16)
858
859 /* ISA supports instructions DMULT and DMULTU. */
860 #define ISA_HAS_DMULT (TARGET_64BIT && !TARGET_MIPS5900)
861
862 /* ISA supports instructions MULT and MULTU.
863 This is always true, but the macro is needed for ISA_HAS_<D>MULT
864 in mips.md. */
865 #define ISA_HAS_MULT (1)
866
867 /* ISA supports instructions DDIV and DDIVU. */
868 #define ISA_HAS_DDIV (TARGET_64BIT && !TARGET_MIPS5900)
869
870 /* ISA supports instructions DIV and DIVU.
871 This is always true, but the macro is needed for ISA_HAS_<D>DIV
872 in mips.md. */
873 #define ISA_HAS_DIV (1)
874
875 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
876 || TARGET_LOONGSON_3A) \
877 && !TARGET_MIPS16)
878
879 /* ISA has the floating-point conditional move instructions introduced
880 in mips4. */
881 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
882 || mips_isa_rev >= 1) \
883 && !TARGET_MIPS5500 \
884 && !TARGET_MIPS16)
885
886 /* ISA has the integer conditional move instructions introduced in mips4 and
887 ST Loongson 2E/2F. */
888 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
889 || TARGET_MIPS5900 \
890 || TARGET_LOONGSON_2EF)
891
892 /* ISA has LDC1 and SDC1. */
893 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
894 && !TARGET_MIPS5900 \
895 && !TARGET_MIPS16)
896
897 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
898 branch on CC, and move (both FP and non-FP) on CC. */
899 #define ISA_HAS_8CC (ISA_MIPS4 || mips_isa_rev >= 1)
900
901 /* This is a catch all for other mips4 instructions: indexed load, the
902 FP madd and msub instructions, and the FP recip and recip sqrt
903 instructions. Note that this macro should only be used by other
904 ISA_HAS_* macros. */
905 #define ISA_HAS_FP4 ((ISA_MIPS4 \
906 || ISA_MIPS64 \
907 || mips_isa_rev >= 2) \
908 && !TARGET_MIPS16)
909
910 /* ISA has floating-point indexed load and store instructions
911 (LWXC1, LDXC1, SWXC1 and SDXC1). */
912 #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
913
914 /* ISA has paired-single instructions. */
915 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS64 || mips_isa_rev >= 2)
916
917 /* ISA has conditional trap instructions. */
918 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
919 && !TARGET_MIPS16)
920
921 /* ISA has integer multiply-accumulate instructions, madd and msub. */
922 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1)
923
924 /* Integer multiply-accumulate instructions should be generated. */
925 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
926
927 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
928 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
929
930 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
931 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
932
933 /* ISA has floating-point nmadd and nmsub instructions
934 'd = -((a * b) [+-] c)'. */
935 #define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4
936
937 /* ISA has floating-point nmadd and nmsub instructions
938 'c = -((a * b) [+-] c)'. */
939 #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF
940
941 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
942 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
943 doubles are stored in pairs of FPRs, so for safety's sake, we apply
944 this restriction to the MIPS IV ISA too. */
945 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
946 (((ISA_HAS_FP4 \
947 && ((MODE) == SFmode \
948 || ((TARGET_FLOAT64 \
949 || mips_isa_rev >= 2) \
950 && (MODE) == DFmode))) \
951 || (TARGET_SB1 \
952 && (MODE) == V2SFmode)) \
953 && !TARGET_MIPS16)
954
955 /* ISA has count leading zeroes/ones instruction (not implemented). */
956 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
957
958 /* ISA has three operand multiply instructions that put
959 the high part in an accumulator: mulhi or mulhiu. */
960 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
961 || TARGET_MIPS5500 \
962 || TARGET_SR71K) \
963 && !TARGET_MIPS16)
964
965 /* ISA has three operand multiply instructions that negate the
966 result and put the result in an accumulator. */
967 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
968 || TARGET_MIPS5500 \
969 || TARGET_SR71K) \
970 && !TARGET_MIPS16)
971
972 /* ISA has three operand multiply instructions that subtract the
973 result from a 4th operand and put the result in an accumulator. */
974 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
975 || TARGET_MIPS5500 \
976 || TARGET_SR71K) \
977 && !TARGET_MIPS16)
978
979 /* ISA has three operand multiply instructions that add the result
980 to a 4th operand and put the result in an accumulator. */
981 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
982 || TARGET_MIPS4130 \
983 || TARGET_MIPS5400 \
984 || TARGET_MIPS5500 \
985 || TARGET_SR71K) \
986 && !TARGET_MIPS16)
987
988 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
989 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
990 || TARGET_MIPS4130) \
991 && !TARGET_MIPS16)
992
993 /* ISA has the "ror" (rotate right) instructions. */
994 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
995 || TARGET_MIPS5400 \
996 || TARGET_MIPS5500 \
997 || TARGET_SR71K \
998 || TARGET_SMARTMIPS) \
999 && !TARGET_MIPS16)
1000
1001 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1002 64-bit targets also provide DSBH and DSHD. */
1003 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1004
1005 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1006 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1007 || TARGET_LOONGSON_2EF \
1008 || TARGET_MIPS5900 \
1009 || mips_isa_rev >= 1) \
1010 && !TARGET_MIPS16)
1011
1012 /* ISA has data indexed prefetch instructions. This controls use of
1013 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1014 (prefx is a cop1x instruction, so can only be used if FP is
1015 enabled.) */
1016 #define ISA_HAS_PREFETCHX ISA_HAS_FP4
1017
1018 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1019 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1020 also requires TARGET_DOUBLE_FLOAT. */
1021 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1022
1023 /* ISA includes the MIPS32r2 seb and seh instructions. */
1024 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1025
1026 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1027 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1028
1029 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1030 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && mips_isa_rev >= 2)
1031
1032 /* ISA has lwxs instruction (load w/scaled index address. */
1033 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1034 && !TARGET_MIPS16)
1035
1036 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1037 #define ISA_HAS_LBX (TARGET_OCTEON2)
1038 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1039 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1040 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1041 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1042 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1043 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1044 && TARGET_64BIT)
1045
1046 /* The DSP ASE is available. */
1047 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1048
1049 /* Revision 2 of the DSP ASE is available. */
1050 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1051
1052 /* True if the result of a load is not available to the next instruction.
1053 A nop will then be needed between instructions like "lw $4,..."
1054 and "addiu $4,$4,1". */
1055 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1056 && !TARGET_MIPS3900 \
1057 && !TARGET_MIPS5900 \
1058 && !TARGET_MIPS16 \
1059 && !TARGET_MICROMIPS)
1060
1061 /* Likewise mtc1 and mfc1. */
1062 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1063 && !TARGET_MIPS5900 \
1064 && !TARGET_LOONGSON_2EF)
1065
1066 /* Likewise floating-point comparisons. */
1067 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1068 && !TARGET_MIPS5900 \
1069 && !TARGET_LOONGSON_2EF)
1070
1071 /* True if mflo and mfhi can be immediately followed by instructions
1072 which write to the HI and LO registers.
1073
1074 According to MIPS specifications, MIPS ISAs I, II, and III need
1075 (at least) two instructions between the reads of HI/LO and
1076 instructions which write them, and later ISAs do not. Contradicting
1077 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1078 the UM for the NEC Vr5000) document needing the instructions between
1079 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1080 MIPS64 and later ISAs to have the interlocks, plus any specific
1081 earlier-ISA CPUs for which CPU documentation declares that the
1082 instructions are really interlocked. */
1083 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1084 || TARGET_MIPS5500 \
1085 || TARGET_MIPS5900 \
1086 || TARGET_LOONGSON_2EF)
1087
1088 /* ISA includes synci, jr.hb and jalr.hb. */
1089 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1090
1091 /* ISA includes sync. */
1092 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1093 #define GENERATE_SYNC \
1094 (target_flags_explicit & MASK_LLSC \
1095 ? TARGET_LLSC && !TARGET_MIPS16 \
1096 : ISA_HAS_SYNC)
1097
1098 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1099 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1100 instructions. */
1101 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1102 #define GENERATE_LL_SC \
1103 (target_flags_explicit & MASK_LLSC \
1104 ? TARGET_LLSC && !TARGET_MIPS16 \
1105 : ISA_HAS_LL_SC)
1106
1107 #define ISA_HAS_SWAP (TARGET_XLP)
1108 #define ISA_HAS_LDADD (TARGET_XLP)
1109
1110 /* ISA includes the baddu instruction. */
1111 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1112
1113 /* ISA includes the bbit* instructions. */
1114 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1115
1116 /* ISA includes the cins instruction. */
1117 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1118
1119 /* ISA includes the exts instruction. */
1120 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1121
1122 /* ISA includes the seq and sne instructions. */
1123 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1124
1125 /* ISA includes the pop instruction. */
1126 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1127
1128 /* The CACHE instruction is available in non-MIPS16 code. */
1129 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1130
1131 /* The CACHE instruction is available. */
1132 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1133 \f
1134 /* Tell collect what flags to pass to nm. */
1135 #ifndef NM_FLAGS
1136 #define NM_FLAGS "-Bn"
1137 #endif
1138
1139 \f
1140 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1141 the assembler. It may be overridden by subtargets.
1142
1143 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1144 COFF debugging info. */
1145
1146 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1147 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1148 %{g} %{g0} %{g1} %{g2} %{g3} \
1149 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1150 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1151 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1152 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1153 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1154 #endif
1155
1156 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1157 overridden by subtargets. */
1158
1159 #ifndef SUBTARGET_ASM_SPEC
1160 #define SUBTARGET_ASM_SPEC ""
1161 #endif
1162
1163 #undef ASM_SPEC
1164 #define ASM_SPEC "\
1165 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1166 %{mips32*} %{mips64*} \
1167 %{mips16} %{mno-mips16:-no-mips16} \
1168 %{mmicromips} %{mno-micromips} \
1169 %{mips3d} %{mno-mips3d:-no-mips3d} \
1170 %{mdmx} %{mno-mdmx:-no-mdmx} \
1171 %{mdsp} %{mno-dsp} \
1172 %{mdspr2} %{mno-dspr2} \
1173 %{mmcu} %{mno-mcu} \
1174 %{meva} %{mno-eva} \
1175 %{mvirt} %{mno-virt} \
1176 %{mxpa} %{mno-xpa} \
1177 %{msmartmips} %{mno-smartmips} \
1178 %{mmt} %{mno-mt} \
1179 %{mfix-rm7000} %{mno-fix-rm7000} \
1180 %{mfix-vr4120} %{mfix-vr4130} \
1181 %{mfix-24k} \
1182 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1183 %(subtarget_asm_debugging_spec) \
1184 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1185 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1186 %{mfp32} %{mfp64} %{mnan=*} \
1187 %{mshared} %{mno-shared} \
1188 %{msym32} %{mno-sym32} \
1189 %{mtune=*} \
1190 %(subtarget_asm_spec)"
1191
1192 /* Extra switches sometimes passed to the linker. */
1193
1194 #ifndef LINK_SPEC
1195 #define LINK_SPEC "\
1196 %(endian_spec) \
1197 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1198 %{shared}"
1199 #endif /* LINK_SPEC defined */
1200
1201
1202 /* Specs for the compiler proper */
1203
1204 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1205 overridden by subtargets. */
1206 #ifndef SUBTARGET_CC1_SPEC
1207 #define SUBTARGET_CC1_SPEC ""
1208 #endif
1209
1210 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1211
1212 #undef CC1_SPEC
1213 #define CC1_SPEC "\
1214 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1215 %(subtarget_cc1_spec)"
1216
1217 /* Preprocessor specs. */
1218
1219 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1220 overridden by subtargets. */
1221 #ifndef SUBTARGET_CPP_SPEC
1222 #define SUBTARGET_CPP_SPEC ""
1223 #endif
1224
1225 #define CPP_SPEC "%(subtarget_cpp_spec)"
1226
1227 /* This macro defines names of additional specifications to put in the specs
1228 that can be used in various specifications like CC1_SPEC. Its definition
1229 is an initializer with a subgrouping for each command option.
1230
1231 Each subgrouping contains a string constant, that defines the
1232 specification name, and a string constant that used by the GCC driver
1233 program.
1234
1235 Do not define this macro if it does not need to do anything. */
1236
1237 #define EXTRA_SPECS \
1238 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1239 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1240 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1241 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1242 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1243 { "endian_spec", ENDIAN_SPEC }, \
1244 SUBTARGET_EXTRA_SPECS
1245
1246 #ifndef SUBTARGET_EXTRA_SPECS
1247 #define SUBTARGET_EXTRA_SPECS
1248 #endif
1249 \f
1250 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1251 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1252
1253 #ifndef PREFERRED_DEBUGGING_TYPE
1254 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1255 #endif
1256
1257 /* The size of DWARF addresses should be the same as the size of symbols
1258 in the target file format. They shouldn't depend on things like -msym32,
1259 because many DWARF consumers do not allow the mixture of address sizes
1260 that one would then get from linking -msym32 code with -msym64 code.
1261
1262 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1263 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1264 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1265
1266 /* By default, turn on GDB extensions. */
1267 #define DEFAULT_GDB_EXTENSIONS 1
1268
1269 /* Local compiler-generated symbols must have a prefix that the assembler
1270 understands. By default, this is $, although some targets (e.g.,
1271 NetBSD-ELF) need to override this. */
1272
1273 #ifndef LOCAL_LABEL_PREFIX
1274 #define LOCAL_LABEL_PREFIX "$"
1275 #endif
1276
1277 /* By default on the mips, external symbols do not have an underscore
1278 prepended, but some targets (e.g., NetBSD) require this. */
1279
1280 #ifndef USER_LABEL_PREFIX
1281 #define USER_LABEL_PREFIX ""
1282 #endif
1283
1284 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1285 since the length can run past this up to a continuation point. */
1286 #undef DBX_CONTIN_LENGTH
1287 #define DBX_CONTIN_LENGTH 1500
1288
1289 /* How to renumber registers for dbx and gdb. */
1290 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1291
1292 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1293 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1294
1295 /* The DWARF 2 CFA column which tracks the return address. */
1296 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1297
1298 /* Before the prologue, RA lives in r31. */
1299 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1300
1301 /* Describe how we implement __builtin_eh_return. */
1302 #define EH_RETURN_DATA_REGNO(N) \
1303 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1304
1305 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1306
1307 #define EH_USES(N) mips_eh_uses (N)
1308
1309 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1310 The default for this in 64-bit mode is 8, which causes problems with
1311 SFmode register saves. */
1312 #define DWARF_CIE_DATA_ALIGNMENT -4
1313
1314 /* Correct the offset of automatic variables and arguments. Note that
1315 the MIPS debug format wants all automatic variables and arguments
1316 to be in terms of the virtual frame pointer (stack pointer before
1317 any adjustment in the function), while the MIPS 3.0 linker wants
1318 the frame pointer to be the stack pointer after the initial
1319 adjustment. */
1320
1321 #define DEBUGGER_AUTO_OFFSET(X) \
1322 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1323 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1324 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1325 \f
1326 /* Target machine storage layout */
1327
1328 #define BITS_BIG_ENDIAN 0
1329 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1330 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1331
1332 #define MAX_BITS_PER_WORD 64
1333
1334 /* Width of a word, in units (bytes). */
1335 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1336 #ifndef IN_LIBGCC2
1337 #define MIN_UNITS_PER_WORD 4
1338 #endif
1339
1340 /* For MIPS, width of a floating point register. */
1341 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1342
1343 /* The number of consecutive floating-point registers needed to store the
1344 largest format supported by the FPU. */
1345 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1346
1347 /* The number of consecutive floating-point registers needed to store the
1348 smallest format supported by the FPU. */
1349 #define MIN_FPRS_PER_FMT \
1350 (mips_isa_rev >= 1 ? 1 : MAX_FPRS_PER_FMT)
1351
1352 /* The largest size of value that can be held in floating-point
1353 registers and moved with a single instruction. */
1354 #define UNITS_PER_HWFPVALUE \
1355 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1356
1357 /* The largest size of value that can be held in floating-point
1358 registers. */
1359 #define UNITS_PER_FPVALUE \
1360 (TARGET_SOFT_FLOAT_ABI ? 0 \
1361 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1362 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1363
1364 /* The number of bytes in a double. */
1365 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1366
1367 /* Set the sizes of the core types. */
1368 #define SHORT_TYPE_SIZE 16
1369 #define INT_TYPE_SIZE 32
1370 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1371 #define LONG_LONG_TYPE_SIZE 64
1372
1373 #define FLOAT_TYPE_SIZE 32
1374 #define DOUBLE_TYPE_SIZE 64
1375 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1376
1377 /* Define the sizes of fixed-point types. */
1378 #define SHORT_FRACT_TYPE_SIZE 8
1379 #define FRACT_TYPE_SIZE 16
1380 #define LONG_FRACT_TYPE_SIZE 32
1381 #define LONG_LONG_FRACT_TYPE_SIZE 64
1382
1383 #define SHORT_ACCUM_TYPE_SIZE 16
1384 #define ACCUM_TYPE_SIZE 32
1385 #define LONG_ACCUM_TYPE_SIZE 64
1386 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1387 doesn't support 128-bit integers for MIPS32 currently. */
1388 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1389
1390 /* long double is not a fixed mode, but the idea is that, if we
1391 support long double, we also want a 128-bit integer type. */
1392 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1393
1394 #ifdef IN_LIBGCC2
1395 #if ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1396 || (defined _ABI64 && _MIPS_SIM == _ABI64))
1397 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1398 # else
1399 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1400 # endif
1401 #endif
1402
1403 /* Width in bits of a pointer. */
1404 #ifndef POINTER_SIZE
1405 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1406 #endif
1407
1408 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1409 #define PARM_BOUNDARY BITS_PER_WORD
1410
1411 /* Allocation boundary (in *bits*) for the code of a function. */
1412 #define FUNCTION_BOUNDARY 32
1413
1414 /* Alignment of field after `int : 0' in a structure. */
1415 #define EMPTY_FIELD_BOUNDARY 32
1416
1417 /* Every structure's size must be a multiple of this. */
1418 /* 8 is observed right on a DECstation and on riscos 4.02. */
1419 #define STRUCTURE_SIZE_BOUNDARY 8
1420
1421 /* There is no point aligning anything to a rounder boundary than this. */
1422 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1423
1424 /* All accesses must be aligned. */
1425 #define STRICT_ALIGNMENT 1
1426
1427 /* Define this if you wish to imitate the way many other C compilers
1428 handle alignment of bitfields and the structures that contain
1429 them.
1430
1431 The behavior is that the type written for a bit-field (`int',
1432 `short', or other integer type) imposes an alignment for the
1433 entire structure, as if the structure really did contain an
1434 ordinary field of that type. In addition, the bit-field is placed
1435 within the structure so that it would fit within such a field,
1436 not crossing a boundary for it.
1437
1438 Thus, on most machines, a bit-field whose type is written as `int'
1439 would not cross a four-byte boundary, and would force four-byte
1440 alignment for the whole structure. (The alignment used may not
1441 be four bytes; it is controlled by the other alignment
1442 parameters.)
1443
1444 If the macro is defined, its definition should be a C expression;
1445 a nonzero value for the expression enables this behavior. */
1446
1447 #define PCC_BITFIELD_TYPE_MATTERS 1
1448
1449 /* If defined, a C expression to compute the alignment given to a
1450 constant that is being placed in memory. CONSTANT is the constant
1451 and ALIGN is the alignment that the object would ordinarily have.
1452 The value of this macro is used instead of that alignment to align
1453 the object.
1454
1455 If this macro is not defined, then ALIGN is used.
1456
1457 The typical use of this macro is to increase alignment for string
1458 constants to be word aligned so that `strcpy' calls that copy
1459 constants can be done inline. */
1460
1461 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1462 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1463 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1464
1465 /* If defined, a C expression to compute the alignment for a static
1466 variable. TYPE is the data type, and ALIGN is the alignment that
1467 the object would ordinarily have. The value of this macro is used
1468 instead of that alignment to align the object.
1469
1470 If this macro is not defined, then ALIGN is used.
1471
1472 One use of this macro is to increase alignment of medium-size
1473 data to make it all fit in fewer cache lines. Another is to
1474 cause character arrays to be word-aligned so that `strcpy' calls
1475 that copy constants to character arrays can be done inline. */
1476
1477 #undef DATA_ALIGNMENT
1478 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1479 ((((ALIGN) < BITS_PER_WORD) \
1480 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1481 || TREE_CODE (TYPE) == UNION_TYPE \
1482 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1483
1484 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1485 character arrays to be word-aligned so that `strcpy' calls that copy
1486 constants to character arrays can be done inline, and 'strcmp' can be
1487 optimised to use word loads. */
1488 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1489 DATA_ALIGNMENT (TYPE, ALIGN)
1490
1491 #define PAD_VARARGS_DOWN \
1492 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1493
1494 /* Define if operations between registers always perform the operation
1495 on the full register even if a narrower mode is specified. */
1496 #define WORD_REGISTER_OPERATIONS
1497
1498 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1499 moves. All other references are zero extended. */
1500 #define LOAD_EXTEND_OP(MODE) \
1501 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1502 ? SIGN_EXTEND : ZERO_EXTEND)
1503
1504 /* Define this macro if it is advisable to hold scalars in registers
1505 in a wider mode than that declared by the program. In such cases,
1506 the value is constrained to be within the bounds of the declared
1507 type, but kept valid in the wider mode. The signedness of the
1508 extension may differ from that of the type. */
1509
1510 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1511 if (GET_MODE_CLASS (MODE) == MODE_INT \
1512 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1513 { \
1514 if ((MODE) == SImode) \
1515 (UNSIGNEDP) = 0; \
1516 (MODE) = Pmode; \
1517 }
1518
1519 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1520 Extensions of pointers to word_mode must be signed. */
1521 #define POINTERS_EXTEND_UNSIGNED false
1522
1523 /* Define if loading short immediate values into registers sign extends. */
1524 #define SHORT_IMMEDIATES_SIGN_EXTEND
1525
1526 /* The [d]clz instructions have the natural values at 0. */
1527
1528 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1529 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1530 \f
1531 /* Standard register usage. */
1532
1533 /* Number of hardware registers. We have:
1534
1535 - 32 integer registers
1536 - 32 floating point registers
1537 - 8 condition code registers
1538 - 2 accumulator registers (hi and lo)
1539 - 32 registers each for coprocessors 0, 2 and 3
1540 - 4 fake registers:
1541 - ARG_POINTER_REGNUM
1542 - FRAME_POINTER_REGNUM
1543 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1544 - CPRESTORE_SLOT_REGNUM
1545 - 2 dummy entries that were used at various times in the past.
1546 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1547 - 6 DSP control registers */
1548
1549 #define FIRST_PSEUDO_REGISTER 188
1550
1551 /* By default, fix the kernel registers ($26 and $27), the global
1552 pointer ($28) and the stack pointer ($29). This can change
1553 depending on the command-line options.
1554
1555 Regarding coprocessor registers: without evidence to the contrary,
1556 it's best to assume that each coprocessor register has a unique
1557 use. This can be overridden, in, e.g., mips_option_override or
1558 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1559 inappropriate for a particular target. */
1560
1561 #define FIXED_REGISTERS \
1562 { \
1563 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1564 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1565 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1566 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1567 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1568 /* COP0 registers */ \
1569 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1570 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1571 /* COP2 registers */ \
1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1573 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1574 /* COP3 registers */ \
1575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1576 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1577 /* 6 DSP accumulator registers & 6 control registers */ \
1578 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1579 }
1580
1581
1582 /* Set up this array for o32 by default.
1583
1584 Note that we don't mark $31 as a call-clobbered register. The idea is
1585 that it's really the call instructions themselves which clobber $31.
1586 We don't care what the called function does with it afterwards.
1587
1588 This approach makes it easier to implement sibcalls. Unlike normal
1589 calls, sibcalls don't clobber $31, so the register reaches the
1590 called function in tact. EPILOGUE_USES says that $31 is useful
1591 to the called function. */
1592
1593 #define CALL_USED_REGISTERS \
1594 { \
1595 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1596 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1597 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1598 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1599 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1600 /* COP0 registers */ \
1601 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1602 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1603 /* COP2 registers */ \
1604 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1605 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1606 /* COP3 registers */ \
1607 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1608 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1609 /* 6 DSP accumulator registers & 6 control registers */ \
1610 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1611 }
1612
1613
1614 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1615
1616 #define CALL_REALLY_USED_REGISTERS \
1617 { /* General registers. */ \
1618 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1619 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1620 /* Floating-point registers. */ \
1621 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1622 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1623 /* Others. */ \
1624 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1625 /* COP0 registers */ \
1626 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1627 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1628 /* COP2 registers */ \
1629 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1630 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1631 /* COP3 registers */ \
1632 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1633 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1634 /* 6 DSP accumulator registers & 6 control registers */ \
1635 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1636 }
1637
1638 /* Internal macros to classify a register number as to whether it's a
1639 general purpose register, a floating point register, a
1640 multiply/divide register, or a status register. */
1641
1642 #define GP_REG_FIRST 0
1643 #define GP_REG_LAST 31
1644 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1645 #define GP_DBX_FIRST 0
1646 #define K0_REG_NUM (GP_REG_FIRST + 26)
1647 #define K1_REG_NUM (GP_REG_FIRST + 27)
1648 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1649
1650 #define FP_REG_FIRST 32
1651 #define FP_REG_LAST 63
1652 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1653 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1654
1655 #define MD_REG_FIRST 64
1656 #define MD_REG_LAST 65
1657 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1658 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1659
1660 /* The DWARF 2 CFA column which tracks the return address from a
1661 signal handler context. This means that to maintain backwards
1662 compatibility, no hard register can be assigned this column if it
1663 would need to be handled by the DWARF unwinder. */
1664 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1665
1666 #define ST_REG_FIRST 67
1667 #define ST_REG_LAST 74
1668 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1669
1670
1671 /* FIXME: renumber. */
1672 #define COP0_REG_FIRST 80
1673 #define COP0_REG_LAST 111
1674 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1675
1676 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1677 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1678 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1679
1680 #define COP2_REG_FIRST 112
1681 #define COP2_REG_LAST 143
1682 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1683
1684 #define COP3_REG_FIRST 144
1685 #define COP3_REG_LAST 175
1686 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1687
1688 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1689 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1690 #define ALL_COP_REG_LAST COP3_REG_LAST
1691 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1692
1693 #define DSP_ACC_REG_FIRST 176
1694 #define DSP_ACC_REG_LAST 181
1695 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1696
1697 #define AT_REGNUM (GP_REG_FIRST + 1)
1698 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1699 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1700
1701 /* A few bitfield locations for the coprocessor registers. */
1702 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1703 the cause register for the EIC interrupt mode. */
1704 #define CAUSE_IPL 10
1705 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1706 #define SR_IPL 10
1707 /* Exception Level is at bit 1 of the status register. */
1708 #define SR_EXL 1
1709 /* Interrupt Enable is at bit 0 of the status register. */
1710 #define SR_IE 0
1711
1712 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1713 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1714 should be used instead. */
1715 #define FPSW_REGNUM ST_REG_FIRST
1716
1717 #define GP_REG_P(REGNO) \
1718 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1719 #define M16_REG_P(REGNO) \
1720 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1721 #define M16STORE_REG_P(REGNO) \
1722 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1723 #define FP_REG_P(REGNO) \
1724 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1725 #define MD_REG_P(REGNO) \
1726 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1727 #define ST_REG_P(REGNO) \
1728 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1729 #define COP0_REG_P(REGNO) \
1730 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1731 #define COP2_REG_P(REGNO) \
1732 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1733 #define COP3_REG_P(REGNO) \
1734 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1735 #define ALL_COP_REG_P(REGNO) \
1736 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1737 /* Test if REGNO is one of the 6 new DSP accumulators. */
1738 #define DSP_ACC_REG_P(REGNO) \
1739 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1740 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1741 #define ACC_REG_P(REGNO) \
1742 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1743
1744 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1745
1746 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1747 to initialize the mips16 gp pseudo register. */
1748 #define CONST_GP_P(X) \
1749 (GET_CODE (X) == CONST \
1750 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1751 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1752
1753 /* Return coprocessor number from register number. */
1754
1755 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1756 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1757 : COP3_REG_P (REGNO) ? '3' : '?')
1758
1759
1760 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1761
1762 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1763 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1764
1765 #define MODES_TIEABLE_P mips_modes_tieable_p
1766
1767 /* Register to use for pushing function arguments. */
1768 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1769
1770 /* These two registers don't really exist: they get eliminated to either
1771 the stack or hard frame pointer. */
1772 #define ARG_POINTER_REGNUM 77
1773 #define FRAME_POINTER_REGNUM 78
1774
1775 /* $30 is not available on the mips16, so we use $17 as the frame
1776 pointer. */
1777 #define HARD_FRAME_POINTER_REGNUM \
1778 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1779
1780 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1781 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1782
1783 /* Register in which static-chain is passed to a function. */
1784 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1785
1786 /* Registers used as temporaries in prologue/epilogue code:
1787
1788 - If a MIPS16 PIC function needs access to _gp, it first loads
1789 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1790
1791 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1792 register. The register must not conflict with MIPS16_PIC_TEMP.
1793
1794 - If we aren't generating MIPS16 code, the prologue can also use
1795 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1796
1797 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1798 register.
1799
1800 If we're generating MIPS16 code, these registers must come from the
1801 core set of 8. The prologue registers mustn't conflict with any
1802 incoming arguments, the static chain pointer, or the frame pointer.
1803 The epilogue temporary mustn't conflict with the return registers,
1804 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1805 or the EH data registers.
1806
1807 If we're generating interrupt handlers, we use K0 as a temporary register
1808 in prologue/epilogue code. */
1809
1810 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1811 #define MIPS_PROLOGUE_TEMP_REGNUM \
1812 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1813 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1814 (TARGET_MIPS16 \
1815 ? (gcc_unreachable (), INVALID_REGNUM) \
1816 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1817 #define MIPS_EPILOGUE_TEMP_REGNUM \
1818 (cfun->machine->interrupt_handler_p \
1819 ? K0_REG_NUM \
1820 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1821
1822 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1823 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1824 #define MIPS_PROLOGUE_TEMP2(MODE) \
1825 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1826 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1827
1828 /* Define this macro if it is as good or better to call a constant
1829 function address than to call an address kept in a register. */
1830 #define NO_FUNCTION_CSE 1
1831
1832 /* The ABI-defined global pointer. Sometimes we use a different
1833 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1834 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1835
1836 /* We normally use $28 as the global pointer. However, when generating
1837 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1838 register instead. They can then avoid saving and restoring $28
1839 and perhaps avoid using a frame at all.
1840
1841 When a leaf function uses something other than $28, mips_expand_prologue
1842 will modify pic_offset_table_rtx in place. Take the register number
1843 from there after reload. */
1844 #define PIC_OFFSET_TABLE_REGNUM \
1845 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1846 \f
1847 /* Define the classes of registers for register constraints in the
1848 machine description. Also define ranges of constants.
1849
1850 One of the classes must always be named ALL_REGS and include all hard regs.
1851 If there is more than one class, another class must be named NO_REGS
1852 and contain no registers.
1853
1854 The name GENERAL_REGS must be the name of a class (or an alias for
1855 another name such as ALL_REGS). This is the class of registers
1856 that is allowed by "g" or "r" in a register constraint.
1857 Also, registers outside this class are allocated only when
1858 instructions express preferences for them.
1859
1860 The classes must be numbered in nondecreasing order; that is,
1861 a larger-numbered class must never be contained completely
1862 in a smaller-numbered class.
1863
1864 For any two classes, it is very desirable that there be another
1865 class that represents their union. */
1866
1867 enum reg_class
1868 {
1869 NO_REGS, /* no registers in set */
1870 M16_STORE_REGS, /* microMIPS store registers */
1871 M16_REGS, /* mips16 directly accessible registers */
1872 M16_SP_REGS, /* mips16 + $sp */
1873 T_REG, /* mips16 T register ($24) */
1874 M16_T_REGS, /* mips16 registers plus T register */
1875 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1876 V1_REG, /* Register $v1 ($3) used for TLS access. */
1877 SPILL_REGS, /* All but $sp and call preserved regs are in here */
1878 LEA_REGS, /* Every GPR except $25 */
1879 GR_REGS, /* integer registers */
1880 FP_REGS, /* floating point registers */
1881 MD0_REG, /* first multiply/divide register */
1882 MD1_REG, /* second multiply/divide register */
1883 MD_REGS, /* multiply/divide registers (hi/lo) */
1884 COP0_REGS, /* generic coprocessor classes */
1885 COP2_REGS,
1886 COP3_REGS,
1887 ST_REGS, /* status registers (fp status) */
1888 DSP_ACC_REGS, /* DSP accumulator registers */
1889 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1890 FRAME_REGS, /* $arg and $frame */
1891 GR_AND_MD0_REGS, /* union classes */
1892 GR_AND_MD1_REGS,
1893 GR_AND_MD_REGS,
1894 GR_AND_ACC_REGS,
1895 ALL_REGS, /* all registers */
1896 LIM_REG_CLASSES /* max value + 1 */
1897 };
1898
1899 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1900
1901 #define GENERAL_REGS GR_REGS
1902
1903 /* An initializer containing the names of the register classes as C
1904 string constants. These names are used in writing some of the
1905 debugging dumps. */
1906
1907 #define REG_CLASS_NAMES \
1908 { \
1909 "NO_REGS", \
1910 "M16_STORE_REGS", \
1911 "M16_REGS", \
1912 "M16_SP_REGS", \
1913 "T_REG", \
1914 "M16_T_REGS", \
1915 "PIC_FN_ADDR_REG", \
1916 "V1_REG", \
1917 "SPILL_REGS", \
1918 "LEA_REGS", \
1919 "GR_REGS", \
1920 "FP_REGS", \
1921 "MD0_REG", \
1922 "MD1_REG", \
1923 "MD_REGS", \
1924 /* coprocessor registers */ \
1925 "COP0_REGS", \
1926 "COP2_REGS", \
1927 "COP3_REGS", \
1928 "ST_REGS", \
1929 "DSP_ACC_REGS", \
1930 "ACC_REGS", \
1931 "FRAME_REGS", \
1932 "GR_AND_MD0_REGS", \
1933 "GR_AND_MD1_REGS", \
1934 "GR_AND_MD_REGS", \
1935 "GR_AND_ACC_REGS", \
1936 "ALL_REGS" \
1937 }
1938
1939 /* An initializer containing the contents of the register classes,
1940 as integers which are bit masks. The Nth integer specifies the
1941 contents of class N. The way the integer MASK is interpreted is
1942 that register R is in the class if `MASK & (1 << R)' is 1.
1943
1944 When the machine has more than 32 registers, an integer does not
1945 suffice. Then the integers are replaced by sub-initializers,
1946 braced groupings containing several integers. Each
1947 sub-initializer must be suitable as an initializer for the type
1948 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1949
1950 #define REG_CLASS_CONTENTS \
1951 { \
1952 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1953 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
1954 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1955 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
1956 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1957 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1958 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1959 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1960 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
1961 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1962 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1963 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1964 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1965 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1966 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1967 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1968 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1969 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1970 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1971 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1972 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1973 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1974 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1975 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1976 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1977 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1978 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1979 }
1980
1981
1982 /* A C expression whose value is a register class containing hard
1983 register REGNO. In general there is more that one such class;
1984 choose a class which is "minimal", meaning that no smaller class
1985 also contains the register. */
1986
1987 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1988
1989 /* A macro whose definition is the name of the class to which a
1990 valid base register must belong. A base register is one used in
1991 an address which is the register value plus a displacement. */
1992
1993 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
1994
1995 /* A macro whose definition is the name of the class to which a
1996 valid index register must belong. An index register is one used
1997 in an address where its value is either multiplied by a scale
1998 factor or added to another register (as well as added to a
1999 displacement). */
2000
2001 #define INDEX_REG_CLASS NO_REGS
2002
2003 /* We generally want to put call-clobbered registers ahead of
2004 call-saved ones. (IRA expects this.) */
2005
2006 #define REG_ALLOC_ORDER \
2007 { /* Accumulator registers. When GPRs and accumulators have equal \
2008 cost, we generally prefer to use accumulators. For example, \
2009 a division of multiplication result is better allocated to LO, \
2010 so that we put the MFLO at the point of use instead of at the \
2011 point of definition. It's also needed if we're to take advantage \
2012 of the extra accumulators available with -mdspr2. In some cases, \
2013 it can also help to reduce register pressure. */ \
2014 64, 65,176,177,178,179,180,181, \
2015 /* Call-clobbered GPRs. */ \
2016 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2017 24, 25, 31, \
2018 /* The global pointer. This is call-clobbered for o32 and o64 \
2019 abicalls, call-saved for n32 and n64 abicalls, and a program \
2020 invariant otherwise. Putting it between the call-clobbered \
2021 and call-saved registers should cope with all eventualities. */ \
2022 28, \
2023 /* Call-saved GPRs. */ \
2024 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2025 /* GPRs that can never be exposed to the register allocator. */ \
2026 0, 26, 27, 29, \
2027 /* Call-clobbered FPRs. */ \
2028 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2029 48, 49, 50, 51, \
2030 /* FPRs that are usually call-saved. The odd ones are actually \
2031 call-clobbered for n32, but listing them ahead of the even \
2032 registers might encourage the register allocator to fragment \
2033 the available FPR pairs. We need paired FPRs to store long \
2034 doubles, so it isn't clear that using a different order \
2035 for n32 would be a win. */ \
2036 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2037 /* None of the remaining classes have defined call-saved \
2038 registers. */ \
2039 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2040 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2041 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2042 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2043 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2044 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2045 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2046 182,183,184,185,186,187 \
2047 }
2048
2049 /* True if VALUE is an unsigned 6-bit number. */
2050
2051 #define UIMM6_OPERAND(VALUE) \
2052 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2053
2054 /* True if VALUE is a signed 10-bit number. */
2055
2056 #define IMM10_OPERAND(VALUE) \
2057 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2058
2059 /* True if VALUE is a signed 16-bit number. */
2060
2061 #define SMALL_OPERAND(VALUE) \
2062 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2063
2064 /* True if VALUE is an unsigned 16-bit number. */
2065
2066 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2067 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2068
2069 /* True if VALUE can be loaded into a register using LUI. */
2070
2071 #define LUI_OPERAND(VALUE) \
2072 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2073 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2074
2075 /* Return a value X with the low 16 bits clear, and such that
2076 VALUE - X is a signed 16-bit value. */
2077
2078 #define CONST_HIGH_PART(VALUE) \
2079 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2080
2081 #define CONST_LOW_PART(VALUE) \
2082 ((VALUE) - CONST_HIGH_PART (VALUE))
2083
2084 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2085 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2086 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2087 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2088
2089 /* The HI and LO registers can only be reloaded via the general
2090 registers. Condition code registers can only be loaded to the
2091 general registers, and from the floating point registers. */
2092
2093 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2094 mips_secondary_reload_class (CLASS, MODE, X, true)
2095 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2096 mips_secondary_reload_class (CLASS, MODE, X, false)
2097
2098 /* Return the maximum number of consecutive registers
2099 needed to represent mode MODE in a register of class CLASS. */
2100
2101 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2102
2103 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2104 mips_cannot_change_mode_class (FROM, TO, CLASS)
2105 \f
2106 /* Stack layout; function entry, exit and calling. */
2107
2108 #define STACK_GROWS_DOWNWARD
2109
2110 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2111
2112 /* Size of the area allocated in the frame to save the GP. */
2113
2114 #define MIPS_GP_SAVE_AREA_SIZE \
2115 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2116
2117 /* The offset of the first local variable from the frame pointer. See
2118 mips_compute_frame_info for details about the frame layout. */
2119
2120 #define STARTING_FRAME_OFFSET \
2121 (FRAME_GROWS_DOWNWARD \
2122 ? 0 \
2123 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2124
2125 #define RETURN_ADDR_RTX mips_return_addr
2126
2127 /* Mask off the MIPS16 ISA bit in unwind addresses.
2128
2129 The reason for this is a little subtle. When unwinding a call,
2130 we are given the call's return address, which on most targets
2131 is the address of the following instruction. However, what we
2132 actually want to find is the EH region for the call itself.
2133 The target-independent unwind code therefore searches for "RA - 1".
2134
2135 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2136 RA - 1 is therefore the real (even-valued) start of the return
2137 instruction. EH region labels are usually odd-valued MIPS16 symbols
2138 too, so a search for an even address within a MIPS16 region would
2139 usually work.
2140
2141 However, there is an exception. If the end of an EH region is also
2142 the end of a function, the end label is allowed to be even. This is
2143 necessary because a following non-MIPS16 function may also need EH
2144 information for its first instruction.
2145
2146 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2147 non-ISA-encoded address. This probably isn't ideal, but it is
2148 the traditional (legacy) behavior. It is therefore only safe
2149 to search MIPS EH regions for an _odd-valued_ address.
2150
2151 Masking off the ISA bit means that the target-independent code
2152 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2153 #define MASK_RETURN_ADDR GEN_INT (-2)
2154
2155
2156 /* Similarly, don't use the least-significant bit to tell pointers to
2157 code from vtable index. */
2158
2159 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2160
2161 /* The eliminations to $17 are only used for mips16 code. See the
2162 definition of HARD_FRAME_POINTER_REGNUM. */
2163
2164 #define ELIMINABLE_REGS \
2165 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2166 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2167 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2168 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2169 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2170 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2171
2172 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2173 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2174
2175 /* Allocate stack space for arguments at the beginning of each function. */
2176 #define ACCUMULATE_OUTGOING_ARGS 1
2177
2178 /* The argument pointer always points to the first argument. */
2179 #define FIRST_PARM_OFFSET(FNDECL) 0
2180
2181 /* o32 and o64 reserve stack space for all argument registers. */
2182 #define REG_PARM_STACK_SPACE(FNDECL) \
2183 (TARGET_OLDABI \
2184 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2185 : 0)
2186
2187 /* Define this if it is the responsibility of the caller to
2188 allocate the area reserved for arguments passed in registers.
2189 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2190 of this macro is to determine whether the space is included in
2191 `crtl->outgoing_args_size'. */
2192 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2193
2194 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2195 \f
2196 /* Symbolic macros for the registers used to return integer and floating
2197 point values. */
2198
2199 #define GP_RETURN (GP_REG_FIRST + 2)
2200 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2201
2202 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2203
2204 /* Symbolic macros for the first/last argument registers. */
2205
2206 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2207 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2208 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2209 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2210
2211 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2212 are used for returning complex double values in soft-float code, so $6 is the
2213 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2214 $gp itself as the temporary. */
2215 #define POST_CALL_TMP_REG \
2216 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2217
2218 /* 1 if N is a possible register number for function argument passing.
2219 We have no FP argument registers when soft-float. When FP registers
2220 are 32 bits, we can't directly reference the odd numbered ones. */
2221
2222 #define FUNCTION_ARG_REGNO_P(N) \
2223 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2224 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2225 && !fixed_regs[N])
2226 \f
2227 /* This structure has to cope with two different argument allocation
2228 schemes. Most MIPS ABIs view the arguments as a structure, of which
2229 the first N words go in registers and the rest go on the stack. If I
2230 < N, the Ith word might go in Ith integer argument register or in a
2231 floating-point register. For these ABIs, we only need to remember
2232 the offset of the current argument into the structure.
2233
2234 The EABI instead allocates the integer and floating-point arguments
2235 separately. The first N words of FP arguments go in FP registers,
2236 the rest go on the stack. Likewise, the first N words of the other
2237 arguments go in integer registers, and the rest go on the stack. We
2238 need to maintain three counts: the number of integer registers used,
2239 the number of floating-point registers used, and the number of words
2240 passed on the stack.
2241
2242 We could keep separate information for the two ABIs (a word count for
2243 the standard ABIs, and three separate counts for the EABI). But it
2244 seems simpler to view the standard ABIs as forms of EABI that do not
2245 allocate floating-point registers.
2246
2247 So for the standard ABIs, the first N words are allocated to integer
2248 registers, and mips_function_arg decides on an argument-by-argument
2249 basis whether that argument should really go in an integer register,
2250 or in a floating-point one. */
2251
2252 typedef struct mips_args {
2253 /* Always true for varargs functions. Otherwise true if at least
2254 one argument has been passed in an integer register. */
2255 int gp_reg_found;
2256
2257 /* The number of arguments seen so far. */
2258 unsigned int arg_number;
2259
2260 /* The number of integer registers used so far. For all ABIs except
2261 EABI, this is the number of words that have been added to the
2262 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2263 unsigned int num_gprs;
2264
2265 /* For EABI, the number of floating-point registers used so far. */
2266 unsigned int num_fprs;
2267
2268 /* The number of words passed on the stack. */
2269 unsigned int stack_words;
2270
2271 /* On the mips16, we need to keep track of which floating point
2272 arguments were passed in general registers, but would have been
2273 passed in the FP regs if this were a 32-bit function, so that we
2274 can move them to the FP regs if we wind up calling a 32-bit
2275 function. We record this information in fp_code, encoded in base
2276 four. A zero digit means no floating point argument, a one digit
2277 means an SFmode argument, and a two digit means a DFmode argument,
2278 and a three digit is not used. The low order digit is the first
2279 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2280 an SFmode argument. ??? A more sophisticated approach will be
2281 needed if MIPS_ABI != ABI_32. */
2282 int fp_code;
2283
2284 /* True if the function has a prototype. */
2285 int prototype;
2286 } CUMULATIVE_ARGS;
2287
2288 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2289 for a call to a function whose data type is FNTYPE.
2290 For a library call, FNTYPE is 0. */
2291
2292 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2293 mips_init_cumulative_args (&CUM, FNTYPE)
2294
2295 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2296 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2297
2298 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2299 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2300
2301 /* True if using EABI and varargs can be passed in floating-point
2302 registers. Under these conditions, we need a more complex form
2303 of va_list, which tracks GPR, FPR and stack arguments separately. */
2304 #define EABI_FLOAT_VARARGS_P \
2305 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2306
2307 \f
2308 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2309
2310 /* Treat LOC as a byte offset from the stack pointer and round it up
2311 to the next fully-aligned offset. */
2312 #define MIPS_STACK_ALIGN(LOC) \
2313 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2314
2315 \f
2316 /* Output assembler code to FILE to increment profiler label # LABELNO
2317 for profiling a function entry. */
2318
2319 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2320
2321 /* The profiler preserves all interesting registers, including $31. */
2322 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2323
2324 /* No mips port has ever used the profiler counter word, so don't emit it
2325 or the label for it. */
2326
2327 #define NO_PROFILE_COUNTERS 1
2328
2329 /* Define this macro if the code for function profiling should come
2330 before the function prologue. Normally, the profiling code comes
2331 after. */
2332
2333 /* #define PROFILE_BEFORE_PROLOGUE */
2334
2335 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2336 the stack pointer does not matter. The value is tested only in
2337 functions that have frame pointers.
2338 No definition is equivalent to always zero. */
2339
2340 #define EXIT_IGNORE_STACK 1
2341
2342 \f
2343 /* Trampolines are a block of code followed by two pointers. */
2344
2345 #define TRAMPOLINE_SIZE \
2346 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2347
2348 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2349 pointers from a single LUI base. */
2350
2351 #define TRAMPOLINE_ALIGNMENT 64
2352
2353 /* mips_trampoline_init calls this library function to flush
2354 program and data caches. */
2355
2356 #ifndef CACHE_FLUSH_FUNC
2357 #define CACHE_FLUSH_FUNC "_flush_cache"
2358 #endif
2359
2360 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2361 /* Flush both caches. We need to flush the data cache in case \
2362 the system has a write-back cache. */ \
2363 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2364 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2365 GEN_INT (3), TYPE_MODE (integer_type_node))
2366
2367 \f
2368 /* Addressing modes, and classification of registers for them. */
2369
2370 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2371 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2372 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2373 \f
2374 /* Maximum number of registers that can appear in a valid memory address. */
2375
2376 #define MAX_REGS_PER_ADDRESS 1
2377
2378 /* Check for constness inline but use mips_legitimate_address_p
2379 to check whether a constant really is an address. */
2380
2381 #define CONSTANT_ADDRESS_P(X) \
2382 (CONSTANT_P (X) && memory_address_p (SImode, X))
2383
2384 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2385 'the start of the function that this code is output in'. */
2386
2387 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2388 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2389 asm_fprintf ((FILE), "%U%s", \
2390 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2391 else \
2392 asm_fprintf ((FILE), "%U%s", (NAME))
2393 \f
2394 /* Flag to mark a function decl symbol that requires a long call. */
2395 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2396 #define SYMBOL_REF_LONG_CALL_P(X) \
2397 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2398
2399 /* This flag marks functions that cannot be lazily bound. */
2400 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2401 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2402 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2403
2404 /* True if we're generating a form of MIPS16 code in which jump tables
2405 are stored in the text section and encoded as 16-bit PC-relative
2406 offsets. This is only possible when general text loads are allowed,
2407 since the table access itself will be an "lh" instruction. If the
2408 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2409 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2410
2411 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2412
2413 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2414
2415 /* Only use short offsets if their range will not overflow. */
2416 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2417 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2418 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2419 : SImode)
2420
2421 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2422
2423 /* Define this as 1 if `char' should by default be signed; else as 0. */
2424 #ifndef DEFAULT_SIGNED_CHAR
2425 #define DEFAULT_SIGNED_CHAR 1
2426 #endif
2427
2428 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2429 we generally don't want to use them for copying arbitrary data.
2430 A single N-word move is usually the same cost as N single-word moves. */
2431 #define MOVE_MAX UNITS_PER_WORD
2432 #define MAX_MOVE_MAX 8
2433
2434 /* Define this macro as a C expression which is nonzero if
2435 accessing less than a word of memory (i.e. a `char' or a
2436 `short') is no faster than accessing a word of memory, i.e., if
2437 such access require more than one instruction or if there is no
2438 difference in cost between byte and (aligned) word loads.
2439
2440 On RISC machines, it tends to generate better code to define
2441 this as 1, since it avoids making a QI or HI mode register.
2442
2443 But, generating word accesses for -mips16 is generally bad as shifts
2444 (often extended) would be needed for byte accesses. */
2445 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2446
2447 /* Standard MIPS integer shifts truncate the shift amount to the
2448 width of the shifted operand. However, Loongson vector shifts
2449 do not truncate the shift amount at all. */
2450 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2451
2452 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2453 is done just by pretending it is already truncated. */
2454 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2455 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2456
2457
2458 /* Specify the machine mode that pointers have.
2459 After generation of rtl, the compiler makes no further distinction
2460 between pointers and any other objects of this machine mode. */
2461
2462 #ifndef Pmode
2463 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2464 #endif
2465
2466 /* Give call MEMs SImode since it is the "most permissive" mode
2467 for both 32-bit and 64-bit targets. */
2468
2469 #define FUNCTION_MODE SImode
2470
2471 \f
2472 /* We allocate $fcc registers by hand and can't cope with moves of
2473 CCmode registers to and from pseudos (or memory). */
2474 #define AVOID_CCMODE_COPIES
2475
2476 /* A C expression for the cost of a branch instruction. A value of
2477 1 is the default; other values are interpreted relative to that. */
2478
2479 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2480 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2481
2482 /* The MIPS port has several functions that return an instruction count.
2483 Multiplying the count by this value gives the number of bytes that
2484 the instructions occupy. */
2485 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2486
2487 /* The length of a NOP in bytes. */
2488 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2489
2490 /* If defined, modifies the length assigned to instruction INSN as a
2491 function of the context in which it is used. LENGTH is an lvalue
2492 that contains the initially computed length of the insn and should
2493 be updated with the correct length of the insn. */
2494 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2495 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2496
2497 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2498 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2499 its operands. */
2500 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2501 "%*" OPCODE "%?\t" OPERANDS "%/"
2502
2503 /* Return an asm string that forces INSN to be treated as an absolute
2504 J or JAL instruction instead of an assembler macro. */
2505 #define MIPS_ABSOLUTE_JUMP(INSN) \
2506 (TARGET_ABICALLS_PIC2 \
2507 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2508 : INSN)
2509
2510 /* Return the asm template for a call. INSN is the instruction's mnemonic
2511 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2512 number of the target. SIZE_OPNO is the operand number of the argument size
2513 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2514 -1 and the call is indirect, use the function symbol from the call
2515 attributes to attach a R_MIPS_JALR relocation to the call.
2516
2517 When generating GOT code without explicit relocation operators,
2518 all calls should use assembly macros. Otherwise, all indirect
2519 calls should use "jr" or "jalr"; we will arrange to restore $gp
2520 afterwards if necessary. Finally, we can only generate direct
2521 calls for -mabicalls by temporarily switching to non-PIC mode.
2522
2523 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2524 instruction is in the delay slot of jal(r). */
2525 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2526 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2527 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2528 : REG_P (OPERANDS[TARGET_OPNO]) \
2529 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2530 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2531 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2532 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2533 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2534 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2535 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2536 ? MIPS_ABSOLUTE_JUMP ("%*" INSN "%!\t%" #TARGET_OPNO "%/") \
2537 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/")) \
2538
2539 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2540 "jrc" when nop is in the delay slot of "jr". */
2541
2542 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2543 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2544 ? "%*j\t%" #OPNO "%/" \
2545 : REG_P (OPERANDS[OPNO]) \
2546 ? "%*jr%:\t%" #OPNO \
2547 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2548
2549 \f
2550 /* Control the assembler format that we output. */
2551
2552 /* Output to assembler file text saying following lines
2553 may contain character constants, extra white space, comments, etc. */
2554
2555 #ifndef ASM_APP_ON
2556 #define ASM_APP_ON " #APP\n"
2557 #endif
2558
2559 /* Output to assembler file text saying following lines
2560 no longer contain unusual constructs. */
2561
2562 #ifndef ASM_APP_OFF
2563 #define ASM_APP_OFF " #NO_APP\n"
2564 #endif
2565
2566 #define REGISTER_NAMES \
2567 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2568 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2569 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2570 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2571 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2572 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2573 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2574 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2575 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2576 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2577 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2578 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2579 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2580 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2581 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2582 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2583 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2584 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2585 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2586 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2587 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2588 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2589 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2590 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2591
2592 /* List the "software" names for each register. Also list the numerical
2593 names for $fp and $sp. */
2594
2595 #define ADDITIONAL_REGISTER_NAMES \
2596 { \
2597 { "$29", 29 + GP_REG_FIRST }, \
2598 { "$30", 30 + GP_REG_FIRST }, \
2599 { "at", 1 + GP_REG_FIRST }, \
2600 { "v0", 2 + GP_REG_FIRST }, \
2601 { "v1", 3 + GP_REG_FIRST }, \
2602 { "a0", 4 + GP_REG_FIRST }, \
2603 { "a1", 5 + GP_REG_FIRST }, \
2604 { "a2", 6 + GP_REG_FIRST }, \
2605 { "a3", 7 + GP_REG_FIRST }, \
2606 { "t0", 8 + GP_REG_FIRST }, \
2607 { "t1", 9 + GP_REG_FIRST }, \
2608 { "t2", 10 + GP_REG_FIRST }, \
2609 { "t3", 11 + GP_REG_FIRST }, \
2610 { "t4", 12 + GP_REG_FIRST }, \
2611 { "t5", 13 + GP_REG_FIRST }, \
2612 { "t6", 14 + GP_REG_FIRST }, \
2613 { "t7", 15 + GP_REG_FIRST }, \
2614 { "s0", 16 + GP_REG_FIRST }, \
2615 { "s1", 17 + GP_REG_FIRST }, \
2616 { "s2", 18 + GP_REG_FIRST }, \
2617 { "s3", 19 + GP_REG_FIRST }, \
2618 { "s4", 20 + GP_REG_FIRST }, \
2619 { "s5", 21 + GP_REG_FIRST }, \
2620 { "s6", 22 + GP_REG_FIRST }, \
2621 { "s7", 23 + GP_REG_FIRST }, \
2622 { "t8", 24 + GP_REG_FIRST }, \
2623 { "t9", 25 + GP_REG_FIRST }, \
2624 { "k0", 26 + GP_REG_FIRST }, \
2625 { "k1", 27 + GP_REG_FIRST }, \
2626 { "gp", 28 + GP_REG_FIRST }, \
2627 { "sp", 29 + GP_REG_FIRST }, \
2628 { "fp", 30 + GP_REG_FIRST }, \
2629 { "ra", 31 + GP_REG_FIRST } \
2630 }
2631
2632 #define DBR_OUTPUT_SEQEND(STREAM) \
2633 do \
2634 { \
2635 /* Undo the effect of '%*'. */ \
2636 mips_pop_asm_switch (&mips_nomacro); \
2637 mips_pop_asm_switch (&mips_noreorder); \
2638 /* Emit a blank line after the delay slot for emphasis. */ \
2639 fputs ("\n", STREAM); \
2640 } \
2641 while (0)
2642
2643 /* The MIPS implementation uses some labels for its own purpose. The
2644 following lists what labels are created, and are all formed by the
2645 pattern $L[a-z].*. The machine independent portion of GCC creates
2646 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2647
2648 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2649 $Lb[0-9]+ Begin blocks for MIPS debug support
2650 $Lc[0-9]+ Label for use in s<xx> operation.
2651 $Le[0-9]+ End blocks for MIPS debug support */
2652
2653 #undef ASM_DECLARE_OBJECT_NAME
2654 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2655 mips_declare_object (STREAM, NAME, "", ":\n")
2656
2657 /* Globalizing directive for a label. */
2658 #define GLOBAL_ASM_OP "\t.globl\t"
2659
2660 /* This says how to define a global common symbol. */
2661
2662 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2663
2664 /* This says how to define a local common symbol (i.e., not visible to
2665 linker). */
2666
2667 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2668 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2669 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2670 #endif
2671
2672 /* This says how to output an external. It would be possible not to
2673 output anything and let undefined symbol become external. However
2674 the assembler uses length information on externals to allocate in
2675 data/sdata bss/sbss, thereby saving exec time. */
2676
2677 #undef ASM_OUTPUT_EXTERNAL
2678 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2679 mips_output_external(STREAM,DECL,NAME)
2680
2681 /* This is how to declare a function name. The actual work of
2682 emitting the label is moved to function_prologue, so that we can
2683 get the line number correctly emitted before the .ent directive,
2684 and after any .file directives. Define as empty so that the function
2685 is not declared before the .ent directive elsewhere. */
2686
2687 #undef ASM_DECLARE_FUNCTION_NAME
2688 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2689
2690 /* This is how to store into the string LABEL
2691 the symbol_ref name of an internal numbered label where
2692 PREFIX is the class of label and NUM is the number within the class.
2693 This is suitable for output with `assemble_name'. */
2694
2695 #undef ASM_GENERATE_INTERNAL_LABEL
2696 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2697 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2698
2699 /* Print debug labels as "foo = ." rather than "foo:" because they should
2700 represent a byte pointer rather than an ISA-encoded address. This is
2701 particularly important for code like:
2702
2703 $LFBxxx = .
2704 .cfi_startproc
2705 ...
2706 .section .gcc_except_table,...
2707 ...
2708 .uleb128 foo-$LFBxxx
2709
2710 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2711 likewise a byte pointer rather than an ISA-encoded address.
2712
2713 At the time of writing, this hook is not used for the function end
2714 label:
2715
2716 $LFExxx:
2717 .end foo
2718
2719 But this doesn't matter, because GAS doesn't treat a pre-.end label
2720 as a MIPS16 one anyway. */
2721
2722 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2723 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2724
2725 /* This is how to output an element of a case-vector that is absolute. */
2726
2727 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2728 fprintf (STREAM, "\t%s\t%sL%d\n", \
2729 ptr_mode == DImode ? ".dword" : ".word", \
2730 LOCAL_LABEL_PREFIX, \
2731 VALUE)
2732
2733 /* This is how to output an element of a case-vector. We can make the
2734 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2735 is supported. */
2736
2737 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2738 do { \
2739 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2740 { \
2741 if (GET_MODE (BODY) == HImode) \
2742 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2743 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2744 else \
2745 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2746 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2747 } \
2748 else if (TARGET_GPWORD) \
2749 fprintf (STREAM, "\t%s\t%sL%d\n", \
2750 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2751 LOCAL_LABEL_PREFIX, VALUE); \
2752 else if (TARGET_RTP_PIC) \
2753 { \
2754 /* Make the entry relative to the start of the function. */ \
2755 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2756 fprintf (STREAM, "\t%s\t%sL%d-", \
2757 Pmode == DImode ? ".dword" : ".word", \
2758 LOCAL_LABEL_PREFIX, VALUE); \
2759 assemble_name (STREAM, XSTR (fnsym, 0)); \
2760 fprintf (STREAM, "\n"); \
2761 } \
2762 else \
2763 fprintf (STREAM, "\t%s\t%sL%d\n", \
2764 ptr_mode == DImode ? ".dword" : ".word", \
2765 LOCAL_LABEL_PREFIX, VALUE); \
2766 } while (0)
2767
2768 /* This is how to output an assembler line
2769 that says to advance the location counter
2770 to a multiple of 2**LOG bytes. */
2771
2772 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2773 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2774
2775 /* This is how to output an assembler line to advance the location
2776 counter by SIZE bytes. */
2777
2778 #undef ASM_OUTPUT_SKIP
2779 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2780 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2781
2782 /* This is how to output a string. */
2783 #undef ASM_OUTPUT_ASCII
2784 #define ASM_OUTPUT_ASCII mips_output_ascii
2785
2786 \f
2787 /* Default to -G 8 */
2788 #ifndef MIPS_DEFAULT_GVALUE
2789 #define MIPS_DEFAULT_GVALUE 8
2790 #endif
2791
2792 /* Define the strings to put out for each section in the object file. */
2793 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2794 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2795
2796 #undef READONLY_DATA_SECTION_ASM_OP
2797 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2798 \f
2799 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2800 do \
2801 { \
2802 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2803 TARGET_64BIT ? "daddiu" : "addiu", \
2804 reg_names[STACK_POINTER_REGNUM], \
2805 reg_names[STACK_POINTER_REGNUM], \
2806 TARGET_64BIT ? "sd" : "sw", \
2807 reg_names[REGNO], \
2808 reg_names[STACK_POINTER_REGNUM]); \
2809 } \
2810 while (0)
2811
2812 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2813 do \
2814 { \
2815 mips_push_asm_switch (&mips_noreorder); \
2816 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2817 TARGET_64BIT ? "ld" : "lw", \
2818 reg_names[REGNO], \
2819 reg_names[STACK_POINTER_REGNUM], \
2820 TARGET_64BIT ? "daddu" : "addu", \
2821 reg_names[STACK_POINTER_REGNUM], \
2822 reg_names[STACK_POINTER_REGNUM]); \
2823 mips_pop_asm_switch (&mips_noreorder); \
2824 } \
2825 while (0)
2826
2827 /* How to start an assembler comment.
2828 The leading space is important (the mips native assembler requires it). */
2829 #ifndef ASM_COMMENT_START
2830 #define ASM_COMMENT_START " #"
2831 #endif
2832 \f
2833 #undef SIZE_TYPE
2834 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2835
2836 #undef PTRDIFF_TYPE
2837 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2838
2839 /* The maximum number of bytes that can be copied by one iteration of
2840 a movmemsi loop; see mips_block_move_loop. */
2841 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2842 (UNITS_PER_WORD * 4)
2843
2844 /* The maximum number of bytes that can be copied by a straight-line
2845 implementation of movmemsi; see mips_block_move_straight. We want
2846 to make sure that any loop-based implementation will iterate at
2847 least twice. */
2848 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2849 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2850
2851 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2852 values were determined experimentally by benchmarking with CSiBE.
2853 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2854 for o32 where we have to restore $gp afterwards as well as make an
2855 indirect call), but in practice, bumping this up higher for
2856 TARGET_ABICALLS doesn't make much difference to code size. */
2857
2858 #define MIPS_CALL_RATIO 8
2859
2860 /* Any loop-based implementation of movmemsi will have at least
2861 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2862 moves, so allow individual copies of fewer elements.
2863
2864 When movmemsi is not available, use a value approximating
2865 the length of a memcpy call sequence, so that move_by_pieces
2866 will generate inline code if it is shorter than a function call.
2867 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2868 we'll have to generate a load/store pair for each, halve the
2869 value of MIPS_CALL_RATIO to take that into account. */
2870
2871 #define MOVE_RATIO(speed) \
2872 (HAVE_movmemsi \
2873 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2874 : MIPS_CALL_RATIO / 2)
2875
2876 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2877 mips_move_by_pieces_p (SIZE, ALIGN)
2878
2879 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2880 of the length of a memset call, but use the default otherwise. */
2881
2882 #define CLEAR_RATIO(speed)\
2883 ((speed) ? 15 : MIPS_CALL_RATIO)
2884
2885 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2886 optimizing for size adjust the ratio to account for the overhead of
2887 loading the constant and replicating it across the word. */
2888
2889 #define SET_RATIO(speed) \
2890 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2891
2892 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2893 mips_store_by_pieces_p (SIZE, ALIGN)
2894 \f
2895 /* Since the bits of the _init and _fini function is spread across
2896 many object files, each potentially with its own GP, we must assume
2897 we need to load our GP. We don't preserve $gp or $ra, since each
2898 init/fini chunk is supposed to initialize $gp, and crti/crtn
2899 already take care of preserving $ra and, when appropriate, $gp. */
2900 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2901 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2902 asm (SECTION_OP "\n\
2903 .set push\n\
2904 .set nomips16\n\
2905 .set noreorder\n\
2906 bal 1f\n\
2907 nop\n\
2908 1: .cpload $31\n\
2909 .set reorder\n\
2910 jal " USER_LABEL_PREFIX #FUNC "\n\
2911 .set pop\n\
2912 " TEXT_SECTION_ASM_OP);
2913 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2914 || (defined _ABI64 && _MIPS_SIM == _ABI64))
2915 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2916 asm (SECTION_OP "\n\
2917 .set push\n\
2918 .set nomips16\n\
2919 .set noreorder\n\
2920 bal 1f\n\
2921 nop\n\
2922 1: .set reorder\n\
2923 .cpsetup $31, $2, 1b\n\
2924 jal " USER_LABEL_PREFIX #FUNC "\n\
2925 .set pop\n\
2926 " TEXT_SECTION_ASM_OP);
2927 #endif
2928
2929 #ifndef HAVE_AS_TLS
2930 #define HAVE_AS_TLS 0
2931 #endif
2932
2933 #ifndef HAVE_AS_NAN
2934 #define HAVE_AS_NAN 0
2935 #endif
2936
2937 #ifndef USED_FOR_TARGET
2938 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2939 struct mips_asm_switch {
2940 /* The FOO in the description above. */
2941 const char *name;
2942
2943 /* The current block nesting level, or 0 if we aren't in a block. */
2944 int nesting_level;
2945 };
2946
2947 extern const enum reg_class mips_regno_to_class[];
2948 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2949 extern const char *current_function_file; /* filename current function is in */
2950 extern int num_source_filenames; /* current .file # */
2951 extern struct mips_asm_switch mips_noreorder;
2952 extern struct mips_asm_switch mips_nomacro;
2953 extern struct mips_asm_switch mips_noat;
2954 extern int mips_dbx_regno[];
2955 extern int mips_dwarf_regno[];
2956 extern bool mips_split_p[];
2957 extern bool mips_split_hi_p[];
2958 extern bool mips_use_pcrel_pool_p[];
2959 extern const char *mips_lo_relocs[];
2960 extern const char *mips_hi_relocs[];
2961 extern enum processor mips_arch; /* which cpu to codegen for */
2962 extern enum processor mips_tune; /* which cpu to schedule for */
2963 extern int mips_isa; /* architectural level */
2964 extern int mips_isa_rev;
2965 extern const struct mips_cpu_info *mips_arch_info;
2966 extern const struct mips_cpu_info *mips_tune_info;
2967 extern unsigned int mips_base_compression_flags;
2968 extern GTY(()) struct target_globals *mips16_globals;
2969 #endif
2970
2971 /* Enable querying of DFA units. */
2972 #define CPU_UNITS_QUERY 1
2973
2974 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2975 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2976
2977 /* As on most targets, we want the .eh_frame section to be read-only where
2978 possible. And as on most targets, this means two things:
2979
2980 (a) Non-locally-binding pointers must have an indirect encoding,
2981 so that the addresses in the .eh_frame section itself become
2982 locally-binding.
2983
2984 (b) A shared library's .eh_frame section must encode locally-binding
2985 pointers in a relative (relocation-free) form.
2986
2987 However, MIPS has traditionally not allowed directives like:
2988
2989 .long x-.
2990
2991 in cases where "x" is in a different section, or is not defined in the
2992 same assembly file. We are therefore unable to emit the PC-relative
2993 form required by (b) at assembly time.
2994
2995 Fortunately, the linker is able to convert absolute addresses into
2996 PC-relative addresses on our behalf. Unfortunately, only certain
2997 versions of the linker know how to do this for indirect pointers,
2998 and for personality data. We must fall back on using writable
2999 .eh_frame sections for shared libraries if the linker does not
3000 support this feature. */
3001 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3002 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3003
3004 /* For switching between MIPS16 and non-MIPS16 modes. */
3005 #define SWITCHABLE_TARGET 1
3006
3007 /* Several named MIPS patterns depend on Pmode. These patterns have the
3008 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3009 Add the appropriate suffix to generator function NAME and invoke it
3010 with arguments ARGS. */
3011 #define PMODE_INSN(NAME, ARGS) \
3012 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)