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mips.h (ISA_HAS_FP4): Correct formatting.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS64 (mips_isa == 64)
212 #define ISA_MIPS64R2 (mips_isa == 65)
213
214 /* Architecture target defines. */
215 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
216 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
217 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
218 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
219 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
220 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
221 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
222 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
223 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
224 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
225 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
226 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
227 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
228 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
229 || mips_arch == PROCESSOR_OCTEON2)
230 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
231 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
232 || mips_arch == PROCESSOR_SB1A)
233 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
234 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
235
236 /* Scheduling target defines. */
237 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
238 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
239 || mips_tune == PROCESSOR_24KF2_1 \
240 || mips_tune == PROCESSOR_24KF1_1)
241 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
242 || mips_tune == PROCESSOR_74KF2_1 \
243 || mips_tune == PROCESSOR_74KF1_1 \
244 || mips_tune == PROCESSOR_74KF3_2)
245 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
246 || mips_tune == PROCESSOR_LOONGSON_2F)
247 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
248 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
249 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
250 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
251 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
252 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
253 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
254 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
255 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
256 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
257 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
258 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
259 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
260 || mips_tune == PROCESSOR_OCTEON2)
261 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
262 || mips_tune == PROCESSOR_SB1A)
263
264 /* Whether vector modes and intrinsics for ST Microelectronics
265 Loongson-2E/2F processors should be enabled. In o32 pairs of
266 floating-point registers provide 64-bit values. */
267 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
268 && (TARGET_LOONGSON_2EF \
269 || TARGET_LOONGSON_3A))
270
271 /* True if the pre-reload scheduler should try to create chains of
272 multiply-add or multiply-subtract instructions. For example,
273 suppose we have:
274
275 t1 = a * b
276 t2 = t1 + c * d
277 t3 = e * f
278 t4 = t3 - g * h
279
280 t1 will have a higher priority than t2 and t3 will have a higher
281 priority than t4. However, before reload, there is no dependence
282 between t1 and t3, and they can often have similar priorities.
283 The scheduler will then tend to prefer:
284
285 t1 = a * b
286 t3 = e * f
287 t2 = t1 + c * d
288 t4 = t3 - g * h
289
290 which stops us from making full use of macc/madd-style instructions.
291 This sort of situation occurs frequently in Fourier transforms and
292 in unrolled loops.
293
294 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
295 queue so that chained multiply-add and multiply-subtract instructions
296 appear ahead of any other instruction that is likely to clobber lo.
297 In the example above, if t2 and t3 become ready at the same time,
298 the code ensures that t2 is scheduled first.
299
300 Multiply-accumulate instructions are a bigger win for some targets
301 than others, so this macro is defined on an opt-in basis. */
302 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
303 || TUNE_MIPS4120 \
304 || TUNE_MIPS4130 \
305 || TUNE_24K)
306
307 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
308 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
309
310 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
311 directly accessible, while the command-line options select
312 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
313 in use. */
314 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
315 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
316
317 /* False if SC acts as a memory barrier with respect to itself,
318 otherwise a SYNC will be emitted after SC for atomic operations
319 that require ordering between the SC and following loads and
320 stores. It does not tell anything about ordering of loads and
321 stores prior to and following the SC, only about the SC itself and
322 those loads and stores follow it. */
323 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
324
325 /* Define preprocessor macros for the -march and -mtune options.
326 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
327 processor. If INFO's canonical name is "foo", define PREFIX to
328 be "foo", and define an additional macro PREFIX_FOO. */
329 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
330 do \
331 { \
332 char *macro, *p; \
333 \
334 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
335 for (p = macro; *p != 0; p++) \
336 if (*p == '+') \
337 *p = 'P'; \
338 else \
339 *p = TOUPPER (*p); \
340 \
341 builtin_define (macro); \
342 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
343 free (macro); \
344 } \
345 while (0)
346
347 /* Target CPU builtins. */
348 #define TARGET_CPU_CPP_BUILTINS() \
349 do \
350 { \
351 builtin_assert ("machine=mips"); \
352 builtin_assert ("cpu=mips"); \
353 builtin_define ("__mips__"); \
354 builtin_define ("_mips"); \
355 \
356 /* We do this here because __mips is defined below and so we \
357 can't use builtin_define_std. We don't ever want to define \
358 "mips" for VxWorks because some of the VxWorks headers \
359 construct include filenames from a root directory macro, \
360 an architecture macro and a filename, where the architecture \
361 macro expands to 'mips'. If we define 'mips' to 1, the \
362 architecture macro expands to 1 as well. */ \
363 if (!flag_iso && !TARGET_VXWORKS) \
364 builtin_define ("mips"); \
365 \
366 if (TARGET_64BIT) \
367 builtin_define ("__mips64"); \
368 \
369 /* Treat _R3000 and _R4000 like register-size \
370 defines, which is how they've historically \
371 been used. */ \
372 if (TARGET_64BIT) \
373 { \
374 builtin_define_std ("R4000"); \
375 builtin_define ("_R4000"); \
376 } \
377 else \
378 { \
379 builtin_define_std ("R3000"); \
380 builtin_define ("_R3000"); \
381 } \
382 \
383 if (TARGET_FLOAT64) \
384 builtin_define ("__mips_fpr=64"); \
385 else \
386 builtin_define ("__mips_fpr=32"); \
387 \
388 if (mips_base_compression_flags & MASK_MIPS16) \
389 builtin_define ("__mips16"); \
390 \
391 if (TARGET_MIPS3D) \
392 builtin_define ("__mips3d"); \
393 \
394 if (TARGET_SMARTMIPS) \
395 builtin_define ("__mips_smartmips"); \
396 \
397 if (mips_base_compression_flags & MASK_MICROMIPS) \
398 builtin_define ("__mips_micromips"); \
399 \
400 if (TARGET_MCU) \
401 builtin_define ("__mips_mcu"); \
402 \
403 if (TARGET_EVA) \
404 builtin_define ("__mips_eva"); \
405 \
406 if (TARGET_DSP) \
407 { \
408 builtin_define ("__mips_dsp"); \
409 if (TARGET_DSPR2) \
410 { \
411 builtin_define ("__mips_dspr2"); \
412 builtin_define ("__mips_dsp_rev=2"); \
413 } \
414 else \
415 builtin_define ("__mips_dsp_rev=1"); \
416 } \
417 \
418 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
419 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
420 \
421 if (ISA_MIPS1) \
422 { \
423 builtin_define ("__mips=1"); \
424 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
425 } \
426 else if (ISA_MIPS2) \
427 { \
428 builtin_define ("__mips=2"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
430 } \
431 else if (ISA_MIPS3) \
432 { \
433 builtin_define ("__mips=3"); \
434 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
435 } \
436 else if (ISA_MIPS4) \
437 { \
438 builtin_define ("__mips=4"); \
439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
440 } \
441 else if (ISA_MIPS32) \
442 { \
443 builtin_define ("__mips=32"); \
444 builtin_define ("__mips_isa_rev=1"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
446 } \
447 else if (ISA_MIPS32R2) \
448 { \
449 builtin_define ("__mips=32"); \
450 builtin_define ("__mips_isa_rev=2"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
452 } \
453 else if (ISA_MIPS64) \
454 { \
455 builtin_define ("__mips=64"); \
456 builtin_define ("__mips_isa_rev=1"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
458 } \
459 else if (ISA_MIPS64R2) \
460 { \
461 builtin_define ("__mips=64"); \
462 builtin_define ("__mips_isa_rev=2"); \
463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
464 } \
465 \
466 switch (mips_abi) \
467 { \
468 case ABI_32: \
469 builtin_define ("_ABIO32=1"); \
470 builtin_define ("_MIPS_SIM=_ABIO32"); \
471 break; \
472 \
473 case ABI_N32: \
474 builtin_define ("_ABIN32=2"); \
475 builtin_define ("_MIPS_SIM=_ABIN32"); \
476 break; \
477 \
478 case ABI_64: \
479 builtin_define ("_ABI64=3"); \
480 builtin_define ("_MIPS_SIM=_ABI64"); \
481 break; \
482 \
483 case ABI_O64: \
484 builtin_define ("_ABIO64=4"); \
485 builtin_define ("_MIPS_SIM=_ABIO64"); \
486 break; \
487 } \
488 \
489 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
490 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
491 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
492 builtin_define_with_int_value ("_MIPS_FPSET", \
493 32 / MAX_FPRS_PER_FMT); \
494 \
495 /* These defines reflect the ABI in use, not whether the \
496 FPU is directly accessible. */ \
497 if (TARGET_NO_FLOAT) \
498 builtin_define ("__mips_no_float"); \
499 else if (TARGET_HARD_FLOAT_ABI) \
500 builtin_define ("__mips_hard_float"); \
501 else \
502 builtin_define ("__mips_soft_float"); \
503 \
504 if (TARGET_SINGLE_FLOAT) \
505 builtin_define ("__mips_single_float"); \
506 \
507 if (TARGET_PAIRED_SINGLE_FLOAT) \
508 builtin_define ("__mips_paired_single_float"); \
509 \
510 if (TARGET_BIG_ENDIAN) \
511 { \
512 builtin_define_std ("MIPSEB"); \
513 builtin_define ("_MIPSEB"); \
514 } \
515 else \
516 { \
517 builtin_define_std ("MIPSEL"); \
518 builtin_define ("_MIPSEL"); \
519 } \
520 \
521 /* Whether calls should go through $25. The separate __PIC__ \
522 macro indicates whether abicalls code might use a GOT. */ \
523 if (TARGET_ABICALLS) \
524 builtin_define ("__mips_abicalls"); \
525 \
526 /* Whether Loongson vector modes are enabled. */ \
527 if (TARGET_LOONGSON_VECTORS) \
528 builtin_define ("__mips_loongson_vector_rev"); \
529 \
530 /* Historical Octeon macro. */ \
531 if (TARGET_OCTEON) \
532 builtin_define ("__OCTEON__"); \
533 \
534 if (TARGET_SYNCI) \
535 builtin_define ("__mips_synci"); \
536 \
537 /* Macros dependent on the C dialect. */ \
538 if (preprocessing_asm_p ()) \
539 { \
540 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
541 builtin_define ("_LANGUAGE_ASSEMBLY"); \
542 } \
543 else if (c_dialect_cxx ()) \
544 { \
545 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
546 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
547 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
548 } \
549 else \
550 { \
551 builtin_define_std ("LANGUAGE_C"); \
552 builtin_define ("_LANGUAGE_C"); \
553 } \
554 if (c_dialect_objc ()) \
555 { \
556 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
557 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
558 /* Bizarre, but retained for backwards compatibility. */ \
559 builtin_define_std ("LANGUAGE_C"); \
560 builtin_define ("_LANGUAGE_C"); \
561 } \
562 \
563 if (mips_abi == ABI_EABI) \
564 builtin_define ("__mips_eabi"); \
565 \
566 if (TARGET_CACHE_BUILTIN) \
567 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
568 } \
569 while (0)
570
571 /* Default target_flags if no switches are specified */
572
573 #ifndef TARGET_DEFAULT
574 #define TARGET_DEFAULT 0
575 #endif
576
577 #ifndef TARGET_CPU_DEFAULT
578 #define TARGET_CPU_DEFAULT 0
579 #endif
580
581 #ifndef TARGET_ENDIAN_DEFAULT
582 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
583 #endif
584
585 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
586 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
587 #endif
588
589 #ifdef IN_LIBGCC2
590 #undef TARGET_64BIT
591 /* Make this compile time constant for libgcc2 */
592 #ifdef __mips64
593 #define TARGET_64BIT 1
594 #else
595 #define TARGET_64BIT 0
596 #endif
597 #endif /* IN_LIBGCC2 */
598
599 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
600 when compiled with hardware floating point. This is because MIPS16
601 code cannot save and restore the floating-point registers, which is
602 important if in a mixed MIPS16/non-MIPS16 environment. */
603
604 #ifdef IN_LIBGCC2
605 #if __mips_hard_float
606 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
607 #endif
608 #endif /* IN_LIBGCC2 */
609
610 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
611
612 #ifndef MULTILIB_ENDIAN_DEFAULT
613 #if TARGET_ENDIAN_DEFAULT == 0
614 #define MULTILIB_ENDIAN_DEFAULT "EL"
615 #else
616 #define MULTILIB_ENDIAN_DEFAULT "EB"
617 #endif
618 #endif
619
620 #ifndef MULTILIB_ISA_DEFAULT
621 #if MIPS_ISA_DEFAULT == 1
622 #define MULTILIB_ISA_DEFAULT "mips1"
623 #elif MIPS_ISA_DEFAULT == 2
624 #define MULTILIB_ISA_DEFAULT "mips2"
625 #elif MIPS_ISA_DEFAULT == 3
626 #define MULTILIB_ISA_DEFAULT "mips3"
627 #elif MIPS_ISA_DEFAULT == 4
628 #define MULTILIB_ISA_DEFAULT "mips4"
629 #elif MIPS_ISA_DEFAULT == 32
630 #define MULTILIB_ISA_DEFAULT "mips32"
631 #elif MIPS_ISA_DEFAULT == 33
632 #define MULTILIB_ISA_DEFAULT "mips32r2"
633 #elif MIPS_ISA_DEFAULT == 64
634 #define MULTILIB_ISA_DEFAULT "mips64"
635 #elif MIPS_ISA_DEFAULT == 65
636 #define MULTILIB_ISA_DEFAULT "mips64r2"
637 #else
638 #define MULTILIB_ISA_DEFAULT "mips1"
639 #endif
640 #endif
641
642 #ifndef MIPS_ABI_DEFAULT
643 #define MIPS_ABI_DEFAULT ABI_32
644 #endif
645
646 /* Use the most portable ABI flag for the ASM specs. */
647
648 #if MIPS_ABI_DEFAULT == ABI_32
649 #define MULTILIB_ABI_DEFAULT "mabi=32"
650 #elif MIPS_ABI_DEFAULT == ABI_O64
651 #define MULTILIB_ABI_DEFAULT "mabi=o64"
652 #elif MIPS_ABI_DEFAULT == ABI_N32
653 #define MULTILIB_ABI_DEFAULT "mabi=n32"
654 #elif MIPS_ABI_DEFAULT == ABI_64
655 #define MULTILIB_ABI_DEFAULT "mabi=64"
656 #elif MIPS_ABI_DEFAULT == ABI_EABI
657 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
658 #endif
659
660 #ifndef MULTILIB_DEFAULTS
661 #define MULTILIB_DEFAULTS \
662 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
663 #endif
664
665 /* We must pass -EL to the linker by default for little endian embedded
666 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
667 linker will default to using big-endian output files. The OUTPUT_FORMAT
668 line must be in the linker script, otherwise -EB/-EL will not work. */
669
670 #ifndef ENDIAN_SPEC
671 #if TARGET_ENDIAN_DEFAULT == 0
672 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
673 #else
674 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
675 #endif
676 #endif
677
678 /* A spec condition that matches all non-mips16 -mips arguments. */
679
680 #define MIPS_ISA_LEVEL_OPTION_SPEC \
681 "mips1|mips2|mips3|mips4|mips32*|mips64*"
682
683 /* A spec condition that matches all non-mips16 architecture arguments. */
684
685 #define MIPS_ARCH_OPTION_SPEC \
686 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
687
688 /* A spec that infers a -mips argument from an -march argument,
689 or injects the default if no architecture is specified. */
690
691 #define MIPS_ISA_LEVEL_SPEC \
692 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
693 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
694 %{march=mips2|march=r6000:-mips2} \
695 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
696 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
697 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
698 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
699 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
700 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
701 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
702 |march=xlr|march=loongson3a: -mips64} \
703 %{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
704 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
705
706 /* A spec that infers a -mhard-float or -msoft-float setting from an
707 -march argument. Note that soft-float and hard-float code are not
708 link-compatible. */
709
710 #define MIPS_ARCH_FLOAT_SPEC \
711 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
712 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
713 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
714 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
715 march=*: -mhard-float}"
716
717 /* A spec condition that matches 32-bit options. It only works if
718 MIPS_ISA_LEVEL_SPEC has been applied. */
719
720 #define MIPS_32BIT_OPTION_SPEC \
721 "mips1|mips2|mips32*|mgp32"
722
723 /* Infer a -msynci setting from a -mips argument, on the assumption that
724 -msynci is desired where possible. */
725 #define MIPS_ISA_SYNCI_SPEC \
726 "%{msynci|mno-synci:;:%{mips32r2|mips64r2:-msynci;:-mno-synci}}"
727
728 #if (MIPS_ABI_DEFAULT == ABI_O64 \
729 || MIPS_ABI_DEFAULT == ABI_N32 \
730 || MIPS_ABI_DEFAULT == ABI_64)
731 #define OPT_ARCH64 "mabi=32|mgp32:;"
732 #define OPT_ARCH32 "mabi=32|mgp32"
733 #else
734 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
735 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
736 #endif
737
738 /* Support for a compile-time default CPU, et cetera. The rules are:
739 --with-arch is ignored if -march is specified or a -mips is specified
740 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
741 --with-tune is ignored if -mtune is specified; likewise
742 --with-tune-32 and --with-tune-64.
743 --with-abi is ignored if -mabi is specified.
744 --with-float is ignored if -mhard-float or -msoft-float are
745 specified.
746 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
747 specified. */
748 #define OPTION_DEFAULT_SPECS \
749 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
750 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
751 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
752 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
753 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
754 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
755 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
756 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
757 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
758 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
759 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
760 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
761
762 /* A spec that infers the -mdsp setting from an -march argument. */
763 #define BASE_DRIVER_SELF_SPECS \
764 "%{!mno-dsp: \
765 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
766 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
767
768 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
769
770 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
771 && ISA_HAS_COND_TRAP)
772
773 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
774
775 /* True if the ABI can only work with 64-bit integer registers. We
776 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
777 otherwise floating-point registers must also be 64-bit. */
778 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
779
780 /* Likewise for 32-bit regs. */
781 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
782
783 /* True if the file format uses 64-bit symbols. At present, this is
784 only true for n64, which uses 64-bit ELF. */
785 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
786
787 /* True if symbols are 64 bits wide. This is usually determined by
788 the ABI's file format, but it can be overridden by -msym32. Note that
789 overriding the size with -msym32 changes the ABI of relocatable objects,
790 although it doesn't change the ABI of a fully-linked object. */
791 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
792 && Pmode == DImode \
793 && !TARGET_SYM32)
794
795 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
796 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
797 || ISA_MIPS4 \
798 || ISA_MIPS64 \
799 || ISA_MIPS64R2)
800
801 /* ISA has branch likely instructions (e.g. mips2). */
802 /* Disable branchlikely for tx39 until compare rewrite. They haven't
803 been generated up to this point. */
804 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
805
806 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
807 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
808 || TARGET_MIPS5400 \
809 || TARGET_MIPS5500 \
810 || TARGET_MIPS5900 \
811 || TARGET_MIPS7000 \
812 || TARGET_MIPS9000 \
813 || TARGET_MAD \
814 || ISA_MIPS32 \
815 || ISA_MIPS32R2 \
816 || ISA_MIPS64 \
817 || ISA_MIPS64R2) \
818 && !TARGET_MIPS16)
819
820 /* ISA has a three-operand multiplication instruction. */
821 #define ISA_HAS_DMUL3 (TARGET_64BIT \
822 && TARGET_OCTEON \
823 && !TARGET_MIPS16)
824
825 /* ISA supports instructions DMULT and DMULTU. */
826 #define ISA_HAS_DMULT (TARGET_64BIT && !TARGET_MIPS5900)
827
828 /* ISA supports instructions MULT and MULTU.
829 This is always true, but the macro is needed for ISA_HAS_<D>MULT
830 in mips.md. */
831 #define ISA_HAS_MULT (1)
832
833 /* ISA supports instructions DDIV and DDIVU. */
834 #define ISA_HAS_DDIV (TARGET_64BIT && !TARGET_MIPS5900)
835
836 /* ISA supports instructions DIV and DIVU.
837 This is always true, but the macro is needed for ISA_HAS_<D>DIV
838 in mips.md. */
839 #define ISA_HAS_DIV (1)
840
841 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
842 || TARGET_LOONGSON_3A) \
843 && !TARGET_MIPS16)
844
845 /* ISA has the floating-point conditional move instructions introduced
846 in mips4. */
847 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
848 || ISA_MIPS32 \
849 || ISA_MIPS32R2 \
850 || ISA_MIPS64 \
851 || ISA_MIPS64R2) \
852 && !TARGET_MIPS5500 \
853 && !TARGET_MIPS16)
854
855 /* ISA has the integer conditional move instructions introduced in mips4 and
856 ST Loongson 2E/2F. */
857 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
858 || TARGET_MIPS5900 \
859 || TARGET_LOONGSON_2EF)
860
861 /* ISA has LDC1 and SDC1. */
862 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
863
864 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
865 branch on CC, and move (both FP and non-FP) on CC. */
866 #define ISA_HAS_8CC (ISA_MIPS4 \
867 || ISA_MIPS32 \
868 || ISA_MIPS32R2 \
869 || ISA_MIPS64 \
870 || ISA_MIPS64R2)
871
872 /* This is a catch all for other mips4 instructions: indexed load, the
873 FP madd and msub instructions, and the FP recip and recip sqrt
874 instructions. */
875 #define ISA_HAS_FP4 ((ISA_MIPS4 \
876 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
877 || ISA_MIPS64 \
878 || ISA_MIPS64R2) \
879 && !TARGET_MIPS16)
880
881 /* ISA has paired-single instructions. */
882 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
883
884 /* ISA has conditional trap instructions. */
885 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
886 && !TARGET_MIPS16)
887
888 /* ISA has integer multiply-accumulate instructions, madd and msub. */
889 #define ISA_HAS_MADD_MSUB (ISA_MIPS32 \
890 || ISA_MIPS32R2 \
891 || ISA_MIPS64 \
892 || ISA_MIPS64R2)
893
894 /* Integer multiply-accumulate instructions should be generated. */
895 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
896
897 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
898 #define ISA_HAS_FP_MADD4_MSUB4 (ISA_HAS_FP4 \
899 || (ISA_MIPS32R2 && !TARGET_MIPS16))
900
901 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
902 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
903
904 /* ISA has floating-point nmadd and nmsub instructions
905 'd = -((a * b) [+-] c)'. */
906 #define ISA_HAS_NMADD4_NMSUB4 (ISA_HAS_FP4 \
907 || (ISA_MIPS32R2 && !TARGET_MIPS16))
908
909 /* ISA has floating-point nmadd and nmsub instructions
910 'c = -((a * b) [+-] c)'. */
911 #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF
912
913 /* ISA has count leading zeroes/ones instruction (not implemented). */
914 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
915 || ISA_MIPS32R2 \
916 || ISA_MIPS64 \
917 || ISA_MIPS64R2) \
918 && !TARGET_MIPS16)
919
920 /* ISA has three operand multiply instructions that put
921 the high part in an accumulator: mulhi or mulhiu. */
922 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
923 || TARGET_MIPS5500 \
924 || TARGET_SR71K) \
925 && !TARGET_MIPS16)
926
927 /* ISA has three operand multiply instructions that negate the
928 result and put the result in an accumulator. */
929 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
930 || TARGET_MIPS5500 \
931 || TARGET_SR71K) \
932 && !TARGET_MIPS16)
933
934 /* ISA has three operand multiply instructions that subtract the
935 result from a 4th operand and put the result in an accumulator. */
936 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
937 || TARGET_MIPS5500 \
938 || TARGET_SR71K) \
939 && !TARGET_MIPS16)
940
941 /* ISA has three operand multiply instructions that add the result
942 to a 4th operand and put the result in an accumulator. */
943 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
944 || TARGET_MIPS4130 \
945 || TARGET_MIPS5400 \
946 || TARGET_MIPS5500 \
947 || TARGET_SR71K) \
948 && !TARGET_MIPS16)
949
950 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
951 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
952 || TARGET_MIPS4130) \
953 && !TARGET_MIPS16)
954
955 /* ISA has the "ror" (rotate right) instructions. */
956 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
957 || ISA_MIPS64R2 \
958 || TARGET_MIPS5400 \
959 || TARGET_MIPS5500 \
960 || TARGET_SR71K \
961 || TARGET_SMARTMIPS) \
962 && !TARGET_MIPS16)
963
964 /* ISA has data prefetch instructions. This controls use of 'pref'. */
965 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
966 || TARGET_LOONGSON_2EF \
967 || TARGET_MIPS5900 \
968 || ISA_MIPS32 \
969 || ISA_MIPS32R2 \
970 || ISA_MIPS64 \
971 || ISA_MIPS64R2) \
972 && !TARGET_MIPS16)
973
974 /* ISA has data indexed prefetch instructions. This controls use of
975 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
976 (prefx is a cop1x instruction, so can only be used if FP is
977 enabled.) */
978 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
979 || ISA_MIPS32R2 \
980 || ISA_MIPS64 \
981 || ISA_MIPS64R2) \
982 && !TARGET_MIPS16)
983
984 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
985 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
986 also requires TARGET_DOUBLE_FLOAT. */
987 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
988
989 /* ISA includes the MIPS32r2 seb and seh instructions. */
990 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
991 || ISA_MIPS64R2) \
992 && !TARGET_MIPS16)
993
994 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
995 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
996 || ISA_MIPS64R2) \
997 && !TARGET_MIPS16)
998
999 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1000 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
1001 && (ISA_MIPS32R2 \
1002 || ISA_MIPS64R2))
1003
1004 /* ISA has lwxs instruction (load w/scaled index address. */
1005 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1006 && !TARGET_MIPS16)
1007
1008 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1009 #define ISA_HAS_LBX (TARGET_OCTEON2)
1010 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1011 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1012 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1013 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1014 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1015 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1016 && TARGET_64BIT)
1017
1018 /* The DSP ASE is available. */
1019 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1020
1021 /* Revision 2 of the DSP ASE is available. */
1022 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1023
1024 /* True if the result of a load is not available to the next instruction.
1025 A nop will then be needed between instructions like "lw $4,..."
1026 and "addiu $4,$4,1". */
1027 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1028 && !TARGET_MIPS3900 \
1029 && !TARGET_MIPS5900 \
1030 && !TARGET_MIPS16 \
1031 && !TARGET_MICROMIPS)
1032
1033 /* Likewise mtc1 and mfc1. */
1034 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1035 && !TARGET_MIPS5900 \
1036 && !TARGET_LOONGSON_2EF)
1037
1038 /* Likewise floating-point comparisons. */
1039 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1040 && !TARGET_MIPS5900 \
1041 && !TARGET_LOONGSON_2EF)
1042
1043 /* True if mflo and mfhi can be immediately followed by instructions
1044 which write to the HI and LO registers.
1045
1046 According to MIPS specifications, MIPS ISAs I, II, and III need
1047 (at least) two instructions between the reads of HI/LO and
1048 instructions which write them, and later ISAs do not. Contradicting
1049 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1050 the UM for the NEC Vr5000) document needing the instructions between
1051 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1052 MIPS64 and later ISAs to have the interlocks, plus any specific
1053 earlier-ISA CPUs for which CPU documentation declares that the
1054 instructions are really interlocked. */
1055 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1056 || ISA_MIPS32R2 \
1057 || ISA_MIPS64 \
1058 || ISA_MIPS64R2 \
1059 || TARGET_MIPS5500 \
1060 || TARGET_MIPS5900 \
1061 || TARGET_LOONGSON_2EF)
1062
1063 /* ISA includes synci, jr.hb and jalr.hb. */
1064 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1065 || ISA_MIPS64R2) \
1066 && !TARGET_MIPS16)
1067
1068 /* ISA includes sync. */
1069 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1070 #define GENERATE_SYNC \
1071 (target_flags_explicit & MASK_LLSC \
1072 ? TARGET_LLSC && !TARGET_MIPS16 \
1073 : ISA_HAS_SYNC)
1074
1075 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1076 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1077 instructions. */
1078 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1079 #define GENERATE_LL_SC \
1080 (target_flags_explicit & MASK_LLSC \
1081 ? TARGET_LLSC && !TARGET_MIPS16 \
1082 : ISA_HAS_LL_SC)
1083
1084 #define ISA_HAS_SWAP (TARGET_XLP)
1085 #define ISA_HAS_LDADD (TARGET_XLP)
1086
1087 /* ISA includes the baddu instruction. */
1088 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1089
1090 /* ISA includes the bbit* instructions. */
1091 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1092
1093 /* ISA includes the cins instruction. */
1094 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1095
1096 /* ISA includes the exts instruction. */
1097 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1098
1099 /* ISA includes the seq and sne instructions. */
1100 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1101
1102 /* ISA includes the pop instruction. */
1103 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1104
1105 /* The CACHE instruction is available in non-MIPS16 code. */
1106 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1107
1108 /* The CACHE instruction is available. */
1109 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1110 \f
1111 /* Tell collect what flags to pass to nm. */
1112 #ifndef NM_FLAGS
1113 #define NM_FLAGS "-Bn"
1114 #endif
1115
1116 \f
1117 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1118 the assembler. It may be overridden by subtargets.
1119
1120 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1121 COFF debugging info. */
1122
1123 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1124 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1125 %{g} %{g0} %{g1} %{g2} %{g3} \
1126 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1127 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1128 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1129 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1130 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1131 #endif
1132
1133 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1134 overridden by subtargets. */
1135
1136 #ifndef SUBTARGET_ASM_SPEC
1137 #define SUBTARGET_ASM_SPEC ""
1138 #endif
1139
1140 #undef ASM_SPEC
1141 #define ASM_SPEC "\
1142 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1143 %{mips32*} %{mips64*} \
1144 %{mips16} %{mno-mips16:-no-mips16} \
1145 %{mmicromips} %{mno-micromips} \
1146 %{mips3d} %{mno-mips3d:-no-mips3d} \
1147 %{mdmx} %{mno-mdmx:-no-mdmx} \
1148 %{mdsp} %{mno-dsp} \
1149 %{mdspr2} %{mno-dspr2} \
1150 %{mmcu} %{mno-mcu} \
1151 %{meva} %{mno-eva} \
1152 %{msmartmips} %{mno-smartmips} \
1153 %{mmt} %{mno-mt} \
1154 %{mfix-vr4120} %{mfix-vr4130} \
1155 %{mfix-24k} \
1156 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1157 %(subtarget_asm_debugging_spec) \
1158 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1159 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1160 %{mfp32} %{mfp64} \
1161 %{mshared} %{mno-shared} \
1162 %{msym32} %{mno-sym32} \
1163 %{mtune=*} \
1164 %(subtarget_asm_spec)"
1165
1166 /* Extra switches sometimes passed to the linker. */
1167
1168 #ifndef LINK_SPEC
1169 #define LINK_SPEC "\
1170 %(endian_spec) \
1171 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1172 %{shared}"
1173 #endif /* LINK_SPEC defined */
1174
1175
1176 /* Specs for the compiler proper */
1177
1178 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1179 overridden by subtargets. */
1180 #ifndef SUBTARGET_CC1_SPEC
1181 #define SUBTARGET_CC1_SPEC ""
1182 #endif
1183
1184 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1185
1186 #undef CC1_SPEC
1187 #define CC1_SPEC "\
1188 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1189 %(subtarget_cc1_spec)"
1190
1191 /* Preprocessor specs. */
1192
1193 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1194 overridden by subtargets. */
1195 #ifndef SUBTARGET_CPP_SPEC
1196 #define SUBTARGET_CPP_SPEC ""
1197 #endif
1198
1199 #define CPP_SPEC "%(subtarget_cpp_spec)"
1200
1201 /* This macro defines names of additional specifications to put in the specs
1202 that can be used in various specifications like CC1_SPEC. Its definition
1203 is an initializer with a subgrouping for each command option.
1204
1205 Each subgrouping contains a string constant, that defines the
1206 specification name, and a string constant that used by the GCC driver
1207 program.
1208
1209 Do not define this macro if it does not need to do anything. */
1210
1211 #define EXTRA_SPECS \
1212 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1213 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1214 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1215 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1216 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1217 { "endian_spec", ENDIAN_SPEC }, \
1218 SUBTARGET_EXTRA_SPECS
1219
1220 #ifndef SUBTARGET_EXTRA_SPECS
1221 #define SUBTARGET_EXTRA_SPECS
1222 #endif
1223 \f
1224 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1225 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1226
1227 #ifndef PREFERRED_DEBUGGING_TYPE
1228 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1229 #endif
1230
1231 /* The size of DWARF addresses should be the same as the size of symbols
1232 in the target file format. They shouldn't depend on things like -msym32,
1233 because many DWARF consumers do not allow the mixture of address sizes
1234 that one would then get from linking -msym32 code with -msym64 code.
1235
1236 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1237 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1238 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1239
1240 /* By default, turn on GDB extensions. */
1241 #define DEFAULT_GDB_EXTENSIONS 1
1242
1243 /* Local compiler-generated symbols must have a prefix that the assembler
1244 understands. By default, this is $, although some targets (e.g.,
1245 NetBSD-ELF) need to override this. */
1246
1247 #ifndef LOCAL_LABEL_PREFIX
1248 #define LOCAL_LABEL_PREFIX "$"
1249 #endif
1250
1251 /* By default on the mips, external symbols do not have an underscore
1252 prepended, but some targets (e.g., NetBSD) require this. */
1253
1254 #ifndef USER_LABEL_PREFIX
1255 #define USER_LABEL_PREFIX ""
1256 #endif
1257
1258 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1259 since the length can run past this up to a continuation point. */
1260 #undef DBX_CONTIN_LENGTH
1261 #define DBX_CONTIN_LENGTH 1500
1262
1263 /* How to renumber registers for dbx and gdb. */
1264 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1265
1266 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1267 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1268
1269 /* The DWARF 2 CFA column which tracks the return address. */
1270 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1271
1272 /* Before the prologue, RA lives in r31. */
1273 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1274
1275 /* Describe how we implement __builtin_eh_return. */
1276 #define EH_RETURN_DATA_REGNO(N) \
1277 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1278
1279 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1280
1281 #define EH_USES(N) mips_eh_uses (N)
1282
1283 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1284 The default for this in 64-bit mode is 8, which causes problems with
1285 SFmode register saves. */
1286 #define DWARF_CIE_DATA_ALIGNMENT -4
1287
1288 /* Correct the offset of automatic variables and arguments. Note that
1289 the MIPS debug format wants all automatic variables and arguments
1290 to be in terms of the virtual frame pointer (stack pointer before
1291 any adjustment in the function), while the MIPS 3.0 linker wants
1292 the frame pointer to be the stack pointer after the initial
1293 adjustment. */
1294
1295 #define DEBUGGER_AUTO_OFFSET(X) \
1296 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1297 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1298 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1299 \f
1300 /* Target machine storage layout */
1301
1302 #define BITS_BIG_ENDIAN 0
1303 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1304 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1305
1306 #define MAX_BITS_PER_WORD 64
1307
1308 /* Width of a word, in units (bytes). */
1309 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1310 #ifndef IN_LIBGCC2
1311 #define MIN_UNITS_PER_WORD 4
1312 #endif
1313
1314 /* For MIPS, width of a floating point register. */
1315 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1316
1317 /* The number of consecutive floating-point registers needed to store the
1318 largest format supported by the FPU. */
1319 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1320
1321 /* The number of consecutive floating-point registers needed to store the
1322 smallest format supported by the FPU. */
1323 #define MIN_FPRS_PER_FMT \
1324 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1325 ? 1 : MAX_FPRS_PER_FMT)
1326
1327 /* The largest size of value that can be held in floating-point
1328 registers and moved with a single instruction. */
1329 #define UNITS_PER_HWFPVALUE \
1330 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1331
1332 /* The largest size of value that can be held in floating-point
1333 registers. */
1334 #define UNITS_PER_FPVALUE \
1335 (TARGET_SOFT_FLOAT_ABI ? 0 \
1336 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1337 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1338
1339 /* The number of bytes in a double. */
1340 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1341
1342 /* Set the sizes of the core types. */
1343 #define SHORT_TYPE_SIZE 16
1344 #define INT_TYPE_SIZE 32
1345 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1346 #define LONG_LONG_TYPE_SIZE 64
1347
1348 #define FLOAT_TYPE_SIZE 32
1349 #define DOUBLE_TYPE_SIZE 64
1350 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1351
1352 /* Define the sizes of fixed-point types. */
1353 #define SHORT_FRACT_TYPE_SIZE 8
1354 #define FRACT_TYPE_SIZE 16
1355 #define LONG_FRACT_TYPE_SIZE 32
1356 #define LONG_LONG_FRACT_TYPE_SIZE 64
1357
1358 #define SHORT_ACCUM_TYPE_SIZE 16
1359 #define ACCUM_TYPE_SIZE 32
1360 #define LONG_ACCUM_TYPE_SIZE 64
1361 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1362 doesn't support 128-bit integers for MIPS32 currently. */
1363 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1364
1365 /* long double is not a fixed mode, but the idea is that, if we
1366 support long double, we also want a 128-bit integer type. */
1367 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1368
1369 #ifdef IN_LIBGCC2
1370 #if ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1371 || (defined _ABI64 && _MIPS_SIM == _ABI64))
1372 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1373 # else
1374 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1375 # endif
1376 #endif
1377
1378 /* Width in bits of a pointer. */
1379 #ifndef POINTER_SIZE
1380 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1381 #endif
1382
1383 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1384 #define PARM_BOUNDARY BITS_PER_WORD
1385
1386 /* Allocation boundary (in *bits*) for the code of a function. */
1387 #define FUNCTION_BOUNDARY 32
1388
1389 /* Alignment of field after `int : 0' in a structure. */
1390 #define EMPTY_FIELD_BOUNDARY 32
1391
1392 /* Every structure's size must be a multiple of this. */
1393 /* 8 is observed right on a DECstation and on riscos 4.02. */
1394 #define STRUCTURE_SIZE_BOUNDARY 8
1395
1396 /* There is no point aligning anything to a rounder boundary than this. */
1397 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1398
1399 /* All accesses must be aligned. */
1400 #define STRICT_ALIGNMENT 1
1401
1402 /* Define this if you wish to imitate the way many other C compilers
1403 handle alignment of bitfields and the structures that contain
1404 them.
1405
1406 The behavior is that the type written for a bit-field (`int',
1407 `short', or other integer type) imposes an alignment for the
1408 entire structure, as if the structure really did contain an
1409 ordinary field of that type. In addition, the bit-field is placed
1410 within the structure so that it would fit within such a field,
1411 not crossing a boundary for it.
1412
1413 Thus, on most machines, a bit-field whose type is written as `int'
1414 would not cross a four-byte boundary, and would force four-byte
1415 alignment for the whole structure. (The alignment used may not
1416 be four bytes; it is controlled by the other alignment
1417 parameters.)
1418
1419 If the macro is defined, its definition should be a C expression;
1420 a nonzero value for the expression enables this behavior. */
1421
1422 #define PCC_BITFIELD_TYPE_MATTERS 1
1423
1424 /* If defined, a C expression to compute the alignment given to a
1425 constant that is being placed in memory. CONSTANT is the constant
1426 and ALIGN is the alignment that the object would ordinarily have.
1427 The value of this macro is used instead of that alignment to align
1428 the object.
1429
1430 If this macro is not defined, then ALIGN is used.
1431
1432 The typical use of this macro is to increase alignment for string
1433 constants to be word aligned so that `strcpy' calls that copy
1434 constants can be done inline. */
1435
1436 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1437 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1438 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1439
1440 /* If defined, a C expression to compute the alignment for a static
1441 variable. TYPE is the data type, and ALIGN is the alignment that
1442 the object would ordinarily have. The value of this macro is used
1443 instead of that alignment to align the object.
1444
1445 If this macro is not defined, then ALIGN is used.
1446
1447 One use of this macro is to increase alignment of medium-size
1448 data to make it all fit in fewer cache lines. Another is to
1449 cause character arrays to be word-aligned so that `strcpy' calls
1450 that copy constants to character arrays can be done inline. */
1451
1452 #undef DATA_ALIGNMENT
1453 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1454 ((((ALIGN) < BITS_PER_WORD) \
1455 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1456 || TREE_CODE (TYPE) == UNION_TYPE \
1457 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1458
1459 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1460 character arrays to be word-aligned so that `strcpy' calls that copy
1461 constants to character arrays can be done inline, and 'strcmp' can be
1462 optimised to use word loads. */
1463 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1464 DATA_ALIGNMENT (TYPE, ALIGN)
1465
1466 #define PAD_VARARGS_DOWN \
1467 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1468
1469 /* Define if operations between registers always perform the operation
1470 on the full register even if a narrower mode is specified. */
1471 #define WORD_REGISTER_OPERATIONS
1472
1473 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1474 moves. All other references are zero extended. */
1475 #define LOAD_EXTEND_OP(MODE) \
1476 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1477 ? SIGN_EXTEND : ZERO_EXTEND)
1478
1479 /* Define this macro if it is advisable to hold scalars in registers
1480 in a wider mode than that declared by the program. In such cases,
1481 the value is constrained to be within the bounds of the declared
1482 type, but kept valid in the wider mode. The signedness of the
1483 extension may differ from that of the type. */
1484
1485 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1486 if (GET_MODE_CLASS (MODE) == MODE_INT \
1487 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1488 { \
1489 if ((MODE) == SImode) \
1490 (UNSIGNEDP) = 0; \
1491 (MODE) = Pmode; \
1492 }
1493
1494 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1495 Extensions of pointers to word_mode must be signed. */
1496 #define POINTERS_EXTEND_UNSIGNED false
1497
1498 /* Define if loading short immediate values into registers sign extends. */
1499 #define SHORT_IMMEDIATES_SIGN_EXTEND
1500
1501 /* The [d]clz instructions have the natural values at 0. */
1502
1503 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1504 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1505 \f
1506 /* Standard register usage. */
1507
1508 /* Number of hardware registers. We have:
1509
1510 - 32 integer registers
1511 - 32 floating point registers
1512 - 8 condition code registers
1513 - 2 accumulator registers (hi and lo)
1514 - 32 registers each for coprocessors 0, 2 and 3
1515 - 4 fake registers:
1516 - ARG_POINTER_REGNUM
1517 - FRAME_POINTER_REGNUM
1518 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1519 - CPRESTORE_SLOT_REGNUM
1520 - 2 dummy entries that were used at various times in the past.
1521 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1522 - 6 DSP control registers */
1523
1524 #define FIRST_PSEUDO_REGISTER 188
1525
1526 /* By default, fix the kernel registers ($26 and $27), the global
1527 pointer ($28) and the stack pointer ($29). This can change
1528 depending on the command-line options.
1529
1530 Regarding coprocessor registers: without evidence to the contrary,
1531 it's best to assume that each coprocessor register has a unique
1532 use. This can be overridden, in, e.g., mips_option_override or
1533 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1534 inappropriate for a particular target. */
1535
1536 #define FIXED_REGISTERS \
1537 { \
1538 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1539 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1540 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1541 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1542 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1543 /* COP0 registers */ \
1544 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1545 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1546 /* COP2 registers */ \
1547 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1548 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1549 /* COP3 registers */ \
1550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1551 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1552 /* 6 DSP accumulator registers & 6 control registers */ \
1553 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1554 }
1555
1556
1557 /* Set up this array for o32 by default.
1558
1559 Note that we don't mark $31 as a call-clobbered register. The idea is
1560 that it's really the call instructions themselves which clobber $31.
1561 We don't care what the called function does with it afterwards.
1562
1563 This approach makes it easier to implement sibcalls. Unlike normal
1564 calls, sibcalls don't clobber $31, so the register reaches the
1565 called function in tact. EPILOGUE_USES says that $31 is useful
1566 to the called function. */
1567
1568 #define CALL_USED_REGISTERS \
1569 { \
1570 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1571 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1573 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1575 /* COP0 registers */ \
1576 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1578 /* COP2 registers */ \
1579 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1580 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1581 /* COP3 registers */ \
1582 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1583 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1584 /* 6 DSP accumulator registers & 6 control registers */ \
1585 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1586 }
1587
1588
1589 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1590
1591 #define CALL_REALLY_USED_REGISTERS \
1592 { /* General registers. */ \
1593 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1594 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1595 /* Floating-point registers. */ \
1596 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1597 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1598 /* Others. */ \
1599 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1600 /* COP0 registers */ \
1601 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1602 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1603 /* COP2 registers */ \
1604 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1605 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1606 /* COP3 registers */ \
1607 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1608 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1609 /* 6 DSP accumulator registers & 6 control registers */ \
1610 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1611 }
1612
1613 /* Internal macros to classify a register number as to whether it's a
1614 general purpose register, a floating point register, a
1615 multiply/divide register, or a status register. */
1616
1617 #define GP_REG_FIRST 0
1618 #define GP_REG_LAST 31
1619 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1620 #define GP_DBX_FIRST 0
1621 #define K0_REG_NUM (GP_REG_FIRST + 26)
1622 #define K1_REG_NUM (GP_REG_FIRST + 27)
1623 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1624
1625 #define FP_REG_FIRST 32
1626 #define FP_REG_LAST 63
1627 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1628 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1629
1630 #define MD_REG_FIRST 64
1631 #define MD_REG_LAST 65
1632 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1633 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1634
1635 /* The DWARF 2 CFA column which tracks the return address from a
1636 signal handler context. This means that to maintain backwards
1637 compatibility, no hard register can be assigned this column if it
1638 would need to be handled by the DWARF unwinder. */
1639 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1640
1641 #define ST_REG_FIRST 67
1642 #define ST_REG_LAST 74
1643 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1644
1645
1646 /* FIXME: renumber. */
1647 #define COP0_REG_FIRST 80
1648 #define COP0_REG_LAST 111
1649 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1650
1651 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1652 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1653 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1654
1655 #define COP2_REG_FIRST 112
1656 #define COP2_REG_LAST 143
1657 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1658
1659 #define COP3_REG_FIRST 144
1660 #define COP3_REG_LAST 175
1661 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1662
1663 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1664 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1665 #define ALL_COP_REG_LAST COP3_REG_LAST
1666 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1667
1668 #define DSP_ACC_REG_FIRST 176
1669 #define DSP_ACC_REG_LAST 181
1670 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1671
1672 #define AT_REGNUM (GP_REG_FIRST + 1)
1673 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1674 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1675
1676 /* A few bitfield locations for the coprocessor registers. */
1677 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1678 the cause register for the EIC interrupt mode. */
1679 #define CAUSE_IPL 10
1680 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1681 #define SR_IPL 10
1682 /* Exception Level is at bit 1 of the status register. */
1683 #define SR_EXL 1
1684 /* Interrupt Enable is at bit 0 of the status register. */
1685 #define SR_IE 0
1686
1687 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1688 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1689 should be used instead. */
1690 #define FPSW_REGNUM ST_REG_FIRST
1691
1692 #define GP_REG_P(REGNO) \
1693 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1694 #define M16_REG_P(REGNO) \
1695 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1696 #define M16STORE_REG_P(REGNO) \
1697 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1698 #define FP_REG_P(REGNO) \
1699 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1700 #define MD_REG_P(REGNO) \
1701 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1702 #define ST_REG_P(REGNO) \
1703 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1704 #define COP0_REG_P(REGNO) \
1705 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1706 #define COP2_REG_P(REGNO) \
1707 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1708 #define COP3_REG_P(REGNO) \
1709 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1710 #define ALL_COP_REG_P(REGNO) \
1711 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1712 /* Test if REGNO is one of the 6 new DSP accumulators. */
1713 #define DSP_ACC_REG_P(REGNO) \
1714 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1715 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1716 #define ACC_REG_P(REGNO) \
1717 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1718
1719 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1720
1721 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1722 to initialize the mips16 gp pseudo register. */
1723 #define CONST_GP_P(X) \
1724 (GET_CODE (X) == CONST \
1725 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1726 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1727
1728 /* Return coprocessor number from register number. */
1729
1730 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1731 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1732 : COP3_REG_P (REGNO) ? '3' : '?')
1733
1734
1735 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1736
1737 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1738 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1739
1740 #define MODES_TIEABLE_P mips_modes_tieable_p
1741
1742 /* Register to use for pushing function arguments. */
1743 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1744
1745 /* These two registers don't really exist: they get eliminated to either
1746 the stack or hard frame pointer. */
1747 #define ARG_POINTER_REGNUM 77
1748 #define FRAME_POINTER_REGNUM 78
1749
1750 /* $30 is not available on the mips16, so we use $17 as the frame
1751 pointer. */
1752 #define HARD_FRAME_POINTER_REGNUM \
1753 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1754
1755 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1756 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1757
1758 /* Register in which static-chain is passed to a function. */
1759 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1760
1761 /* Registers used as temporaries in prologue/epilogue code:
1762
1763 - If a MIPS16 PIC function needs access to _gp, it first loads
1764 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1765
1766 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1767 register. The register must not conflict with MIPS16_PIC_TEMP.
1768
1769 - If we aren't generating MIPS16 code, the prologue can also use
1770 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1771
1772 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1773 register.
1774
1775 If we're generating MIPS16 code, these registers must come from the
1776 core set of 8. The prologue registers mustn't conflict with any
1777 incoming arguments, the static chain pointer, or the frame pointer.
1778 The epilogue temporary mustn't conflict with the return registers,
1779 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1780 or the EH data registers.
1781
1782 If we're generating interrupt handlers, we use K0 as a temporary register
1783 in prologue/epilogue code. */
1784
1785 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1786 #define MIPS_PROLOGUE_TEMP_REGNUM \
1787 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1788 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1789 (TARGET_MIPS16 \
1790 ? (gcc_unreachable (), INVALID_REGNUM) \
1791 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1792 #define MIPS_EPILOGUE_TEMP_REGNUM \
1793 (cfun->machine->interrupt_handler_p \
1794 ? K0_REG_NUM \
1795 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1796
1797 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1798 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1799 #define MIPS_PROLOGUE_TEMP2(MODE) \
1800 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1801 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1802
1803 /* Define this macro if it is as good or better to call a constant
1804 function address than to call an address kept in a register. */
1805 #define NO_FUNCTION_CSE 1
1806
1807 /* The ABI-defined global pointer. Sometimes we use a different
1808 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1809 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1810
1811 /* We normally use $28 as the global pointer. However, when generating
1812 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1813 register instead. They can then avoid saving and restoring $28
1814 and perhaps avoid using a frame at all.
1815
1816 When a leaf function uses something other than $28, mips_expand_prologue
1817 will modify pic_offset_table_rtx in place. Take the register number
1818 from there after reload. */
1819 #define PIC_OFFSET_TABLE_REGNUM \
1820 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1821 \f
1822 /* Define the classes of registers for register constraints in the
1823 machine description. Also define ranges of constants.
1824
1825 One of the classes must always be named ALL_REGS and include all hard regs.
1826 If there is more than one class, another class must be named NO_REGS
1827 and contain no registers.
1828
1829 The name GENERAL_REGS must be the name of a class (or an alias for
1830 another name such as ALL_REGS). This is the class of registers
1831 that is allowed by "g" or "r" in a register constraint.
1832 Also, registers outside this class are allocated only when
1833 instructions express preferences for them.
1834
1835 The classes must be numbered in nondecreasing order; that is,
1836 a larger-numbered class must never be contained completely
1837 in a smaller-numbered class.
1838
1839 For any two classes, it is very desirable that there be another
1840 class that represents their union. */
1841
1842 enum reg_class
1843 {
1844 NO_REGS, /* no registers in set */
1845 M16_REGS, /* mips16 directly accessible registers */
1846 T_REG, /* mips16 T register ($24) */
1847 M16_T_REGS, /* mips16 registers plus T register */
1848 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1849 V1_REG, /* Register $v1 ($3) used for TLS access. */
1850 LEA_REGS, /* Every GPR except $25 */
1851 GR_REGS, /* integer registers */
1852 FP_REGS, /* floating point registers */
1853 MD0_REG, /* first multiply/divide register */
1854 MD1_REG, /* second multiply/divide register */
1855 MD_REGS, /* multiply/divide registers (hi/lo) */
1856 COP0_REGS, /* generic coprocessor classes */
1857 COP2_REGS,
1858 COP3_REGS,
1859 ST_REGS, /* status registers (fp status) */
1860 DSP_ACC_REGS, /* DSP accumulator registers */
1861 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1862 FRAME_REGS, /* $arg and $frame */
1863 GR_AND_MD0_REGS, /* union classes */
1864 GR_AND_MD1_REGS,
1865 GR_AND_MD_REGS,
1866 GR_AND_ACC_REGS,
1867 ALL_REGS, /* all registers */
1868 LIM_REG_CLASSES /* max value + 1 */
1869 };
1870
1871 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1872
1873 #define GENERAL_REGS GR_REGS
1874
1875 /* An initializer containing the names of the register classes as C
1876 string constants. These names are used in writing some of the
1877 debugging dumps. */
1878
1879 #define REG_CLASS_NAMES \
1880 { \
1881 "NO_REGS", \
1882 "M16_REGS", \
1883 "T_REG", \
1884 "M16_T_REGS", \
1885 "PIC_FN_ADDR_REG", \
1886 "V1_REG", \
1887 "LEA_REGS", \
1888 "GR_REGS", \
1889 "FP_REGS", \
1890 "MD0_REG", \
1891 "MD1_REG", \
1892 "MD_REGS", \
1893 /* coprocessor registers */ \
1894 "COP0_REGS", \
1895 "COP2_REGS", \
1896 "COP3_REGS", \
1897 "ST_REGS", \
1898 "DSP_ACC_REGS", \
1899 "ACC_REGS", \
1900 "FRAME_REGS", \
1901 "GR_AND_MD0_REGS", \
1902 "GR_AND_MD1_REGS", \
1903 "GR_AND_MD_REGS", \
1904 "GR_AND_ACC_REGS", \
1905 "ALL_REGS" \
1906 }
1907
1908 /* An initializer containing the contents of the register classes,
1909 as integers which are bit masks. The Nth integer specifies the
1910 contents of class N. The way the integer MASK is interpreted is
1911 that register R is in the class if `MASK & (1 << R)' is 1.
1912
1913 When the machine has more than 32 registers, an integer does not
1914 suffice. Then the integers are replaced by sub-initializers,
1915 braced groupings containing several integers. Each
1916 sub-initializer must be suitable as an initializer for the type
1917 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1918
1919 #define REG_CLASS_CONTENTS \
1920 { \
1921 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1922 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1923 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1924 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1925 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1926 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1927 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1928 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1929 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1930 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1931 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1932 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1933 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1934 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1935 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1936 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1937 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1938 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1939 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1940 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1941 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1942 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1943 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1944 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1945 }
1946
1947
1948 /* A C expression whose value is a register class containing hard
1949 register REGNO. In general there is more that one such class;
1950 choose a class which is "minimal", meaning that no smaller class
1951 also contains the register. */
1952
1953 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1954
1955 /* A macro whose definition is the name of the class to which a
1956 valid base register must belong. A base register is one used in
1957 an address which is the register value plus a displacement. */
1958
1959 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1960
1961 /* A macro whose definition is the name of the class to which a
1962 valid index register must belong. An index register is one used
1963 in an address where its value is either multiplied by a scale
1964 factor or added to another register (as well as added to a
1965 displacement). */
1966
1967 #define INDEX_REG_CLASS NO_REGS
1968
1969 /* We generally want to put call-clobbered registers ahead of
1970 call-saved ones. (IRA expects this.) */
1971
1972 #define REG_ALLOC_ORDER \
1973 { /* Accumulator registers. When GPRs and accumulators have equal \
1974 cost, we generally prefer to use accumulators. For example, \
1975 a division of multiplication result is better allocated to LO, \
1976 so that we put the MFLO at the point of use instead of at the \
1977 point of definition. It's also needed if we're to take advantage \
1978 of the extra accumulators available with -mdspr2. In some cases, \
1979 it can also help to reduce register pressure. */ \
1980 64, 65,176,177,178,179,180,181, \
1981 /* Call-clobbered GPRs. */ \
1982 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1983 24, 25, 31, \
1984 /* The global pointer. This is call-clobbered for o32 and o64 \
1985 abicalls, call-saved for n32 and n64 abicalls, and a program \
1986 invariant otherwise. Putting it between the call-clobbered \
1987 and call-saved registers should cope with all eventualities. */ \
1988 28, \
1989 /* Call-saved GPRs. */ \
1990 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1991 /* GPRs that can never be exposed to the register allocator. */ \
1992 0, 26, 27, 29, \
1993 /* Call-clobbered FPRs. */ \
1994 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1995 48, 49, 50, 51, \
1996 /* FPRs that are usually call-saved. The odd ones are actually \
1997 call-clobbered for n32, but listing them ahead of the even \
1998 registers might encourage the register allocator to fragment \
1999 the available FPR pairs. We need paired FPRs to store long \
2000 doubles, so it isn't clear that using a different order \
2001 for n32 would be a win. */ \
2002 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2003 /* None of the remaining classes have defined call-saved \
2004 registers. */ \
2005 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2006 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2007 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2008 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2009 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2010 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2011 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2012 182,183,184,185,186,187 \
2013 }
2014
2015 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
2016 to be rearranged based on a particular function. On the mips16, we
2017 want to allocate $24 (T_REG) before other registers for
2018 instructions for which it is possible. */
2019
2020 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2021
2022 /* True if VALUE is an unsigned 6-bit number. */
2023
2024 #define UIMM6_OPERAND(VALUE) \
2025 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2026
2027 /* True if VALUE is a signed 10-bit number. */
2028
2029 #define IMM10_OPERAND(VALUE) \
2030 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2031
2032 /* True if VALUE is a signed 16-bit number. */
2033
2034 #define SMALL_OPERAND(VALUE) \
2035 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2036
2037 /* True if VALUE is an unsigned 16-bit number. */
2038
2039 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2040 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2041
2042 /* True if VALUE can be loaded into a register using LUI. */
2043
2044 #define LUI_OPERAND(VALUE) \
2045 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2046 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2047
2048 /* Return a value X with the low 16 bits clear, and such that
2049 VALUE - X is a signed 16-bit value. */
2050
2051 #define CONST_HIGH_PART(VALUE) \
2052 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2053
2054 #define CONST_LOW_PART(VALUE) \
2055 ((VALUE) - CONST_HIGH_PART (VALUE))
2056
2057 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2058 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2059 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2060 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2061
2062 /* The HI and LO registers can only be reloaded via the general
2063 registers. Condition code registers can only be loaded to the
2064 general registers, and from the floating point registers. */
2065
2066 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2067 mips_secondary_reload_class (CLASS, MODE, X, true)
2068 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2069 mips_secondary_reload_class (CLASS, MODE, X, false)
2070
2071 /* Return the maximum number of consecutive registers
2072 needed to represent mode MODE in a register of class CLASS. */
2073
2074 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2075
2076 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2077 mips_cannot_change_mode_class (FROM, TO, CLASS)
2078 \f
2079 /* Stack layout; function entry, exit and calling. */
2080
2081 #define STACK_GROWS_DOWNWARD
2082
2083 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2084
2085 /* Size of the area allocated in the frame to save the GP. */
2086
2087 #define MIPS_GP_SAVE_AREA_SIZE \
2088 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2089
2090 /* The offset of the first local variable from the frame pointer. See
2091 mips_compute_frame_info for details about the frame layout. */
2092
2093 #define STARTING_FRAME_OFFSET \
2094 (FRAME_GROWS_DOWNWARD \
2095 ? 0 \
2096 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2097
2098 #define RETURN_ADDR_RTX mips_return_addr
2099
2100 /* Mask off the MIPS16 ISA bit in unwind addresses.
2101
2102 The reason for this is a little subtle. When unwinding a call,
2103 we are given the call's return address, which on most targets
2104 is the address of the following instruction. However, what we
2105 actually want to find is the EH region for the call itself.
2106 The target-independent unwind code therefore searches for "RA - 1".
2107
2108 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2109 RA - 1 is therefore the real (even-valued) start of the return
2110 instruction. EH region labels are usually odd-valued MIPS16 symbols
2111 too, so a search for an even address within a MIPS16 region would
2112 usually work.
2113
2114 However, there is an exception. If the end of an EH region is also
2115 the end of a function, the end label is allowed to be even. This is
2116 necessary because a following non-MIPS16 function may also need EH
2117 information for its first instruction.
2118
2119 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2120 non-ISA-encoded address. This probably isn't ideal, but it is
2121 the traditional (legacy) behavior. It is therefore only safe
2122 to search MIPS EH regions for an _odd-valued_ address.
2123
2124 Masking off the ISA bit means that the target-independent code
2125 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2126 #define MASK_RETURN_ADDR GEN_INT (-2)
2127
2128
2129 /* Similarly, don't use the least-significant bit to tell pointers to
2130 code from vtable index. */
2131
2132 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2133
2134 /* The eliminations to $17 are only used for mips16 code. See the
2135 definition of HARD_FRAME_POINTER_REGNUM. */
2136
2137 #define ELIMINABLE_REGS \
2138 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2139 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2140 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2141 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2142 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2143 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2144
2145 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2146 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2147
2148 /* Allocate stack space for arguments at the beginning of each function. */
2149 #define ACCUMULATE_OUTGOING_ARGS 1
2150
2151 /* The argument pointer always points to the first argument. */
2152 #define FIRST_PARM_OFFSET(FNDECL) 0
2153
2154 /* o32 and o64 reserve stack space for all argument registers. */
2155 #define REG_PARM_STACK_SPACE(FNDECL) \
2156 (TARGET_OLDABI \
2157 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2158 : 0)
2159
2160 /* Define this if it is the responsibility of the caller to
2161 allocate the area reserved for arguments passed in registers.
2162 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2163 of this macro is to determine whether the space is included in
2164 `crtl->outgoing_args_size'. */
2165 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2166
2167 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2168 \f
2169 /* Symbolic macros for the registers used to return integer and floating
2170 point values. */
2171
2172 #define GP_RETURN (GP_REG_FIRST + 2)
2173 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2174
2175 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2176
2177 /* Symbolic macros for the first/last argument registers. */
2178
2179 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2180 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2181 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2182 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2183
2184 /* 1 if N is a possible register number for function argument passing.
2185 We have no FP argument registers when soft-float. When FP registers
2186 are 32 bits, we can't directly reference the odd numbered ones. */
2187
2188 #define FUNCTION_ARG_REGNO_P(N) \
2189 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2190 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2191 && !fixed_regs[N])
2192 \f
2193 /* This structure has to cope with two different argument allocation
2194 schemes. Most MIPS ABIs view the arguments as a structure, of which
2195 the first N words go in registers and the rest go on the stack. If I
2196 < N, the Ith word might go in Ith integer argument register or in a
2197 floating-point register. For these ABIs, we only need to remember
2198 the offset of the current argument into the structure.
2199
2200 The EABI instead allocates the integer and floating-point arguments
2201 separately. The first N words of FP arguments go in FP registers,
2202 the rest go on the stack. Likewise, the first N words of the other
2203 arguments go in integer registers, and the rest go on the stack. We
2204 need to maintain three counts: the number of integer registers used,
2205 the number of floating-point registers used, and the number of words
2206 passed on the stack.
2207
2208 We could keep separate information for the two ABIs (a word count for
2209 the standard ABIs, and three separate counts for the EABI). But it
2210 seems simpler to view the standard ABIs as forms of EABI that do not
2211 allocate floating-point registers.
2212
2213 So for the standard ABIs, the first N words are allocated to integer
2214 registers, and mips_function_arg decides on an argument-by-argument
2215 basis whether that argument should really go in an integer register,
2216 or in a floating-point one. */
2217
2218 typedef struct mips_args {
2219 /* Always true for varargs functions. Otherwise true if at least
2220 one argument has been passed in an integer register. */
2221 int gp_reg_found;
2222
2223 /* The number of arguments seen so far. */
2224 unsigned int arg_number;
2225
2226 /* The number of integer registers used so far. For all ABIs except
2227 EABI, this is the number of words that have been added to the
2228 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2229 unsigned int num_gprs;
2230
2231 /* For EABI, the number of floating-point registers used so far. */
2232 unsigned int num_fprs;
2233
2234 /* The number of words passed on the stack. */
2235 unsigned int stack_words;
2236
2237 /* On the mips16, we need to keep track of which floating point
2238 arguments were passed in general registers, but would have been
2239 passed in the FP regs if this were a 32-bit function, so that we
2240 can move them to the FP regs if we wind up calling a 32-bit
2241 function. We record this information in fp_code, encoded in base
2242 four. A zero digit means no floating point argument, a one digit
2243 means an SFmode argument, and a two digit means a DFmode argument,
2244 and a three digit is not used. The low order digit is the first
2245 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2246 an SFmode argument. ??? A more sophisticated approach will be
2247 needed if MIPS_ABI != ABI_32. */
2248 int fp_code;
2249
2250 /* True if the function has a prototype. */
2251 int prototype;
2252 } CUMULATIVE_ARGS;
2253
2254 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2255 for a call to a function whose data type is FNTYPE.
2256 For a library call, FNTYPE is 0. */
2257
2258 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2259 mips_init_cumulative_args (&CUM, FNTYPE)
2260
2261 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2262 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2263
2264 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2265 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2266
2267 /* True if using EABI and varargs can be passed in floating-point
2268 registers. Under these conditions, we need a more complex form
2269 of va_list, which tracks GPR, FPR and stack arguments separately. */
2270 #define EABI_FLOAT_VARARGS_P \
2271 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2272
2273 \f
2274 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2275
2276 /* Treat LOC as a byte offset from the stack pointer and round it up
2277 to the next fully-aligned offset. */
2278 #define MIPS_STACK_ALIGN(LOC) \
2279 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2280
2281 \f
2282 /* Output assembler code to FILE to increment profiler label # LABELNO
2283 for profiling a function entry. */
2284
2285 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2286
2287 /* The profiler preserves all interesting registers, including $31. */
2288 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2289
2290 /* No mips port has ever used the profiler counter word, so don't emit it
2291 or the label for it. */
2292
2293 #define NO_PROFILE_COUNTERS 1
2294
2295 /* Define this macro if the code for function profiling should come
2296 before the function prologue. Normally, the profiling code comes
2297 after. */
2298
2299 /* #define PROFILE_BEFORE_PROLOGUE */
2300
2301 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2302 the stack pointer does not matter. The value is tested only in
2303 functions that have frame pointers.
2304 No definition is equivalent to always zero. */
2305
2306 #define EXIT_IGNORE_STACK 1
2307
2308 \f
2309 /* Trampolines are a block of code followed by two pointers. */
2310
2311 #define TRAMPOLINE_SIZE \
2312 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2313
2314 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2315 pointers from a single LUI base. */
2316
2317 #define TRAMPOLINE_ALIGNMENT 64
2318
2319 /* mips_trampoline_init calls this library function to flush
2320 program and data caches. */
2321
2322 #ifndef CACHE_FLUSH_FUNC
2323 #define CACHE_FLUSH_FUNC "_flush_cache"
2324 #endif
2325
2326 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2327 /* Flush both caches. We need to flush the data cache in case \
2328 the system has a write-back cache. */ \
2329 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2330 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2331 GEN_INT (3), TYPE_MODE (integer_type_node))
2332
2333 \f
2334 /* Addressing modes, and classification of registers for them. */
2335
2336 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2337 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2338 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2339 \f
2340 /* Maximum number of registers that can appear in a valid memory address. */
2341
2342 #define MAX_REGS_PER_ADDRESS 1
2343
2344 /* Check for constness inline but use mips_legitimate_address_p
2345 to check whether a constant really is an address. */
2346
2347 #define CONSTANT_ADDRESS_P(X) \
2348 (CONSTANT_P (X) && memory_address_p (SImode, X))
2349
2350 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2351 'the start of the function that this code is output in'. */
2352
2353 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2354 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2355 asm_fprintf ((FILE), "%U%s", \
2356 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2357 else \
2358 asm_fprintf ((FILE), "%U%s", (NAME))
2359 \f
2360 /* Flag to mark a function decl symbol that requires a long call. */
2361 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2362 #define SYMBOL_REF_LONG_CALL_P(X) \
2363 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2364
2365 /* This flag marks functions that cannot be lazily bound. */
2366 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2367 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2368 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2369
2370 /* True if we're generating a form of MIPS16 code in which jump tables
2371 are stored in the text section and encoded as 16-bit PC-relative
2372 offsets. This is only possible when general text loads are allowed,
2373 since the table access itself will be an "lh" instruction. If the
2374 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2375 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2376
2377 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2378
2379 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2380
2381 /* Only use short offsets if their range will not overflow. */
2382 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2383 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2384 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2385 : SImode)
2386
2387 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2388
2389 /* Define this as 1 if `char' should by default be signed; else as 0. */
2390 #ifndef DEFAULT_SIGNED_CHAR
2391 #define DEFAULT_SIGNED_CHAR 1
2392 #endif
2393
2394 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2395 we generally don't want to use them for copying arbitrary data.
2396 A single N-word move is usually the same cost as N single-word moves. */
2397 #define MOVE_MAX UNITS_PER_WORD
2398 #define MAX_MOVE_MAX 8
2399
2400 /* Define this macro as a C expression which is nonzero if
2401 accessing less than a word of memory (i.e. a `char' or a
2402 `short') is no faster than accessing a word of memory, i.e., if
2403 such access require more than one instruction or if there is no
2404 difference in cost between byte and (aligned) word loads.
2405
2406 On RISC machines, it tends to generate better code to define
2407 this as 1, since it avoids making a QI or HI mode register.
2408
2409 But, generating word accesses for -mips16 is generally bad as shifts
2410 (often extended) would be needed for byte accesses. */
2411 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2412
2413 /* Standard MIPS integer shifts truncate the shift amount to the
2414 width of the shifted operand. However, Loongson vector shifts
2415 do not truncate the shift amount at all. */
2416 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2417
2418 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2419 is done just by pretending it is already truncated. */
2420 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2421 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2422
2423
2424 /* Specify the machine mode that pointers have.
2425 After generation of rtl, the compiler makes no further distinction
2426 between pointers and any other objects of this machine mode. */
2427
2428 #ifndef Pmode
2429 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2430 #endif
2431
2432 /* Give call MEMs SImode since it is the "most permissive" mode
2433 for both 32-bit and 64-bit targets. */
2434
2435 #define FUNCTION_MODE SImode
2436
2437 \f
2438 /* We allocate $fcc registers by hand and can't cope with moves of
2439 CCmode registers to and from pseudos (or memory). */
2440 #define AVOID_CCMODE_COPIES
2441
2442 /* A C expression for the cost of a branch instruction. A value of
2443 1 is the default; other values are interpreted relative to that. */
2444
2445 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2446 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2447
2448 /* The MIPS port has several functions that return an instruction count.
2449 Multiplying the count by this value gives the number of bytes that
2450 the instructions occupy. */
2451 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2452
2453 /* The length of a NOP in bytes. */
2454 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2455
2456 /* If defined, modifies the length assigned to instruction INSN as a
2457 function of the context in which it is used. LENGTH is an lvalue
2458 that contains the initially computed length of the insn and should
2459 be updated with the correct length of the insn. */
2460 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2461 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2462
2463 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2464 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2465 its operands. */
2466 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2467 "%*" OPCODE "%?\t" OPERANDS "%/"
2468
2469 /* Return an asm string that forces INSN to be treated as an absolute
2470 J or JAL instruction instead of an assembler macro. */
2471 #define MIPS_ABSOLUTE_JUMP(INSN) \
2472 (TARGET_ABICALLS_PIC2 \
2473 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2474 : INSN)
2475
2476 /* Return the asm template for a call. INSN is the instruction's mnemonic
2477 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2478 number of the target. SIZE_OPNO is the operand number of the argument size
2479 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2480 -1 and the call is indirect, use the function symbol from the call
2481 attributes to attach a R_MIPS_JALR relocation to the call.
2482
2483 When generating GOT code without explicit relocation operators,
2484 all calls should use assembly macros. Otherwise, all indirect
2485 calls should use "jr" or "jalr"; we will arrange to restore $gp
2486 afterwards if necessary. Finally, we can only generate direct
2487 calls for -mabicalls by temporarily switching to non-PIC mode.
2488
2489 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2490 instruction is in the delay slot of jal(r). */
2491 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2492 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2493 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2494 : REG_P (OPERANDS[TARGET_OPNO]) \
2495 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2496 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2497 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2498 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2499 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2500 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2501 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2502
2503 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2504 "jrc" when nop is in the delay slot of "jr". */
2505
2506 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2507 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2508 ? "%*j\t%" #OPNO "%/" \
2509 : REG_P (OPERANDS[OPNO]) \
2510 ? "%*jr%:\t%" #OPNO \
2511 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2512
2513 \f
2514 /* Control the assembler format that we output. */
2515
2516 /* Output to assembler file text saying following lines
2517 may contain character constants, extra white space, comments, etc. */
2518
2519 #ifndef ASM_APP_ON
2520 #define ASM_APP_ON " #APP\n"
2521 #endif
2522
2523 /* Output to assembler file text saying following lines
2524 no longer contain unusual constructs. */
2525
2526 #ifndef ASM_APP_OFF
2527 #define ASM_APP_OFF " #NO_APP\n"
2528 #endif
2529
2530 #define REGISTER_NAMES \
2531 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2532 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2533 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2534 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2535 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2536 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2537 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2538 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2539 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2540 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2541 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2542 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2543 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2544 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2545 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2546 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2547 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2548 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2549 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2550 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2551 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2552 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2553 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2554 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2555
2556 /* List the "software" names for each register. Also list the numerical
2557 names for $fp and $sp. */
2558
2559 #define ADDITIONAL_REGISTER_NAMES \
2560 { \
2561 { "$29", 29 + GP_REG_FIRST }, \
2562 { "$30", 30 + GP_REG_FIRST }, \
2563 { "at", 1 + GP_REG_FIRST }, \
2564 { "v0", 2 + GP_REG_FIRST }, \
2565 { "v1", 3 + GP_REG_FIRST }, \
2566 { "a0", 4 + GP_REG_FIRST }, \
2567 { "a1", 5 + GP_REG_FIRST }, \
2568 { "a2", 6 + GP_REG_FIRST }, \
2569 { "a3", 7 + GP_REG_FIRST }, \
2570 { "t0", 8 + GP_REG_FIRST }, \
2571 { "t1", 9 + GP_REG_FIRST }, \
2572 { "t2", 10 + GP_REG_FIRST }, \
2573 { "t3", 11 + GP_REG_FIRST }, \
2574 { "t4", 12 + GP_REG_FIRST }, \
2575 { "t5", 13 + GP_REG_FIRST }, \
2576 { "t6", 14 + GP_REG_FIRST }, \
2577 { "t7", 15 + GP_REG_FIRST }, \
2578 { "s0", 16 + GP_REG_FIRST }, \
2579 { "s1", 17 + GP_REG_FIRST }, \
2580 { "s2", 18 + GP_REG_FIRST }, \
2581 { "s3", 19 + GP_REG_FIRST }, \
2582 { "s4", 20 + GP_REG_FIRST }, \
2583 { "s5", 21 + GP_REG_FIRST }, \
2584 { "s6", 22 + GP_REG_FIRST }, \
2585 { "s7", 23 + GP_REG_FIRST }, \
2586 { "t8", 24 + GP_REG_FIRST }, \
2587 { "t9", 25 + GP_REG_FIRST }, \
2588 { "k0", 26 + GP_REG_FIRST }, \
2589 { "k1", 27 + GP_REG_FIRST }, \
2590 { "gp", 28 + GP_REG_FIRST }, \
2591 { "sp", 29 + GP_REG_FIRST }, \
2592 { "fp", 30 + GP_REG_FIRST }, \
2593 { "ra", 31 + GP_REG_FIRST } \
2594 }
2595
2596 #define DBR_OUTPUT_SEQEND(STREAM) \
2597 do \
2598 { \
2599 /* Undo the effect of '%*'. */ \
2600 mips_pop_asm_switch (&mips_nomacro); \
2601 mips_pop_asm_switch (&mips_noreorder); \
2602 /* Emit a blank line after the delay slot for emphasis. */ \
2603 fputs ("\n", STREAM); \
2604 } \
2605 while (0)
2606
2607 /* The MIPS implementation uses some labels for its own purpose. The
2608 following lists what labels are created, and are all formed by the
2609 pattern $L[a-z].*. The machine independent portion of GCC creates
2610 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2611
2612 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2613 $Lb[0-9]+ Begin blocks for MIPS debug support
2614 $Lc[0-9]+ Label for use in s<xx> operation.
2615 $Le[0-9]+ End blocks for MIPS debug support */
2616
2617 #undef ASM_DECLARE_OBJECT_NAME
2618 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2619 mips_declare_object (STREAM, NAME, "", ":\n")
2620
2621 /* Globalizing directive for a label. */
2622 #define GLOBAL_ASM_OP "\t.globl\t"
2623
2624 /* This says how to define a global common symbol. */
2625
2626 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2627
2628 /* This says how to define a local common symbol (i.e., not visible to
2629 linker). */
2630
2631 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2632 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2633 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2634 #endif
2635
2636 /* This says how to output an external. It would be possible not to
2637 output anything and let undefined symbol become external. However
2638 the assembler uses length information on externals to allocate in
2639 data/sdata bss/sbss, thereby saving exec time. */
2640
2641 #undef ASM_OUTPUT_EXTERNAL
2642 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2643 mips_output_external(STREAM,DECL,NAME)
2644
2645 /* This is how to declare a function name. The actual work of
2646 emitting the label is moved to function_prologue, so that we can
2647 get the line number correctly emitted before the .ent directive,
2648 and after any .file directives. Define as empty so that the function
2649 is not declared before the .ent directive elsewhere. */
2650
2651 #undef ASM_DECLARE_FUNCTION_NAME
2652 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2653
2654 /* This is how to store into the string LABEL
2655 the symbol_ref name of an internal numbered label where
2656 PREFIX is the class of label and NUM is the number within the class.
2657 This is suitable for output with `assemble_name'. */
2658
2659 #undef ASM_GENERATE_INTERNAL_LABEL
2660 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2661 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2662
2663 /* Print debug labels as "foo = ." rather than "foo:" because they should
2664 represent a byte pointer rather than an ISA-encoded address. This is
2665 particularly important for code like:
2666
2667 $LFBxxx = .
2668 .cfi_startproc
2669 ...
2670 .section .gcc_except_table,...
2671 ...
2672 .uleb128 foo-$LFBxxx
2673
2674 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2675 likewise a byte pointer rather than an ISA-encoded address.
2676
2677 At the time of writing, this hook is not used for the function end
2678 label:
2679
2680 $LFExxx:
2681 .end foo
2682
2683 But this doesn't matter, because GAS doesn't treat a pre-.end label
2684 as a MIPS16 one anyway. */
2685
2686 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2687 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2688
2689 /* This is how to output an element of a case-vector that is absolute. */
2690
2691 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2692 fprintf (STREAM, "\t%s\t%sL%d\n", \
2693 ptr_mode == DImode ? ".dword" : ".word", \
2694 LOCAL_LABEL_PREFIX, \
2695 VALUE)
2696
2697 /* This is how to output an element of a case-vector. We can make the
2698 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2699 is supported. */
2700
2701 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2702 do { \
2703 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2704 { \
2705 if (GET_MODE (BODY) == HImode) \
2706 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2707 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2708 else \
2709 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2710 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2711 } \
2712 else if (TARGET_GPWORD) \
2713 fprintf (STREAM, "\t%s\t%sL%d\n", \
2714 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2715 LOCAL_LABEL_PREFIX, VALUE); \
2716 else if (TARGET_RTP_PIC) \
2717 { \
2718 /* Make the entry relative to the start of the function. */ \
2719 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2720 fprintf (STREAM, "\t%s\t%sL%d-", \
2721 Pmode == DImode ? ".dword" : ".word", \
2722 LOCAL_LABEL_PREFIX, VALUE); \
2723 assemble_name (STREAM, XSTR (fnsym, 0)); \
2724 fprintf (STREAM, "\n"); \
2725 } \
2726 else \
2727 fprintf (STREAM, "\t%s\t%sL%d\n", \
2728 ptr_mode == DImode ? ".dword" : ".word", \
2729 LOCAL_LABEL_PREFIX, VALUE); \
2730 } while (0)
2731
2732 /* This is how to output an assembler line
2733 that says to advance the location counter
2734 to a multiple of 2**LOG bytes. */
2735
2736 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2737 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2738
2739 /* This is how to output an assembler line to advance the location
2740 counter by SIZE bytes. */
2741
2742 #undef ASM_OUTPUT_SKIP
2743 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2744 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2745
2746 /* This is how to output a string. */
2747 #undef ASM_OUTPUT_ASCII
2748 #define ASM_OUTPUT_ASCII mips_output_ascii
2749
2750 \f
2751 /* Default to -G 8 */
2752 #ifndef MIPS_DEFAULT_GVALUE
2753 #define MIPS_DEFAULT_GVALUE 8
2754 #endif
2755
2756 /* Define the strings to put out for each section in the object file. */
2757 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2758 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2759
2760 #undef READONLY_DATA_SECTION_ASM_OP
2761 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2762 \f
2763 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2764 do \
2765 { \
2766 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2767 TARGET_64BIT ? "daddiu" : "addiu", \
2768 reg_names[STACK_POINTER_REGNUM], \
2769 reg_names[STACK_POINTER_REGNUM], \
2770 TARGET_64BIT ? "sd" : "sw", \
2771 reg_names[REGNO], \
2772 reg_names[STACK_POINTER_REGNUM]); \
2773 } \
2774 while (0)
2775
2776 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2777 do \
2778 { \
2779 mips_push_asm_switch (&mips_noreorder); \
2780 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2781 TARGET_64BIT ? "ld" : "lw", \
2782 reg_names[REGNO], \
2783 reg_names[STACK_POINTER_REGNUM], \
2784 TARGET_64BIT ? "daddu" : "addu", \
2785 reg_names[STACK_POINTER_REGNUM], \
2786 reg_names[STACK_POINTER_REGNUM]); \
2787 mips_pop_asm_switch (&mips_noreorder); \
2788 } \
2789 while (0)
2790
2791 /* How to start an assembler comment.
2792 The leading space is important (the mips native assembler requires it). */
2793 #ifndef ASM_COMMENT_START
2794 #define ASM_COMMENT_START " #"
2795 #endif
2796 \f
2797 #undef SIZE_TYPE
2798 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2799
2800 #undef PTRDIFF_TYPE
2801 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2802
2803 /* The maximum number of bytes that can be copied by one iteration of
2804 a movmemsi loop; see mips_block_move_loop. */
2805 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2806 (UNITS_PER_WORD * 4)
2807
2808 /* The maximum number of bytes that can be copied by a straight-line
2809 implementation of movmemsi; see mips_block_move_straight. We want
2810 to make sure that any loop-based implementation will iterate at
2811 least twice. */
2812 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2813 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2814
2815 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2816 values were determined experimentally by benchmarking with CSiBE.
2817 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2818 for o32 where we have to restore $gp afterwards as well as make an
2819 indirect call), but in practice, bumping this up higher for
2820 TARGET_ABICALLS doesn't make much difference to code size. */
2821
2822 #define MIPS_CALL_RATIO 8
2823
2824 /* Any loop-based implementation of movmemsi will have at least
2825 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2826 moves, so allow individual copies of fewer elements.
2827
2828 When movmemsi is not available, use a value approximating
2829 the length of a memcpy call sequence, so that move_by_pieces
2830 will generate inline code if it is shorter than a function call.
2831 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2832 we'll have to generate a load/store pair for each, halve the
2833 value of MIPS_CALL_RATIO to take that into account. */
2834
2835 #define MOVE_RATIO(speed) \
2836 (HAVE_movmemsi \
2837 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2838 : MIPS_CALL_RATIO / 2)
2839
2840 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2841 mips_move_by_pieces_p (SIZE, ALIGN)
2842
2843 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2844 of the length of a memset call, but use the default otherwise. */
2845
2846 #define CLEAR_RATIO(speed)\
2847 ((speed) ? 15 : MIPS_CALL_RATIO)
2848
2849 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2850 optimizing for size adjust the ratio to account for the overhead of
2851 loading the constant and replicating it across the word. */
2852
2853 #define SET_RATIO(speed) \
2854 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2855
2856 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2857 mips_store_by_pieces_p (SIZE, ALIGN)
2858 \f
2859 /* Since the bits of the _init and _fini function is spread across
2860 many object files, each potentially with its own GP, we must assume
2861 we need to load our GP. We don't preserve $gp or $ra, since each
2862 init/fini chunk is supposed to initialize $gp, and crti/crtn
2863 already take care of preserving $ra and, when appropriate, $gp. */
2864 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2865 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2866 asm (SECTION_OP "\n\
2867 .set push\n\
2868 .set nomips16\n\
2869 .set noreorder\n\
2870 bal 1f\n\
2871 nop\n\
2872 1: .cpload $31\n\
2873 .set reorder\n\
2874 jal " USER_LABEL_PREFIX #FUNC "\n\
2875 .set pop\n\
2876 " TEXT_SECTION_ASM_OP);
2877 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2878 || (defined _ABI64 && _MIPS_SIM == _ABI64))
2879 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2880 asm (SECTION_OP "\n\
2881 .set push\n\
2882 .set nomips16\n\
2883 .set noreorder\n\
2884 bal 1f\n\
2885 nop\n\
2886 1: .set reorder\n\
2887 .cpsetup $31, $2, 1b\n\
2888 jal " USER_LABEL_PREFIX #FUNC "\n\
2889 .set pop\n\
2890 " TEXT_SECTION_ASM_OP);
2891 #endif
2892
2893 #ifndef HAVE_AS_TLS
2894 #define HAVE_AS_TLS 0
2895 #endif
2896
2897 #ifndef USED_FOR_TARGET
2898 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2899 struct mips_asm_switch {
2900 /* The FOO in the description above. */
2901 const char *name;
2902
2903 /* The current block nesting level, or 0 if we aren't in a block. */
2904 int nesting_level;
2905 };
2906
2907 extern const enum reg_class mips_regno_to_class[];
2908 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2909 extern const char *current_function_file; /* filename current function is in */
2910 extern int num_source_filenames; /* current .file # */
2911 extern struct mips_asm_switch mips_noreorder;
2912 extern struct mips_asm_switch mips_nomacro;
2913 extern struct mips_asm_switch mips_noat;
2914 extern int mips_dbx_regno[];
2915 extern int mips_dwarf_regno[];
2916 extern bool mips_split_p[];
2917 extern bool mips_split_hi_p[];
2918 extern bool mips_use_pcrel_pool_p[];
2919 extern const char *mips_lo_relocs[];
2920 extern const char *mips_hi_relocs[];
2921 extern enum processor mips_arch; /* which cpu to codegen for */
2922 extern enum processor mips_tune; /* which cpu to schedule for */
2923 extern int mips_isa; /* architectural level */
2924 extern const struct mips_cpu_info *mips_arch_info;
2925 extern const struct mips_cpu_info *mips_tune_info;
2926 extern unsigned int mips_base_compression_flags;
2927 extern GTY(()) struct target_globals *mips16_globals;
2928 #endif
2929
2930 /* Enable querying of DFA units. */
2931 #define CPU_UNITS_QUERY 1
2932
2933 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2934 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2935
2936 /* As on most targets, we want the .eh_frame section to be read-only where
2937 possible. And as on most targets, this means two things:
2938
2939 (a) Non-locally-binding pointers must have an indirect encoding,
2940 so that the addresses in the .eh_frame section itself become
2941 locally-binding.
2942
2943 (b) A shared library's .eh_frame section must encode locally-binding
2944 pointers in a relative (relocation-free) form.
2945
2946 However, MIPS has traditionally not allowed directives like:
2947
2948 .long x-.
2949
2950 in cases where "x" is in a different section, or is not defined in the
2951 same assembly file. We are therefore unable to emit the PC-relative
2952 form required by (b) at assembly time.
2953
2954 Fortunately, the linker is able to convert absolute addresses into
2955 PC-relative addresses on our behalf. Unfortunately, only certain
2956 versions of the linker know how to do this for indirect pointers,
2957 and for personality data. We must fall back on using writable
2958 .eh_frame sections for shared libraries if the linker does not
2959 support this feature. */
2960 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2961 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2962
2963 /* For switching between MIPS16 and non-MIPS16 modes. */
2964 #define SWITCHABLE_TARGET 1
2965
2966 /* Several named MIPS patterns depend on Pmode. These patterns have the
2967 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2968 Add the appropriate suffix to generator function NAME and invoke it
2969 with arguments ARGS. */
2970 #define PMODE_INSN(NAME, ARGS) \
2971 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)