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Fix Linux multilib configurations with default architectures
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS32R3 (mips_isa == 34)
212 #define ISA_MIPS32R5 (mips_isa == 36)
213 #define ISA_MIPS32R6 (mips_isa == 37)
214 #define ISA_MIPS64 (mips_isa == 64)
215 #define ISA_MIPS64R2 (mips_isa == 65)
216 #define ISA_MIPS64R3 (mips_isa == 66)
217 #define ISA_MIPS64R5 (mips_isa == 68)
218 #define ISA_MIPS64R6 (mips_isa == 69)
219
220 /* Architecture target defines. */
221 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
222 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
223 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
224 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
225 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
226 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
227 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
228 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
229 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
230 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
231 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
232 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
233 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
234 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
235 || mips_arch == PROCESSOR_OCTEON2 \
236 || mips_arch == PROCESSOR_OCTEON3)
237 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
238 || mips_arch == PROCESSOR_OCTEON3)
239 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
240 || mips_arch == PROCESSOR_SB1A)
241 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
242 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
243
244 /* Scheduling target defines. */
245 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
246 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
247 || mips_tune == PROCESSOR_24KF2_1 \
248 || mips_tune == PROCESSOR_24KF1_1)
249 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
250 || mips_tune == PROCESSOR_74KF2_1 \
251 || mips_tune == PROCESSOR_74KF1_1 \
252 || mips_tune == PROCESSOR_74KF3_2)
253 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
254 || mips_tune == PROCESSOR_LOONGSON_2F)
255 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
256 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
257 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
258 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
259 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
260 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
261 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
262 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
263 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
264 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
265 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
266 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
267 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
268 || mips_tune == PROCESSOR_OCTEON2 \
269 || mips_tune == PROCESSOR_OCTEON3)
270 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
271 || mips_tune == PROCESSOR_SB1A)
272 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
273
274 /* Whether vector modes and intrinsics for ST Microelectronics
275 Loongson-2E/2F processors should be enabled. In o32 pairs of
276 floating-point registers provide 64-bit values. */
277 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
278 && (TARGET_LOONGSON_2EF \
279 || TARGET_LOONGSON_3A))
280
281 /* True if the pre-reload scheduler should try to create chains of
282 multiply-add or multiply-subtract instructions. For example,
283 suppose we have:
284
285 t1 = a * b
286 t2 = t1 + c * d
287 t3 = e * f
288 t4 = t3 - g * h
289
290 t1 will have a higher priority than t2 and t3 will have a higher
291 priority than t4. However, before reload, there is no dependence
292 between t1 and t3, and they can often have similar priorities.
293 The scheduler will then tend to prefer:
294
295 t1 = a * b
296 t3 = e * f
297 t2 = t1 + c * d
298 t4 = t3 - g * h
299
300 which stops us from making full use of macc/madd-style instructions.
301 This sort of situation occurs frequently in Fourier transforms and
302 in unrolled loops.
303
304 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
305 queue so that chained multiply-add and multiply-subtract instructions
306 appear ahead of any other instruction that is likely to clobber lo.
307 In the example above, if t2 and t3 become ready at the same time,
308 the code ensures that t2 is scheduled first.
309
310 Multiply-accumulate instructions are a bigger win for some targets
311 than others, so this macro is defined on an opt-in basis. */
312 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
313 || TUNE_MIPS4120 \
314 || TUNE_MIPS4130 \
315 || TUNE_24K \
316 || TUNE_P5600)
317
318 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
319 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
320
321 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
322 directly accessible, while the command-line options select
323 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
324 in use. */
325 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
326 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
327
328 /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents
329 -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */
330 #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX)
331
332 /* TARGET_O32_FP64A_ABI represents all the conditions that form the
333 o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */
334 #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \
335 && !TARGET_ODD_SPREG)
336
337 /* False if SC acts as a memory barrier with respect to itself,
338 otherwise a SYNC will be emitted after SC for atomic operations
339 that require ordering between the SC and following loads and
340 stores. It does not tell anything about ordering of loads and
341 stores prior to and following the SC, only about the SC itself and
342 those loads and stores follow it. */
343 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
344
345 /* Define preprocessor macros for the -march and -mtune options.
346 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
347 processor. If INFO's canonical name is "foo", define PREFIX to
348 be "foo", and define an additional macro PREFIX_FOO. */
349 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
350 do \
351 { \
352 char *macro, *p; \
353 \
354 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
355 for (p = macro; *p != 0; p++) \
356 if (*p == '+') \
357 *p = 'P'; \
358 else \
359 *p = TOUPPER (*p); \
360 \
361 builtin_define (macro); \
362 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
363 free (macro); \
364 } \
365 while (0)
366
367 /* Target CPU builtins. */
368 #define TARGET_CPU_CPP_BUILTINS() \
369 do \
370 { \
371 builtin_assert ("machine=mips"); \
372 builtin_assert ("cpu=mips"); \
373 builtin_define ("__mips__"); \
374 builtin_define ("_mips"); \
375 \
376 /* We do this here because __mips is defined below and so we \
377 can't use builtin_define_std. We don't ever want to define \
378 "mips" for VxWorks because some of the VxWorks headers \
379 construct include filenames from a root directory macro, \
380 an architecture macro and a filename, where the architecture \
381 macro expands to 'mips'. If we define 'mips' to 1, the \
382 architecture macro expands to 1 as well. */ \
383 if (!flag_iso && !TARGET_VXWORKS) \
384 builtin_define ("mips"); \
385 \
386 if (TARGET_64BIT) \
387 builtin_define ("__mips64"); \
388 \
389 /* Treat _R3000 and _R4000 like register-size \
390 defines, which is how they've historically \
391 been used. */ \
392 if (TARGET_64BIT) \
393 { \
394 builtin_define_std ("R4000"); \
395 builtin_define ("_R4000"); \
396 } \
397 else \
398 { \
399 builtin_define_std ("R3000"); \
400 builtin_define ("_R3000"); \
401 } \
402 \
403 if (TARGET_FLOAT64) \
404 builtin_define ("__mips_fpr=64"); \
405 else if (TARGET_FLOATXX) \
406 builtin_define ("__mips_fpr=0"); \
407 else \
408 builtin_define ("__mips_fpr=32"); \
409 \
410 if (mips_base_compression_flags & MASK_MIPS16) \
411 builtin_define ("__mips16"); \
412 \
413 if (TARGET_MIPS3D) \
414 builtin_define ("__mips3d"); \
415 \
416 if (TARGET_SMARTMIPS) \
417 builtin_define ("__mips_smartmips"); \
418 \
419 if (mips_base_compression_flags & MASK_MICROMIPS) \
420 builtin_define ("__mips_micromips"); \
421 \
422 if (TARGET_MCU) \
423 builtin_define ("__mips_mcu"); \
424 \
425 if (TARGET_EVA) \
426 builtin_define ("__mips_eva"); \
427 \
428 if (TARGET_DSP) \
429 { \
430 builtin_define ("__mips_dsp"); \
431 if (TARGET_DSPR2) \
432 { \
433 builtin_define ("__mips_dspr2"); \
434 builtin_define ("__mips_dsp_rev=2"); \
435 } \
436 else \
437 builtin_define ("__mips_dsp_rev=1"); \
438 } \
439 \
440 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
441 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
442 \
443 if (ISA_MIPS1) \
444 { \
445 builtin_define ("__mips=1"); \
446 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
447 } \
448 else if (ISA_MIPS2) \
449 { \
450 builtin_define ("__mips=2"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
452 } \
453 else if (ISA_MIPS3) \
454 { \
455 builtin_define ("__mips=3"); \
456 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
457 } \
458 else if (ISA_MIPS4) \
459 { \
460 builtin_define ("__mips=4"); \
461 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
462 } \
463 else if (mips_isa >= 32 && mips_isa < 64) \
464 { \
465 builtin_define ("__mips=32"); \
466 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
467 } \
468 else if (mips_isa >= 64) \
469 { \
470 builtin_define ("__mips=64"); \
471 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
472 } \
473 if (mips_isa_rev > 0) \
474 builtin_define_with_int_value ("__mips_isa_rev", \
475 mips_isa_rev); \
476 \
477 switch (mips_abi) \
478 { \
479 case ABI_32: \
480 builtin_define ("_ABIO32=1"); \
481 builtin_define ("_MIPS_SIM=_ABIO32"); \
482 break; \
483 \
484 case ABI_N32: \
485 builtin_define ("_ABIN32=2"); \
486 builtin_define ("_MIPS_SIM=_ABIN32"); \
487 break; \
488 \
489 case ABI_64: \
490 builtin_define ("_ABI64=3"); \
491 builtin_define ("_MIPS_SIM=_ABI64"); \
492 break; \
493 \
494 case ABI_O64: \
495 builtin_define ("_ABIO64=4"); \
496 builtin_define ("_MIPS_SIM=_ABIO64"); \
497 break; \
498 } \
499 \
500 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
501 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
502 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
503 builtin_define_with_int_value ("_MIPS_FPSET", \
504 32 / MAX_FPRS_PER_FMT); \
505 builtin_define_with_int_value ("_MIPS_SPFPSET", \
506 TARGET_ODD_SPREG ? 32 : 16); \
507 \
508 /* These defines reflect the ABI in use, not whether the \
509 FPU is directly accessible. */ \
510 if (TARGET_NO_FLOAT) \
511 builtin_define ("__mips_no_float"); \
512 else if (TARGET_HARD_FLOAT_ABI) \
513 builtin_define ("__mips_hard_float"); \
514 else \
515 builtin_define ("__mips_soft_float"); \
516 \
517 if (TARGET_SINGLE_FLOAT) \
518 builtin_define ("__mips_single_float"); \
519 \
520 if (TARGET_PAIRED_SINGLE_FLOAT) \
521 builtin_define ("__mips_paired_single_float"); \
522 \
523 if (mips_abs == MIPS_IEEE_754_2008) \
524 builtin_define ("__mips_abs2008"); \
525 \
526 if (mips_nan == MIPS_IEEE_754_2008) \
527 builtin_define ("__mips_nan2008"); \
528 \
529 if (TARGET_BIG_ENDIAN) \
530 { \
531 builtin_define_std ("MIPSEB"); \
532 builtin_define ("_MIPSEB"); \
533 } \
534 else \
535 { \
536 builtin_define_std ("MIPSEL"); \
537 builtin_define ("_MIPSEL"); \
538 } \
539 \
540 /* Whether calls should go through $25. The separate __PIC__ \
541 macro indicates whether abicalls code might use a GOT. */ \
542 if (TARGET_ABICALLS) \
543 builtin_define ("__mips_abicalls"); \
544 \
545 /* Whether Loongson vector modes are enabled. */ \
546 if (TARGET_LOONGSON_VECTORS) \
547 builtin_define ("__mips_loongson_vector_rev"); \
548 \
549 /* Historical Octeon macro. */ \
550 if (TARGET_OCTEON) \
551 builtin_define ("__OCTEON__"); \
552 \
553 if (TARGET_SYNCI) \
554 builtin_define ("__mips_synci"); \
555 \
556 /* Macros dependent on the C dialect. */ \
557 if (preprocessing_asm_p ()) \
558 { \
559 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
560 builtin_define ("_LANGUAGE_ASSEMBLY"); \
561 } \
562 else if (c_dialect_cxx ()) \
563 { \
564 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
565 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
566 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
567 } \
568 else \
569 { \
570 builtin_define_std ("LANGUAGE_C"); \
571 builtin_define ("_LANGUAGE_C"); \
572 } \
573 if (c_dialect_objc ()) \
574 { \
575 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
576 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
577 /* Bizarre, but retained for backwards compatibility. */ \
578 builtin_define_std ("LANGUAGE_C"); \
579 builtin_define ("_LANGUAGE_C"); \
580 } \
581 \
582 if (mips_abi == ABI_EABI) \
583 builtin_define ("__mips_eabi"); \
584 \
585 if (TARGET_CACHE_BUILTIN) \
586 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
587 } \
588 while (0)
589
590 /* Default target_flags if no switches are specified */
591
592 #ifndef TARGET_DEFAULT
593 #define TARGET_DEFAULT 0
594 #endif
595
596 #ifndef TARGET_CPU_DEFAULT
597 #define TARGET_CPU_DEFAULT 0
598 #endif
599
600 #ifndef TARGET_ENDIAN_DEFAULT
601 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
602 #endif
603
604 #ifdef IN_LIBGCC2
605 #undef TARGET_64BIT
606 /* Make this compile time constant for libgcc2 */
607 #ifdef __mips64
608 #define TARGET_64BIT 1
609 #else
610 #define TARGET_64BIT 0
611 #endif
612 #endif /* IN_LIBGCC2 */
613
614 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
615 when compiled with hardware floating point. This is because MIPS16
616 code cannot save and restore the floating-point registers, which is
617 important if in a mixed MIPS16/non-MIPS16 environment. */
618
619 #ifdef IN_LIBGCC2
620 #if __mips_hard_float
621 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
622 #endif
623 #endif /* IN_LIBGCC2 */
624
625 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
626
627 #ifndef MULTILIB_ENDIAN_DEFAULT
628 #if TARGET_ENDIAN_DEFAULT == 0
629 #define MULTILIB_ENDIAN_DEFAULT "EL"
630 #else
631 #define MULTILIB_ENDIAN_DEFAULT "EB"
632 #endif
633 #endif
634
635 #ifndef MULTILIB_ISA_DEFAULT
636 #if MIPS_ISA_DEFAULT == 1
637 #define MULTILIB_ISA_DEFAULT "mips1"
638 #elif MIPS_ISA_DEFAULT == 2
639 #define MULTILIB_ISA_DEFAULT "mips2"
640 #elif MIPS_ISA_DEFAULT == 3
641 #define MULTILIB_ISA_DEFAULT "mips3"
642 #elif MIPS_ISA_DEFAULT == 4
643 #define MULTILIB_ISA_DEFAULT "mips4"
644 #elif MIPS_ISA_DEFAULT == 32
645 #define MULTILIB_ISA_DEFAULT "mips32"
646 #elif MIPS_ISA_DEFAULT == 33
647 #define MULTILIB_ISA_DEFAULT "mips32r2"
648 #elif MIPS_ISA_DEFAULT == 37
649 #define MULTILIB_ISA_DEFAULT "mips32r6"
650 #elif MIPS_ISA_DEFAULT == 64
651 #define MULTILIB_ISA_DEFAULT "mips64"
652 #elif MIPS_ISA_DEFAULT == 65
653 #define MULTILIB_ISA_DEFAULT "mips64r2"
654 #elif MIPS_ISA_DEFAULT == 69
655 #define MULTILIB_ISA_DEFAULT "mips64r6"
656 #else
657 #define MULTILIB_ISA_DEFAULT "mips1"
658 #endif
659 #endif
660
661 #ifndef MIPS_ABI_DEFAULT
662 #define MIPS_ABI_DEFAULT ABI_32
663 #endif
664
665 /* Use the most portable ABI flag for the ASM specs. */
666
667 #if MIPS_ABI_DEFAULT == ABI_32
668 #define MULTILIB_ABI_DEFAULT "mabi=32"
669 #elif MIPS_ABI_DEFAULT == ABI_O64
670 #define MULTILIB_ABI_DEFAULT "mabi=o64"
671 #elif MIPS_ABI_DEFAULT == ABI_N32
672 #define MULTILIB_ABI_DEFAULT "mabi=n32"
673 #elif MIPS_ABI_DEFAULT == ABI_64
674 #define MULTILIB_ABI_DEFAULT "mabi=64"
675 #elif MIPS_ABI_DEFAULT == ABI_EABI
676 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
677 #endif
678
679 #ifndef MULTILIB_DEFAULTS
680 #define MULTILIB_DEFAULTS \
681 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
682 #endif
683
684 /* We must pass -EL to the linker by default for little endian embedded
685 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
686 linker will default to using big-endian output files. The OUTPUT_FORMAT
687 line must be in the linker script, otherwise -EB/-EL will not work. */
688
689 #ifndef ENDIAN_SPEC
690 #if TARGET_ENDIAN_DEFAULT == 0
691 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
692 #else
693 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
694 #endif
695 #endif
696
697 /* A spec condition that matches all non-mips16 -mips arguments. */
698
699 #define MIPS_ISA_LEVEL_OPTION_SPEC \
700 "mips1|mips2|mips3|mips4|mips32*|mips64*"
701
702 /* A spec condition that matches all non-mips16 architecture arguments. */
703
704 #define MIPS_ARCH_OPTION_SPEC \
705 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
706
707 /* A spec that infers a -mips argument from an -march argument. */
708
709 #define MIPS_ISA_LEVEL_SPEC \
710 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
711 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
712 %{march=mips2|march=r6000:-mips2} \
713 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
714 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
715 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
716 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
717 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
718 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
719 %{march=mips32r3: -mips32r3} \
720 %{march=mips32r5|march=p5600: -mips32r5} \
721 %{march=mips32r6: -mips32r6} \
722 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
723 |march=xlr: -mips64} \
724 %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
725 %{march=mips64r3: -mips64r3} \
726 %{march=mips64r5: -mips64r5} \
727 %{march=mips64r6: -mips64r6}}"
728
729 /* A spec that injects the default multilib ISA if no architecture is
730 specified. */
731
732 #define MIPS_DEFAULT_ISA_LEVEL_SPEC \
733 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
734 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
735
736 /* A spec that infers a -mhard-float or -msoft-float setting from an
737 -march argument. Note that soft-float and hard-float code are not
738 link-compatible. */
739
740 #define MIPS_ARCH_FLOAT_SPEC \
741 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
742 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
743 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
744 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
745 march=*: -mhard-float}"
746
747 /* A spec condition that matches 32-bit options. It only works if
748 MIPS_ISA_LEVEL_SPEC has been applied. */
749
750 #define MIPS_32BIT_OPTION_SPEC \
751 "mips1|mips2|mips32*|mgp32"
752
753 /* A spec condition that matches architectures should be targeted with
754 o32 FPXX for compatibility reasons. */
755 #define MIPS_FPXX_OPTION_SPEC \
756 "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \
757 mips64|mips64r2|mips64r3|mips64r5"
758
759 /* Infer a -msynci setting from a -mips argument, on the assumption that
760 -msynci is desired where possible. */
761 #define MIPS_ISA_SYNCI_SPEC \
762 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \
763 |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}"
764
765 /* Infer a -mnan=2008 setting from a -mips argument. */
766 #define MIPS_ISA_NAN2008_SPEC \
767 "%{mnan*:;mips32r6|mips64r6:-mnan=2008}"
768
769 #if (MIPS_ABI_DEFAULT == ABI_O64 \
770 || MIPS_ABI_DEFAULT == ABI_N32 \
771 || MIPS_ABI_DEFAULT == ABI_64)
772 #define OPT_ARCH64 "mabi=32|mgp32:;"
773 #define OPT_ARCH32 "mabi=32|mgp32"
774 #else
775 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
776 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
777 #endif
778
779 /* Support for a compile-time default CPU, et cetera. The rules are:
780 --with-arch is ignored if -march is specified or a -mips is specified
781 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
782 --with-tune is ignored if -mtune is specified; likewise
783 --with-tune-32 and --with-tune-64.
784 --with-abi is ignored if -mabi is specified.
785 --with-float is ignored if -mhard-float or -msoft-float are
786 specified.
787 --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are
788 specified.
789 --with-nan is ignored if -mnan is specified.
790 --with-fp-32 is ignored if -msoft-float, -msingle-float or -mfp are specified.
791 --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg
792 or -mno-odd-spreg are specified.
793 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
794 specified. */
795 #define OPTION_DEFAULT_SPECS \
796 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
797 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
798 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
799 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
800 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
801 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
802 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
803 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
804 {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \
805 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
806 {"fp_32", "%{" OPT_ARCH32 \
807 ":%{!msoft-float:%{!msingle-float:%{!mfp*:-mfp%(VALUE)}}}}" }, \
808 {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \
809 "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \
810 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
811 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
812 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
813 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
814
815 /* A spec that infers the:
816 -mnan=2008 setting from a -mips argument,
817 -mdsp setting from a -march argument. */
818 #define BASE_DRIVER_SELF_SPECS \
819 MIPS_ISA_NAN2008_SPEC, \
820 "%{!mno-dsp: \
821 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
822 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
823
824 #define DRIVER_SELF_SPECS \
825 MIPS_ISA_LEVEL_SPEC, \
826 BASE_DRIVER_SELF_SPECS
827
828 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
829 && ISA_HAS_COND_TRAP)
830
831 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
832
833 /* True if the ABI can only work with 64-bit integer registers. We
834 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
835 otherwise floating-point registers must also be 64-bit. */
836 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
837
838 /* Likewise for 32-bit regs. */
839 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
840
841 /* True if the file format uses 64-bit symbols. At present, this is
842 only true for n64, which uses 64-bit ELF. */
843 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
844
845 /* True if symbols are 64 bits wide. This is usually determined by
846 the ABI's file format, but it can be overridden by -msym32. Note that
847 overriding the size with -msym32 changes the ABI of relocatable objects,
848 although it doesn't change the ABI of a fully-linked object. */
849 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
850 && Pmode == DImode \
851 && !TARGET_SYM32)
852
853 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
854 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
855 || ISA_MIPS4 \
856 || ISA_MIPS64 \
857 || ISA_MIPS64R2 \
858 || ISA_MIPS64R3 \
859 || ISA_MIPS64R5 \
860 || ISA_MIPS64R6)
861
862 #define ISA_HAS_JR (mips_isa_rev <= 5)
863
864 /* ISA has branch likely instructions (e.g. mips2). */
865 /* Disable branchlikely for tx39 until compare rewrite. They haven't
866 been generated up to this point. */
867 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5)
868
869 /* ISA has 32 single-precision registers. */
870 #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \
871 && !TARGET_LOONGSON_3A) \
872 || TARGET_FLOAT64 \
873 || TARGET_MIPS5900)
874
875 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
876 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
877 || TARGET_MIPS5400 \
878 || TARGET_MIPS5500 \
879 || TARGET_MIPS5900 \
880 || TARGET_MIPS7000 \
881 || TARGET_MIPS9000 \
882 || TARGET_MAD \
883 || (mips_isa_rev >= 1 \
884 && mips_isa_rev <= 5)) \
885 && !TARGET_MIPS16)
886
887 /* ISA has a three-operand multiplication instruction. */
888 #define ISA_HAS_DMUL3 (TARGET_64BIT \
889 && TARGET_OCTEON \
890 && !TARGET_MIPS16)
891
892 /* ISA has HI and LO registers. */
893 #define ISA_HAS_HILO (mips_isa_rev <= 5)
894
895 /* ISA supports instructions DMULT and DMULTU. */
896 #define ISA_HAS_DMULT (TARGET_64BIT \
897 && !TARGET_MIPS5900 \
898 && mips_isa_rev <= 5)
899
900 /* ISA supports instructions MULT and MULTU. */
901 #define ISA_HAS_MULT (mips_isa_rev <= 5)
902
903 /* ISA supports instructions MUL, MULU, MUH, MUHU. */
904 #define ISA_HAS_R6MUL (mips_isa_rev >= 6)
905
906 /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */
907 #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6)
908
909 /* ISA supports instructions DDIV and DDIVU. */
910 #define ISA_HAS_DDIV (TARGET_64BIT \
911 && !TARGET_MIPS5900 \
912 && mips_isa_rev <= 5)
913
914 /* ISA supports instructions DIV and DIVU.
915 This is always true, but the macro is needed for ISA_HAS_<D>DIV
916 in mips.md. */
917 #define ISA_HAS_DIV (mips_isa_rev <= 5)
918
919 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
920 || TARGET_LOONGSON_3A) \
921 && !TARGET_MIPS16)
922
923 /* ISA supports instructions DIV, DIVU, MOD and MODU. */
924 #define ISA_HAS_R6DIV (mips_isa_rev >= 6)
925
926 /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */
927 #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6)
928
929 /* ISA has the floating-point conditional move instructions introduced
930 in mips4. */
931 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
932 || (mips_isa_rev >= 1 \
933 && mips_isa_rev <= 5)) \
934 && !TARGET_MIPS5500 \
935 && !TARGET_MIPS16)
936
937 /* ISA has the integer conditional move instructions introduced in mips4 and
938 ST Loongson 2E/2F. */
939 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
940 || TARGET_MIPS5900 \
941 || TARGET_LOONGSON_2EF)
942
943 /* ISA has LDC1 and SDC1. */
944 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
945 && !TARGET_MIPS5900 \
946 && !TARGET_MIPS16)
947
948 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
949 branch on CC, and move (both FP and non-FP) on CC. */
950 #define ISA_HAS_8CC (ISA_MIPS4 \
951 || (mips_isa_rev >= 1 \
952 && mips_isa_rev <= 5))
953
954 /* ISA has the FP condition code instructions that store the flag in an
955 FP register. */
956 #define ISA_HAS_CCF (mips_isa_rev >= 6)
957
958 #define ISA_HAS_SEL (mips_isa_rev >= 6)
959
960 /* This is a catch all for other mips4 instructions: indexed load, the
961 FP madd and msub instructions, and the FP recip and recip sqrt
962 instructions. Note that this macro should only be used by other
963 ISA_HAS_* macros. */
964 #define ISA_HAS_FP4 ((ISA_MIPS4 \
965 || ISA_MIPS64 \
966 || (mips_isa_rev >= 2 \
967 && mips_isa_rev <= 5)) \
968 && !TARGET_MIPS16)
969
970 /* ISA has floating-point indexed load and store instructions
971 (LWXC1, LDXC1, SWXC1 and SDXC1). */
972 #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
973
974 /* ISA has paired-single instructions. */
975 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS64 \
976 || (mips_isa_rev >= 2 \
977 && mips_isa_rev <= 5))
978
979 /* ISA has conditional trap instructions. */
980 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
981 && !TARGET_MIPS16)
982
983 /* ISA has conditional trap with immediate instructions. */
984 #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \
985 && mips_isa_rev <= 5 \
986 && !TARGET_MIPS16)
987
988 /* ISA has integer multiply-accumulate instructions, madd and msub. */
989 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \
990 && mips_isa_rev <= 5)
991
992 /* Integer multiply-accumulate instructions should be generated. */
993 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
994
995 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
996 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
997
998 /* ISA has floating-point MADDF and MSUBF instructions 'd = d [+-] a * b'. */
999 #define ISA_HAS_FP_MADDF_MSUBF (mips_isa_rev >= 6)
1000
1001 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
1002 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
1003
1004 /* ISA has floating-point nmadd and nmsub instructions
1005 'd = -((a * b) [+-] c)'. */
1006 #define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4
1007
1008 /* ISA has floating-point nmadd and nmsub instructions
1009 'c = -((a * b) [+-] c)'. */
1010 #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF
1011
1012 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
1013 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
1014 doubles are stored in pairs of FPRs, so for safety's sake, we apply
1015 this restriction to the MIPS IV ISA too. */
1016 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
1017 (((ISA_HAS_FP4 \
1018 && ((MODE) == SFmode \
1019 || ((TARGET_FLOAT64 \
1020 || mips_isa_rev >= 2) \
1021 && (MODE) == DFmode))) \
1022 || (((MODE) == SFmode \
1023 || (MODE) == DFmode) \
1024 && (mips_isa_rev >= 6)) \
1025 || (TARGET_SB1 \
1026 && (MODE) == V2SFmode)) \
1027 && !TARGET_MIPS16)
1028
1029 #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16)
1030
1031 #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5)
1032
1033 #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2)
1034
1035 /* ISA has count leading zeroes/ones instruction (not implemented). */
1036 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
1037
1038 /* ISA has three operand multiply instructions that put
1039 the high part in an accumulator: mulhi or mulhiu. */
1040 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
1041 || TARGET_MIPS5500 \
1042 || TARGET_SR71K) \
1043 && !TARGET_MIPS16)
1044
1045 /* ISA has three operand multiply instructions that negate the
1046 result and put the result in an accumulator. */
1047 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
1048 || TARGET_MIPS5500 \
1049 || TARGET_SR71K) \
1050 && !TARGET_MIPS16)
1051
1052 /* ISA has three operand multiply instructions that subtract the
1053 result from a 4th operand and put the result in an accumulator. */
1054 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
1055 || TARGET_MIPS5500 \
1056 || TARGET_SR71K) \
1057 && !TARGET_MIPS16)
1058
1059 /* ISA has three operand multiply instructions that add the result
1060 to a 4th operand and put the result in an accumulator. */
1061 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
1062 || TARGET_MIPS4130 \
1063 || TARGET_MIPS5400 \
1064 || TARGET_MIPS5500 \
1065 || TARGET_SR71K) \
1066 && !TARGET_MIPS16)
1067
1068 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
1069 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
1070 || TARGET_MIPS4130) \
1071 && !TARGET_MIPS16)
1072
1073 /* ISA has the "ror" (rotate right) instructions. */
1074 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
1075 || TARGET_MIPS5400 \
1076 || TARGET_MIPS5500 \
1077 || TARGET_SR71K \
1078 || TARGET_SMARTMIPS) \
1079 && !TARGET_MIPS16)
1080
1081 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1082 64-bit targets also provide DSBH and DSHD. */
1083 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1084
1085 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1086 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1087 || TARGET_LOONGSON_2EF \
1088 || TARGET_MIPS5900 \
1089 || mips_isa_rev >= 1) \
1090 && !TARGET_MIPS16)
1091
1092 /* ISA has data prefetch with limited 9-bit displacement. */
1093 #define ISA_HAS_PREFETCH_9BIT (mips_isa_rev >= 6)
1094
1095 /* ISA has data indexed prefetch instructions. This controls use of
1096 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1097 (prefx is a cop1x instruction, so can only be used if FP is
1098 enabled.) */
1099 #define ISA_HAS_PREFETCHX ISA_HAS_FP4
1100
1101 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1102 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1103 also requires TARGET_DOUBLE_FLOAT. */
1104 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1105
1106 /* ISA includes the MIPS32r2 seb and seh instructions. */
1107 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1108
1109 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1110 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1111
1112 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1113 #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \
1114 && mips_isa_rev >= 2)
1115
1116 /* ISA has lwxs instruction (load w/scaled index address. */
1117 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1118 && !TARGET_MIPS16)
1119
1120 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1121 #define ISA_HAS_LBX (TARGET_OCTEON2)
1122 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1123 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1124 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1125 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1126 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1127 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1128 && TARGET_64BIT)
1129
1130 /* The DSP ASE is available. */
1131 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1132
1133 /* Revision 2 of the DSP ASE is available. */
1134 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1135
1136 /* True if the result of a load is not available to the next instruction.
1137 A nop will then be needed between instructions like "lw $4,..."
1138 and "addiu $4,$4,1". */
1139 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1140 && !TARGET_MIPS3900 \
1141 && !TARGET_MIPS5900 \
1142 && !TARGET_MIPS16 \
1143 && !TARGET_MICROMIPS)
1144
1145 /* Likewise mtc1 and mfc1. */
1146 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1147 && !TARGET_MIPS5900 \
1148 && !TARGET_LOONGSON_2EF)
1149
1150 /* Likewise floating-point comparisons. */
1151 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1152 && !TARGET_MIPS5900 \
1153 && !TARGET_LOONGSON_2EF)
1154
1155 /* True if mflo and mfhi can be immediately followed by instructions
1156 which write to the HI and LO registers.
1157
1158 According to MIPS specifications, MIPS ISAs I, II, and III need
1159 (at least) two instructions between the reads of HI/LO and
1160 instructions which write them, and later ISAs do not. Contradicting
1161 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1162 the UM for the NEC Vr5000) document needing the instructions between
1163 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1164 MIPS64 and later ISAs to have the interlocks, plus any specific
1165 earlier-ISA CPUs for which CPU documentation declares that the
1166 instructions are really interlocked. */
1167 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1168 || TARGET_MIPS5500 \
1169 || TARGET_MIPS5900 \
1170 || TARGET_LOONGSON_2EF)
1171
1172 /* ISA includes synci, jr.hb and jalr.hb. */
1173 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1174
1175 /* ISA includes sync. */
1176 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1177 #define GENERATE_SYNC \
1178 (target_flags_explicit & MASK_LLSC \
1179 ? TARGET_LLSC && !TARGET_MIPS16 \
1180 : ISA_HAS_SYNC)
1181
1182 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1183 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1184 instructions. */
1185 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1186 #define GENERATE_LL_SC \
1187 (target_flags_explicit & MASK_LLSC \
1188 ? TARGET_LLSC && !TARGET_MIPS16 \
1189 : ISA_HAS_LL_SC)
1190
1191 #define ISA_HAS_SWAP (TARGET_XLP)
1192 #define ISA_HAS_LDADD (TARGET_XLP)
1193
1194 /* ISA includes the baddu instruction. */
1195 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1196
1197 /* ISA includes the bbit* instructions. */
1198 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1199
1200 /* ISA includes the cins instruction. */
1201 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1202
1203 /* ISA includes the exts instruction. */
1204 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1205
1206 /* ISA includes the seq and sne instructions. */
1207 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1208
1209 /* ISA includes the pop instruction. */
1210 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1211
1212 /* The CACHE instruction is available in non-MIPS16 code. */
1213 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1214
1215 /* The CACHE instruction is available. */
1216 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1217 \f
1218 /* Tell collect what flags to pass to nm. */
1219 #ifndef NM_FLAGS
1220 #define NM_FLAGS "-Bn"
1221 #endif
1222
1223 \f
1224 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1225 the assembler. It may be overridden by subtargets.
1226
1227 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1228 COFF debugging info. */
1229
1230 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1231 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1232 %{g} %{g0} %{g1} %{g2} %{g3} \
1233 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1234 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1235 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1236 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1237 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1238 #endif
1239
1240 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1241 overridden by subtargets. */
1242
1243 #ifndef SUBTARGET_ASM_SPEC
1244 #define SUBTARGET_ASM_SPEC ""
1245 #endif
1246
1247 #undef ASM_SPEC
1248 #define ASM_SPEC "\
1249 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1250 %{mips32*} %{mips64*} \
1251 %{mips16} %{mno-mips16:-no-mips16} \
1252 %{mmicromips} %{mno-micromips} \
1253 %{mips3d} %{mno-mips3d:-no-mips3d} \
1254 %{mdmx} %{mno-mdmx:-no-mdmx} \
1255 %{mdsp} %{mno-dsp} \
1256 %{mdspr2} %{mno-dspr2} \
1257 %{mmcu} %{mno-mcu} \
1258 %{meva} %{mno-eva} \
1259 %{mvirt} %{mno-virt} \
1260 %{mxpa} %{mno-xpa} \
1261 %{msmartmips} %{mno-smartmips} \
1262 %{mmt} %{mno-mt} \
1263 %{mfix-rm7000} %{mno-fix-rm7000} \
1264 %{mfix-vr4120} %{mfix-vr4130} \
1265 %{mfix-24k} \
1266 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1267 %(subtarget_asm_debugging_spec) \
1268 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1269 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1270 %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \
1271 %{modd-spreg} %{mno-odd-spreg} \
1272 %{mshared} %{mno-shared} \
1273 %{msym32} %{mno-sym32} \
1274 %{mtune=*} \
1275 %{mhard-float} %{msoft-float} \
1276 %{msingle-float} %{mdouble-float} \
1277 %(subtarget_asm_spec)"
1278
1279 /* Extra switches sometimes passed to the linker. */
1280
1281 #ifndef LINK_SPEC
1282 #define LINK_SPEC "\
1283 %(endian_spec) \
1284 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1285 %{shared}"
1286 #endif /* LINK_SPEC defined */
1287
1288
1289 /* Specs for the compiler proper */
1290
1291 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1292 overridden by subtargets. */
1293 #ifndef SUBTARGET_CC1_SPEC
1294 #define SUBTARGET_CC1_SPEC ""
1295 #endif
1296
1297 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1298
1299 #undef CC1_SPEC
1300 #define CC1_SPEC "\
1301 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1302 %(subtarget_cc1_spec)"
1303
1304 /* Preprocessor specs. */
1305
1306 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1307 overridden by subtargets. */
1308 #ifndef SUBTARGET_CPP_SPEC
1309 #define SUBTARGET_CPP_SPEC ""
1310 #endif
1311
1312 #define CPP_SPEC "%(subtarget_cpp_spec)"
1313
1314 /* This macro defines names of additional specifications to put in the specs
1315 that can be used in various specifications like CC1_SPEC. Its definition
1316 is an initializer with a subgrouping for each command option.
1317
1318 Each subgrouping contains a string constant, that defines the
1319 specification name, and a string constant that used by the GCC driver
1320 program.
1321
1322 Do not define this macro if it does not need to do anything. */
1323
1324 #define EXTRA_SPECS \
1325 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1326 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1327 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1328 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1329 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1330 { "endian_spec", ENDIAN_SPEC }, \
1331 SUBTARGET_EXTRA_SPECS
1332
1333 #ifndef SUBTARGET_EXTRA_SPECS
1334 #define SUBTARGET_EXTRA_SPECS
1335 #endif
1336 \f
1337 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1338 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1339
1340 #ifndef PREFERRED_DEBUGGING_TYPE
1341 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1342 #endif
1343
1344 /* The size of DWARF addresses should be the same as the size of symbols
1345 in the target file format. They shouldn't depend on things like -msym32,
1346 because many DWARF consumers do not allow the mixture of address sizes
1347 that one would then get from linking -msym32 code with -msym64 code.
1348
1349 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1350 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1351 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1352
1353 /* By default, turn on GDB extensions. */
1354 #define DEFAULT_GDB_EXTENSIONS 1
1355
1356 /* Registers may have a prefix which can be ignored when matching
1357 user asm and register definitions. */
1358 #ifndef REGISTER_PREFIX
1359 #define REGISTER_PREFIX "$"
1360 #endif
1361
1362 /* Local compiler-generated symbols must have a prefix that the assembler
1363 understands. By default, this is $, although some targets (e.g.,
1364 NetBSD-ELF) need to override this. */
1365
1366 #ifndef LOCAL_LABEL_PREFIX
1367 #define LOCAL_LABEL_PREFIX "$"
1368 #endif
1369
1370 /* By default on the mips, external symbols do not have an underscore
1371 prepended, but some targets (e.g., NetBSD) require this. */
1372
1373 #ifndef USER_LABEL_PREFIX
1374 #define USER_LABEL_PREFIX ""
1375 #endif
1376
1377 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1378 since the length can run past this up to a continuation point. */
1379 #undef DBX_CONTIN_LENGTH
1380 #define DBX_CONTIN_LENGTH 1500
1381
1382 /* How to renumber registers for dbx and gdb. */
1383 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1384
1385 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1386 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1387
1388 /* The DWARF 2 CFA column which tracks the return address. */
1389 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1390
1391 /* Before the prologue, RA lives in r31. */
1392 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1393
1394 /* Describe how we implement __builtin_eh_return. */
1395 #define EH_RETURN_DATA_REGNO(N) \
1396 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1397
1398 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1399
1400 #define EH_USES(N) mips_eh_uses (N)
1401
1402 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1403 The default for this in 64-bit mode is 8, which causes problems with
1404 SFmode register saves. */
1405 #define DWARF_CIE_DATA_ALIGNMENT -4
1406
1407 /* Correct the offset of automatic variables and arguments. Note that
1408 the MIPS debug format wants all automatic variables and arguments
1409 to be in terms of the virtual frame pointer (stack pointer before
1410 any adjustment in the function), while the MIPS 3.0 linker wants
1411 the frame pointer to be the stack pointer after the initial
1412 adjustment. */
1413
1414 #define DEBUGGER_AUTO_OFFSET(X) \
1415 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1416 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1417 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1418 \f
1419 /* Target machine storage layout */
1420
1421 #define BITS_BIG_ENDIAN 0
1422 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1423 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1424
1425 #define MAX_BITS_PER_WORD 64
1426
1427 /* Width of a word, in units (bytes). */
1428 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1429 #ifndef IN_LIBGCC2
1430 #define MIN_UNITS_PER_WORD 4
1431 #endif
1432
1433 /* For MIPS, width of a floating point register. */
1434 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1435
1436 /* The number of consecutive floating-point registers needed to store the
1437 largest format supported by the FPU. */
1438 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1439
1440 /* The number of consecutive floating-point registers needed to store the
1441 smallest format supported by the FPU. */
1442 #define MIN_FPRS_PER_FMT \
1443 (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT)
1444
1445 /* The largest size of value that can be held in floating-point
1446 registers and moved with a single instruction. */
1447 #define UNITS_PER_HWFPVALUE \
1448 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1449
1450 /* The largest size of value that can be held in floating-point
1451 registers. */
1452 #define UNITS_PER_FPVALUE \
1453 (TARGET_SOFT_FLOAT_ABI ? 0 \
1454 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1455 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1456
1457 /* The number of bytes in a double. */
1458 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1459
1460 /* Set the sizes of the core types. */
1461 #define SHORT_TYPE_SIZE 16
1462 #define INT_TYPE_SIZE 32
1463 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1464 #define LONG_LONG_TYPE_SIZE 64
1465
1466 #define FLOAT_TYPE_SIZE 32
1467 #define DOUBLE_TYPE_SIZE 64
1468 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1469
1470 /* Define the sizes of fixed-point types. */
1471 #define SHORT_FRACT_TYPE_SIZE 8
1472 #define FRACT_TYPE_SIZE 16
1473 #define LONG_FRACT_TYPE_SIZE 32
1474 #define LONG_LONG_FRACT_TYPE_SIZE 64
1475
1476 #define SHORT_ACCUM_TYPE_SIZE 16
1477 #define ACCUM_TYPE_SIZE 32
1478 #define LONG_ACCUM_TYPE_SIZE 64
1479 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1480 doesn't support 128-bit integers for MIPS32 currently. */
1481 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1482
1483 /* long double is not a fixed mode, but the idea is that, if we
1484 support long double, we also want a 128-bit integer type. */
1485 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1486
1487 /* Width in bits of a pointer. */
1488 #ifndef POINTER_SIZE
1489 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1490 #endif
1491
1492 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1493 #define PARM_BOUNDARY BITS_PER_WORD
1494
1495 /* Allocation boundary (in *bits*) for the code of a function. */
1496 #define FUNCTION_BOUNDARY 32
1497
1498 /* Alignment of field after `int : 0' in a structure. */
1499 #define EMPTY_FIELD_BOUNDARY 32
1500
1501 /* Every structure's size must be a multiple of this. */
1502 /* 8 is observed right on a DECstation and on riscos 4.02. */
1503 #define STRUCTURE_SIZE_BOUNDARY 8
1504
1505 /* There is no point aligning anything to a rounder boundary than this. */
1506 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1507
1508 /* All accesses must be aligned. */
1509 #define STRICT_ALIGNMENT 1
1510
1511 /* Define this if you wish to imitate the way many other C compilers
1512 handle alignment of bitfields and the structures that contain
1513 them.
1514
1515 The behavior is that the type written for a bit-field (`int',
1516 `short', or other integer type) imposes an alignment for the
1517 entire structure, as if the structure really did contain an
1518 ordinary field of that type. In addition, the bit-field is placed
1519 within the structure so that it would fit within such a field,
1520 not crossing a boundary for it.
1521
1522 Thus, on most machines, a bit-field whose type is written as `int'
1523 would not cross a four-byte boundary, and would force four-byte
1524 alignment for the whole structure. (The alignment used may not
1525 be four bytes; it is controlled by the other alignment
1526 parameters.)
1527
1528 If the macro is defined, its definition should be a C expression;
1529 a nonzero value for the expression enables this behavior. */
1530
1531 #define PCC_BITFIELD_TYPE_MATTERS 1
1532
1533 /* If defined, a C expression to compute the alignment given to a
1534 constant that is being placed in memory. CONSTANT is the constant
1535 and ALIGN is the alignment that the object would ordinarily have.
1536 The value of this macro is used instead of that alignment to align
1537 the object.
1538
1539 If this macro is not defined, then ALIGN is used.
1540
1541 The typical use of this macro is to increase alignment for string
1542 constants to be word aligned so that `strcpy' calls that copy
1543 constants can be done inline. */
1544
1545 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1546 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1547 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1548
1549 /* If defined, a C expression to compute the alignment for a static
1550 variable. TYPE is the data type, and ALIGN is the alignment that
1551 the object would ordinarily have. The value of this macro is used
1552 instead of that alignment to align the object.
1553
1554 If this macro is not defined, then ALIGN is used.
1555
1556 One use of this macro is to increase alignment of medium-size
1557 data to make it all fit in fewer cache lines. Another is to
1558 cause character arrays to be word-aligned so that `strcpy' calls
1559 that copy constants to character arrays can be done inline. */
1560
1561 #undef DATA_ALIGNMENT
1562 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1563 ((((ALIGN) < BITS_PER_WORD) \
1564 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1565 || TREE_CODE (TYPE) == UNION_TYPE \
1566 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1567
1568 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1569 character arrays to be word-aligned so that `strcpy' calls that copy
1570 constants to character arrays can be done inline, and 'strcmp' can be
1571 optimised to use word loads. */
1572 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1573 DATA_ALIGNMENT (TYPE, ALIGN)
1574
1575 #define PAD_VARARGS_DOWN \
1576 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1577
1578 /* Define if operations between registers always perform the operation
1579 on the full register even if a narrower mode is specified. */
1580 #define WORD_REGISTER_OPERATIONS
1581
1582 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1583 moves. All other references are zero extended. */
1584 #define LOAD_EXTEND_OP(MODE) \
1585 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1586 ? SIGN_EXTEND : ZERO_EXTEND)
1587
1588 /* Define this macro if it is advisable to hold scalars in registers
1589 in a wider mode than that declared by the program. In such cases,
1590 the value is constrained to be within the bounds of the declared
1591 type, but kept valid in the wider mode. The signedness of the
1592 extension may differ from that of the type. */
1593
1594 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1595 if (GET_MODE_CLASS (MODE) == MODE_INT \
1596 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1597 { \
1598 if ((MODE) == SImode) \
1599 (UNSIGNEDP) = 0; \
1600 (MODE) = Pmode; \
1601 }
1602
1603 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1604 Extensions of pointers to word_mode must be signed. */
1605 #define POINTERS_EXTEND_UNSIGNED false
1606
1607 /* Define if loading short immediate values into registers sign extends. */
1608 #define SHORT_IMMEDIATES_SIGN_EXTEND
1609
1610 /* The [d]clz instructions have the natural values at 0. */
1611
1612 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1613 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1614 \f
1615 /* Standard register usage. */
1616
1617 /* Number of hardware registers. We have:
1618
1619 - 32 integer registers
1620 - 32 floating point registers
1621 - 8 condition code registers
1622 - 2 accumulator registers (hi and lo)
1623 - 32 registers each for coprocessors 0, 2 and 3
1624 - 4 fake registers:
1625 - ARG_POINTER_REGNUM
1626 - FRAME_POINTER_REGNUM
1627 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1628 - CPRESTORE_SLOT_REGNUM
1629 - 2 dummy entries that were used at various times in the past.
1630 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1631 - 6 DSP control registers */
1632
1633 #define FIRST_PSEUDO_REGISTER 188
1634
1635 /* By default, fix the kernel registers ($26 and $27), the global
1636 pointer ($28) and the stack pointer ($29). This can change
1637 depending on the command-line options.
1638
1639 Regarding coprocessor registers: without evidence to the contrary,
1640 it's best to assume that each coprocessor register has a unique
1641 use. This can be overridden, in, e.g., mips_option_override or
1642 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1643 inappropriate for a particular target. */
1644
1645 #define FIXED_REGISTERS \
1646 { \
1647 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1648 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1649 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1650 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1651 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1652 /* COP0 registers */ \
1653 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1654 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1655 /* COP2 registers */ \
1656 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1657 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1658 /* COP3 registers */ \
1659 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1660 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1661 /* 6 DSP accumulator registers & 6 control registers */ \
1662 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1663 }
1664
1665
1666 /* Set up this array for o32 by default.
1667
1668 Note that we don't mark $31 as a call-clobbered register. The idea is
1669 that it's really the call instructions themselves which clobber $31.
1670 We don't care what the called function does with it afterwards.
1671
1672 This approach makes it easier to implement sibcalls. Unlike normal
1673 calls, sibcalls don't clobber $31, so the register reaches the
1674 called function in tact. EPILOGUE_USES says that $31 is useful
1675 to the called function. */
1676
1677 #define CALL_USED_REGISTERS \
1678 { \
1679 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1680 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1681 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1682 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1683 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1684 /* COP0 registers */ \
1685 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1686 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1687 /* COP2 registers */ \
1688 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1689 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1690 /* COP3 registers */ \
1691 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1692 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1693 /* 6 DSP accumulator registers & 6 control registers */ \
1694 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1695 }
1696
1697
1698 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1699
1700 #define CALL_REALLY_USED_REGISTERS \
1701 { /* General registers. */ \
1702 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1703 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1704 /* Floating-point registers. */ \
1705 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1706 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1707 /* Others. */ \
1708 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1709 /* COP0 registers */ \
1710 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1711 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1712 /* COP2 registers */ \
1713 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1714 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1715 /* COP3 registers */ \
1716 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1717 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1718 /* 6 DSP accumulator registers & 6 control registers */ \
1719 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1720 }
1721
1722 /* Internal macros to classify a register number as to whether it's a
1723 general purpose register, a floating point register, a
1724 multiply/divide register, or a status register. */
1725
1726 #define GP_REG_FIRST 0
1727 #define GP_REG_LAST 31
1728 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1729 #define GP_DBX_FIRST 0
1730 #define K0_REG_NUM (GP_REG_FIRST + 26)
1731 #define K1_REG_NUM (GP_REG_FIRST + 27)
1732 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1733
1734 #define FP_REG_FIRST 32
1735 #define FP_REG_LAST 63
1736 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1737 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1738
1739 #define MD_REG_FIRST 64
1740 #define MD_REG_LAST 65
1741 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1742 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1743
1744 /* The DWARF 2 CFA column which tracks the return address from a
1745 signal handler context. This means that to maintain backwards
1746 compatibility, no hard register can be assigned this column if it
1747 would need to be handled by the DWARF unwinder. */
1748 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1749
1750 #define ST_REG_FIRST 67
1751 #define ST_REG_LAST 74
1752 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1753
1754
1755 /* FIXME: renumber. */
1756 #define COP0_REG_FIRST 80
1757 #define COP0_REG_LAST 111
1758 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1759
1760 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1761 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1762 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1763
1764 #define COP2_REG_FIRST 112
1765 #define COP2_REG_LAST 143
1766 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1767
1768 #define COP3_REG_FIRST 144
1769 #define COP3_REG_LAST 175
1770 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1771
1772 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1773 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1774 #define ALL_COP_REG_LAST COP3_REG_LAST
1775 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1776
1777 #define DSP_ACC_REG_FIRST 176
1778 #define DSP_ACC_REG_LAST 181
1779 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1780
1781 #define AT_REGNUM (GP_REG_FIRST + 1)
1782 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1783 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1784
1785 /* A few bitfield locations for the coprocessor registers. */
1786 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1787 the cause register for the EIC interrupt mode. */
1788 #define CAUSE_IPL 10
1789 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1790 #define SR_IPL 10
1791 /* Exception Level is at bit 1 of the status register. */
1792 #define SR_EXL 1
1793 /* Interrupt Enable is at bit 0 of the status register. */
1794 #define SR_IE 0
1795
1796 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1797 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1798 should be used instead. */
1799 #define FPSW_REGNUM ST_REG_FIRST
1800
1801 #define GP_REG_P(REGNO) \
1802 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1803 #define M16_REG_P(REGNO) \
1804 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1805 #define M16STORE_REG_P(REGNO) \
1806 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1807 #define FP_REG_P(REGNO) \
1808 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1809 #define MD_REG_P(REGNO) \
1810 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1811 #define ST_REG_P(REGNO) \
1812 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1813 #define COP0_REG_P(REGNO) \
1814 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1815 #define COP2_REG_P(REGNO) \
1816 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1817 #define COP3_REG_P(REGNO) \
1818 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1819 #define ALL_COP_REG_P(REGNO) \
1820 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1821 /* Test if REGNO is one of the 6 new DSP accumulators. */
1822 #define DSP_ACC_REG_P(REGNO) \
1823 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1824 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1825 #define ACC_REG_P(REGNO) \
1826 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1827
1828 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1829
1830 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1831 to initialize the mips16 gp pseudo register. */
1832 #define CONST_GP_P(X) \
1833 (GET_CODE (X) == CONST \
1834 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1835 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1836
1837 /* Return coprocessor number from register number. */
1838
1839 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1840 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1841 : COP3_REG_P (REGNO) ? '3' : '?')
1842
1843
1844 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1845
1846 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1847 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1848
1849 /* Select a register mode required for caller save of hard regno REGNO. */
1850 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1851 mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE)
1852
1853 /* Odd-numbered single-precision registers are not considered callee-saved
1854 for o32 FPXX as they will be clobbered when run on an FR=1 FPU. */
1855 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1856 (TARGET_FLOATXX && hard_regno_nregs[REGNO][MODE] == 1 \
1857 && FP_REG_P (REGNO) && ((REGNO) & 1))
1858
1859 #define MODES_TIEABLE_P mips_modes_tieable_p
1860
1861 /* Register to use for pushing function arguments. */
1862 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1863
1864 /* These two registers don't really exist: they get eliminated to either
1865 the stack or hard frame pointer. */
1866 #define ARG_POINTER_REGNUM 77
1867 #define FRAME_POINTER_REGNUM 78
1868
1869 /* $30 is not available on the mips16, so we use $17 as the frame
1870 pointer. */
1871 #define HARD_FRAME_POINTER_REGNUM \
1872 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1873
1874 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1875 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1876
1877 /* Register in which static-chain is passed to a function. */
1878 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1879
1880 /* Registers used as temporaries in prologue/epilogue code:
1881
1882 - If a MIPS16 PIC function needs access to _gp, it first loads
1883 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1884
1885 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1886 register. The register must not conflict with MIPS16_PIC_TEMP.
1887
1888 - If we aren't generating MIPS16 code, the prologue can also use
1889 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1890
1891 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1892 register.
1893
1894 If we're generating MIPS16 code, these registers must come from the
1895 core set of 8. The prologue registers mustn't conflict with any
1896 incoming arguments, the static chain pointer, or the frame pointer.
1897 The epilogue temporary mustn't conflict with the return registers,
1898 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1899 or the EH data registers.
1900
1901 If we're generating interrupt handlers, we use K0 as a temporary register
1902 in prologue/epilogue code. */
1903
1904 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1905 #define MIPS_PROLOGUE_TEMP_REGNUM \
1906 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1907 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1908 (TARGET_MIPS16 \
1909 ? (gcc_unreachable (), INVALID_REGNUM) \
1910 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1911 #define MIPS_EPILOGUE_TEMP_REGNUM \
1912 (cfun->machine->interrupt_handler_p \
1913 ? K0_REG_NUM \
1914 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1915
1916 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1917 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1918 #define MIPS_PROLOGUE_TEMP2(MODE) \
1919 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1920 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1921
1922 /* Define this macro if it is as good or better to call a constant
1923 function address than to call an address kept in a register. */
1924 #define NO_FUNCTION_CSE 1
1925
1926 /* The ABI-defined global pointer. Sometimes we use a different
1927 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1928 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1929
1930 /* We normally use $28 as the global pointer. However, when generating
1931 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1932 register instead. They can then avoid saving and restoring $28
1933 and perhaps avoid using a frame at all.
1934
1935 When a leaf function uses something other than $28, mips_expand_prologue
1936 will modify pic_offset_table_rtx in place. Take the register number
1937 from there after reload. */
1938 #define PIC_OFFSET_TABLE_REGNUM \
1939 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1940 \f
1941 /* Define the classes of registers for register constraints in the
1942 machine description. Also define ranges of constants.
1943
1944 One of the classes must always be named ALL_REGS and include all hard regs.
1945 If there is more than one class, another class must be named NO_REGS
1946 and contain no registers.
1947
1948 The name GENERAL_REGS must be the name of a class (or an alias for
1949 another name such as ALL_REGS). This is the class of registers
1950 that is allowed by "g" or "r" in a register constraint.
1951 Also, registers outside this class are allocated only when
1952 instructions express preferences for them.
1953
1954 The classes must be numbered in nondecreasing order; that is,
1955 a larger-numbered class must never be contained completely
1956 in a smaller-numbered class.
1957
1958 For any two classes, it is very desirable that there be another
1959 class that represents their union. */
1960
1961 enum reg_class
1962 {
1963 NO_REGS, /* no registers in set */
1964 M16_STORE_REGS, /* microMIPS store registers */
1965 M16_REGS, /* mips16 directly accessible registers */
1966 M16_SP_REGS, /* mips16 + $sp */
1967 T_REG, /* mips16 T register ($24) */
1968 M16_T_REGS, /* mips16 registers plus T register */
1969 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1970 V1_REG, /* Register $v1 ($3) used for TLS access. */
1971 SPILL_REGS, /* All but $sp and call preserved regs are in here */
1972 LEA_REGS, /* Every GPR except $25 */
1973 GR_REGS, /* integer registers */
1974 FP_REGS, /* floating point registers */
1975 MD0_REG, /* first multiply/divide register */
1976 MD1_REG, /* second multiply/divide register */
1977 MD_REGS, /* multiply/divide registers (hi/lo) */
1978 COP0_REGS, /* generic coprocessor classes */
1979 COP2_REGS,
1980 COP3_REGS,
1981 ST_REGS, /* status registers (fp status) */
1982 DSP_ACC_REGS, /* DSP accumulator registers */
1983 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1984 FRAME_REGS, /* $arg and $frame */
1985 GR_AND_MD0_REGS, /* union classes */
1986 GR_AND_MD1_REGS,
1987 GR_AND_MD_REGS,
1988 GR_AND_ACC_REGS,
1989 ALL_REGS, /* all registers */
1990 LIM_REG_CLASSES /* max value + 1 */
1991 };
1992
1993 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1994
1995 #define GENERAL_REGS GR_REGS
1996
1997 /* An initializer containing the names of the register classes as C
1998 string constants. These names are used in writing some of the
1999 debugging dumps. */
2000
2001 #define REG_CLASS_NAMES \
2002 { \
2003 "NO_REGS", \
2004 "M16_STORE_REGS", \
2005 "M16_REGS", \
2006 "M16_SP_REGS", \
2007 "T_REG", \
2008 "M16_T_REGS", \
2009 "PIC_FN_ADDR_REG", \
2010 "V1_REG", \
2011 "SPILL_REGS", \
2012 "LEA_REGS", \
2013 "GR_REGS", \
2014 "FP_REGS", \
2015 "MD0_REG", \
2016 "MD1_REG", \
2017 "MD_REGS", \
2018 /* coprocessor registers */ \
2019 "COP0_REGS", \
2020 "COP2_REGS", \
2021 "COP3_REGS", \
2022 "ST_REGS", \
2023 "DSP_ACC_REGS", \
2024 "ACC_REGS", \
2025 "FRAME_REGS", \
2026 "GR_AND_MD0_REGS", \
2027 "GR_AND_MD1_REGS", \
2028 "GR_AND_MD_REGS", \
2029 "GR_AND_ACC_REGS", \
2030 "ALL_REGS" \
2031 }
2032
2033 /* An initializer containing the contents of the register classes,
2034 as integers which are bit masks. The Nth integer specifies the
2035 contents of class N. The way the integer MASK is interpreted is
2036 that register R is in the class if `MASK & (1 << R)' is 1.
2037
2038 When the machine has more than 32 registers, an integer does not
2039 suffice. Then the integers are replaced by sub-initializers,
2040 braced groupings containing several integers. Each
2041 sub-initializer must be suitable as an initializer for the type
2042 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2043
2044 #define REG_CLASS_CONTENTS \
2045 { \
2046 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
2047 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
2048 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
2049 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
2050 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
2051 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
2052 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
2053 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
2054 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
2055 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
2056 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
2057 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
2058 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
2059 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
2060 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
2061 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
2062 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
2063 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
2064 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
2065 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
2066 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
2067 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
2068 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
2069 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
2070 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
2071 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
2072 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
2073 }
2074
2075
2076 /* A C expression whose value is a register class containing hard
2077 register REGNO. In general there is more that one such class;
2078 choose a class which is "minimal", meaning that no smaller class
2079 also contains the register. */
2080
2081 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2082
2083 /* A macro whose definition is the name of the class to which a
2084 valid base register must belong. A base register is one used in
2085 an address which is the register value plus a displacement. */
2086
2087 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
2088
2089 /* A macro whose definition is the name of the class to which a
2090 valid index register must belong. An index register is one used
2091 in an address where its value is either multiplied by a scale
2092 factor or added to another register (as well as added to a
2093 displacement). */
2094
2095 #define INDEX_REG_CLASS NO_REGS
2096
2097 /* We generally want to put call-clobbered registers ahead of
2098 call-saved ones. (IRA expects this.) */
2099
2100 #define REG_ALLOC_ORDER \
2101 { /* Accumulator registers. When GPRs and accumulators have equal \
2102 cost, we generally prefer to use accumulators. For example, \
2103 a division of multiplication result is better allocated to LO, \
2104 so that we put the MFLO at the point of use instead of at the \
2105 point of definition. It's also needed if we're to take advantage \
2106 of the extra accumulators available with -mdspr2. In some cases, \
2107 it can also help to reduce register pressure. */ \
2108 64, 65,176,177,178,179,180,181, \
2109 /* Call-clobbered GPRs. */ \
2110 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2111 24, 25, 31, \
2112 /* The global pointer. This is call-clobbered for o32 and o64 \
2113 abicalls, call-saved for n32 and n64 abicalls, and a program \
2114 invariant otherwise. Putting it between the call-clobbered \
2115 and call-saved registers should cope with all eventualities. */ \
2116 28, \
2117 /* Call-saved GPRs. */ \
2118 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2119 /* GPRs that can never be exposed to the register allocator. */ \
2120 0, 26, 27, 29, \
2121 /* Call-clobbered FPRs. */ \
2122 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2123 48, 49, 50, 51, \
2124 /* FPRs that are usually call-saved. The odd ones are actually \
2125 call-clobbered for n32, but listing them ahead of the even \
2126 registers might encourage the register allocator to fragment \
2127 the available FPR pairs. We need paired FPRs to store long \
2128 doubles, so it isn't clear that using a different order \
2129 for n32 would be a win. */ \
2130 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2131 /* None of the remaining classes have defined call-saved \
2132 registers. */ \
2133 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2134 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2135 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2136 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2137 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2138 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2139 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2140 182,183,184,185,186,187 \
2141 }
2142
2143 /* True if VALUE is an unsigned 6-bit number. */
2144
2145 #define UIMM6_OPERAND(VALUE) \
2146 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2147
2148 /* True if VALUE is a signed 10-bit number. */
2149
2150 #define IMM10_OPERAND(VALUE) \
2151 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2152
2153 /* True if VALUE is a signed 16-bit number. */
2154
2155 #define SMALL_OPERAND(VALUE) \
2156 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2157
2158 /* True if VALUE is an unsigned 16-bit number. */
2159
2160 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2161 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2162
2163 /* True if VALUE can be loaded into a register using LUI. */
2164
2165 #define LUI_OPERAND(VALUE) \
2166 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2167 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2168
2169 /* Return a value X with the low 16 bits clear, and such that
2170 VALUE - X is a signed 16-bit value. */
2171
2172 #define CONST_HIGH_PART(VALUE) \
2173 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2174
2175 #define CONST_LOW_PART(VALUE) \
2176 ((VALUE) - CONST_HIGH_PART (VALUE))
2177
2178 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2179 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2180 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2181 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2182 #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255))
2183
2184 /* The HI and LO registers can only be reloaded via the general
2185 registers. Condition code registers can only be loaded to the
2186 general registers, and from the floating point registers. */
2187
2188 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2189 mips_secondary_reload_class (CLASS, MODE, X, true)
2190 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2191 mips_secondary_reload_class (CLASS, MODE, X, false)
2192
2193 /* When targeting the o32 FPXX ABI, all moves with a length of doubleword
2194 or greater must be performed by FR-mode-aware instructions.
2195 This can be achieved using MFHC1/MTHC1 when these instructions are
2196 available but otherwise moves must go via memory.
2197 For the o32 FP64A ABI, all odd-numbered moves with a length of
2198 doubleword or greater are required to use memory. Using MTC1/MFC1
2199 to access the lower-half of these registers would require a forbidden
2200 single-precision access. We require all double-word moves to use
2201 memory because adding even and odd floating-point registers classes
2202 would have a significant impact on the backend. */
2203 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2204 mips_secondary_memory_needed ((CLASS1), (CLASS2), (MODE))
2205
2206 /* Return the maximum number of consecutive registers
2207 needed to represent mode MODE in a register of class CLASS. */
2208
2209 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2210
2211 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2212 mips_cannot_change_mode_class (FROM, TO, CLASS)
2213 \f
2214 /* Stack layout; function entry, exit and calling. */
2215
2216 #define STACK_GROWS_DOWNWARD
2217
2218 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2219
2220 /* Size of the area allocated in the frame to save the GP. */
2221
2222 #define MIPS_GP_SAVE_AREA_SIZE \
2223 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2224
2225 /* The offset of the first local variable from the frame pointer. See
2226 mips_compute_frame_info for details about the frame layout. */
2227
2228 #define STARTING_FRAME_OFFSET \
2229 (FRAME_GROWS_DOWNWARD \
2230 ? 0 \
2231 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2232
2233 #define RETURN_ADDR_RTX mips_return_addr
2234
2235 /* Mask off the MIPS16 ISA bit in unwind addresses.
2236
2237 The reason for this is a little subtle. When unwinding a call,
2238 we are given the call's return address, which on most targets
2239 is the address of the following instruction. However, what we
2240 actually want to find is the EH region for the call itself.
2241 The target-independent unwind code therefore searches for "RA - 1".
2242
2243 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2244 RA - 1 is therefore the real (even-valued) start of the return
2245 instruction. EH region labels are usually odd-valued MIPS16 symbols
2246 too, so a search for an even address within a MIPS16 region would
2247 usually work.
2248
2249 However, there is an exception. If the end of an EH region is also
2250 the end of a function, the end label is allowed to be even. This is
2251 necessary because a following non-MIPS16 function may also need EH
2252 information for its first instruction.
2253
2254 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2255 non-ISA-encoded address. This probably isn't ideal, but it is
2256 the traditional (legacy) behavior. It is therefore only safe
2257 to search MIPS EH regions for an _odd-valued_ address.
2258
2259 Masking off the ISA bit means that the target-independent code
2260 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2261 #define MASK_RETURN_ADDR GEN_INT (-2)
2262
2263
2264 /* Similarly, don't use the least-significant bit to tell pointers to
2265 code from vtable index. */
2266
2267 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2268
2269 /* The eliminations to $17 are only used for mips16 code. See the
2270 definition of HARD_FRAME_POINTER_REGNUM. */
2271
2272 #define ELIMINABLE_REGS \
2273 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2274 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2275 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2276 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2277 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2278 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2279
2280 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2281 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2282
2283 /* Allocate stack space for arguments at the beginning of each function. */
2284 #define ACCUMULATE_OUTGOING_ARGS 1
2285
2286 /* The argument pointer always points to the first argument. */
2287 #define FIRST_PARM_OFFSET(FNDECL) 0
2288
2289 /* o32 and o64 reserve stack space for all argument registers. */
2290 #define REG_PARM_STACK_SPACE(FNDECL) \
2291 (TARGET_OLDABI \
2292 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2293 : 0)
2294
2295 /* Define this if it is the responsibility of the caller to
2296 allocate the area reserved for arguments passed in registers.
2297 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2298 of this macro is to determine whether the space is included in
2299 `crtl->outgoing_args_size'. */
2300 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2301
2302 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2303 \f
2304 /* Symbolic macros for the registers used to return integer and floating
2305 point values. */
2306
2307 #define GP_RETURN (GP_REG_FIRST + 2)
2308 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2309
2310 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2311
2312 /* Symbolic macros for the first/last argument registers. */
2313
2314 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2315 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2316 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2317 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2318
2319 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2320 are used for returning complex double values in soft-float code, so $6 is the
2321 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2322 $gp itself as the temporary. */
2323 #define POST_CALL_TMP_REG \
2324 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2325
2326 /* 1 if N is a possible register number for function argument passing.
2327 We have no FP argument registers when soft-float. Special handling
2328 is required for O32 where only even numbered registers are used for
2329 O32-FPXX and O32-FP64. */
2330
2331 #define FUNCTION_ARG_REGNO_P(N) \
2332 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2333 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2334 && (mips_abi != ABI_32 \
2335 || TARGET_FLOAT32 \
2336 || ((N) % 2 == 0)))) \
2337 && !fixed_regs[N])
2338 \f
2339 /* This structure has to cope with two different argument allocation
2340 schemes. Most MIPS ABIs view the arguments as a structure, of which
2341 the first N words go in registers and the rest go on the stack. If I
2342 < N, the Ith word might go in Ith integer argument register or in a
2343 floating-point register. For these ABIs, we only need to remember
2344 the offset of the current argument into the structure.
2345
2346 The EABI instead allocates the integer and floating-point arguments
2347 separately. The first N words of FP arguments go in FP registers,
2348 the rest go on the stack. Likewise, the first N words of the other
2349 arguments go in integer registers, and the rest go on the stack. We
2350 need to maintain three counts: the number of integer registers used,
2351 the number of floating-point registers used, and the number of words
2352 passed on the stack.
2353
2354 We could keep separate information for the two ABIs (a word count for
2355 the standard ABIs, and three separate counts for the EABI). But it
2356 seems simpler to view the standard ABIs as forms of EABI that do not
2357 allocate floating-point registers.
2358
2359 So for the standard ABIs, the first N words are allocated to integer
2360 registers, and mips_function_arg decides on an argument-by-argument
2361 basis whether that argument should really go in an integer register,
2362 or in a floating-point one. */
2363
2364 typedef struct mips_args {
2365 /* Always true for varargs functions. Otherwise true if at least
2366 one argument has been passed in an integer register. */
2367 int gp_reg_found;
2368
2369 /* The number of arguments seen so far. */
2370 unsigned int arg_number;
2371
2372 /* The number of integer registers used so far. For all ABIs except
2373 EABI, this is the number of words that have been added to the
2374 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2375 unsigned int num_gprs;
2376
2377 /* For EABI, the number of floating-point registers used so far. */
2378 unsigned int num_fprs;
2379
2380 /* The number of words passed on the stack. */
2381 unsigned int stack_words;
2382
2383 /* On the mips16, we need to keep track of which floating point
2384 arguments were passed in general registers, but would have been
2385 passed in the FP regs if this were a 32-bit function, so that we
2386 can move them to the FP regs if we wind up calling a 32-bit
2387 function. We record this information in fp_code, encoded in base
2388 four. A zero digit means no floating point argument, a one digit
2389 means an SFmode argument, and a two digit means a DFmode argument,
2390 and a three digit is not used. The low order digit is the first
2391 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2392 an SFmode argument. ??? A more sophisticated approach will be
2393 needed if MIPS_ABI != ABI_32. */
2394 int fp_code;
2395
2396 /* True if the function has a prototype. */
2397 int prototype;
2398 } CUMULATIVE_ARGS;
2399
2400 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2401 for a call to a function whose data type is FNTYPE.
2402 For a library call, FNTYPE is 0. */
2403
2404 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2405 mips_init_cumulative_args (&CUM, FNTYPE)
2406
2407 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2408 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2409
2410 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2411 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2412
2413 /* True if using EABI and varargs can be passed in floating-point
2414 registers. Under these conditions, we need a more complex form
2415 of va_list, which tracks GPR, FPR and stack arguments separately. */
2416 #define EABI_FLOAT_VARARGS_P \
2417 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2418
2419 \f
2420 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2421
2422 /* Treat LOC as a byte offset from the stack pointer and round it up
2423 to the next fully-aligned offset. */
2424 #define MIPS_STACK_ALIGN(LOC) \
2425 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2426
2427 \f
2428 /* Output assembler code to FILE to increment profiler label # LABELNO
2429 for profiling a function entry. */
2430
2431 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2432
2433 /* The profiler preserves all interesting registers, including $31. */
2434 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2435
2436 /* No mips port has ever used the profiler counter word, so don't emit it
2437 or the label for it. */
2438
2439 #define NO_PROFILE_COUNTERS 1
2440
2441 /* Define this macro if the code for function profiling should come
2442 before the function prologue. Normally, the profiling code comes
2443 after. */
2444
2445 /* #define PROFILE_BEFORE_PROLOGUE */
2446
2447 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2448 the stack pointer does not matter. The value is tested only in
2449 functions that have frame pointers.
2450 No definition is equivalent to always zero. */
2451
2452 #define EXIT_IGNORE_STACK 1
2453
2454 \f
2455 /* Trampolines are a block of code followed by two pointers. */
2456
2457 #define TRAMPOLINE_SIZE \
2458 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2459
2460 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2461 pointers from a single LUI base. */
2462
2463 #define TRAMPOLINE_ALIGNMENT 64
2464
2465 /* mips_trampoline_init calls this library function to flush
2466 program and data caches. */
2467
2468 #ifndef CACHE_FLUSH_FUNC
2469 #define CACHE_FLUSH_FUNC "_flush_cache"
2470 #endif
2471
2472 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2473 /* Flush both caches. We need to flush the data cache in case \
2474 the system has a write-back cache. */ \
2475 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2476 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2477 GEN_INT (3), TYPE_MODE (integer_type_node))
2478
2479 \f
2480 /* Addressing modes, and classification of registers for them. */
2481
2482 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2483 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2484 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2485 \f
2486 /* Maximum number of registers that can appear in a valid memory address. */
2487
2488 #define MAX_REGS_PER_ADDRESS 1
2489
2490 /* Check for constness inline but use mips_legitimate_address_p
2491 to check whether a constant really is an address. */
2492
2493 #define CONSTANT_ADDRESS_P(X) \
2494 (CONSTANT_P (X) && memory_address_p (SImode, X))
2495
2496 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2497 'the start of the function that this code is output in'. */
2498
2499 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2500 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2501 asm_fprintf ((FILE), "%U%s", \
2502 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2503 else \
2504 asm_fprintf ((FILE), "%U%s", (NAME))
2505 \f
2506 /* Flag to mark a function decl symbol that requires a long call. */
2507 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2508 #define SYMBOL_REF_LONG_CALL_P(X) \
2509 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2510
2511 /* This flag marks functions that cannot be lazily bound. */
2512 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2513 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2514 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2515
2516 /* True if we're generating a form of MIPS16 code in which jump tables
2517 are stored in the text section and encoded as 16-bit PC-relative
2518 offsets. This is only possible when general text loads are allowed,
2519 since the table access itself will be an "lh" instruction. If the
2520 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2521 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2522
2523 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2524
2525 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2526
2527 /* Only use short offsets if their range will not overflow. */
2528 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2529 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2530 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2531 : SImode)
2532
2533 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2534
2535 /* Define this as 1 if `char' should by default be signed; else as 0. */
2536 #ifndef DEFAULT_SIGNED_CHAR
2537 #define DEFAULT_SIGNED_CHAR 1
2538 #endif
2539
2540 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2541 we generally don't want to use them for copying arbitrary data.
2542 A single N-word move is usually the same cost as N single-word moves. */
2543 #define MOVE_MAX UNITS_PER_WORD
2544 #define MAX_MOVE_MAX 8
2545
2546 /* Define this macro as a C expression which is nonzero if
2547 accessing less than a word of memory (i.e. a `char' or a
2548 `short') is no faster than accessing a word of memory, i.e., if
2549 such access require more than one instruction or if there is no
2550 difference in cost between byte and (aligned) word loads.
2551
2552 On RISC machines, it tends to generate better code to define
2553 this as 1, since it avoids making a QI or HI mode register.
2554
2555 But, generating word accesses for -mips16 is generally bad as shifts
2556 (often extended) would be needed for byte accesses. */
2557 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2558
2559 /* Standard MIPS integer shifts truncate the shift amount to the
2560 width of the shifted operand. However, Loongson vector shifts
2561 do not truncate the shift amount at all. */
2562 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2563
2564 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2565 is done just by pretending it is already truncated. */
2566 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2567 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2568
2569
2570 /* Specify the machine mode that pointers have.
2571 After generation of rtl, the compiler makes no further distinction
2572 between pointers and any other objects of this machine mode. */
2573
2574 #ifndef Pmode
2575 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2576 #endif
2577
2578 /* Give call MEMs SImode since it is the "most permissive" mode
2579 for both 32-bit and 64-bit targets. */
2580
2581 #define FUNCTION_MODE SImode
2582
2583 \f
2584 /* We allocate $fcc registers by hand and can't cope with moves of
2585 CCmode registers to and from pseudos (or memory). */
2586 #define AVOID_CCMODE_COPIES
2587
2588 /* A C expression for the cost of a branch instruction. A value of
2589 1 is the default; other values are interpreted relative to that. */
2590
2591 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2592 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2593
2594 /* The MIPS port has several functions that return an instruction count.
2595 Multiplying the count by this value gives the number of bytes that
2596 the instructions occupy. */
2597 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2598
2599 /* The length of a NOP in bytes. */
2600 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2601
2602 /* If defined, modifies the length assigned to instruction INSN as a
2603 function of the context in which it is used. LENGTH is an lvalue
2604 that contains the initially computed length of the insn and should
2605 be updated with the correct length of the insn. */
2606 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2607 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2608
2609 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2610 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2611 its operands. */
2612 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2613 "%*" OPCODE "%?\t" OPERANDS "%/"
2614
2615 /* Return an asm string that forces INSN to be treated as an absolute
2616 J or JAL instruction instead of an assembler macro. */
2617 #define MIPS_ABSOLUTE_JUMP(INSN) \
2618 (TARGET_ABICALLS_PIC2 \
2619 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2620 : INSN)
2621
2622 /* Return the asm template for a call. INSN is the instruction's mnemonic
2623 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2624 number of the target. SIZE_OPNO is the operand number of the argument size
2625 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2626 -1 and the call is indirect, use the function symbol from the call
2627 attributes to attach a R_MIPS_JALR relocation to the call.
2628
2629 When generating GOT code without explicit relocation operators,
2630 all calls should use assembly macros. Otherwise, all indirect
2631 calls should use "jr" or "jalr"; we will arrange to restore $gp
2632 afterwards if necessary. Finally, we can only generate direct
2633 calls for -mabicalls by temporarily switching to non-PIC mode.
2634
2635 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2636 instruction is in the delay slot of jal(r). */
2637 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2638 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2639 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2640 : REG_P (OPERANDS[TARGET_OPNO]) \
2641 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2642 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2643 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2644 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2645 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2646 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2647 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2648 ? MIPS_ABSOLUTE_JUMP ("%*" INSN "%!\t%" #TARGET_OPNO "%/") \
2649 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/")) \
2650
2651 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2652 "jrc" when nop is in the delay slot of "jr". */
2653
2654 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2655 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2656 ? "%*j\t%" #OPNO "%/" \
2657 : REG_P (OPERANDS[OPNO]) \
2658 ? "%*jr%:\t%" #OPNO \
2659 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2660
2661 \f
2662 /* Control the assembler format that we output. */
2663
2664 /* Output to assembler file text saying following lines
2665 may contain character constants, extra white space, comments, etc. */
2666
2667 #ifndef ASM_APP_ON
2668 #define ASM_APP_ON " #APP\n"
2669 #endif
2670
2671 /* Output to assembler file text saying following lines
2672 no longer contain unusual constructs. */
2673
2674 #ifndef ASM_APP_OFF
2675 #define ASM_APP_OFF " #NO_APP\n"
2676 #endif
2677
2678 #define REGISTER_NAMES \
2679 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2680 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2681 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2682 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2683 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2684 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2685 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2686 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2687 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2688 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2689 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2690 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2691 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2692 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2693 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2694 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2695 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2696 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2697 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2698 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2699 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2700 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2701 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2702 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2703
2704 /* List the "software" names for each register. Also list the numerical
2705 names for $fp and $sp. */
2706
2707 #define ADDITIONAL_REGISTER_NAMES \
2708 { \
2709 { "$29", 29 + GP_REG_FIRST }, \
2710 { "$30", 30 + GP_REG_FIRST }, \
2711 { "at", 1 + GP_REG_FIRST }, \
2712 { "v0", 2 + GP_REG_FIRST }, \
2713 { "v1", 3 + GP_REG_FIRST }, \
2714 { "a0", 4 + GP_REG_FIRST }, \
2715 { "a1", 5 + GP_REG_FIRST }, \
2716 { "a2", 6 + GP_REG_FIRST }, \
2717 { "a3", 7 + GP_REG_FIRST }, \
2718 { "t0", 8 + GP_REG_FIRST }, \
2719 { "t1", 9 + GP_REG_FIRST }, \
2720 { "t2", 10 + GP_REG_FIRST }, \
2721 { "t3", 11 + GP_REG_FIRST }, \
2722 { "t4", 12 + GP_REG_FIRST }, \
2723 { "t5", 13 + GP_REG_FIRST }, \
2724 { "t6", 14 + GP_REG_FIRST }, \
2725 { "t7", 15 + GP_REG_FIRST }, \
2726 { "s0", 16 + GP_REG_FIRST }, \
2727 { "s1", 17 + GP_REG_FIRST }, \
2728 { "s2", 18 + GP_REG_FIRST }, \
2729 { "s3", 19 + GP_REG_FIRST }, \
2730 { "s4", 20 + GP_REG_FIRST }, \
2731 { "s5", 21 + GP_REG_FIRST }, \
2732 { "s6", 22 + GP_REG_FIRST }, \
2733 { "s7", 23 + GP_REG_FIRST }, \
2734 { "t8", 24 + GP_REG_FIRST }, \
2735 { "t9", 25 + GP_REG_FIRST }, \
2736 { "k0", 26 + GP_REG_FIRST }, \
2737 { "k1", 27 + GP_REG_FIRST }, \
2738 { "gp", 28 + GP_REG_FIRST }, \
2739 { "sp", 29 + GP_REG_FIRST }, \
2740 { "fp", 30 + GP_REG_FIRST }, \
2741 { "ra", 31 + GP_REG_FIRST } \
2742 }
2743
2744 #define DBR_OUTPUT_SEQEND(STREAM) \
2745 do \
2746 { \
2747 /* Undo the effect of '%*'. */ \
2748 mips_pop_asm_switch (&mips_nomacro); \
2749 mips_pop_asm_switch (&mips_noreorder); \
2750 /* Emit a blank line after the delay slot for emphasis. */ \
2751 fputs ("\n", STREAM); \
2752 } \
2753 while (0)
2754
2755 /* The MIPS implementation uses some labels for its own purpose. The
2756 following lists what labels are created, and are all formed by the
2757 pattern $L[a-z].*. The machine independent portion of GCC creates
2758 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2759
2760 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2761 $Lb[0-9]+ Begin blocks for MIPS debug support
2762 $Lc[0-9]+ Label for use in s<xx> operation.
2763 $Le[0-9]+ End blocks for MIPS debug support */
2764
2765 #undef ASM_DECLARE_OBJECT_NAME
2766 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2767 mips_declare_object (STREAM, NAME, "", ":\n")
2768
2769 /* Globalizing directive for a label. */
2770 #define GLOBAL_ASM_OP "\t.globl\t"
2771
2772 /* This says how to define a global common symbol. */
2773
2774 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2775
2776 /* This says how to define a local common symbol (i.e., not visible to
2777 linker). */
2778
2779 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2780 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2781 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2782 #endif
2783
2784 /* This says how to output an external. It would be possible not to
2785 output anything and let undefined symbol become external. However
2786 the assembler uses length information on externals to allocate in
2787 data/sdata bss/sbss, thereby saving exec time. */
2788
2789 #undef ASM_OUTPUT_EXTERNAL
2790 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2791 mips_output_external(STREAM,DECL,NAME)
2792
2793 /* This is how to declare a function name. The actual work of
2794 emitting the label is moved to function_prologue, so that we can
2795 get the line number correctly emitted before the .ent directive,
2796 and after any .file directives. Define as empty so that the function
2797 is not declared before the .ent directive elsewhere. */
2798
2799 #undef ASM_DECLARE_FUNCTION_NAME
2800 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2801
2802 /* This is how to store into the string LABEL
2803 the symbol_ref name of an internal numbered label where
2804 PREFIX is the class of label and NUM is the number within the class.
2805 This is suitable for output with `assemble_name'. */
2806
2807 #undef ASM_GENERATE_INTERNAL_LABEL
2808 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2809 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2810
2811 /* Print debug labels as "foo = ." rather than "foo:" because they should
2812 represent a byte pointer rather than an ISA-encoded address. This is
2813 particularly important for code like:
2814
2815 $LFBxxx = .
2816 .cfi_startproc
2817 ...
2818 .section .gcc_except_table,...
2819 ...
2820 .uleb128 foo-$LFBxxx
2821
2822 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2823 likewise a byte pointer rather than an ISA-encoded address.
2824
2825 At the time of writing, this hook is not used for the function end
2826 label:
2827
2828 $LFExxx:
2829 .end foo
2830
2831 But this doesn't matter, because GAS doesn't treat a pre-.end label
2832 as a MIPS16 one anyway. */
2833
2834 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2835 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2836
2837 /* This is how to output an element of a case-vector that is absolute. */
2838
2839 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2840 fprintf (STREAM, "\t%s\t%sL%d\n", \
2841 ptr_mode == DImode ? ".dword" : ".word", \
2842 LOCAL_LABEL_PREFIX, \
2843 VALUE)
2844
2845 /* This is how to output an element of a case-vector. We can make the
2846 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2847 is supported. */
2848
2849 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2850 do { \
2851 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2852 { \
2853 if (GET_MODE (BODY) == HImode) \
2854 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2855 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2856 else \
2857 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2858 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2859 } \
2860 else if (TARGET_GPWORD) \
2861 fprintf (STREAM, "\t%s\t%sL%d\n", \
2862 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2863 LOCAL_LABEL_PREFIX, VALUE); \
2864 else if (TARGET_RTP_PIC) \
2865 { \
2866 /* Make the entry relative to the start of the function. */ \
2867 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2868 fprintf (STREAM, "\t%s\t%sL%d-", \
2869 Pmode == DImode ? ".dword" : ".word", \
2870 LOCAL_LABEL_PREFIX, VALUE); \
2871 assemble_name (STREAM, XSTR (fnsym, 0)); \
2872 fprintf (STREAM, "\n"); \
2873 } \
2874 else \
2875 fprintf (STREAM, "\t%s\t%sL%d\n", \
2876 ptr_mode == DImode ? ".dword" : ".word", \
2877 LOCAL_LABEL_PREFIX, VALUE); \
2878 } while (0)
2879
2880 /* This is how to output an assembler line
2881 that says to advance the location counter
2882 to a multiple of 2**LOG bytes. */
2883
2884 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2885 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2886
2887 /* This is how to output an assembler line to advance the location
2888 counter by SIZE bytes. */
2889
2890 #undef ASM_OUTPUT_SKIP
2891 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2892 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2893
2894 /* This is how to output a string. */
2895 #undef ASM_OUTPUT_ASCII
2896 #define ASM_OUTPUT_ASCII mips_output_ascii
2897
2898 \f
2899 /* Default to -G 8 */
2900 #ifndef MIPS_DEFAULT_GVALUE
2901 #define MIPS_DEFAULT_GVALUE 8
2902 #endif
2903
2904 /* Define the strings to put out for each section in the object file. */
2905 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2906 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2907
2908 #undef READONLY_DATA_SECTION_ASM_OP
2909 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2910 \f
2911 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2912 do \
2913 { \
2914 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2915 TARGET_64BIT ? "daddiu" : "addiu", \
2916 reg_names[STACK_POINTER_REGNUM], \
2917 reg_names[STACK_POINTER_REGNUM], \
2918 TARGET_64BIT ? "sd" : "sw", \
2919 reg_names[REGNO], \
2920 reg_names[STACK_POINTER_REGNUM]); \
2921 } \
2922 while (0)
2923
2924 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2925 do \
2926 { \
2927 mips_push_asm_switch (&mips_noreorder); \
2928 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2929 TARGET_64BIT ? "ld" : "lw", \
2930 reg_names[REGNO], \
2931 reg_names[STACK_POINTER_REGNUM], \
2932 TARGET_64BIT ? "daddu" : "addu", \
2933 reg_names[STACK_POINTER_REGNUM], \
2934 reg_names[STACK_POINTER_REGNUM]); \
2935 mips_pop_asm_switch (&mips_noreorder); \
2936 } \
2937 while (0)
2938
2939 /* How to start an assembler comment.
2940 The leading space is important (the mips native assembler requires it). */
2941 #ifndef ASM_COMMENT_START
2942 #define ASM_COMMENT_START " #"
2943 #endif
2944 \f
2945 #undef SIZE_TYPE
2946 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2947
2948 #undef PTRDIFF_TYPE
2949 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2950
2951 /* The maximum number of bytes that can be copied by one iteration of
2952 a movmemsi loop; see mips_block_move_loop. */
2953 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2954 (UNITS_PER_WORD * 4)
2955
2956 /* The maximum number of bytes that can be copied by a straight-line
2957 implementation of movmemsi; see mips_block_move_straight. We want
2958 to make sure that any loop-based implementation will iterate at
2959 least twice. */
2960 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2961 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2962
2963 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2964 values were determined experimentally by benchmarking with CSiBE.
2965 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2966 for o32 where we have to restore $gp afterwards as well as make an
2967 indirect call), but in practice, bumping this up higher for
2968 TARGET_ABICALLS doesn't make much difference to code size. */
2969
2970 #define MIPS_CALL_RATIO 8
2971
2972 /* Any loop-based implementation of movmemsi will have at least
2973 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2974 moves, so allow individual copies of fewer elements.
2975
2976 When movmemsi is not available, use a value approximating
2977 the length of a memcpy call sequence, so that move_by_pieces
2978 will generate inline code if it is shorter than a function call.
2979 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2980 we'll have to generate a load/store pair for each, halve the
2981 value of MIPS_CALL_RATIO to take that into account. */
2982
2983 #define MOVE_RATIO(speed) \
2984 (HAVE_movmemsi \
2985 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2986 : MIPS_CALL_RATIO / 2)
2987
2988 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2989 of the length of a memset call, but use the default otherwise. */
2990
2991 #define CLEAR_RATIO(speed)\
2992 ((speed) ? 15 : MIPS_CALL_RATIO)
2993
2994 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2995 optimizing for size adjust the ratio to account for the overhead of
2996 loading the constant and replicating it across the word. */
2997
2998 #define SET_RATIO(speed) \
2999 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3000 \f
3001 /* Since the bits of the _init and _fini function is spread across
3002 many object files, each potentially with its own GP, we must assume
3003 we need to load our GP. We don't preserve $gp or $ra, since each
3004 init/fini chunk is supposed to initialize $gp, and crti/crtn
3005 already take care of preserving $ra and, when appropriate, $gp. */
3006 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3007 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3008 asm (SECTION_OP "\n\
3009 .set push\n\
3010 .set nomips16\n\
3011 .set noreorder\n\
3012 bal 1f\n\
3013 nop\n\
3014 1: .cpload $31\n\
3015 .set reorder\n\
3016 jal " USER_LABEL_PREFIX #FUNC "\n\
3017 .set pop\n\
3018 " TEXT_SECTION_ASM_OP);
3019 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3020 || (defined _ABI64 && _MIPS_SIM == _ABI64))
3021 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3022 asm (SECTION_OP "\n\
3023 .set push\n\
3024 .set nomips16\n\
3025 .set noreorder\n\
3026 bal 1f\n\
3027 nop\n\
3028 1: .set reorder\n\
3029 .cpsetup $31, $2, 1b\n\
3030 jal " USER_LABEL_PREFIX #FUNC "\n\
3031 .set pop\n\
3032 " TEXT_SECTION_ASM_OP);
3033 #endif
3034
3035 #ifndef HAVE_AS_TLS
3036 #define HAVE_AS_TLS 0
3037 #endif
3038
3039 #ifndef HAVE_AS_NAN
3040 #define HAVE_AS_NAN 0
3041 #endif
3042
3043 #ifndef USED_FOR_TARGET
3044 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3045 struct mips_asm_switch {
3046 /* The FOO in the description above. */
3047 const char *name;
3048
3049 /* The current block nesting level, or 0 if we aren't in a block. */
3050 int nesting_level;
3051 };
3052
3053 extern const enum reg_class mips_regno_to_class[];
3054 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3055 extern const char *current_function_file; /* filename current function is in */
3056 extern int num_source_filenames; /* current .file # */
3057 extern struct mips_asm_switch mips_noreorder;
3058 extern struct mips_asm_switch mips_nomacro;
3059 extern struct mips_asm_switch mips_noat;
3060 extern int mips_dbx_regno[];
3061 extern int mips_dwarf_regno[];
3062 extern bool mips_split_p[];
3063 extern bool mips_split_hi_p[];
3064 extern bool mips_use_pcrel_pool_p[];
3065 extern const char *mips_lo_relocs[];
3066 extern const char *mips_hi_relocs[];
3067 extern enum processor mips_arch; /* which cpu to codegen for */
3068 extern enum processor mips_tune; /* which cpu to schedule for */
3069 extern int mips_isa; /* architectural level */
3070 extern int mips_isa_rev;
3071 extern const struct mips_cpu_info *mips_arch_info;
3072 extern const struct mips_cpu_info *mips_tune_info;
3073 extern unsigned int mips_base_compression_flags;
3074 extern GTY(()) struct target_globals *mips16_globals;
3075 #endif
3076
3077 /* Enable querying of DFA units. */
3078 #define CPU_UNITS_QUERY 1
3079
3080 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3081 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3082
3083 /* As on most targets, we want the .eh_frame section to be read-only where
3084 possible. And as on most targets, this means two things:
3085
3086 (a) Non-locally-binding pointers must have an indirect encoding,
3087 so that the addresses in the .eh_frame section itself become
3088 locally-binding.
3089
3090 (b) A shared library's .eh_frame section must encode locally-binding
3091 pointers in a relative (relocation-free) form.
3092
3093 However, MIPS has traditionally not allowed directives like:
3094
3095 .long x-.
3096
3097 in cases where "x" is in a different section, or is not defined in the
3098 same assembly file. We are therefore unable to emit the PC-relative
3099 form required by (b) at assembly time.
3100
3101 Fortunately, the linker is able to convert absolute addresses into
3102 PC-relative addresses on our behalf. Unfortunately, only certain
3103 versions of the linker know how to do this for indirect pointers,
3104 and for personality data. We must fall back on using writable
3105 .eh_frame sections for shared libraries if the linker does not
3106 support this feature. */
3107 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3108 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3109
3110 /* For switching between MIPS16 and non-MIPS16 modes. */
3111 #define SWITCHABLE_TARGET 1
3112
3113 /* Several named MIPS patterns depend on Pmode. These patterns have the
3114 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3115 Add the appropriate suffix to generator function NAME and invoke it
3116 with arguments ARGS. */
3117 #define PMODE_INSN(NAME, ARGS) \
3118 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
3119
3120 /* If we are *not* using multilibs and the default ABI is not ABI_32 we
3121 need to change these from /lib and /usr/lib. */
3122 #if MIPS_ABI_DEFAULT == ABI_N32
3123 #define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
3124 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
3125 #elif MIPS_ABI_DEFAULT == ABI_64
3126 #define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
3127 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
3128 #endif