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mips-cpus.def (34kn): New.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
4 2012
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky (lich@inria.inria.fr).
7 Changed by Michael Meissner (meissner@osf.org).
8 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
9 Brendan Eich (brendan@microunity.com).
10
11 This file is part of GCC.
12
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
16 any later version.
17
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
26
27
28 #include "config/vxworks-dummy.h"
29
30 #ifdef GENERATOR_FILE
31 /* This is used in some insn conditions, so needs to be declared, but
32 does not need to be defined. */
33 extern int target_flags_explicit;
34 #endif
35
36 /* MIPS external variables defined in mips.c. */
37
38 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
39 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
40 to work on a 64-bit machine. */
41
42 #define ABI_32 0
43 #define ABI_N32 1
44 #define ABI_64 2
45 #define ABI_EABI 3
46 #define ABI_O64 4
47
48 /* Masks that affect tuning.
49
50 PTF_AVOID_BRANCHLIKELY
51 Set if it is usually not profitable to use branch-likely instructions
52 for this target, typically because the branches are always predicted
53 taken and so incur a large overhead when not taken. */
54 #define PTF_AVOID_BRANCHLIKELY 0x1
55
56 /* Information about one recognized processor. Defined here for the
57 benefit of TARGET_CPU_CPP_BUILTINS. */
58 struct mips_cpu_info {
59 /* The 'canonical' name of the processor as far as GCC is concerned.
60 It's typically a manufacturer's prefix followed by a numerical
61 designation. It should be lowercase. */
62 const char *name;
63
64 /* The internal processor number that most closely matches this
65 entry. Several processors can have the same value, if there's no
66 difference between them from GCC's point of view. */
67 enum processor cpu;
68
69 /* The ISA level that the processor implements. */
70 int isa;
71
72 /* A mask of PTF_* values. */
73 unsigned int tune_flags;
74 };
75
76 #include "config/mips/mips-opts.h"
77
78 /* Macros to silence warnings about numbers being signed in traditional
79 C and unsigned in ISO C when compiled on 32-bit hosts. */
80
81 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
82 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
83 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
84
85 \f
86 /* Run-time compilation parameters selecting different hardware subsets. */
87
88 /* True if we are generating position-independent VxWorks RTP code. */
89 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
90
91 /* True if the output file is marked as ".abicalls; .option pic0"
92 (-call_nonpic). */
93 #define TARGET_ABICALLS_PIC0 \
94 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
95
96 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
97 #define TARGET_ABICALLS_PIC2 \
98 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
99
100 /* True if the call patterns should be split into a jalr followed by
101 an instruction to restore $gp. It is only safe to split the load
102 from the call when every use of $gp is explicit.
103
104 See mips_must_initialize_gp_p for details about how we manage the
105 global pointer. */
106
107 #define TARGET_SPLIT_CALLS \
108 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
109
110 /* True if we're generating a form of -mabicalls in which we can use
111 operators like %hi and %lo to refer to locally-binding symbols.
112 We can only do this for -mno-shared, and only then if we can use
113 relocation operations instead of assembly macros. It isn't really
114 worth using absolute sequences for 64-bit symbols because GOT
115 accesses are so much shorter. */
116
117 #define TARGET_ABSOLUTE_ABICALLS \
118 (TARGET_ABICALLS \
119 && !TARGET_SHARED \
120 && TARGET_EXPLICIT_RELOCS \
121 && !ABI_HAS_64BIT_SYMBOLS)
122
123 /* True if we can optimize sibling calls. For simplicity, we only
124 handle cases in which call_insn_operand will reject invalid
125 sibcall addresses. There are two cases in which this isn't true:
126
127 - TARGET_MIPS16. call_insn_operand accepts constant addresses
128 but there is no direct jump instruction. It isn't worth
129 using sibling calls in this case anyway; they would usually
130 be longer than normal calls.
131
132 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
133 accepts global constants, but all sibcalls must be indirect. */
134 #define TARGET_SIBCALLS \
135 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
136
137 /* True if we need to use a global offset table to access some symbols. */
138 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
139
140 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
141 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
142
143 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
144 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
145
146 /* True if we should use .cprestore to store to the cprestore slot.
147
148 We continue to use .cprestore for explicit-reloc code so that JALs
149 inside inline asms will work correctly. */
150 #define TARGET_CPRESTORE_DIRECTIVE \
151 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
152
153 /* True if we can use the J and JAL instructions. */
154 #define TARGET_ABSOLUTE_JUMPS \
155 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
156
157 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
158 This is true for both the PIC and non-PIC VxWorks RTP modes. */
159 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
160
161 /* True if .gpword or .gpdword should be used for switch tables. */
162 #define TARGET_GPWORD \
163 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
164
165 /* True if the output must have a writable .eh_frame.
166 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
167 #ifdef HAVE_LD_PERSONALITY_RELAXATION
168 #define TARGET_WRITABLE_EH_FRAME 0
169 #else
170 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
171 #endif
172
173 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
174 #ifdef HAVE_AS_DSPR1_MULT
175 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
176 #else
177 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
178 #endif
179
180 /* Generate mips16 code */
181 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
182 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
183 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
184 /* Generate mips16e register save/restore sequences. */
185 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
186
187 /* True if we're generating a form of MIPS16 code in which general
188 text loads are allowed. */
189 #define TARGET_MIPS16_TEXT_LOADS \
190 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
191
192 /* True if we're generating a form of MIPS16 code in which PC-relative
193 loads are allowed. */
194 #define TARGET_MIPS16_PCREL_LOADS \
195 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
196
197 /* Generic ISA defines. */
198 #define ISA_MIPS1 (mips_isa == 1)
199 #define ISA_MIPS2 (mips_isa == 2)
200 #define ISA_MIPS3 (mips_isa == 3)
201 #define ISA_MIPS4 (mips_isa == 4)
202 #define ISA_MIPS32 (mips_isa == 32)
203 #define ISA_MIPS32R2 (mips_isa == 33)
204 #define ISA_MIPS64 (mips_isa == 64)
205 #define ISA_MIPS64R2 (mips_isa == 65)
206
207 /* Architecture target defines. */
208 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
209 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
210 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
211 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
212 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
213 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
214 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
215 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
216 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
217 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
218 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
219 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
220 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
221 || mips_arch == PROCESSOR_OCTEON2)
222 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
223 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
224 || mips_arch == PROCESSOR_SB1A)
225 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
226 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
227
228 /* Scheduling target defines. */
229 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
230 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
231 || mips_tune == PROCESSOR_24KF2_1 \
232 || mips_tune == PROCESSOR_24KF1_1)
233 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
234 || mips_tune == PROCESSOR_74KF2_1 \
235 || mips_tune == PROCESSOR_74KF1_1 \
236 || mips_tune == PROCESSOR_74KF3_2)
237 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
238 || mips_tune == PROCESSOR_LOONGSON_2F)
239 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
240 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
241 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
242 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
243 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
244 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
245 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
246 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
247 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
248 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
249 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
250 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
251 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
252 || mips_tune == PROCESSOR_OCTEON2)
253 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
254 || mips_tune == PROCESSOR_SB1A)
255
256 /* Whether vector modes and intrinsics for ST Microelectronics
257 Loongson-2E/2F processors should be enabled. In o32 pairs of
258 floating-point registers provide 64-bit values. */
259 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
260 && (TARGET_LOONGSON_2EF \
261 || TARGET_LOONGSON_3A))
262
263 /* True if the pre-reload scheduler should try to create chains of
264 multiply-add or multiply-subtract instructions. For example,
265 suppose we have:
266
267 t1 = a * b
268 t2 = t1 + c * d
269 t3 = e * f
270 t4 = t3 - g * h
271
272 t1 will have a higher priority than t2 and t3 will have a higher
273 priority than t4. However, before reload, there is no dependence
274 between t1 and t3, and they can often have similar priorities.
275 The scheduler will then tend to prefer:
276
277 t1 = a * b
278 t3 = e * f
279 t2 = t1 + c * d
280 t4 = t3 - g * h
281
282 which stops us from making full use of macc/madd-style instructions.
283 This sort of situation occurs frequently in Fourier transforms and
284 in unrolled loops.
285
286 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
287 queue so that chained multiply-add and multiply-subtract instructions
288 appear ahead of any other instruction that is likely to clobber lo.
289 In the example above, if t2 and t3 become ready at the same time,
290 the code ensures that t2 is scheduled first.
291
292 Multiply-accumulate instructions are a bigger win for some targets
293 than others, so this macro is defined on an opt-in basis. */
294 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
295 || TUNE_MIPS4120 \
296 || TUNE_MIPS4130 \
297 || TUNE_24K)
298
299 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
300 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
301
302 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
303 directly accessible, while the command-line options select
304 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
305 in use. */
306 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
307 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
308
309 /* False if SC acts as a memory barrier with respect to itself,
310 otherwise a SYNC will be emitted after SC for atomic operations
311 that require ordering between the SC and following loads and
312 stores. It does not tell anything about ordering of loads and
313 stores prior to and following the SC, only about the SC itself and
314 those loads and stores follow it. */
315 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
316
317 /* Define preprocessor macros for the -march and -mtune options.
318 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
319 processor. If INFO's canonical name is "foo", define PREFIX to
320 be "foo", and define an additional macro PREFIX_FOO. */
321 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
322 do \
323 { \
324 char *macro, *p; \
325 \
326 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
327 for (p = macro; *p != 0; p++) \
328 if (*p == '+') \
329 *p = 'P'; \
330 else \
331 *p = TOUPPER (*p); \
332 \
333 builtin_define (macro); \
334 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
335 free (macro); \
336 } \
337 while (0)
338
339 /* Target CPU builtins. */
340 #define TARGET_CPU_CPP_BUILTINS() \
341 do \
342 { \
343 builtin_assert ("machine=mips"); \
344 builtin_assert ("cpu=mips"); \
345 builtin_define ("__mips__"); \
346 builtin_define ("_mips"); \
347 \
348 /* We do this here because __mips is defined below and so we \
349 can't use builtin_define_std. We don't ever want to define \
350 "mips" for VxWorks because some of the VxWorks headers \
351 construct include filenames from a root directory macro, \
352 an architecture macro and a filename, where the architecture \
353 macro expands to 'mips'. If we define 'mips' to 1, the \
354 architecture macro expands to 1 as well. */ \
355 if (!flag_iso && !TARGET_VXWORKS) \
356 builtin_define ("mips"); \
357 \
358 if (TARGET_64BIT) \
359 builtin_define ("__mips64"); \
360 \
361 /* Treat _R3000 and _R4000 like register-size \
362 defines, which is how they've historically \
363 been used. */ \
364 if (TARGET_64BIT) \
365 { \
366 builtin_define_std ("R4000"); \
367 builtin_define ("_R4000"); \
368 } \
369 else \
370 { \
371 builtin_define_std ("R3000"); \
372 builtin_define ("_R3000"); \
373 } \
374 \
375 if (TARGET_FLOAT64) \
376 builtin_define ("__mips_fpr=64"); \
377 else \
378 builtin_define ("__mips_fpr=32"); \
379 \
380 if (mips_base_mips16) \
381 builtin_define ("__mips16"); \
382 \
383 if (TARGET_MIPS3D) \
384 builtin_define ("__mips3d"); \
385 \
386 if (TARGET_SMARTMIPS) \
387 builtin_define ("__mips_smartmips"); \
388 \
389 if (TARGET_MCU) \
390 builtin_define ("__mips_mcu"); \
391 \
392 if (TARGET_DSP) \
393 { \
394 builtin_define ("__mips_dsp"); \
395 if (TARGET_DSPR2) \
396 { \
397 builtin_define ("__mips_dspr2"); \
398 builtin_define ("__mips_dsp_rev=2"); \
399 } \
400 else \
401 builtin_define ("__mips_dsp_rev=1"); \
402 } \
403 \
404 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
405 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
406 \
407 if (ISA_MIPS1) \
408 { \
409 builtin_define ("__mips=1"); \
410 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
411 } \
412 else if (ISA_MIPS2) \
413 { \
414 builtin_define ("__mips=2"); \
415 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
416 } \
417 else if (ISA_MIPS3) \
418 { \
419 builtin_define ("__mips=3"); \
420 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
421 } \
422 else if (ISA_MIPS4) \
423 { \
424 builtin_define ("__mips=4"); \
425 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
426 } \
427 else if (ISA_MIPS32) \
428 { \
429 builtin_define ("__mips=32"); \
430 builtin_define ("__mips_isa_rev=1"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
432 } \
433 else if (ISA_MIPS32R2) \
434 { \
435 builtin_define ("__mips=32"); \
436 builtin_define ("__mips_isa_rev=2"); \
437 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
438 } \
439 else if (ISA_MIPS64) \
440 { \
441 builtin_define ("__mips=64"); \
442 builtin_define ("__mips_isa_rev=1"); \
443 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
444 } \
445 else if (ISA_MIPS64R2) \
446 { \
447 builtin_define ("__mips=64"); \
448 builtin_define ("__mips_isa_rev=2"); \
449 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
450 } \
451 \
452 switch (mips_abi) \
453 { \
454 case ABI_32: \
455 builtin_define ("_ABIO32=1"); \
456 builtin_define ("_MIPS_SIM=_ABIO32"); \
457 break; \
458 \
459 case ABI_N32: \
460 builtin_define ("_ABIN32=2"); \
461 builtin_define ("_MIPS_SIM=_ABIN32"); \
462 break; \
463 \
464 case ABI_64: \
465 builtin_define ("_ABI64=3"); \
466 builtin_define ("_MIPS_SIM=_ABI64"); \
467 break; \
468 \
469 case ABI_O64: \
470 builtin_define ("_ABIO64=4"); \
471 builtin_define ("_MIPS_SIM=_ABIO64"); \
472 break; \
473 } \
474 \
475 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
476 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
477 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
478 builtin_define_with_int_value ("_MIPS_FPSET", \
479 32 / MAX_FPRS_PER_FMT); \
480 \
481 /* These defines reflect the ABI in use, not whether the \
482 FPU is directly accessible. */ \
483 if (TARGET_NO_FLOAT) \
484 builtin_define ("__mips_no_float"); \
485 else if (TARGET_HARD_FLOAT_ABI) \
486 builtin_define ("__mips_hard_float"); \
487 else \
488 builtin_define ("__mips_soft_float"); \
489 \
490 if (TARGET_SINGLE_FLOAT) \
491 builtin_define ("__mips_single_float"); \
492 \
493 if (TARGET_PAIRED_SINGLE_FLOAT) \
494 builtin_define ("__mips_paired_single_float"); \
495 \
496 if (TARGET_BIG_ENDIAN) \
497 { \
498 builtin_define_std ("MIPSEB"); \
499 builtin_define ("_MIPSEB"); \
500 } \
501 else \
502 { \
503 builtin_define_std ("MIPSEL"); \
504 builtin_define ("_MIPSEL"); \
505 } \
506 \
507 /* Whether calls should go through $25. The separate __PIC__ \
508 macro indicates whether abicalls code might use a GOT. */ \
509 if (TARGET_ABICALLS) \
510 builtin_define ("__mips_abicalls"); \
511 \
512 /* Whether Loongson vector modes are enabled. */ \
513 if (TARGET_LOONGSON_VECTORS) \
514 builtin_define ("__mips_loongson_vector_rev"); \
515 \
516 /* Historical Octeon macro. */ \
517 if (TARGET_OCTEON) \
518 builtin_define ("__OCTEON__"); \
519 \
520 /* Macros dependent on the C dialect. */ \
521 if (preprocessing_asm_p ()) \
522 { \
523 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
524 builtin_define ("_LANGUAGE_ASSEMBLY"); \
525 } \
526 else if (c_dialect_cxx ()) \
527 { \
528 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
529 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
530 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
531 } \
532 else \
533 { \
534 builtin_define_std ("LANGUAGE_C"); \
535 builtin_define ("_LANGUAGE_C"); \
536 } \
537 if (c_dialect_objc ()) \
538 { \
539 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
540 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
541 /* Bizarre, but retained for backwards compatibility. */ \
542 builtin_define_std ("LANGUAGE_C"); \
543 builtin_define ("_LANGUAGE_C"); \
544 } \
545 \
546 if (mips_abi == ABI_EABI) \
547 builtin_define ("__mips_eabi"); \
548 \
549 if (TARGET_CACHE_BUILTIN) \
550 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
551 } \
552 while (0)
553
554 /* Default target_flags if no switches are specified */
555
556 #ifndef TARGET_DEFAULT
557 #define TARGET_DEFAULT 0
558 #endif
559
560 #ifndef TARGET_CPU_DEFAULT
561 #define TARGET_CPU_DEFAULT 0
562 #endif
563
564 #ifndef TARGET_ENDIAN_DEFAULT
565 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
566 #endif
567
568 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
569 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
570 #endif
571
572 #ifdef IN_LIBGCC2
573 #undef TARGET_64BIT
574 /* Make this compile time constant for libgcc2 */
575 #ifdef __mips64
576 #define TARGET_64BIT 1
577 #else
578 #define TARGET_64BIT 0
579 #endif
580 #endif /* IN_LIBGCC2 */
581
582 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
583 when compiled with hardware floating point. This is because MIPS16
584 code cannot save and restore the floating-point registers, which is
585 important if in a mixed MIPS16/non-MIPS16 environment. */
586
587 #ifdef IN_LIBGCC2
588 #if __mips_hard_float
589 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
590 #endif
591 #endif /* IN_LIBGCC2 */
592
593 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
594
595 #ifndef MULTILIB_ENDIAN_DEFAULT
596 #if TARGET_ENDIAN_DEFAULT == 0
597 #define MULTILIB_ENDIAN_DEFAULT "EL"
598 #else
599 #define MULTILIB_ENDIAN_DEFAULT "EB"
600 #endif
601 #endif
602
603 #ifndef MULTILIB_ISA_DEFAULT
604 # if MIPS_ISA_DEFAULT == 1
605 # define MULTILIB_ISA_DEFAULT "mips1"
606 # else
607 # if MIPS_ISA_DEFAULT == 2
608 # define MULTILIB_ISA_DEFAULT "mips2"
609 # else
610 # if MIPS_ISA_DEFAULT == 3
611 # define MULTILIB_ISA_DEFAULT "mips3"
612 # else
613 # if MIPS_ISA_DEFAULT == 4
614 # define MULTILIB_ISA_DEFAULT "mips4"
615 # else
616 # if MIPS_ISA_DEFAULT == 32
617 # define MULTILIB_ISA_DEFAULT "mips32"
618 # else
619 # if MIPS_ISA_DEFAULT == 33
620 # define MULTILIB_ISA_DEFAULT "mips32r2"
621 # else
622 # if MIPS_ISA_DEFAULT == 64
623 # define MULTILIB_ISA_DEFAULT "mips64"
624 # else
625 # if MIPS_ISA_DEFAULT == 65
626 # define MULTILIB_ISA_DEFAULT "mips64r2"
627 # else
628 # define MULTILIB_ISA_DEFAULT "mips1"
629 # endif
630 # endif
631 # endif
632 # endif
633 # endif
634 # endif
635 # endif
636 # endif
637 #endif
638
639 #ifndef MIPS_ABI_DEFAULT
640 #define MIPS_ABI_DEFAULT ABI_32
641 #endif
642
643 /* Use the most portable ABI flag for the ASM specs. */
644
645 #if MIPS_ABI_DEFAULT == ABI_32
646 #define MULTILIB_ABI_DEFAULT "mabi=32"
647 #endif
648
649 #if MIPS_ABI_DEFAULT == ABI_O64
650 #define MULTILIB_ABI_DEFAULT "mabi=o64"
651 #endif
652
653 #if MIPS_ABI_DEFAULT == ABI_N32
654 #define MULTILIB_ABI_DEFAULT "mabi=n32"
655 #endif
656
657 #if MIPS_ABI_DEFAULT == ABI_64
658 #define MULTILIB_ABI_DEFAULT "mabi=64"
659 #endif
660
661 #if MIPS_ABI_DEFAULT == ABI_EABI
662 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
663 #endif
664
665 #ifndef MULTILIB_DEFAULTS
666 #define MULTILIB_DEFAULTS \
667 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
668 #endif
669
670 /* We must pass -EL to the linker by default for little endian embedded
671 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
672 linker will default to using big-endian output files. The OUTPUT_FORMAT
673 line must be in the linker script, otherwise -EB/-EL will not work. */
674
675 #ifndef ENDIAN_SPEC
676 #if TARGET_ENDIAN_DEFAULT == 0
677 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
678 #else
679 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
680 #endif
681 #endif
682
683 /* A spec condition that matches all non-mips16 -mips arguments. */
684
685 #define MIPS_ISA_LEVEL_OPTION_SPEC \
686 "mips1|mips2|mips3|mips4|mips32*|mips64*"
687
688 /* A spec condition that matches all non-mips16 architecture arguments. */
689
690 #define MIPS_ARCH_OPTION_SPEC \
691 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
692
693 /* A spec that infers a -mips argument from an -march argument,
694 or injects the default if no architecture is specified. */
695
696 #define MIPS_ISA_LEVEL_SPEC \
697 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
698 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
699 %{march=mips2|march=r6000:-mips2} \
700 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
701 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
702 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
703 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
704 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
705 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
706 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
707 |march=xlr|march=loongson3a: -mips64} \
708 %{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
709 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
710
711 /* A spec that infers a -mhard-float or -msoft-float setting from an
712 -march argument. Note that soft-float and hard-float code are not
713 link-compatible. */
714
715 #define MIPS_ARCH_FLOAT_SPEC \
716 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
717 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
718 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
719 |march=octeon|march=xlr: -msoft-float; \
720 march=*: -mhard-float}"
721
722 /* A spec condition that matches 32-bit options. It only works if
723 MIPS_ISA_LEVEL_SPEC has been applied. */
724
725 #define MIPS_32BIT_OPTION_SPEC \
726 "mips1|mips2|mips32*|mgp32"
727
728 #if MIPS_ABI_DEFAULT == ABI_O64 \
729 || MIPS_ABI_DEFAULT == ABI_N32 \
730 || MIPS_ABI_DEFAULT == ABI_64
731 #define OPT_ARCH64 "mabi=32|mgp32:;"
732 #define OPT_ARCH32 "mabi=32|mgp32"
733 #else
734 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
735 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
736 #endif
737
738 /* Support for a compile-time default CPU, et cetera. The rules are:
739 --with-arch is ignored if -march is specified or a -mips is specified
740 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
741 --with-tune is ignored if -mtune is specified; likewise
742 --with-tune-32 and --with-tune-64.
743 --with-abi is ignored if -mabi is specified.
744 --with-float is ignored if -mhard-float or -msoft-float are
745 specified.
746 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
747 specified. */
748 #define OPTION_DEFAULT_SPECS \
749 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
750 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
751 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
752 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
753 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
754 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
755 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
756 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
757 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
758 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
759 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
760 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
761
762
763 /* A spec that infers the -mdsp setting from an -march argument. */
764 #define BASE_DRIVER_SELF_SPECS \
765 "%{!mno-dsp: \
766 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
767 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
768
769 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
770
771 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
772 && ISA_HAS_COND_TRAP)
773
774 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
775
776 /* True if the ABI can only work with 64-bit integer registers. We
777 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
778 otherwise floating-point registers must also be 64-bit. */
779 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
780
781 /* Likewise for 32-bit regs. */
782 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
783
784 /* True if the file format uses 64-bit symbols. At present, this is
785 only true for n64, which uses 64-bit ELF. */
786 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
787
788 /* True if symbols are 64 bits wide. This is usually determined by
789 the ABI's file format, but it can be overridden by -msym32. Note that
790 overriding the size with -msym32 changes the ABI of relocatable objects,
791 although it doesn't change the ABI of a fully-linked object. */
792 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
793 && Pmode == DImode \
794 && !TARGET_SYM32)
795
796 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
797 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
798 || ISA_MIPS4 \
799 || ISA_MIPS64 \
800 || ISA_MIPS64R2)
801
802 /* ISA has branch likely instructions (e.g. mips2). */
803 /* Disable branchlikely for tx39 until compare rewrite. They haven't
804 been generated up to this point. */
805 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
806
807 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
808 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
809 || TARGET_MIPS5400 \
810 || TARGET_MIPS5500 \
811 || TARGET_MIPS7000 \
812 || TARGET_MIPS9000 \
813 || TARGET_MAD \
814 || ISA_MIPS32 \
815 || ISA_MIPS32R2 \
816 || ISA_MIPS64 \
817 || ISA_MIPS64R2) \
818 && !TARGET_MIPS16)
819
820 /* ISA has a three-operand multiplication instruction. */
821 #define ISA_HAS_DMUL3 (TARGET_64BIT \
822 && TARGET_OCTEON \
823 && !TARGET_MIPS16)
824
825 /* ISA has the floating-point conditional move instructions introduced
826 in mips4. */
827 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
828 || ISA_MIPS32 \
829 || ISA_MIPS32R2 \
830 || ISA_MIPS64 \
831 || ISA_MIPS64R2) \
832 && !TARGET_MIPS5500 \
833 && !TARGET_MIPS16)
834
835 /* ISA has the integer conditional move instructions introduced in mips4 and
836 ST Loongson 2E/2F. */
837 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
838
839 /* ISA has LDC1 and SDC1. */
840 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
841
842 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
843 branch on CC, and move (both FP and non-FP) on CC. */
844 #define ISA_HAS_8CC (ISA_MIPS4 \
845 || ISA_MIPS32 \
846 || ISA_MIPS32R2 \
847 || ISA_MIPS64 \
848 || ISA_MIPS64R2)
849
850 /* This is a catch all for other mips4 instructions: indexed load, the
851 FP madd and msub instructions, and the FP recip and recip sqrt
852 instructions. */
853 #define ISA_HAS_FP4 ((ISA_MIPS4 \
854 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
855 || ISA_MIPS64 \
856 || ISA_MIPS64R2) \
857 && !TARGET_MIPS16)
858
859 /* ISA has paired-single instructions. */
860 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
861
862 /* ISA has conditional trap instructions. */
863 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
864 && !TARGET_MIPS16)
865
866 /* ISA has integer multiply-accumulate instructions, madd and msub. */
867 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
868 || ISA_MIPS32R2 \
869 || ISA_MIPS64 \
870 || ISA_MIPS64R2) \
871 && !TARGET_MIPS16)
872
873 /* Integer multiply-accumulate instructions should be generated. */
874 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
875
876 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
877 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
878
879 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
880 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
881
882 /* ISA has floating-point nmadd and nmsub instructions
883 'd = -((a * b) [+-] c)'. */
884 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
885 ((ISA_MIPS4 \
886 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
887 || ISA_MIPS64 \
888 || ISA_MIPS64R2) \
889 && (!TARGET_MIPS5400 || TARGET_MAD) \
890 && !TARGET_MIPS16)
891
892 /* ISA has floating-point nmadd and nmsub instructions
893 'c = -((a * b) [+-] c)'. */
894 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
895 TARGET_LOONGSON_2EF
896
897 /* ISA has count leading zeroes/ones instruction (not implemented). */
898 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
899 || ISA_MIPS32R2 \
900 || ISA_MIPS64 \
901 || ISA_MIPS64R2) \
902 && !TARGET_MIPS16)
903
904 /* ISA has three operand multiply instructions that put
905 the high part in an accumulator: mulhi or mulhiu. */
906 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
907 || TARGET_MIPS5500 \
908 || TARGET_SR71K) \
909 && !TARGET_MIPS16)
910
911 /* ISA has three operand multiply instructions that
912 negates the result and puts the result in an accumulator. */
913 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
914 || TARGET_MIPS5500 \
915 || TARGET_SR71K) \
916 && !TARGET_MIPS16)
917
918 /* ISA has three operand multiply instructions that subtracts the
919 result from a 4th operand and puts the result in an accumulator. */
920 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
921 || TARGET_MIPS5500 \
922 || TARGET_SR71K) \
923 && !TARGET_MIPS16)
924
925 /* ISA has three operand multiply instructions that the result
926 from a 4th operand and puts the result in an accumulator. */
927 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
928 || TARGET_MIPS4130 \
929 || TARGET_MIPS5400 \
930 || TARGET_MIPS5500 \
931 || TARGET_SR71K) \
932 && !TARGET_MIPS16)
933
934 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
935 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
936 || TARGET_MIPS4130) \
937 && !TARGET_MIPS16)
938
939 /* ISA has the "ror" (rotate right) instructions. */
940 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
941 || ISA_MIPS64R2 \
942 || TARGET_MIPS5400 \
943 || TARGET_MIPS5500 \
944 || TARGET_SR71K \
945 || TARGET_SMARTMIPS) \
946 && !TARGET_MIPS16)
947
948 /* ISA has data prefetch instructions. This controls use of 'pref'. */
949 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
950 || TARGET_LOONGSON_2EF \
951 || ISA_MIPS32 \
952 || ISA_MIPS32R2 \
953 || ISA_MIPS64 \
954 || ISA_MIPS64R2) \
955 && !TARGET_MIPS16)
956
957 /* ISA has data indexed prefetch instructions. This controls use of
958 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
959 (prefx is a cop1x instruction, so can only be used if FP is
960 enabled.) */
961 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
962 || ISA_MIPS32R2 \
963 || ISA_MIPS64 \
964 || ISA_MIPS64R2) \
965 && !TARGET_MIPS16)
966
967 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
968 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
969 also requires TARGET_DOUBLE_FLOAT. */
970 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
971
972 /* ISA includes the MIPS32r2 seb and seh instructions. */
973 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
974 || ISA_MIPS64R2) \
975 && !TARGET_MIPS16)
976
977 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
978 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
979 || ISA_MIPS64R2) \
980 && !TARGET_MIPS16)
981
982 /* ISA has instructions for accessing top part of 64-bit fp regs. */
983 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
984 && (ISA_MIPS32R2 \
985 || ISA_MIPS64R2))
986
987 /* ISA has lwxs instruction (load w/scaled index address. */
988 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
989
990 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
991 #define ISA_HAS_LBX (TARGET_OCTEON2)
992 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
993 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
994 #define ISA_HAS_LHUX (TARGET_OCTEON2)
995 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
996 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
997 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
998 && TARGET_64BIT)
999
1000 /* The DSP ASE is available. */
1001 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1002
1003 /* Revision 2 of the DSP ASE is available. */
1004 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1005
1006 /* True if the result of a load is not available to the next instruction.
1007 A nop will then be needed between instructions like "lw $4,..."
1008 and "addiu $4,$4,1". */
1009 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1010 && !TARGET_MIPS3900 \
1011 && !TARGET_MIPS16)
1012
1013 /* Likewise mtc1 and mfc1. */
1014 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1015 && !TARGET_LOONGSON_2EF)
1016
1017 /* Likewise floating-point comparisons. */
1018 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1019 && !TARGET_LOONGSON_2EF)
1020
1021 /* True if mflo and mfhi can be immediately followed by instructions
1022 which write to the HI and LO registers.
1023
1024 According to MIPS specifications, MIPS ISAs I, II, and III need
1025 (at least) two instructions between the reads of HI/LO and
1026 instructions which write them, and later ISAs do not. Contradicting
1027 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1028 the UM for the NEC Vr5000) document needing the instructions between
1029 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1030 MIPS64 and later ISAs to have the interlocks, plus any specific
1031 earlier-ISA CPUs for which CPU documentation declares that the
1032 instructions are really interlocked. */
1033 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1034 || ISA_MIPS32R2 \
1035 || ISA_MIPS64 \
1036 || ISA_MIPS64R2 \
1037 || TARGET_MIPS5500 \
1038 || TARGET_LOONGSON_2EF)
1039
1040 /* ISA includes synci, jr.hb and jalr.hb. */
1041 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1042 || ISA_MIPS64R2) \
1043 && !TARGET_MIPS16)
1044
1045 /* ISA includes sync. */
1046 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1047 #define GENERATE_SYNC \
1048 (target_flags_explicit & MASK_LLSC \
1049 ? TARGET_LLSC && !TARGET_MIPS16 \
1050 : ISA_HAS_SYNC)
1051
1052 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1053 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1054 instructions. */
1055 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1056 #define GENERATE_LL_SC \
1057 (target_flags_explicit & MASK_LLSC \
1058 ? TARGET_LLSC && !TARGET_MIPS16 \
1059 : ISA_HAS_LL_SC)
1060
1061 #define ISA_HAS_SWAP (TARGET_XLP)
1062 #define ISA_HAS_LDADD (TARGET_XLP)
1063
1064 /* ISA includes the baddu instruction. */
1065 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1066
1067 /* ISA includes the bbit* instructions. */
1068 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1069
1070 /* ISA includes the cins instruction. */
1071 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1072
1073 /* ISA includes the exts instruction. */
1074 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1075
1076 /* ISA includes the seq and sne instructions. */
1077 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1078
1079 /* ISA includes the pop instruction. */
1080 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1081
1082 /* The CACHE instruction is available in non-MIPS16 code. */
1083 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1084
1085 /* The CACHE instruction is available. */
1086 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1087 \f
1088 /* Tell collect what flags to pass to nm. */
1089 #ifndef NM_FLAGS
1090 #define NM_FLAGS "-Bn"
1091 #endif
1092
1093 \f
1094 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1095 the assembler. It may be overridden by subtargets.
1096
1097 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1098 COFF debugging info. */
1099
1100 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1101 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1102 %{g} %{g0} %{g1} %{g2} %{g3} \
1103 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1104 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1105 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1106 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1107 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1108 #endif
1109
1110 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1111 overridden by subtargets. */
1112
1113 #ifndef SUBTARGET_ASM_SPEC
1114 #define SUBTARGET_ASM_SPEC ""
1115 #endif
1116
1117 #undef ASM_SPEC
1118 #define ASM_SPEC "\
1119 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1120 %{mips32*} %{mips64*} \
1121 %{mips16} %{mno-mips16:-no-mips16} \
1122 %{mips3d} %{mno-mips3d:-no-mips3d} \
1123 %{mdmx} %{mno-mdmx:-no-mdmx} \
1124 %{mdsp} %{mno-dsp} \
1125 %{mdspr2} %{mno-dspr2} \
1126 %{mmcu} %{mno-mcu} \
1127 %{msmartmips} %{mno-smartmips} \
1128 %{mmt} %{mno-mt} \
1129 %{mfix-vr4120} %{mfix-vr4130} \
1130 %{mfix-24k} \
1131 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1132 %(subtarget_asm_debugging_spec) \
1133 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1134 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1135 %{mfp32} %{mfp64} \
1136 %{mshared} %{mno-shared} \
1137 %{msym32} %{mno-sym32} \
1138 %{mtune=*} \
1139 %(subtarget_asm_spec)"
1140
1141 /* Extra switches sometimes passed to the linker. */
1142
1143 #ifndef LINK_SPEC
1144 #define LINK_SPEC "\
1145 %(endian_spec) \
1146 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1147 %{shared}"
1148 #endif /* LINK_SPEC defined */
1149
1150
1151 /* Specs for the compiler proper */
1152
1153 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1154 overridden by subtargets. */
1155 #ifndef SUBTARGET_CC1_SPEC
1156 #define SUBTARGET_CC1_SPEC ""
1157 #endif
1158
1159 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1160
1161 #undef CC1_SPEC
1162 #define CC1_SPEC "\
1163 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1164 %(subtarget_cc1_spec)"
1165
1166 /* Preprocessor specs. */
1167
1168 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1169 overridden by subtargets. */
1170 #ifndef SUBTARGET_CPP_SPEC
1171 #define SUBTARGET_CPP_SPEC ""
1172 #endif
1173
1174 #define CPP_SPEC "%(subtarget_cpp_spec)"
1175
1176 /* This macro defines names of additional specifications to put in the specs
1177 that can be used in various specifications like CC1_SPEC. Its definition
1178 is an initializer with a subgrouping for each command option.
1179
1180 Each subgrouping contains a string constant, that defines the
1181 specification name, and a string constant that used by the GCC driver
1182 program.
1183
1184 Do not define this macro if it does not need to do anything. */
1185
1186 #define EXTRA_SPECS \
1187 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1188 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1189 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1190 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1191 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1192 { "endian_spec", ENDIAN_SPEC }, \
1193 SUBTARGET_EXTRA_SPECS
1194
1195 #ifndef SUBTARGET_EXTRA_SPECS
1196 #define SUBTARGET_EXTRA_SPECS
1197 #endif
1198 \f
1199 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1200 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1201
1202 #ifndef PREFERRED_DEBUGGING_TYPE
1203 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1204 #endif
1205
1206 /* The size of DWARF addresses should be the same as the size of symbols
1207 in the target file format. They shouldn't depend on things like -msym32,
1208 because many DWARF consumers do not allow the mixture of address sizes
1209 that one would then get from linking -msym32 code with -msym64 code.
1210
1211 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1212 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1213 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1214
1215 /* By default, turn on GDB extensions. */
1216 #define DEFAULT_GDB_EXTENSIONS 1
1217
1218 /* Local compiler-generated symbols must have a prefix that the assembler
1219 understands. By default, this is $, although some targets (e.g.,
1220 NetBSD-ELF) need to override this. */
1221
1222 #ifndef LOCAL_LABEL_PREFIX
1223 #define LOCAL_LABEL_PREFIX "$"
1224 #endif
1225
1226 /* By default on the mips, external symbols do not have an underscore
1227 prepended, but some targets (e.g., NetBSD) require this. */
1228
1229 #ifndef USER_LABEL_PREFIX
1230 #define USER_LABEL_PREFIX ""
1231 #endif
1232
1233 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1234 since the length can run past this up to a continuation point. */
1235 #undef DBX_CONTIN_LENGTH
1236 #define DBX_CONTIN_LENGTH 1500
1237
1238 /* How to renumber registers for dbx and gdb. */
1239 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1240
1241 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1242 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1243
1244 /* The DWARF 2 CFA column which tracks the return address. */
1245 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1246
1247 /* Before the prologue, RA lives in r31. */
1248 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1249
1250 /* Describe how we implement __builtin_eh_return. */
1251 #define EH_RETURN_DATA_REGNO(N) \
1252 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1253
1254 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1255
1256 #define EH_USES(N) mips_eh_uses (N)
1257
1258 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1259 The default for this in 64-bit mode is 8, which causes problems with
1260 SFmode register saves. */
1261 #define DWARF_CIE_DATA_ALIGNMENT -4
1262
1263 /* Correct the offset of automatic variables and arguments. Note that
1264 the MIPS debug format wants all automatic variables and arguments
1265 to be in terms of the virtual frame pointer (stack pointer before
1266 any adjustment in the function), while the MIPS 3.0 linker wants
1267 the frame pointer to be the stack pointer after the initial
1268 adjustment. */
1269
1270 #define DEBUGGER_AUTO_OFFSET(X) \
1271 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1272 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1273 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1274 \f
1275 /* Target machine storage layout */
1276
1277 #define BITS_BIG_ENDIAN 0
1278 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1279 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1280
1281 #define MAX_BITS_PER_WORD 64
1282
1283 /* Width of a word, in units (bytes). */
1284 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1285 #ifndef IN_LIBGCC2
1286 #define MIN_UNITS_PER_WORD 4
1287 #endif
1288
1289 /* For MIPS, width of a floating point register. */
1290 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1291
1292 /* The number of consecutive floating-point registers needed to store the
1293 largest format supported by the FPU. */
1294 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1295
1296 /* The number of consecutive floating-point registers needed to store the
1297 smallest format supported by the FPU. */
1298 #define MIN_FPRS_PER_FMT \
1299 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1300 ? 1 : MAX_FPRS_PER_FMT)
1301
1302 /* The largest size of value that can be held in floating-point
1303 registers and moved with a single instruction. */
1304 #define UNITS_PER_HWFPVALUE \
1305 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1306
1307 /* The largest size of value that can be held in floating-point
1308 registers. */
1309 #define UNITS_PER_FPVALUE \
1310 (TARGET_SOFT_FLOAT_ABI ? 0 \
1311 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1312 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1313
1314 /* The number of bytes in a double. */
1315 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1316
1317 /* Set the sizes of the core types. */
1318 #define SHORT_TYPE_SIZE 16
1319 #define INT_TYPE_SIZE 32
1320 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1321 #define LONG_LONG_TYPE_SIZE 64
1322
1323 #define FLOAT_TYPE_SIZE 32
1324 #define DOUBLE_TYPE_SIZE 64
1325 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1326
1327 /* Define the sizes of fixed-point types. */
1328 #define SHORT_FRACT_TYPE_SIZE 8
1329 #define FRACT_TYPE_SIZE 16
1330 #define LONG_FRACT_TYPE_SIZE 32
1331 #define LONG_LONG_FRACT_TYPE_SIZE 64
1332
1333 #define SHORT_ACCUM_TYPE_SIZE 16
1334 #define ACCUM_TYPE_SIZE 32
1335 #define LONG_ACCUM_TYPE_SIZE 64
1336 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1337 doesn't support 128-bit integers for MIPS32 currently. */
1338 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1339
1340 /* long double is not a fixed mode, but the idea is that, if we
1341 support long double, we also want a 128-bit integer type. */
1342 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1343
1344 #ifdef IN_LIBGCC2
1345 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1346 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1347 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1348 # else
1349 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1350 # endif
1351 #endif
1352
1353 /* Width in bits of a pointer. */
1354 #ifndef POINTER_SIZE
1355 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1356 #endif
1357
1358 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1359 #define PARM_BOUNDARY BITS_PER_WORD
1360
1361 /* Allocation boundary (in *bits*) for the code of a function. */
1362 #define FUNCTION_BOUNDARY 32
1363
1364 /* Alignment of field after `int : 0' in a structure. */
1365 #define EMPTY_FIELD_BOUNDARY 32
1366
1367 /* Every structure's size must be a multiple of this. */
1368 /* 8 is observed right on a DECstation and on riscos 4.02. */
1369 #define STRUCTURE_SIZE_BOUNDARY 8
1370
1371 /* There is no point aligning anything to a rounder boundary than this. */
1372 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1373
1374 /* All accesses must be aligned. */
1375 #define STRICT_ALIGNMENT 1
1376
1377 /* Define this if you wish to imitate the way many other C compilers
1378 handle alignment of bitfields and the structures that contain
1379 them.
1380
1381 The behavior is that the type written for a bit-field (`int',
1382 `short', or other integer type) imposes an alignment for the
1383 entire structure, as if the structure really did contain an
1384 ordinary field of that type. In addition, the bit-field is placed
1385 within the structure so that it would fit within such a field,
1386 not crossing a boundary for it.
1387
1388 Thus, on most machines, a bit-field whose type is written as `int'
1389 would not cross a four-byte boundary, and would force four-byte
1390 alignment for the whole structure. (The alignment used may not
1391 be four bytes; it is controlled by the other alignment
1392 parameters.)
1393
1394 If the macro is defined, its definition should be a C expression;
1395 a nonzero value for the expression enables this behavior. */
1396
1397 #define PCC_BITFIELD_TYPE_MATTERS 1
1398
1399 /* If defined, a C expression to compute the alignment given to a
1400 constant that is being placed in memory. CONSTANT is the constant
1401 and ALIGN is the alignment that the object would ordinarily have.
1402 The value of this macro is used instead of that alignment to align
1403 the object.
1404
1405 If this macro is not defined, then ALIGN is used.
1406
1407 The typical use of this macro is to increase alignment for string
1408 constants to be word aligned so that `strcpy' calls that copy
1409 constants can be done inline. */
1410
1411 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1412 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1413 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1414
1415 /* If defined, a C expression to compute the alignment for a static
1416 variable. TYPE is the data type, and ALIGN is the alignment that
1417 the object would ordinarily have. The value of this macro is used
1418 instead of that alignment to align the object.
1419
1420 If this macro is not defined, then ALIGN is used.
1421
1422 One use of this macro is to increase alignment of medium-size
1423 data to make it all fit in fewer cache lines. Another is to
1424 cause character arrays to be word-aligned so that `strcpy' calls
1425 that copy constants to character arrays can be done inline. */
1426
1427 #undef DATA_ALIGNMENT
1428 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1429 ((((ALIGN) < BITS_PER_WORD) \
1430 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1431 || TREE_CODE (TYPE) == UNION_TYPE \
1432 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1433
1434 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1435 character arrays to be word-aligned so that `strcpy' calls that copy
1436 constants to character arrays can be done inline, and 'strcmp' can be
1437 optimised to use word loads. */
1438 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1439 DATA_ALIGNMENT (TYPE, ALIGN)
1440
1441 #define PAD_VARARGS_DOWN \
1442 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1443
1444 /* Define if operations between registers always perform the operation
1445 on the full register even if a narrower mode is specified. */
1446 #define WORD_REGISTER_OPERATIONS
1447
1448 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1449 moves. All other references are zero extended. */
1450 #define LOAD_EXTEND_OP(MODE) \
1451 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1452 ? SIGN_EXTEND : ZERO_EXTEND)
1453
1454 /* Define this macro if it is advisable to hold scalars in registers
1455 in a wider mode than that declared by the program. In such cases,
1456 the value is constrained to be within the bounds of the declared
1457 type, but kept valid in the wider mode. The signedness of the
1458 extension may differ from that of the type. */
1459
1460 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1461 if (GET_MODE_CLASS (MODE) == MODE_INT \
1462 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1463 { \
1464 if ((MODE) == SImode) \
1465 (UNSIGNEDP) = 0; \
1466 (MODE) = Pmode; \
1467 }
1468
1469 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1470 Extensions of pointers to word_mode must be signed. */
1471 #define POINTERS_EXTEND_UNSIGNED false
1472
1473 /* Define if loading short immediate values into registers sign extends. */
1474 #define SHORT_IMMEDIATES_SIGN_EXTEND
1475
1476 /* The [d]clz instructions have the natural values at 0. */
1477
1478 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1479 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1480 \f
1481 /* Standard register usage. */
1482
1483 /* Number of hardware registers. We have:
1484
1485 - 32 integer registers
1486 - 32 floating point registers
1487 - 8 condition code registers
1488 - 2 accumulator registers (hi and lo)
1489 - 32 registers each for coprocessors 0, 2 and 3
1490 - 4 fake registers:
1491 - ARG_POINTER_REGNUM
1492 - FRAME_POINTER_REGNUM
1493 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1494 - CPRESTORE_SLOT_REGNUM
1495 - 2 dummy entries that were used at various times in the past.
1496 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1497 - 6 DSP control registers */
1498
1499 #define FIRST_PSEUDO_REGISTER 188
1500
1501 /* By default, fix the kernel registers ($26 and $27), the global
1502 pointer ($28) and the stack pointer ($29). This can change
1503 depending on the command-line options.
1504
1505 Regarding coprocessor registers: without evidence to the contrary,
1506 it's best to assume that each coprocessor register has a unique
1507 use. This can be overridden, in, e.g., mips_option_override or
1508 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1509 inappropriate for a particular target. */
1510
1511 #define FIXED_REGISTERS \
1512 { \
1513 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1514 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1515 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1516 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1517 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1518 /* COP0 registers */ \
1519 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1520 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1521 /* COP2 registers */ \
1522 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1523 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1524 /* COP3 registers */ \
1525 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1526 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1527 /* 6 DSP accumulator registers & 6 control registers */ \
1528 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1529 }
1530
1531
1532 /* Set up this array for o32 by default.
1533
1534 Note that we don't mark $31 as a call-clobbered register. The idea is
1535 that it's really the call instructions themselves which clobber $31.
1536 We don't care what the called function does with it afterwards.
1537
1538 This approach makes it easier to implement sibcalls. Unlike normal
1539 calls, sibcalls don't clobber $31, so the register reaches the
1540 called function in tact. EPILOGUE_USES says that $31 is useful
1541 to the called function. */
1542
1543 #define CALL_USED_REGISTERS \
1544 { \
1545 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1546 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1547 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1548 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1550 /* COP0 registers */ \
1551 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1553 /* COP2 registers */ \
1554 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1555 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1556 /* COP3 registers */ \
1557 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1558 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1559 /* 6 DSP accumulator registers & 6 control registers */ \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1561 }
1562
1563
1564 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1565
1566 #define CALL_REALLY_USED_REGISTERS \
1567 { /* General registers. */ \
1568 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1569 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1570 /* Floating-point registers. */ \
1571 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1572 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1573 /* Others. */ \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1575 /* COP0 registers */ \
1576 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1577 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1578 /* COP2 registers */ \
1579 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1580 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1581 /* COP3 registers */ \
1582 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1583 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1584 /* 6 DSP accumulator registers & 6 control registers */ \
1585 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1586 }
1587
1588 /* Internal macros to classify a register number as to whether it's a
1589 general purpose register, a floating point register, a
1590 multiply/divide register, or a status register. */
1591
1592 #define GP_REG_FIRST 0
1593 #define GP_REG_LAST 31
1594 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1595 #define GP_DBX_FIRST 0
1596 #define K0_REG_NUM (GP_REG_FIRST + 26)
1597 #define K1_REG_NUM (GP_REG_FIRST + 27)
1598 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1599
1600 #define FP_REG_FIRST 32
1601 #define FP_REG_LAST 63
1602 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1603 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1604
1605 #define MD_REG_FIRST 64
1606 #define MD_REG_LAST 65
1607 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1608 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1609
1610 /* The DWARF 2 CFA column which tracks the return address from a
1611 signal handler context. This means that to maintain backwards
1612 compatibility, no hard register can be assigned this column if it
1613 would need to be handled by the DWARF unwinder. */
1614 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1615
1616 #define ST_REG_FIRST 67
1617 #define ST_REG_LAST 74
1618 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1619
1620
1621 /* FIXME: renumber. */
1622 #define COP0_REG_FIRST 80
1623 #define COP0_REG_LAST 111
1624 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1625
1626 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1627 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1628 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1629
1630 #define COP2_REG_FIRST 112
1631 #define COP2_REG_LAST 143
1632 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1633
1634 #define COP3_REG_FIRST 144
1635 #define COP3_REG_LAST 175
1636 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1637 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1638 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1639
1640 #define DSP_ACC_REG_FIRST 176
1641 #define DSP_ACC_REG_LAST 181
1642 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1643
1644 #define AT_REGNUM (GP_REG_FIRST + 1)
1645 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1646 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1647
1648 /* A few bitfield locations for the coprocessor registers. */
1649 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1650 the cause register for the EIC interrupt mode. */
1651 #define CAUSE_IPL 10
1652 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1653 #define SR_IPL 10
1654 /* Exception Level is at bit 1 of the status register. */
1655 #define SR_EXL 1
1656 /* Interrupt Enable is at bit 0 of the status register. */
1657 #define SR_IE 0
1658
1659 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1660 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1661 should be used instead. */
1662 #define FPSW_REGNUM ST_REG_FIRST
1663
1664 #define GP_REG_P(REGNO) \
1665 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1666 #define M16_REG_P(REGNO) \
1667 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1668 #define FP_REG_P(REGNO) \
1669 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1670 #define MD_REG_P(REGNO) \
1671 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1672 #define ST_REG_P(REGNO) \
1673 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1674 #define COP0_REG_P(REGNO) \
1675 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1676 #define COP2_REG_P(REGNO) \
1677 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1678 #define COP3_REG_P(REGNO) \
1679 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1680 #define ALL_COP_REG_P(REGNO) \
1681 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1682 /* Test if REGNO is one of the 6 new DSP accumulators. */
1683 #define DSP_ACC_REG_P(REGNO) \
1684 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1685 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1686 #define ACC_REG_P(REGNO) \
1687 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1688
1689 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1690
1691 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1692 to initialize the mips16 gp pseudo register. */
1693 #define CONST_GP_P(X) \
1694 (GET_CODE (X) == CONST \
1695 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1696 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1697
1698 /* Return coprocessor number from register number. */
1699
1700 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1701 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1702 : COP3_REG_P (REGNO) ? '3' : '?')
1703
1704
1705 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1706
1707 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1708 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1709
1710 #define MODES_TIEABLE_P mips_modes_tieable_p
1711
1712 /* Register to use for pushing function arguments. */
1713 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1714
1715 /* These two registers don't really exist: they get eliminated to either
1716 the stack or hard frame pointer. */
1717 #define ARG_POINTER_REGNUM 77
1718 #define FRAME_POINTER_REGNUM 78
1719
1720 /* $30 is not available on the mips16, so we use $17 as the frame
1721 pointer. */
1722 #define HARD_FRAME_POINTER_REGNUM \
1723 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1724
1725 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1726 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1727
1728 /* Register in which static-chain is passed to a function. */
1729 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1730
1731 /* Registers used as temporaries in prologue/epilogue code:
1732
1733 - If a MIPS16 PIC function needs access to _gp, it first loads
1734 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1735
1736 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1737 register. The register must not conflict with MIPS16_PIC_TEMP.
1738
1739 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1740 register.
1741
1742 If we're generating MIPS16 code, these registers must come from the
1743 core set of 8. The prologue registers mustn't conflict with any
1744 incoming arguments, the static chain pointer, or the frame pointer.
1745 The epilogue temporary mustn't conflict with the return registers,
1746 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1747 or the EH data registers.
1748
1749 If we're generating interrupt handlers, we use K0 as a temporary register
1750 in prologue/epilogue code. */
1751
1752 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1753 #define MIPS_PROLOGUE_TEMP_REGNUM \
1754 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1755 #define MIPS_EPILOGUE_TEMP_REGNUM \
1756 (cfun->machine->interrupt_handler_p \
1757 ? K0_REG_NUM \
1758 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1759
1760 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1761 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1762 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1763
1764 /* Define this macro if it is as good or better to call a constant
1765 function address than to call an address kept in a register. */
1766 #define NO_FUNCTION_CSE 1
1767
1768 /* The ABI-defined global pointer. Sometimes we use a different
1769 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1770 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1771
1772 /* We normally use $28 as the global pointer. However, when generating
1773 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1774 register instead. They can then avoid saving and restoring $28
1775 and perhaps avoid using a frame at all.
1776
1777 When a leaf function uses something other than $28, mips_expand_prologue
1778 will modify pic_offset_table_rtx in place. Take the register number
1779 from there after reload. */
1780 #define PIC_OFFSET_TABLE_REGNUM \
1781 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1782 \f
1783 /* Define the classes of registers for register constraints in the
1784 machine description. Also define ranges of constants.
1785
1786 One of the classes must always be named ALL_REGS and include all hard regs.
1787 If there is more than one class, another class must be named NO_REGS
1788 and contain no registers.
1789
1790 The name GENERAL_REGS must be the name of a class (or an alias for
1791 another name such as ALL_REGS). This is the class of registers
1792 that is allowed by "g" or "r" in a register constraint.
1793 Also, registers outside this class are allocated only when
1794 instructions express preferences for them.
1795
1796 The classes must be numbered in nondecreasing order; that is,
1797 a larger-numbered class must never be contained completely
1798 in a smaller-numbered class.
1799
1800 For any two classes, it is very desirable that there be another
1801 class that represents their union. */
1802
1803 enum reg_class
1804 {
1805 NO_REGS, /* no registers in set */
1806 M16_REGS, /* mips16 directly accessible registers */
1807 T_REG, /* mips16 T register ($24) */
1808 M16_T_REGS, /* mips16 registers plus T register */
1809 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1810 V1_REG, /* Register $v1 ($3) used for TLS access. */
1811 LEA_REGS, /* Every GPR except $25 */
1812 GR_REGS, /* integer registers */
1813 FP_REGS, /* floating point registers */
1814 MD0_REG, /* first multiply/divide register */
1815 MD1_REG, /* second multiply/divide register */
1816 MD_REGS, /* multiply/divide registers (hi/lo) */
1817 COP0_REGS, /* generic coprocessor classes */
1818 COP2_REGS,
1819 COP3_REGS,
1820 ST_REGS, /* status registers (fp status) */
1821 DSP_ACC_REGS, /* DSP accumulator registers */
1822 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1823 FRAME_REGS, /* $arg and $frame */
1824 GR_AND_MD0_REGS, /* union classes */
1825 GR_AND_MD1_REGS,
1826 GR_AND_MD_REGS,
1827 GR_AND_ACC_REGS,
1828 ALL_REGS, /* all registers */
1829 LIM_REG_CLASSES /* max value + 1 */
1830 };
1831
1832 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1833
1834 #define GENERAL_REGS GR_REGS
1835
1836 /* An initializer containing the names of the register classes as C
1837 string constants. These names are used in writing some of the
1838 debugging dumps. */
1839
1840 #define REG_CLASS_NAMES \
1841 { \
1842 "NO_REGS", \
1843 "M16_REGS", \
1844 "T_REG", \
1845 "M16_T_REGS", \
1846 "PIC_FN_ADDR_REG", \
1847 "V1_REG", \
1848 "LEA_REGS", \
1849 "GR_REGS", \
1850 "FP_REGS", \
1851 "MD0_REG", \
1852 "MD1_REG", \
1853 "MD_REGS", \
1854 /* coprocessor registers */ \
1855 "COP0_REGS", \
1856 "COP2_REGS", \
1857 "COP3_REGS", \
1858 "ST_REGS", \
1859 "DSP_ACC_REGS", \
1860 "ACC_REGS", \
1861 "FRAME_REGS", \
1862 "GR_AND_MD0_REGS", \
1863 "GR_AND_MD1_REGS", \
1864 "GR_AND_MD_REGS", \
1865 "GR_AND_ACC_REGS", \
1866 "ALL_REGS" \
1867 }
1868
1869 /* An initializer containing the contents of the register classes,
1870 as integers which are bit masks. The Nth integer specifies the
1871 contents of class N. The way the integer MASK is interpreted is
1872 that register R is in the class if `MASK & (1 << R)' is 1.
1873
1874 When the machine has more than 32 registers, an integer does not
1875 suffice. Then the integers are replaced by sub-initializers,
1876 braced groupings containing several integers. Each
1877 sub-initializer must be suitable as an initializer for the type
1878 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1879
1880 #define REG_CLASS_CONTENTS \
1881 { \
1882 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1883 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1884 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1885 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1886 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1887 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1888 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1889 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1890 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1891 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1892 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1893 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1894 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1895 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1896 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1897 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1898 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1899 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1900 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1901 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1902 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1903 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1904 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1905 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1906 }
1907
1908
1909 /* A C expression whose value is a register class containing hard
1910 register REGNO. In general there is more that one such class;
1911 choose a class which is "minimal", meaning that no smaller class
1912 also contains the register. */
1913
1914 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1915
1916 /* A macro whose definition is the name of the class to which a
1917 valid base register must belong. A base register is one used in
1918 an address which is the register value plus a displacement. */
1919
1920 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1921
1922 /* A macro whose definition is the name of the class to which a
1923 valid index register must belong. An index register is one used
1924 in an address where its value is either multiplied by a scale
1925 factor or added to another register (as well as added to a
1926 displacement). */
1927
1928 #define INDEX_REG_CLASS NO_REGS
1929
1930 /* We generally want to put call-clobbered registers ahead of
1931 call-saved ones. (IRA expects this.) */
1932
1933 #define REG_ALLOC_ORDER \
1934 { /* Accumulator registers. When GPRs and accumulators have equal \
1935 cost, we generally prefer to use accumulators. For example, \
1936 a division of multiplication result is better allocated to LO, \
1937 so that we put the MFLO at the point of use instead of at the \
1938 point of definition. It's also needed if we're to take advantage \
1939 of the extra accumulators available with -mdspr2. In some cases, \
1940 it can also help to reduce register pressure. */ \
1941 64, 65,176,177,178,179,180,181, \
1942 /* Call-clobbered GPRs. */ \
1943 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1944 24, 25, 31, \
1945 /* The global pointer. This is call-clobbered for o32 and o64 \
1946 abicalls, call-saved for n32 and n64 abicalls, and a program \
1947 invariant otherwise. Putting it between the call-clobbered \
1948 and call-saved registers should cope with all eventualities. */ \
1949 28, \
1950 /* Call-saved GPRs. */ \
1951 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1952 /* GPRs that can never be exposed to the register allocator. */ \
1953 0, 26, 27, 29, \
1954 /* Call-clobbered FPRs. */ \
1955 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1956 48, 49, 50, 51, \
1957 /* FPRs that are usually call-saved. The odd ones are actually \
1958 call-clobbered for n32, but listing them ahead of the even \
1959 registers might encourage the register allocator to fragment \
1960 the available FPR pairs. We need paired FPRs to store long \
1961 doubles, so it isn't clear that using a different order \
1962 for n32 would be a win. */ \
1963 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1964 /* None of the remaining classes have defined call-saved \
1965 registers. */ \
1966 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1967 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1968 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1969 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1970 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1971 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1972 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1973 182,183,184,185,186,187 \
1974 }
1975
1976 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1977 to be rearranged based on a particular function. On the mips16, we
1978 want to allocate $24 (T_REG) before other registers for
1979 instructions for which it is possible. */
1980
1981 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
1982
1983 /* True if VALUE is an unsigned 6-bit number. */
1984
1985 #define UIMM6_OPERAND(VALUE) \
1986 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1987
1988 /* True if VALUE is a signed 10-bit number. */
1989
1990 #define IMM10_OPERAND(VALUE) \
1991 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1992
1993 /* True if VALUE is a signed 16-bit number. */
1994
1995 #define SMALL_OPERAND(VALUE) \
1996 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1997
1998 /* True if VALUE is an unsigned 16-bit number. */
1999
2000 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2001 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2002
2003 /* True if VALUE can be loaded into a register using LUI. */
2004
2005 #define LUI_OPERAND(VALUE) \
2006 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2007 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2008
2009 /* Return a value X with the low 16 bits clear, and such that
2010 VALUE - X is a signed 16-bit value. */
2011
2012 #define CONST_HIGH_PART(VALUE) \
2013 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2014
2015 #define CONST_LOW_PART(VALUE) \
2016 ((VALUE) - CONST_HIGH_PART (VALUE))
2017
2018 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2019 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2020 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2021
2022 /* The HI and LO registers can only be reloaded via the general
2023 registers. Condition code registers can only be loaded to the
2024 general registers, and from the floating point registers. */
2025
2026 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2027 mips_secondary_reload_class (CLASS, MODE, X, true)
2028 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2029 mips_secondary_reload_class (CLASS, MODE, X, false)
2030
2031 /* Return the maximum number of consecutive registers
2032 needed to represent mode MODE in a register of class CLASS. */
2033
2034 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2035
2036 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2037 mips_cannot_change_mode_class (FROM, TO, CLASS)
2038 \f
2039 /* Stack layout; function entry, exit and calling. */
2040
2041 #define STACK_GROWS_DOWNWARD
2042
2043 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2044
2045 /* Size of the area allocated in the frame to save the GP. */
2046
2047 #define MIPS_GP_SAVE_AREA_SIZE \
2048 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2049
2050 /* The offset of the first local variable from the frame pointer. See
2051 mips_compute_frame_info for details about the frame layout. */
2052
2053 #define STARTING_FRAME_OFFSET \
2054 (FRAME_GROWS_DOWNWARD \
2055 ? 0 \
2056 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2057
2058 #define RETURN_ADDR_RTX mips_return_addr
2059
2060 /* Mask off the MIPS16 ISA bit in unwind addresses.
2061
2062 The reason for this is a little subtle. When unwinding a call,
2063 we are given the call's return address, which on most targets
2064 is the address of the following instruction. However, what we
2065 actually want to find is the EH region for the call itself.
2066 The target-independent unwind code therefore searches for "RA - 1".
2067
2068 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2069 RA - 1 is therefore the real (even-valued) start of the return
2070 instruction. EH region labels are usually odd-valued MIPS16 symbols
2071 too, so a search for an even address within a MIPS16 region would
2072 usually work.
2073
2074 However, there is an exception. If the end of an EH region is also
2075 the end of a function, the end label is allowed to be even. This is
2076 necessary because a following non-MIPS16 function may also need EH
2077 information for its first instruction.
2078
2079 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2080 non-ISA-encoded address. This probably isn't ideal, but it is
2081 the traditional (legacy) behavior. It is therefore only safe
2082 to search MIPS EH regions for an _odd-valued_ address.
2083
2084 Masking off the ISA bit means that the target-independent code
2085 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2086 #define MASK_RETURN_ADDR GEN_INT (-2)
2087
2088
2089 /* Similarly, don't use the least-significant bit to tell pointers to
2090 code from vtable index. */
2091
2092 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2093
2094 /* The eliminations to $17 are only used for mips16 code. See the
2095 definition of HARD_FRAME_POINTER_REGNUM. */
2096
2097 #define ELIMINABLE_REGS \
2098 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2099 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2100 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2101 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2102 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2103 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2104
2105 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2106 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2107
2108 /* Allocate stack space for arguments at the beginning of each function. */
2109 #define ACCUMULATE_OUTGOING_ARGS 1
2110
2111 /* The argument pointer always points to the first argument. */
2112 #define FIRST_PARM_OFFSET(FNDECL) 0
2113
2114 /* o32 and o64 reserve stack space for all argument registers. */
2115 #define REG_PARM_STACK_SPACE(FNDECL) \
2116 (TARGET_OLDABI \
2117 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2118 : 0)
2119
2120 /* Define this if it is the responsibility of the caller to
2121 allocate the area reserved for arguments passed in registers.
2122 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2123 of this macro is to determine whether the space is included in
2124 `crtl->outgoing_args_size'. */
2125 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2126
2127 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2128 \f
2129 /* Symbolic macros for the registers used to return integer and floating
2130 point values. */
2131
2132 #define GP_RETURN (GP_REG_FIRST + 2)
2133 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2134
2135 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2136
2137 /* Symbolic macros for the first/last argument registers. */
2138
2139 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2140 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2141 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2142 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2143
2144 /* 1 if N is a possible register number for function argument passing.
2145 We have no FP argument registers when soft-float. When FP registers
2146 are 32 bits, we can't directly reference the odd numbered ones. */
2147
2148 #define FUNCTION_ARG_REGNO_P(N) \
2149 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2150 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2151 && !fixed_regs[N])
2152 \f
2153 /* This structure has to cope with two different argument allocation
2154 schemes. Most MIPS ABIs view the arguments as a structure, of which
2155 the first N words go in registers and the rest go on the stack. If I
2156 < N, the Ith word might go in Ith integer argument register or in a
2157 floating-point register. For these ABIs, we only need to remember
2158 the offset of the current argument into the structure.
2159
2160 The EABI instead allocates the integer and floating-point arguments
2161 separately. The first N words of FP arguments go in FP registers,
2162 the rest go on the stack. Likewise, the first N words of the other
2163 arguments go in integer registers, and the rest go on the stack. We
2164 need to maintain three counts: the number of integer registers used,
2165 the number of floating-point registers used, and the number of words
2166 passed on the stack.
2167
2168 We could keep separate information for the two ABIs (a word count for
2169 the standard ABIs, and three separate counts for the EABI). But it
2170 seems simpler to view the standard ABIs as forms of EABI that do not
2171 allocate floating-point registers.
2172
2173 So for the standard ABIs, the first N words are allocated to integer
2174 registers, and mips_function_arg decides on an argument-by-argument
2175 basis whether that argument should really go in an integer register,
2176 or in a floating-point one. */
2177
2178 typedef struct mips_args {
2179 /* Always true for varargs functions. Otherwise true if at least
2180 one argument has been passed in an integer register. */
2181 int gp_reg_found;
2182
2183 /* The number of arguments seen so far. */
2184 unsigned int arg_number;
2185
2186 /* The number of integer registers used so far. For all ABIs except
2187 EABI, this is the number of words that have been added to the
2188 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2189 unsigned int num_gprs;
2190
2191 /* For EABI, the number of floating-point registers used so far. */
2192 unsigned int num_fprs;
2193
2194 /* The number of words passed on the stack. */
2195 unsigned int stack_words;
2196
2197 /* On the mips16, we need to keep track of which floating point
2198 arguments were passed in general registers, but would have been
2199 passed in the FP regs if this were a 32-bit function, so that we
2200 can move them to the FP regs if we wind up calling a 32-bit
2201 function. We record this information in fp_code, encoded in base
2202 four. A zero digit means no floating point argument, a one digit
2203 means an SFmode argument, and a two digit means a DFmode argument,
2204 and a three digit is not used. The low order digit is the first
2205 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2206 an SFmode argument. ??? A more sophisticated approach will be
2207 needed if MIPS_ABI != ABI_32. */
2208 int fp_code;
2209
2210 /* True if the function has a prototype. */
2211 int prototype;
2212 } CUMULATIVE_ARGS;
2213
2214 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2215 for a call to a function whose data type is FNTYPE.
2216 For a library call, FNTYPE is 0. */
2217
2218 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2219 mips_init_cumulative_args (&CUM, FNTYPE)
2220
2221 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2222 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2223
2224 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2225 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2226
2227 /* True if using EABI and varargs can be passed in floating-point
2228 registers. Under these conditions, we need a more complex form
2229 of va_list, which tracks GPR, FPR and stack arguments separately. */
2230 #define EABI_FLOAT_VARARGS_P \
2231 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2232
2233 \f
2234 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2235
2236 /* Treat LOC as a byte offset from the stack pointer and round it up
2237 to the next fully-aligned offset. */
2238 #define MIPS_STACK_ALIGN(LOC) \
2239 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2240
2241 \f
2242 /* Output assembler code to FILE to increment profiler label # LABELNO
2243 for profiling a function entry. */
2244
2245 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2246
2247 /* The profiler preserves all interesting registers, including $31. */
2248 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2249
2250 /* No mips port has ever used the profiler counter word, so don't emit it
2251 or the label for it. */
2252
2253 #define NO_PROFILE_COUNTERS 1
2254
2255 /* Define this macro if the code for function profiling should come
2256 before the function prologue. Normally, the profiling code comes
2257 after. */
2258
2259 /* #define PROFILE_BEFORE_PROLOGUE */
2260
2261 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2262 the stack pointer does not matter. The value is tested only in
2263 functions that have frame pointers.
2264 No definition is equivalent to always zero. */
2265
2266 #define EXIT_IGNORE_STACK 1
2267
2268 \f
2269 /* Trampolines are a block of code followed by two pointers. */
2270
2271 #define TRAMPOLINE_SIZE \
2272 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2273
2274 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2275 pointers from a single LUI base. */
2276
2277 #define TRAMPOLINE_ALIGNMENT 64
2278
2279 /* mips_trampoline_init calls this library function to flush
2280 program and data caches. */
2281
2282 #ifndef CACHE_FLUSH_FUNC
2283 #define CACHE_FLUSH_FUNC "_flush_cache"
2284 #endif
2285
2286 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2287 /* Flush both caches. We need to flush the data cache in case \
2288 the system has a write-back cache. */ \
2289 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2290 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2291 GEN_INT (3), TYPE_MODE (integer_type_node))
2292
2293 \f
2294 /* Addressing modes, and classification of registers for them. */
2295
2296 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2297 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2298 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2299 \f
2300 /* Maximum number of registers that can appear in a valid memory address. */
2301
2302 #define MAX_REGS_PER_ADDRESS 1
2303
2304 /* Check for constness inline but use mips_legitimate_address_p
2305 to check whether a constant really is an address. */
2306
2307 #define CONSTANT_ADDRESS_P(X) \
2308 (CONSTANT_P (X) && memory_address_p (SImode, X))
2309
2310 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2311 'the start of the function that this code is output in'. */
2312
2313 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2314 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2315 asm_fprintf ((FILE), "%U%s", \
2316 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2317 else \
2318 asm_fprintf ((FILE), "%U%s", (NAME))
2319 \f
2320 /* Flag to mark a function decl symbol that requires a long call. */
2321 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2322 #define SYMBOL_REF_LONG_CALL_P(X) \
2323 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2324
2325 /* This flag marks functions that cannot be lazily bound. */
2326 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2327 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2328 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2329
2330 /* True if we're generating a form of MIPS16 code in which jump tables
2331 are stored in the text section and encoded as 16-bit PC-relative
2332 offsets. This is only possible when general text loads are allowed,
2333 since the table access itself will be an "lh" instruction. */
2334 /* ??? 16-bit offsets can overflow in large functions. */
2335 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2336
2337 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2338
2339 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2340
2341 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2342
2343 /* Define this as 1 if `char' should by default be signed; else as 0. */
2344 #ifndef DEFAULT_SIGNED_CHAR
2345 #define DEFAULT_SIGNED_CHAR 1
2346 #endif
2347
2348 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2349 we generally don't want to use them for copying arbitrary data.
2350 A single N-word move is usually the same cost as N single-word moves. */
2351 #define MOVE_MAX UNITS_PER_WORD
2352 #define MAX_MOVE_MAX 8
2353
2354 /* Define this macro as a C expression which is nonzero if
2355 accessing less than a word of memory (i.e. a `char' or a
2356 `short') is no faster than accessing a word of memory, i.e., if
2357 such access require more than one instruction or if there is no
2358 difference in cost between byte and (aligned) word loads.
2359
2360 On RISC machines, it tends to generate better code to define
2361 this as 1, since it avoids making a QI or HI mode register.
2362
2363 But, generating word accesses for -mips16 is generally bad as shifts
2364 (often extended) would be needed for byte accesses. */
2365 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2366
2367 /* Standard MIPS integer shifts truncate the shift amount to the
2368 width of the shifted operand. However, Loongson vector shifts
2369 do not truncate the shift amount at all. */
2370 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2371
2372 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2373 is done just by pretending it is already truncated. */
2374 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2375 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2376
2377
2378 /* Specify the machine mode that pointers have.
2379 After generation of rtl, the compiler makes no further distinction
2380 between pointers and any other objects of this machine mode. */
2381
2382 #ifndef Pmode
2383 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2384 #endif
2385
2386 /* Give call MEMs SImode since it is the "most permissive" mode
2387 for both 32-bit and 64-bit targets. */
2388
2389 #define FUNCTION_MODE SImode
2390
2391 \f
2392
2393 /* Define if copies to/from condition code registers should be avoided.
2394
2395 This is needed for the MIPS because reload_outcc is not complete;
2396 it needs to handle cases where the source is a general or another
2397 condition code register. */
2398 #define AVOID_CCMODE_COPIES
2399
2400 /* A C expression for the cost of a branch instruction. A value of
2401 1 is the default; other values are interpreted relative to that. */
2402
2403 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2404 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2405
2406 /* If defined, modifies the length assigned to instruction INSN as a
2407 function of the context in which it is used. LENGTH is an lvalue
2408 that contains the initially computed length of the insn and should
2409 be updated with the correct length of the insn. */
2410 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2411 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2412
2413 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2414 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2415 its operands. */
2416 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2417 "%*" OPCODE "%?\t" OPERANDS "%/"
2418
2419 /* Return an asm string that forces INSN to be treated as an absolute
2420 J or JAL instruction instead of an assembler macro. */
2421 #define MIPS_ABSOLUTE_JUMP(INSN) \
2422 (TARGET_ABICALLS_PIC2 \
2423 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2424 : INSN)
2425
2426 /* Return the asm template for a call. INSN is the instruction's mnemonic
2427 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2428 number of the target. SIZE_OPNO is the operand number of the argument size
2429 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2430 -1 and the call is indirect, use the function symbol from the call
2431 attributes to attach a R_MIPS_JALR relocation to the call.
2432
2433 When generating GOT code without explicit relocation operators,
2434 all calls should use assembly macros. Otherwise, all indirect
2435 calls should use "jr" or "jalr"; we will arrange to restore $gp
2436 afterwards if necessary. Finally, we can only generate direct
2437 calls for -mabicalls by temporarily switching to non-PIC mode. */
2438 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2439 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2440 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2441 : (REG_P (OPERANDS[TARGET_OPNO]) \
2442 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2443 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2444 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2445 : REG_P (OPERANDS[TARGET_OPNO]) \
2446 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2447 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2448 \f
2449 /* Control the assembler format that we output. */
2450
2451 /* Output to assembler file text saying following lines
2452 may contain character constants, extra white space, comments, etc. */
2453
2454 #ifndef ASM_APP_ON
2455 #define ASM_APP_ON " #APP\n"
2456 #endif
2457
2458 /* Output to assembler file text saying following lines
2459 no longer contain unusual constructs. */
2460
2461 #ifndef ASM_APP_OFF
2462 #define ASM_APP_OFF " #NO_APP\n"
2463 #endif
2464
2465 #define REGISTER_NAMES \
2466 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2467 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2468 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2469 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2470 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2471 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2472 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2473 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2474 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2475 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2476 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2477 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2478 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2479 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2480 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2481 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2482 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2483 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2484 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2485 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2486 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2487 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2488 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2489 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2490
2491 /* List the "software" names for each register. Also list the numerical
2492 names for $fp and $sp. */
2493
2494 #define ADDITIONAL_REGISTER_NAMES \
2495 { \
2496 { "$29", 29 + GP_REG_FIRST }, \
2497 { "$30", 30 + GP_REG_FIRST }, \
2498 { "at", 1 + GP_REG_FIRST }, \
2499 { "v0", 2 + GP_REG_FIRST }, \
2500 { "v1", 3 + GP_REG_FIRST }, \
2501 { "a0", 4 + GP_REG_FIRST }, \
2502 { "a1", 5 + GP_REG_FIRST }, \
2503 { "a2", 6 + GP_REG_FIRST }, \
2504 { "a3", 7 + GP_REG_FIRST }, \
2505 { "t0", 8 + GP_REG_FIRST }, \
2506 { "t1", 9 + GP_REG_FIRST }, \
2507 { "t2", 10 + GP_REG_FIRST }, \
2508 { "t3", 11 + GP_REG_FIRST }, \
2509 { "t4", 12 + GP_REG_FIRST }, \
2510 { "t5", 13 + GP_REG_FIRST }, \
2511 { "t6", 14 + GP_REG_FIRST }, \
2512 { "t7", 15 + GP_REG_FIRST }, \
2513 { "s0", 16 + GP_REG_FIRST }, \
2514 { "s1", 17 + GP_REG_FIRST }, \
2515 { "s2", 18 + GP_REG_FIRST }, \
2516 { "s3", 19 + GP_REG_FIRST }, \
2517 { "s4", 20 + GP_REG_FIRST }, \
2518 { "s5", 21 + GP_REG_FIRST }, \
2519 { "s6", 22 + GP_REG_FIRST }, \
2520 { "s7", 23 + GP_REG_FIRST }, \
2521 { "t8", 24 + GP_REG_FIRST }, \
2522 { "t9", 25 + GP_REG_FIRST }, \
2523 { "k0", 26 + GP_REG_FIRST }, \
2524 { "k1", 27 + GP_REG_FIRST }, \
2525 { "gp", 28 + GP_REG_FIRST }, \
2526 { "sp", 29 + GP_REG_FIRST }, \
2527 { "fp", 30 + GP_REG_FIRST }, \
2528 { "ra", 31 + GP_REG_FIRST } \
2529 }
2530
2531 #define DBR_OUTPUT_SEQEND(STREAM) \
2532 do \
2533 { \
2534 /* Undo the effect of '%*'. */ \
2535 mips_pop_asm_switch (&mips_nomacro); \
2536 mips_pop_asm_switch (&mips_noreorder); \
2537 /* Emit a blank line after the delay slot for emphasis. */ \
2538 fputs ("\n", STREAM); \
2539 } \
2540 while (0)
2541
2542 /* The MIPS implementation uses some labels for its own purpose. The
2543 following lists what labels are created, and are all formed by the
2544 pattern $L[a-z].*. The machine independent portion of GCC creates
2545 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2546
2547 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2548 $Lb[0-9]+ Begin blocks for MIPS debug support
2549 $Lc[0-9]+ Label for use in s<xx> operation.
2550 $Le[0-9]+ End blocks for MIPS debug support */
2551
2552 #undef ASM_DECLARE_OBJECT_NAME
2553 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2554 mips_declare_object (STREAM, NAME, "", ":\n")
2555
2556 /* Globalizing directive for a label. */
2557 #define GLOBAL_ASM_OP "\t.globl\t"
2558
2559 /* This says how to define a global common symbol. */
2560
2561 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2562
2563 /* This says how to define a local common symbol (i.e., not visible to
2564 linker). */
2565
2566 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2567 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2568 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2569 #endif
2570
2571 /* This says how to output an external. It would be possible not to
2572 output anything and let undefined symbol become external. However
2573 the assembler uses length information on externals to allocate in
2574 data/sdata bss/sbss, thereby saving exec time. */
2575
2576 #undef ASM_OUTPUT_EXTERNAL
2577 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2578 mips_output_external(STREAM,DECL,NAME)
2579
2580 /* This is how to declare a function name. The actual work of
2581 emitting the label is moved to function_prologue, so that we can
2582 get the line number correctly emitted before the .ent directive,
2583 and after any .file directives. Define as empty so that the function
2584 is not declared before the .ent directive elsewhere. */
2585
2586 #undef ASM_DECLARE_FUNCTION_NAME
2587 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2588
2589 /* This is how to store into the string LABEL
2590 the symbol_ref name of an internal numbered label where
2591 PREFIX is the class of label and NUM is the number within the class.
2592 This is suitable for output with `assemble_name'. */
2593
2594 #undef ASM_GENERATE_INTERNAL_LABEL
2595 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2596 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2597
2598 /* Print debug labels as "foo = ." rather than "foo:" because they should
2599 represent a byte pointer rather than an ISA-encoded address. This is
2600 particularly important for code like:
2601
2602 $LFBxxx = .
2603 .cfi_startproc
2604 ...
2605 .section .gcc_except_table,...
2606 ...
2607 .uleb128 foo-$LFBxxx
2608
2609 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2610 likewise a byte pointer rather than an ISA-encoded address.
2611
2612 At the time of writing, this hook is not used for the function end
2613 label:
2614
2615 $LFExxx:
2616 .end foo
2617
2618 But this doesn't matter, because GAS doesn't treat a pre-.end label
2619 as a MIPS16 one anyway. */
2620
2621 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2622 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2623
2624 /* This is how to output an element of a case-vector that is absolute. */
2625
2626 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2627 fprintf (STREAM, "\t%s\t%sL%d\n", \
2628 ptr_mode == DImode ? ".dword" : ".word", \
2629 LOCAL_LABEL_PREFIX, \
2630 VALUE)
2631
2632 /* This is how to output an element of a case-vector. We can make the
2633 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2634 is supported. */
2635
2636 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2637 do { \
2638 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2639 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2640 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2641 else if (TARGET_GPWORD) \
2642 fprintf (STREAM, "\t%s\t%sL%d\n", \
2643 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2644 LOCAL_LABEL_PREFIX, VALUE); \
2645 else if (TARGET_RTP_PIC) \
2646 { \
2647 /* Make the entry relative to the start of the function. */ \
2648 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2649 fprintf (STREAM, "\t%s\t%sL%d-", \
2650 Pmode == DImode ? ".dword" : ".word", \
2651 LOCAL_LABEL_PREFIX, VALUE); \
2652 assemble_name (STREAM, XSTR (fnsym, 0)); \
2653 fprintf (STREAM, "\n"); \
2654 } \
2655 else \
2656 fprintf (STREAM, "\t%s\t%sL%d\n", \
2657 ptr_mode == DImode ? ".dword" : ".word", \
2658 LOCAL_LABEL_PREFIX, VALUE); \
2659 } while (0)
2660
2661 /* This is how to output an assembler line
2662 that says to advance the location counter
2663 to a multiple of 2**LOG bytes. */
2664
2665 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2666 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2667
2668 /* This is how to output an assembler line to advance the location
2669 counter by SIZE bytes. */
2670
2671 #undef ASM_OUTPUT_SKIP
2672 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2673 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2674
2675 /* This is how to output a string. */
2676 #undef ASM_OUTPUT_ASCII
2677 #define ASM_OUTPUT_ASCII mips_output_ascii
2678
2679 \f
2680 /* Default to -G 8 */
2681 #ifndef MIPS_DEFAULT_GVALUE
2682 #define MIPS_DEFAULT_GVALUE 8
2683 #endif
2684
2685 /* Define the strings to put out for each section in the object file. */
2686 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2687 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2688
2689 #undef READONLY_DATA_SECTION_ASM_OP
2690 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2691 \f
2692 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2693 do \
2694 { \
2695 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2696 TARGET_64BIT ? "daddiu" : "addiu", \
2697 reg_names[STACK_POINTER_REGNUM], \
2698 reg_names[STACK_POINTER_REGNUM], \
2699 TARGET_64BIT ? "sd" : "sw", \
2700 reg_names[REGNO], \
2701 reg_names[STACK_POINTER_REGNUM]); \
2702 } \
2703 while (0)
2704
2705 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2706 do \
2707 { \
2708 mips_push_asm_switch (&mips_noreorder); \
2709 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2710 TARGET_64BIT ? "ld" : "lw", \
2711 reg_names[REGNO], \
2712 reg_names[STACK_POINTER_REGNUM], \
2713 TARGET_64BIT ? "daddu" : "addu", \
2714 reg_names[STACK_POINTER_REGNUM], \
2715 reg_names[STACK_POINTER_REGNUM]); \
2716 mips_pop_asm_switch (&mips_noreorder); \
2717 } \
2718 while (0)
2719
2720 /* How to start an assembler comment.
2721 The leading space is important (the mips native assembler requires it). */
2722 #ifndef ASM_COMMENT_START
2723 #define ASM_COMMENT_START " #"
2724 #endif
2725 \f
2726 #undef SIZE_TYPE
2727 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2728
2729 #undef PTRDIFF_TYPE
2730 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2731
2732 /* The maximum number of bytes that can be copied by one iteration of
2733 a movmemsi loop; see mips_block_move_loop. */
2734 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2735 (UNITS_PER_WORD * 4)
2736
2737 /* The maximum number of bytes that can be copied by a straight-line
2738 implementation of movmemsi; see mips_block_move_straight. We want
2739 to make sure that any loop-based implementation will iterate at
2740 least twice. */
2741 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2742 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2743
2744 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2745 values were determined experimentally by benchmarking with CSiBE.
2746 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2747 for o32 where we have to restore $gp afterwards as well as make an
2748 indirect call), but in practice, bumping this up higher for
2749 TARGET_ABICALLS doesn't make much difference to code size. */
2750
2751 #define MIPS_CALL_RATIO 8
2752
2753 /* Any loop-based implementation of movmemsi will have at least
2754 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2755 moves, so allow individual copies of fewer elements.
2756
2757 When movmemsi is not available, use a value approximating
2758 the length of a memcpy call sequence, so that move_by_pieces
2759 will generate inline code if it is shorter than a function call.
2760 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2761 we'll have to generate a load/store pair for each, halve the
2762 value of MIPS_CALL_RATIO to take that into account. */
2763
2764 #define MOVE_RATIO(speed) \
2765 (HAVE_movmemsi \
2766 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2767 : MIPS_CALL_RATIO / 2)
2768
2769 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2770 mips_move_by_pieces_p (SIZE, ALIGN)
2771
2772 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2773 of the length of a memset call, but use the default otherwise. */
2774
2775 #define CLEAR_RATIO(speed)\
2776 ((speed) ? 15 : MIPS_CALL_RATIO)
2777
2778 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2779 optimizing for size adjust the ratio to account for the overhead of
2780 loading the constant and replicating it across the word. */
2781
2782 #define SET_RATIO(speed) \
2783 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2784
2785 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2786 mips_store_by_pieces_p (SIZE, ALIGN)
2787 \f
2788 #ifndef __mips16
2789 /* Since the bits of the _init and _fini function is spread across
2790 many object files, each potentially with its own GP, we must assume
2791 we need to load our GP. We don't preserve $gp or $ra, since each
2792 init/fini chunk is supposed to initialize $gp, and crti/crtn
2793 already take care of preserving $ra and, when appropriate, $gp. */
2794 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2795 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2796 asm (SECTION_OP "\n\
2797 .set noreorder\n\
2798 bal 1f\n\
2799 nop\n\
2800 1: .cpload $31\n\
2801 .set reorder\n\
2802 jal " USER_LABEL_PREFIX #FUNC "\n\
2803 " TEXT_SECTION_ASM_OP);
2804 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2805 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2806 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2807 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2808 asm (SECTION_OP "\n\
2809 .set noreorder\n\
2810 bal 1f\n\
2811 nop\n\
2812 1: .set reorder\n\
2813 .cpsetup $31, $2, 1b\n\
2814 jal " USER_LABEL_PREFIX #FUNC "\n\
2815 " TEXT_SECTION_ASM_OP);
2816 #endif
2817 #endif
2818
2819 #ifndef HAVE_AS_TLS
2820 #define HAVE_AS_TLS 0
2821 #endif
2822
2823 #ifndef USED_FOR_TARGET
2824 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2825 struct mips_asm_switch {
2826 /* The FOO in the description above. */
2827 const char *name;
2828
2829 /* The current block nesting level, or 0 if we aren't in a block. */
2830 int nesting_level;
2831 };
2832
2833 extern const enum reg_class mips_regno_to_class[];
2834 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2835 extern const char *current_function_file; /* filename current function is in */
2836 extern int num_source_filenames; /* current .file # */
2837 extern struct mips_asm_switch mips_noreorder;
2838 extern struct mips_asm_switch mips_nomacro;
2839 extern struct mips_asm_switch mips_noat;
2840 extern int mips_dbx_regno[];
2841 extern int mips_dwarf_regno[];
2842 extern bool mips_split_p[];
2843 extern bool mips_split_hi_p[];
2844 extern bool mips_use_pcrel_pool_p[];
2845 extern const char *mips_lo_relocs[];
2846 extern const char *mips_hi_relocs[];
2847 extern enum processor mips_arch; /* which cpu to codegen for */
2848 extern enum processor mips_tune; /* which cpu to schedule for */
2849 extern int mips_isa; /* architectural level */
2850 extern const struct mips_cpu_info *mips_arch_info;
2851 extern const struct mips_cpu_info *mips_tune_info;
2852 extern bool mips_base_mips16;
2853 extern GTY(()) struct target_globals *mips16_globals;
2854 #endif
2855
2856 /* Enable querying of DFA units. */
2857 #define CPU_UNITS_QUERY 1
2858
2859 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2860 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2861
2862 /* As on most targets, we want the .eh_frame section to be read-only where
2863 possible. And as on most targets, this means two things:
2864
2865 (a) Non-locally-binding pointers must have an indirect encoding,
2866 so that the addresses in the .eh_frame section itself become
2867 locally-binding.
2868
2869 (b) A shared library's .eh_frame section must encode locally-binding
2870 pointers in a relative (relocation-free) form.
2871
2872 However, MIPS has traditionally not allowed directives like:
2873
2874 .long x-.
2875
2876 in cases where "x" is in a different section, or is not defined in the
2877 same assembly file. We are therefore unable to emit the PC-relative
2878 form required by (b) at assembly time.
2879
2880 Fortunately, the linker is able to convert absolute addresses into
2881 PC-relative addresses on our behalf. Unfortunately, only certain
2882 versions of the linker know how to do this for indirect pointers,
2883 and for personality data. We must fall back on using writable
2884 .eh_frame sections for shared libraries if the linker does not
2885 support this feature. */
2886 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2887 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2888
2889 /* For switching between MIPS16 and non-MIPS16 modes. */
2890 #define SWITCHABLE_TARGET 1
2891
2892 /* Several named MIPS patterns depend on Pmode. These patterns have the
2893 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2894 Add the appropriate suffix to generator function NAME and invoke it
2895 with arguments ARGS. */
2896 #define PMODE_INSN(NAME, ARGS) \
2897 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)