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linux.h (GLIBC_DYNAMIC_LINKER): Handle `-mnan=2008'.
[gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS64 (mips_isa == 64)
212 #define ISA_MIPS64R2 (mips_isa == 65)
213
214 /* Architecture target defines. */
215 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
216 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
217 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
218 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
219 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
220 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
221 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
222 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
223 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
224 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
225 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
226 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
227 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
228 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
229 || mips_arch == PROCESSOR_OCTEON2)
230 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2)
231 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
232 || mips_arch == PROCESSOR_SB1A)
233 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
234 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
235
236 /* Scheduling target defines. */
237 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
238 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
239 || mips_tune == PROCESSOR_24KF2_1 \
240 || mips_tune == PROCESSOR_24KF1_1)
241 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
242 || mips_tune == PROCESSOR_74KF2_1 \
243 || mips_tune == PROCESSOR_74KF1_1 \
244 || mips_tune == PROCESSOR_74KF3_2)
245 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
246 || mips_tune == PROCESSOR_LOONGSON_2F)
247 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
248 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
249 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
250 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
251 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
252 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
253 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
254 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
255 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
256 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
257 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
258 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
259 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
260 || mips_tune == PROCESSOR_OCTEON2)
261 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
262 || mips_tune == PROCESSOR_SB1A)
263
264 /* Whether vector modes and intrinsics for ST Microelectronics
265 Loongson-2E/2F processors should be enabled. In o32 pairs of
266 floating-point registers provide 64-bit values. */
267 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
268 && (TARGET_LOONGSON_2EF \
269 || TARGET_LOONGSON_3A))
270
271 /* True if the pre-reload scheduler should try to create chains of
272 multiply-add or multiply-subtract instructions. For example,
273 suppose we have:
274
275 t1 = a * b
276 t2 = t1 + c * d
277 t3 = e * f
278 t4 = t3 - g * h
279
280 t1 will have a higher priority than t2 and t3 will have a higher
281 priority than t4. However, before reload, there is no dependence
282 between t1 and t3, and they can often have similar priorities.
283 The scheduler will then tend to prefer:
284
285 t1 = a * b
286 t3 = e * f
287 t2 = t1 + c * d
288 t4 = t3 - g * h
289
290 which stops us from making full use of macc/madd-style instructions.
291 This sort of situation occurs frequently in Fourier transforms and
292 in unrolled loops.
293
294 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
295 queue so that chained multiply-add and multiply-subtract instructions
296 appear ahead of any other instruction that is likely to clobber lo.
297 In the example above, if t2 and t3 become ready at the same time,
298 the code ensures that t2 is scheduled first.
299
300 Multiply-accumulate instructions are a bigger win for some targets
301 than others, so this macro is defined on an opt-in basis. */
302 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
303 || TUNE_MIPS4120 \
304 || TUNE_MIPS4130 \
305 || TUNE_24K)
306
307 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
308 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
309
310 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
311 directly accessible, while the command-line options select
312 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
313 in use. */
314 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
315 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
316
317 /* False if SC acts as a memory barrier with respect to itself,
318 otherwise a SYNC will be emitted after SC for atomic operations
319 that require ordering between the SC and following loads and
320 stores. It does not tell anything about ordering of loads and
321 stores prior to and following the SC, only about the SC itself and
322 those loads and stores follow it. */
323 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
324
325 /* Define preprocessor macros for the -march and -mtune options.
326 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
327 processor. If INFO's canonical name is "foo", define PREFIX to
328 be "foo", and define an additional macro PREFIX_FOO. */
329 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
330 do \
331 { \
332 char *macro, *p; \
333 \
334 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
335 for (p = macro; *p != 0; p++) \
336 if (*p == '+') \
337 *p = 'P'; \
338 else \
339 *p = TOUPPER (*p); \
340 \
341 builtin_define (macro); \
342 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
343 free (macro); \
344 } \
345 while (0)
346
347 /* Target CPU builtins. */
348 #define TARGET_CPU_CPP_BUILTINS() \
349 do \
350 { \
351 builtin_assert ("machine=mips"); \
352 builtin_assert ("cpu=mips"); \
353 builtin_define ("__mips__"); \
354 builtin_define ("_mips"); \
355 \
356 /* We do this here because __mips is defined below and so we \
357 can't use builtin_define_std. We don't ever want to define \
358 "mips" for VxWorks because some of the VxWorks headers \
359 construct include filenames from a root directory macro, \
360 an architecture macro and a filename, where the architecture \
361 macro expands to 'mips'. If we define 'mips' to 1, the \
362 architecture macro expands to 1 as well. */ \
363 if (!flag_iso && !TARGET_VXWORKS) \
364 builtin_define ("mips"); \
365 \
366 if (TARGET_64BIT) \
367 builtin_define ("__mips64"); \
368 \
369 /* Treat _R3000 and _R4000 like register-size \
370 defines, which is how they've historically \
371 been used. */ \
372 if (TARGET_64BIT) \
373 { \
374 builtin_define_std ("R4000"); \
375 builtin_define ("_R4000"); \
376 } \
377 else \
378 { \
379 builtin_define_std ("R3000"); \
380 builtin_define ("_R3000"); \
381 } \
382 \
383 if (TARGET_FLOAT64) \
384 builtin_define ("__mips_fpr=64"); \
385 else \
386 builtin_define ("__mips_fpr=32"); \
387 \
388 if (mips_base_compression_flags & MASK_MIPS16) \
389 builtin_define ("__mips16"); \
390 \
391 if (TARGET_MIPS3D) \
392 builtin_define ("__mips3d"); \
393 \
394 if (TARGET_SMARTMIPS) \
395 builtin_define ("__mips_smartmips"); \
396 \
397 if (mips_base_compression_flags & MASK_MICROMIPS) \
398 builtin_define ("__mips_micromips"); \
399 \
400 if (TARGET_MCU) \
401 builtin_define ("__mips_mcu"); \
402 \
403 if (TARGET_EVA) \
404 builtin_define ("__mips_eva"); \
405 \
406 if (TARGET_DSP) \
407 { \
408 builtin_define ("__mips_dsp"); \
409 if (TARGET_DSPR2) \
410 { \
411 builtin_define ("__mips_dspr2"); \
412 builtin_define ("__mips_dsp_rev=2"); \
413 } \
414 else \
415 builtin_define ("__mips_dsp_rev=1"); \
416 } \
417 \
418 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
419 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
420 \
421 if (ISA_MIPS1) \
422 { \
423 builtin_define ("__mips=1"); \
424 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
425 } \
426 else if (ISA_MIPS2) \
427 { \
428 builtin_define ("__mips=2"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
430 } \
431 else if (ISA_MIPS3) \
432 { \
433 builtin_define ("__mips=3"); \
434 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
435 } \
436 else if (ISA_MIPS4) \
437 { \
438 builtin_define ("__mips=4"); \
439 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
440 } \
441 else if (ISA_MIPS32) \
442 { \
443 builtin_define ("__mips=32"); \
444 builtin_define ("__mips_isa_rev=1"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
446 } \
447 else if (ISA_MIPS32R2) \
448 { \
449 builtin_define ("__mips=32"); \
450 builtin_define ("__mips_isa_rev=2"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
452 } \
453 else if (ISA_MIPS64) \
454 { \
455 builtin_define ("__mips=64"); \
456 builtin_define ("__mips_isa_rev=1"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
458 } \
459 else if (ISA_MIPS64R2) \
460 { \
461 builtin_define ("__mips=64"); \
462 builtin_define ("__mips_isa_rev=2"); \
463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
464 } \
465 \
466 switch (mips_abi) \
467 { \
468 case ABI_32: \
469 builtin_define ("_ABIO32=1"); \
470 builtin_define ("_MIPS_SIM=_ABIO32"); \
471 break; \
472 \
473 case ABI_N32: \
474 builtin_define ("_ABIN32=2"); \
475 builtin_define ("_MIPS_SIM=_ABIN32"); \
476 break; \
477 \
478 case ABI_64: \
479 builtin_define ("_ABI64=3"); \
480 builtin_define ("_MIPS_SIM=_ABI64"); \
481 break; \
482 \
483 case ABI_O64: \
484 builtin_define ("_ABIO64=4"); \
485 builtin_define ("_MIPS_SIM=_ABIO64"); \
486 break; \
487 } \
488 \
489 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
490 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
491 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
492 builtin_define_with_int_value ("_MIPS_FPSET", \
493 32 / MAX_FPRS_PER_FMT); \
494 \
495 /* These defines reflect the ABI in use, not whether the \
496 FPU is directly accessible. */ \
497 if (TARGET_NO_FLOAT) \
498 builtin_define ("__mips_no_float"); \
499 else if (TARGET_HARD_FLOAT_ABI) \
500 builtin_define ("__mips_hard_float"); \
501 else \
502 builtin_define ("__mips_soft_float"); \
503 \
504 if (TARGET_SINGLE_FLOAT) \
505 builtin_define ("__mips_single_float"); \
506 \
507 if (TARGET_PAIRED_SINGLE_FLOAT) \
508 builtin_define ("__mips_paired_single_float"); \
509 \
510 if (mips_abs == MIPS_IEEE_754_2008) \
511 builtin_define ("__mips_abs2008"); \
512 \
513 if (mips_nan == MIPS_IEEE_754_2008) \
514 builtin_define ("__mips_nan2008"); \
515 \
516 if (TARGET_BIG_ENDIAN) \
517 { \
518 builtin_define_std ("MIPSEB"); \
519 builtin_define ("_MIPSEB"); \
520 } \
521 else \
522 { \
523 builtin_define_std ("MIPSEL"); \
524 builtin_define ("_MIPSEL"); \
525 } \
526 \
527 /* Whether calls should go through $25. The separate __PIC__ \
528 macro indicates whether abicalls code might use a GOT. */ \
529 if (TARGET_ABICALLS) \
530 builtin_define ("__mips_abicalls"); \
531 \
532 /* Whether Loongson vector modes are enabled. */ \
533 if (TARGET_LOONGSON_VECTORS) \
534 builtin_define ("__mips_loongson_vector_rev"); \
535 \
536 /* Historical Octeon macro. */ \
537 if (TARGET_OCTEON) \
538 builtin_define ("__OCTEON__"); \
539 \
540 if (TARGET_SYNCI) \
541 builtin_define ("__mips_synci"); \
542 \
543 /* Macros dependent on the C dialect. */ \
544 if (preprocessing_asm_p ()) \
545 { \
546 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
547 builtin_define ("_LANGUAGE_ASSEMBLY"); \
548 } \
549 else if (c_dialect_cxx ()) \
550 { \
551 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
552 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
553 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
554 } \
555 else \
556 { \
557 builtin_define_std ("LANGUAGE_C"); \
558 builtin_define ("_LANGUAGE_C"); \
559 } \
560 if (c_dialect_objc ()) \
561 { \
562 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
563 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
564 /* Bizarre, but retained for backwards compatibility. */ \
565 builtin_define_std ("LANGUAGE_C"); \
566 builtin_define ("_LANGUAGE_C"); \
567 } \
568 \
569 if (mips_abi == ABI_EABI) \
570 builtin_define ("__mips_eabi"); \
571 \
572 if (TARGET_CACHE_BUILTIN) \
573 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
574 } \
575 while (0)
576
577 /* Default target_flags if no switches are specified */
578
579 #ifndef TARGET_DEFAULT
580 #define TARGET_DEFAULT 0
581 #endif
582
583 #ifndef TARGET_CPU_DEFAULT
584 #define TARGET_CPU_DEFAULT 0
585 #endif
586
587 #ifndef TARGET_ENDIAN_DEFAULT
588 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
589 #endif
590
591 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
592 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
593 #endif
594
595 #ifdef IN_LIBGCC2
596 #undef TARGET_64BIT
597 /* Make this compile time constant for libgcc2 */
598 #ifdef __mips64
599 #define TARGET_64BIT 1
600 #else
601 #define TARGET_64BIT 0
602 #endif
603 #endif /* IN_LIBGCC2 */
604
605 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
606 when compiled with hardware floating point. This is because MIPS16
607 code cannot save and restore the floating-point registers, which is
608 important if in a mixed MIPS16/non-MIPS16 environment. */
609
610 #ifdef IN_LIBGCC2
611 #if __mips_hard_float
612 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
613 #endif
614 #endif /* IN_LIBGCC2 */
615
616 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
617
618 #ifndef MULTILIB_ENDIAN_DEFAULT
619 #if TARGET_ENDIAN_DEFAULT == 0
620 #define MULTILIB_ENDIAN_DEFAULT "EL"
621 #else
622 #define MULTILIB_ENDIAN_DEFAULT "EB"
623 #endif
624 #endif
625
626 #ifndef MULTILIB_ISA_DEFAULT
627 #if MIPS_ISA_DEFAULT == 1
628 #define MULTILIB_ISA_DEFAULT "mips1"
629 #elif MIPS_ISA_DEFAULT == 2
630 #define MULTILIB_ISA_DEFAULT "mips2"
631 #elif MIPS_ISA_DEFAULT == 3
632 #define MULTILIB_ISA_DEFAULT "mips3"
633 #elif MIPS_ISA_DEFAULT == 4
634 #define MULTILIB_ISA_DEFAULT "mips4"
635 #elif MIPS_ISA_DEFAULT == 32
636 #define MULTILIB_ISA_DEFAULT "mips32"
637 #elif MIPS_ISA_DEFAULT == 33
638 #define MULTILIB_ISA_DEFAULT "mips32r2"
639 #elif MIPS_ISA_DEFAULT == 64
640 #define MULTILIB_ISA_DEFAULT "mips64"
641 #elif MIPS_ISA_DEFAULT == 65
642 #define MULTILIB_ISA_DEFAULT "mips64r2"
643 #else
644 #define MULTILIB_ISA_DEFAULT "mips1"
645 #endif
646 #endif
647
648 #ifndef MIPS_ABI_DEFAULT
649 #define MIPS_ABI_DEFAULT ABI_32
650 #endif
651
652 /* Use the most portable ABI flag for the ASM specs. */
653
654 #if MIPS_ABI_DEFAULT == ABI_32
655 #define MULTILIB_ABI_DEFAULT "mabi=32"
656 #elif MIPS_ABI_DEFAULT == ABI_O64
657 #define MULTILIB_ABI_DEFAULT "mabi=o64"
658 #elif MIPS_ABI_DEFAULT == ABI_N32
659 #define MULTILIB_ABI_DEFAULT "mabi=n32"
660 #elif MIPS_ABI_DEFAULT == ABI_64
661 #define MULTILIB_ABI_DEFAULT "mabi=64"
662 #elif MIPS_ABI_DEFAULT == ABI_EABI
663 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
664 #endif
665
666 #ifndef MULTILIB_DEFAULTS
667 #define MULTILIB_DEFAULTS \
668 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
669 #endif
670
671 /* We must pass -EL to the linker by default for little endian embedded
672 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
673 linker will default to using big-endian output files. The OUTPUT_FORMAT
674 line must be in the linker script, otherwise -EB/-EL will not work. */
675
676 #ifndef ENDIAN_SPEC
677 #if TARGET_ENDIAN_DEFAULT == 0
678 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
679 #else
680 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
681 #endif
682 #endif
683
684 /* A spec condition that matches all non-mips16 -mips arguments. */
685
686 #define MIPS_ISA_LEVEL_OPTION_SPEC \
687 "mips1|mips2|mips3|mips4|mips32*|mips64*"
688
689 /* A spec condition that matches all non-mips16 architecture arguments. */
690
691 #define MIPS_ARCH_OPTION_SPEC \
692 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
693
694 /* A spec that infers a -mips argument from an -march argument,
695 or injects the default if no architecture is specified. */
696
697 #define MIPS_ISA_LEVEL_SPEC \
698 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
699 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
700 %{march=mips2|march=r6000:-mips2} \
701 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
702 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
703 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
704 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
705 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
706 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
707 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
708 |march=xlr|march=loongson3a: -mips64} \
709 %{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
710 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
711
712 /* A spec that infers a -mhard-float or -msoft-float setting from an
713 -march argument. Note that soft-float and hard-float code are not
714 link-compatible. */
715
716 #define MIPS_ARCH_FLOAT_SPEC \
717 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
718 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
719 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
720 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
721 march=*: -mhard-float}"
722
723 /* A spec condition that matches 32-bit options. It only works if
724 MIPS_ISA_LEVEL_SPEC has been applied. */
725
726 #define MIPS_32BIT_OPTION_SPEC \
727 "mips1|mips2|mips32*|mgp32"
728
729 /* Infer a -msynci setting from a -mips argument, on the assumption that
730 -msynci is desired where possible. */
731 #define MIPS_ISA_SYNCI_SPEC \
732 "%{msynci|mno-synci:;:%{mips32r2|mips64r2:-msynci;:-mno-synci}}"
733
734 #if (MIPS_ABI_DEFAULT == ABI_O64 \
735 || MIPS_ABI_DEFAULT == ABI_N32 \
736 || MIPS_ABI_DEFAULT == ABI_64)
737 #define OPT_ARCH64 "mabi=32|mgp32:;"
738 #define OPT_ARCH32 "mabi=32|mgp32"
739 #else
740 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
741 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
742 #endif
743
744 /* Support for a compile-time default CPU, et cetera. The rules are:
745 --with-arch is ignored if -march is specified or a -mips is specified
746 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
747 --with-tune is ignored if -mtune is specified; likewise
748 --with-tune-32 and --with-tune-64.
749 --with-abi is ignored if -mabi is specified.
750 --with-float is ignored if -mhard-float or -msoft-float are
751 specified.
752 --with-nan is ignored if -mnan is specified.
753 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
754 specified. */
755 #define OPTION_DEFAULT_SPECS \
756 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
757 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
758 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
759 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
760 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
761 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
762 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
763 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
764 {"fpu", "%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}" }, \
765 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
766 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
767 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
768 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
769 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
770
771 /* A spec that infers the -mdsp setting from an -march argument. */
772 #define BASE_DRIVER_SELF_SPECS \
773 "%{!mno-dsp: \
774 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
775 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
776
777 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
778
779 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
780 && ISA_HAS_COND_TRAP)
781
782 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
783
784 /* True if the ABI can only work with 64-bit integer registers. We
785 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
786 otherwise floating-point registers must also be 64-bit. */
787 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
788
789 /* Likewise for 32-bit regs. */
790 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
791
792 /* True if the file format uses 64-bit symbols. At present, this is
793 only true for n64, which uses 64-bit ELF. */
794 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
795
796 /* True if symbols are 64 bits wide. This is usually determined by
797 the ABI's file format, but it can be overridden by -msym32. Note that
798 overriding the size with -msym32 changes the ABI of relocatable objects,
799 although it doesn't change the ABI of a fully-linked object. */
800 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
801 && Pmode == DImode \
802 && !TARGET_SYM32)
803
804 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
805 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
806 || ISA_MIPS4 \
807 || ISA_MIPS64 \
808 || ISA_MIPS64R2)
809
810 /* ISA has branch likely instructions (e.g. mips2). */
811 /* Disable branchlikely for tx39 until compare rewrite. They haven't
812 been generated up to this point. */
813 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
814
815 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
816 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
817 || TARGET_MIPS5400 \
818 || TARGET_MIPS5500 \
819 || TARGET_MIPS5900 \
820 || TARGET_MIPS7000 \
821 || TARGET_MIPS9000 \
822 || TARGET_MAD \
823 || ISA_MIPS32 \
824 || ISA_MIPS32R2 \
825 || ISA_MIPS64 \
826 || ISA_MIPS64R2) \
827 && !TARGET_MIPS16)
828
829 /* ISA has a three-operand multiplication instruction. */
830 #define ISA_HAS_DMUL3 (TARGET_64BIT \
831 && TARGET_OCTEON \
832 && !TARGET_MIPS16)
833
834 /* ISA supports instructions DMULT and DMULTU. */
835 #define ISA_HAS_DMULT (TARGET_64BIT && !TARGET_MIPS5900)
836
837 /* ISA supports instructions MULT and MULTU.
838 This is always true, but the macro is needed for ISA_HAS_<D>MULT
839 in mips.md. */
840 #define ISA_HAS_MULT (1)
841
842 /* ISA supports instructions DDIV and DDIVU. */
843 #define ISA_HAS_DDIV (TARGET_64BIT && !TARGET_MIPS5900)
844
845 /* ISA supports instructions DIV and DIVU.
846 This is always true, but the macro is needed for ISA_HAS_<D>DIV
847 in mips.md. */
848 #define ISA_HAS_DIV (1)
849
850 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
851 || TARGET_LOONGSON_3A) \
852 && !TARGET_MIPS16)
853
854 /* ISA has the floating-point conditional move instructions introduced
855 in mips4. */
856 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
857 || ISA_MIPS32 \
858 || ISA_MIPS32R2 \
859 || ISA_MIPS64 \
860 || ISA_MIPS64R2) \
861 && !TARGET_MIPS5500 \
862 && !TARGET_MIPS16)
863
864 /* ISA has the integer conditional move instructions introduced in mips4 and
865 ST Loongson 2E/2F. */
866 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
867 || TARGET_MIPS5900 \
868 || TARGET_LOONGSON_2EF)
869
870 /* ISA has LDC1 and SDC1. */
871 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
872 && !TARGET_MIPS5900 \
873 && !TARGET_MIPS16)
874
875 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
876 branch on CC, and move (both FP and non-FP) on CC. */
877 #define ISA_HAS_8CC (ISA_MIPS4 \
878 || ISA_MIPS32 \
879 || ISA_MIPS32R2 \
880 || ISA_MIPS64 \
881 || ISA_MIPS64R2)
882
883 /* This is a catch all for other mips4 instructions: indexed load, the
884 FP madd and msub instructions, and the FP recip and recip sqrt
885 instructions. */
886 #define ISA_HAS_FP4 ((ISA_MIPS4 \
887 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
888 || ISA_MIPS64 \
889 || ISA_MIPS64R2) \
890 && !TARGET_MIPS16)
891
892 /* ISA has paired-single instructions. */
893 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
894
895 /* ISA has conditional trap instructions. */
896 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
897 && !TARGET_MIPS16)
898
899 /* ISA has integer multiply-accumulate instructions, madd and msub. */
900 #define ISA_HAS_MADD_MSUB (ISA_MIPS32 \
901 || ISA_MIPS32R2 \
902 || ISA_MIPS64 \
903 || ISA_MIPS64R2)
904
905 /* Integer multiply-accumulate instructions should be generated. */
906 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
907
908 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
909 #define ISA_HAS_FP_MADD4_MSUB4 (ISA_HAS_FP4 \
910 || (ISA_MIPS32R2 && !TARGET_MIPS16))
911
912 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
913 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
914
915 /* ISA has floating-point nmadd and nmsub instructions
916 'd = -((a * b) [+-] c)'. */
917 #define ISA_HAS_NMADD4_NMSUB4 (ISA_HAS_FP4 \
918 || (ISA_MIPS32R2 && !TARGET_MIPS16))
919
920 /* ISA has floating-point nmadd and nmsub instructions
921 'c = -((a * b) [+-] c)'. */
922 #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF
923
924 /* ISA has count leading zeroes/ones instruction (not implemented). */
925 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
926 || ISA_MIPS32R2 \
927 || ISA_MIPS64 \
928 || ISA_MIPS64R2) \
929 && !TARGET_MIPS16)
930
931 /* ISA has three operand multiply instructions that put
932 the high part in an accumulator: mulhi or mulhiu. */
933 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
934 || TARGET_MIPS5500 \
935 || TARGET_SR71K) \
936 && !TARGET_MIPS16)
937
938 /* ISA has three operand multiply instructions that negate the
939 result and put the result in an accumulator. */
940 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
941 || TARGET_MIPS5500 \
942 || TARGET_SR71K) \
943 && !TARGET_MIPS16)
944
945 /* ISA has three operand multiply instructions that subtract the
946 result from a 4th operand and put the result in an accumulator. */
947 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
948 || TARGET_MIPS5500 \
949 || TARGET_SR71K) \
950 && !TARGET_MIPS16)
951
952 /* ISA has three operand multiply instructions that add the result
953 to a 4th operand and put the result in an accumulator. */
954 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
955 || TARGET_MIPS4130 \
956 || TARGET_MIPS5400 \
957 || TARGET_MIPS5500 \
958 || TARGET_SR71K) \
959 && !TARGET_MIPS16)
960
961 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
962 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
963 || TARGET_MIPS4130) \
964 && !TARGET_MIPS16)
965
966 /* ISA has the "ror" (rotate right) instructions. */
967 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
968 || ISA_MIPS64R2 \
969 || TARGET_MIPS5400 \
970 || TARGET_MIPS5500 \
971 || TARGET_SR71K \
972 || TARGET_SMARTMIPS) \
973 && !TARGET_MIPS16)
974
975 /* ISA has data prefetch instructions. This controls use of 'pref'. */
976 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
977 || TARGET_LOONGSON_2EF \
978 || TARGET_MIPS5900 \
979 || ISA_MIPS32 \
980 || ISA_MIPS32R2 \
981 || ISA_MIPS64 \
982 || ISA_MIPS64R2) \
983 && !TARGET_MIPS16)
984
985 /* ISA has data indexed prefetch instructions. This controls use of
986 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
987 (prefx is a cop1x instruction, so can only be used if FP is
988 enabled.) */
989 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
990 || ISA_MIPS32R2 \
991 || ISA_MIPS64 \
992 || ISA_MIPS64R2) \
993 && !TARGET_MIPS16)
994
995 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
996 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
997 also requires TARGET_DOUBLE_FLOAT. */
998 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
999
1000 /* ISA includes the MIPS32r2 seb and seh instructions. */
1001 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
1002 || ISA_MIPS64R2) \
1003 && !TARGET_MIPS16)
1004
1005 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1006 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
1007 || ISA_MIPS64R2) \
1008 && !TARGET_MIPS16)
1009
1010 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1011 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
1012 && (ISA_MIPS32R2 \
1013 || ISA_MIPS64R2))
1014
1015 /* ISA has lwxs instruction (load w/scaled index address. */
1016 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1017 && !TARGET_MIPS16)
1018
1019 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1020 #define ISA_HAS_LBX (TARGET_OCTEON2)
1021 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1022 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1023 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1024 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1025 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1026 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1027 && TARGET_64BIT)
1028
1029 /* The DSP ASE is available. */
1030 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1031
1032 /* Revision 2 of the DSP ASE is available. */
1033 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1034
1035 /* True if the result of a load is not available to the next instruction.
1036 A nop will then be needed between instructions like "lw $4,..."
1037 and "addiu $4,$4,1". */
1038 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1039 && !TARGET_MIPS3900 \
1040 && !TARGET_MIPS5900 \
1041 && !TARGET_MIPS16 \
1042 && !TARGET_MICROMIPS)
1043
1044 /* Likewise mtc1 and mfc1. */
1045 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1046 && !TARGET_MIPS5900 \
1047 && !TARGET_LOONGSON_2EF)
1048
1049 /* Likewise floating-point comparisons. */
1050 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1051 && !TARGET_MIPS5900 \
1052 && !TARGET_LOONGSON_2EF)
1053
1054 /* True if mflo and mfhi can be immediately followed by instructions
1055 which write to the HI and LO registers.
1056
1057 According to MIPS specifications, MIPS ISAs I, II, and III need
1058 (at least) two instructions between the reads of HI/LO and
1059 instructions which write them, and later ISAs do not. Contradicting
1060 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1061 the UM for the NEC Vr5000) document needing the instructions between
1062 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1063 MIPS64 and later ISAs to have the interlocks, plus any specific
1064 earlier-ISA CPUs for which CPU documentation declares that the
1065 instructions are really interlocked. */
1066 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1067 || ISA_MIPS32R2 \
1068 || ISA_MIPS64 \
1069 || ISA_MIPS64R2 \
1070 || TARGET_MIPS5500 \
1071 || TARGET_MIPS5900 \
1072 || TARGET_LOONGSON_2EF)
1073
1074 /* ISA includes synci, jr.hb and jalr.hb. */
1075 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1076 || ISA_MIPS64R2) \
1077 && !TARGET_MIPS16)
1078
1079 /* ISA includes sync. */
1080 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1081 #define GENERATE_SYNC \
1082 (target_flags_explicit & MASK_LLSC \
1083 ? TARGET_LLSC && !TARGET_MIPS16 \
1084 : ISA_HAS_SYNC)
1085
1086 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1087 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1088 instructions. */
1089 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1090 #define GENERATE_LL_SC \
1091 (target_flags_explicit & MASK_LLSC \
1092 ? TARGET_LLSC && !TARGET_MIPS16 \
1093 : ISA_HAS_LL_SC)
1094
1095 #define ISA_HAS_SWAP (TARGET_XLP)
1096 #define ISA_HAS_LDADD (TARGET_XLP)
1097
1098 /* ISA includes the baddu instruction. */
1099 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1100
1101 /* ISA includes the bbit* instructions. */
1102 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1103
1104 /* ISA includes the cins instruction. */
1105 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1106
1107 /* ISA includes the exts instruction. */
1108 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1109
1110 /* ISA includes the seq and sne instructions. */
1111 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1112
1113 /* ISA includes the pop instruction. */
1114 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1115
1116 /* The CACHE instruction is available in non-MIPS16 code. */
1117 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1118
1119 /* The CACHE instruction is available. */
1120 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1121 \f
1122 /* Tell collect what flags to pass to nm. */
1123 #ifndef NM_FLAGS
1124 #define NM_FLAGS "-Bn"
1125 #endif
1126
1127 \f
1128 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1129 the assembler. It may be overridden by subtargets.
1130
1131 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1132 COFF debugging info. */
1133
1134 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1135 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1136 %{g} %{g0} %{g1} %{g2} %{g3} \
1137 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1138 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1139 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1140 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1141 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1142 #endif
1143
1144 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1145 overridden by subtargets. */
1146
1147 #ifndef SUBTARGET_ASM_SPEC
1148 #define SUBTARGET_ASM_SPEC ""
1149 #endif
1150
1151 #undef ASM_SPEC
1152 #define ASM_SPEC "\
1153 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1154 %{mips32*} %{mips64*} \
1155 %{mips16} %{mno-mips16:-no-mips16} \
1156 %{mmicromips} %{mno-micromips} \
1157 %{mips3d} %{mno-mips3d:-no-mips3d} \
1158 %{mdmx} %{mno-mdmx:-no-mdmx} \
1159 %{mdsp} %{mno-dsp} \
1160 %{mdspr2} %{mno-dspr2} \
1161 %{mmcu} %{mno-mcu} \
1162 %{meva} %{mno-eva} \
1163 %{msmartmips} %{mno-smartmips} \
1164 %{mmt} %{mno-mt} \
1165 %{mfix-vr4120} %{mfix-vr4130} \
1166 %{mfix-24k} \
1167 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1168 %(subtarget_asm_debugging_spec) \
1169 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1170 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1171 %{mfp32} %{mfp64} %{mnan=*} \
1172 %{mshared} %{mno-shared} \
1173 %{msym32} %{mno-sym32} \
1174 %{mtune=*} \
1175 %(subtarget_asm_spec)"
1176
1177 /* Extra switches sometimes passed to the linker. */
1178
1179 #ifndef LINK_SPEC
1180 #define LINK_SPEC "\
1181 %(endian_spec) \
1182 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1183 %{shared}"
1184 #endif /* LINK_SPEC defined */
1185
1186
1187 /* Specs for the compiler proper */
1188
1189 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1190 overridden by subtargets. */
1191 #ifndef SUBTARGET_CC1_SPEC
1192 #define SUBTARGET_CC1_SPEC ""
1193 #endif
1194
1195 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1196
1197 #undef CC1_SPEC
1198 #define CC1_SPEC "\
1199 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1200 %(subtarget_cc1_spec)"
1201
1202 /* Preprocessor specs. */
1203
1204 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1205 overridden by subtargets. */
1206 #ifndef SUBTARGET_CPP_SPEC
1207 #define SUBTARGET_CPP_SPEC ""
1208 #endif
1209
1210 #define CPP_SPEC "%(subtarget_cpp_spec)"
1211
1212 /* This macro defines names of additional specifications to put in the specs
1213 that can be used in various specifications like CC1_SPEC. Its definition
1214 is an initializer with a subgrouping for each command option.
1215
1216 Each subgrouping contains a string constant, that defines the
1217 specification name, and a string constant that used by the GCC driver
1218 program.
1219
1220 Do not define this macro if it does not need to do anything. */
1221
1222 #define EXTRA_SPECS \
1223 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1224 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1225 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1226 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1227 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1228 { "endian_spec", ENDIAN_SPEC }, \
1229 SUBTARGET_EXTRA_SPECS
1230
1231 #ifndef SUBTARGET_EXTRA_SPECS
1232 #define SUBTARGET_EXTRA_SPECS
1233 #endif
1234 \f
1235 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1236 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1237
1238 #ifndef PREFERRED_DEBUGGING_TYPE
1239 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1240 #endif
1241
1242 /* The size of DWARF addresses should be the same as the size of symbols
1243 in the target file format. They shouldn't depend on things like -msym32,
1244 because many DWARF consumers do not allow the mixture of address sizes
1245 that one would then get from linking -msym32 code with -msym64 code.
1246
1247 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1248 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1249 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1250
1251 /* By default, turn on GDB extensions. */
1252 #define DEFAULT_GDB_EXTENSIONS 1
1253
1254 /* Local compiler-generated symbols must have a prefix that the assembler
1255 understands. By default, this is $, although some targets (e.g.,
1256 NetBSD-ELF) need to override this. */
1257
1258 #ifndef LOCAL_LABEL_PREFIX
1259 #define LOCAL_LABEL_PREFIX "$"
1260 #endif
1261
1262 /* By default on the mips, external symbols do not have an underscore
1263 prepended, but some targets (e.g., NetBSD) require this. */
1264
1265 #ifndef USER_LABEL_PREFIX
1266 #define USER_LABEL_PREFIX ""
1267 #endif
1268
1269 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1270 since the length can run past this up to a continuation point. */
1271 #undef DBX_CONTIN_LENGTH
1272 #define DBX_CONTIN_LENGTH 1500
1273
1274 /* How to renumber registers for dbx and gdb. */
1275 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1276
1277 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1278 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1279
1280 /* The DWARF 2 CFA column which tracks the return address. */
1281 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1282
1283 /* Before the prologue, RA lives in r31. */
1284 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1285
1286 /* Describe how we implement __builtin_eh_return. */
1287 #define EH_RETURN_DATA_REGNO(N) \
1288 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1289
1290 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1291
1292 #define EH_USES(N) mips_eh_uses (N)
1293
1294 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1295 The default for this in 64-bit mode is 8, which causes problems with
1296 SFmode register saves. */
1297 #define DWARF_CIE_DATA_ALIGNMENT -4
1298
1299 /* Correct the offset of automatic variables and arguments. Note that
1300 the MIPS debug format wants all automatic variables and arguments
1301 to be in terms of the virtual frame pointer (stack pointer before
1302 any adjustment in the function), while the MIPS 3.0 linker wants
1303 the frame pointer to be the stack pointer after the initial
1304 adjustment. */
1305
1306 #define DEBUGGER_AUTO_OFFSET(X) \
1307 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1308 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1309 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1310 \f
1311 /* Target machine storage layout */
1312
1313 #define BITS_BIG_ENDIAN 0
1314 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1315 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1316
1317 #define MAX_BITS_PER_WORD 64
1318
1319 /* Width of a word, in units (bytes). */
1320 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1321 #ifndef IN_LIBGCC2
1322 #define MIN_UNITS_PER_WORD 4
1323 #endif
1324
1325 /* For MIPS, width of a floating point register. */
1326 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1327
1328 /* The number of consecutive floating-point registers needed to store the
1329 largest format supported by the FPU. */
1330 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1331
1332 /* The number of consecutive floating-point registers needed to store the
1333 smallest format supported by the FPU. */
1334 #define MIN_FPRS_PER_FMT \
1335 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1336 ? 1 : MAX_FPRS_PER_FMT)
1337
1338 /* The largest size of value that can be held in floating-point
1339 registers and moved with a single instruction. */
1340 #define UNITS_PER_HWFPVALUE \
1341 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1342
1343 /* The largest size of value that can be held in floating-point
1344 registers. */
1345 #define UNITS_PER_FPVALUE \
1346 (TARGET_SOFT_FLOAT_ABI ? 0 \
1347 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1348 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1349
1350 /* The number of bytes in a double. */
1351 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1352
1353 /* Set the sizes of the core types. */
1354 #define SHORT_TYPE_SIZE 16
1355 #define INT_TYPE_SIZE 32
1356 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1357 #define LONG_LONG_TYPE_SIZE 64
1358
1359 #define FLOAT_TYPE_SIZE 32
1360 #define DOUBLE_TYPE_SIZE 64
1361 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1362
1363 /* Define the sizes of fixed-point types. */
1364 #define SHORT_FRACT_TYPE_SIZE 8
1365 #define FRACT_TYPE_SIZE 16
1366 #define LONG_FRACT_TYPE_SIZE 32
1367 #define LONG_LONG_FRACT_TYPE_SIZE 64
1368
1369 #define SHORT_ACCUM_TYPE_SIZE 16
1370 #define ACCUM_TYPE_SIZE 32
1371 #define LONG_ACCUM_TYPE_SIZE 64
1372 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1373 doesn't support 128-bit integers for MIPS32 currently. */
1374 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1375
1376 /* long double is not a fixed mode, but the idea is that, if we
1377 support long double, we also want a 128-bit integer type. */
1378 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1379
1380 #ifdef IN_LIBGCC2
1381 #if ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1382 || (defined _ABI64 && _MIPS_SIM == _ABI64))
1383 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1384 # else
1385 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1386 # endif
1387 #endif
1388
1389 /* Width in bits of a pointer. */
1390 #ifndef POINTER_SIZE
1391 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1392 #endif
1393
1394 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1395 #define PARM_BOUNDARY BITS_PER_WORD
1396
1397 /* Allocation boundary (in *bits*) for the code of a function. */
1398 #define FUNCTION_BOUNDARY 32
1399
1400 /* Alignment of field after `int : 0' in a structure. */
1401 #define EMPTY_FIELD_BOUNDARY 32
1402
1403 /* Every structure's size must be a multiple of this. */
1404 /* 8 is observed right on a DECstation and on riscos 4.02. */
1405 #define STRUCTURE_SIZE_BOUNDARY 8
1406
1407 /* There is no point aligning anything to a rounder boundary than this. */
1408 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1409
1410 /* All accesses must be aligned. */
1411 #define STRICT_ALIGNMENT 1
1412
1413 /* Define this if you wish to imitate the way many other C compilers
1414 handle alignment of bitfields and the structures that contain
1415 them.
1416
1417 The behavior is that the type written for a bit-field (`int',
1418 `short', or other integer type) imposes an alignment for the
1419 entire structure, as if the structure really did contain an
1420 ordinary field of that type. In addition, the bit-field is placed
1421 within the structure so that it would fit within such a field,
1422 not crossing a boundary for it.
1423
1424 Thus, on most machines, a bit-field whose type is written as `int'
1425 would not cross a four-byte boundary, and would force four-byte
1426 alignment for the whole structure. (The alignment used may not
1427 be four bytes; it is controlled by the other alignment
1428 parameters.)
1429
1430 If the macro is defined, its definition should be a C expression;
1431 a nonzero value for the expression enables this behavior. */
1432
1433 #define PCC_BITFIELD_TYPE_MATTERS 1
1434
1435 /* If defined, a C expression to compute the alignment given to a
1436 constant that is being placed in memory. CONSTANT is the constant
1437 and ALIGN is the alignment that the object would ordinarily have.
1438 The value of this macro is used instead of that alignment to align
1439 the object.
1440
1441 If this macro is not defined, then ALIGN is used.
1442
1443 The typical use of this macro is to increase alignment for string
1444 constants to be word aligned so that `strcpy' calls that copy
1445 constants can be done inline. */
1446
1447 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1448 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1449 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1450
1451 /* If defined, a C expression to compute the alignment for a static
1452 variable. TYPE is the data type, and ALIGN is the alignment that
1453 the object would ordinarily have. The value of this macro is used
1454 instead of that alignment to align the object.
1455
1456 If this macro is not defined, then ALIGN is used.
1457
1458 One use of this macro is to increase alignment of medium-size
1459 data to make it all fit in fewer cache lines. Another is to
1460 cause character arrays to be word-aligned so that `strcpy' calls
1461 that copy constants to character arrays can be done inline. */
1462
1463 #undef DATA_ALIGNMENT
1464 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1465 ((((ALIGN) < BITS_PER_WORD) \
1466 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1467 || TREE_CODE (TYPE) == UNION_TYPE \
1468 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1469
1470 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1471 character arrays to be word-aligned so that `strcpy' calls that copy
1472 constants to character arrays can be done inline, and 'strcmp' can be
1473 optimised to use word loads. */
1474 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1475 DATA_ALIGNMENT (TYPE, ALIGN)
1476
1477 #define PAD_VARARGS_DOWN \
1478 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1479
1480 /* Define if operations between registers always perform the operation
1481 on the full register even if a narrower mode is specified. */
1482 #define WORD_REGISTER_OPERATIONS
1483
1484 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1485 moves. All other references are zero extended. */
1486 #define LOAD_EXTEND_OP(MODE) \
1487 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1488 ? SIGN_EXTEND : ZERO_EXTEND)
1489
1490 /* Define this macro if it is advisable to hold scalars in registers
1491 in a wider mode than that declared by the program. In such cases,
1492 the value is constrained to be within the bounds of the declared
1493 type, but kept valid in the wider mode. The signedness of the
1494 extension may differ from that of the type. */
1495
1496 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1497 if (GET_MODE_CLASS (MODE) == MODE_INT \
1498 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1499 { \
1500 if ((MODE) == SImode) \
1501 (UNSIGNEDP) = 0; \
1502 (MODE) = Pmode; \
1503 }
1504
1505 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1506 Extensions of pointers to word_mode must be signed. */
1507 #define POINTERS_EXTEND_UNSIGNED false
1508
1509 /* Define if loading short immediate values into registers sign extends. */
1510 #define SHORT_IMMEDIATES_SIGN_EXTEND
1511
1512 /* The [d]clz instructions have the natural values at 0. */
1513
1514 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1515 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1516 \f
1517 /* Standard register usage. */
1518
1519 /* Number of hardware registers. We have:
1520
1521 - 32 integer registers
1522 - 32 floating point registers
1523 - 8 condition code registers
1524 - 2 accumulator registers (hi and lo)
1525 - 32 registers each for coprocessors 0, 2 and 3
1526 - 4 fake registers:
1527 - ARG_POINTER_REGNUM
1528 - FRAME_POINTER_REGNUM
1529 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1530 - CPRESTORE_SLOT_REGNUM
1531 - 2 dummy entries that were used at various times in the past.
1532 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1533 - 6 DSP control registers */
1534
1535 #define FIRST_PSEUDO_REGISTER 188
1536
1537 /* By default, fix the kernel registers ($26 and $27), the global
1538 pointer ($28) and the stack pointer ($29). This can change
1539 depending on the command-line options.
1540
1541 Regarding coprocessor registers: without evidence to the contrary,
1542 it's best to assume that each coprocessor register has a unique
1543 use. This can be overridden, in, e.g., mips_option_override or
1544 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1545 inappropriate for a particular target. */
1546
1547 #define FIXED_REGISTERS \
1548 { \
1549 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1550 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1551 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1552 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1553 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1554 /* COP0 registers */ \
1555 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1557 /* COP2 registers */ \
1558 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1559 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1560 /* COP3 registers */ \
1561 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1562 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1563 /* 6 DSP accumulator registers & 6 control registers */ \
1564 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1565 }
1566
1567
1568 /* Set up this array for o32 by default.
1569
1570 Note that we don't mark $31 as a call-clobbered register. The idea is
1571 that it's really the call instructions themselves which clobber $31.
1572 We don't care what the called function does with it afterwards.
1573
1574 This approach makes it easier to implement sibcalls. Unlike normal
1575 calls, sibcalls don't clobber $31, so the register reaches the
1576 called function in tact. EPILOGUE_USES says that $31 is useful
1577 to the called function. */
1578
1579 #define CALL_USED_REGISTERS \
1580 { \
1581 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1582 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1583 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1584 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1585 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1586 /* COP0 registers */ \
1587 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1588 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1589 /* COP2 registers */ \
1590 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1591 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1592 /* COP3 registers */ \
1593 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1594 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1595 /* 6 DSP accumulator registers & 6 control registers */ \
1596 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1597 }
1598
1599
1600 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1601
1602 #define CALL_REALLY_USED_REGISTERS \
1603 { /* General registers. */ \
1604 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1605 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1606 /* Floating-point registers. */ \
1607 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1608 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1609 /* Others. */ \
1610 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1611 /* COP0 registers */ \
1612 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1613 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1614 /* COP2 registers */ \
1615 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1616 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1617 /* COP3 registers */ \
1618 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1619 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1620 /* 6 DSP accumulator registers & 6 control registers */ \
1621 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1622 }
1623
1624 /* Internal macros to classify a register number as to whether it's a
1625 general purpose register, a floating point register, a
1626 multiply/divide register, or a status register. */
1627
1628 #define GP_REG_FIRST 0
1629 #define GP_REG_LAST 31
1630 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1631 #define GP_DBX_FIRST 0
1632 #define K0_REG_NUM (GP_REG_FIRST + 26)
1633 #define K1_REG_NUM (GP_REG_FIRST + 27)
1634 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1635
1636 #define FP_REG_FIRST 32
1637 #define FP_REG_LAST 63
1638 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1639 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1640
1641 #define MD_REG_FIRST 64
1642 #define MD_REG_LAST 65
1643 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1644 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1645
1646 /* The DWARF 2 CFA column which tracks the return address from a
1647 signal handler context. This means that to maintain backwards
1648 compatibility, no hard register can be assigned this column if it
1649 would need to be handled by the DWARF unwinder. */
1650 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1651
1652 #define ST_REG_FIRST 67
1653 #define ST_REG_LAST 74
1654 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1655
1656
1657 /* FIXME: renumber. */
1658 #define COP0_REG_FIRST 80
1659 #define COP0_REG_LAST 111
1660 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1661
1662 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1663 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1664 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1665
1666 #define COP2_REG_FIRST 112
1667 #define COP2_REG_LAST 143
1668 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1669
1670 #define COP3_REG_FIRST 144
1671 #define COP3_REG_LAST 175
1672 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1673
1674 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1675 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1676 #define ALL_COP_REG_LAST COP3_REG_LAST
1677 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1678
1679 #define DSP_ACC_REG_FIRST 176
1680 #define DSP_ACC_REG_LAST 181
1681 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1682
1683 #define AT_REGNUM (GP_REG_FIRST + 1)
1684 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1685 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1686
1687 /* A few bitfield locations for the coprocessor registers. */
1688 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1689 the cause register for the EIC interrupt mode. */
1690 #define CAUSE_IPL 10
1691 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1692 #define SR_IPL 10
1693 /* Exception Level is at bit 1 of the status register. */
1694 #define SR_EXL 1
1695 /* Interrupt Enable is at bit 0 of the status register. */
1696 #define SR_IE 0
1697
1698 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1699 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1700 should be used instead. */
1701 #define FPSW_REGNUM ST_REG_FIRST
1702
1703 #define GP_REG_P(REGNO) \
1704 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1705 #define M16_REG_P(REGNO) \
1706 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1707 #define M16STORE_REG_P(REGNO) \
1708 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1709 #define FP_REG_P(REGNO) \
1710 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1711 #define MD_REG_P(REGNO) \
1712 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1713 #define ST_REG_P(REGNO) \
1714 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1715 #define COP0_REG_P(REGNO) \
1716 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1717 #define COP2_REG_P(REGNO) \
1718 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1719 #define COP3_REG_P(REGNO) \
1720 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1721 #define ALL_COP_REG_P(REGNO) \
1722 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1723 /* Test if REGNO is one of the 6 new DSP accumulators. */
1724 #define DSP_ACC_REG_P(REGNO) \
1725 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1726 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1727 #define ACC_REG_P(REGNO) \
1728 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1729
1730 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1731
1732 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1733 to initialize the mips16 gp pseudo register. */
1734 #define CONST_GP_P(X) \
1735 (GET_CODE (X) == CONST \
1736 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1737 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1738
1739 /* Return coprocessor number from register number. */
1740
1741 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1742 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1743 : COP3_REG_P (REGNO) ? '3' : '?')
1744
1745
1746 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1747
1748 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1749 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1750
1751 #define MODES_TIEABLE_P mips_modes_tieable_p
1752
1753 /* Register to use for pushing function arguments. */
1754 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1755
1756 /* These two registers don't really exist: they get eliminated to either
1757 the stack or hard frame pointer. */
1758 #define ARG_POINTER_REGNUM 77
1759 #define FRAME_POINTER_REGNUM 78
1760
1761 /* $30 is not available on the mips16, so we use $17 as the frame
1762 pointer. */
1763 #define HARD_FRAME_POINTER_REGNUM \
1764 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1765
1766 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1767 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1768
1769 /* Register in which static-chain is passed to a function. */
1770 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1771
1772 /* Registers used as temporaries in prologue/epilogue code:
1773
1774 - If a MIPS16 PIC function needs access to _gp, it first loads
1775 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1776
1777 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1778 register. The register must not conflict with MIPS16_PIC_TEMP.
1779
1780 - If we aren't generating MIPS16 code, the prologue can also use
1781 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1782
1783 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1784 register.
1785
1786 If we're generating MIPS16 code, these registers must come from the
1787 core set of 8. The prologue registers mustn't conflict with any
1788 incoming arguments, the static chain pointer, or the frame pointer.
1789 The epilogue temporary mustn't conflict with the return registers,
1790 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1791 or the EH data registers.
1792
1793 If we're generating interrupt handlers, we use K0 as a temporary register
1794 in prologue/epilogue code. */
1795
1796 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1797 #define MIPS_PROLOGUE_TEMP_REGNUM \
1798 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1799 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1800 (TARGET_MIPS16 \
1801 ? (gcc_unreachable (), INVALID_REGNUM) \
1802 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1803 #define MIPS_EPILOGUE_TEMP_REGNUM \
1804 (cfun->machine->interrupt_handler_p \
1805 ? K0_REG_NUM \
1806 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1807
1808 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1809 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1810 #define MIPS_PROLOGUE_TEMP2(MODE) \
1811 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1812 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1813
1814 /* Define this macro if it is as good or better to call a constant
1815 function address than to call an address kept in a register. */
1816 #define NO_FUNCTION_CSE 1
1817
1818 /* The ABI-defined global pointer. Sometimes we use a different
1819 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1820 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1821
1822 /* We normally use $28 as the global pointer. However, when generating
1823 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1824 register instead. They can then avoid saving and restoring $28
1825 and perhaps avoid using a frame at all.
1826
1827 When a leaf function uses something other than $28, mips_expand_prologue
1828 will modify pic_offset_table_rtx in place. Take the register number
1829 from there after reload. */
1830 #define PIC_OFFSET_TABLE_REGNUM \
1831 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1832 \f
1833 /* Define the classes of registers for register constraints in the
1834 machine description. Also define ranges of constants.
1835
1836 One of the classes must always be named ALL_REGS and include all hard regs.
1837 If there is more than one class, another class must be named NO_REGS
1838 and contain no registers.
1839
1840 The name GENERAL_REGS must be the name of a class (or an alias for
1841 another name such as ALL_REGS). This is the class of registers
1842 that is allowed by "g" or "r" in a register constraint.
1843 Also, registers outside this class are allocated only when
1844 instructions express preferences for them.
1845
1846 The classes must be numbered in nondecreasing order; that is,
1847 a larger-numbered class must never be contained completely
1848 in a smaller-numbered class.
1849
1850 For any two classes, it is very desirable that there be another
1851 class that represents their union. */
1852
1853 enum reg_class
1854 {
1855 NO_REGS, /* no registers in set */
1856 M16_REGS, /* mips16 directly accessible registers */
1857 T_REG, /* mips16 T register ($24) */
1858 M16_T_REGS, /* mips16 registers plus T register */
1859 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1860 V1_REG, /* Register $v1 ($3) used for TLS access. */
1861 LEA_REGS, /* Every GPR except $25 */
1862 GR_REGS, /* integer registers */
1863 FP_REGS, /* floating point registers */
1864 MD0_REG, /* first multiply/divide register */
1865 MD1_REG, /* second multiply/divide register */
1866 MD_REGS, /* multiply/divide registers (hi/lo) */
1867 COP0_REGS, /* generic coprocessor classes */
1868 COP2_REGS,
1869 COP3_REGS,
1870 ST_REGS, /* status registers (fp status) */
1871 DSP_ACC_REGS, /* DSP accumulator registers */
1872 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1873 FRAME_REGS, /* $arg and $frame */
1874 GR_AND_MD0_REGS, /* union classes */
1875 GR_AND_MD1_REGS,
1876 GR_AND_MD_REGS,
1877 GR_AND_ACC_REGS,
1878 ALL_REGS, /* all registers */
1879 LIM_REG_CLASSES /* max value + 1 */
1880 };
1881
1882 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1883
1884 #define GENERAL_REGS GR_REGS
1885
1886 /* An initializer containing the names of the register classes as C
1887 string constants. These names are used in writing some of the
1888 debugging dumps. */
1889
1890 #define REG_CLASS_NAMES \
1891 { \
1892 "NO_REGS", \
1893 "M16_REGS", \
1894 "T_REG", \
1895 "M16_T_REGS", \
1896 "PIC_FN_ADDR_REG", \
1897 "V1_REG", \
1898 "LEA_REGS", \
1899 "GR_REGS", \
1900 "FP_REGS", \
1901 "MD0_REG", \
1902 "MD1_REG", \
1903 "MD_REGS", \
1904 /* coprocessor registers */ \
1905 "COP0_REGS", \
1906 "COP2_REGS", \
1907 "COP3_REGS", \
1908 "ST_REGS", \
1909 "DSP_ACC_REGS", \
1910 "ACC_REGS", \
1911 "FRAME_REGS", \
1912 "GR_AND_MD0_REGS", \
1913 "GR_AND_MD1_REGS", \
1914 "GR_AND_MD_REGS", \
1915 "GR_AND_ACC_REGS", \
1916 "ALL_REGS" \
1917 }
1918
1919 /* An initializer containing the contents of the register classes,
1920 as integers which are bit masks. The Nth integer specifies the
1921 contents of class N. The way the integer MASK is interpreted is
1922 that register R is in the class if `MASK & (1 << R)' is 1.
1923
1924 When the machine has more than 32 registers, an integer does not
1925 suffice. Then the integers are replaced by sub-initializers,
1926 braced groupings containing several integers. Each
1927 sub-initializer must be suitable as an initializer for the type
1928 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1929
1930 #define REG_CLASS_CONTENTS \
1931 { \
1932 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1933 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1934 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1935 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1936 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1937 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1938 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1939 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1940 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1941 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1942 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1943 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1944 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1945 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1946 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1947 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1948 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1949 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1950 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1951 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1952 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1953 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1954 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1955 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1956 }
1957
1958
1959 /* A C expression whose value is a register class containing hard
1960 register REGNO. In general there is more that one such class;
1961 choose a class which is "minimal", meaning that no smaller class
1962 also contains the register. */
1963
1964 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1965
1966 /* A macro whose definition is the name of the class to which a
1967 valid base register must belong. A base register is one used in
1968 an address which is the register value plus a displacement. */
1969
1970 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1971
1972 /* A macro whose definition is the name of the class to which a
1973 valid index register must belong. An index register is one used
1974 in an address where its value is either multiplied by a scale
1975 factor or added to another register (as well as added to a
1976 displacement). */
1977
1978 #define INDEX_REG_CLASS NO_REGS
1979
1980 /* We generally want to put call-clobbered registers ahead of
1981 call-saved ones. (IRA expects this.) */
1982
1983 #define REG_ALLOC_ORDER \
1984 { /* Accumulator registers. When GPRs and accumulators have equal \
1985 cost, we generally prefer to use accumulators. For example, \
1986 a division of multiplication result is better allocated to LO, \
1987 so that we put the MFLO at the point of use instead of at the \
1988 point of definition. It's also needed if we're to take advantage \
1989 of the extra accumulators available with -mdspr2. In some cases, \
1990 it can also help to reduce register pressure. */ \
1991 64, 65,176,177,178,179,180,181, \
1992 /* Call-clobbered GPRs. */ \
1993 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1994 24, 25, 31, \
1995 /* The global pointer. This is call-clobbered for o32 and o64 \
1996 abicalls, call-saved for n32 and n64 abicalls, and a program \
1997 invariant otherwise. Putting it between the call-clobbered \
1998 and call-saved registers should cope with all eventualities. */ \
1999 28, \
2000 /* Call-saved GPRs. */ \
2001 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2002 /* GPRs that can never be exposed to the register allocator. */ \
2003 0, 26, 27, 29, \
2004 /* Call-clobbered FPRs. */ \
2005 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2006 48, 49, 50, 51, \
2007 /* FPRs that are usually call-saved. The odd ones are actually \
2008 call-clobbered for n32, but listing them ahead of the even \
2009 registers might encourage the register allocator to fragment \
2010 the available FPR pairs. We need paired FPRs to store long \
2011 doubles, so it isn't clear that using a different order \
2012 for n32 would be a win. */ \
2013 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2014 /* None of the remaining classes have defined call-saved \
2015 registers. */ \
2016 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2017 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2018 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2019 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2020 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2021 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2022 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2023 182,183,184,185,186,187 \
2024 }
2025
2026 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
2027 to be rearranged based on a particular function. On the mips16, we
2028 want to allocate $24 (T_REG) before other registers for
2029 instructions for which it is possible. */
2030
2031 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2032
2033 /* True if VALUE is an unsigned 6-bit number. */
2034
2035 #define UIMM6_OPERAND(VALUE) \
2036 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2037
2038 /* True if VALUE is a signed 10-bit number. */
2039
2040 #define IMM10_OPERAND(VALUE) \
2041 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2042
2043 /* True if VALUE is a signed 16-bit number. */
2044
2045 #define SMALL_OPERAND(VALUE) \
2046 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2047
2048 /* True if VALUE is an unsigned 16-bit number. */
2049
2050 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2051 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2052
2053 /* True if VALUE can be loaded into a register using LUI. */
2054
2055 #define LUI_OPERAND(VALUE) \
2056 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2057 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2058
2059 /* Return a value X with the low 16 bits clear, and such that
2060 VALUE - X is a signed 16-bit value. */
2061
2062 #define CONST_HIGH_PART(VALUE) \
2063 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2064
2065 #define CONST_LOW_PART(VALUE) \
2066 ((VALUE) - CONST_HIGH_PART (VALUE))
2067
2068 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2069 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2070 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2071 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2072
2073 /* The HI and LO registers can only be reloaded via the general
2074 registers. Condition code registers can only be loaded to the
2075 general registers, and from the floating point registers. */
2076
2077 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2078 mips_secondary_reload_class (CLASS, MODE, X, true)
2079 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2080 mips_secondary_reload_class (CLASS, MODE, X, false)
2081
2082 /* Return the maximum number of consecutive registers
2083 needed to represent mode MODE in a register of class CLASS. */
2084
2085 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2086
2087 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2088 mips_cannot_change_mode_class (FROM, TO, CLASS)
2089 \f
2090 /* Stack layout; function entry, exit and calling. */
2091
2092 #define STACK_GROWS_DOWNWARD
2093
2094 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2095
2096 /* Size of the area allocated in the frame to save the GP. */
2097
2098 #define MIPS_GP_SAVE_AREA_SIZE \
2099 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2100
2101 /* The offset of the first local variable from the frame pointer. See
2102 mips_compute_frame_info for details about the frame layout. */
2103
2104 #define STARTING_FRAME_OFFSET \
2105 (FRAME_GROWS_DOWNWARD \
2106 ? 0 \
2107 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2108
2109 #define RETURN_ADDR_RTX mips_return_addr
2110
2111 /* Mask off the MIPS16 ISA bit in unwind addresses.
2112
2113 The reason for this is a little subtle. When unwinding a call,
2114 we are given the call's return address, which on most targets
2115 is the address of the following instruction. However, what we
2116 actually want to find is the EH region for the call itself.
2117 The target-independent unwind code therefore searches for "RA - 1".
2118
2119 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2120 RA - 1 is therefore the real (even-valued) start of the return
2121 instruction. EH region labels are usually odd-valued MIPS16 symbols
2122 too, so a search for an even address within a MIPS16 region would
2123 usually work.
2124
2125 However, there is an exception. If the end of an EH region is also
2126 the end of a function, the end label is allowed to be even. This is
2127 necessary because a following non-MIPS16 function may also need EH
2128 information for its first instruction.
2129
2130 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2131 non-ISA-encoded address. This probably isn't ideal, but it is
2132 the traditional (legacy) behavior. It is therefore only safe
2133 to search MIPS EH regions for an _odd-valued_ address.
2134
2135 Masking off the ISA bit means that the target-independent code
2136 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2137 #define MASK_RETURN_ADDR GEN_INT (-2)
2138
2139
2140 /* Similarly, don't use the least-significant bit to tell pointers to
2141 code from vtable index. */
2142
2143 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2144
2145 /* The eliminations to $17 are only used for mips16 code. See the
2146 definition of HARD_FRAME_POINTER_REGNUM. */
2147
2148 #define ELIMINABLE_REGS \
2149 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2150 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2151 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2152 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2153 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2154 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2155
2156 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2157 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2158
2159 /* Allocate stack space for arguments at the beginning of each function. */
2160 #define ACCUMULATE_OUTGOING_ARGS 1
2161
2162 /* The argument pointer always points to the first argument. */
2163 #define FIRST_PARM_OFFSET(FNDECL) 0
2164
2165 /* o32 and o64 reserve stack space for all argument registers. */
2166 #define REG_PARM_STACK_SPACE(FNDECL) \
2167 (TARGET_OLDABI \
2168 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2169 : 0)
2170
2171 /* Define this if it is the responsibility of the caller to
2172 allocate the area reserved for arguments passed in registers.
2173 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2174 of this macro is to determine whether the space is included in
2175 `crtl->outgoing_args_size'. */
2176 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2177
2178 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2179 \f
2180 /* Symbolic macros for the registers used to return integer and floating
2181 point values. */
2182
2183 #define GP_RETURN (GP_REG_FIRST + 2)
2184 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2185
2186 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2187
2188 /* Symbolic macros for the first/last argument registers. */
2189
2190 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2191 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2192 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2193 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2194
2195 /* 1 if N is a possible register number for function argument passing.
2196 We have no FP argument registers when soft-float. When FP registers
2197 are 32 bits, we can't directly reference the odd numbered ones. */
2198
2199 #define FUNCTION_ARG_REGNO_P(N) \
2200 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2201 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2202 && !fixed_regs[N])
2203 \f
2204 /* This structure has to cope with two different argument allocation
2205 schemes. Most MIPS ABIs view the arguments as a structure, of which
2206 the first N words go in registers and the rest go on the stack. If I
2207 < N, the Ith word might go in Ith integer argument register or in a
2208 floating-point register. For these ABIs, we only need to remember
2209 the offset of the current argument into the structure.
2210
2211 The EABI instead allocates the integer and floating-point arguments
2212 separately. The first N words of FP arguments go in FP registers,
2213 the rest go on the stack. Likewise, the first N words of the other
2214 arguments go in integer registers, and the rest go on the stack. We
2215 need to maintain three counts: the number of integer registers used,
2216 the number of floating-point registers used, and the number of words
2217 passed on the stack.
2218
2219 We could keep separate information for the two ABIs (a word count for
2220 the standard ABIs, and three separate counts for the EABI). But it
2221 seems simpler to view the standard ABIs as forms of EABI that do not
2222 allocate floating-point registers.
2223
2224 So for the standard ABIs, the first N words are allocated to integer
2225 registers, and mips_function_arg decides on an argument-by-argument
2226 basis whether that argument should really go in an integer register,
2227 or in a floating-point one. */
2228
2229 typedef struct mips_args {
2230 /* Always true for varargs functions. Otherwise true if at least
2231 one argument has been passed in an integer register. */
2232 int gp_reg_found;
2233
2234 /* The number of arguments seen so far. */
2235 unsigned int arg_number;
2236
2237 /* The number of integer registers used so far. For all ABIs except
2238 EABI, this is the number of words that have been added to the
2239 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2240 unsigned int num_gprs;
2241
2242 /* For EABI, the number of floating-point registers used so far. */
2243 unsigned int num_fprs;
2244
2245 /* The number of words passed on the stack. */
2246 unsigned int stack_words;
2247
2248 /* On the mips16, we need to keep track of which floating point
2249 arguments were passed in general registers, but would have been
2250 passed in the FP regs if this were a 32-bit function, so that we
2251 can move them to the FP regs if we wind up calling a 32-bit
2252 function. We record this information in fp_code, encoded in base
2253 four. A zero digit means no floating point argument, a one digit
2254 means an SFmode argument, and a two digit means a DFmode argument,
2255 and a three digit is not used. The low order digit is the first
2256 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2257 an SFmode argument. ??? A more sophisticated approach will be
2258 needed if MIPS_ABI != ABI_32. */
2259 int fp_code;
2260
2261 /* True if the function has a prototype. */
2262 int prototype;
2263 } CUMULATIVE_ARGS;
2264
2265 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2266 for a call to a function whose data type is FNTYPE.
2267 For a library call, FNTYPE is 0. */
2268
2269 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2270 mips_init_cumulative_args (&CUM, FNTYPE)
2271
2272 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2273 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2274
2275 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2276 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2277
2278 /* True if using EABI and varargs can be passed in floating-point
2279 registers. Under these conditions, we need a more complex form
2280 of va_list, which tracks GPR, FPR and stack arguments separately. */
2281 #define EABI_FLOAT_VARARGS_P \
2282 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2283
2284 \f
2285 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2286
2287 /* Treat LOC as a byte offset from the stack pointer and round it up
2288 to the next fully-aligned offset. */
2289 #define MIPS_STACK_ALIGN(LOC) \
2290 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2291
2292 \f
2293 /* Output assembler code to FILE to increment profiler label # LABELNO
2294 for profiling a function entry. */
2295
2296 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2297
2298 /* The profiler preserves all interesting registers, including $31. */
2299 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2300
2301 /* No mips port has ever used the profiler counter word, so don't emit it
2302 or the label for it. */
2303
2304 #define NO_PROFILE_COUNTERS 1
2305
2306 /* Define this macro if the code for function profiling should come
2307 before the function prologue. Normally, the profiling code comes
2308 after. */
2309
2310 /* #define PROFILE_BEFORE_PROLOGUE */
2311
2312 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2313 the stack pointer does not matter. The value is tested only in
2314 functions that have frame pointers.
2315 No definition is equivalent to always zero. */
2316
2317 #define EXIT_IGNORE_STACK 1
2318
2319 \f
2320 /* Trampolines are a block of code followed by two pointers. */
2321
2322 #define TRAMPOLINE_SIZE \
2323 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2324
2325 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2326 pointers from a single LUI base. */
2327
2328 #define TRAMPOLINE_ALIGNMENT 64
2329
2330 /* mips_trampoline_init calls this library function to flush
2331 program and data caches. */
2332
2333 #ifndef CACHE_FLUSH_FUNC
2334 #define CACHE_FLUSH_FUNC "_flush_cache"
2335 #endif
2336
2337 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2338 /* Flush both caches. We need to flush the data cache in case \
2339 the system has a write-back cache. */ \
2340 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2341 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2342 GEN_INT (3), TYPE_MODE (integer_type_node))
2343
2344 \f
2345 /* Addressing modes, and classification of registers for them. */
2346
2347 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2348 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2349 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2350 \f
2351 /* Maximum number of registers that can appear in a valid memory address. */
2352
2353 #define MAX_REGS_PER_ADDRESS 1
2354
2355 /* Check for constness inline but use mips_legitimate_address_p
2356 to check whether a constant really is an address. */
2357
2358 #define CONSTANT_ADDRESS_P(X) \
2359 (CONSTANT_P (X) && memory_address_p (SImode, X))
2360
2361 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2362 'the start of the function that this code is output in'. */
2363
2364 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2365 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2366 asm_fprintf ((FILE), "%U%s", \
2367 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2368 else \
2369 asm_fprintf ((FILE), "%U%s", (NAME))
2370 \f
2371 /* Flag to mark a function decl symbol that requires a long call. */
2372 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2373 #define SYMBOL_REF_LONG_CALL_P(X) \
2374 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2375
2376 /* This flag marks functions that cannot be lazily bound. */
2377 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2378 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2379 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2380
2381 /* True if we're generating a form of MIPS16 code in which jump tables
2382 are stored in the text section and encoded as 16-bit PC-relative
2383 offsets. This is only possible when general text loads are allowed,
2384 since the table access itself will be an "lh" instruction. If the
2385 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2386 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2387
2388 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2389
2390 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2391
2392 /* Only use short offsets if their range will not overflow. */
2393 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2394 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2395 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2396 : SImode)
2397
2398 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2399
2400 /* Define this as 1 if `char' should by default be signed; else as 0. */
2401 #ifndef DEFAULT_SIGNED_CHAR
2402 #define DEFAULT_SIGNED_CHAR 1
2403 #endif
2404
2405 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2406 we generally don't want to use them for copying arbitrary data.
2407 A single N-word move is usually the same cost as N single-word moves. */
2408 #define MOVE_MAX UNITS_PER_WORD
2409 #define MAX_MOVE_MAX 8
2410
2411 /* Define this macro as a C expression which is nonzero if
2412 accessing less than a word of memory (i.e. a `char' or a
2413 `short') is no faster than accessing a word of memory, i.e., if
2414 such access require more than one instruction or if there is no
2415 difference in cost between byte and (aligned) word loads.
2416
2417 On RISC machines, it tends to generate better code to define
2418 this as 1, since it avoids making a QI or HI mode register.
2419
2420 But, generating word accesses for -mips16 is generally bad as shifts
2421 (often extended) would be needed for byte accesses. */
2422 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2423
2424 /* Standard MIPS integer shifts truncate the shift amount to the
2425 width of the shifted operand. However, Loongson vector shifts
2426 do not truncate the shift amount at all. */
2427 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2428
2429 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2430 is done just by pretending it is already truncated. */
2431 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2432 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2433
2434
2435 /* Specify the machine mode that pointers have.
2436 After generation of rtl, the compiler makes no further distinction
2437 between pointers and any other objects of this machine mode. */
2438
2439 #ifndef Pmode
2440 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2441 #endif
2442
2443 /* Give call MEMs SImode since it is the "most permissive" mode
2444 for both 32-bit and 64-bit targets. */
2445
2446 #define FUNCTION_MODE SImode
2447
2448 \f
2449 /* We allocate $fcc registers by hand and can't cope with moves of
2450 CCmode registers to and from pseudos (or memory). */
2451 #define AVOID_CCMODE_COPIES
2452
2453 /* A C expression for the cost of a branch instruction. A value of
2454 1 is the default; other values are interpreted relative to that. */
2455
2456 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2457 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2458
2459 /* The MIPS port has several functions that return an instruction count.
2460 Multiplying the count by this value gives the number of bytes that
2461 the instructions occupy. */
2462 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2463
2464 /* The length of a NOP in bytes. */
2465 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2466
2467 /* If defined, modifies the length assigned to instruction INSN as a
2468 function of the context in which it is used. LENGTH is an lvalue
2469 that contains the initially computed length of the insn and should
2470 be updated with the correct length of the insn. */
2471 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2472 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2473
2474 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2475 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2476 its operands. */
2477 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2478 "%*" OPCODE "%?\t" OPERANDS "%/"
2479
2480 /* Return an asm string that forces INSN to be treated as an absolute
2481 J or JAL instruction instead of an assembler macro. */
2482 #define MIPS_ABSOLUTE_JUMP(INSN) \
2483 (TARGET_ABICALLS_PIC2 \
2484 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2485 : INSN)
2486
2487 /* Return the asm template for a call. INSN is the instruction's mnemonic
2488 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2489 number of the target. SIZE_OPNO is the operand number of the argument size
2490 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2491 -1 and the call is indirect, use the function symbol from the call
2492 attributes to attach a R_MIPS_JALR relocation to the call.
2493
2494 When generating GOT code without explicit relocation operators,
2495 all calls should use assembly macros. Otherwise, all indirect
2496 calls should use "jr" or "jalr"; we will arrange to restore $gp
2497 afterwards if necessary. Finally, we can only generate direct
2498 calls for -mabicalls by temporarily switching to non-PIC mode.
2499
2500 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2501 instruction is in the delay slot of jal(r). */
2502 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2503 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2504 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2505 : REG_P (OPERANDS[TARGET_OPNO]) \
2506 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2507 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2508 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2509 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2510 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2511 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2512 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2513
2514 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2515 "jrc" when nop is in the delay slot of "jr". */
2516
2517 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2518 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2519 ? "%*j\t%" #OPNO "%/" \
2520 : REG_P (OPERANDS[OPNO]) \
2521 ? "%*jr%:\t%" #OPNO \
2522 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2523
2524 \f
2525 /* Control the assembler format that we output. */
2526
2527 /* Output to assembler file text saying following lines
2528 may contain character constants, extra white space, comments, etc. */
2529
2530 #ifndef ASM_APP_ON
2531 #define ASM_APP_ON " #APP\n"
2532 #endif
2533
2534 /* Output to assembler file text saying following lines
2535 no longer contain unusual constructs. */
2536
2537 #ifndef ASM_APP_OFF
2538 #define ASM_APP_OFF " #NO_APP\n"
2539 #endif
2540
2541 #define REGISTER_NAMES \
2542 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2543 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2544 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2545 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2546 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2547 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2548 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2549 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2550 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2551 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2552 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2553 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2554 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2555 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2556 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2557 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2558 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2559 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2560 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2561 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2562 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2563 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2564 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2565 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2566
2567 /* List the "software" names for each register. Also list the numerical
2568 names for $fp and $sp. */
2569
2570 #define ADDITIONAL_REGISTER_NAMES \
2571 { \
2572 { "$29", 29 + GP_REG_FIRST }, \
2573 { "$30", 30 + GP_REG_FIRST }, \
2574 { "at", 1 + GP_REG_FIRST }, \
2575 { "v0", 2 + GP_REG_FIRST }, \
2576 { "v1", 3 + GP_REG_FIRST }, \
2577 { "a0", 4 + GP_REG_FIRST }, \
2578 { "a1", 5 + GP_REG_FIRST }, \
2579 { "a2", 6 + GP_REG_FIRST }, \
2580 { "a3", 7 + GP_REG_FIRST }, \
2581 { "t0", 8 + GP_REG_FIRST }, \
2582 { "t1", 9 + GP_REG_FIRST }, \
2583 { "t2", 10 + GP_REG_FIRST }, \
2584 { "t3", 11 + GP_REG_FIRST }, \
2585 { "t4", 12 + GP_REG_FIRST }, \
2586 { "t5", 13 + GP_REG_FIRST }, \
2587 { "t6", 14 + GP_REG_FIRST }, \
2588 { "t7", 15 + GP_REG_FIRST }, \
2589 { "s0", 16 + GP_REG_FIRST }, \
2590 { "s1", 17 + GP_REG_FIRST }, \
2591 { "s2", 18 + GP_REG_FIRST }, \
2592 { "s3", 19 + GP_REG_FIRST }, \
2593 { "s4", 20 + GP_REG_FIRST }, \
2594 { "s5", 21 + GP_REG_FIRST }, \
2595 { "s6", 22 + GP_REG_FIRST }, \
2596 { "s7", 23 + GP_REG_FIRST }, \
2597 { "t8", 24 + GP_REG_FIRST }, \
2598 { "t9", 25 + GP_REG_FIRST }, \
2599 { "k0", 26 + GP_REG_FIRST }, \
2600 { "k1", 27 + GP_REG_FIRST }, \
2601 { "gp", 28 + GP_REG_FIRST }, \
2602 { "sp", 29 + GP_REG_FIRST }, \
2603 { "fp", 30 + GP_REG_FIRST }, \
2604 { "ra", 31 + GP_REG_FIRST } \
2605 }
2606
2607 #define DBR_OUTPUT_SEQEND(STREAM) \
2608 do \
2609 { \
2610 /* Undo the effect of '%*'. */ \
2611 mips_pop_asm_switch (&mips_nomacro); \
2612 mips_pop_asm_switch (&mips_noreorder); \
2613 /* Emit a blank line after the delay slot for emphasis. */ \
2614 fputs ("\n", STREAM); \
2615 } \
2616 while (0)
2617
2618 /* The MIPS implementation uses some labels for its own purpose. The
2619 following lists what labels are created, and are all formed by the
2620 pattern $L[a-z].*. The machine independent portion of GCC creates
2621 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2622
2623 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2624 $Lb[0-9]+ Begin blocks for MIPS debug support
2625 $Lc[0-9]+ Label for use in s<xx> operation.
2626 $Le[0-9]+ End blocks for MIPS debug support */
2627
2628 #undef ASM_DECLARE_OBJECT_NAME
2629 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2630 mips_declare_object (STREAM, NAME, "", ":\n")
2631
2632 /* Globalizing directive for a label. */
2633 #define GLOBAL_ASM_OP "\t.globl\t"
2634
2635 /* This says how to define a global common symbol. */
2636
2637 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2638
2639 /* This says how to define a local common symbol (i.e., not visible to
2640 linker). */
2641
2642 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2643 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2644 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2645 #endif
2646
2647 /* This says how to output an external. It would be possible not to
2648 output anything and let undefined symbol become external. However
2649 the assembler uses length information on externals to allocate in
2650 data/sdata bss/sbss, thereby saving exec time. */
2651
2652 #undef ASM_OUTPUT_EXTERNAL
2653 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2654 mips_output_external(STREAM,DECL,NAME)
2655
2656 /* This is how to declare a function name. The actual work of
2657 emitting the label is moved to function_prologue, so that we can
2658 get the line number correctly emitted before the .ent directive,
2659 and after any .file directives. Define as empty so that the function
2660 is not declared before the .ent directive elsewhere. */
2661
2662 #undef ASM_DECLARE_FUNCTION_NAME
2663 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2664
2665 /* This is how to store into the string LABEL
2666 the symbol_ref name of an internal numbered label where
2667 PREFIX is the class of label and NUM is the number within the class.
2668 This is suitable for output with `assemble_name'. */
2669
2670 #undef ASM_GENERATE_INTERNAL_LABEL
2671 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2672 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2673
2674 /* Print debug labels as "foo = ." rather than "foo:" because they should
2675 represent a byte pointer rather than an ISA-encoded address. This is
2676 particularly important for code like:
2677
2678 $LFBxxx = .
2679 .cfi_startproc
2680 ...
2681 .section .gcc_except_table,...
2682 ...
2683 .uleb128 foo-$LFBxxx
2684
2685 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2686 likewise a byte pointer rather than an ISA-encoded address.
2687
2688 At the time of writing, this hook is not used for the function end
2689 label:
2690
2691 $LFExxx:
2692 .end foo
2693
2694 But this doesn't matter, because GAS doesn't treat a pre-.end label
2695 as a MIPS16 one anyway. */
2696
2697 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2698 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2699
2700 /* This is how to output an element of a case-vector that is absolute. */
2701
2702 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2703 fprintf (STREAM, "\t%s\t%sL%d\n", \
2704 ptr_mode == DImode ? ".dword" : ".word", \
2705 LOCAL_LABEL_PREFIX, \
2706 VALUE)
2707
2708 /* This is how to output an element of a case-vector. We can make the
2709 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2710 is supported. */
2711
2712 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2713 do { \
2714 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2715 { \
2716 if (GET_MODE (BODY) == HImode) \
2717 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2718 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2719 else \
2720 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2721 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2722 } \
2723 else if (TARGET_GPWORD) \
2724 fprintf (STREAM, "\t%s\t%sL%d\n", \
2725 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2726 LOCAL_LABEL_PREFIX, VALUE); \
2727 else if (TARGET_RTP_PIC) \
2728 { \
2729 /* Make the entry relative to the start of the function. */ \
2730 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2731 fprintf (STREAM, "\t%s\t%sL%d-", \
2732 Pmode == DImode ? ".dword" : ".word", \
2733 LOCAL_LABEL_PREFIX, VALUE); \
2734 assemble_name (STREAM, XSTR (fnsym, 0)); \
2735 fprintf (STREAM, "\n"); \
2736 } \
2737 else \
2738 fprintf (STREAM, "\t%s\t%sL%d\n", \
2739 ptr_mode == DImode ? ".dword" : ".word", \
2740 LOCAL_LABEL_PREFIX, VALUE); \
2741 } while (0)
2742
2743 /* This is how to output an assembler line
2744 that says to advance the location counter
2745 to a multiple of 2**LOG bytes. */
2746
2747 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2748 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2749
2750 /* This is how to output an assembler line to advance the location
2751 counter by SIZE bytes. */
2752
2753 #undef ASM_OUTPUT_SKIP
2754 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2755 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2756
2757 /* This is how to output a string. */
2758 #undef ASM_OUTPUT_ASCII
2759 #define ASM_OUTPUT_ASCII mips_output_ascii
2760
2761 \f
2762 /* Default to -G 8 */
2763 #ifndef MIPS_DEFAULT_GVALUE
2764 #define MIPS_DEFAULT_GVALUE 8
2765 #endif
2766
2767 /* Define the strings to put out for each section in the object file. */
2768 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2769 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2770
2771 #undef READONLY_DATA_SECTION_ASM_OP
2772 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2773 \f
2774 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2775 do \
2776 { \
2777 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2778 TARGET_64BIT ? "daddiu" : "addiu", \
2779 reg_names[STACK_POINTER_REGNUM], \
2780 reg_names[STACK_POINTER_REGNUM], \
2781 TARGET_64BIT ? "sd" : "sw", \
2782 reg_names[REGNO], \
2783 reg_names[STACK_POINTER_REGNUM]); \
2784 } \
2785 while (0)
2786
2787 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2788 do \
2789 { \
2790 mips_push_asm_switch (&mips_noreorder); \
2791 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2792 TARGET_64BIT ? "ld" : "lw", \
2793 reg_names[REGNO], \
2794 reg_names[STACK_POINTER_REGNUM], \
2795 TARGET_64BIT ? "daddu" : "addu", \
2796 reg_names[STACK_POINTER_REGNUM], \
2797 reg_names[STACK_POINTER_REGNUM]); \
2798 mips_pop_asm_switch (&mips_noreorder); \
2799 } \
2800 while (0)
2801
2802 /* How to start an assembler comment.
2803 The leading space is important (the mips native assembler requires it). */
2804 #ifndef ASM_COMMENT_START
2805 #define ASM_COMMENT_START " #"
2806 #endif
2807 \f
2808 #undef SIZE_TYPE
2809 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2810
2811 #undef PTRDIFF_TYPE
2812 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2813
2814 /* The maximum number of bytes that can be copied by one iteration of
2815 a movmemsi loop; see mips_block_move_loop. */
2816 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2817 (UNITS_PER_WORD * 4)
2818
2819 /* The maximum number of bytes that can be copied by a straight-line
2820 implementation of movmemsi; see mips_block_move_straight. We want
2821 to make sure that any loop-based implementation will iterate at
2822 least twice. */
2823 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2824 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2825
2826 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2827 values were determined experimentally by benchmarking with CSiBE.
2828 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2829 for o32 where we have to restore $gp afterwards as well as make an
2830 indirect call), but in practice, bumping this up higher for
2831 TARGET_ABICALLS doesn't make much difference to code size. */
2832
2833 #define MIPS_CALL_RATIO 8
2834
2835 /* Any loop-based implementation of movmemsi will have at least
2836 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2837 moves, so allow individual copies of fewer elements.
2838
2839 When movmemsi is not available, use a value approximating
2840 the length of a memcpy call sequence, so that move_by_pieces
2841 will generate inline code if it is shorter than a function call.
2842 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2843 we'll have to generate a load/store pair for each, halve the
2844 value of MIPS_CALL_RATIO to take that into account. */
2845
2846 #define MOVE_RATIO(speed) \
2847 (HAVE_movmemsi \
2848 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2849 : MIPS_CALL_RATIO / 2)
2850
2851 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2852 mips_move_by_pieces_p (SIZE, ALIGN)
2853
2854 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2855 of the length of a memset call, but use the default otherwise. */
2856
2857 #define CLEAR_RATIO(speed)\
2858 ((speed) ? 15 : MIPS_CALL_RATIO)
2859
2860 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2861 optimizing for size adjust the ratio to account for the overhead of
2862 loading the constant and replicating it across the word. */
2863
2864 #define SET_RATIO(speed) \
2865 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2866
2867 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2868 mips_store_by_pieces_p (SIZE, ALIGN)
2869 \f
2870 /* Since the bits of the _init and _fini function is spread across
2871 many object files, each potentially with its own GP, we must assume
2872 we need to load our GP. We don't preserve $gp or $ra, since each
2873 init/fini chunk is supposed to initialize $gp, and crti/crtn
2874 already take care of preserving $ra and, when appropriate, $gp. */
2875 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2876 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2877 asm (SECTION_OP "\n\
2878 .set push\n\
2879 .set nomips16\n\
2880 .set noreorder\n\
2881 bal 1f\n\
2882 nop\n\
2883 1: .cpload $31\n\
2884 .set reorder\n\
2885 jal " USER_LABEL_PREFIX #FUNC "\n\
2886 .set pop\n\
2887 " TEXT_SECTION_ASM_OP);
2888 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2889 || (defined _ABI64 && _MIPS_SIM == _ABI64))
2890 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2891 asm (SECTION_OP "\n\
2892 .set push\n\
2893 .set nomips16\n\
2894 .set noreorder\n\
2895 bal 1f\n\
2896 nop\n\
2897 1: .set reorder\n\
2898 .cpsetup $31, $2, 1b\n\
2899 jal " USER_LABEL_PREFIX #FUNC "\n\
2900 .set pop\n\
2901 " TEXT_SECTION_ASM_OP);
2902 #endif
2903
2904 #ifndef HAVE_AS_TLS
2905 #define HAVE_AS_TLS 0
2906 #endif
2907
2908 #ifndef HAVE_AS_NAN
2909 #define HAVE_AS_NAN 0
2910 #endif
2911
2912 #ifndef USED_FOR_TARGET
2913 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2914 struct mips_asm_switch {
2915 /* The FOO in the description above. */
2916 const char *name;
2917
2918 /* The current block nesting level, or 0 if we aren't in a block. */
2919 int nesting_level;
2920 };
2921
2922 extern const enum reg_class mips_regno_to_class[];
2923 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2924 extern const char *current_function_file; /* filename current function is in */
2925 extern int num_source_filenames; /* current .file # */
2926 extern struct mips_asm_switch mips_noreorder;
2927 extern struct mips_asm_switch mips_nomacro;
2928 extern struct mips_asm_switch mips_noat;
2929 extern int mips_dbx_regno[];
2930 extern int mips_dwarf_regno[];
2931 extern bool mips_split_p[];
2932 extern bool mips_split_hi_p[];
2933 extern bool mips_use_pcrel_pool_p[];
2934 extern const char *mips_lo_relocs[];
2935 extern const char *mips_hi_relocs[];
2936 extern enum processor mips_arch; /* which cpu to codegen for */
2937 extern enum processor mips_tune; /* which cpu to schedule for */
2938 extern int mips_isa; /* architectural level */
2939 extern const struct mips_cpu_info *mips_arch_info;
2940 extern const struct mips_cpu_info *mips_tune_info;
2941 extern unsigned int mips_base_compression_flags;
2942 extern GTY(()) struct target_globals *mips16_globals;
2943 #endif
2944
2945 /* Enable querying of DFA units. */
2946 #define CPU_UNITS_QUERY 1
2947
2948 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2949 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2950
2951 /* As on most targets, we want the .eh_frame section to be read-only where
2952 possible. And as on most targets, this means two things:
2953
2954 (a) Non-locally-binding pointers must have an indirect encoding,
2955 so that the addresses in the .eh_frame section itself become
2956 locally-binding.
2957
2958 (b) A shared library's .eh_frame section must encode locally-binding
2959 pointers in a relative (relocation-free) form.
2960
2961 However, MIPS has traditionally not allowed directives like:
2962
2963 .long x-.
2964
2965 in cases where "x" is in a different section, or is not defined in the
2966 same assembly file. We are therefore unable to emit the PC-relative
2967 form required by (b) at assembly time.
2968
2969 Fortunately, the linker is able to convert absolute addresses into
2970 PC-relative addresses on our behalf. Unfortunately, only certain
2971 versions of the linker know how to do this for indirect pointers,
2972 and for personality data. We must fall back on using writable
2973 .eh_frame sections for shared libraries if the linker does not
2974 support this feature. */
2975 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2976 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
2977
2978 /* For switching between MIPS16 and non-MIPS16 modes. */
2979 #define SWITCHABLE_TARGET 1
2980
2981 /* Several named MIPS patterns depend on Pmode. These patterns have the
2982 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
2983 Add the appropriate suffix to generator function NAME and invoke it
2984 with arguments ARGS. */
2985 #define PMODE_INSN(NAME, ARGS) \
2986 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)