1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
27 [(UNSPEC_LOAD_DF_LOW 0)
28 (UNSPEC_LOAD_DF_HIGH 1)
29 (UNSPEC_STORE_DF_HIGH 2)
33 (UNSPEC_NONLOCAL_GOTO_RECEIVER 6)
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_TLS_GET_TP 28)
52 (UNSPEC_CLEAR_HAZARD 33)
56 (UNSPEC_COMPARE_AND_SWAP 37)
57 (UNSPEC_SYNC_OLD_OP 38)
58 (UNSPEC_SYNC_NEW_OP 39)
59 (UNSPEC_SYNC_EXCHANGE 40)
60 (UNSPEC_MEMORY_BARRIER 41)
62 (UNSPEC_ADDRESS_FIRST 100)
66 ;; For MIPS Paired-Singled Floating Point Instructions.
68 (UNSPEC_MOVE_TF_PS 200)
71 ;; MIPS64/MIPS32R2 alnv.ps
74 ;; MIPS-3D instructions
78 (UNSPEC_CVT_PW_PS 205)
79 (UNSPEC_CVT_PS_PW 206)
87 (UNSPEC_SINGLE_CC 213)
90 ;; MIPS DSP ASE Revision 0.98 3/24/2005
98 (UNSPEC_RADDU_W_QB 307)
100 (UNSPEC_PRECRQ_QB_PH 309)
101 (UNSPEC_PRECRQ_PH_W 310)
102 (UNSPEC_PRECRQ_RS_PH_W 311)
103 (UNSPEC_PRECRQU_S_QB_PH 312)
104 (UNSPEC_PRECEQ_W_PHL 313)
105 (UNSPEC_PRECEQ_W_PHR 314)
106 (UNSPEC_PRECEQU_PH_QBL 315)
107 (UNSPEC_PRECEQU_PH_QBR 316)
108 (UNSPEC_PRECEQU_PH_QBLA 317)
109 (UNSPEC_PRECEQU_PH_QBRA 318)
110 (UNSPEC_PRECEU_PH_QBL 319)
111 (UNSPEC_PRECEU_PH_QBR 320)
112 (UNSPEC_PRECEU_PH_QBLA 321)
113 (UNSPEC_PRECEU_PH_QBRA 322)
119 (UNSPEC_MULEU_S_PH_QBL 328)
120 (UNSPEC_MULEU_S_PH_QBR 329)
121 (UNSPEC_MULQ_RS_PH 330)
122 (UNSPEC_MULEQ_S_W_PHL 331)
123 (UNSPEC_MULEQ_S_W_PHR 332)
124 (UNSPEC_DPAU_H_QBL 333)
125 (UNSPEC_DPAU_H_QBR 334)
126 (UNSPEC_DPSU_H_QBL 335)
127 (UNSPEC_DPSU_H_QBR 336)
128 (UNSPEC_DPAQ_S_W_PH 337)
129 (UNSPEC_DPSQ_S_W_PH 338)
130 (UNSPEC_MULSAQ_S_W_PH 339)
131 (UNSPEC_DPAQ_SA_L_W 340)
132 (UNSPEC_DPSQ_SA_L_W 341)
133 (UNSPEC_MAQ_S_W_PHL 342)
134 (UNSPEC_MAQ_S_W_PHR 343)
135 (UNSPEC_MAQ_SA_W_PHL 344)
136 (UNSPEC_MAQ_SA_W_PHR 345)
144 (UNSPEC_CMPGU_EQ_QB 353)
145 (UNSPEC_CMPGU_LT_QB 354)
146 (UNSPEC_CMPGU_LE_QB 355)
148 (UNSPEC_PACKRL_PH 357)
150 (UNSPEC_EXTR_R_W 359)
151 (UNSPEC_EXTR_RS_W 360)
152 (UNSPEC_EXTR_S_H 361)
160 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
161 (UNSPEC_ABSQ_S_QB 400)
163 (UNSPEC_ADDU_S_PH 402)
164 (UNSPEC_ADDUH_QB 403)
165 (UNSPEC_ADDUH_R_QB 404)
168 (UNSPEC_CMPGDU_EQ_QB 407)
169 (UNSPEC_CMPGDU_LT_QB 408)
170 (UNSPEC_CMPGDU_LE_QB 409)
171 (UNSPEC_DPA_W_PH 410)
172 (UNSPEC_DPS_W_PH 411)
178 (UNSPEC_MUL_S_PH 417)
179 (UNSPEC_MULQ_RS_W 418)
180 (UNSPEC_MULQ_S_PH 419)
181 (UNSPEC_MULQ_S_W 420)
182 (UNSPEC_MULSA_W_PH 421)
185 (UNSPEC_PRECR_QB_PH 424)
186 (UNSPEC_PRECR_SRA_PH_W 425)
187 (UNSPEC_PRECR_SRA_R_PH_W 426)
190 (UNSPEC_SHRA_R_QB 429)
193 (UNSPEC_SUBU_S_PH 432)
194 (UNSPEC_SUBUH_QB 433)
195 (UNSPEC_SUBUH_R_QB 434)
196 (UNSPEC_ADDQH_PH 435)
197 (UNSPEC_ADDQH_R_PH 436)
199 (UNSPEC_ADDQH_R_W 438)
200 (UNSPEC_SUBQH_PH 439)
201 (UNSPEC_SUBQH_R_PH 440)
203 (UNSPEC_SUBQH_R_W 442)
204 (UNSPEC_DPAX_W_PH 443)
205 (UNSPEC_DPSX_W_PH 444)
206 (UNSPEC_DPAQX_S_W_PH 445)
207 (UNSPEC_DPAQX_SA_W_PH 446)
208 (UNSPEC_DPSQX_S_W_PH 447)
209 (UNSPEC_DPSQX_SA_W_PH 448)
213 (include "predicates.md")
214 (include "constraints.md")
216 ;; ....................
220 ;; ....................
222 (define_attr "got" "unset,xgot_high,load"
223 (const_string "unset"))
225 ;; For jal instructions, this attribute is DIRECT when the target address
226 ;; is symbolic and INDIRECT when it is a register.
227 (define_attr "jal" "unset,direct,indirect"
228 (const_string "unset"))
230 ;; This attribute is YES if the instruction is a jal macro (not a
231 ;; real jal instruction).
233 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
234 ;; an instruction to restore $gp. Direct jals are also macros for
235 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
236 ;; the target address into a register.
237 (define_attr "jal_macro" "no,yes"
238 (cond [(eq_attr "jal" "direct")
239 (symbol_ref "TARGET_CALL_CLOBBERED_GP
240 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
241 (eq_attr "jal" "indirect")
242 (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
243 (const_string "no")))
245 ;; Classification of each insn.
246 ;; branch conditional branch
247 ;; jump unconditional jump
248 ;; call unconditional call
249 ;; load load instruction(s)
250 ;; fpload floating point load
251 ;; fpidxload floating point indexed load
252 ;; store store instruction(s)
253 ;; fpstore floating point store
254 ;; fpidxstore floating point indexed store
255 ;; prefetch memory prefetch (register + offset)
256 ;; prefetchx memory indexed prefetch (register + register)
257 ;; condmove conditional moves
258 ;; mfc transfer from coprocessor
259 ;; mtc transfer to coprocessor
260 ;; mthilo transfer to hi/lo registers
261 ;; mfhilo transfer from hi/lo registers
262 ;; const load constant
263 ;; arith integer arithmetic instructions
264 ;; logical integer logical instructions
265 ;; shift integer shift instructions
266 ;; slt set less than instructions
267 ;; signext sign extend instructions
268 ;; clz the clz and clo instructions
269 ;; trap trap if instructions
270 ;; imul integer multiply 2 operands
271 ;; imul3 integer multiply 3 operands
272 ;; imadd integer multiply-add
273 ;; idiv integer divide
274 ;; move integer register move ({,D}ADD{,U} with rt = 0)
275 ;; fmove floating point register move
276 ;; fadd floating point add/subtract
277 ;; fmul floating point multiply
278 ;; fmadd floating point multiply-add
279 ;; fdiv floating point divide
280 ;; frdiv floating point reciprocal divide
281 ;; frdiv1 floating point reciprocal divide step 1
282 ;; frdiv2 floating point reciprocal divide step 2
283 ;; fabs floating point absolute value
284 ;; fneg floating point negation
285 ;; fcmp floating point compare
286 ;; fcvt floating point convert
287 ;; fsqrt floating point square root
288 ;; frsqrt floating point reciprocal square root
289 ;; frsqrt1 floating point reciprocal square root step1
290 ;; frsqrt2 floating point reciprocal square root step2
291 ;; multi multiword sequence (or user asm statements)
294 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,logical,shift,slt,signext,clz,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
295 (cond [(eq_attr "jal" "!unset") (const_string "call")
296 (eq_attr "got" "load") (const_string "load")]
297 (const_string "unknown")))
299 ;; Main data type used by the insn
300 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
301 (const_string "unknown"))
303 ;; Mode for conversion types (fcvt)
304 ;; I2S integer to float single (SI/DI to SF)
305 ;; I2D integer to float double (SI/DI to DF)
306 ;; S2I float to integer (SF to SI/DI)
307 ;; D2I float to integer (DF to SI/DI)
308 ;; D2S double to float single
309 ;; S2D float single to double
311 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
312 (const_string "unknown"))
314 ;; Is this an extended instruction in mips16 mode?
315 (define_attr "extended_mips16" "no,yes"
318 ;; Length of instruction in bytes.
319 (define_attr "length" ""
320 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
321 ;; If a branch is outside this range, we have a choice of two
322 ;; sequences. For PIC, an out-of-range branch like:
327 ;; becomes the equivalent of:
336 ;; where the load address can be up to three instructions long
339 ;; The non-PIC case is similar except that we use a direct
340 ;; jump instead of an la/jr pair. Since the target of this
341 ;; jump is an absolute 28-bit bit address (the other bits
342 ;; coming from the address of the delay slot) this form cannot
343 ;; cross a 256MB boundary. We could provide the option of
344 ;; using la/jr in this case too, but we do not do so at
347 ;; Note that this value does not account for the delay slot
348 ;; instruction, whose length is added separately. If the RTL
349 ;; pattern has no explicit delay slot, mips_adjust_insn_length
350 ;; will add the length of the implicit nop. The values for
351 ;; forward and backward branches will be different as well.
352 (eq_attr "type" "branch")
353 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
354 (le (minus (pc) (match_dup 1)) (const_int 131068)))
356 (ne (symbol_ref "flag_pic") (const_int 0))
360 (eq_attr "got" "load")
362 (eq_attr "got" "xgot_high")
365 (eq_attr "type" "const")
366 (symbol_ref "mips_const_insns (operands[1]) * 4")
367 (eq_attr "type" "load,fpload")
368 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
369 (eq_attr "type" "store,fpstore")
370 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
372 ;; In the worst case, a call macro will take 8 instructions:
374 ;; lui $25,%call_hi(FOO)
376 ;; lw $25,%call_lo(FOO)($25)
382 (eq_attr "jal_macro" "yes")
385 (and (eq_attr "extended_mips16" "yes")
386 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
389 ;; Various VR4120 errata require a nop to be inserted after a macc
390 ;; instruction. The assembler does this for us, so account for
391 ;; the worst-case length here.
392 (and (eq_attr "type" "imadd")
393 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
396 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
397 ;; the result of the second one is missed. The assembler should work
398 ;; around this by inserting a nop after the first dmult.
399 (and (eq_attr "type" "imul,imul3")
400 (and (eq_attr "mode" "DI")
401 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
404 (eq_attr "type" "idiv")
405 (symbol_ref "mips_idiv_insns () * 4")
408 ;; Attribute describing the processor. This attribute must match exactly
409 ;; with the processor_type enumeration in mips.h.
411 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
412 (const (symbol_ref "mips_tune")))
414 ;; The type of hardware hazard associated with this instruction.
415 ;; DELAY means that the next instruction cannot read the result
416 ;; of this one. HILO means that the next two instructions cannot
417 ;; write to HI or LO.
418 (define_attr "hazard" "none,delay,hilo"
419 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
420 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
421 (const_string "delay")
423 (and (eq_attr "type" "mfc,mtc")
424 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
425 (const_string "delay")
427 (and (eq_attr "type" "fcmp")
428 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
429 (const_string "delay")
431 ;; The r4000 multiplication patterns include an mflo instruction.
432 (and (eq_attr "type" "imul")
433 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
434 (const_string "hilo")
436 (and (eq_attr "type" "mfhilo")
437 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
438 (const_string "hilo")]
439 (const_string "none")))
441 ;; Is it a single instruction?
442 (define_attr "single_insn" "no,yes"
443 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
445 ;; Can the instruction be put into a delay slot?
446 (define_attr "can_delay" "no,yes"
447 (if_then_else (and (eq_attr "type" "!branch,call,jump")
448 (and (eq_attr "hazard" "none")
449 (eq_attr "single_insn" "yes")))
451 (const_string "no")))
453 ;; Attribute defining whether or not we can use the branch-likely instructions
454 (define_attr "branch_likely" "no,yes"
456 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
458 (const_string "no"))))
460 ;; True if an instruction might assign to hi or lo when reloaded.
461 ;; This is used by the TUNE_MACC_CHAINS code.
462 (define_attr "may_clobber_hilo" "no,yes"
463 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
465 (const_string "no")))
467 ;; Describe a user's asm statement.
468 (define_asm_attributes
469 [(set_attr "type" "multi")
470 (set_attr "can_delay" "no")])
472 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
473 ;; from the same template.
474 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
476 ;; This mode iterator allows :P to be used for patterns that operate on
477 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
478 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
480 ;; This mode iterator allows :MOVECC to be used anywhere that a
481 ;; conditional-move-type condition is needed.
482 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
484 ;; This mode iterator allows the QI and HI extension patterns to be defined from
485 ;; the same template.
486 (define_mode_iterator SHORT [QI HI])
488 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
489 ;; floating-point mode is allowed.
490 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
491 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
492 (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
494 ;; Like ANYF, but only applies to scalar modes.
495 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
496 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
498 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
499 ;; 32-bit version and "dsubu" in the 64-bit version.
500 (define_mode_attr d [(SI "") (DI "d")
501 (QQ "") (HQ "") (SQ "") (DQ "d")
502 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
503 (HA "") (SA "") (DA "d")
504 (UHA "") (USA "") (UDA "d")])
506 ;; This attribute gives the length suffix for a sign- or zero-extension
508 (define_mode_attr size [(QI "b") (HI "h")])
510 ;; This attributes gives the mode mask of a SHORT.
511 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
513 ;; Mode attributes for GPR loads and stores.
514 (define_mode_attr load [(SI "lw") (DI "ld")])
515 (define_mode_attr store [(SI "sw") (DI "sd")])
517 ;; Similarly for MIPS IV indexed FPR loads and stores.
518 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
519 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
521 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
522 ;; are different. Some forms of unextended addiu have an 8-bit immediate
523 ;; field but the equivalent daddiu has only a 5-bit field.
524 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
526 ;; This attribute gives the best constraint to use for registers of
528 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
530 ;; This attribute gives the format suffix for floating-point operations.
531 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
533 ;; This attribute gives the upper-case mode name for one unit of a
534 ;; floating-point mode.
535 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
537 ;; This attribute gives the integer mode that has the same size as a
539 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
540 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
541 (HA "HI") (SA "SI") (DA "DI")
542 (UHA "HI") (USA "SI") (UDA "DI")
543 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
544 (V2HQ "SI") (V2HA "SI")])
546 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
548 ;; In certain cases, div.s and div.ps may have a rounding error
549 ;; and/or wrong inexact flag.
551 ;; Therefore, we only allow div.s if not working around SB-1 rev2
552 ;; errata or if a slight loss of precision is OK.
553 (define_mode_attr divide_condition
554 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
555 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
557 ; This attribute gives the condition for which sqrt instructions exist.
558 (define_mode_attr sqrt_condition
559 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
561 ; This attribute gives the condition for which recip and rsqrt instructions
563 (define_mode_attr recip_condition
564 [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
566 ;; This code iterator allows all branch instructions to be generated from
567 ;; a single define_expand template.
568 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
569 eq ne gt ge lt le gtu geu ltu leu])
571 ;; This code iterator allows signed and unsigned widening multiplications
572 ;; to use the same template.
573 (define_code_iterator any_extend [sign_extend zero_extend])
575 ;; This code iterator allows the three shift instructions to be generated
576 ;; from the same template.
577 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
579 ;; This code iterator allows all native floating-point comparisons to be
580 ;; generated from the same template.
581 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
583 ;; This code iterator is used for comparisons that can be implemented
584 ;; by swapping the operands.
585 (define_code_iterator swapped_fcond [ge gt unge ungt])
587 ;; <u> expands to an empty string when doing a signed operation and
588 ;; "u" when doing an unsigned operation.
589 (define_code_attr u [(sign_extend "") (zero_extend "u")])
591 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
592 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
594 ;; <optab> expands to the name of the optab for a particular code.
595 (define_code_attr optab [(ashift "ashl")
602 ;; <insn> expands to the name of the insn that implements a particular code.
603 (define_code_attr insn [(ashift "sll")
610 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
611 (define_code_attr fcond [(unordered "un")
619 ;; Similar, but for swapped conditions.
620 (define_code_attr swapped_fcond [(ge "le")
625 ;; Atomic fetch bitwise operations.
626 (define_code_iterator fetchop_bit [ior xor and])
628 ;; <immediate_insn> expands to the name of the insn that implements
629 ;; a particular code to operate in immediate values.
630 (define_code_attr immediate_insn [(ior "ori") (xor "xori") (and "andi")])
633 ;; .........................
635 ;; Branch, call and jump delay slots
637 ;; .........................
639 (define_delay (and (eq_attr "type" "branch")
640 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
641 [(eq_attr "can_delay" "yes")
643 (and (eq_attr "branch_likely" "yes")
644 (eq_attr "can_delay" "yes"))])
646 (define_delay (eq_attr "type" "jump")
647 [(eq_attr "can_delay" "yes")
651 (define_delay (and (eq_attr "type" "call")
652 (eq_attr "jal_macro" "no"))
653 [(eq_attr "can_delay" "yes")
657 ;; Pipeline descriptions.
659 ;; generic.md provides a fallback for processors without a specific
660 ;; pipeline description. It is derived from the old define_function_unit
661 ;; version and uses the "alu" and "imuldiv" units declared below.
663 ;; Some of the processor-specific files are also derived from old
664 ;; define_function_unit descriptions and simply override the parts of
665 ;; generic.md that don't apply. The other processor-specific files
666 ;; are self-contained.
667 (define_automaton "alu,imuldiv")
669 (define_cpu_unit "alu" "alu")
670 (define_cpu_unit "imuldiv" "imuldiv")
691 (include "generic.md")
694 ;; ....................
698 ;; ....................
702 [(trap_if (const_int 1) (const_int 0))]
705 if (ISA_HAS_COND_TRAP)
707 else if (TARGET_MIPS16)
712 [(set_attr "type" "trap")])
714 (define_expand "conditional_trap"
715 [(trap_if (match_operator 0 "comparison_operator"
716 [(match_dup 2) (match_dup 3)])
717 (match_operand 1 "const_int_operand"))]
720 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
721 && operands[1] == const0_rtx)
723 mips_gen_conditional_trap (operands);
730 (define_insn "*conditional_trap<mode>"
731 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
732 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
733 (match_operand:GPR 2 "arith_operand" "dI")])
737 [(set_attr "type" "trap")])
740 ;; ....................
744 ;; ....................
747 (define_insn "add<mode>3"
748 [(set (match_operand:ANYF 0 "register_operand" "=f")
749 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
750 (match_operand:ANYF 2 "register_operand" "f")))]
752 "add.<fmt>\t%0,%1,%2"
753 [(set_attr "type" "fadd")
754 (set_attr "mode" "<UNITMODE>")])
756 (define_expand "add<mode>3"
757 [(set (match_operand:GPR 0 "register_operand")
758 (plus:GPR (match_operand:GPR 1 "register_operand")
759 (match_operand:GPR 2 "arith_operand")))]
762 (define_insn "*add<mode>3"
763 [(set (match_operand:GPR 0 "register_operand" "=d,d")
764 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
765 (match_operand:GPR 2 "arith_operand" "d,Q")))]
770 [(set_attr "type" "arith")
771 (set_attr "mode" "<MODE>")])
773 (define_insn "*add<mode>3_mips16"
774 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
775 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
776 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
784 [(set_attr "type" "arith")
785 (set_attr "mode" "<MODE>")
786 (set_attr_alternative "length"
787 [(if_then_else (match_operand 2 "m16_simm8_8")
790 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
793 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
796 (if_then_else (match_operand 2 "m16_simm4_1")
801 ;; On the mips16, we can sometimes split an add of a constant which is
802 ;; a 4 byte instruction into two adds which are both 2 byte
803 ;; instructions. There are two cases: one where we are adding a
804 ;; constant plus a register to another register, and one where we are
805 ;; simply adding a constant to a register.
808 [(set (match_operand:SI 0 "register_operand")
809 (plus:SI (match_dup 0)
810 (match_operand:SI 1 "const_int_operand")))]
811 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
812 && REG_P (operands[0])
813 && M16_REG_P (REGNO (operands[0]))
814 && GET_CODE (operands[1]) == CONST_INT
815 && ((INTVAL (operands[1]) > 0x7f
816 && INTVAL (operands[1]) <= 0x7f + 0x7f)
817 || (INTVAL (operands[1]) < - 0x80
818 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
819 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
820 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
822 HOST_WIDE_INT val = INTVAL (operands[1]);
826 operands[1] = GEN_INT (0x7f);
827 operands[2] = GEN_INT (val - 0x7f);
831 operands[1] = GEN_INT (- 0x80);
832 operands[2] = GEN_INT (val + 0x80);
837 [(set (match_operand:SI 0 "register_operand")
838 (plus:SI (match_operand:SI 1 "register_operand")
839 (match_operand:SI 2 "const_int_operand")))]
840 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
841 && REG_P (operands[0])
842 && M16_REG_P (REGNO (operands[0]))
843 && REG_P (operands[1])
844 && M16_REG_P (REGNO (operands[1]))
845 && REGNO (operands[0]) != REGNO (operands[1])
846 && GET_CODE (operands[2]) == CONST_INT
847 && ((INTVAL (operands[2]) > 0x7
848 && INTVAL (operands[2]) <= 0x7 + 0x7f)
849 || (INTVAL (operands[2]) < - 0x8
850 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
851 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
852 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
854 HOST_WIDE_INT val = INTVAL (operands[2]);
858 operands[2] = GEN_INT (0x7);
859 operands[3] = GEN_INT (val - 0x7);
863 operands[2] = GEN_INT (- 0x8);
864 operands[3] = GEN_INT (val + 0x8);
869 [(set (match_operand:DI 0 "register_operand")
870 (plus:DI (match_dup 0)
871 (match_operand:DI 1 "const_int_operand")))]
872 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
873 && REG_P (operands[0])
874 && M16_REG_P (REGNO (operands[0]))
875 && GET_CODE (operands[1]) == CONST_INT
876 && ((INTVAL (operands[1]) > 0xf
877 && INTVAL (operands[1]) <= 0xf + 0xf)
878 || (INTVAL (operands[1]) < - 0x10
879 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
880 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
881 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
883 HOST_WIDE_INT val = INTVAL (operands[1]);
887 operands[1] = GEN_INT (0xf);
888 operands[2] = GEN_INT (val - 0xf);
892 operands[1] = GEN_INT (- 0x10);
893 operands[2] = GEN_INT (val + 0x10);
898 [(set (match_operand:DI 0 "register_operand")
899 (plus:DI (match_operand:DI 1 "register_operand")
900 (match_operand:DI 2 "const_int_operand")))]
901 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
902 && REG_P (operands[0])
903 && M16_REG_P (REGNO (operands[0]))
904 && REG_P (operands[1])
905 && M16_REG_P (REGNO (operands[1]))
906 && REGNO (operands[0]) != REGNO (operands[1])
907 && GET_CODE (operands[2]) == CONST_INT
908 && ((INTVAL (operands[2]) > 0x7
909 && INTVAL (operands[2]) <= 0x7 + 0xf)
910 || (INTVAL (operands[2]) < - 0x8
911 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
912 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
913 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
915 HOST_WIDE_INT val = INTVAL (operands[2]);
919 operands[2] = GEN_INT (0x7);
920 operands[3] = GEN_INT (val - 0x7);
924 operands[2] = GEN_INT (- 0x8);
925 operands[3] = GEN_INT (val + 0x8);
929 (define_insn "*addsi3_extended"
930 [(set (match_operand:DI 0 "register_operand" "=d,d")
932 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
933 (match_operand:SI 2 "arith_operand" "d,Q"))))]
934 "TARGET_64BIT && !TARGET_MIPS16"
938 [(set_attr "type" "arith")
939 (set_attr "mode" "SI")])
941 ;; Split this insn so that the addiu splitters can have a crack at it.
942 ;; Use a conservative length estimate until the split.
943 (define_insn_and_split "*addsi3_extended_mips16"
944 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
946 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
947 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
948 "TARGET_64BIT && TARGET_MIPS16"
950 "&& reload_completed"
951 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
952 { operands[3] = gen_lowpart (SImode, operands[0]); }
953 [(set_attr "type" "arith")
954 (set_attr "mode" "SI")
955 (set_attr "extended_mips16" "yes")])
958 ;; ....................
962 ;; ....................
965 (define_insn "sub<mode>3"
966 [(set (match_operand:ANYF 0 "register_operand" "=f")
967 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
968 (match_operand:ANYF 2 "register_operand" "f")))]
970 "sub.<fmt>\t%0,%1,%2"
971 [(set_attr "type" "fadd")
972 (set_attr "mode" "<UNITMODE>")])
974 (define_insn "sub<mode>3"
975 [(set (match_operand:GPR 0 "register_operand" "=d")
976 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
977 (match_operand:GPR 2 "register_operand" "d")))]
980 [(set_attr "type" "arith")
981 (set_attr "mode" "<MODE>")])
983 (define_insn "*subsi3_extended"
984 [(set (match_operand:DI 0 "register_operand" "=d")
986 (minus:SI (match_operand:SI 1 "register_operand" "d")
987 (match_operand:SI 2 "register_operand" "d"))))]
990 [(set_attr "type" "arith")
991 (set_attr "mode" "DI")])
994 ;; ....................
998 ;; ....................
1001 (define_expand "mul<mode>3"
1002 [(set (match_operand:SCALARF 0 "register_operand")
1003 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1004 (match_operand:SCALARF 2 "register_operand")))]
1008 (define_insn "*mul<mode>3"
1009 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1010 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1011 (match_operand:SCALARF 2 "register_operand" "f")))]
1012 "!TARGET_4300_MUL_FIX"
1013 "mul.<fmt>\t%0,%1,%2"
1014 [(set_attr "type" "fmul")
1015 (set_attr "mode" "<MODE>")])
1017 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1018 ;; operands may corrupt immediately following multiplies. This is a
1019 ;; simple fix to insert NOPs.
1021 (define_insn "*mul<mode>3_r4300"
1022 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1023 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1024 (match_operand:SCALARF 2 "register_operand" "f")))]
1025 "TARGET_4300_MUL_FIX"
1026 "mul.<fmt>\t%0,%1,%2\;nop"
1027 [(set_attr "type" "fmul")
1028 (set_attr "mode" "<MODE>")
1029 (set_attr "length" "8")])
1031 (define_insn "mulv2sf3"
1032 [(set (match_operand:V2SF 0 "register_operand" "=f")
1033 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1034 (match_operand:V2SF 2 "register_operand" "f")))]
1035 "TARGET_PAIRED_SINGLE_FLOAT"
1037 [(set_attr "type" "fmul")
1038 (set_attr "mode" "SF")])
1040 ;; The original R4000 has a cpu bug. If a double-word or a variable
1041 ;; shift executes while an integer multiplication is in progress, the
1042 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1043 ;; with the mult on the R4000.
1045 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1046 ;; (also valid for MIPS R4000MC processors):
1048 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1049 ;; this errata description.
1050 ;; The following code sequence causes the R4000 to incorrectly
1051 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1052 ;; instruction. If the dsra32 instruction is executed during an
1053 ;; integer multiply, the dsra32 will only shift by the amount in
1054 ;; specified in the instruction rather than the amount plus 32
1056 ;; instruction 1: mult rs,rt integer multiply
1057 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1058 ;; right arithmetic + 32
1059 ;; Workaround: A dsra32 instruction placed after an integer
1060 ;; multiply should not be one of the 11 instructions after the
1061 ;; multiply instruction."
1065 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1066 ;; the following description.
1067 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1068 ;; 64-bit versions) may produce incorrect results under the
1069 ;; following conditions:
1070 ;; 1) An integer multiply is currently executing
1071 ;; 2) These types of shift instructions are executed immediately
1072 ;; following an integer divide instruction.
1074 ;; 1) Make sure no integer multiply is running wihen these
1075 ;; instruction are executed. If this cannot be predicted at
1076 ;; compile time, then insert a "mfhi" to R0 instruction
1077 ;; immediately after the integer multiply instruction. This
1078 ;; will cause the integer multiply to complete before the shift
1080 ;; 2) Separate integer divide and these two classes of shift
1081 ;; instructions by another instruction or a noop."
1083 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1086 (define_expand "mulsi3"
1087 [(set (match_operand:SI 0 "register_operand")
1088 (mult:SI (match_operand:SI 1 "register_operand")
1089 (match_operand:SI 2 "register_operand")))]
1093 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1094 else if (TARGET_FIX_R4000)
1095 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1097 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1101 (define_expand "muldi3"
1102 [(set (match_operand:DI 0 "register_operand")
1103 (mult:DI (match_operand:DI 1 "register_operand")
1104 (match_operand:DI 2 "register_operand")))]
1107 if (TARGET_FIX_R4000)
1108 emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
1110 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
1114 (define_insn "mulsi3_mult3"
1115 [(set (match_operand:SI 0 "register_operand" "=d,l")
1116 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1117 (match_operand:SI 2 "register_operand" "d,d")))
1118 (clobber (match_scratch:SI 3 "=h,h"))
1119 (clobber (match_scratch:SI 4 "=l,X"))]
1122 if (which_alternative == 1)
1123 return "mult\t%1,%2";
1124 if (TARGET_MIPS3900)
1125 return "mult\t%0,%1,%2";
1126 return "mul\t%0,%1,%2";
1128 [(set_attr "type" "imul3,imul")
1129 (set_attr "mode" "SI")])
1131 ;; If a register gets allocated to LO, and we spill to memory, the reload
1132 ;; will include a move from LO to a GPR. Merge it into the multiplication
1133 ;; if it can set the GPR directly.
1136 ;; Operand 1: GPR (1st multiplication operand)
1137 ;; Operand 2: GPR (2nd multiplication operand)
1139 ;; Operand 4: GPR (destination)
1142 [(set (match_operand:SI 0 "register_operand")
1143 (mult:SI (match_operand:SI 1 "register_operand")
1144 (match_operand:SI 2 "register_operand")))
1145 (clobber (match_operand:SI 3 "register_operand"))
1146 (clobber (scratch:SI))])
1147 (set (match_operand:SI 4 "register_operand")
1148 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1149 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1152 (mult:SI (match_dup 1)
1154 (clobber (match_dup 3))
1155 (clobber (match_dup 0))])])
1157 (define_insn "mul<mode>3_internal"
1158 [(set (match_operand:GPR 0 "register_operand" "=l")
1159 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1160 (match_operand:GPR 2 "register_operand" "d")))
1161 (clobber (match_scratch:GPR 3 "=h"))]
1164 [(set_attr "type" "imul")
1165 (set_attr "mode" "<MODE>")])
1167 (define_insn "mul<mode>3_r4000"
1168 [(set (match_operand:GPR 0 "register_operand" "=d")
1169 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1170 (match_operand:GPR 2 "register_operand" "d")))
1171 (clobber (match_scratch:GPR 3 "=h"))
1172 (clobber (match_scratch:GPR 4 "=l"))]
1174 "<d>mult\t%1,%2\;mflo\t%0"
1175 [(set_attr "type" "imul")
1176 (set_attr "mode" "<MODE>")
1177 (set_attr "length" "8")])
1179 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1180 ;; of "mult; mflo". They have the same latency, but the first form gives
1181 ;; us an extra cycle to compute the operands.
1184 ;; Operand 1: GPR (1st multiplication operand)
1185 ;; Operand 2: GPR (2nd multiplication operand)
1187 ;; Operand 4: GPR (destination)
1190 [(set (match_operand:SI 0 "register_operand")
1191 (mult:SI (match_operand:SI 1 "register_operand")
1192 (match_operand:SI 2 "register_operand")))
1193 (clobber (match_operand:SI 3 "register_operand"))])
1194 (set (match_operand:SI 4 "register_operand")
1195 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1196 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1201 (plus:SI (mult:SI (match_dup 1)
1205 (plus:SI (mult:SI (match_dup 1)
1208 (clobber (match_dup 3))])])
1210 ;; Multiply-accumulate patterns
1212 ;; For processors that can copy the output to a general register:
1214 ;; The all-d alternative is needed because the combiner will find this
1215 ;; pattern and then register alloc/reload will move registers around to
1216 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1218 ;; The last alternative should be made slightly less desirable, but adding
1219 ;; "?" to the constraint is too strong, and causes values to be loaded into
1220 ;; LO even when that's more costly. For now, using "*d" mostly does the
1222 (define_insn "*mul_acc_si"
1223 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1224 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1225 (match_operand:SI 2 "register_operand" "d,d,d"))
1226 (match_operand:SI 3 "register_operand" "0,l,*d")))
1227 (clobber (match_scratch:SI 4 "=h,h,h"))
1228 (clobber (match_scratch:SI 5 "=X,3,l"))
1229 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1231 || GENERATE_MADD_MSUB)
1234 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1235 if (which_alternative == 2)
1237 if (GENERATE_MADD_MSUB && which_alternative != 0)
1239 return madd[which_alternative];
1241 [(set_attr "type" "imadd")
1242 (set_attr "mode" "SI")
1243 (set_attr "length" "4,4,8")])
1245 ;; Split the above insn if we failed to get LO allocated.
1247 [(set (match_operand:SI 0 "register_operand")
1248 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1249 (match_operand:SI 2 "register_operand"))
1250 (match_operand:SI 3 "register_operand")))
1251 (clobber (match_scratch:SI 4))
1252 (clobber (match_scratch:SI 5))
1253 (clobber (match_scratch:SI 6))]
1254 "reload_completed && !TARGET_DEBUG_D_MODE
1255 && GP_REG_P (true_regnum (operands[0]))
1256 && GP_REG_P (true_regnum (operands[3]))"
1257 [(parallel [(set (match_dup 6)
1258 (mult:SI (match_dup 1) (match_dup 2)))
1259 (clobber (match_dup 4))
1260 (clobber (match_dup 5))])
1261 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1264 ;; Splitter to copy result of MADD to a general register
1266 [(set (match_operand:SI 0 "register_operand")
1267 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1268 (match_operand:SI 2 "register_operand"))
1269 (match_operand:SI 3 "register_operand")))
1270 (clobber (match_scratch:SI 4))
1271 (clobber (match_scratch:SI 5))
1272 (clobber (match_scratch:SI 6))]
1273 "reload_completed && !TARGET_DEBUG_D_MODE
1274 && GP_REG_P (true_regnum (operands[0]))
1275 && true_regnum (operands[3]) == LO_REGNUM"
1276 [(parallel [(set (match_dup 3)
1277 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1279 (clobber (match_dup 4))
1280 (clobber (match_dup 5))
1281 (clobber (match_dup 6))])
1282 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1285 (define_insn "*macc"
1286 [(set (match_operand:SI 0 "register_operand" "=l,d")
1287 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1288 (match_operand:SI 2 "register_operand" "d,d"))
1289 (match_operand:SI 3 "register_operand" "0,l")))
1290 (clobber (match_scratch:SI 4 "=h,h"))
1291 (clobber (match_scratch:SI 5 "=X,3"))]
1294 if (which_alternative == 1)
1295 return "macc\t%0,%1,%2";
1296 else if (TARGET_MIPS5500)
1297 return "madd\t%1,%2";
1299 /* The VR4130 assumes that there is a two-cycle latency between a macc
1300 that "writes" to $0 and an instruction that reads from it. We avoid
1301 this by assigning to $1 instead. */
1302 return "%[macc\t%@,%1,%2%]";
1304 [(set_attr "type" "imadd")
1305 (set_attr "mode" "SI")])
1307 (define_insn "*msac"
1308 [(set (match_operand:SI 0 "register_operand" "=l,d")
1309 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1310 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1311 (match_operand:SI 3 "register_operand" "d,d"))))
1312 (clobber (match_scratch:SI 4 "=h,h"))
1313 (clobber (match_scratch:SI 5 "=X,1"))]
1316 if (which_alternative == 1)
1317 return "msac\t%0,%2,%3";
1318 else if (TARGET_MIPS5500)
1319 return "msub\t%2,%3";
1321 return "msac\t$0,%2,%3";
1323 [(set_attr "type" "imadd")
1324 (set_attr "mode" "SI")])
1326 ;; An msac-like instruction implemented using negation and a macc.
1327 (define_insn_and_split "*msac_using_macc"
1328 [(set (match_operand:SI 0 "register_operand" "=l,d")
1329 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1330 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1331 (match_operand:SI 3 "register_operand" "d,d"))))
1332 (clobber (match_scratch:SI 4 "=h,h"))
1333 (clobber (match_scratch:SI 5 "=X,1"))
1334 (clobber (match_scratch:SI 6 "=d,d"))]
1335 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1337 "&& reload_completed"
1339 (neg:SI (match_dup 3)))
1342 (plus:SI (mult:SI (match_dup 2)
1345 (clobber (match_dup 4))
1346 (clobber (match_dup 5))])]
1348 [(set_attr "type" "imadd")
1349 (set_attr "length" "8")])
1351 ;; Patterns generated by the define_peephole2 below.
1353 (define_insn "*macc2"
1354 [(set (match_operand:SI 0 "register_operand" "=l")
1355 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1356 (match_operand:SI 2 "register_operand" "d"))
1358 (set (match_operand:SI 3 "register_operand" "=d")
1359 (plus:SI (mult:SI (match_dup 1)
1362 (clobber (match_scratch:SI 4 "=h"))]
1363 "ISA_HAS_MACC && reload_completed"
1365 [(set_attr "type" "imadd")
1366 (set_attr "mode" "SI")])
1368 (define_insn "*msac2"
1369 [(set (match_operand:SI 0 "register_operand" "=l")
1370 (minus:SI (match_dup 0)
1371 (mult:SI (match_operand:SI 1 "register_operand" "d")
1372 (match_operand:SI 2 "register_operand" "d"))))
1373 (set (match_operand:SI 3 "register_operand" "=d")
1374 (minus:SI (match_dup 0)
1375 (mult:SI (match_dup 1)
1377 (clobber (match_scratch:SI 4 "=h"))]
1378 "ISA_HAS_MSAC && reload_completed"
1380 [(set_attr "type" "imadd")
1381 (set_attr "mode" "SI")])
1383 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1387 ;; Operand 1: macc/msac
1389 ;; Operand 3: GPR (destination)
1392 [(set (match_operand:SI 0 "register_operand")
1393 (match_operand:SI 1 "macc_msac_operand"))
1394 (clobber (match_operand:SI 2 "register_operand"))
1395 (clobber (scratch:SI))])
1396 (set (match_operand:SI 3 "register_operand")
1397 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1399 [(parallel [(set (match_dup 0)
1403 (clobber (match_dup 2))])]
1406 ;; When we have a three-address multiplication instruction, it should
1407 ;; be faster to do a separate multiply and add, rather than moving
1408 ;; something into LO in order to use a macc instruction.
1410 ;; This peephole needs a scratch register to cater for the case when one
1411 ;; of the multiplication operands is the same as the destination.
1413 ;; Operand 0: GPR (scratch)
1415 ;; Operand 2: GPR (addend)
1416 ;; Operand 3: GPR (destination)
1417 ;; Operand 4: macc/msac
1419 ;; Operand 6: new multiplication
1420 ;; Operand 7: new addition/subtraction
1422 [(match_scratch:SI 0 "d")
1423 (set (match_operand:SI 1 "register_operand")
1424 (match_operand:SI 2 "register_operand"))
1427 [(set (match_operand:SI 3 "register_operand")
1428 (match_operand:SI 4 "macc_msac_operand"))
1429 (clobber (match_operand:SI 5 "register_operand"))
1430 (clobber (match_dup 1))])]
1432 && true_regnum (operands[1]) == LO_REGNUM
1433 && peep2_reg_dead_p (2, operands[1])
1434 && GP_REG_P (true_regnum (operands[3]))"
1435 [(parallel [(set (match_dup 0)
1437 (clobber (match_dup 5))
1438 (clobber (match_dup 1))])
1442 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1443 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1444 operands[2], operands[0]);
1447 ;; Same as above, except LO is the initial target of the macc.
1449 ;; Operand 0: GPR (scratch)
1451 ;; Operand 2: GPR (addend)
1452 ;; Operand 3: macc/msac
1454 ;; Operand 5: GPR (destination)
1455 ;; Operand 6: new multiplication
1456 ;; Operand 7: new addition/subtraction
1458 [(match_scratch:SI 0 "d")
1459 (set (match_operand:SI 1 "register_operand")
1460 (match_operand:SI 2 "register_operand"))
1464 (match_operand:SI 3 "macc_msac_operand"))
1465 (clobber (match_operand:SI 4 "register_operand"))
1466 (clobber (scratch:SI))])
1468 (set (match_operand:SI 5 "register_operand")
1469 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1470 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1471 [(parallel [(set (match_dup 0)
1473 (clobber (match_dup 4))
1474 (clobber (match_dup 1))])
1478 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1479 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1480 operands[2], operands[0]);
1483 (define_insn "*mul_sub_si"
1484 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1485 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1486 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1487 (match_operand:SI 3 "register_operand" "d,d,d"))))
1488 (clobber (match_scratch:SI 4 "=h,h,h"))
1489 (clobber (match_scratch:SI 5 "=X,1,l"))
1490 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1491 "GENERATE_MADD_MSUB"
1496 [(set_attr "type" "imadd")
1497 (set_attr "mode" "SI")
1498 (set_attr "length" "4,8,8")])
1500 ;; Split the above insn if we failed to get LO allocated.
1502 [(set (match_operand:SI 0 "register_operand")
1503 (minus:SI (match_operand:SI 1 "register_operand")
1504 (mult:SI (match_operand:SI 2 "register_operand")
1505 (match_operand:SI 3 "register_operand"))))
1506 (clobber (match_scratch:SI 4))
1507 (clobber (match_scratch:SI 5))
1508 (clobber (match_scratch:SI 6))]
1509 "reload_completed && !TARGET_DEBUG_D_MODE
1510 && GP_REG_P (true_regnum (operands[0]))
1511 && GP_REG_P (true_regnum (operands[1]))"
1512 [(parallel [(set (match_dup 6)
1513 (mult:SI (match_dup 2) (match_dup 3)))
1514 (clobber (match_dup 4))
1515 (clobber (match_dup 5))])
1516 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1519 ;; Splitter to copy result of MSUB to a general register
1521 [(set (match_operand:SI 0 "register_operand")
1522 (minus:SI (match_operand:SI 1 "register_operand")
1523 (mult:SI (match_operand:SI 2 "register_operand")
1524 (match_operand:SI 3 "register_operand"))))
1525 (clobber (match_scratch:SI 4))
1526 (clobber (match_scratch:SI 5))
1527 (clobber (match_scratch:SI 6))]
1528 "reload_completed && !TARGET_DEBUG_D_MODE
1529 && GP_REG_P (true_regnum (operands[0]))
1530 && true_regnum (operands[1]) == LO_REGNUM"
1531 [(parallel [(set (match_dup 1)
1532 (minus:SI (match_dup 1)
1533 (mult:SI (match_dup 2) (match_dup 3))))
1534 (clobber (match_dup 4))
1535 (clobber (match_dup 5))
1536 (clobber (match_dup 6))])
1537 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1540 (define_insn "*muls"
1541 [(set (match_operand:SI 0 "register_operand" "=l,d")
1542 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1543 (match_operand:SI 2 "register_operand" "d,d"))))
1544 (clobber (match_scratch:SI 3 "=h,h"))
1545 (clobber (match_scratch:SI 4 "=X,l"))]
1550 [(set_attr "type" "imul,imul3")
1551 (set_attr "mode" "SI")])
1553 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1555 (define_expand "<u>mulsidi3"
1557 [(set (match_operand:DI 0 "register_operand")
1558 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1559 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1560 (clobber (scratch:DI))
1561 (clobber (scratch:DI))
1562 (clobber (scratch:DI))])]
1563 "!TARGET_64BIT || !TARGET_FIX_R4000"
1567 if (!TARGET_FIX_R4000)
1568 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1571 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1577 (define_insn "<u>mulsidi3_32bit_internal"
1578 [(set (match_operand:DI 0 "register_operand" "=x")
1579 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1580 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1581 "!TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_DSPR2"
1583 [(set_attr "type" "imul")
1584 (set_attr "mode" "SI")])
1586 (define_insn "<u>mulsidi3_32bit_r4000"
1587 [(set (match_operand:DI 0 "register_operand" "=d")
1588 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1589 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1590 (clobber (match_scratch:DI 3 "=x"))]
1591 "!TARGET_64BIT && TARGET_FIX_R4000"
1592 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1593 [(set_attr "type" "imul")
1594 (set_attr "mode" "SI")
1595 (set_attr "length" "12")])
1597 (define_insn_and_split "*<u>mulsidi3_64bit"
1598 [(set (match_operand:DI 0 "register_operand" "=d")
1599 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1600 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1601 (clobber (match_scratch:DI 3 "=l"))
1602 (clobber (match_scratch:DI 4 "=h"))
1603 (clobber (match_scratch:DI 5 "=d"))]
1604 "TARGET_64BIT && !TARGET_FIX_R4000"
1606 "&& reload_completed"
1610 (mult:SI (match_dup 1)
1614 (mult:DI (any_extend:DI (match_dup 1))
1615 (any_extend:DI (match_dup 2)))
1618 ;; OP5 <- LO, OP0 <- HI
1619 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1620 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1624 (ashift:DI (match_dup 5)
1627 (lshiftrt:DI (match_dup 5)
1630 ;; Shift OP0 into place.
1632 (ashift:DI (match_dup 0)
1635 ;; OR the two halves together
1637 (ior:DI (match_dup 0)
1640 [(set_attr "type" "imul")
1641 (set_attr "mode" "SI")
1642 (set_attr "length" "24")])
1644 (define_insn "*<u>mulsidi3_64bit_parts"
1645 [(set (match_operand:DI 0 "register_operand" "=l")
1647 (mult:SI (match_operand:SI 2 "register_operand" "d")
1648 (match_operand:SI 3 "register_operand" "d"))))
1649 (set (match_operand:DI 1 "register_operand" "=h")
1651 (mult:DI (any_extend:DI (match_dup 2))
1652 (any_extend:DI (match_dup 3)))
1654 "TARGET_64BIT && !TARGET_FIX_R4000"
1656 [(set_attr "type" "imul")
1657 (set_attr "mode" "SI")])
1659 ;; Widening multiply with negation.
1660 (define_insn "*muls<u>_di"
1661 [(set (match_operand:DI 0 "register_operand" "=x")
1664 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1665 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1666 "!TARGET_64BIT && ISA_HAS_MULS"
1668 [(set_attr "type" "imul")
1669 (set_attr "mode" "SI")])
1671 (define_insn "<u>msubsidi4"
1672 [(set (match_operand:DI 0 "register_operand" "=ka")
1674 (match_operand:DI 3 "register_operand" "0")
1676 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1677 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1678 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || TARGET_DSPR2)"
1681 return "msub<u>\t%q0,%1,%2";
1682 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1683 return "msub<u>\t%1,%2";
1685 return "msac<u>\t$0,%1,%2";
1687 [(set_attr "type" "imadd")
1688 (set_attr "mode" "SI")])
1690 ;; _highpart patterns
1692 (define_expand "<su>mulsi3_highpart"
1693 [(set (match_operand:SI 0 "register_operand")
1696 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1697 (any_extend:DI (match_operand:SI 2 "register_operand")))
1699 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1702 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1706 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1711 (define_insn "<su>mulsi3_highpart_internal"
1712 [(set (match_operand:SI 0 "register_operand" "=h")
1715 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1716 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1718 (clobber (match_scratch:SI 3 "=l"))]
1719 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1721 [(set_attr "type" "imul")
1722 (set_attr "mode" "SI")])
1724 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1725 [(set (match_operand:SI 0 "register_operand" "=h,d")
1729 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1730 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1732 (clobber (match_scratch:SI 3 "=l,l"))
1733 (clobber (match_scratch:SI 4 "=X,h"))]
1738 [(set_attr "type" "imul,imul3")
1739 (set_attr "mode" "SI")])
1741 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1742 [(set (match_operand:SI 0 "register_operand" "=h,d")
1747 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1748 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1750 (clobber (match_scratch:SI 3 "=l,l"))
1751 (clobber (match_scratch:SI 4 "=X,h"))]
1755 mulshi<u>\t%0,%1,%2"
1756 [(set_attr "type" "imul,imul3")
1757 (set_attr "mode" "SI")])
1759 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1760 ;; errata MD(0), which says that dmultu does not always produce the
1762 (define_insn "<su>muldi3_highpart"
1763 [(set (match_operand:DI 0 "register_operand" "=h")
1767 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1768 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1770 (clobber (match_scratch:DI 3 "=l"))]
1771 "TARGET_64BIT && !TARGET_FIX_R4000
1772 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1774 [(set_attr "type" "imul")
1775 (set_attr "mode" "DI")])
1777 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
1778 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
1780 (define_insn "madsi"
1781 [(set (match_operand:SI 0 "register_operand" "+l")
1782 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1783 (match_operand:SI 2 "register_operand" "d"))
1785 (clobber (match_scratch:SI 3 "=h"))]
1788 [(set_attr "type" "imadd")
1789 (set_attr "mode" "SI")])
1791 (define_insn "<u>maddsidi4"
1792 [(set (match_operand:DI 0 "register_operand" "=ka")
1794 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1795 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1796 (match_operand:DI 3 "register_operand" "0")))]
1797 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || TARGET_DSPR2)
1801 return "mad<u>\t%1,%2";
1802 else if (TARGET_DSPR2)
1803 return "madd<u>\t%q0,%1,%2";
1804 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
1805 return "madd<u>\t%1,%2";
1807 /* See comment in *macc. */
1808 return "%[macc<u>\t%@,%1,%2%]";
1810 [(set_attr "type" "imadd")
1811 (set_attr "mode" "SI")])
1813 ;; Floating point multiply accumulate instructions.
1815 (define_insn "*madd<mode>"
1816 [(set (match_operand:ANYF 0 "register_operand" "=f")
1817 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1818 (match_operand:ANYF 2 "register_operand" "f"))
1819 (match_operand:ANYF 3 "register_operand" "f")))]
1820 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1821 "madd.<fmt>\t%0,%3,%1,%2"
1822 [(set_attr "type" "fmadd")
1823 (set_attr "mode" "<UNITMODE>")])
1825 (define_insn "*msub<mode>"
1826 [(set (match_operand:ANYF 0 "register_operand" "=f")
1827 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1828 (match_operand:ANYF 2 "register_operand" "f"))
1829 (match_operand:ANYF 3 "register_operand" "f")))]
1830 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1831 "msub.<fmt>\t%0,%3,%1,%2"
1832 [(set_attr "type" "fmadd")
1833 (set_attr "mode" "<UNITMODE>")])
1835 (define_insn "*nmadd<mode>"
1836 [(set (match_operand:ANYF 0 "register_operand" "=f")
1837 (neg:ANYF (plus:ANYF
1838 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1839 (match_operand:ANYF 2 "register_operand" "f"))
1840 (match_operand:ANYF 3 "register_operand" "f"))))]
1841 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1842 && HONOR_SIGNED_ZEROS (<MODE>mode)
1843 && !HONOR_NANS (<MODE>mode)"
1844 "nmadd.<fmt>\t%0,%3,%1,%2"
1845 [(set_attr "type" "fmadd")
1846 (set_attr "mode" "<UNITMODE>")])
1848 (define_insn "*nmadd<mode>_fastmath"
1849 [(set (match_operand:ANYF 0 "register_operand" "=f")
1851 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1852 (match_operand:ANYF 2 "register_operand" "f"))
1853 (match_operand:ANYF 3 "register_operand" "f")))]
1854 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1855 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1856 && !HONOR_NANS (<MODE>mode)"
1857 "nmadd.<fmt>\t%0,%3,%1,%2"
1858 [(set_attr "type" "fmadd")
1859 (set_attr "mode" "<UNITMODE>")])
1861 (define_insn "*nmsub<mode>"
1862 [(set (match_operand:ANYF 0 "register_operand" "=f")
1863 (neg:ANYF (minus:ANYF
1864 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1865 (match_operand:ANYF 3 "register_operand" "f"))
1866 (match_operand:ANYF 1 "register_operand" "f"))))]
1867 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1868 && HONOR_SIGNED_ZEROS (<MODE>mode)
1869 && !HONOR_NANS (<MODE>mode)"
1870 "nmsub.<fmt>\t%0,%1,%2,%3"
1871 [(set_attr "type" "fmadd")
1872 (set_attr "mode" "<UNITMODE>")])
1874 (define_insn "*nmsub<mode>_fastmath"
1875 [(set (match_operand:ANYF 0 "register_operand" "=f")
1877 (match_operand:ANYF 1 "register_operand" "f")
1878 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1879 (match_operand:ANYF 3 "register_operand" "f"))))]
1880 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1881 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1882 && !HONOR_NANS (<MODE>mode)"
1883 "nmsub.<fmt>\t%0,%1,%2,%3"
1884 [(set_attr "type" "fmadd")
1885 (set_attr "mode" "<UNITMODE>")])
1888 ;; ....................
1890 ;; DIVISION and REMAINDER
1892 ;; ....................
1895 (define_expand "div<mode>3"
1896 [(set (match_operand:ANYF 0 "register_operand")
1897 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1898 (match_operand:ANYF 2 "register_operand")))]
1899 "<divide_condition>"
1901 if (const_1_operand (operands[1], <MODE>mode))
1902 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
1903 operands[1] = force_reg (<MODE>mode, operands[1]);
1906 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1908 ;; If an mfc1 or dmfc1 happens to access the floating point register
1909 ;; file at the same time a long latency operation (div, sqrt, recip,
1910 ;; sqrt) iterates an intermediate result back through the floating
1911 ;; point register file bypass, then instead returning the correct
1912 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1913 ;; result of the long latency operation.
1915 ;; The workaround is to insert an unconditional 'mov' from/to the
1916 ;; long latency op destination register.
1918 (define_insn "*div<mode>3"
1919 [(set (match_operand:ANYF 0 "register_operand" "=f")
1920 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1921 (match_operand:ANYF 2 "register_operand" "f")))]
1922 "<divide_condition>"
1925 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1927 return "div.<fmt>\t%0,%1,%2";
1929 [(set_attr "type" "fdiv")
1930 (set_attr "mode" "<UNITMODE>")
1931 (set (attr "length")
1932 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1936 (define_insn "*recip<mode>3"
1937 [(set (match_operand:ANYF 0 "register_operand" "=f")
1938 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1939 (match_operand:ANYF 2 "register_operand" "f")))]
1940 "<recip_condition> && flag_unsafe_math_optimizations"
1943 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1945 return "recip.<fmt>\t%0,%2";
1947 [(set_attr "type" "frdiv")
1948 (set_attr "mode" "<UNITMODE>")
1949 (set (attr "length")
1950 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1954 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
1955 ;; with negative operands. We use special libgcc functions instead.
1956 (define_insn "divmod<mode>4"
1957 [(set (match_operand:GPR 0 "register_operand" "=l")
1958 (div:GPR (match_operand:GPR 1 "register_operand" "d")
1959 (match_operand:GPR 2 "register_operand" "d")))
1960 (set (match_operand:GPR 3 "register_operand" "=h")
1961 (mod:GPR (match_dup 1)
1963 "!TARGET_FIX_VR4120"
1964 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
1965 [(set_attr "type" "idiv")
1966 (set_attr "mode" "<MODE>")])
1968 (define_insn "udivmod<mode>4"
1969 [(set (match_operand:GPR 0 "register_operand" "=l")
1970 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
1971 (match_operand:GPR 2 "register_operand" "d")))
1972 (set (match_operand:GPR 3 "register_operand" "=h")
1973 (umod:GPR (match_dup 1)
1976 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
1977 [(set_attr "type" "idiv")
1978 (set_attr "mode" "<MODE>")])
1981 ;; ....................
1985 ;; ....................
1987 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
1988 ;; "*div[sd]f3" comment for details).
1990 (define_insn "sqrt<mode>2"
1991 [(set (match_operand:ANYF 0 "register_operand" "=f")
1992 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1996 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
1998 return "sqrt.<fmt>\t%0,%1";
2000 [(set_attr "type" "fsqrt")
2001 (set_attr "mode" "<UNITMODE>")
2002 (set (attr "length")
2003 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2007 (define_insn "*rsqrt<mode>a"
2008 [(set (match_operand:ANYF 0 "register_operand" "=f")
2009 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2010 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2011 "<recip_condition> && flag_unsafe_math_optimizations"
2014 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2016 return "rsqrt.<fmt>\t%0,%2";
2018 [(set_attr "type" "frsqrt")
2019 (set_attr "mode" "<UNITMODE>")
2020 (set (attr "length")
2021 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2025 (define_insn "*rsqrt<mode>b"
2026 [(set (match_operand:ANYF 0 "register_operand" "=f")
2027 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2028 (match_operand:ANYF 2 "register_operand" "f"))))]
2029 "<recip_condition> && flag_unsafe_math_optimizations"
2032 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2034 return "rsqrt.<fmt>\t%0,%2";
2036 [(set_attr "type" "frsqrt")
2037 (set_attr "mode" "<UNITMODE>")
2038 (set (attr "length")
2039 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2044 ;; ....................
2048 ;; ....................
2050 ;; Do not use the integer abs macro instruction, since that signals an
2051 ;; exception on -2147483648 (sigh).
2053 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2054 ;; invalid; it does not clear their sign bits. We therefore can't use
2055 ;; abs.fmt if the signs of NaNs matter.
2057 (define_insn "abs<mode>2"
2058 [(set (match_operand:ANYF 0 "register_operand" "=f")
2059 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2060 "!HONOR_NANS (<MODE>mode)"
2062 [(set_attr "type" "fabs")
2063 (set_attr "mode" "<UNITMODE>")])
2066 ;; ...................
2068 ;; Count leading zeroes.
2070 ;; ...................
2073 (define_insn "clz<mode>2"
2074 [(set (match_operand:GPR 0 "register_operand" "=d")
2075 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2078 [(set_attr "type" "clz")
2079 (set_attr "mode" "<MODE>")])
2082 ;; ....................
2084 ;; NEGATION and ONE'S COMPLEMENT
2086 ;; ....................
2088 (define_insn "negsi2"
2089 [(set (match_operand:SI 0 "register_operand" "=d")
2090 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2094 return "neg\t%0,%1";
2096 return "subu\t%0,%.,%1";
2098 [(set_attr "type" "arith")
2099 (set_attr "mode" "SI")])
2101 (define_insn "negdi2"
2102 [(set (match_operand:DI 0 "register_operand" "=d")
2103 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2104 "TARGET_64BIT && !TARGET_MIPS16"
2106 [(set_attr "type" "arith")
2107 (set_attr "mode" "DI")])
2109 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2110 ;; invalid; it does not flip their sign bit. We therefore can't use
2111 ;; neg.fmt if the signs of NaNs matter.
2113 (define_insn "neg<mode>2"
2114 [(set (match_operand:ANYF 0 "register_operand" "=f")
2115 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2116 "!HONOR_NANS (<MODE>mode)"
2118 [(set_attr "type" "fneg")
2119 (set_attr "mode" "<UNITMODE>")])
2121 (define_insn "one_cmpl<mode>2"
2122 [(set (match_operand:GPR 0 "register_operand" "=d")
2123 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2127 return "not\t%0,%1";
2129 return "nor\t%0,%.,%1";
2131 [(set_attr "type" "logical")
2132 (set_attr "mode" "<MODE>")])
2135 ;; ....................
2139 ;; ....................
2142 ;; Many of these instructions use trivial define_expands, because we
2143 ;; want to use a different set of constraints when TARGET_MIPS16.
2145 (define_expand "and<mode>3"
2146 [(set (match_operand:GPR 0 "register_operand")
2147 (and:GPR (match_operand:GPR 1 "register_operand")
2148 (match_operand:GPR 2 "uns_arith_operand")))]
2152 operands[2] = force_reg (<MODE>mode, operands[2]);
2155 (define_insn "*and<mode>3"
2156 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2157 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2158 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2163 [(set_attr "type" "logical")
2164 (set_attr "mode" "<MODE>")])
2166 (define_insn "*and<mode>3_mips16"
2167 [(set (match_operand:GPR 0 "register_operand" "=d")
2168 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2169 (match_operand:GPR 2 "register_operand" "d")))]
2172 [(set_attr "type" "logical")
2173 (set_attr "mode" "<MODE>")])
2175 (define_expand "ior<mode>3"
2176 [(set (match_operand:GPR 0 "register_operand")
2177 (ior:GPR (match_operand:GPR 1 "register_operand")
2178 (match_operand:GPR 2 "uns_arith_operand")))]
2182 operands[2] = force_reg (<MODE>mode, operands[2]);
2185 (define_insn "*ior<mode>3"
2186 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2187 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2188 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2193 [(set_attr "type" "logical")
2194 (set_attr "mode" "<MODE>")])
2196 (define_insn "*ior<mode>3_mips16"
2197 [(set (match_operand:GPR 0 "register_operand" "=d")
2198 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2199 (match_operand:GPR 2 "register_operand" "d")))]
2202 [(set_attr "type" "logical")
2203 (set_attr "mode" "<MODE>")])
2205 (define_expand "xor<mode>3"
2206 [(set (match_operand:GPR 0 "register_operand")
2207 (xor:GPR (match_operand:GPR 1 "register_operand")
2208 (match_operand:GPR 2 "uns_arith_operand")))]
2213 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2214 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2215 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2220 [(set_attr "type" "logical")
2221 (set_attr "mode" "<MODE>")])
2224 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2225 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2226 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2232 [(set_attr "type" "logical,arith,arith")
2233 (set_attr "mode" "<MODE>")
2234 (set_attr_alternative "length"
2236 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2241 (define_insn "*nor<mode>3"
2242 [(set (match_operand:GPR 0 "register_operand" "=d")
2243 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2244 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2247 [(set_attr "type" "logical")
2248 (set_attr "mode" "<MODE>")])
2251 ;; ....................
2255 ;; ....................
2259 (define_insn "truncdfsf2"
2260 [(set (match_operand:SF 0 "register_operand" "=f")
2261 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2262 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2264 [(set_attr "type" "fcvt")
2265 (set_attr "cnv_mode" "D2S")
2266 (set_attr "mode" "SF")])
2268 ;; Integer truncation patterns. Truncating SImode values to smaller
2269 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2270 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2271 ;; need to make sure that the lower 32 bits are properly sign-extended
2272 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2273 ;; smaller than SImode is equivalent to two separate truncations:
2276 ;; DI ---> HI == DI ---> SI ---> HI
2277 ;; DI ---> QI == DI ---> SI ---> QI
2279 ;; Step A needs a real instruction but step B does not.
2281 (define_insn "truncdisi2"
2282 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2283 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2288 [(set_attr "type" "shift,store")
2289 (set_attr "mode" "SI")
2290 (set_attr "extended_mips16" "yes,*")])
2292 (define_insn "truncdihi2"
2293 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2294 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2299 [(set_attr "type" "shift,store")
2300 (set_attr "mode" "SI")
2301 (set_attr "extended_mips16" "yes,*")])
2303 (define_insn "truncdiqi2"
2304 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2305 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2310 [(set_attr "type" "shift,store")
2311 (set_attr "mode" "SI")
2312 (set_attr "extended_mips16" "yes,*")])
2314 ;; Combiner patterns to optimize shift/truncate combinations.
2317 [(set (match_operand:SI 0 "register_operand" "=d")
2319 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2320 (match_operand:DI 2 "const_arith_operand" ""))))]
2321 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2323 [(set_attr "type" "shift")
2324 (set_attr "mode" "SI")])
2327 [(set (match_operand:SI 0 "register_operand" "=d")
2328 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2330 "TARGET_64BIT && !TARGET_MIPS16"
2332 [(set_attr "type" "shift")
2333 (set_attr "mode" "SI")])
2336 ;; Combiner patterns for truncate/sign_extend combinations. They use
2337 ;; the shift/truncate patterns above.
2339 (define_insn_and_split ""
2340 [(set (match_operand:SI 0 "register_operand" "=d")
2342 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2343 "TARGET_64BIT && !TARGET_MIPS16"
2345 "&& reload_completed"
2347 (ashift:DI (match_dup 1)
2350 (truncate:SI (ashiftrt:DI (match_dup 2)
2352 { operands[2] = gen_lowpart (DImode, operands[0]); })
2354 (define_insn_and_split ""
2355 [(set (match_operand:SI 0 "register_operand" "=d")
2357 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2358 "TARGET_64BIT && !TARGET_MIPS16"
2360 "&& reload_completed"
2362 (ashift:DI (match_dup 1)
2365 (truncate:SI (ashiftrt:DI (match_dup 2)
2367 { operands[2] = gen_lowpart (DImode, operands[0]); })
2370 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2373 [(set (match_operand:SI 0 "register_operand" "=d")
2374 (zero_extend:SI (truncate:HI
2375 (match_operand:DI 1 "register_operand" "d"))))]
2376 "TARGET_64BIT && !TARGET_MIPS16"
2377 "andi\t%0,%1,0xffff"
2378 [(set_attr "type" "logical")
2379 (set_attr "mode" "SI")])
2382 [(set (match_operand:SI 0 "register_operand" "=d")
2383 (zero_extend:SI (truncate:QI
2384 (match_operand:DI 1 "register_operand" "d"))))]
2385 "TARGET_64BIT && !TARGET_MIPS16"
2387 [(set_attr "type" "logical")
2388 (set_attr "mode" "SI")])
2391 [(set (match_operand:HI 0 "register_operand" "=d")
2392 (zero_extend:HI (truncate:QI
2393 (match_operand:DI 1 "register_operand" "d"))))]
2394 "TARGET_64BIT && !TARGET_MIPS16"
2396 [(set_attr "type" "logical")
2397 (set_attr "mode" "HI")])
2400 ;; ....................
2404 ;; ....................
2408 (define_insn_and_split "zero_extendsidi2"
2409 [(set (match_operand:DI 0 "register_operand" "=d,d")
2410 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2415 "&& reload_completed && REG_P (operands[1])"
2417 (ashift:DI (match_dup 1) (const_int 32)))
2419 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2420 { operands[1] = gen_lowpart (DImode, operands[1]); }
2421 [(set_attr "type" "multi,load")
2422 (set_attr "mode" "DI")
2423 (set_attr "length" "8,*")])
2425 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2426 ;; because of TRULY_NOOP_TRUNCATION.
2428 (define_insn_and_split "*clear_upper32"
2429 [(set (match_operand:DI 0 "register_operand" "=d,d")
2430 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2431 (const_int 4294967295)))]
2434 if (which_alternative == 0)
2437 operands[1] = gen_lowpart (SImode, operands[1]);
2438 return "lwu\t%0,%1";
2440 "&& reload_completed && REG_P (operands[1])"
2442 (ashift:DI (match_dup 1) (const_int 32)))
2444 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2446 [(set_attr "type" "multi,load")
2447 (set_attr "mode" "DI")
2448 (set_attr "length" "8,*")])
2450 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2451 [(set (match_operand:GPR 0 "register_operand")
2452 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2455 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2456 && !memory_operand (operands[1], <SHORT:MODE>mode))
2458 emit_insn (gen_and<GPR:mode>3 (operands[0],
2459 gen_lowpart (<GPR:MODE>mode, operands[1]),
2460 force_reg (<GPR:MODE>mode,
2461 GEN_INT (<SHORT:mask>))));
2466 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2467 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2469 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2472 andi\t%0,%1,<SHORT:mask>
2473 l<SHORT:size>u\t%0,%1"
2474 [(set_attr "type" "logical,load")
2475 (set_attr "mode" "<GPR:MODE>")])
2477 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2478 [(set (match_operand:GPR 0 "register_operand" "=d")
2479 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2481 "ze<SHORT:size>\t%0"
2482 [(set_attr "type" "arith")
2483 (set_attr "mode" "<GPR:MODE>")])
2485 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2486 [(set (match_operand:GPR 0 "register_operand" "=d")
2487 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2489 "l<SHORT:size>u\t%0,%1"
2490 [(set_attr "type" "load")
2491 (set_attr "mode" "<GPR:MODE>")])
2493 (define_expand "zero_extendqihi2"
2494 [(set (match_operand:HI 0 "register_operand")
2495 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2498 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2500 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2506 (define_insn "*zero_extendqihi2"
2507 [(set (match_operand:HI 0 "register_operand" "=d,d")
2508 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2513 [(set_attr "type" "logical,load")
2514 (set_attr "mode" "HI")])
2516 (define_insn "*zero_extendqihi2_mips16"
2517 [(set (match_operand:HI 0 "register_operand" "=d")
2518 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2521 [(set_attr "type" "load")
2522 (set_attr "mode" "HI")])
2525 ;; ....................
2529 ;; ....................
2532 ;; Those for integer source operand are ordered widest source type first.
2534 ;; When TARGET_64BIT, all SImode integer registers should already be in
2535 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2536 ;; therefore get rid of register->register instructions if we constrain
2537 ;; the source to be in the same register as the destination.
2539 ;; The register alternative has type "arith" so that the pre-reload
2540 ;; scheduler will treat it as a move. This reflects what happens if
2541 ;; the register alternative needs a reload.
2542 (define_insn_and_split "extendsidi2"
2543 [(set (match_operand:DI 0 "register_operand" "=d,d")
2544 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2549 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2552 emit_note (NOTE_INSN_DELETED);
2555 [(set_attr "type" "arith,load")
2556 (set_attr "mode" "DI")])
2558 (define_expand "extend<SHORT:mode><GPR:mode>2"
2559 [(set (match_operand:GPR 0 "register_operand")
2560 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2563 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2564 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2565 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2569 l<SHORT:size>\t%0,%1"
2570 [(set_attr "type" "signext,load")
2571 (set_attr "mode" "<GPR:MODE>")])
2573 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2574 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2576 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2577 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2580 l<SHORT:size>\t%0,%1"
2581 "&& reload_completed && REG_P (operands[1])"
2582 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2583 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2585 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2586 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2587 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2589 [(set_attr "type" "arith,load")
2590 (set_attr "mode" "<GPR:MODE>")
2591 (set_attr "length" "8,*")])
2593 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2594 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2596 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2599 se<SHORT:size>\t%0,%1
2600 l<SHORT:size>\t%0,%1"
2601 [(set_attr "type" "signext,load")
2602 (set_attr "mode" "<GPR:MODE>")])
2604 (define_expand "extendqihi2"
2605 [(set (match_operand:HI 0 "register_operand")
2606 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2609 (define_insn "*extendqihi2_mips16e"
2610 [(set (match_operand:HI 0 "register_operand" "=d,d")
2611 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
2616 [(set_attr "type" "signext,load")
2617 (set_attr "mode" "SI")])
2619 (define_insn_and_split "*extendqihi2"
2620 [(set (match_operand:HI 0 "register_operand" "=d,d")
2622 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2623 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2627 "&& reload_completed && REG_P (operands[1])"
2628 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
2629 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
2631 operands[0] = gen_lowpart (SImode, operands[0]);
2632 operands[1] = gen_lowpart (SImode, operands[1]);
2633 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
2634 - GET_MODE_BITSIZE (QImode));
2636 [(set_attr "type" "multi,load")
2637 (set_attr "mode" "SI")
2638 (set_attr "length" "8,*")])
2640 (define_insn "*extendqihi2_seb"
2641 [(set (match_operand:HI 0 "register_operand" "=d,d")
2643 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2648 [(set_attr "type" "signext,load")
2649 (set_attr "mode" "SI")])
2651 (define_insn "extendsfdf2"
2652 [(set (match_operand:DF 0 "register_operand" "=f")
2653 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2654 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2656 [(set_attr "type" "fcvt")
2657 (set_attr "cnv_mode" "S2D")
2658 (set_attr "mode" "DF")])
2661 ;; ....................
2665 ;; ....................
2667 (define_expand "fix_truncdfsi2"
2668 [(set (match_operand:SI 0 "register_operand")
2669 (fix:SI (match_operand:DF 1 "register_operand")))]
2670 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2672 if (!ISA_HAS_TRUNC_W)
2674 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2679 (define_insn "fix_truncdfsi2_insn"
2680 [(set (match_operand:SI 0 "register_operand" "=f")
2681 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2682 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2684 [(set_attr "type" "fcvt")
2685 (set_attr "mode" "DF")
2686 (set_attr "cnv_mode" "D2I")
2687 (set_attr "length" "4")])
2689 (define_insn "fix_truncdfsi2_macro"
2690 [(set (match_operand:SI 0 "register_operand" "=f")
2691 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2692 (clobber (match_scratch:DF 2 "=d"))]
2693 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2696 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2698 return "trunc.w.d %0,%1,%2";
2700 [(set_attr "type" "fcvt")
2701 (set_attr "mode" "DF")
2702 (set_attr "cnv_mode" "D2I")
2703 (set_attr "length" "36")])
2705 (define_expand "fix_truncsfsi2"
2706 [(set (match_operand:SI 0 "register_operand")
2707 (fix:SI (match_operand:SF 1 "register_operand")))]
2710 if (!ISA_HAS_TRUNC_W)
2712 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2717 (define_insn "fix_truncsfsi2_insn"
2718 [(set (match_operand:SI 0 "register_operand" "=f")
2719 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2720 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2722 [(set_attr "type" "fcvt")
2723 (set_attr "mode" "SF")
2724 (set_attr "cnv_mode" "S2I")
2725 (set_attr "length" "4")])
2727 (define_insn "fix_truncsfsi2_macro"
2728 [(set (match_operand:SI 0 "register_operand" "=f")
2729 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2730 (clobber (match_scratch:SF 2 "=d"))]
2731 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2734 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2736 return "trunc.w.s %0,%1,%2";
2738 [(set_attr "type" "fcvt")
2739 (set_attr "mode" "SF")
2740 (set_attr "cnv_mode" "S2I")
2741 (set_attr "length" "36")])
2744 (define_insn "fix_truncdfdi2"
2745 [(set (match_operand:DI 0 "register_operand" "=f")
2746 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2747 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2749 [(set_attr "type" "fcvt")
2750 (set_attr "mode" "DF")
2751 (set_attr "cnv_mode" "D2I")
2752 (set_attr "length" "4")])
2755 (define_insn "fix_truncsfdi2"
2756 [(set (match_operand:DI 0 "register_operand" "=f")
2757 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2758 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2760 [(set_attr "type" "fcvt")
2761 (set_attr "mode" "SF")
2762 (set_attr "cnv_mode" "S2I")
2763 (set_attr "length" "4")])
2766 (define_insn "floatsidf2"
2767 [(set (match_operand:DF 0 "register_operand" "=f")
2768 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2769 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2771 [(set_attr "type" "fcvt")
2772 (set_attr "mode" "DF")
2773 (set_attr "cnv_mode" "I2D")
2774 (set_attr "length" "4")])
2777 (define_insn "floatdidf2"
2778 [(set (match_operand:DF 0 "register_operand" "=f")
2779 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2780 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2782 [(set_attr "type" "fcvt")
2783 (set_attr "mode" "DF")
2784 (set_attr "cnv_mode" "I2D")
2785 (set_attr "length" "4")])
2788 (define_insn "floatsisf2"
2789 [(set (match_operand:SF 0 "register_operand" "=f")
2790 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2793 [(set_attr "type" "fcvt")
2794 (set_attr "mode" "SF")
2795 (set_attr "cnv_mode" "I2S")
2796 (set_attr "length" "4")])
2799 (define_insn "floatdisf2"
2800 [(set (match_operand:SF 0 "register_operand" "=f")
2801 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2802 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2804 [(set_attr "type" "fcvt")
2805 (set_attr "mode" "SF")
2806 (set_attr "cnv_mode" "I2S")
2807 (set_attr "length" "4")])
2810 (define_expand "fixuns_truncdfsi2"
2811 [(set (match_operand:SI 0 "register_operand")
2812 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2813 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2815 rtx reg1 = gen_reg_rtx (DFmode);
2816 rtx reg2 = gen_reg_rtx (DFmode);
2817 rtx reg3 = gen_reg_rtx (SImode);
2818 rtx label1 = gen_label_rtx ();
2819 rtx label2 = gen_label_rtx ();
2820 REAL_VALUE_TYPE offset;
2822 real_2expN (&offset, 31, DFmode);
2824 if (reg1) /* Turn off complaints about unreached code. */
2826 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2827 do_pending_stack_adjust ();
2829 emit_insn (gen_cmpdf (operands[1], reg1));
2830 emit_jump_insn (gen_bge (label1));
2832 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2833 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2834 gen_rtx_LABEL_REF (VOIDmode, label2)));
2837 emit_label (label1);
2838 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2839 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
2840 (BITMASK_HIGH, SImode)));
2842 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2843 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2845 emit_label (label2);
2847 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2848 fields, and can't be used for REG_NOTES anyway). */
2849 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2855 (define_expand "fixuns_truncdfdi2"
2856 [(set (match_operand:DI 0 "register_operand")
2857 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2858 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2860 rtx reg1 = gen_reg_rtx (DFmode);
2861 rtx reg2 = gen_reg_rtx (DFmode);
2862 rtx reg3 = gen_reg_rtx (DImode);
2863 rtx label1 = gen_label_rtx ();
2864 rtx label2 = gen_label_rtx ();
2865 REAL_VALUE_TYPE offset;
2867 real_2expN (&offset, 63, DFmode);
2869 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2870 do_pending_stack_adjust ();
2872 emit_insn (gen_cmpdf (operands[1], reg1));
2873 emit_jump_insn (gen_bge (label1));
2875 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2876 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2877 gen_rtx_LABEL_REF (VOIDmode, label2)));
2880 emit_label (label1);
2881 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2882 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
2883 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2885 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2886 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2888 emit_label (label2);
2890 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2891 fields, and can't be used for REG_NOTES anyway). */
2892 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2897 (define_expand "fixuns_truncsfsi2"
2898 [(set (match_operand:SI 0 "register_operand")
2899 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2902 rtx reg1 = gen_reg_rtx (SFmode);
2903 rtx reg2 = gen_reg_rtx (SFmode);
2904 rtx reg3 = gen_reg_rtx (SImode);
2905 rtx label1 = gen_label_rtx ();
2906 rtx label2 = gen_label_rtx ();
2907 REAL_VALUE_TYPE offset;
2909 real_2expN (&offset, 31, SFmode);
2911 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2912 do_pending_stack_adjust ();
2914 emit_insn (gen_cmpsf (operands[1], reg1));
2915 emit_jump_insn (gen_bge (label1));
2917 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2918 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2919 gen_rtx_LABEL_REF (VOIDmode, label2)));
2922 emit_label (label1);
2923 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2924 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
2925 (BITMASK_HIGH, SImode)));
2927 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2928 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2930 emit_label (label2);
2932 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2933 fields, and can't be used for REG_NOTES anyway). */
2934 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2939 (define_expand "fixuns_truncsfdi2"
2940 [(set (match_operand:DI 0 "register_operand")
2941 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
2942 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2944 rtx reg1 = gen_reg_rtx (SFmode);
2945 rtx reg2 = gen_reg_rtx (SFmode);
2946 rtx reg3 = gen_reg_rtx (DImode);
2947 rtx label1 = gen_label_rtx ();
2948 rtx label2 = gen_label_rtx ();
2949 REAL_VALUE_TYPE offset;
2951 real_2expN (&offset, 63, SFmode);
2953 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2954 do_pending_stack_adjust ();
2956 emit_insn (gen_cmpsf (operands[1], reg1));
2957 emit_jump_insn (gen_bge (label1));
2959 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
2960 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2961 gen_rtx_LABEL_REF (VOIDmode, label2)));
2964 emit_label (label1);
2965 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2966 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
2967 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2969 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
2970 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2972 emit_label (label2);
2974 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2975 fields, and can't be used for REG_NOTES anyway). */
2976 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2981 ;; ....................
2985 ;; ....................
2987 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
2989 (define_expand "extv"
2990 [(set (match_operand 0 "register_operand")
2991 (sign_extract (match_operand:QI 1 "memory_operand")
2992 (match_operand 2 "immediate_operand")
2993 (match_operand 3 "immediate_operand")))]
2996 if (mips_expand_unaligned_load (operands[0], operands[1],
2997 INTVAL (operands[2]),
2998 INTVAL (operands[3])))
3004 (define_expand "extzv"
3005 [(set (match_operand 0 "register_operand")
3006 (zero_extract (match_operand 1 "nonimmediate_operand")
3007 (match_operand 2 "immediate_operand")
3008 (match_operand 3 "immediate_operand")))]
3011 if (mips_expand_unaligned_load (operands[0], operands[1],
3012 INTVAL (operands[2]),
3013 INTVAL (operands[3])))
3015 else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3]))
3017 if (GET_MODE (operands[0]) == DImode)
3018 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3021 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3029 (define_insn "extzv<mode>"
3030 [(set (match_operand:GPR 0 "register_operand" "=d")
3031 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3032 (match_operand:SI 2 "immediate_operand" "I")
3033 (match_operand:SI 3 "immediate_operand" "I")))]
3034 "mips_use_ins_ext_p (operands[1], operands[2], operands[3])"
3035 "<d>ext\t%0,%1,%3,%2"
3036 [(set_attr "type" "arith")
3037 (set_attr "mode" "<MODE>")])
3040 (define_expand "insv"
3041 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3042 (match_operand 1 "immediate_operand")
3043 (match_operand 2 "immediate_operand"))
3044 (match_operand 3 "reg_or_0_operand"))]
3047 if (mips_expand_unaligned_store (operands[0], operands[3],
3048 INTVAL (operands[1]),
3049 INTVAL (operands[2])))
3051 else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2]))
3053 if (GET_MODE (operands[0]) == DImode)
3054 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3057 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3065 (define_insn "insv<mode>"
3066 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3067 (match_operand:SI 1 "immediate_operand" "I")
3068 (match_operand:SI 2 "immediate_operand" "I"))
3069 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3070 "mips_use_ins_ext_p (operands[0], operands[1], operands[2])"
3071 "<d>ins\t%0,%z3,%2,%1"
3072 [(set_attr "type" "arith")
3073 (set_attr "mode" "<MODE>")])
3075 ;; Unaligned word moves generated by the bit field patterns.
3077 ;; As far as the rtl is concerned, both the left-part and right-part
3078 ;; instructions can access the whole field. However, the real operand
3079 ;; refers to just the first or the last byte (depending on endianness).
3080 ;; We therefore use two memory operands to each instruction, one to
3081 ;; describe the rtl effect and one to use in the assembly output.
3083 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3084 ;; This allows us to use the standard length calculations for the "load"
3085 ;; and "store" type attributes.
3087 (define_insn "mov_<load>l"
3088 [(set (match_operand:GPR 0 "register_operand" "=d")
3089 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3090 (match_operand:QI 2 "memory_operand" "m")]
3092 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3094 [(set_attr "type" "load")
3095 (set_attr "mode" "<MODE>")])
3097 (define_insn "mov_<load>r"
3098 [(set (match_operand:GPR 0 "register_operand" "=d")
3099 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3100 (match_operand:QI 2 "memory_operand" "m")
3101 (match_operand:GPR 3 "register_operand" "0")]
3102 UNSPEC_LOAD_RIGHT))]
3103 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3105 [(set_attr "type" "load")
3106 (set_attr "mode" "<MODE>")])
3108 (define_insn "mov_<store>l"
3109 [(set (match_operand:BLK 0 "memory_operand" "=m")
3110 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3111 (match_operand:QI 2 "memory_operand" "m")]
3112 UNSPEC_STORE_LEFT))]
3113 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3115 [(set_attr "type" "store")
3116 (set_attr "mode" "<MODE>")])
3118 (define_insn "mov_<store>r"
3119 [(set (match_operand:BLK 0 "memory_operand" "+m")
3120 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3121 (match_operand:QI 2 "memory_operand" "m")
3123 UNSPEC_STORE_RIGHT))]
3124 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3126 [(set_attr "type" "store")
3127 (set_attr "mode" "<MODE>")])
3129 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3130 ;; The required value is:
3132 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3134 ;; which translates to:
3136 ;; lui op0,%highest(op1)
3137 ;; daddiu op0,op0,%higher(op1)
3139 ;; daddiu op0,op0,%hi(op1)
3142 ;; The split is deferred until after flow2 to allow the peephole2 below
3144 (define_insn_and_split "*lea_high64"
3145 [(set (match_operand:DI 0 "register_operand" "=d")
3146 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3147 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3149 "&& epilogue_completed"
3150 [(set (match_dup 0) (high:DI (match_dup 2)))
3151 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3152 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3153 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3154 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3156 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3157 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3159 [(set_attr "length" "20")])
3161 ;; Use a scratch register to reduce the latency of the above pattern
3162 ;; on superscalar machines. The optimized sequence is:
3164 ;; lui op1,%highest(op2)
3166 ;; daddiu op1,op1,%higher(op2)
3168 ;; daddu op1,op1,op0
3170 [(set (match_operand:DI 1 "register_operand")
3171 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3172 (match_scratch:DI 0 "d")]
3173 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3174 [(set (match_dup 1) (high:DI (match_dup 3)))
3175 (set (match_dup 0) (high:DI (match_dup 4)))
3176 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3177 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3178 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3180 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3181 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3184 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3185 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3186 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3187 ;; used once. We can then use the sequence:
3189 ;; lui op0,%highest(op1)
3191 ;; daddiu op0,op0,%higher(op1)
3192 ;; daddiu op2,op2,%lo(op1)
3194 ;; daddu op0,op0,op2
3196 ;; which takes 4 cycles on most superscalar targets.
3197 (define_insn_and_split "*lea64"
3198 [(set (match_operand:DI 0 "register_operand" "=d")
3199 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3200 (clobber (match_scratch:DI 2 "=&d"))]
3201 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3203 "&& reload_completed"
3204 [(set (match_dup 0) (high:DI (match_dup 3)))
3205 (set (match_dup 2) (high:DI (match_dup 4)))
3206 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3207 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3208 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3209 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3211 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3212 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3214 [(set_attr "length" "24")])
3216 ;; Split HIGHs into:
3221 ;; on MIPS16 targets.
3223 [(set (match_operand:SI 0 "register_operand" "=d")
3224 (high:SI (match_operand:SI 1 "absolute_symbolic_operand" "")))]
3225 "TARGET_MIPS16 && reload_completed"
3226 [(set (match_dup 0) (match_dup 2))
3227 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3229 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3232 ;; Insns to fetch a symbol from a big GOT.
3234 (define_insn_and_split "*xgot_hi<mode>"
3235 [(set (match_operand:P 0 "register_operand" "=d")
3236 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3237 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3239 "&& reload_completed"
3240 [(set (match_dup 0) (high:P (match_dup 2)))
3241 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3243 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3244 operands[3] = pic_offset_table_rtx;
3246 [(set_attr "got" "xgot_high")
3247 (set_attr "mode" "<MODE>")])
3249 (define_insn_and_split "*xgot_lo<mode>"
3250 [(set (match_operand:P 0 "register_operand" "=d")
3251 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3252 (match_operand:P 2 "got_disp_operand" "")))]
3253 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3255 "&& reload_completed"
3257 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3258 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3259 [(set_attr "got" "load")
3260 (set_attr "mode" "<MODE>")])
3262 ;; Insns to fetch a symbol from a normal GOT.
3264 (define_insn_and_split "*got_disp<mode>"
3265 [(set (match_operand:P 0 "register_operand" "=d")
3266 (match_operand:P 1 "got_disp_operand" ""))]
3267 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
3269 "&& reload_completed"
3271 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3273 operands[2] = pic_offset_table_rtx;
3274 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3276 [(set_attr "got" "load")
3277 (set_attr "mode" "<MODE>")])
3279 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3281 (define_insn_and_split "*got_page<mode>"
3282 [(set (match_operand:P 0 "register_operand" "=d")
3283 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3284 "TARGET_EXPLICIT_RELOCS"
3286 "&& reload_completed"
3288 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3290 operands[2] = pic_offset_table_rtx;
3291 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3293 [(set_attr "got" "load")
3294 (set_attr "mode" "<MODE>")])
3296 ;; Lower-level instructions for loading an address from the GOT.
3297 ;; We could use MEMs, but an unspec gives more optimization
3300 (define_insn "load_got<mode>"
3301 [(set (match_operand:P 0 "register_operand" "=d")
3302 (unspec:P [(match_operand:P 1 "register_operand" "d")
3303 (match_operand:P 2 "immediate_operand" "")]
3306 "<load>\t%0,%R2(%1)"
3307 [(set_attr "type" "load")
3308 (set_attr "mode" "<MODE>")
3309 (set_attr "length" "4")])
3311 ;; Instructions for adding the low 16 bits of an address to a register.
3312 ;; Operand 2 is the address: print_operand works out which relocation
3313 ;; should be applied.
3315 (define_insn "*low<mode>"
3316 [(set (match_operand:P 0 "register_operand" "=d")
3317 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3318 (match_operand:P 2 "immediate_operand" "")))]
3320 "<d>addiu\t%0,%1,%R2"
3321 [(set_attr "type" "arith")
3322 (set_attr "mode" "<MODE>")])
3324 (define_insn "*low<mode>_mips16"
3325 [(set (match_operand:P 0 "register_operand" "=d")
3326 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3327 (match_operand:P 2 "immediate_operand" "")))]
3330 [(set_attr "type" "arith")
3331 (set_attr "mode" "<MODE>")
3332 (set_attr "length" "8")])
3334 ;; Allow combine to split complex const_int load sequences, using operand 2
3335 ;; to store the intermediate results. See move_operand for details.
3337 [(set (match_operand:GPR 0 "register_operand")
3338 (match_operand:GPR 1 "splittable_const_int_operand"))
3339 (clobber (match_operand:GPR 2 "register_operand"))]
3343 mips_move_integer (operands[0], operands[2], INTVAL (operands[1]));
3347 ;; Likewise, for symbolic operands.
3349 [(set (match_operand:P 0 "register_operand")
3350 (match_operand:P 1))
3351 (clobber (match_operand:P 2 "register_operand"))]
3352 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3353 [(set (match_dup 0) (match_dup 3))]
3355 mips_split_symbol (operands[2], operands[1],
3356 MAX_MACHINE_MODE, &operands[3]);
3359 ;; 64-bit integer moves
3361 ;; Unlike most other insns, the move insns can't be split with
3362 ;; different predicates, because register spilling and other parts of
3363 ;; the compiler, have memoized the insn number already.
3365 (define_expand "movdi"
3366 [(set (match_operand:DI 0 "")
3367 (match_operand:DI 1 ""))]
3370 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3374 ;; For mips16, we need a special case to handle storing $31 into
3375 ;; memory, since we don't have a constraint to match $31. This
3376 ;; instruction can be generated by save_restore_insns.
3378 (define_insn "*mov<mode>_ra"
3379 [(set (match_operand:GPR 0 "stack_operand" "=m")
3383 [(set_attr "type" "store")
3384 (set_attr "mode" "<MODE>")])
3386 (define_insn "*movdi_32bit"
3387 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3388 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3389 "!TARGET_64BIT && !TARGET_FLOAT64 && !TARGET_MIPS16
3390 && (register_operand (operands[0], DImode)
3391 || reg_or_0_operand (operands[1], DImode))"
3392 { return mips_output_move (operands[0], operands[1]); }
3393 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store")
3394 (set_attr "mode" "DI")
3395 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3397 (define_insn "*movdi_gp32_fp64"
3398 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*f,*d,*m")
3399 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*f,*J*d,*m,*f,*f"))]
3400 "!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
3401 && (register_operand (operands[0], DImode)
3402 || reg_or_0_operand (operands[1], DImode))"
3403 { return mips_output_move (operands[0], operands[1]); }
3404 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,fmove,mtc,fpload,mfc,fpstore")
3405 (set_attr "mode" "DI")
3406 (set_attr "length" "8,16,*,*,8,8,4,8,*,8,*")])
3408 (define_insn "*movdi_32bit_mips16"
3409 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3410 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3411 "!TARGET_64BIT && TARGET_MIPS16
3412 && (register_operand (operands[0], DImode)
3413 || register_operand (operands[1], DImode))"
3414 { return mips_output_move (operands[0], operands[1]); }
3415 [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo")
3416 (set_attr "mode" "DI")
3417 (set_attr "length" "8,8,8,8,12,*,*,8")])
3419 (define_insn "*movdi_64bit"
3420 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3421 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3422 "TARGET_64BIT && !TARGET_MIPS16
3423 && (register_operand (operands[0], DImode)
3424 || reg_or_0_operand (operands[1], DImode))"
3425 { return mips_output_move (operands[0], operands[1]); }
3426 [(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
3427 (set_attr "mode" "DI")
3428 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
3430 (define_insn "*movdi_64bit_mips16"
3431 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
3432 (match_operand:DI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))]
3433 "TARGET_64BIT && TARGET_MIPS16
3434 && (register_operand (operands[0], DImode)
3435 || register_operand (operands[1], DImode))"
3436 { return mips_output_move (operands[0], operands[1]); }
3437 [(set_attr "type" "move,move,move,arith,arith,load,const,load,store")
3438 (set_attr "mode" "DI")
3439 (set_attr_alternative "length"
3443 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3446 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3452 (const_string "*")])])
3455 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3456 ;; when the original load is a 4 byte instruction but the add and the
3457 ;; load are 2 2 byte instructions.
3460 [(set (match_operand:DI 0 "register_operand")
3461 (mem:DI (plus:DI (match_dup 0)
3462 (match_operand:DI 1 "const_int_operand"))))]
3463 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3464 && !TARGET_DEBUG_D_MODE
3465 && REG_P (operands[0])
3466 && M16_REG_P (REGNO (operands[0]))
3467 && GET_CODE (operands[1]) == CONST_INT
3468 && ((INTVAL (operands[1]) < 0
3469 && INTVAL (operands[1]) >= -0x10)
3470 || (INTVAL (operands[1]) >= 32 * 8
3471 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3472 || (INTVAL (operands[1]) >= 0
3473 && INTVAL (operands[1]) < 32 * 8
3474 && (INTVAL (operands[1]) & 7) != 0))"
3475 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3476 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3478 HOST_WIDE_INT val = INTVAL (operands[1]);
3481 operands[2] = const0_rtx;
3482 else if (val >= 32 * 8)
3486 operands[1] = GEN_INT (0x8 + off);
3487 operands[2] = GEN_INT (val - off - 0x8);
3493 operands[1] = GEN_INT (off);
3494 operands[2] = GEN_INT (val - off);
3498 ;; 32-bit Integer moves
3500 ;; Unlike most other insns, the move insns can't be split with
3501 ;; different predicates, because register spilling and other parts of
3502 ;; the compiler, have memoized the insn number already.
3504 (define_expand "movsi"
3505 [(set (match_operand:SI 0 "")
3506 (match_operand:SI 1 ""))]
3509 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3513 ;; The difference between these two is whether or not ints are allowed
3514 ;; in FP registers (off by default, use -mdebugh to enable).
3516 (define_insn "*movsi_internal"
3517 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3518 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
3520 && (register_operand (operands[0], SImode)
3521 || reg_or_0_operand (operands[1], SImode))"
3522 { return mips_output_move (operands[0], operands[1]); }
3523 [(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
3524 (set_attr "mode" "SI")
3525 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
3527 (define_insn "*movsi_mips16"
3528 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
3529 (match_operand:SI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))]
3531 && (register_operand (operands[0], SImode)
3532 || register_operand (operands[1], SImode))"
3533 { return mips_output_move (operands[0], operands[1]); }
3534 [(set_attr "type" "move,move,move,arith,arith,load,const,load,store")
3535 (set_attr "mode" "SI")
3536 (set_attr_alternative "length"
3540 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3543 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3549 (const_string "*")])])
3551 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3552 ;; when the original load is a 4 byte instruction but the add and the
3553 ;; load are 2 2 byte instructions.
3556 [(set (match_operand:SI 0 "register_operand")
3557 (mem:SI (plus:SI (match_dup 0)
3558 (match_operand:SI 1 "const_int_operand"))))]
3559 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3560 && REG_P (operands[0])
3561 && M16_REG_P (REGNO (operands[0]))
3562 && GET_CODE (operands[1]) == CONST_INT
3563 && ((INTVAL (operands[1]) < 0
3564 && INTVAL (operands[1]) >= -0x80)
3565 || (INTVAL (operands[1]) >= 32 * 4
3566 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3567 || (INTVAL (operands[1]) >= 0
3568 && INTVAL (operands[1]) < 32 * 4
3569 && (INTVAL (operands[1]) & 3) != 0))"
3570 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3571 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3573 HOST_WIDE_INT val = INTVAL (operands[1]);
3576 operands[2] = const0_rtx;
3577 else if (val >= 32 * 4)
3581 operands[1] = GEN_INT (0x7c + off);
3582 operands[2] = GEN_INT (val - off - 0x7c);
3588 operands[1] = GEN_INT (off);
3589 operands[2] = GEN_INT (val - off);
3593 ;; On the mips16, we can split a load of certain constants into a load
3594 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3598 [(set (match_operand:SI 0 "register_operand")
3599 (match_operand:SI 1 "const_int_operand"))]
3600 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3601 && REG_P (operands[0])
3602 && M16_REG_P (REGNO (operands[0]))
3603 && GET_CODE (operands[1]) == CONST_INT
3604 && INTVAL (operands[1]) >= 0x100
3605 && INTVAL (operands[1]) <= 0xff + 0x7f"
3606 [(set (match_dup 0) (match_dup 1))
3607 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3609 int val = INTVAL (operands[1]);
3611 operands[1] = GEN_INT (0xff);
3612 operands[2] = GEN_INT (val - 0xff);
3615 ;; This insn handles moving CCmode values. It's really just a
3616 ;; slightly simplified copy of movsi_internal2, with additional cases
3617 ;; to move a condition register to a general register and to move
3618 ;; between the general registers and the floating point registers.
3620 (define_insn "movcc"
3621 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3622 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3623 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3624 { return mips_output_move (operands[0], operands[1]); }
3625 [(set_attr "type" "multi,move,load,store,mfc,mtc,fmove,fpload,fpstore")
3626 (set_attr "mode" "SI")
3627 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3629 ;; Reload condition code registers. reload_incc and reload_outcc
3630 ;; both handle moves from arbitrary operands into condition code
3631 ;; registers. reload_incc handles the more common case in which
3632 ;; a source operand is constrained to be in a condition-code
3633 ;; register, but has not been allocated to one.
3635 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3636 ;; constraints do not include 'z'. reload_outcc handles the case
3637 ;; when such an operand is allocated to a condition-code register.
3639 ;; Note that reloads from a condition code register to some
3640 ;; other location can be done using ordinary moves. Moving
3641 ;; into a GPR takes a single movcc, moving elsewhere takes
3642 ;; two. We can leave these cases to the generic reload code.
3643 (define_expand "reload_incc"
3644 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3645 (match_operand:CC 1 "general_operand" ""))
3646 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3647 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3649 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3653 (define_expand "reload_outcc"
3654 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3655 (match_operand:CC 1 "register_operand" ""))
3656 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3657 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3659 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3663 ;; MIPS4 supports loading and storing a floating point register from
3664 ;; the sum of two general registers. We use two versions for each of
3665 ;; these four instructions: one where the two general registers are
3666 ;; SImode, and one where they are DImode. This is because general
3667 ;; registers will be in SImode when they hold 32-bit values, but,
3668 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
3669 ;; instructions will still work correctly.
3671 ;; ??? Perhaps it would be better to support these instructions by
3672 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3673 ;; these instructions can only be used to load and store floating
3674 ;; point registers, that would probably cause trouble in reload.
3676 (define_insn "*<ANYF:loadx>_<P:mode>"
3677 [(set (match_operand:ANYF 0 "register_operand" "=f")
3678 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3679 (match_operand:P 2 "register_operand" "d"))))]
3681 "<ANYF:loadx>\t%0,%1(%2)"
3682 [(set_attr "type" "fpidxload")
3683 (set_attr "mode" "<ANYF:UNITMODE>")])
3685 (define_insn "*<ANYF:storex>_<P:mode>"
3686 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3687 (match_operand:P 2 "register_operand" "d")))
3688 (match_operand:ANYF 0 "register_operand" "f"))]
3690 "<ANYF:storex>\t%0,%1(%2)"
3691 [(set_attr "type" "fpidxstore")
3692 (set_attr "mode" "<ANYF:UNITMODE>")])
3694 ;; Scaled indexed address load.
3695 ;; Per md.texi, we only need to look for a pattern with multiply in the
3696 ;; address expression, not shift.
3698 (define_insn "*lwxs"
3699 [(set (match_operand:SI 0 "register_operand" "=d")
3700 (mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
3702 (match_operand:SI 2 "register_operand" "d"))))]
3705 [(set_attr "type" "load")
3706 (set_attr "mode" "SI")
3707 (set_attr "length" "4")])
3709 ;; 16-bit Integer moves
3711 ;; Unlike most other insns, the move insns can't be split with
3712 ;; different predicates, because register spilling and other parts of
3713 ;; the compiler, have memoized the insn number already.
3714 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3716 (define_expand "movhi"
3717 [(set (match_operand:HI 0 "")
3718 (match_operand:HI 1 ""))]
3721 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3725 (define_insn "*movhi_internal"
3726 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3727 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3729 && (register_operand (operands[0], HImode)
3730 || reg_or_0_operand (operands[1], HImode))"
3740 [(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
3741 (set_attr "mode" "HI")
3742 (set_attr "length" "4,4,*,*,4,4,4,4")])
3744 (define_insn "*movhi_mips16"
3745 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3746 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3748 && (register_operand (operands[0], HImode)
3749 || register_operand (operands[1], HImode))"
3758 [(set_attr "type" "move,move,move,arith,arith,load,store")
3759 (set_attr "mode" "HI")
3760 (set_attr_alternative "length"
3764 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3767 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3771 (const_string "*")])])
3774 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3775 ;; when the original load is a 4 byte instruction but the add and the
3776 ;; load are 2 2 byte instructions.
3779 [(set (match_operand:HI 0 "register_operand")
3780 (mem:HI (plus:SI (match_dup 0)
3781 (match_operand:SI 1 "const_int_operand"))))]
3782 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3783 && REG_P (operands[0])
3784 && M16_REG_P (REGNO (operands[0]))
3785 && GET_CODE (operands[1]) == CONST_INT
3786 && ((INTVAL (operands[1]) < 0
3787 && INTVAL (operands[1]) >= -0x80)
3788 || (INTVAL (operands[1]) >= 32 * 2
3789 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3790 || (INTVAL (operands[1]) >= 0
3791 && INTVAL (operands[1]) < 32 * 2
3792 && (INTVAL (operands[1]) & 1) != 0))"
3793 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3794 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3796 HOST_WIDE_INT val = INTVAL (operands[1]);
3799 operands[2] = const0_rtx;
3800 else if (val >= 32 * 2)
3804 operands[1] = GEN_INT (0x7e + off);
3805 operands[2] = GEN_INT (val - off - 0x7e);
3811 operands[1] = GEN_INT (off);
3812 operands[2] = GEN_INT (val - off);
3816 ;; 8-bit Integer moves
3818 ;; Unlike most other insns, the move insns can't be split with
3819 ;; different predicates, because register spilling and other parts of
3820 ;; the compiler, have memoized the insn number already.
3821 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3823 (define_expand "movqi"
3824 [(set (match_operand:QI 0 "")
3825 (match_operand:QI 1 ""))]
3828 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3832 (define_insn "*movqi_internal"
3833 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3834 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3836 && (register_operand (operands[0], QImode)
3837 || reg_or_0_operand (operands[1], QImode))"
3847 [(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
3848 (set_attr "mode" "QI")
3849 (set_attr "length" "4,4,*,*,4,4,4,4")])
3851 (define_insn "*movqi_mips16"
3852 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3853 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3855 && (register_operand (operands[0], QImode)
3856 || register_operand (operands[1], QImode))"
3865 [(set_attr "type" "move,move,move,arith,arith,load,store")
3866 (set_attr "mode" "QI")
3867 (set_attr "length" "4,4,4,4,8,*,*")])
3869 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3870 ;; when the original load is a 4 byte instruction but the add and the
3871 ;; load are 2 2 byte instructions.
3874 [(set (match_operand:QI 0 "register_operand")
3875 (mem:QI (plus:SI (match_dup 0)
3876 (match_operand:SI 1 "const_int_operand"))))]
3877 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3878 && REG_P (operands[0])
3879 && M16_REG_P (REGNO (operands[0]))
3880 && GET_CODE (operands[1]) == CONST_INT
3881 && ((INTVAL (operands[1]) < 0
3882 && INTVAL (operands[1]) >= -0x80)
3883 || (INTVAL (operands[1]) >= 32
3884 && INTVAL (operands[1]) <= 31 + 0x7f))"
3885 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3886 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3888 HOST_WIDE_INT val = INTVAL (operands[1]);
3891 operands[2] = const0_rtx;
3894 operands[1] = GEN_INT (0x7f);
3895 operands[2] = GEN_INT (val - 0x7f);
3899 ;; 32-bit floating point moves
3901 (define_expand "movsf"
3902 [(set (match_operand:SF 0 "")
3903 (match_operand:SF 1 ""))]
3906 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3910 (define_insn "*movsf_hardfloat"
3911 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3912 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3914 && (register_operand (operands[0], SFmode)
3915 || reg_or_0_operand (operands[1], SFmode))"
3916 { return mips_output_move (operands[0], operands[1]); }
3917 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3918 (set_attr "mode" "SF")
3919 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3921 (define_insn "*movsf_softfloat"
3922 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3923 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3924 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3925 && (register_operand (operands[0], SFmode)
3926 || reg_or_0_operand (operands[1], SFmode))"
3927 { return mips_output_move (operands[0], operands[1]); }
3928 [(set_attr "type" "move,load,store")
3929 (set_attr "mode" "SF")
3930 (set_attr "length" "4,*,*")])
3932 (define_insn "*movsf_mips16"
3933 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
3934 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
3936 && (register_operand (operands[0], SFmode)
3937 || register_operand (operands[1], SFmode))"
3938 { return mips_output_move (operands[0], operands[1]); }
3939 [(set_attr "type" "move,move,move,load,store")
3940 (set_attr "mode" "SF")
3941 (set_attr "length" "4,4,4,*,*")])
3944 ;; 64-bit floating point moves
3946 (define_expand "movdf"
3947 [(set (match_operand:DF 0 "")
3948 (match_operand:DF 1 ""))]
3951 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
3955 (define_insn "*movdf_hardfloat_64bit"
3956 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3957 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3958 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
3959 && (register_operand (operands[0], DFmode)
3960 || reg_or_0_operand (operands[1], DFmode))"
3961 { return mips_output_move (operands[0], operands[1]); }
3962 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3963 (set_attr "mode" "DF")
3964 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3966 ;; This pattern applies to both !TARGET_FLOAT64 and TARGET_FLOAT64.
3967 (define_insn "*movdf_hardfloat_32bit"
3968 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3969 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3970 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
3971 && (register_operand (operands[0], DFmode)
3972 || reg_or_0_operand (operands[1], DFmode))"
3973 { return mips_output_move (operands[0], operands[1]); }
3974 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3975 (set_attr "mode" "DF")
3976 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
3978 (define_insn "*movdf_softfloat"
3979 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
3980 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
3981 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
3982 && (register_operand (operands[0], DFmode)
3983 || reg_or_0_operand (operands[1], DFmode))"
3984 { return mips_output_move (operands[0], operands[1]); }
3985 [(set_attr "type" "multi,load,store,mfc,mtc,fmove")
3986 (set_attr "mode" "DF")
3987 (set_attr "length" "8,*,*,4,4,4")])
3989 (define_insn "*movdf_mips16"
3990 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
3991 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
3993 && (register_operand (operands[0], DFmode)
3994 || register_operand (operands[1], DFmode))"
3995 { return mips_output_move (operands[0], operands[1]); }
3996 [(set_attr "type" "multi,multi,multi,load,store")
3997 (set_attr "mode" "DF")
3998 (set_attr "length" "8,8,8,*,*")])
4001 [(set (match_operand:DI 0 "nonimmediate_operand")
4002 (match_operand:DI 1 "move_operand"))]
4003 "reload_completed && !TARGET_64BIT
4004 && mips_split_64bit_move_p (operands[0], operands[1])"
4007 mips_split_64bit_move (operands[0], operands[1]);
4012 [(set (match_operand:DF 0 "nonimmediate_operand")
4013 (match_operand:DF 1 "move_operand"))]
4014 "reload_completed && !TARGET_64BIT
4015 && mips_split_64bit_move_p (operands[0], operands[1])"
4018 mips_split_64bit_move (operands[0], operands[1]);
4022 ;; When generating mips16 code, split moves of negative constants into
4023 ;; a positive "li" followed by a negation.
4025 [(set (match_operand 0 "register_operand")
4026 (match_operand 1 "const_int_operand"))]
4027 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4031 (neg:SI (match_dup 2)))]
4033 operands[2] = gen_lowpart (SImode, operands[0]);
4034 operands[3] = GEN_INT (-INTVAL (operands[1]));
4037 ;; 64-bit paired-single floating point moves
4039 (define_expand "movv2sf"
4040 [(set (match_operand:V2SF 0)
4041 (match_operand:V2SF 1))]
4042 "TARGET_PAIRED_SINGLE_FLOAT"
4044 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4048 (define_insn "movv2sf_hardfloat_64bit"
4049 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4050 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4051 "TARGET_PAIRED_SINGLE_FLOAT
4053 && (register_operand (operands[0], V2SFmode)
4054 || reg_or_0_operand (operands[1], V2SFmode))"
4055 { return mips_output_move (operands[0], operands[1]); }
4056 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4057 (set_attr "mode" "SF")
4058 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
4060 ;; The HI and LO registers are not truly independent. If we move an mthi
4061 ;; instruction before an mflo instruction, it will make the result of the
4062 ;; mflo unpredictable. The same goes for mtlo and mfhi.
4064 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
4065 ;; Operand 1 is the register we want, operand 2 is the other one.
4067 ;; When generating VR4120 or VR4130 code, we use macc{,hi} and
4068 ;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
4069 ;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
4071 (define_expand "mfhilo_<mode>"
4072 [(set (match_operand:GPR 0 "register_operand")
4073 (unspec:GPR [(match_operand:GPR 1 "register_operand")
4074 (match_operand:GPR 2 "register_operand")]
4077 (define_insn "*mfhilo_<mode>"
4078 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4079 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4080 (match_operand:GPR 2 "register_operand" "l,h")]
4084 [(set_attr "type" "mfhilo")
4085 (set_attr "mode" "<MODE>")])
4087 (define_insn "*mfhilo_<mode>_macc"
4088 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4089 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4090 (match_operand:GPR 2 "register_operand" "l,h")]
4096 [(set_attr "type" "mfhilo")
4097 (set_attr "mode" "<MODE>")])
4099 ;; Patterns for loading or storing part of a paired floating point
4100 ;; register. We need them because odd-numbered floating-point registers
4101 ;; are not fully independent: see mips_split_64bit_move.
4103 ;; Load the low word of operand 0 with operand 1.
4104 (define_insn "load_df_low"
4105 [(set (match_operand:DF 0 "register_operand" "=f,f")
4106 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
4107 UNSPEC_LOAD_DF_LOW))]
4108 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4110 operands[0] = mips_subword (operands[0], 0);
4111 return mips_output_move (operands[0], operands[1]);
4113 [(set_attr "type" "mtc,fpload")
4114 (set_attr "mode" "SF")])
4116 ;; Load the high word of operand 0 from operand 1, preserving the value
4118 (define_insn "load_df_high"
4119 [(set (match_operand:DF 0 "register_operand" "=f,f")
4120 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
4121 (match_operand:DF 2 "register_operand" "0,0")]
4122 UNSPEC_LOAD_DF_HIGH))]
4123 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4125 operands[0] = mips_subword (operands[0], 1);
4126 return mips_output_move (operands[0], operands[1]);
4128 [(set_attr "type" "mtc,fpload")
4129 (set_attr "mode" "SF")])
4131 ;; Store the high word of operand 1 in operand 0. The corresponding
4132 ;; low-word move is done in the normal way.
4133 (define_insn "store_df_high"
4134 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
4135 (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
4136 UNSPEC_STORE_DF_HIGH))]
4137 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4139 operands[1] = mips_subword (operands[1], 1);
4140 return mips_output_move (operands[0], operands[1]);
4142 [(set_attr "type" "mfc,fpstore")
4143 (set_attr "mode" "SF")])
4145 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4146 ;; value in the low word.
4147 (define_insn "mthc1"
4148 [(set (match_operand:DF 0 "register_operand" "=f")
4149 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ")
4150 (match_operand:DF 2 "register_operand" "0")]
4152 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4154 [(set_attr "type" "mtc")
4155 (set_attr "mode" "SF")])
4157 ;; Move high word of operand 1 to operand 0 using mfhc1. The corresponding
4158 ;; low-word move is done in the normal way.
4159 (define_insn "mfhc1"
4160 [(set (match_operand:SI 0 "register_operand" "=d")
4161 (unspec:SI [(match_operand:DF 1 "register_operand" "f")]
4163 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4165 [(set_attr "type" "mfc")
4166 (set_attr "mode" "SF")])
4168 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4169 (define_expand "load_const_gp"
4170 [(set (match_operand 0 "register_operand" "=d")
4171 (const (unspec [(const_int 0)] UNSPEC_GP)))])
4173 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4174 ;; of _gp from the start of this function. Operand 1 is the incoming
4175 ;; function address.
4176 (define_insn_and_split "loadgp_newabi"
4177 [(unspec_volatile [(match_operand 0 "" "")
4178 (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
4179 "mips_current_loadgp_style () == LOADGP_NEWABI"
4182 [(set (match_dup 2) (match_dup 3))
4183 (set (match_dup 2) (match_dup 4))
4184 (set (match_dup 2) (match_dup 5))]
4186 operands[2] = pic_offset_table_rtx;
4187 operands[3] = gen_rtx_HIGH (Pmode, operands[0]);
4188 operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]);
4189 operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]);
4191 [(set_attr "length" "12")])
4193 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4194 (define_insn_and_split "loadgp_absolute"
4195 [(unspec_volatile [(match_operand 0 "" "")] UNSPEC_LOADGP)]
4196 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4201 mips_emit_move (pic_offset_table_rtx, operands[0]);
4204 [(set_attr "length" "8")])
4206 ;; The use of gp is hidden when not using explicit relocations.
4207 ;; This blockage instruction prevents the gp load from being
4208 ;; scheduled after an implicit use of gp. It also prevents
4209 ;; the load from being deleted as dead.
4210 (define_insn "loadgp_blockage"
4211 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
4214 [(set_attr "type" "unknown")
4215 (set_attr "mode" "none")
4216 (set_attr "length" "0")])
4218 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4219 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4220 (define_insn "loadgp_rtp"
4221 [(unspec_volatile [(match_operand 0 "symbol_ref_operand")
4222 (match_operand 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4223 "mips_current_loadgp_style () == LOADGP_RTP"
4225 [(set_attr "length" "12")])
4228 [(unspec_volatile [(match_operand:P 0 "symbol_ref_operand")
4229 (match_operand:P 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4230 "mips_current_loadgp_style () == LOADGP_RTP"
4231 [(set (match_dup 2) (high:P (match_dup 3)))
4232 (set (match_dup 2) (unspec:P [(match_dup 2)
4233 (match_dup 3)] UNSPEC_LOAD_GOT))
4234 (set (match_dup 2) (unspec:P [(match_dup 2)
4235 (match_dup 4)] UNSPEC_LOAD_GOT))]
4237 operands[2] = pic_offset_table_rtx;
4238 operands[3] = mips_unspec_address (operands[0], SYMBOL_ABSOLUTE);
4239 operands[4] = mips_unspec_address (operands[1], SYMBOL_HALF);
4242 ;; Emit a .cprestore directive, which normally expands to a single store
4243 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4244 ;; code so that jals inside inline asms will work correctly.
4245 (define_insn "cprestore"
4246 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
4251 if (set_nomacro && which_alternative == 1)
4252 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4254 return ".cprestore\t%0";
4256 [(set_attr "type" "store")
4257 (set_attr "length" "4,12")])
4259 ;; Expand in-line code to clear the instruction cache between operand[0] and
4261 (define_expand "clear_cache"
4262 [(match_operand 0 "pmode_register_operand")
4263 (match_operand 1 "pmode_register_operand")]
4269 mips_expand_synci_loop (operands[0], operands[1]);
4270 emit_insn (gen_sync ());
4271 emit_insn (gen_clear_hazard ());
4273 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4275 rtx len = gen_reg_rtx (Pmode);
4276 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4277 /* Flush both caches. We need to flush the data cache in case
4278 the system has a write-back cache. */
4279 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func),
4280 0, VOIDmode, 3, operands[0], Pmode, len, Pmode,
4281 GEN_INT (3), TYPE_MODE (integer_type_node));
4287 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4291 (define_insn "synci"
4292 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4297 (define_insn "rdhwr"
4298 [(set (match_operand:SI 0 "register_operand" "=d")
4299 (unspec_volatile [(match_operand:SI 1 "const_int_operand" "n")]
4304 (define_insn "clear_hazard"
4305 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4306 (clobber (reg:SI 31))]
4309 return ".set\tpush\n"
4310 "\t.set\tnoreorder\n"
4314 "1:\taddiu\t$31,$31,12\n"
4319 [(set_attr "length" "20")])
4321 ;; Atomic memory operations.
4323 (define_insn "memory_barrier"
4324 [(set (mem:BLK (scratch))
4325 (unspec:BLK [(const_int 0)] UNSPEC_MEMORY_BARRIER))]
4329 (define_insn "sync_compare_and_swap<mode>"
4330 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4331 (match_operand:GPR 1 "memory_operand" "+R,R"))
4333 (unspec_volatile:GPR [(match_operand:GPR 2 "register_operand" "d,d")
4334 (match_operand:GPR 3 "arith_operand" "I,d")]
4335 UNSPEC_COMPARE_AND_SWAP))]
4338 if (which_alternative == 0)
4339 return MIPS_COMPARE_AND_SWAP ("<d>", "li");
4341 return MIPS_COMPARE_AND_SWAP ("<d>", "move");
4343 [(set_attr "length" "28")])
4345 (define_insn "sync_add<mode>"
4346 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4347 (unspec_volatile:GPR
4348 [(plus:GPR (match_dup 0)
4349 (match_operand:GPR 1 "arith_operand" "I,d"))]
4350 UNSPEC_SYNC_OLD_OP))]
4353 if (which_alternative == 0)
4354 return MIPS_SYNC_OP ("<d>", "<d>addiu");
4356 return MIPS_SYNC_OP ("<d>", "<d>addu");
4358 [(set_attr "length" "24")])
4360 (define_insn "sync_sub<mode>"
4361 [(set (match_operand:GPR 0 "memory_operand" "+R")
4362 (unspec_volatile:GPR
4363 [(minus:GPR (match_dup 0)
4364 (match_operand:GPR 1 "register_operand" "d"))]
4365 UNSPEC_SYNC_OLD_OP))]
4368 return MIPS_SYNC_OP ("<d>", "<d>subu");
4370 [(set_attr "length" "24")])
4372 (define_insn "sync_old_add<mode>"
4373 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4374 (match_operand:GPR 1 "memory_operand" "+R,R"))
4376 (unspec_volatile:GPR
4377 [(plus:GPR (match_dup 1)
4378 (match_operand:GPR 2 "arith_operand" "I,d"))]
4379 UNSPEC_SYNC_OLD_OP))]
4382 if (which_alternative == 0)
4383 return MIPS_SYNC_OLD_OP ("<d>", "<d>addiu");
4385 return MIPS_SYNC_OLD_OP ("<d>", "<d>addu");
4387 [(set_attr "length" "24")])
4389 (define_insn "sync_old_sub<mode>"
4390 [(set (match_operand:GPR 0 "register_operand" "=&d")
4391 (match_operand:GPR 1 "memory_operand" "+R"))
4393 (unspec_volatile:GPR
4394 [(minus:GPR (match_dup 1)
4395 (match_operand:GPR 2 "register_operand" "d"))]
4396 UNSPEC_SYNC_OLD_OP))]
4399 return MIPS_SYNC_OLD_OP ("<d>", "<d>subu");
4401 [(set_attr "length" "24")])
4403 (define_insn "sync_new_add<mode>"
4404 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4405 (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
4406 (match_operand:GPR 2 "arith_operand" "I,d")))
4408 (unspec_volatile:GPR
4409 [(plus:GPR (match_dup 1) (match_dup 2))]
4410 UNSPEC_SYNC_NEW_OP))]
4413 if (which_alternative == 0)
4414 return MIPS_SYNC_NEW_OP ("<d>", "<d>addiu");
4416 return MIPS_SYNC_NEW_OP ("<d>", "<d>addu");
4418 [(set_attr "length" "24")])
4420 (define_insn "sync_new_sub<mode>"
4421 [(set (match_operand:GPR 0 "register_operand" "=&d")
4422 (minus:GPR (match_operand:GPR 1 "memory_operand" "+R")
4423 (match_operand:GPR 2 "register_operand" "d")))
4425 (unspec_volatile:GPR
4426 [(minus:GPR (match_dup 1) (match_dup 2))]
4427 UNSPEC_SYNC_NEW_OP))]
4430 return MIPS_SYNC_NEW_OP ("<d>", "<d>subu");
4432 [(set_attr "length" "24")])
4434 (define_insn "sync_<optab><mode>"
4435 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4436 (unspec_volatile:GPR
4437 [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
4439 UNSPEC_SYNC_OLD_OP))]
4442 if (which_alternative == 0)
4443 return MIPS_SYNC_OP ("<d>", "<immediate_insn>");
4445 return MIPS_SYNC_OP ("<d>", "<insn>");
4447 [(set_attr "length" "24")])
4449 (define_insn "sync_old_<optab><mode>"
4450 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4451 (match_operand:GPR 1 "memory_operand" "+R,R"))
4453 (unspec_volatile:GPR
4454 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
4456 UNSPEC_SYNC_OLD_OP))]
4459 if (which_alternative == 0)
4460 return MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>");
4462 return MIPS_SYNC_OLD_OP ("<d>", "<insn>");
4464 [(set_attr "length" "24")])
4466 (define_insn "sync_new_<optab><mode>"
4467 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4468 (match_operand:GPR 1 "memory_operand" "+R,R"))
4470 (unspec_volatile:GPR
4471 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
4473 UNSPEC_SYNC_NEW_OP))]
4476 if (which_alternative == 0)
4477 return MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>");
4479 return MIPS_SYNC_NEW_OP ("<d>", "<insn>");
4481 [(set_attr "length" "24")])
4483 (define_insn "sync_nand<mode>"
4484 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4485 (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
4486 UNSPEC_SYNC_OLD_OP))]
4489 if (which_alternative == 0)
4490 return MIPS_SYNC_NAND ("<d>", "andi");
4492 return MIPS_SYNC_NAND ("<d>", "and");
4494 [(set_attr "length" "28")])
4496 (define_insn "sync_old_nand<mode>"
4497 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4498 (match_operand:GPR 1 "memory_operand" "+R,R"))
4500 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
4501 UNSPEC_SYNC_OLD_OP))]
4504 if (which_alternative == 0)
4505 return MIPS_SYNC_OLD_NAND ("<d>", "andi");
4507 return MIPS_SYNC_OLD_NAND ("<d>", "and");
4509 [(set_attr "length" "28")])
4511 (define_insn "sync_new_nand<mode>"
4512 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4513 (match_operand:GPR 1 "memory_operand" "+R,R"))
4515 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
4516 UNSPEC_SYNC_NEW_OP))]
4519 if (which_alternative == 0)
4520 return MIPS_SYNC_NEW_NAND ("<d>", "andi");
4522 return MIPS_SYNC_NEW_NAND ("<d>", "and");
4524 [(set_attr "length" "28")])
4526 (define_insn "sync_lock_test_and_set<mode>"
4527 [(set (match_operand:GPR 0 "register_operand" "=&d,d")
4528 (match_operand:GPR 1 "memory_operand" "+R,R"))
4530 (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
4531 UNSPEC_SYNC_EXCHANGE))]
4534 if (which_alternative == 0)
4535 return MIPS_SYNC_EXCHANGE ("<d>", "li");
4537 return MIPS_SYNC_EXCHANGE ("<d>", "move");
4539 [(set_attr "length" "24")])
4541 ;; Block moves, see mips.c for more details.
4542 ;; Argument 0 is the destination
4543 ;; Argument 1 is the source
4544 ;; Argument 2 is the length
4545 ;; Argument 3 is the alignment
4547 (define_expand "movmemsi"
4548 [(parallel [(set (match_operand:BLK 0 "general_operand")
4549 (match_operand:BLK 1 "general_operand"))
4550 (use (match_operand:SI 2 ""))
4551 (use (match_operand:SI 3 "const_int_operand"))])]
4552 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4554 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4561 ;; ....................
4565 ;; ....................
4567 (define_expand "<optab><mode>3"
4568 [(set (match_operand:GPR 0 "register_operand")
4569 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4570 (match_operand:SI 2 "arith_operand")))]
4573 /* On the mips16, a shift of more than 8 is a four byte instruction,
4574 so, for a shift between 8 and 16, it is just as fast to do two
4575 shifts of 8 or less. If there is a lot of shifting going on, we
4576 may win in CSE. Otherwise combine will put the shifts back
4577 together again. This can be called by function_arg, so we must
4578 be careful not to allocate a new register if we've reached the
4582 && GET_CODE (operands[2]) == CONST_INT
4583 && INTVAL (operands[2]) > 8
4584 && INTVAL (operands[2]) <= 16
4585 && !reload_in_progress
4586 && !reload_completed)
4588 rtx temp = gen_reg_rtx (<MODE>mode);
4590 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4591 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4592 GEN_INT (INTVAL (operands[2]) - 8)));
4597 (define_insn "*<optab><mode>3"
4598 [(set (match_operand:GPR 0 "register_operand" "=d")
4599 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4600 (match_operand:SI 2 "arith_operand" "dI")))]
4603 if (GET_CODE (operands[2]) == CONST_INT)
4604 operands[2] = GEN_INT (INTVAL (operands[2])
4605 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4607 return "<d><insn>\t%0,%1,%2";
4609 [(set_attr "type" "shift")
4610 (set_attr "mode" "<MODE>")])
4612 (define_insn "*<optab>si3_extend"
4613 [(set (match_operand:DI 0 "register_operand" "=d")
4615 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4616 (match_operand:SI 2 "arith_operand" "dI"))))]
4617 "TARGET_64BIT && !TARGET_MIPS16"
4619 if (GET_CODE (operands[2]) == CONST_INT)
4620 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4622 return "<insn>\t%0,%1,%2";
4624 [(set_attr "type" "shift")
4625 (set_attr "mode" "SI")])
4627 (define_insn "*<optab>si3_mips16"
4628 [(set (match_operand:SI 0 "register_operand" "=d,d")
4629 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4630 (match_operand:SI 2 "arith_operand" "d,I")))]
4633 if (which_alternative == 0)
4634 return "<insn>\t%0,%2";
4636 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4637 return "<insn>\t%0,%1,%2";
4639 [(set_attr "type" "shift")
4640 (set_attr "mode" "SI")
4641 (set_attr_alternative "length"
4643 (if_then_else (match_operand 2 "m16_uimm3_b")
4647 ;; We need separate DImode MIPS16 patterns because of the irregularity
4649 (define_insn "*ashldi3_mips16"
4650 [(set (match_operand:DI 0 "register_operand" "=d,d")
4651 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4652 (match_operand:SI 2 "arith_operand" "d,I")))]
4653 "TARGET_64BIT && TARGET_MIPS16"
4655 if (which_alternative == 0)
4656 return "dsll\t%0,%2";
4658 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4659 return "dsll\t%0,%1,%2";
4661 [(set_attr "type" "shift")
4662 (set_attr "mode" "DI")
4663 (set_attr_alternative "length"
4665 (if_then_else (match_operand 2 "m16_uimm3_b")
4669 (define_insn "*ashrdi3_mips16"
4670 [(set (match_operand:DI 0 "register_operand" "=d,d")
4671 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4672 (match_operand:SI 2 "arith_operand" "d,I")))]
4673 "TARGET_64BIT && TARGET_MIPS16"
4675 if (GET_CODE (operands[2]) == CONST_INT)
4676 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4678 return "dsra\t%0,%2";
4680 [(set_attr "type" "shift")
4681 (set_attr "mode" "DI")
4682 (set_attr_alternative "length"
4684 (if_then_else (match_operand 2 "m16_uimm3_b")
4688 (define_insn "*lshrdi3_mips16"
4689 [(set (match_operand:DI 0 "register_operand" "=d,d")
4690 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4691 (match_operand:SI 2 "arith_operand" "d,I")))]
4692 "TARGET_64BIT && TARGET_MIPS16"
4694 if (GET_CODE (operands[2]) == CONST_INT)
4695 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4697 return "dsrl\t%0,%2";
4699 [(set_attr "type" "shift")
4700 (set_attr "mode" "DI")
4701 (set_attr_alternative "length"
4703 (if_then_else (match_operand 2 "m16_uimm3_b")
4707 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4710 [(set (match_operand:GPR 0 "register_operand")
4711 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4712 (match_operand:GPR 2 "const_int_operand")))]
4713 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4714 && GET_CODE (operands[2]) == CONST_INT
4715 && INTVAL (operands[2]) > 8
4716 && INTVAL (operands[2]) <= 16"
4717 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4718 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4719 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4721 ;; If we load a byte on the mips16 as a bitfield, the resulting
4722 ;; sequence of instructions is too complicated for combine, because it
4723 ;; involves four instructions: a load, a shift, a constant load into a
4724 ;; register, and an and (the key problem here is that the mips16 does
4725 ;; not have and immediate). We recognize a shift of a load in order
4726 ;; to make it simple enough for combine to understand.
4728 ;; The length here is the worst case: the length of the split version
4729 ;; will be more accurate.
4730 (define_insn_and_split ""
4731 [(set (match_operand:SI 0 "register_operand" "=d")
4732 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4733 (match_operand:SI 2 "immediate_operand" "I")))]
4737 [(set (match_dup 0) (match_dup 1))
4738 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4740 [(set_attr "type" "load")
4741 (set_attr "mode" "SI")
4742 (set_attr "length" "16")])
4744 (define_insn "rotr<mode>3"
4745 [(set (match_operand:GPR 0 "register_operand" "=d")
4746 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4747 (match_operand:SI 2 "arith_operand" "dI")))]
4750 if (GET_CODE (operands[2]) == CONST_INT)
4751 gcc_assert (INTVAL (operands[2]) >= 0
4752 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4754 return "<d>ror\t%0,%1,%2";
4756 [(set_attr "type" "shift")
4757 (set_attr "mode" "<MODE>")])
4760 ;; ....................
4764 ;; ....................
4766 ;; Flow here is rather complex:
4768 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4769 ;; into cmp_operands[] but generates no RTL.
4771 ;; 2) The appropriate branch define_expand is called, which then
4772 ;; creates the appropriate RTL for the comparison and branch.
4773 ;; Different CC modes are used, based on what type of branch is
4774 ;; done, so that we can constrain things appropriately. There
4775 ;; are assumptions in the rest of GCC that break if we fold the
4776 ;; operands into the branches for integer operations, and use cc0
4777 ;; for floating point, so we use the fp status register instead.
4778 ;; If needed, an appropriate temporary is created to hold the
4779 ;; of the integer compare.
4781 (define_expand "cmp<mode>"
4783 (compare:CC (match_operand:GPR 0 "register_operand")
4784 (match_operand:GPR 1 "nonmemory_operand")))]
4787 cmp_operands[0] = operands[0];
4788 cmp_operands[1] = operands[1];
4792 (define_expand "cmp<mode>"
4794 (compare:CC (match_operand:SCALARF 0 "register_operand")
4795 (match_operand:SCALARF 1 "register_operand")))]
4798 cmp_operands[0] = operands[0];
4799 cmp_operands[1] = operands[1];
4804 ;; ....................
4806 ;; CONDITIONAL BRANCHES
4808 ;; ....................
4810 ;; Conditional branches on floating-point equality tests.
4812 (define_insn "*branch_fp"
4815 (match_operator 0 "equality_operator"
4816 [(match_operand:CC 2 "register_operand" "z")
4818 (label_ref (match_operand 1 "" ""))
4822 return mips_output_conditional_branch (insn, operands,
4823 MIPS_BRANCH ("b%F0", "%Z2%1"),
4824 MIPS_BRANCH ("b%W0", "%Z2%1"));
4826 [(set_attr "type" "branch")
4827 (set_attr "mode" "none")])
4829 (define_insn "*branch_fp_inverted"
4832 (match_operator 0 "equality_operator"
4833 [(match_operand:CC 2 "register_operand" "z")
4836 (label_ref (match_operand 1 "" ""))))]
4839 return mips_output_conditional_branch (insn, operands,
4840 MIPS_BRANCH ("b%W0", "%Z2%1"),
4841 MIPS_BRANCH ("b%F0", "%Z2%1"));
4843 [(set_attr "type" "branch")
4844 (set_attr "mode" "none")])
4846 ;; Conditional branches on ordered comparisons with zero.
4848 (define_insn "*branch_order<mode>"
4851 (match_operator 0 "order_operator"
4852 [(match_operand:GPR 2 "register_operand" "d")
4854 (label_ref (match_operand 1 "" ""))
4857 { return mips_output_order_conditional_branch (insn, operands, false); }
4858 [(set_attr "type" "branch")
4859 (set_attr "mode" "none")])
4861 (define_insn "*branch_order<mode>_inverted"
4864 (match_operator 0 "order_operator"
4865 [(match_operand:GPR 2 "register_operand" "d")
4868 (label_ref (match_operand 1 "" ""))))]
4870 { return mips_output_order_conditional_branch (insn, operands, true); }
4871 [(set_attr "type" "branch")
4872 (set_attr "mode" "none")])
4874 ;; Conditional branch on equality comparison.
4876 (define_insn "*branch_equality<mode>"
4879 (match_operator 0 "equality_operator"
4880 [(match_operand:GPR 2 "register_operand" "d")
4881 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4882 (label_ref (match_operand 1 "" ""))
4886 return mips_output_conditional_branch (insn, operands,
4887 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
4888 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
4890 [(set_attr "type" "branch")
4891 (set_attr "mode" "none")])
4893 (define_insn "*branch_equality<mode>_inverted"
4896 (match_operator 0 "equality_operator"
4897 [(match_operand:GPR 2 "register_operand" "d")
4898 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4900 (label_ref (match_operand 1 "" ""))))]
4903 return mips_output_conditional_branch (insn, operands,
4904 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
4905 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
4907 [(set_attr "type" "branch")
4908 (set_attr "mode" "none")])
4912 (define_insn "*branch_equality<mode>_mips16"
4915 (match_operator 0 "equality_operator"
4916 [(match_operand:GPR 1 "register_operand" "d,t")
4918 (match_operand 2 "pc_or_label_operand" "")
4919 (match_operand 3 "pc_or_label_operand" "")))]
4922 if (operands[2] != pc_rtx)
4924 if (which_alternative == 0)
4925 return "b%C0z\t%1,%2";
4927 return "bt%C0z\t%2";
4931 if (which_alternative == 0)
4932 return "b%N0z\t%1,%3";
4934 return "bt%N0z\t%3";
4937 [(set_attr "type" "branch")
4938 (set_attr "mode" "none")
4939 (set_attr "length" "8")])
4941 (define_expand "b<code>"
4943 (if_then_else (any_cond:CC (cc0)
4945 (label_ref (match_operand 0 ""))
4949 gen_conditional_branch (operands, <CODE>);
4953 ;; Used to implement built-in functions.
4954 (define_expand "condjump"
4956 (if_then_else (match_operand 0)
4957 (label_ref (match_operand 1))
4961 ;; ....................
4963 ;; SETTING A REGISTER FROM A COMPARISON
4965 ;; ....................
4967 (define_expand "seq"
4968 [(set (match_operand:SI 0 "register_operand")
4969 (eq:SI (match_dup 1)
4972 { if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
4974 (define_insn "*seq_<mode>"
4975 [(set (match_operand:GPR 0 "register_operand" "=d")
4976 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4980 [(set_attr "type" "slt")
4981 (set_attr "mode" "<MODE>")])
4983 (define_insn "*seq_<mode>_mips16"
4984 [(set (match_operand:GPR 0 "register_operand" "=t")
4985 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4989 [(set_attr "type" "slt")
4990 (set_attr "mode" "<MODE>")])
4992 ;; "sne" uses sltu instructions in which the first operand is $0.
4993 ;; This isn't possible in mips16 code.
4995 (define_expand "sne"
4996 [(set (match_operand:SI 0 "register_operand")
4997 (ne:SI (match_dup 1)
5000 { if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
5002 (define_insn "*sne_<mode>"
5003 [(set (match_operand:GPR 0 "register_operand" "=d")
5004 (ne:GPR (match_operand:GPR 1 "register_operand" "d")
5008 [(set_attr "type" "slt")
5009 (set_attr "mode" "<MODE>")])
5011 (define_expand "sgt"
5012 [(set (match_operand:SI 0 "register_operand")
5013 (gt:SI (match_dup 1)
5016 { if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
5018 (define_insn "*sgt_<mode>"
5019 [(set (match_operand:GPR 0 "register_operand" "=d")
5020 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
5021 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5024 [(set_attr "type" "slt")
5025 (set_attr "mode" "<MODE>")])
5027 (define_insn "*sgt_<mode>_mips16"
5028 [(set (match_operand:GPR 0 "register_operand" "=t")
5029 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
5030 (match_operand:GPR 2 "register_operand" "d")))]
5033 [(set_attr "type" "slt")
5034 (set_attr "mode" "<MODE>")])
5036 (define_expand "sge"
5037 [(set (match_operand:SI 0 "register_operand")
5038 (ge:SI (match_dup 1)
5041 { if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
5043 (define_insn "*sge_<mode>"
5044 [(set (match_operand:GPR 0 "register_operand" "=d")
5045 (ge:GPR (match_operand:GPR 1 "register_operand" "d")
5049 [(set_attr "type" "slt")
5050 (set_attr "mode" "<MODE>")])
5052 (define_expand "slt"
5053 [(set (match_operand:SI 0 "register_operand")
5054 (lt:SI (match_dup 1)
5057 { if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
5059 (define_insn "*slt_<mode>"
5060 [(set (match_operand:GPR 0 "register_operand" "=d")
5061 (lt:GPR (match_operand:GPR 1 "register_operand" "d")
5062 (match_operand:GPR 2 "arith_operand" "dI")))]
5065 [(set_attr "type" "slt")
5066 (set_attr "mode" "<MODE>")])
5068 (define_insn "*slt_<mode>_mips16"
5069 [(set (match_operand:GPR 0 "register_operand" "=t,t")
5070 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
5071 (match_operand:GPR 2 "arith_operand" "d,I")))]
5074 [(set_attr "type" "slt")
5075 (set_attr "mode" "<MODE>")
5076 (set_attr_alternative "length"
5078 (if_then_else (match_operand 2 "m16_uimm8_1")
5082 (define_expand "sle"
5083 [(set (match_operand:SI 0 "register_operand")
5084 (le:SI (match_dup 1)
5087 { if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
5089 (define_insn "*sle_<mode>"
5090 [(set (match_operand:GPR 0 "register_operand" "=d")
5091 (le:GPR (match_operand:GPR 1 "register_operand" "d")
5092 (match_operand:GPR 2 "sle_operand" "")))]
5095 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5096 return "slt\t%0,%1,%2";
5098 [(set_attr "type" "slt")
5099 (set_attr "mode" "<MODE>")])
5101 (define_insn "*sle_<mode>_mips16"
5102 [(set (match_operand:GPR 0 "register_operand" "=t")
5103 (le:GPR (match_operand:GPR 1 "register_operand" "d")
5104 (match_operand:GPR 2 "sle_operand" "")))]
5107 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5108 return "slt\t%1,%2";
5110 [(set_attr "type" "slt")
5111 (set_attr "mode" "<MODE>")
5112 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5116 (define_expand "sgtu"
5117 [(set (match_operand:SI 0 "register_operand")
5118 (gtu:SI (match_dup 1)
5121 { if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
5123 (define_insn "*sgtu_<mode>"
5124 [(set (match_operand:GPR 0 "register_operand" "=d")
5125 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
5126 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5129 [(set_attr "type" "slt")
5130 (set_attr "mode" "<MODE>")])
5132 (define_insn "*sgtu_<mode>_mips16"
5133 [(set (match_operand:GPR 0 "register_operand" "=t")
5134 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
5135 (match_operand:GPR 2 "register_operand" "d")))]
5138 [(set_attr "type" "slt")
5139 (set_attr "mode" "<MODE>")])
5141 (define_expand "sgeu"
5142 [(set (match_operand:SI 0 "register_operand")
5143 (geu:SI (match_dup 1)
5146 { if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
5148 (define_insn "*sge_<mode>"
5149 [(set (match_operand:GPR 0 "register_operand" "=d")
5150 (geu:GPR (match_operand:GPR 1 "register_operand" "d")
5154 [(set_attr "type" "slt")
5155 (set_attr "mode" "<MODE>")])
5157 (define_expand "sltu"
5158 [(set (match_operand:SI 0 "register_operand")
5159 (ltu:SI (match_dup 1)
5162 { if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
5164 (define_insn "*sltu_<mode>"
5165 [(set (match_operand:GPR 0 "register_operand" "=d")
5166 (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
5167 (match_operand:GPR 2 "arith_operand" "dI")))]
5170 [(set_attr "type" "slt")
5171 (set_attr "mode" "<MODE>")])
5173 (define_insn "*sltu_<mode>_mips16"
5174 [(set (match_operand:GPR 0 "register_operand" "=t,t")
5175 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
5176 (match_operand:GPR 2 "arith_operand" "d,I")))]
5179 [(set_attr "type" "slt")
5180 (set_attr "mode" "<MODE>")
5181 (set_attr_alternative "length"
5183 (if_then_else (match_operand 2 "m16_uimm8_1")
5187 (define_expand "sleu"
5188 [(set (match_operand:SI 0 "register_operand")
5189 (leu:SI (match_dup 1)
5192 { if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
5194 (define_insn "*sleu_<mode>"
5195 [(set (match_operand:GPR 0 "register_operand" "=d")
5196 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
5197 (match_operand:GPR 2 "sleu_operand" "")))]
5200 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5201 return "sltu\t%0,%1,%2";
5203 [(set_attr "type" "slt")
5204 (set_attr "mode" "<MODE>")])
5206 (define_insn "*sleu_<mode>_mips16"
5207 [(set (match_operand:GPR 0 "register_operand" "=t")
5208 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
5209 (match_operand:GPR 2 "sleu_operand" "")))]
5212 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5213 return "sltu\t%1,%2";
5215 [(set_attr "type" "slt")
5216 (set_attr "mode" "<MODE>")
5217 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5222 ;; ....................
5224 ;; FLOATING POINT COMPARISONS
5226 ;; ....................
5228 (define_insn "s<code>_<mode>"
5229 [(set (match_operand:CC 0 "register_operand" "=z")
5230 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5231 (match_operand:SCALARF 2 "register_operand" "f")))]
5233 "c.<fcond>.<fmt>\t%Z0%1,%2"
5234 [(set_attr "type" "fcmp")
5235 (set_attr "mode" "FPSW")])
5237 (define_insn "s<code>_<mode>"
5238 [(set (match_operand:CC 0 "register_operand" "=z")
5239 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5240 (match_operand:SCALARF 2 "register_operand" "f")))]
5242 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5243 [(set_attr "type" "fcmp")
5244 (set_attr "mode" "FPSW")])
5247 ;; ....................
5249 ;; UNCONDITIONAL BRANCHES
5251 ;; ....................
5253 ;; Unconditional branches.
5257 (label_ref (match_operand 0 "" "")))]
5262 if (get_attr_length (insn) <= 8)
5263 return "%*b\t%l0%/";
5266 output_asm_insn (mips_output_load_label (), operands);
5267 return "%*jr\t%@%/%]";
5271 return "%*j\t%l0%/";
5273 [(set_attr "type" "jump")
5274 (set_attr "mode" "none")
5275 (set (attr "length")
5276 ;; We can't use `j' when emitting PIC. Emit a branch if it's
5277 ;; in range, otherwise load the address of the branch target into
5278 ;; $at and then jump to it.
5280 (ior (eq (symbol_ref "flag_pic") (const_int 0))
5281 (lt (abs (minus (match_dup 0)
5282 (plus (pc) (const_int 4))))
5283 (const_int 131072)))
5284 (const_int 4) (const_int 16)))])
5286 ;; We need a different insn for the mips16, because a mips16 branch
5287 ;; does not have a delay slot.
5291 (label_ref (match_operand 0 "" "")))]
5294 [(set_attr "type" "branch")
5295 (set_attr "mode" "none")
5296 (set_attr "length" "8")])
5298 (define_expand "indirect_jump"
5299 [(set (pc) (match_operand 0 "register_operand"))]
5302 operands[0] = force_reg (Pmode, operands[0]);
5303 if (Pmode == SImode)
5304 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5306 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5310 (define_insn "indirect_jump<mode>"
5311 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5314 [(set_attr "type" "jump")
5315 (set_attr "mode" "none")])
5317 (define_expand "tablejump"
5319 (match_operand 0 "register_operand"))
5320 (use (label_ref (match_operand 1 "")))]
5323 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5324 operands[0] = expand_binop (Pmode, add_optab,
5325 convert_to_mode (Pmode, operands[0], false),
5326 gen_rtx_LABEL_REF (Pmode, operands[1]),
5328 else if (TARGET_GPWORD)
5329 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5330 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5331 else if (TARGET_RTP_PIC)
5333 /* When generating RTP PIC, we use case table entries that are relative
5334 to the start of the function. Add the function's address to the
5336 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5337 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5338 start, 0, 0, OPTAB_WIDEN);
5341 if (Pmode == SImode)
5342 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5344 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5348 (define_insn "tablejump<mode>"
5350 (match_operand:P 0 "register_operand" "d"))
5351 (use (label_ref (match_operand 1 "" "")))]
5354 [(set_attr "type" "jump")
5355 (set_attr "mode" "none")])
5357 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5358 ;; While it is possible to either pull it off the stack (in the
5359 ;; o32 case) or recalculate it given t9 and our target label,
5360 ;; it takes 3 or 4 insns to do so.
5362 (define_expand "builtin_setjmp_setup"
5363 [(use (match_operand 0 "register_operand"))]
5368 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5369 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5373 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5374 ;; that older code did recalculate the gp from $25. Continue to jump through
5375 ;; $25 for compatibility (we lose nothing by doing so).
5377 (define_expand "builtin_longjmp"
5378 [(use (match_operand 0 "register_operand"))]
5381 /* The elements of the buffer are, in order: */
5382 int W = GET_MODE_SIZE (Pmode);
5383 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5384 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5385 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5386 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5387 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5388 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5389 The target is bound to be using $28 as the global pointer
5390 but the current function might not be. */
5391 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5393 /* This bit is similar to expand_builtin_longjmp except that it
5394 restores $gp as well. */
5395 mips_emit_move (hard_frame_pointer_rtx, fp);
5396 mips_emit_move (pv, lab);
5397 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5398 mips_emit_move (gp, gpv);
5399 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5400 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5401 emit_insn (gen_rtx_USE (VOIDmode, gp));
5402 emit_indirect_jump (pv);
5407 ;; ....................
5409 ;; Function prologue/epilogue
5411 ;; ....................
5414 (define_expand "prologue"
5418 mips_expand_prologue ();
5422 ;; Block any insns from being moved before this point, since the
5423 ;; profiling call to mcount can use various registers that aren't
5424 ;; saved or used to pass arguments.
5426 (define_insn "blockage"
5427 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5430 [(set_attr "type" "unknown")
5431 (set_attr "mode" "none")
5432 (set_attr "length" "0")])
5434 (define_expand "epilogue"
5438 mips_expand_epilogue (false);
5442 (define_expand "sibcall_epilogue"
5446 mips_expand_epilogue (true);
5450 ;; Trivial return. Make it look like a normal return insn as that
5451 ;; allows jump optimizations to work better.
5453 (define_insn "return"
5455 "mips_can_use_return_insn ()"
5457 [(set_attr "type" "jump")
5458 (set_attr "mode" "none")])
5462 (define_insn "return_internal"
5464 (use (match_operand 0 "pmode_register_operand" ""))]
5467 [(set_attr "type" "jump")
5468 (set_attr "mode" "none")])
5470 ;; This is used in compiling the unwind routines.
5471 (define_expand "eh_return"
5472 [(use (match_operand 0 "general_operand"))]
5475 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
5477 if (GET_MODE (operands[0]) != gpr_mode)
5478 operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
5480 emit_insn (gen_eh_set_lr_di (operands[0]));
5482 emit_insn (gen_eh_set_lr_si (operands[0]));
5487 ;; Clobber the return address on the stack. We can't expand this
5488 ;; until we know where it will be put in the stack frame.
5490 (define_insn "eh_set_lr_si"
5491 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5492 (clobber (match_scratch:SI 1 "=&d"))]
5496 (define_insn "eh_set_lr_di"
5497 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5498 (clobber (match_scratch:DI 1 "=&d"))]
5503 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5504 (clobber (match_scratch 1))]
5505 "reload_completed && !TARGET_DEBUG_D_MODE"
5508 mips_set_return_address (operands[0], operands[1]);
5512 (define_insn_and_split "nonlocal_goto_receiver"
5514 (unspec_volatile:SI [(const_int 0)] UNSPEC_NONLOCAL_GOTO_RECEIVER))]
5515 "TARGET_CALL_CLOBBERED_GP"
5517 "&& reload_completed"
5523 [(set_attr "type" "load")
5524 (set_attr "length" "12")])
5527 ;; ....................
5531 ;; ....................
5533 ;; Instructions to load a call address from the GOT. The address might
5534 ;; point to a function or to a lazy binding stub. In the latter case,
5535 ;; the stub will use the dynamic linker to resolve the function, which
5536 ;; in turn will change the GOT entry to point to the function's real
5539 ;; This means that every call, even pure and constant ones, can
5540 ;; potentially modify the GOT entry. And once a stub has been called,
5541 ;; we must not call it again.
5543 ;; We represent this restriction using an imaginary fixed register that
5544 ;; acts like a GOT version number. By making the register call-clobbered,
5545 ;; we tell the target-independent code that the address could be changed
5546 ;; by any call insn.
5547 (define_insn "load_call<mode>"
5548 [(set (match_operand:P 0 "register_operand" "=d")
5549 (unspec:P [(match_operand:P 1 "register_operand" "r")
5550 (match_operand:P 2 "immediate_operand" "")
5551 (reg:P FAKE_CALL_REGNO)]
5554 "<load>\t%0,%R2(%1)"
5555 [(set_attr "type" "load")
5556 (set_attr "mode" "<MODE>")
5557 (set_attr "length" "4")])
5559 ;; Sibling calls. All these patterns use jump instructions.
5561 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5562 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5563 ;; is defined in terms of call_insn_operand, the same is true of the
5566 ;; When we use an indirect jump, we need a register that will be
5567 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5568 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5569 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5572 (define_expand "sibcall"
5573 [(parallel [(call (match_operand 0 "")
5574 (match_operand 1 ""))
5575 (use (match_operand 2 "")) ;; next_arg_reg
5576 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5579 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
5583 (define_insn "sibcall_internal"
5584 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5585 (match_operand 1 "" ""))]
5586 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5587 { return MIPS_CALL ("j", operands, 0); }
5588 [(set_attr "type" "call")])
5590 (define_expand "sibcall_value"
5591 [(parallel [(set (match_operand 0 "")
5592 (call (match_operand 1 "")
5593 (match_operand 2 "")))
5594 (use (match_operand 3 ""))])] ;; next_arg_reg
5597 mips_expand_call (operands[0], XEXP (operands[1], 0),
5598 operands[2], operands[3], true);
5602 (define_insn "sibcall_value_internal"
5603 [(set (match_operand 0 "register_operand" "")
5604 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5605 (match_operand 2 "" "")))]
5606 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5607 { return MIPS_CALL ("j", operands, 1); }
5608 [(set_attr "type" "call")])
5610 (define_insn "sibcall_value_multiple_internal"
5611 [(set (match_operand 0 "register_operand" "")
5612 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5613 (match_operand 2 "" "")))
5614 (set (match_operand 3 "register_operand" "")
5615 (call (mem:SI (match_dup 1))
5617 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5618 { return MIPS_CALL ("j", operands, 1); }
5619 [(set_attr "type" "call")])
5621 (define_expand "call"
5622 [(parallel [(call (match_operand 0 "")
5623 (match_operand 1 ""))
5624 (use (match_operand 2 "")) ;; next_arg_reg
5625 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5628 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
5632 ;; This instruction directly corresponds to an assembly-language "jal".
5633 ;; There are four cases:
5636 ;; Both symbolic and register destinations are OK. The pattern
5637 ;; always expands to a single mips instruction.
5639 ;; - -mabicalls/-mno-explicit-relocs:
5640 ;; Again, both symbolic and register destinations are OK.
5641 ;; The call is treated as a multi-instruction black box.
5643 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5644 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5647 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5648 ;; Only "jal $25" is allowed. The call is actually two instructions:
5649 ;; "jalr $25" followed by an insn to reload $gp.
5651 ;; In the last case, we can generate the individual instructions with
5652 ;; a define_split. There are several things to be wary of:
5654 ;; - We can't expose the load of $gp before reload. If we did,
5655 ;; it might get removed as dead, but reload can introduce new
5656 ;; uses of $gp by rematerializing constants.
5658 ;; - We shouldn't restore $gp after calls that never return.
5659 ;; It isn't valid to insert instructions between a noreturn
5660 ;; call and the following barrier.
5662 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5663 ;; instruction preserves $gp and so have no effect on its liveness.
5664 ;; But once we generate the separate insns, it becomes obvious that
5665 ;; $gp is not live on entry to the call.
5667 ;; ??? The operands[2] = insn check is a hack to make the original insn
5668 ;; available to the splitter.
5669 (define_insn_and_split "call_internal"
5670 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5671 (match_operand 1 "" ""))
5672 (clobber (reg:SI 31))]
5674 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5675 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5678 emit_call_insn (gen_call_split (operands[0], operands[1]));
5679 if (!find_reg_note (operands[2], REG_NORETURN, 0))
5683 [(set_attr "jal" "indirect,direct")
5684 (set_attr "extended_mips16" "no,yes")])
5686 ;; A pattern for calls that must be made directly. It is used for
5687 ;; MIPS16 calls that the linker may need to redirect to a hard-float
5688 ;; stub; the linker relies on the call relocation type to detect when
5689 ;; such redirection is needed.
5690 (define_insn "call_internal_direct"
5691 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
5694 (clobber (reg:SI 31))]
5696 { return MIPS_CALL ("jal", operands, 0); })
5698 (define_insn "call_split"
5699 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5700 (match_operand 1 "" ""))
5701 (clobber (reg:SI 31))
5702 (clobber (reg:SI 28))]
5703 "TARGET_SPLIT_CALLS"
5704 { return MIPS_CALL ("jal", operands, 0); }
5705 [(set_attr "type" "call")])
5707 (define_expand "call_value"
5708 [(parallel [(set (match_operand 0 "")
5709 (call (match_operand 1 "")
5710 (match_operand 2 "")))
5711 (use (match_operand 3 ""))])] ;; next_arg_reg
5714 mips_expand_call (operands[0], XEXP (operands[1], 0),
5715 operands[2], operands[3], false);
5719 ;; See comment for call_internal.
5720 (define_insn_and_split "call_value_internal"
5721 [(set (match_operand 0 "register_operand" "")
5722 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5723 (match_operand 2 "" "")))
5724 (clobber (reg:SI 31))]
5726 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5727 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5730 emit_call_insn (gen_call_value_split (operands[0], operands[1],
5732 if (!find_reg_note (operands[3], REG_NORETURN, 0))
5736 [(set_attr "jal" "indirect,direct")
5737 (set_attr "extended_mips16" "no,yes")])
5739 (define_insn "call_value_split"
5740 [(set (match_operand 0 "register_operand" "")
5741 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5742 (match_operand 2 "" "")))
5743 (clobber (reg:SI 31))
5744 (clobber (reg:SI 28))]
5745 "TARGET_SPLIT_CALLS"
5746 { return MIPS_CALL ("jal", operands, 1); }
5747 [(set_attr "type" "call")])
5749 ;; See call_internal_direct.
5750 (define_insn "call_value_internal_direct"
5751 [(set (match_operand 0 "register_operand")
5752 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
5755 (clobber (reg:SI 31))]
5757 { return MIPS_CALL ("jal", operands, 1); })
5759 ;; See comment for call_internal.
5760 (define_insn_and_split "call_value_multiple_internal"
5761 [(set (match_operand 0 "register_operand" "")
5762 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5763 (match_operand 2 "" "")))
5764 (set (match_operand 3 "register_operand" "")
5765 (call (mem:SI (match_dup 1))
5767 (clobber (reg:SI 31))]
5769 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5770 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5773 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
5774 operands[2], operands[3]));
5775 if (!find_reg_note (operands[4], REG_NORETURN, 0))
5779 [(set_attr "jal" "indirect,direct")
5780 (set_attr "extended_mips16" "no,yes")])
5782 (define_insn "call_value_multiple_split"
5783 [(set (match_operand 0 "register_operand" "")
5784 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5785 (match_operand 2 "" "")))
5786 (set (match_operand 3 "register_operand" "")
5787 (call (mem:SI (match_dup 1))
5789 (clobber (reg:SI 31))
5790 (clobber (reg:SI 28))]
5791 "TARGET_SPLIT_CALLS"
5792 { return MIPS_CALL ("jal", operands, 1); }
5793 [(set_attr "type" "call")])
5795 ;; Call subroutine returning any type.
5797 (define_expand "untyped_call"
5798 [(parallel [(call (match_operand 0 "")
5800 (match_operand 1 "")
5801 (match_operand 2 "")])]
5806 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5808 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5810 rtx set = XVECEXP (operands[2], 0, i);
5811 mips_emit_move (SET_DEST (set), SET_SRC (set));
5814 emit_insn (gen_blockage ());
5819 ;; ....................
5823 ;; ....................
5827 (define_insn "prefetch"
5828 [(prefetch (match_operand:QI 0 "address_operand" "p")
5829 (match_operand 1 "const_int_operand" "n")
5830 (match_operand 2 "const_int_operand" "n"))]
5831 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
5833 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
5834 return "pref\t%1,%a0";
5836 [(set_attr "type" "prefetch")])
5838 (define_insn "*prefetch_indexed_<mode>"
5839 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
5840 (match_operand:P 1 "register_operand" "d"))
5841 (match_operand 2 "const_int_operand" "n")
5842 (match_operand 3 "const_int_operand" "n"))]
5843 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5845 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
5846 return "prefx\t%2,%1(%0)";
5848 [(set_attr "type" "prefetchx")])
5854 [(set_attr "type" "nop")
5855 (set_attr "mode" "none")])
5857 ;; Like nop, but commented out when outside a .set noreorder block.
5858 (define_insn "hazard_nop"
5867 [(set_attr "type" "nop")])
5869 ;; MIPS4 Conditional move instructions.
5871 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
5872 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5874 (match_operator:MOVECC 4 "equality_operator"
5875 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5877 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
5878 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
5883 [(set_attr "type" "condmove")
5884 (set_attr "mode" "<GPR:MODE>")])
5886 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
5887 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
5888 (if_then_else:SCALARF
5889 (match_operator:MOVECC 4 "equality_operator"
5890 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5892 (match_operand:SCALARF 2 "register_operand" "f,0")
5893 (match_operand:SCALARF 3 "register_operand" "0,f")))]
5896 mov%T4.<fmt>\t%0,%2,%1
5897 mov%t4.<fmt>\t%0,%3,%1"
5898 [(set_attr "type" "condmove")
5899 (set_attr "mode" "<SCALARF:MODE>")])
5901 ;; These are the main define_expand's used to make conditional moves.
5903 (define_expand "mov<mode>cc"
5904 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5905 (set (match_operand:GPR 0 "register_operand")
5906 (if_then_else:GPR (match_dup 5)
5907 (match_operand:GPR 2 "reg_or_0_operand")
5908 (match_operand:GPR 3 "reg_or_0_operand")))]
5911 gen_conditional_move (operands);
5915 (define_expand "mov<mode>cc"
5916 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5917 (set (match_operand:SCALARF 0 "register_operand")
5918 (if_then_else:SCALARF (match_dup 5)
5919 (match_operand:SCALARF 2 "register_operand")
5920 (match_operand:SCALARF 3 "register_operand")))]
5923 gen_conditional_move (operands);
5928 ;; ....................
5930 ;; mips16 inline constant tables
5932 ;; ....................
5935 (define_insn "consttable_int"
5936 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
5937 (match_operand 1 "const_int_operand" "")]
5938 UNSPEC_CONSTTABLE_INT)]
5941 assemble_integer (operands[0], INTVAL (operands[1]),
5942 BITS_PER_UNIT * INTVAL (operands[1]), 1);
5945 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
5947 (define_insn "consttable_float"
5948 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
5949 UNSPEC_CONSTTABLE_FLOAT)]
5954 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
5955 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
5956 assemble_real (d, GET_MODE (operands[0]),
5957 GET_MODE_BITSIZE (GET_MODE (operands[0])));
5960 [(set (attr "length")
5961 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
5963 (define_insn "align"
5964 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
5967 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
5970 [(match_operand 0 "small_data_pattern")]
5973 { operands[0] = mips_rewrite_small_data (operands[0]); })
5976 ;; ....................
5978 ;; MIPS16e Save/Restore
5980 ;; ....................
5983 (define_insn "*mips16e_save_restore"
5984 [(match_parallel 0 ""
5985 [(set (match_operand:SI 1 "register_operand")
5986 (plus:SI (match_dup 1)
5987 (match_operand:SI 2 "const_int_operand")))])]
5988 "operands[1] == stack_pointer_rtx
5989 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
5990 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
5991 [(set_attr "type" "arith")
5992 (set_attr "extended_mips16" "yes")])
5994 ; Thread-Local Storage
5996 ; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
5997 ; MIPS architecture defines this register, and no current
5998 ; implementation provides it; instead, any OS which supports TLS is
5999 ; expected to trap and emulate this instruction. rdhwr is part of the
6000 ; MIPS 32r2 specification, but we use it on any architecture because
6001 ; we expect it to be emulated. Use .set to force the assembler to
6004 (define_insn "tls_get_tp_<mode>"
6005 [(set (match_operand:P 0 "register_operand" "=v")
6006 (unspec:P [(const_int 0)]
6007 UNSPEC_TLS_GET_TP))]
6008 "HAVE_AS_TLS && !TARGET_MIPS16"
6009 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
6010 [(set_attr "type" "unknown")
6011 ; Since rdhwr always generates a trap for now, putting it in a delay
6012 ; slot would make the kernel's emulation of it much slower.
6013 (set_attr "can_delay" "no")
6014 (set_attr "mode" "<MODE>")])
6016 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6018 (include "mips-ps-3d.md")
6020 ; The MIPS DSP Instructions.
6022 (include "mips-dsp.md")
6024 ; The MIPS DSP REV 2 Instructions.
6026 (include "mips-dspr2.md")
6028 ; MIPS fixed-point instructions.
6029 (include "mips-fixed.md")