1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
51 (UNSPEC_TLS_GET_TP 30)
54 (UNSPEC_CLEAR_HAZARD 33)
58 (UNSPEC_COMPARE_AND_SWAP 37)
59 (UNSPEC_COMPARE_AND_SWAP_12 38)
60 (UNSPEC_SYNC_OLD_OP 39)
61 (UNSPEC_SYNC_NEW_OP 40)
62 (UNSPEC_SYNC_NEW_OP_12 41)
63 (UNSPEC_SYNC_OLD_OP_12 42)
64 (UNSPEC_SYNC_EXCHANGE 43)
65 (UNSPEC_SYNC_EXCHANGE_12 44)
66 (UNSPEC_MEMORY_BARRIER 45)
67 (UNSPEC_SET_GOT_VERSION 46)
68 (UNSPEC_UPDATE_GOT_VERSION 47)
77 (UNSPEC_ADDRESS_FIRST 100)
80 (GOT_VERSION_REGNUM 79)
82 ;; For MIPS Paired-Singled Floating Point Instructions.
84 (UNSPEC_MOVE_TF_PS 200)
87 ;; MIPS64/MIPS32R2 alnv.ps
90 ;; MIPS-3D instructions
94 (UNSPEC_CVT_PW_PS 205)
95 (UNSPEC_CVT_PS_PW 206)
103 (UNSPEC_SINGLE_CC 213)
106 ;; MIPS DSP ASE Revision 0.98 3/24/2005
114 (UNSPEC_RADDU_W_QB 307)
116 (UNSPEC_PRECRQ_QB_PH 309)
117 (UNSPEC_PRECRQ_PH_W 310)
118 (UNSPEC_PRECRQ_RS_PH_W 311)
119 (UNSPEC_PRECRQU_S_QB_PH 312)
120 (UNSPEC_PRECEQ_W_PHL 313)
121 (UNSPEC_PRECEQ_W_PHR 314)
122 (UNSPEC_PRECEQU_PH_QBL 315)
123 (UNSPEC_PRECEQU_PH_QBR 316)
124 (UNSPEC_PRECEQU_PH_QBLA 317)
125 (UNSPEC_PRECEQU_PH_QBRA 318)
126 (UNSPEC_PRECEU_PH_QBL 319)
127 (UNSPEC_PRECEU_PH_QBR 320)
128 (UNSPEC_PRECEU_PH_QBLA 321)
129 (UNSPEC_PRECEU_PH_QBRA 322)
135 (UNSPEC_MULEU_S_PH_QBL 328)
136 (UNSPEC_MULEU_S_PH_QBR 329)
137 (UNSPEC_MULQ_RS_PH 330)
138 (UNSPEC_MULEQ_S_W_PHL 331)
139 (UNSPEC_MULEQ_S_W_PHR 332)
140 (UNSPEC_DPAU_H_QBL 333)
141 (UNSPEC_DPAU_H_QBR 334)
142 (UNSPEC_DPSU_H_QBL 335)
143 (UNSPEC_DPSU_H_QBR 336)
144 (UNSPEC_DPAQ_S_W_PH 337)
145 (UNSPEC_DPSQ_S_W_PH 338)
146 (UNSPEC_MULSAQ_S_W_PH 339)
147 (UNSPEC_DPAQ_SA_L_W 340)
148 (UNSPEC_DPSQ_SA_L_W 341)
149 (UNSPEC_MAQ_S_W_PHL 342)
150 (UNSPEC_MAQ_S_W_PHR 343)
151 (UNSPEC_MAQ_SA_W_PHL 344)
152 (UNSPEC_MAQ_SA_W_PHR 345)
160 (UNSPEC_CMPGU_EQ_QB 353)
161 (UNSPEC_CMPGU_LT_QB 354)
162 (UNSPEC_CMPGU_LE_QB 355)
164 (UNSPEC_PACKRL_PH 357)
166 (UNSPEC_EXTR_R_W 359)
167 (UNSPEC_EXTR_RS_W 360)
168 (UNSPEC_EXTR_S_H 361)
176 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
177 (UNSPEC_ABSQ_S_QB 400)
179 (UNSPEC_ADDU_S_PH 402)
180 (UNSPEC_ADDUH_QB 403)
181 (UNSPEC_ADDUH_R_QB 404)
184 (UNSPEC_CMPGDU_EQ_QB 407)
185 (UNSPEC_CMPGDU_LT_QB 408)
186 (UNSPEC_CMPGDU_LE_QB 409)
187 (UNSPEC_DPA_W_PH 410)
188 (UNSPEC_DPS_W_PH 411)
194 (UNSPEC_MUL_S_PH 417)
195 (UNSPEC_MULQ_RS_W 418)
196 (UNSPEC_MULQ_S_PH 419)
197 (UNSPEC_MULQ_S_W 420)
198 (UNSPEC_MULSA_W_PH 421)
201 (UNSPEC_PRECR_QB_PH 424)
202 (UNSPEC_PRECR_SRA_PH_W 425)
203 (UNSPEC_PRECR_SRA_R_PH_W 426)
206 (UNSPEC_SHRA_R_QB 429)
209 (UNSPEC_SUBU_S_PH 432)
210 (UNSPEC_SUBUH_QB 433)
211 (UNSPEC_SUBUH_R_QB 434)
212 (UNSPEC_ADDQH_PH 435)
213 (UNSPEC_ADDQH_R_PH 436)
215 (UNSPEC_ADDQH_R_W 438)
216 (UNSPEC_SUBQH_PH 439)
217 (UNSPEC_SUBQH_R_PH 440)
219 (UNSPEC_SUBQH_R_W 442)
220 (UNSPEC_DPAX_W_PH 443)
221 (UNSPEC_DPSX_W_PH 444)
222 (UNSPEC_DPAQX_S_W_PH 445)
223 (UNSPEC_DPAQX_SA_W_PH 446)
224 (UNSPEC_DPSQX_S_W_PH 447)
225 (UNSPEC_DPSQX_SA_W_PH 448)
227 ;; ST Microelectronics Loongson-2E/2F.
228 (UNSPEC_LOONGSON_PAVG 500)
229 (UNSPEC_LOONGSON_PCMPEQ 501)
230 (UNSPEC_LOONGSON_PCMPGT 502)
231 (UNSPEC_LOONGSON_PEXTR 503)
232 (UNSPEC_LOONGSON_PINSR_0 504)
233 (UNSPEC_LOONGSON_PINSR_1 505)
234 (UNSPEC_LOONGSON_PINSR_2 506)
235 (UNSPEC_LOONGSON_PINSR_3 507)
236 (UNSPEC_LOONGSON_PMADD 508)
237 (UNSPEC_LOONGSON_PMOVMSK 509)
238 (UNSPEC_LOONGSON_PMULHU 510)
239 (UNSPEC_LOONGSON_PMULH 511)
240 (UNSPEC_LOONGSON_PMULL 512)
241 (UNSPEC_LOONGSON_PMULU 513)
242 (UNSPEC_LOONGSON_PASUBUB 514)
243 (UNSPEC_LOONGSON_BIADD 515)
244 (UNSPEC_LOONGSON_PSADBH 516)
245 (UNSPEC_LOONGSON_PSHUFH 517)
246 (UNSPEC_LOONGSON_PUNPCKH 518)
247 (UNSPEC_LOONGSON_PUNPCKL 519)
248 (UNSPEC_LOONGSON_PADDD 520)
249 (UNSPEC_LOONGSON_PSUBD 521)
251 ;; Used in loongson2ef.md
252 (UNSPEC_LOONGSON_ALU1_TURN_ENABLED_INSN 530)
253 (UNSPEC_LOONGSON_ALU2_TURN_ENABLED_INSN 531)
254 (UNSPEC_LOONGSON_FALU1_TURN_ENABLED_INSN 532)
255 (UNSPEC_LOONGSON_FALU2_TURN_ENABLED_INSN 533)
257 (UNSPEC_MIPS_CACHE 600)
258 (UNSPEC_R10K_CACHE_BARRIER 601)
262 (include "predicates.md")
263 (include "constraints.md")
265 ;; ....................
269 ;; ....................
271 (define_attr "got" "unset,xgot_high,load"
272 (const_string "unset"))
274 ;; For jal instructions, this attribute is DIRECT when the target address
275 ;; is symbolic and INDIRECT when it is a register.
276 (define_attr "jal" "unset,direct,indirect"
277 (const_string "unset"))
279 ;; This attribute is YES if the instruction is a jal macro (not a
280 ;; real jal instruction).
282 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
283 ;; an instruction to restore $gp. Direct jals are also macros for
284 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
285 ;; the target address into a register.
286 (define_attr "jal_macro" "no,yes"
287 (cond [(eq_attr "jal" "direct")
288 (symbol_ref "((TARGET_CALL_CLOBBERED_GP
289 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS))
290 ? JAL_MACRO_YES : JAL_MACRO_NO)")
291 (eq_attr "jal" "indirect")
292 (symbol_ref "(TARGET_CALL_CLOBBERED_GP
293 ? JAL_MACRO_YES : JAL_MACRO_NO)")]
294 (const_string "no")))
296 ;; Classification of moves, extensions and truncations. Most values
297 ;; are as for "type" (see below) but there are also the following
298 ;; move-specific values:
300 ;; constN move an N-constraint integer into a MIPS16 register
301 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
302 ;; to produce a sign-extended DEST, even if SRC is not
303 ;; properly sign-extended
304 ;; andi a single ANDI instruction
305 ;; loadpool move a constant into a MIPS16 register by loading it
307 ;; shift_shift a shift left followed by a shift right
308 ;; lui_movf an LUI followed by a MOVF (for d<-z CC moves)
310 ;; This attribute is used to determine the instruction's length and
311 ;; scheduling type. For doubleword moves, the attribute always describes
312 ;; the split instructions; in some cases, it is more appropriate for the
313 ;; scheduling type to be "multi" instead.
314 (define_attr "move_type"
315 "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
316 const,constN,signext,sll0,andi,loadpool,shift_shift,lui_movf"
317 (const_string "unknown"))
319 ;; Main data type used by the insn
320 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
321 (const_string "unknown"))
323 ;; True if the main data type is twice the size of a word.
324 (define_attr "dword_mode" "no,yes"
325 (cond [(and (eq_attr "mode" "DI,DF")
326 (eq (symbol_ref "TARGET_64BIT") (const_int 0)))
329 (and (eq_attr "mode" "TI,TF")
330 (ne (symbol_ref "TARGET_64BIT") (const_int 0)))
331 (const_string "yes")]
332 (const_string "no")))
334 ;; Classification of each insn.
335 ;; branch conditional branch
336 ;; jump unconditional jump
337 ;; call unconditional call
338 ;; load load instruction(s)
339 ;; fpload floating point load
340 ;; fpidxload floating point indexed load
341 ;; store store instruction(s)
342 ;; fpstore floating point store
343 ;; fpidxstore floating point indexed store
344 ;; prefetch memory prefetch (register + offset)
345 ;; prefetchx memory indexed prefetch (register + register)
346 ;; condmove conditional moves
347 ;; mtc transfer to coprocessor
348 ;; mfc transfer from coprocessor
349 ;; mthilo transfer to hi/lo registers
350 ;; mfhilo transfer from hi/lo registers
351 ;; const load constant
352 ;; arith integer arithmetic instructions
353 ;; logical integer logical instructions
354 ;; shift integer shift instructions
355 ;; slt set less than instructions
356 ;; signext sign extend instructions
357 ;; clz the clz and clo instructions
358 ;; pop the pop instruction
359 ;; trap trap if instructions
360 ;; imul integer multiply 2 operands
361 ;; imul3 integer multiply 3 operands
362 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
363 ;; imadd integer multiply-add
364 ;; idiv integer divide 2 operands
365 ;; idiv3 integer divide 3 operands
366 ;; move integer register move ({,D}ADD{,U} with rt = 0)
367 ;; fmove floating point register move
368 ;; fadd floating point add/subtract
369 ;; fmul floating point multiply
370 ;; fmadd floating point multiply-add
371 ;; fdiv floating point divide
372 ;; frdiv floating point reciprocal divide
373 ;; frdiv1 floating point reciprocal divide step 1
374 ;; frdiv2 floating point reciprocal divide step 2
375 ;; fabs floating point absolute value
376 ;; fneg floating point negation
377 ;; fcmp floating point compare
378 ;; fcvt floating point convert
379 ;; fsqrt floating point square root
380 ;; frsqrt floating point reciprocal square root
381 ;; frsqrt1 floating point reciprocal square root step1
382 ;; frsqrt2 floating point reciprocal square root step2
383 ;; multi multiword sequence (or user asm statements)
385 ;; ghost an instruction that produces no real code
387 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
388 prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
389 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
390 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
391 frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
392 (cond [(eq_attr "jal" "!unset") (const_string "call")
393 (eq_attr "got" "load") (const_string "load")
395 ;; If a doubleword move uses these expensive instructions,
396 ;; it is usually better to schedule them in the same way
397 ;; as the singleword form, rather than as "multi".
398 (eq_attr "move_type" "load") (const_string "load")
399 (eq_attr "move_type" "fpload") (const_string "fpload")
400 (eq_attr "move_type" "store") (const_string "store")
401 (eq_attr "move_type" "fpstore") (const_string "fpstore")
402 (eq_attr "move_type" "mtc") (const_string "mtc")
403 (eq_attr "move_type" "mfc") (const_string "mfc")
404 (eq_attr "move_type" "mthilo") (const_string "mthilo")
405 (eq_attr "move_type" "mfhilo") (const_string "mfhilo")
407 ;; These types of move are always single insns.
408 (eq_attr "move_type" "fmove") (const_string "fmove")
409 (eq_attr "move_type" "loadpool") (const_string "load")
410 (eq_attr "move_type" "signext") (const_string "signext")
411 (eq_attr "move_type" "sll0") (const_string "shift")
412 (eq_attr "move_type" "andi") (const_string "logical")
414 ;; These types of move are always split.
415 (eq_attr "move_type" "constN,shift_shift")
416 (const_string "multi")
418 ;; These types of move are split for doubleword modes only.
419 (and (eq_attr "move_type" "move,const")
420 (eq_attr "dword_mode" "yes"))
421 (const_string "multi")
422 (eq_attr "move_type" "move") (const_string "move")
423 (eq_attr "move_type" "const") (const_string "const")]
424 ;; We classify "lui_movf" as "unknown" rather than "multi"
425 ;; because we don't split it. FIXME: we should split instead.
426 (const_string "unknown")))
428 ;; Mode for conversion types (fcvt)
429 ;; I2S integer to float single (SI/DI to SF)
430 ;; I2D integer to float double (SI/DI to DF)
431 ;; S2I float to integer (SF to SI/DI)
432 ;; D2I float to integer (DF to SI/DI)
433 ;; D2S double to float single
434 ;; S2D float single to double
436 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
437 (const_string "unknown"))
439 ;; Is this an extended instruction in mips16 mode?
440 (define_attr "extended_mips16" "no,yes"
441 (if_then_else (ior (eq_attr "move_type" "sll0")
442 (eq_attr "type" "branch")
443 (eq_attr "jal" "direct"))
445 (const_string "no")))
447 ;; Length of instruction in bytes.
448 (define_attr "length" ""
449 (cond [(and (eq_attr "extended_mips16" "yes")
450 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
453 ;; Direct branch instructions have a range of [-0x40000,0x3fffc].
454 ;; If a branch is outside this range, we have a choice of two
455 ;; sequences. For PIC, an out-of-range branch like:
460 ;; becomes the equivalent of:
469 ;; where the load address can be up to three instructions long
472 ;; The non-PIC case is similar except that we use a direct
473 ;; jump instead of an la/jr pair. Since the target of this
474 ;; jump is an absolute 28-bit bit address (the other bits
475 ;; coming from the address of the delay slot) this form cannot
476 ;; cross a 256MB boundary. We could provide the option of
477 ;; using la/jr in this case too, but we do not do so at
480 ;; Note that this value does not account for the delay slot
481 ;; instruction, whose length is added separately. If the RTL
482 ;; pattern has no explicit delay slot, mips_adjust_insn_length
483 ;; will add the length of the implicit nop. The values for
484 ;; forward and backward branches will be different as well.
485 (eq_attr "type" "branch")
486 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
487 (le (minus (pc) (match_dup 1)) (const_int 131068)))
489 (ne (symbol_ref "flag_pic") (const_int 0))
493 ;; "Ghost" instructions occupy no space.
494 (eq_attr "type" "ghost")
497 (eq_attr "got" "load")
498 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
501 (eq_attr "got" "xgot_high")
504 ;; In general, constant-pool loads are extended instructions.
505 (eq_attr "move_type" "loadpool")
508 ;; LUI_MOVFs are decomposed into two separate instructions.
509 (eq_attr "move_type" "lui_movf")
512 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
513 ;; They are extended instructions on MIPS16 targets.
514 (eq_attr "move_type" "shift_shift")
515 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
519 ;; Check for doubleword moves that are decomposed into two
521 (and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")
522 (eq_attr "dword_mode" "yes"))
525 ;; Doubleword CONST{,N} moves are split into two word
527 (and (eq_attr "move_type" "const,constN")
528 (eq_attr "dword_mode" "yes"))
529 (symbol_ref "mips_split_const_insns (operands[1]) * 4")
531 ;; Otherwise, constants, loads and stores are handled by external
533 (eq_attr "move_type" "const,constN")
534 (symbol_ref "mips_const_insns (operands[1]) * 4")
535 (eq_attr "move_type" "load,fpload")
536 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
537 (eq_attr "move_type" "store,fpstore")
538 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
540 ;; In the worst case, a call macro will take 8 instructions:
542 ;; lui $25,%call_hi(FOO)
544 ;; lw $25,%call_lo(FOO)($25)
550 (eq_attr "jal_macro" "yes")
553 ;; Various VR4120 errata require a nop to be inserted after a macc
554 ;; instruction. The assembler does this for us, so account for
555 ;; the worst-case length here.
556 (and (eq_attr "type" "imadd")
557 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
560 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
561 ;; the result of the second one is missed. The assembler should work
562 ;; around this by inserting a nop after the first dmult.
563 (and (eq_attr "type" "imul,imul3")
564 (and (eq_attr "mode" "DI")
565 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
568 (eq_attr "type" "idiv,idiv3")
569 (symbol_ref "mips_idiv_insns () * 4")
572 ;; Attribute describing the processor. This attribute must match exactly
573 ;; with the processor_type enumeration in mips.h.
575 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,r10000,sb1,sb1a,sr71000,xlr"
576 (const (symbol_ref "mips_tune_attr")))
578 ;; The type of hardware hazard associated with this instruction.
579 ;; DELAY means that the next instruction cannot read the result
580 ;; of this one. HILO means that the next two instructions cannot
581 ;; write to HI or LO.
582 (define_attr "hazard" "none,delay,hilo"
583 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
584 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
585 (const_string "delay")
587 (and (eq_attr "type" "mfc,mtc")
588 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
589 (const_string "delay")
591 (and (eq_attr "type" "fcmp")
592 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
593 (const_string "delay")
595 ;; The r4000 multiplication patterns include an mflo instruction.
596 (and (eq_attr "type" "imul")
597 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
598 (const_string "hilo")
600 (and (eq_attr "type" "mfhilo")
601 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
602 (const_string "hilo")]
603 (const_string "none")))
605 ;; Is it a single instruction?
606 (define_attr "single_insn" "no,yes"
607 (symbol_ref "(get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)
608 ? SINGLE_INSN_YES : SINGLE_INSN_NO)"))
610 ;; Can the instruction be put into a delay slot?
611 (define_attr "can_delay" "no,yes"
612 (if_then_else (and (eq_attr "type" "!branch,call,jump")
613 (and (eq_attr "hazard" "none")
614 (eq_attr "single_insn" "yes")))
616 (const_string "no")))
618 ;; Attribute defining whether or not we can use the branch-likely
620 (define_attr "branch_likely" "no,yes"
621 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
623 (const_string "no")))
625 ;; True if an instruction might assign to hi or lo when reloaded.
626 ;; This is used by the TUNE_MACC_CHAINS code.
627 (define_attr "may_clobber_hilo" "no,yes"
628 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
630 (const_string "no")))
632 ;; Describe a user's asm statement.
633 (define_asm_attributes
634 [(set_attr "type" "multi")
635 (set_attr "can_delay" "no")])
637 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
638 ;; from the same template.
639 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
641 ;; A copy of GPR that can be used when a pattern has two independent
643 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
645 ;; This mode iterator allows :HILO to be used as the mode of the
646 ;; concatenated HI and LO registers.
647 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
649 ;; This mode iterator allows :P to be used for patterns that operate on
650 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
651 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
653 ;; This mode iterator allows :MOVECC to be used anywhere that a
654 ;; conditional-move-type condition is needed.
655 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
656 (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
658 ;; 32-bit integer moves for which we provide move patterns.
659 (define_mode_iterator IMOVE32
668 (V4UQQ "TARGET_DSP")])
670 ;; 64-bit modes for which we provide move patterns.
671 (define_mode_iterator MOVE64
673 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
674 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
675 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
676 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
678 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
679 (define_mode_iterator MOVE128 [TI TF])
681 ;; This mode iterator allows the QI and HI extension patterns to be
682 ;; defined from the same template.
683 (define_mode_iterator SHORT [QI HI])
685 ;; Likewise the 64-bit truncate-and-shift patterns.
686 (define_mode_iterator SUBDI [QI HI SI])
688 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
689 ;; floating-point mode is allowed.
690 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
691 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
692 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
694 ;; Like ANYF, but only applies to scalar modes.
695 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
696 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
698 ;; A floating-point mode for which moves involving FPRs may need to be split.
699 (define_mode_iterator SPLITF
700 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
701 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
702 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
703 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
704 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
705 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
706 (TF "TARGET_64BIT && TARGET_FLOAT64")])
708 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
709 ;; 32-bit version and "dsubu" in the 64-bit version.
710 (define_mode_attr d [(SI "") (DI "d")
711 (QQ "") (HQ "") (SQ "") (DQ "d")
712 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
713 (HA "") (SA "") (DA "d")
714 (UHA "") (USA "") (UDA "d")])
716 ;; Same as d but upper-case.
717 (define_mode_attr D [(SI "") (DI "D")
718 (QQ "") (HQ "") (SQ "") (DQ "D")
719 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
720 (HA "") (SA "") (DA "D")
721 (UHA "") (USA "") (UDA "D")])
723 ;; This attribute gives the length suffix for a sign- or zero-extension
725 (define_mode_attr size [(QI "b") (HI "h")])
727 ;; This attributes gives the mode mask of a SHORT.
728 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
730 ;; Mode attributes for GPR loads.
731 (define_mode_attr load [(SI "lw") (DI "ld")])
732 ;; Instruction names for stores.
733 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])
735 ;; Similarly for MIPS IV indexed FPR loads and stores.
736 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
737 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
739 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
740 ;; are different. Some forms of unextended addiu have an 8-bit immediate
741 ;; field but the equivalent daddiu has only a 5-bit field.
742 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
744 ;; This attribute gives the best constraint to use for registers of
746 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
748 ;; This attribute gives the format suffix for floating-point operations.
749 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
751 ;; This attribute gives the upper-case mode name for one unit of a
752 ;; floating-point mode.
753 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
755 ;; This attribute gives the integer mode that has the same size as a
757 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
758 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
759 (HA "HI") (SA "SI") (DA "DI")
760 (UHA "HI") (USA "SI") (UDA "DI")
761 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
762 (V2HQ "SI") (V2HA "SI")])
764 ;; This attribute gives the integer mode that has half the size of
765 ;; the controlling mode.
766 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
767 (V2SI "SI") (V4HI "SI") (V8QI "SI")
770 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
772 ;; In certain cases, div.s and div.ps may have a rounding error
773 ;; and/or wrong inexact flag.
775 ;; Therefore, we only allow div.s if not working around SB-1 rev2
776 ;; errata or if a slight loss of precision is OK.
777 (define_mode_attr divide_condition
778 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
779 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
781 ;; This attribute gives the conditions under which SQRT.fmt instructions
783 (define_mode_attr sqrt_condition
784 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
786 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
787 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
788 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
789 ;; so for safety's sake, we apply this restriction to all targets.
790 (define_mode_attr recip_condition
792 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
793 (V2SF "TARGET_SB1")])
795 ;; This code iterator allows signed and unsigned widening multiplications
796 ;; to use the same template.
797 (define_code_iterator any_extend [sign_extend zero_extend])
799 ;; This code iterator allows the two right shift instructions to be
800 ;; generated from the same template.
801 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
803 ;; This code iterator allows the three shift instructions to be generated
804 ;; from the same template.
805 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
807 ;; This code iterator allows unsigned and signed division to be generated
808 ;; from the same template.
809 (define_code_iterator any_div [div udiv])
811 ;; This code iterator allows unsigned and signed modulus to be generated
812 ;; from the same template.
813 (define_code_iterator any_mod [mod umod])
815 ;; This code iterator allows all native floating-point comparisons to be
816 ;; generated from the same template.
817 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
819 ;; This code iterator is used for comparisons that can be implemented
820 ;; by swapping the operands.
821 (define_code_iterator swapped_fcond [ge gt unge ungt])
823 ;; Equality operators.
824 (define_code_iterator equality_op [eq ne])
826 ;; These code iterators allow the signed and unsigned scc operations to use
827 ;; the same template.
828 (define_code_iterator any_gt [gt gtu])
829 (define_code_iterator any_ge [ge geu])
830 (define_code_iterator any_lt [lt ltu])
831 (define_code_iterator any_le [le leu])
833 ;; <u> expands to an empty string when doing a signed operation and
834 ;; "u" when doing an unsigned operation.
835 (define_code_attr u [(sign_extend "") (zero_extend "u")
843 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
844 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
846 ;; <optab> expands to the name of the optab for a particular code.
847 (define_code_attr optab [(ashift "ashl")
856 ;; <insn> expands to the name of the insn that implements a particular code.
857 (define_code_attr insn [(ashift "sll")
866 ;; <immediate_insn> expands to the name of the insn that implements
867 ;; a particular code to operate on immediate values.
868 (define_code_attr immediate_insn [(ior "ori")
872 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
873 (define_code_attr fcond [(unordered "un")
881 ;; Similar, but for swapped conditions.
882 (define_code_attr swapped_fcond [(ge "le")
887 ;; The value of the bit when the branch is taken for branch_bit patterns.
888 ;; Comparison is always against zero so this depends on the operator.
889 (define_code_attr bbv [(eq "0") (ne "1")])
891 ;; This is the inverse value of bbv.
892 (define_code_attr bbinv [(eq "1") (ne "0")])
894 ;; .........................
896 ;; Branch, call and jump delay slots
898 ;; .........................
900 (define_delay (and (eq_attr "type" "branch")
901 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
902 (eq_attr "branch_likely" "yes"))
903 [(eq_attr "can_delay" "yes")
905 (eq_attr "can_delay" "yes")])
907 ;; Branches that don't have likely variants do not annul on false.
908 (define_delay (and (eq_attr "type" "branch")
909 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
910 (eq_attr "branch_likely" "no"))
911 [(eq_attr "can_delay" "yes")
915 (define_delay (eq_attr "type" "jump")
916 [(eq_attr "can_delay" "yes")
920 (define_delay (and (eq_attr "type" "call")
921 (eq_attr "jal_macro" "no"))
922 [(eq_attr "can_delay" "yes")
926 ;; Pipeline descriptions.
928 ;; generic.md provides a fallback for processors without a specific
929 ;; pipeline description. It is derived from the old define_function_unit
930 ;; version and uses the "alu" and "imuldiv" units declared below.
932 ;; Some of the processor-specific files are also derived from old
933 ;; define_function_unit descriptions and simply override the parts of
934 ;; generic.md that don't apply. The other processor-specific files
935 ;; are self-contained.
936 (define_automaton "alu,imuldiv")
938 (define_cpu_unit "alu" "alu")
939 (define_cpu_unit "imuldiv" "imuldiv")
941 ;; Ghost instructions produce no real code and introduce no hazards.
942 ;; They exist purely to express an effect on dataflow.
943 (define_insn_reservation "ghost" 0
944 (eq_attr "type" "ghost")
965 (include "loongson2ef.md")
966 (include "octeon.md")
970 (include "generic.md")
973 ;; ....................
977 ;; ....................
981 [(trap_if (const_int 1) (const_int 0))]
984 if (ISA_HAS_COND_TRAP)
986 else if (TARGET_MIPS16)
991 [(set_attr "type" "trap")])
993 (define_expand "ctrap<mode>4"
994 [(trap_if (match_operator 0 "comparison_operator"
995 [(match_operand:GPR 1 "reg_or_0_operand")
996 (match_operand:GPR 2 "arith_operand")])
997 (match_operand 3 "const_0_operand"))]
1000 mips_expand_conditional_trap (operands[0]);
1004 (define_insn "*conditional_trap<mode>"
1005 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1006 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1007 (match_operand:GPR 2 "arith_operand" "dI")])
1011 [(set_attr "type" "trap")])
1014 ;; ....................
1018 ;; ....................
1021 (define_insn "add<mode>3"
1022 [(set (match_operand:ANYF 0 "register_operand" "=f")
1023 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1024 (match_operand:ANYF 2 "register_operand" "f")))]
1026 "add.<fmt>\t%0,%1,%2"
1027 [(set_attr "type" "fadd")
1028 (set_attr "mode" "<UNITMODE>")])
1030 (define_expand "add<mode>3"
1031 [(set (match_operand:GPR 0 "register_operand")
1032 (plus:GPR (match_operand:GPR 1 "register_operand")
1033 (match_operand:GPR 2 "arith_operand")))]
1036 (define_insn "*add<mode>3"
1037 [(set (match_operand:GPR 0 "register_operand" "=d,d")
1038 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
1039 (match_operand:GPR 2 "arith_operand" "d,Q")))]
1044 [(set_attr "type" "arith")
1045 (set_attr "mode" "<MODE>")])
1047 (define_insn "*add<mode>3_mips16"
1048 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
1049 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
1050 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
1058 [(set_attr "type" "arith")
1059 (set_attr "mode" "<MODE>")
1060 (set_attr_alternative "length"
1061 [(if_then_else (match_operand 2 "m16_simm8_8")
1064 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
1067 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
1070 (if_then_else (match_operand 2 "m16_simm4_1")
1075 ;; On the mips16, we can sometimes split an add of a constant which is
1076 ;; a 4 byte instruction into two adds which are both 2 byte
1077 ;; instructions. There are two cases: one where we are adding a
1078 ;; constant plus a register to another register, and one where we are
1079 ;; simply adding a constant to a register.
1082 [(set (match_operand:SI 0 "d_operand")
1083 (plus:SI (match_dup 0)
1084 (match_operand:SI 1 "const_int_operand")))]
1085 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1086 && ((INTVAL (operands[1]) > 0x7f
1087 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1088 || (INTVAL (operands[1]) < - 0x80
1089 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1090 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1091 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1093 HOST_WIDE_INT val = INTVAL (operands[1]);
1097 operands[1] = GEN_INT (0x7f);
1098 operands[2] = GEN_INT (val - 0x7f);
1102 operands[1] = GEN_INT (- 0x80);
1103 operands[2] = GEN_INT (val + 0x80);
1108 [(set (match_operand:SI 0 "d_operand")
1109 (plus:SI (match_operand:SI 1 "d_operand")
1110 (match_operand:SI 2 "const_int_operand")))]
1111 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1112 && REGNO (operands[0]) != REGNO (operands[1])
1113 && ((INTVAL (operands[2]) > 0x7
1114 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1115 || (INTVAL (operands[2]) < - 0x8
1116 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1117 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1118 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1120 HOST_WIDE_INT val = INTVAL (operands[2]);
1124 operands[2] = GEN_INT (0x7);
1125 operands[3] = GEN_INT (val - 0x7);
1129 operands[2] = GEN_INT (- 0x8);
1130 operands[3] = GEN_INT (val + 0x8);
1135 [(set (match_operand:DI 0 "d_operand")
1136 (plus:DI (match_dup 0)
1137 (match_operand:DI 1 "const_int_operand")))]
1138 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1139 && ((INTVAL (operands[1]) > 0xf
1140 && INTVAL (operands[1]) <= 0xf + 0xf)
1141 || (INTVAL (operands[1]) < - 0x10
1142 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1143 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1144 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1146 HOST_WIDE_INT val = INTVAL (operands[1]);
1150 operands[1] = GEN_INT (0xf);
1151 operands[2] = GEN_INT (val - 0xf);
1155 operands[1] = GEN_INT (- 0x10);
1156 operands[2] = GEN_INT (val + 0x10);
1161 [(set (match_operand:DI 0 "d_operand")
1162 (plus:DI (match_operand:DI 1 "d_operand")
1163 (match_operand:DI 2 "const_int_operand")))]
1164 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1165 && REGNO (operands[0]) != REGNO (operands[1])
1166 && ((INTVAL (operands[2]) > 0x7
1167 && INTVAL (operands[2]) <= 0x7 + 0xf)
1168 || (INTVAL (operands[2]) < - 0x8
1169 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1170 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1171 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1173 HOST_WIDE_INT val = INTVAL (operands[2]);
1177 operands[2] = GEN_INT (0x7);
1178 operands[3] = GEN_INT (val - 0x7);
1182 operands[2] = GEN_INT (- 0x8);
1183 operands[3] = GEN_INT (val + 0x8);
1187 (define_insn "*addsi3_extended"
1188 [(set (match_operand:DI 0 "register_operand" "=d,d")
1190 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1191 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1192 "TARGET_64BIT && !TARGET_MIPS16"
1196 [(set_attr "type" "arith")
1197 (set_attr "mode" "SI")])
1199 ;; Split this insn so that the addiu splitters can have a crack at it.
1200 ;; Use a conservative length estimate until the split.
1201 (define_insn_and_split "*addsi3_extended_mips16"
1202 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1204 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1205 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1206 "TARGET_64BIT && TARGET_MIPS16"
1208 "&& reload_completed"
1209 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1210 { operands[3] = gen_lowpart (SImode, operands[0]); }
1211 [(set_attr "type" "arith")
1212 (set_attr "mode" "SI")
1213 (set_attr "extended_mips16" "yes")])
1215 ;; Combiner patterns for unsigned byte-add.
1217 (define_insn "*baddu_si_eb"
1218 [(set (match_operand:SI 0 "register_operand" "=d")
1221 (plus:SI (match_operand:SI 1 "register_operand" "d")
1222 (match_operand:SI 2 "register_operand" "d")) 3)))]
1223 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
1225 [(set_attr "type" "arith")])
1227 (define_insn "*baddu_si_el"
1228 [(set (match_operand:SI 0 "register_operand" "=d")
1231 (plus:SI (match_operand:SI 1 "register_operand" "d")
1232 (match_operand:SI 2 "register_operand" "d")) 0)))]
1233 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
1235 [(set_attr "type" "arith")])
1237 (define_insn "*baddu_di<mode>"
1238 [(set (match_operand:GPR 0 "register_operand" "=d")
1241 (plus:DI (match_operand:DI 1 "register_operand" "d")
1242 (match_operand:DI 2 "register_operand" "d")))))]
1243 "ISA_HAS_BADDU && TARGET_64BIT"
1245 [(set_attr "type" "arith")])
1248 ;; ....................
1252 ;; ....................
1255 (define_insn "sub<mode>3"
1256 [(set (match_operand:ANYF 0 "register_operand" "=f")
1257 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1258 (match_operand:ANYF 2 "register_operand" "f")))]
1260 "sub.<fmt>\t%0,%1,%2"
1261 [(set_attr "type" "fadd")
1262 (set_attr "mode" "<UNITMODE>")])
1264 (define_insn "sub<mode>3"
1265 [(set (match_operand:GPR 0 "register_operand" "=d")
1266 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1267 (match_operand:GPR 2 "register_operand" "d")))]
1270 [(set_attr "type" "arith")
1271 (set_attr "mode" "<MODE>")])
1273 (define_insn "*subsi3_extended"
1274 [(set (match_operand:DI 0 "register_operand" "=d")
1276 (minus:SI (match_operand:SI 1 "register_operand" "d")
1277 (match_operand:SI 2 "register_operand" "d"))))]
1280 [(set_attr "type" "arith")
1281 (set_attr "mode" "DI")])
1284 ;; ....................
1288 ;; ....................
1291 (define_expand "mul<mode>3"
1292 [(set (match_operand:SCALARF 0 "register_operand")
1293 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1294 (match_operand:SCALARF 2 "register_operand")))]
1298 (define_insn "*mul<mode>3"
1299 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1300 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1301 (match_operand:SCALARF 2 "register_operand" "f")))]
1302 "!TARGET_4300_MUL_FIX"
1303 "mul.<fmt>\t%0,%1,%2"
1304 [(set_attr "type" "fmul")
1305 (set_attr "mode" "<MODE>")])
1307 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1308 ;; operands may corrupt immediately following multiplies. This is a
1309 ;; simple fix to insert NOPs.
1311 (define_insn "*mul<mode>3_r4300"
1312 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1313 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1314 (match_operand:SCALARF 2 "register_operand" "f")))]
1315 "TARGET_4300_MUL_FIX"
1316 "mul.<fmt>\t%0,%1,%2\;nop"
1317 [(set_attr "type" "fmul")
1318 (set_attr "mode" "<MODE>")
1319 (set_attr "length" "8")])
1321 (define_insn "mulv2sf3"
1322 [(set (match_operand:V2SF 0 "register_operand" "=f")
1323 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1324 (match_operand:V2SF 2 "register_operand" "f")))]
1325 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1327 [(set_attr "type" "fmul")
1328 (set_attr "mode" "SF")])
1330 ;; The original R4000 has a cpu bug. If a double-word or a variable
1331 ;; shift executes while an integer multiplication is in progress, the
1332 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1333 ;; with the mult on the R4000.
1335 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1336 ;; (also valid for MIPS R4000MC processors):
1338 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1339 ;; this errata description.
1340 ;; The following code sequence causes the R4000 to incorrectly
1341 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1342 ;; instruction. If the dsra32 instruction is executed during an
1343 ;; integer multiply, the dsra32 will only shift by the amount in
1344 ;; specified in the instruction rather than the amount plus 32
1346 ;; instruction 1: mult rs,rt integer multiply
1347 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1348 ;; right arithmetic + 32
1349 ;; Workaround: A dsra32 instruction placed after an integer
1350 ;; multiply should not be one of the 11 instructions after the
1351 ;; multiply instruction."
1355 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1356 ;; the following description.
1357 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1358 ;; 64-bit versions) may produce incorrect results under the
1359 ;; following conditions:
1360 ;; 1) An integer multiply is currently executing
1361 ;; 2) These types of shift instructions are executed immediately
1362 ;; following an integer divide instruction.
1364 ;; 1) Make sure no integer multiply is running wihen these
1365 ;; instruction are executed. If this cannot be predicted at
1366 ;; compile time, then insert a "mfhi" to R0 instruction
1367 ;; immediately after the integer multiply instruction. This
1368 ;; will cause the integer multiply to complete before the shift
1370 ;; 2) Separate integer divide and these two classes of shift
1371 ;; instructions by another instruction or a noop."
1373 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1376 (define_expand "mul<mode>3"
1377 [(set (match_operand:GPR 0 "register_operand")
1378 (mult:GPR (match_operand:GPR 1 "register_operand")
1379 (match_operand:GPR 2 "register_operand")))]
1382 if (TARGET_LOONGSON_2EF)
1383 emit_insn (gen_mul<mode>3_mul3_ls2ef (operands[0], operands[1],
1385 else if (ISA_HAS_<D>MUL3)
1386 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1387 else if (TARGET_FIX_R4000)
1388 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1391 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1395 (define_insn "mul<mode>3_mul3_ls2ef"
1396 [(set (match_operand:GPR 0 "register_operand" "=d")
1397 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1398 (match_operand:GPR 2 "register_operand" "d")))]
1399 "TARGET_LOONGSON_2EF"
1400 "<d>multu.g\t%0,%1,%2"
1401 [(set_attr "type" "imul3nc")
1402 (set_attr "mode" "<MODE>")])
1404 (define_insn "mul<mode>3_mul3"
1405 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1406 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1407 (match_operand:GPR 2 "register_operand" "d,d")))
1408 (clobber (match_scratch:GPR 3 "=l,X"))]
1411 if (which_alternative == 1)
1412 return "<d>mult\t%1,%2";
1413 if (<MODE>mode == SImode && TARGET_MIPS3900)
1414 return "mult\t%0,%1,%2";
1415 return "<d>mul\t%0,%1,%2";
1417 [(set_attr "type" "imul3,imul")
1418 (set_attr "mode" "<MODE>")])
1420 ;; If a register gets allocated to LO, and we spill to memory, the reload
1421 ;; will include a move from LO to a GPR. Merge it into the multiplication
1422 ;; if it can set the GPR directly.
1425 ;; Operand 1: GPR (1st multiplication operand)
1426 ;; Operand 2: GPR (2nd multiplication operand)
1427 ;; Operand 3: GPR (destination)
1430 [(set (match_operand:SI 0 "lo_operand")
1431 (mult:SI (match_operand:SI 1 "d_operand")
1432 (match_operand:SI 2 "d_operand")))
1433 (clobber (scratch:SI))])
1434 (set (match_operand:SI 3 "d_operand")
1436 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1439 (mult:SI (match_dup 1)
1441 (clobber (match_dup 0))])])
1443 (define_insn "mul<mode>3_internal"
1444 [(set (match_operand:GPR 0 "register_operand" "=l")
1445 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1446 (match_operand:GPR 2 "register_operand" "d")))]
1449 [(set_attr "type" "imul")
1450 (set_attr "mode" "<MODE>")])
1452 (define_insn "mul<mode>3_r4000"
1453 [(set (match_operand:GPR 0 "register_operand" "=d")
1454 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1455 (match_operand:GPR 2 "register_operand" "d")))
1456 (clobber (match_scratch:GPR 3 "=l"))]
1458 "<d>mult\t%1,%2\;mflo\t%0"
1459 [(set_attr "type" "imul")
1460 (set_attr "mode" "<MODE>")
1461 (set_attr "length" "8")])
1463 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1464 ;; of "mult; mflo". They have the same latency, but the first form gives
1465 ;; us an extra cycle to compute the operands.
1468 ;; Operand 1: GPR (1st multiplication operand)
1469 ;; Operand 2: GPR (2nd multiplication operand)
1470 ;; Operand 3: GPR (destination)
1472 [(set (match_operand:SI 0 "lo_operand")
1473 (mult:SI (match_operand:SI 1 "d_operand")
1474 (match_operand:SI 2 "d_operand")))
1475 (set (match_operand:SI 3 "d_operand")
1477 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1482 (plus:SI (mult:SI (match_dup 1)
1486 (plus:SI (mult:SI (match_dup 1)
1490 ;; Multiply-accumulate patterns
1492 ;; This pattern is first matched by combine, which tries to use the
1493 ;; pattern wherever it can. We don't know until later whether it
1494 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1495 ;; so we need to keep both options open.
1497 ;; The second alternative has a "?" marker because it is generally
1498 ;; one instruction more costly than the first alternative. This "?"
1499 ;; marker is enough to convey the relative costs to the register
1502 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1503 ;; reloads of the other operands, even though operands 4 and 5 need no
1504 ;; copy instructions. Reload therefore thinks that the second alternative
1505 ;; is two reloads more costly than the first. We add "*?*?" to the first
1506 ;; alternative as a counterweight.
1507 (define_insn "*mul_acc_si"
1508 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1509 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1510 (match_operand:SI 2 "register_operand" "d,d"))
1511 (match_operand:SI 3 "register_operand" "0,d")))
1512 (clobber (match_scratch:SI 4 "=X,l"))
1513 (clobber (match_scratch:SI 5 "=X,&d"))]
1514 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1518 [(set_attr "type" "imadd")
1519 (set_attr "mode" "SI")
1520 (set_attr "length" "4,8")])
1522 ;; The same idea applies here. The middle alternative needs one less
1523 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1524 (define_insn "*mul_acc_si_r3900"
1525 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
1526 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1527 (match_operand:SI 2 "register_operand" "d,d,d"))
1528 (match_operand:SI 3 "register_operand" "0,l,d")))
1529 (clobber (match_scratch:SI 4 "=X,3,l"))
1530 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1531 "TARGET_MIPS3900 && !TARGET_MIPS16"
1536 [(set_attr "type" "imadd")
1537 (set_attr "mode" "SI")
1538 (set_attr "length" "4,4,8")])
1540 ;; Split *mul_acc_si if both the source and destination accumulator
1543 [(set (match_operand:SI 0 "d_operand")
1544 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1545 (match_operand:SI 2 "d_operand"))
1546 (match_operand:SI 3 "d_operand")))
1547 (clobber (match_operand:SI 4 "lo_operand"))
1548 (clobber (match_operand:SI 5 "d_operand"))]
1550 [(parallel [(set (match_dup 5)
1551 (mult:SI (match_dup 1) (match_dup 2)))
1552 (clobber (match_dup 4))])
1553 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1556 (define_insn "*macc"
1557 [(set (match_operand:SI 0 "register_operand" "=l,d")
1558 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1559 (match_operand:SI 2 "register_operand" "d,d"))
1560 (match_operand:SI 3 "register_operand" "0,l")))
1561 (clobber (match_scratch:SI 4 "=X,3"))]
1564 if (which_alternative == 1)
1565 return "macc\t%0,%1,%2";
1566 else if (TARGET_MIPS5500)
1567 return "madd\t%1,%2";
1569 /* The VR4130 assumes that there is a two-cycle latency between a macc
1570 that "writes" to $0 and an instruction that reads from it. We avoid
1571 this by assigning to $1 instead. */
1572 return "%[macc\t%@,%1,%2%]";
1574 [(set_attr "type" "imadd")
1575 (set_attr "mode" "SI")])
1577 (define_insn "*msac"
1578 [(set (match_operand:SI 0 "register_operand" "=l,d")
1579 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1580 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1581 (match_operand:SI 3 "register_operand" "d,d"))))
1582 (clobber (match_scratch:SI 4 "=X,1"))]
1585 if (which_alternative == 1)
1586 return "msac\t%0,%2,%3";
1587 else if (TARGET_MIPS5500)
1588 return "msub\t%2,%3";
1590 return "msac\t$0,%2,%3";
1592 [(set_attr "type" "imadd")
1593 (set_attr "mode" "SI")])
1595 ;; An msac-like instruction implemented using negation and a macc.
1596 (define_insn_and_split "*msac_using_macc"
1597 [(set (match_operand:SI 0 "register_operand" "=l,d")
1598 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1599 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1600 (match_operand:SI 3 "register_operand" "d,d"))))
1601 (clobber (match_scratch:SI 4 "=X,1"))
1602 (clobber (match_scratch:SI 5 "=d,d"))]
1603 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1605 "&& reload_completed"
1607 (neg:SI (match_dup 3)))
1610 (plus:SI (mult:SI (match_dup 2)
1613 (clobber (match_dup 4))])]
1615 [(set_attr "type" "imadd")
1616 (set_attr "length" "8")])
1618 ;; Patterns generated by the define_peephole2 below.
1620 (define_insn "*macc2"
1621 [(set (match_operand:SI 0 "register_operand" "=l")
1622 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1623 (match_operand:SI 2 "register_operand" "d"))
1625 (set (match_operand:SI 3 "register_operand" "=d")
1626 (plus:SI (mult:SI (match_dup 1)
1629 "ISA_HAS_MACC && reload_completed"
1631 [(set_attr "type" "imadd")
1632 (set_attr "mode" "SI")])
1634 (define_insn "*msac2"
1635 [(set (match_operand:SI 0 "register_operand" "=l")
1636 (minus:SI (match_dup 0)
1637 (mult:SI (match_operand:SI 1 "register_operand" "d")
1638 (match_operand:SI 2 "register_operand" "d"))))
1639 (set (match_operand:SI 3 "register_operand" "=d")
1640 (minus:SI (match_dup 0)
1641 (mult:SI (match_dup 1)
1643 "ISA_HAS_MSAC && reload_completed"
1645 [(set_attr "type" "imadd")
1646 (set_attr "mode" "SI")])
1648 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1652 ;; Operand 1: macc/msac
1653 ;; Operand 2: GPR (destination)
1656 [(set (match_operand:SI 0 "lo_operand")
1657 (match_operand:SI 1 "macc_msac_operand"))
1658 (clobber (scratch:SI))])
1659 (set (match_operand:SI 2 "d_operand")
1662 [(parallel [(set (match_dup 0)
1667 ;; When we have a three-address multiplication instruction, it should
1668 ;; be faster to do a separate multiply and add, rather than moving
1669 ;; something into LO in order to use a macc instruction.
1671 ;; This peephole needs a scratch register to cater for the case when one
1672 ;; of the multiplication operands is the same as the destination.
1674 ;; Operand 0: GPR (scratch)
1676 ;; Operand 2: GPR (addend)
1677 ;; Operand 3: GPR (destination)
1678 ;; Operand 4: macc/msac
1679 ;; Operand 5: new multiplication
1680 ;; Operand 6: new addition/subtraction
1682 [(match_scratch:SI 0 "d")
1683 (set (match_operand:SI 1 "lo_operand")
1684 (match_operand:SI 2 "d_operand"))
1687 [(set (match_operand:SI 3 "d_operand")
1688 (match_operand:SI 4 "macc_msac_operand"))
1689 (clobber (match_dup 1))])]
1690 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1691 [(parallel [(set (match_dup 0)
1693 (clobber (match_dup 1))])
1697 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1698 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1699 operands[2], operands[0]);
1702 ;; Same as above, except LO is the initial target of the macc.
1704 ;; Operand 0: GPR (scratch)
1706 ;; Operand 2: GPR (addend)
1707 ;; Operand 3: macc/msac
1708 ;; Operand 4: GPR (destination)
1709 ;; Operand 5: new multiplication
1710 ;; Operand 6: new addition/subtraction
1712 [(match_scratch:SI 0 "d")
1713 (set (match_operand:SI 1 "lo_operand")
1714 (match_operand:SI 2 "d_operand"))
1718 (match_operand:SI 3 "macc_msac_operand"))
1719 (clobber (scratch:SI))])
1721 (set (match_operand:SI 4 "d_operand")
1723 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1724 [(parallel [(set (match_dup 0)
1726 (clobber (match_dup 1))])
1730 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1731 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1732 operands[2], operands[0]);
1735 ;; See the comment above *mul_add_si for details.
1736 (define_insn "*mul_sub_si"
1737 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1738 (minus:SI (match_operand:SI 1 "register_operand" "0,d")
1739 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1740 (match_operand:SI 3 "register_operand" "d,d"))))
1741 (clobber (match_scratch:SI 4 "=X,l"))
1742 (clobber (match_scratch:SI 5 "=X,&d"))]
1743 "GENERATE_MADD_MSUB"
1747 [(set_attr "type" "imadd")
1748 (set_attr "mode" "SI")
1749 (set_attr "length" "4,8")])
1751 ;; Split *mul_sub_si if both the source and destination accumulator
1754 [(set (match_operand:SI 0 "d_operand")
1755 (minus:SI (match_operand:SI 1 "d_operand")
1756 (mult:SI (match_operand:SI 2 "d_operand")
1757 (match_operand:SI 3 "d_operand"))))
1758 (clobber (match_operand:SI 4 "lo_operand"))
1759 (clobber (match_operand:SI 5 "d_operand"))]
1761 [(parallel [(set (match_dup 5)
1762 (mult:SI (match_dup 2) (match_dup 3)))
1763 (clobber (match_dup 4))])
1764 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1767 (define_insn "*muls"
1768 [(set (match_operand:SI 0 "register_operand" "=l,d")
1769 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1770 (match_operand:SI 2 "register_operand" "d,d"))))
1771 (clobber (match_scratch:SI 3 "=X,l"))]
1776 [(set_attr "type" "imul,imul3")
1777 (set_attr "mode" "SI")])
1779 (define_expand "<u>mulsidi3"
1780 [(set (match_operand:DI 0 "register_operand")
1781 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1782 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1783 "!TARGET_64BIT || !TARGET_FIX_R4000"
1786 emit_insn (gen_<u>mulsidi3_64bit (operands[0], operands[1], operands[2]));
1787 else if (TARGET_FIX_R4000)
1788 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1791 emit_insn (gen_<u>mulsidi3_32bit (operands[0], operands[1], operands[2]));
1795 (define_insn "<u>mulsidi3_32bit"
1796 [(set (match_operand:DI 0 "register_operand" "=x")
1797 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1798 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1799 "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
1801 [(set_attr "type" "imul")
1802 (set_attr "mode" "SI")])
1804 (define_insn "<u>mulsidi3_32bit_r4000"
1805 [(set (match_operand:DI 0 "register_operand" "=d")
1806 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1807 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1808 (clobber (match_scratch:DI 3 "=x"))]
1809 "!TARGET_64BIT && TARGET_FIX_R4000"
1810 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
1811 [(set_attr "type" "imul")
1812 (set_attr "mode" "SI")
1813 (set_attr "length" "12")])
1815 (define_insn_and_split "<u>mulsidi3_64bit"
1816 [(set (match_operand:DI 0 "register_operand" "=d")
1817 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1818 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1819 (clobber (match_scratch:TI 3 "=x"))
1820 (clobber (match_scratch:DI 4 "=d"))]
1821 "TARGET_64BIT && !TARGET_FIX_R4000"
1823 "&& reload_completed"
1825 (unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
1826 (any_extend:DI (match_dup 2)))]
1829 ;; OP4 <- LO, OP0 <- HI
1830 (set (match_dup 4) (match_dup 5))
1831 (set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
1835 (ashift:DI (match_dup 4)
1838 (lshiftrt:DI (match_dup 4)
1841 ;; Shift OP0 into place.
1843 (ashift:DI (match_dup 0)
1846 ;; OR the two halves together
1848 (ior:DI (match_dup 0)
1850 { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); }
1851 [(set_attr "type" "imul")
1852 (set_attr "mode" "SI")
1853 (set_attr "length" "24")])
1855 (define_insn "<u>mulsidi3_64bit_hilo"
1856 [(set (match_operand:TI 0 "register_operand" "=x")
1859 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1860 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
1862 "TARGET_64BIT && !TARGET_FIX_R4000"
1864 [(set_attr "type" "imul")
1865 (set_attr "mode" "SI")])
1867 ;; Widening multiply with negation.
1868 (define_insn "*muls<u>_di"
1869 [(set (match_operand:DI 0 "register_operand" "=x")
1872 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1873 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1874 "!TARGET_64BIT && ISA_HAS_MULS"
1876 [(set_attr "type" "imul")
1877 (set_attr "mode" "SI")])
1879 (define_insn "<u>msubsidi4"
1880 [(set (match_operand:DI 0 "register_operand" "=ka")
1882 (match_operand:DI 3 "register_operand" "0")
1884 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1885 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1886 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
1889 return "msub<u>\t%q0,%1,%2";
1890 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1891 return "msub<u>\t%1,%2";
1893 return "msac<u>\t$0,%1,%2";
1895 [(set_attr "type" "imadd")
1896 (set_attr "mode" "SI")])
1898 ;; _highpart patterns
1900 (define_expand "<su>mulsi3_highpart"
1901 [(set (match_operand:SI 0 "register_operand")
1904 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1905 (any_extend:DI (match_operand:SI 2 "register_operand")))
1910 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1914 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1919 (define_insn_and_split "<su>mulsi3_highpart_internal"
1920 [(set (match_operand:SI 0 "register_operand" "=d")
1923 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1924 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1926 (clobber (match_scratch:SI 3 "=l"))]
1928 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1929 "&& reload_completed && !TARGET_FIX_R4000"
1936 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1937 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1938 emit_insn (gen_mfhisi_ti (operands[0], hilo));
1942 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1943 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1944 emit_insn (gen_mfhisi_di (operands[0], hilo));
1948 [(set_attr "type" "imul")
1949 (set_attr "mode" "SI")
1950 (set_attr "length" "8")])
1952 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1953 [(set (match_operand:SI 0 "register_operand" "=d")
1957 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1958 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1960 (clobber (match_scratch:SI 3 "=l"))]
1962 "mulhi<u>\t%0,%1,%2"
1963 [(set_attr "type" "imul3")
1964 (set_attr "mode" "SI")])
1966 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1967 [(set (match_operand:SI 0 "register_operand" "=d")
1972 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1973 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1975 (clobber (match_scratch:SI 3 "=l"))]
1977 "mulshi<u>\t%0,%1,%2"
1978 [(set_attr "type" "imul3")
1979 (set_attr "mode" "SI")])
1981 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1982 ;; errata MD(0), which says that dmultu does not always produce the
1984 (define_insn_and_split "<su>muldi3_highpart"
1985 [(set (match_operand:DI 0 "register_operand" "=d")
1988 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1989 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1991 (clobber (match_scratch:DI 3 "=l"))]
1992 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1993 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1994 "&& reload_completed && !TARGET_FIX_R4000"
1999 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2000 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2001 emit_insn (gen_mfhidi_ti (operands[0], hilo));
2004 [(set_attr "type" "imul")
2005 (set_attr "mode" "DI")
2006 (set_attr "length" "8")])
2008 (define_expand "<u>mulditi3"
2009 [(set (match_operand:TI 0 "register_operand")
2010 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2011 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
2012 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2014 if (TARGET_FIX_R4000)
2015 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2017 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2022 (define_insn "<u>mulditi3_internal"
2023 [(set (match_operand:TI 0 "register_operand" "=x")
2024 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2025 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2027 && !TARGET_FIX_R4000
2028 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2030 [(set_attr "type" "imul")
2031 (set_attr "mode" "DI")])
2033 (define_insn "<u>mulditi3_r4000"
2034 [(set (match_operand:TI 0 "register_operand" "=d")
2035 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2036 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2037 (clobber (match_scratch:TI 3 "=x"))]
2040 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2041 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2042 [(set_attr "type" "imul")
2043 (set_attr "mode" "DI")
2044 (set_attr "length" "12")])
2046 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2047 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2049 (define_insn "madsi"
2050 [(set (match_operand:SI 0 "register_operand" "+l")
2051 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2052 (match_operand:SI 2 "register_operand" "d"))
2056 [(set_attr "type" "imadd")
2057 (set_attr "mode" "SI")])
2059 (define_insn "<u>maddsidi4"
2060 [(set (match_operand:DI 0 "register_operand" "=ka")
2062 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2063 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2064 (match_operand:DI 3 "register_operand" "0")))]
2065 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
2069 return "mad<u>\t%1,%2";
2070 else if (ISA_HAS_DSPR2)
2071 return "madd<u>\t%q0,%1,%2";
2072 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2073 return "madd<u>\t%1,%2";
2075 /* See comment in *macc. */
2076 return "%[macc<u>\t%@,%1,%2%]";
2078 [(set_attr "type" "imadd")
2079 (set_attr "mode" "SI")])
2081 ;; Floating point multiply accumulate instructions.
2083 (define_insn "*madd4<mode>"
2084 [(set (match_operand:ANYF 0 "register_operand" "=f")
2085 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2086 (match_operand:ANYF 2 "register_operand" "f"))
2087 (match_operand:ANYF 3 "register_operand" "f")))]
2088 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2089 "madd.<fmt>\t%0,%3,%1,%2"
2090 [(set_attr "type" "fmadd")
2091 (set_attr "mode" "<UNITMODE>")])
2093 (define_insn "*madd3<mode>"
2094 [(set (match_operand:ANYF 0 "register_operand" "=f")
2095 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2096 (match_operand:ANYF 2 "register_operand" "f"))
2097 (match_operand:ANYF 3 "register_operand" "0")))]
2098 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2099 "madd.<fmt>\t%0,%1,%2"
2100 [(set_attr "type" "fmadd")
2101 (set_attr "mode" "<UNITMODE>")])
2103 (define_insn "*msub4<mode>"
2104 [(set (match_operand:ANYF 0 "register_operand" "=f")
2105 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2106 (match_operand:ANYF 2 "register_operand" "f"))
2107 (match_operand:ANYF 3 "register_operand" "f")))]
2108 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2109 "msub.<fmt>\t%0,%3,%1,%2"
2110 [(set_attr "type" "fmadd")
2111 (set_attr "mode" "<UNITMODE>")])
2113 (define_insn "*msub3<mode>"
2114 [(set (match_operand:ANYF 0 "register_operand" "=f")
2115 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2116 (match_operand:ANYF 2 "register_operand" "f"))
2117 (match_operand:ANYF 3 "register_operand" "0")))]
2118 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2119 "msub.<fmt>\t%0,%1,%2"
2120 [(set_attr "type" "fmadd")
2121 (set_attr "mode" "<UNITMODE>")])
2123 (define_insn "*nmadd4<mode>"
2124 [(set (match_operand:ANYF 0 "register_operand" "=f")
2125 (neg:ANYF (plus:ANYF
2126 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2127 (match_operand:ANYF 2 "register_operand" "f"))
2128 (match_operand:ANYF 3 "register_operand" "f"))))]
2129 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2130 && TARGET_FUSED_MADD
2131 && HONOR_SIGNED_ZEROS (<MODE>mode)
2132 && !HONOR_NANS (<MODE>mode)"
2133 "nmadd.<fmt>\t%0,%3,%1,%2"
2134 [(set_attr "type" "fmadd")
2135 (set_attr "mode" "<UNITMODE>")])
2137 (define_insn "*nmadd3<mode>"
2138 [(set (match_operand:ANYF 0 "register_operand" "=f")
2139 (neg:ANYF (plus:ANYF
2140 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2141 (match_operand:ANYF 2 "register_operand" "f"))
2142 (match_operand:ANYF 3 "register_operand" "0"))))]
2143 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2144 && TARGET_FUSED_MADD
2145 && HONOR_SIGNED_ZEROS (<MODE>mode)
2146 && !HONOR_NANS (<MODE>mode)"
2147 "nmadd.<fmt>\t%0,%1,%2"
2148 [(set_attr "type" "fmadd")
2149 (set_attr "mode" "<UNITMODE>")])
2151 (define_insn "*nmadd4<mode>_fastmath"
2152 [(set (match_operand:ANYF 0 "register_operand" "=f")
2154 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2155 (match_operand:ANYF 2 "register_operand" "f"))
2156 (match_operand:ANYF 3 "register_operand" "f")))]
2157 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2158 && TARGET_FUSED_MADD
2159 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2160 && !HONOR_NANS (<MODE>mode)"
2161 "nmadd.<fmt>\t%0,%3,%1,%2"
2162 [(set_attr "type" "fmadd")
2163 (set_attr "mode" "<UNITMODE>")])
2165 (define_insn "*nmadd3<mode>_fastmath"
2166 [(set (match_operand:ANYF 0 "register_operand" "=f")
2168 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2169 (match_operand:ANYF 2 "register_operand" "f"))
2170 (match_operand:ANYF 3 "register_operand" "0")))]
2171 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2172 && TARGET_FUSED_MADD
2173 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2174 && !HONOR_NANS (<MODE>mode)"
2175 "nmadd.<fmt>\t%0,%1,%2"
2176 [(set_attr "type" "fmadd")
2177 (set_attr "mode" "<UNITMODE>")])
2179 (define_insn "*nmsub4<mode>"
2180 [(set (match_operand:ANYF 0 "register_operand" "=f")
2181 (neg:ANYF (minus:ANYF
2182 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2183 (match_operand:ANYF 3 "register_operand" "f"))
2184 (match_operand:ANYF 1 "register_operand" "f"))))]
2185 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2186 && TARGET_FUSED_MADD
2187 && HONOR_SIGNED_ZEROS (<MODE>mode)
2188 && !HONOR_NANS (<MODE>mode)"
2189 "nmsub.<fmt>\t%0,%1,%2,%3"
2190 [(set_attr "type" "fmadd")
2191 (set_attr "mode" "<UNITMODE>")])
2193 (define_insn "*nmsub3<mode>"
2194 [(set (match_operand:ANYF 0 "register_operand" "=f")
2195 (neg:ANYF (minus:ANYF
2196 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2197 (match_operand:ANYF 3 "register_operand" "f"))
2198 (match_operand:ANYF 1 "register_operand" "0"))))]
2199 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2200 && TARGET_FUSED_MADD
2201 && HONOR_SIGNED_ZEROS (<MODE>mode)
2202 && !HONOR_NANS (<MODE>mode)"
2203 "nmsub.<fmt>\t%0,%1,%2"
2204 [(set_attr "type" "fmadd")
2205 (set_attr "mode" "<UNITMODE>")])
2207 (define_insn "*nmsub4<mode>_fastmath"
2208 [(set (match_operand:ANYF 0 "register_operand" "=f")
2210 (match_operand:ANYF 1 "register_operand" "f")
2211 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2212 (match_operand:ANYF 3 "register_operand" "f"))))]
2213 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2214 && TARGET_FUSED_MADD
2215 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2216 && !HONOR_NANS (<MODE>mode)"
2217 "nmsub.<fmt>\t%0,%1,%2,%3"
2218 [(set_attr "type" "fmadd")
2219 (set_attr "mode" "<UNITMODE>")])
2221 (define_insn "*nmsub3<mode>_fastmath"
2222 [(set (match_operand:ANYF 0 "register_operand" "=f")
2224 (match_operand:ANYF 1 "register_operand" "f")
2225 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2226 (match_operand:ANYF 3 "register_operand" "0"))))]
2227 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2228 && TARGET_FUSED_MADD
2229 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2230 && !HONOR_NANS (<MODE>mode)"
2231 "nmsub.<fmt>\t%0,%1,%2"
2232 [(set_attr "type" "fmadd")
2233 (set_attr "mode" "<UNITMODE>")])
2236 ;; ....................
2238 ;; DIVISION and REMAINDER
2240 ;; ....................
2243 (define_expand "div<mode>3"
2244 [(set (match_operand:ANYF 0 "register_operand")
2245 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2246 (match_operand:ANYF 2 "register_operand")))]
2247 "<divide_condition>"
2249 if (const_1_operand (operands[1], <MODE>mode))
2250 if (!(<recip_condition> && flag_unsafe_math_optimizations))
2251 operands[1] = force_reg (<MODE>mode, operands[1]);
2254 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2256 ;; If an mfc1 or dmfc1 happens to access the floating point register
2257 ;; file at the same time a long latency operation (div, sqrt, recip,
2258 ;; sqrt) iterates an intermediate result back through the floating
2259 ;; point register file bypass, then instead returning the correct
2260 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2261 ;; result of the long latency operation.
2263 ;; The workaround is to insert an unconditional 'mov' from/to the
2264 ;; long latency op destination register.
2266 (define_insn "*div<mode>3"
2267 [(set (match_operand:ANYF 0 "register_operand" "=f")
2268 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2269 (match_operand:ANYF 2 "register_operand" "f")))]
2270 "<divide_condition>"
2273 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2275 return "div.<fmt>\t%0,%1,%2";
2277 [(set_attr "type" "fdiv")
2278 (set_attr "mode" "<UNITMODE>")
2279 (set (attr "length")
2280 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2284 (define_insn "*recip<mode>3"
2285 [(set (match_operand:ANYF 0 "register_operand" "=f")
2286 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2287 (match_operand:ANYF 2 "register_operand" "f")))]
2288 "<recip_condition> && flag_unsafe_math_optimizations"
2291 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2293 return "recip.<fmt>\t%0,%2";
2295 [(set_attr "type" "frdiv")
2296 (set_attr "mode" "<UNITMODE>")
2297 (set (attr "length")
2298 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2302 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2303 ;; with negative operands. We use special libgcc functions instead.
2304 (define_insn_and_split "divmod<mode>4"
2305 [(set (match_operand:GPR 0 "register_operand" "=l")
2306 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2307 (match_operand:GPR 2 "register_operand" "d")))
2308 (set (match_operand:GPR 3 "register_operand" "=d")
2309 (mod:GPR (match_dup 1)
2311 "!TARGET_FIX_VR4120"
2313 "&& reload_completed"
2320 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2321 emit_insn (gen_divmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2322 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2326 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2327 emit_insn (gen_divmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2328 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2332 [(set_attr "type" "idiv")
2333 (set_attr "mode" "<MODE>")
2334 (set_attr "length" "8")])
2336 (define_insn_and_split "udivmod<mode>4"
2337 [(set (match_operand:GPR 0 "register_operand" "=l")
2338 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2339 (match_operand:GPR 2 "register_operand" "d")))
2340 (set (match_operand:GPR 3 "register_operand" "=d")
2341 (umod:GPR (match_dup 1)
2352 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2353 emit_insn (gen_udivmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2354 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2358 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2359 emit_insn (gen_udivmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2360 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2364 [(set_attr "type" "idiv")
2365 (set_attr "mode" "<MODE>")
2366 (set_attr "length" "8")])
2368 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2369 [(set (match_operand:HILO 0 "register_operand" "=x")
2371 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2372 (match_operand:GPR 2 "register_operand" "d"))]
2375 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2376 [(set_attr "type" "idiv")
2377 (set_attr "mode" "<GPR:MODE>")])
2380 ;; ....................
2384 ;; ....................
2386 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2387 ;; "*div[sd]f3" comment for details).
2389 (define_insn "sqrt<mode>2"
2390 [(set (match_operand:ANYF 0 "register_operand" "=f")
2391 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2395 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2397 return "sqrt.<fmt>\t%0,%1";
2399 [(set_attr "type" "fsqrt")
2400 (set_attr "mode" "<UNITMODE>")
2401 (set (attr "length")
2402 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2406 (define_insn "*rsqrt<mode>a"
2407 [(set (match_operand:ANYF 0 "register_operand" "=f")
2408 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2409 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2410 "<recip_condition> && flag_unsafe_math_optimizations"
2413 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2415 return "rsqrt.<fmt>\t%0,%2";
2417 [(set_attr "type" "frsqrt")
2418 (set_attr "mode" "<UNITMODE>")
2419 (set (attr "length")
2420 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2424 (define_insn "*rsqrt<mode>b"
2425 [(set (match_operand:ANYF 0 "register_operand" "=f")
2426 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2427 (match_operand:ANYF 2 "register_operand" "f"))))]
2428 "<recip_condition> && flag_unsafe_math_optimizations"
2431 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2433 return "rsqrt.<fmt>\t%0,%2";
2435 [(set_attr "type" "frsqrt")
2436 (set_attr "mode" "<UNITMODE>")
2437 (set (attr "length")
2438 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2443 ;; ....................
2447 ;; ....................
2449 ;; Do not use the integer abs macro instruction, since that signals an
2450 ;; exception on -2147483648 (sigh).
2452 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2453 ;; invalid; it does not clear their sign bits. We therefore can't use
2454 ;; abs.fmt if the signs of NaNs matter.
2456 (define_insn "abs<mode>2"
2457 [(set (match_operand:ANYF 0 "register_operand" "=f")
2458 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2459 "!HONOR_NANS (<MODE>mode)"
2461 [(set_attr "type" "fabs")
2462 (set_attr "mode" "<UNITMODE>")])
2465 ;; ...................
2467 ;; Count leading zeroes.
2469 ;; ...................
2472 (define_insn "clz<mode>2"
2473 [(set (match_operand:GPR 0 "register_operand" "=d")
2474 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2477 [(set_attr "type" "clz")
2478 (set_attr "mode" "<MODE>")])
2481 ;; ...................
2483 ;; Count number of set bits.
2485 ;; ...................
2488 (define_insn "popcount<mode>2"
2489 [(set (match_operand:GPR 0 "register_operand" "=d")
2490 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
2493 [(set_attr "type" "pop")
2494 (set_attr "mode" "<MODE>")])
2497 ;; ....................
2499 ;; NEGATION and ONE'S COMPLEMENT
2501 ;; ....................
2503 (define_insn "negsi2"
2504 [(set (match_operand:SI 0 "register_operand" "=d")
2505 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2509 return "neg\t%0,%1";
2511 return "subu\t%0,%.,%1";
2513 [(set_attr "type" "arith")
2514 (set_attr "mode" "SI")])
2516 (define_insn "negdi2"
2517 [(set (match_operand:DI 0 "register_operand" "=d")
2518 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2519 "TARGET_64BIT && !TARGET_MIPS16"
2521 [(set_attr "type" "arith")
2522 (set_attr "mode" "DI")])
2524 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2525 ;; invalid; it does not flip their sign bit. We therefore can't use
2526 ;; neg.fmt if the signs of NaNs matter.
2528 (define_insn "neg<mode>2"
2529 [(set (match_operand:ANYF 0 "register_operand" "=f")
2530 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2531 "!HONOR_NANS (<MODE>mode)"
2533 [(set_attr "type" "fneg")
2534 (set_attr "mode" "<UNITMODE>")])
2536 (define_insn "one_cmpl<mode>2"
2537 [(set (match_operand:GPR 0 "register_operand" "=d")
2538 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2542 return "not\t%0,%1";
2544 return "nor\t%0,%.,%1";
2546 [(set_attr "type" "logical")
2547 (set_attr "mode" "<MODE>")])
2550 ;; ....................
2554 ;; ....................
2557 ;; Many of these instructions use trivial define_expands, because we
2558 ;; want to use a different set of constraints when TARGET_MIPS16.
2560 (define_expand "and<mode>3"
2561 [(set (match_operand:GPR 0 "register_operand")
2562 (and:GPR (match_operand:GPR 1 "register_operand")
2563 (match_operand:GPR 2 "uns_arith_operand")))]
2567 operands[2] = force_reg (<MODE>mode, operands[2]);
2570 (define_insn "*and<mode>3"
2571 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2572 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2573 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2578 [(set_attr "type" "logical")
2579 (set_attr "mode" "<MODE>")])
2581 (define_insn "*and<mode>3_mips16"
2582 [(set (match_operand:GPR 0 "register_operand" "=d")
2583 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2584 (match_operand:GPR 2 "register_operand" "d")))]
2587 [(set_attr "type" "logical")
2588 (set_attr "mode" "<MODE>")])
2590 (define_expand "ior<mode>3"
2591 [(set (match_operand:GPR 0 "register_operand")
2592 (ior:GPR (match_operand:GPR 1 "register_operand")
2593 (match_operand:GPR 2 "uns_arith_operand")))]
2597 operands[2] = force_reg (<MODE>mode, operands[2]);
2600 (define_insn "*ior<mode>3"
2601 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2602 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2603 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2608 [(set_attr "type" "logical")
2609 (set_attr "mode" "<MODE>")])
2611 (define_insn "*ior<mode>3_mips16"
2612 [(set (match_operand:GPR 0 "register_operand" "=d")
2613 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2614 (match_operand:GPR 2 "register_operand" "d")))]
2617 [(set_attr "type" "logical")
2618 (set_attr "mode" "<MODE>")])
2620 (define_expand "xor<mode>3"
2621 [(set (match_operand:GPR 0 "register_operand")
2622 (xor:GPR (match_operand:GPR 1 "register_operand")
2623 (match_operand:GPR 2 "uns_arith_operand")))]
2628 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2629 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2630 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2635 [(set_attr "type" "logical")
2636 (set_attr "mode" "<MODE>")])
2639 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2640 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2641 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2647 [(set_attr "type" "logical,arith,arith")
2648 (set_attr "mode" "<MODE>")
2649 (set_attr_alternative "length"
2651 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2656 (define_insn "*nor<mode>3"
2657 [(set (match_operand:GPR 0 "register_operand" "=d")
2658 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2659 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2662 [(set_attr "type" "logical")
2663 (set_attr "mode" "<MODE>")])
2666 ;; ....................
2670 ;; ....................
2674 (define_insn "truncdfsf2"
2675 [(set (match_operand:SF 0 "register_operand" "=f")
2676 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2677 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2679 [(set_attr "type" "fcvt")
2680 (set_attr "cnv_mode" "D2S")
2681 (set_attr "mode" "SF")])
2683 ;; Integer truncation patterns. Truncating SImode values to smaller
2684 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2685 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2686 ;; need to make sure that the lower 32 bits are properly sign-extended
2687 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2688 ;; smaller than SImode is equivalent to two separate truncations:
2691 ;; DI ---> HI == DI ---> SI ---> HI
2692 ;; DI ---> QI == DI ---> SI ---> QI
2694 ;; Step A needs a real instruction but step B does not.
2696 (define_insn "truncdi<mode>2"
2697 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m")
2698 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))]
2703 [(set_attr "move_type" "sll0,store")
2704 (set_attr "mode" "SI")])
2706 ;; Combiner patterns to optimize shift/truncate combinations.
2708 (define_insn "*ashr_trunc<mode>"
2709 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2711 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2712 (match_operand:DI 2 "const_arith_operand" ""))))]
2713 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
2715 [(set_attr "type" "shift")
2716 (set_attr "mode" "<MODE>")])
2718 (define_insn "*lshr32_trunc<mode>"
2719 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2721 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2723 "TARGET_64BIT && !TARGET_MIPS16"
2725 [(set_attr "type" "shift")
2726 (set_attr "mode" "<MODE>")])
2728 ;; Logical shift by 32 or more results in proper SI values so
2729 ;; truncation is removed by the middle end.
2730 (define_insn "*<optab>_trunc<mode>_exts"
2731 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2733 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
2734 (match_operand:DI 2 "const_arith_operand" ""))))]
2735 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
2737 [(set_attr "type" "arith")
2738 (set_attr "mode" "<MODE>")])
2741 ;; ....................
2745 ;; ....................
2749 (define_insn_and_split "zero_extendsidi2"
2750 [(set (match_operand:DI 0 "register_operand" "=d,d")
2751 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2756 "&& reload_completed && REG_P (operands[1])"
2758 (ashift:DI (match_dup 1) (const_int 32)))
2760 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2761 { operands[1] = gen_lowpart (DImode, operands[1]); }
2762 [(set_attr "move_type" "shift_shift,load")
2763 (set_attr "mode" "DI")])
2765 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2766 ;; because of TRULY_NOOP_TRUNCATION.
2768 (define_insn_and_split "*clear_upper32"
2769 [(set (match_operand:DI 0 "register_operand" "=d,d")
2770 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,W")
2771 (const_int 4294967295)))]
2774 if (which_alternative == 0)
2777 operands[1] = gen_lowpart (SImode, operands[1]);
2778 return "lwu\t%0,%1";
2780 "&& reload_completed && REG_P (operands[1])"
2782 (ashift:DI (match_dup 1) (const_int 32)))
2784 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2786 [(set_attr "move_type" "shift_shift,load")
2787 (set_attr "mode" "DI")])
2789 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2790 [(set (match_operand:GPR 0 "register_operand")
2791 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2794 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2795 && !memory_operand (operands[1], <SHORT:MODE>mode))
2797 emit_insn (gen_and<GPR:mode>3 (operands[0],
2798 gen_lowpart (<GPR:MODE>mode, operands[1]),
2799 force_reg (<GPR:MODE>mode,
2800 GEN_INT (<SHORT:mask>))));
2805 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2806 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2808 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2811 andi\t%0,%1,<SHORT:mask>
2812 l<SHORT:size>u\t%0,%1"
2813 [(set_attr "move_type" "andi,load")
2814 (set_attr "mode" "<GPR:MODE>")])
2816 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2817 [(set (match_operand:GPR 0 "register_operand" "=d")
2818 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2820 "ze<SHORT:size>\t%0"
2821 ;; This instruction is effectively a special encoding of ANDI.
2822 [(set_attr "move_type" "andi")
2823 (set_attr "mode" "<GPR:MODE>")])
2825 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2826 [(set (match_operand:GPR 0 "register_operand" "=d")
2827 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2829 "l<SHORT:size>u\t%0,%1"
2830 [(set_attr "move_type" "load")
2831 (set_attr "mode" "<GPR:MODE>")])
2833 (define_expand "zero_extendqihi2"
2834 [(set (match_operand:HI 0 "register_operand")
2835 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2838 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2840 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2846 (define_insn "*zero_extendqihi2"
2847 [(set (match_operand:HI 0 "register_operand" "=d,d")
2848 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2853 [(set_attr "move_type" "andi,load")
2854 (set_attr "mode" "HI")])
2856 (define_insn "*zero_extendqihi2_mips16"
2857 [(set (match_operand:HI 0 "register_operand" "=d")
2858 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2861 [(set_attr "move_type" "load")
2862 (set_attr "mode" "HI")])
2864 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2866 (define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
2867 [(set (match_operand:GPR 0 "register_operand" "=d")
2869 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2870 "TARGET_64BIT && !TARGET_MIPS16"
2872 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
2873 return "andi\t%0,%1,%x2";
2875 [(set_attr "type" "logical")
2876 (set_attr "mode" "<GPR:MODE>")])
2878 (define_insn "*zero_extendhi_truncqi"
2879 [(set (match_operand:HI 0 "register_operand" "=d")
2881 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2882 "TARGET_64BIT && !TARGET_MIPS16"
2884 [(set_attr "type" "logical")
2885 (set_attr "mode" "HI")])
2888 ;; ....................
2892 ;; ....................
2895 ;; Those for integer source operand are ordered widest source type first.
2897 ;; When TARGET_64BIT, all SImode integer registers should already be in
2898 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2899 ;; therefore get rid of register->register instructions if we constrain
2900 ;; the source to be in the same register as the destination.
2902 ;; The register alternative has type "arith" so that the pre-reload
2903 ;; scheduler will treat it as a move. This reflects what happens if
2904 ;; the register alternative needs a reload.
2905 (define_insn_and_split "extendsidi2"
2906 [(set (match_operand:DI 0 "register_operand" "=d,d")
2907 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2912 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2915 emit_note (NOTE_INSN_DELETED);
2918 [(set_attr "move_type" "move,load")
2919 (set_attr "mode" "DI")])
2921 (define_expand "extend<SHORT:mode><GPR:mode>2"
2922 [(set (match_operand:GPR 0 "register_operand")
2923 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2926 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2927 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2928 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2932 l<SHORT:size>\t%0,%1"
2933 [(set_attr "move_type" "signext,load")
2934 (set_attr "mode" "<GPR:MODE>")])
2936 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2937 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2939 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2940 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2943 l<SHORT:size>\t%0,%1"
2944 "&& reload_completed && REG_P (operands[1])"
2945 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2946 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2948 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2949 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2950 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2952 [(set_attr "move_type" "shift_shift,load")
2953 (set_attr "mode" "<GPR:MODE>")])
2955 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2956 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2958 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2961 se<SHORT:size>\t%0,%1
2962 l<SHORT:size>\t%0,%1"
2963 [(set_attr "move_type" "signext,load")
2964 (set_attr "mode" "<GPR:MODE>")])
2966 (define_expand "extendqihi2"
2967 [(set (match_operand:HI 0 "register_operand")
2968 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2971 (define_insn "*extendqihi2_mips16e"
2972 [(set (match_operand:HI 0 "register_operand" "=d,d")
2973 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
2978 [(set_attr "move_type" "signext,load")
2979 (set_attr "mode" "SI")])
2981 (define_insn_and_split "*extendqihi2"
2982 [(set (match_operand:HI 0 "register_operand" "=d,d")
2984 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2985 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2989 "&& reload_completed && REG_P (operands[1])"
2990 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
2991 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
2993 operands[0] = gen_lowpart (SImode, operands[0]);
2994 operands[1] = gen_lowpart (SImode, operands[1]);
2995 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
2996 - GET_MODE_BITSIZE (QImode));
2998 [(set_attr "move_type" "shift_shift,load")
2999 (set_attr "mode" "SI")])
3001 (define_insn "*extendqihi2_seb"
3002 [(set (match_operand:HI 0 "register_operand" "=d,d")
3004 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3009 [(set_attr "move_type" "signext,load")
3010 (set_attr "mode" "SI")])
3012 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
3013 ;; use the shift/truncate patterns.
3015 (define_insn_and_split "*extenddi_truncate<mode>"
3016 [(set (match_operand:DI 0 "register_operand" "=d")
3018 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3019 "TARGET_64BIT && !TARGET_MIPS16"
3023 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode));
3024 return "exts\t%0,%1,0,%m2";
3026 "&& reload_completed && !ISA_HAS_EXTS"
3028 (ashift:DI (match_dup 1)
3031 (ashiftrt:DI (match_dup 2)
3034 operands[2] = gen_lowpart (DImode, operands[0]);
3035 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3037 [(set_attr "type" "arith")
3038 (set_attr "mode" "DI")])
3040 (define_insn_and_split "*extendsi_truncate<mode>"
3041 [(set (match_operand:SI 0 "register_operand" "=d")
3043 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3044 "TARGET_64BIT && !TARGET_MIPS16"
3048 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode));
3049 return "exts\t%0,%1,0,%m2";
3051 "&& reload_completed && !ISA_HAS_EXTS"
3053 (ashift:DI (match_dup 1)
3056 (truncate:SI (ashiftrt:DI (match_dup 2)
3059 operands[2] = gen_lowpart (DImode, operands[0]);
3060 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3062 [(set_attr "type" "arith")
3063 (set_attr "mode" "SI")])
3065 (define_insn_and_split "*extendhi_truncateqi"
3066 [(set (match_operand:HI 0 "register_operand" "=d")
3068 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3069 "TARGET_64BIT && !TARGET_MIPS16"
3071 return ISA_HAS_EXTS ? "exts\t%0,%1,0,7" : "#";
3073 "&& reload_completed && !ISA_HAS_EXTS"
3075 (ashift:DI (match_dup 1)
3078 (truncate:HI (ashiftrt:DI (match_dup 2)
3081 operands[2] = gen_lowpart (DImode, operands[0]);
3083 [(set_attr "type" "arith")
3084 (set_attr "mode" "SI")])
3086 (define_insn "extendsfdf2"
3087 [(set (match_operand:DF 0 "register_operand" "=f")
3088 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3089 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3091 [(set_attr "type" "fcvt")
3092 (set_attr "cnv_mode" "S2D")
3093 (set_attr "mode" "DF")])
3096 ;; ....................
3100 ;; ....................
3102 (define_expand "fix_truncdfsi2"
3103 [(set (match_operand:SI 0 "register_operand")
3104 (fix:SI (match_operand:DF 1 "register_operand")))]
3105 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3107 if (!ISA_HAS_TRUNC_W)
3109 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3114 (define_insn "fix_truncdfsi2_insn"
3115 [(set (match_operand:SI 0 "register_operand" "=f")
3116 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3117 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3119 [(set_attr "type" "fcvt")
3120 (set_attr "mode" "DF")
3121 (set_attr "cnv_mode" "D2I")])
3123 (define_insn "fix_truncdfsi2_macro"
3124 [(set (match_operand:SI 0 "register_operand" "=f")
3125 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3126 (clobber (match_scratch:DF 2 "=d"))]
3127 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3130 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3132 return "trunc.w.d %0,%1,%2";
3134 [(set_attr "type" "fcvt")
3135 (set_attr "mode" "DF")
3136 (set_attr "cnv_mode" "D2I")
3137 (set_attr "length" "36")])
3139 (define_expand "fix_truncsfsi2"
3140 [(set (match_operand:SI 0 "register_operand")
3141 (fix:SI (match_operand:SF 1 "register_operand")))]
3144 if (!ISA_HAS_TRUNC_W)
3146 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3151 (define_insn "fix_truncsfsi2_insn"
3152 [(set (match_operand:SI 0 "register_operand" "=f")
3153 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3154 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3156 [(set_attr "type" "fcvt")
3157 (set_attr "mode" "SF")
3158 (set_attr "cnv_mode" "S2I")])
3160 (define_insn "fix_truncsfsi2_macro"
3161 [(set (match_operand:SI 0 "register_operand" "=f")
3162 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3163 (clobber (match_scratch:SF 2 "=d"))]
3164 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3167 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3169 return "trunc.w.s %0,%1,%2";
3171 [(set_attr "type" "fcvt")
3172 (set_attr "mode" "SF")
3173 (set_attr "cnv_mode" "S2I")
3174 (set_attr "length" "36")])
3177 (define_insn "fix_truncdfdi2"
3178 [(set (match_operand:DI 0 "register_operand" "=f")
3179 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3180 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3182 [(set_attr "type" "fcvt")
3183 (set_attr "mode" "DF")
3184 (set_attr "cnv_mode" "D2I")])
3187 (define_insn "fix_truncsfdi2"
3188 [(set (match_operand:DI 0 "register_operand" "=f")
3189 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3190 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3192 [(set_attr "type" "fcvt")
3193 (set_attr "mode" "SF")
3194 (set_attr "cnv_mode" "S2I")])
3197 (define_insn "floatsidf2"
3198 [(set (match_operand:DF 0 "register_operand" "=f")
3199 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3200 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3202 [(set_attr "type" "fcvt")
3203 (set_attr "mode" "DF")
3204 (set_attr "cnv_mode" "I2D")])
3207 (define_insn "floatdidf2"
3208 [(set (match_operand:DF 0 "register_operand" "=f")
3209 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3210 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3212 [(set_attr "type" "fcvt")
3213 (set_attr "mode" "DF")
3214 (set_attr "cnv_mode" "I2D")])
3217 (define_insn "floatsisf2"
3218 [(set (match_operand:SF 0 "register_operand" "=f")
3219 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3222 [(set_attr "type" "fcvt")
3223 (set_attr "mode" "SF")
3224 (set_attr "cnv_mode" "I2S")])
3227 (define_insn "floatdisf2"
3228 [(set (match_operand:SF 0 "register_operand" "=f")
3229 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3230 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3232 [(set_attr "type" "fcvt")
3233 (set_attr "mode" "SF")
3234 (set_attr "cnv_mode" "I2S")])
3237 (define_expand "fixuns_truncdfsi2"
3238 [(set (match_operand:SI 0 "register_operand")
3239 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3240 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3242 rtx reg1 = gen_reg_rtx (DFmode);
3243 rtx reg2 = gen_reg_rtx (DFmode);
3244 rtx reg3 = gen_reg_rtx (SImode);
3245 rtx label1 = gen_label_rtx ();
3246 rtx label2 = gen_label_rtx ();
3248 REAL_VALUE_TYPE offset;
3250 real_2expN (&offset, 31, DFmode);
3252 if (reg1) /* Turn off complaints about unreached code. */
3254 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3255 do_pending_stack_adjust ();
3257 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3258 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3260 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3261 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3262 gen_rtx_LABEL_REF (VOIDmode, label2)));
3265 emit_label (label1);
3266 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3267 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3268 (BITMASK_HIGH, SImode)));
3270 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3271 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3273 emit_label (label2);
3275 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3276 fields, and can't be used for REG_NOTES anyway). */
3277 emit_use (stack_pointer_rtx);
3283 (define_expand "fixuns_truncdfdi2"
3284 [(set (match_operand:DI 0 "register_operand")
3285 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3286 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3288 rtx reg1 = gen_reg_rtx (DFmode);
3289 rtx reg2 = gen_reg_rtx (DFmode);
3290 rtx reg3 = gen_reg_rtx (DImode);
3291 rtx label1 = gen_label_rtx ();
3292 rtx label2 = gen_label_rtx ();
3294 REAL_VALUE_TYPE offset;
3296 real_2expN (&offset, 63, DFmode);
3298 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3299 do_pending_stack_adjust ();
3301 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3302 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3304 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3305 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3306 gen_rtx_LABEL_REF (VOIDmode, label2)));
3309 emit_label (label1);
3310 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3311 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3312 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3314 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3315 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3317 emit_label (label2);
3319 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3320 fields, and can't be used for REG_NOTES anyway). */
3321 emit_use (stack_pointer_rtx);
3326 (define_expand "fixuns_truncsfsi2"
3327 [(set (match_operand:SI 0 "register_operand")
3328 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
3331 rtx reg1 = gen_reg_rtx (SFmode);
3332 rtx reg2 = gen_reg_rtx (SFmode);
3333 rtx reg3 = gen_reg_rtx (SImode);
3334 rtx label1 = gen_label_rtx ();
3335 rtx label2 = gen_label_rtx ();
3337 REAL_VALUE_TYPE offset;
3339 real_2expN (&offset, 31, SFmode);
3341 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3342 do_pending_stack_adjust ();
3344 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3345 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3347 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3348 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3349 gen_rtx_LABEL_REF (VOIDmode, label2)));
3352 emit_label (label1);
3353 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3354 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3355 (BITMASK_HIGH, SImode)));
3357 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3358 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3360 emit_label (label2);
3362 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3363 fields, and can't be used for REG_NOTES anyway). */
3364 emit_use (stack_pointer_rtx);
3369 (define_expand "fixuns_truncsfdi2"
3370 [(set (match_operand:DI 0 "register_operand")
3371 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3372 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3374 rtx reg1 = gen_reg_rtx (SFmode);
3375 rtx reg2 = gen_reg_rtx (SFmode);
3376 rtx reg3 = gen_reg_rtx (DImode);
3377 rtx label1 = gen_label_rtx ();
3378 rtx label2 = gen_label_rtx ();
3380 REAL_VALUE_TYPE offset;
3382 real_2expN (&offset, 63, SFmode);
3384 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3385 do_pending_stack_adjust ();
3387 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3388 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3390 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3391 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3392 gen_rtx_LABEL_REF (VOIDmode, label2)));
3395 emit_label (label1);
3396 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3397 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3398 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3400 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3401 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3403 emit_label (label2);
3405 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3406 fields, and can't be used for REG_NOTES anyway). */
3407 emit_use (stack_pointer_rtx);
3412 ;; ....................
3416 ;; ....................
3418 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3420 (define_expand "extv"
3421 [(set (match_operand 0 "register_operand")
3422 (sign_extract (match_operand 1 "nonimmediate_operand")
3423 (match_operand 2 "const_int_operand")
3424 (match_operand 3 "const_int_operand")))]
3427 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3428 INTVAL (operands[2]),
3429 INTVAL (operands[3])))
3431 else if (register_operand (operands[1], GET_MODE (operands[0]))
3432 && ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32)
3434 if (GET_MODE (operands[0]) == DImode)
3435 emit_insn (gen_extvdi (operands[0], operands[1], operands[2],
3438 emit_insn (gen_extvsi (operands[0], operands[1], operands[2],
3446 (define_insn "extv<mode>"
3447 [(set (match_operand:GPR 0 "register_operand" "=d")
3448 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3449 (match_operand 2 "const_int_operand" "")
3450 (match_operand 3 "const_int_operand" "")))]
3451 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
3452 "exts\t%0,%1,%3,%m2"
3453 [(set_attr "type" "arith")
3454 (set_attr "mode" "<MODE>")])
3457 (define_expand "extzv"
3458 [(set (match_operand 0 "register_operand")
3459 (zero_extract (match_operand 1 "nonimmediate_operand")
3460 (match_operand 2 "const_int_operand")
3461 (match_operand 3 "const_int_operand")))]
3464 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3465 INTVAL (operands[2]),
3466 INTVAL (operands[3])))
3468 else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3469 INTVAL (operands[3])))
3471 if (GET_MODE (operands[0]) == DImode)
3472 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3475 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3483 (define_insn "extzv<mode>"
3484 [(set (match_operand:GPR 0 "register_operand" "=d")
3485 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3486 (match_operand 2 "const_int_operand" "")
3487 (match_operand 3 "const_int_operand" "")))]
3488 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3489 INTVAL (operands[3]))"
3490 "<d>ext\t%0,%1,%3,%2"
3491 [(set_attr "type" "arith")
3492 (set_attr "mode" "<MODE>")])
3494 (define_insn "*extzv_trunc<mode>_exts"
3495 [(set (match_operand:GPR 0 "register_operand" "=d")
3497 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
3498 (match_operand 2 "const_int_operand" "")
3499 (match_operand 3 "const_int_operand" ""))))]
3500 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3502 [(set_attr "type" "arith")
3503 (set_attr "mode" "<MODE>")])
3506 (define_expand "insv"
3507 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3508 (match_operand 1 "immediate_operand")
3509 (match_operand 2 "immediate_operand"))
3510 (match_operand 3 "reg_or_0_operand"))]
3513 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3514 INTVAL (operands[1]),
3515 INTVAL (operands[2])))
3517 else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3518 INTVAL (operands[2])))
3520 if (GET_MODE (operands[0]) == DImode)
3521 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3524 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3532 (define_insn "insv<mode>"
3533 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3534 (match_operand:SI 1 "immediate_operand" "I")
3535 (match_operand:SI 2 "immediate_operand" "I"))
3536 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3537 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3538 INTVAL (operands[2]))"
3539 "<d>ins\t%0,%z3,%2,%1"
3540 [(set_attr "type" "arith")
3541 (set_attr "mode" "<MODE>")])
3543 ;; Combiner pattern for cins (clear and insert bit field). We can
3544 ;; implement mask-and-shift-left operation with this. Note that if
3545 ;; the upper bit of the mask is set in an SImode operation, the mask
3546 ;; itself will be sign-extended. mask_low_and_shift_len will
3547 ;; therefore be greater than our threshold of 32.
3549 (define_insn "*cins<mode>"
3550 [(set (match_operand:GPR 0 "register_operand" "=d")
3552 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
3553 (match_operand:GPR 2 "const_int_operand" ""))
3554 (match_operand:GPR 3 "const_int_operand" "")))]
3556 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
3559 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
3560 return "cins\t%0,%1,%2,%m3";
3562 [(set_attr "type" "shift")
3563 (set_attr "mode" "<MODE>")])
3565 ;; Unaligned word moves generated by the bit field patterns.
3567 ;; As far as the rtl is concerned, both the left-part and right-part
3568 ;; instructions can access the whole field. However, the real operand
3569 ;; refers to just the first or the last byte (depending on endianness).
3570 ;; We therefore use two memory operands to each instruction, one to
3571 ;; describe the rtl effect and one to use in the assembly output.
3573 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3574 ;; This allows us to use the standard length calculations for the "load"
3575 ;; and "store" type attributes.
3577 (define_insn "mov_<load>l"
3578 [(set (match_operand:GPR 0 "register_operand" "=d")
3579 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3580 (match_operand:QI 2 "memory_operand" "m")]
3582 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3584 [(set_attr "move_type" "load")
3585 (set_attr "mode" "<MODE>")])
3587 (define_insn "mov_<load>r"
3588 [(set (match_operand:GPR 0 "register_operand" "=d")
3589 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3590 (match_operand:QI 2 "memory_operand" "m")
3591 (match_operand:GPR 3 "register_operand" "0")]
3592 UNSPEC_LOAD_RIGHT))]
3593 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3595 [(set_attr "move_type" "load")
3596 (set_attr "mode" "<MODE>")])
3598 (define_insn "mov_<store>l"
3599 [(set (match_operand:BLK 0 "memory_operand" "=m")
3600 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3601 (match_operand:QI 2 "memory_operand" "m")]
3602 UNSPEC_STORE_LEFT))]
3603 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3605 [(set_attr "move_type" "store")
3606 (set_attr "mode" "<MODE>")])
3608 (define_insn "mov_<store>r"
3609 [(set (match_operand:BLK 0 "memory_operand" "+m")
3610 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3611 (match_operand:QI 2 "memory_operand" "m")
3613 UNSPEC_STORE_RIGHT))]
3614 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3616 [(set_attr "move_type" "store")
3617 (set_attr "mode" "<MODE>")])
3619 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3620 ;; The required value is:
3622 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3624 ;; which translates to:
3626 ;; lui op0,%highest(op1)
3627 ;; daddiu op0,op0,%higher(op1)
3629 ;; daddiu op0,op0,%hi(op1)
3632 ;; The split is deferred until after flow2 to allow the peephole2 below
3634 (define_insn_and_split "*lea_high64"
3635 [(set (match_operand:DI 0 "register_operand" "=d")
3636 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3637 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3639 "&& epilogue_completed"
3640 [(set (match_dup 0) (high:DI (match_dup 2)))
3641 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3642 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3643 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3644 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3646 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3647 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3649 [(set_attr "length" "20")])
3651 ;; Use a scratch register to reduce the latency of the above pattern
3652 ;; on superscalar machines. The optimized sequence is:
3654 ;; lui op1,%highest(op2)
3656 ;; daddiu op1,op1,%higher(op2)
3658 ;; daddu op1,op1,op0
3660 [(set (match_operand:DI 1 "d_operand")
3661 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3662 (match_scratch:DI 0 "d")]
3663 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3664 [(set (match_dup 1) (high:DI (match_dup 3)))
3665 (set (match_dup 0) (high:DI (match_dup 4)))
3666 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3667 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3668 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3670 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3671 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3674 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3675 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3676 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3677 ;; used once. We can then use the sequence:
3679 ;; lui op0,%highest(op1)
3681 ;; daddiu op0,op0,%higher(op1)
3682 ;; daddiu op2,op2,%lo(op1)
3684 ;; daddu op0,op0,op2
3686 ;; which takes 4 cycles on most superscalar targets.
3687 (define_insn_and_split "*lea64"
3688 [(set (match_operand:DI 0 "register_operand" "=d")
3689 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3690 (clobber (match_scratch:DI 2 "=&d"))]
3691 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3693 "&& reload_completed"
3694 [(set (match_dup 0) (high:DI (match_dup 3)))
3695 (set (match_dup 2) (high:DI (match_dup 4)))
3696 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3697 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3698 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3699 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3701 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3702 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3704 [(set_attr "length" "24")])
3706 ;; Split HIGHs into:
3711 ;; on MIPS16 targets.
3713 [(set (match_operand:SI 0 "d_operand")
3714 (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))]
3715 "TARGET_MIPS16 && reload_completed"
3716 [(set (match_dup 0) (match_dup 2))
3717 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3719 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3722 ;; Insns to fetch a symbol from a big GOT.
3724 (define_insn_and_split "*xgot_hi<mode>"
3725 [(set (match_operand:P 0 "register_operand" "=d")
3726 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3727 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3729 "&& reload_completed"
3730 [(set (match_dup 0) (high:P (match_dup 2)))
3731 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3733 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3734 operands[3] = pic_offset_table_rtx;
3736 [(set_attr "got" "xgot_high")
3737 (set_attr "mode" "<MODE>")])
3739 (define_insn_and_split "*xgot_lo<mode>"
3740 [(set (match_operand:P 0 "register_operand" "=d")
3741 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3742 (match_operand:P 2 "got_disp_operand" "")))]
3743 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3745 "&& reload_completed"
3747 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3748 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3749 [(set_attr "got" "load")
3750 (set_attr "mode" "<MODE>")])
3752 ;; Insns to fetch a symbol from a normal GOT.
3754 (define_insn_and_split "*got_disp<mode>"
3755 [(set (match_operand:P 0 "register_operand" "=d")
3756 (match_operand:P 1 "got_disp_operand" ""))]
3757 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
3759 "&& reload_completed"
3760 [(set (match_dup 0) (match_dup 2))]
3761 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
3762 [(set_attr "got" "load")
3763 (set_attr "mode" "<MODE>")])
3765 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3767 (define_insn_and_split "*got_page<mode>"
3768 [(set (match_operand:P 0 "register_operand" "=d")
3769 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3770 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
3772 "&& reload_completed"
3773 [(set (match_dup 0) (match_dup 2))]
3774 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
3775 [(set_attr "got" "load")
3776 (set_attr "mode" "<MODE>")])
3778 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
3779 (define_expand "unspec_got<mode>"
3780 [(unspec:P [(match_operand:P 0)
3781 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
3783 ;; Lower-level instructions for loading an address from the GOT.
3784 ;; We could use MEMs, but an unspec gives more optimization
3787 (define_insn "load_got<mode>"
3788 [(set (match_operand:P 0 "register_operand" "=d")
3789 (unspec:P [(match_operand:P 1 "register_operand" "d")
3790 (match_operand:P 2 "immediate_operand" "")]
3793 "<load>\t%0,%R2(%1)"
3794 [(set_attr "got" "load")
3795 (set_attr "mode" "<MODE>")])
3797 ;; Instructions for adding the low 16 bits of an address to a register.
3798 ;; Operand 2 is the address: mips_print_operand works out which relocation
3799 ;; should be applied.
3801 (define_insn "*low<mode>"
3802 [(set (match_operand:P 0 "register_operand" "=d")
3803 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3804 (match_operand:P 2 "immediate_operand" "")))]
3806 "<d>addiu\t%0,%1,%R2"
3807 [(set_attr "type" "arith")
3808 (set_attr "mode" "<MODE>")])
3810 (define_insn "*low<mode>_mips16"
3811 [(set (match_operand:P 0 "register_operand" "=d")
3812 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3813 (match_operand:P 2 "immediate_operand" "")))]
3816 [(set_attr "type" "arith")
3817 (set_attr "mode" "<MODE>")
3818 (set_attr "extended_mips16" "yes")])
3820 ;; Expose MIPS16 uses of the global pointer after reload if the function
3821 ;; is responsible for setting up the register itself.
3823 [(set (match_operand:GPR 0 "d_operand")
3824 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
3825 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
3826 [(set (match_dup 0) (match_dup 1))]
3827 { operands[1] = pic_offset_table_rtx; })
3829 ;; Allow combine to split complex const_int load sequences, using operand 2
3830 ;; to store the intermediate results. See move_operand for details.
3832 [(set (match_operand:GPR 0 "register_operand")
3833 (match_operand:GPR 1 "splittable_const_int_operand"))
3834 (clobber (match_operand:GPR 2 "register_operand"))]
3838 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
3842 ;; Likewise, for symbolic operands.
3844 [(set (match_operand:P 0 "register_operand")
3845 (match_operand:P 1))
3846 (clobber (match_operand:P 2 "register_operand"))]
3847 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3848 [(set (match_dup 0) (match_dup 3))]
3850 mips_split_symbol (operands[2], operands[1],
3851 MAX_MACHINE_MODE, &operands[3]);
3854 ;; 64-bit integer moves
3856 ;; Unlike most other insns, the move insns can't be split with
3857 ;; different predicates, because register spilling and other parts of
3858 ;; the compiler, have memoized the insn number already.
3860 (define_expand "movdi"
3861 [(set (match_operand:DI 0 "")
3862 (match_operand:DI 1 ""))]
3865 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3869 ;; For mips16, we need a special case to handle storing $31 into
3870 ;; memory, since we don't have a constraint to match $31. This
3871 ;; instruction can be generated by save_restore_insns.
3873 (define_insn "*mov<mode>_ra"
3874 [(set (match_operand:GPR 0 "stack_operand" "=m")
3878 [(set_attr "move_type" "store")
3879 (set_attr "mode" "<MODE>")])
3881 (define_insn "*movdi_32bit"
3882 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
3883 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
3884 "!TARGET_64BIT && !TARGET_MIPS16
3885 && (register_operand (operands[0], DImode)
3886 || reg_or_0_operand (operands[1], DImode))"
3887 { return mips_output_move (operands[0], operands[1]); }
3888 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
3889 (set_attr "mode" "DI")])
3891 (define_insn "*movdi_32bit_mips16"
3892 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3893 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3894 "!TARGET_64BIT && TARGET_MIPS16
3895 && (register_operand (operands[0], DImode)
3896 || register_operand (operands[1], DImode))"
3897 { return mips_output_move (operands[0], operands[1]); }
3898 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
3899 (set_attr "mode" "DI")])
3901 (define_insn "*movdi_64bit"
3902 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3903 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3904 "TARGET_64BIT && !TARGET_MIPS16
3905 && (register_operand (operands[0], DImode)
3906 || reg_or_0_operand (operands[1], DImode))"
3907 { return mips_output_move (operands[0], operands[1]); }
3908 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3909 (set_attr "mode" "DI")])
3911 (define_insn "*movdi_64bit_mips16"
3912 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
3913 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
3914 "TARGET_64BIT && TARGET_MIPS16
3915 && (register_operand (operands[0], DImode)
3916 || register_operand (operands[1], DImode))"
3917 { return mips_output_move (operands[0], operands[1]); }
3918 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
3919 (set_attr "mode" "DI")])
3921 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3922 ;; when the original load is a 4 byte instruction but the add and the
3923 ;; load are 2 2 byte instructions.
3926 [(set (match_operand:DI 0 "d_operand")
3927 (mem:DI (plus:DI (match_dup 0)
3928 (match_operand:DI 1 "const_int_operand"))))]
3929 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3930 && !TARGET_DEBUG_D_MODE
3931 && ((INTVAL (operands[1]) < 0
3932 && INTVAL (operands[1]) >= -0x10)
3933 || (INTVAL (operands[1]) >= 32 * 8
3934 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3935 || (INTVAL (operands[1]) >= 0
3936 && INTVAL (operands[1]) < 32 * 8
3937 && (INTVAL (operands[1]) & 7) != 0))"
3938 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3939 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3941 HOST_WIDE_INT val = INTVAL (operands[1]);
3944 operands[2] = const0_rtx;
3945 else if (val >= 32 * 8)
3949 operands[1] = GEN_INT (0x8 + off);
3950 operands[2] = GEN_INT (val - off - 0x8);
3956 operands[1] = GEN_INT (off);
3957 operands[2] = GEN_INT (val - off);
3961 ;; 32-bit Integer moves
3963 ;; Unlike most other insns, the move insns can't be split with
3964 ;; different predicates, because register spilling and other parts of
3965 ;; the compiler, have memoized the insn number already.
3967 (define_expand "mov<mode>"
3968 [(set (match_operand:IMOVE32 0 "")
3969 (match_operand:IMOVE32 1 ""))]
3972 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
3976 ;; The difference between these two is whether or not ints are allowed
3977 ;; in FP registers (off by default, use -mdebugh to enable).
3979 (define_insn "*mov<mode>_internal"
3980 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3981 (match_operand:IMOVE32 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3983 && (register_operand (operands[0], <MODE>mode)
3984 || reg_or_0_operand (operands[1], <MODE>mode))"
3985 { return mips_output_move (operands[0], operands[1]); }
3986 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3987 (set_attr "mode" "SI")])
3989 (define_insn "*mov<mode>_mips16"
3990 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
3991 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
3993 && (register_operand (operands[0], <MODE>mode)
3994 || register_operand (operands[1], <MODE>mode))"
3995 { return mips_output_move (operands[0], operands[1]); }
3996 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
3997 (set_attr "mode" "SI")])
3999 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
4000 ;; when the original load is a 4 byte instruction but the add and the
4001 ;; load are 2 2 byte instructions.
4004 [(set (match_operand:SI 0 "d_operand")
4005 (mem:SI (plus:SI (match_dup 0)
4006 (match_operand:SI 1 "const_int_operand"))))]
4007 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4008 && ((INTVAL (operands[1]) < 0
4009 && INTVAL (operands[1]) >= -0x80)
4010 || (INTVAL (operands[1]) >= 32 * 4
4011 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4012 || (INTVAL (operands[1]) >= 0
4013 && INTVAL (operands[1]) < 32 * 4
4014 && (INTVAL (operands[1]) & 3) != 0))"
4015 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4016 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4018 HOST_WIDE_INT val = INTVAL (operands[1]);
4021 operands[2] = const0_rtx;
4022 else if (val >= 32 * 4)
4026 operands[1] = GEN_INT (0x7c + off);
4027 operands[2] = GEN_INT (val - off - 0x7c);
4033 operands[1] = GEN_INT (off);
4034 operands[2] = GEN_INT (val - off);
4038 ;; On the mips16, we can split a load of certain constants into a load
4039 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4043 [(set (match_operand:SI 0 "d_operand")
4044 (match_operand:SI 1 "const_int_operand"))]
4045 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4046 && INTVAL (operands[1]) >= 0x100
4047 && INTVAL (operands[1]) <= 0xff + 0x7f"
4048 [(set (match_dup 0) (match_dup 1))
4049 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4051 int val = INTVAL (operands[1]);
4053 operands[1] = GEN_INT (0xff);
4054 operands[2] = GEN_INT (val - 0xff);
4057 ;; This insn handles moving CCmode values. It's really just a
4058 ;; slightly simplified copy of movsi_internal2, with additional cases
4059 ;; to move a condition register to a general register and to move
4060 ;; between the general registers and the floating point registers.
4062 (define_insn "movcc"
4063 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
4064 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
4065 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4066 { return mips_output_move (operands[0], operands[1]); }
4067 [(set_attr "move_type" "lui_movf,move,load,store,mfc,mtc,fmove,fpload,fpstore")
4068 (set_attr "mode" "SI")])
4070 ;; Reload condition code registers. reload_incc and reload_outcc
4071 ;; both handle moves from arbitrary operands into condition code
4072 ;; registers. reload_incc handles the more common case in which
4073 ;; a source operand is constrained to be in a condition-code
4074 ;; register, but has not been allocated to one.
4076 ;; Sometimes, such as in movcc, we have a CCmode destination whose
4077 ;; constraints do not include 'z'. reload_outcc handles the case
4078 ;; when such an operand is allocated to a condition-code register.
4080 ;; Note that reloads from a condition code register to some
4081 ;; other location can be done using ordinary moves. Moving
4082 ;; into a GPR takes a single movcc, moving elsewhere takes
4083 ;; two. We can leave these cases to the generic reload code.
4084 (define_expand "reload_incc"
4085 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4086 (match_operand:CC 1 "general_operand" ""))
4087 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4088 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4090 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4094 (define_expand "reload_outcc"
4095 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4096 (match_operand:CC 1 "register_operand" ""))
4097 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4098 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4100 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4104 ;; MIPS4 supports loading and storing a floating point register from
4105 ;; the sum of two general registers. We use two versions for each of
4106 ;; these four instructions: one where the two general registers are
4107 ;; SImode, and one where they are DImode. This is because general
4108 ;; registers will be in SImode when they hold 32-bit values, but,
4109 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4110 ;; instructions will still work correctly.
4112 ;; ??? Perhaps it would be better to support these instructions by
4113 ;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since
4114 ;; these instructions can only be used to load and store floating
4115 ;; point registers, that would probably cause trouble in reload.
4117 (define_insn "*<ANYF:loadx>_<P:mode>"
4118 [(set (match_operand:ANYF 0 "register_operand" "=f")
4119 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4120 (match_operand:P 2 "register_operand" "d"))))]
4122 "<ANYF:loadx>\t%0,%1(%2)"
4123 [(set_attr "type" "fpidxload")
4124 (set_attr "mode" "<ANYF:UNITMODE>")])
4126 (define_insn "*<ANYF:storex>_<P:mode>"
4127 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4128 (match_operand:P 2 "register_operand" "d")))
4129 (match_operand:ANYF 0 "register_operand" "f"))]
4131 "<ANYF:storex>\t%0,%1(%2)"
4132 [(set_attr "type" "fpidxstore")
4133 (set_attr "mode" "<ANYF:UNITMODE>")])
4135 ;; Scaled indexed address load.
4136 ;; Per md.texi, we only need to look for a pattern with multiply in the
4137 ;; address expression, not shift.
4139 (define_insn "*lwxs"
4140 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4142 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
4144 (match_operand:SI 2 "register_operand" "d"))))]
4147 [(set_attr "type" "load")
4148 (set_attr "mode" "SI")])
4150 ;; 16-bit Integer moves
4152 ;; Unlike most other insns, the move insns can't be split with
4153 ;; different predicates, because register spilling and other parts of
4154 ;; the compiler, have memoized the insn number already.
4155 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4157 (define_expand "movhi"
4158 [(set (match_operand:HI 0 "")
4159 (match_operand:HI 1 ""))]
4162 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4166 (define_insn "*movhi_internal"
4167 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4168 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4170 && (register_operand (operands[0], HImode)
4171 || reg_or_0_operand (operands[1], HImode))"
4172 { return mips_output_move (operands[0], operands[1]); }
4173 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4174 (set_attr "mode" "HI")])
4176 (define_insn "*movhi_mips16"
4177 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4178 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4180 && (register_operand (operands[0], HImode)
4181 || register_operand (operands[1], HImode))"
4182 { return mips_output_move (operands[0], operands[1]); }
4183 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4184 (set_attr "mode" "HI")])
4186 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4187 ;; when the original load is a 4 byte instruction but the add and the
4188 ;; load are 2 2 byte instructions.
4191 [(set (match_operand:HI 0 "d_operand")
4192 (mem:HI (plus:SI (match_dup 0)
4193 (match_operand:SI 1 "const_int_operand"))))]
4194 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4195 && ((INTVAL (operands[1]) < 0
4196 && INTVAL (operands[1]) >= -0x80)
4197 || (INTVAL (operands[1]) >= 32 * 2
4198 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4199 || (INTVAL (operands[1]) >= 0
4200 && INTVAL (operands[1]) < 32 * 2
4201 && (INTVAL (operands[1]) & 1) != 0))"
4202 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4203 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4205 HOST_WIDE_INT val = INTVAL (operands[1]);
4208 operands[2] = const0_rtx;
4209 else if (val >= 32 * 2)
4213 operands[1] = GEN_INT (0x7e + off);
4214 operands[2] = GEN_INT (val - off - 0x7e);
4220 operands[1] = GEN_INT (off);
4221 operands[2] = GEN_INT (val - off);
4225 ;; 8-bit Integer moves
4227 ;; Unlike most other insns, the move insns can't be split with
4228 ;; different predicates, because register spilling and other parts of
4229 ;; the compiler, have memoized the insn number already.
4230 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4232 (define_expand "movqi"
4233 [(set (match_operand:QI 0 "")
4234 (match_operand:QI 1 ""))]
4237 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4241 (define_insn "*movqi_internal"
4242 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4243 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4245 && (register_operand (operands[0], QImode)
4246 || reg_or_0_operand (operands[1], QImode))"
4247 { return mips_output_move (operands[0], operands[1]); }
4248 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4249 (set_attr "mode" "QI")])
4251 (define_insn "*movqi_mips16"
4252 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4253 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4255 && (register_operand (operands[0], QImode)
4256 || register_operand (operands[1], QImode))"
4257 { return mips_output_move (operands[0], operands[1]); }
4258 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4259 (set_attr "mode" "QI")])
4261 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4262 ;; when the original load is a 4 byte instruction but the add and the
4263 ;; load are 2 2 byte instructions.
4266 [(set (match_operand:QI 0 "d_operand")
4267 (mem:QI (plus:SI (match_dup 0)
4268 (match_operand:SI 1 "const_int_operand"))))]
4269 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4270 && ((INTVAL (operands[1]) < 0
4271 && INTVAL (operands[1]) >= -0x80)
4272 || (INTVAL (operands[1]) >= 32
4273 && INTVAL (operands[1]) <= 31 + 0x7f))"
4274 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4275 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4277 HOST_WIDE_INT val = INTVAL (operands[1]);
4280 operands[2] = const0_rtx;
4283 operands[1] = GEN_INT (0x7f);
4284 operands[2] = GEN_INT (val - 0x7f);
4288 ;; 32-bit floating point moves
4290 (define_expand "movsf"
4291 [(set (match_operand:SF 0 "")
4292 (match_operand:SF 1 ""))]
4295 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4299 (define_insn "*movsf_hardfloat"
4300 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4301 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4303 && (register_operand (operands[0], SFmode)
4304 || reg_or_0_operand (operands[1], SFmode))"
4305 { return mips_output_move (operands[0], operands[1]); }
4306 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4307 (set_attr "mode" "SF")])
4309 (define_insn "*movsf_softfloat"
4310 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4311 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4312 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4313 && (register_operand (operands[0], SFmode)
4314 || reg_or_0_operand (operands[1], SFmode))"
4315 { return mips_output_move (operands[0], operands[1]); }
4316 [(set_attr "move_type" "move,load,store")
4317 (set_attr "mode" "SF")])
4319 (define_insn "*movsf_mips16"
4320 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4321 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4323 && (register_operand (operands[0], SFmode)
4324 || register_operand (operands[1], SFmode))"
4325 { return mips_output_move (operands[0], operands[1]); }
4326 [(set_attr "move_type" "move,move,move,load,store")
4327 (set_attr "mode" "SF")])
4329 ;; 64-bit floating point moves
4331 (define_expand "movdf"
4332 [(set (match_operand:DF 0 "")
4333 (match_operand:DF 1 ""))]
4336 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4340 (define_insn "*movdf_hardfloat"
4341 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4342 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4343 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
4344 && (register_operand (operands[0], DFmode)
4345 || reg_or_0_operand (operands[1], DFmode))"
4346 { return mips_output_move (operands[0], operands[1]); }
4347 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4348 (set_attr "mode" "DF")])
4350 (define_insn "*movdf_softfloat"
4351 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
4352 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
4353 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4354 && (register_operand (operands[0], DFmode)
4355 || reg_or_0_operand (operands[1], DFmode))"
4356 { return mips_output_move (operands[0], operands[1]); }
4357 [(set_attr "move_type" "move,load,store")
4358 (set_attr "mode" "DF")])
4360 (define_insn "*movdf_mips16"
4361 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4362 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4364 && (register_operand (operands[0], DFmode)
4365 || register_operand (operands[1], DFmode))"
4366 { return mips_output_move (operands[0], operands[1]); }
4367 [(set_attr "move_type" "move,move,move,load,store")
4368 (set_attr "mode" "DF")])
4370 ;; 128-bit integer moves
4372 (define_expand "movti"
4373 [(set (match_operand:TI 0)
4374 (match_operand:TI 1))]
4377 if (mips_legitimize_move (TImode, operands[0], operands[1]))
4381 (define_insn "*movti"
4382 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4383 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*d*J,*a"))]
4386 && (register_operand (operands[0], TImode)
4387 || reg_or_0_operand (operands[1], TImode))"
4389 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4390 (set_attr "mode" "TI")])
4392 (define_insn "*movti_mips16"
4393 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4394 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4397 && (register_operand (operands[0], TImode)
4398 || register_operand (operands[1], TImode))"
4400 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4401 (set_attr "mode" "TI")])
4403 ;; 128-bit floating point moves
4405 (define_expand "movtf"
4406 [(set (match_operand:TF 0)
4407 (match_operand:TF 1))]
4410 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4414 ;; This pattern handles both hard- and soft-float cases.
4415 (define_insn "*movtf"
4416 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4417 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4420 && (register_operand (operands[0], TFmode)
4421 || reg_or_0_operand (operands[1], TFmode))"
4423 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
4424 (set_attr "mode" "TF")])
4426 (define_insn "*movtf_mips16"
4427 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4428 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4431 && (register_operand (operands[0], TFmode)
4432 || register_operand (operands[1], TFmode))"
4434 [(set_attr "move_type" "move,move,move,load,store")
4435 (set_attr "mode" "TF")])
4438 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4439 (match_operand:MOVE64 1 "move_operand"))]
4440 "reload_completed && !TARGET_64BIT
4441 && mips_split_64bit_move_p (operands[0], operands[1])"
4444 mips_split_doubleword_move (operands[0], operands[1]);
4449 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4450 (match_operand:MOVE128 1 "move_operand"))]
4451 "TARGET_64BIT && reload_completed"
4454 mips_split_doubleword_move (operands[0], operands[1]);
4458 ;; When generating mips16 code, split moves of negative constants into
4459 ;; a positive "li" followed by a negation.
4461 [(set (match_operand 0 "d_operand")
4462 (match_operand 1 "const_int_operand"))]
4463 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4467 (neg:SI (match_dup 2)))]
4469 operands[2] = gen_lowpart (SImode, operands[0]);
4470 operands[3] = GEN_INT (-INTVAL (operands[1]));
4473 ;; 64-bit paired-single floating point moves
4475 (define_expand "movv2sf"
4476 [(set (match_operand:V2SF 0)
4477 (match_operand:V2SF 1))]
4478 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4480 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4484 (define_insn "*movv2sf"
4485 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4486 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4488 && TARGET_PAIRED_SINGLE_FLOAT
4489 && (register_operand (operands[0], V2SFmode)
4490 || reg_or_0_operand (operands[1], V2SFmode))"
4491 { return mips_output_move (operands[0], operands[1]); }
4492 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4493 (set_attr "mode" "DF")])
4495 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
4496 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
4498 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
4499 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
4500 ;; and the errata related to -mfix-vr4130.
4501 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
4502 [(set (match_operand:GPR 0 "register_operand" "=d")
4503 (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")]
4506 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
4507 [(set_attr "move_type" "mfhilo")
4508 (set_attr "mode" "<GPR:MODE>")])
4510 ;; Set the high part of a HI/LO value, given that the low part has
4511 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
4512 ;; why we can't just use (reg:GPR HI_REGNUM).
4513 (define_insn "mthi<GPR:mode>_<HILO:mode>"
4514 [(set (match_operand:HILO 0 "register_operand" "=x")
4515 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4516 (match_operand:GPR 2 "register_operand" "l")]
4520 [(set_attr "move_type" "mthilo")
4521 (set_attr "mode" "SI")])
4523 ;; Emit a doubleword move in which exactly one of the operands is
4524 ;; a floating-point register. We can't just emit two normal moves
4525 ;; because of the constraints imposed by the FPU register model;
4526 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4527 ;; the FPR whole and use special patterns to refer to each word of
4528 ;; the other operand.
4530 (define_expand "move_doubleword_fpr<mode>"
4531 [(set (match_operand:SPLITF 0)
4532 (match_operand:SPLITF 1))]
4535 if (FP_REG_RTX_P (operands[0]))
4537 rtx low = mips_subword (operands[1], 0);
4538 rtx high = mips_subword (operands[1], 1);
4539 emit_insn (gen_load_low<mode> (operands[0], low));
4540 if (TARGET_FLOAT64 && !TARGET_64BIT)
4541 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4543 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4547 rtx low = mips_subword (operands[0], 0);
4548 rtx high = mips_subword (operands[0], 1);
4549 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4550 if (TARGET_FLOAT64 && !TARGET_64BIT)
4551 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4553 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4558 ;; Load the low word of operand 0 with operand 1.
4559 (define_insn "load_low<mode>"
4560 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4561 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4565 operands[0] = mips_subword (operands[0], 0);
4566 return mips_output_move (operands[0], operands[1]);
4568 [(set_attr "move_type" "mtc,fpload")
4569 (set_attr "mode" "<HALFMODE>")])
4571 ;; Load the high word of operand 0 from operand 1, preserving the value
4573 (define_insn "load_high<mode>"
4574 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4575 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4576 (match_operand:SPLITF 2 "register_operand" "0,0")]
4580 operands[0] = mips_subword (operands[0], 1);
4581 return mips_output_move (operands[0], operands[1]);
4583 [(set_attr "move_type" "mtc,fpload")
4584 (set_attr "mode" "<HALFMODE>")])
4586 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4587 ;; high word and 0 to store the low word.
4588 (define_insn "store_word<mode>"
4589 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4590 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4591 (match_operand 2 "const_int_operand")]
4592 UNSPEC_STORE_WORD))]
4595 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4596 return mips_output_move (operands[0], operands[1]);
4598 [(set_attr "move_type" "mfc,fpstore")
4599 (set_attr "mode" "<HALFMODE>")])
4601 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4602 ;; value in the low word.
4603 (define_insn "mthc1<mode>"
4604 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4605 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
4606 (match_operand:SPLITF 2 "register_operand" "0")]
4608 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4610 [(set_attr "move_type" "mtc")
4611 (set_attr "mode" "<HALFMODE>")])
4613 ;; Move high word of operand 1 to operand 0 using mfhc1.
4614 (define_insn "mfhc1<mode>"
4615 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4616 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4618 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4620 [(set_attr "move_type" "mfc")
4621 (set_attr "mode" "<HALFMODE>")])
4623 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4624 (define_expand "load_const_gp_<mode>"
4625 [(set (match_operand:P 0 "register_operand" "=d")
4626 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4628 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4629 ;; of _gp from the start of this function. Operand 1 is the incoming
4630 ;; function address.
4631 (define_insn_and_split "loadgp_newabi_<mode>"
4632 [(set (match_operand:P 0 "register_operand" "=d")
4633 (unspec_volatile:P [(match_operand:P 1)
4634 (match_operand:P 2 "register_operand" "d")]
4636 "mips_current_loadgp_style () == LOADGP_NEWABI"
4639 [(set (match_dup 0) (match_dup 3))
4640 (set (match_dup 0) (match_dup 4))
4641 (set (match_dup 0) (match_dup 5))]
4643 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4644 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4645 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4647 [(set_attr "length" "12")])
4649 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4650 (define_insn_and_split "loadgp_absolute_<mode>"
4651 [(set (match_operand:P 0 "register_operand" "=d")
4652 (unspec_volatile:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4653 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4658 mips_emit_move (operands[0], operands[1]);
4661 [(set_attr "length" "8")])
4663 ;; This blockage instruction prevents the gp load from being
4664 ;; scheduled after an implicit use of gp. It also prevents
4665 ;; the load from being deleted as dead.
4666 (define_insn "loadgp_blockage"
4667 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
4670 [(set_attr "type" "ghost")
4671 (set_attr "mode" "none")])
4673 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4674 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4675 (define_insn_and_split "loadgp_rtp_<mode>"
4676 [(set (match_operand:P 0 "register_operand" "=d")
4677 (unspec_volatile:P [(match_operand:P 1 "symbol_ref_operand")
4678 (match_operand:P 2 "symbol_ref_operand")]
4680 "mips_current_loadgp_style () == LOADGP_RTP"
4683 [(set (match_dup 0) (high:P (match_dup 3)))
4684 (set (match_dup 0) (unspec:P [(match_dup 0)
4685 (match_dup 3)] UNSPEC_LOAD_GOT))
4686 (set (match_dup 0) (unspec:P [(match_dup 0)
4687 (match_dup 4)] UNSPEC_LOAD_GOT))]
4689 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
4690 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
4692 [(set_attr "length" "12")])
4694 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
4695 ;; global pointer and operand 1 is the MIPS16 register that holds
4696 ;; the required value.
4697 (define_insn_and_split "copygp_mips16"
4698 [(set (match_operand:SI 0 "register_operand" "=y")
4699 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
4703 "&& reload_completed"
4704 [(set (match_dup 0) (match_dup 1))])
4706 ;; Emit a .cprestore directive, which normally expands to a single store
4707 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4708 ;; code so that jals inside inline asms will work correctly.
4709 (define_insn "cprestore"
4710 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
4715 if (set_nomacro && which_alternative == 1)
4716 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4718 return ".cprestore\t%0";
4720 [(set_attr "type" "store")
4721 (set_attr "length" "4,12")])
4723 ;; Expand in-line code to clear the instruction cache between operand[0] and
4725 (define_expand "clear_cache"
4726 [(match_operand 0 "pmode_register_operand")
4727 (match_operand 1 "pmode_register_operand")]
4733 mips_expand_synci_loop (operands[0], operands[1]);
4734 emit_insn (gen_sync ());
4735 emit_insn (Pmode == SImode
4736 ? gen_clear_hazard_si ()
4737 : gen_clear_hazard_di ());
4739 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4741 rtx len = gen_reg_rtx (Pmode);
4742 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4743 MIPS_ICACHE_SYNC (operands[0], len);
4749 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4753 (define_insn "synci"
4754 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4759 (define_insn "rdhwr_synci_step_<mode>"
4760 [(set (match_operand:P 0 "register_operand" "=d")
4761 (unspec_volatile [(const_int 1)]
4766 (define_insn "clear_hazard_<mode>"
4767 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4768 (clobber (reg:P 31))]
4771 return "%(%<bal\t1f\n"
4773 "1:\t<d>addiu\t$31,$31,12\n"
4777 [(set_attr "length" "20")])
4779 ;; Cache operations for R4000-style caches.
4780 (define_insn "mips_cache"
4781 [(set (mem:BLK (scratch))
4782 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
4783 (match_operand:QI 1 "address_operand" "p")]
4784 UNSPEC_MIPS_CACHE))]
4788 ;; Similar, but with the operands hard-coded to an R10K cache barrier
4789 ;; operation. We keep the pattern distinct so that we can identify
4790 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
4791 ;; the operation is never inserted into a delay slot.
4792 (define_insn "r10k_cache_barrier"
4793 [(set (mem:BLK (scratch))
4794 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
4797 [(set_attr "can_delay" "no")])
4799 ;; Block moves, see mips.c for more details.
4800 ;; Argument 0 is the destination
4801 ;; Argument 1 is the source
4802 ;; Argument 2 is the length
4803 ;; Argument 3 is the alignment
4805 (define_expand "movmemsi"
4806 [(parallel [(set (match_operand:BLK 0 "general_operand")
4807 (match_operand:BLK 1 "general_operand"))
4808 (use (match_operand:SI 2 ""))
4809 (use (match_operand:SI 3 "const_int_operand"))])]
4810 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4812 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4819 ;; ....................
4823 ;; ....................
4825 (define_expand "<optab><mode>3"
4826 [(set (match_operand:GPR 0 "register_operand")
4827 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4828 (match_operand:SI 2 "arith_operand")))]
4831 /* On the mips16, a shift of more than 8 is a four byte instruction,
4832 so, for a shift between 8 and 16, it is just as fast to do two
4833 shifts of 8 or less. If there is a lot of shifting going on, we
4834 may win in CSE. Otherwise combine will put the shifts back
4835 together again. This can be called by mips_function_arg, so we must
4836 be careful not to allocate a new register if we've reached the
4840 && GET_CODE (operands[2]) == CONST_INT
4841 && INTVAL (operands[2]) > 8
4842 && INTVAL (operands[2]) <= 16
4843 && !reload_in_progress
4844 && !reload_completed)
4846 rtx temp = gen_reg_rtx (<MODE>mode);
4848 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4849 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4850 GEN_INT (INTVAL (operands[2]) - 8)));
4855 (define_insn "*<optab><mode>3"
4856 [(set (match_operand:GPR 0 "register_operand" "=d")
4857 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4858 (match_operand:SI 2 "arith_operand" "dI")))]
4861 if (GET_CODE (operands[2]) == CONST_INT)
4862 operands[2] = GEN_INT (INTVAL (operands[2])
4863 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4865 return "<d><insn>\t%0,%1,%2";
4867 [(set_attr "type" "shift")
4868 (set_attr "mode" "<MODE>")])
4870 (define_insn "*<optab>si3_extend"
4871 [(set (match_operand:DI 0 "register_operand" "=d")
4873 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4874 (match_operand:SI 2 "arith_operand" "dI"))))]
4875 "TARGET_64BIT && !TARGET_MIPS16"
4877 if (GET_CODE (operands[2]) == CONST_INT)
4878 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4880 return "<insn>\t%0,%1,%2";
4882 [(set_attr "type" "shift")
4883 (set_attr "mode" "SI")])
4885 (define_insn "*<optab>si3_mips16"
4886 [(set (match_operand:SI 0 "register_operand" "=d,d")
4887 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4888 (match_operand:SI 2 "arith_operand" "d,I")))]
4891 if (which_alternative == 0)
4892 return "<insn>\t%0,%2";
4894 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4895 return "<insn>\t%0,%1,%2";
4897 [(set_attr "type" "shift")
4898 (set_attr "mode" "SI")
4899 (set_attr_alternative "length"
4901 (if_then_else (match_operand 2 "m16_uimm3_b")
4905 ;; We need separate DImode MIPS16 patterns because of the irregularity
4907 (define_insn "*ashldi3_mips16"
4908 [(set (match_operand:DI 0 "register_operand" "=d,d")
4909 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4910 (match_operand:SI 2 "arith_operand" "d,I")))]
4911 "TARGET_64BIT && TARGET_MIPS16"
4913 if (which_alternative == 0)
4914 return "dsll\t%0,%2";
4916 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4917 return "dsll\t%0,%1,%2";
4919 [(set_attr "type" "shift")
4920 (set_attr "mode" "DI")
4921 (set_attr_alternative "length"
4923 (if_then_else (match_operand 2 "m16_uimm3_b")
4927 (define_insn "*ashrdi3_mips16"
4928 [(set (match_operand:DI 0 "register_operand" "=d,d")
4929 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4930 (match_operand:SI 2 "arith_operand" "d,I")))]
4931 "TARGET_64BIT && TARGET_MIPS16"
4933 if (GET_CODE (operands[2]) == CONST_INT)
4934 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4936 return "dsra\t%0,%2";
4938 [(set_attr "type" "shift")
4939 (set_attr "mode" "DI")
4940 (set_attr_alternative "length"
4942 (if_then_else (match_operand 2 "m16_uimm3_b")
4946 (define_insn "*lshrdi3_mips16"
4947 [(set (match_operand:DI 0 "register_operand" "=d,d")
4948 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4949 (match_operand:SI 2 "arith_operand" "d,I")))]
4950 "TARGET_64BIT && TARGET_MIPS16"
4952 if (GET_CODE (operands[2]) == CONST_INT)
4953 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4955 return "dsrl\t%0,%2";
4957 [(set_attr "type" "shift")
4958 (set_attr "mode" "DI")
4959 (set_attr_alternative "length"
4961 (if_then_else (match_operand 2 "m16_uimm3_b")
4965 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4968 [(set (match_operand:GPR 0 "d_operand")
4969 (any_shift:GPR (match_operand:GPR 1 "d_operand")
4970 (match_operand:GPR 2 "const_int_operand")))]
4971 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4972 && INTVAL (operands[2]) > 8
4973 && INTVAL (operands[2]) <= 16"
4974 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4975 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4976 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4978 ;; If we load a byte on the mips16 as a bitfield, the resulting
4979 ;; sequence of instructions is too complicated for combine, because it
4980 ;; involves four instructions: a load, a shift, a constant load into a
4981 ;; register, and an and (the key problem here is that the mips16 does
4982 ;; not have and immediate). We recognize a shift of a load in order
4983 ;; to make it simple enough for combine to understand.
4985 ;; The length here is the worst case: the length of the split version
4986 ;; will be more accurate.
4987 (define_insn_and_split ""
4988 [(set (match_operand:SI 0 "register_operand" "=d")
4989 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4990 (match_operand:SI 2 "immediate_operand" "I")))]
4994 [(set (match_dup 0) (match_dup 1))
4995 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4997 [(set_attr "type" "load")
4998 (set_attr "mode" "SI")
4999 (set_attr "length" "16")])
5001 (define_insn "rotr<mode>3"
5002 [(set (match_operand:GPR 0 "register_operand" "=d")
5003 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
5004 (match_operand:SI 2 "arith_operand" "dI")))]
5007 if (GET_CODE (operands[2]) == CONST_INT)
5008 gcc_assert (INTVAL (operands[2]) >= 0
5009 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5011 return "<d>ror\t%0,%1,%2";
5013 [(set_attr "type" "shift")
5014 (set_attr "mode" "<MODE>")])
5017 ;; ....................
5019 ;; CONDITIONAL BRANCHES
5021 ;; ....................
5023 ;; Conditional branches on floating-point equality tests.
5025 (define_insn "*branch_fp"
5028 (match_operator 0 "equality_operator"
5029 [(match_operand:CC 2 "register_operand" "z")
5031 (label_ref (match_operand 1 "" ""))
5035 return mips_output_conditional_branch (insn, operands,
5036 MIPS_BRANCH ("b%F0", "%Z2%1"),
5037 MIPS_BRANCH ("b%W0", "%Z2%1"));
5039 [(set_attr "type" "branch")
5040 (set_attr "mode" "none")])
5042 (define_insn "*branch_fp_inverted"
5045 (match_operator 0 "equality_operator"
5046 [(match_operand:CC 2 "register_operand" "z")
5049 (label_ref (match_operand 1 "" ""))))]
5052 return mips_output_conditional_branch (insn, operands,
5053 MIPS_BRANCH ("b%W0", "%Z2%1"),
5054 MIPS_BRANCH ("b%F0", "%Z2%1"));
5056 [(set_attr "type" "branch")
5057 (set_attr "mode" "none")])
5059 ;; Conditional branches on ordered comparisons with zero.
5061 (define_insn "*branch_order<mode>"
5064 (match_operator 0 "order_operator"
5065 [(match_operand:GPR 2 "register_operand" "d")
5067 (label_ref (match_operand 1 "" ""))
5070 { return mips_output_order_conditional_branch (insn, operands, false); }
5071 [(set_attr "type" "branch")
5072 (set_attr "mode" "none")])
5074 (define_insn "*branch_order<mode>_inverted"
5077 (match_operator 0 "order_operator"
5078 [(match_operand:GPR 2 "register_operand" "d")
5081 (label_ref (match_operand 1 "" ""))))]
5083 { return mips_output_order_conditional_branch (insn, operands, true); }
5084 [(set_attr "type" "branch")
5085 (set_attr "mode" "none")])
5087 ;; Conditional branch on equality comparison.
5089 (define_insn "*branch_equality<mode>"
5092 (match_operator 0 "equality_operator"
5093 [(match_operand:GPR 2 "register_operand" "d")
5094 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5095 (label_ref (match_operand 1 "" ""))
5099 return mips_output_conditional_branch (insn, operands,
5100 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
5101 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
5103 [(set_attr "type" "branch")
5104 (set_attr "mode" "none")])
5106 (define_insn "*branch_equality<mode>_inverted"
5109 (match_operator 0 "equality_operator"
5110 [(match_operand:GPR 2 "register_operand" "d")
5111 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5113 (label_ref (match_operand 1 "" ""))))]
5116 return mips_output_conditional_branch (insn, operands,
5117 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
5118 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
5120 [(set_attr "type" "branch")
5121 (set_attr "mode" "none")])
5125 (define_insn "*branch_equality<mode>_mips16"
5128 (match_operator 0 "equality_operator"
5129 [(match_operand:GPR 1 "register_operand" "d,t")
5131 (match_operand 2 "pc_or_label_operand" "")
5132 (match_operand 3 "pc_or_label_operand" "")))]
5135 if (operands[2] != pc_rtx)
5137 if (which_alternative == 0)
5138 return "b%C0z\t%1,%2";
5140 return "bt%C0z\t%2";
5144 if (which_alternative == 0)
5145 return "b%N0z\t%1,%3";
5147 return "bt%N0z\t%3";
5150 [(set_attr "type" "branch")
5151 (set_attr "mode" "none")])
5153 (define_expand "cbranch<mode>4"
5155 (if_then_else (match_operator 0 "comparison_operator"
5156 [(match_operand:GPR 1 "register_operand")
5157 (match_operand:GPR 2 "nonmemory_operand")])
5158 (label_ref (match_operand 3 ""))
5162 mips_expand_conditional_branch (operands);
5166 (define_expand "cbranch<mode>4"
5168 (if_then_else (match_operator 0 "comparison_operator"
5169 [(match_operand:SCALARF 1 "register_operand")
5170 (match_operand:SCALARF 2 "register_operand")])
5171 (label_ref (match_operand 3 ""))
5175 mips_expand_conditional_branch (operands);
5179 ;; Used to implement built-in functions.
5180 (define_expand "condjump"
5182 (if_then_else (match_operand 0)
5183 (label_ref (match_operand 1))
5186 ;; Branch if bit is set/clear.
5188 (define_insn "*branch_bit<bbv><mode>"
5191 (equality_op (zero_extract:GPR
5192 (match_operand:GPR 0 "register_operand" "d")
5194 (match_operand 2 "const_int_operand" ""))
5196 (label_ref (match_operand 1 ""))
5198 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5201 mips_output_conditional_branch (insn, operands,
5202 MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1"),
5203 MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1"));
5205 [(set_attr "type" "branch")
5206 (set_attr "mode" "none")
5207 (set_attr "branch_likely" "no")])
5209 (define_insn "*branch_bit<bbv><mode>_inverted"
5212 (equality_op (zero_extract:GPR
5213 (match_operand:GPR 0 "register_operand" "d")
5215 (match_operand 2 "const_int_operand" ""))
5218 (label_ref (match_operand 1 ""))))]
5219 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5222 mips_output_conditional_branch (insn, operands,
5223 MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1"),
5224 MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1"));
5226 [(set_attr "type" "branch")
5227 (set_attr "mode" "none")
5228 (set_attr "branch_likely" "no")])
5231 ;; ....................
5233 ;; SETTING A REGISTER FROM A COMPARISON
5235 ;; ....................
5237 ;; Destination is always set in SI mode.
5239 (define_expand "cstore<mode>4"
5240 [(set (match_operand:SI 0 "register_operand")
5241 (match_operator:SI 1 "mips_cstore_operator"
5242 [(match_operand:GPR 2 "register_operand")
5243 (match_operand:GPR 3 "nonmemory_operand")]))]
5246 mips_expand_scc (operands);
5250 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
5251 [(set (match_operand:GPR2 0 "register_operand" "=d")
5252 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5254 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5256 [(set_attr "type" "slt")
5257 (set_attr "mode" "<GPR:MODE>")])
5259 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
5260 [(set (match_operand:GPR2 0 "register_operand" "=t")
5261 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5263 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5265 [(set_attr "type" "slt")
5266 (set_attr "mode" "<GPR:MODE>")])
5268 ;; Generate sltiu unless using seq results in better code.
5269 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
5270 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5271 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5272 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5278 [(set_attr "type" "slt")
5279 (set_attr "mode" "<GPR:MODE>")])
5281 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
5282 [(set (match_operand:GPR2 0 "register_operand" "=d")
5283 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5285 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5287 [(set_attr "type" "slt")
5288 (set_attr "mode" "<GPR:MODE>")])
5290 ;; Generate sltu unless using sne results in better code.
5291 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
5292 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5293 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5294 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5300 [(set_attr "type" "slt")
5301 (set_attr "mode" "<GPR:MODE>")])
5303 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5304 [(set (match_operand:GPR2 0 "register_operand" "=d")
5305 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5306 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5309 [(set_attr "type" "slt")
5310 (set_attr "mode" "<GPR:MODE>")])
5312 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5313 [(set (match_operand:GPR2 0 "register_operand" "=t")
5314 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5315 (match_operand:GPR 2 "register_operand" "d")))]
5318 [(set_attr "type" "slt")
5319 (set_attr "mode" "<GPR:MODE>")])
5321 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5322 [(set (match_operand:GPR2 0 "register_operand" "=d")
5323 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5327 [(set_attr "type" "slt")
5328 (set_attr "mode" "<GPR:MODE>")])
5330 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5331 [(set (match_operand:GPR2 0 "register_operand" "=d")
5332 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5333 (match_operand:GPR 2 "arith_operand" "dI")))]
5336 [(set_attr "type" "slt")
5337 (set_attr "mode" "<GPR:MODE>")])
5339 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5340 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5341 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5342 (match_operand:GPR 2 "arith_operand" "d,I")))]
5345 [(set_attr "type" "slt")
5346 (set_attr "mode" "<GPR:MODE>")
5347 (set_attr_alternative "length"
5349 (if_then_else (match_operand 2 "m16_uimm8_1")
5353 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5354 [(set (match_operand:GPR2 0 "register_operand" "=d")
5355 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5356 (match_operand:GPR 2 "sle_operand" "")))]
5359 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5360 return "slt<u>\t%0,%1,%2";
5362 [(set_attr "type" "slt")
5363 (set_attr "mode" "<GPR:MODE>")])
5365 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5366 [(set (match_operand:GPR2 0 "register_operand" "=t")
5367 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5368 (match_operand:GPR 2 "sle_operand" "")))]
5371 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5372 return "slt<u>\t%1,%2";
5374 [(set_attr "type" "slt")
5375 (set_attr "mode" "<GPR:MODE>")
5376 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5381 ;; ....................
5383 ;; FLOATING POINT COMPARISONS
5385 ;; ....................
5387 (define_insn "s<code>_<mode>"
5388 [(set (match_operand:CC 0 "register_operand" "=z")
5389 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5390 (match_operand:SCALARF 2 "register_operand" "f")))]
5392 "c.<fcond>.<fmt>\t%Z0%1,%2"
5393 [(set_attr "type" "fcmp")
5394 (set_attr "mode" "FPSW")])
5396 (define_insn "s<code>_<mode>"
5397 [(set (match_operand:CC 0 "register_operand" "=z")
5398 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5399 (match_operand:SCALARF 2 "register_operand" "f")))]
5401 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5402 [(set_attr "type" "fcmp")
5403 (set_attr "mode" "FPSW")])
5406 ;; ....................
5408 ;; UNCONDITIONAL BRANCHES
5410 ;; ....................
5412 ;; Unconditional branches.
5416 (label_ref (match_operand 0 "" "")))]
5421 if (get_attr_length (insn) <= 8)
5422 return "%*b\t%l0%/";
5425 output_asm_insn (mips_output_load_label (), operands);
5426 return "%*jr\t%@%/%]";
5430 return "%*j\t%l0%/";
5432 [(set_attr "type" "jump")
5433 (set_attr "mode" "none")
5434 (set (attr "length")
5435 ;; We can't use `j' when emitting PIC. Emit a branch if it's
5436 ;; in range, otherwise load the address of the branch target into
5437 ;; $at and then jump to it.
5439 (ior (eq (symbol_ref "flag_pic") (const_int 0))
5440 (lt (abs (minus (match_dup 0)
5441 (plus (pc) (const_int 4))))
5442 (const_int 131072)))
5443 (const_int 4) (const_int 16)))])
5445 ;; We need a different insn for the mips16, because a mips16 branch
5446 ;; does not have a delay slot.
5450 (label_ref (match_operand 0 "" "")))]
5453 [(set_attr "type" "branch")
5454 (set_attr "mode" "none")])
5456 (define_expand "indirect_jump"
5457 [(set (pc) (match_operand 0 "register_operand"))]
5460 operands[0] = force_reg (Pmode, operands[0]);
5461 if (Pmode == SImode)
5462 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5464 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5468 (define_insn "indirect_jump<mode>"
5469 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5472 [(set_attr "type" "jump")
5473 (set_attr "mode" "none")])
5475 (define_expand "tablejump"
5477 (match_operand 0 "register_operand"))
5478 (use (label_ref (match_operand 1 "")))]
5481 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5482 operands[0] = expand_binop (Pmode, add_optab,
5483 convert_to_mode (Pmode, operands[0], false),
5484 gen_rtx_LABEL_REF (Pmode, operands[1]),
5486 else if (TARGET_GPWORD)
5487 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5488 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5489 else if (TARGET_RTP_PIC)
5491 /* When generating RTP PIC, we use case table entries that are relative
5492 to the start of the function. Add the function's address to the
5494 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5495 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5496 start, 0, 0, OPTAB_WIDEN);
5499 if (Pmode == SImode)
5500 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5502 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5506 (define_insn "tablejump<mode>"
5508 (match_operand:P 0 "register_operand" "d"))
5509 (use (label_ref (match_operand 1 "" "")))]
5512 [(set_attr "type" "jump")
5513 (set_attr "mode" "none")])
5515 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5516 ;; While it is possible to either pull it off the stack (in the
5517 ;; o32 case) or recalculate it given t9 and our target label,
5518 ;; it takes 3 or 4 insns to do so.
5520 (define_expand "builtin_setjmp_setup"
5521 [(use (match_operand 0 "register_operand"))]
5526 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5527 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5531 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5532 ;; that older code did recalculate the gp from $25. Continue to jump through
5533 ;; $25 for compatibility (we lose nothing by doing so).
5535 (define_expand "builtin_longjmp"
5536 [(use (match_operand 0 "register_operand"))]
5539 /* The elements of the buffer are, in order: */
5540 int W = GET_MODE_SIZE (Pmode);
5541 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5542 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5543 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5544 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5545 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5546 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5547 The target is bound to be using $28 as the global pointer
5548 but the current function might not be. */
5549 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5551 /* This bit is similar to expand_builtin_longjmp except that it
5552 restores $gp as well. */
5553 mips_emit_move (hard_frame_pointer_rtx, fp);
5554 mips_emit_move (pv, lab);
5555 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5556 mips_emit_move (gp, gpv);
5557 emit_use (hard_frame_pointer_rtx);
5558 emit_use (stack_pointer_rtx);
5560 emit_indirect_jump (pv);
5565 ;; ....................
5567 ;; Function prologue/epilogue
5569 ;; ....................
5572 (define_expand "prologue"
5576 mips_expand_prologue ();
5580 ;; Block any insns from being moved before this point, since the
5581 ;; profiling call to mcount can use various registers that aren't
5582 ;; saved or used to pass arguments.
5584 (define_insn "blockage"
5585 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5588 [(set_attr "type" "ghost")
5589 (set_attr "mode" "none")])
5591 (define_expand "epilogue"
5595 mips_expand_epilogue (false);
5599 (define_expand "sibcall_epilogue"
5603 mips_expand_epilogue (true);
5607 ;; Trivial return. Make it look like a normal return insn as that
5608 ;; allows jump optimizations to work better.
5610 (define_expand "return"
5612 "mips_can_use_return_insn ()"
5613 { mips_expand_before_return (); })
5615 (define_insn "*return"
5617 "mips_can_use_return_insn ()"
5619 [(set_attr "type" "jump")
5620 (set_attr "mode" "none")])
5624 (define_insn "return_internal"
5626 (use (match_operand 0 "pmode_register_operand" ""))]
5629 [(set_attr "type" "jump")
5630 (set_attr "mode" "none")])
5632 ;; Exception return.
5633 (define_insn "mips_eret"
5635 (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
5638 [(set_attr "type" "trap")
5639 (set_attr "mode" "none")])
5641 ;; Debug exception return.
5642 (define_insn "mips_deret"
5644 (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
5647 [(set_attr "type" "trap")
5648 (set_attr "mode" "none")])
5650 ;; Disable interrupts.
5651 (define_insn "mips_di"
5652 [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
5655 [(set_attr "type" "trap")
5656 (set_attr "mode" "none")])
5658 ;; Execution hazard barrier.
5659 (define_insn "mips_ehb"
5660 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
5663 [(set_attr "type" "trap")
5664 (set_attr "mode" "none")])
5666 ;; Read GPR from previous shadow register set.
5667 (define_insn "mips_rdpgpr"
5668 [(set (match_operand:SI 0 "register_operand" "=d")
5669 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
5673 [(set_attr "type" "move")
5674 (set_attr "mode" "SI")])
5676 ;; Move involving COP0 registers.
5677 (define_insn "cop0_move"
5678 [(set (match_operand:SI 0 "register_operand" "=B,d")
5679 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
5682 { return mips_output_move (operands[0], operands[1]); }
5683 [(set_attr "type" "mtc,mfc")
5684 (set_attr "mode" "SI")])
5686 ;; This is used in compiling the unwind routines.
5687 (define_expand "eh_return"
5688 [(use (match_operand 0 "general_operand"))]
5691 if (GET_MODE (operands[0]) != word_mode)
5692 operands[0] = convert_to_mode (word_mode, operands[0], 0);
5694 emit_insn (gen_eh_set_lr_di (operands[0]));
5696 emit_insn (gen_eh_set_lr_si (operands[0]));
5700 ;; Clobber the return address on the stack. We can't expand this
5701 ;; until we know where it will be put in the stack frame.
5703 (define_insn "eh_set_lr_si"
5704 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5705 (clobber (match_scratch:SI 1 "=&d"))]
5709 (define_insn "eh_set_lr_di"
5710 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5711 (clobber (match_scratch:DI 1 "=&d"))]
5716 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5717 (clobber (match_scratch 1))]
5721 mips_set_return_address (operands[0], operands[1]);
5725 (define_expand "exception_receiver"
5729 /* See the comment above load_call<mode> for details. */
5730 emit_insn (gen_set_got_version ());
5732 /* If we have a call-clobbered $gp, restore it from its save slot. */
5733 if (HAVE_restore_gp)
5734 emit_insn (gen_restore_gp ());
5738 (define_expand "nonlocal_goto_receiver"
5742 /* See the comment above load_call<mode> for details. */
5743 emit_insn (gen_set_got_version ());
5747 ;; Restore $gp from its .cprestore stack slot. The instruction remains
5748 ;; volatile until all uses of $28 are exposed.
5749 (define_insn_and_split "restore_gp"
5751 (unspec_volatile:SI [(const_int 0)] UNSPEC_RESTORE_GP))
5752 (clobber (match_scratch:SI 0 "=&d"))]
5753 "TARGET_CALL_CLOBBERED_GP"
5755 "&& reload_completed"
5758 mips_restore_gp (operands[0]);
5761 [(set_attr "type" "load")
5762 (set_attr "length" "12")])
5765 ;; ....................
5769 ;; ....................
5771 ;; Instructions to load a call address from the GOT. The address might
5772 ;; point to a function or to a lazy binding stub. In the latter case,
5773 ;; the stub will use the dynamic linker to resolve the function, which
5774 ;; in turn will change the GOT entry to point to the function's real
5777 ;; This means that every call, even pure and constant ones, can
5778 ;; potentially modify the GOT entry. And once a stub has been called,
5779 ;; we must not call it again.
5781 ;; We represent this restriction using an imaginary, fixed, call-saved
5782 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
5783 ;; live throughout the function and to change its value after every
5784 ;; potential call site. This stops any rtx value that uses the register
5785 ;; from being computed before an earlier call. To do this, we:
5787 ;; - Ensure that the register is live on entry to the function,
5788 ;; so that it is never thought to be used uninitalized.
5790 ;; - Ensure that the register is live on exit from the function,
5791 ;; so that it is live throughout.
5793 ;; - Make each call (lazily-bound or not) use the current value
5794 ;; of GOT_VERSION_REGNUM, so that updates of the register are
5795 ;; not moved across call boundaries.
5797 ;; - Add "ghost" definitions of the register to the beginning of
5798 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
5799 ;; edges may involve calls that normal paths don't. (E.g. the
5800 ;; unwinding code that handles a non-call exception may change
5801 ;; lazily-bound GOT entries.) We do this by making the
5802 ;; exception_receiver and nonlocal_goto_receiver expanders emit
5803 ;; a set_got_version instruction.
5805 ;; - After each call (lazily-bound or not), use a "ghost"
5806 ;; update_got_version instruction to change the register's value.
5807 ;; This instruction mimics the _possible_ effect of the dynamic
5808 ;; resolver during the call and it remains live even if the call
5809 ;; itself becomes dead.
5811 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
5812 ;; The register is therefore not a valid register_operand
5813 ;; and cannot be moved to or from other registers.
5815 ;; Convenience expander that generates the rhs of a load_call<mode> insn.
5816 (define_expand "unspec_call<mode>"
5817 [(unspec:P [(match_operand:P 0)
5819 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL)])
5821 (define_insn "load_call<mode>"
5822 [(set (match_operand:P 0 "register_operand" "=d")
5823 (unspec:P [(match_operand:P 1 "register_operand" "d")
5824 (match_operand:P 2 "immediate_operand" "")
5825 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
5827 "<load>\t%0,%R2(%1)"
5828 [(set_attr "got" "load")
5829 (set_attr "mode" "<MODE>")])
5831 (define_insn "set_got_version"
5832 [(set (reg:SI GOT_VERSION_REGNUM)
5833 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
5836 [(set_attr "type" "ghost")])
5838 (define_insn "update_got_version"
5839 [(set (reg:SI GOT_VERSION_REGNUM)
5840 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
5843 [(set_attr "type" "ghost")])
5845 ;; Sibling calls. All these patterns use jump instructions.
5847 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5848 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5849 ;; is defined in terms of call_insn_operand, the same is true of the
5852 ;; When we use an indirect jump, we need a register that will be
5853 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5854 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5855 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5858 (define_expand "sibcall"
5859 [(parallel [(call (match_operand 0 "")
5860 (match_operand 1 ""))
5861 (use (match_operand 2 "")) ;; next_arg_reg
5862 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5865 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
5866 operands[1], operands[2], false);
5870 (define_insn "sibcall_internal"
5871 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5872 (match_operand 1 "" ""))]
5873 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5874 { return MIPS_CALL ("j", operands, 0); }
5875 [(set_attr "type" "call")])
5877 (define_expand "sibcall_value"
5878 [(parallel [(set (match_operand 0 "")
5879 (call (match_operand 1 "")
5880 (match_operand 2 "")))
5881 (use (match_operand 3 ""))])] ;; next_arg_reg
5884 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
5885 operands[2], operands[3], false);
5889 (define_insn "sibcall_value_internal"
5890 [(set (match_operand 0 "register_operand" "")
5891 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5892 (match_operand 2 "" "")))]
5893 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5894 { return MIPS_CALL ("j", operands, 1); }
5895 [(set_attr "type" "call")])
5897 (define_insn "sibcall_value_multiple_internal"
5898 [(set (match_operand 0 "register_operand" "")
5899 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5900 (match_operand 2 "" "")))
5901 (set (match_operand 3 "register_operand" "")
5902 (call (mem:SI (match_dup 1))
5904 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5905 { return MIPS_CALL ("j", operands, 1); }
5906 [(set_attr "type" "call")])
5908 (define_expand "call"
5909 [(parallel [(call (match_operand 0 "")
5910 (match_operand 1 ""))
5911 (use (match_operand 2 "")) ;; next_arg_reg
5912 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5915 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
5916 operands[1], operands[2], false);
5920 ;; This instruction directly corresponds to an assembly-language "jal".
5921 ;; There are four cases:
5924 ;; Both symbolic and register destinations are OK. The pattern
5925 ;; always expands to a single mips instruction.
5927 ;; - -mabicalls/-mno-explicit-relocs:
5928 ;; Again, both symbolic and register destinations are OK.
5929 ;; The call is treated as a multi-instruction black box.
5931 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5932 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5935 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5936 ;; Only "jal $25" is allowed. The call is actually two instructions:
5937 ;; "jalr $25" followed by an insn to reload $gp.
5939 ;; In the last case, we can generate the individual instructions with
5940 ;; a define_split. There are several things to be wary of:
5942 ;; - We can't expose the load of $gp before reload. If we did,
5943 ;; it might get removed as dead, but reload can introduce new
5944 ;; uses of $gp by rematerializing constants.
5946 ;; - We shouldn't restore $gp after calls that never return.
5947 ;; It isn't valid to insert instructions between a noreturn
5948 ;; call and the following barrier.
5950 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5951 ;; instruction preserves $gp and so have no effect on its liveness.
5952 ;; But once we generate the separate insns, it becomes obvious that
5953 ;; $gp is not live on entry to the call.
5955 ;; ??? The operands[2] = insn check is a hack to make the original insn
5956 ;; available to the splitter.
5957 (define_insn_and_split "call_internal"
5958 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5959 (match_operand 1 "" ""))
5960 (clobber (reg:SI 31))]
5962 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5963 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5966 mips_split_call (operands[2], gen_call_split (operands[0], operands[1]));
5969 [(set_attr "jal" "indirect,direct")])
5971 (define_insn "call_split"
5972 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5973 (match_operand 1 "" ""))
5974 (clobber (reg:SI 31))
5975 (clobber (reg:SI 28))]
5976 "TARGET_SPLIT_CALLS"
5977 { return MIPS_CALL ("jal", operands, 0); }
5978 [(set_attr "type" "call")])
5980 ;; A pattern for calls that must be made directly. It is used for
5981 ;; MIPS16 calls that the linker may need to redirect to a hard-float
5982 ;; stub; the linker relies on the call relocation type to detect when
5983 ;; such redirection is needed.
5984 (define_insn_and_split "call_internal_direct"
5985 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
5988 (clobber (reg:SI 31))]
5990 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5991 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5994 mips_split_call (operands[2],
5995 gen_call_direct_split (operands[0], operands[1]));
5998 [(set_attr "type" "call")])
6000 (define_insn "call_direct_split"
6001 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6004 (clobber (reg:SI 31))
6005 (clobber (reg:SI 28))]
6006 "TARGET_SPLIT_CALLS"
6007 { return MIPS_CALL ("jal", operands, 0); }
6008 [(set_attr "type" "call")])
6010 (define_expand "call_value"
6011 [(parallel [(set (match_operand 0 "")
6012 (call (match_operand 1 "")
6013 (match_operand 2 "")))
6014 (use (match_operand 3 ""))])] ;; next_arg_reg
6017 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
6018 operands[2], operands[3], false);
6022 ;; See comment for call_internal.
6023 (define_insn_and_split "call_value_internal"
6024 [(set (match_operand 0 "register_operand" "")
6025 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6026 (match_operand 2 "" "")))
6027 (clobber (reg:SI 31))]
6029 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6030 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
6033 mips_split_call (operands[3],
6034 gen_call_value_split (operands[0], operands[1],
6038 [(set_attr "jal" "indirect,direct")])
6040 (define_insn "call_value_split"
6041 [(set (match_operand 0 "register_operand" "")
6042 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6043 (match_operand 2 "" "")))
6044 (clobber (reg:SI 31))
6045 (clobber (reg:SI 28))]
6046 "TARGET_SPLIT_CALLS"
6047 { return MIPS_CALL ("jal", operands, 1); }
6048 [(set_attr "type" "call")])
6050 ;; See call_internal_direct.
6051 (define_insn_and_split "call_value_internal_direct"
6052 [(set (match_operand 0 "register_operand")
6053 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6056 (clobber (reg:SI 31))]
6058 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6059 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
6062 mips_split_call (operands[3],
6063 gen_call_value_direct_split (operands[0], operands[1],
6067 [(set_attr "type" "call")])
6069 (define_insn "call_value_direct_split"
6070 [(set (match_operand 0 "register_operand")
6071 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6074 (clobber (reg:SI 31))
6075 (clobber (reg:SI 28))]
6076 "TARGET_SPLIT_CALLS"
6077 { return MIPS_CALL ("jal", operands, 1); }
6078 [(set_attr "type" "call")])
6080 ;; See comment for call_internal.
6081 (define_insn_and_split "call_value_multiple_internal"
6082 [(set (match_operand 0 "register_operand" "")
6083 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6084 (match_operand 2 "" "")))
6085 (set (match_operand 3 "register_operand" "")
6086 (call (mem:SI (match_dup 1))
6088 (clobber (reg:SI 31))]
6090 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6091 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
6094 mips_split_call (operands[4],
6095 gen_call_value_multiple_split (operands[0], operands[1],
6096 operands[2], operands[3]));
6099 [(set_attr "jal" "indirect,direct")])
6101 (define_insn "call_value_multiple_split"
6102 [(set (match_operand 0 "register_operand" "")
6103 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6104 (match_operand 2 "" "")))
6105 (set (match_operand 3 "register_operand" "")
6106 (call (mem:SI (match_dup 1))
6108 (clobber (reg:SI 31))
6109 (clobber (reg:SI 28))]
6110 "TARGET_SPLIT_CALLS"
6111 { return MIPS_CALL ("jal", operands, 1); }
6112 [(set_attr "type" "call")])
6114 ;; Call subroutine returning any type.
6116 (define_expand "untyped_call"
6117 [(parallel [(call (match_operand 0 "")
6119 (match_operand 1 "")
6120 (match_operand 2 "")])]
6125 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6127 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6129 rtx set = XVECEXP (operands[2], 0, i);
6130 mips_emit_move (SET_DEST (set), SET_SRC (set));
6133 emit_insn (gen_blockage ());
6138 ;; ....................
6142 ;; ....................
6146 (define_insn "prefetch"
6147 [(prefetch (match_operand:QI 0 "address_operand" "p")
6148 (match_operand 1 "const_int_operand" "n")
6149 (match_operand 2 "const_int_operand" "n"))]
6150 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6152 if (TARGET_LOONGSON_2EF)
6153 /* Loongson 2[ef] use load to $0 to perform prefetching. */
6154 return "ld\t$0,%a0";
6155 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6156 return "pref\t%1,%a0";
6158 [(set_attr "type" "prefetch")])
6160 (define_insn "*prefetch_indexed_<mode>"
6161 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6162 (match_operand:P 1 "register_operand" "d"))
6163 (match_operand 2 "const_int_operand" "n")
6164 (match_operand 3 "const_int_operand" "n"))]
6165 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6167 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6168 return "prefx\t%2,%1(%0)";
6170 [(set_attr "type" "prefetchx")])
6176 [(set_attr "type" "nop")
6177 (set_attr "mode" "none")])
6179 ;; Like nop, but commented out when outside a .set noreorder block.
6180 (define_insn "hazard_nop"
6189 [(set_attr "type" "nop")])
6191 ;; MIPS4 Conditional move instructions.
6193 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6194 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6196 (match_operator:MOVECC 4 "equality_operator"
6197 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6199 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6200 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6205 [(set_attr "type" "condmove")
6206 (set_attr "mode" "<GPR:MODE>")])
6208 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6209 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6210 (if_then_else:SCALARF
6211 (match_operator:MOVECC 4 "equality_operator"
6212 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6214 (match_operand:SCALARF 2 "register_operand" "f,0")
6215 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6216 "ISA_HAS_FP_CONDMOVE"
6218 mov%T4.<fmt>\t%0,%2,%1
6219 mov%t4.<fmt>\t%0,%3,%1"
6220 [(set_attr "type" "condmove")
6221 (set_attr "mode" "<SCALARF:MODE>")])
6223 ;; These are the main define_expand's used to make conditional moves.
6225 (define_expand "mov<mode>cc"
6226 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6227 (set (match_operand:GPR 0 "register_operand")
6228 (if_then_else:GPR (match_dup 5)
6229 (match_operand:GPR 2 "reg_or_0_operand")
6230 (match_operand:GPR 3 "reg_or_0_operand")))]
6233 mips_expand_conditional_move (operands);
6237 (define_expand "mov<mode>cc"
6238 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6239 (set (match_operand:SCALARF 0 "register_operand")
6240 (if_then_else:SCALARF (match_dup 5)
6241 (match_operand:SCALARF 2 "register_operand")
6242 (match_operand:SCALARF 3 "register_operand")))]
6243 "ISA_HAS_FP_CONDMOVE"
6245 mips_expand_conditional_move (operands);
6250 ;; ....................
6252 ;; mips16 inline constant tables
6254 ;; ....................
6257 (define_insn "consttable_int"
6258 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6259 (match_operand 1 "const_int_operand" "")]
6260 UNSPEC_CONSTTABLE_INT)]
6263 assemble_integer (operands[0], INTVAL (operands[1]),
6264 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6267 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6269 (define_insn "consttable_float"
6270 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6271 UNSPEC_CONSTTABLE_FLOAT)]
6276 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6277 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6278 assemble_real (d, GET_MODE (operands[0]),
6279 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6282 [(set (attr "length")
6283 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6285 (define_insn "align"
6286 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6289 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6292 [(match_operand 0 "small_data_pattern")]
6295 { operands[0] = mips_rewrite_small_data (operands[0]); })
6298 ;; ....................
6300 ;; MIPS16e Save/Restore
6302 ;; ....................
6305 (define_insn "*mips16e_save_restore"
6306 [(match_parallel 0 ""
6307 [(set (match_operand:SI 1 "register_operand")
6308 (plus:SI (match_dup 1)
6309 (match_operand:SI 2 "const_int_operand")))])]
6310 "operands[1] == stack_pointer_rtx
6311 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6312 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6313 [(set_attr "type" "arith")
6314 (set_attr "extended_mips16" "yes")])
6316 ;; Thread-Local Storage
6318 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
6319 ;; MIPS architecture defines this register, and no current
6320 ;; implementation provides it; instead, any OS which supports TLS is
6321 ;; expected to trap and emulate this instruction. rdhwr is part of the
6322 ;; MIPS 32r2 specification, but we use it on any architecture because
6323 ;; we expect it to be emulated. Use .set to force the assembler to
6326 ;; We do not use a constraint to force the destination to be $3
6327 ;; because $3 can appear explicitly as a function return value.
6328 ;; If we leave the use of $3 implicit in the constraints until
6329 ;; reload, we may end up making a $3 return value live across
6330 ;; the instruction, leading to a spill failure when reloading it.
6331 (define_insn_and_split "tls_get_tp_<mode>"
6332 [(set (match_operand:P 0 "register_operand" "=d")
6333 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6334 (clobber (reg:P TLS_GET_TP_REGNUM))]
6335 "HAVE_AS_TLS && !TARGET_MIPS16"
6337 "&& reload_completed"
6338 [(set (reg:P TLS_GET_TP_REGNUM)
6339 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6340 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6342 [(set_attr "type" "unknown")
6343 ; Since rdhwr always generates a trap for now, putting it in a delay
6344 ; slot would make the kernel's emulation of it much slower.
6345 (set_attr "can_delay" "no")
6346 (set_attr "mode" "<MODE>")
6347 (set_attr "length" "8")])
6349 (define_insn "*tls_get_tp_<mode>_split"
6350 [(set (reg:P TLS_GET_TP_REGNUM)
6351 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
6352 "HAVE_AS_TLS && !TARGET_MIPS16"
6353 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
6354 [(set_attr "type" "unknown")
6355 ; See tls_get_tp_<mode>
6356 (set_attr "can_delay" "no")
6357 (set_attr "mode" "<MODE>")])
6359 ;; Synchronization instructions.
6363 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6365 (include "mips-ps-3d.md")
6367 ; The MIPS DSP Instructions.
6369 (include "mips-dsp.md")
6371 ; The MIPS DSP REV 2 Instructions.
6373 (include "mips-dspr2.md")
6375 ; MIPS fixed-point instructions.
6376 (include "mips-fixed.md")
6378 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6379 (include "loongson.md")