1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
27 [(UNSPEC_LOAD_DF_LOW 0)
28 (UNSPEC_LOAD_DF_HIGH 1)
29 (UNSPEC_STORE_DF_HIGH 2)
33 (UNSPEC_NONLOCAL_GOTO_RECEIVER 6)
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_TLS_GET_TP 28)
52 (UNSPEC_CLEAR_HAZARD 33)
57 (UNSPEC_ADDRESS_FIRST 100)
61 ;; For MIPS Paired-Singled Floating Point Instructions.
63 (UNSPEC_MOVE_TF_PS 200)
66 ;; MIPS64/MIPS32R2 alnv.ps
69 ;; MIPS-3D instructions
73 (UNSPEC_CVT_PW_PS 205)
74 (UNSPEC_CVT_PS_PW 206)
82 (UNSPEC_SINGLE_CC 213)
85 ;; MIPS DSP ASE Revision 0.98 3/24/2005
93 (UNSPEC_RADDU_W_QB 307)
95 (UNSPEC_PRECRQ_QB_PH 309)
96 (UNSPEC_PRECRQ_PH_W 310)
97 (UNSPEC_PRECRQ_RS_PH_W 311)
98 (UNSPEC_PRECRQU_S_QB_PH 312)
99 (UNSPEC_PRECEQ_W_PHL 313)
100 (UNSPEC_PRECEQ_W_PHR 314)
101 (UNSPEC_PRECEQU_PH_QBL 315)
102 (UNSPEC_PRECEQU_PH_QBR 316)
103 (UNSPEC_PRECEQU_PH_QBLA 317)
104 (UNSPEC_PRECEQU_PH_QBRA 318)
105 (UNSPEC_PRECEU_PH_QBL 319)
106 (UNSPEC_PRECEU_PH_QBR 320)
107 (UNSPEC_PRECEU_PH_QBLA 321)
108 (UNSPEC_PRECEU_PH_QBRA 322)
114 (UNSPEC_MULEU_S_PH_QBL 328)
115 (UNSPEC_MULEU_S_PH_QBR 329)
116 (UNSPEC_MULQ_RS_PH 330)
117 (UNSPEC_MULEQ_S_W_PHL 331)
118 (UNSPEC_MULEQ_S_W_PHR 332)
119 (UNSPEC_DPAU_H_QBL 333)
120 (UNSPEC_DPAU_H_QBR 334)
121 (UNSPEC_DPSU_H_QBL 335)
122 (UNSPEC_DPSU_H_QBR 336)
123 (UNSPEC_DPAQ_S_W_PH 337)
124 (UNSPEC_DPSQ_S_W_PH 338)
125 (UNSPEC_MULSAQ_S_W_PH 339)
126 (UNSPEC_DPAQ_SA_L_W 340)
127 (UNSPEC_DPSQ_SA_L_W 341)
128 (UNSPEC_MAQ_S_W_PHL 342)
129 (UNSPEC_MAQ_S_W_PHR 343)
130 (UNSPEC_MAQ_SA_W_PHL 344)
131 (UNSPEC_MAQ_SA_W_PHR 345)
139 (UNSPEC_CMPGU_EQ_QB 353)
140 (UNSPEC_CMPGU_LT_QB 354)
141 (UNSPEC_CMPGU_LE_QB 355)
143 (UNSPEC_PACKRL_PH 357)
145 (UNSPEC_EXTR_R_W 359)
146 (UNSPEC_EXTR_RS_W 360)
147 (UNSPEC_EXTR_S_H 361)
155 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
156 (UNSPEC_ABSQ_S_QB 400)
158 (UNSPEC_ADDU_S_PH 402)
159 (UNSPEC_ADDUH_QB 403)
160 (UNSPEC_ADDUH_R_QB 404)
163 (UNSPEC_CMPGDU_EQ_QB 407)
164 (UNSPEC_CMPGDU_LT_QB 408)
165 (UNSPEC_CMPGDU_LE_QB 409)
166 (UNSPEC_DPA_W_PH 410)
167 (UNSPEC_DPS_W_PH 411)
173 (UNSPEC_MUL_S_PH 417)
174 (UNSPEC_MULQ_RS_W 418)
175 (UNSPEC_MULQ_S_PH 419)
176 (UNSPEC_MULQ_S_W 420)
177 (UNSPEC_MULSA_W_PH 421)
180 (UNSPEC_PRECR_QB_PH 424)
181 (UNSPEC_PRECR_SRA_PH_W 425)
182 (UNSPEC_PRECR_SRA_R_PH_W 426)
185 (UNSPEC_SHRA_R_QB 429)
188 (UNSPEC_SUBU_S_PH 432)
189 (UNSPEC_SUBUH_QB 433)
190 (UNSPEC_SUBUH_R_QB 434)
191 (UNSPEC_ADDQH_PH 435)
192 (UNSPEC_ADDQH_R_PH 436)
194 (UNSPEC_ADDQH_R_W 438)
195 (UNSPEC_SUBQH_PH 439)
196 (UNSPEC_SUBQH_R_PH 440)
198 (UNSPEC_SUBQH_R_W 442)
199 (UNSPEC_DPAX_W_PH 443)
200 (UNSPEC_DPSX_W_PH 444)
201 (UNSPEC_DPAQX_S_W_PH 445)
202 (UNSPEC_DPAQX_SA_W_PH 446)
203 (UNSPEC_DPSQX_S_W_PH 447)
204 (UNSPEC_DPSQX_SA_W_PH 448)
208 (include "predicates.md")
209 (include "constraints.md")
211 ;; ....................
215 ;; ....................
217 (define_attr "got" "unset,xgot_high,load"
218 (const_string "unset"))
220 ;; For jal instructions, this attribute is DIRECT when the target address
221 ;; is symbolic and INDIRECT when it is a register.
222 (define_attr "jal" "unset,direct,indirect"
223 (const_string "unset"))
225 ;; This attribute is YES if the instruction is a jal macro (not a
226 ;; real jal instruction).
228 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
229 ;; an instruction to restore $gp. Direct jals are also macros for
230 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
231 ;; the target address into a register.
232 (define_attr "jal_macro" "no,yes"
233 (cond [(eq_attr "jal" "direct")
234 (symbol_ref "TARGET_CALL_CLOBBERED_GP
235 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
236 (eq_attr "jal" "indirect")
237 (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
238 (const_string "no")))
240 ;; Classification of each insn.
241 ;; branch conditional branch
242 ;; jump unconditional jump
243 ;; call unconditional call
244 ;; load load instruction(s)
245 ;; fpload floating point load
246 ;; fpidxload floating point indexed load
247 ;; store store instruction(s)
248 ;; fpstore floating point store
249 ;; fpidxstore floating point indexed store
250 ;; prefetch memory prefetch (register + offset)
251 ;; prefetchx memory indexed prefetch (register + register)
252 ;; condmove conditional moves
253 ;; mfc transfer from coprocessor
254 ;; mtc transfer to coprocessor
255 ;; mthilo transfer to hi/lo registers
256 ;; mfhilo transfer from hi/lo registers
257 ;; const load constant
258 ;; arith integer arithmetic instructions
259 ;; logical integer logical instructions
260 ;; shift integer shift instructions
261 ;; slt set less than instructions
262 ;; signext sign extend instructions
263 ;; clz the clz and clo instructions
264 ;; trap trap if instructions
265 ;; imul integer multiply 2 operands
266 ;; imul3 integer multiply 3 operands
267 ;; imadd integer multiply-add
268 ;; idiv integer divide
269 ;; move integer register move ({,D}ADD{,U} with rt = 0)
270 ;; fmove floating point register move
271 ;; fadd floating point add/subtract
272 ;; fmul floating point multiply
273 ;; fmadd floating point multiply-add
274 ;; fdiv floating point divide
275 ;; frdiv floating point reciprocal divide
276 ;; frdiv1 floating point reciprocal divide step 1
277 ;; frdiv2 floating point reciprocal divide step 2
278 ;; fabs floating point absolute value
279 ;; fneg floating point negation
280 ;; fcmp floating point compare
281 ;; fcvt floating point convert
282 ;; fsqrt floating point square root
283 ;; frsqrt floating point reciprocal square root
284 ;; frsqrt1 floating point reciprocal square root step1
285 ;; frsqrt2 floating point reciprocal square root step2
286 ;; multi multiword sequence (or user asm statements)
289 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,logical,shift,slt,signext,clz,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
290 (cond [(eq_attr "jal" "!unset") (const_string "call")
291 (eq_attr "got" "load") (const_string "load")]
292 (const_string "unknown")))
294 ;; Main data type used by the insn
295 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
296 (const_string "unknown"))
298 ;; Mode for conversion types (fcvt)
299 ;; I2S integer to float single (SI/DI to SF)
300 ;; I2D integer to float double (SI/DI to DF)
301 ;; S2I float to integer (SF to SI/DI)
302 ;; D2I float to integer (DF to SI/DI)
303 ;; D2S double to float single
304 ;; S2D float single to double
306 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
307 (const_string "unknown"))
309 ;; Is this an extended instruction in mips16 mode?
310 (define_attr "extended_mips16" "no,yes"
313 ;; Length of instruction in bytes.
314 (define_attr "length" ""
315 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
316 ;; If a branch is outside this range, we have a choice of two
317 ;; sequences. For PIC, an out-of-range branch like:
322 ;; becomes the equivalent of:
331 ;; where the load address can be up to three instructions long
334 ;; The non-PIC case is similar except that we use a direct
335 ;; jump instead of an la/jr pair. Since the target of this
336 ;; jump is an absolute 28-bit bit address (the other bits
337 ;; coming from the address of the delay slot) this form cannot
338 ;; cross a 256MB boundary. We could provide the option of
339 ;; using la/jr in this case too, but we do not do so at
342 ;; Note that this value does not account for the delay slot
343 ;; instruction, whose length is added separately. If the RTL
344 ;; pattern has no explicit delay slot, mips_adjust_insn_length
345 ;; will add the length of the implicit nop. The values for
346 ;; forward and backward branches will be different as well.
347 (eq_attr "type" "branch")
348 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
349 (le (minus (pc) (match_dup 1)) (const_int 131068)))
351 (ne (symbol_ref "flag_pic") (const_int 0))
355 (eq_attr "got" "load")
357 (eq_attr "got" "xgot_high")
360 (eq_attr "type" "const")
361 (symbol_ref "mips_const_insns (operands[1]) * 4")
362 (eq_attr "type" "load,fpload")
363 (symbol_ref "mips_fetch_insns (operands[1]) * 4")
364 (eq_attr "type" "store,fpstore")
365 (symbol_ref "mips_fetch_insns (operands[0]) * 4")
367 ;; In the worst case, a call macro will take 8 instructions:
369 ;; lui $25,%call_hi(FOO)
371 ;; lw $25,%call_lo(FOO)($25)
377 (eq_attr "jal_macro" "yes")
380 (and (eq_attr "extended_mips16" "yes")
381 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
384 ;; Various VR4120 errata require a nop to be inserted after a macc
385 ;; instruction. The assembler does this for us, so account for
386 ;; the worst-case length here.
387 (and (eq_attr "type" "imadd")
388 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
391 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
392 ;; the result of the second one is missed. The assembler should work
393 ;; around this by inserting a nop after the first dmult.
394 (and (eq_attr "type" "imul,imul3")
395 (and (eq_attr "mode" "DI")
396 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
399 (eq_attr "type" "idiv")
400 (symbol_ref "mips_idiv_insns () * 4")
403 ;; Attribute describing the processor. This attribute must match exactly
404 ;; with the processor_type enumeration in mips.h.
406 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
407 (const (symbol_ref "mips_tune")))
409 ;; The type of hardware hazard associated with this instruction.
410 ;; DELAY means that the next instruction cannot read the result
411 ;; of this one. HILO means that the next two instructions cannot
412 ;; write to HI or LO.
413 (define_attr "hazard" "none,delay,hilo"
414 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
415 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
416 (const_string "delay")
418 (and (eq_attr "type" "mfc,mtc")
419 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
420 (const_string "delay")
422 (and (eq_attr "type" "fcmp")
423 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
424 (const_string "delay")
426 ;; The r4000 multiplication patterns include an mflo instruction.
427 (and (eq_attr "type" "imul")
428 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
429 (const_string "hilo")
431 (and (eq_attr "type" "mfhilo")
432 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
433 (const_string "hilo")]
434 (const_string "none")))
436 ;; Is it a single instruction?
437 (define_attr "single_insn" "no,yes"
438 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
440 ;; Can the instruction be put into a delay slot?
441 (define_attr "can_delay" "no,yes"
442 (if_then_else (and (eq_attr "type" "!branch,call,jump")
443 (and (eq_attr "hazard" "none")
444 (eq_attr "single_insn" "yes")))
446 (const_string "no")))
448 ;; Attribute defining whether or not we can use the branch-likely instructions
449 (define_attr "branch_likely" "no,yes"
451 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
453 (const_string "no"))))
455 ;; True if an instruction might assign to hi or lo when reloaded.
456 ;; This is used by the TUNE_MACC_CHAINS code.
457 (define_attr "may_clobber_hilo" "no,yes"
458 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
460 (const_string "no")))
462 ;; Describe a user's asm statement.
463 (define_asm_attributes
464 [(set_attr "type" "multi")
465 (set_attr "can_delay" "no")])
467 ;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated
468 ;; from the same template.
469 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
471 ;; This mode macro allows :P to be used for patterns that operate on
472 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
473 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
475 ;; This mode macro allows :MOVECC to be used anywhere that a
476 ;; conditional-move-type condition is needed.
477 (define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
479 ;; This mode macro allows the QI and HI extension patterns to be defined from
480 ;; the same template.
481 (define_mode_macro SHORT [QI HI])
483 ;; This mode macro allows :ANYF to be used wherever a scalar or vector
484 ;; floating-point mode is allowed.
485 (define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
486 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
487 (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
489 ;; Like ANYF, but only applies to scalar modes.
490 (define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")
491 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
493 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
494 ;; 32-bit version and "dsubu" in the 64-bit version.
495 (define_mode_attr d [(SI "") (DI "d")])
497 ;; This attribute gives the length suffix for a sign- or zero-extension
499 (define_mode_attr size [(QI "b") (HI "h")])
501 ;; This attributes gives the mode mask of a SHORT.
502 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
504 ;; Mode attributes for GPR loads and stores.
505 (define_mode_attr load [(SI "lw") (DI "ld")])
506 (define_mode_attr store [(SI "sw") (DI "sd")])
508 ;; Similarly for MIPS IV indexed FPR loads and stores.
509 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
510 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
512 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
513 ;; are different. Some forms of unextended addiu have an 8-bit immediate
514 ;; field but the equivalent daddiu has only a 5-bit field.
515 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
517 ;; This attribute gives the best constraint to use for registers of
519 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
521 ;; This attribute gives the format suffix for floating-point operations.
522 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
524 ;; This attribute gives the upper-case mode name for one unit of a
525 ;; floating-point mode.
526 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
528 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
530 ;; In certain cases, div.s and div.ps may have a rounding error
531 ;; and/or wrong inexact flag.
533 ;; Therefore, we only allow div.s if not working around SB-1 rev2
534 ;; errata or if a slight loss of precision is OK.
535 (define_mode_attr divide_condition
536 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
537 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
539 ; This attribute gives the condition for which sqrt instructions exist.
540 (define_mode_attr sqrt_condition
541 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
543 ; This attribute gives the condition for which recip and rsqrt instructions
545 (define_mode_attr recip_condition
546 [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
548 ;; This code macro allows all branch instructions to be generated from
549 ;; a single define_expand template.
550 (define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
551 eq ne gt ge lt le gtu geu ltu leu])
553 ;; This code macro allows signed and unsigned widening multiplications
554 ;; to use the same template.
555 (define_code_macro any_extend [sign_extend zero_extend])
557 ;; This code macro allows the three shift instructions to be generated
558 ;; from the same template.
559 (define_code_macro any_shift [ashift ashiftrt lshiftrt])
561 ;; This code macro allows all native floating-point comparisons to be
562 ;; generated from the same template.
563 (define_code_macro fcond [unordered uneq unlt unle eq lt le])
565 ;; This code macro is used for comparisons that can be implemented
566 ;; by swapping the operands.
567 (define_code_macro swapped_fcond [ge gt unge ungt])
569 ;; <u> expands to an empty string when doing a signed operation and
570 ;; "u" when doing an unsigned operation.
571 (define_code_attr u [(sign_extend "") (zero_extend "u")])
573 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
574 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
576 ;; <optab> expands to the name of the optab for a particular code.
577 (define_code_attr optab [(ashift "ashl")
581 ;; <insn> expands to the name of the insn that implements a particular code.
582 (define_code_attr insn [(ashift "sll")
586 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
587 (define_code_attr fcond [(unordered "un")
595 ;; Similar, but for swapped conditions.
596 (define_code_attr swapped_fcond [(ge "le")
601 ;; .........................
603 ;; Branch, call and jump delay slots
605 ;; .........................
607 (define_delay (and (eq_attr "type" "branch")
608 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
609 [(eq_attr "can_delay" "yes")
611 (and (eq_attr "branch_likely" "yes")
612 (eq_attr "can_delay" "yes"))])
614 (define_delay (eq_attr "type" "jump")
615 [(eq_attr "can_delay" "yes")
619 (define_delay (and (eq_attr "type" "call")
620 (eq_attr "jal_macro" "no"))
621 [(eq_attr "can_delay" "yes")
625 ;; Pipeline descriptions.
627 ;; generic.md provides a fallback for processors without a specific
628 ;; pipeline description. It is derived from the old define_function_unit
629 ;; version and uses the "alu" and "imuldiv" units declared below.
631 ;; Some of the processor-specific files are also derived from old
632 ;; define_function_unit descriptions and simply override the parts of
633 ;; generic.md that don't apply. The other processor-specific files
634 ;; are self-contained.
635 (define_automaton "alu,imuldiv")
637 (define_cpu_unit "alu" "alu")
638 (define_cpu_unit "imuldiv" "imuldiv")
659 (include "generic.md")
662 ;; ....................
666 ;; ....................
670 [(trap_if (const_int 1) (const_int 0))]
673 if (ISA_HAS_COND_TRAP)
675 else if (TARGET_MIPS16)
680 [(set_attr "type" "trap")])
682 (define_expand "conditional_trap"
683 [(trap_if (match_operator 0 "comparison_operator"
684 [(match_dup 2) (match_dup 3)])
685 (match_operand 1 "const_int_operand"))]
688 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
689 && operands[1] == const0_rtx)
691 mips_gen_conditional_trap (operands);
698 (define_insn "*conditional_trap<mode>"
699 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
700 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
701 (match_operand:GPR 2 "arith_operand" "dI")])
705 [(set_attr "type" "trap")])
708 ;; ....................
712 ;; ....................
715 (define_insn "add<mode>3"
716 [(set (match_operand:ANYF 0 "register_operand" "=f")
717 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
718 (match_operand:ANYF 2 "register_operand" "f")))]
720 "add.<fmt>\t%0,%1,%2"
721 [(set_attr "type" "fadd")
722 (set_attr "mode" "<UNITMODE>")])
724 (define_expand "add<mode>3"
725 [(set (match_operand:GPR 0 "register_operand")
726 (plus:GPR (match_operand:GPR 1 "register_operand")
727 (match_operand:GPR 2 "arith_operand")))]
730 (define_insn "*add<mode>3"
731 [(set (match_operand:GPR 0 "register_operand" "=d,d")
732 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
733 (match_operand:GPR 2 "arith_operand" "d,Q")))]
738 [(set_attr "type" "arith")
739 (set_attr "mode" "<MODE>")])
741 (define_insn "*add<mode>3_mips16"
742 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
743 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
744 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
752 [(set_attr "type" "arith")
753 (set_attr "mode" "<MODE>")
754 (set_attr_alternative "length"
755 [(if_then_else (match_operand 2 "m16_simm8_8")
758 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
761 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
764 (if_then_else (match_operand 2 "m16_simm4_1")
769 ;; On the mips16, we can sometimes split an add of a constant which is
770 ;; a 4 byte instruction into two adds which are both 2 byte
771 ;; instructions. There are two cases: one where we are adding a
772 ;; constant plus a register to another register, and one where we are
773 ;; simply adding a constant to a register.
776 [(set (match_operand:SI 0 "register_operand")
777 (plus:SI (match_dup 0)
778 (match_operand:SI 1 "const_int_operand")))]
779 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
780 && REG_P (operands[0])
781 && M16_REG_P (REGNO (operands[0]))
782 && GET_CODE (operands[1]) == CONST_INT
783 && ((INTVAL (operands[1]) > 0x7f
784 && INTVAL (operands[1]) <= 0x7f + 0x7f)
785 || (INTVAL (operands[1]) < - 0x80
786 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
787 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
788 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
790 HOST_WIDE_INT val = INTVAL (operands[1]);
794 operands[1] = GEN_INT (0x7f);
795 operands[2] = GEN_INT (val - 0x7f);
799 operands[1] = GEN_INT (- 0x80);
800 operands[2] = GEN_INT (val + 0x80);
805 [(set (match_operand:SI 0 "register_operand")
806 (plus:SI (match_operand:SI 1 "register_operand")
807 (match_operand:SI 2 "const_int_operand")))]
808 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
809 && REG_P (operands[0])
810 && M16_REG_P (REGNO (operands[0]))
811 && REG_P (operands[1])
812 && M16_REG_P (REGNO (operands[1]))
813 && REGNO (operands[0]) != REGNO (operands[1])
814 && GET_CODE (operands[2]) == CONST_INT
815 && ((INTVAL (operands[2]) > 0x7
816 && INTVAL (operands[2]) <= 0x7 + 0x7f)
817 || (INTVAL (operands[2]) < - 0x8
818 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
819 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
820 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
822 HOST_WIDE_INT val = INTVAL (operands[2]);
826 operands[2] = GEN_INT (0x7);
827 operands[3] = GEN_INT (val - 0x7);
831 operands[2] = GEN_INT (- 0x8);
832 operands[3] = GEN_INT (val + 0x8);
837 [(set (match_operand:DI 0 "register_operand")
838 (plus:DI (match_dup 0)
839 (match_operand:DI 1 "const_int_operand")))]
840 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
841 && REG_P (operands[0])
842 && M16_REG_P (REGNO (operands[0]))
843 && GET_CODE (operands[1]) == CONST_INT
844 && ((INTVAL (operands[1]) > 0xf
845 && INTVAL (operands[1]) <= 0xf + 0xf)
846 || (INTVAL (operands[1]) < - 0x10
847 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
848 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
849 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
851 HOST_WIDE_INT val = INTVAL (operands[1]);
855 operands[1] = GEN_INT (0xf);
856 operands[2] = GEN_INT (val - 0xf);
860 operands[1] = GEN_INT (- 0x10);
861 operands[2] = GEN_INT (val + 0x10);
866 [(set (match_operand:DI 0 "register_operand")
867 (plus:DI (match_operand:DI 1 "register_operand")
868 (match_operand:DI 2 "const_int_operand")))]
869 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
870 && REG_P (operands[0])
871 && M16_REG_P (REGNO (operands[0]))
872 && REG_P (operands[1])
873 && M16_REG_P (REGNO (operands[1]))
874 && REGNO (operands[0]) != REGNO (operands[1])
875 && GET_CODE (operands[2]) == CONST_INT
876 && ((INTVAL (operands[2]) > 0x7
877 && INTVAL (operands[2]) <= 0x7 + 0xf)
878 || (INTVAL (operands[2]) < - 0x8
879 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
880 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
881 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
883 HOST_WIDE_INT val = INTVAL (operands[2]);
887 operands[2] = GEN_INT (0x7);
888 operands[3] = GEN_INT (val - 0x7);
892 operands[2] = GEN_INT (- 0x8);
893 operands[3] = GEN_INT (val + 0x8);
897 (define_insn "*addsi3_extended"
898 [(set (match_operand:DI 0 "register_operand" "=d,d")
900 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
901 (match_operand:SI 2 "arith_operand" "d,Q"))))]
902 "TARGET_64BIT && !TARGET_MIPS16"
906 [(set_attr "type" "arith")
907 (set_attr "mode" "SI")])
909 ;; Split this insn so that the addiu splitters can have a crack at it.
910 ;; Use a conservative length estimate until the split.
911 (define_insn_and_split "*addsi3_extended_mips16"
912 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
914 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
915 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
916 "TARGET_64BIT && TARGET_MIPS16"
918 "&& reload_completed"
919 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
920 { operands[3] = gen_lowpart (SImode, operands[0]); }
921 [(set_attr "type" "arith")
922 (set_attr "mode" "SI")
923 (set_attr "extended_mips16" "yes")])
926 ;; ....................
930 ;; ....................
933 (define_insn "sub<mode>3"
934 [(set (match_operand:ANYF 0 "register_operand" "=f")
935 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
936 (match_operand:ANYF 2 "register_operand" "f")))]
938 "sub.<fmt>\t%0,%1,%2"
939 [(set_attr "type" "fadd")
940 (set_attr "mode" "<UNITMODE>")])
942 (define_insn "sub<mode>3"
943 [(set (match_operand:GPR 0 "register_operand" "=d")
944 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
945 (match_operand:GPR 2 "register_operand" "d")))]
948 [(set_attr "type" "arith")
949 (set_attr "mode" "<MODE>")])
951 (define_insn "*subsi3_extended"
952 [(set (match_operand:DI 0 "register_operand" "=d")
954 (minus:SI (match_operand:SI 1 "register_operand" "d")
955 (match_operand:SI 2 "register_operand" "d"))))]
958 [(set_attr "type" "arith")
959 (set_attr "mode" "DI")])
962 ;; ....................
966 ;; ....................
969 (define_expand "mul<mode>3"
970 [(set (match_operand:SCALARF 0 "register_operand")
971 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
972 (match_operand:SCALARF 2 "register_operand")))]
976 (define_insn "*mul<mode>3"
977 [(set (match_operand:SCALARF 0 "register_operand" "=f")
978 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
979 (match_operand:SCALARF 2 "register_operand" "f")))]
980 "!TARGET_4300_MUL_FIX"
981 "mul.<fmt>\t%0,%1,%2"
982 [(set_attr "type" "fmul")
983 (set_attr "mode" "<MODE>")])
985 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
986 ;; operands may corrupt immediately following multiplies. This is a
987 ;; simple fix to insert NOPs.
989 (define_insn "*mul<mode>3_r4300"
990 [(set (match_operand:SCALARF 0 "register_operand" "=f")
991 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
992 (match_operand:SCALARF 2 "register_operand" "f")))]
993 "TARGET_4300_MUL_FIX"
994 "mul.<fmt>\t%0,%1,%2\;nop"
995 [(set_attr "type" "fmul")
996 (set_attr "mode" "<MODE>")
997 (set_attr "length" "8")])
999 (define_insn "mulv2sf3"
1000 [(set (match_operand:V2SF 0 "register_operand" "=f")
1001 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1002 (match_operand:V2SF 2 "register_operand" "f")))]
1003 "TARGET_PAIRED_SINGLE_FLOAT"
1005 [(set_attr "type" "fmul")
1006 (set_attr "mode" "SF")])
1008 ;; The original R4000 has a cpu bug. If a double-word or a variable
1009 ;; shift executes while an integer multiplication is in progress, the
1010 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1011 ;; with the mult on the R4000.
1013 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1014 ;; (also valid for MIPS R4000MC processors):
1016 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1017 ;; this errata description.
1018 ;; The following code sequence causes the R4000 to incorrectly
1019 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1020 ;; instruction. If the dsra32 instruction is executed during an
1021 ;; integer multiply, the dsra32 will only shift by the amount in
1022 ;; specified in the instruction rather than the amount plus 32
1024 ;; instruction 1: mult rs,rt integer multiply
1025 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1026 ;; right arithmetic + 32
1027 ;; Workaround: A dsra32 instruction placed after an integer
1028 ;; multiply should not be one of the 11 instructions after the
1029 ;; multiply instruction."
1033 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1034 ;; the following description.
1035 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1036 ;; 64-bit versions) may produce incorrect results under the
1037 ;; following conditions:
1038 ;; 1) An integer multiply is currently executing
1039 ;; 2) These types of shift instructions are executed immediately
1040 ;; following an integer divide instruction.
1042 ;; 1) Make sure no integer multiply is running wihen these
1043 ;; instruction are executed. If this cannot be predicted at
1044 ;; compile time, then insert a "mfhi" to R0 instruction
1045 ;; immediately after the integer multiply instruction. This
1046 ;; will cause the integer multiply to complete before the shift
1048 ;; 2) Separate integer divide and these two classes of shift
1049 ;; instructions by another instruction or a noop."
1051 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1054 (define_expand "mulsi3"
1055 [(set (match_operand:SI 0 "register_operand")
1056 (mult:SI (match_operand:SI 1 "register_operand")
1057 (match_operand:SI 2 "register_operand")))]
1061 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1062 else if (TARGET_FIX_R4000)
1063 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1065 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1069 (define_expand "muldi3"
1070 [(set (match_operand:DI 0 "register_operand")
1071 (mult:DI (match_operand:DI 1 "register_operand")
1072 (match_operand:DI 2 "register_operand")))]
1075 if (TARGET_FIX_R4000)
1076 emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
1078 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
1082 (define_insn "mulsi3_mult3"
1083 [(set (match_operand:SI 0 "register_operand" "=d,l")
1084 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1085 (match_operand:SI 2 "register_operand" "d,d")))
1086 (clobber (match_scratch:SI 3 "=h,h"))
1087 (clobber (match_scratch:SI 4 "=l,X"))]
1090 if (which_alternative == 1)
1091 return "mult\t%1,%2";
1092 if (TARGET_MIPS3900)
1093 return "mult\t%0,%1,%2";
1094 return "mul\t%0,%1,%2";
1096 [(set_attr "type" "imul3,imul")
1097 (set_attr "mode" "SI")])
1099 ;; If a register gets allocated to LO, and we spill to memory, the reload
1100 ;; will include a move from LO to a GPR. Merge it into the multiplication
1101 ;; if it can set the GPR directly.
1104 ;; Operand 1: GPR (1st multiplication operand)
1105 ;; Operand 2: GPR (2nd multiplication operand)
1107 ;; Operand 4: GPR (destination)
1110 [(set (match_operand:SI 0 "register_operand")
1111 (mult:SI (match_operand:SI 1 "register_operand")
1112 (match_operand:SI 2 "register_operand")))
1113 (clobber (match_operand:SI 3 "register_operand"))
1114 (clobber (scratch:SI))])
1115 (set (match_operand:SI 4 "register_operand")
1116 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1117 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1120 (mult:SI (match_dup 1)
1122 (clobber (match_dup 3))
1123 (clobber (match_dup 0))])])
1125 (define_insn "mul<mode>3_internal"
1126 [(set (match_operand:GPR 0 "register_operand" "=l")
1127 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1128 (match_operand:GPR 2 "register_operand" "d")))
1129 (clobber (match_scratch:GPR 3 "=h"))]
1132 [(set_attr "type" "imul")
1133 (set_attr "mode" "<MODE>")])
1135 (define_insn "mul<mode>3_r4000"
1136 [(set (match_operand:GPR 0 "register_operand" "=d")
1137 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1138 (match_operand:GPR 2 "register_operand" "d")))
1139 (clobber (match_scratch:GPR 3 "=h"))
1140 (clobber (match_scratch:GPR 4 "=l"))]
1142 "<d>mult\t%1,%2\;mflo\t%0"
1143 [(set_attr "type" "imul")
1144 (set_attr "mode" "<MODE>")
1145 (set_attr "length" "8")])
1147 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1148 ;; of "mult; mflo". They have the same latency, but the first form gives
1149 ;; us an extra cycle to compute the operands.
1152 ;; Operand 1: GPR (1st multiplication operand)
1153 ;; Operand 2: GPR (2nd multiplication operand)
1155 ;; Operand 4: GPR (destination)
1158 [(set (match_operand:SI 0 "register_operand")
1159 (mult:SI (match_operand:SI 1 "register_operand")
1160 (match_operand:SI 2 "register_operand")))
1161 (clobber (match_operand:SI 3 "register_operand"))])
1162 (set (match_operand:SI 4 "register_operand")
1163 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1164 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1169 (plus:SI (mult:SI (match_dup 1)
1173 (plus:SI (mult:SI (match_dup 1)
1176 (clobber (match_dup 3))])])
1178 ;; Multiply-accumulate patterns
1180 ;; For processors that can copy the output to a general register:
1182 ;; The all-d alternative is needed because the combiner will find this
1183 ;; pattern and then register alloc/reload will move registers around to
1184 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1186 ;; The last alternative should be made slightly less desirable, but adding
1187 ;; "?" to the constraint is too strong, and causes values to be loaded into
1188 ;; LO even when that's more costly. For now, using "*d" mostly does the
1190 (define_insn "*mul_acc_si"
1191 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1192 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1193 (match_operand:SI 2 "register_operand" "d,d,d"))
1194 (match_operand:SI 3 "register_operand" "0,l,*d")))
1195 (clobber (match_scratch:SI 4 "=h,h,h"))
1196 (clobber (match_scratch:SI 5 "=X,3,l"))
1197 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1199 || GENERATE_MADD_MSUB)
1202 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1203 if (which_alternative == 2)
1205 if (GENERATE_MADD_MSUB && which_alternative != 0)
1207 return madd[which_alternative];
1209 [(set_attr "type" "imadd")
1210 (set_attr "mode" "SI")
1211 (set_attr "length" "4,4,8")])
1213 ;; Split the above insn if we failed to get LO allocated.
1215 [(set (match_operand:SI 0 "register_operand")
1216 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1217 (match_operand:SI 2 "register_operand"))
1218 (match_operand:SI 3 "register_operand")))
1219 (clobber (match_scratch:SI 4))
1220 (clobber (match_scratch:SI 5))
1221 (clobber (match_scratch:SI 6))]
1222 "reload_completed && !TARGET_DEBUG_D_MODE
1223 && GP_REG_P (true_regnum (operands[0]))
1224 && GP_REG_P (true_regnum (operands[3]))"
1225 [(parallel [(set (match_dup 6)
1226 (mult:SI (match_dup 1) (match_dup 2)))
1227 (clobber (match_dup 4))
1228 (clobber (match_dup 5))])
1229 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1232 ;; Splitter to copy result of MADD to a general register
1234 [(set (match_operand:SI 0 "register_operand")
1235 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1236 (match_operand:SI 2 "register_operand"))
1237 (match_operand:SI 3 "register_operand")))
1238 (clobber (match_scratch:SI 4))
1239 (clobber (match_scratch:SI 5))
1240 (clobber (match_scratch:SI 6))]
1241 "reload_completed && !TARGET_DEBUG_D_MODE
1242 && GP_REG_P (true_regnum (operands[0]))
1243 && true_regnum (operands[3]) == LO_REGNUM"
1244 [(parallel [(set (match_dup 3)
1245 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1247 (clobber (match_dup 4))
1248 (clobber (match_dup 5))
1249 (clobber (match_dup 6))])
1250 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1253 (define_insn "*macc"
1254 [(set (match_operand:SI 0 "register_operand" "=l,d")
1255 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1256 (match_operand:SI 2 "register_operand" "d,d"))
1257 (match_operand:SI 3 "register_operand" "0,l")))
1258 (clobber (match_scratch:SI 4 "=h,h"))
1259 (clobber (match_scratch:SI 5 "=X,3"))]
1262 if (which_alternative == 1)
1263 return "macc\t%0,%1,%2";
1264 else if (TARGET_MIPS5500)
1265 return "madd\t%1,%2";
1267 /* The VR4130 assumes that there is a two-cycle latency between a macc
1268 that "writes" to $0 and an instruction that reads from it. We avoid
1269 this by assigning to $1 instead. */
1270 return "%[macc\t%@,%1,%2%]";
1272 [(set_attr "type" "imadd")
1273 (set_attr "mode" "SI")])
1275 (define_insn "*msac"
1276 [(set (match_operand:SI 0 "register_operand" "=l,d")
1277 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1278 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1279 (match_operand:SI 3 "register_operand" "d,d"))))
1280 (clobber (match_scratch:SI 4 "=h,h"))
1281 (clobber (match_scratch:SI 5 "=X,1"))]
1284 if (which_alternative == 1)
1285 return "msac\t%0,%2,%3";
1286 else if (TARGET_MIPS5500)
1287 return "msub\t%2,%3";
1289 return "msac\t$0,%2,%3";
1291 [(set_attr "type" "imadd")
1292 (set_attr "mode" "SI")])
1294 ;; An msac-like instruction implemented using negation and a macc.
1295 (define_insn_and_split "*msac_using_macc"
1296 [(set (match_operand:SI 0 "register_operand" "=l,d")
1297 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1298 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1299 (match_operand:SI 3 "register_operand" "d,d"))))
1300 (clobber (match_scratch:SI 4 "=h,h"))
1301 (clobber (match_scratch:SI 5 "=X,1"))
1302 (clobber (match_scratch:SI 6 "=d,d"))]
1303 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1305 "&& reload_completed"
1307 (neg:SI (match_dup 3)))
1310 (plus:SI (mult:SI (match_dup 2)
1313 (clobber (match_dup 4))
1314 (clobber (match_dup 5))])]
1316 [(set_attr "type" "imadd")
1317 (set_attr "length" "8")])
1319 ;; Patterns generated by the define_peephole2 below.
1321 (define_insn "*macc2"
1322 [(set (match_operand:SI 0 "register_operand" "=l")
1323 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1324 (match_operand:SI 2 "register_operand" "d"))
1326 (set (match_operand:SI 3 "register_operand" "=d")
1327 (plus:SI (mult:SI (match_dup 1)
1330 (clobber (match_scratch:SI 4 "=h"))]
1331 "ISA_HAS_MACC && reload_completed"
1333 [(set_attr "type" "imadd")
1334 (set_attr "mode" "SI")])
1336 (define_insn "*msac2"
1337 [(set (match_operand:SI 0 "register_operand" "=l")
1338 (minus:SI (match_dup 0)
1339 (mult:SI (match_operand:SI 1 "register_operand" "d")
1340 (match_operand:SI 2 "register_operand" "d"))))
1341 (set (match_operand:SI 3 "register_operand" "=d")
1342 (minus:SI (match_dup 0)
1343 (mult:SI (match_dup 1)
1345 (clobber (match_scratch:SI 4 "=h"))]
1346 "ISA_HAS_MSAC && reload_completed"
1348 [(set_attr "type" "imadd")
1349 (set_attr "mode" "SI")])
1351 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1355 ;; Operand 1: macc/msac
1357 ;; Operand 3: GPR (destination)
1360 [(set (match_operand:SI 0 "register_operand")
1361 (match_operand:SI 1 "macc_msac_operand"))
1362 (clobber (match_operand:SI 2 "register_operand"))
1363 (clobber (scratch:SI))])
1364 (set (match_operand:SI 3 "register_operand")
1365 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1367 [(parallel [(set (match_dup 0)
1371 (clobber (match_dup 2))])]
1374 ;; When we have a three-address multiplication instruction, it should
1375 ;; be faster to do a separate multiply and add, rather than moving
1376 ;; something into LO in order to use a macc instruction.
1378 ;; This peephole needs a scratch register to cater for the case when one
1379 ;; of the multiplication operands is the same as the destination.
1381 ;; Operand 0: GPR (scratch)
1383 ;; Operand 2: GPR (addend)
1384 ;; Operand 3: GPR (destination)
1385 ;; Operand 4: macc/msac
1387 ;; Operand 6: new multiplication
1388 ;; Operand 7: new addition/subtraction
1390 [(match_scratch:SI 0 "d")
1391 (set (match_operand:SI 1 "register_operand")
1392 (match_operand:SI 2 "register_operand"))
1395 [(set (match_operand:SI 3 "register_operand")
1396 (match_operand:SI 4 "macc_msac_operand"))
1397 (clobber (match_operand:SI 5 "register_operand"))
1398 (clobber (match_dup 1))])]
1400 && true_regnum (operands[1]) == LO_REGNUM
1401 && peep2_reg_dead_p (2, operands[1])
1402 && GP_REG_P (true_regnum (operands[3]))"
1403 [(parallel [(set (match_dup 0)
1405 (clobber (match_dup 5))
1406 (clobber (match_dup 1))])
1410 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1411 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1412 operands[2], operands[0]);
1415 ;; Same as above, except LO is the initial target of the macc.
1417 ;; Operand 0: GPR (scratch)
1419 ;; Operand 2: GPR (addend)
1420 ;; Operand 3: macc/msac
1422 ;; Operand 5: GPR (destination)
1423 ;; Operand 6: new multiplication
1424 ;; Operand 7: new addition/subtraction
1426 [(match_scratch:SI 0 "d")
1427 (set (match_operand:SI 1 "register_operand")
1428 (match_operand:SI 2 "register_operand"))
1432 (match_operand:SI 3 "macc_msac_operand"))
1433 (clobber (match_operand:SI 4 "register_operand"))
1434 (clobber (scratch:SI))])
1436 (set (match_operand:SI 5 "register_operand")
1437 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1438 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1439 [(parallel [(set (match_dup 0)
1441 (clobber (match_dup 4))
1442 (clobber (match_dup 1))])
1446 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1447 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1448 operands[2], operands[0]);
1451 (define_insn "*mul_sub_si"
1452 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1453 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1454 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1455 (match_operand:SI 3 "register_operand" "d,d,d"))))
1456 (clobber (match_scratch:SI 4 "=h,h,h"))
1457 (clobber (match_scratch:SI 5 "=X,1,l"))
1458 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1459 "GENERATE_MADD_MSUB"
1464 [(set_attr "type" "imadd")
1465 (set_attr "mode" "SI")
1466 (set_attr "length" "4,8,8")])
1468 ;; Split the above insn if we failed to get LO allocated.
1470 [(set (match_operand:SI 0 "register_operand")
1471 (minus:SI (match_operand:SI 1 "register_operand")
1472 (mult:SI (match_operand:SI 2 "register_operand")
1473 (match_operand:SI 3 "register_operand"))))
1474 (clobber (match_scratch:SI 4))
1475 (clobber (match_scratch:SI 5))
1476 (clobber (match_scratch:SI 6))]
1477 "reload_completed && !TARGET_DEBUG_D_MODE
1478 && GP_REG_P (true_regnum (operands[0]))
1479 && GP_REG_P (true_regnum (operands[1]))"
1480 [(parallel [(set (match_dup 6)
1481 (mult:SI (match_dup 2) (match_dup 3)))
1482 (clobber (match_dup 4))
1483 (clobber (match_dup 5))])
1484 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1487 ;; Splitter to copy result of MSUB to a general register
1489 [(set (match_operand:SI 0 "register_operand")
1490 (minus:SI (match_operand:SI 1 "register_operand")
1491 (mult:SI (match_operand:SI 2 "register_operand")
1492 (match_operand:SI 3 "register_operand"))))
1493 (clobber (match_scratch:SI 4))
1494 (clobber (match_scratch:SI 5))
1495 (clobber (match_scratch:SI 6))]
1496 "reload_completed && !TARGET_DEBUG_D_MODE
1497 && GP_REG_P (true_regnum (operands[0]))
1498 && true_regnum (operands[1]) == LO_REGNUM"
1499 [(parallel [(set (match_dup 1)
1500 (minus:SI (match_dup 1)
1501 (mult:SI (match_dup 2) (match_dup 3))))
1502 (clobber (match_dup 4))
1503 (clobber (match_dup 5))
1504 (clobber (match_dup 6))])
1505 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1508 (define_insn "*muls"
1509 [(set (match_operand:SI 0 "register_operand" "=l,d")
1510 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1511 (match_operand:SI 2 "register_operand" "d,d"))))
1512 (clobber (match_scratch:SI 3 "=h,h"))
1513 (clobber (match_scratch:SI 4 "=X,l"))]
1518 [(set_attr "type" "imul,imul3")
1519 (set_attr "mode" "SI")])
1521 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1523 (define_expand "<u>mulsidi3"
1525 [(set (match_operand:DI 0 "register_operand")
1526 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1527 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1528 (clobber (scratch:DI))
1529 (clobber (scratch:DI))
1530 (clobber (scratch:DI))])]
1531 "!TARGET_64BIT || !TARGET_FIX_R4000"
1535 if (!TARGET_FIX_R4000)
1536 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1539 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1545 (define_insn "<u>mulsidi3_32bit_internal"
1546 [(set (match_operand:DI 0 "register_operand" "=x")
1547 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1548 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1549 "!TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_DSPR2"
1551 [(set_attr "type" "imul")
1552 (set_attr "mode" "SI")])
1554 (define_insn "<u>mulsidi3_32bit_r4000"
1555 [(set (match_operand:DI 0 "register_operand" "=d")
1556 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1557 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1558 (clobber (match_scratch:DI 3 "=x"))]
1559 "!TARGET_64BIT && TARGET_FIX_R4000"
1560 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1561 [(set_attr "type" "imul")
1562 (set_attr "mode" "SI")
1563 (set_attr "length" "12")])
1565 (define_insn_and_split "*<u>mulsidi3_64bit"
1566 [(set (match_operand:DI 0 "register_operand" "=d")
1567 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1568 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1569 (clobber (match_scratch:DI 3 "=l"))
1570 (clobber (match_scratch:DI 4 "=h"))
1571 (clobber (match_scratch:DI 5 "=d"))]
1572 "TARGET_64BIT && !TARGET_FIX_R4000"
1574 "&& reload_completed"
1578 (mult:SI (match_dup 1)
1582 (mult:DI (any_extend:DI (match_dup 1))
1583 (any_extend:DI (match_dup 2)))
1586 ;; OP5 <- LO, OP0 <- HI
1587 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1588 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1592 (ashift:DI (match_dup 5)
1595 (lshiftrt:DI (match_dup 5)
1598 ;; Shift OP0 into place.
1600 (ashift:DI (match_dup 0)
1603 ;; OR the two halves together
1605 (ior:DI (match_dup 0)
1608 [(set_attr "type" "imul")
1609 (set_attr "mode" "SI")
1610 (set_attr "length" "24")])
1612 (define_insn "*<u>mulsidi3_64bit_parts"
1613 [(set (match_operand:DI 0 "register_operand" "=l")
1615 (mult:SI (match_operand:SI 2 "register_operand" "d")
1616 (match_operand:SI 3 "register_operand" "d"))))
1617 (set (match_operand:DI 1 "register_operand" "=h")
1619 (mult:DI (any_extend:DI (match_dup 2))
1620 (any_extend:DI (match_dup 3)))
1622 "TARGET_64BIT && !TARGET_FIX_R4000"
1624 [(set_attr "type" "imul")
1625 (set_attr "mode" "SI")])
1627 ;; Widening multiply with negation.
1628 (define_insn "*muls<u>_di"
1629 [(set (match_operand:DI 0 "register_operand" "=x")
1632 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1633 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1634 "!TARGET_64BIT && ISA_HAS_MULS"
1636 [(set_attr "type" "imul")
1637 (set_attr "mode" "SI")])
1639 (define_insn "<u>msubsidi4"
1640 [(set (match_operand:DI 0 "register_operand" "=ka")
1642 (match_operand:DI 3 "register_operand" "0")
1644 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1645 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1646 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || TARGET_DSPR2)"
1649 return "msub<u>\t%q0,%1,%2";
1650 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1651 return "msub<u>\t%1,%2";
1653 return "msac<u>\t$0,%1,%2";
1655 [(set_attr "type" "imadd")
1656 (set_attr "mode" "SI")])
1658 ;; _highpart patterns
1660 (define_expand "<su>mulsi3_highpart"
1661 [(set (match_operand:SI 0 "register_operand")
1664 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1665 (any_extend:DI (match_operand:SI 2 "register_operand")))
1667 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1670 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1674 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1679 (define_insn "<su>mulsi3_highpart_internal"
1680 [(set (match_operand:SI 0 "register_operand" "=h")
1683 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1684 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1686 (clobber (match_scratch:SI 3 "=l"))]
1687 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1689 [(set_attr "type" "imul")
1690 (set_attr "mode" "SI")])
1692 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1693 [(set (match_operand:SI 0 "register_operand" "=h,d")
1697 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1698 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1700 (clobber (match_scratch:SI 3 "=l,l"))
1701 (clobber (match_scratch:SI 4 "=X,h"))]
1706 [(set_attr "type" "imul,imul3")
1707 (set_attr "mode" "SI")])
1709 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1710 [(set (match_operand:SI 0 "register_operand" "=h,d")
1715 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1716 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1718 (clobber (match_scratch:SI 3 "=l,l"))
1719 (clobber (match_scratch:SI 4 "=X,h"))]
1723 mulshi<u>\t%0,%1,%2"
1724 [(set_attr "type" "imul,imul3")
1725 (set_attr "mode" "SI")])
1727 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1728 ;; errata MD(0), which says that dmultu does not always produce the
1730 (define_insn "<su>muldi3_highpart"
1731 [(set (match_operand:DI 0 "register_operand" "=h")
1735 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1736 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1738 (clobber (match_scratch:DI 3 "=l"))]
1739 "TARGET_64BIT && !TARGET_FIX_R4000
1740 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1742 [(set_attr "type" "imul")
1743 (set_attr "mode" "DI")])
1745 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
1746 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
1748 (define_insn "madsi"
1749 [(set (match_operand:SI 0 "register_operand" "+l")
1750 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1751 (match_operand:SI 2 "register_operand" "d"))
1753 (clobber (match_scratch:SI 3 "=h"))]
1756 [(set_attr "type" "imadd")
1757 (set_attr "mode" "SI")])
1759 (define_insn "<u>maddsidi4"
1760 [(set (match_operand:DI 0 "register_operand" "=ka")
1762 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1763 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1764 (match_operand:DI 3 "register_operand" "0")))]
1765 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || TARGET_DSPR2)
1769 return "mad<u>\t%1,%2";
1770 else if (TARGET_DSPR2)
1771 return "madd<u>\t%q0,%1,%2";
1772 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
1773 return "madd<u>\t%1,%2";
1775 /* See comment in *macc. */
1776 return "%[macc<u>\t%@,%1,%2%]";
1778 [(set_attr "type" "imadd")
1779 (set_attr "mode" "SI")])
1781 ;; Floating point multiply accumulate instructions.
1783 (define_insn "*madd<mode>"
1784 [(set (match_operand:ANYF 0 "register_operand" "=f")
1785 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1786 (match_operand:ANYF 2 "register_operand" "f"))
1787 (match_operand:ANYF 3 "register_operand" "f")))]
1788 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1789 "madd.<fmt>\t%0,%3,%1,%2"
1790 [(set_attr "type" "fmadd")
1791 (set_attr "mode" "<UNITMODE>")])
1793 (define_insn "*msub<mode>"
1794 [(set (match_operand:ANYF 0 "register_operand" "=f")
1795 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1796 (match_operand:ANYF 2 "register_operand" "f"))
1797 (match_operand:ANYF 3 "register_operand" "f")))]
1798 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1799 "msub.<fmt>\t%0,%3,%1,%2"
1800 [(set_attr "type" "fmadd")
1801 (set_attr "mode" "<UNITMODE>")])
1803 (define_insn "*nmadd<mode>"
1804 [(set (match_operand:ANYF 0 "register_operand" "=f")
1805 (neg:ANYF (plus:ANYF
1806 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1807 (match_operand:ANYF 2 "register_operand" "f"))
1808 (match_operand:ANYF 3 "register_operand" "f"))))]
1809 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1810 && HONOR_SIGNED_ZEROS (<MODE>mode)
1811 && !HONOR_NANS (<MODE>mode)"
1812 "nmadd.<fmt>\t%0,%3,%1,%2"
1813 [(set_attr "type" "fmadd")
1814 (set_attr "mode" "<UNITMODE>")])
1816 (define_insn "*nmadd<mode>_fastmath"
1817 [(set (match_operand:ANYF 0 "register_operand" "=f")
1819 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1820 (match_operand:ANYF 2 "register_operand" "f"))
1821 (match_operand:ANYF 3 "register_operand" "f")))]
1822 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1823 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1824 && !HONOR_NANS (<MODE>mode)"
1825 "nmadd.<fmt>\t%0,%3,%1,%2"
1826 [(set_attr "type" "fmadd")
1827 (set_attr "mode" "<UNITMODE>")])
1829 (define_insn "*nmsub<mode>"
1830 [(set (match_operand:ANYF 0 "register_operand" "=f")
1831 (neg:ANYF (minus:ANYF
1832 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1833 (match_operand:ANYF 3 "register_operand" "f"))
1834 (match_operand:ANYF 1 "register_operand" "f"))))]
1835 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1836 && HONOR_SIGNED_ZEROS (<MODE>mode)
1837 && !HONOR_NANS (<MODE>mode)"
1838 "nmsub.<fmt>\t%0,%1,%2,%3"
1839 [(set_attr "type" "fmadd")
1840 (set_attr "mode" "<UNITMODE>")])
1842 (define_insn "*nmsub<mode>_fastmath"
1843 [(set (match_operand:ANYF 0 "register_operand" "=f")
1845 (match_operand:ANYF 1 "register_operand" "f")
1846 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1847 (match_operand:ANYF 3 "register_operand" "f"))))]
1848 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1849 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1850 && !HONOR_NANS (<MODE>mode)"
1851 "nmsub.<fmt>\t%0,%1,%2,%3"
1852 [(set_attr "type" "fmadd")
1853 (set_attr "mode" "<UNITMODE>")])
1856 ;; ....................
1858 ;; DIVISION and REMAINDER
1860 ;; ....................
1863 (define_expand "div<mode>3"
1864 [(set (match_operand:ANYF 0 "register_operand")
1865 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1866 (match_operand:ANYF 2 "register_operand")))]
1867 "<divide_condition>"
1869 if (const_1_operand (operands[1], <MODE>mode))
1870 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
1871 operands[1] = force_reg (<MODE>mode, operands[1]);
1874 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1876 ;; If an mfc1 or dmfc1 happens to access the floating point register
1877 ;; file at the same time a long latency operation (div, sqrt, recip,
1878 ;; sqrt) iterates an intermediate result back through the floating
1879 ;; point register file bypass, then instead returning the correct
1880 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1881 ;; result of the long latency operation.
1883 ;; The workaround is to insert an unconditional 'mov' from/to the
1884 ;; long latency op destination register.
1886 (define_insn "*div<mode>3"
1887 [(set (match_operand:ANYF 0 "register_operand" "=f")
1888 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1889 (match_operand:ANYF 2 "register_operand" "f")))]
1890 "<divide_condition>"
1893 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1895 return "div.<fmt>\t%0,%1,%2";
1897 [(set_attr "type" "fdiv")
1898 (set_attr "mode" "<UNITMODE>")
1899 (set (attr "length")
1900 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1904 (define_insn "*recip<mode>3"
1905 [(set (match_operand:ANYF 0 "register_operand" "=f")
1906 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1907 (match_operand:ANYF 2 "register_operand" "f")))]
1908 "<recip_condition> && flag_unsafe_math_optimizations"
1911 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1913 return "recip.<fmt>\t%0,%2";
1915 [(set_attr "type" "frdiv")
1916 (set_attr "mode" "<UNITMODE>")
1917 (set (attr "length")
1918 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1922 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
1923 ;; with negative operands. We use special libgcc functions instead.
1924 (define_insn "divmod<mode>4"
1925 [(set (match_operand:GPR 0 "register_operand" "=l")
1926 (div:GPR (match_operand:GPR 1 "register_operand" "d")
1927 (match_operand:GPR 2 "register_operand" "d")))
1928 (set (match_operand:GPR 3 "register_operand" "=h")
1929 (mod:GPR (match_dup 1)
1931 "!TARGET_FIX_VR4120"
1932 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
1933 [(set_attr "type" "idiv")
1934 (set_attr "mode" "<MODE>")])
1936 (define_insn "udivmod<mode>4"
1937 [(set (match_operand:GPR 0 "register_operand" "=l")
1938 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
1939 (match_operand:GPR 2 "register_operand" "d")))
1940 (set (match_operand:GPR 3 "register_operand" "=h")
1941 (umod:GPR (match_dup 1)
1944 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
1945 [(set_attr "type" "idiv")
1946 (set_attr "mode" "<MODE>")])
1949 ;; ....................
1953 ;; ....................
1955 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
1956 ;; "*div[sd]f3" comment for details).
1958 (define_insn "sqrt<mode>2"
1959 [(set (match_operand:ANYF 0 "register_operand" "=f")
1960 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1964 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
1966 return "sqrt.<fmt>\t%0,%1";
1968 [(set_attr "type" "fsqrt")
1969 (set_attr "mode" "<UNITMODE>")
1970 (set (attr "length")
1971 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1975 (define_insn "*rsqrt<mode>a"
1976 [(set (match_operand:ANYF 0 "register_operand" "=f")
1977 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1978 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
1979 "<recip_condition> && flag_unsafe_math_optimizations"
1982 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1984 return "rsqrt.<fmt>\t%0,%2";
1986 [(set_attr "type" "frsqrt")
1987 (set_attr "mode" "<UNITMODE>")
1988 (set (attr "length")
1989 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1993 (define_insn "*rsqrt<mode>b"
1994 [(set (match_operand:ANYF 0 "register_operand" "=f")
1995 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1996 (match_operand:ANYF 2 "register_operand" "f"))))]
1997 "<recip_condition> && flag_unsafe_math_optimizations"
2000 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2002 return "rsqrt.<fmt>\t%0,%2";
2004 [(set_attr "type" "frsqrt")
2005 (set_attr "mode" "<UNITMODE>")
2006 (set (attr "length")
2007 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2012 ;; ....................
2016 ;; ....................
2018 ;; Do not use the integer abs macro instruction, since that signals an
2019 ;; exception on -2147483648 (sigh).
2021 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2022 ;; invalid; it does not clear their sign bits. We therefore can't use
2023 ;; abs.fmt if the signs of NaNs matter.
2025 (define_insn "abs<mode>2"
2026 [(set (match_operand:ANYF 0 "register_operand" "=f")
2027 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2028 "!HONOR_NANS (<MODE>mode)"
2030 [(set_attr "type" "fabs")
2031 (set_attr "mode" "<UNITMODE>")])
2034 ;; ...................
2036 ;; Count leading zeroes.
2038 ;; ...................
2041 (define_insn "clz<mode>2"
2042 [(set (match_operand:GPR 0 "register_operand" "=d")
2043 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2046 [(set_attr "type" "clz")
2047 (set_attr "mode" "<MODE>")])
2050 ;; ....................
2052 ;; NEGATION and ONE'S COMPLEMENT
2054 ;; ....................
2056 (define_insn "negsi2"
2057 [(set (match_operand:SI 0 "register_operand" "=d")
2058 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2062 return "neg\t%0,%1";
2064 return "subu\t%0,%.,%1";
2066 [(set_attr "type" "arith")
2067 (set_attr "mode" "SI")])
2069 (define_insn "negdi2"
2070 [(set (match_operand:DI 0 "register_operand" "=d")
2071 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2072 "TARGET_64BIT && !TARGET_MIPS16"
2074 [(set_attr "type" "arith")
2075 (set_attr "mode" "DI")])
2077 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2078 ;; invalid; it does not flip their sign bit. We therefore can't use
2079 ;; neg.fmt if the signs of NaNs matter.
2081 (define_insn "neg<mode>2"
2082 [(set (match_operand:ANYF 0 "register_operand" "=f")
2083 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2084 "!HONOR_NANS (<MODE>mode)"
2086 [(set_attr "type" "fneg")
2087 (set_attr "mode" "<UNITMODE>")])
2089 (define_insn "one_cmpl<mode>2"
2090 [(set (match_operand:GPR 0 "register_operand" "=d")
2091 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2095 return "not\t%0,%1";
2097 return "nor\t%0,%.,%1";
2099 [(set_attr "type" "logical")
2100 (set_attr "mode" "<MODE>")])
2103 ;; ....................
2107 ;; ....................
2110 ;; Many of these instructions use trivial define_expands, because we
2111 ;; want to use a different set of constraints when TARGET_MIPS16.
2113 (define_expand "and<mode>3"
2114 [(set (match_operand:GPR 0 "register_operand")
2115 (and:GPR (match_operand:GPR 1 "register_operand")
2116 (match_operand:GPR 2 "uns_arith_operand")))]
2120 operands[2] = force_reg (<MODE>mode, operands[2]);
2123 (define_insn "*and<mode>3"
2124 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2125 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2126 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2131 [(set_attr "type" "logical")
2132 (set_attr "mode" "<MODE>")])
2134 (define_insn "*and<mode>3_mips16"
2135 [(set (match_operand:GPR 0 "register_operand" "=d")
2136 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2137 (match_operand:GPR 2 "register_operand" "d")))]
2140 [(set_attr "type" "logical")
2141 (set_attr "mode" "<MODE>")])
2143 (define_expand "ior<mode>3"
2144 [(set (match_operand:GPR 0 "register_operand")
2145 (ior:GPR (match_operand:GPR 1 "register_operand")
2146 (match_operand:GPR 2 "uns_arith_operand")))]
2150 operands[2] = force_reg (<MODE>mode, operands[2]);
2153 (define_insn "*ior<mode>3"
2154 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2155 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2156 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2161 [(set_attr "type" "logical")
2162 (set_attr "mode" "<MODE>")])
2164 (define_insn "*ior<mode>3_mips16"
2165 [(set (match_operand:GPR 0 "register_operand" "=d")
2166 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2167 (match_operand:GPR 2 "register_operand" "d")))]
2170 [(set_attr "type" "logical")
2171 (set_attr "mode" "<MODE>")])
2173 (define_expand "xor<mode>3"
2174 [(set (match_operand:GPR 0 "register_operand")
2175 (xor:GPR (match_operand:GPR 1 "register_operand")
2176 (match_operand:GPR 2 "uns_arith_operand")))]
2181 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2182 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2183 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2188 [(set_attr "type" "logical")
2189 (set_attr "mode" "<MODE>")])
2192 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2193 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2194 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2200 [(set_attr "type" "logical,arith,arith")
2201 (set_attr "mode" "<MODE>")
2202 (set_attr_alternative "length"
2204 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2209 (define_insn "*nor<mode>3"
2210 [(set (match_operand:GPR 0 "register_operand" "=d")
2211 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2212 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2215 [(set_attr "type" "logical")
2216 (set_attr "mode" "<MODE>")])
2219 ;; ....................
2223 ;; ....................
2227 (define_insn "truncdfsf2"
2228 [(set (match_operand:SF 0 "register_operand" "=f")
2229 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2230 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2232 [(set_attr "type" "fcvt")
2233 (set_attr "cnv_mode" "D2S")
2234 (set_attr "mode" "SF")])
2236 ;; Integer truncation patterns. Truncating SImode values to smaller
2237 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2238 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2239 ;; need to make sure that the lower 32 bits are properly sign-extended
2240 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2241 ;; smaller than SImode is equivalent to two separate truncations:
2244 ;; DI ---> HI == DI ---> SI ---> HI
2245 ;; DI ---> QI == DI ---> SI ---> QI
2247 ;; Step A needs a real instruction but step B does not.
2249 (define_insn "truncdisi2"
2250 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2251 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2256 [(set_attr "type" "shift,store")
2257 (set_attr "mode" "SI")
2258 (set_attr "extended_mips16" "yes,*")])
2260 (define_insn "truncdihi2"
2261 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2262 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2267 [(set_attr "type" "shift,store")
2268 (set_attr "mode" "SI")
2269 (set_attr "extended_mips16" "yes,*")])
2271 (define_insn "truncdiqi2"
2272 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2273 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2278 [(set_attr "type" "shift,store")
2279 (set_attr "mode" "SI")
2280 (set_attr "extended_mips16" "yes,*")])
2282 ;; Combiner patterns to optimize shift/truncate combinations.
2285 [(set (match_operand:SI 0 "register_operand" "=d")
2287 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2288 (match_operand:DI 2 "const_arith_operand" ""))))]
2289 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2291 [(set_attr "type" "shift")
2292 (set_attr "mode" "SI")])
2295 [(set (match_operand:SI 0 "register_operand" "=d")
2296 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2298 "TARGET_64BIT && !TARGET_MIPS16"
2300 [(set_attr "type" "shift")
2301 (set_attr "mode" "SI")])
2304 ;; Combiner patterns for truncate/sign_extend combinations. They use
2305 ;; the shift/truncate patterns above.
2307 (define_insn_and_split ""
2308 [(set (match_operand:SI 0 "register_operand" "=d")
2310 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2311 "TARGET_64BIT && !TARGET_MIPS16"
2313 "&& reload_completed"
2315 (ashift:DI (match_dup 1)
2318 (truncate:SI (ashiftrt:DI (match_dup 2)
2320 { operands[2] = gen_lowpart (DImode, operands[0]); })
2322 (define_insn_and_split ""
2323 [(set (match_operand:SI 0 "register_operand" "=d")
2325 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2326 "TARGET_64BIT && !TARGET_MIPS16"
2328 "&& reload_completed"
2330 (ashift:DI (match_dup 1)
2333 (truncate:SI (ashiftrt:DI (match_dup 2)
2335 { operands[2] = gen_lowpart (DImode, operands[0]); })
2338 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2341 [(set (match_operand:SI 0 "register_operand" "=d")
2342 (zero_extend:SI (truncate:HI
2343 (match_operand:DI 1 "register_operand" "d"))))]
2344 "TARGET_64BIT && !TARGET_MIPS16"
2345 "andi\t%0,%1,0xffff"
2346 [(set_attr "type" "logical")
2347 (set_attr "mode" "SI")])
2350 [(set (match_operand:SI 0 "register_operand" "=d")
2351 (zero_extend:SI (truncate:QI
2352 (match_operand:DI 1 "register_operand" "d"))))]
2353 "TARGET_64BIT && !TARGET_MIPS16"
2355 [(set_attr "type" "logical")
2356 (set_attr "mode" "SI")])
2359 [(set (match_operand:HI 0 "register_operand" "=d")
2360 (zero_extend:HI (truncate:QI
2361 (match_operand:DI 1 "register_operand" "d"))))]
2362 "TARGET_64BIT && !TARGET_MIPS16"
2364 [(set_attr "type" "logical")
2365 (set_attr "mode" "HI")])
2368 ;; ....................
2372 ;; ....................
2376 (define_insn_and_split "zero_extendsidi2"
2377 [(set (match_operand:DI 0 "register_operand" "=d,d")
2378 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2383 "&& reload_completed && REG_P (operands[1])"
2385 (ashift:DI (match_dup 1) (const_int 32)))
2387 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2388 { operands[1] = gen_lowpart (DImode, operands[1]); }
2389 [(set_attr "type" "multi,load")
2390 (set_attr "mode" "DI")
2391 (set_attr "length" "8,*")])
2393 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2394 ;; because of TRULY_NOOP_TRUNCATION.
2396 (define_insn_and_split "*clear_upper32"
2397 [(set (match_operand:DI 0 "register_operand" "=d,d")
2398 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2399 (const_int 4294967295)))]
2402 if (which_alternative == 0)
2405 operands[1] = gen_lowpart (SImode, operands[1]);
2406 return "lwu\t%0,%1";
2408 "&& reload_completed && REG_P (operands[1])"
2410 (ashift:DI (match_dup 1) (const_int 32)))
2412 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2414 [(set_attr "type" "multi,load")
2415 (set_attr "mode" "DI")
2416 (set_attr "length" "8,*")])
2418 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2419 [(set (match_operand:GPR 0 "register_operand")
2420 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2423 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2424 && !memory_operand (operands[1], <SHORT:MODE>mode))
2426 emit_insn (gen_and<GPR:mode>3 (operands[0],
2427 gen_lowpart (<GPR:MODE>mode, operands[1]),
2428 force_reg (<GPR:MODE>mode,
2429 GEN_INT (<SHORT:mask>))));
2434 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2435 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2437 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2440 andi\t%0,%1,<SHORT:mask>
2441 l<SHORT:size>u\t%0,%1"
2442 [(set_attr "type" "logical,load")
2443 (set_attr "mode" "<GPR:MODE>")])
2445 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2446 [(set (match_operand:GPR 0 "register_operand" "=d")
2447 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2449 "ze<SHORT:size>\t%0"
2450 [(set_attr "type" "arith")
2451 (set_attr "mode" "<GPR:MODE>")])
2453 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2454 [(set (match_operand:GPR 0 "register_operand" "=d")
2455 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2457 "l<SHORT:size>u\t%0,%1"
2458 [(set_attr "type" "load")
2459 (set_attr "mode" "<GPR:MODE>")])
2461 (define_expand "zero_extendqihi2"
2462 [(set (match_operand:HI 0 "register_operand")
2463 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2466 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2468 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2474 (define_insn "*zero_extendqihi2"
2475 [(set (match_operand:HI 0 "register_operand" "=d,d")
2476 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2481 [(set_attr "type" "logical,load")
2482 (set_attr "mode" "HI")])
2484 (define_insn "*zero_extendqihi2_mips16"
2485 [(set (match_operand:HI 0 "register_operand" "=d")
2486 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2489 [(set_attr "type" "load")
2490 (set_attr "mode" "HI")])
2493 ;; ....................
2497 ;; ....................
2500 ;; Those for integer source operand are ordered widest source type first.
2502 ;; When TARGET_64BIT, all SImode integer registers should already be in
2503 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2504 ;; therefore get rid of register->register instructions if we constrain
2505 ;; the source to be in the same register as the destination.
2507 ;; The register alternative has type "arith" so that the pre-reload
2508 ;; scheduler will treat it as a move. This reflects what happens if
2509 ;; the register alternative needs a reload.
2510 (define_insn_and_split "extendsidi2"
2511 [(set (match_operand:DI 0 "register_operand" "=d,d")
2512 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2517 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2520 emit_note (NOTE_INSN_DELETED);
2523 [(set_attr "type" "arith,load")
2524 (set_attr "mode" "DI")])
2526 (define_expand "extend<SHORT:mode><GPR:mode>2"
2527 [(set (match_operand:GPR 0 "register_operand")
2528 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2531 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2532 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2533 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2537 l<SHORT:size>\t%0,%1"
2538 [(set_attr "type" "signext,load")
2539 (set_attr "mode" "<GPR:MODE>")])
2541 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2542 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2544 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2545 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2548 l<SHORT:size>\t%0,%1"
2549 "&& reload_completed && REG_P (operands[1])"
2550 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2551 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2553 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2554 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2555 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2557 [(set_attr "type" "arith,load")
2558 (set_attr "mode" "<GPR:MODE>")
2559 (set_attr "length" "8,*")])
2561 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2562 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2564 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2567 se<SHORT:size>\t%0,%1
2568 l<SHORT:size>\t%0,%1"
2569 [(set_attr "type" "signext,load")
2570 (set_attr "mode" "<GPR:MODE>")])
2572 (define_expand "extendqihi2"
2573 [(set (match_operand:HI 0 "register_operand")
2574 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2577 (define_insn "*extendqihi2_mips16e"
2578 [(set (match_operand:HI 0 "register_operand" "=d,d")
2579 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
2584 [(set_attr "type" "signext,load")
2585 (set_attr "mode" "SI")])
2587 (define_insn_and_split "*extendqihi2"
2588 [(set (match_operand:HI 0 "register_operand" "=d,d")
2590 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2591 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2595 "&& reload_completed && REG_P (operands[1])"
2596 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
2597 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
2599 operands[0] = gen_lowpart (SImode, operands[0]);
2600 operands[1] = gen_lowpart (SImode, operands[1]);
2601 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
2602 - GET_MODE_BITSIZE (QImode));
2604 [(set_attr "type" "multi,load")
2605 (set_attr "mode" "SI")
2606 (set_attr "length" "8,*")])
2608 (define_insn "*extendqihi2_seb"
2609 [(set (match_operand:HI 0 "register_operand" "=d,d")
2611 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2616 [(set_attr "type" "signext,load")
2617 (set_attr "mode" "SI")])
2619 (define_insn "extendsfdf2"
2620 [(set (match_operand:DF 0 "register_operand" "=f")
2621 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2622 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2624 [(set_attr "type" "fcvt")
2625 (set_attr "cnv_mode" "S2D")
2626 (set_attr "mode" "DF")])
2629 ;; ....................
2633 ;; ....................
2635 (define_expand "fix_truncdfsi2"
2636 [(set (match_operand:SI 0 "register_operand")
2637 (fix:SI (match_operand:DF 1 "register_operand")))]
2638 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2640 if (!ISA_HAS_TRUNC_W)
2642 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2647 (define_insn "fix_truncdfsi2_insn"
2648 [(set (match_operand:SI 0 "register_operand" "=f")
2649 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2650 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2652 [(set_attr "type" "fcvt")
2653 (set_attr "mode" "DF")
2654 (set_attr "cnv_mode" "D2I")
2655 (set_attr "length" "4")])
2657 (define_insn "fix_truncdfsi2_macro"
2658 [(set (match_operand:SI 0 "register_operand" "=f")
2659 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2660 (clobber (match_scratch:DF 2 "=d"))]
2661 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2664 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2666 return "trunc.w.d %0,%1,%2";
2668 [(set_attr "type" "fcvt")
2669 (set_attr "mode" "DF")
2670 (set_attr "cnv_mode" "D2I")
2671 (set_attr "length" "36")])
2673 (define_expand "fix_truncsfsi2"
2674 [(set (match_operand:SI 0 "register_operand")
2675 (fix:SI (match_operand:SF 1 "register_operand")))]
2678 if (!ISA_HAS_TRUNC_W)
2680 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2685 (define_insn "fix_truncsfsi2_insn"
2686 [(set (match_operand:SI 0 "register_operand" "=f")
2687 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2688 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2690 [(set_attr "type" "fcvt")
2691 (set_attr "mode" "SF")
2692 (set_attr "cnv_mode" "S2I")
2693 (set_attr "length" "4")])
2695 (define_insn "fix_truncsfsi2_macro"
2696 [(set (match_operand:SI 0 "register_operand" "=f")
2697 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2698 (clobber (match_scratch:SF 2 "=d"))]
2699 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2702 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2704 return "trunc.w.s %0,%1,%2";
2706 [(set_attr "type" "fcvt")
2707 (set_attr "mode" "SF")
2708 (set_attr "cnv_mode" "S2I")
2709 (set_attr "length" "36")])
2712 (define_insn "fix_truncdfdi2"
2713 [(set (match_operand:DI 0 "register_operand" "=f")
2714 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2715 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2717 [(set_attr "type" "fcvt")
2718 (set_attr "mode" "DF")
2719 (set_attr "cnv_mode" "D2I")
2720 (set_attr "length" "4")])
2723 (define_insn "fix_truncsfdi2"
2724 [(set (match_operand:DI 0 "register_operand" "=f")
2725 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2726 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2728 [(set_attr "type" "fcvt")
2729 (set_attr "mode" "SF")
2730 (set_attr "cnv_mode" "S2I")
2731 (set_attr "length" "4")])
2734 (define_insn "floatsidf2"
2735 [(set (match_operand:DF 0 "register_operand" "=f")
2736 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2737 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2739 [(set_attr "type" "fcvt")
2740 (set_attr "mode" "DF")
2741 (set_attr "cnv_mode" "I2D")
2742 (set_attr "length" "4")])
2745 (define_insn "floatdidf2"
2746 [(set (match_operand:DF 0 "register_operand" "=f")
2747 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2748 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2750 [(set_attr "type" "fcvt")
2751 (set_attr "mode" "DF")
2752 (set_attr "cnv_mode" "I2D")
2753 (set_attr "length" "4")])
2756 (define_insn "floatsisf2"
2757 [(set (match_operand:SF 0 "register_operand" "=f")
2758 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2761 [(set_attr "type" "fcvt")
2762 (set_attr "mode" "SF")
2763 (set_attr "cnv_mode" "I2S")
2764 (set_attr "length" "4")])
2767 (define_insn "floatdisf2"
2768 [(set (match_operand:SF 0 "register_operand" "=f")
2769 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2770 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2772 [(set_attr "type" "fcvt")
2773 (set_attr "mode" "SF")
2774 (set_attr "cnv_mode" "I2S")
2775 (set_attr "length" "4")])
2778 (define_expand "fixuns_truncdfsi2"
2779 [(set (match_operand:SI 0 "register_operand")
2780 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2781 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2783 rtx reg1 = gen_reg_rtx (DFmode);
2784 rtx reg2 = gen_reg_rtx (DFmode);
2785 rtx reg3 = gen_reg_rtx (SImode);
2786 rtx label1 = gen_label_rtx ();
2787 rtx label2 = gen_label_rtx ();
2788 REAL_VALUE_TYPE offset;
2790 real_2expN (&offset, 31);
2792 if (reg1) /* Turn off complaints about unreached code. */
2794 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2795 do_pending_stack_adjust ();
2797 emit_insn (gen_cmpdf (operands[1], reg1));
2798 emit_jump_insn (gen_bge (label1));
2800 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2801 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2802 gen_rtx_LABEL_REF (VOIDmode, label2)));
2805 emit_label (label1);
2806 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2807 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2808 (BITMASK_HIGH, SImode)));
2810 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2811 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2813 emit_label (label2);
2815 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2816 fields, and can't be used for REG_NOTES anyway). */
2817 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2823 (define_expand "fixuns_truncdfdi2"
2824 [(set (match_operand:DI 0 "register_operand")
2825 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2826 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2828 rtx reg1 = gen_reg_rtx (DFmode);
2829 rtx reg2 = gen_reg_rtx (DFmode);
2830 rtx reg3 = gen_reg_rtx (DImode);
2831 rtx label1 = gen_label_rtx ();
2832 rtx label2 = gen_label_rtx ();
2833 REAL_VALUE_TYPE offset;
2835 real_2expN (&offset, 63);
2837 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2838 do_pending_stack_adjust ();
2840 emit_insn (gen_cmpdf (operands[1], reg1));
2841 emit_jump_insn (gen_bge (label1));
2843 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2844 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2845 gen_rtx_LABEL_REF (VOIDmode, label2)));
2848 emit_label (label1);
2849 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2850 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2851 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2853 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2854 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2856 emit_label (label2);
2858 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2859 fields, and can't be used for REG_NOTES anyway). */
2860 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2865 (define_expand "fixuns_truncsfsi2"
2866 [(set (match_operand:SI 0 "register_operand")
2867 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2870 rtx reg1 = gen_reg_rtx (SFmode);
2871 rtx reg2 = gen_reg_rtx (SFmode);
2872 rtx reg3 = gen_reg_rtx (SImode);
2873 rtx label1 = gen_label_rtx ();
2874 rtx label2 = gen_label_rtx ();
2875 REAL_VALUE_TYPE offset;
2877 real_2expN (&offset, 31);
2879 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2880 do_pending_stack_adjust ();
2882 emit_insn (gen_cmpsf (operands[1], reg1));
2883 emit_jump_insn (gen_bge (label1));
2885 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2886 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2887 gen_rtx_LABEL_REF (VOIDmode, label2)));
2890 emit_label (label1);
2891 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2892 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2893 (BITMASK_HIGH, SImode)));
2895 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2896 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2898 emit_label (label2);
2900 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2901 fields, and can't be used for REG_NOTES anyway). */
2902 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2907 (define_expand "fixuns_truncsfdi2"
2908 [(set (match_operand:DI 0 "register_operand")
2909 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
2910 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2912 rtx reg1 = gen_reg_rtx (SFmode);
2913 rtx reg2 = gen_reg_rtx (SFmode);
2914 rtx reg3 = gen_reg_rtx (DImode);
2915 rtx label1 = gen_label_rtx ();
2916 rtx label2 = gen_label_rtx ();
2917 REAL_VALUE_TYPE offset;
2919 real_2expN (&offset, 63);
2921 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2922 do_pending_stack_adjust ();
2924 emit_insn (gen_cmpsf (operands[1], reg1));
2925 emit_jump_insn (gen_bge (label1));
2927 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
2928 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2929 gen_rtx_LABEL_REF (VOIDmode, label2)));
2932 emit_label (label1);
2933 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2934 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2935 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2937 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
2938 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2940 emit_label (label2);
2942 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2943 fields, and can't be used for REG_NOTES anyway). */
2944 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2949 ;; ....................
2953 ;; ....................
2955 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
2957 (define_expand "extv"
2958 [(set (match_operand 0 "register_operand")
2959 (sign_extract (match_operand:QI 1 "memory_operand")
2960 (match_operand 2 "immediate_operand")
2961 (match_operand 3 "immediate_operand")))]
2964 if (mips_expand_unaligned_load (operands[0], operands[1],
2965 INTVAL (operands[2]),
2966 INTVAL (operands[3])))
2972 (define_expand "extzv"
2973 [(set (match_operand 0 "register_operand")
2974 (zero_extract (match_operand 1 "nonimmediate_operand")
2975 (match_operand 2 "immediate_operand")
2976 (match_operand 3 "immediate_operand")))]
2979 if (mips_expand_unaligned_load (operands[0], operands[1],
2980 INTVAL (operands[2]),
2981 INTVAL (operands[3])))
2983 else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3]))
2985 if (GET_MODE (operands[0]) == DImode)
2986 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
2989 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
2997 (define_insn "extzv<mode>"
2998 [(set (match_operand:GPR 0 "register_operand" "=d")
2999 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3000 (match_operand:SI 2 "immediate_operand" "I")
3001 (match_operand:SI 3 "immediate_operand" "I")))]
3002 "mips_use_ins_ext_p (operands[1], operands[2], operands[3])"
3003 "<d>ext\t%0,%1,%3,%2"
3004 [(set_attr "type" "arith")
3005 (set_attr "mode" "<MODE>")])
3008 (define_expand "insv"
3009 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3010 (match_operand 1 "immediate_operand")
3011 (match_operand 2 "immediate_operand"))
3012 (match_operand 3 "reg_or_0_operand"))]
3015 if (mips_expand_unaligned_store (operands[0], operands[3],
3016 INTVAL (operands[1]),
3017 INTVAL (operands[2])))
3019 else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2]))
3021 if (GET_MODE (operands[0]) == DImode)
3022 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3025 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3033 (define_insn "insv<mode>"
3034 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3035 (match_operand:SI 1 "immediate_operand" "I")
3036 (match_operand:SI 2 "immediate_operand" "I"))
3037 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3038 "mips_use_ins_ext_p (operands[0], operands[1], operands[2])"
3039 "<d>ins\t%0,%z3,%2,%1"
3040 [(set_attr "type" "arith")
3041 (set_attr "mode" "<MODE>")])
3043 ;; Unaligned word moves generated by the bit field patterns.
3045 ;; As far as the rtl is concerned, both the left-part and right-part
3046 ;; instructions can access the whole field. However, the real operand
3047 ;; refers to just the first or the last byte (depending on endianness).
3048 ;; We therefore use two memory operands to each instruction, one to
3049 ;; describe the rtl effect and one to use in the assembly output.
3051 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3052 ;; This allows us to use the standard length calculations for the "load"
3053 ;; and "store" type attributes.
3055 (define_insn "mov_<load>l"
3056 [(set (match_operand:GPR 0 "register_operand" "=d")
3057 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3058 (match_operand:QI 2 "memory_operand" "m")]
3060 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3062 [(set_attr "type" "load")
3063 (set_attr "mode" "<MODE>")])
3065 (define_insn "mov_<load>r"
3066 [(set (match_operand:GPR 0 "register_operand" "=d")
3067 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3068 (match_operand:QI 2 "memory_operand" "m")
3069 (match_operand:GPR 3 "register_operand" "0")]
3070 UNSPEC_LOAD_RIGHT))]
3071 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3073 [(set_attr "type" "load")
3074 (set_attr "mode" "<MODE>")])
3076 (define_insn "mov_<store>l"
3077 [(set (match_operand:BLK 0 "memory_operand" "=m")
3078 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3079 (match_operand:QI 2 "memory_operand" "m")]
3080 UNSPEC_STORE_LEFT))]
3081 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3083 [(set_attr "type" "store")
3084 (set_attr "mode" "<MODE>")])
3086 (define_insn "mov_<store>r"
3087 [(set (match_operand:BLK 0 "memory_operand" "+m")
3088 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3089 (match_operand:QI 2 "memory_operand" "m")
3091 UNSPEC_STORE_RIGHT))]
3092 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3094 [(set_attr "type" "store")
3095 (set_attr "mode" "<MODE>")])
3097 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3098 ;; The required value is:
3100 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3102 ;; which translates to:
3104 ;; lui op0,%highest(op1)
3105 ;; daddiu op0,op0,%higher(op1)
3107 ;; daddiu op0,op0,%hi(op1)
3110 ;; The split is deferred until after flow2 to allow the peephole2 below
3112 (define_insn_and_split "*lea_high64"
3113 [(set (match_operand:DI 0 "register_operand" "=d")
3114 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3115 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3117 "&& epilogue_completed"
3118 [(set (match_dup 0) (high:DI (match_dup 2)))
3119 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3120 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3121 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3122 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3124 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3125 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3127 [(set_attr "length" "20")])
3129 ;; Use a scratch register to reduce the latency of the above pattern
3130 ;; on superscalar machines. The optimized sequence is:
3132 ;; lui op1,%highest(op2)
3134 ;; daddiu op1,op1,%higher(op2)
3136 ;; daddu op1,op1,op0
3138 [(set (match_operand:DI 1 "register_operand")
3139 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3140 (match_scratch:DI 0 "d")]
3141 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3142 [(set (match_dup 1) (high:DI (match_dup 3)))
3143 (set (match_dup 0) (high:DI (match_dup 4)))
3144 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3145 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3146 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3148 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3149 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3152 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3153 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3154 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3155 ;; used once. We can then use the sequence:
3157 ;; lui op0,%highest(op1)
3159 ;; daddiu op0,op0,%higher(op1)
3160 ;; daddiu op2,op2,%lo(op1)
3162 ;; daddu op0,op0,op2
3164 ;; which takes 4 cycles on most superscalar targets.
3165 (define_insn_and_split "*lea64"
3166 [(set (match_operand:DI 0 "register_operand" "=d")
3167 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3168 (clobber (match_scratch:DI 2 "=&d"))]
3169 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3171 "&& reload_completed"
3172 [(set (match_dup 0) (high:DI (match_dup 3)))
3173 (set (match_dup 2) (high:DI (match_dup 4)))
3174 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3175 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3176 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3177 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3179 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3180 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3182 [(set_attr "length" "24")])
3184 ;; Insns to fetch a symbol from a big GOT.
3186 (define_insn_and_split "*xgot_hi<mode>"
3187 [(set (match_operand:P 0 "register_operand" "=d")
3188 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3189 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3191 "&& reload_completed"
3192 [(set (match_dup 0) (high:P (match_dup 2)))
3193 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3195 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3196 operands[3] = pic_offset_table_rtx;
3198 [(set_attr "got" "xgot_high")
3199 (set_attr "mode" "<MODE>")])
3201 (define_insn_and_split "*xgot_lo<mode>"
3202 [(set (match_operand:P 0 "register_operand" "=d")
3203 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3204 (match_operand:P 2 "got_disp_operand" "")))]
3205 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3207 "&& reload_completed"
3209 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3210 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3211 [(set_attr "got" "load")
3212 (set_attr "mode" "<MODE>")])
3214 ;; Insns to fetch a symbol from a normal GOT.
3216 (define_insn_and_split "*got_disp<mode>"
3217 [(set (match_operand:P 0 "register_operand" "=d")
3218 (match_operand:P 1 "got_disp_operand" ""))]
3219 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
3221 "&& reload_completed"
3223 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3225 operands[2] = pic_offset_table_rtx;
3226 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3228 [(set_attr "got" "load")
3229 (set_attr "mode" "<MODE>")])
3231 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3233 (define_insn_and_split "*got_page<mode>"
3234 [(set (match_operand:P 0 "register_operand" "=d")
3235 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3236 "TARGET_EXPLICIT_RELOCS"
3238 "&& reload_completed"
3240 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3242 operands[2] = pic_offset_table_rtx;
3243 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3245 [(set_attr "got" "load")
3246 (set_attr "mode" "<MODE>")])
3248 ;; Lower-level instructions for loading an address from the GOT.
3249 ;; We could use MEMs, but an unspec gives more optimization
3252 (define_insn "load_got<mode>"
3253 [(set (match_operand:P 0 "register_operand" "=d")
3254 (unspec:P [(match_operand:P 1 "register_operand" "d")
3255 (match_operand:P 2 "immediate_operand" "")]
3258 "<load>\t%0,%R2(%1)"
3259 [(set_attr "type" "load")
3260 (set_attr "mode" "<MODE>")
3261 (set_attr "length" "4")])
3263 ;; Instructions for adding the low 16 bits of an address to a register.
3264 ;; Operand 2 is the address: print_operand works out which relocation
3265 ;; should be applied.
3267 (define_insn "*low<mode>"
3268 [(set (match_operand:P 0 "register_operand" "=d")
3269 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3270 (match_operand:P 2 "immediate_operand" "")))]
3272 "<d>addiu\t%0,%1,%R2"
3273 [(set_attr "type" "arith")
3274 (set_attr "mode" "<MODE>")])
3276 (define_insn "*low<mode>_mips16"
3277 [(set (match_operand:P 0 "register_operand" "=d")
3278 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3279 (match_operand:P 2 "immediate_operand" "")))]
3282 [(set_attr "type" "arith")
3283 (set_attr "mode" "<MODE>")
3284 (set_attr "length" "8")])
3286 ;; Allow combine to split complex const_int load sequences, using operand 2
3287 ;; to store the intermediate results. See move_operand for details.
3289 [(set (match_operand:GPR 0 "register_operand")
3290 (match_operand:GPR 1 "splittable_const_int_operand"))
3291 (clobber (match_operand:GPR 2 "register_operand"))]
3295 mips_move_integer (operands[0], operands[2], INTVAL (operands[1]));
3299 ;; Likewise, for symbolic operands.
3301 [(set (match_operand:P 0 "register_operand")
3302 (match_operand:P 1))
3303 (clobber (match_operand:P 2 "register_operand"))]
3304 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3305 [(set (match_dup 0) (match_dup 3))]
3307 mips_split_symbol (operands[2], operands[1],
3308 MAX_MACHINE_MODE, &operands[3]);
3311 ;; 64-bit integer moves
3313 ;; Unlike most other insns, the move insns can't be split with
3314 ;; different predicates, because register spilling and other parts of
3315 ;; the compiler, have memoized the insn number already.
3317 (define_expand "movdi"
3318 [(set (match_operand:DI 0 "")
3319 (match_operand:DI 1 ""))]
3322 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3326 ;; For mips16, we need a special case to handle storing $31 into
3327 ;; memory, since we don't have a constraint to match $31. This
3328 ;; instruction can be generated by save_restore_insns.
3330 (define_insn "*mov<mode>_ra"
3331 [(set (match_operand:GPR 0 "stack_operand" "=m")
3335 [(set_attr "type" "store")
3336 (set_attr "mode" "<MODE>")])
3338 (define_insn "*movdi_32bit"
3339 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3340 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3341 "!TARGET_64BIT && !TARGET_FLOAT64 && !TARGET_MIPS16
3342 && (register_operand (operands[0], DImode)
3343 || reg_or_0_operand (operands[1], DImode))"
3344 { return mips_output_move (operands[0], operands[1]); }
3345 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store")
3346 (set_attr "mode" "DI")
3347 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3349 (define_insn "*movdi_gp32_fp64"
3350 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*f,*d,*m")
3351 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*f,*J*d,*m,*f,*f"))]
3352 "!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
3353 && (register_operand (operands[0], DImode)
3354 || reg_or_0_operand (operands[1], DImode))"
3355 { return mips_output_move (operands[0], operands[1]); }
3356 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,fmove,mtc,fpload,mfc,fpstore")
3357 (set_attr "mode" "DI")
3358 (set_attr "length" "8,16,*,*,8,8,4,8,*,8,*")])
3360 (define_insn "*movdi_32bit_mips16"
3361 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3362 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3363 "!TARGET_64BIT && TARGET_MIPS16
3364 && (register_operand (operands[0], DImode)
3365 || register_operand (operands[1], DImode))"
3366 { return mips_output_move (operands[0], operands[1]); }
3367 [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo")
3368 (set_attr "mode" "DI")
3369 (set_attr "length" "8,8,8,8,12,*,*,8")])
3371 (define_insn "*movdi_64bit"
3372 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3373 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3374 "TARGET_64BIT && !TARGET_MIPS16
3375 && (register_operand (operands[0], DImode)
3376 || reg_or_0_operand (operands[1], DImode))"
3377 { return mips_output_move (operands[0], operands[1]); }
3378 [(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
3379 (set_attr "mode" "DI")
3380 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
3382 (define_insn "*movdi_64bit_mips16"
3383 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3384 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3385 "TARGET_64BIT && TARGET_MIPS16
3386 && (register_operand (operands[0], DImode)
3387 || register_operand (operands[1], DImode))"
3388 { return mips_output_move (operands[0], operands[1]); }
3389 [(set_attr "type" "move,move,move,arith,arith,const,load,store")
3390 (set_attr "mode" "DI")
3391 (set_attr_alternative "length"
3395 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3398 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3403 (const_string "*")])])
3406 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3407 ;; when the original load is a 4 byte instruction but the add and the
3408 ;; load are 2 2 byte instructions.
3411 [(set (match_operand:DI 0 "register_operand")
3412 (mem:DI (plus:DI (match_dup 0)
3413 (match_operand:DI 1 "const_int_operand"))))]
3414 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3415 && !TARGET_DEBUG_D_MODE
3416 && REG_P (operands[0])
3417 && M16_REG_P (REGNO (operands[0]))
3418 && GET_CODE (operands[1]) == CONST_INT
3419 && ((INTVAL (operands[1]) < 0
3420 && INTVAL (operands[1]) >= -0x10)
3421 || (INTVAL (operands[1]) >= 32 * 8
3422 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3423 || (INTVAL (operands[1]) >= 0
3424 && INTVAL (operands[1]) < 32 * 8
3425 && (INTVAL (operands[1]) & 7) != 0))"
3426 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3427 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3429 HOST_WIDE_INT val = INTVAL (operands[1]);
3432 operands[2] = const0_rtx;
3433 else if (val >= 32 * 8)
3437 operands[1] = GEN_INT (0x8 + off);
3438 operands[2] = GEN_INT (val - off - 0x8);
3444 operands[1] = GEN_INT (off);
3445 operands[2] = GEN_INT (val - off);
3449 ;; 32-bit Integer moves
3451 ;; Unlike most other insns, the move insns can't be split with
3452 ;; different predicates, because register spilling and other parts of
3453 ;; the compiler, have memoized the insn number already.
3455 (define_expand "movsi"
3456 [(set (match_operand:SI 0 "")
3457 (match_operand:SI 1 ""))]
3460 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3464 ;; The difference between these two is whether or not ints are allowed
3465 ;; in FP registers (off by default, use -mdebugh to enable).
3467 (define_insn "*movsi_internal"
3468 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3469 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
3471 && (register_operand (operands[0], SImode)
3472 || reg_or_0_operand (operands[1], SImode))"
3473 { return mips_output_move (operands[0], operands[1]); }
3474 [(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
3475 (set_attr "mode" "SI")
3476 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
3478 (define_insn "*movsi_mips16"
3479 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3480 (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3482 && (register_operand (operands[0], SImode)
3483 || register_operand (operands[1], SImode))"
3484 { return mips_output_move (operands[0], operands[1]); }
3485 [(set_attr "type" "move,move,move,arith,arith,const,load,store")
3486 (set_attr "mode" "SI")
3487 (set_attr_alternative "length"
3491 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3494 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3499 (const_string "*")])])
3501 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3502 ;; when the original load is a 4 byte instruction but the add and the
3503 ;; load are 2 2 byte instructions.
3506 [(set (match_operand:SI 0 "register_operand")
3507 (mem:SI (plus:SI (match_dup 0)
3508 (match_operand:SI 1 "const_int_operand"))))]
3509 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3510 && REG_P (operands[0])
3511 && M16_REG_P (REGNO (operands[0]))
3512 && GET_CODE (operands[1]) == CONST_INT
3513 && ((INTVAL (operands[1]) < 0
3514 && INTVAL (operands[1]) >= -0x80)
3515 || (INTVAL (operands[1]) >= 32 * 4
3516 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3517 || (INTVAL (operands[1]) >= 0
3518 && INTVAL (operands[1]) < 32 * 4
3519 && (INTVAL (operands[1]) & 3) != 0))"
3520 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3521 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3523 HOST_WIDE_INT val = INTVAL (operands[1]);
3526 operands[2] = const0_rtx;
3527 else if (val >= 32 * 4)
3531 operands[1] = GEN_INT (0x7c + off);
3532 operands[2] = GEN_INT (val - off - 0x7c);
3538 operands[1] = GEN_INT (off);
3539 operands[2] = GEN_INT (val - off);
3543 ;; On the mips16, we can split a load of certain constants into a load
3544 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3548 [(set (match_operand:SI 0 "register_operand")
3549 (match_operand:SI 1 "const_int_operand"))]
3550 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3551 && REG_P (operands[0])
3552 && M16_REG_P (REGNO (operands[0]))
3553 && GET_CODE (operands[1]) == CONST_INT
3554 && INTVAL (operands[1]) >= 0x100
3555 && INTVAL (operands[1]) <= 0xff + 0x7f"
3556 [(set (match_dup 0) (match_dup 1))
3557 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3559 int val = INTVAL (operands[1]);
3561 operands[1] = GEN_INT (0xff);
3562 operands[2] = GEN_INT (val - 0xff);
3565 ;; This insn handles moving CCmode values. It's really just a
3566 ;; slightly simplified copy of movsi_internal2, with additional cases
3567 ;; to move a condition register to a general register and to move
3568 ;; between the general registers and the floating point registers.
3570 (define_insn "movcc"
3571 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3572 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3573 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3574 { return mips_output_move (operands[0], operands[1]); }
3575 [(set_attr "type" "multi,move,load,store,mfc,mtc,fmove,fpload,fpstore")
3576 (set_attr "mode" "SI")
3577 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3579 ;; Reload condition code registers. reload_incc and reload_outcc
3580 ;; both handle moves from arbitrary operands into condition code
3581 ;; registers. reload_incc handles the more common case in which
3582 ;; a source operand is constrained to be in a condition-code
3583 ;; register, but has not been allocated to one.
3585 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3586 ;; constraints do not include 'z'. reload_outcc handles the case
3587 ;; when such an operand is allocated to a condition-code register.
3589 ;; Note that reloads from a condition code register to some
3590 ;; other location can be done using ordinary moves. Moving
3591 ;; into a GPR takes a single movcc, moving elsewhere takes
3592 ;; two. We can leave these cases to the generic reload code.
3593 (define_expand "reload_incc"
3594 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3595 (match_operand:CC 1 "general_operand" ""))
3596 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3597 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3599 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3603 (define_expand "reload_outcc"
3604 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3605 (match_operand:CC 1 "register_operand" ""))
3606 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3607 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3609 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3613 ;; MIPS4 supports loading and storing a floating point register from
3614 ;; the sum of two general registers. We use two versions for each of
3615 ;; these four instructions: one where the two general registers are
3616 ;; SImode, and one where they are DImode. This is because general
3617 ;; registers will be in SImode when they hold 32-bit values, but,
3618 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
3619 ;; instructions will still work correctly.
3621 ;; ??? Perhaps it would be better to support these instructions by
3622 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3623 ;; these instructions can only be used to load and store floating
3624 ;; point registers, that would probably cause trouble in reload.
3626 (define_insn "*<ANYF:loadx>_<P:mode>"
3627 [(set (match_operand:ANYF 0 "register_operand" "=f")
3628 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3629 (match_operand:P 2 "register_operand" "d"))))]
3631 "<ANYF:loadx>\t%0,%1(%2)"
3632 [(set_attr "type" "fpidxload")
3633 (set_attr "mode" "<ANYF:UNITMODE>")])
3635 (define_insn "*<ANYF:storex>_<P:mode>"
3636 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3637 (match_operand:P 2 "register_operand" "d")))
3638 (match_operand:ANYF 0 "register_operand" "f"))]
3640 "<ANYF:storex>\t%0,%1(%2)"
3641 [(set_attr "type" "fpidxstore")
3642 (set_attr "mode" "<ANYF:UNITMODE>")])
3644 ;; Scaled indexed address load.
3645 ;; Per md.texi, we only need to look for a pattern with multiply in the
3646 ;; address expression, not shift.
3648 (define_insn "*lwxs"
3649 [(set (match_operand:SI 0 "register_operand" "=d")
3650 (mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
3652 (match_operand:SI 2 "register_operand" "d"))))]
3655 [(set_attr "type" "load")
3656 (set_attr "mode" "SI")
3657 (set_attr "length" "4")])
3659 ;; 16-bit Integer moves
3661 ;; Unlike most other insns, the move insns can't be split with
3662 ;; different predicates, because register spilling and other parts of
3663 ;; the compiler, have memoized the insn number already.
3664 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3666 (define_expand "movhi"
3667 [(set (match_operand:HI 0 "")
3668 (match_operand:HI 1 ""))]
3671 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3675 (define_insn "*movhi_internal"
3676 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3677 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3679 && (register_operand (operands[0], HImode)
3680 || reg_or_0_operand (operands[1], HImode))"
3690 [(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
3691 (set_attr "mode" "HI")
3692 (set_attr "length" "4,4,*,*,4,4,4,4")])
3694 (define_insn "*movhi_mips16"
3695 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3696 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3698 && (register_operand (operands[0], HImode)
3699 || register_operand (operands[1], HImode))"
3708 [(set_attr "type" "move,move,move,arith,arith,load,store")
3709 (set_attr "mode" "HI")
3710 (set_attr_alternative "length"
3714 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3717 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3721 (const_string "*")])])
3724 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3725 ;; when the original load is a 4 byte instruction but the add and the
3726 ;; load are 2 2 byte instructions.
3729 [(set (match_operand:HI 0 "register_operand")
3730 (mem:HI (plus:SI (match_dup 0)
3731 (match_operand:SI 1 "const_int_operand"))))]
3732 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3733 && REG_P (operands[0])
3734 && M16_REG_P (REGNO (operands[0]))
3735 && GET_CODE (operands[1]) == CONST_INT
3736 && ((INTVAL (operands[1]) < 0
3737 && INTVAL (operands[1]) >= -0x80)
3738 || (INTVAL (operands[1]) >= 32 * 2
3739 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3740 || (INTVAL (operands[1]) >= 0
3741 && INTVAL (operands[1]) < 32 * 2
3742 && (INTVAL (operands[1]) & 1) != 0))"
3743 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3744 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3746 HOST_WIDE_INT val = INTVAL (operands[1]);
3749 operands[2] = const0_rtx;
3750 else if (val >= 32 * 2)
3754 operands[1] = GEN_INT (0x7e + off);
3755 operands[2] = GEN_INT (val - off - 0x7e);
3761 operands[1] = GEN_INT (off);
3762 operands[2] = GEN_INT (val - off);
3766 ;; 8-bit Integer moves
3768 ;; Unlike most other insns, the move insns can't be split with
3769 ;; different predicates, because register spilling and other parts of
3770 ;; the compiler, have memoized the insn number already.
3771 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3773 (define_expand "movqi"
3774 [(set (match_operand:QI 0 "")
3775 (match_operand:QI 1 ""))]
3778 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3782 (define_insn "*movqi_internal"
3783 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3784 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3786 && (register_operand (operands[0], QImode)
3787 || reg_or_0_operand (operands[1], QImode))"
3797 [(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
3798 (set_attr "mode" "QI")
3799 (set_attr "length" "4,4,*,*,4,4,4,4")])
3801 (define_insn "*movqi_mips16"
3802 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3803 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3805 && (register_operand (operands[0], QImode)
3806 || register_operand (operands[1], QImode))"
3815 [(set_attr "type" "move,move,move,arith,arith,load,store")
3816 (set_attr "mode" "QI")
3817 (set_attr "length" "4,4,4,4,8,*,*")])
3819 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3820 ;; when the original load is a 4 byte instruction but the add and the
3821 ;; load are 2 2 byte instructions.
3824 [(set (match_operand:QI 0 "register_operand")
3825 (mem:QI (plus:SI (match_dup 0)
3826 (match_operand:SI 1 "const_int_operand"))))]
3827 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3828 && REG_P (operands[0])
3829 && M16_REG_P (REGNO (operands[0]))
3830 && GET_CODE (operands[1]) == CONST_INT
3831 && ((INTVAL (operands[1]) < 0
3832 && INTVAL (operands[1]) >= -0x80)
3833 || (INTVAL (operands[1]) >= 32
3834 && INTVAL (operands[1]) <= 31 + 0x7f))"
3835 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3836 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3838 HOST_WIDE_INT val = INTVAL (operands[1]);
3841 operands[2] = const0_rtx;
3844 operands[1] = GEN_INT (0x7f);
3845 operands[2] = GEN_INT (val - 0x7f);
3849 ;; 32-bit floating point moves
3851 (define_expand "movsf"
3852 [(set (match_operand:SF 0 "")
3853 (match_operand:SF 1 ""))]
3856 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3860 (define_insn "*movsf_hardfloat"
3861 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3862 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3864 && (register_operand (operands[0], SFmode)
3865 || reg_or_0_operand (operands[1], SFmode))"
3866 { return mips_output_move (operands[0], operands[1]); }
3867 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3868 (set_attr "mode" "SF")
3869 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3871 (define_insn "*movsf_softfloat"
3872 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3873 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3874 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3875 && (register_operand (operands[0], SFmode)
3876 || reg_or_0_operand (operands[1], SFmode))"
3877 { return mips_output_move (operands[0], operands[1]); }
3878 [(set_attr "type" "move,load,store")
3879 (set_attr "mode" "SF")
3880 (set_attr "length" "4,*,*")])
3882 (define_insn "*movsf_mips16"
3883 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
3884 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
3886 && (register_operand (operands[0], SFmode)
3887 || register_operand (operands[1], SFmode))"
3888 { return mips_output_move (operands[0], operands[1]); }
3889 [(set_attr "type" "move,move,move,load,store")
3890 (set_attr "mode" "SF")
3891 (set_attr "length" "4,4,4,*,*")])
3894 ;; 64-bit floating point moves
3896 (define_expand "movdf"
3897 [(set (match_operand:DF 0 "")
3898 (match_operand:DF 1 ""))]
3901 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
3905 (define_insn "*movdf_hardfloat_64bit"
3906 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3907 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3908 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
3909 && (register_operand (operands[0], DFmode)
3910 || reg_or_0_operand (operands[1], DFmode))"
3911 { return mips_output_move (operands[0], operands[1]); }
3912 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3913 (set_attr "mode" "DF")
3914 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3916 ;; This pattern applies to both !TARGET_FLOAT64 and TARGET_FLOAT64.
3917 (define_insn "*movdf_hardfloat_32bit"
3918 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3919 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3920 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
3921 && (register_operand (operands[0], DFmode)
3922 || reg_or_0_operand (operands[1], DFmode))"
3923 { return mips_output_move (operands[0], operands[1]); }
3924 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3925 (set_attr "mode" "DF")
3926 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
3928 (define_insn "*movdf_softfloat"
3929 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
3930 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
3931 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
3932 && (register_operand (operands[0], DFmode)
3933 || reg_or_0_operand (operands[1], DFmode))"
3934 { return mips_output_move (operands[0], operands[1]); }
3935 [(set_attr "type" "multi,load,store,mfc,mtc,fmove")
3936 (set_attr "mode" "DF")
3937 (set_attr "length" "8,*,*,4,4,4")])
3939 (define_insn "*movdf_mips16"
3940 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
3941 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
3943 && (register_operand (operands[0], DFmode)
3944 || register_operand (operands[1], DFmode))"
3945 { return mips_output_move (operands[0], operands[1]); }
3946 [(set_attr "type" "multi,multi,multi,load,store")
3947 (set_attr "mode" "DF")
3948 (set_attr "length" "8,8,8,*,*")])
3951 [(set (match_operand:DI 0 "nonimmediate_operand")
3952 (match_operand:DI 1 "move_operand"))]
3953 "reload_completed && !TARGET_64BIT
3954 && mips_split_64bit_move_p (operands[0], operands[1])"
3957 mips_split_64bit_move (operands[0], operands[1]);
3962 [(set (match_operand:DF 0 "nonimmediate_operand")
3963 (match_operand:DF 1 "move_operand"))]
3964 "reload_completed && !TARGET_64BIT
3965 && mips_split_64bit_move_p (operands[0], operands[1])"
3968 mips_split_64bit_move (operands[0], operands[1]);
3972 ;; When generating mips16 code, split moves of negative constants into
3973 ;; a positive "li" followed by a negation.
3975 [(set (match_operand 0 "register_operand")
3976 (match_operand 1 "const_int_operand"))]
3977 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
3981 (neg:SI (match_dup 2)))]
3983 operands[2] = gen_lowpart (SImode, operands[0]);
3984 operands[3] = GEN_INT (-INTVAL (operands[1]));
3987 ;; 64-bit paired-single floating point moves
3989 (define_expand "movv2sf"
3990 [(set (match_operand:V2SF 0)
3991 (match_operand:V2SF 1))]
3992 "TARGET_PAIRED_SINGLE_FLOAT"
3994 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
3998 (define_insn "movv2sf_hardfloat_64bit"
3999 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4000 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4001 "TARGET_PAIRED_SINGLE_FLOAT
4003 && (register_operand (operands[0], V2SFmode)
4004 || reg_or_0_operand (operands[1], V2SFmode))"
4005 { return mips_output_move (operands[0], operands[1]); }
4006 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4007 (set_attr "mode" "SF")
4008 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
4010 ;; The HI and LO registers are not truly independent. If we move an mthi
4011 ;; instruction before an mflo instruction, it will make the result of the
4012 ;; mflo unpredictable. The same goes for mtlo and mfhi.
4014 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
4015 ;; Operand 1 is the register we want, operand 2 is the other one.
4017 ;; When generating VR4120 or VR4130 code, we use macc{,hi} and
4018 ;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
4019 ;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
4021 (define_expand "mfhilo_<mode>"
4022 [(set (match_operand:GPR 0 "register_operand")
4023 (unspec:GPR [(match_operand:GPR 1 "register_operand")
4024 (match_operand:GPR 2 "register_operand")]
4027 (define_insn "*mfhilo_<mode>"
4028 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4029 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4030 (match_operand:GPR 2 "register_operand" "l,h")]
4034 [(set_attr "type" "mfhilo")
4035 (set_attr "mode" "<MODE>")])
4037 (define_insn "*mfhilo_<mode>_macc"
4038 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4039 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4040 (match_operand:GPR 2 "register_operand" "l,h")]
4046 [(set_attr "type" "mfhilo")
4047 (set_attr "mode" "<MODE>")])
4049 ;; Patterns for loading or storing part of a paired floating point
4050 ;; register. We need them because odd-numbered floating-point registers
4051 ;; are not fully independent: see mips_split_64bit_move.
4053 ;; Load the low word of operand 0 with operand 1.
4054 (define_insn "load_df_low"
4055 [(set (match_operand:DF 0 "register_operand" "=f,f")
4056 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
4057 UNSPEC_LOAD_DF_LOW))]
4058 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4060 operands[0] = mips_subword (operands[0], 0);
4061 return mips_output_move (operands[0], operands[1]);
4063 [(set_attr "type" "mtc,fpload")
4064 (set_attr "mode" "SF")])
4066 ;; Load the high word of operand 0 from operand 1, preserving the value
4068 (define_insn "load_df_high"
4069 [(set (match_operand:DF 0 "register_operand" "=f,f")
4070 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
4071 (match_operand:DF 2 "register_operand" "0,0")]
4072 UNSPEC_LOAD_DF_HIGH))]
4073 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4075 operands[0] = mips_subword (operands[0], 1);
4076 return mips_output_move (operands[0], operands[1]);
4078 [(set_attr "type" "mtc,fpload")
4079 (set_attr "mode" "SF")])
4081 ;; Store the high word of operand 1 in operand 0. The corresponding
4082 ;; low-word move is done in the normal way.
4083 (define_insn "store_df_high"
4084 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
4085 (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
4086 UNSPEC_STORE_DF_HIGH))]
4087 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4089 operands[1] = mips_subword (operands[1], 1);
4090 return mips_output_move (operands[0], operands[1]);
4092 [(set_attr "type" "mfc,fpstore")
4093 (set_attr "mode" "SF")])
4095 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4096 ;; value in the low word.
4097 (define_insn "mthc1"
4098 [(set (match_operand:DF 0 "register_operand" "=f")
4099 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ")
4100 (match_operand:DF 2 "register_operand" "0")]
4102 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4104 [(set_attr "type" "mtc")
4105 (set_attr "mode" "SF")])
4107 ;; Move high word of operand 1 to operand 0 using mfhc1. The corresponding
4108 ;; low-word move is done in the normal way.
4109 (define_insn "mfhc1"
4110 [(set (match_operand:SI 0 "register_operand" "=d")
4111 (unspec:SI [(match_operand:DF 1 "register_operand" "f")]
4113 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4115 [(set_attr "type" "mfc")
4116 (set_attr "mode" "SF")])
4118 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4119 (define_expand "load_const_gp"
4120 [(set (match_operand 0 "register_operand" "=d")
4121 (const (unspec [(const_int 0)] UNSPEC_GP)))])
4123 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4124 ;; of _gp from the start of this function. Operand 1 is the incoming
4125 ;; function address.
4126 (define_insn_and_split "loadgp_newabi"
4127 [(unspec_volatile [(match_operand 0 "" "")
4128 (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
4129 "mips_current_loadgp_style () == LOADGP_NEWABI"
4132 [(set (match_dup 2) (match_dup 3))
4133 (set (match_dup 2) (match_dup 4))
4134 (set (match_dup 2) (match_dup 5))]
4136 operands[2] = pic_offset_table_rtx;
4137 operands[3] = gen_rtx_HIGH (Pmode, operands[0]);
4138 operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]);
4139 operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]);
4141 [(set_attr "length" "12")])
4143 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4144 (define_insn_and_split "loadgp_absolute"
4145 [(unspec_volatile [(match_operand 0 "" "")] UNSPEC_LOADGP)]
4146 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4151 emit_move_insn (pic_offset_table_rtx, operands[0]);
4154 [(set_attr "length" "8")])
4156 ;; The use of gp is hidden when not using explicit relocations.
4157 ;; This blockage instruction prevents the gp load from being
4158 ;; scheduled after an implicit use of gp. It also prevents
4159 ;; the load from being deleted as dead.
4160 (define_insn "loadgp_blockage"
4161 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
4164 [(set_attr "type" "unknown")
4165 (set_attr "mode" "none")
4166 (set_attr "length" "0")])
4168 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4169 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4170 (define_insn "loadgp_rtp"
4171 [(unspec_volatile [(match_operand 0 "symbol_ref_operand")
4172 (match_operand 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4173 "mips_current_loadgp_style () == LOADGP_RTP"
4175 [(set_attr "length" "12")])
4178 [(unspec_volatile [(match_operand:P 0 "symbol_ref_operand")
4179 (match_operand:P 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4180 "mips_current_loadgp_style () == LOADGP_RTP"
4181 [(set (match_dup 2) (high:P (match_dup 3)))
4182 (set (match_dup 2) (unspec:P [(match_dup 2)
4183 (match_dup 3)] UNSPEC_LOAD_GOT))
4184 (set (match_dup 2) (unspec:P [(match_dup 2)
4185 (match_dup 4)] UNSPEC_LOAD_GOT))]
4187 operands[2] = pic_offset_table_rtx;
4188 operands[3] = mips_unspec_address (operands[0], SYMBOL_ABSOLUTE);
4189 operands[4] = mips_unspec_address (operands[1], SYMBOL_HALF);
4192 ;; Emit a .cprestore directive, which normally expands to a single store
4193 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4194 ;; code so that jals inside inline asms will work correctly.
4195 (define_insn "cprestore"
4196 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
4201 if (set_nomacro && which_alternative == 1)
4202 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4204 return ".cprestore\t%0";
4206 [(set_attr "type" "store")
4207 (set_attr "length" "4,12")])
4209 ;; Expand in-line code to clear the instruction cache between operand[0] and
4211 (define_expand "clear_cache"
4212 [(match_operand 0 "pmode_register_operand")
4213 (match_operand 1 "pmode_register_operand")]
4219 mips_expand_synci_loop (operands[0], operands[1]);
4220 emit_insn (gen_sync ());
4221 emit_insn (gen_clear_hazard ());
4223 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4225 rtx len = gen_reg_rtx (Pmode);
4226 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4227 /* Flush both caches. We need to flush the data cache in case
4228 the system has a write-back cache. */
4229 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func),
4230 0, VOIDmode, 3, operands[0], Pmode, len, Pmode,
4231 GEN_INT (3), TYPE_MODE (integer_type_node));
4237 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4241 (define_insn "synci"
4242 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4247 (define_insn "rdhwr"
4248 [(set (match_operand:SI 0 "general_operand" "=d")
4249 (unspec_volatile [(match_operand:SI 1 "const_int_operand" "n")]
4254 (define_insn "clear_hazard"
4255 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4256 (clobber (reg:SI 31))]
4259 return ".set\tpush\n"
4260 "\t.set\tnoreorder\n"
4264 "1:\taddiu\t$31,$31,12\n"
4269 [(set_attr "length" "20")])
4271 ;; Block moves, see mips.c for more details.
4272 ;; Argument 0 is the destination
4273 ;; Argument 1 is the source
4274 ;; Argument 2 is the length
4275 ;; Argument 3 is the alignment
4277 (define_expand "movmemsi"
4278 [(parallel [(set (match_operand:BLK 0 "general_operand")
4279 (match_operand:BLK 1 "general_operand"))
4280 (use (match_operand:SI 2 ""))
4281 (use (match_operand:SI 3 "const_int_operand"))])]
4282 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4284 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4291 ;; ....................
4295 ;; ....................
4297 (define_expand "<optab><mode>3"
4298 [(set (match_operand:GPR 0 "register_operand")
4299 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4300 (match_operand:SI 2 "arith_operand")))]
4303 /* On the mips16, a shift of more than 8 is a four byte instruction,
4304 so, for a shift between 8 and 16, it is just as fast to do two
4305 shifts of 8 or less. If there is a lot of shifting going on, we
4306 may win in CSE. Otherwise combine will put the shifts back
4307 together again. This can be called by function_arg, so we must
4308 be careful not to allocate a new register if we've reached the
4312 && GET_CODE (operands[2]) == CONST_INT
4313 && INTVAL (operands[2]) > 8
4314 && INTVAL (operands[2]) <= 16
4315 && !reload_in_progress
4316 && !reload_completed)
4318 rtx temp = gen_reg_rtx (<MODE>mode);
4320 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4321 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4322 GEN_INT (INTVAL (operands[2]) - 8)));
4327 (define_insn "*<optab><mode>3"
4328 [(set (match_operand:GPR 0 "register_operand" "=d")
4329 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4330 (match_operand:SI 2 "arith_operand" "dI")))]
4333 if (GET_CODE (operands[2]) == CONST_INT)
4334 operands[2] = GEN_INT (INTVAL (operands[2])
4335 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4337 return "<d><insn>\t%0,%1,%2";
4339 [(set_attr "type" "shift")
4340 (set_attr "mode" "<MODE>")])
4342 (define_insn "*<optab>si3_extend"
4343 [(set (match_operand:DI 0 "register_operand" "=d")
4345 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4346 (match_operand:SI 2 "arith_operand" "dI"))))]
4347 "TARGET_64BIT && !TARGET_MIPS16"
4349 if (GET_CODE (operands[2]) == CONST_INT)
4350 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4352 return "<insn>\t%0,%1,%2";
4354 [(set_attr "type" "shift")
4355 (set_attr "mode" "SI")])
4357 (define_insn "*<optab>si3_mips16"
4358 [(set (match_operand:SI 0 "register_operand" "=d,d")
4359 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4360 (match_operand:SI 2 "arith_operand" "d,I")))]
4363 if (which_alternative == 0)
4364 return "<insn>\t%0,%2";
4366 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4367 return "<insn>\t%0,%1,%2";
4369 [(set_attr "type" "shift")
4370 (set_attr "mode" "SI")
4371 (set_attr_alternative "length"
4373 (if_then_else (match_operand 2 "m16_uimm3_b")
4377 ;; We need separate DImode MIPS16 patterns because of the irregularity
4379 (define_insn "*ashldi3_mips16"
4380 [(set (match_operand:DI 0 "register_operand" "=d,d")
4381 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4382 (match_operand:SI 2 "arith_operand" "d,I")))]
4383 "TARGET_64BIT && TARGET_MIPS16"
4385 if (which_alternative == 0)
4386 return "dsll\t%0,%2";
4388 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4389 return "dsll\t%0,%1,%2";
4391 [(set_attr "type" "shift")
4392 (set_attr "mode" "DI")
4393 (set_attr_alternative "length"
4395 (if_then_else (match_operand 2 "m16_uimm3_b")
4399 (define_insn "*ashrdi3_mips16"
4400 [(set (match_operand:DI 0 "register_operand" "=d,d")
4401 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4402 (match_operand:SI 2 "arith_operand" "d,I")))]
4403 "TARGET_64BIT && TARGET_MIPS16"
4405 if (GET_CODE (operands[2]) == CONST_INT)
4406 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4408 return "dsra\t%0,%2";
4410 [(set_attr "type" "shift")
4411 (set_attr "mode" "DI")
4412 (set_attr_alternative "length"
4414 (if_then_else (match_operand 2 "m16_uimm3_b")
4418 (define_insn "*lshrdi3_mips16"
4419 [(set (match_operand:DI 0 "register_operand" "=d,d")
4420 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4421 (match_operand:SI 2 "arith_operand" "d,I")))]
4422 "TARGET_64BIT && TARGET_MIPS16"
4424 if (GET_CODE (operands[2]) == CONST_INT)
4425 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4427 return "dsrl\t%0,%2";
4429 [(set_attr "type" "shift")
4430 (set_attr "mode" "DI")
4431 (set_attr_alternative "length"
4433 (if_then_else (match_operand 2 "m16_uimm3_b")
4437 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4440 [(set (match_operand:GPR 0 "register_operand")
4441 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4442 (match_operand:GPR 2 "const_int_operand")))]
4443 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4444 && GET_CODE (operands[2]) == CONST_INT
4445 && INTVAL (operands[2]) > 8
4446 && INTVAL (operands[2]) <= 16"
4447 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4448 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4449 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4451 ;; If we load a byte on the mips16 as a bitfield, the resulting
4452 ;; sequence of instructions is too complicated for combine, because it
4453 ;; involves four instructions: a load, a shift, a constant load into a
4454 ;; register, and an and (the key problem here is that the mips16 does
4455 ;; not have and immediate). We recognize a shift of a load in order
4456 ;; to make it simple enough for combine to understand.
4458 ;; The length here is the worst case: the length of the split version
4459 ;; will be more accurate.
4460 (define_insn_and_split ""
4461 [(set (match_operand:SI 0 "register_operand" "=d")
4462 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4463 (match_operand:SI 2 "immediate_operand" "I")))]
4467 [(set (match_dup 0) (match_dup 1))
4468 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4470 [(set_attr "type" "load")
4471 (set_attr "mode" "SI")
4472 (set_attr "length" "16")])
4474 (define_insn "rotr<mode>3"
4475 [(set (match_operand:GPR 0 "register_operand" "=d")
4476 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4477 (match_operand:SI 2 "arith_operand" "dI")))]
4480 if (GET_CODE (operands[2]) == CONST_INT)
4481 gcc_assert (INTVAL (operands[2]) >= 0
4482 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4484 return "<d>ror\t%0,%1,%2";
4486 [(set_attr "type" "shift")
4487 (set_attr "mode" "<MODE>")])
4490 ;; ....................
4494 ;; ....................
4496 ;; Flow here is rather complex:
4498 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4499 ;; into cmp_operands[] but generates no RTL.
4501 ;; 2) The appropriate branch define_expand is called, which then
4502 ;; creates the appropriate RTL for the comparison and branch.
4503 ;; Different CC modes are used, based on what type of branch is
4504 ;; done, so that we can constrain things appropriately. There
4505 ;; are assumptions in the rest of GCC that break if we fold the
4506 ;; operands into the branches for integer operations, and use cc0
4507 ;; for floating point, so we use the fp status register instead.
4508 ;; If needed, an appropriate temporary is created to hold the
4509 ;; of the integer compare.
4511 (define_expand "cmp<mode>"
4513 (compare:CC (match_operand:GPR 0 "register_operand")
4514 (match_operand:GPR 1 "nonmemory_operand")))]
4517 cmp_operands[0] = operands[0];
4518 cmp_operands[1] = operands[1];
4522 (define_expand "cmp<mode>"
4524 (compare:CC (match_operand:SCALARF 0 "register_operand")
4525 (match_operand:SCALARF 1 "register_operand")))]
4528 cmp_operands[0] = operands[0];
4529 cmp_operands[1] = operands[1];
4534 ;; ....................
4536 ;; CONDITIONAL BRANCHES
4538 ;; ....................
4540 ;; Conditional branches on floating-point equality tests.
4542 (define_insn "*branch_fp"
4545 (match_operator 0 "equality_operator"
4546 [(match_operand:CC 2 "register_operand" "z")
4548 (label_ref (match_operand 1 "" ""))
4552 return mips_output_conditional_branch (insn, operands,
4553 MIPS_BRANCH ("b%F0", "%Z2%1"),
4554 MIPS_BRANCH ("b%W0", "%Z2%1"));
4556 [(set_attr "type" "branch")
4557 (set_attr "mode" "none")])
4559 (define_insn "*branch_fp_inverted"
4562 (match_operator 0 "equality_operator"
4563 [(match_operand:CC 2 "register_operand" "z")
4566 (label_ref (match_operand 1 "" ""))))]
4569 return mips_output_conditional_branch (insn, operands,
4570 MIPS_BRANCH ("b%W0", "%Z2%1"),
4571 MIPS_BRANCH ("b%F0", "%Z2%1"));
4573 [(set_attr "type" "branch")
4574 (set_attr "mode" "none")])
4576 ;; Conditional branches on ordered comparisons with zero.
4578 (define_insn "*branch_order<mode>"
4581 (match_operator 0 "order_operator"
4582 [(match_operand:GPR 2 "register_operand" "d")
4584 (label_ref (match_operand 1 "" ""))
4587 { return mips_output_order_conditional_branch (insn, operands, false); }
4588 [(set_attr "type" "branch")
4589 (set_attr "mode" "none")])
4591 (define_insn "*branch_order<mode>_inverted"
4594 (match_operator 0 "order_operator"
4595 [(match_operand:GPR 2 "register_operand" "d")
4598 (label_ref (match_operand 1 "" ""))))]
4600 { return mips_output_order_conditional_branch (insn, operands, true); }
4601 [(set_attr "type" "branch")
4602 (set_attr "mode" "none")])
4604 ;; Conditional branch on equality comparison.
4606 (define_insn "*branch_equality<mode>"
4609 (match_operator 0 "equality_operator"
4610 [(match_operand:GPR 2 "register_operand" "d")
4611 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4612 (label_ref (match_operand 1 "" ""))
4616 return mips_output_conditional_branch (insn, operands,
4617 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
4618 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
4620 [(set_attr "type" "branch")
4621 (set_attr "mode" "none")])
4623 (define_insn "*branch_equality<mode>_inverted"
4626 (match_operator 0 "equality_operator"
4627 [(match_operand:GPR 2 "register_operand" "d")
4628 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4630 (label_ref (match_operand 1 "" ""))))]
4633 return mips_output_conditional_branch (insn, operands,
4634 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
4635 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
4637 [(set_attr "type" "branch")
4638 (set_attr "mode" "none")])
4642 (define_insn "*branch_equality<mode>_mips16"
4645 (match_operator 0 "equality_operator"
4646 [(match_operand:GPR 1 "register_operand" "d,t")
4648 (match_operand 2 "pc_or_label_operand" "")
4649 (match_operand 3 "pc_or_label_operand" "")))]
4652 if (operands[2] != pc_rtx)
4654 if (which_alternative == 0)
4655 return "b%C0z\t%1,%2";
4657 return "bt%C0z\t%2";
4661 if (which_alternative == 0)
4662 return "b%N0z\t%1,%3";
4664 return "bt%N0z\t%3";
4667 [(set_attr "type" "branch")
4668 (set_attr "mode" "none")
4669 (set_attr "length" "8")])
4671 (define_expand "b<code>"
4673 (if_then_else (any_cond:CC (cc0)
4675 (label_ref (match_operand 0 ""))
4679 gen_conditional_branch (operands, <CODE>);
4683 ;; Used to implement built-in functions.
4684 (define_expand "condjump"
4686 (if_then_else (match_operand 0)
4687 (label_ref (match_operand 1))
4691 ;; ....................
4693 ;; SETTING A REGISTER FROM A COMPARISON
4695 ;; ....................
4697 (define_expand "seq"
4698 [(set (match_operand:SI 0 "register_operand")
4699 (eq:SI (match_dup 1)
4702 { if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
4704 (define_insn "*seq_<mode>"
4705 [(set (match_operand:GPR 0 "register_operand" "=d")
4706 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4710 [(set_attr "type" "slt")
4711 (set_attr "mode" "<MODE>")])
4713 (define_insn "*seq_<mode>_mips16"
4714 [(set (match_operand:GPR 0 "register_operand" "=t")
4715 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4719 [(set_attr "type" "slt")
4720 (set_attr "mode" "<MODE>")])
4722 ;; "sne" uses sltu instructions in which the first operand is $0.
4723 ;; This isn't possible in mips16 code.
4725 (define_expand "sne"
4726 [(set (match_operand:SI 0 "register_operand")
4727 (ne:SI (match_dup 1)
4730 { if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
4732 (define_insn "*sne_<mode>"
4733 [(set (match_operand:GPR 0 "register_operand" "=d")
4734 (ne:GPR (match_operand:GPR 1 "register_operand" "d")
4738 [(set_attr "type" "slt")
4739 (set_attr "mode" "<MODE>")])
4741 (define_expand "sgt"
4742 [(set (match_operand:SI 0 "register_operand")
4743 (gt:SI (match_dup 1)
4746 { if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
4748 (define_insn "*sgt_<mode>"
4749 [(set (match_operand:GPR 0 "register_operand" "=d")
4750 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4751 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4754 [(set_attr "type" "slt")
4755 (set_attr "mode" "<MODE>")])
4757 (define_insn "*sgt_<mode>_mips16"
4758 [(set (match_operand:GPR 0 "register_operand" "=t")
4759 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4760 (match_operand:GPR 2 "register_operand" "d")))]
4763 [(set_attr "type" "slt")
4764 (set_attr "mode" "<MODE>")])
4766 (define_expand "sge"
4767 [(set (match_operand:SI 0 "register_operand")
4768 (ge:SI (match_dup 1)
4771 { if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
4773 (define_insn "*sge_<mode>"
4774 [(set (match_operand:GPR 0 "register_operand" "=d")
4775 (ge:GPR (match_operand:GPR 1 "register_operand" "d")
4779 [(set_attr "type" "slt")
4780 (set_attr "mode" "<MODE>")])
4782 (define_expand "slt"
4783 [(set (match_operand:SI 0 "register_operand")
4784 (lt:SI (match_dup 1)
4787 { if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
4789 (define_insn "*slt_<mode>"
4790 [(set (match_operand:GPR 0 "register_operand" "=d")
4791 (lt:GPR (match_operand:GPR 1 "register_operand" "d")
4792 (match_operand:GPR 2 "arith_operand" "dI")))]
4795 [(set_attr "type" "slt")
4796 (set_attr "mode" "<MODE>")])
4798 (define_insn "*slt_<mode>_mips16"
4799 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4800 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
4801 (match_operand:GPR 2 "arith_operand" "d,I")))]
4804 [(set_attr "type" "slt")
4805 (set_attr "mode" "<MODE>")
4806 (set_attr_alternative "length"
4808 (if_then_else (match_operand 2 "m16_uimm8_1")
4812 (define_expand "sle"
4813 [(set (match_operand:SI 0 "register_operand")
4814 (le:SI (match_dup 1)
4817 { if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
4819 (define_insn "*sle_<mode>"
4820 [(set (match_operand:GPR 0 "register_operand" "=d")
4821 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4822 (match_operand:GPR 2 "sle_operand" "")))]
4825 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4826 return "slt\t%0,%1,%2";
4828 [(set_attr "type" "slt")
4829 (set_attr "mode" "<MODE>")])
4831 (define_insn "*sle_<mode>_mips16"
4832 [(set (match_operand:GPR 0 "register_operand" "=t")
4833 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4834 (match_operand:GPR 2 "sle_operand" "")))]
4837 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4838 return "slt\t%1,%2";
4840 [(set_attr "type" "slt")
4841 (set_attr "mode" "<MODE>")
4842 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4846 (define_expand "sgtu"
4847 [(set (match_operand:SI 0 "register_operand")
4848 (gtu:SI (match_dup 1)
4851 { if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
4853 (define_insn "*sgtu_<mode>"
4854 [(set (match_operand:GPR 0 "register_operand" "=d")
4855 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4856 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4859 [(set_attr "type" "slt")
4860 (set_attr "mode" "<MODE>")])
4862 (define_insn "*sgtu_<mode>_mips16"
4863 [(set (match_operand:GPR 0 "register_operand" "=t")
4864 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4865 (match_operand:GPR 2 "register_operand" "d")))]
4868 [(set_attr "type" "slt")
4869 (set_attr "mode" "<MODE>")])
4871 (define_expand "sgeu"
4872 [(set (match_operand:SI 0 "register_operand")
4873 (geu:SI (match_dup 1)
4876 { if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
4878 (define_insn "*sge_<mode>"
4879 [(set (match_operand:GPR 0 "register_operand" "=d")
4880 (geu:GPR (match_operand:GPR 1 "register_operand" "d")
4884 [(set_attr "type" "slt")
4885 (set_attr "mode" "<MODE>")])
4887 (define_expand "sltu"
4888 [(set (match_operand:SI 0 "register_operand")
4889 (ltu:SI (match_dup 1)
4892 { if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
4894 (define_insn "*sltu_<mode>"
4895 [(set (match_operand:GPR 0 "register_operand" "=d")
4896 (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
4897 (match_operand:GPR 2 "arith_operand" "dI")))]
4900 [(set_attr "type" "slt")
4901 (set_attr "mode" "<MODE>")])
4903 (define_insn "*sltu_<mode>_mips16"
4904 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4905 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
4906 (match_operand:GPR 2 "arith_operand" "d,I")))]
4909 [(set_attr "type" "slt")
4910 (set_attr "mode" "<MODE>")
4911 (set_attr_alternative "length"
4913 (if_then_else (match_operand 2 "m16_uimm8_1")
4917 (define_expand "sleu"
4918 [(set (match_operand:SI 0 "register_operand")
4919 (leu:SI (match_dup 1)
4922 { if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
4924 (define_insn "*sleu_<mode>"
4925 [(set (match_operand:GPR 0 "register_operand" "=d")
4926 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4927 (match_operand:GPR 2 "sleu_operand" "")))]
4930 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4931 return "sltu\t%0,%1,%2";
4933 [(set_attr "type" "slt")
4934 (set_attr "mode" "<MODE>")])
4936 (define_insn "*sleu_<mode>_mips16"
4937 [(set (match_operand:GPR 0 "register_operand" "=t")
4938 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4939 (match_operand:GPR 2 "sleu_operand" "")))]
4942 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4943 return "sltu\t%1,%2";
4945 [(set_attr "type" "slt")
4946 (set_attr "mode" "<MODE>")
4947 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4952 ;; ....................
4954 ;; FLOATING POINT COMPARISONS
4956 ;; ....................
4958 (define_insn "s<code>_<mode>"
4959 [(set (match_operand:CC 0 "register_operand" "=z")
4960 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4961 (match_operand:SCALARF 2 "register_operand" "f")))]
4963 "c.<fcond>.<fmt>\t%Z0%1,%2"
4964 [(set_attr "type" "fcmp")
4965 (set_attr "mode" "FPSW")])
4967 (define_insn "s<code>_<mode>"
4968 [(set (match_operand:CC 0 "register_operand" "=z")
4969 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4970 (match_operand:SCALARF 2 "register_operand" "f")))]
4972 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
4973 [(set_attr "type" "fcmp")
4974 (set_attr "mode" "FPSW")])
4977 ;; ....................
4979 ;; UNCONDITIONAL BRANCHES
4981 ;; ....................
4983 ;; Unconditional branches.
4987 (label_ref (match_operand 0 "" "")))]
4992 if (get_attr_length (insn) <= 8)
4993 return "%*b\t%l0%/";
4996 output_asm_insn (mips_output_load_label (), operands);
4997 return "%*jr\t%@%/%]";
5001 return "%*j\t%l0%/";
5003 [(set_attr "type" "jump")
5004 (set_attr "mode" "none")
5005 (set (attr "length")
5006 ;; We can't use `j' when emitting PIC. Emit a branch if it's
5007 ;; in range, otherwise load the address of the branch target into
5008 ;; $at and then jump to it.
5010 (ior (eq (symbol_ref "flag_pic") (const_int 0))
5011 (lt (abs (minus (match_dup 0)
5012 (plus (pc) (const_int 4))))
5013 (const_int 131072)))
5014 (const_int 4) (const_int 16)))])
5016 ;; We need a different insn for the mips16, because a mips16 branch
5017 ;; does not have a delay slot.
5021 (label_ref (match_operand 0 "" "")))]
5024 [(set_attr "type" "branch")
5025 (set_attr "mode" "none")
5026 (set_attr "length" "8")])
5028 (define_expand "indirect_jump"
5029 [(set (pc) (match_operand 0 "register_operand"))]
5032 operands[0] = force_reg (Pmode, operands[0]);
5033 if (Pmode == SImode)
5034 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5036 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5040 (define_insn "indirect_jump<mode>"
5041 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5044 [(set_attr "type" "jump")
5045 (set_attr "mode" "none")])
5047 (define_expand "tablejump"
5049 (match_operand 0 "register_operand"))
5050 (use (label_ref (match_operand 1 "")))]
5054 operands[0] = expand_binop (Pmode, add_optab,
5055 convert_to_mode (Pmode, operands[0], false),
5056 gen_rtx_LABEL_REF (Pmode, operands[1]),
5058 else if (TARGET_GPWORD)
5059 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5060 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5061 else if (TARGET_RTP_PIC)
5063 /* When generating RTP PIC, we use case table entries that are relative
5064 to the start of the function. Add the function's address to the
5066 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5067 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5068 start, 0, 0, OPTAB_WIDEN);
5071 if (Pmode == SImode)
5072 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5074 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5078 (define_insn "tablejump<mode>"
5080 (match_operand:P 0 "register_operand" "d"))
5081 (use (label_ref (match_operand 1 "" "")))]
5084 [(set_attr "type" "jump")
5085 (set_attr "mode" "none")])
5087 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5088 ;; While it is possible to either pull it off the stack (in the
5089 ;; o32 case) or recalculate it given t9 and our target label,
5090 ;; it takes 3 or 4 insns to do so.
5092 (define_expand "builtin_setjmp_setup"
5093 [(use (match_operand 0 "register_operand"))]
5098 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5099 emit_move_insn (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5103 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5104 ;; that older code did recalculate the gp from $25. Continue to jump through
5105 ;; $25 for compatibility (we lose nothing by doing so).
5107 (define_expand "builtin_longjmp"
5108 [(use (match_operand 0 "register_operand"))]
5111 /* The elements of the buffer are, in order: */
5112 int W = GET_MODE_SIZE (Pmode);
5113 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5114 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5115 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5116 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5117 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5118 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5119 The target is bound to be using $28 as the global pointer
5120 but the current function might not be. */
5121 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5123 /* This bit is similar to expand_builtin_longjmp except that it
5124 restores $gp as well. */
5125 emit_move_insn (hard_frame_pointer_rtx, fp);
5126 emit_move_insn (pv, lab);
5127 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5128 emit_move_insn (gp, gpv);
5129 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5130 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5131 emit_insn (gen_rtx_USE (VOIDmode, gp));
5132 emit_indirect_jump (pv);
5137 ;; ....................
5139 ;; Function prologue/epilogue
5141 ;; ....................
5144 (define_expand "prologue"
5148 mips_expand_prologue ();
5152 ;; Block any insns from being moved before this point, since the
5153 ;; profiling call to mcount can use various registers that aren't
5154 ;; saved or used to pass arguments.
5156 (define_insn "blockage"
5157 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5160 [(set_attr "type" "unknown")
5161 (set_attr "mode" "none")
5162 (set_attr "length" "0")])
5164 (define_expand "epilogue"
5168 mips_expand_epilogue (false);
5172 (define_expand "sibcall_epilogue"
5176 mips_expand_epilogue (true);
5180 ;; Trivial return. Make it look like a normal return insn as that
5181 ;; allows jump optimizations to work better.
5183 (define_insn "return"
5185 "mips_can_use_return_insn ()"
5187 [(set_attr "type" "jump")
5188 (set_attr "mode" "none")])
5192 (define_insn "return_internal"
5194 (use (match_operand 0 "pmode_register_operand" ""))]
5197 [(set_attr "type" "jump")
5198 (set_attr "mode" "none")])
5200 ;; This is used in compiling the unwind routines.
5201 (define_expand "eh_return"
5202 [(use (match_operand 0 "general_operand"))]
5205 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
5207 if (GET_MODE (operands[0]) != gpr_mode)
5208 operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
5210 emit_insn (gen_eh_set_lr_di (operands[0]));
5212 emit_insn (gen_eh_set_lr_si (operands[0]));
5217 ;; Clobber the return address on the stack. We can't expand this
5218 ;; until we know where it will be put in the stack frame.
5220 (define_insn "eh_set_lr_si"
5221 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5222 (clobber (match_scratch:SI 1 "=&d"))]
5226 (define_insn "eh_set_lr_di"
5227 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5228 (clobber (match_scratch:DI 1 "=&d"))]
5233 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5234 (clobber (match_scratch 1))]
5235 "reload_completed && !TARGET_DEBUG_D_MODE"
5238 mips_set_return_address (operands[0], operands[1]);
5242 (define_insn_and_split "nonlocal_goto_receiver"
5244 (unspec_volatile:SI [(const_int 0)] UNSPEC_NONLOCAL_GOTO_RECEIVER))]
5245 "TARGET_CALL_CLOBBERED_GP"
5247 "&& reload_completed"
5253 [(set_attr "type" "load")
5254 (set_attr "length" "12")])
5257 ;; ....................
5261 ;; ....................
5263 ;; Instructions to load a call address from the GOT. The address might
5264 ;; point to a function or to a lazy binding stub. In the latter case,
5265 ;; the stub will use the dynamic linker to resolve the function, which
5266 ;; in turn will change the GOT entry to point to the function's real
5269 ;; This means that every call, even pure and constant ones, can
5270 ;; potentially modify the GOT entry. And once a stub has been called,
5271 ;; we must not call it again.
5273 ;; We represent this restriction using an imaginary fixed register that
5274 ;; acts like a GOT version number. By making the register call-clobbered,
5275 ;; we tell the target-independent code that the address could be changed
5276 ;; by any call insn.
5277 (define_insn "load_call<mode>"
5278 [(set (match_operand:P 0 "register_operand" "=d")
5279 (unspec:P [(match_operand:P 1 "register_operand" "r")
5280 (match_operand:P 2 "immediate_operand" "")
5281 (reg:P FAKE_CALL_REGNO)]
5284 "<load>\t%0,%R2(%1)"
5285 [(set_attr "type" "load")
5286 (set_attr "mode" "<MODE>")
5287 (set_attr "length" "4")])
5289 ;; Sibling calls. All these patterns use jump instructions.
5291 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5292 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5293 ;; is defined in terms of call_insn_operand, the same is true of the
5296 ;; When we use an indirect jump, we need a register that will be
5297 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5298 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5299 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5302 (define_expand "sibcall"
5303 [(parallel [(call (match_operand 0 "")
5304 (match_operand 1 ""))
5305 (use (match_operand 2 "")) ;; next_arg_reg
5306 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5309 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
5313 (define_insn "sibcall_internal"
5314 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5315 (match_operand 1 "" ""))]
5316 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5317 { return MIPS_CALL ("j", operands, 0); }
5318 [(set_attr "type" "call")])
5320 (define_expand "sibcall_value"
5321 [(parallel [(set (match_operand 0 "")
5322 (call (match_operand 1 "")
5323 (match_operand 2 "")))
5324 (use (match_operand 3 ""))])] ;; next_arg_reg
5327 mips_expand_call (operands[0], XEXP (operands[1], 0),
5328 operands[2], operands[3], true);
5332 (define_insn "sibcall_value_internal"
5333 [(set (match_operand 0 "register_operand" "")
5334 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5335 (match_operand 2 "" "")))]
5336 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5337 { return MIPS_CALL ("j", operands, 1); }
5338 [(set_attr "type" "call")])
5340 (define_insn "sibcall_value_multiple_internal"
5341 [(set (match_operand 0 "register_operand" "")
5342 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5343 (match_operand 2 "" "")))
5344 (set (match_operand 3 "register_operand" "")
5345 (call (mem:SI (match_dup 1))
5347 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5348 { return MIPS_CALL ("j", operands, 1); }
5349 [(set_attr "type" "call")])
5351 (define_expand "call"
5352 [(parallel [(call (match_operand 0 "")
5353 (match_operand 1 ""))
5354 (use (match_operand 2 "")) ;; next_arg_reg
5355 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5358 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
5362 ;; This instruction directly corresponds to an assembly-language "jal".
5363 ;; There are four cases:
5366 ;; Both symbolic and register destinations are OK. The pattern
5367 ;; always expands to a single mips instruction.
5369 ;; - -mabicalls/-mno-explicit-relocs:
5370 ;; Again, both symbolic and register destinations are OK.
5371 ;; The call is treated as a multi-instruction black box.
5373 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5374 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5377 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5378 ;; Only "jal $25" is allowed. The call is actually two instructions:
5379 ;; "jalr $25" followed by an insn to reload $gp.
5381 ;; In the last case, we can generate the individual instructions with
5382 ;; a define_split. There are several things to be wary of:
5384 ;; - We can't expose the load of $gp before reload. If we did,
5385 ;; it might get removed as dead, but reload can introduce new
5386 ;; uses of $gp by rematerializing constants.
5388 ;; - We shouldn't restore $gp after calls that never return.
5389 ;; It isn't valid to insert instructions between a noreturn
5390 ;; call and the following barrier.
5392 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5393 ;; instruction preserves $gp and so have no effect on its liveness.
5394 ;; But once we generate the separate insns, it becomes obvious that
5395 ;; $gp is not live on entry to the call.
5397 ;; ??? The operands[2] = insn check is a hack to make the original insn
5398 ;; available to the splitter.
5399 (define_insn_and_split "call_internal"
5400 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5401 (match_operand 1 "" ""))
5402 (clobber (reg:SI 31))]
5404 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5405 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5408 emit_call_insn (gen_call_split (operands[0], operands[1]));
5409 if (!find_reg_note (operands[2], REG_NORETURN, 0))
5413 [(set_attr "jal" "indirect,direct")
5414 (set_attr "extended_mips16" "no,yes")])
5416 (define_insn "call_split"
5417 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5418 (match_operand 1 "" ""))
5419 (clobber (reg:SI 31))
5420 (clobber (reg:SI 28))]
5421 "TARGET_SPLIT_CALLS"
5422 { return MIPS_CALL ("jal", operands, 0); }
5423 [(set_attr "type" "call")])
5425 (define_expand "call_value"
5426 [(parallel [(set (match_operand 0 "")
5427 (call (match_operand 1 "")
5428 (match_operand 2 "")))
5429 (use (match_operand 3 ""))])] ;; next_arg_reg
5432 mips_expand_call (operands[0], XEXP (operands[1], 0),
5433 operands[2], operands[3], false);
5437 ;; See comment for call_internal.
5438 (define_insn_and_split "call_value_internal"
5439 [(set (match_operand 0 "register_operand" "")
5440 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5441 (match_operand 2 "" "")))
5442 (clobber (reg:SI 31))]
5444 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5445 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5448 emit_call_insn (gen_call_value_split (operands[0], operands[1],
5450 if (!find_reg_note (operands[3], REG_NORETURN, 0))
5454 [(set_attr "jal" "indirect,direct")
5455 (set_attr "extended_mips16" "no,yes")])
5457 (define_insn "call_value_split"
5458 [(set (match_operand 0 "register_operand" "")
5459 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5460 (match_operand 2 "" "")))
5461 (clobber (reg:SI 31))
5462 (clobber (reg:SI 28))]
5463 "TARGET_SPLIT_CALLS"
5464 { return MIPS_CALL ("jal", operands, 1); }
5465 [(set_attr "type" "call")])
5467 ;; See comment for call_internal.
5468 (define_insn_and_split "call_value_multiple_internal"
5469 [(set (match_operand 0 "register_operand" "")
5470 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5471 (match_operand 2 "" "")))
5472 (set (match_operand 3 "register_operand" "")
5473 (call (mem:SI (match_dup 1))
5475 (clobber (reg:SI 31))]
5477 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5478 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5481 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
5482 operands[2], operands[3]));
5483 if (!find_reg_note (operands[4], REG_NORETURN, 0))
5487 [(set_attr "jal" "indirect,direct")
5488 (set_attr "extended_mips16" "no,yes")])
5490 (define_insn "call_value_multiple_split"
5491 [(set (match_operand 0 "register_operand" "")
5492 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5493 (match_operand 2 "" "")))
5494 (set (match_operand 3 "register_operand" "")
5495 (call (mem:SI (match_dup 1))
5497 (clobber (reg:SI 31))
5498 (clobber (reg:SI 28))]
5499 "TARGET_SPLIT_CALLS"
5500 { return MIPS_CALL ("jal", operands, 1); }
5501 [(set_attr "type" "call")])
5503 ;; Call subroutine returning any type.
5505 (define_expand "untyped_call"
5506 [(parallel [(call (match_operand 0 "")
5508 (match_operand 1 "")
5509 (match_operand 2 "")])]
5514 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5516 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5518 rtx set = XVECEXP (operands[2], 0, i);
5519 emit_move_insn (SET_DEST (set), SET_SRC (set));
5522 emit_insn (gen_blockage ());
5527 ;; ....................
5531 ;; ....................
5535 (define_insn "prefetch"
5536 [(prefetch (match_operand:QI 0 "address_operand" "p")
5537 (match_operand 1 "const_int_operand" "n")
5538 (match_operand 2 "const_int_operand" "n"))]
5539 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
5541 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
5542 return "pref\t%1,%a0";
5544 [(set_attr "type" "prefetch")])
5546 (define_insn "*prefetch_indexed_<mode>"
5547 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
5548 (match_operand:P 1 "register_operand" "d"))
5549 (match_operand 2 "const_int_operand" "n")
5550 (match_operand 3 "const_int_operand" "n"))]
5551 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5553 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
5554 return "prefx\t%2,%1(%0)";
5556 [(set_attr "type" "prefetchx")])
5562 [(set_attr "type" "nop")
5563 (set_attr "mode" "none")])
5565 ;; Like nop, but commented out when outside a .set noreorder block.
5566 (define_insn "hazard_nop"
5575 [(set_attr "type" "nop")])
5577 ;; MIPS4 Conditional move instructions.
5579 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
5580 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5582 (match_operator:MOVECC 4 "equality_operator"
5583 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5585 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
5586 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
5591 [(set_attr "type" "condmove")
5592 (set_attr "mode" "<GPR:MODE>")])
5594 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
5595 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
5596 (if_then_else:SCALARF
5597 (match_operator:MOVECC 4 "equality_operator"
5598 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5600 (match_operand:SCALARF 2 "register_operand" "f,0")
5601 (match_operand:SCALARF 3 "register_operand" "0,f")))]
5604 mov%T4.<fmt>\t%0,%2,%1
5605 mov%t4.<fmt>\t%0,%3,%1"
5606 [(set_attr "type" "condmove")
5607 (set_attr "mode" "<SCALARF:MODE>")])
5609 ;; These are the main define_expand's used to make conditional moves.
5611 (define_expand "mov<mode>cc"
5612 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5613 (set (match_operand:GPR 0 "register_operand")
5614 (if_then_else:GPR (match_dup 5)
5615 (match_operand:GPR 2 "reg_or_0_operand")
5616 (match_operand:GPR 3 "reg_or_0_operand")))]
5619 gen_conditional_move (operands);
5623 (define_expand "mov<mode>cc"
5624 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5625 (set (match_operand:SCALARF 0 "register_operand")
5626 (if_then_else:SCALARF (match_dup 5)
5627 (match_operand:SCALARF 2 "register_operand")
5628 (match_operand:SCALARF 3 "register_operand")))]
5631 gen_conditional_move (operands);
5636 ;; ....................
5638 ;; mips16 inline constant tables
5640 ;; ....................
5643 (define_insn "consttable_int"
5644 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
5645 (match_operand 1 "const_int_operand" "")]
5646 UNSPEC_CONSTTABLE_INT)]
5649 assemble_integer (operands[0], INTVAL (operands[1]),
5650 BITS_PER_UNIT * INTVAL (operands[1]), 1);
5653 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
5655 (define_insn "consttable_float"
5656 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
5657 UNSPEC_CONSTTABLE_FLOAT)]
5662 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
5663 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
5664 assemble_real (d, GET_MODE (operands[0]),
5665 GET_MODE_BITSIZE (GET_MODE (operands[0])));
5668 [(set (attr "length")
5669 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
5671 (define_insn "align"
5672 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
5675 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
5678 [(match_operand 0 "small_data_pattern")]
5681 { operands[0] = mips_rewrite_small_data (operands[0]); })
5684 ;; ....................
5686 ;; MIPS16e Save/Restore
5688 ;; ....................
5691 (define_insn "*mips16e_save_restore"
5692 [(match_parallel 0 ""
5693 [(set (match_operand:SI 1 "register_operand")
5694 (plus:SI (match_dup 1)
5695 (match_operand:SI 2 "const_int_operand")))])]
5696 "operands[1] == stack_pointer_rtx
5697 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
5698 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
5699 [(set_attr "type" "arith")
5700 (set_attr "extended_mips16" "yes")])
5702 ; Thread-Local Storage
5704 ; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
5705 ; MIPS architecture defines this register, and no current
5706 ; implementation provides it; instead, any OS which supports TLS is
5707 ; expected to trap and emulate this instruction. rdhwr is part of the
5708 ; MIPS 32r2 specification, but we use it on any architecture because
5709 ; we expect it to be emulated. Use .set to force the assembler to
5712 (define_insn "tls_get_tp_<mode>"
5713 [(set (match_operand:P 0 "register_operand" "=v")
5714 (unspec:P [(const_int 0)]
5715 UNSPEC_TLS_GET_TP))]
5716 "HAVE_AS_TLS && !TARGET_MIPS16"
5717 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
5718 [(set_attr "type" "unknown")
5719 ; Since rdhwr always generates a trap for now, putting it in a delay
5720 ; slot would make the kernel's emulation of it much slower.
5721 (set_attr "can_delay" "no")
5722 (set_attr "mode" "<MODE>")])
5724 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
5726 (include "mips-ps-3d.md")
5728 ; The MIPS DSP Instructions.
5730 (include "mips-dsp.md")
5732 ; The MIPS DSP REV 2 Instructions.
5734 (include "mips-dspr2.md")