1 ;; Predicate definitions for MIPS.
2 ;; Copyright (C) 2004-2021 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_predicate "const_uns_arith_operand"
21 (and (match_code "const_int")
22 (match_test "SMALL_OPERAND_UNSIGNED (INTVAL (op))")))
24 (define_predicate "uns_arith_operand"
25 (ior (match_operand 0 "const_uns_arith_operand")
26 (match_operand 0 "register_operand")))
28 (define_predicate "const_arith_operand"
29 (and (match_code "const_int")
30 (match_test "SMALL_OPERAND (INTVAL (op))")))
32 (define_predicate "arith_operand"
33 (ior (match_operand 0 "const_arith_operand")
34 (match_operand 0 "register_operand")))
36 (define_predicate "const_immlsa_operand"
37 (and (match_code "const_int")
38 (match_test "IN_RANGE (INTVAL (op), 1, 4)")))
40 (define_predicate "const_msa_branch_operand"
41 (and (match_code "const_int")
42 (match_test "IN_RANGE (INTVAL (op), -1024, 1023)")))
44 (define_predicate "const_uimm3_operand"
45 (and (match_code "const_int")
46 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
48 (define_predicate "const_uimm4_operand"
49 (and (match_code "const_int")
50 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
52 (define_predicate "const_uimm5_operand"
53 (and (match_code "const_int")
54 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
56 (define_predicate "const_uimm6_operand"
57 (and (match_code "const_int")
58 (match_test "UIMM6_OPERAND (INTVAL (op))")))
60 (define_predicate "const_uimm8_operand"
61 (and (match_code "const_int")
62 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
64 (define_predicate "const_imm5_operand"
65 (and (match_code "const_int")
66 (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
68 (define_predicate "const_imm10_operand"
69 (and (match_code "const_int")
70 (match_test "IMM10_OPERAND (INTVAL (op))")))
72 (define_predicate "reg_imm10_operand"
73 (ior (match_operand 0 "const_imm10_operand")
74 (match_operand 0 "register_operand")))
76 (define_predicate "aq10b_operand"
77 (and (match_code "const_int")
78 (match_test "mips_signed_immediate_p (INTVAL (op), 10, 0)")))
80 (define_predicate "aq10h_operand"
81 (and (match_code "const_int")
82 (match_test "mips_signed_immediate_p (INTVAL (op), 10, 1)")))
84 (define_predicate "aq10w_operand"
85 (and (match_code "const_int")
86 (match_test "mips_signed_immediate_p (INTVAL (op), 10, 2)")))
88 (define_predicate "aq10d_operand"
89 (and (match_code "const_int")
90 (match_test "mips_signed_immediate_p (INTVAL (op), 10, 3)")))
92 (define_predicate "sle_operand"
93 (and (match_code "const_int")
94 (match_test "SMALL_OPERAND (INTVAL (op) + 1)")))
96 (define_predicate "sleu_operand"
97 (and (match_operand 0 "sle_operand")
98 (match_test "INTVAL (op) + 1 != 0")))
100 (define_predicate "const_0_operand"
101 (and (match_code "const_int,const_double,const_vector")
102 (match_test "op == CONST0_RTX (GET_MODE (op))")))
104 (define_predicate "const_m1_operand"
105 (and (match_code "const_int,const_double,const_vector")
106 (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
108 (define_predicate "reg_or_m1_operand"
109 (ior (match_operand 0 "const_m1_operand")
110 (match_operand 0 "register_operand")))
112 (define_predicate "reg_or_0_operand"
113 (ior (and (match_operand 0 "const_0_operand")
114 (not (match_test "TARGET_MIPS16")))
115 (match_operand 0 "register_operand")))
117 (define_predicate "const_1_operand"
118 (and (match_code "const_int,const_double,const_vector")
119 (match_test "op == CONST1_RTX (GET_MODE (op))")))
121 (define_predicate "reg_or_1_operand"
122 (ior (match_operand 0 "const_1_operand")
123 (match_operand 0 "register_operand")))
125 ;; These are used in vec_merge, hence accept bitmask as const_int.
126 (define_predicate "const_exp_2_operand"
127 (and (match_code "const_int")
128 (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 1)")))
130 (define_predicate "const_exp_4_operand"
131 (and (match_code "const_int")
132 (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 3)")))
134 (define_predicate "const_exp_8_operand"
135 (and (match_code "const_int")
136 (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 7)")))
138 (define_predicate "const_exp_16_operand"
139 (and (match_code "const_int")
140 (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 15)")))
142 ;; This is used for indexing into vectors, and hence only accepts const_int.
143 (define_predicate "const_0_or_1_operand"
144 (and (match_code "const_int")
145 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
147 (define_predicate "const_2_or_3_operand"
148 (and (match_code "const_int")
149 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
151 (define_predicate "const_0_to_3_operand"
152 (and (match_code "const_int")
153 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
155 (define_predicate "qi_mask_operand"
156 (and (match_code "const_int")
157 (match_test "UINTVAL (op) == 0xff")))
159 (define_predicate "hi_mask_operand"
160 (and (match_code "const_int")
161 (match_test "UINTVAL (op) == 0xffff")))
163 (define_predicate "si_mask_operand"
164 (and (match_code "const_int")
165 (match_test "UINTVAL (op) == 0xffffffff")))
167 (define_predicate "and_load_operand"
168 (ior (match_operand 0 "qi_mask_operand")
169 (match_operand 0 "hi_mask_operand")
170 (match_operand 0 "si_mask_operand")))
172 (define_predicate "low_bitmask_operand"
173 (and (match_test "ISA_HAS_EXT_INS")
174 (match_code "const_int")
175 (match_test "low_bitmask_len (mode, INTVAL (op)) > 16")))
177 (define_predicate "and_reg_operand"
178 (ior (match_operand 0 "register_operand")
179 (and (not (match_test "TARGET_MIPS16"))
180 (match_operand 0 "const_uns_arith_operand"))
181 (match_operand 0 "low_bitmask_operand")
182 (match_operand 0 "si_mask_operand")))
184 (define_predicate "and_operand"
185 (ior (match_operand 0 "and_load_operand")
186 (match_operand 0 "and_reg_operand")))
188 (define_predicate "d_operand"
189 (and (match_code "reg")
190 (match_test "TARGET_MIPS16
191 ? M16_REG_P (REGNO (op))
192 : GP_REG_P (REGNO (op))")))
194 (define_predicate "lwsp_swsp_operand"
195 (and (match_code "mem")
196 (match_test "lwsp_swsp_address_p (XEXP (op, 0), mode)")))
198 (define_predicate "lw16_sw16_operand"
199 (and (match_code "mem")
200 (match_test "m16_based_address_p (XEXP (op, 0), mode, uw4_operand)")))
202 (define_predicate "lhu16_sh16_operand"
203 (and (match_code "mem")
204 (match_test "m16_based_address_p (XEXP (op, 0), mode, uh4_operand)")))
206 (define_predicate "lbu16_operand"
207 (and (match_code "mem")
208 (match_test "m16_based_address_p (XEXP (op, 0), mode, db4_operand)")))
210 (define_predicate "sb16_operand"
211 (and (match_code "mem")
212 (match_test "m16_based_address_p (XEXP (op, 0), mode, ub4_operand)")))
214 (define_predicate "db4_operand"
215 (and (match_code "const_int")
216 (match_test "mips_unsigned_immediate_p (INTVAL (op) + 1, 4, 0)")))
218 (define_predicate "db7_operand"
219 (and (match_code "const_int")
220 (match_test "mips_unsigned_immediate_p (INTVAL (op) + 1, 7, 0)")))
222 (define_predicate "db8_operand"
223 (and (match_code "const_int")
224 (match_test "mips_unsigned_immediate_p (INTVAL (op) + 1, 8, 0)")))
226 (define_predicate "ib3_operand"
227 (and (match_code "const_int")
228 (match_test "mips_unsigned_immediate_p (INTVAL (op) - 1, 3, 0)")))
230 (define_predicate "sb4_operand"
231 (and (match_code "const_int")
232 (match_test "mips_signed_immediate_p (INTVAL (op), 4, 0)")))
234 (define_predicate "sb5_operand"
235 (and (match_code "const_int")
236 (match_test "mips_signed_immediate_p (INTVAL (op), 5, 0)")))
238 (define_predicate "sb8_operand"
239 (and (match_code "const_int")
240 (match_test "mips_signed_immediate_p (INTVAL (op), 8, 0)")))
242 (define_predicate "sd8_operand"
243 (and (match_code "const_int")
244 (match_test "mips_signed_immediate_p (INTVAL (op), 8, 3)")))
246 (define_predicate "ub4_operand"
247 (and (match_code "const_int")
248 (match_test "mips_unsigned_immediate_p (INTVAL (op), 4, 0)")))
250 (define_predicate "ub8_operand"
251 (and (match_code "const_int")
252 (match_test "mips_unsigned_immediate_p (INTVAL (op), 8, 0)")))
254 (define_predicate "uh4_operand"
255 (and (match_code "const_int")
256 (match_test "mips_unsigned_immediate_p (INTVAL (op), 4, 1)")))
258 (define_predicate "uw4_operand"
259 (and (match_code "const_int")
260 (match_test "mips_unsigned_immediate_p (INTVAL (op), 4, 2)")))
262 (define_predicate "uw5_operand"
263 (and (match_code "const_int")
264 (match_test "mips_unsigned_immediate_p (INTVAL (op), 5, 2)")))
266 (define_predicate "uw6_operand"
267 (and (match_code "const_int")
268 (match_test "mips_unsigned_immediate_p (INTVAL (op), 6, 2)")))
270 (define_predicate "uw8_operand"
271 (and (match_code "const_int")
272 (match_test "mips_unsigned_immediate_p (INTVAL (op), 8, 2)")))
274 (define_predicate "addiur2_operand"
275 (and (match_code "const_int")
276 (ior (match_test "INTVAL (op) == -1")
277 (match_test "INTVAL (op) == 1")
278 (match_test "INTVAL (op) == 4")
279 (match_test "INTVAL (op) == 8")
280 (match_test "INTVAL (op) == 12")
281 (match_test "INTVAL (op) == 16")
282 (match_test "INTVAL (op) == 20")
283 (match_test "INTVAL (op) == 24"))))
285 (define_predicate "addiusp_operand"
286 (and (match_code "const_int")
287 (ior (match_test "(IN_RANGE (INTVAL (op), 2, 257))")
288 (match_test "(IN_RANGE (INTVAL (op), -258, -3))"))))
290 (define_predicate "andi16_operand"
291 (and (match_code "const_int")
292 (ior (match_test "IN_RANGE (INTVAL (op), 1, 4)")
293 (match_test "IN_RANGE (INTVAL (op), 7, 8)")
294 (match_test "IN_RANGE (INTVAL (op), 15, 16)")
295 (match_test "IN_RANGE (INTVAL (op), 31, 32)")
296 (match_test "IN_RANGE (INTVAL (op), 63, 64)")
297 (match_test "INTVAL (op) == 255")
298 (match_test "INTVAL (op) == 32768")
299 (match_test "INTVAL (op) == 65535"))))
301 (define_predicate "movep_src_register"
302 (and (match_code "reg")
303 (ior (match_test ("IN_RANGE (REGNO (op), 2, 3)"))
304 (match_test ("IN_RANGE (REGNO (op), 16, 20)")))))
306 (define_predicate "movep_src_operand"
307 (ior (match_operand 0 "const_0_operand")
308 (match_operand 0 "movep_src_register")))
310 (define_predicate "lo_operand"
311 (and (match_code "reg")
312 (match_test "REGNO (op) == LO_REGNUM")))
314 (define_predicate "hilo_operand"
315 (and (match_code "reg")
316 (match_test "MD_REG_P (REGNO (op))")))
318 (define_predicate "fcc_reload_operand"
319 (and (match_code "reg,subreg")
320 (match_test "ST_REG_P (true_regnum (op))")))
322 (define_predicate "muldiv_target_operand"
323 (if_then_else (match_test "TARGET_MIPS16")
324 (match_operand 0 "hilo_operand")
325 (match_operand 0 "register_operand")))
327 (define_predicate "const_call_insn_operand"
328 (match_code "const,symbol_ref,label_ref")
330 enum mips_symbol_type symbol_type;
332 if (!mips_symbolic_constant_p (op, SYMBOL_CONTEXT_CALL, &symbol_type))
337 case SYMBOL_ABSOLUTE:
338 /* We can only use direct calls if we're sure that the target
339 function does not need $25 to be valid on entry. */
340 if (mips_use_pic_fn_addr_reg_p (op))
343 /* If -mlong-calls or if this function has an explicit long_call
344 attribute, we must use register addressing. The
345 SYMBOL_FLAG_LONG_CALL bit is set by mips_encode_section_info. */
346 return !(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LONG_CALL_P (op));
348 case SYMBOL_GOT_DISP:
349 /* Without explicit relocs, there is no special syntax for
350 loading the address of a call destination into a register.
351 Using "la $25,foo; jal $25" would prevent the lazy binding
352 of "foo", so keep the address of global symbols with the
354 return !TARGET_EXPLICIT_RELOCS;
361 (define_predicate "call_insn_operand"
362 (ior (match_operand 0 "const_call_insn_operand")
363 (match_operand 0 "register_operand")))
365 ;; A legitimate CONST_INT operand that takes more than one instruction
367 (define_predicate "splittable_const_int_operand"
368 (match_code "const_int")
370 /* When generating mips16 code, TARGET_LEGITIMATE_CONSTANT_P rejects
371 CONST_INTs that can't be loaded using simple insns. */
375 /* Don't handle multi-word moves this way; we don't want to introduce
376 the individual word-mode moves until after reload. */
377 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
380 /* Otherwise check whether the constant can be loaded in a single
382 return !LUI_INT (op) && !SMALL_INT (op) && !SMALL_INT_UNSIGNED (op);
385 (define_predicate "move_operand"
386 ;; Allow HI and LO to be used as the source of a MIPS16 move.
387 (ior (match_operand 0 "general_operand")
388 (match_operand 0 "hilo_operand"))
390 enum mips_symbol_type symbol_type;
392 /* The thinking here is as follows:
394 (1) The move expanders should split complex load sequences into
395 individual instructions. Those individual instructions can
396 then be optimized by all rtl passes.
398 (2) The target of pre-reload load sequences should not be used
399 to store temporary results. If the target register is only
400 assigned one value, reload can rematerialize that value
401 on demand, rather than spill it to the stack.
403 (3) If we allowed pre-reload passes like combine and cse to recreate
404 complex load sequences, we would want to be able to split the
405 sequences before reload as well, so that the pre-reload scheduler
406 can see the individual instructions. This falls foul of (2);
407 the splitter would be forced to reuse the target register for
408 intermediate results.
410 (4) We want to define complex load splitters for combine. These
411 splitters can request a temporary scratch register, which avoids
412 the problem in (2). They allow things like:
414 (set (reg T1) (high SYM))
415 (set (reg T2) (low (reg T1) SYM))
416 (set (reg X) (plus (reg T2) (const_int OFFSET)))
420 (set (reg T3) (high SYM+OFFSET))
421 (set (reg X) (lo_sum (reg T3) SYM+OFFSET))
423 if T2 is only used this once. */
424 switch (GET_CODE (op))
427 return !splittable_const_int_operand (op, mode);
434 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &symbol_type)
435 && !mips_split_p[symbol_type]);
439 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &symbol_type)
440 && !mips_split_hi_p[symbol_type]);
447 (define_predicate "cprestore_save_slot_operand"
448 (and (match_code "mem")
449 (match_test "mips_cprestore_address_p (XEXP (op, 0), false)")))
451 (define_predicate "cprestore_load_slot_operand"
452 (and (match_code "mem")
453 (match_test "mips_cprestore_address_p (XEXP (op, 0), true)")))
455 (define_predicate "consttable_operand"
456 (match_test "CONSTANT_P (op)"))
458 (define_predicate "symbolic_operand"
459 (match_code "const,symbol_ref,label_ref")
461 enum mips_symbol_type type;
462 return mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &type);
465 (define_predicate "absolute_symbolic_operand"
466 (match_code "const,symbol_ref,label_ref")
468 enum mips_symbol_type type;
469 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &type)
470 && type == SYMBOL_ABSOLUTE);
473 (define_predicate "symbolic_operand_with_high"
474 (match_code "const,symbol_ref,label_ref")
476 enum mips_symbol_type type;
477 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &type)
478 && mips_hi_relocs[(int) type]);
481 (define_predicate "force_to_mem_operand"
482 (match_code "const,symbol_ref,label_ref")
484 enum mips_symbol_type symbol_type;
485 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &symbol_type)
486 && mips_use_pcrel_pool_p[(int) symbol_type]);
489 (define_predicate "got_disp_operand"
490 (match_code "const,symbol_ref,label_ref")
492 enum mips_symbol_type type;
493 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &type)
494 && type == SYMBOL_GOT_DISP);
497 (define_predicate "got_page_ofst_operand"
498 (match_code "const,symbol_ref,label_ref")
500 enum mips_symbol_type type;
501 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &type)
502 && type == SYMBOL_GOT_PAGE_OFST);
505 (define_predicate "tls_reloc_operand"
506 (match_code "const,symbol_ref,label_ref")
508 enum mips_symbol_type type;
509 return (mips_symbolic_constant_p (op, SYMBOL_CONTEXT_LEA, &type)
510 && (type == SYMBOL_DTPREL || type == SYMBOL_TPREL));
513 (define_predicate "symbol_ref_operand"
514 (match_code "symbol_ref"))
516 (define_predicate "stack_operand"
517 (and (match_code "mem")
518 (match_test "mips_stack_address_p (XEXP (op, 0), GET_MODE (op))")))
520 (define_predicate "macc_msac_operand"
521 (ior (and (match_code "plus") (match_test "ISA_HAS_MACC"))
522 (and (match_code "minus") (match_test "ISA_HAS_MSAC")))
524 rtx mult = XEXP (op, GET_CODE (op) == PLUS ? 0 : 1);
525 rtx accum = XEXP (op, GET_CODE (op) == PLUS ? 1 : 0);
526 return (GET_CODE (mult) == MULT
527 && REG_P (XEXP (mult, 0))
528 && REG_P (XEXP (mult, 1))
533 (define_predicate "equality_operator"
534 (match_code "eq,ne"))
536 (define_predicate "extend_operator"
537 (match_code "zero_extend,sign_extend"))
539 (define_predicate "trap_comparison_operator"
540 (match_code "eq,ne,lt,ltu,ge,geu"))
542 (define_predicate "order_operator"
543 (match_code "lt,ltu,le,leu,ge,geu,gt,gtu")
545 if (XEXP (op, 1) == const0_rtx)
549 && (GET_CODE (op) == LT || GET_CODE (op) == LTU
550 || GET_CODE (op) == GE || GET_CODE (op) == GEU))
556 ;; For NE, cstore uses sltu instructions in which the first operand is $0.
557 ;; This isn't possible in mips16 code.
559 (define_predicate "mips_cstore_operator"
560 (ior (match_code "eq,gt,gtu,ge,geu,lt,ltu,le,leu")
561 (and (match_code "ne") (not (match_test "TARGET_MIPS16")))))
563 (define_predicate "small_data_pattern"
564 (and (match_code "set,parallel,unspec,unspec_volatile,prefetch")
565 (match_test "mips_small_data_pattern_p (op)")))
567 (define_predicate "mem_noofs_operand"
568 (and (match_code "mem")
569 (match_code "reg" "0")))
571 ;; Return 1 if the operand is in non-volatile memory.
572 (define_predicate "non_volatile_mem_operand"
573 (and (match_operand 0 "memory_operand")
574 (not (match_test "MEM_VOLATILE_P (op)"))))
576 (define_predicate "const_vector_same_val_operand"
577 (match_code "const_vector")
579 return mips_const_vector_same_val_p (op, mode);
582 (define_predicate "const_vector_same_simm5_operand"
583 (match_code "const_vector")
585 return mips_const_vector_same_int_p (op, mode, -16, 15);
588 (define_predicate "const_vector_same_uimm5_operand"
589 (match_code "const_vector")
591 return mips_const_vector_same_int_p (op, mode, 0, 31);
594 (define_predicate "const_vector_same_ximm5_operand"
595 (match_code "const_vector")
597 return mips_const_vector_same_int_p (op, mode, -31, 31);
600 (define_predicate "const_vector_same_uimm6_operand"
601 (match_code "const_vector")
603 return mips_const_vector_same_int_p (op, mode, 0, 63);
606 (define_predicate "const_vector_same_uimm8_operand"
607 (match_code "const_vector")
609 return mips_const_vector_same_int_p (op, mode, 0, 255);
612 (define_predicate "par_const_vector_shf_set_operand"
613 (match_code "parallel")
615 return mips_const_vector_shuffle_set_p (op, mode);
618 (define_predicate "reg_or_vector_same_val_operand"
619 (ior (match_operand 0 "register_operand")
620 (match_operand 0 "const_vector_same_val_operand")))
622 (define_predicate "reg_or_vector_same_simm5_operand"
623 (ior (match_operand 0 "register_operand")
624 (match_operand 0 "const_vector_same_simm5_operand")))
626 (define_predicate "reg_or_vector_same_uimm5_operand"
627 (ior (match_operand 0 "register_operand")
628 (match_operand 0 "const_vector_same_uimm5_operand")))
630 (define_predicate "reg_or_vector_same_ximm5_operand"
631 (ior (match_operand 0 "register_operand")
632 (match_operand 0 "const_vector_same_ximm5_operand")))
634 (define_predicate "reg_or_vector_same_uimm6_operand"
635 (ior (match_operand 0 "register_operand")
636 (match_operand 0 "const_vector_same_uimm6_operand")))