1 ;; GCC machine description for Matsushita MN10300
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 ;; 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Jeff Law (law@cygnus.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; The original PO technology requires these to be ordered by speed,
24 ;; so that assigner will pick the fastest.
26 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
43 ;; This is used to encode LIW patterns.
45 ;; This is for the low overhead loop instructions.
49 (include "predicates.md")
50 (include "constraints.md")
52 ;; Processor type. This attribute must exactly match the processor_type
53 ;; enumeration in mn10300.h.
54 (define_attr "cpu" "mn10300,am33,am33_2,am34"
55 (const (symbol_ref "(enum attr_cpu) mn10300_tune_cpu")))
57 ;; Used to control the "enabled" attribute on a per-instruction basis.
58 (define_attr "isa" "base,am33,am33_2,am34"
59 (const_string "base"))
61 (define_attr "enabled" ""
62 (cond [(eq_attr "isa" "base")
65 (and (eq_attr "isa" "am33")
66 (match_test "TARGET_AM33"))
69 (and (eq_attr "isa" "am33_2")
70 (match_test "TARGET_AM33_2"))
73 (and (eq_attr "isa" "am34")
74 (match_test "TARGET_AM34"))
80 (define_mode_iterator INT [QI HI SI])
83 ;; Bundling of smaller insns into a long instruction word (LIW)
84 (define_automaton "liw_bundling")
85 (automata_option "ndfa")
87 (define_cpu_unit "liw_op1_u,liw_op2_u" "liw_bundling")
89 (define_attr "liw" "op1,op2,both,either"
90 (const_string "both"))
91 ;; Note: this list must match the one defined for liw_op_names[].
92 (define_attr "liw_op" "add,cmp,sub,mov,and,or,xor,asr,lsr,asl,none,max"
93 (const_string "none"))
95 (define_insn_reservation "liw_op1" 1
96 (and (ior (eq_attr "cpu" "am33")
97 (eq_attr "cpu" "am33_2")
98 (eq_attr "cpu" "am34"))
99 (eq_attr "liw" "op1"))
101 (define_insn_reservation "liw_op2" 1
102 (and (ior (eq_attr "cpu" "am33")
103 (eq_attr "cpu" "am33_2")
104 (eq_attr "cpu" "am34"))
105 (eq_attr "liw" "op2"))
107 (define_insn_reservation "liw_both" 1
108 (and (ior (eq_attr "cpu" "am33")
109 (eq_attr "cpu" "am33_2")
110 (eq_attr "cpu" "am34"))
111 (eq_attr "liw" "both"))
112 "liw_op1_u + liw_op2_u");
113 (define_insn_reservation "liw_either" 1
114 (and (ior (eq_attr "cpu" "am33")
115 (eq_attr "cpu" "am33_2")
116 (eq_attr "cpu" "am34"))
117 (eq_attr "liw" "either"))
118 "liw_op1_u | liw_op2_u");
120 ;; ----------------------------------------------------------------------
121 ;; Pipeline description.
122 ;; ----------------------------------------------------------------------
124 ;; The AM33 only has a single pipeline. It has five stages (fetch,
125 ;; decode, execute, memory access, writeback) each of which normally
126 ;; takes a single CPU clock cycle.
128 ;; The timings attribute consists of two numbers, the first is the
129 ;; throughput, which is the number of cycles the instruction takes
130 ;; to execute and generate a result. The second is the latency
131 ;; which is the effective number of cycles the instruction takes to
132 ;; execute if its result is used by the following instruction. The
133 ;; latency is always greater than or equal to the throughput.
134 ;; These values were taken from the Appendix of the "MN103E Series
135 ;; Instruction Manual" and the timings for the AM34.
137 ;; Note - it would be nice to use strings rather than integers for
138 ;; the possible values of this attribute, so that we can have the
139 ;; gcc build mechanism check for values that are not supported by
140 ;; the reservations below. But this will not work because the code
141 ;; in mn10300_adjust_sched_cost() needs integers not strings.
143 (define_attr "timings" "" (const_int 11))
145 (define_automaton "pipelining")
146 (define_cpu_unit "throughput" "pipelining")
148 (define_insn_reservation "throughput__1_latency__1" 1
149 (eq_attr "timings" "11") "throughput")
150 (define_insn_reservation "throughput__1_latency__2" 2
151 (eq_attr "timings" "12") "throughput,nothing")
152 (define_insn_reservation "throughput__1_latency__3" 3
153 (eq_attr "timings" "13") "throughput,nothing*2")
154 (define_insn_reservation "throughput__1_latency__4" 4
155 (eq_attr "timings" "14") "throughput,nothing*3")
156 (define_insn_reservation "throughput__2_latency__2" 2
157 (eq_attr "timings" "22") "throughput*2")
158 (define_insn_reservation "throughput__2_latency__3" 3
159 (eq_attr "timings" "23") "throughput*2,nothing")
160 (define_insn_reservation "throughput__2_latency__4" 4
161 (eq_attr "timings" "24") "throughput*2,nothing*2")
162 (define_insn_reservation "throughput__2_latency__5" 5
163 (eq_attr "timings" "25") "throughput*2,nothing*3")
164 (define_insn_reservation "throughput__3_latency__3" 3
165 (eq_attr "timings" "33") "throughput*3")
166 (define_insn_reservation "throughput__3_latency__7" 7
167 (eq_attr "timings" "37") "throughput*3,nothing*4")
168 (define_insn_reservation "throughput__4_latency__4" 4
169 (eq_attr "timings" "44") "throughput*4")
170 (define_insn_reservation "throughput__4_latency__7" 7
171 (eq_attr "timings" "47") "throughput*4,nothing*3")
172 (define_insn_reservation "throughput__4_latency__8" 8
173 (eq_attr "timings" "48") "throughput*4,nothing*4")
174 (define_insn_reservation "throughput__5_latency__5" 5
175 (eq_attr "timings" "55") "throughput*5")
176 (define_insn_reservation "throughput__6_latency__6" 6
177 (eq_attr "timings" "66") "throughput*6")
178 (define_insn_reservation "throughput__7_latency__7" 7
179 (eq_attr "timings" "77") "throughput*7")
180 (define_insn_reservation "throughput__7_latency__8" 8
181 (eq_attr "timings" "78") "throughput*7,nothing")
182 (define_insn_reservation "throughput__8_latency__8" 8
183 (eq_attr "timings" "88") "throughput*8")
184 (define_insn_reservation "throughput__9_latency__9" 9
185 (eq_attr "timings" "99") "throughput*9")
186 (define_insn_reservation "throughput__8_latency_14" 14
187 (eq_attr "timings" "814") "throughput*8,nothing*6")
188 (define_insn_reservation "throughput__9_latency_10" 10
189 (eq_attr "timings" "910") "throughput*9,nothing")
190 (define_insn_reservation "throughput_10_latency_10" 10
191 (eq_attr "timings" "1010") "throughput*10")
192 (define_insn_reservation "throughput_12_latency_16" 16
193 (eq_attr "timings" "1216") "throughput*12,nothing*4")
194 (define_insn_reservation "throughput_13_latency_13" 13
195 (eq_attr "timings" "1313") "throughput*13")
196 (define_insn_reservation "throughput_14_latency_14" 14
197 (eq_attr "timings" "1414") "throughput*14")
198 (define_insn_reservation "throughput_13_latency_17" 17
199 (eq_attr "timings" "1317") "throughput*13,nothing*4")
200 (define_insn_reservation "throughput_23_latency_27" 27
201 (eq_attr "timings" "2327") "throughput*23,nothing*4")
202 (define_insn_reservation "throughput_25_latency_31" 31
203 (eq_attr "timings" "2531") "throughput*25,nothing*6")
204 (define_insn_reservation "throughput_38_latency_39" 39
205 (eq_attr "timings" "3839") "throughput*38,nothing")
206 (define_insn_reservation "throughput_39_latency_40" 40
207 (eq_attr "timings" "3940") "throughput*39,nothing")
208 (define_insn_reservation "throughput_40_latency_40" 40
209 (eq_attr "timings" "4040") "throughput*40")
210 (define_insn_reservation "throughput_41_latency_42" 42
211 (eq_attr "timings" "4142") "throughput*41,nothing")
212 (define_insn_reservation "throughput_42_latency_43" 44
213 (eq_attr "timings" "4243") "throughput*42,nothing")
214 (define_insn_reservation "throughput_43_latency_44" 44
215 (eq_attr "timings" "4344") "throughput*43,nothing")
216 (define_insn_reservation "throughput_45_latency_46" 46
217 (eq_attr "timings" "4546") "throughput*45,nothing")
218 (define_insn_reservation "throughput_47_latency_53" 53
219 (eq_attr "timings" "4753") "throughput*47,nothing*6")
221 ;; Note - the conflict between memory load/store instructions
222 ;; and floating point instructions described in section 1-7-4
223 ;; of Chapter 3 of the MN103E Series Instruction Manual is
224 ;; handled by the mn10300_adjust_sched_cost function.
226 ;; ----------------------------------------------------------------------
228 ;; ----------------------------------------------------------------------
232 (define_expand "movqi"
233 [(set (match_operand:QI 0 "nonimmediate_operand")
234 (match_operand:QI 1 "general_operand"))]
237 /* One of the ops has to be in a register. */
238 if (!register_operand (operand0, QImode)
239 && !register_operand (operand1, QImode))
240 operands[1] = force_reg (QImode, operand1);
243 (define_insn "*movqi_internal"
244 [(set (match_operand:QI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m,*z,d")
245 (match_operand:QI 1 "general_operand" " 0,D*r, i,m,D,d,*z"))]
246 "(register_operand (operands[0], QImode)
247 || register_operand (operands[1], QImode))"
249 switch (which_alternative)
260 return "movbu %1,%0";
265 [(set_attr_alternative "timings"
269 (if_then_else (eq_attr "cpu" "am34")
270 (const_int 13) (const_int 24))
271 (if_then_else (eq_attr "cpu" "am34")
272 (const_int 11) (const_int 22))
280 (define_expand "movhi"
281 [(set (match_operand:HI 0 "nonimmediate_operand")
282 (match_operand:HI 1 "general_operand"))]
285 /* One of the ops has to be in a register. */
286 if (!register_operand (operand1, HImode)
287 && !register_operand (operand0, HImode))
288 operands[1] = force_reg (HImode, operand1);
291 (define_insn "*movhi_internal"
292 [(set (match_operand:HI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m,*z,d")
293 (match_operand:HI 1 "general_operand" " 0, i,D*r,m,D,d,*z"))]
294 "(register_operand (operands[0], HImode)
295 || register_operand (operands[1], HImode))"
297 switch (which_alternative)
302 /* Note that "MOV imm8,An" is already zero-extending, and is 2 bytes.
303 We have "MOV imm16,Dn" at 3 bytes. The only win for the 4 byte
304 movu is for an 8-bit unsigned move into Rn. */
306 && CONST_INT_P (operands[1])
307 && IN_RANGE (INTVAL (operands[1]), 0x80, 0xff)
308 && REGNO_EXTENDED_P (REGNO (operands[0]), 1))
317 return "movhu %1,%0";
322 [(set_attr_alternative "timings"
325 (if_then_else (eq_attr "cpu" "am34")
326 (const_int 11) (const_int 22))
327 (if_then_else (eq_attr "cpu" "am34")
328 (const_int 13) (const_int 24))
329 (if_then_else (eq_attr "cpu" "am34")
330 (const_int 11) (const_int 22))
331 (if_then_else (eq_attr "cpu" "am34")
332 (const_int 11) (const_int 22))
333 (if_then_else (eq_attr "cpu" "am34")
334 (const_int 11) (const_int 22))
340 ;; We use this to handle addition of two values when one operand is the
341 ;; stack pointer and the other is a memory reference of some kind. Reload
342 ;; does not handle them correctly without this expander.
343 (define_expand "reload_plus_sp_const"
344 [(set (match_operand:SI 0 "register_operand" "=r")
345 (match_operand:SI 1 "impossible_plus_operand" ""))
346 (clobber (match_operand:SI 2 "register_operand" "=&A"))]
349 rtx dest, scratch, other;
352 scratch = operands[2];
354 other = XEXP (operands[1], 1);
355 if (other == stack_pointer_rtx)
356 other = XEXP (operands[1], 0);
358 if (true_regnum (other) == true_regnum (dest))
360 gcc_assert (true_regnum (scratch) != true_regnum (dest));
361 emit_move_insn (scratch, stack_pointer_rtx);
362 emit_insn (gen_addsi3 (dest, dest, scratch));
364 else if (TARGET_AM33 || REGNO_REG_CLASS (true_regnum (dest)) == ADDRESS_REGS)
366 emit_move_insn (dest, stack_pointer_rtx);
367 if (other == stack_pointer_rtx)
368 emit_insn (gen_addsi3 (dest, dest, dest));
369 else if (other != const0_rtx)
370 emit_insn (gen_addsi3 (dest, dest, other));
374 emit_move_insn (scratch, stack_pointer_rtx);
375 if (other == stack_pointer_rtx)
377 emit_move_insn (dest, scratch);
378 emit_insn (gen_addsi3 (dest, dest, dest));
380 else if (other != const0_rtx)
382 emit_move_insn (dest, other);
383 emit_insn (gen_addsi3 (dest, dest, scratch));
386 emit_move_insn (dest, scratch);
391 (define_expand "movsi"
392 [(set (match_operand:SI 0 "nonimmediate_operand")
393 (match_operand:SI 1 "general_operand"))]
396 /* One of the ops has to be in a register. */
397 if (!register_operand (operand1, SImode)
398 && !register_operand (operand0, SImode))
399 operands[1] = force_reg (SImode, operand1);
403 if (SYMBOLIC_CONST_P (operands[1]))
405 if (MEM_P (operands[0]))
406 operands[1] = force_reg (Pmode, operands[1]);
409 temp = (!can_create_pseudo_p ()
411 : gen_reg_rtx (Pmode));
412 operands[1] = mn10300_legitimize_pic_address (operands[1], temp);
415 else if (GET_CODE (operands[1]) == CONST
416 && GET_CODE (XEXP (operands[1], 0)) == PLUS
417 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
419 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
420 temp = mn10300_legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
422 operands[1] = expand_binop (SImode, add_optab, temp,
423 XEXP (XEXP (operands[1], 0), 1),
424 (!can_create_pseudo_p ()
426 : gen_reg_rtx (Pmode)),
432 (define_insn "*movsi_internal"
433 [(set (match_operand:SI 0 "nonimmediate_operand"
434 "=r,r,r,r,m,r, A,*y,*y,*z,*d")
435 (match_operand:SI 1 "general_operand"
436 " 0,O,i,r,r,m,*y, A, i,*d,*z"))]
437 "register_operand (operands[0], SImode)
438 || register_operand (operands[1], SImode)"
440 switch (which_alternative)
444 case 1: /* imm-reg. */
446 /* See movhi for a discussion of sizes for 8-bit movu. Note that the
447 24-bit movu is 6 bytes, which is the same size as the full 32-bit
448 mov form for An and Dn. So again movu is only a win for Rn. */
450 && CONST_INT_P (operands[1])
451 && REGNO_EXTENDED_P (REGNO (operands[0]), 1))
453 HOST_WIDE_INT val = INTVAL (operands[1]);
454 if (IN_RANGE (val, 0x80, 0xff)
455 || IN_RANGE (val, 0x800000, 0xffffff))
459 case 3: /* reg-reg */
460 case 4: /* reg-mem */
461 case 5: /* mem-reg */
465 case 9: /* reg-mdr */
466 case 10: /* mdr-reg */
472 [(set_attr "isa" "*,*,*,*,*,*,*,*,am33,*,*")
473 (set_attr "liw" "*,either,*,either,*,*,*,*,*,*,*")
474 (set_attr "liw_op" "mov")
475 (set_attr_alternative "timings"
480 (if_then_else (eq_attr "cpu" "am34")
481 (const_int 11) (const_int 22))
482 (if_then_else (eq_attr "cpu" "am34")
483 (const_int 13) (const_int 24))
484 (if_then_else (eq_attr "cpu" "am34")
485 (const_int 11) (const_int 22))
486 (if_then_else (eq_attr "cpu" "am34")
487 (const_int 13) (const_int 24))
494 (define_expand "movsf"
495 [(set (match_operand:SF 0 "nonimmediate_operand")
496 (match_operand:SF 1 "general_operand"))]
499 /* One of the ops has to be in a register. */
500 if (!register_operand (operand1, SFmode)
501 && !register_operand (operand0, SFmode))
502 operands[1] = force_reg (SFmode, operand1);
505 (define_insn "*movsf_internal"
506 [(set (match_operand:SF 0 "nonimmediate_operand" "=rf,r,f,r,f,r,f,r,m,f,Q,z,d")
507 (match_operand:SF 1 "general_operand" " 0,F,F,r,f,f,r,m,r,Q,f,d,z"))]
509 && (register_operand (operands[0], SFmode)
510 || register_operand (operands[1], SFmode))"
512 switch (which_alternative)
534 [(set_attr_alternative "timings"
537 (if_then_else (eq_attr "cpu" "am34")
538 (const_int 47) (const_int 25))
540 (if_then_else (eq_attr "cpu" "am34")
541 (const_int 13) (const_int 14))
542 (if_then_else (eq_attr "cpu" "am34")
543 (const_int 13) (const_int 12))
544 (if_then_else (eq_attr "cpu" "am34")
545 (const_int 13) (const_int 14))
546 (if_then_else (eq_attr "cpu" "am34")
547 (const_int 13) (const_int 24))
548 (if_then_else (eq_attr "cpu" "am34")
549 (const_int 13) (const_int 24))
550 (if_then_else (eq_attr "cpu" "am34")
551 (const_int 13) (const_int 24))
552 (if_then_else (eq_attr "cpu" "am34")
553 (const_int 13) (const_int 24))
559 ;; If the flags register is not live, generate CLR instead of MOV 0.
560 ;; For MN103, this is only legal for DATA_REGS; for AM33 this is legal
561 ;; but not a win for ADDRESS_REGS.
563 [(set (match_operand:INT 0 "register_operand" "") (const_int 0))]
564 "peep2_regno_dead_p (0, CC_REG)
565 && (REGNO_DATA_P (REGNO (operands[0]), 1)
566 || REGNO_EXTENDED_P (REGNO (operands[0]), 1))"
567 [(parallel [(set (match_dup 0) (const_int 0))
568 (clobber (reg:CC CC_REG))])]
571 (define_insn "*mov<mode>_clr"
572 [(set (match_operand:INT 0 "register_operand" "=D")
574 (clobber (reg:CC CC_REG))]
579 ;; ----------------------------------------------------------------------
581 ;; ----------------------------------------------------------------------
583 (define_insn "addsi3"
584 [(set (match_operand:SI 0 "register_operand" "=r,r,r,!*y,!r")
585 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0, r")
586 (match_operand:SI 2 "nonmemory_operand" "r,O,i, i, r")))
587 (clobber (reg:CC CC_REG))]
589 { return mn10300_output_add (operands, false); }
590 [(set_attr "timings" "11,11,11,11,22")
591 (set_attr "liw" "either,either,*,*,*")
592 (set_attr "liw_op" "add")]
595 ;; Note that ADD IMM,SP does not set the flags, so omit that here.
596 (define_insn "*addsi3_flags"
597 [(set (match_operand:SI 0 "register_operand" "=r,!r")
598 (plus:SI (match_operand:SI 1 "register_operand" "%0, r")
599 (match_operand:SI 2 "nonmemory_operand" "ri, r")))
601 (compare (plus:SI (match_dup 1) (match_dup 2))
603 "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
604 { return mn10300_output_add (operands, true); }
605 [(set_attr "timings" "11,22")]
608 ;; A helper to expand the above, with the CC_MODE filled in.
609 (define_expand "addsi3_flags"
610 [(parallel [(set (match_operand:SI 0 "register_operand")
611 (plus:SI (match_operand:SI 1 "register_operand")
612 (match_operand:SI 2 "nonmemory_operand")))
613 (set (reg:CCZNC CC_REG)
614 (compare:CCZNC (plus:SI (match_dup 1) (match_dup 2))
619 (define_insn "addc_internal"
620 [(set (match_operand:SI 0 "register_operand" "=D,r,r")
623 (ltu:SI (reg:CC CC_REG) (const_int 0))
624 (match_operand:SI 1 "register_operand" "%0,0,r"))
625 (match_operand:SI 2 "reg_or_am33_const_operand" " D,i,r")))
626 (clobber (reg:CC CC_REG))]
632 [(set_attr "isa" "*,am33,am33")]
635 (define_expand "adddi3"
636 [(set (match_operand:DI 0 "register_operand" "")
637 (plus:DI (match_operand:DI 1 "register_operand" "")
638 (match_operand:DI 2 "nonmemory_operand" "")))]
641 rtx op0l, op0h, op1l, op1h, op2l, op2h;
643 op0l = gen_lowpart (SImode, operands[0]);
644 op1l = gen_lowpart (SImode, operands[1]);
645 op2l = gen_lowpart (SImode, operands[2]);
646 op0h = gen_highpart (SImode, operands[0]);
647 op1h = gen_highpart (SImode, operands[1]);
648 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
650 if (!reg_or_am33_const_operand (op2h, SImode))
651 op2h = force_reg (SImode, op2h);
653 emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));
657 ;; Note that reload only supports one commutative operand. Thus we cannot
658 ;; auto-swap both the high and low outputs with their matching constraints.
659 ;; For MN103, we're strapped for registers but thankfully the alternatives
660 ;; are few. For AM33, it becomes much easier to not represent the early
661 ;; clobber and 6 permutations of immediate and three-operand adds, but
662 ;; instead allocate a scratch register and do the expansion by hand.
664 (define_insn_and_split "adddi3_internal"
665 [(set (match_operand:SI 0 "register_operand" "=r, r, r")
666 (plus:SI (match_operand:SI 2 "register_operand" "%0, 0, r")
667 (match_operand:SI 3 "nonmemory_operand" "ri,ri,ri")))
668 (set (match_operand:SI 1 "register_operand" "=D, D, r")
671 (ltu:SI (plus:SI (match_dup 2) (match_dup 3)) (match_dup 2))
672 (match_operand:SI 4 "register_operand" " 1, D, r"))
673 (match_operand:SI 5 "reg_or_am33_const_operand" " D, 1,ri")))
674 (clobber (match_scratch:SI 6 "=X, X,&r"))
675 (clobber (reg:CC CC_REG))]
681 rtx op0l = operands[0];
682 rtx op0h = operands[1];
683 rtx op1l = operands[2];
684 rtx op2l = operands[3];
685 rtx op1h = operands[4];
686 rtx op2h = operands[5];
687 rtx scratch = operands[6];
690 if (reg_overlap_mentioned_p (op0l, op1h))
692 emit_move_insn (scratch, op0l);
694 if (reg_overlap_mentioned_p (op0l, op2h))
697 else if (reg_overlap_mentioned_p (op0l, op2h))
699 emit_move_insn (scratch, op0l);
703 if (rtx_equal_p (op0l, op1l))
705 else if (rtx_equal_p (op0l, op2l))
706 x = op1l, op1l = op2l, op2l = x;
709 gcc_assert (TARGET_AM33);
712 emit_move_insn (op0l, op2l);
717 emit_insn (gen_addsi3_flags (op0l, op1l, op2l));
719 if (rtx_equal_p (op0h, op1h))
721 else if (rtx_equal_p (op0h, op2h))
722 x = op1h, op1h = op2h, op2h = x;
725 gcc_assert (TARGET_AM33);
728 emit_move_insn (op0h, op2h);
733 emit_insn (gen_addc_internal (op0h, op1h, op2h));
736 [(set_attr "isa" "*,*,am33")]
739 ;; The following pattern is generated by combine when it proves that one
740 ;; of the inputs to the low-part of the double-word add is zero, and thus
741 ;; no carry is generated into the high-part.
743 (define_insn_and_split "*adddi3_degenerate"
744 [(set (match_operand:SI 0 "register_operand" "=&r,&r")
745 (match_operand:SI 2 "nonmemory_operand" " 0, 0"))
746 (set (match_operand:SI 1 "register_operand" "=r , r")
747 (plus:SI (match_operand:SI 3 "register_operand" "%1 , r")
748 (match_operand:SI 4 "nonmemory_operand" "ri, r")))
749 (clobber (reg:CC CC_REG))]
755 rtx scratch = NULL_RTX;
756 if (!rtx_equal_p (operands[0], operands[2]))
758 gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1]));
759 if (reg_overlap_mentioned_p (operands[0], operands[3])
760 || reg_overlap_mentioned_p (operands[0], operands[4]))
762 scratch = gen_reg_rtx (SImode);
763 emit_move_insn (scratch, operands[2]);
766 emit_move_insn (operands[0], operands[2]);
768 emit_insn (gen_addsi3 (operands[1], operands[3], operands[4]));
770 emit_move_insn (operands[0], scratch);
774 ;; ----------------------------------------------------------------------
775 ;; SUBTRACT INSTRUCTIONS
776 ;; ----------------------------------------------------------------------
778 (define_insn "subsi3"
779 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
780 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r")
781 (match_operand:SI 2 "nonmemory_operand" "r,O,i,r")))
782 (clobber (reg:CC CC_REG))]
789 [(set_attr "isa" "*,*,*,am33")
790 (set_attr "liw" "either,either,*,*")
791 (set_attr "liw_op" "sub")
792 (set_attr "timings" "11,11,11,22")]
795 (define_insn "*subsi3_flags"
796 [(set (match_operand:SI 0 "register_operand" "=r, r")
797 (minus:SI (match_operand:SI 1 "register_operand" "0, r")
798 (match_operand:SI 2 "nonmemory_operand" "ri,r")))
800 (compare (minus:SI (match_dup 1) (match_dup 2))
802 "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
806 [(set_attr "isa" "*,am33")
807 (set_attr "timings" "11,22")]
810 ;; A helper to expand the above, with the CC_MODE filled in.
811 (define_expand "subsi3_flags"
812 [(parallel [(set (match_operand:SI 0 "register_operand")
813 (minus:SI (match_operand:SI 1 "register_operand")
814 (match_operand:SI 2 "nonmemory_operand")))
815 (set (reg:CCZNC CC_REG)
816 (compare:CCZNC (minus:SI (match_dup 1) (match_dup 2))
821 (define_insn "subc_internal"
822 [(set (match_operand:SI 0 "register_operand" "=D,r,r")
824 (minus:SI (match_operand:SI 1 "register_operand" " 0,0,r")
825 (match_operand:SI 2 "reg_or_am33_const_operand" " D,i,r"))
826 (geu:SI (reg:CC CC_REG) (const_int 0))))
827 (clobber (reg:CC CC_REG))]
833 [(set_attr "isa" "*,am33,am33")]
836 (define_expand "subdi3"
837 [(set (match_operand:DI 0 "register_operand" "")
838 (minus:DI (match_operand:DI 1 "register_operand" "")
839 (match_operand:DI 2 "nonmemory_operand" "")))]
842 rtx op0l, op0h, op1l, op1h, op2l, op2h;
844 op0l = gen_lowpart (SImode, operands[0]);
845 op1l = gen_lowpart (SImode, operands[1]);
846 op2l = gen_lowpart (SImode, operands[2]);
847 op0h = gen_highpart (SImode, operands[0]);
848 op1h = gen_highpart (SImode, operands[1]);
849 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
851 if (!reg_or_am33_const_operand (op2h, SImode))
852 op2h = force_reg (SImode, op2h);
854 emit_insn (gen_subdi3_internal (op0l, op0h, op1l, op1h, op2l, op2h));
858 ;; As with adddi3, the use of the scratch register helps reduce the
859 ;; number of permutations for AM33.
860 ;; ??? The early clobber on op0 avoids a reload bug wherein both output
861 ;; registers are set the same. Consider negate, where both op2 and op3
862 ;; are 0, are csed to the same input register, and reload fails to undo
863 ;; the cse when satisfying the matching constraints.
865 (define_insn_and_split "subdi3_internal"
866 [(set (match_operand:SI 0 "register_operand" "=&r, r")
868 (match_operand:SI 2 "register_operand" " 0, r")
869 (match_operand:SI 4 "nonmemory_operand" " ri,ri")))
870 (set (match_operand:SI 1 "register_operand" "=D , r")
873 (match_operand:SI 3 "register_operand" " 1, r")
874 (match_operand:SI 5 "reg_or_am33_const_operand" " D,ri"))
875 (ltu:SI (match_dup 2) (match_dup 4))))
876 (clobber (match_scratch:SI 6 "=X ,&r"))
877 (clobber (reg:CC CC_REG))]
883 rtx op0l = operands[0];
884 rtx op0h = operands[1];
885 rtx op1l = operands[2];
886 rtx op1h = operands[3];
887 rtx op2l = operands[4];
888 rtx op2h = operands[5];
889 rtx scratch = operands[6];
891 if (reg_overlap_mentioned_p (op0l, op1h))
893 emit_move_insn (scratch, op0l);
895 if (reg_overlap_mentioned_p (op0l, op2h))
898 else if (reg_overlap_mentioned_p (op0l, op2h))
900 emit_move_insn (scratch, op0l);
904 if (!rtx_equal_p (op0l, op1l))
906 gcc_assert (TARGET_AM33);
909 emit_move_insn (op0l, op1l);
913 emit_insn (gen_subsi3_flags (op0l, op1l, op2l));
915 if (!rtx_equal_p (op0h, op1h))
917 gcc_assert (TARGET_AM33);
920 emit_move_insn (op0h, op1h);
924 emit_insn (gen_subc_internal (op0h, op1h, op2h));
927 [(set_attr "isa" "*,am33")]
930 ;; The following pattern is generated by combine when it proves that one
931 ;; of the inputs to the low-part of the double-word sub is zero, and thus
932 ;; no carry is generated into the high-part.
934 (define_insn_and_split "*subdi3_degenerate"
935 [(set (match_operand:SI 0 "register_operand" "=&r,&r")
936 (match_operand:SI 2 "nonmemory_operand" " 0, 0"))
937 (set (match_operand:SI 1 "register_operand" "=r , r")
938 (minus:SI (match_operand:SI 3 "register_operand" " 1, r")
939 (match_operand:SI 4 "nonmemory_operand" " ri, r")))
940 (clobber (reg:CC CC_REG))]
946 rtx scratch = NULL_RTX;
947 if (!rtx_equal_p (operands[0], operands[2]))
949 gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1]));
950 if (reg_overlap_mentioned_p (operands[0], operands[3])
951 || reg_overlap_mentioned_p (operands[0], operands[4]))
953 scratch = gen_reg_rtx (SImode);
954 emit_move_insn (scratch, operands[2]);
957 emit_move_insn (operands[0], operands[2]);
959 emit_insn (gen_subsi3 (operands[1], operands[3], operands[4]));
961 emit_move_insn (operands[0], scratch);
965 (define_insn_and_split "negsi2"
966 [(set (match_operand:SI 0 "register_operand" "=D,&r")
967 (neg:SI (match_operand:SI 1 "register_operand" " 0, r")))
968 (clobber (reg:CC CC_REG))]
971 "&& reload_completed"
974 /* Recall that twos-compliment is ones-compliment plus one. When
975 allocated in DATA_REGS this is 2+1 bytes; otherwise (for am33)
978 For AM33, it would have been possible to load zero and use the
979 three-address subtract to have a total size of 3+4*N bytes for
980 multiple negations, plus increased throughput. Not attempted here. */
982 if (true_regnum (operands[0]) == true_regnum (operands[1]))
984 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
985 emit_insn (gen_addsi3 (operands[0], operands[0], const1_rtx));
989 emit_move_insn (operands[0], const0_rtx);
990 emit_insn (gen_subsi3 (operands[0], operands[0], operands[1]));
995 ;; ----------------------------------------------------------------------
996 ;; MULTIPLY INSTRUCTIONS
997 ;; ----------------------------------------------------------------------
999 ;; ??? Note that AM33 has a third multiply variant that puts the high part
1000 ;; into the MDRQ register, however this variant also constrains the inputs
1001 ;; to be in DATA_REGS and thus isn't as helpful as it might be considering
1002 ;; the existance of the 4-operand multiply. Nor is there a set of divide
1003 ;; insns that use MDRQ. Given that there is an IMM->MDRQ insn, this would
1004 ;; have been very handy for starting udivmodsi4...
1006 (define_expand "mulsidi3"
1007 [(set (match_operand:DI 0 "register_operand" "")
1008 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
1009 (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))]
1012 emit_insn (gen_mulsidi3_internal (gen_lowpart (SImode, operands[0]),
1013 gen_highpart (SImode, operands[0]),
1014 operands[1], operands[2]));
1018 (define_insn "mulsidi3_internal"
1019 [(set (match_operand:SI 0 "register_operand" "=D,r")
1020 (mult:SI (match_operand:SI 2 "register_operand" "%0,r")
1021 (match_operand:SI 3 "register_operand" " D,r")))
1022 (set (match_operand:SI 1 "register_operand" "=z,r")
1025 (mult:DI (sign_extend:DI (match_dup 2))
1026 (sign_extend:DI (match_dup 3)))
1028 (clobber (reg:CC CC_REG))]
1031 if (which_alternative == 1)
1032 return "mul %2,%3,%1,%0";
1033 else if (TARGET_MULT_BUG)
1034 return "nop\;nop\;mul %3,%0";
1038 [(set_attr "isa" "*,am33")
1039 (set (attr "timings")
1040 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
1043 (define_expand "umulsidi3"
1044 [(set (match_operand:DI 0 "register_operand" "")
1045 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
1046 (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))
1047 (clobber (reg:CC CC_REG))]
1050 emit_insn (gen_umulsidi3_internal (gen_lowpart (SImode, operands[0]),
1051 gen_highpart (SImode, operands[0]),
1052 operands[1], operands[2]));
1056 (define_insn "umulsidi3_internal"
1057 [(set (match_operand:SI 0 "register_operand" "=D,r")
1058 (mult:SI (match_operand:SI 2 "register_operand" "%0,r")
1059 (match_operand:SI 3 "register_operand" " D,r")))
1060 (set (match_operand:SI 1 "register_operand" "=z,r")
1063 (mult:DI (zero_extend:DI (match_dup 2))
1064 (zero_extend:DI (match_dup 3)))
1066 (clobber (reg:CC CC_REG))]
1069 if (which_alternative == 1)
1070 return "mulu %2,%3,%1,%0";
1071 else if (TARGET_MULT_BUG)
1072 return "nop\;nop\;mulu %3,%0";
1074 return "mulu %3,%0";
1076 [(set_attr "isa" "*,am33")
1077 (set (attr "timings")
1078 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
1081 (define_expand "mulsi3"
1082 [(parallel [(set (match_operand:SI 0 "register_operand")
1083 (mult:SI (match_operand:SI 1 "register_operand")
1084 (match_operand:SI 2 "reg_or_am33_const_operand")))
1085 (clobber (match_scratch:SI 3))
1086 (clobber (reg:CC CC_REG))])]
1090 (define_insn "*mulsi3"
1091 [(set (match_operand:SI 0 "register_operand" "=D, r,r")
1092 (mult:SI (match_operand:SI 2 "register_operand" "%0, 0,r")
1093 (match_operand:SI 3 "reg_or_am33_const_operand" " D,ri,r")))
1094 (clobber (match_scratch:SI 1 "=z, z,r"))
1095 (clobber (reg:CC CC_REG))]
1098 if (which_alternative == 2)
1099 return "mul %2,%3,%1,%0";
1100 else if (TARGET_MULT_BUG)
1101 return "nop\;nop\;mul %3,%0";
1105 [(set_attr "isa" "*,am33,am33")
1106 (set (attr "timings")
1107 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
1110 (define_expand "udivmodsi4"
1111 [(parallel [(set (match_operand:SI 0 "register_operand")
1112 (udiv:SI (match_operand:SI 1 "register_operand")
1113 (match_operand:SI 2 "register_operand")))
1114 (set (match_operand:SI 3 "register_operand")
1115 (umod:SI (match_dup 1) (match_dup 2)))
1117 (clobber (reg:CC CC_REG))])]
1121 ;; Note the trick to get reload to put the zero into the MDR register,
1122 ;; rather than exposing the load early and letting CSE or someone try
1123 ;; to share the zeros between division insns. Which tends to result
1124 ;; in sequences like 0->r0->d0->mdr.
1126 (define_insn "*udivmodsi4"
1127 [(set (match_operand:SI 0 "register_operand" "=D")
1128 (udiv:SI (match_operand:SI 2 "register_operand" " 0")
1129 (match_operand:SI 3 "register_operand" " D")))
1130 (set (match_operand:SI 1 "register_operand" "=z")
1131 (umod:SI (match_dup 2) (match_dup 3)))
1132 (use (match_operand:SI 4 "nonmemory_operand" " 1"))
1133 (clobber (reg:CC CC_REG))]
1136 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1137 (const_int 3839) (const_int 4243)))]
1140 (define_expand "divmodsi4"
1141 [(parallel [(set (match_operand:SI 0 "register_operand" "")
1142 (div:SI (match_operand:SI 1 "register_operand" "")
1143 (match_operand:SI 2 "register_operand" "")))
1144 (set (match_operand:SI 3 "register_operand" "")
1145 (mod:SI (match_dup 1) (match_dup 2)))
1147 (clobber (reg:CC CC_REG))])]
1150 operands[4] = gen_reg_rtx (SImode);
1151 emit_insn (gen_ext_internal (operands[4], operands[1]));
1154 ;; ??? Ideally we'd represent this via shift, but it seems like adding a
1155 ;; special-case pattern for (ashiftrt x 31) is just as likely to result
1156 ;; in poor register allocation choices.
1157 (define_insn "ext_internal"
1158 [(set (match_operand:SI 0 "register_operand" "=z")
1159 (unspec:SI [(match_operand:SI 1 "register_operand" "D")] UNSPEC_EXT))]
1164 (define_insn "*divmodsi4"
1165 [(set (match_operand:SI 0 "register_operand" "=D")
1166 (div:SI (match_operand:SI 2 "register_operand" " 0")
1167 (match_operand:SI 3 "register_operand" " D")))
1168 (set (match_operand:SI 1 "register_operand" "=z")
1169 (mod:SI (match_dup 2) (match_dup 3)))
1170 (use (match_operand:SI 4 "register_operand" " 1"))
1171 (clobber (reg:CC CC_REG))]
1174 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1175 (const_int 3839) (const_int 4243)))]
1179 ;; ----------------------------------------------------------------------
1181 ;; ----------------------------------------------------------------------
1183 (define_insn "andsi3"
1184 [(set (match_operand:SI 0 "register_operand" "=D,D,r")
1185 (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1186 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1187 (clobber (reg:CC CC_REG))]
1193 [(set_attr "isa" "*,*,am33")
1194 (set_attr "liw" "*,op1,*")
1195 (set_attr "liw_op" "and")
1196 (set_attr "timings" "22,11,11")]
1199 (define_insn "*andsi3_flags"
1200 [(set (match_operand:SI 0 "register_operand" "=D,D,r")
1201 (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1202 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1204 (compare (and:SI (match_dup 1) (match_dup 2))
1206 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
1211 [(set_attr "isa" "*,*,am33")
1212 (set_attr "timings" "22,11,11")]
1215 ;; Make sure we generate extensions instead of ANDs.
1218 [(parallel [(set (match_operand:SI 0 "register_operand" "")
1219 (and:SI (match_operand:SI 1 "register_operand" "")
1221 (clobber (reg:CC CC_REG))])]
1223 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
1224 { operands[1] = gen_lowpart (QImode, operands[1]); }
1228 [(parallel [(set (match_operand:SI 0 "register_operand" "")
1229 (and:SI (match_operand:SI 1 "register_operand" "")
1231 (clobber (reg:CC CC_REG))])]
1233 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
1234 { operands[1] = gen_lowpart (HImode, operands[1]); }
1237 ;; Split AND by an appropriate constant into two shifts. Recall that
1238 ;; operations with a full 32-bit immediate require an extra cycle, so
1239 ;; this is a size optimization with no speed penalty. This only applies
1240 ;; do DATA_REGS; the shift insns that AM33 adds are too large for a win.
1243 [(parallel [(set (match_operand:SI 0 "register_operand" "")
1244 (and:SI (match_dup 0)
1245 (match_operand:SI 1 "const_int_operand" "")))
1246 (clobber (reg:CC CC_REG))])]
1248 && REGNO_DATA_P (true_regnum (operands[0]), 1)
1249 && mn10300_split_and_operand_count (operands[1]) != 0"
1252 int count = mn10300_split_and_operand_count (operands[1]);
1255 emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (count)));
1256 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (count)));
1260 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (-count)));
1261 emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (-count)));
1266 ;; ----------------------------------------------------------------------
1268 ;; ----------------------------------------------------------------------
1270 (define_insn "iorsi3"
1271 [(set (match_operand:SI 0 "register_operand" "=D,D,r")
1272 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1273 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1274 (clobber (reg:CC CC_REG))]
1280 [(set_attr "isa" "*,*,am33")
1281 (set_attr "liw" "*,op1,*")
1282 (set_attr "liw_op" "or")
1283 (set_attr "timings" "22,11,11")]
1286 (define_insn "*iorsi3_flags"
1287 [(set (match_operand:SI 0 "register_operand" "=D,D,r")
1288 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1289 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1291 (compare (ior:SI (match_dup 1) (match_dup 2))
1293 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
1298 [(set_attr "isa" "*,*,am33")
1299 (set_attr "timings" "22,11,11")]
1302 ;; ----------------------------------------------------------------------
1304 ;; ----------------------------------------------------------------------
1306 (define_insn "xorsi3"
1307 [(set (match_operand:SI 0 "register_operand" "=D,D,r")
1308 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1309 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1310 (clobber (reg:CC CC_REG))]
1316 [(set_attr "isa" "*,*,am33")
1317 (set_attr "liw" "*,op1,*")
1318 (set_attr "liw_op" "xor")
1319 (set_attr "timings" "22,11,11")]
1322 (define_insn "*xorsi3_flags"
1323 [(set (match_operand:SI 0 "register_operand" "=D,D,r")
1324 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1325 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1327 (compare (xor:SI (match_dup 1) (match_dup 2))
1329 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
1334 [(set_attr "isa" "*,*,am33")
1335 (set_attr "timings" "22,11,11")]
1338 ;; ----------------------------------------------------------------------
1340 ;; ----------------------------------------------------------------------
1342 (define_insn "one_cmplsi2"
1343 [(set (match_operand:SI 0 "register_operand" "=D")
1344 (not:SI (match_operand:SI 1 "register_operand" " 0")))
1345 (clobber (reg:CC CC_REG))]
1350 (define_insn "*one_cmplsi2_flags"
1351 [(set (match_operand:SI 0 "register_operand" "=D")
1352 (not:SI (match_operand:SI 1 "register_operand" " 0")))
1354 (compare (not:SI (match_dup 1))
1356 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
1360 ;; ----------------------------------------------------------------------
1361 ;; COMPARE AND BRANCH INSTRUCTIONS
1362 ;; ----------------------------------------------------------------------
1364 ;; We expand the comparison into a single insn so that it will not be split
1366 (define_expand "cbranchsi4"
1369 (match_operator 0 "ordered_comparison_operator"
1370 [(match_operand:SI 1 "register_operand")
1371 (match_operand:SI 2 "nonmemory_operand")])
1372 (label_ref (match_operand 3 ""))
1378 (define_insn_and_split "*cbranchsi4_cmp"
1380 (if_then_else (match_operator 3 "ordered_comparison_operator"
1381 [(match_operand:SI 0 "register_operand" "r")
1382 (match_operand:SI 1 "nonmemory_operand" "ri")])
1383 (match_operand 2 "label_ref_operand" "")
1390 mn10300_split_cbranch (CCmode, operands[3], operands[2]);
1394 (define_insn "cmpsi"
1396 (compare (match_operand:SI 0 "register_operand" "r,r,r")
1397 (match_operand:SI 1 "nonmemory_operand" "r,O,i")))]
1400 /* The operands of CMP must be distinct registers. In the case where
1401 we've failed to optimize the comparison of a register to itself, we
1402 must use another method to set the Z flag. We can achieve this
1403 effect with a BTST 0,D0. This will not alter the contents of D0;
1404 the use of d0 is arbitrary; any data register would work. */
1405 if (rtx_equal_p (operands[0], operands[1]))
1410 [(set_attr_alternative "timings"
1411 [(if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))
1412 (if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))
1413 (if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))])
1414 (set_attr "liw" "either,either,*")
1415 (set_attr "liw_op" "cmp")]
1418 (define_insn "*integer_conditional_branch"
1420 (if_then_else (match_operator 0 "comparison_operator"
1421 [(match_operand 2 "int_mode_flags" "")
1423 (label_ref (match_operand 1 "" ""))
1429 (define_insn_and_split "*cbranchsi4_btst"
1432 (match_operator 3 "CCZN_comparison_operator"
1433 [(and:SI (match_operand:SI 0 "register_operand" "D")
1434 (match_operand:SI 1 "immediate_operand" "i"))
1436 (match_operand 2 "label_ref_operand" "")
1443 mn10300_split_cbranch (CCZNmode, operands[3], operands[2]);
1447 (define_insn "*btstsi"
1448 [(set (reg:CCZN CC_REG)
1450 (and:SI (match_operand:SI 0 "register_operand" "D")
1451 (match_operand:SI 1 "immediate_operand" "i"))
1457 (define_expand "cbranchsf4"
1460 (match_operator 0 "ordered_comparison_operator"
1461 [(match_operand:SF 1 "register_operand")
1462 (match_operand:SF 2 "nonmemory_operand")])
1463 (label_ref (match_operand 3 ""))
1469 (define_insn_and_split "*cbranchsf4_cmp"
1471 (if_then_else (match_operator 3 "ordered_comparison_operator"
1472 [(match_operand:SF 0 "register_operand" "f")
1473 (match_operand:SF 1 "nonmemory_operand" "fF")])
1474 (match_operand 2 "label_ref_operand" "")
1479 "&& reload_completed"
1482 mn10300_split_cbranch (CC_FLOATmode, operands[3], operands[2]);
1486 (define_insn "*am33_cmpsf"
1487 [(set (reg:CC_FLOAT CC_REG)
1488 (compare:CC_FLOAT (match_operand:SF 0 "register_operand" "f")
1489 (match_operand:SF 1 "nonmemory_operand" "fF")))]
1490 "TARGET_AM33_2 && reload_completed"
1492 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1493 (const_int 17) (const_int 25)))]
1496 (define_insn "*float_conditional_branch"
1498 (if_then_else (match_operator 0 "comparison_operator"
1499 [(reg:CC_FLOAT CC_REG) (const_int 0)])
1500 (label_ref (match_operand 1 "" ""))
1502 "TARGET_AM33_2 && reload_completed"
1504 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1505 (const_int 44) (const_int 33)))]
1508 ;; Unconditional and other jump instructions.
1512 (label_ref (match_operand 0 "" "")))]
1515 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1516 (const_int 11) (const_int 44)))]
1519 (define_insn "indirect_jump"
1520 [(set (pc) (match_operand:SI 0 "register_operand" "a"))]
1523 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1524 (const_int 11) (const_int 33)))]
1527 (define_expand "builtin_setjmp_receiver"
1528 [(match_operand 0 "" "")]
1531 emit_insn (gen_load_pic ());
1535 (define_expand "casesi"
1536 [(match_operand:SI 0 "register_operand")
1537 (match_operand:SI 1 "immediate_operand")
1538 (match_operand:SI 2 "immediate_operand")
1539 (match_operand 3 "" "") (match_operand 4 "")]
1542 rtx table = gen_reg_rtx (SImode);
1543 rtx index = gen_reg_rtx (SImode);
1544 rtx addr = gen_reg_rtx (Pmode);
1547 emit_move_insn (table, gen_rtx_LABEL_REF (VOIDmode, operands[3]));
1548 emit_insn (gen_addsi3 (index, operands[0], GEN_INT (- INTVAL (operands[1]))));
1549 test = gen_rtx_fmt_ee (GTU, VOIDmode, index, operands[2]);
1550 emit_jump_insn (gen_cbranchsi4 (test, index, operands[2], operands[4]));
1552 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
1553 emit_move_insn (addr, gen_rtx_MEM (SImode,
1554 gen_rtx_PLUS (SImode, table, index)));
1556 emit_insn (gen_addsi3 (addr, addr, table));
1558 emit_jump_insn (gen_tablejump (addr, operands[3]));
1562 (define_insn "tablejump"
1563 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1564 (use (label_ref (match_operand 1 "" "")))]
1567 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1568 (const_int 11) (const_int 33)))]
1571 ;; Call subroutine with no return value.
1573 (define_expand "call"
1574 [(call (match_operand:QI 0 "general_operand")
1575 (match_operand:SI 1 "general_operand"))]
1578 rtx fn = XEXP (operands[0], 0);
1580 if (flag_pic && GET_CODE (fn) == SYMBOL_REF)
1582 if (MN10300_GLOBAL_P (fn))
1584 /* The PLT code won't run on AM30, but then, there's no
1585 shared library support for AM30 either, so we just assume
1586 the linker is going to adjust all @PLT relocs to the
1588 emit_use (pic_offset_table_rtx);
1589 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT);
1592 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC);
1594 if (! call_address_operand (fn, VOIDmode))
1595 fn = force_reg (SImode, fn);
1597 XEXP (operands[0], 0) = fn;
1600 (define_insn "*call_internal"
1601 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "a,S"))
1602 (match_operand:SI 1 "" ""))]
1607 [(set_attr_alternative "timings"
1608 [(if_then_else (eq_attr "cpu" "am34")
1609 (const_int 33) (const_int 44))
1610 (if_then_else (eq_attr "cpu" "am34")
1611 (const_int 55) (const_int 33))
1616 ;; Call subroutine, returning value in operand 0
1617 ;; (which must be a hard register).
1619 (define_expand "call_value"
1620 [(set (match_operand 0 "")
1621 (call (match_operand:QI 1 "general_operand")
1622 (match_operand:SI 2 "general_operand")))]
1625 rtx fn = XEXP (operands[1], 0);
1627 if (flag_pic && GET_CODE (fn) == SYMBOL_REF)
1629 if (MN10300_GLOBAL_P (fn))
1631 /* The PLT code won't run on AM30, but then, there's no
1632 shared library support for AM30 either, so we just assume
1633 the linker is going to adjust all @PLT relocs to the
1635 emit_use (pic_offset_table_rtx);
1636 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT);
1639 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC);
1641 if (! call_address_operand (fn, VOIDmode))
1642 fn = force_reg (SImode, fn);
1644 XEXP (operands[1], 0) = fn;
1647 (define_insn "call_value_internal"
1648 [(set (match_operand 0 "" "")
1649 (call (mem:QI (match_operand:SI 1 "call_address_operand" "a,S"))
1650 (match_operand:SI 2 "" "")))]
1655 [(set_attr_alternative "timings"
1656 [(if_then_else (eq_attr "cpu" "am34")
1657 (const_int 33) (const_int 44))
1658 (if_then_else (eq_attr "cpu" "am34")
1659 (const_int 55) (const_int 33))
1664 (define_expand "untyped_call"
1665 [(parallel [(call (match_operand 0 "")
1667 (match_operand 1 "")
1668 (match_operand 2 "")])]
1673 emit_call_insn (gen_call (operands[0], const0_rtx));
1675 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1677 rtx set = XVECEXP (operands[2], 0, i);
1678 emit_move_insn (SET_DEST (set), SET_SRC (set));
1689 ;; ----------------------------------------------------------------------
1690 ;; EXTEND INSTRUCTIONS
1691 ;; ----------------------------------------------------------------------
1693 (define_insn "zero_extendqisi2"
1694 [(set (match_operand:SI 0 "register_operand" "=D,D,r")
1696 (match_operand:QI 1 "nonimmediate_operand" " 0,m,r")))]
1702 [(set_attr "isa" "*,*,am33")
1703 (set_attr_alternative "timings"
1705 (if_then_else (eq_attr "cpu" "am34")
1706 (const_int 13) (const_int 24))
1711 (define_insn "zero_extendhisi2"
1712 [(set (match_operand:SI 0 "register_operand" "=D,D,r")
1714 (match_operand:HI 1 "nonimmediate_operand" " 0,m,r")))]
1720 [(set_attr "isa" "*,*,am33")
1721 (set_attr_alternative "timings"
1723 (if_then_else (eq_attr "cpu" "am34")
1724 (const_int 13) (const_int 24))
1728 (define_insn "extendqisi2"
1729 [(set (match_operand:SI 0 "register_operand" "=D,r")
1731 (match_operand:QI 1 "register_operand" "0,r")))]
1736 [(set_attr "isa" "*,am33")]
1739 (define_insn "extendhisi2"
1740 [(set (match_operand:SI 0 "register_operand" "=D,r")
1742 (match_operand:HI 1 "register_operand" "0,r")))]
1747 [(set_attr "isa" "*,am33")]
1750 ;; ----------------------------------------------------------------------
1752 ;; ----------------------------------------------------------------------
1754 (define_insn "ashlsi3"
1755 [(set (match_operand:SI 0 "register_operand" "=r,D,d,d,D,D,D,r")
1757 (match_operand:SI 1 "register_operand" " 0,0,0,0,0,0,0,r")
1758 (match_operand:QI 2 "nonmemory_operand" " J,K,M,L,D,O,i,r")))
1759 (clobber (reg:CC CC_REG))]
1770 [(set_attr "isa" "*,*,*,*,*,*,*,am33")
1771 (set_attr "liw" "op2,op2,op2,op2,op2,op2,*,*")
1772 (set_attr "liw_op" "asl")
1773 (set_attr "timings" "11,11,22,22,11,11,11,11")]
1776 (define_insn "lshrsi3"
1777 [(set (match_operand:SI 0 "register_operand" "=D,D,D,r")
1779 (match_operand:SI 1 "register_operand" "0,0,0,r")
1780 (match_operand:QI 2 "nonmemory_operand" "D,O,i,r")))
1781 (clobber (reg:CC CC_REG))]
1788 [(set_attr "isa" "*,*,*,am33")
1789 (set_attr "liw" "op2,op2,*,*")
1790 (set_attr "liw_op" "lsr")]
1793 (define_insn "ashrsi3"
1794 [(set (match_operand:SI 0 "register_operand" "=D,D,D,r")
1796 (match_operand:SI 1 "register_operand" "0,0,0,r")
1797 (match_operand:QI 2 "nonmemory_operand" "D,O,i,r")))
1798 (clobber (reg:CC CC_REG))]
1805 [(set_attr "isa" "*,*,*,am33")
1806 (set_attr "liw" "op2,op2,*,*")
1807 (set_attr "liw_op" "asr")]
1810 ;; ----------------------------------------------------------------------
1812 ;; ----------------------------------------------------------------------
1814 ;; Note the use of the (const_int 0) when generating the insn that matches
1815 ;; the bsch pattern. This ensures that the destination register is
1816 ;; initialised with 0 which will make the BSCH instruction set searching
1819 ;; The XOR in the instruction sequence below is there because the BSCH
1820 ;; instruction returns the bit number of the highest set bit and we want
1821 ;; the number of zero bits above that bit. The AM33 does not have a
1822 ;; reverse subtraction instruction, but we can use a simple xor instead
1823 ;; since we know that the top 27 bits are clear.
1824 (define_expand "clzsi2"
1825 [(parallel [(set (match_operand:SI 0 "register_operand")
1826 (unspec:SI [(match_operand:SI 1 "register_operand")
1827 (const_int 0)] UNSPEC_BSCH))
1828 (clobber (reg:CC CC_REG))])
1829 (parallel [(set (match_dup 0)
1830 (xor:SI (match_dup 0)
1832 (clobber (reg:CC CC_REG))])]
1836 (define_insn "*bsch"
1837 [(set (match_operand:SI 0 "register_operand" "=r")
1838 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1839 (match_operand:SI 2 "nonmemory_operand" "0")]
1841 (clobber (reg:CC CC_REG))]
1846 ;; ----------------------------------------------------------------------
1848 ;; ----------------------------------------------------------------------
1850 (define_insn "abssf2"
1851 [(set (match_operand:SF 0 "register_operand" "=f,f")
1852 (abs:SF (match_operand:SF 1 "register_operand" "0,?f")))]
1857 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1858 (const_int 17) (const_int 14)))]
1861 (define_insn "negsf2"
1862 [(set (match_operand:SF 0 "register_operand" "=f,f")
1863 (neg:SF (match_operand:SF 1 "register_operand" "0,?f")))]
1868 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1869 (const_int 17) (const_int 14)))]
1872 (define_expand "sqrtsf2"
1873 [(set (match_operand:SF 0 "register_operand" "")
1874 (sqrt:SF (match_operand:SF 1 "register_operand" "")))]
1875 "TARGET_AM33_2 && flag_unsafe_math_optimizations"
1877 rtx scratch = gen_reg_rtx (SFmode);
1878 emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode)));
1879 emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)),
1884 (define_insn "rsqrtsf2"
1885 [(set (match_operand:SF 0 "register_operand" "=f,f")
1886 (div:SF (match_operand:SF 2 "const_1f_operand" "F,F")
1887 (sqrt:SF (match_operand:SF 1 "register_operand" "0,?f"))))
1888 (clobber (reg:CC_FLOAT CC_REG))]
1893 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1894 (const_int 4753) (const_int 2327)))]
1897 (define_insn "addsf3"
1898 [(set (match_operand:SF 0 "register_operand" "=f,f")
1899 (plus:SF (match_operand:SF 1 "register_operand" "%0,f")
1900 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1901 (clobber (reg:CC_FLOAT CC_REG))]
1906 [(set_attr_alternative "timings"
1907 [(if_then_else (eq_attr "cpu" "am34")
1908 (const_int 17) (const_int 14))
1909 (if_then_else (eq_attr "cpu" "am34")
1910 (const_int 17) (const_int 25))
1914 (define_insn "subsf3"
1915 [(set (match_operand:SF 0 "register_operand" "=f,f")
1916 (minus:SF (match_operand:SF 1 "register_operand" "0,f")
1917 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1918 (clobber (reg:CC_FLOAT CC_REG))]
1923 [(set_attr_alternative "timings"
1924 [(if_then_else (eq_attr "cpu" "am34")
1925 (const_int 17) (const_int 14))
1926 (if_then_else (eq_attr "cpu" "am34")
1927 (const_int 17) (const_int 25))
1931 (define_insn "mulsf3"
1932 [(set (match_operand:SF 0 "register_operand" "=f,f")
1933 (mult:SF (match_operand:SF 1 "register_operand" "%0,f")
1934 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1935 (clobber (reg:CC_FLOAT CC_REG))
1941 [(set_attr_alternative "timings"
1942 [(if_then_else (eq_attr "cpu" "am34")
1943 (const_int 17) (const_int 14))
1944 (if_then_else (eq_attr "cpu" "am34")
1945 (const_int 17) (const_int 25))
1949 (define_insn "divsf3"
1950 [(set (match_operand:SF 0 "register_operand" "=f,f")
1951 (div:SF (match_operand:SF 1 "register_operand" "0,f")
1952 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1953 (clobber (reg:CC_FLOAT CC_REG))]
1958 [(set_attr_alternative "timings"
1959 [(if_then_else (eq_attr "cpu" "am34")
1960 (const_int 2531) (const_int 1216))
1961 (if_then_else (eq_attr "cpu" "am34")
1962 (const_int 2531) (const_int 1317))
1966 (define_insn "fmasf4"
1967 [(set (match_operand:SF 0 "register_operand" "=c")
1968 (fma:SF (match_operand:SF 1 "register_operand" "f")
1969 (match_operand:SF 2 "register_operand" "f")
1970 (match_operand:SF 3 "register_operand" "f")))
1971 (clobber (reg:CC_FLOAT CC_REG))
1974 "fmadd %1, %2, %3, %0"
1975 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1976 (const_int 17) (const_int 24)))]
1979 (define_insn "fmssf4"
1980 [(set (match_operand:SF 0 "register_operand" "=c")
1981 (fma:SF (match_operand:SF 1 "register_operand" "f")
1982 (match_operand:SF 2 "register_operand" "f")
1983 (neg:SF (match_operand:SF 3 "register_operand" "f"))))
1984 (clobber (reg:CC_FLOAT CC_REG))
1987 "fmsub %1, %2, %3, %0"
1988 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1989 (const_int 17) (const_int 24)))]
1992 (define_insn "fnmasf4"
1993 [(set (match_operand:SF 0 "register_operand" "=c")
1994 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
1995 (match_operand:SF 2 "register_operand" "f")
1996 (match_operand:SF 3 "register_operand" "f")))
1997 (clobber (reg:CC_FLOAT CC_REG))
2000 "fnmadd %1, %2, %3, %0"
2001 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2002 (const_int 17) (const_int 24)))]
2005 (define_insn "fnmssf4"
2006 [(set (match_operand:SF 0 "register_operand" "=c")
2007 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
2008 (match_operand:SF 2 "register_operand" "f")
2009 (neg:SF (match_operand:SF 3 "register_operand" "f"))))
2010 (clobber (reg:CC_FLOAT CC_REG))
2013 "fnmsub %1, %2, %3, %0"
2014 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2015 (const_int 17) (const_int 24)))]
2018 ;; ----------------------------------------------------------------------
2019 ;; PROLOGUE/EPILOGUE
2020 ;; ----------------------------------------------------------------------
2021 (define_expand "prologue"
2024 { mn10300_expand_prologue (); DONE; }
2027 (define_expand "epilogue"
2030 { mn10300_expand_epilogue (); DONE; }
2033 (define_insn "return"
2035 "mn10300_can_use_rets_insn ()"
2037 /* The RETF insn is 4 cycles faster than RETS, though 1 byte larger. */
2038 if (optimize_insn_for_speed_p () && mn10300_can_use_retf_insn ())
2044 (define_insn "return_ret"
2046 (use (match_operand:SI 0 "const_int_operand" ""))]
2049 /* The RETF insn is up to 3 cycles faster than RET. */
2050 fputs ((mn10300_can_use_retf_insn () ? "\tretf " : "\tret "), asm_out_file);
2051 mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs ());
2052 fprintf (asm_out_file, ",%d\n", (int) INTVAL (operands[0]));
2056 ;; This instruction matches one generated by mn10300_gen_multiple_store()
2057 (define_insn "store_movm"
2058 [(match_parallel 0 "mn10300_store_multiple_operation"
2059 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand 1 "" "")))])]
2062 fputs ("\tmovm ", asm_out_file);
2063 mn10300_print_reg_list (asm_out_file,
2064 mn10300_store_multiple_operation (operands[0],
2066 fprintf (asm_out_file, ",(sp)\n");
2069 ;; Assume that no more than 8 registers will be pushed.
2070 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2071 (const_int 99) (const_int 88)))]
2074 (define_expand "load_pic"
2079 emit_insn (gen_am33_load_pic (pic_offset_table_rtx));
2080 else if (mn10300_frame_size () == 0)
2081 emit_insn (gen_mn10300_load_pic0 (pic_offset_table_rtx));
2083 emit_insn (gen_mn10300_load_pic1 (pic_offset_table_rtx));
2087 (define_insn "am33_load_pic"
2088 [(set (match_operand:SI 0 "register_operand" "=a")
2089 (unspec:SI [(const_int 0)] UNSPEC_GOT))
2090 (clobber (reg:CC CC_REG))]
2093 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
2094 return ".LPIC%=:\;mov pc,%0\;add %1-(.LPIC%=-.),%0";
2096 [(set_attr "timings" "33")]
2099 ;; Load pic register with push/pop of stack.
2100 (define_insn "mn10300_load_pic0"
2101 [(set (match_operand:SI 0 "register_operand" "=a")
2102 (unspec:SI [(const_int 0)] UNSPEC_GOT))
2103 (clobber (reg:SI MDR_REG))
2104 (clobber (reg:CC CC_REG))]
2107 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
2108 return ("add -4,sp\;"
2112 "add %1-(.LPIC%=-.),%0");
2114 [(set_attr "timings" "88")]
2117 ;; Load pic register re-using existing stack space.
2118 (define_insn "mn10300_load_pic1"
2119 [(set (match_operand:SI 0 "register_operand" "=a")
2120 (unspec:SI [(const_int 0)] UNSPEC_GOT))
2121 (clobber (mem:SI (reg:SI SP_REG)))
2122 (clobber (reg:SI MDR_REG))
2123 (clobber (reg:CC CC_REG))]
2126 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
2127 return ("calls .LPIC%=\n"
2130 "add %1-(.LPIC%=-.),%0");
2132 [(set_attr "timings" "66")]
2135 ;; The mode on operand 3 has been deliberately omitted because it
2136 ;; can be either SI (for arithmetic operations) or QI (for shifts).
2138 [(set (match_operand:SI 0 "register_operand" "=r")
2139 (unspec:SI [(match_dup 0)
2140 (match_operand 2 "liw_operand" "rO")
2141 (match_operand:SI 4 "const_int_operand" "")]
2143 (set (match_operand:SI 1 "register_operand" "=r")
2144 (unspec:SI [(match_dup 1)
2145 (match_operand 3 "liw_operand" "rO")
2146 (match_operand:SI 5 "const_int_operand" "")]
2149 "%W4_%W5 %2, %0, %3, %1"
2150 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2151 (const_int 13) (const_int 12)))]
2154 ;; The mode on operand 1 has been deliberately omitted because it
2155 ;; can be either SI (for arithmetic operations) or QI (for shifts).
2156 (define_insn "cmp_liw"
2157 [(set (reg:CC CC_REG)
2158 (compare:CC (match_operand:SI 2 "register_operand" "r")
2159 (match_operand 3 "liw_operand" "rO")))
2160 (set (match_operand:SI 0 "register_operand" "=r")
2161 (unspec:SI [(match_dup 0)
2162 (match_operand 1 "liw_operand" "rO")
2163 (match_operand:SI 4 "const_int_operand" "")]
2166 "cmp_%W4 %3, %2, %1, %0"
2167 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2168 (const_int 13) (const_int 12)))]
2171 (define_insn "liw_cmp"
2172 [(set (match_operand:SI 0 "register_operand" "=r")
2173 (unspec:SI [(match_dup 0)
2174 (match_operand 1 "liw_operand" "rO")
2175 (match_operand:SI 4 "const_int_operand" "")]
2177 (set (reg:CC CC_REG)
2178 (compare:CC (match_operand:SI 2 "register_operand" "r")
2179 (match_operand 3 "liw_operand" "rO")))]
2181 "%W4_cmp %1, %0, %3, %2"
2182 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2183 (const_int 13) (const_int 12)))]
2186 ;; Note - in theory the doloop patterns could be used here to express
2187 ;; the SETLB and Lcc instructions. In practice this does not work because
2188 ;; the acceptable forms of the doloop patterns do not include UNSPECs
2189 ;; and without them gcc's basic block reordering code can duplicate the
2190 ;; doloop_end pattern, leading to bogus multiple decrements of the loop
2193 (define_insn "setlb"
2194 [(unspec [(const_int 0)] UNSPEC_SETLB)]
2195 "TARGET_AM33 && TARGET_ALLOW_SETLB"
2201 (if_then_else (match_operator 0 "comparison_operator"
2202 [(reg:CC CC_REG) (const_int 0)])
2203 (label_ref (match_operand 1 "" ""))
2205 (unspec [(const_int 1)] UNSPEC_SETLB)]
2206 "TARGET_AM33 && TARGET_ALLOW_SETLB"
2207 "L%b0 # loop back to: %1"
2212 (if_then_else (match_operator 0 "comparison_operator"
2213 [(reg:CC_FLOAT CC_REG) (const_int 0)])
2214 (label_ref (match_operand 1 "" ""))
2216 (unspec [(const_int 2)] UNSPEC_SETLB)]
2217 "TARGET_AM33_2 && TARGET_ALLOW_SETLB"
2218 "FL%b0 # loop back to: %1"
2219 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") (const_int 44) (const_int 11)))]